1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
53 #include "sched-int.h"
56 #include "gimple-iterator.h"
57 #include "gimple-walk.h"
60 #include "tm-constrs.h"
63 #include "tree-vectorizer.h"
67 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
70 #include "gstab.h" /* for N_SLINE */
73 #ifndef TARGET_NO_PROTOTYPE
74 #define TARGET_NO_PROTOTYPE 0
77 #define min(A,B) ((A) < (B) ? (A) : (B))
78 #define max(A,B) ((A) > (B) ? (A) : (B))
80 /* Structure used to define the rs6000 stack */
81 typedef struct rs6000_stack
{
82 int reload_completed
; /* stack info won't change from here on */
83 int first_gp_reg_save
; /* first callee saved GP register used */
84 int first_fp_reg_save
; /* first callee saved FP register used */
85 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
86 int lr_save_p
; /* true if the link reg needs to be saved */
87 int cr_save_p
; /* true if the CR reg needs to be saved */
88 unsigned int vrsave_mask
; /* mask of vec registers to save */
89 int push_p
; /* true if we need to allocate stack space */
90 int calls_p
; /* true if the function makes any calls */
91 int world_save_p
; /* true if we're saving *everything*:
92 r13-r31, cr, f14-f31, vrsave, v20-v31 */
93 enum rs6000_abi abi
; /* which ABI to use */
94 int gp_save_offset
; /* offset to save GP regs from initial SP */
95 int fp_save_offset
; /* offset to save FP regs from initial SP */
96 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
97 int lr_save_offset
; /* offset to save LR from initial SP */
98 int cr_save_offset
; /* offset to save CR from initial SP */
99 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
100 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
101 int varargs_save_offset
; /* offset to save the varargs registers */
102 int ehrd_offset
; /* offset to EH return data */
103 int ehcr_offset
; /* offset to EH CR field data */
104 int reg_size
; /* register size (4 or 8) */
105 HOST_WIDE_INT vars_size
; /* variable save area size */
106 int parm_size
; /* outgoing parameter size */
107 int save_size
; /* save area size */
108 int fixed_size
; /* fixed size of stack frame */
109 int gp_size
; /* size of saved GP registers */
110 int fp_size
; /* size of saved FP registers */
111 int altivec_size
; /* size of saved AltiVec registers */
112 int cr_size
; /* size to hold CR if not in save_size */
113 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
114 int altivec_padding_size
; /* size of altivec alignment padding if
116 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
117 int spe_padding_size
;
118 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
119 int spe_64bit_regs_used
;
123 /* A C structure for machine-specific, per-function data.
124 This is added to the cfun structure. */
125 typedef struct GTY(()) machine_function
127 /* Some local-dynamic symbol. */
128 const char *some_ld_name
;
129 /* Whether the instruction chain has been scanned already. */
130 int insn_chain_scanned_p
;
131 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
132 int ra_needs_full_frame
;
133 /* Flags if __builtin_return_address (0) was used. */
135 /* Cache lr_save_p after expansion of builtin_eh_return. */
137 /* Whether we need to save the TOC to the reserved stack location in the
138 function prologue. */
139 bool save_toc_in_prologue
;
140 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
141 varargs save area. */
142 HOST_WIDE_INT varargs_save_offset
;
143 /* Temporary stack slot to use for SDmode copies. This slot is
144 64-bits wide and is allocated early enough so that the offset
145 does not overflow the 16-bit load/store offset field. */
146 rtx sdmode_stack_slot
;
147 /* Flag if r2 setup is needed with ELFv2 ABI. */
148 bool r2_setup_needed
;
151 /* Support targetm.vectorize.builtin_mask_for_load. */
152 static GTY(()) tree altivec_builtin_mask_for_load
;
154 /* Set to nonzero once AIX common-mode calls have been defined. */
155 static GTY(()) int common_mode_defined
;
157 /* Label number of label created for -mrelocatable, to call to so we can
158 get the address of the GOT section */
159 static int rs6000_pic_labelno
;
162 /* Counter for labels which are to be placed in .fixup. */
163 int fixuplabelno
= 0;
166 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
169 /* Specify the machine mode that pointers have. After generation of rtl, the
170 compiler makes no further distinction between pointers and any other objects
171 of this machine mode. The type is unsigned since not all things that
172 include rs6000.h also include machmode.h. */
173 unsigned rs6000_pmode
;
175 /* Width in bits of a pointer. */
176 unsigned rs6000_pointer_size
;
178 #ifdef HAVE_AS_GNU_ATTRIBUTE
179 /* Flag whether floating point values have been passed/returned. */
180 static bool rs6000_passes_float
;
181 /* Flag whether vector values have been passed/returned. */
182 static bool rs6000_passes_vector
;
183 /* Flag whether small (<= 8 byte) structures have been returned. */
184 static bool rs6000_returns_struct
;
187 /* Value is TRUE if register/mode pair is acceptable. */
188 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
190 /* Maximum number of registers needed for a given register class and mode. */
191 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
193 /* How many registers are needed for a given register and mode. */
194 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
196 /* Map register number to register class. */
197 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
199 static int dbg_cost_ctrl
;
201 /* Built in types. */
202 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
203 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
205 /* Flag to say the TOC is initialized */
207 char toc_label_name
[10];
209 /* Cached value of rs6000_variable_issue. This is cached in
210 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
211 static short cached_can_issue_more
;
213 static GTY(()) section
*read_only_data_section
;
214 static GTY(()) section
*private_data_section
;
215 static GTY(()) section
*tls_data_section
;
216 static GTY(()) section
*tls_private_data_section
;
217 static GTY(()) section
*read_only_private_data_section
;
218 static GTY(()) section
*sdata2_section
;
219 static GTY(()) section
*toc_section
;
221 struct builtin_description
223 const HOST_WIDE_INT mask
;
224 const enum insn_code icode
;
225 const char *const name
;
226 const enum rs6000_builtins code
;
229 /* Describe the vector unit used for modes. */
230 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
231 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
233 /* Register classes for various constraints that are based on the target
235 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
237 /* Describe the alignment of a vector. */
238 int rs6000_vector_align
[NUM_MACHINE_MODES
];
240 /* Map selected modes to types for builtins. */
241 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
243 /* What modes to automatically generate reciprocal divide estimate (fre) and
244 reciprocal sqrt (frsqrte) for. */
245 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
247 /* Masks to determine which reciprocal esitmate instructions to generate
249 enum rs6000_recip_mask
{
250 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
251 RECIP_DF_DIV
= 0x002,
252 RECIP_V4SF_DIV
= 0x004,
253 RECIP_V2DF_DIV
= 0x008,
255 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
256 RECIP_DF_RSQRT
= 0x020,
257 RECIP_V4SF_RSQRT
= 0x040,
258 RECIP_V2DF_RSQRT
= 0x080,
260 /* Various combination of flags for -mrecip=xxx. */
262 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
263 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
264 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
266 RECIP_HIGH_PRECISION
= RECIP_ALL
,
268 /* On low precision machines like the power5, don't enable double precision
269 reciprocal square root estimate, since it isn't accurate enough. */
270 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
273 /* -mrecip options. */
276 const char *string
; /* option name */
277 unsigned int mask
; /* mask bits to set */
278 } recip_options
[] = {
279 { "all", RECIP_ALL
},
280 { "none", RECIP_NONE
},
281 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
283 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
284 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
285 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
286 | RECIP_V2DF_RSQRT
) },
287 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
288 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
291 /* Pointer to function (in rs6000-c.c) that can define or undefine target
292 macros that have changed. Languages that don't support the preprocessor
293 don't link in rs6000-c.c, so we can't call it directly. */
294 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
296 /* Simplfy register classes into simpler classifications. We assume
297 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
298 check for standard register classes (gpr/floating/altivec/vsx) and
299 floating/vector classes (float/altivec/vsx). */
301 enum rs6000_reg_type
{
314 /* Map register class to register type. */
315 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
317 /* First/last register type for the 'normal' register types (i.e. general
318 purpose, floating point, altivec, and VSX registers). */
319 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
321 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
324 /* Register classes we care about in secondary reload or go if legitimate
325 address. We only need to worry about GPR, FPR, and Altivec registers here,
326 along an ANY field that is the OR of the 3 register classes. */
328 enum rs6000_reload_reg_type
{
329 RELOAD_REG_GPR
, /* General purpose registers. */
330 RELOAD_REG_FPR
, /* Traditional floating point regs. */
331 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
332 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
336 /* For setting up register classes, loop through the 3 register classes mapping
337 into real registers, and skip the ANY class, which is just an OR of the
339 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
340 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
342 /* Map reload register type to a register in the register class. */
343 struct reload_reg_map_type
{
344 const char *name
; /* Register class name. */
345 int reg
; /* Register in the register class. */
348 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
349 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
350 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
351 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
352 { "Any", -1 }, /* RELOAD_REG_ANY. */
355 /* Mask bits for each register class, indexed per mode. Historically the
356 compiler has been more restrictive which types can do PRE_MODIFY instead of
357 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
358 typedef unsigned char addr_mask_type
;
360 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
361 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
362 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
363 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
364 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
365 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
367 /* Register type masks based on the type, of valid addressing modes. */
368 struct rs6000_reg_addr
{
369 enum insn_code reload_load
; /* INSN to reload for loading. */
370 enum insn_code reload_store
; /* INSN to reload for storing. */
371 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
372 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
373 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
374 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
377 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
379 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
381 mode_supports_pre_incdec_p (enum machine_mode mode
)
383 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
387 /* Helper function to say whether a mode supports PRE_MODIFY. */
389 mode_supports_pre_modify_p (enum machine_mode mode
)
391 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
396 /* Target cpu costs. */
398 struct processor_costs
{
399 const int mulsi
; /* cost of SImode multiplication. */
400 const int mulsi_const
; /* cost of SImode multiplication by constant. */
401 const int mulsi_const9
; /* cost of SImode mult by short constant. */
402 const int muldi
; /* cost of DImode multiplication. */
403 const int divsi
; /* cost of SImode division. */
404 const int divdi
; /* cost of DImode division. */
405 const int fp
; /* cost of simple SFmode and DFmode insns. */
406 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
407 const int sdiv
; /* cost of SFmode division (fdivs). */
408 const int ddiv
; /* cost of DFmode division (fdiv). */
409 const int cache_line_size
; /* cache line size in bytes. */
410 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
411 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
412 const int simultaneous_prefetches
; /* number of parallel prefetch
416 const struct processor_costs
*rs6000_cost
;
418 /* Processor costs (relative to an add) */
420 /* Instruction size costs on 32bit processors. */
422 struct processor_costs size32_cost
= {
423 COSTS_N_INSNS (1), /* mulsi */
424 COSTS_N_INSNS (1), /* mulsi_const */
425 COSTS_N_INSNS (1), /* mulsi_const9 */
426 COSTS_N_INSNS (1), /* muldi */
427 COSTS_N_INSNS (1), /* divsi */
428 COSTS_N_INSNS (1), /* divdi */
429 COSTS_N_INSNS (1), /* fp */
430 COSTS_N_INSNS (1), /* dmul */
431 COSTS_N_INSNS (1), /* sdiv */
432 COSTS_N_INSNS (1), /* ddiv */
439 /* Instruction size costs on 64bit processors. */
441 struct processor_costs size64_cost
= {
442 COSTS_N_INSNS (1), /* mulsi */
443 COSTS_N_INSNS (1), /* mulsi_const */
444 COSTS_N_INSNS (1), /* mulsi_const9 */
445 COSTS_N_INSNS (1), /* muldi */
446 COSTS_N_INSNS (1), /* divsi */
447 COSTS_N_INSNS (1), /* divdi */
448 COSTS_N_INSNS (1), /* fp */
449 COSTS_N_INSNS (1), /* dmul */
450 COSTS_N_INSNS (1), /* sdiv */
451 COSTS_N_INSNS (1), /* ddiv */
458 /* Instruction costs on RS64A processors. */
460 struct processor_costs rs64a_cost
= {
461 COSTS_N_INSNS (20), /* mulsi */
462 COSTS_N_INSNS (12), /* mulsi_const */
463 COSTS_N_INSNS (8), /* mulsi_const9 */
464 COSTS_N_INSNS (34), /* muldi */
465 COSTS_N_INSNS (65), /* divsi */
466 COSTS_N_INSNS (67), /* divdi */
467 COSTS_N_INSNS (4), /* fp */
468 COSTS_N_INSNS (4), /* dmul */
469 COSTS_N_INSNS (31), /* sdiv */
470 COSTS_N_INSNS (31), /* ddiv */
471 128, /* cache line size */
477 /* Instruction costs on MPCCORE processors. */
479 struct processor_costs mpccore_cost
= {
480 COSTS_N_INSNS (2), /* mulsi */
481 COSTS_N_INSNS (2), /* mulsi_const */
482 COSTS_N_INSNS (2), /* mulsi_const9 */
483 COSTS_N_INSNS (2), /* muldi */
484 COSTS_N_INSNS (6), /* divsi */
485 COSTS_N_INSNS (6), /* divdi */
486 COSTS_N_INSNS (4), /* fp */
487 COSTS_N_INSNS (5), /* dmul */
488 COSTS_N_INSNS (10), /* sdiv */
489 COSTS_N_INSNS (17), /* ddiv */
490 32, /* cache line size */
496 /* Instruction costs on PPC403 processors. */
498 struct processor_costs ppc403_cost
= {
499 COSTS_N_INSNS (4), /* mulsi */
500 COSTS_N_INSNS (4), /* mulsi_const */
501 COSTS_N_INSNS (4), /* mulsi_const9 */
502 COSTS_N_INSNS (4), /* muldi */
503 COSTS_N_INSNS (33), /* divsi */
504 COSTS_N_INSNS (33), /* divdi */
505 COSTS_N_INSNS (11), /* fp */
506 COSTS_N_INSNS (11), /* dmul */
507 COSTS_N_INSNS (11), /* sdiv */
508 COSTS_N_INSNS (11), /* ddiv */
509 32, /* cache line size */
515 /* Instruction costs on PPC405 processors. */
517 struct processor_costs ppc405_cost
= {
518 COSTS_N_INSNS (5), /* mulsi */
519 COSTS_N_INSNS (4), /* mulsi_const */
520 COSTS_N_INSNS (3), /* mulsi_const9 */
521 COSTS_N_INSNS (5), /* muldi */
522 COSTS_N_INSNS (35), /* divsi */
523 COSTS_N_INSNS (35), /* divdi */
524 COSTS_N_INSNS (11), /* fp */
525 COSTS_N_INSNS (11), /* dmul */
526 COSTS_N_INSNS (11), /* sdiv */
527 COSTS_N_INSNS (11), /* ddiv */
528 32, /* cache line size */
534 /* Instruction costs on PPC440 processors. */
536 struct processor_costs ppc440_cost
= {
537 COSTS_N_INSNS (3), /* mulsi */
538 COSTS_N_INSNS (2), /* mulsi_const */
539 COSTS_N_INSNS (2), /* mulsi_const9 */
540 COSTS_N_INSNS (3), /* muldi */
541 COSTS_N_INSNS (34), /* divsi */
542 COSTS_N_INSNS (34), /* divdi */
543 COSTS_N_INSNS (5), /* fp */
544 COSTS_N_INSNS (5), /* dmul */
545 COSTS_N_INSNS (19), /* sdiv */
546 COSTS_N_INSNS (33), /* ddiv */
547 32, /* cache line size */
553 /* Instruction costs on PPC476 processors. */
555 struct processor_costs ppc476_cost
= {
556 COSTS_N_INSNS (4), /* mulsi */
557 COSTS_N_INSNS (4), /* mulsi_const */
558 COSTS_N_INSNS (4), /* mulsi_const9 */
559 COSTS_N_INSNS (4), /* muldi */
560 COSTS_N_INSNS (11), /* divsi */
561 COSTS_N_INSNS (11), /* divdi */
562 COSTS_N_INSNS (6), /* fp */
563 COSTS_N_INSNS (6), /* dmul */
564 COSTS_N_INSNS (19), /* sdiv */
565 COSTS_N_INSNS (33), /* ddiv */
566 32, /* l1 cache line size */
572 /* Instruction costs on PPC601 processors. */
574 struct processor_costs ppc601_cost
= {
575 COSTS_N_INSNS (5), /* mulsi */
576 COSTS_N_INSNS (5), /* mulsi_const */
577 COSTS_N_INSNS (5), /* mulsi_const9 */
578 COSTS_N_INSNS (5), /* muldi */
579 COSTS_N_INSNS (36), /* divsi */
580 COSTS_N_INSNS (36), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (5), /* dmul */
583 COSTS_N_INSNS (17), /* sdiv */
584 COSTS_N_INSNS (31), /* ddiv */
585 32, /* cache line size */
591 /* Instruction costs on PPC603 processors. */
593 struct processor_costs ppc603_cost
= {
594 COSTS_N_INSNS (5), /* mulsi */
595 COSTS_N_INSNS (3), /* mulsi_const */
596 COSTS_N_INSNS (2), /* mulsi_const9 */
597 COSTS_N_INSNS (5), /* muldi */
598 COSTS_N_INSNS (37), /* divsi */
599 COSTS_N_INSNS (37), /* divdi */
600 COSTS_N_INSNS (3), /* fp */
601 COSTS_N_INSNS (4), /* dmul */
602 COSTS_N_INSNS (18), /* sdiv */
603 COSTS_N_INSNS (33), /* ddiv */
604 32, /* cache line size */
610 /* Instruction costs on PPC604 processors. */
612 struct processor_costs ppc604_cost
= {
613 COSTS_N_INSNS (4), /* mulsi */
614 COSTS_N_INSNS (4), /* mulsi_const */
615 COSTS_N_INSNS (4), /* mulsi_const9 */
616 COSTS_N_INSNS (4), /* muldi */
617 COSTS_N_INSNS (20), /* divsi */
618 COSTS_N_INSNS (20), /* divdi */
619 COSTS_N_INSNS (3), /* fp */
620 COSTS_N_INSNS (3), /* dmul */
621 COSTS_N_INSNS (18), /* sdiv */
622 COSTS_N_INSNS (32), /* ddiv */
623 32, /* cache line size */
629 /* Instruction costs on PPC604e processors. */
631 struct processor_costs ppc604e_cost
= {
632 COSTS_N_INSNS (2), /* mulsi */
633 COSTS_N_INSNS (2), /* mulsi_const */
634 COSTS_N_INSNS (2), /* mulsi_const9 */
635 COSTS_N_INSNS (2), /* muldi */
636 COSTS_N_INSNS (20), /* divsi */
637 COSTS_N_INSNS (20), /* divdi */
638 COSTS_N_INSNS (3), /* fp */
639 COSTS_N_INSNS (3), /* dmul */
640 COSTS_N_INSNS (18), /* sdiv */
641 COSTS_N_INSNS (32), /* ddiv */
642 32, /* cache line size */
648 /* Instruction costs on PPC620 processors. */
650 struct processor_costs ppc620_cost
= {
651 COSTS_N_INSNS (5), /* mulsi */
652 COSTS_N_INSNS (4), /* mulsi_const */
653 COSTS_N_INSNS (3), /* mulsi_const9 */
654 COSTS_N_INSNS (7), /* muldi */
655 COSTS_N_INSNS (21), /* divsi */
656 COSTS_N_INSNS (37), /* divdi */
657 COSTS_N_INSNS (3), /* fp */
658 COSTS_N_INSNS (3), /* dmul */
659 COSTS_N_INSNS (18), /* sdiv */
660 COSTS_N_INSNS (32), /* ddiv */
661 128, /* cache line size */
667 /* Instruction costs on PPC630 processors. */
669 struct processor_costs ppc630_cost
= {
670 COSTS_N_INSNS (5), /* mulsi */
671 COSTS_N_INSNS (4), /* mulsi_const */
672 COSTS_N_INSNS (3), /* mulsi_const9 */
673 COSTS_N_INSNS (7), /* muldi */
674 COSTS_N_INSNS (21), /* divsi */
675 COSTS_N_INSNS (37), /* divdi */
676 COSTS_N_INSNS (3), /* fp */
677 COSTS_N_INSNS (3), /* dmul */
678 COSTS_N_INSNS (17), /* sdiv */
679 COSTS_N_INSNS (21), /* ddiv */
680 128, /* cache line size */
686 /* Instruction costs on Cell processor. */
687 /* COSTS_N_INSNS (1) ~ one add. */
689 struct processor_costs ppccell_cost
= {
690 COSTS_N_INSNS (9/2)+2, /* mulsi */
691 COSTS_N_INSNS (6/2), /* mulsi_const */
692 COSTS_N_INSNS (6/2), /* mulsi_const9 */
693 COSTS_N_INSNS (15/2)+2, /* muldi */
694 COSTS_N_INSNS (38/2), /* divsi */
695 COSTS_N_INSNS (70/2), /* divdi */
696 COSTS_N_INSNS (10/2), /* fp */
697 COSTS_N_INSNS (10/2), /* dmul */
698 COSTS_N_INSNS (74/2), /* sdiv */
699 COSTS_N_INSNS (74/2), /* ddiv */
700 128, /* cache line size */
706 /* Instruction costs on PPC750 and PPC7400 processors. */
708 struct processor_costs ppc750_cost
= {
709 COSTS_N_INSNS (5), /* mulsi */
710 COSTS_N_INSNS (3), /* mulsi_const */
711 COSTS_N_INSNS (2), /* mulsi_const9 */
712 COSTS_N_INSNS (5), /* muldi */
713 COSTS_N_INSNS (17), /* divsi */
714 COSTS_N_INSNS (17), /* divdi */
715 COSTS_N_INSNS (3), /* fp */
716 COSTS_N_INSNS (3), /* dmul */
717 COSTS_N_INSNS (17), /* sdiv */
718 COSTS_N_INSNS (31), /* ddiv */
719 32, /* cache line size */
725 /* Instruction costs on PPC7450 processors. */
727 struct processor_costs ppc7450_cost
= {
728 COSTS_N_INSNS (4), /* mulsi */
729 COSTS_N_INSNS (3), /* mulsi_const */
730 COSTS_N_INSNS (3), /* mulsi_const9 */
731 COSTS_N_INSNS (4), /* muldi */
732 COSTS_N_INSNS (23), /* divsi */
733 COSTS_N_INSNS (23), /* divdi */
734 COSTS_N_INSNS (5), /* fp */
735 COSTS_N_INSNS (5), /* dmul */
736 COSTS_N_INSNS (21), /* sdiv */
737 COSTS_N_INSNS (35), /* ddiv */
738 32, /* cache line size */
744 /* Instruction costs on PPC8540 processors. */
746 struct processor_costs ppc8540_cost
= {
747 COSTS_N_INSNS (4), /* mulsi */
748 COSTS_N_INSNS (4), /* mulsi_const */
749 COSTS_N_INSNS (4), /* mulsi_const9 */
750 COSTS_N_INSNS (4), /* muldi */
751 COSTS_N_INSNS (19), /* divsi */
752 COSTS_N_INSNS (19), /* divdi */
753 COSTS_N_INSNS (4), /* fp */
754 COSTS_N_INSNS (4), /* dmul */
755 COSTS_N_INSNS (29), /* sdiv */
756 COSTS_N_INSNS (29), /* ddiv */
757 32, /* cache line size */
760 1, /* prefetch streams /*/
763 /* Instruction costs on E300C2 and E300C3 cores. */
765 struct processor_costs ppce300c2c3_cost
= {
766 COSTS_N_INSNS (4), /* mulsi */
767 COSTS_N_INSNS (4), /* mulsi_const */
768 COSTS_N_INSNS (4), /* mulsi_const9 */
769 COSTS_N_INSNS (4), /* muldi */
770 COSTS_N_INSNS (19), /* divsi */
771 COSTS_N_INSNS (19), /* divdi */
772 COSTS_N_INSNS (3), /* fp */
773 COSTS_N_INSNS (4), /* dmul */
774 COSTS_N_INSNS (18), /* sdiv */
775 COSTS_N_INSNS (33), /* ddiv */
779 1, /* prefetch streams /*/
782 /* Instruction costs on PPCE500MC processors. */
784 struct processor_costs ppce500mc_cost
= {
785 COSTS_N_INSNS (4), /* mulsi */
786 COSTS_N_INSNS (4), /* mulsi_const */
787 COSTS_N_INSNS (4), /* mulsi_const9 */
788 COSTS_N_INSNS (4), /* muldi */
789 COSTS_N_INSNS (14), /* divsi */
790 COSTS_N_INSNS (14), /* divdi */
791 COSTS_N_INSNS (8), /* fp */
792 COSTS_N_INSNS (10), /* dmul */
793 COSTS_N_INSNS (36), /* sdiv */
794 COSTS_N_INSNS (66), /* ddiv */
795 64, /* cache line size */
798 1, /* prefetch streams /*/
801 /* Instruction costs on PPCE500MC64 processors. */
803 struct processor_costs ppce500mc64_cost
= {
804 COSTS_N_INSNS (4), /* mulsi */
805 COSTS_N_INSNS (4), /* mulsi_const */
806 COSTS_N_INSNS (4), /* mulsi_const9 */
807 COSTS_N_INSNS (4), /* muldi */
808 COSTS_N_INSNS (14), /* divsi */
809 COSTS_N_INSNS (14), /* divdi */
810 COSTS_N_INSNS (4), /* fp */
811 COSTS_N_INSNS (10), /* dmul */
812 COSTS_N_INSNS (36), /* sdiv */
813 COSTS_N_INSNS (66), /* ddiv */
814 64, /* cache line size */
817 1, /* prefetch streams /*/
820 /* Instruction costs on PPCE5500 processors. */
822 struct processor_costs ppce5500_cost
= {
823 COSTS_N_INSNS (5), /* mulsi */
824 COSTS_N_INSNS (5), /* mulsi_const */
825 COSTS_N_INSNS (4), /* mulsi_const9 */
826 COSTS_N_INSNS (5), /* muldi */
827 COSTS_N_INSNS (14), /* divsi */
828 COSTS_N_INSNS (14), /* divdi */
829 COSTS_N_INSNS (7), /* fp */
830 COSTS_N_INSNS (10), /* dmul */
831 COSTS_N_INSNS (36), /* sdiv */
832 COSTS_N_INSNS (66), /* ddiv */
833 64, /* cache line size */
836 1, /* prefetch streams /*/
839 /* Instruction costs on PPCE6500 processors. */
841 struct processor_costs ppce6500_cost
= {
842 COSTS_N_INSNS (5), /* mulsi */
843 COSTS_N_INSNS (5), /* mulsi_const */
844 COSTS_N_INSNS (4), /* mulsi_const9 */
845 COSTS_N_INSNS (5), /* muldi */
846 COSTS_N_INSNS (14), /* divsi */
847 COSTS_N_INSNS (14), /* divdi */
848 COSTS_N_INSNS (7), /* fp */
849 COSTS_N_INSNS (10), /* dmul */
850 COSTS_N_INSNS (36), /* sdiv */
851 COSTS_N_INSNS (66), /* ddiv */
852 64, /* cache line size */
855 1, /* prefetch streams /*/
858 /* Instruction costs on AppliedMicro Titan processors. */
860 struct processor_costs titan_cost
= {
861 COSTS_N_INSNS (5), /* mulsi */
862 COSTS_N_INSNS (5), /* mulsi_const */
863 COSTS_N_INSNS (5), /* mulsi_const9 */
864 COSTS_N_INSNS (5), /* muldi */
865 COSTS_N_INSNS (18), /* divsi */
866 COSTS_N_INSNS (18), /* divdi */
867 COSTS_N_INSNS (10), /* fp */
868 COSTS_N_INSNS (10), /* dmul */
869 COSTS_N_INSNS (46), /* sdiv */
870 COSTS_N_INSNS (72), /* ddiv */
871 32, /* cache line size */
874 1, /* prefetch streams /*/
877 /* Instruction costs on POWER4 and POWER5 processors. */
879 struct processor_costs power4_cost
= {
880 COSTS_N_INSNS (3), /* mulsi */
881 COSTS_N_INSNS (2), /* mulsi_const */
882 COSTS_N_INSNS (2), /* mulsi_const9 */
883 COSTS_N_INSNS (4), /* muldi */
884 COSTS_N_INSNS (18), /* divsi */
885 COSTS_N_INSNS (34), /* divdi */
886 COSTS_N_INSNS (3), /* fp */
887 COSTS_N_INSNS (3), /* dmul */
888 COSTS_N_INSNS (17), /* sdiv */
889 COSTS_N_INSNS (17), /* ddiv */
890 128, /* cache line size */
893 8, /* prefetch streams /*/
896 /* Instruction costs on POWER6 processors. */
898 struct processor_costs power6_cost
= {
899 COSTS_N_INSNS (8), /* mulsi */
900 COSTS_N_INSNS (8), /* mulsi_const */
901 COSTS_N_INSNS (8), /* mulsi_const9 */
902 COSTS_N_INSNS (8), /* muldi */
903 COSTS_N_INSNS (22), /* divsi */
904 COSTS_N_INSNS (28), /* divdi */
905 COSTS_N_INSNS (3), /* fp */
906 COSTS_N_INSNS (3), /* dmul */
907 COSTS_N_INSNS (13), /* sdiv */
908 COSTS_N_INSNS (16), /* ddiv */
909 128, /* cache line size */
912 16, /* prefetch streams */
915 /* Instruction costs on POWER7 processors. */
917 struct processor_costs power7_cost
= {
918 COSTS_N_INSNS (2), /* mulsi */
919 COSTS_N_INSNS (2), /* mulsi_const */
920 COSTS_N_INSNS (2), /* mulsi_const9 */
921 COSTS_N_INSNS (2), /* muldi */
922 COSTS_N_INSNS (18), /* divsi */
923 COSTS_N_INSNS (34), /* divdi */
924 COSTS_N_INSNS (3), /* fp */
925 COSTS_N_INSNS (3), /* dmul */
926 COSTS_N_INSNS (13), /* sdiv */
927 COSTS_N_INSNS (16), /* ddiv */
928 128, /* cache line size */
931 12, /* prefetch streams */
934 /* Instruction costs on POWER8 processors. */
936 struct processor_costs power8_cost
= {
937 COSTS_N_INSNS (3), /* mulsi */
938 COSTS_N_INSNS (3), /* mulsi_const */
939 COSTS_N_INSNS (3), /* mulsi_const9 */
940 COSTS_N_INSNS (3), /* muldi */
941 COSTS_N_INSNS (19), /* divsi */
942 COSTS_N_INSNS (35), /* divdi */
943 COSTS_N_INSNS (3), /* fp */
944 COSTS_N_INSNS (3), /* dmul */
945 COSTS_N_INSNS (14), /* sdiv */
946 COSTS_N_INSNS (17), /* ddiv */
947 128, /* cache line size */
950 12, /* prefetch streams */
953 /* Instruction costs on POWER A2 processors. */
955 struct processor_costs ppca2_cost
= {
956 COSTS_N_INSNS (16), /* mulsi */
957 COSTS_N_INSNS (16), /* mulsi_const */
958 COSTS_N_INSNS (16), /* mulsi_const9 */
959 COSTS_N_INSNS (16), /* muldi */
960 COSTS_N_INSNS (22), /* divsi */
961 COSTS_N_INSNS (28), /* divdi */
962 COSTS_N_INSNS (3), /* fp */
963 COSTS_N_INSNS (3), /* dmul */
964 COSTS_N_INSNS (59), /* sdiv */
965 COSTS_N_INSNS (72), /* ddiv */
969 16, /* prefetch streams */
973 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
974 #undef RS6000_BUILTIN_1
975 #undef RS6000_BUILTIN_2
976 #undef RS6000_BUILTIN_3
977 #undef RS6000_BUILTIN_A
978 #undef RS6000_BUILTIN_D
979 #undef RS6000_BUILTIN_E
980 #undef RS6000_BUILTIN_H
981 #undef RS6000_BUILTIN_P
982 #undef RS6000_BUILTIN_Q
983 #undef RS6000_BUILTIN_S
984 #undef RS6000_BUILTIN_X
986 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
987 { NAME, ICODE, MASK, ATTR },
989 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
990 { NAME, ICODE, MASK, ATTR },
992 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
993 { NAME, ICODE, MASK, ATTR },
995 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
996 { NAME, ICODE, MASK, ATTR },
998 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
999 { NAME, ICODE, MASK, ATTR },
1001 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1002 { NAME, ICODE, MASK, ATTR },
1004 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1005 { NAME, ICODE, MASK, ATTR },
1007 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1008 { NAME, ICODE, MASK, ATTR },
1010 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1011 { NAME, ICODE, MASK, ATTR },
1013 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1014 { NAME, ICODE, MASK, ATTR },
1016 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1017 { NAME, ICODE, MASK, ATTR },
1019 struct rs6000_builtin_info_type
{
1021 const enum insn_code icode
;
1022 const HOST_WIDE_INT mask
;
1023 const unsigned attr
;
1026 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1028 #include "rs6000-builtin.def"
1031 #undef RS6000_BUILTIN_1
1032 #undef RS6000_BUILTIN_2
1033 #undef RS6000_BUILTIN_3
1034 #undef RS6000_BUILTIN_A
1035 #undef RS6000_BUILTIN_D
1036 #undef RS6000_BUILTIN_E
1037 #undef RS6000_BUILTIN_H
1038 #undef RS6000_BUILTIN_P
1039 #undef RS6000_BUILTIN_Q
1040 #undef RS6000_BUILTIN_S
1041 #undef RS6000_BUILTIN_X
1043 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1044 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1047 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1048 static bool spe_func_has_64bit_regs_p (void);
1049 static struct machine_function
* rs6000_init_machine_status (void);
1050 static int rs6000_ra_ever_killed (void);
1051 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1052 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1053 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1054 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1055 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
1056 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1057 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1058 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1060 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1061 static bool is_microcoded_insn (rtx
);
1062 static bool is_nonpipeline_insn (rtx
);
1063 static bool is_cracked_insn (rtx
);
1064 static bool is_load_insn (rtx
, rtx
*);
1065 static bool is_store_insn (rtx
, rtx
*);
1066 static bool set_to_load_agen (rtx
,rtx
);
1067 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1068 static bool insn_must_be_first_in_group (rtx
);
1069 static bool insn_must_be_last_in_group (rtx
);
1070 static void altivec_init_builtins (void);
1071 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1072 enum machine_mode
, enum machine_mode
,
1073 enum rs6000_builtins
, const char *name
);
1074 static void rs6000_common_init_builtins (void);
1075 static void paired_init_builtins (void);
1076 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1077 static void spe_init_builtins (void);
1078 static void htm_init_builtins (void);
1079 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1080 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1081 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1082 static rs6000_stack_t
*rs6000_stack_info (void);
1083 static void is_altivec_return_reg (rtx
, void *);
1084 int easy_vector_constant (rtx
, enum machine_mode
);
1085 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1086 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1087 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1088 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1089 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1092 static void macho_branch_islands (void);
1094 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1096 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1098 static bool rs6000_mode_dependent_address (const_rtx
);
1099 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1100 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1101 enum machine_mode
, rtx
);
1102 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1105 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1106 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1108 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1110 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1113 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1116 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1119 static bool rs6000_save_toc_in_prologue_p (void);
1121 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1123 = rs6000_legitimize_reload_address
;
1125 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1126 = rs6000_mode_dependent_address
;
1128 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1129 enum machine_mode
, rtx
)
1130 = rs6000_secondary_reload_class
;
1132 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1133 = rs6000_preferred_reload_class
;
1135 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1137 = rs6000_secondary_memory_needed
;
1139 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1142 = rs6000_cannot_change_mode_class
;
1144 const int INSN_NOT_AVAILABLE
= -1;
1146 static void rs6000_print_isa_options (FILE *, int, const char *,
1148 static void rs6000_print_builtin_options (FILE *, int, const char *,
1151 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1152 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1153 enum rs6000_reg_type
,
1155 secondary_reload_info
*,
1158 /* Hash table stuff for keeping track of TOC entries. */
1160 struct GTY(()) toc_hash_struct
1162 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1163 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1165 enum machine_mode key_mode
;
1169 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1171 /* Hash table to keep track of the argument types for builtin functions. */
1173 struct GTY(()) builtin_hash_struct
1176 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1177 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1180 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1183 /* Default register names. */
1184 char rs6000_reg_names
[][8] =
1186 "0", "1", "2", "3", "4", "5", "6", "7",
1187 "8", "9", "10", "11", "12", "13", "14", "15",
1188 "16", "17", "18", "19", "20", "21", "22", "23",
1189 "24", "25", "26", "27", "28", "29", "30", "31",
1190 "0", "1", "2", "3", "4", "5", "6", "7",
1191 "8", "9", "10", "11", "12", "13", "14", "15",
1192 "16", "17", "18", "19", "20", "21", "22", "23",
1193 "24", "25", "26", "27", "28", "29", "30", "31",
1194 "mq", "lr", "ctr","ap",
1195 "0", "1", "2", "3", "4", "5", "6", "7",
1197 /* AltiVec registers. */
1198 "0", "1", "2", "3", "4", "5", "6", "7",
1199 "8", "9", "10", "11", "12", "13", "14", "15",
1200 "16", "17", "18", "19", "20", "21", "22", "23",
1201 "24", "25", "26", "27", "28", "29", "30", "31",
1203 /* SPE registers. */
1204 "spe_acc", "spefscr",
1205 /* Soft frame pointer. */
1207 /* HTM SPR registers. */
1208 "tfhar", "tfiar", "texasr"
1211 #ifdef TARGET_REGNAMES
1212 static const char alt_reg_names
[][8] =
1214 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1215 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1216 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1217 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1218 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1219 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1220 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1221 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1222 "mq", "lr", "ctr", "ap",
1223 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1225 /* AltiVec registers. */
1226 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1227 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1228 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1229 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1231 /* SPE registers. */
1232 "spe_acc", "spefscr",
1233 /* Soft frame pointer. */
1235 /* HTM SPR registers. */
1236 "tfhar", "tfiar", "texasr"
1240 /* Table of valid machine attributes. */
1242 static const struct attribute_spec rs6000_attribute_table
[] =
1244 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1245 affects_type_identity } */
1246 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1248 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1250 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1252 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1254 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1256 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1257 SUBTARGET_ATTRIBUTE_TABLE
,
1259 { NULL
, 0, 0, false, false, false, NULL
, false }
1262 #ifndef TARGET_PROFILE_KERNEL
1263 #define TARGET_PROFILE_KERNEL 0
1266 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1267 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1269 /* Initialize the GCC target structure. */
1270 #undef TARGET_ATTRIBUTE_TABLE
1271 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1272 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1273 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1274 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1275 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1277 #undef TARGET_ASM_ALIGNED_DI_OP
1278 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1280 /* Default unaligned ops are only provided for ELF. Find the ops needed
1281 for non-ELF systems. */
1282 #ifndef OBJECT_FORMAT_ELF
1284 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1286 #undef TARGET_ASM_UNALIGNED_HI_OP
1287 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1288 #undef TARGET_ASM_UNALIGNED_SI_OP
1289 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1290 #undef TARGET_ASM_UNALIGNED_DI_OP
1291 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1294 #undef TARGET_ASM_UNALIGNED_HI_OP
1295 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1296 #undef TARGET_ASM_UNALIGNED_SI_OP
1297 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1298 #undef TARGET_ASM_UNALIGNED_DI_OP
1299 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1300 #undef TARGET_ASM_ALIGNED_DI_OP
1301 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1305 /* This hook deals with fixups for relocatable code and DI-mode objects
1307 #undef TARGET_ASM_INTEGER
1308 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1310 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1311 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1312 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1315 #undef TARGET_SET_UP_BY_PROLOGUE
1316 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1318 #undef TARGET_HAVE_TLS
1319 #define TARGET_HAVE_TLS HAVE_AS_TLS
1321 #undef TARGET_CANNOT_FORCE_CONST_MEM
1322 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1324 #undef TARGET_DELEGITIMIZE_ADDRESS
1325 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1327 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1328 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1330 #undef TARGET_ASM_FUNCTION_PROLOGUE
1331 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1332 #undef TARGET_ASM_FUNCTION_EPILOGUE
1333 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1335 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1336 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1338 #undef TARGET_LEGITIMIZE_ADDRESS
1339 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1341 #undef TARGET_SCHED_VARIABLE_ISSUE
1342 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1344 #undef TARGET_SCHED_ISSUE_RATE
1345 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1346 #undef TARGET_SCHED_ADJUST_COST
1347 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1348 #undef TARGET_SCHED_ADJUST_PRIORITY
1349 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1350 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1351 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1352 #undef TARGET_SCHED_INIT
1353 #define TARGET_SCHED_INIT rs6000_sched_init
1354 #undef TARGET_SCHED_FINISH
1355 #define TARGET_SCHED_FINISH rs6000_sched_finish
1356 #undef TARGET_SCHED_REORDER
1357 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1358 #undef TARGET_SCHED_REORDER2
1359 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1361 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1362 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1364 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1365 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1367 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1368 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1369 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1370 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1371 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1372 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1373 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1374 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1376 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1377 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1378 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1379 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1380 rs6000_builtin_support_vector_misalignment
1381 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1382 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1383 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1384 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1385 rs6000_builtin_vectorization_cost
1386 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1387 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1388 rs6000_preferred_simd_mode
1389 #undef TARGET_VECTORIZE_INIT_COST
1390 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1391 #undef TARGET_VECTORIZE_ADD_STMT_COST
1392 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1393 #undef TARGET_VECTORIZE_FINISH_COST
1394 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1395 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1396 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1398 #undef TARGET_INIT_BUILTINS
1399 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1400 #undef TARGET_BUILTIN_DECL
1401 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1403 #undef TARGET_EXPAND_BUILTIN
1404 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1406 #undef TARGET_MANGLE_TYPE
1407 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1409 #undef TARGET_INIT_LIBFUNCS
1410 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1413 #undef TARGET_BINDS_LOCAL_P
1414 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1417 #undef TARGET_MS_BITFIELD_LAYOUT_P
1418 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1420 #undef TARGET_ASM_OUTPUT_MI_THUNK
1421 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1423 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1424 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1426 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1427 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1429 #undef TARGET_REGISTER_MOVE_COST
1430 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1431 #undef TARGET_MEMORY_MOVE_COST
1432 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1433 #undef TARGET_RTX_COSTS
1434 #define TARGET_RTX_COSTS rs6000_rtx_costs
1435 #undef TARGET_ADDRESS_COST
1436 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1438 #undef TARGET_DWARF_REGISTER_SPAN
1439 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1441 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1442 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1444 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1445 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1447 /* On rs6000, function arguments are promoted, as are function return
1449 #undef TARGET_PROMOTE_FUNCTION_MODE
1450 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1452 #undef TARGET_RETURN_IN_MEMORY
1453 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1455 #undef TARGET_RETURN_IN_MSB
1456 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1458 #undef TARGET_SETUP_INCOMING_VARARGS
1459 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1461 /* Always strict argument naming on rs6000. */
1462 #undef TARGET_STRICT_ARGUMENT_NAMING
1463 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1464 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1465 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1466 #undef TARGET_SPLIT_COMPLEX_ARG
1467 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1468 #undef TARGET_MUST_PASS_IN_STACK
1469 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1470 #undef TARGET_PASS_BY_REFERENCE
1471 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1472 #undef TARGET_ARG_PARTIAL_BYTES
1473 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1474 #undef TARGET_FUNCTION_ARG_ADVANCE
1475 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1476 #undef TARGET_FUNCTION_ARG
1477 #define TARGET_FUNCTION_ARG rs6000_function_arg
1478 #undef TARGET_FUNCTION_ARG_BOUNDARY
1479 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1481 #undef TARGET_BUILD_BUILTIN_VA_LIST
1482 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1484 #undef TARGET_EXPAND_BUILTIN_VA_START
1485 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1487 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1488 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1490 #undef TARGET_EH_RETURN_FILTER_MODE
1491 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1493 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1494 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1496 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1497 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1499 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1500 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1502 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1503 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1505 #undef TARGET_OPTION_OVERRIDE
1506 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1508 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1509 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1510 rs6000_builtin_vectorized_function
1513 #undef TARGET_STACK_PROTECT_FAIL
1514 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1517 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1518 The PowerPC architecture requires only weak consistency among
1519 processors--that is, memory accesses between processors need not be
1520 sequentially consistent and memory accesses among processors can occur
1521 in any order. The ability to order memory accesses weakly provides
1522 opportunities for more efficient use of the system bus. Unless a
1523 dependency exists, the 604e allows read operations to precede store
1525 #undef TARGET_RELAXED_ORDERING
1526 #define TARGET_RELAXED_ORDERING true
1529 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1530 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1533 /* Use a 32-bit anchor range. This leads to sequences like:
1535 addis tmp,anchor,high
1538 where tmp itself acts as an anchor, and can be shared between
1539 accesses to the same 64k page. */
1540 #undef TARGET_MIN_ANCHOR_OFFSET
1541 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1542 #undef TARGET_MAX_ANCHOR_OFFSET
1543 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1544 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1545 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1546 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1547 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1549 #undef TARGET_BUILTIN_RECIPROCAL
1550 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1552 #undef TARGET_EXPAND_TO_RTL_HOOK
1553 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1555 #undef TARGET_INSTANTIATE_DECLS
1556 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1558 #undef TARGET_SECONDARY_RELOAD
1559 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1561 #undef TARGET_LEGITIMATE_ADDRESS_P
1562 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1564 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1565 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1568 #define TARGET_LRA_P rs6000_lra_p
1570 #undef TARGET_CAN_ELIMINATE
1571 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1573 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1574 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1576 #undef TARGET_TRAMPOLINE_INIT
1577 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1579 #undef TARGET_FUNCTION_VALUE
1580 #define TARGET_FUNCTION_VALUE rs6000_function_value
1582 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1583 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1585 #undef TARGET_OPTION_SAVE
1586 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1588 #undef TARGET_OPTION_RESTORE
1589 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1591 #undef TARGET_OPTION_PRINT
1592 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1594 #undef TARGET_CAN_INLINE_P
1595 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1597 #undef TARGET_SET_CURRENT_FUNCTION
1598 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1600 #undef TARGET_LEGITIMATE_CONSTANT_P
1601 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1603 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1604 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1606 #undef TARGET_CAN_USE_DOLOOP_P
1607 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1610 /* Processor table. */
1613 const char *const name
; /* Canonical processor name. */
1614 const enum processor_type processor
; /* Processor type enum value. */
1615 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1618 static struct rs6000_ptt
const processor_target_table
[] =
1620 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1621 #include "rs6000-cpus.def"
1625 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1629 rs6000_cpu_name_lookup (const char *name
)
1635 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1636 if (! strcmp (name
, processor_target_table
[i
].name
))
1644 /* Return number of consecutive hard regs needed starting at reg REGNO
1645 to hold something of mode MODE.
1646 This is ordinarily the length in words of a value of mode MODE
1647 but can be less for certain modes in special long registers.
1649 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1650 scalar instructions. The upper 32 bits are only available to the
1653 POWER and PowerPC GPRs hold 32 bits worth;
1654 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1657 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1659 unsigned HOST_WIDE_INT reg_size
;
1661 /* TF/TD modes are special in that they always take 2 registers. */
1662 if (FP_REGNO_P (regno
))
1663 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1664 ? UNITS_PER_VSX_WORD
1665 : UNITS_PER_FP_WORD
);
1667 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1668 reg_size
= UNITS_PER_SPE_WORD
;
1670 else if (ALTIVEC_REGNO_P (regno
))
1671 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1673 /* The value returned for SCmode in the E500 double case is 2 for
1674 ABI compatibility; storing an SCmode value in a single register
1675 would require function_arg and rs6000_spe_function_arg to handle
1676 SCmode so as to pass the value correctly in a pair of
1678 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1679 && !DECIMAL_FLOAT_MODE_P (mode
))
1680 reg_size
= UNITS_PER_FP_WORD
;
1683 reg_size
= UNITS_PER_WORD
;
1685 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1688 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1691 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1693 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1695 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1696 register combinations, and use PTImode where we need to deal with quad
1697 word memory operations. Don't allow quad words in the argument or frame
1698 pointer registers, just registers 0..31. */
1699 if (mode
== PTImode
)
1700 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1701 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1702 && ((regno
& 1) == 0));
1704 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1705 implementations. Don't allow an item to be split between a FP register
1706 and an Altivec register. Allow TImode in all VSX registers if the user
1708 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1709 && (VECTOR_MEM_VSX_P (mode
)
1710 || (TARGET_VSX_SCALAR_FLOAT
&& mode
== SFmode
)
1711 || (TARGET_VSX_SCALAR_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
1712 || (TARGET_VSX_TIMODE
&& mode
== TImode
)))
1714 if (FP_REGNO_P (regno
))
1715 return FP_REGNO_P (last_regno
);
1717 if (ALTIVEC_REGNO_P (regno
))
1719 if (mode
== SFmode
&& !TARGET_UPPER_REGS_SF
)
1722 if ((mode
== DFmode
|| mode
== DImode
) && !TARGET_UPPER_REGS_DF
)
1725 return ALTIVEC_REGNO_P (last_regno
);
1729 /* The GPRs can hold any mode, but values bigger than one register
1730 cannot go past R31. */
1731 if (INT_REGNO_P (regno
))
1732 return INT_REGNO_P (last_regno
);
1734 /* The float registers (except for VSX vector modes) can only hold floating
1735 modes and DImode. */
1736 if (FP_REGNO_P (regno
))
1738 if (SCALAR_FLOAT_MODE_P (mode
)
1739 && (mode
!= TDmode
|| (regno
% 2) == 0)
1740 && FP_REGNO_P (last_regno
))
1743 if (GET_MODE_CLASS (mode
) == MODE_INT
1744 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1747 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1748 && PAIRED_VECTOR_MODE (mode
))
1754 /* The CR register can only hold CC modes. */
1755 if (CR_REGNO_P (regno
))
1756 return GET_MODE_CLASS (mode
) == MODE_CC
;
1758 if (CA_REGNO_P (regno
))
1759 return mode
== BImode
;
1761 /* AltiVec only in AldyVec registers. */
1762 if (ALTIVEC_REGNO_P (regno
))
1763 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1765 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1766 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1769 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1770 and it must be able to fit within the register set. */
1772 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1775 /* Print interesting facts about registers. */
1777 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1781 for (r
= first_regno
; r
<= last_regno
; ++r
)
1783 const char *comma
= "";
1786 if (first_regno
== last_regno
)
1787 fprintf (stderr
, "%s:\t", reg_name
);
1789 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1792 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1793 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1797 fprintf (stderr
, ",\n\t");
1802 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1803 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1804 rs6000_hard_regno_nregs
[m
][r
]);
1806 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1811 if (call_used_regs
[r
])
1815 fprintf (stderr
, ",\n\t");
1820 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1828 fprintf (stderr
, ",\n\t");
1833 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1839 fprintf (stderr
, ",\n\t");
1843 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1844 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1849 fprintf (stderr
, ",\n\t");
1853 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1858 rs6000_debug_vector_unit (enum rs6000_vector v
)
1864 case VECTOR_NONE
: ret
= "none"; break;
1865 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1866 case VECTOR_VSX
: ret
= "vsx"; break;
1867 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1868 case VECTOR_PAIRED
: ret
= "paired"; break;
1869 case VECTOR_SPE
: ret
= "spe"; break;
1870 case VECTOR_OTHER
: ret
= "other"; break;
1871 default: ret
= "unknown"; break;
1877 /* Print the address masks in a human readble fashion. */
1879 rs6000_debug_print_mode (ssize_t m
)
1883 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1884 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1886 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1888 " %s: %c%c%c%c%c%c",
1889 reload_reg_map
[rc
].name
,
1890 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1891 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1892 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1893 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1894 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1895 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1898 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1899 || rs6000_vector_mem
[m
] != VECTOR_NONE
1900 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1901 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
1904 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
1905 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1906 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1907 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1908 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
1911 fputs ("\n", stderr
);
1914 #define DEBUG_FMT_ID "%-32s= "
1915 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1916 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1917 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1919 /* Print various interesting information with -mdebug=reg. */
1921 rs6000_debug_reg_global (void)
1923 static const char *const tf
[2] = { "false", "true" };
1924 const char *nl
= (const char *)0;
1927 char costly_num
[20];
1929 char flags_buffer
[40];
1930 const char *costly_str
;
1931 const char *nop_str
;
1932 const char *trace_str
;
1933 const char *abi_str
;
1934 const char *cmodel_str
;
1935 struct cl_target_option cl_opts
;
1937 /* Modes we want tieable information on. */
1938 static const enum machine_mode print_tieable_modes
[] = {
1972 /* Virtual regs we are interested in. */
1973 const static struct {
1974 int regno
; /* register number. */
1975 const char *name
; /* register name. */
1976 } virtual_regs
[] = {
1977 { STACK_POINTER_REGNUM
, "stack pointer:" },
1978 { TOC_REGNUM
, "toc: " },
1979 { STATIC_CHAIN_REGNUM
, "static chain: " },
1980 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
1981 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
1982 { ARG_POINTER_REGNUM
, "arg pointer: " },
1983 { FRAME_POINTER_REGNUM
, "frame pointer:" },
1984 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
1985 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
1986 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
1987 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
1988 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
1989 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
1990 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
1991 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
1992 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
1995 fputs ("\nHard register information:\n", stderr
);
1996 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
1997 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
1998 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2001 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2002 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2003 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2004 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2005 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2006 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2007 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2008 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2010 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2011 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2012 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2016 "d reg_class = %s\n"
2017 "f reg_class = %s\n"
2018 "v reg_class = %s\n"
2019 "wa reg_class = %s\n"
2020 "wd reg_class = %s\n"
2021 "wf reg_class = %s\n"
2022 "wg reg_class = %s\n"
2023 "wl reg_class = %s\n"
2024 "wm reg_class = %s\n"
2025 "wr reg_class = %s\n"
2026 "ws reg_class = %s\n"
2027 "wt reg_class = %s\n"
2028 "wu reg_class = %s\n"
2029 "wv reg_class = %s\n"
2030 "ww reg_class = %s\n"
2031 "wx reg_class = %s\n"
2032 "wy reg_class = %s\n"
2033 "wz reg_class = %s\n"
2035 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2036 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2037 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2038 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2039 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2040 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2041 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2042 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2043 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2044 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2045 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2046 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2047 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2048 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2049 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2050 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2051 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2052 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2055 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2056 rs6000_debug_print_mode (m
);
2058 fputs ("\n", stderr
);
2060 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2062 enum machine_mode mode1
= print_tieable_modes
[m1
];
2063 bool first_time
= true;
2065 nl
= (const char *)0;
2066 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2068 enum machine_mode mode2
= print_tieable_modes
[m2
];
2069 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2073 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2078 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2083 fputs ("\n", stderr
);
2089 if (rs6000_recip_control
)
2091 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2093 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2094 if (rs6000_recip_bits
[m
])
2097 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2099 (RS6000_RECIP_AUTO_RE_P (m
)
2101 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2102 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2104 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2107 fputs ("\n", stderr
);
2110 if (rs6000_cpu_index
>= 0)
2112 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2114 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2116 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2117 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2120 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2122 if (rs6000_tune_index
>= 0)
2124 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2126 = processor_target_table
[rs6000_tune_index
].target_enable
;
2128 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2129 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2132 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2134 cl_target_option_save (&cl_opts
, &global_options
);
2135 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2138 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2139 rs6000_isa_flags_explicit
);
2141 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2142 rs6000_builtin_mask
);
2144 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2146 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2147 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2149 switch (rs6000_sched_costly_dep
)
2151 case max_dep_latency
:
2152 costly_str
= "max_dep_latency";
2156 costly_str
= "no_dep_costly";
2159 case all_deps_costly
:
2160 costly_str
= "all_deps_costly";
2163 case true_store_to_load_dep_costly
:
2164 costly_str
= "true_store_to_load_dep_costly";
2167 case store_to_load_dep_costly
:
2168 costly_str
= "store_to_load_dep_costly";
2172 costly_str
= costly_num
;
2173 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2177 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2179 switch (rs6000_sched_insert_nops
)
2181 case sched_finish_regroup_exact
:
2182 nop_str
= "sched_finish_regroup_exact";
2185 case sched_finish_pad_groups
:
2186 nop_str
= "sched_finish_pad_groups";
2189 case sched_finish_none
:
2190 nop_str
= "sched_finish_none";
2195 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2199 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2201 switch (rs6000_sdata
)
2208 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2212 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2216 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2221 switch (rs6000_traceback
)
2223 case traceback_default
: trace_str
= "default"; break;
2224 case traceback_none
: trace_str
= "none"; break;
2225 case traceback_part
: trace_str
= "part"; break;
2226 case traceback_full
: trace_str
= "full"; break;
2227 default: trace_str
= "unknown"; break;
2230 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2232 switch (rs6000_current_cmodel
)
2234 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2235 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2236 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2237 default: cmodel_str
= "unknown"; break;
2240 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2242 switch (rs6000_current_abi
)
2244 case ABI_NONE
: abi_str
= "none"; break;
2245 case ABI_AIX
: abi_str
= "aix"; break;
2246 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2247 case ABI_V4
: abi_str
= "V4"; break;
2248 case ABI_DARWIN
: abi_str
= "darwin"; break;
2249 default: abi_str
= "unknown"; break;
2252 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2254 if (rs6000_altivec_abi
)
2255 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2258 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2260 if (rs6000_darwin64_abi
)
2261 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2263 if (rs6000_float_gprs
)
2264 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2266 if (TARGET_LINK_STACK
)
2267 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2269 if (targetm
.lra_p ())
2270 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2272 if (TARGET_P8_FUSION
)
2273 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2274 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2276 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2277 TARGET_SECURE_PLT
? "secure" : "bss");
2278 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2279 aix_struct_return
? "aix" : "sysv");
2280 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2281 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2282 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2283 tf
[!!rs6000_align_branch_targets
]);
2284 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2285 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2286 rs6000_long_double_type_size
);
2287 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2288 (int)rs6000_sched_restricted_insns_priority
);
2289 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2291 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2292 (int)RS6000_BUILTIN_COUNT
);
2296 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2297 legitimate address support to figure out the appropriate addressing to
2301 rs6000_setup_reg_addr_masks (void)
2303 ssize_t rc
, reg
, m
, nregs
;
2304 addr_mask_type any_addr_mask
, addr_mask
;
2306 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2308 /* SDmode is special in that we want to access it only via REG+REG
2309 addressing on power7 and above, since we want to use the LFIWZX and
2310 STFIWZX instructions to load it. */
2311 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2314 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2317 reg
= reload_reg_map
[rc
].reg
;
2319 /* Can mode values go in the GPR/FPR/Altivec registers? */
2320 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2322 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2323 addr_mask
|= RELOAD_REG_VALID
;
2325 /* Indicate if the mode takes more than 1 physical register. If
2326 it takes a single register, indicate it can do REG+REG
2328 if (nregs
> 1 || m
== BLKmode
)
2329 addr_mask
|= RELOAD_REG_MULTIPLE
;
2331 addr_mask
|= RELOAD_REG_INDEXED
;
2333 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2334 addressing. Restrict addressing on SPE for 64-bit types
2335 because of the SUBREG hackery used to address 64-bit floats in
2336 '32-bit' GPRs. To simplify secondary reload, don't allow
2337 update forms on scalar floating point types that can go in the
2341 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2342 && GET_MODE_SIZE (m
) <= 8
2343 && !VECTOR_MODE_P (m
)
2344 && !COMPLEX_MODE_P (m
)
2346 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m
) == 8)
2347 && !(m
== DFmode
&& TARGET_UPPER_REGS_DF
)
2348 && !(m
== SFmode
&& TARGET_UPPER_REGS_SF
))
2350 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2352 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2353 we don't allow PRE_MODIFY for some multi-register
2358 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2362 if (TARGET_POWERPC64
)
2363 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2369 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2375 /* GPR and FPR registers can do REG+OFFSET addressing, except
2376 possibly for SDmode. */
2377 if ((addr_mask
!= 0) && !indexed_only_p
2378 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2379 addr_mask
|= RELOAD_REG_OFFSET
;
2381 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2382 any_addr_mask
|= addr_mask
;
2385 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2390 /* Initialize the various global tables that are based on register size. */
2392 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2398 /* Precalculate REGNO_REG_CLASS. */
2399 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2400 for (r
= 1; r
< 32; ++r
)
2401 rs6000_regno_regclass
[r
] = BASE_REGS
;
2403 for (r
= 32; r
< 64; ++r
)
2404 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2406 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2407 rs6000_regno_regclass
[r
] = NO_REGS
;
2409 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2410 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2412 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2413 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2414 rs6000_regno_regclass
[r
] = CR_REGS
;
2416 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2417 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2418 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2419 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2420 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2421 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2422 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2423 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2424 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2425 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2426 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2427 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2429 /* Precalculate register class to simpler reload register class. We don't
2430 need all of the register classes that are combinations of different
2431 classes, just the simple ones that have constraint letters. */
2432 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2433 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2435 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2436 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2437 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2438 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2439 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2440 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2441 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2442 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2443 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2444 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2445 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2446 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2450 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2451 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2455 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2456 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2459 /* Precalculate the valid memory formats as well as the vector information,
2460 this must be set up before the rs6000_hard_regno_nregs_internal calls
2462 gcc_assert ((int)VECTOR_NONE
== 0);
2463 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2464 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2466 gcc_assert ((int)CODE_FOR_nothing
== 0);
2467 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2469 gcc_assert ((int)NO_REGS
== 0);
2470 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2472 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2473 believes it can use native alignment or still uses 128-bit alignment. */
2474 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2485 /* V2DF mode, VSX only. */
2488 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2489 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2490 rs6000_vector_align
[V2DFmode
] = align64
;
2493 /* V4SF mode, either VSX or Altivec. */
2496 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2497 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2498 rs6000_vector_align
[V4SFmode
] = align32
;
2500 else if (TARGET_ALTIVEC
)
2502 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2503 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2504 rs6000_vector_align
[V4SFmode
] = align32
;
2507 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2511 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2512 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2513 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2514 rs6000_vector_align
[V4SImode
] = align32
;
2515 rs6000_vector_align
[V8HImode
] = align32
;
2516 rs6000_vector_align
[V16QImode
] = align32
;
2520 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2521 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2522 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2526 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2527 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2528 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2532 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2533 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2536 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2537 rs6000_vector_unit
[V2DImode
]
2538 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2539 rs6000_vector_align
[V2DImode
] = align64
;
2542 /* DFmode, see if we want to use the VSX unit. */
2543 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2545 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2546 rs6000_vector_mem
[DFmode
]
2547 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2548 rs6000_vector_align
[DFmode
] = align64
;
2551 /* Allow TImode in VSX register and set the VSX memory macros. */
2552 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2554 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2555 rs6000_vector_align
[TImode
] = align64
;
2558 /* TODO add SPE and paired floating point vector support. */
2560 /* Register class constraints for the constraints that depend on compile
2561 switches. When the VSX code was added, different constraints were added
2562 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2563 of the VSX registers are used. The register classes for scalar floating
2564 point types is set, based on whether we allow that type into the upper
2565 (Altivec) registers. GCC has register classes to target the Altivec
2566 registers for load/store operations, to select using a VSX memory
2567 operation instead of the traditional floating point operation. The
2570 d - Register class to use with traditional DFmode instructions.
2571 f - Register class to use with traditional SFmode instructions.
2572 v - Altivec register.
2573 wa - Any VSX register.
2574 wd - Preferred register class for V2DFmode.
2575 wf - Preferred register class for V4SFmode.
2576 wg - Float register for power6x move insns.
2577 wl - Float register if we can do 32-bit signed int loads.
2578 wm - VSX register for ISA 2.07 direct move operations.
2579 wr - GPR if 64-bit mode is permitted.
2580 ws - Register class to do ISA 2.06 DF operations.
2581 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2582 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2583 wt - VSX register for TImode in VSX registers.
2584 ww - Register class to do SF conversions in with VSX operations.
2585 wx - Float register if we can do 32-bit int stores.
2586 wy - Register class to do ISA 2.07 SF operations.
2587 wz - Float register if we can do 32-bit unsigned int loads. */
2589 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2590 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2592 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2593 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2597 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2598 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2599 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2601 if (TARGET_VSX_TIMODE
)
2602 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2604 if (TARGET_UPPER_REGS_DF
)
2606 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2607 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2610 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2613 /* Add conditional constraints based on various options, to allow us to
2614 collapse multiple insn patterns. */
2616 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2619 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2622 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2624 if (TARGET_DIRECT_MOVE
)
2625 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2627 if (TARGET_POWERPC64
)
2628 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2630 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
)
2632 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2633 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2634 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2636 else if (TARGET_P8_VECTOR
)
2638 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2639 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2641 else if (TARGET_VSX
)
2642 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2645 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2648 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2650 /* Set up the reload helper and direct move functions. */
2651 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2655 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2656 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2657 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2658 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2659 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2660 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2661 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2662 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2663 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2664 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2665 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2666 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2667 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2669 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2670 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2671 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2672 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2674 if (TARGET_P8_VECTOR
)
2676 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2677 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2678 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2679 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2681 if (TARGET_VSX_TIMODE
)
2683 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2684 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2686 if (TARGET_DIRECT_MOVE
)
2688 if (TARGET_POWERPC64
)
2690 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2691 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2692 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2693 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2694 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2695 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2696 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2697 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2699 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2700 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2701 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2702 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2703 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2704 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2705 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2706 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2710 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2711 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2712 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2718 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2719 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2720 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2721 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2722 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2723 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2724 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2725 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2726 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2727 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2728 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2729 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2730 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2732 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2733 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2734 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2735 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2737 if (TARGET_P8_VECTOR
)
2739 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2740 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2741 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2742 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2744 if (TARGET_VSX_TIMODE
)
2746 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2747 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2752 /* Precalculate HARD_REGNO_NREGS. */
2753 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2754 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2755 rs6000_hard_regno_nregs
[m
][r
]
2756 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2758 /* Precalculate HARD_REGNO_MODE_OK. */
2759 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2760 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2761 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2762 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2764 /* Precalculate CLASS_MAX_NREGS sizes. */
2765 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2769 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2770 reg_size
= UNITS_PER_VSX_WORD
;
2772 else if (c
== ALTIVEC_REGS
)
2773 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2775 else if (c
== FLOAT_REGS
)
2776 reg_size
= UNITS_PER_FP_WORD
;
2779 reg_size
= UNITS_PER_WORD
;
2781 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2783 int reg_size2
= reg_size
;
2785 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2786 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2787 && (m
== TDmode
|| m
== TFmode
))
2788 reg_size2
= UNITS_PER_FP_WORD
;
2790 rs6000_class_max_nregs
[m
][c
]
2791 = (GET_MODE_SIZE (m
) + reg_size2
- 1) / reg_size2
;
2795 if (TARGET_E500_DOUBLE
)
2796 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2798 /* Calculate which modes to automatically generate code to use a the
2799 reciprocal divide and square root instructions. In the future, possibly
2800 automatically generate the instructions even if the user did not specify
2801 -mrecip. The older machines double precision reciprocal sqrt estimate is
2802 not accurate enough. */
2803 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2805 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2807 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2808 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2809 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2810 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2811 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2813 if (TARGET_FRSQRTES
)
2814 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2816 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2817 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2818 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2819 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2820 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2822 if (rs6000_recip_control
)
2824 if (!flag_finite_math_only
)
2825 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2826 if (flag_trapping_math
)
2827 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2828 if (!flag_reciprocal_math
)
2829 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2830 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2832 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2833 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2834 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2836 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2837 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2838 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2840 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2841 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2842 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2844 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2845 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2846 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2848 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2849 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2850 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2852 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2853 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2854 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2856 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2857 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2858 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2860 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2861 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2862 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2866 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2867 legitimate address support to figure out the appropriate addressing to
2869 rs6000_setup_reg_addr_masks ();
2871 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2873 if (TARGET_DEBUG_REG
)
2874 rs6000_debug_reg_global ();
2876 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2878 "SImode variable mult cost = %d\n"
2879 "SImode constant mult cost = %d\n"
2880 "SImode short constant mult cost = %d\n"
2881 "DImode multipliciation cost = %d\n"
2882 "SImode division cost = %d\n"
2883 "DImode division cost = %d\n"
2884 "Simple fp operation cost = %d\n"
2885 "DFmode multiplication cost = %d\n"
2886 "SFmode division cost = %d\n"
2887 "DFmode division cost = %d\n"
2888 "cache line size = %d\n"
2889 "l1 cache size = %d\n"
2890 "l2 cache size = %d\n"
2891 "simultaneous prefetches = %d\n"
2894 rs6000_cost
->mulsi_const
,
2895 rs6000_cost
->mulsi_const9
,
2903 rs6000_cost
->cache_line_size
,
2904 rs6000_cost
->l1_cache_size
,
2905 rs6000_cost
->l2_cache_size
,
2906 rs6000_cost
->simultaneous_prefetches
);
2911 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2914 darwin_rs6000_override_options (void)
2916 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2918 rs6000_altivec_abi
= 1;
2919 TARGET_ALTIVEC_VRSAVE
= 1;
2920 rs6000_current_abi
= ABI_DARWIN
;
2922 if (DEFAULT_ABI
== ABI_DARWIN
2924 darwin_one_byte_bool
= 1;
2926 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2928 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2929 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2933 rs6000_default_long_calls
= 1;
2934 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2937 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2939 if (!flag_mkernel
&& !flag_apple_kext
2941 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2942 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2944 /* Unless the user (not the configurer) has explicitly overridden
2945 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2946 G4 unless targeting the kernel. */
2949 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2950 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2951 && ! global_options_set
.x_rs6000_cpu_index
)
2953 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2958 /* If not otherwise specified by a target, make 'long double' equivalent to
2961 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2962 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2965 /* Return the builtin mask of the various options used that could affect which
2966 builtins were used. In the past we used target_flags, but we've run out of
2967 bits, and some options like SPE and PAIRED are no longer in
2971 rs6000_builtin_mask_calculate (void)
2973 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2974 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2975 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2976 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2977 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2978 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2979 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2980 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2981 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2982 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
2983 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
2984 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
2985 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0));
2988 /* Override command line options. Mostly we process the processor type and
2989 sometimes adjust other TARGET_ options. */
2992 rs6000_option_override_internal (bool global_init_p
)
2995 bool have_cpu
= false;
2997 /* The default cpu requested at configure time, if any. */
2998 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3000 HOST_WIDE_INT set_masks
;
3003 struct cl_target_option
*main_target_opt
3004 = ((global_init_p
|| target_option_default_node
== NULL
)
3005 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3007 /* Remember the explicit arguments. */
3009 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3011 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3012 library functions, so warn about it. The flag may be useful for
3013 performance studies from time to time though, so don't disable it
3015 if (global_options_set
.x_rs6000_alignment_flags
3016 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3017 && DEFAULT_ABI
== ABI_DARWIN
3019 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3020 " it is incompatible with the installed C and C++ libraries");
3022 /* Numerous experiment shows that IRA based loop pressure
3023 calculation works better for RTL loop invariant motion on targets
3024 with enough (>= 32) registers. It is an expensive optimization.
3025 So it is on only for peak performance. */
3026 if (optimize
>= 3 && global_init_p
)
3027 flag_ira_loop_pressure
= 1;
3029 /* Set the pointer size. */
3032 rs6000_pmode
= (int)DImode
;
3033 rs6000_pointer_size
= 64;
3037 rs6000_pmode
= (int)SImode
;
3038 rs6000_pointer_size
= 32;
3041 /* Some OSs don't support saving the high part of 64-bit registers on context
3042 switch. Other OSs don't support saving Altivec registers. On those OSs,
3043 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3044 if the user wants either, the user must explicitly specify them and we
3045 won't interfere with the user's specification. */
3047 set_masks
= POWERPC_MASKS
;
3048 #ifdef OS_MISSING_POWERPC64
3049 if (OS_MISSING_POWERPC64
)
3050 set_masks
&= ~OPTION_MASK_POWERPC64
;
3052 #ifdef OS_MISSING_ALTIVEC
3053 if (OS_MISSING_ALTIVEC
)
3054 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3057 /* Don't override by the processor default if given explicitly. */
3058 set_masks
&= ~rs6000_isa_flags_explicit
;
3060 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3061 the cpu in a target attribute or pragma, but did not specify a tuning
3062 option, use the cpu for the tuning option rather than the option specified
3063 with -mtune on the command line. Process a '--with-cpu' configuration
3064 request as an implicit --cpu. */
3065 if (rs6000_cpu_index
>= 0)
3067 cpu_index
= rs6000_cpu_index
;
3070 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3072 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3075 else if (implicit_cpu
)
3077 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3082 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3083 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3087 gcc_assert (cpu_index
>= 0);
3089 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3090 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3091 with those from the cpu, except for options that were explicitly set. If
3092 we don't have a cpu, do not override the target bits set in
3096 rs6000_isa_flags
&= ~set_masks
;
3097 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3101 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3102 & ~rs6000_isa_flags_explicit
);
3104 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3105 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3106 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3107 to using rs6000_isa_flags, we need to do the initialization here. */
3109 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3111 if (rs6000_tune_index
>= 0)
3112 tune_index
= rs6000_tune_index
;
3114 rs6000_tune_index
= tune_index
= cpu_index
;
3118 enum processor_type tune_proc
3119 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3122 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3123 if (processor_target_table
[i
].processor
== tune_proc
)
3125 rs6000_tune_index
= tune_index
= i
;
3130 gcc_assert (tune_index
>= 0);
3131 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3133 /* Pick defaults for SPE related control flags. Do this early to make sure
3134 that the TARGET_ macros are representative ASAP. */
3136 int spe_capable_cpu
=
3137 (rs6000_cpu
== PROCESSOR_PPC8540
3138 || rs6000_cpu
== PROCESSOR_PPC8548
);
3140 if (!global_options_set
.x_rs6000_spe_abi
)
3141 rs6000_spe_abi
= spe_capable_cpu
;
3143 if (!global_options_set
.x_rs6000_spe
)
3144 rs6000_spe
= spe_capable_cpu
;
3146 if (!global_options_set
.x_rs6000_float_gprs
)
3148 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3149 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3153 if (global_options_set
.x_rs6000_spe_abi
3156 error ("not configured for SPE ABI");
3158 if (global_options_set
.x_rs6000_spe
3161 error ("not configured for SPE instruction set");
3163 if (main_target_opt
!= NULL
3164 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3165 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3166 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3167 error ("target attribute or pragma changes SPE ABI");
3169 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3170 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3171 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3174 error ("AltiVec not supported in this target");
3176 error ("SPE not supported in this target");
3178 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3181 error ("SPE not supported in this target");
3184 /* Disable Cell microcode if we are optimizing for the Cell
3185 and not optimizing for size. */
3186 if (rs6000_gen_cell_microcode
== -1)
3187 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3190 /* If we are optimizing big endian systems for space and it's OK to
3191 use instructions that would be microcoded on the Cell, use the
3192 load/store multiple and string instructions. */
3193 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3194 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3195 | OPTION_MASK_STRING
);
3197 /* Don't allow -mmultiple or -mstring on little endian systems
3198 unless the cpu is a 750, because the hardware doesn't support the
3199 instructions used in little endian mode, and causes an alignment
3200 trap. The 750 does not cause an alignment trap (except when the
3201 target is unaligned). */
3203 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3205 if (TARGET_MULTIPLE
)
3207 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3208 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3209 warning (0, "-mmultiple is not supported on little endian systems");
3214 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3215 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3216 warning (0, "-mstring is not supported on little endian systems");
3220 /* Add some warnings for VSX. */
3223 const char *msg
= NULL
;
3224 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3225 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3227 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3228 msg
= N_("-mvsx requires hardware floating point");
3231 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3232 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3235 else if (TARGET_PAIRED_FLOAT
)
3236 msg
= N_("-mvsx and -mpaired are incompatible");
3237 else if (TARGET_AVOID_XFORM
> 0)
3238 msg
= N_("-mvsx needs indexed addressing");
3239 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3240 & OPTION_MASK_ALTIVEC
))
3242 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3243 msg
= N_("-mvsx and -mno-altivec are incompatible");
3245 msg
= N_("-mno-altivec disables vsx");
3251 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3252 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3256 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3257 the -mcpu setting to enable options that conflict. */
3258 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3259 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3260 | OPTION_MASK_ALTIVEC
3261 | OPTION_MASK_VSX
)) != 0)
3262 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3263 | OPTION_MASK_DIRECT_MOVE
)
3264 & ~rs6000_isa_flags_explicit
);
3266 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3267 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3269 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3270 unless the user explicitly used the -mno-<option> to disable the code. */
3271 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3272 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3273 else if (TARGET_VSX
)
3274 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3275 else if (TARGET_POPCNTD
)
3276 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3277 else if (TARGET_DFP
)
3278 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3279 else if (TARGET_CMPB
)
3280 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3281 else if (TARGET_FPRND
)
3282 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3283 else if (TARGET_POPCNTB
)
3284 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3285 else if (TARGET_ALTIVEC
)
3286 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3288 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3290 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3291 error ("-mcrypto requires -maltivec");
3292 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3295 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3297 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3298 error ("-mdirect-move requires -mvsx");
3299 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3302 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3304 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3305 error ("-mpower8-vector requires -maltivec");
3306 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3309 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3311 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3312 error ("-mpower8-vector requires -mvsx");
3313 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3316 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3318 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3319 error ("-mvsx-timode requires -mvsx");
3320 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3323 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3324 silently turn off quad memory mode. */
3325 if (TARGET_QUAD_MEMORY
&& !TARGET_POWERPC64
)
3327 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3328 warning (0, N_("-mquad-memory requires 64-bit mode"));
3330 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3333 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3334 generating power8 instructions. */
3335 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3336 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3337 & OPTION_MASK_P8_FUSION
);
3339 /* Power8 does not fuse sign extended loads with the addis. If we are
3340 optimizing at high levels for speed, convert a sign extended load into a
3341 zero extending load, and an explicit sign extension. */
3342 if (TARGET_P8_FUSION
3343 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3344 && optimize_function_for_speed_p (cfun
)
3346 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3348 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3349 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3351 /* E500mc does "better" if we inline more aggressively. Respect the
3352 user's opinion, though. */
3353 if (rs6000_block_move_inline_limit
== 0
3354 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3355 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3356 || rs6000_cpu
== PROCESSOR_PPCE5500
3357 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3358 rs6000_block_move_inline_limit
= 128;
3360 /* store_one_arg depends on expand_block_move to handle at least the
3361 size of reg_parm_stack_space. */
3362 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3363 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3367 /* If the appropriate debug option is enabled, replace the target hooks
3368 with debug versions that call the real version and then prints
3369 debugging information. */
3370 if (TARGET_DEBUG_COST
)
3372 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3373 targetm
.address_cost
= rs6000_debug_address_cost
;
3374 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3377 if (TARGET_DEBUG_ADDR
)
3379 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3380 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3381 rs6000_secondary_reload_class_ptr
3382 = rs6000_debug_secondary_reload_class
;
3383 rs6000_secondary_memory_needed_ptr
3384 = rs6000_debug_secondary_memory_needed
;
3385 rs6000_cannot_change_mode_class_ptr
3386 = rs6000_debug_cannot_change_mode_class
;
3387 rs6000_preferred_reload_class_ptr
3388 = rs6000_debug_preferred_reload_class
;
3389 rs6000_legitimize_reload_address_ptr
3390 = rs6000_debug_legitimize_reload_address
;
3391 rs6000_mode_dependent_address_ptr
3392 = rs6000_debug_mode_dependent_address
;
3395 if (rs6000_veclibabi_name
)
3397 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3398 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3401 error ("unknown vectorization library ABI type (%s) for "
3402 "-mveclibabi= switch", rs6000_veclibabi_name
);
3408 if (!global_options_set
.x_rs6000_long_double_type_size
)
3410 if (main_target_opt
!= NULL
3411 && (main_target_opt
->x_rs6000_long_double_type_size
3412 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3413 error ("target attribute or pragma changes long double size");
3415 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3418 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3419 if (!global_options_set
.x_rs6000_ieeequad
)
3420 rs6000_ieeequad
= 1;
3423 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3424 target attribute or pragma which automatically enables both options,
3425 unless the altivec ABI was set. This is set by default for 64-bit, but
3427 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3428 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3429 & ~rs6000_isa_flags_explicit
);
3431 /* Enable Altivec ABI for AIX -maltivec. */
3432 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3434 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3435 error ("target attribute or pragma changes AltiVec ABI");
3437 rs6000_altivec_abi
= 1;
3440 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3441 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3442 be explicitly overridden in either case. */
3445 if (!global_options_set
.x_rs6000_altivec_abi
3446 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3448 if (main_target_opt
!= NULL
&&
3449 !main_target_opt
->x_rs6000_altivec_abi
)
3450 error ("target attribute or pragma changes AltiVec ABI");
3452 rs6000_altivec_abi
= 1;
3456 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3457 So far, the only darwin64 targets are also MACH-O. */
3459 && DEFAULT_ABI
== ABI_DARWIN
3462 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3463 error ("target attribute or pragma changes darwin64 ABI");
3466 rs6000_darwin64_abi
= 1;
3467 /* Default to natural alignment, for better performance. */
3468 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3472 /* Place FP constants in the constant pool instead of TOC
3473 if section anchors enabled. */
3474 if (flag_section_anchors
3475 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3476 TARGET_NO_FP_IN_TOC
= 1;
3478 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3479 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3481 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3482 SUBTARGET_OVERRIDE_OPTIONS
;
3484 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3485 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3487 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3488 SUB3TARGET_OVERRIDE_OPTIONS
;
3491 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3492 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3494 /* For the E500 family of cores, reset the single/double FP flags to let us
3495 check that they remain constant across attributes or pragmas. Also,
3496 clear a possible request for string instructions, not supported and which
3497 we might have silently queried above for -Os.
3499 For other families, clear ISEL in case it was set implicitly.
3504 case PROCESSOR_PPC8540
:
3505 case PROCESSOR_PPC8548
:
3506 case PROCESSOR_PPCE500MC
:
3507 case PROCESSOR_PPCE500MC64
:
3508 case PROCESSOR_PPCE5500
:
3509 case PROCESSOR_PPCE6500
:
3511 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3512 rs6000_double_float
= TARGET_E500_DOUBLE
;
3514 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3520 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3521 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3526 if (main_target_opt
)
3528 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3529 error ("target attribute or pragma changes single precision floating "
3531 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3532 error ("target attribute or pragma changes double precision floating "
3536 /* Detect invalid option combinations with E500. */
3539 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3540 && rs6000_cpu
!= PROCESSOR_POWER5
3541 && rs6000_cpu
!= PROCESSOR_POWER6
3542 && rs6000_cpu
!= PROCESSOR_POWER7
3543 && rs6000_cpu
!= PROCESSOR_POWER8
3544 && rs6000_cpu
!= PROCESSOR_PPCA2
3545 && rs6000_cpu
!= PROCESSOR_CELL
3546 && rs6000_cpu
!= PROCESSOR_PPC476
);
3547 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3548 || rs6000_cpu
== PROCESSOR_POWER5
3549 || rs6000_cpu
== PROCESSOR_POWER7
3550 || rs6000_cpu
== PROCESSOR_POWER8
);
3551 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3552 || rs6000_cpu
== PROCESSOR_POWER5
3553 || rs6000_cpu
== PROCESSOR_POWER6
3554 || rs6000_cpu
== PROCESSOR_POWER7
3555 || rs6000_cpu
== PROCESSOR_POWER8
3556 || rs6000_cpu
== PROCESSOR_PPCE500MC
3557 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3558 || rs6000_cpu
== PROCESSOR_PPCE5500
3559 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3561 /* Allow debug switches to override the above settings. These are set to -1
3562 in rs6000.opt to indicate the user hasn't directly set the switch. */
3563 if (TARGET_ALWAYS_HINT
>= 0)
3564 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3566 if (TARGET_SCHED_GROUPS
>= 0)
3567 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3569 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3570 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3572 rs6000_sched_restricted_insns_priority
3573 = (rs6000_sched_groups
? 1 : 0);
3575 /* Handle -msched-costly-dep option. */
3576 rs6000_sched_costly_dep
3577 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3579 if (rs6000_sched_costly_dep_str
)
3581 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3582 rs6000_sched_costly_dep
= no_dep_costly
;
3583 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3584 rs6000_sched_costly_dep
= all_deps_costly
;
3585 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3586 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3587 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3588 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3590 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3591 atoi (rs6000_sched_costly_dep_str
));
3594 /* Handle -minsert-sched-nops option. */
3595 rs6000_sched_insert_nops
3596 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3598 if (rs6000_sched_insert_nops_str
)
3600 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3601 rs6000_sched_insert_nops
= sched_finish_none
;
3602 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3603 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3604 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3605 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3607 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3608 atoi (rs6000_sched_insert_nops_str
));
3613 #ifdef TARGET_REGNAMES
3614 /* If the user desires alternate register names, copy in the
3615 alternate names now. */
3616 if (TARGET_REGNAMES
)
3617 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3620 /* Set aix_struct_return last, after the ABI is determined.
3621 If -maix-struct-return or -msvr4-struct-return was explicitly
3622 used, don't override with the ABI default. */
3623 if (!global_options_set
.x_aix_struct_return
)
3624 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3627 /* IBM XL compiler defaults to unsigned bitfields. */
3628 if (TARGET_XL_COMPAT
)
3629 flag_signed_bitfields
= 0;
3632 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3633 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3636 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3638 /* We can only guarantee the availability of DI pseudo-ops when
3639 assembling for 64-bit targets. */
3642 targetm
.asm_out
.aligned_op
.di
= NULL
;
3643 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3647 /* Set branch target alignment, if not optimizing for size. */
3650 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3651 aligned 8byte to avoid misprediction by the branch predictor. */
3652 if (rs6000_cpu
== PROCESSOR_TITAN
3653 || rs6000_cpu
== PROCESSOR_CELL
)
3655 if (align_functions
<= 0)
3656 align_functions
= 8;
3657 if (align_jumps
<= 0)
3659 if (align_loops
<= 0)
3662 if (rs6000_align_branch_targets
)
3664 if (align_functions
<= 0)
3665 align_functions
= 16;
3666 if (align_jumps
<= 0)
3668 if (align_loops
<= 0)
3670 can_override_loop_align
= 1;
3674 if (align_jumps_max_skip
<= 0)
3675 align_jumps_max_skip
= 15;
3676 if (align_loops_max_skip
<= 0)
3677 align_loops_max_skip
= 15;
3680 /* Arrange to save and restore machine status around nested functions. */
3681 init_machine_status
= rs6000_init_machine_status
;
3683 /* We should always be splitting complex arguments, but we can't break
3684 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3685 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
3686 targetm
.calls
.split_complex_arg
= NULL
;
3689 /* Initialize rs6000_cost with the appropriate target costs. */
3691 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3695 case PROCESSOR_RS64A
:
3696 rs6000_cost
= &rs64a_cost
;
3699 case PROCESSOR_MPCCORE
:
3700 rs6000_cost
= &mpccore_cost
;
3703 case PROCESSOR_PPC403
:
3704 rs6000_cost
= &ppc403_cost
;
3707 case PROCESSOR_PPC405
:
3708 rs6000_cost
= &ppc405_cost
;
3711 case PROCESSOR_PPC440
:
3712 rs6000_cost
= &ppc440_cost
;
3715 case PROCESSOR_PPC476
:
3716 rs6000_cost
= &ppc476_cost
;
3719 case PROCESSOR_PPC601
:
3720 rs6000_cost
= &ppc601_cost
;
3723 case PROCESSOR_PPC603
:
3724 rs6000_cost
= &ppc603_cost
;
3727 case PROCESSOR_PPC604
:
3728 rs6000_cost
= &ppc604_cost
;
3731 case PROCESSOR_PPC604e
:
3732 rs6000_cost
= &ppc604e_cost
;
3735 case PROCESSOR_PPC620
:
3736 rs6000_cost
= &ppc620_cost
;
3739 case PROCESSOR_PPC630
:
3740 rs6000_cost
= &ppc630_cost
;
3743 case PROCESSOR_CELL
:
3744 rs6000_cost
= &ppccell_cost
;
3747 case PROCESSOR_PPC750
:
3748 case PROCESSOR_PPC7400
:
3749 rs6000_cost
= &ppc750_cost
;
3752 case PROCESSOR_PPC7450
:
3753 rs6000_cost
= &ppc7450_cost
;
3756 case PROCESSOR_PPC8540
:
3757 case PROCESSOR_PPC8548
:
3758 rs6000_cost
= &ppc8540_cost
;
3761 case PROCESSOR_PPCE300C2
:
3762 case PROCESSOR_PPCE300C3
:
3763 rs6000_cost
= &ppce300c2c3_cost
;
3766 case PROCESSOR_PPCE500MC
:
3767 rs6000_cost
= &ppce500mc_cost
;
3770 case PROCESSOR_PPCE500MC64
:
3771 rs6000_cost
= &ppce500mc64_cost
;
3774 case PROCESSOR_PPCE5500
:
3775 rs6000_cost
= &ppce5500_cost
;
3778 case PROCESSOR_PPCE6500
:
3779 rs6000_cost
= &ppce6500_cost
;
3782 case PROCESSOR_TITAN
:
3783 rs6000_cost
= &titan_cost
;
3786 case PROCESSOR_POWER4
:
3787 case PROCESSOR_POWER5
:
3788 rs6000_cost
= &power4_cost
;
3791 case PROCESSOR_POWER6
:
3792 rs6000_cost
= &power6_cost
;
3795 case PROCESSOR_POWER7
:
3796 rs6000_cost
= &power7_cost
;
3799 case PROCESSOR_POWER8
:
3800 rs6000_cost
= &power8_cost
;
3803 case PROCESSOR_PPCA2
:
3804 rs6000_cost
= &ppca2_cost
;
3813 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3814 rs6000_cost
->simultaneous_prefetches
,
3815 global_options
.x_param_values
,
3816 global_options_set
.x_param_values
);
3817 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3818 global_options
.x_param_values
,
3819 global_options_set
.x_param_values
);
3820 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3821 rs6000_cost
->cache_line_size
,
3822 global_options
.x_param_values
,
3823 global_options_set
.x_param_values
);
3824 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3825 global_options
.x_param_values
,
3826 global_options_set
.x_param_values
);
3828 /* Increase loop peeling limits based on performance analysis. */
3829 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3830 global_options
.x_param_values
,
3831 global_options_set
.x_param_values
);
3832 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3833 global_options
.x_param_values
,
3834 global_options_set
.x_param_values
);
3836 /* If using typedef char *va_list, signal that
3837 __builtin_va_start (&ap, 0) can be optimized to
3838 ap = __builtin_next_arg (0). */
3839 if (DEFAULT_ABI
!= ABI_V4
)
3840 targetm
.expand_builtin_va_start
= NULL
;
3843 /* Set up single/double float flags.
3844 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3845 then set both flags. */
3846 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3847 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3848 rs6000_single_float
= rs6000_double_float
= 1;
3850 /* If not explicitly specified via option, decide whether to generate indexed
3851 load/store instructions. */
3852 if (TARGET_AVOID_XFORM
== -1)
3853 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3854 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3855 need indexed accesses and the type used is the scalar type of the element
3856 being loaded or stored. */
3857 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3858 && !TARGET_ALTIVEC
);
3860 /* Set the -mrecip options. */
3861 if (rs6000_recip_name
)
3863 char *p
= ASTRDUP (rs6000_recip_name
);
3865 unsigned int mask
, i
;
3868 while ((q
= strtok (p
, ",")) != NULL
)
3879 if (!strcmp (q
, "default"))
3880 mask
= ((TARGET_RECIP_PRECISION
)
3881 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3884 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3885 if (!strcmp (q
, recip_options
[i
].string
))
3887 mask
= recip_options
[i
].mask
;
3891 if (i
== ARRAY_SIZE (recip_options
))
3893 error ("unknown option for -mrecip=%s", q
);
3901 rs6000_recip_control
&= ~mask
;
3903 rs6000_recip_control
|= mask
;
3907 /* Set the builtin mask of the various options used that could affect which
3908 builtins were used. In the past we used target_flags, but we've run out
3909 of bits, and some options like SPE and PAIRED are no longer in
3911 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3912 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3915 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3916 rs6000_builtin_mask
);
3917 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3920 /* Initialize all of the registers. */
3921 rs6000_init_hard_regno_mode_ok (global_init_p
);
3923 /* Save the initial options in case the user does function specific options */
3925 target_option_default_node
= target_option_current_node
3926 = build_target_option_node (&global_options
);
3928 /* If not explicitly specified via option, decide whether to generate the
3929 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3930 if (TARGET_LINK_STACK
== -1)
3931 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3936 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3937 define the target cpu type. */
3940 rs6000_option_override (void)
3942 (void) rs6000_option_override_internal (true);
3946 /* Implement targetm.vectorize.builtin_mask_for_load. */
3948 rs6000_builtin_mask_for_load (void)
3950 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3951 return altivec_builtin_mask_for_load
;
3956 /* Implement LOOP_ALIGN. */
3958 rs6000_loop_align (rtx label
)
3963 /* Don't override loop alignment if -falign-loops was specified. */
3964 if (!can_override_loop_align
)
3965 return align_loops_log
;
3967 bb
= BLOCK_FOR_INSN (label
);
3968 ninsns
= num_loop_insns(bb
->loop_father
);
3970 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3971 if (ninsns
> 4 && ninsns
<= 8
3972 && (rs6000_cpu
== PROCESSOR_POWER4
3973 || rs6000_cpu
== PROCESSOR_POWER5
3974 || rs6000_cpu
== PROCESSOR_POWER6
3975 || rs6000_cpu
== PROCESSOR_POWER7
3976 || rs6000_cpu
== PROCESSOR_POWER8
))
3979 return align_loops_log
;
3982 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3984 rs6000_loop_align_max_skip (rtx label
)
3986 return (1 << rs6000_loop_align (label
)) - 1;
3989 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3990 after applying N number of iterations. This routine does not determine
3991 how may iterations are required to reach desired alignment. */
3994 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4001 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4004 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4014 /* Assuming that all other types are naturally aligned. CHECKME! */
4019 /* Return true if the vector misalignment factor is supported by the
4022 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4029 /* Return if movmisalign pattern is not supported for this mode. */
4030 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4033 if (misalignment
== -1)
4035 /* Misalignment factor is unknown at compile time but we know
4036 it's word aligned. */
4037 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4039 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4041 if (element_size
== 64 || element_size
== 32)
4048 /* VSX supports word-aligned vector. */
4049 if (misalignment
% 4 == 0)
4055 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4057 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4058 tree vectype
, int misalign
)
4063 switch (type_of_cost
)
4073 case cond_branch_not_taken
:
4082 case vec_promote_demote
:
4088 case cond_branch_taken
:
4091 case unaligned_load
:
4092 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4094 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4096 /* Double word aligned. */
4104 /* Double word aligned. */
4108 /* Unknown misalignment. */
4121 /* Misaligned loads are not supported. */
4126 case unaligned_store
:
4127 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4129 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4131 /* Double word aligned. */
4139 /* Double word aligned. */
4143 /* Unknown misalignment. */
4156 /* Misaligned stores are not supported. */
4162 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4163 elem_type
= TREE_TYPE (vectype
);
4164 /* 32-bit vectors loaded into registers are stored as double
4165 precision, so we need n/2 converts in addition to the usual
4166 n/2 merges to construct a vector of short floats from them. */
4167 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4168 && TYPE_PRECISION (elem_type
) == 32)
4169 return elements
+ 1;
4171 return elements
/ 2 + 1;
4178 /* Implement targetm.vectorize.preferred_simd_mode. */
4180 static enum machine_mode
4181 rs6000_preferred_simd_mode (enum machine_mode mode
)
4190 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4214 if (TARGET_PAIRED_FLOAT
4220 typedef struct _rs6000_cost_data
4222 struct loop
*loop_info
;
4226 /* Test for likely overcommitment of vector hardware resources. If a
4227 loop iteration is relatively large, and too large a percentage of
4228 instructions in the loop are vectorized, the cost model may not
4229 adequately reflect delays from unavailable vector resources.
4230 Penalize the loop body cost for this case. */
4233 rs6000_density_test (rs6000_cost_data
*data
)
4235 const int DENSITY_PCT_THRESHOLD
= 85;
4236 const int DENSITY_SIZE_THRESHOLD
= 70;
4237 const int DENSITY_PENALTY
= 10;
4238 struct loop
*loop
= data
->loop_info
;
4239 basic_block
*bbs
= get_loop_body (loop
);
4240 int nbbs
= loop
->num_nodes
;
4241 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4244 for (i
= 0; i
< nbbs
; i
++)
4246 basic_block bb
= bbs
[i
];
4247 gimple_stmt_iterator gsi
;
4249 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4251 gimple stmt
= gsi_stmt (gsi
);
4252 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4254 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4255 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4261 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4263 if (density_pct
> DENSITY_PCT_THRESHOLD
4264 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4266 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4267 if (dump_enabled_p ())
4268 dump_printf_loc (MSG_NOTE
, vect_location
,
4269 "density %d%%, cost %d exceeds threshold, penalizing "
4270 "loop body cost by %d%%", density_pct
,
4271 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4275 /* Implement targetm.vectorize.init_cost. */
4278 rs6000_init_cost (struct loop
*loop_info
)
4280 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4281 data
->loop_info
= loop_info
;
4282 data
->cost
[vect_prologue
] = 0;
4283 data
->cost
[vect_body
] = 0;
4284 data
->cost
[vect_epilogue
] = 0;
4288 /* Implement targetm.vectorize.add_stmt_cost. */
4291 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4292 struct _stmt_vec_info
*stmt_info
, int misalign
,
4293 enum vect_cost_model_location where
)
4295 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4296 unsigned retval
= 0;
4298 if (flag_vect_cost_model
)
4300 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4301 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4303 /* Statements in an inner loop relative to the loop being
4304 vectorized are weighted more heavily. The value here is
4305 arbitrary and could potentially be improved with analysis. */
4306 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4307 count
*= 50; /* FIXME. */
4309 retval
= (unsigned) (count
* stmt_cost
);
4310 cost_data
->cost
[where
] += retval
;
4316 /* Implement targetm.vectorize.finish_cost. */
4319 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4320 unsigned *body_cost
, unsigned *epilogue_cost
)
4322 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4324 if (cost_data
->loop_info
)
4325 rs6000_density_test (cost_data
);
4327 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4328 *body_cost
= cost_data
->cost
[vect_body
];
4329 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4332 /* Implement targetm.vectorize.destroy_cost_data. */
4335 rs6000_destroy_cost_data (void *data
)
4340 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4341 library with vectorized intrinsics. */
4344 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4347 const char *suffix
= NULL
;
4348 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4351 enum machine_mode el_mode
, in_mode
;
4354 /* Libmass is suitable for unsafe math only as it does not correctly support
4355 parts of IEEE with the required precision such as denormals. Only support
4356 it if we have VSX to use the simd d2 or f4 functions.
4357 XXX: Add variable length support. */
4358 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4361 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4362 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4363 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4364 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4365 if (el_mode
!= in_mode
4369 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4371 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4374 case BUILT_IN_ATAN2
:
4375 case BUILT_IN_HYPOT
:
4381 case BUILT_IN_ACOSH
:
4383 case BUILT_IN_ASINH
:
4385 case BUILT_IN_ATANH
:
4393 case BUILT_IN_EXPM1
:
4394 case BUILT_IN_LGAMMA
:
4395 case BUILT_IN_LOG10
:
4396 case BUILT_IN_LOG1P
:
4404 bdecl
= builtin_decl_implicit (fn
);
4405 suffix
= "d2"; /* pow -> powd2 */
4406 if (el_mode
!= DFmode
4412 case BUILT_IN_ATAN2F
:
4413 case BUILT_IN_HYPOTF
:
4418 case BUILT_IN_ACOSF
:
4419 case BUILT_IN_ACOSHF
:
4420 case BUILT_IN_ASINF
:
4421 case BUILT_IN_ASINHF
:
4422 case BUILT_IN_ATANF
:
4423 case BUILT_IN_ATANHF
:
4424 case BUILT_IN_CBRTF
:
4426 case BUILT_IN_COSHF
:
4428 case BUILT_IN_ERFCF
:
4429 case BUILT_IN_EXP2F
:
4431 case BUILT_IN_EXPM1F
:
4432 case BUILT_IN_LGAMMAF
:
4433 case BUILT_IN_LOG10F
:
4434 case BUILT_IN_LOG1PF
:
4435 case BUILT_IN_LOG2F
:
4438 case BUILT_IN_SINHF
:
4439 case BUILT_IN_SQRTF
:
4441 case BUILT_IN_TANHF
:
4442 bdecl
= builtin_decl_implicit (fn
);
4443 suffix
= "4"; /* powf -> powf4 */
4444 if (el_mode
!= SFmode
4457 gcc_assert (suffix
!= NULL
);
4458 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4462 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4463 strcat (name
, suffix
);
4466 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4467 else if (n_args
== 2)
4468 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4472 /* Build a function declaration for the vectorized function. */
4473 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4474 FUNCTION_DECL
, get_identifier (name
), fntype
);
4475 TREE_PUBLIC (new_fndecl
) = 1;
4476 DECL_EXTERNAL (new_fndecl
) = 1;
4477 DECL_IS_NOVOPS (new_fndecl
) = 1;
4478 TREE_READONLY (new_fndecl
) = 1;
4483 /* Returns a function decl for a vectorized version of the builtin function
4484 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4485 if it is not available. */
4488 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4491 enum machine_mode in_mode
, out_mode
;
4494 if (TARGET_DEBUG_BUILTIN
)
4495 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4496 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4497 GET_MODE_NAME (TYPE_MODE (type_out
)),
4498 GET_MODE_NAME (TYPE_MODE (type_in
)));
4500 if (TREE_CODE (type_out
) != VECTOR_TYPE
4501 || TREE_CODE (type_in
) != VECTOR_TYPE
4502 || !TARGET_VECTORIZE_BUILTINS
)
4505 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4506 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4507 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4508 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4510 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4512 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4515 case BUILT_IN_CLZIMAX
:
4516 case BUILT_IN_CLZLL
:
4519 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4521 if (out_mode
== QImode
&& out_n
== 16)
4522 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4523 else if (out_mode
== HImode
&& out_n
== 8)
4524 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4525 else if (out_mode
== SImode
&& out_n
== 4)
4526 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4527 else if (out_mode
== DImode
&& out_n
== 2)
4528 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4531 case BUILT_IN_COPYSIGN
:
4532 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4533 && out_mode
== DFmode
&& out_n
== 2
4534 && in_mode
== DFmode
&& in_n
== 2)
4535 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4537 case BUILT_IN_COPYSIGNF
:
4538 if (out_mode
!= SFmode
|| out_n
!= 4
4539 || in_mode
!= SFmode
|| in_n
!= 4)
4541 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4542 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4543 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4544 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4546 case BUILT_IN_POPCOUNTIMAX
:
4547 case BUILT_IN_POPCOUNTLL
:
4548 case BUILT_IN_POPCOUNTL
:
4549 case BUILT_IN_POPCOUNT
:
4550 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4552 if (out_mode
== QImode
&& out_n
== 16)
4553 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4554 else if (out_mode
== HImode
&& out_n
== 8)
4555 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4556 else if (out_mode
== SImode
&& out_n
== 4)
4557 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4558 else if (out_mode
== DImode
&& out_n
== 2)
4559 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4563 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4564 && out_mode
== DFmode
&& out_n
== 2
4565 && in_mode
== DFmode
&& in_n
== 2)
4566 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4568 case BUILT_IN_SQRTF
:
4569 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4570 && out_mode
== SFmode
&& out_n
== 4
4571 && in_mode
== SFmode
&& in_n
== 4)
4572 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4575 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4576 && out_mode
== DFmode
&& out_n
== 2
4577 && in_mode
== DFmode
&& in_n
== 2)
4578 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4580 case BUILT_IN_CEILF
:
4581 if (out_mode
!= SFmode
|| out_n
!= 4
4582 || in_mode
!= SFmode
|| in_n
!= 4)
4584 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4585 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4586 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4587 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4589 case BUILT_IN_FLOOR
:
4590 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4591 && out_mode
== DFmode
&& out_n
== 2
4592 && in_mode
== DFmode
&& in_n
== 2)
4593 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4595 case BUILT_IN_FLOORF
:
4596 if (out_mode
!= SFmode
|| out_n
!= 4
4597 || in_mode
!= SFmode
|| in_n
!= 4)
4599 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4600 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4601 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4602 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4605 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4606 && out_mode
== DFmode
&& out_n
== 2
4607 && in_mode
== DFmode
&& in_n
== 2)
4608 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4611 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4612 && out_mode
== SFmode
&& out_n
== 4
4613 && in_mode
== SFmode
&& in_n
== 4)
4614 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4615 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4616 && out_mode
== SFmode
&& out_n
== 4
4617 && in_mode
== SFmode
&& in_n
== 4)
4618 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4620 case BUILT_IN_TRUNC
:
4621 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4622 && out_mode
== DFmode
&& out_n
== 2
4623 && in_mode
== DFmode
&& in_n
== 2)
4624 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4626 case BUILT_IN_TRUNCF
:
4627 if (out_mode
!= SFmode
|| out_n
!= 4
4628 || in_mode
!= SFmode
|| in_n
!= 4)
4630 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4631 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4632 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4633 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4635 case BUILT_IN_NEARBYINT
:
4636 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4637 && flag_unsafe_math_optimizations
4638 && out_mode
== DFmode
&& out_n
== 2
4639 && in_mode
== DFmode
&& in_n
== 2)
4640 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4642 case BUILT_IN_NEARBYINTF
:
4643 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4644 && flag_unsafe_math_optimizations
4645 && out_mode
== SFmode
&& out_n
== 4
4646 && in_mode
== SFmode
&& in_n
== 4)
4647 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4650 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4651 && !flag_trapping_math
4652 && out_mode
== DFmode
&& out_n
== 2
4653 && in_mode
== DFmode
&& in_n
== 2)
4654 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4656 case BUILT_IN_RINTF
:
4657 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4658 && !flag_trapping_math
4659 && out_mode
== SFmode
&& out_n
== 4
4660 && in_mode
== SFmode
&& in_n
== 4)
4661 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4668 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4670 enum rs6000_builtins fn
4671 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4674 case RS6000_BUILTIN_RSQRTF
:
4675 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4676 && out_mode
== SFmode
&& out_n
== 4
4677 && in_mode
== SFmode
&& in_n
== 4)
4678 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4680 case RS6000_BUILTIN_RSQRT
:
4681 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4682 && out_mode
== DFmode
&& out_n
== 2
4683 && in_mode
== DFmode
&& in_n
== 2)
4684 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4686 case RS6000_BUILTIN_RECIPF
:
4687 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4688 && out_mode
== SFmode
&& out_n
== 4
4689 && in_mode
== SFmode
&& in_n
== 4)
4690 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4692 case RS6000_BUILTIN_RECIP
:
4693 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4694 && out_mode
== DFmode
&& out_n
== 2
4695 && in_mode
== DFmode
&& in_n
== 2)
4696 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4703 /* Generate calls to libmass if appropriate. */
4704 if (rs6000_veclib_handler
)
4705 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4710 /* Default CPU string for rs6000*_file_start functions. */
4711 static const char *rs6000_default_cpu
;
4713 /* Do anything needed at the start of the asm file. */
4716 rs6000_file_start (void)
4719 const char *start
= buffer
;
4720 FILE *file
= asm_out_file
;
4722 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4724 default_file_start ();
4726 if (flag_verbose_asm
)
4728 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4730 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4732 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4736 if (global_options_set
.x_rs6000_cpu_index
)
4738 fprintf (file
, "%s -mcpu=%s", start
,
4739 processor_target_table
[rs6000_cpu_index
].name
);
4743 if (global_options_set
.x_rs6000_tune_index
)
4745 fprintf (file
, "%s -mtune=%s", start
,
4746 processor_target_table
[rs6000_tune_index
].name
);
4750 if (PPC405_ERRATUM77
)
4752 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4756 #ifdef USING_ELFOS_H
4757 switch (rs6000_sdata
)
4759 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4760 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4761 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4762 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4765 if (rs6000_sdata
&& g_switch_value
)
4767 fprintf (file
, "%s -G %d", start
,
4777 if (DEFAULT_ABI
== ABI_ELFv2
)
4778 fprintf (file
, "\t.abiversion 2\n");
4780 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
4781 || (TARGET_ELF
&& flag_pic
== 2))
4783 switch_to_section (toc_section
);
4784 switch_to_section (text_section
);
4789 /* Return nonzero if this function is known to have a null epilogue. */
4792 direct_return (void)
4794 if (reload_completed
)
4796 rs6000_stack_t
*info
= rs6000_stack_info ();
4798 if (info
->first_gp_reg_save
== 32
4799 && info
->first_fp_reg_save
== 64
4800 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4801 && ! info
->lr_save_p
4802 && ! info
->cr_save_p
4803 && info
->vrsave_mask
== 0
4811 /* Return the number of instructions it takes to form a constant in an
4812 integer register. */
4815 num_insns_constant_wide (HOST_WIDE_INT value
)
4817 /* signed constant loadable with addi */
4818 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4821 /* constant loadable with addis */
4822 else if ((value
& 0xffff) == 0
4823 && (value
>> 31 == -1 || value
>> 31 == 0))
4826 else if (TARGET_POWERPC64
)
4828 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4829 HOST_WIDE_INT high
= value
>> 31;
4831 if (high
== 0 || high
== -1)
4837 return num_insns_constant_wide (high
) + 1;
4839 return num_insns_constant_wide (low
) + 1;
4841 return (num_insns_constant_wide (high
)
4842 + num_insns_constant_wide (low
) + 1);
4850 num_insns_constant (rtx op
, enum machine_mode mode
)
4852 HOST_WIDE_INT low
, high
;
4854 switch (GET_CODE (op
))
4857 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4858 && mask64_operand (op
, mode
))
4861 return num_insns_constant_wide (INTVAL (op
));
4864 if (mode
== SFmode
|| mode
== SDmode
)
4869 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4870 if (DECIMAL_FLOAT_MODE_P (mode
))
4871 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4873 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4874 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4880 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4881 if (DECIMAL_FLOAT_MODE_P (mode
))
4882 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4884 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4885 high
= l
[WORDS_BIG_ENDIAN
== 0];
4886 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4889 return (num_insns_constant_wide (low
)
4890 + num_insns_constant_wide (high
));
4893 if ((high
== 0 && low
>= 0)
4894 || (high
== -1 && low
< 0))
4895 return num_insns_constant_wide (low
);
4897 else if (mask64_operand (op
, mode
))
4901 return num_insns_constant_wide (high
) + 1;
4904 return (num_insns_constant_wide (high
)
4905 + num_insns_constant_wide (low
) + 1);
4913 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4914 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4915 corresponding element of the vector, but for V4SFmode and V2SFmode,
4916 the corresponding "float" is interpreted as an SImode integer. */
4919 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4923 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4924 gcc_assert (GET_MODE (op
) != V2DImode
4925 && GET_MODE (op
) != V2DFmode
);
4927 tmp
= CONST_VECTOR_ELT (op
, elt
);
4928 if (GET_MODE (op
) == V4SFmode
4929 || GET_MODE (op
) == V2SFmode
)
4930 tmp
= gen_lowpart (SImode
, tmp
);
4931 return INTVAL (tmp
);
4934 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4935 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4936 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4937 all items are set to the same value and contain COPIES replicas of the
4938 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4939 operand and the others are set to the value of the operand's msb. */
4942 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4944 enum machine_mode mode
= GET_MODE (op
);
4945 enum machine_mode inner
= GET_MODE_INNER (mode
);
4953 HOST_WIDE_INT splat_val
;
4954 HOST_WIDE_INT msb_val
;
4956 if (mode
== V2DImode
|| mode
== V2DFmode
)
4959 nunits
= GET_MODE_NUNITS (mode
);
4960 bitsize
= GET_MODE_BITSIZE (inner
);
4961 mask
= GET_MODE_MASK (inner
);
4963 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
4965 msb_val
= val
> 0 ? 0 : -1;
4967 /* Construct the value to be splatted, if possible. If not, return 0. */
4968 for (i
= 2; i
<= copies
; i
*= 2)
4970 HOST_WIDE_INT small_val
;
4972 small_val
= splat_val
>> bitsize
;
4974 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4976 splat_val
= small_val
;
4979 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4980 if (EASY_VECTOR_15 (splat_val
))
4983 /* Also check if we can splat, and then add the result to itself. Do so if
4984 the value is positive, of if the splat instruction is using OP's mode;
4985 for splat_val < 0, the splat and the add should use the same mode. */
4986 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
4987 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
4990 /* Also check if are loading up the most significant bit which can be done by
4991 loading up -1 and shifting the value left by -1. */
4992 else if (EASY_VECTOR_MSB (splat_val
, inner
))
4998 /* Check if VAL is present in every STEP-th element, and the
4999 other elements are filled with its most significant bit. */
5000 for (i
= 1; i
< nunits
; ++i
)
5002 HOST_WIDE_INT desired_val
;
5003 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5004 if ((i
& (step
- 1)) == 0)
5007 desired_val
= msb_val
;
5009 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5017 /* Return true if OP is of the given MODE and can be synthesized
5018 with a vspltisb, vspltish or vspltisw. */
5021 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5023 unsigned step
, copies
;
5025 if (mode
== VOIDmode
)
5026 mode
= GET_MODE (op
);
5027 else if (mode
!= GET_MODE (op
))
5030 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5032 if (mode
== V2DFmode
)
5033 return zero_constant (op
, mode
);
5035 if (mode
== V2DImode
)
5037 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
5039 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5040 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5043 if (zero_constant (op
, mode
))
5046 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5047 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5053 /* Start with a vspltisw. */
5054 step
= GET_MODE_NUNITS (mode
) / 4;
5057 if (vspltis_constant (op
, step
, copies
))
5060 /* Then try with a vspltish. */
5066 if (vspltis_constant (op
, step
, copies
))
5069 /* And finally a vspltisb. */
5075 if (vspltis_constant (op
, step
, copies
))
5081 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5082 result is OP. Abort if it is not possible. */
5085 gen_easy_altivec_constant (rtx op
)
5087 enum machine_mode mode
= GET_MODE (op
);
5088 int nunits
= GET_MODE_NUNITS (mode
);
5089 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5090 unsigned step
= nunits
/ 4;
5091 unsigned copies
= 1;
5093 /* Start with a vspltisw. */
5094 if (vspltis_constant (op
, step
, copies
))
5095 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5097 /* Then try with a vspltish. */
5103 if (vspltis_constant (op
, step
, copies
))
5104 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5106 /* And finally a vspltisb. */
5112 if (vspltis_constant (op
, step
, copies
))
5113 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5119 output_vec_const_move (rtx
*operands
)
5122 enum machine_mode mode
;
5127 mode
= GET_MODE (dest
);
5131 if (zero_constant (vec
, mode
))
5132 return "xxlxor %x0,%x0,%x0";
5134 if (mode
== V2DImode
5135 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5136 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5137 return "vspltisw %0,-1";
5143 if (zero_constant (vec
, mode
))
5144 return "vxor %0,%0,%0";
5146 splat_vec
= gen_easy_altivec_constant (vec
);
5147 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5148 operands
[1] = XEXP (splat_vec
, 0);
5149 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5152 switch (GET_MODE (splat_vec
))
5155 return "vspltisw %0,%1";
5158 return "vspltish %0,%1";
5161 return "vspltisb %0,%1";
5168 gcc_assert (TARGET_SPE
);
5170 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5171 pattern of V1DI, V4HI, and V2SF.
5173 FIXME: We should probably return # and add post reload
5174 splitters for these, but this way is so easy ;-). */
5175 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5176 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5177 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5178 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5180 return "li %0,%1\n\tevmergelo %0,%0,%0";
5182 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5185 /* Initialize TARGET of vector PAIRED to VALS. */
5188 paired_expand_vector_init (rtx target
, rtx vals
)
5190 enum machine_mode mode
= GET_MODE (target
);
5191 int n_elts
= GET_MODE_NUNITS (mode
);
5193 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5196 for (i
= 0; i
< n_elts
; ++i
)
5198 x
= XVECEXP (vals
, 0, i
);
5199 if (!(CONST_INT_P (x
)
5200 || GET_CODE (x
) == CONST_DOUBLE
5201 || GET_CODE (x
) == CONST_FIXED
))
5206 /* Load from constant pool. */
5207 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5213 /* The vector is initialized only with non-constants. */
5214 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5215 XVECEXP (vals
, 0, 1));
5217 emit_move_insn (target
, new_rtx
);
5221 /* One field is non-constant and the other one is a constant. Load the
5222 constant from the constant pool and use ps_merge instruction to
5223 construct the whole vector. */
5224 op1
= XVECEXP (vals
, 0, 0);
5225 op2
= XVECEXP (vals
, 0, 1);
5227 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5229 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5230 emit_move_insn (tmp
, constant_op
);
5232 if (CONSTANT_P (op1
))
5233 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5235 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5237 emit_move_insn (target
, new_rtx
);
5241 paired_expand_vector_move (rtx operands
[])
5243 rtx op0
= operands
[0], op1
= operands
[1];
5245 emit_move_insn (op0
, op1
);
5248 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5249 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5250 operands for the relation operation COND. This is a recursive
5254 paired_emit_vector_compare (enum rtx_code rcode
,
5255 rtx dest
, rtx op0
, rtx op1
,
5256 rtx cc_op0
, rtx cc_op1
)
5258 rtx tmp
= gen_reg_rtx (V2SFmode
);
5261 gcc_assert (TARGET_PAIRED_FLOAT
);
5262 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5268 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5272 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5273 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5277 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5280 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5283 tmp1
= gen_reg_rtx (V2SFmode
);
5284 max
= gen_reg_rtx (V2SFmode
);
5285 min
= gen_reg_rtx (V2SFmode
);
5286 gen_reg_rtx (V2SFmode
);
5288 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5289 emit_insn (gen_selv2sf4
5290 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5291 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5292 emit_insn (gen_selv2sf4
5293 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5294 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5295 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5298 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5301 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5304 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5307 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5310 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5319 /* Emit vector conditional expression.
5320 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5321 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5324 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5325 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5327 enum rtx_code rcode
= GET_CODE (cond
);
5329 if (!TARGET_PAIRED_FLOAT
)
5332 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5337 /* Initialize vector TARGET to VALS. */
5340 rs6000_expand_vector_init (rtx target
, rtx vals
)
5342 enum machine_mode mode
= GET_MODE (target
);
5343 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5344 int n_elts
= GET_MODE_NUNITS (mode
);
5345 int n_var
= 0, one_var
= -1;
5346 bool all_same
= true, all_const_zero
= true;
5350 for (i
= 0; i
< n_elts
; ++i
)
5352 x
= XVECEXP (vals
, 0, i
);
5353 if (!(CONST_INT_P (x
)
5354 || GET_CODE (x
) == CONST_DOUBLE
5355 || GET_CODE (x
) == CONST_FIXED
))
5356 ++n_var
, one_var
= i
;
5357 else if (x
!= CONST0_RTX (inner_mode
))
5358 all_const_zero
= false;
5360 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5366 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5367 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5368 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5370 /* Zero register. */
5371 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5372 gen_rtx_XOR (mode
, target
, target
)));
5375 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5377 /* Splat immediate. */
5378 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5383 /* Load from constant pool. */
5384 emit_move_insn (target
, const_vec
);
5389 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5390 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5392 rtx op0
= XVECEXP (vals
, 0, 0);
5393 rtx op1
= XVECEXP (vals
, 0, 1);
5396 if (!MEM_P (op0
) && !REG_P (op0
))
5397 op0
= force_reg (inner_mode
, op0
);
5398 if (mode
== V2DFmode
)
5399 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5401 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5405 op0
= force_reg (inner_mode
, op0
);
5406 op1
= force_reg (inner_mode
, op1
);
5407 if (mode
== V2DFmode
)
5408 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5410 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5415 /* With single precision floating point on VSX, know that internally single
5416 precision is actually represented as a double, and either make 2 V2DF
5417 vectors, and convert these vectors to single precision, or do one
5418 conversion, and splat the result to the other elements. */
5419 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5423 rtx freg
= gen_reg_rtx (V4SFmode
);
5424 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5425 rtx cvt
= ((TARGET_XSCVDPSPN
)
5426 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5427 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5430 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
5434 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5435 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5436 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5437 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5438 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5439 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5440 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5441 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5443 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5444 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5445 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5446 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5447 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5452 /* Store value to stack temp. Load vector element. Splat. However, splat
5453 of 64-bit items is not supported on Altivec. */
5454 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5457 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5458 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5459 XVECEXP (vals
, 0, 0));
5460 x
= gen_rtx_UNSPEC (VOIDmode
,
5461 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5462 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5464 gen_rtx_SET (VOIDmode
,
5467 field
= (BYTES_BIG_ENDIAN
? const0_rtx
5468 : GEN_INT (GET_MODE_NUNITS (mode
) - 1));
5469 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5470 gen_rtx_PARALLEL (VOIDmode
,
5471 gen_rtvec (1, field
)));
5472 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5473 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5477 /* One field is non-constant. Load constant then overwrite
5481 rtx copy
= copy_rtx (vals
);
5483 /* Load constant part of vector, substitute neighboring value for
5485 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5486 rs6000_expand_vector_init (target
, copy
);
5488 /* Insert variable. */
5489 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5493 /* Construct the vector in memory one field at a time
5494 and load the whole vector. */
5495 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5496 for (i
= 0; i
< n_elts
; i
++)
5497 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5498 i
* GET_MODE_SIZE (inner_mode
)),
5499 XVECEXP (vals
, 0, i
));
5500 emit_move_insn (target
, mem
);
5503 /* Set field ELT of TARGET to VAL. */
5506 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5508 enum machine_mode mode
= GET_MODE (target
);
5509 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5510 rtx reg
= gen_reg_rtx (mode
);
5512 int width
= GET_MODE_SIZE (inner_mode
);
5515 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5517 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5518 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5519 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5523 /* Load single variable value. */
5524 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5525 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5526 x
= gen_rtx_UNSPEC (VOIDmode
,
5527 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5528 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5530 gen_rtx_SET (VOIDmode
,
5534 /* Linear sequence. */
5535 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5536 for (i
= 0; i
< 16; ++i
)
5537 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5539 /* Set permute mask to insert element into target. */
5540 for (i
= 0; i
< width
; ++i
)
5541 XVECEXP (mask
, 0, elt
*width
+ i
)
5542 = GEN_INT (i
+ 0x10);
5543 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5545 if (BYTES_BIG_ENDIAN
)
5546 x
= gen_rtx_UNSPEC (mode
,
5547 gen_rtvec (3, target
, reg
,
5548 force_reg (V16QImode
, x
)),
5552 /* Invert selector. */
5553 rtx splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
5554 gen_rtx_CONST_INT (QImode
, -1));
5555 rtx tmp
= gen_reg_rtx (V16QImode
);
5556 emit_move_insn (tmp
, splat
);
5557 x
= gen_rtx_MINUS (V16QImode
, tmp
, force_reg (V16QImode
, x
));
5558 emit_move_insn (tmp
, x
);
5560 /* Permute with operands reversed and adjusted selector. */
5561 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5565 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5568 /* Extract field ELT from VEC into TARGET. */
5571 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5573 enum machine_mode mode
= GET_MODE (vec
);
5574 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5577 if (VECTOR_MEM_VSX_P (mode
))
5584 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5587 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5590 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5595 /* Allocate mode-sized buffer. */
5596 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5598 emit_move_insn (mem
, vec
);
5600 /* Add offset to field within buffer matching vector element. */
5601 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5603 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5606 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5607 implement ANDing by the mask IN. */
5609 build_mask64_2_operands (rtx in
, rtx
*out
)
5611 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5614 gcc_assert (GET_CODE (in
) == CONST_INT
);
5619 /* Assume c initially something like 0x00fff000000fffff. The idea
5620 is to rotate the word so that the middle ^^^^^^ group of zeros
5621 is at the MS end and can be cleared with an rldicl mask. We then
5622 rotate back and clear off the MS ^^ group of zeros with a
5624 c
= ~c
; /* c == 0xff000ffffff00000 */
5625 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5626 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5627 c
= ~c
; /* c == 0x00fff000000fffff */
5628 c
&= -lsb
; /* c == 0x00fff00000000000 */
5629 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5630 c
= ~c
; /* c == 0xff000fffffffffff */
5631 c
&= -lsb
; /* c == 0xff00000000000000 */
5633 while ((lsb
>>= 1) != 0)
5634 shift
++; /* shift == 44 on exit from loop */
5635 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5636 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5637 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5641 /* Assume c initially something like 0xff000f0000000000. The idea
5642 is to rotate the word so that the ^^^ middle group of zeros
5643 is at the LS end and can be cleared with an rldicr mask. We then
5644 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5646 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5647 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5648 c
= ~c
; /* c == 0x00fff0ffffffffff */
5649 c
&= -lsb
; /* c == 0x00fff00000000000 */
5650 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5651 c
= ~c
; /* c == 0xff000fffffffffff */
5652 c
&= -lsb
; /* c == 0xff00000000000000 */
5654 while ((lsb
>>= 1) != 0)
5655 shift
++; /* shift == 44 on exit from loop */
5656 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5657 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5658 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5661 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5662 masks will be all 1's. We are guaranteed more than one transition. */
5663 out
[0] = GEN_INT (64 - shift
);
5664 out
[1] = GEN_INT (m1
);
5665 out
[2] = GEN_INT (shift
);
5666 out
[3] = GEN_INT (m2
);
5669 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5672 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5674 if (TARGET_E500_DOUBLE
)
5676 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5677 subreg:TI and reg:TF. Decimal float modes are like integer
5678 modes (only low part of each register used) for this
5680 if (GET_CODE (op
) == SUBREG
5681 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5682 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5683 && REG_P (SUBREG_REG (op
))
5684 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5685 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5688 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5690 if (GET_CODE (op
) == SUBREG
5691 && (mode
== DFmode
|| mode
== TFmode
)
5692 && REG_P (SUBREG_REG (op
))
5693 && (GET_MODE (SUBREG_REG (op
)) == DImode
5694 || GET_MODE (SUBREG_REG (op
)) == TImode
5695 || GET_MODE (SUBREG_REG (op
)) == PTImode
5696 || GET_MODE (SUBREG_REG (op
)) == DDmode
5697 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5702 && GET_CODE (op
) == SUBREG
5704 && REG_P (SUBREG_REG (op
))
5705 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5711 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5712 selects whether the alignment is abi mandated, optional, or
5713 both abi and optional alignment. */
5716 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5718 if (how
!= align_opt
)
5720 if (TREE_CODE (type
) == VECTOR_TYPE
)
5722 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5723 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5728 else if (align
< 128)
5731 else if (TARGET_E500_DOUBLE
5732 && TREE_CODE (type
) == REAL_TYPE
5733 && TYPE_MODE (type
) == DFmode
)
5740 if (how
!= align_abi
)
5742 if (TREE_CODE (type
) == ARRAY_TYPE
5743 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5745 if (align
< BITS_PER_WORD
)
5746 align
= BITS_PER_WORD
;
5753 /* AIX increases natural record alignment to doubleword if the first
5754 field is an FP double while the FP fields remain word aligned. */
5757 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5758 unsigned int specified
)
5760 unsigned int align
= MAX (computed
, specified
);
5761 tree field
= TYPE_FIELDS (type
);
5763 /* Skip all non field decls */
5764 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5765 field
= DECL_CHAIN (field
);
5767 if (field
!= NULL
&& field
!= type
)
5769 type
= TREE_TYPE (field
);
5770 while (TREE_CODE (type
) == ARRAY_TYPE
)
5771 type
= TREE_TYPE (type
);
5773 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5774 align
= MAX (align
, 64);
5780 /* Darwin increases record alignment to the natural alignment of
5784 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5785 unsigned int specified
)
5787 unsigned int align
= MAX (computed
, specified
);
5789 if (TYPE_PACKED (type
))
5792 /* Find the first field, looking down into aggregates. */
5794 tree field
= TYPE_FIELDS (type
);
5795 /* Skip all non field decls */
5796 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5797 field
= DECL_CHAIN (field
);
5800 /* A packed field does not contribute any extra alignment. */
5801 if (DECL_PACKED (field
))
5803 type
= TREE_TYPE (field
);
5804 while (TREE_CODE (type
) == ARRAY_TYPE
)
5805 type
= TREE_TYPE (type
);
5806 } while (AGGREGATE_TYPE_P (type
));
5808 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5809 align
= MAX (align
, TYPE_ALIGN (type
));
5814 /* Return 1 for an operand in small memory on V.4/eabi. */
5817 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5818 enum machine_mode mode ATTRIBUTE_UNUSED
)
5823 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5826 if (DEFAULT_ABI
!= ABI_V4
)
5829 /* Vector and float memory instructions have a limited offset on the
5830 SPE, so using a vector or float variable directly as an operand is
5833 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5836 if (GET_CODE (op
) == SYMBOL_REF
)
5839 else if (GET_CODE (op
) != CONST
5840 || GET_CODE (XEXP (op
, 0)) != PLUS
5841 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5842 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5847 rtx sum
= XEXP (op
, 0);
5848 HOST_WIDE_INT summand
;
5850 /* We have to be careful here, because it is the referenced address
5851 that must be 32k from _SDA_BASE_, not just the symbol. */
5852 summand
= INTVAL (XEXP (sum
, 1));
5853 if (summand
< 0 || summand
> g_switch_value
)
5856 sym_ref
= XEXP (sum
, 0);
5859 return SYMBOL_REF_SMALL_P (sym_ref
);
5865 /* Return true if either operand is a general purpose register. */
5868 gpr_or_gpr_p (rtx op0
, rtx op1
)
5870 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5871 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5874 /* Return true if this is a move direct operation between GPR registers and
5875 floating point/VSX registers. */
5878 direct_move_p (rtx op0
, rtx op1
)
5882 if (!REG_P (op0
) || !REG_P (op1
))
5885 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
5888 regno0
= REGNO (op0
);
5889 regno1
= REGNO (op1
);
5890 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
5893 if (INT_REGNO_P (regno0
))
5894 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
5896 else if (INT_REGNO_P (regno1
))
5898 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
5901 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
5908 /* Return true if this is a load or store quad operation. */
5911 quad_load_store_p (rtx op0
, rtx op1
)
5915 if (!TARGET_QUAD_MEMORY
)
5918 else if (REG_P (op0
) && MEM_P (op1
))
5919 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
5920 && quad_memory_operand (op1
, GET_MODE (op1
))
5921 && !reg_overlap_mentioned_p (op0
, op1
));
5923 else if (MEM_P (op0
) && REG_P (op1
))
5924 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
5925 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
5930 if (TARGET_DEBUG_ADDR
)
5932 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
5933 ret
? "true" : "false");
5934 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
5940 /* Given an address, return a constant offset term if one exists. */
5943 address_offset (rtx op
)
5945 if (GET_CODE (op
) == PRE_INC
5946 || GET_CODE (op
) == PRE_DEC
)
5948 else if (GET_CODE (op
) == PRE_MODIFY
5949 || GET_CODE (op
) == LO_SUM
)
5952 if (GET_CODE (op
) == CONST
)
5955 if (GET_CODE (op
) == PLUS
)
5958 if (CONST_INT_P (op
))
5964 /* Return true if the MEM operand is a memory operand suitable for use
5965 with a (full width, possibly multiple) gpr load/store. On
5966 powerpc64 this means the offset must be divisible by 4.
5967 Implements 'Y' constraint.
5969 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5970 a constraint function we know the operand has satisfied a suitable
5971 memory predicate. Also accept some odd rtl generated by reload
5972 (see rs6000_legitimize_reload_address for various forms). It is
5973 important that reload rtl be accepted by appropriate constraints
5974 but not by the operand predicate.
5976 Offsetting a lo_sum should not be allowed, except where we know by
5977 alignment that a 32k boundary is not crossed, but see the ???
5978 comment in rs6000_legitimize_reload_address. Note that by
5979 "offsetting" here we mean a further offset to access parts of the
5980 MEM. It's fine to have a lo_sum where the inner address is offset
5981 from a sym, since the same sym+offset will appear in the high part
5982 of the address calculation. */
5985 mem_operand_gpr (rtx op
, enum machine_mode mode
)
5987 unsigned HOST_WIDE_INT offset
;
5989 rtx addr
= XEXP (op
, 0);
5991 op
= address_offset (addr
);
5995 offset
= INTVAL (op
);
5996 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
5999 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6000 gcc_assert (extra
>= 0);
6002 if (GET_CODE (addr
) == LO_SUM
)
6003 /* For lo_sum addresses, we must allow any offset except one that
6004 causes a wrap, so test only the low 16 bits. */
6005 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6007 return offset
+ 0x8000 < 0x10000u
- extra
;
6010 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6013 reg_offset_addressing_ok_p (enum machine_mode mode
)
6024 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6025 TImode is not a vector mode, if we want to use the VSX registers to
6026 move it around, we need to restrict ourselves to reg+reg
6028 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6036 /* Paired vector modes. Only reg+reg addressing is valid. */
6037 if (TARGET_PAIRED_FLOAT
)
6042 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6043 addressing for the LFIWZX and STFIWX instructions. */
6044 if (TARGET_NO_SDMODE_STACK
)
6056 virtual_stack_registers_memory_p (rtx op
)
6060 if (GET_CODE (op
) == REG
)
6061 regnum
= REGNO (op
);
6063 else if (GET_CODE (op
) == PLUS
6064 && GET_CODE (XEXP (op
, 0)) == REG
6065 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6066 regnum
= REGNO (XEXP (op
, 0));
6071 return (regnum
>= FIRST_VIRTUAL_REGISTER
6072 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6075 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6076 is known to not straddle a 32k boundary. */
6079 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6080 enum machine_mode mode
)
6083 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6085 if (GET_CODE (op
) != SYMBOL_REF
)
6088 dsize
= GET_MODE_SIZE (mode
);
6089 decl
= SYMBOL_REF_DECL (op
);
6095 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6096 replacing memory addresses with an anchor plus offset. We
6097 could find the decl by rummaging around in the block->objects
6098 VEC for the given offset but that seems like too much work. */
6099 dalign
= BITS_PER_UNIT
;
6100 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6101 && SYMBOL_REF_ANCHOR_P (op
)
6102 && SYMBOL_REF_BLOCK (op
) != NULL
)
6104 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6106 dalign
= block
->alignment
;
6107 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6109 else if (CONSTANT_POOL_ADDRESS_P (op
))
6111 /* It would be nice to have get_pool_align().. */
6112 enum machine_mode cmode
= get_pool_mode (op
);
6114 dalign
= GET_MODE_ALIGNMENT (cmode
);
6117 else if (DECL_P (decl
))
6119 dalign
= DECL_ALIGN (decl
);
6123 /* Allow BLKmode when the entire object is known to not
6124 cross a 32k boundary. */
6125 if (!DECL_SIZE_UNIT (decl
))
6128 if (!host_integerp (DECL_SIZE_UNIT (decl
), 1))
6131 dsize
= tree_low_cst (DECL_SIZE_UNIT (decl
), 1);
6135 return dalign
/ BITS_PER_UNIT
>= dsize
;
6140 type
= TREE_TYPE (decl
);
6142 dalign
= TYPE_ALIGN (type
);
6143 if (CONSTANT_CLASS_P (decl
))
6144 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6146 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6150 /* BLKmode, check the entire object. */
6151 if (TREE_CODE (decl
) == STRING_CST
)
6152 dsize
= TREE_STRING_LENGTH (decl
);
6153 else if (TYPE_SIZE_UNIT (type
)
6154 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
6155 dsize
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
6161 return dalign
/ BITS_PER_UNIT
>= dsize
;
6165 /* Find how many bits of the alignment we know for this access. */
6166 mask
= dalign
/ BITS_PER_UNIT
- 1;
6167 lsb
= offset
& -offset
;
6171 return dalign
>= dsize
;
6175 constant_pool_expr_p (rtx op
)
6179 split_const (op
, &base
, &offset
);
6180 return (GET_CODE (base
) == SYMBOL_REF
6181 && CONSTANT_POOL_ADDRESS_P (base
)
6182 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6185 static const_rtx tocrel_base
, tocrel_offset
;
6187 /* Return true if OP is a toc pointer relative address (the output
6188 of create_TOC_reference). If STRICT, do not match high part or
6189 non-split -mcmodel=large/medium toc pointer relative addresses. */
6192 toc_relative_expr_p (const_rtx op
, bool strict
)
6197 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6199 /* Only match the low part. */
6200 if (GET_CODE (op
) == LO_SUM
6201 && REG_P (XEXP (op
, 0))
6202 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6209 tocrel_offset
= const0_rtx
;
6210 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6212 tocrel_base
= XEXP (op
, 0);
6213 tocrel_offset
= XEXP (op
, 1);
6216 return (GET_CODE (tocrel_base
) == UNSPEC
6217 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6220 /* Return true if X is a constant pool address, and also for cmodel=medium
6221 if X is a toc-relative address known to be offsettable within MODE. */
6224 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6227 return (toc_relative_expr_p (x
, strict
)
6228 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6229 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6231 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6232 INTVAL (tocrel_offset
), mode
)));
6236 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6238 return (DEFAULT_ABI
== ABI_V4
6239 && !flag_pic
&& !TARGET_TOC
6240 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6241 && small_data_operand (x
, mode
));
6244 /* SPE offset addressing is limited to 5-bits worth of double words. */
6245 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6248 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6249 bool strict
, bool worst_case
)
6251 unsigned HOST_WIDE_INT offset
;
6254 if (GET_CODE (x
) != PLUS
)
6256 if (!REG_P (XEXP (x
, 0)))
6258 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6260 if (!reg_offset_addressing_ok_p (mode
))
6261 return virtual_stack_registers_memory_p (x
);
6262 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6264 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6267 offset
= INTVAL (XEXP (x
, 1));
6275 /* SPE vector modes. */
6276 return SPE_CONST_OFFSET_OK (offset
);
6281 /* On e500v2, we may have:
6283 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6285 Which gets addressed with evldd instructions. */
6286 if (TARGET_E500_DOUBLE
)
6287 return SPE_CONST_OFFSET_OK (offset
);
6289 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6291 if (VECTOR_MEM_VSX_P (mode
))
6296 if (!TARGET_POWERPC64
)
6298 else if (offset
& 3)
6306 if (TARGET_E500_DOUBLE
)
6307 return (SPE_CONST_OFFSET_OK (offset
)
6308 && SPE_CONST_OFFSET_OK (offset
+ 8));
6313 if (!TARGET_POWERPC64
)
6315 else if (offset
& 3)
6324 return offset
< 0x10000 - extra
;
6328 legitimate_indexed_address_p (rtx x
, int strict
)
6332 if (GET_CODE (x
) != PLUS
)
6338 /* Recognize the rtl generated by reload which we know will later be
6339 replaced with proper base and index regs. */
6341 && reload_in_progress
6342 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6346 return (REG_P (op0
) && REG_P (op1
)
6347 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6348 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6349 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6350 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6354 avoiding_indexed_address_p (enum machine_mode mode
)
6356 /* Avoid indexed addressing for modes that have non-indexed
6357 load/store instruction forms. */
6358 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6362 legitimate_indirect_address_p (rtx x
, int strict
)
6364 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6368 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6370 if (!TARGET_MACHO
|| !flag_pic
6371 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6375 if (GET_CODE (x
) != LO_SUM
)
6377 if (GET_CODE (XEXP (x
, 0)) != REG
)
6379 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6383 return CONSTANT_P (x
);
6387 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6389 if (GET_CODE (x
) != LO_SUM
)
6391 if (GET_CODE (XEXP (x
, 0)) != REG
)
6393 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6395 /* Restrict addressing for DI because of our SUBREG hackery. */
6396 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6400 if (TARGET_ELF
|| TARGET_MACHO
)
6404 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6406 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6407 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6408 recognizes some LO_SUM addresses as valid although this
6409 function says opposite. In most cases, LRA through different
6410 transformations can generate correct code for address reloads.
6411 It can not manage only some LO_SUM cases. So we need to add
6412 code analogous to one in rs6000_legitimize_reload_address for
6413 LOW_SUM here saying that some addresses are still valid. */
6414 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6415 && small_toc_ref (x
, VOIDmode
));
6416 if (TARGET_TOC
&& ! large_toc_ok
)
6418 if (GET_MODE_NUNITS (mode
) != 1)
6420 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6421 && !(/* ??? Assume floating point reg based on mode? */
6422 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6423 && (mode
== DFmode
|| mode
== DDmode
)))
6426 return CONSTANT_P (x
) || large_toc_ok
;
6433 /* Try machine-dependent ways of modifying an illegitimate address
6434 to be legitimate. If we find one, return the new, valid address.
6435 This is used from only one place: `memory_address' in explow.c.
6437 OLDX is the address as it was before break_out_memory_refs was
6438 called. In some cases it is useful to look at this to decide what
6441 It is always safe for this function to do nothing. It exists to
6442 recognize opportunities to optimize the output.
6444 On RS/6000, first check for the sum of a register with a constant
6445 integer that is out of range. If so, generate code to add the
6446 constant with the low-order 16 bits masked to the register and force
6447 this result into another register (this can be done with `cau').
6448 Then generate an address of REG+(CONST&0xffff), allowing for the
6449 possibility of bit 16 being a one.
6451 Then check for the sum of a register and something not constant, try to
6452 load the other things into a register and return the sum. */
6455 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6456 enum machine_mode mode
)
6460 if (!reg_offset_addressing_ok_p (mode
))
6462 if (virtual_stack_registers_memory_p (x
))
6465 /* In theory we should not be seeing addresses of the form reg+0,
6466 but just in case it is generated, optimize it away. */
6467 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6468 return force_reg (Pmode
, XEXP (x
, 0));
6470 /* For TImode with load/store quad, restrict addresses to just a single
6471 pointer, so it works with both GPRs and VSX registers. */
6472 /* Make sure both operands are registers. */
6473 else if (GET_CODE (x
) == PLUS
6474 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6475 return gen_rtx_PLUS (Pmode
,
6476 force_reg (Pmode
, XEXP (x
, 0)),
6477 force_reg (Pmode
, XEXP (x
, 1)));
6479 return force_reg (Pmode
, x
);
6481 if (GET_CODE (x
) == SYMBOL_REF
)
6483 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6485 return rs6000_legitimize_tls_address (x
, model
);
6495 /* As in legitimate_offset_address_p we do not assume
6496 worst-case. The mode here is just a hint as to the registers
6497 used. A TImode is usually in gprs, but may actually be in
6498 fprs. Leave worst-case scenario for reload to handle via
6499 insn constraints. PTImode is only GPRs. */
6506 if (GET_CODE (x
) == PLUS
6507 && GET_CODE (XEXP (x
, 0)) == REG
6508 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6509 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6511 && !(SPE_VECTOR_MODE (mode
)
6512 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6514 HOST_WIDE_INT high_int
, low_int
;
6516 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6517 if (low_int
>= 0x8000 - extra
)
6519 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6520 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6521 GEN_INT (high_int
)), 0);
6522 return plus_constant (Pmode
, sum
, low_int
);
6524 else if (GET_CODE (x
) == PLUS
6525 && GET_CODE (XEXP (x
, 0)) == REG
6526 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6527 && GET_MODE_NUNITS (mode
) == 1
6528 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6529 || (/* ??? Assume floating point reg based on mode? */
6530 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6531 && (mode
== DFmode
|| mode
== DDmode
)))
6532 && !avoiding_indexed_address_p (mode
))
6534 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6535 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6537 else if (SPE_VECTOR_MODE (mode
)
6538 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6542 /* We accept [reg + reg] and [reg + OFFSET]. */
6544 if (GET_CODE (x
) == PLUS
)
6546 rtx op1
= XEXP (x
, 0);
6547 rtx op2
= XEXP (x
, 1);
6550 op1
= force_reg (Pmode
, op1
);
6552 if (GET_CODE (op2
) != REG
6553 && (GET_CODE (op2
) != CONST_INT
6554 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6555 || (GET_MODE_SIZE (mode
) > 8
6556 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6557 op2
= force_reg (Pmode
, op2
);
6559 /* We can't always do [reg + reg] for these, because [reg +
6560 reg + offset] is not a legitimate addressing mode. */
6561 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6563 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6564 return force_reg (Pmode
, y
);
6569 return force_reg (Pmode
, x
);
6571 else if ((TARGET_ELF
6573 || !MACHO_DYNAMIC_NO_PIC_P
6579 && GET_CODE (x
) != CONST_INT
6580 && GET_CODE (x
) != CONST_DOUBLE
6582 && GET_MODE_NUNITS (mode
) == 1
6583 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6584 || (/* ??? Assume floating point reg based on mode? */
6585 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6586 && (mode
== DFmode
|| mode
== DDmode
))))
6588 rtx reg
= gen_reg_rtx (Pmode
);
6590 emit_insn (gen_elf_high (reg
, x
));
6592 emit_insn (gen_macho_high (reg
, x
));
6593 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6596 && GET_CODE (x
) == SYMBOL_REF
6597 && constant_pool_expr_p (x
)
6598 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6599 return create_TOC_reference (x
, NULL_RTX
);
6604 /* Debug version of rs6000_legitimize_address. */
6606 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6612 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6613 insns
= get_insns ();
6619 "\nrs6000_legitimize_address: mode %s, old code %s, "
6620 "new code %s, modified\n",
6621 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6622 GET_RTX_NAME (GET_CODE (ret
)));
6624 fprintf (stderr
, "Original address:\n");
6627 fprintf (stderr
, "oldx:\n");
6630 fprintf (stderr
, "New address:\n");
6635 fprintf (stderr
, "Insns added:\n");
6636 debug_rtx_list (insns
, 20);
6642 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6643 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6654 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6655 We need to emit DTP-relative relocations. */
6657 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6659 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6664 fputs ("\t.long\t", file
);
6667 fputs (DOUBLE_INT_ASM_OP
, file
);
6672 output_addr_const (file
, x
);
6673 fputs ("@dtprel+0x8000", file
);
6676 /* In the name of slightly smaller debug output, and to cater to
6677 general assembler lossage, recognize various UNSPEC sequences
6678 and turn them back into a direct symbol reference. */
6681 rs6000_delegitimize_address (rtx orig_x
)
6685 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6691 if (TARGET_CMODEL
!= CMODEL_SMALL
6692 && GET_CODE (y
) == LO_SUM
)
6696 if (GET_CODE (y
) == PLUS
6697 && GET_MODE (y
) == Pmode
6698 && CONST_INT_P (XEXP (y
, 1)))
6700 offset
= XEXP (y
, 1);
6704 if (GET_CODE (y
) == UNSPEC
6705 && XINT (y
, 1) == UNSPEC_TOCREL
)
6707 #ifdef ENABLE_CHECKING
6708 if (REG_P (XVECEXP (y
, 0, 1))
6709 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6713 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6715 /* Weirdness alert. df_note_compute can replace r2 with a
6716 debug_expr when this unspec is in a debug_insn.
6717 Seen in gcc.dg/pr51957-1.c */
6725 y
= XVECEXP (y
, 0, 0);
6728 /* Do not associate thread-local symbols with the original
6729 constant pool symbol. */
6731 && GET_CODE (y
) == SYMBOL_REF
6732 && CONSTANT_POOL_ADDRESS_P (y
)
6733 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
6737 if (offset
!= NULL_RTX
)
6738 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6739 if (!MEM_P (orig_x
))
6742 return replace_equiv_address_nv (orig_x
, y
);
6746 && GET_CODE (orig_x
) == LO_SUM
6747 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6749 y
= XEXP (XEXP (orig_x
, 1), 0);
6750 if (GET_CODE (y
) == UNSPEC
6751 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6752 return XVECEXP (y
, 0, 0);
6758 /* Return true if X shouldn't be emitted into the debug info.
6759 The linker doesn't like .toc section references from
6760 .debug_* sections, so reject .toc section symbols. */
6763 rs6000_const_not_ok_for_debug_p (rtx x
)
6765 if (GET_CODE (x
) == SYMBOL_REF
6766 && CONSTANT_POOL_ADDRESS_P (x
))
6768 rtx c
= get_pool_constant (x
);
6769 enum machine_mode cmode
= get_pool_mode (x
);
6770 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6777 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6779 static GTY(()) rtx rs6000_tls_symbol
;
6781 rs6000_tls_get_addr (void)
6783 if (!rs6000_tls_symbol
)
6784 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6786 return rs6000_tls_symbol
;
6789 /* Construct the SYMBOL_REF for TLS GOT references. */
6791 static GTY(()) rtx rs6000_got_symbol
;
6793 rs6000_got_sym (void)
6795 if (!rs6000_got_symbol
)
6797 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6798 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6799 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6802 return rs6000_got_symbol
;
6805 /* AIX Thread-Local Address support. */
6808 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6810 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6814 name
= XSTR (addr
, 0);
6815 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6816 or the symbol will be in TLS private data section. */
6817 if (name
[strlen (name
) - 1] != ']'
6818 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6819 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6821 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6822 strcpy (tlsname
, name
);
6824 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6825 tlsaddr
= copy_rtx (addr
);
6826 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6831 /* Place addr into TOC constant pool. */
6832 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6834 /* Output the TOC entry and create the MEM referencing the value. */
6835 if (constant_pool_expr_p (XEXP (sym
, 0))
6836 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6838 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6839 mem
= gen_const_mem (Pmode
, tocref
);
6840 set_mem_alias_set (mem
, get_TOC_alias_set ());
6845 /* Use global-dynamic for local-dynamic. */
6846 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6847 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6849 /* Create new TOC reference for @m symbol. */
6850 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6851 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6852 strcpy (tlsname
, "*LCM");
6853 strcat (tlsname
, name
+ 3);
6854 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6855 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6856 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6857 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6858 set_mem_alias_set (modmem
, get_TOC_alias_set ());
6860 rtx modreg
= gen_reg_rtx (Pmode
);
6861 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
6863 tmpreg
= gen_reg_rtx (Pmode
);
6864 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6866 dest
= gen_reg_rtx (Pmode
);
6868 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
6870 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
6873 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
6874 else if (TARGET_32BIT
)
6876 tlsreg
= gen_reg_rtx (SImode
);
6877 emit_insn (gen_tls_get_tpointer (tlsreg
));
6880 tlsreg
= gen_rtx_REG (DImode
, 13);
6882 /* Load the TOC value into temporary register. */
6883 tmpreg
= gen_reg_rtx (Pmode
);
6884 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6885 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
6886 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
6888 /* Add TOC symbol value to TLS pointer. */
6889 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
6894 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
6895 this (thread-local) address. */
6898 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6903 return rs6000_legitimize_tls_address_aix (addr
, model
);
6905 dest
= gen_reg_rtx (Pmode
);
6906 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
6912 tlsreg
= gen_rtx_REG (Pmode
, 13);
6913 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
6917 tlsreg
= gen_rtx_REG (Pmode
, 2);
6918 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
6922 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
6926 tmp
= gen_reg_rtx (Pmode
);
6929 tlsreg
= gen_rtx_REG (Pmode
, 13);
6930 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6934 tlsreg
= gen_rtx_REG (Pmode
, 2);
6935 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6939 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6941 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6946 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6948 /* We currently use relocations like @got@tlsgd for tls, which
6949 means the linker will handle allocation of tls entries, placing
6950 them in the .got section. So use a pointer to the .got section,
6951 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6952 or to secondary GOT sections used by 32-bit -fPIC. */
6954 got
= gen_rtx_REG (Pmode
, 2);
6958 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6961 rtx gsym
= rs6000_got_sym ();
6962 got
= gen_reg_rtx (Pmode
);
6964 rs6000_emit_move (got
, gsym
, Pmode
);
6969 tmp1
= gen_reg_rtx (Pmode
);
6970 tmp2
= gen_reg_rtx (Pmode
);
6971 mem
= gen_const_mem (Pmode
, tmp1
);
6972 lab
= gen_label_rtx ();
6973 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6974 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6975 if (TARGET_LINK_STACK
)
6976 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6977 emit_move_insn (tmp2
, mem
);
6978 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
6979 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
6984 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
6986 tga
= rs6000_tls_get_addr ();
6987 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
6988 1, const0_rtx
, Pmode
);
6990 r3
= gen_rtx_REG (Pmode
, 3);
6991 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
6994 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
6996 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
6998 else if (DEFAULT_ABI
== ABI_V4
)
6999 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7002 call_insn
= last_call_insn ();
7003 PATTERN (call_insn
) = insn
;
7004 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7005 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7006 pic_offset_table_rtx
);
7008 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7010 tga
= rs6000_tls_get_addr ();
7011 tmp1
= gen_reg_rtx (Pmode
);
7012 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7013 1, const0_rtx
, Pmode
);
7015 r3
= gen_rtx_REG (Pmode
, 3);
7016 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7019 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7021 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7023 else if (DEFAULT_ABI
== ABI_V4
)
7024 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7027 call_insn
= last_call_insn ();
7028 PATTERN (call_insn
) = insn
;
7029 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7030 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7031 pic_offset_table_rtx
);
7033 if (rs6000_tls_size
== 16)
7036 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7038 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7040 else if (rs6000_tls_size
== 32)
7042 tmp2
= gen_reg_rtx (Pmode
);
7044 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7046 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7049 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7051 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7055 tmp2
= gen_reg_rtx (Pmode
);
7057 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7059 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7061 insn
= gen_rtx_SET (Pmode
, dest
,
7062 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7068 /* IE, or 64-bit offset LE. */
7069 tmp2
= gen_reg_rtx (Pmode
);
7071 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7073 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7076 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7078 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7086 /* Return 1 if X contains a thread-local symbol. */
7089 rs6000_tls_referenced_p (rtx x
)
7091 if (! TARGET_HAVE_TLS
)
7094 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
7097 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7100 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7102 if (GET_CODE (x
) == HIGH
7103 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7106 /* A TLS symbol in the TOC cannot contain a sum. */
7107 if (GET_CODE (x
) == CONST
7108 && GET_CODE (XEXP (x
, 0)) == PLUS
7109 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7110 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7113 /* Do not place an ELF TLS symbol in the constant pool. */
7114 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
7117 /* Return 1 if *X is a thread-local symbol. This is the same as
7118 rs6000_tls_symbol_ref except for the type of the unused argument. */
7121 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7123 return RS6000_SYMBOL_REF_TLS_P (*x
);
7126 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7127 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7128 can be addressed relative to the toc pointer. */
7131 use_toc_relative_ref (rtx sym
)
7133 return ((constant_pool_expr_p (sym
)
7134 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7135 get_pool_mode (sym
)))
7136 || (TARGET_CMODEL
== CMODEL_MEDIUM
7137 && SYMBOL_REF_LOCAL_P (sym
)));
7140 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7141 replace the input X, or the original X if no replacement is called for.
7142 The output parameter *WIN is 1 if the calling macro should goto WIN,
7145 For RS/6000, we wish to handle large displacements off a base
7146 register by splitting the addend across an addiu/addis and the mem insn.
7147 This cuts number of extra insns needed from 3 to 1.
7149 On Darwin, we use this to generate code for floating point constants.
7150 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7151 The Darwin code is inside #if TARGET_MACHO because only then are the
7152 machopic_* functions defined. */
7154 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7155 int opnum
, int type
,
7156 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7158 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7160 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7161 DFmode/DImode MEM. */
7164 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7165 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7166 reg_offset_p
= false;
7168 /* We must recognize output that we have already generated ourselves. */
7169 if (GET_CODE (x
) == PLUS
7170 && GET_CODE (XEXP (x
, 0)) == PLUS
7171 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7172 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7173 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7175 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7176 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7177 opnum
, (enum reload_type
) type
);
7182 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7183 if (GET_CODE (x
) == LO_SUM
7184 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7186 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7187 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7188 opnum
, (enum reload_type
) type
);
7194 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7195 && GET_CODE (x
) == LO_SUM
7196 && GET_CODE (XEXP (x
, 0)) == PLUS
7197 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7198 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7199 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7200 && machopic_operand_p (XEXP (x
, 1)))
7202 /* Result of previous invocation of this function on Darwin
7203 floating point constant. */
7204 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7205 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7206 opnum
, (enum reload_type
) type
);
7212 if (TARGET_CMODEL
!= CMODEL_SMALL
7214 && small_toc_ref (x
, VOIDmode
))
7216 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7217 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7218 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7219 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7220 opnum
, (enum reload_type
) type
);
7225 if (GET_CODE (x
) == PLUS
7226 && GET_CODE (XEXP (x
, 0)) == REG
7227 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7228 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7229 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7231 && !SPE_VECTOR_MODE (mode
)
7232 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7233 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7235 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7236 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7238 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7240 /* Check for 32-bit overflow. */
7241 if (high
+ low
!= val
)
7247 /* Reload the high part into a base reg; leave the low part
7248 in the mem directly. */
7250 x
= gen_rtx_PLUS (GET_MODE (x
),
7251 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7255 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7256 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7257 opnum
, (enum reload_type
) type
);
7262 if (GET_CODE (x
) == SYMBOL_REF
7264 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7265 && !SPE_VECTOR_MODE (mode
)
7267 && DEFAULT_ABI
== ABI_DARWIN
7268 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7269 && machopic_symbol_defined_p (x
)
7271 && DEFAULT_ABI
== ABI_V4
7274 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7275 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7277 ??? Assume floating point reg based on mode? This assumption is
7278 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7279 where reload ends up doing a DFmode load of a constant from
7280 mem using two gprs. Unfortunately, at this point reload
7281 hasn't yet selected regs so poking around in reload data
7282 won't help and even if we could figure out the regs reliably,
7283 we'd still want to allow this transformation when the mem is
7284 naturally aligned. Since we say the address is good here, we
7285 can't disable offsets from LO_SUMs in mem_operand_gpr.
7286 FIXME: Allow offset from lo_sum for other modes too, when
7287 mem is sufficiently aligned. */
7290 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7292 && (mode
!= DImode
|| TARGET_POWERPC64
)
7293 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7294 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7299 rtx offset
= machopic_gen_offset (x
);
7300 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7301 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7302 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7306 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7307 gen_rtx_HIGH (Pmode
, x
), x
);
7309 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7310 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7311 opnum
, (enum reload_type
) type
);
7316 /* Reload an offset address wrapped by an AND that represents the
7317 masking of the lower bits. Strip the outer AND and let reload
7318 convert the offset address into an indirect address. For VSX,
7319 force reload to create the address with an AND in a separate
7320 register, because we can't guarantee an altivec register will
7322 if (VECTOR_MEM_ALTIVEC_P (mode
)
7323 && GET_CODE (x
) == AND
7324 && GET_CODE (XEXP (x
, 0)) == PLUS
7325 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7326 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7327 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7328 && INTVAL (XEXP (x
, 1)) == -16)
7337 && GET_CODE (x
) == SYMBOL_REF
7338 && use_toc_relative_ref (x
))
7340 x
= create_TOC_reference (x
, NULL_RTX
);
7341 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7342 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7343 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7344 opnum
, (enum reload_type
) type
);
7352 /* Debug version of rs6000_legitimize_reload_address. */
7354 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7355 int opnum
, int type
,
7356 int ind_levels
, int *win
)
7358 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7361 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7362 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7363 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7367 fprintf (stderr
, "Same address returned\n");
7369 fprintf (stderr
, "NULL returned\n");
7372 fprintf (stderr
, "New address:\n");
7379 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7380 that is a valid memory address for an instruction.
7381 The MODE argument is the machine mode for the MEM expression
7382 that wants to use this address.
7384 On the RS/6000, there are four valid address: a SYMBOL_REF that
7385 refers to a constant pool entry of an address (or the sum of it
7386 plus a constant), a short (16-bit signed) constant plus a register,
7387 the sum of two registers, or a register indirect, possibly with an
7388 auto-increment. For DFmode, DDmode and DImode with a constant plus
7389 register, we must ensure that both words are addressable or PowerPC64
7390 with offset word aligned.
7392 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7393 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7394 because adjacent memory cells are accessed by adding word-sized offsets
7395 during assembly output. */
7397 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7399 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7401 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7402 if (VECTOR_MEM_ALTIVEC_P (mode
)
7403 && GET_CODE (x
) == AND
7404 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7405 && INTVAL (XEXP (x
, 1)) == -16)
7408 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7410 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7413 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7414 && mode_supports_pre_incdec_p (mode
)
7415 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7417 if (virtual_stack_registers_memory_p (x
))
7419 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7422 && legitimate_constant_pool_address_p (x
, mode
,
7423 reg_ok_strict
|| lra_in_progress
))
7425 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7426 allow register indirect addresses. This will allow the values to go in
7427 either GPRs or VSX registers without reloading. The vector types would
7428 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7429 somewhat split, in that some uses are GPR based, and some VSX based. */
7430 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7432 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7435 && GET_CODE (x
) == PLUS
7436 && GET_CODE (XEXP (x
, 0)) == REG
7437 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7438 || XEXP (x
, 0) == arg_pointer_rtx
)
7439 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7441 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7445 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7447 || (mode
!= DFmode
&& mode
!= DDmode
)
7448 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7449 && (TARGET_POWERPC64
|| mode
!= DImode
)
7450 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7452 && !avoiding_indexed_address_p (mode
)
7453 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7455 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7456 && mode_supports_pre_modify_p (mode
)
7457 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7458 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7459 reg_ok_strict
, false)
7460 || (!avoiding_indexed_address_p (mode
)
7461 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7462 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7464 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7469 /* Debug version of rs6000_legitimate_address_p. */
7471 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7474 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7476 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7477 "strict = %d, reload = %s, code = %s\n",
7478 ret
? "true" : "false",
7479 GET_MODE_NAME (mode
),
7483 : (reload_in_progress
? "progress" : "before")),
7484 GET_RTX_NAME (GET_CODE (x
)));
7490 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7493 rs6000_mode_dependent_address_p (const_rtx addr
,
7494 addr_space_t as ATTRIBUTE_UNUSED
)
7496 return rs6000_mode_dependent_address_ptr (addr
);
7499 /* Go to LABEL if ADDR (a legitimate address expression)
7500 has an effect that depends on the machine mode it is used for.
7502 On the RS/6000 this is true of all integral offsets (since AltiVec
7503 and VSX modes don't allow them) or is a pre-increment or decrement.
7505 ??? Except that due to conceptual problems in offsettable_address_p
7506 we can't really report the problems of integral offsets. So leave
7507 this assuming that the adjustable offset must be valid for the
7508 sub-words of a TFmode operand, which is what we had before. */
7511 rs6000_mode_dependent_address (const_rtx addr
)
7513 switch (GET_CODE (addr
))
7516 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7517 is considered a legitimate address before reload, so there
7518 are no offset restrictions in that case. Note that this
7519 condition is safe in strict mode because any address involving
7520 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7521 been rejected as illegitimate. */
7522 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7523 && XEXP (addr
, 0) != arg_pointer_rtx
7524 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7526 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7527 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7532 /* Anything in the constant pool is sufficiently aligned that
7533 all bytes have the same high part address. */
7534 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7536 /* Auto-increment cases are now treated generically in recog.c. */
7538 return TARGET_UPDATE
;
7540 /* AND is only allowed in Altivec loads. */
7551 /* Debug version of rs6000_mode_dependent_address. */
7553 rs6000_debug_mode_dependent_address (const_rtx addr
)
7555 bool ret
= rs6000_mode_dependent_address (addr
);
7557 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7558 ret
? "true" : "false");
7564 /* Implement FIND_BASE_TERM. */
7567 rs6000_find_base_term (rtx op
)
7572 if (GET_CODE (base
) == CONST
)
7573 base
= XEXP (base
, 0);
7574 if (GET_CODE (base
) == PLUS
)
7575 base
= XEXP (base
, 0);
7576 if (GET_CODE (base
) == UNSPEC
)
7577 switch (XINT (base
, 1))
7580 case UNSPEC_MACHOPIC_OFFSET
:
7581 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7582 for aliasing purposes. */
7583 return XVECEXP (base
, 0, 0);
7589 /* More elaborate version of recog's offsettable_memref_p predicate
7590 that works around the ??? note of rs6000_mode_dependent_address.
7591 In particular it accepts
7593 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7595 in 32-bit mode, that the recog predicate rejects. */
7598 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7605 /* First mimic offsettable_memref_p. */
7606 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7609 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7610 the latter predicate knows nothing about the mode of the memory
7611 reference and, therefore, assumes that it is the largest supported
7612 mode (TFmode). As a consequence, legitimate offsettable memory
7613 references are rejected. rs6000_legitimate_offset_address_p contains
7614 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7615 at least with a little bit of help here given that we know the
7616 actual registers used. */
7617 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7618 || GET_MODE_SIZE (reg_mode
) == 4);
7619 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7623 /* Change register usage conditional on target flags. */
7625 rs6000_conditional_register_usage (void)
7629 if (TARGET_DEBUG_TARGET
)
7630 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7632 /* Set MQ register fixed (already call_used) so that it will not be
7636 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7638 fixed_regs
[13] = call_used_regs
[13]
7639 = call_really_used_regs
[13] = 1;
7641 /* Conditionally disable FPRs. */
7642 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7643 for (i
= 32; i
< 64; i
++)
7644 fixed_regs
[i
] = call_used_regs
[i
]
7645 = call_really_used_regs
[i
] = 1;
7647 /* The TOC register is not killed across calls in a way that is
7648 visible to the compiler. */
7649 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7650 call_really_used_regs
[2] = 0;
7652 if (DEFAULT_ABI
== ABI_V4
7653 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7655 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7657 if (DEFAULT_ABI
== ABI_V4
7658 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7660 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7661 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7662 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7664 if (DEFAULT_ABI
== ABI_DARWIN
7665 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7666 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7667 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7668 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7670 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7671 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7672 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7676 global_regs
[SPEFSCR_REGNO
] = 1;
7677 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7678 registers in prologues and epilogues. We no longer use r14
7679 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7680 pool for link-compatibility with older versions of GCC. Once
7681 "old" code has died out, we can return r14 to the allocation
7684 = call_used_regs
[14]
7685 = call_really_used_regs
[14] = 1;
7688 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7690 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7691 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7692 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7695 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7696 global_regs
[VSCR_REGNO
] = 1;
7698 if (TARGET_ALTIVEC_ABI
)
7700 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7701 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7703 /* AIX reserves VR20:31 in non-extended ABI mode. */
7705 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7706 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7711 /* Try to output insns to set TARGET equal to the constant C if it can
7712 be done in less than N insns. Do all computations in MODE.
7713 Returns the place where the output has been placed if it can be
7714 done and the insns have been emitted. If it would take more than N
7715 insns, zero is returned and no insns and emitted. */
7718 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7719 rtx source
, int n ATTRIBUTE_UNUSED
)
7721 rtx result
, insn
, set
;
7722 HOST_WIDE_INT c0
, c1
;
7729 dest
= gen_reg_rtx (mode
);
7730 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7734 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7736 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7737 GEN_INT (INTVAL (source
)
7738 & (~ (HOST_WIDE_INT
) 0xffff))));
7739 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7740 gen_rtx_IOR (SImode
, copy_rtx (result
),
7741 GEN_INT (INTVAL (source
) & 0xffff))));
7746 switch (GET_CODE (source
))
7749 c0
= INTVAL (source
);
7757 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7764 insn
= get_last_insn ();
7765 set
= single_set (insn
);
7766 if (! CONSTANT_P (SET_SRC (set
)))
7767 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7772 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7773 fall back to a straight forward decomposition. We do this to avoid
7774 exponential run times encountered when looking for longer sequences
7775 with rs6000_emit_set_const. */
7777 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7779 if (!TARGET_POWERPC64
)
7781 rtx operand1
, operand2
;
7783 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7785 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7787 emit_move_insn (operand1
, GEN_INT (c1
));
7788 emit_move_insn (operand2
, GEN_INT (c2
));
7792 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7795 ud2
= (c1
& 0xffff0000) >> 16;
7798 ud4
= (c2
& 0xffff0000) >> 16;
7800 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7801 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7802 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7804 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7805 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7807 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7810 emit_move_insn (copy_rtx (dest
),
7811 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7814 else if (ud3
== 0 && ud4
== 0)
7816 gcc_assert (ud2
& 0x8000);
7817 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7820 emit_move_insn (copy_rtx (dest
),
7821 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7823 emit_move_insn (copy_rtx (dest
),
7824 gen_rtx_ZERO_EXTEND (DImode
,
7825 gen_lowpart (SImode
,
7828 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7829 || (ud4
== 0 && ! (ud3
& 0x8000)))
7831 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7834 emit_move_insn (copy_rtx (dest
),
7835 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7837 emit_move_insn (copy_rtx (dest
),
7838 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7841 emit_move_insn (copy_rtx (dest
),
7842 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7847 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7850 emit_move_insn (copy_rtx (dest
),
7851 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7854 emit_move_insn (copy_rtx (dest
),
7855 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7858 emit_move_insn (copy_rtx (dest
),
7859 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7860 GEN_INT (ud2
<< 16)));
7862 emit_move_insn (copy_rtx (dest
),
7863 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7870 /* Helper for the following. Get rid of [r+r] memory refs
7871 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
7874 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7876 if (reload_in_progress
)
7879 if (GET_CODE (operands
[0]) == MEM
7880 && GET_CODE (XEXP (operands
[0], 0)) != REG
7881 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7882 GET_MODE (operands
[0]), false))
7884 = replace_equiv_address (operands
[0],
7885 copy_addr_to_reg (XEXP (operands
[0], 0)));
7887 if (GET_CODE (operands
[1]) == MEM
7888 && GET_CODE (XEXP (operands
[1], 0)) != REG
7889 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7890 GET_MODE (operands
[1]), false))
7892 = replace_equiv_address (operands
[1],
7893 copy_addr_to_reg (XEXP (operands
[1], 0)));
7896 /* Generate a vector of constants to permute MODE for a little-endian
7897 storage operation by swapping the two halves of a vector. */
7899 rs6000_const_vec (enum machine_mode mode
)
7924 v
= rtvec_alloc (subparts
);
7926 for (i
= 0; i
< subparts
/ 2; ++i
)
7927 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
7928 for (i
= subparts
/ 2; i
< subparts
; ++i
)
7929 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
7934 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
7935 for a VSX load or store operation. */
7937 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
7939 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
7940 return gen_rtx_VEC_SELECT (mode
, source
, par
);
7943 /* Emit a little-endian load from vector memory location SOURCE to VSX
7944 register DEST in mode MODE. The load is done with two permuting
7945 insn's that represent an lxvd2x and xxpermdi. */
7947 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
7949 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
7950 rtx permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
7951 rtx permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7952 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
7953 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
7956 /* Emit a little-endian store to vector memory location DEST from VSX
7957 register SOURCE in mode MODE. The store is done with two permuting
7958 insn's that represent an xxpermdi and an stxvd2x. */
7960 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
7962 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
7963 rtx permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
7964 rtx permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7965 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
7966 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
7969 /* Emit a sequence representing a little-endian VSX load or store,
7970 moving data from SOURCE to DEST in mode MODE. This is done
7971 separately from rs6000_emit_move to ensure it is called only
7972 during expand. LE VSX loads and stores introduced later are
7973 handled with a split. The expand-time RTL generation allows
7974 us to optimize away redundant pairs of register-permutes. */
7976 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
7978 gcc_assert (!BYTES_BIG_ENDIAN
7979 && VECTOR_MEM_VSX_P (mode
)
7981 && (MEM_P (source
) ^ MEM_P (dest
)));
7985 gcc_assert (REG_P (dest
));
7986 rs6000_emit_le_vsx_load (dest
, source
, mode
);
7990 if (!REG_P (source
))
7991 source
= force_reg (mode
, source
);
7992 rs6000_emit_le_vsx_store (dest
, source
, mode
);
7996 /* Emit a move from SOURCE to DEST in mode MODE. */
7998 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
8002 operands
[1] = source
;
8004 if (TARGET_DEBUG_ADDR
)
8007 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8008 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8009 GET_MODE_NAME (mode
),
8012 can_create_pseudo_p ());
8014 fprintf (stderr
, "source:\n");
8018 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8019 if (GET_CODE (operands
[1]) == CONST_DOUBLE
8020 && ! FLOAT_MODE_P (mode
)
8021 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8023 /* FIXME. This should never happen. */
8024 /* Since it seems that it does, do the safe thing and convert
8026 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
8028 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
8029 || FLOAT_MODE_P (mode
)
8030 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
8031 || CONST_DOUBLE_LOW (operands
[1]) < 0)
8032 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
8033 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
8035 /* Check if GCC is setting up a block move that will end up using FP
8036 registers as temporaries. We must make sure this is acceptable. */
8037 if (GET_CODE (operands
[0]) == MEM
8038 && GET_CODE (operands
[1]) == MEM
8040 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8041 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8042 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8043 ? 32 : MEM_ALIGN (operands
[0])))
8044 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8046 : MEM_ALIGN (operands
[1]))))
8047 && ! MEM_VOLATILE_P (operands
[0])
8048 && ! MEM_VOLATILE_P (operands
[1]))
8050 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8051 adjust_address (operands
[1], SImode
, 0));
8052 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8053 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8057 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8058 && !gpc_reg_operand (operands
[1], mode
))
8059 operands
[1] = force_reg (mode
, operands
[1]);
8061 /* Recognize the case where operand[1] is a reference to thread-local
8062 data and load its address to a register. */
8063 if (rs6000_tls_referenced_p (operands
[1]))
8065 enum tls_model model
;
8066 rtx tmp
= operands
[1];
8069 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8071 addend
= XEXP (XEXP (tmp
, 0), 1);
8072 tmp
= XEXP (XEXP (tmp
, 0), 0);
8075 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8076 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8077 gcc_assert (model
!= 0);
8079 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8082 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8083 tmp
= force_operand (tmp
, operands
[0]);
8088 /* Handle the case where reload calls us with an invalid address. */
8089 if (reload_in_progress
&& mode
== Pmode
8090 && (! general_operand (operands
[1], mode
)
8091 || ! nonimmediate_operand (operands
[0], mode
)))
8094 /* 128-bit constant floating-point values on Darwin should really be
8095 loaded as two parts. */
8096 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8097 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8099 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8100 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8102 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8103 GET_MODE_SIZE (DFmode
)),
8104 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8105 GET_MODE_SIZE (DFmode
)),
8110 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8111 cfun
->machine
->sdmode_stack_slot
=
8112 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8117 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8118 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8119 && (REG_P (operands
[1])
8120 || (GET_CODE (operands
[1]) == SUBREG
8121 && REG_P (SUBREG_REG (operands
[1])))))
8123 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8124 ? SUBREG_REG (operands
[1]) : operands
[1]);
8127 if (regno
>= FIRST_PSEUDO_REGISTER
)
8129 cl
= reg_preferred_class (regno
);
8130 gcc_assert (cl
!= NO_REGS
);
8131 regno
= ira_class_hard_regs
[cl
][0];
8133 if (FP_REGNO_P (regno
))
8135 if (GET_MODE (operands
[0]) != DDmode
)
8136 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8137 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8139 else if (INT_REGNO_P (regno
))
8140 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8147 && (REG_P (operands
[0])
8148 || (GET_CODE (operands
[0]) == SUBREG
8149 && REG_P (SUBREG_REG (operands
[0]))))
8150 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8151 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8153 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8154 ? SUBREG_REG (operands
[0]) : operands
[0]);
8157 if (regno
>= FIRST_PSEUDO_REGISTER
)
8159 cl
= reg_preferred_class (regno
);
8160 gcc_assert (cl
!= NO_REGS
);
8161 regno
= ira_class_hard_regs
[cl
][0];
8163 if (FP_REGNO_P (regno
))
8165 if (GET_MODE (operands
[1]) != DDmode
)
8166 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8167 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8169 else if (INT_REGNO_P (regno
))
8170 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8176 if (reload_in_progress
8178 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8179 && MEM_P (operands
[0])
8180 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8181 && REG_P (operands
[1]))
8183 if (FP_REGNO_P (REGNO (operands
[1])))
8185 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8186 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8187 emit_insn (gen_movsd_store (mem
, operands
[1]));
8189 else if (INT_REGNO_P (REGNO (operands
[1])))
8191 rtx mem
= operands
[0];
8192 if (BYTES_BIG_ENDIAN
)
8193 mem
= adjust_address_nv (mem
, mode
, 4);
8194 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8195 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8201 if (reload_in_progress
8203 && REG_P (operands
[0])
8204 && MEM_P (operands
[1])
8205 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8206 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8208 if (FP_REGNO_P (REGNO (operands
[0])))
8210 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8211 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8212 emit_insn (gen_movsd_load (operands
[0], mem
));
8214 else if (INT_REGNO_P (REGNO (operands
[0])))
8216 rtx mem
= operands
[1];
8217 if (BYTES_BIG_ENDIAN
)
8218 mem
= adjust_address_nv (mem
, mode
, 4);
8219 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8220 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8227 /* FIXME: In the long term, this switch statement should go away
8228 and be replaced by a sequence of tests based on things like
8234 if (CONSTANT_P (operands
[1])
8235 && GET_CODE (operands
[1]) != CONST_INT
)
8236 operands
[1] = force_const_mem (mode
, operands
[1]);
8241 rs6000_eliminate_indexed_memrefs (operands
);
8248 if (CONSTANT_P (operands
[1])
8249 && ! easy_fp_constant (operands
[1], mode
))
8250 operands
[1] = force_const_mem (mode
, operands
[1]);
8263 if (CONSTANT_P (operands
[1])
8264 && !easy_vector_constant (operands
[1], mode
))
8265 operands
[1] = force_const_mem (mode
, operands
[1]);
8270 /* Use default pattern for address of ELF small data */
8273 && DEFAULT_ABI
== ABI_V4
8274 && (GET_CODE (operands
[1]) == SYMBOL_REF
8275 || GET_CODE (operands
[1]) == CONST
)
8276 && small_data_operand (operands
[1], mode
))
8278 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8282 if (DEFAULT_ABI
== ABI_V4
8283 && mode
== Pmode
&& mode
== SImode
8284 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8286 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8290 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8294 && CONSTANT_P (operands
[1])
8295 && GET_CODE (operands
[1]) != HIGH
8296 && GET_CODE (operands
[1]) != CONST_INT
)
8298 rtx target
= (!can_create_pseudo_p ()
8300 : gen_reg_rtx (mode
));
8302 /* If this is a function address on -mcall-aixdesc,
8303 convert it to the address of the descriptor. */
8304 if (DEFAULT_ABI
== ABI_AIX
8305 && GET_CODE (operands
[1]) == SYMBOL_REF
8306 && XSTR (operands
[1], 0)[0] == '.')
8308 const char *name
= XSTR (operands
[1], 0);
8310 while (*name
== '.')
8312 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8313 CONSTANT_POOL_ADDRESS_P (new_ref
)
8314 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8315 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8316 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8317 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8318 operands
[1] = new_ref
;
8321 if (DEFAULT_ABI
== ABI_DARWIN
)
8324 if (MACHO_DYNAMIC_NO_PIC_P
)
8326 /* Take care of any required data indirection. */
8327 operands
[1] = rs6000_machopic_legitimize_pic_address (
8328 operands
[1], mode
, operands
[0]);
8329 if (operands
[0] != operands
[1])
8330 emit_insn (gen_rtx_SET (VOIDmode
,
8331 operands
[0], operands
[1]));
8335 emit_insn (gen_macho_high (target
, operands
[1]));
8336 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8340 emit_insn (gen_elf_high (target
, operands
[1]));
8341 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8345 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8346 and we have put it in the TOC, we just need to make a TOC-relative
8349 && GET_CODE (operands
[1]) == SYMBOL_REF
8350 && use_toc_relative_ref (operands
[1]))
8351 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8352 else if (mode
== Pmode
8353 && CONSTANT_P (operands
[1])
8354 && GET_CODE (operands
[1]) != HIGH
8355 && ((GET_CODE (operands
[1]) != CONST_INT
8356 && ! easy_fp_constant (operands
[1], mode
))
8357 || (GET_CODE (operands
[1]) == CONST_INT
8358 && (num_insns_constant (operands
[1], mode
)
8359 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8360 || (GET_CODE (operands
[0]) == REG
8361 && FP_REGNO_P (REGNO (operands
[0]))))
8362 && !toc_relative_expr_p (operands
[1], false)
8363 && (TARGET_CMODEL
== CMODEL_SMALL
8364 || can_create_pseudo_p ()
8365 || (REG_P (operands
[0])
8366 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8370 /* Darwin uses a special PIC legitimizer. */
8371 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8374 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8376 if (operands
[0] != operands
[1])
8377 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8382 /* If we are to limit the number of things we put in the TOC and
8383 this is a symbol plus a constant we can add in one insn,
8384 just put the symbol in the TOC and add the constant. Don't do
8385 this if reload is in progress. */
8386 if (GET_CODE (operands
[1]) == CONST
8387 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8388 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8389 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8390 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8391 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8392 && ! side_effects_p (operands
[0]))
8395 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8396 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8398 sym
= force_reg (mode
, sym
);
8399 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8403 operands
[1] = force_const_mem (mode
, operands
[1]);
8406 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8407 && constant_pool_expr_p (XEXP (operands
[1], 0))
8408 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8409 get_pool_constant (XEXP (operands
[1], 0)),
8410 get_pool_mode (XEXP (operands
[1], 0))))
8412 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8414 operands
[1] = gen_const_mem (mode
, tocref
);
8415 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8421 if (!VECTOR_MEM_VSX_P (TImode
))
8422 rs6000_eliminate_indexed_memrefs (operands
);
8426 rs6000_eliminate_indexed_memrefs (operands
);
8430 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8433 /* Above, we may have called force_const_mem which may have returned
8434 an invalid address. If we can, fix this up; otherwise, reload will
8435 have to deal with it. */
8436 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8437 operands
[1] = validize_mem (operands
[1]);
8440 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8443 /* Return true if a structure, union or array containing FIELD should be
8444 accessed using `BLKMODE'.
8446 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8447 entire thing in a DI and use subregs to access the internals.
8448 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8449 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8450 best thing to do is set structs to BLKmode and avoid Severe Tire
8453 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8454 fit into 1, whereas DI still needs two. */
8457 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8459 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8460 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8463 /* Nonzero if we can use a floating-point register to pass this arg. */
8464 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8465 (SCALAR_FLOAT_MODE_P (MODE) \
8466 && (CUM)->fregno <= FP_ARG_MAX_REG \
8467 && TARGET_HARD_FLOAT && TARGET_FPRS)
8469 /* Nonzero if we can use an AltiVec register to pass this arg. */
8470 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8471 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8472 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8473 && TARGET_ALTIVEC_ABI \
8476 /* Walk down the type tree of TYPE counting consecutive base elements.
8477 If *MODEP is VOIDmode, then set it to the first valid floating point
8478 or vector type. If a non-floating point or vector type is found, or
8479 if a floating point or vector type that doesn't match a non-VOIDmode
8480 *MODEP is found, then return -1, otherwise return the count in the
8484 rs6000_aggregate_candidate (const_tree type
, enum machine_mode
*modep
)
8486 enum machine_mode mode
;
8489 switch (TREE_CODE (type
))
8492 mode
= TYPE_MODE (type
);
8493 if (!SCALAR_FLOAT_MODE_P (mode
))
8496 if (*modep
== VOIDmode
)
8505 mode
= TYPE_MODE (TREE_TYPE (type
));
8506 if (!SCALAR_FLOAT_MODE_P (mode
))
8509 if (*modep
== VOIDmode
)
8518 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
8521 /* Use V4SImode as representative of all 128-bit vector types. */
8522 size
= int_size_in_bytes (type
);
8532 if (*modep
== VOIDmode
)
8535 /* Vector modes are considered to be opaque: two vectors are
8536 equivalent for the purposes of being homogeneous aggregates
8537 if they are the same size. */
8546 tree index
= TYPE_DOMAIN (type
);
8548 /* Can't handle incomplete types. */
8549 if (!COMPLETE_TYPE_P (type
))
8552 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
8555 || !TYPE_MAX_VALUE (index
)
8556 || !host_integerp (TYPE_MAX_VALUE (index
), 1)
8557 || !TYPE_MIN_VALUE (index
)
8558 || !host_integerp (TYPE_MIN_VALUE (index
), 1)
8562 count
*= (1 + tree_low_cst (TYPE_MAX_VALUE (index
), 1)
8563 - tree_low_cst (TYPE_MIN_VALUE (index
), 1));
8565 /* There must be no padding. */
8566 if (!host_integerp (TYPE_SIZE (type
), 1)
8567 || (tree_low_cst (TYPE_SIZE (type
), 1)
8568 != count
* GET_MODE_BITSIZE (*modep
)))
8580 /* Can't handle incomplete types. */
8581 if (!COMPLETE_TYPE_P (type
))
8584 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8586 if (TREE_CODE (field
) != FIELD_DECL
)
8589 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8595 /* There must be no padding. */
8596 if (!host_integerp (TYPE_SIZE (type
), 1)
8597 || (tree_low_cst (TYPE_SIZE (type
), 1)
8598 != count
* GET_MODE_BITSIZE (*modep
)))
8605 case QUAL_UNION_TYPE
:
8607 /* These aren't very interesting except in a degenerate case. */
8612 /* Can't handle incomplete types. */
8613 if (!COMPLETE_TYPE_P (type
))
8616 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8618 if (TREE_CODE (field
) != FIELD_DECL
)
8621 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8624 count
= count
> sub_count
? count
: sub_count
;
8627 /* There must be no padding. */
8628 if (!host_integerp (TYPE_SIZE (type
), 1)
8629 || (tree_low_cst (TYPE_SIZE (type
), 1)
8630 != count
* GET_MODE_BITSIZE (*modep
)))
8643 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
8644 float or vector aggregate that shall be passed in FP/vector registers
8645 according to the ELFv2 ABI, return the homogeneous element mode in
8646 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
8648 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
8651 rs6000_discover_homogeneous_aggregate (enum machine_mode mode
, const_tree type
,
8652 enum machine_mode
*elt_mode
,
8655 /* Note that we do not accept complex types at the top level as
8656 homogeneous aggregates; these types are handled via the
8657 targetm.calls.split_complex_arg mechanism. Complex types
8658 can be elements of homogeneous aggregates, however. */
8659 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
8661 enum machine_mode field_mode
= VOIDmode
;
8662 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
8664 if (field_count
> 0)
8666 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
8667 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
8669 /* The ELFv2 ABI allows homogeneous aggregates to occupy
8670 up to AGGR_ARG_NUM_REG registers. */
8671 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
8674 *elt_mode
= field_mode
;
8676 *n_elts
= field_count
;
8689 /* Return a nonzero value to say to return the function value in
8690 memory, just as large structures are always returned. TYPE will be
8691 the data type of the value, and FNTYPE will be the type of the
8692 function doing the returning, or @code{NULL} for libcalls.
8694 The AIX ABI for the RS/6000 specifies that all structures are
8695 returned in memory. The Darwin ABI does the same.
8697 For the Darwin 64 Bit ABI, a function result can be returned in
8698 registers or in memory, depending on the size of the return data
8699 type. If it is returned in registers, the value occupies the same
8700 registers as it would if it were the first and only function
8701 argument. Otherwise, the function places its result in memory at
8702 the location pointed to by GPR3.
8704 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8705 but a draft put them in memory, and GCC used to implement the draft
8706 instead of the final standard. Therefore, aix_struct_return
8707 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8708 compatibility can change DRAFT_V4_STRUCT_RET to override the
8709 default, and -m switches get the final word. See
8710 rs6000_option_override_internal for more details.
8712 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8713 long double support is enabled. These values are returned in memory.
8715 int_size_in_bytes returns -1 for variable size objects, which go in
8716 memory always. The cast to unsigned makes -1 > 8. */
8719 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8721 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8723 && rs6000_darwin64_abi
8724 && TREE_CODE (type
) == RECORD_TYPE
8725 && int_size_in_bytes (type
) > 0)
8727 CUMULATIVE_ARGS valcum
;
8731 valcum
.fregno
= FP_ARG_MIN_REG
;
8732 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8733 /* Do a trial code generation as if this were going to be passed
8734 as an argument; if any part goes in memory, we return NULL. */
8735 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8738 /* Otherwise fall through to more conventional ABI rules. */
8741 #if HAVE_UPC_PTS_STRUCT_REP
8742 if (POINTER_TYPE_P (type
) && upc_shared_type_p (TREE_TYPE (type
)))
8746 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
8747 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
8751 /* The ELFv2 ABI returns aggregates up to 16B in registers */
8752 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
8753 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
8756 if (AGGREGATE_TYPE_P (type
)
8757 && (aix_struct_return
8758 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8761 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8762 modes only exist for GCC vector types if -maltivec. */
8763 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8764 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8767 /* Return synthetic vectors in memory. */
8768 if (TREE_CODE (type
) == VECTOR_TYPE
8769 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8771 static bool warned_for_return_big_vectors
= false;
8772 if (!warned_for_return_big_vectors
)
8774 warning (0, "GCC vector returned by reference: "
8775 "non-standard ABI extension with no compatibility guarantee");
8776 warned_for_return_big_vectors
= true;
8781 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8787 /* Specify whether values returned in registers should be at the most
8788 significant end of a register. We want aggregates returned by
8789 value to match the way aggregates are passed to functions. */
8792 rs6000_return_in_msb (const_tree valtype
)
8794 return (DEFAULT_ABI
== ABI_ELFv2
8796 && AGGREGATE_TYPE_P (valtype
)
8797 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
8800 #ifdef HAVE_AS_GNU_ATTRIBUTE
8801 /* Return TRUE if a call to function FNDECL may be one that
8802 potentially affects the function calling ABI of the object file. */
8805 call_ABI_of_interest (tree fndecl
)
8807 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8809 struct cgraph_node
*c_node
;
8811 /* Libcalls are always interesting. */
8812 if (fndecl
== NULL_TREE
)
8815 /* Any call to an external function is interesting. */
8816 if (DECL_EXTERNAL (fndecl
))
8819 /* Interesting functions that we are emitting in this object file. */
8820 c_node
= cgraph_get_node (fndecl
);
8821 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8822 return !cgraph_only_called_directly_p (c_node
);
8828 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8829 for a call to a function whose data type is FNTYPE.
8830 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8832 For incoming args we set the number of arguments in the prototype large
8833 so we never return a PARALLEL. */
8836 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8837 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8838 int libcall
, int n_named_args
,
8839 tree fndecl ATTRIBUTE_UNUSED
,
8840 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8842 static CUMULATIVE_ARGS zero_cumulative
;
8844 *cum
= zero_cumulative
;
8846 cum
->fregno
= FP_ARG_MIN_REG
;
8847 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8848 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8849 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8850 ? CALL_LIBCALL
: CALL_NORMAL
);
8851 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8852 cum
->stdarg
= stdarg_p (fntype
);
8854 cum
->nargs_prototype
= 0;
8855 if (incoming
|| cum
->prototype
)
8856 cum
->nargs_prototype
= n_named_args
;
8858 /* Check for a longcall attribute. */
8859 if ((!fntype
&& rs6000_default_long_calls
)
8861 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
8862 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
8863 cum
->call_cookie
|= CALL_LONG
;
8865 if (TARGET_DEBUG_ARG
)
8867 fprintf (stderr
, "\ninit_cumulative_args:");
8870 tree ret_type
= TREE_TYPE (fntype
);
8871 fprintf (stderr
, " ret code = %s,",
8872 get_tree_code_name (TREE_CODE (ret_type
)));
8875 if (cum
->call_cookie
& CALL_LONG
)
8876 fprintf (stderr
, " longcall,");
8878 fprintf (stderr
, " proto = %d, nargs = %d\n",
8879 cum
->prototype
, cum
->nargs_prototype
);
8882 #ifdef HAVE_AS_GNU_ATTRIBUTE
8883 if (DEFAULT_ABI
== ABI_V4
)
8885 cum
->escapes
= call_ABI_of_interest (fndecl
);
8892 return_type
= TREE_TYPE (fntype
);
8893 return_mode
= TYPE_MODE (return_type
);
8896 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
8898 if (return_type
!= NULL
)
8900 if (TREE_CODE (return_type
) == RECORD_TYPE
8901 && TYPE_TRANSPARENT_AGGR (return_type
))
8903 return_type
= TREE_TYPE (first_field (return_type
));
8904 return_mode
= TYPE_MODE (return_type
);
8906 if (AGGREGATE_TYPE_P (return_type
)
8907 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
8909 rs6000_returns_struct
= true;
8911 if (SCALAR_FLOAT_MODE_P (return_mode
))
8912 rs6000_passes_float
= true;
8913 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
8914 || SPE_VECTOR_MODE (return_mode
))
8915 rs6000_passes_vector
= true;
8922 && TARGET_ALTIVEC_ABI
8923 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
8925 error ("cannot return value in vector register because"
8926 " altivec instructions are disabled, use -maltivec"
8931 /* Return true if TYPE must be passed on the stack and not in registers. */
8934 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
8936 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
8937 return must_pass_in_stack_var_size (mode
, type
);
8939 return must_pass_in_stack_var_size_or_pad (mode
, type
);
8942 /* If defined, a C expression which determines whether, and in which
8943 direction, to pad out an argument with extra space. The value
8944 should be of type `enum direction': either `upward' to pad above
8945 the argument, `downward' to pad below, or `none' to inhibit
8948 For the AIX ABI structs are always stored left shifted in their
8952 function_arg_padding (enum machine_mode mode
, const_tree type
)
8954 #ifndef AGGREGATE_PADDING_FIXED
8955 #define AGGREGATE_PADDING_FIXED 0
8957 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
8958 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
8961 if (!AGGREGATE_PADDING_FIXED
)
8963 /* GCC used to pass structures of the same size as integer types as
8964 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
8965 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
8966 passed padded downward, except that -mstrict-align further
8967 muddied the water in that multi-component structures of 2 and 4
8968 bytes in size were passed padded upward.
8970 The following arranges for best compatibility with previous
8971 versions of gcc, but removes the -mstrict-align dependency. */
8972 if (BYTES_BIG_ENDIAN
)
8974 HOST_WIDE_INT size
= 0;
8976 if (mode
== BLKmode
)
8978 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
8979 size
= int_size_in_bytes (type
);
8982 size
= GET_MODE_SIZE (mode
);
8984 if (size
== 1 || size
== 2 || size
== 4)
8990 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
8992 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
8996 /* Fall back to the default. */
8997 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9000 /* If defined, a C expression that gives the alignment boundary, in bits,
9001 of an argument with the specified mode and type. If it is not defined,
9002 PARM_BOUNDARY is used for all arguments.
9004 V.4 wants long longs and doubles to be double word aligned. Just
9005 testing the mode size is a boneheaded way to do this as it means
9006 that other types such as complex int are also double word aligned.
9007 However, we're stuck with this because changing the ABI might break
9008 existing library interfaces.
9010 Doubleword align SPE vectors.
9011 Quadword align Altivec/VSX vectors.
9012 Quadword align large synthetic vector types. */
9015 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9017 enum machine_mode elt_mode
;
9020 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9022 if (DEFAULT_ABI
== ABI_V4
9023 && (GET_MODE_SIZE (mode
) == 8
9024 || (TARGET_HARD_FLOAT
9026 && (mode
== TFmode
|| mode
== TDmode
))))
9028 else if (SPE_VECTOR_MODE (mode
)
9029 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9030 && int_size_in_bytes (type
) >= 8
9031 && int_size_in_bytes (type
) < 16))
9033 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9034 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9035 && int_size_in_bytes (type
) >= 16))
9037 else if (((TARGET_MACHO
&& rs6000_darwin64_abi
)
9038 || DEFAULT_ABI
== ABI_ELFv2
9039 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
9041 && type
&& TYPE_ALIGN (type
) > 64)
9044 return PARM_BOUNDARY
;
9047 /* The offset in words to the start of the parameter save area. */
9050 rs6000_parm_offset (void)
9052 return (DEFAULT_ABI
== ABI_V4
? 2
9053 : DEFAULT_ABI
== ABI_ELFv2
? 4
9057 /* For a function parm of MODE and TYPE, return the starting word in
9058 the parameter area. NWORDS of the parameter area are already used. */
9061 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
9062 unsigned int nwords
)
9066 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9067 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9070 /* Compute the size (in words) of a function argument. */
9072 static unsigned long
9073 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
9077 if (mode
!= BLKmode
)
9078 size
= GET_MODE_SIZE (mode
);
9080 size
= int_size_in_bytes (type
);
9083 return (size
+ 3) >> 2;
9085 return (size
+ 7) >> 3;
9088 /* Use this to flush pending int fields. */
9091 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9092 HOST_WIDE_INT bitpos
, int final
)
9094 unsigned int startbit
, endbit
;
9095 int intregs
, intoffset
;
9096 enum machine_mode mode
;
9098 /* Handle the situations where a float is taking up the first half
9099 of the GPR, and the other half is empty (typically due to
9100 alignment restrictions). We can detect this by a 8-byte-aligned
9101 int field, or by seeing that this is the final flush for this
9102 argument. Count the word and continue on. */
9103 if (cum
->floats_in_gpr
== 1
9104 && (cum
->intoffset
% 64 == 0
9105 || (cum
->intoffset
== -1 && final
)))
9108 cum
->floats_in_gpr
= 0;
9111 if (cum
->intoffset
== -1)
9114 intoffset
= cum
->intoffset
;
9115 cum
->intoffset
= -1;
9116 cum
->floats_in_gpr
= 0;
9118 if (intoffset
% BITS_PER_WORD
!= 0)
9120 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9122 if (mode
== BLKmode
)
9124 /* We couldn't find an appropriate mode, which happens,
9125 e.g., in packed structs when there are 3 bytes to load.
9126 Back intoffset back to the beginning of the word in this
9128 intoffset
= intoffset
& -BITS_PER_WORD
;
9132 startbit
= intoffset
& -BITS_PER_WORD
;
9133 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9134 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9135 cum
->words
+= intregs
;
9136 /* words should be unsigned. */
9137 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9139 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9144 /* The darwin64 ABI calls for us to recurse down through structs,
9145 looking for elements passed in registers. Unfortunately, we have
9146 to track int register count here also because of misalignments
9147 in powerpc alignment mode. */
9150 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9152 HOST_WIDE_INT startbitpos
)
9156 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9157 if (TREE_CODE (f
) == FIELD_DECL
)
9159 HOST_WIDE_INT bitpos
= startbitpos
;
9160 tree ftype
= TREE_TYPE (f
);
9161 enum machine_mode mode
;
9162 if (ftype
== error_mark_node
)
9164 mode
= TYPE_MODE (ftype
);
9166 if (DECL_SIZE (f
) != 0
9167 && host_integerp (bit_position (f
), 1))
9168 bitpos
+= int_bit_position (f
);
9170 /* ??? FIXME: else assume zero offset. */
9172 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9173 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9174 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9176 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9177 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9178 cum
->fregno
+= n_fpregs
;
9179 /* Single-precision floats present a special problem for
9180 us, because they are smaller than an 8-byte GPR, and so
9181 the structure-packing rules combined with the standard
9182 varargs behavior mean that we want to pack float/float
9183 and float/int combinations into a single register's
9184 space. This is complicated by the arg advance flushing,
9185 which works on arbitrarily large groups of int-type
9189 if (cum
->floats_in_gpr
== 1)
9191 /* Two floats in a word; count the word and reset
9194 cum
->floats_in_gpr
= 0;
9196 else if (bitpos
% 64 == 0)
9198 /* A float at the beginning of an 8-byte word;
9199 count it and put off adjusting cum->words until
9200 we see if a arg advance flush is going to do it
9202 cum
->floats_in_gpr
++;
9206 /* The float is at the end of a word, preceded
9207 by integer fields, so the arg advance flush
9208 just above has already set cum->words and
9209 everything is taken care of. */
9213 cum
->words
+= n_fpregs
;
9215 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9217 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9221 else if (cum
->intoffset
== -1)
9222 cum
->intoffset
= bitpos
;
9226 /* Check for an item that needs to be considered specially under the darwin 64
9227 bit ABI. These are record types where the mode is BLK or the structure is
9230 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
9232 return rs6000_darwin64_abi
9233 && ((mode
== BLKmode
9234 && TREE_CODE (type
) == RECORD_TYPE
9235 && int_size_in_bytes (type
) > 0)
9236 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9237 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9240 /* Update the data in CUM to advance over an argument
9241 of mode MODE and data type TYPE.
9242 (TYPE is null for libcalls where that information may not be available.)
9244 Note that for args passed by reference, function_arg will be called
9245 with MODE and TYPE set to that of the pointer to the arg, not the arg
9249 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9250 const_tree type
, bool named
, int depth
)
9252 enum machine_mode elt_mode
;
9255 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9257 /* Only tick off an argument if we're not recursing. */
9259 cum
->nargs_prototype
--;
9261 #ifdef HAVE_AS_GNU_ATTRIBUTE
9262 if (DEFAULT_ABI
== ABI_V4
9265 if (SCALAR_FLOAT_MODE_P (mode
))
9266 rs6000_passes_float
= true;
9267 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9268 rs6000_passes_vector
= true;
9269 else if (SPE_VECTOR_MODE (mode
)
9271 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9272 rs6000_passes_vector
= true;
9276 if (TARGET_ALTIVEC_ABI
9277 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9278 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9279 && int_size_in_bytes (type
) == 16)))
9283 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9285 cum
->vregno
+= n_elts
;
9287 if (!TARGET_ALTIVEC
)
9288 error ("cannot pass argument in vector register because"
9289 " altivec instructions are disabled, use -maltivec"
9292 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9293 even if it is going to be passed in a vector register.
9294 Darwin does the same for variable-argument functions. */
9295 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9297 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9307 /* Vector parameters must be 16-byte aligned. In 32-bit
9308 mode this means we need to take into account the offset
9309 to the parameter save area. In 64-bit mode, they just
9310 have to start on an even word, since the parameter save
9311 area is 16-byte aligned. */
9313 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9315 align
= cum
->words
& 1;
9316 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9318 if (TARGET_DEBUG_ARG
)
9320 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9322 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9323 cum
->nargs_prototype
, cum
->prototype
,
9324 GET_MODE_NAME (mode
));
9328 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9330 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9333 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9335 int size
= int_size_in_bytes (type
);
9336 /* Variable sized types have size == -1 and are
9337 treated as if consisting entirely of ints.
9338 Pad to 16 byte boundary if needed. */
9339 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9340 && (cum
->words
% 2) != 0)
9342 /* For varargs, we can just go up by the size of the struct. */
9344 cum
->words
+= (size
+ 7) / 8;
9347 /* It is tempting to say int register count just goes up by
9348 sizeof(type)/8, but this is wrong in a case such as
9349 { int; double; int; } [powerpc alignment]. We have to
9350 grovel through the fields for these too. */
9352 cum
->floats_in_gpr
= 0;
9353 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9354 rs6000_darwin64_record_arg_advance_flush (cum
,
9355 size
* BITS_PER_UNIT
, 1);
9357 if (TARGET_DEBUG_ARG
)
9359 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9360 cum
->words
, TYPE_ALIGN (type
), size
);
9362 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9363 cum
->nargs_prototype
, cum
->prototype
,
9364 GET_MODE_NAME (mode
));
9367 else if (DEFAULT_ABI
== ABI_V4
)
9369 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9370 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9371 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9372 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9373 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9375 /* _Decimal128 must use an even/odd register pair. This assumes
9376 that the register number is odd when fregno is odd. */
9377 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9380 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9381 <= FP_ARG_V4_MAX_REG
)
9382 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9385 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9386 if (mode
== DFmode
|| mode
== TFmode
9387 || mode
== DDmode
|| mode
== TDmode
)
9388 cum
->words
+= cum
->words
& 1;
9389 cum
->words
+= rs6000_arg_size (mode
, type
);
9394 int n_words
= rs6000_arg_size (mode
, type
);
9395 int gregno
= cum
->sysv_gregno
;
9397 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9398 (r7,r8) or (r9,r10). As does any other 2 word item such
9399 as complex int due to a historical mistake. */
9401 gregno
+= (1 - gregno
) & 1;
9403 /* Multi-reg args are not split between registers and stack. */
9404 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9406 /* Long long and SPE vectors are aligned on the stack.
9407 So are other 2 word items such as complex int due to
9408 a historical mistake. */
9410 cum
->words
+= cum
->words
& 1;
9411 cum
->words
+= n_words
;
9414 /* Note: continuing to accumulate gregno past when we've started
9415 spilling to the stack indicates the fact that we've started
9416 spilling to the stack to expand_builtin_saveregs. */
9417 cum
->sysv_gregno
= gregno
+ n_words
;
9420 if (TARGET_DEBUG_ARG
)
9422 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9423 cum
->words
, cum
->fregno
);
9424 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9425 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9426 fprintf (stderr
, "mode = %4s, named = %d\n",
9427 GET_MODE_NAME (mode
), named
);
9432 int n_words
= rs6000_arg_size (mode
, type
);
9433 int start_words
= cum
->words
;
9434 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9436 cum
->words
= align_words
+ n_words
;
9438 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9439 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9441 /* _Decimal128 must be passed in an even/odd float register pair.
9442 This assumes that the register number is odd when fregno is
9444 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9446 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9449 if (TARGET_DEBUG_ARG
)
9451 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9452 cum
->words
, cum
->fregno
);
9453 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9454 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9455 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9456 named
, align_words
- start_words
, depth
);
9462 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9463 const_tree type
, bool named
)
9465 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9470 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9477 r1
= gen_rtx_REG (DImode
, gregno
);
9478 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9479 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9483 r1
= gen_rtx_REG (DImode
, gregno
);
9484 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9485 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9486 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9487 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9490 r1
= gen_rtx_REG (DImode
, gregno
);
9491 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9492 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9493 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9494 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9495 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9496 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9497 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9498 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9505 /* Determine where to put a SIMD argument on the SPE. */
9507 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9510 int gregno
= cum
->sysv_gregno
;
9512 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9513 are passed and returned in a pair of GPRs for ABI compatibility. */
9514 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9515 || mode
== DCmode
|| mode
== TCmode
))
9517 int n_words
= rs6000_arg_size (mode
, type
);
9519 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9521 gregno
+= (1 - gregno
) & 1;
9523 /* Multi-reg args are not split between registers and stack. */
9524 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9527 return spe_build_register_parallel (mode
, gregno
);
9531 int n_words
= rs6000_arg_size (mode
, type
);
9533 /* SPE vectors are put in odd registers. */
9534 if (n_words
== 2 && (gregno
& 1) == 0)
9537 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9540 enum machine_mode m
= SImode
;
9542 r1
= gen_rtx_REG (m
, gregno
);
9543 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9544 r2
= gen_rtx_REG (m
, gregno
+ 1);
9545 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9546 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9553 if (gregno
<= GP_ARG_MAX_REG
)
9554 return gen_rtx_REG (mode
, gregno
);
9560 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9561 structure between cum->intoffset and bitpos to integer registers. */
9564 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9565 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9567 enum machine_mode mode
;
9569 unsigned int startbit
, endbit
;
9570 int this_regno
, intregs
, intoffset
;
9573 if (cum
->intoffset
== -1)
9576 intoffset
= cum
->intoffset
;
9577 cum
->intoffset
= -1;
9579 /* If this is the trailing part of a word, try to only load that
9580 much into the register. Otherwise load the whole register. Note
9581 that in the latter case we may pick up unwanted bits. It's not a
9582 problem at the moment but may wish to revisit. */
9584 if (intoffset
% BITS_PER_WORD
!= 0)
9586 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9588 if (mode
== BLKmode
)
9590 /* We couldn't find an appropriate mode, which happens,
9591 e.g., in packed structs when there are 3 bytes to load.
9592 Back intoffset back to the beginning of the word in this
9594 intoffset
= intoffset
& -BITS_PER_WORD
;
9601 startbit
= intoffset
& -BITS_PER_WORD
;
9602 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9603 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9604 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9606 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9609 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9613 intoffset
/= BITS_PER_UNIT
;
9616 regno
= GP_ARG_MIN_REG
+ this_regno
;
9617 reg
= gen_rtx_REG (mode
, regno
);
9619 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9622 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9626 while (intregs
> 0);
9629 /* Recursive workhorse for the following. */
9632 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9633 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9638 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9639 if (TREE_CODE (f
) == FIELD_DECL
)
9641 HOST_WIDE_INT bitpos
= startbitpos
;
9642 tree ftype
= TREE_TYPE (f
);
9643 enum machine_mode mode
;
9644 if (ftype
== error_mark_node
)
9646 mode
= TYPE_MODE (ftype
);
9648 if (DECL_SIZE (f
) != 0
9649 && host_integerp (bit_position (f
), 1))
9650 bitpos
+= int_bit_position (f
);
9652 /* ??? FIXME: else assume zero offset. */
9654 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9655 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9656 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
9658 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9662 case SCmode
: mode
= SFmode
; break;
9663 case DCmode
: mode
= DFmode
; break;
9664 case TCmode
: mode
= TFmode
; break;
9668 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9669 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9671 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9672 && (mode
== TFmode
|| mode
== TDmode
));
9673 /* Long double or _Decimal128 split over regs and memory. */
9674 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9678 = gen_rtx_EXPR_LIST (VOIDmode
,
9679 gen_rtx_REG (mode
, cum
->fregno
++),
9680 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9681 if (mode
== TFmode
|| mode
== TDmode
)
9684 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9686 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9688 = gen_rtx_EXPR_LIST (VOIDmode
,
9689 gen_rtx_REG (mode
, cum
->vregno
++),
9690 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9692 else if (cum
->intoffset
== -1)
9693 cum
->intoffset
= bitpos
;
9697 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9698 the register(s) to be used for each field and subfield of a struct
9699 being passed by value, along with the offset of where the
9700 register's value may be found in the block. FP fields go in FP
9701 register, vector fields go in vector registers, and everything
9702 else goes in int registers, packed as in memory.
9704 This code is also used for function return values. RETVAL indicates
9705 whether this is the case.
9707 Much of this is taken from the SPARC V9 port, which has a similar
9708 calling convention. */
9711 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9712 bool named
, bool retval
)
9714 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9715 int k
= 1, kbase
= 1;
9716 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
9717 /* This is a copy; modifications are not visible to our caller. */
9718 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9719 CUMULATIVE_ARGS
*cum
= ©_cum
;
9721 /* Pad to 16 byte boundary if needed. */
9722 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9723 && (cum
->words
% 2) != 0)
9730 /* Put entries into rvec[] for individual FP and vector fields, and
9731 for the chunks of memory that go in int regs. Note we start at
9732 element 1; 0 is reserved for an indication of using memory, and
9733 may or may not be filled in below. */
9734 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9735 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9737 /* If any part of the struct went on the stack put all of it there.
9738 This hack is because the generic code for
9739 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9740 parts of the struct are not at the beginning. */
9744 return NULL_RTX
; /* doesn't go in registers at all */
9746 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9748 if (k
> 1 || cum
->use_stack
)
9749 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9754 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9757 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9762 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9764 if (align_words
>= GP_ARG_NUM_REG
)
9767 n_units
= rs6000_arg_size (mode
, type
);
9769 /* Optimize the simple case where the arg fits in one gpr, except in
9770 the case of BLKmode due to assign_parms assuming that registers are
9771 BITS_PER_WORD wide. */
9773 || (n_units
== 1 && mode
!= BLKmode
))
9774 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9777 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9778 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9779 using a magic NULL_RTX component.
9780 This is not strictly correct. Only some of the arg belongs in
9781 memory, not all of it. However, the normal scheme using
9782 function_arg_partial_nregs can result in unusual subregs, eg.
9783 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9784 store the whole arg to memory is often more efficient than code
9785 to store pieces, and we know that space is available in the right
9786 place for the whole arg. */
9787 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9792 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9793 rtx off
= GEN_INT (i
++ * 4);
9794 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9796 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9798 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9801 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
9802 but must also be copied into the parameter save area starting at
9803 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
9804 to the GPRs and/or memory. Return the number of elements used. */
9807 rs6000_psave_function_arg (enum machine_mode mode
, const_tree type
,
9808 int align_words
, rtx
*rvec
)
9812 if (align_words
< GP_ARG_NUM_REG
)
9814 int n_words
= rs6000_arg_size (mode
, type
);
9816 if (align_words
+ n_words
> GP_ARG_NUM_REG
9818 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9820 /* If this is partially on the stack, then we only
9821 include the portion actually in registers here. */
9822 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9825 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9827 /* Not all of the arg fits in gprs. Say that it goes in memory
9828 too, using a magic NULL_RTX component. Also see comment in
9829 rs6000_mixed_function_arg for why the normal
9830 function_arg_partial_nregs scheme doesn't work in this case. */
9831 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9836 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
9837 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9838 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9840 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9844 /* The whole arg fits in gprs. */
9845 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9846 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9851 /* It's entirely in memory. */
9852 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9858 /* RVEC is a vector of K components of an argument of mode MODE.
9859 Construct the final function_arg return value from it. */
9862 rs6000_finish_function_arg (enum machine_mode mode
, rtx
*rvec
, int k
)
9864 gcc_assert (k
>= 1);
9866 /* Avoid returning a PARALLEL in the trivial cases. */
9869 if (XEXP (rvec
[0], 0) == NULL_RTX
)
9872 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
9873 return XEXP (rvec
[0], 0);
9876 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9879 /* Determine where to put an argument to a function.
9880 Value is zero to push the argument on the stack,
9881 or a hard register in which to store the argument.
9883 MODE is the argument's machine mode.
9884 TYPE is the data type of the argument (as a tree).
9885 This is null for libcalls where that information may
9887 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9888 the preceding args and about the function being called. It is
9889 not modified in this routine.
9890 NAMED is nonzero if this argument is a named parameter
9891 (otherwise it is an extra parameter matching an ellipsis).
9893 On RS/6000 the first eight words of non-FP are normally in registers
9894 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
9895 Under V.4, the first 8 FP args are in registers.
9897 If this is floating-point and no prototype is specified, we use
9898 both an FP and integer register (or possibly FP reg and stack). Library
9899 functions (when CALL_LIBCALL is set) always have the proper types for args,
9900 so we can pass the FP value just in one register. emit_library_function
9901 doesn't support PARALLEL anyway.
9903 Note that for args passed by reference, function_arg will be called
9904 with MODE and TYPE set to that of the pointer to the arg, not the arg
9908 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
9909 const_tree type
, bool named
)
9911 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9912 enum rs6000_abi abi
= DEFAULT_ABI
;
9913 enum machine_mode elt_mode
;
9916 /* Return a marker to indicate whether CR1 needs to set or clear the
9917 bit that V.4 uses to say fp args were passed in registers.
9918 Assume that we don't need the marker for software floating point,
9919 or compiler generated library calls. */
9920 if (mode
== VOIDmode
)
9923 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
9925 || (cum
->nargs_prototype
< 0
9926 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
9928 /* For the SPE, we need to crxor CR6 always. */
9930 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
9931 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9932 return GEN_INT (cum
->call_cookie
9933 | ((cum
->fregno
== FP_ARG_MIN_REG
)
9934 ? CALL_V4_SET_FP_ARGS
9935 : CALL_V4_CLEAR_FP_ARGS
));
9938 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
9941 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9943 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9945 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
9946 if (rslt
!= NULL_RTX
)
9948 /* Else fall through to usual handling. */
9951 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9953 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
9957 /* Do we also need to pass this argument in the parameter
9959 if (TARGET_64BIT
&& ! cum
->prototype
)
9961 int align_words
= (cum
->words
+ 1) & ~1;
9962 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
9965 /* Describe where this argument goes in the vector registers. */
9966 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
9968 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
9969 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
9970 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9973 return rs6000_finish_function_arg (mode
, rvec
, k
);
9975 else if (TARGET_ALTIVEC_ABI
9976 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
9977 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9978 && int_size_in_bytes (type
) == 16)))
9980 if (named
|| abi
== ABI_V4
)
9984 /* Vector parameters to varargs functions under AIX or Darwin
9985 get passed in memory and possibly also in GPRs. */
9986 int align
, align_words
, n_words
;
9987 enum machine_mode part_mode
;
9989 /* Vector parameters must be 16-byte aligned. In 32-bit
9990 mode this means we need to take into account the offset
9991 to the parameter save area. In 64-bit mode, they just
9992 have to start on an even word, since the parameter save
9993 area is 16-byte aligned. */
9995 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9997 align
= cum
->words
& 1;
9998 align_words
= cum
->words
+ align
;
10000 /* Out of registers? Memory, then. */
10001 if (align_words
>= GP_ARG_NUM_REG
)
10004 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10005 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10007 /* The vector value goes in GPRs. Only the part of the
10008 value in GPRs is reported here. */
10010 n_words
= rs6000_arg_size (mode
, type
);
10011 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10012 /* Fortunately, there are only two possibilities, the value
10013 is either wholly in GPRs or half in GPRs and half not. */
10014 part_mode
= DImode
;
10016 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10019 else if (TARGET_SPE_ABI
&& TARGET_SPE
10020 && (SPE_VECTOR_MODE (mode
)
10021 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10024 || mode
== TCmode
))))
10025 return rs6000_spe_function_arg (cum
, mode
, type
);
10027 else if (abi
== ABI_V4
)
10029 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10030 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10031 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10032 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10033 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10035 /* _Decimal128 must use an even/odd register pair. This assumes
10036 that the register number is odd when fregno is odd. */
10037 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10040 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10041 <= FP_ARG_V4_MAX_REG
)
10042 return gen_rtx_REG (mode
, cum
->fregno
);
10048 int n_words
= rs6000_arg_size (mode
, type
);
10049 int gregno
= cum
->sysv_gregno
;
10051 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10052 (r7,r8) or (r9,r10). As does any other 2 word item such
10053 as complex int due to a historical mistake. */
10055 gregno
+= (1 - gregno
) & 1;
10057 /* Multi-reg args are not split between registers and stack. */
10058 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10061 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10062 return rs6000_mixed_function_arg (mode
, type
,
10063 gregno
- GP_ARG_MIN_REG
);
10064 return gen_rtx_REG (mode
, gregno
);
10069 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10071 /* _Decimal128 must be passed in an even/odd float register pair.
10072 This assumes that the register number is odd when fregno is odd. */
10073 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10076 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10078 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10081 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10083 /* Do we also need to pass this argument in the parameter
10085 if (type
&& (cum
->nargs_prototype
<= 0
10086 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10087 && TARGET_XL_COMPAT
10088 && align_words
>= GP_ARG_NUM_REG
)))
10089 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10091 /* Describe where this argument goes in the fprs. */
10092 for (i
= 0; i
< n_elts
10093 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10095 /* Check if the argument is split over registers and memory.
10096 This can only ever happen for long double or _Decimal128;
10097 complex types are handled via split_complex_arg. */
10098 enum machine_mode fmode
= elt_mode
;
10099 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10101 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10102 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10105 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10106 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10107 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10110 return rs6000_finish_function_arg (mode
, rvec
, k
);
10112 else if (align_words
< GP_ARG_NUM_REG
)
10114 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10115 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10117 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10124 /* For an arg passed partly in registers and partly in memory, this is
10125 the number of bytes passed in registers. For args passed entirely in
10126 registers or entirely in memory, zero. When an arg is described by a
10127 PARALLEL, perhaps using more than one register type, this function
10128 returns the number of bytes used by the first element of the PARALLEL. */
10131 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
10132 tree type
, bool named
)
10134 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10135 bool passed_in_gprs
= true;
10138 enum machine_mode elt_mode
;
10141 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10143 if (DEFAULT_ABI
== ABI_V4
)
10146 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10148 /* If we are passing this arg in the fixed parameter save area
10149 (gprs or memory) as well as VRs, we do not use the partial
10150 bytes mechanism; instead, rs6000_function_arg will return a
10151 PARALLEL including a memory element as necessary. */
10152 if (TARGET_64BIT
&& ! cum
->prototype
)
10155 /* Otherwise, we pass in VRs only. Check for partial copies. */
10156 passed_in_gprs
= false;
10157 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10158 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10161 /* In this complicated case we just disable the partial_nregs code. */
10162 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10165 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10167 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10169 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10171 /* If we are passing this arg in the fixed parameter save area
10172 (gprs or memory) as well as FPRs, we do not use the partial
10173 bytes mechanism; instead, rs6000_function_arg will return a
10174 PARALLEL including a memory element as necessary. */
10176 && (cum
->nargs_prototype
<= 0
10177 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10178 && TARGET_XL_COMPAT
10179 && align_words
>= GP_ARG_NUM_REG
)))
10182 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10183 passed_in_gprs
= false;
10184 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10185 ret
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10186 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10190 && align_words
< GP_ARG_NUM_REG
10191 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10192 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10194 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10195 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10200 /* A C expression that indicates when an argument must be passed by
10201 reference. If nonzero for an argument, a copy of that argument is
10202 made in memory and a pointer to the argument is passed instead of
10203 the argument itself. The pointer is passed in whatever way is
10204 appropriate for passing a pointer to that type.
10206 Under V.4, aggregates and long double are passed by reference.
10208 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10209 reference unless the AltiVec vector extension ABI is in force.
10211 As an extension to all ABIs, variable sized types are passed by
10215 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10216 enum machine_mode mode
, const_tree type
,
10217 bool named ATTRIBUTE_UNUSED
)
10219 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10221 if (TARGET_DEBUG_ARG
)
10222 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10229 #if HAVE_UPC_PTS_STRUCT_REP
10230 if (DEFAULT_ABI
== ABI_V4
&& POINTER_TYPE_P (type
)
10231 && upc_shared_type_p (TREE_TYPE (type
)))
10233 if (TARGET_DEBUG_ARG
)
10235 "function_arg_pass_by_reference: V4 UPC ptr to shared\n");
10240 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10242 if (TARGET_DEBUG_ARG
)
10243 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10247 if (int_size_in_bytes (type
) < 0)
10249 if (TARGET_DEBUG_ARG
)
10250 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10254 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10255 modes only exist for GCC vector types if -maltivec. */
10256 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10258 if (TARGET_DEBUG_ARG
)
10259 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10263 /* Pass synthetic vectors in memory. */
10264 if (TREE_CODE (type
) == VECTOR_TYPE
10265 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10267 static bool warned_for_pass_big_vectors
= false;
10268 if (TARGET_DEBUG_ARG
)
10269 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10270 if (!warned_for_pass_big_vectors
)
10272 warning (0, "GCC vector passed by reference: "
10273 "non-standard ABI extension with no compatibility guarantee");
10274 warned_for_pass_big_vectors
= true;
10282 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10283 already processes. Return true if the parameter must be passed
10284 (fully or partially) on the stack. */
10287 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10289 enum machine_mode mode
;
10293 /* Catch errors. */
10294 if (type
== NULL
|| type
== error_mark_node
)
10297 /* Handle types with no storage requirement. */
10298 if (TYPE_MODE (type
) == VOIDmode
)
10301 /* Handle complex types. */
10302 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10303 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10304 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10306 /* Handle transparent aggregates. */
10307 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10308 && TYPE_TRANSPARENT_AGGR (type
))
10309 type
= TREE_TYPE (first_field (type
));
10311 /* See if this arg was passed by invisible reference. */
10312 if (pass_by_reference (get_cumulative_args (args_so_far
),
10313 TYPE_MODE (type
), type
, true))
10314 type
= build_pointer_type (type
);
10316 /* Find mode as it is passed by the ABI. */
10317 unsignedp
= TYPE_UNSIGNED (type
);
10318 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10320 /* If we must pass in stack, we need a stack. */
10321 if (rs6000_must_pass_in_stack (mode
, type
))
10324 /* If there is no incoming register, we need a stack. */
10325 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10326 if (entry_parm
== NULL
)
10329 /* Likewise if we need to pass both in registers and on the stack. */
10330 if (GET_CODE (entry_parm
) == PARALLEL
10331 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10334 /* Also true if we're partially in registers and partially not. */
10335 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10338 /* Update info on where next arg arrives in registers. */
10339 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10343 /* Return true if FUN has no prototype, has a variable argument
10344 list, or passes any parameter in memory. */
10347 rs6000_function_parms_need_stack (tree fun
)
10349 function_args_iterator args_iter
;
10351 CUMULATIVE_ARGS args_so_far_v
;
10352 cumulative_args_t args_so_far
;
10355 /* Must be a libcall, all of which only use reg parms. */
10358 fun
= TREE_TYPE (fun
);
10360 /* Varargs functions need the parameter save area. */
10361 if (!prototype_p (fun
) || stdarg_p (fun
))
10364 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fun
, NULL_RTX
);
10365 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10367 if (aggregate_value_p (TREE_TYPE (fun
), fun
))
10369 tree type
= build_pointer_type (TREE_TYPE (fun
));
10370 rs6000_parm_needs_stack (args_so_far
, type
);
10373 FOREACH_FUNCTION_ARGS (fun
, arg_type
, args_iter
)
10374 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10380 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10381 usually a constant depending on the ABI. However, in the ELFv2 ABI
10382 the register parameter area is optional when calling a function that
10383 has a prototype is scope, has no variable argument list, and passes
10384 all parameters in registers. */
10387 rs6000_reg_parm_stack_space (tree fun
)
10389 int reg_parm_stack_space
;
10391 switch (DEFAULT_ABI
)
10394 reg_parm_stack_space
= 0;
10399 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10403 /* ??? Recomputing this every time is a bit expensive. Is there
10404 a place to cache this information? */
10405 if (rs6000_function_parms_need_stack (fun
))
10406 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10408 reg_parm_stack_space
= 0;
10412 return reg_parm_stack_space
;
10416 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
10419 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
10424 for (i
= 0; i
< nregs
; i
++)
10426 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
10427 if (reload_completed
)
10429 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
10432 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
10433 i
* GET_MODE_SIZE (reg_mode
));
10436 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
10440 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
10444 /* Perform any needed actions needed for a function that is receiving a
10445 variable number of arguments.
10449 MODE and TYPE are the mode and type of the current parameter.
10451 PRETEND_SIZE is a variable that should be set to the amount of stack
10452 that must be pushed by the prolog to pretend that our caller pushed
10455 Normally, this macro will push all remaining incoming registers on the
10456 stack and set PRETEND_SIZE to the length of the registers pushed. */
10459 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
10460 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
10463 CUMULATIVE_ARGS next_cum
;
10464 int reg_size
= TARGET_32BIT
? 4 : 8;
10465 rtx save_area
= NULL_RTX
, mem
;
10466 int first_reg_offset
;
10467 alias_set_type set
;
10469 /* Skip the last named argument. */
10470 next_cum
= *get_cumulative_args (cum
);
10471 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
10473 if (DEFAULT_ABI
== ABI_V4
)
10475 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10479 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10480 HOST_WIDE_INT offset
= 0;
10482 /* Try to optimize the size of the varargs save area.
10483 The ABI requires that ap.reg_save_area is doubleword
10484 aligned, but we don't need to allocate space for all
10485 the bytes, only those to which we actually will save
10487 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10488 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10489 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10490 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10491 && cfun
->va_list_fpr_size
)
10494 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10495 * UNITS_PER_FP_WORD
;
10496 if (cfun
->va_list_fpr_size
10497 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10498 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10500 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10501 * UNITS_PER_FP_WORD
;
10505 offset
= -((first_reg_offset
* reg_size
) & ~7);
10506 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10508 gpr_reg_num
= cfun
->va_list_gpr_size
;
10509 if (reg_size
== 4 && (first_reg_offset
& 1))
10512 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10515 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10516 * UNITS_PER_FP_WORD
10517 - (int) (GP_ARG_NUM_REG
* reg_size
);
10519 if (gpr_size
+ fpr_size
)
10522 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10523 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10524 reg_save_area
= XEXP (reg_save_area
, 0);
10525 if (GET_CODE (reg_save_area
) == PLUS
)
10527 gcc_assert (XEXP (reg_save_area
, 0)
10528 == virtual_stack_vars_rtx
);
10529 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10530 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10533 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10536 cfun
->machine
->varargs_save_offset
= offset
;
10537 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10542 first_reg_offset
= next_cum
.words
;
10543 save_area
= virtual_incoming_args_rtx
;
10545 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10546 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10549 set
= get_varargs_alias_set ();
10550 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10551 && cfun
->va_list_gpr_size
)
10553 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10555 if (va_list_gpr_counter_field
)
10556 /* V4 va_list_gpr_size counts number of registers needed. */
10557 n_gpr
= cfun
->va_list_gpr_size
;
10559 /* char * va_list instead counts number of bytes needed. */
10560 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10565 mem
= gen_rtx_MEM (BLKmode
,
10566 plus_constant (Pmode
, save_area
,
10567 first_reg_offset
* reg_size
));
10568 MEM_NOTRAP_P (mem
) = 1;
10569 set_mem_alias_set (mem
, set
);
10570 set_mem_align (mem
, BITS_PER_WORD
);
10572 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10576 /* Save FP registers if needed. */
10577 if (DEFAULT_ABI
== ABI_V4
10578 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10580 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10581 && cfun
->va_list_fpr_size
)
10583 int fregno
= next_cum
.fregno
, nregs
;
10584 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10585 rtx lab
= gen_label_rtx ();
10586 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10587 * UNITS_PER_FP_WORD
);
10590 (gen_rtx_SET (VOIDmode
,
10592 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10593 gen_rtx_NE (VOIDmode
, cr1
,
10595 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10599 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10600 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10602 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10604 plus_constant (Pmode
, save_area
, off
));
10605 MEM_NOTRAP_P (mem
) = 1;
10606 set_mem_alias_set (mem
, set
);
10607 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10608 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10609 ? DFmode
: SFmode
));
10610 emit_move_insn (mem
, gen_rtx_REG (
10611 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10612 ? DFmode
: SFmode
, fregno
));
10619 /* Create the va_list data type. */
10622 rs6000_build_builtin_va_list (void)
10624 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10626 /* For AIX, prefer 'char *' because that's what the system
10627 header files like. */
10628 if (DEFAULT_ABI
!= ABI_V4
)
10629 return build_pointer_type (char_type_node
);
10631 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10632 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10633 get_identifier ("__va_list_tag"), record
);
10635 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10636 unsigned_char_type_node
);
10637 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10638 unsigned_char_type_node
);
10639 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10640 every user file. */
10641 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10642 get_identifier ("reserved"), short_unsigned_type_node
);
10643 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10644 get_identifier ("overflow_arg_area"),
10646 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10647 get_identifier ("reg_save_area"),
10650 va_list_gpr_counter_field
= f_gpr
;
10651 va_list_fpr_counter_field
= f_fpr
;
10653 DECL_FIELD_CONTEXT (f_gpr
) = record
;
10654 DECL_FIELD_CONTEXT (f_fpr
) = record
;
10655 DECL_FIELD_CONTEXT (f_res
) = record
;
10656 DECL_FIELD_CONTEXT (f_ovf
) = record
;
10657 DECL_FIELD_CONTEXT (f_sav
) = record
;
10659 TYPE_STUB_DECL (record
) = type_decl
;
10660 TYPE_NAME (record
) = type_decl
;
10661 TYPE_FIELDS (record
) = f_gpr
;
10662 DECL_CHAIN (f_gpr
) = f_fpr
;
10663 DECL_CHAIN (f_fpr
) = f_res
;
10664 DECL_CHAIN (f_res
) = f_ovf
;
10665 DECL_CHAIN (f_ovf
) = f_sav
;
10667 layout_type (record
);
10669 /* The correct type is an array type of one element. */
10670 return build_array_type (record
, build_index_type (size_zero_node
));
10673 /* Implement va_start. */
10676 rs6000_va_start (tree valist
, rtx nextarg
)
10678 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
10679 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10680 tree gpr
, fpr
, ovf
, sav
, t
;
10682 /* Only SVR4 needs something special. */
10683 if (DEFAULT_ABI
!= ABI_V4
)
10685 std_expand_builtin_va_start (valist
, nextarg
);
10689 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10690 f_fpr
= DECL_CHAIN (f_gpr
);
10691 f_res
= DECL_CHAIN (f_fpr
);
10692 f_ovf
= DECL_CHAIN (f_res
);
10693 f_sav
= DECL_CHAIN (f_ovf
);
10695 valist
= build_simple_mem_ref (valist
);
10696 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10697 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10699 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10701 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10704 /* Count number of gp and fp argument registers used. */
10705 words
= crtl
->args
.info
.words
;
10706 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
10708 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
10711 if (TARGET_DEBUG_ARG
)
10712 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
10713 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
10714 words
, n_gpr
, n_fpr
);
10716 if (cfun
->va_list_gpr_size
)
10718 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
10719 build_int_cst (NULL_TREE
, n_gpr
));
10720 TREE_SIDE_EFFECTS (t
) = 1;
10721 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10724 if (cfun
->va_list_fpr_size
)
10726 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
10727 build_int_cst (NULL_TREE
, n_fpr
));
10728 TREE_SIDE_EFFECTS (t
) = 1;
10729 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10731 #ifdef HAVE_AS_GNU_ATTRIBUTE
10732 if (call_ABI_of_interest (cfun
->decl
))
10733 rs6000_passes_float
= true;
10737 /* Find the overflow area. */
10738 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
10740 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
10741 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
10742 TREE_SIDE_EFFECTS (t
) = 1;
10743 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10745 /* If there were no va_arg invocations, don't set up the register
10747 if (!cfun
->va_list_gpr_size
10748 && !cfun
->va_list_fpr_size
10749 && n_gpr
< GP_ARG_NUM_REG
10750 && n_fpr
< FP_ARG_V4_MAX_REG
)
10753 /* Find the register save area. */
10754 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
10755 if (cfun
->machine
->varargs_save_offset
)
10756 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
10757 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
10758 TREE_SIDE_EFFECTS (t
) = 1;
10759 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10762 /* Implement va_arg. */
10765 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
10766 gimple_seq
*post_p
)
10768 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10769 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
10770 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
10771 tree lab_false
, lab_over
, addr
;
10773 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
10777 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
10779 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
10780 return build_va_arg_indirect_ref (t
);
10783 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
10784 earlier version of gcc, with the property that it always applied alignment
10785 adjustments to the va-args (even for zero-sized types). The cheapest way
10786 to deal with this is to replicate the effect of the part of
10787 std_gimplify_va_arg_expr that carries out the align adjust, for the case
10789 We don't need to check for pass-by-reference because of the test above.
10790 We can return a simplifed answer, since we know there's no offset to add. */
10793 && rs6000_darwin64_abi
)
10794 || DEFAULT_ABI
== ABI_ELFv2
10795 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
10796 && integer_zerop (TYPE_SIZE (type
)))
10798 unsigned HOST_WIDE_INT align
, boundary
;
10799 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
10800 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
10801 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
10802 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
10803 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
10804 boundary
/= BITS_PER_UNIT
;
10805 if (boundary
> align
)
10808 /* This updates arg ptr by the amount that would be necessary
10809 to align the zero-sized (but not zero-alignment) item. */
10810 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10811 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
10812 gimplify_and_add (t
, pre_p
);
10814 t
= fold_convert (sizetype
, valist_tmp
);
10815 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10816 fold_convert (TREE_TYPE (valist
),
10817 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
10818 size_int (-boundary
))));
10819 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
10820 gimplify_and_add (t
, pre_p
);
10822 /* Since it is zero-sized there's no increment for the item itself. */
10823 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
10824 return build_va_arg_indirect_ref (valist_tmp
);
10827 if (DEFAULT_ABI
!= ABI_V4
)
10829 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
10831 tree elem_type
= TREE_TYPE (type
);
10832 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
10833 int elem_size
= GET_MODE_SIZE (elem_mode
);
10835 if (elem_size
< UNITS_PER_WORD
)
10837 tree real_part
, imag_part
;
10838 gimple_seq post
= NULL
;
10840 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10842 /* Copy the value into a temporary, lest the formal temporary
10843 be reused out from under us. */
10844 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
10845 gimple_seq_add_seq (pre_p
, post
);
10847 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10850 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
10854 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
10857 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10858 f_fpr
= DECL_CHAIN (f_gpr
);
10859 f_res
= DECL_CHAIN (f_fpr
);
10860 f_ovf
= DECL_CHAIN (f_res
);
10861 f_sav
= DECL_CHAIN (f_ovf
);
10863 valist
= build_va_arg_indirect_ref (valist
);
10864 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10865 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10867 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10869 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10872 size
= int_size_in_bytes (type
);
10873 rsize
= (size
+ 3) / 4;
10876 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10877 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
10878 || (TARGET_DOUBLE_FLOAT
10879 && (TYPE_MODE (type
) == DFmode
10880 || TYPE_MODE (type
) == TFmode
10881 || TYPE_MODE (type
) == SDmode
10882 || TYPE_MODE (type
) == DDmode
10883 || TYPE_MODE (type
) == TDmode
))))
10885 /* FP args go in FP registers, if present. */
10887 n_reg
= (size
+ 7) / 8;
10888 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
10889 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
10890 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
10895 /* Otherwise into GP registers. */
10904 /* Pull the value out of the saved registers.... */
10907 addr
= create_tmp_var (ptr_type_node
, "addr");
10909 /* AltiVec vectors never go in registers when -mabi=altivec. */
10910 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10914 lab_false
= create_artificial_label (input_location
);
10915 lab_over
= create_artificial_label (input_location
);
10917 /* Long long and SPE vectors are aligned in the registers.
10918 As are any other 2 gpr item such as complex int due to a
10919 historical mistake. */
10921 if (n_reg
== 2 && reg
== gpr
)
10924 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10925 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
10926 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
10927 unshare_expr (reg
), u
);
10929 /* _Decimal128 is passed in even/odd fpr pairs; the stored
10930 reg number is 0 for f1, so we want to make it odd. */
10931 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
10933 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10934 build_int_cst (TREE_TYPE (reg
), 1));
10935 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
10938 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
10939 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
10940 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
10941 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
10942 gimplify_and_add (t
, pre_p
);
10946 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
10948 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10949 build_int_cst (TREE_TYPE (reg
), n_reg
));
10950 u
= fold_convert (sizetype
, u
);
10951 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
10952 t
= fold_build_pointer_plus (t
, u
);
10954 /* _Decimal32 varargs are located in the second word of the 64-bit
10955 FP register for 32-bit binaries. */
10956 if (!TARGET_POWERPC64
10957 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10958 && TYPE_MODE (type
) == SDmode
)
10959 t
= fold_build_pointer_plus_hwi (t
, size
);
10961 gimplify_assign (addr
, t
, pre_p
);
10963 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
10965 stmt
= gimple_build_label (lab_false
);
10966 gimple_seq_add_stmt (pre_p
, stmt
);
10968 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
10970 /* Ensure that we don't find any more args in regs.
10971 Alignment has taken care of for special cases. */
10972 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
10976 /* ... otherwise out of the overflow area. */
10978 /* Care for on-stack alignment if needed. */
10982 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
10983 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
10984 build_int_cst (TREE_TYPE (t
), -align
));
10986 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
10988 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
10990 t
= fold_build_pointer_plus_hwi (t
, size
);
10991 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
10995 stmt
= gimple_build_label (lab_over
);
10996 gimple_seq_add_stmt (pre_p
, stmt
);
10999 if (STRICT_ALIGNMENT
11000 && (TYPE_ALIGN (type
)
11001 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11003 /* The value (of type complex double, for example) may not be
11004 aligned in memory in the saved registers, so copy via a
11005 temporary. (This is the same code as used for SPARC.) */
11006 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11007 tree dest_addr
= build_fold_addr_expr (tmp
);
11009 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11010 3, dest_addr
, addr
, size_int (rsize
* 4));
11012 gimplify_and_add (copy
, pre_p
);
11016 addr
= fold_convert (ptrtype
, addr
);
11017 return build_va_arg_indirect_ref (addr
);
11023 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11026 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11027 const char *attr_string
= "";
11029 gcc_assert (name
!= NULL
);
11030 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11032 if (rs6000_builtin_decls
[(int)code
])
11033 fatal_error ("internal error: builtin function %s already processed", name
);
11035 rs6000_builtin_decls
[(int)code
] = t
=
11036 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11038 /* Set any special attributes. */
11039 if ((classify
& RS6000_BTC_CONST
) != 0)
11041 /* const function, function only depends on the inputs. */
11042 TREE_READONLY (t
) = 1;
11043 TREE_NOTHROW (t
) = 1;
11044 attr_string
= ", pure";
11046 else if ((classify
& RS6000_BTC_PURE
) != 0)
11048 /* pure function, function can read global memory, but does not set any
11050 DECL_PURE_P (t
) = 1;
11051 TREE_NOTHROW (t
) = 1;
11052 attr_string
= ", const";
11054 else if ((classify
& RS6000_BTC_FP
) != 0)
11056 /* Function is a math function. If rounding mode is on, then treat the
11057 function as not reading global memory, but it can have arbitrary side
11058 effects. If it is off, then assume the function is a const function.
11059 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11060 builtin-attribute.def that is used for the math functions. */
11061 TREE_NOTHROW (t
) = 1;
11062 if (flag_rounding_math
)
11064 DECL_PURE_P (t
) = 1;
11065 DECL_IS_NOVOPS (t
) = 1;
11066 attr_string
= ", fp, pure";
11070 TREE_READONLY (t
) = 1;
11071 attr_string
= ", fp, const";
11074 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11075 gcc_unreachable ();
11077 if (TARGET_DEBUG_BUILTIN
)
11078 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11079 (int)code
, name
, attr_string
);
11082 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11084 #undef RS6000_BUILTIN_1
11085 #undef RS6000_BUILTIN_2
11086 #undef RS6000_BUILTIN_3
11087 #undef RS6000_BUILTIN_A
11088 #undef RS6000_BUILTIN_D
11089 #undef RS6000_BUILTIN_E
11090 #undef RS6000_BUILTIN_H
11091 #undef RS6000_BUILTIN_P
11092 #undef RS6000_BUILTIN_Q
11093 #undef RS6000_BUILTIN_S
11094 #undef RS6000_BUILTIN_X
11096 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11097 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11098 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11099 { MASK, ICODE, NAME, ENUM },
11101 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11102 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11103 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11104 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11105 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11106 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11107 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11108 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11110 static const struct builtin_description bdesc_3arg
[] =
11112 #include "rs6000-builtin.def"
11115 /* DST operations: void foo (void *, const int, const char). */
11117 #undef RS6000_BUILTIN_1
11118 #undef RS6000_BUILTIN_2
11119 #undef RS6000_BUILTIN_3
11120 #undef RS6000_BUILTIN_A
11121 #undef RS6000_BUILTIN_D
11122 #undef RS6000_BUILTIN_E
11123 #undef RS6000_BUILTIN_H
11124 #undef RS6000_BUILTIN_P
11125 #undef RS6000_BUILTIN_Q
11126 #undef RS6000_BUILTIN_S
11127 #undef RS6000_BUILTIN_X
11129 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11130 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11131 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11132 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11133 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11134 { MASK, ICODE, NAME, ENUM },
11136 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11137 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11138 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11139 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11140 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11141 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11143 static const struct builtin_description bdesc_dst
[] =
11145 #include "rs6000-builtin.def"
11148 /* Simple binary operations: VECc = foo (VECa, VECb). */
11150 #undef RS6000_BUILTIN_1
11151 #undef RS6000_BUILTIN_2
11152 #undef RS6000_BUILTIN_3
11153 #undef RS6000_BUILTIN_A
11154 #undef RS6000_BUILTIN_D
11155 #undef RS6000_BUILTIN_E
11156 #undef RS6000_BUILTIN_H
11157 #undef RS6000_BUILTIN_P
11158 #undef RS6000_BUILTIN_Q
11159 #undef RS6000_BUILTIN_S
11160 #undef RS6000_BUILTIN_X
11162 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11163 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11164 { MASK, ICODE, NAME, ENUM },
11166 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11167 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11168 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11169 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11170 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11171 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11172 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11173 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11174 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11176 static const struct builtin_description bdesc_2arg
[] =
11178 #include "rs6000-builtin.def"
11181 #undef RS6000_BUILTIN_1
11182 #undef RS6000_BUILTIN_2
11183 #undef RS6000_BUILTIN_3
11184 #undef RS6000_BUILTIN_A
11185 #undef RS6000_BUILTIN_D
11186 #undef RS6000_BUILTIN_E
11187 #undef RS6000_BUILTIN_H
11188 #undef RS6000_BUILTIN_P
11189 #undef RS6000_BUILTIN_Q
11190 #undef RS6000_BUILTIN_S
11191 #undef RS6000_BUILTIN_X
11193 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11194 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11195 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11196 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11197 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11198 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11199 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11200 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11201 { MASK, ICODE, NAME, ENUM },
11203 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11204 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11205 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11207 /* AltiVec predicates. */
11209 static const struct builtin_description bdesc_altivec_preds
[] =
11211 #include "rs6000-builtin.def"
11214 /* SPE predicates. */
11215 #undef RS6000_BUILTIN_1
11216 #undef RS6000_BUILTIN_2
11217 #undef RS6000_BUILTIN_3
11218 #undef RS6000_BUILTIN_A
11219 #undef RS6000_BUILTIN_D
11220 #undef RS6000_BUILTIN_E
11221 #undef RS6000_BUILTIN_H
11222 #undef RS6000_BUILTIN_P
11223 #undef RS6000_BUILTIN_Q
11224 #undef RS6000_BUILTIN_S
11225 #undef RS6000_BUILTIN_X
11227 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11228 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11229 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11230 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11231 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11232 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11233 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11234 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11235 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11236 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11237 { MASK, ICODE, NAME, ENUM },
11239 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11241 static const struct builtin_description bdesc_spe_predicates
[] =
11243 #include "rs6000-builtin.def"
11246 /* SPE evsel predicates. */
11247 #undef RS6000_BUILTIN_1
11248 #undef RS6000_BUILTIN_2
11249 #undef RS6000_BUILTIN_3
11250 #undef RS6000_BUILTIN_A
11251 #undef RS6000_BUILTIN_D
11252 #undef RS6000_BUILTIN_E
11253 #undef RS6000_BUILTIN_H
11254 #undef RS6000_BUILTIN_P
11255 #undef RS6000_BUILTIN_Q
11256 #undef RS6000_BUILTIN_S
11257 #undef RS6000_BUILTIN_X
11259 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11260 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11261 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11262 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11263 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11264 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11265 { MASK, ICODE, NAME, ENUM },
11267 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11268 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11269 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11270 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11271 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11273 static const struct builtin_description bdesc_spe_evsel
[] =
11275 #include "rs6000-builtin.def"
11278 /* PAIRED predicates. */
11279 #undef RS6000_BUILTIN_1
11280 #undef RS6000_BUILTIN_2
11281 #undef RS6000_BUILTIN_3
11282 #undef RS6000_BUILTIN_A
11283 #undef RS6000_BUILTIN_D
11284 #undef RS6000_BUILTIN_E
11285 #undef RS6000_BUILTIN_H
11286 #undef RS6000_BUILTIN_P
11287 #undef RS6000_BUILTIN_Q
11288 #undef RS6000_BUILTIN_S
11289 #undef RS6000_BUILTIN_X
11291 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11292 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11293 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11294 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11295 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11296 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11297 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11298 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11299 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11300 { MASK, ICODE, NAME, ENUM },
11302 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11303 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11305 static const struct builtin_description bdesc_paired_preds
[] =
11307 #include "rs6000-builtin.def"
11310 /* ABS* operations. */
11312 #undef RS6000_BUILTIN_1
11313 #undef RS6000_BUILTIN_2
11314 #undef RS6000_BUILTIN_3
11315 #undef RS6000_BUILTIN_A
11316 #undef RS6000_BUILTIN_D
11317 #undef RS6000_BUILTIN_E
11318 #undef RS6000_BUILTIN_H
11319 #undef RS6000_BUILTIN_P
11320 #undef RS6000_BUILTIN_Q
11321 #undef RS6000_BUILTIN_S
11322 #undef RS6000_BUILTIN_X
11324 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11325 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11326 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11327 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11328 { MASK, ICODE, NAME, ENUM },
11330 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11331 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11332 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11333 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11334 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11335 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11336 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11338 static const struct builtin_description bdesc_abs
[] =
11340 #include "rs6000-builtin.def"
11343 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11346 #undef RS6000_BUILTIN_1
11347 #undef RS6000_BUILTIN_2
11348 #undef RS6000_BUILTIN_3
11349 #undef RS6000_BUILTIN_A
11350 #undef RS6000_BUILTIN_D
11351 #undef RS6000_BUILTIN_E
11352 #undef RS6000_BUILTIN_H
11353 #undef RS6000_BUILTIN_P
11354 #undef RS6000_BUILTIN_Q
11355 #undef RS6000_BUILTIN_S
11356 #undef RS6000_BUILTIN_X
11358 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11359 { MASK, ICODE, NAME, ENUM },
11361 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11362 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11363 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11364 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11365 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11366 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11367 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11368 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11369 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11370 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11372 static const struct builtin_description bdesc_1arg
[] =
11374 #include "rs6000-builtin.def"
11377 /* HTM builtins. */
11378 #undef RS6000_BUILTIN_1
11379 #undef RS6000_BUILTIN_2
11380 #undef RS6000_BUILTIN_3
11381 #undef RS6000_BUILTIN_A
11382 #undef RS6000_BUILTIN_D
11383 #undef RS6000_BUILTIN_E
11384 #undef RS6000_BUILTIN_H
11385 #undef RS6000_BUILTIN_P
11386 #undef RS6000_BUILTIN_Q
11387 #undef RS6000_BUILTIN_S
11388 #undef RS6000_BUILTIN_X
11390 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11391 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11392 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11393 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11394 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11395 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11396 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11397 { MASK, ICODE, NAME, ENUM },
11399 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11400 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11401 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11402 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11404 static const struct builtin_description bdesc_htm
[] =
11406 #include "rs6000-builtin.def"
11409 #undef RS6000_BUILTIN_1
11410 #undef RS6000_BUILTIN_2
11411 #undef RS6000_BUILTIN_3
11412 #undef RS6000_BUILTIN_A
11413 #undef RS6000_BUILTIN_D
11414 #undef RS6000_BUILTIN_E
11415 #undef RS6000_BUILTIN_H
11416 #undef RS6000_BUILTIN_P
11417 #undef RS6000_BUILTIN_Q
11418 #undef RS6000_BUILTIN_S
11420 /* Return true if a builtin function is overloaded. */
11422 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
11424 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
11427 /* Expand an expression EXP that calls a builtin without arguments. */
11429 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
11432 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11434 if (icode
== CODE_FOR_nothing
)
11435 /* Builtin not supported on this processor. */
11439 || GET_MODE (target
) != tmode
11440 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11441 target
= gen_reg_rtx (tmode
);
11443 pat
= GEN_FCN (icode
) (target
);
11453 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11456 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11457 rtx op0
= expand_normal (arg0
);
11458 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11459 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11461 if (icode
== CODE_FOR_nothing
)
11462 /* Builtin not supported on this processor. */
11465 /* If we got invalid arguments bail out before generating bad rtl. */
11466 if (arg0
== error_mark_node
)
11469 if (icode
== CODE_FOR_altivec_vspltisb
11470 || icode
== CODE_FOR_altivec_vspltish
11471 || icode
== CODE_FOR_altivec_vspltisw
11472 || icode
== CODE_FOR_spe_evsplatfi
11473 || icode
== CODE_FOR_spe_evsplati
)
11475 /* Only allow 5-bit *signed* literals. */
11476 if (GET_CODE (op0
) != CONST_INT
11477 || INTVAL (op0
) > 15
11478 || INTVAL (op0
) < -16)
11480 error ("argument 1 must be a 5-bit signed literal");
11486 || GET_MODE (target
) != tmode
11487 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11488 target
= gen_reg_rtx (tmode
);
11490 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11491 op0
= copy_to_mode_reg (mode0
, op0
);
11493 pat
= GEN_FCN (icode
) (target
, op0
);
11502 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11504 rtx pat
, scratch1
, scratch2
;
11505 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11506 rtx op0
= expand_normal (arg0
);
11507 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11508 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11510 /* If we have invalid arguments, bail out before generating bad rtl. */
11511 if (arg0
== error_mark_node
)
11515 || GET_MODE (target
) != tmode
11516 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11517 target
= gen_reg_rtx (tmode
);
11519 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11520 op0
= copy_to_mode_reg (mode0
, op0
);
11522 scratch1
= gen_reg_rtx (mode0
);
11523 scratch2
= gen_reg_rtx (mode0
);
11525 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11534 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11537 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11538 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11539 rtx op0
= expand_normal (arg0
);
11540 rtx op1
= expand_normal (arg1
);
11541 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11542 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11543 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11545 if (icode
== CODE_FOR_nothing
)
11546 /* Builtin not supported on this processor. */
11549 /* If we got invalid arguments bail out before generating bad rtl. */
11550 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11553 if (icode
== CODE_FOR_altivec_vcfux
11554 || icode
== CODE_FOR_altivec_vcfsx
11555 || icode
== CODE_FOR_altivec_vctsxs
11556 || icode
== CODE_FOR_altivec_vctuxs
11557 || icode
== CODE_FOR_altivec_vspltb
11558 || icode
== CODE_FOR_altivec_vsplth
11559 || icode
== CODE_FOR_altivec_vspltw
11560 || icode
== CODE_FOR_spe_evaddiw
11561 || icode
== CODE_FOR_spe_evldd
11562 || icode
== CODE_FOR_spe_evldh
11563 || icode
== CODE_FOR_spe_evldw
11564 || icode
== CODE_FOR_spe_evlhhesplat
11565 || icode
== CODE_FOR_spe_evlhhossplat
11566 || icode
== CODE_FOR_spe_evlhhousplat
11567 || icode
== CODE_FOR_spe_evlwhe
11568 || icode
== CODE_FOR_spe_evlwhos
11569 || icode
== CODE_FOR_spe_evlwhou
11570 || icode
== CODE_FOR_spe_evlwhsplat
11571 || icode
== CODE_FOR_spe_evlwwsplat
11572 || icode
== CODE_FOR_spe_evrlwi
11573 || icode
== CODE_FOR_spe_evslwi
11574 || icode
== CODE_FOR_spe_evsrwis
11575 || icode
== CODE_FOR_spe_evsubifw
11576 || icode
== CODE_FOR_spe_evsrwiu
)
11578 /* Only allow 5-bit unsigned literals. */
11580 if (TREE_CODE (arg1
) != INTEGER_CST
11581 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11583 error ("argument 2 must be a 5-bit unsigned literal");
11589 || GET_MODE (target
) != tmode
11590 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11591 target
= gen_reg_rtx (tmode
);
11593 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11594 op0
= copy_to_mode_reg (mode0
, op0
);
11595 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11596 op1
= copy_to_mode_reg (mode1
, op1
);
11598 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11607 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11610 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
11611 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11612 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11613 rtx op0
= expand_normal (arg0
);
11614 rtx op1
= expand_normal (arg1
);
11615 enum machine_mode tmode
= SImode
;
11616 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11617 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11620 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
11622 error ("argument 1 of __builtin_altivec_predicate must be a constant");
11626 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
11628 gcc_assert (mode0
== mode1
);
11630 /* If we have invalid arguments, bail out before generating bad rtl. */
11631 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11635 || GET_MODE (target
) != tmode
11636 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11637 target
= gen_reg_rtx (tmode
);
11639 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11640 op0
= copy_to_mode_reg (mode0
, op0
);
11641 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11642 op1
= copy_to_mode_reg (mode1
, op1
);
11644 scratch
= gen_reg_rtx (mode0
);
11646 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11651 /* The vec_any* and vec_all* predicates use the same opcodes for two
11652 different operations, but the bits in CR6 will be different
11653 depending on what information we want. So we have to play tricks
11654 with CR6 to get the right bits out.
11656 If you think this is disgusting, look at the specs for the
11657 AltiVec predicates. */
11659 switch (cr6_form_int
)
11662 emit_insn (gen_cr6_test_for_zero (target
));
11665 emit_insn (gen_cr6_test_for_zero_reverse (target
));
11668 emit_insn (gen_cr6_test_for_lt (target
));
11671 emit_insn (gen_cr6_test_for_lt_reverse (target
));
11674 error ("argument 1 of __builtin_altivec_predicate is out of range");
11682 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
11685 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11686 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11687 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11688 enum machine_mode mode0
= Pmode
;
11689 enum machine_mode mode1
= Pmode
;
11690 rtx op0
= expand_normal (arg0
);
11691 rtx op1
= expand_normal (arg1
);
11693 if (icode
== CODE_FOR_nothing
)
11694 /* Builtin not supported on this processor. */
11697 /* If we got invalid arguments bail out before generating bad rtl. */
11698 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11702 || GET_MODE (target
) != tmode
11703 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11704 target
= gen_reg_rtx (tmode
);
11706 op1
= copy_to_mode_reg (mode1
, op1
);
11708 if (op0
== const0_rtx
)
11710 addr
= gen_rtx_MEM (tmode
, op1
);
11714 op0
= copy_to_mode_reg (mode0
, op0
);
11715 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11718 pat
= GEN_FCN (icode
) (target
, addr
);
11728 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
11731 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11732 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11733 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11734 enum machine_mode mode0
= Pmode
;
11735 enum machine_mode mode1
= Pmode
;
11736 rtx op0
= expand_normal (arg0
);
11737 rtx op1
= expand_normal (arg1
);
11739 if (icode
== CODE_FOR_nothing
)
11740 /* Builtin not supported on this processor. */
11743 /* If we got invalid arguments bail out before generating bad rtl. */
11744 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11748 || GET_MODE (target
) != tmode
11749 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11750 target
= gen_reg_rtx (tmode
);
11752 op1
= copy_to_mode_reg (mode1
, op1
);
11754 if (op0
== const0_rtx
)
11756 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
11760 op0
= copy_to_mode_reg (mode0
, op0
);
11761 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11764 pat
= GEN_FCN (icode
) (target
, addr
);
11774 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
11776 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11777 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11778 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11779 rtx op0
= expand_normal (arg0
);
11780 rtx op1
= expand_normal (arg1
);
11781 rtx op2
= expand_normal (arg2
);
11783 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11784 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11785 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
11787 /* Invalid arguments. Bail before doing anything stoopid! */
11788 if (arg0
== error_mark_node
11789 || arg1
== error_mark_node
11790 || arg2
== error_mark_node
)
11793 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
11794 op0
= copy_to_mode_reg (mode2
, op0
);
11795 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
11796 op1
= copy_to_mode_reg (mode0
, op1
);
11797 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11798 op2
= copy_to_mode_reg (mode1
, op2
);
11800 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
11807 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
11809 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11810 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11811 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11812 rtx op0
= expand_normal (arg0
);
11813 rtx op1
= expand_normal (arg1
);
11814 rtx op2
= expand_normal (arg2
);
11816 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11817 enum machine_mode mode1
= Pmode
;
11818 enum machine_mode mode2
= Pmode
;
11820 /* Invalid arguments. Bail before doing anything stoopid! */
11821 if (arg0
== error_mark_node
11822 || arg1
== error_mark_node
11823 || arg2
== error_mark_node
)
11826 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
11827 op0
= copy_to_mode_reg (tmode
, op0
);
11829 op2
= copy_to_mode_reg (mode2
, op2
);
11831 if (op1
== const0_rtx
)
11833 addr
= gen_rtx_MEM (tmode
, op2
);
11837 op1
= copy_to_mode_reg (mode1
, op1
);
11838 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11841 pat
= GEN_FCN (icode
) (addr
, op0
);
11848 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
11850 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11851 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11852 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11853 rtx op0
= expand_normal (arg0
);
11854 rtx op1
= expand_normal (arg1
);
11855 rtx op2
= expand_normal (arg2
);
11857 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11858 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
11859 enum machine_mode mode1
= Pmode
;
11860 enum machine_mode mode2
= Pmode
;
11862 /* Invalid arguments. Bail before doing anything stoopid! */
11863 if (arg0
== error_mark_node
11864 || arg1
== error_mark_node
11865 || arg2
== error_mark_node
)
11868 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
11869 op0
= copy_to_mode_reg (smode
, op0
);
11871 op2
= copy_to_mode_reg (mode2
, op2
);
11873 if (op1
== const0_rtx
)
11875 addr
= gen_rtx_MEM (tmode
, op2
);
11879 op1
= copy_to_mode_reg (mode1
, op1
);
11880 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11883 pat
= GEN_FCN (icode
) (addr
, op0
);
11889 /* Return the appropriate SPR number associated with the given builtin. */
11890 static inline HOST_WIDE_INT
11891 htm_spr_num (enum rs6000_builtins code
)
11893 if (code
== HTM_BUILTIN_GET_TFHAR
11894 || code
== HTM_BUILTIN_SET_TFHAR
)
11896 else if (code
== HTM_BUILTIN_GET_TFIAR
11897 || code
== HTM_BUILTIN_SET_TFIAR
)
11899 else if (code
== HTM_BUILTIN_GET_TEXASR
11900 || code
== HTM_BUILTIN_SET_TEXASR
)
11902 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
11903 || code
== HTM_BUILTIN_SET_TEXASRU
);
11904 return TEXASRU_SPR
;
11907 /* Return the appropriate SPR regno associated with the given builtin. */
11908 static inline HOST_WIDE_INT
11909 htm_spr_regno (enum rs6000_builtins code
)
11911 if (code
== HTM_BUILTIN_GET_TFHAR
11912 || code
== HTM_BUILTIN_SET_TFHAR
)
11913 return TFHAR_REGNO
;
11914 else if (code
== HTM_BUILTIN_GET_TFIAR
11915 || code
== HTM_BUILTIN_SET_TFIAR
)
11916 return TFIAR_REGNO
;
11917 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
11918 || code
== HTM_BUILTIN_SET_TEXASR
11919 || code
== HTM_BUILTIN_GET_TEXASRU
11920 || code
== HTM_BUILTIN_SET_TEXASRU
);
11921 return TEXASR_REGNO
;
11924 /* Return the correct ICODE value depending on whether we are
11925 setting or reading the HTM SPRs. */
11926 static inline enum insn_code
11927 rs6000_htm_spr_icode (bool nonvoid
)
11930 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
11932 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
11935 /* Expand the HTM builtin in EXP and store the result in TARGET.
11936 Store true in *EXPANDEDP if we found a builtin to expand. */
11938 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
11940 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11941 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11942 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11943 const struct builtin_description
*d
;
11946 *expandedp
= false;
11948 /* Expand the HTM builtins. */
11950 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
11951 if (d
->code
== fcode
)
11953 rtx op
[MAX_HTM_OPERANDS
], pat
;
11956 call_expr_arg_iterator iter
;
11957 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
11958 enum insn_code icode
= d
->icode
;
11960 if (attr
& RS6000_BTC_SPR
)
11961 icode
= rs6000_htm_spr_icode (nonvoid
);
11965 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11967 || GET_MODE (target
) != tmode
11968 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11969 target
= gen_reg_rtx (tmode
);
11970 op
[nopnds
++] = target
;
11973 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11975 const struct insn_operand_data
*insn_op
;
11977 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
11980 insn_op
= &insn_data
[icode
].operand
[nopnds
];
11982 op
[nopnds
] = expand_normal (arg
);
11984 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
11986 if (!strcmp (insn_op
->constraint
, "n"))
11988 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
11989 if (!CONST_INT_P (op
[nopnds
]))
11990 error ("argument %d must be an unsigned literal", arg_num
);
11992 error ("argument %d is an unsigned literal that is "
11993 "out of range", arg_num
);
11996 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12002 /* Handle the builtins for extended mnemonics. These accept
12003 no arguments, but map to builtins that take arguments. */
12006 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12007 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12008 op
[nopnds
++] = GEN_INT (1);
12009 #ifdef ENABLE_CHECKING
12010 attr
|= RS6000_BTC_UNARY
;
12013 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12014 op
[nopnds
++] = GEN_INT (0);
12015 #ifdef ENABLE_CHECKING
12016 attr
|= RS6000_BTC_UNARY
;
12023 /* If this builtin accesses SPRs, then pass in the appropriate
12024 SPR number and SPR regno as the last two operands. */
12025 if (attr
& RS6000_BTC_SPR
)
12027 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
12028 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
12031 #ifdef ENABLE_CHECKING
12032 int expected_nopnds
= 0;
12033 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12034 expected_nopnds
= 1;
12035 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12036 expected_nopnds
= 2;
12037 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12038 expected_nopnds
= 3;
12039 if (!(attr
& RS6000_BTC_VOID
))
12040 expected_nopnds
+= 1;
12041 if (attr
& RS6000_BTC_SPR
)
12042 expected_nopnds
+= 2;
12044 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12050 pat
= GEN_FCN (icode
) (op
[0]);
12053 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12056 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12059 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12062 gcc_unreachable ();
12078 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12081 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12082 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12083 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12084 rtx op0
= expand_normal (arg0
);
12085 rtx op1
= expand_normal (arg1
);
12086 rtx op2
= expand_normal (arg2
);
12087 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12088 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12089 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12090 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12092 if (icode
== CODE_FOR_nothing
)
12093 /* Builtin not supported on this processor. */
12096 /* If we got invalid arguments bail out before generating bad rtl. */
12097 if (arg0
== error_mark_node
12098 || arg1
== error_mark_node
12099 || arg2
== error_mark_node
)
12102 /* Check and prepare argument depending on the instruction code.
12104 Note that a switch statement instead of the sequence of tests
12105 would be incorrect as many of the CODE_FOR values could be
12106 CODE_FOR_nothing and that would yield multiple alternatives
12107 with identical values. We'd never reach here at runtime in
12109 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12110 || icode
== CODE_FOR_altivec_vsldoi_v4si
12111 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12112 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12114 /* Only allow 4-bit unsigned literals. */
12116 if (TREE_CODE (arg2
) != INTEGER_CST
12117 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12119 error ("argument 3 must be a 4-bit unsigned literal");
12123 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12124 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12125 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12126 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12127 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12128 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12129 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12130 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12132 /* Only allow 2-bit unsigned literals. */
12134 if (TREE_CODE (arg2
) != INTEGER_CST
12135 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12137 error ("argument 3 must be a 2-bit unsigned literal");
12141 else if (icode
== CODE_FOR_vsx_set_v2df
12142 || icode
== CODE_FOR_vsx_set_v2di
)
12144 /* Only allow 1-bit unsigned literals. */
12146 if (TREE_CODE (arg2
) != INTEGER_CST
12147 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12149 error ("argument 3 must be a 1-bit unsigned literal");
12153 else if (icode
== CODE_FOR_crypto_vshasigmaw
12154 || icode
== CODE_FOR_crypto_vshasigmad
)
12156 /* Check whether the 2nd and 3rd arguments are integer constants and in
12157 range and prepare arguments. */
12159 if (TREE_CODE (arg1
) != INTEGER_CST
12160 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
12162 error ("argument 2 must be 0 or 1");
12167 if (TREE_CODE (arg2
) != INTEGER_CST
12168 || !IN_RANGE (TREE_INT_CST_LOW (arg2
), 0, 15))
12170 error ("argument 3 must be in the range 0..15");
12176 || GET_MODE (target
) != tmode
12177 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12178 target
= gen_reg_rtx (tmode
);
12180 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12181 op0
= copy_to_mode_reg (mode0
, op0
);
12182 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12183 op1
= copy_to_mode_reg (mode1
, op1
);
12184 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12185 op2
= copy_to_mode_reg (mode2
, op2
);
12187 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
12188 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
12190 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12198 /* Expand the lvx builtins. */
12200 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
12202 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12203 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12205 enum machine_mode tmode
, mode0
;
12207 enum insn_code icode
;
12211 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
12212 icode
= CODE_FOR_vector_altivec_load_v16qi
;
12214 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
12215 icode
= CODE_FOR_vector_altivec_load_v8hi
;
12217 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
12218 icode
= CODE_FOR_vector_altivec_load_v4si
;
12220 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
12221 icode
= CODE_FOR_vector_altivec_load_v4sf
;
12223 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
12224 icode
= CODE_FOR_vector_altivec_load_v2df
;
12226 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
12227 icode
= CODE_FOR_vector_altivec_load_v2di
;
12230 *expandedp
= false;
12236 arg0
= CALL_EXPR_ARG (exp
, 0);
12237 op0
= expand_normal (arg0
);
12238 tmode
= insn_data
[icode
].operand
[0].mode
;
12239 mode0
= insn_data
[icode
].operand
[1].mode
;
12242 || GET_MODE (target
) != tmode
12243 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12244 target
= gen_reg_rtx (tmode
);
12246 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12247 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12249 pat
= GEN_FCN (icode
) (target
, op0
);
12256 /* Expand the stvx builtins. */
12258 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12261 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12262 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12264 enum machine_mode mode0
, mode1
;
12266 enum insn_code icode
;
12270 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
12271 icode
= CODE_FOR_vector_altivec_store_v16qi
;
12273 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
12274 icode
= CODE_FOR_vector_altivec_store_v8hi
;
12276 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
12277 icode
= CODE_FOR_vector_altivec_store_v4si
;
12279 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
12280 icode
= CODE_FOR_vector_altivec_store_v4sf
;
12282 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
12283 icode
= CODE_FOR_vector_altivec_store_v2df
;
12285 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
12286 icode
= CODE_FOR_vector_altivec_store_v2di
;
12289 *expandedp
= false;
12293 arg0
= CALL_EXPR_ARG (exp
, 0);
12294 arg1
= CALL_EXPR_ARG (exp
, 1);
12295 op0
= expand_normal (arg0
);
12296 op1
= expand_normal (arg1
);
12297 mode0
= insn_data
[icode
].operand
[0].mode
;
12298 mode1
= insn_data
[icode
].operand
[1].mode
;
12300 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12301 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12302 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12303 op1
= copy_to_mode_reg (mode1
, op1
);
12305 pat
= GEN_FCN (icode
) (op0
, op1
);
12313 /* Expand the dst builtins. */
12315 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12318 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12319 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12320 tree arg0
, arg1
, arg2
;
12321 enum machine_mode mode0
, mode1
;
12322 rtx pat
, op0
, op1
, op2
;
12323 const struct builtin_description
*d
;
12326 *expandedp
= false;
12328 /* Handle DST variants. */
12330 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12331 if (d
->code
== fcode
)
12333 arg0
= CALL_EXPR_ARG (exp
, 0);
12334 arg1
= CALL_EXPR_ARG (exp
, 1);
12335 arg2
= CALL_EXPR_ARG (exp
, 2);
12336 op0
= expand_normal (arg0
);
12337 op1
= expand_normal (arg1
);
12338 op2
= expand_normal (arg2
);
12339 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12340 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12342 /* Invalid arguments, bail out before generating bad rtl. */
12343 if (arg0
== error_mark_node
12344 || arg1
== error_mark_node
12345 || arg2
== error_mark_node
)
12350 if (TREE_CODE (arg2
) != INTEGER_CST
12351 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12353 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
12357 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
12358 op0
= copy_to_mode_reg (Pmode
, op0
);
12359 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
12360 op1
= copy_to_mode_reg (mode1
, op1
);
12362 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
12372 /* Expand vec_init builtin. */
12374 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
12376 enum machine_mode tmode
= TYPE_MODE (type
);
12377 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
12378 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
12379 rtvec v
= rtvec_alloc (n_elt
);
12381 gcc_assert (VECTOR_MODE_P (tmode
));
12382 gcc_assert (n_elt
== call_expr_nargs (exp
));
12384 for (i
= 0; i
< n_elt
; ++i
)
12386 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
12387 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
12390 if (!target
|| !register_operand (target
, tmode
))
12391 target
= gen_reg_rtx (tmode
);
12393 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
12397 /* Return the integer constant in ARG. Constrain it to be in the range
12398 of the subparts of VEC_TYPE; issue an error if not. */
12401 get_element_number (tree vec_type
, tree arg
)
12403 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
12405 if (!host_integerp (arg
, 1)
12406 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
12408 error ("selector must be an integer constant in the range 0..%wi", max
);
12415 /* Expand vec_set builtin. */
12417 altivec_expand_vec_set_builtin (tree exp
)
12419 enum machine_mode tmode
, mode1
;
12420 tree arg0
, arg1
, arg2
;
12424 arg0
= CALL_EXPR_ARG (exp
, 0);
12425 arg1
= CALL_EXPR_ARG (exp
, 1);
12426 arg2
= CALL_EXPR_ARG (exp
, 2);
12428 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
12429 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12430 gcc_assert (VECTOR_MODE_P (tmode
));
12432 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
12433 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
12434 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
12436 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
12437 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
12439 op0
= force_reg (tmode
, op0
);
12440 op1
= force_reg (mode1
, op1
);
12442 rs6000_expand_vector_set (op0
, op1
, elt
);
12447 /* Expand vec_ext builtin. */
12449 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
12451 enum machine_mode tmode
, mode0
;
12456 arg0
= CALL_EXPR_ARG (exp
, 0);
12457 arg1
= CALL_EXPR_ARG (exp
, 1);
12459 op0
= expand_normal (arg0
);
12460 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
12462 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12463 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
12464 gcc_assert (VECTOR_MODE_P (mode0
));
12466 op0
= force_reg (mode0
, op0
);
12468 if (optimize
|| !target
|| !register_operand (target
, tmode
))
12469 target
= gen_reg_rtx (tmode
);
12471 rs6000_expand_vector_extract (target
, op0
, elt
);
12476 /* Expand the builtin in EXP and store the result in TARGET. Store
12477 true in *EXPANDEDP if we found a builtin to expand. */
12479 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12481 const struct builtin_description
*d
;
12483 enum insn_code icode
;
12484 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12487 enum machine_mode tmode
, mode0
;
12488 enum rs6000_builtins fcode
12489 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12491 if (rs6000_overloaded_builtin_p (fcode
))
12494 error ("unresolved overload for Altivec builtin %qF", fndecl
);
12496 /* Given it is invalid, just generate a normal call. */
12497 return expand_call (exp
, target
, false);
12500 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
12504 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
12508 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
12516 case ALTIVEC_BUILTIN_STVX
:
12517 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
12518 case ALTIVEC_BUILTIN_STVEBX
:
12519 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
12520 case ALTIVEC_BUILTIN_STVEHX
:
12521 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
12522 case ALTIVEC_BUILTIN_STVEWX
:
12523 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
12524 case ALTIVEC_BUILTIN_STVXL
:
12525 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
12527 case ALTIVEC_BUILTIN_STVLX
:
12528 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
12529 case ALTIVEC_BUILTIN_STVLXL
:
12530 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
12531 case ALTIVEC_BUILTIN_STVRX
:
12532 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
12533 case ALTIVEC_BUILTIN_STVRXL
:
12534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
12536 case VSX_BUILTIN_STXVD2X_V2DF
:
12537 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
12538 case VSX_BUILTIN_STXVD2X_V2DI
:
12539 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
12540 case VSX_BUILTIN_STXVW4X_V4SF
:
12541 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
12542 case VSX_BUILTIN_STXVW4X_V4SI
:
12543 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
12544 case VSX_BUILTIN_STXVW4X_V8HI
:
12545 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
12546 case VSX_BUILTIN_STXVW4X_V16QI
:
12547 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
12549 case ALTIVEC_BUILTIN_MFVSCR
:
12550 icode
= CODE_FOR_altivec_mfvscr
;
12551 tmode
= insn_data
[icode
].operand
[0].mode
;
12554 || GET_MODE (target
) != tmode
12555 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12556 target
= gen_reg_rtx (tmode
);
12558 pat
= GEN_FCN (icode
) (target
);
12564 case ALTIVEC_BUILTIN_MTVSCR
:
12565 icode
= CODE_FOR_altivec_mtvscr
;
12566 arg0
= CALL_EXPR_ARG (exp
, 0);
12567 op0
= expand_normal (arg0
);
12568 mode0
= insn_data
[icode
].operand
[0].mode
;
12570 /* If we got invalid arguments bail out before generating bad rtl. */
12571 if (arg0
== error_mark_node
)
12574 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12575 op0
= copy_to_mode_reg (mode0
, op0
);
12577 pat
= GEN_FCN (icode
) (op0
);
12582 case ALTIVEC_BUILTIN_DSSALL
:
12583 emit_insn (gen_altivec_dssall ());
12586 case ALTIVEC_BUILTIN_DSS
:
12587 icode
= CODE_FOR_altivec_dss
;
12588 arg0
= CALL_EXPR_ARG (exp
, 0);
12590 op0
= expand_normal (arg0
);
12591 mode0
= insn_data
[icode
].operand
[0].mode
;
12593 /* If we got invalid arguments bail out before generating bad rtl. */
12594 if (arg0
== error_mark_node
)
12597 if (TREE_CODE (arg0
) != INTEGER_CST
12598 || TREE_INT_CST_LOW (arg0
) & ~0x3)
12600 error ("argument to dss must be a 2-bit unsigned literal");
12604 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12605 op0
= copy_to_mode_reg (mode0
, op0
);
12607 emit_insn (gen_altivec_dss (op0
));
12610 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
12611 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
12612 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
12613 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
12614 case VSX_BUILTIN_VEC_INIT_V2DF
:
12615 case VSX_BUILTIN_VEC_INIT_V2DI
:
12616 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
12618 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
12619 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
12620 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
12621 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
12622 case VSX_BUILTIN_VEC_SET_V2DF
:
12623 case VSX_BUILTIN_VEC_SET_V2DI
:
12624 return altivec_expand_vec_set_builtin (exp
);
12626 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
12627 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
12628 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
12629 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
12630 case VSX_BUILTIN_VEC_EXT_V2DF
:
12631 case VSX_BUILTIN_VEC_EXT_V2DI
:
12632 return altivec_expand_vec_ext_builtin (exp
, target
);
12636 /* Fall through. */
12639 /* Expand abs* operations. */
12641 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12642 if (d
->code
== fcode
)
12643 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
12645 /* Expand the AltiVec predicates. */
12646 d
= bdesc_altivec_preds
;
12647 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12648 if (d
->code
== fcode
)
12649 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
12651 /* LV* are funky. We initialized them differently. */
12654 case ALTIVEC_BUILTIN_LVSL
:
12655 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
12656 exp
, target
, false);
12657 case ALTIVEC_BUILTIN_LVSR
:
12658 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
12659 exp
, target
, false);
12660 case ALTIVEC_BUILTIN_LVEBX
:
12661 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
12662 exp
, target
, false);
12663 case ALTIVEC_BUILTIN_LVEHX
:
12664 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
12665 exp
, target
, false);
12666 case ALTIVEC_BUILTIN_LVEWX
:
12667 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
12668 exp
, target
, false);
12669 case ALTIVEC_BUILTIN_LVXL
:
12670 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
12671 exp
, target
, false);
12672 case ALTIVEC_BUILTIN_LVX
:
12673 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
12674 exp
, target
, false);
12675 case ALTIVEC_BUILTIN_LVLX
:
12676 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
12677 exp
, target
, true);
12678 case ALTIVEC_BUILTIN_LVLXL
:
12679 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
12680 exp
, target
, true);
12681 case ALTIVEC_BUILTIN_LVRX
:
12682 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
12683 exp
, target
, true);
12684 case ALTIVEC_BUILTIN_LVRXL
:
12685 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
12686 exp
, target
, true);
12687 case VSX_BUILTIN_LXVD2X_V2DF
:
12688 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
12689 exp
, target
, false);
12690 case VSX_BUILTIN_LXVD2X_V2DI
:
12691 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
12692 exp
, target
, false);
12693 case VSX_BUILTIN_LXVW4X_V4SF
:
12694 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
12695 exp
, target
, false);
12696 case VSX_BUILTIN_LXVW4X_V4SI
:
12697 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
12698 exp
, target
, false);
12699 case VSX_BUILTIN_LXVW4X_V8HI
:
12700 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
12701 exp
, target
, false);
12702 case VSX_BUILTIN_LXVW4X_V16QI
:
12703 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
12704 exp
, target
, false);
12708 /* Fall through. */
12711 *expandedp
= false;
12715 /* Expand the builtin in EXP and store the result in TARGET. Store
12716 true in *EXPANDEDP if we found a builtin to expand. */
12718 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12720 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12721 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12722 const struct builtin_description
*d
;
12729 case PAIRED_BUILTIN_STX
:
12730 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
12731 case PAIRED_BUILTIN_LX
:
12732 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
12735 /* Fall through. */
12738 /* Expand the paired predicates. */
12739 d
= bdesc_paired_preds
;
12740 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
12741 if (d
->code
== fcode
)
12742 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
12744 *expandedp
= false;
12748 /* Binops that need to be initialized manually, but can be expanded
12749 automagically by rs6000_expand_binop_builtin. */
12750 static const struct builtin_description bdesc_2arg_spe
[] =
12752 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
12753 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
12754 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
12755 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
12756 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
12757 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
12758 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
12759 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
12760 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
12761 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
12762 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
12763 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
12764 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
12765 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
12766 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
12767 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
12768 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
12769 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
12770 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
12771 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
12772 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
12773 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
12776 /* Expand the builtin in EXP and store the result in TARGET. Store
12777 true in *EXPANDEDP if we found a builtin to expand.
12779 This expands the SPE builtins that are not simple unary and binary
12782 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12784 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12786 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12787 enum insn_code icode
;
12788 enum machine_mode tmode
, mode0
;
12790 const struct builtin_description
*d
;
12795 /* Syntax check for a 5-bit unsigned immediate. */
12798 case SPE_BUILTIN_EVSTDD
:
12799 case SPE_BUILTIN_EVSTDH
:
12800 case SPE_BUILTIN_EVSTDW
:
12801 case SPE_BUILTIN_EVSTWHE
:
12802 case SPE_BUILTIN_EVSTWHO
:
12803 case SPE_BUILTIN_EVSTWWE
:
12804 case SPE_BUILTIN_EVSTWWO
:
12805 arg1
= CALL_EXPR_ARG (exp
, 2);
12806 if (TREE_CODE (arg1
) != INTEGER_CST
12807 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
12809 error ("argument 2 must be a 5-bit unsigned literal");
12817 /* The evsplat*i instructions are not quite generic. */
12820 case SPE_BUILTIN_EVSPLATFI
:
12821 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
12823 case SPE_BUILTIN_EVSPLATI
:
12824 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
12830 d
= bdesc_2arg_spe
;
12831 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
12832 if (d
->code
== fcode
)
12833 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
12835 d
= bdesc_spe_predicates
;
12836 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
12837 if (d
->code
== fcode
)
12838 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
12840 d
= bdesc_spe_evsel
;
12841 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
12842 if (d
->code
== fcode
)
12843 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
12847 case SPE_BUILTIN_EVSTDDX
:
12848 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
12849 case SPE_BUILTIN_EVSTDHX
:
12850 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
12851 case SPE_BUILTIN_EVSTDWX
:
12852 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
12853 case SPE_BUILTIN_EVSTWHEX
:
12854 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
12855 case SPE_BUILTIN_EVSTWHOX
:
12856 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
12857 case SPE_BUILTIN_EVSTWWEX
:
12858 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
12859 case SPE_BUILTIN_EVSTWWOX
:
12860 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
12861 case SPE_BUILTIN_EVSTDD
:
12862 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
12863 case SPE_BUILTIN_EVSTDH
:
12864 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
12865 case SPE_BUILTIN_EVSTDW
:
12866 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
12867 case SPE_BUILTIN_EVSTWHE
:
12868 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
12869 case SPE_BUILTIN_EVSTWHO
:
12870 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
12871 case SPE_BUILTIN_EVSTWWE
:
12872 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
12873 case SPE_BUILTIN_EVSTWWO
:
12874 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
12875 case SPE_BUILTIN_MFSPEFSCR
:
12876 icode
= CODE_FOR_spe_mfspefscr
;
12877 tmode
= insn_data
[icode
].operand
[0].mode
;
12880 || GET_MODE (target
) != tmode
12881 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12882 target
= gen_reg_rtx (tmode
);
12884 pat
= GEN_FCN (icode
) (target
);
12889 case SPE_BUILTIN_MTSPEFSCR
:
12890 icode
= CODE_FOR_spe_mtspefscr
;
12891 arg0
= CALL_EXPR_ARG (exp
, 0);
12892 op0
= expand_normal (arg0
);
12893 mode0
= insn_data
[icode
].operand
[0].mode
;
12895 if (arg0
== error_mark_node
)
12898 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12899 op0
= copy_to_mode_reg (mode0
, op0
);
12901 pat
= GEN_FCN (icode
) (op0
);
12909 *expandedp
= false;
12914 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12916 rtx pat
, scratch
, tmp
;
12917 tree form
= CALL_EXPR_ARG (exp
, 0);
12918 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12919 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12920 rtx op0
= expand_normal (arg0
);
12921 rtx op1
= expand_normal (arg1
);
12922 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12923 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12925 enum rtx_code code
;
12927 if (TREE_CODE (form
) != INTEGER_CST
)
12929 error ("argument 1 of __builtin_paired_predicate must be a constant");
12933 form_int
= TREE_INT_CST_LOW (form
);
12935 gcc_assert (mode0
== mode1
);
12937 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12941 || GET_MODE (target
) != SImode
12942 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
12943 target
= gen_reg_rtx (SImode
);
12944 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12945 op0
= copy_to_mode_reg (mode0
, op0
);
12946 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12947 op1
= copy_to_mode_reg (mode1
, op1
);
12949 scratch
= gen_reg_rtx (CCFPmode
);
12951 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12973 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
12976 error ("argument 1 of __builtin_paired_predicate is out of range");
12980 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
12981 emit_move_insn (target
, tmp
);
12986 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12988 rtx pat
, scratch
, tmp
;
12989 tree form
= CALL_EXPR_ARG (exp
, 0);
12990 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12991 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12992 rtx op0
= expand_normal (arg0
);
12993 rtx op1
= expand_normal (arg1
);
12994 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12995 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12997 enum rtx_code code
;
12999 if (TREE_CODE (form
) != INTEGER_CST
)
13001 error ("argument 1 of __builtin_spe_predicate must be a constant");
13005 form_int
= TREE_INT_CST_LOW (form
);
13007 gcc_assert (mode0
== mode1
);
13009 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13013 || GET_MODE (target
) != SImode
13014 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13015 target
= gen_reg_rtx (SImode
);
13017 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13018 op0
= copy_to_mode_reg (mode0
, op0
);
13019 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13020 op1
= copy_to_mode_reg (mode1
, op1
);
13022 scratch
= gen_reg_rtx (CCmode
);
13024 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13029 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13030 _lower_. We use one compare, but look in different bits of the
13031 CR for each variant.
13033 There are 2 elements in each SPE simd type (upper/lower). The CR
13034 bits are set as follows:
13036 BIT0 | BIT 1 | BIT 2 | BIT 3
13037 U | L | (U | L) | (U & L)
13039 So, for an "all" relationship, BIT 3 would be set.
13040 For an "any" relationship, BIT 2 would be set. Etc.
13042 Following traditional nomenclature, these bits map to:
13044 BIT0 | BIT 1 | BIT 2 | BIT 3
13047 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13052 /* All variant. OV bit. */
13054 /* We need to get to the OV bit, which is the ORDERED bit. We
13055 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13056 that's ugly and will make validate_condition_mode die.
13057 So let's just use another pattern. */
13058 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13060 /* Any variant. EQ bit. */
13064 /* Upper variant. LT bit. */
13068 /* Lower variant. GT bit. */
13073 error ("argument 1 of __builtin_spe_predicate is out of range");
13077 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13078 emit_move_insn (target
, tmp
);
13083 /* The evsel builtins look like this:
13085 e = __builtin_spe_evsel_OP (a, b, c, d);
13087 and work like this:
13089 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13090 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13094 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
13097 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13098 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13099 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13100 tree arg3
= CALL_EXPR_ARG (exp
, 3);
13101 rtx op0
= expand_normal (arg0
);
13102 rtx op1
= expand_normal (arg1
);
13103 rtx op2
= expand_normal (arg2
);
13104 rtx op3
= expand_normal (arg3
);
13105 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13106 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13108 gcc_assert (mode0
== mode1
);
13110 if (arg0
== error_mark_node
|| arg1
== error_mark_node
13111 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
13115 || GET_MODE (target
) != mode0
13116 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
13117 target
= gen_reg_rtx (mode0
);
13119 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13120 op0
= copy_to_mode_reg (mode0
, op0
);
13121 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13122 op1
= copy_to_mode_reg (mode0
, op1
);
13123 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13124 op2
= copy_to_mode_reg (mode0
, op2
);
13125 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
13126 op3
= copy_to_mode_reg (mode0
, op3
);
13128 /* Generate the compare. */
13129 scratch
= gen_reg_rtx (CCmode
);
13130 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13135 if (mode0
== V2SImode
)
13136 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
13138 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
13143 /* Raise an error message for a builtin function that is called without the
13144 appropriate target options being set. */
13147 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
13149 size_t uns_fncode
= (size_t)fncode
;
13150 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
13151 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
13153 gcc_assert (name
!= NULL
);
13154 if ((fnmask
& RS6000_BTM_CELL
) != 0)
13155 error ("Builtin function %s is only valid for the cell processor", name
);
13156 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
13157 error ("Builtin function %s requires the -mvsx option", name
);
13158 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
13159 error ("Builtin function %s requires the -mhtm option", name
);
13160 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
13161 error ("Builtin function %s requires the -maltivec option", name
);
13162 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
13163 error ("Builtin function %s requires the -mpaired option", name
);
13164 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
13165 error ("Builtin function %s requires the -mspe option", name
);
13167 error ("Builtin function %s is not supported with the current options",
13171 /* Expand an expression EXP that calls a built-in function,
13172 with result going to TARGET if that's convenient
13173 (and in mode MODE if that's convenient).
13174 SUBTARGET may be used as the target for computing one of EXP's operands.
13175 IGNORE is nonzero if the value is to be ignored. */
13178 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13179 enum machine_mode mode ATTRIBUTE_UNUSED
,
13180 int ignore ATTRIBUTE_UNUSED
)
13182 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13183 enum rs6000_builtins fcode
13184 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
13185 size_t uns_fcode
= (size_t)fcode
;
13186 const struct builtin_description
*d
;
13190 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
13191 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
13193 if (TARGET_DEBUG_BUILTIN
)
13195 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
13196 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
13197 const char *name2
= ((icode
!= CODE_FOR_nothing
)
13198 ? get_insn_name ((int)icode
)
13202 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
13204 default: name3
= "unknown"; break;
13205 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
13206 case RS6000_BTC_UNARY
: name3
= "unary"; break;
13207 case RS6000_BTC_BINARY
: name3
= "binary"; break;
13208 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
13209 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
13210 case RS6000_BTC_ABS
: name3
= "abs"; break;
13211 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
13212 case RS6000_BTC_DST
: name3
= "dst"; break;
13217 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13218 (name1
) ? name1
: "---", fcode
,
13219 (name2
) ? name2
: "---", (int)icode
,
13221 func_valid_p
? "" : ", not valid");
13226 rs6000_invalid_builtin (fcode
);
13228 /* Given it is invalid, just generate a normal call. */
13229 return expand_call (exp
, target
, ignore
);
13234 case RS6000_BUILTIN_RECIP
:
13235 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
13237 case RS6000_BUILTIN_RECIPF
:
13238 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
13240 case RS6000_BUILTIN_RSQRTF
:
13241 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
13243 case RS6000_BUILTIN_RSQRT
:
13244 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
13246 case POWER7_BUILTIN_BPERMD
:
13247 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
13248 ? CODE_FOR_bpermd_di
13249 : CODE_FOR_bpermd_si
), exp
, target
);
13251 case RS6000_BUILTIN_GET_TB
:
13252 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
13255 case RS6000_BUILTIN_MFTB
:
13256 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
13257 ? CODE_FOR_rs6000_mftb_di
13258 : CODE_FOR_rs6000_mftb_si
),
13261 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
13262 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
13264 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
13265 : (int) CODE_FOR_altivec_lvsl
);
13266 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13267 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
13271 gcc_assert (TARGET_ALTIVEC
);
13273 arg
= CALL_EXPR_ARG (exp
, 0);
13274 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
13275 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
13276 addr
= memory_address (mode
, op
);
13277 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
13281 /* For the load case need to negate the address. */
13282 op
= gen_reg_rtx (GET_MODE (addr
));
13283 emit_insn (gen_rtx_SET (VOIDmode
, op
,
13284 gen_rtx_NEG (GET_MODE (addr
), addr
)));
13286 op
= gen_rtx_MEM (mode
, op
);
13289 || GET_MODE (target
) != tmode
13290 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13291 target
= gen_reg_rtx (tmode
);
13293 /*pat = gen_altivec_lvsr (target, op);*/
13294 pat
= GEN_FCN (icode
) (target
, op
);
13302 case ALTIVEC_BUILTIN_VCFUX
:
13303 case ALTIVEC_BUILTIN_VCFSX
:
13304 case ALTIVEC_BUILTIN_VCTUXS
:
13305 case ALTIVEC_BUILTIN_VCTSXS
:
13306 /* FIXME: There's got to be a nicer way to handle this case than
13307 constructing a new CALL_EXPR. */
13308 if (call_expr_nargs (exp
) == 1)
13310 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
13311 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
13319 if (TARGET_ALTIVEC
)
13321 ret
= altivec_expand_builtin (exp
, target
, &success
);
13328 ret
= spe_expand_builtin (exp
, target
, &success
);
13333 if (TARGET_PAIRED_FLOAT
)
13335 ret
= paired_expand_builtin (exp
, target
, &success
);
13342 ret
= htm_expand_builtin (exp
, target
, &success
);
13348 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
13350 /* Handle simple unary operations. */
13352 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13353 if (d
->code
== fcode
)
13354 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
13356 /* Handle simple binary operations. */
13358 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13359 if (d
->code
== fcode
)
13360 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13362 /* Handle simple ternary operations. */
13364 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13365 if (d
->code
== fcode
)
13366 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
13368 gcc_unreachable ();
13372 rs6000_init_builtins (void)
13376 enum machine_mode mode
;
13378 if (TARGET_DEBUG_BUILTIN
)
13379 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
13380 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
13381 (TARGET_SPE
) ? ", spe" : "",
13382 (TARGET_ALTIVEC
) ? ", altivec" : "",
13383 (TARGET_VSX
) ? ", vsx" : "");
13385 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
13386 V2SF_type_node
= build_vector_type (float_type_node
, 2);
13387 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
13388 V2DF_type_node
= build_vector_type (double_type_node
, 2);
13389 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
13390 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
13391 V4SF_type_node
= build_vector_type (float_type_node
, 4);
13392 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
13393 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
13395 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
13396 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
13397 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
13398 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
13400 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
13401 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
13402 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
13403 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
13405 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13406 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13407 'vector unsigned short'. */
13409 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
13410 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13411 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
13412 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
13413 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13415 long_integer_type_internal_node
= long_integer_type_node
;
13416 long_unsigned_type_internal_node
= long_unsigned_type_node
;
13417 long_long_integer_type_internal_node
= long_long_integer_type_node
;
13418 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
13419 intQI_type_internal_node
= intQI_type_node
;
13420 uintQI_type_internal_node
= unsigned_intQI_type_node
;
13421 intHI_type_internal_node
= intHI_type_node
;
13422 uintHI_type_internal_node
= unsigned_intHI_type_node
;
13423 intSI_type_internal_node
= intSI_type_node
;
13424 uintSI_type_internal_node
= unsigned_intSI_type_node
;
13425 intDI_type_internal_node
= intDI_type_node
;
13426 uintDI_type_internal_node
= unsigned_intDI_type_node
;
13427 float_type_internal_node
= float_type_node
;
13428 double_type_internal_node
= double_type_node
;
13429 void_type_internal_node
= void_type_node
;
13431 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13433 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
13434 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
13435 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
13436 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
13437 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
13438 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
13439 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
13440 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
13441 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
13442 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
13443 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
13444 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
13445 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
13446 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
13447 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
13448 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
13449 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
13450 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
13451 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
13452 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
13453 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
13455 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
13456 TYPE_NAME (bool_char_type_node
) = tdecl
;
13458 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
13459 TYPE_NAME (bool_short_type_node
) = tdecl
;
13461 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
13462 TYPE_NAME (bool_int_type_node
) = tdecl
;
13464 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
13465 TYPE_NAME (pixel_type_node
) = tdecl
;
13467 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
13468 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
13469 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
13470 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
13471 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
13473 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
13474 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
13476 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
13477 TYPE_NAME (V16QI_type_node
) = tdecl
;
13479 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
13480 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
13482 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
13483 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
13485 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
13486 TYPE_NAME (V8HI_type_node
) = tdecl
;
13488 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
13489 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
13491 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
13492 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
13494 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
13495 TYPE_NAME (V4SI_type_node
) = tdecl
;
13497 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
13498 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
13500 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
13501 TYPE_NAME (V4SF_type_node
) = tdecl
;
13503 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
13504 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
13506 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
13507 TYPE_NAME (V2DF_type_node
) = tdecl
;
13509 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
13510 TYPE_NAME (V2DI_type_node
) = tdecl
;
13512 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
13513 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13515 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
13516 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13518 /* Paired and SPE builtins are only available if you build a compiler with
13519 the appropriate options, so only create those builtins with the
13520 appropriate compiler option. Create Altivec and VSX builtins on machines
13521 with at least the general purpose extensions (970 and newer) to allow the
13522 use of the target attribute. */
13523 if (TARGET_PAIRED_FLOAT
)
13524 paired_init_builtins ();
13526 spe_init_builtins ();
13527 if (TARGET_EXTRA_BUILTINS
)
13528 altivec_init_builtins ();
13530 htm_init_builtins ();
13532 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
13533 rs6000_common_init_builtins ();
13535 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
13536 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
13537 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
13539 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
13540 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
13541 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
13543 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
13544 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
13545 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
13547 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
13548 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
13549 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
13551 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
13552 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
13553 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
13554 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
13556 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13558 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
13561 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13564 ftype
= build_function_type_list (unsigned_intSI_type_node
,
13566 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
13569 /* AIX libm provides clog as __clog. */
13570 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
13571 set_user_assembler_name (tdecl
, "__clog");
13574 #ifdef SUBTARGET_INIT_BUILTINS
13575 SUBTARGET_INIT_BUILTINS
;
13579 /* Returns the rs6000 builtin decl for CODE. */
13582 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
13584 HOST_WIDE_INT fnmask
;
13586 if (code
>= RS6000_BUILTIN_COUNT
)
13587 return error_mark_node
;
13589 fnmask
= rs6000_builtin_info
[code
].mask
;
13590 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
13592 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
13593 return error_mark_node
;
13596 return rs6000_builtin_decls
[code
];
13600 spe_init_builtins (void)
13602 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
13603 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
13604 const struct builtin_description
*d
;
13607 tree v2si_ftype_4_v2si
13608 = build_function_type_list (opaque_V2SI_type_node
,
13609 opaque_V2SI_type_node
,
13610 opaque_V2SI_type_node
,
13611 opaque_V2SI_type_node
,
13612 opaque_V2SI_type_node
,
13615 tree v2sf_ftype_4_v2sf
13616 = build_function_type_list (opaque_V2SF_type_node
,
13617 opaque_V2SF_type_node
,
13618 opaque_V2SF_type_node
,
13619 opaque_V2SF_type_node
,
13620 opaque_V2SF_type_node
,
13623 tree int_ftype_int_v2si_v2si
13624 = build_function_type_list (integer_type_node
,
13626 opaque_V2SI_type_node
,
13627 opaque_V2SI_type_node
,
13630 tree int_ftype_int_v2sf_v2sf
13631 = build_function_type_list (integer_type_node
,
13633 opaque_V2SF_type_node
,
13634 opaque_V2SF_type_node
,
13637 tree void_ftype_v2si_puint_int
13638 = build_function_type_list (void_type_node
,
13639 opaque_V2SI_type_node
,
13644 tree void_ftype_v2si_puint_char
13645 = build_function_type_list (void_type_node
,
13646 opaque_V2SI_type_node
,
13651 tree void_ftype_v2si_pv2si_int
13652 = build_function_type_list (void_type_node
,
13653 opaque_V2SI_type_node
,
13654 opaque_p_V2SI_type_node
,
13658 tree void_ftype_v2si_pv2si_char
13659 = build_function_type_list (void_type_node
,
13660 opaque_V2SI_type_node
,
13661 opaque_p_V2SI_type_node
,
13665 tree void_ftype_int
13666 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13668 tree int_ftype_void
13669 = build_function_type_list (integer_type_node
, NULL_TREE
);
13671 tree v2si_ftype_pv2si_int
13672 = build_function_type_list (opaque_V2SI_type_node
,
13673 opaque_p_V2SI_type_node
,
13677 tree v2si_ftype_puint_int
13678 = build_function_type_list (opaque_V2SI_type_node
,
13683 tree v2si_ftype_pushort_int
13684 = build_function_type_list (opaque_V2SI_type_node
,
13689 tree v2si_ftype_signed_char
13690 = build_function_type_list (opaque_V2SI_type_node
,
13691 signed_char_type_node
,
13694 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
13696 /* Initialize irregular SPE builtins. */
13698 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
13699 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
13700 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
13701 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
13702 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
13703 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
13704 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
13705 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
13706 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
13707 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
13708 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
13709 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
13710 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
13711 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
13712 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
13713 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
13714 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
13715 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
13718 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
13719 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
13720 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
13721 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
13722 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
13723 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
13724 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
13725 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
13726 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
13727 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
13728 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
13729 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
13730 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
13731 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
13732 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
13733 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
13734 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
13735 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
13736 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
13737 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
13738 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
13739 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
13742 d
= bdesc_spe_predicates
;
13743 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
13747 switch (insn_data
[d
->icode
].operand
[1].mode
)
13750 type
= int_ftype_int_v2si_v2si
;
13753 type
= int_ftype_int_v2sf_v2sf
;
13756 gcc_unreachable ();
13759 def_builtin (d
->name
, type
, d
->code
);
13762 /* Evsel predicates. */
13763 d
= bdesc_spe_evsel
;
13764 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
13768 switch (insn_data
[d
->icode
].operand
[1].mode
)
13771 type
= v2si_ftype_4_v2si
;
13774 type
= v2sf_ftype_4_v2sf
;
13777 gcc_unreachable ();
13780 def_builtin (d
->name
, type
, d
->code
);
13785 paired_init_builtins (void)
13787 const struct builtin_description
*d
;
13790 tree int_ftype_int_v2sf_v2sf
13791 = build_function_type_list (integer_type_node
,
13796 tree pcfloat_type_node
=
13797 build_pointer_type (build_qualified_type
13798 (float_type_node
, TYPE_QUAL_CONST
));
13800 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
13801 long_integer_type_node
,
13804 tree void_ftype_v2sf_long_pcfloat
=
13805 build_function_type_list (void_type_node
,
13807 long_integer_type_node
,
13812 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
13813 PAIRED_BUILTIN_LX
);
13816 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
13817 PAIRED_BUILTIN_STX
);
13820 d
= bdesc_paired_preds
;
13821 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
13825 if (TARGET_DEBUG_BUILTIN
)
13826 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
13827 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
13828 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
13830 switch (insn_data
[d
->icode
].operand
[1].mode
)
13833 type
= int_ftype_int_v2sf_v2sf
;
13836 gcc_unreachable ();
13839 def_builtin (d
->name
, type
, d
->code
);
13844 altivec_init_builtins (void)
13846 const struct builtin_description
*d
;
13851 tree pvoid_type_node
= build_pointer_type (void_type_node
);
13853 tree pcvoid_type_node
13854 = build_pointer_type (build_qualified_type (void_type_node
,
13857 tree int_ftype_opaque
13858 = build_function_type_list (integer_type_node
,
13859 opaque_V4SI_type_node
, NULL_TREE
);
13860 tree opaque_ftype_opaque
13861 = build_function_type_list (integer_type_node
, NULL_TREE
);
13862 tree opaque_ftype_opaque_int
13863 = build_function_type_list (opaque_V4SI_type_node
,
13864 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
13865 tree opaque_ftype_opaque_opaque_int
13866 = build_function_type_list (opaque_V4SI_type_node
,
13867 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
13868 integer_type_node
, NULL_TREE
);
13869 tree int_ftype_int_opaque_opaque
13870 = build_function_type_list (integer_type_node
,
13871 integer_type_node
, opaque_V4SI_type_node
,
13872 opaque_V4SI_type_node
, NULL_TREE
);
13873 tree int_ftype_int_v4si_v4si
13874 = build_function_type_list (integer_type_node
,
13875 integer_type_node
, V4SI_type_node
,
13876 V4SI_type_node
, NULL_TREE
);
13877 tree int_ftype_int_v2di_v2di
13878 = build_function_type_list (integer_type_node
,
13879 integer_type_node
, V2DI_type_node
,
13880 V2DI_type_node
, NULL_TREE
);
13881 tree void_ftype_v4si
13882 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
13883 tree v8hi_ftype_void
13884 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
13885 tree void_ftype_void
13886 = build_function_type_list (void_type_node
, NULL_TREE
);
13887 tree void_ftype_int
13888 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13890 tree opaque_ftype_long_pcvoid
13891 = build_function_type_list (opaque_V4SI_type_node
,
13892 long_integer_type_node
, pcvoid_type_node
,
13894 tree v16qi_ftype_long_pcvoid
13895 = build_function_type_list (V16QI_type_node
,
13896 long_integer_type_node
, pcvoid_type_node
,
13898 tree v8hi_ftype_long_pcvoid
13899 = build_function_type_list (V8HI_type_node
,
13900 long_integer_type_node
, pcvoid_type_node
,
13902 tree v4si_ftype_long_pcvoid
13903 = build_function_type_list (V4SI_type_node
,
13904 long_integer_type_node
, pcvoid_type_node
,
13906 tree v4sf_ftype_long_pcvoid
13907 = build_function_type_list (V4SF_type_node
,
13908 long_integer_type_node
, pcvoid_type_node
,
13910 tree v2df_ftype_long_pcvoid
13911 = build_function_type_list (V2DF_type_node
,
13912 long_integer_type_node
, pcvoid_type_node
,
13914 tree v2di_ftype_long_pcvoid
13915 = build_function_type_list (V2DI_type_node
,
13916 long_integer_type_node
, pcvoid_type_node
,
13919 tree void_ftype_opaque_long_pvoid
13920 = build_function_type_list (void_type_node
,
13921 opaque_V4SI_type_node
, long_integer_type_node
,
13922 pvoid_type_node
, NULL_TREE
);
13923 tree void_ftype_v4si_long_pvoid
13924 = build_function_type_list (void_type_node
,
13925 V4SI_type_node
, long_integer_type_node
,
13926 pvoid_type_node
, NULL_TREE
);
13927 tree void_ftype_v16qi_long_pvoid
13928 = build_function_type_list (void_type_node
,
13929 V16QI_type_node
, long_integer_type_node
,
13930 pvoid_type_node
, NULL_TREE
);
13931 tree void_ftype_v8hi_long_pvoid
13932 = build_function_type_list (void_type_node
,
13933 V8HI_type_node
, long_integer_type_node
,
13934 pvoid_type_node
, NULL_TREE
);
13935 tree void_ftype_v4sf_long_pvoid
13936 = build_function_type_list (void_type_node
,
13937 V4SF_type_node
, long_integer_type_node
,
13938 pvoid_type_node
, NULL_TREE
);
13939 tree void_ftype_v2df_long_pvoid
13940 = build_function_type_list (void_type_node
,
13941 V2DF_type_node
, long_integer_type_node
,
13942 pvoid_type_node
, NULL_TREE
);
13943 tree void_ftype_v2di_long_pvoid
13944 = build_function_type_list (void_type_node
,
13945 V2DI_type_node
, long_integer_type_node
,
13946 pvoid_type_node
, NULL_TREE
);
13947 tree int_ftype_int_v8hi_v8hi
13948 = build_function_type_list (integer_type_node
,
13949 integer_type_node
, V8HI_type_node
,
13950 V8HI_type_node
, NULL_TREE
);
13951 tree int_ftype_int_v16qi_v16qi
13952 = build_function_type_list (integer_type_node
,
13953 integer_type_node
, V16QI_type_node
,
13954 V16QI_type_node
, NULL_TREE
);
13955 tree int_ftype_int_v4sf_v4sf
13956 = build_function_type_list (integer_type_node
,
13957 integer_type_node
, V4SF_type_node
,
13958 V4SF_type_node
, NULL_TREE
);
13959 tree int_ftype_int_v2df_v2df
13960 = build_function_type_list (integer_type_node
,
13961 integer_type_node
, V2DF_type_node
,
13962 V2DF_type_node
, NULL_TREE
);
13963 tree v2di_ftype_v2di
13964 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
13965 tree v4si_ftype_v4si
13966 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
13967 tree v8hi_ftype_v8hi
13968 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
13969 tree v16qi_ftype_v16qi
13970 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
13971 tree v4sf_ftype_v4sf
13972 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
13973 tree v2df_ftype_v2df
13974 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
13975 tree void_ftype_pcvoid_int_int
13976 = build_function_type_list (void_type_node
,
13977 pcvoid_type_node
, integer_type_node
,
13978 integer_type_node
, NULL_TREE
);
13980 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
13981 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
13982 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
13983 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
13984 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
13985 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
13986 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
13987 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
13988 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
13989 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
13990 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
13991 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
13992 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
13993 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
13994 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
13995 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
13996 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
13997 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
13998 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
13999 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
14000 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
14001 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
14002 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
14003 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
14004 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
14005 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
14006 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
14007 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
14008 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
14009 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
14011 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
14012 VSX_BUILTIN_LXVD2X_V2DF
);
14013 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
14014 VSX_BUILTIN_LXVD2X_V2DI
);
14015 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
14016 VSX_BUILTIN_LXVW4X_V4SF
);
14017 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
14018 VSX_BUILTIN_LXVW4X_V4SI
);
14019 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
14020 VSX_BUILTIN_LXVW4X_V8HI
);
14021 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
14022 VSX_BUILTIN_LXVW4X_V16QI
);
14023 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
14024 VSX_BUILTIN_STXVD2X_V2DF
);
14025 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
14026 VSX_BUILTIN_STXVD2X_V2DI
);
14027 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
14028 VSX_BUILTIN_STXVW4X_V4SF
);
14029 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
14030 VSX_BUILTIN_STXVW4X_V4SI
);
14031 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
14032 VSX_BUILTIN_STXVW4X_V8HI
);
14033 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
14034 VSX_BUILTIN_STXVW4X_V16QI
);
14035 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
14036 VSX_BUILTIN_VEC_LD
);
14037 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
14038 VSX_BUILTIN_VEC_ST
);
14040 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
14041 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
14042 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
14044 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
14045 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
14046 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
14047 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
14048 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
14049 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
14050 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
14051 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
14052 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
14053 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
14054 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
14055 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
14057 /* Cell builtins. */
14058 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
14059 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
14060 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
14061 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
14063 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
14064 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
14065 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
14066 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
14068 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
14069 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
14070 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
14071 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
14073 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
14074 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
14075 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
14076 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
14078 /* Add the DST variants. */
14080 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14081 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
14083 /* Initialize the predicates. */
14084 d
= bdesc_altivec_preds
;
14085 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14087 enum machine_mode mode1
;
14090 if (rs6000_overloaded_builtin_p (d
->code
))
14093 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14098 type
= int_ftype_int_opaque_opaque
;
14101 type
= int_ftype_int_v2di_v2di
;
14104 type
= int_ftype_int_v4si_v4si
;
14107 type
= int_ftype_int_v8hi_v8hi
;
14110 type
= int_ftype_int_v16qi_v16qi
;
14113 type
= int_ftype_int_v4sf_v4sf
;
14116 type
= int_ftype_int_v2df_v2df
;
14119 gcc_unreachable ();
14122 def_builtin (d
->name
, type
, d
->code
);
14125 /* Initialize the abs* operators. */
14127 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14129 enum machine_mode mode0
;
14132 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14137 type
= v2di_ftype_v2di
;
14140 type
= v4si_ftype_v4si
;
14143 type
= v8hi_ftype_v8hi
;
14146 type
= v16qi_ftype_v16qi
;
14149 type
= v4sf_ftype_v4sf
;
14152 type
= v2df_ftype_v2df
;
14155 gcc_unreachable ();
14158 def_builtin (d
->name
, type
, d
->code
);
14161 /* Initialize target builtin that implements
14162 targetm.vectorize.builtin_mask_for_load. */
14164 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
14165 v16qi_ftype_long_pcvoid
,
14166 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
14167 BUILT_IN_MD
, NULL
, NULL_TREE
);
14168 TREE_READONLY (decl
) = 1;
14169 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14170 altivec_builtin_mask_for_load
= decl
;
14172 /* Access to the vec_init patterns. */
14173 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
14174 integer_type_node
, integer_type_node
,
14175 integer_type_node
, NULL_TREE
);
14176 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
14178 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
14179 short_integer_type_node
,
14180 short_integer_type_node
,
14181 short_integer_type_node
,
14182 short_integer_type_node
,
14183 short_integer_type_node
,
14184 short_integer_type_node
,
14185 short_integer_type_node
, NULL_TREE
);
14186 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
14188 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
14189 char_type_node
, char_type_node
,
14190 char_type_node
, char_type_node
,
14191 char_type_node
, char_type_node
,
14192 char_type_node
, char_type_node
,
14193 char_type_node
, char_type_node
,
14194 char_type_node
, char_type_node
,
14195 char_type_node
, char_type_node
,
14196 char_type_node
, NULL_TREE
);
14197 def_builtin ("__builtin_vec_init_v16qi", ftype
,
14198 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
14200 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
14201 float_type_node
, float_type_node
,
14202 float_type_node
, NULL_TREE
);
14203 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
14205 /* VSX builtins. */
14206 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
14207 double_type_node
, NULL_TREE
);
14208 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
14210 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
14211 intDI_type_node
, NULL_TREE
);
14212 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
14214 /* Access to the vec_set patterns. */
14215 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
14217 integer_type_node
, NULL_TREE
);
14218 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
14220 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
14222 integer_type_node
, NULL_TREE
);
14223 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
14225 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
14227 integer_type_node
, NULL_TREE
);
14228 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
14230 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
14232 integer_type_node
, NULL_TREE
);
14233 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
14235 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
14237 integer_type_node
, NULL_TREE
);
14238 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
14240 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
14242 integer_type_node
, NULL_TREE
);
14243 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
14245 /* Access to the vec_extract patterns. */
14246 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
14247 integer_type_node
, NULL_TREE
);
14248 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
14250 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
14251 integer_type_node
, NULL_TREE
);
14252 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
14254 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
14255 integer_type_node
, NULL_TREE
);
14256 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
14258 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
14259 integer_type_node
, NULL_TREE
);
14260 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
14262 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
14263 integer_type_node
, NULL_TREE
);
14264 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
14266 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
14267 integer_type_node
, NULL_TREE
);
14268 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
14272 htm_init_builtins (void)
14274 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14275 const struct builtin_description
*d
;
14279 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14281 tree op
[MAX_HTM_OPERANDS
], type
;
14282 HOST_WIDE_INT mask
= d
->mask
;
14283 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
14284 bool void_func
= (attr
& RS6000_BTC_VOID
);
14285 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
14287 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
14288 : unsigned_type_node
;
14290 if ((mask
& builtin_mask
) != mask
)
14292 if (TARGET_DEBUG_BUILTIN
)
14293 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
14299 if (TARGET_DEBUG_BUILTIN
)
14300 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
14301 (long unsigned) i
);
14305 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
14307 if (attr_args
== RS6000_BTC_UNARY
)
14308 op
[nopnds
++] = argtype
;
14309 else if (attr_args
== RS6000_BTC_BINARY
)
14311 op
[nopnds
++] = argtype
;
14312 op
[nopnds
++] = argtype
;
14314 else if (attr_args
== RS6000_BTC_TERNARY
)
14316 op
[nopnds
++] = argtype
;
14317 op
[nopnds
++] = argtype
;
14318 op
[nopnds
++] = argtype
;
14324 type
= build_function_type_list (op
[0], NULL_TREE
);
14327 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
14330 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
14333 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
14337 gcc_unreachable ();
14340 def_builtin (d
->name
, type
, d
->code
);
14344 /* Hash function for builtin functions with up to 3 arguments and a return
14347 builtin_hash_function (const void *hash_entry
)
14351 const struct builtin_hash_struct
*bh
=
14352 (const struct builtin_hash_struct
*) hash_entry
;
14354 for (i
= 0; i
< 4; i
++)
14356 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
14357 ret
= (ret
* 2) + bh
->uns_p
[i
];
14363 /* Compare builtin hash entries H1 and H2 for equivalence. */
14365 builtin_hash_eq (const void *h1
, const void *h2
)
14367 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
14368 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
14370 return ((p1
->mode
[0] == p2
->mode
[0])
14371 && (p1
->mode
[1] == p2
->mode
[1])
14372 && (p1
->mode
[2] == p2
->mode
[2])
14373 && (p1
->mode
[3] == p2
->mode
[3])
14374 && (p1
->uns_p
[0] == p2
->uns_p
[0])
14375 && (p1
->uns_p
[1] == p2
->uns_p
[1])
14376 && (p1
->uns_p
[2] == p2
->uns_p
[2])
14377 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
14380 /* Map types for builtin functions with an explicit return type and up to 3
14381 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14382 of the argument. */
14384 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
14385 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
14386 enum rs6000_builtins builtin
, const char *name
)
14388 struct builtin_hash_struct h
;
14389 struct builtin_hash_struct
*h2
;
14393 tree ret_type
= NULL_TREE
;
14394 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
14396 /* Create builtin_hash_table. */
14397 if (builtin_hash_table
== NULL
)
14398 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
14399 builtin_hash_eq
, NULL
);
14401 h
.type
= NULL_TREE
;
14402 h
.mode
[0] = mode_ret
;
14403 h
.mode
[1] = mode_arg0
;
14404 h
.mode
[2] = mode_arg1
;
14405 h
.mode
[3] = mode_arg2
;
14411 /* If the builtin is a type that produces unsigned results or takes unsigned
14412 arguments, and it is returned as a decl for the vectorizer (such as
14413 widening multiplies, permute), make sure the arguments and return value
14414 are type correct. */
14417 /* unsigned 1 argument functions. */
14418 case CRYPTO_BUILTIN_VSBOX
:
14419 case P8V_BUILTIN_VGBBD
:
14424 /* unsigned 2 argument functions. */
14425 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
14426 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
14427 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
14428 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
14429 case CRYPTO_BUILTIN_VCIPHER
:
14430 case CRYPTO_BUILTIN_VCIPHERLAST
:
14431 case CRYPTO_BUILTIN_VNCIPHER
:
14432 case CRYPTO_BUILTIN_VNCIPHERLAST
:
14433 case CRYPTO_BUILTIN_VPMSUMB
:
14434 case CRYPTO_BUILTIN_VPMSUMH
:
14435 case CRYPTO_BUILTIN_VPMSUMW
:
14436 case CRYPTO_BUILTIN_VPMSUMD
:
14437 case CRYPTO_BUILTIN_VPMSUM
:
14443 /* unsigned 3 argument functions. */
14444 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
14445 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
14446 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
14447 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
14448 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
14449 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
14450 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
14451 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
14452 case VSX_BUILTIN_VPERM_16QI_UNS
:
14453 case VSX_BUILTIN_VPERM_8HI_UNS
:
14454 case VSX_BUILTIN_VPERM_4SI_UNS
:
14455 case VSX_BUILTIN_VPERM_2DI_UNS
:
14456 case VSX_BUILTIN_XXSEL_16QI_UNS
:
14457 case VSX_BUILTIN_XXSEL_8HI_UNS
:
14458 case VSX_BUILTIN_XXSEL_4SI_UNS
:
14459 case VSX_BUILTIN_XXSEL_2DI_UNS
:
14460 case CRYPTO_BUILTIN_VPERMXOR
:
14461 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
14462 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
14463 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
14464 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
14465 case CRYPTO_BUILTIN_VSHASIGMAW
:
14466 case CRYPTO_BUILTIN_VSHASIGMAD
:
14467 case CRYPTO_BUILTIN_VSHASIGMA
:
14474 /* signed permute functions with unsigned char mask. */
14475 case ALTIVEC_BUILTIN_VPERM_16QI
:
14476 case ALTIVEC_BUILTIN_VPERM_8HI
:
14477 case ALTIVEC_BUILTIN_VPERM_4SI
:
14478 case ALTIVEC_BUILTIN_VPERM_4SF
:
14479 case ALTIVEC_BUILTIN_VPERM_2DI
:
14480 case ALTIVEC_BUILTIN_VPERM_2DF
:
14481 case VSX_BUILTIN_VPERM_16QI
:
14482 case VSX_BUILTIN_VPERM_8HI
:
14483 case VSX_BUILTIN_VPERM_4SI
:
14484 case VSX_BUILTIN_VPERM_4SF
:
14485 case VSX_BUILTIN_VPERM_2DI
:
14486 case VSX_BUILTIN_VPERM_2DF
:
14490 /* unsigned args, signed return. */
14491 case VSX_BUILTIN_XVCVUXDDP_UNS
:
14492 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
14496 /* signed args, unsigned return. */
14497 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
14498 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
14506 /* Figure out how many args are present. */
14507 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
14511 fatal_error ("internal error: builtin function %s had no type", name
);
14513 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
14514 if (!ret_type
&& h
.uns_p
[0])
14515 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
14518 fatal_error ("internal error: builtin function %s had an unexpected "
14519 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
14521 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
14522 arg_type
[i
] = NULL_TREE
;
14524 for (i
= 0; i
< num_args
; i
++)
14526 int m
= (int) h
.mode
[i
+1];
14527 int uns_p
= h
.uns_p
[i
+1];
14529 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
14530 if (!arg_type
[i
] && uns_p
)
14531 arg_type
[i
] = builtin_mode_to_type
[m
][0];
14534 fatal_error ("internal error: builtin function %s, argument %d "
14535 "had unexpected argument type %s", name
, i
,
14536 GET_MODE_NAME (m
));
14539 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
14540 if (*found
== NULL
)
14542 h2
= ggc_alloc_builtin_hash_struct ();
14544 *found
= (void *)h2
;
14546 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
14547 arg_type
[2], NULL_TREE
);
14550 return ((struct builtin_hash_struct
*)(*found
))->type
;
14554 rs6000_common_init_builtins (void)
14556 const struct builtin_description
*d
;
14559 tree opaque_ftype_opaque
= NULL_TREE
;
14560 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
14561 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
14562 tree v2si_ftype_qi
= NULL_TREE
;
14563 tree v2si_ftype_v2si_qi
= NULL_TREE
;
14564 tree v2si_ftype_int_qi
= NULL_TREE
;
14565 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14567 if (!TARGET_PAIRED_FLOAT
)
14569 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
14570 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
14573 /* Paired and SPE builtins are only available if you build a compiler with
14574 the appropriate options, so only create those builtins with the
14575 appropriate compiler option. Create Altivec and VSX builtins on machines
14576 with at least the general purpose extensions (970 and newer) to allow the
14577 use of the target attribute.. */
14579 if (TARGET_EXTRA_BUILTINS
)
14580 builtin_mask
|= RS6000_BTM_COMMON
;
14582 /* Add the ternary operators. */
14584 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14587 HOST_WIDE_INT mask
= d
->mask
;
14589 if ((mask
& builtin_mask
) != mask
)
14591 if (TARGET_DEBUG_BUILTIN
)
14592 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
14596 if (rs6000_overloaded_builtin_p (d
->code
))
14598 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
14599 type
= opaque_ftype_opaque_opaque_opaque
14600 = build_function_type_list (opaque_V4SI_type_node
,
14601 opaque_V4SI_type_node
,
14602 opaque_V4SI_type_node
,
14603 opaque_V4SI_type_node
,
14608 enum insn_code icode
= d
->icode
;
14611 if (TARGET_DEBUG_BUILTIN
)
14612 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
14618 if (icode
== CODE_FOR_nothing
)
14620 if (TARGET_DEBUG_BUILTIN
)
14621 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
14627 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
14628 insn_data
[icode
].operand
[1].mode
,
14629 insn_data
[icode
].operand
[2].mode
,
14630 insn_data
[icode
].operand
[3].mode
,
14634 def_builtin (d
->name
, type
, d
->code
);
14637 /* Add the binary operators. */
14639 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
14641 enum machine_mode mode0
, mode1
, mode2
;
14643 HOST_WIDE_INT mask
= d
->mask
;
14645 if ((mask
& builtin_mask
) != mask
)
14647 if (TARGET_DEBUG_BUILTIN
)
14648 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
14652 if (rs6000_overloaded_builtin_p (d
->code
))
14654 if (! (type
= opaque_ftype_opaque_opaque
))
14655 type
= opaque_ftype_opaque_opaque
14656 = build_function_type_list (opaque_V4SI_type_node
,
14657 opaque_V4SI_type_node
,
14658 opaque_V4SI_type_node
,
14663 enum insn_code icode
= d
->icode
;
14666 if (TARGET_DEBUG_BUILTIN
)
14667 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
14673 if (icode
== CODE_FOR_nothing
)
14675 if (TARGET_DEBUG_BUILTIN
)
14676 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
14682 mode0
= insn_data
[icode
].operand
[0].mode
;
14683 mode1
= insn_data
[icode
].operand
[1].mode
;
14684 mode2
= insn_data
[icode
].operand
[2].mode
;
14686 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
14688 if (! (type
= v2si_ftype_v2si_qi
))
14689 type
= v2si_ftype_v2si_qi
14690 = build_function_type_list (opaque_V2SI_type_node
,
14691 opaque_V2SI_type_node
,
14696 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
14697 && mode2
== QImode
)
14699 if (! (type
= v2si_ftype_int_qi
))
14700 type
= v2si_ftype_int_qi
14701 = build_function_type_list (opaque_V2SI_type_node
,
14708 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
14712 def_builtin (d
->name
, type
, d
->code
);
14715 /* Add the simple unary operators. */
14717 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
14719 enum machine_mode mode0
, mode1
;
14721 HOST_WIDE_INT mask
= d
->mask
;
14723 if ((mask
& builtin_mask
) != mask
)
14725 if (TARGET_DEBUG_BUILTIN
)
14726 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
14730 if (rs6000_overloaded_builtin_p (d
->code
))
14732 if (! (type
= opaque_ftype_opaque
))
14733 type
= opaque_ftype_opaque
14734 = build_function_type_list (opaque_V4SI_type_node
,
14735 opaque_V4SI_type_node
,
14740 enum insn_code icode
= d
->icode
;
14743 if (TARGET_DEBUG_BUILTIN
)
14744 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
14750 if (icode
== CODE_FOR_nothing
)
14752 if (TARGET_DEBUG_BUILTIN
)
14753 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
14759 mode0
= insn_data
[icode
].operand
[0].mode
;
14760 mode1
= insn_data
[icode
].operand
[1].mode
;
14762 if (mode0
== V2SImode
&& mode1
== QImode
)
14764 if (! (type
= v2si_ftype_qi
))
14765 type
= v2si_ftype_qi
14766 = build_function_type_list (opaque_V2SI_type_node
,
14772 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
14776 def_builtin (d
->name
, type
, d
->code
);
14781 rs6000_init_libfuncs (void)
14783 if (!TARGET_IEEEQUAD
)
14784 /* AIX/Darwin/64-bit Linux quad floating point routines. */
14785 if (!TARGET_XL_COMPAT
)
14787 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
14788 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
14789 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
14790 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
14792 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
14794 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
14795 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
14796 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
14797 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
14798 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
14799 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
14800 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
14802 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
14803 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
14804 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
14805 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
14806 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
14807 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
14808 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
14809 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
14812 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
14813 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
14817 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
14818 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
14819 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
14820 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
14824 /* 32-bit SVR4 quad floating point routines. */
14826 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
14827 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
14828 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
14829 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
14830 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
14831 if (TARGET_PPC_GPOPT
)
14832 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
14834 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
14835 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
14836 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
14837 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
14838 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
14839 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
14841 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
14842 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
14843 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
14844 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
14845 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
14846 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
14847 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
14848 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
14853 /* Expand a block clear operation, and return 1 if successful. Return 0
14854 if we should let the compiler generate normal code.
14856 operands[0] is the destination
14857 operands[1] is the length
14858 operands[3] is the alignment */
14861 expand_block_clear (rtx operands
[])
14863 rtx orig_dest
= operands
[0];
14864 rtx bytes_rtx
= operands
[1];
14865 rtx align_rtx
= operands
[3];
14866 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14867 HOST_WIDE_INT align
;
14868 HOST_WIDE_INT bytes
;
14873 /* If this is not a fixed size move, just call memcpy */
14877 /* This must be a fixed size alignment */
14878 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14879 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14881 /* Anything to clear? */
14882 bytes
= INTVAL (bytes_rtx
);
14886 /* Use the builtin memset after a point, to avoid huge code bloat.
14887 When optimize_size, avoid any significant code bloat; calling
14888 memset is about 4 instructions, so allow for one instruction to
14889 load zero and three to do clearing. */
14890 if (TARGET_ALTIVEC
&& align
>= 128)
14892 else if (TARGET_POWERPC64
&& align
>= 32)
14894 else if (TARGET_SPE
&& align
>= 64)
14899 if (optimize_size
&& bytes
> 3 * clear_step
)
14901 if (! optimize_size
&& bytes
> 8 * clear_step
)
14904 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
14906 enum machine_mode mode
= BLKmode
;
14909 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
14914 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
14919 else if (bytes
>= 8 && TARGET_POWERPC64
14920 /* 64-bit loads and stores require word-aligned
14922 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
14927 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
14928 { /* move 4 bytes */
14932 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
14933 { /* move 2 bytes */
14937 else /* move 1 byte at a time */
14943 dest
= adjust_address (orig_dest
, mode
, offset
);
14945 emit_move_insn (dest
, CONST0_RTX (mode
));
14952 /* Expand a block move operation, and return 1 if successful. Return 0
14953 if we should let the compiler generate normal code.
14955 operands[0] is the destination
14956 operands[1] is the source
14957 operands[2] is the length
14958 operands[3] is the alignment */
14960 #define MAX_MOVE_REG 4
14963 expand_block_move (rtx operands
[])
14965 rtx orig_dest
= operands
[0];
14966 rtx orig_src
= operands
[1];
14967 rtx bytes_rtx
= operands
[2];
14968 rtx align_rtx
= operands
[3];
14969 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14974 rtx stores
[MAX_MOVE_REG
];
14977 /* If this is not a fixed size move, just call memcpy */
14981 /* This must be a fixed size alignment */
14982 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14983 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14985 /* Anything to move? */
14986 bytes
= INTVAL (bytes_rtx
);
14990 if (bytes
> rs6000_block_move_inline_limit
)
14993 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
14996 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
14997 rtx (*mov
) (rtx
, rtx
);
14999 enum machine_mode mode
= BLKmode
;
15002 /* Altivec first, since it will be faster than a string move
15003 when it applies, and usually not significantly larger. */
15004 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
15008 gen_func
.mov
= gen_movv4si
;
15010 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
15014 gen_func
.mov
= gen_movv2si
;
15016 else if (TARGET_STRING
15017 && bytes
> 24 /* move up to 32 bytes at a time */
15023 && ! fixed_regs
[10]
15024 && ! fixed_regs
[11]
15025 && ! fixed_regs
[12])
15027 move_bytes
= (bytes
> 32) ? 32 : bytes
;
15028 gen_func
.movmemsi
= gen_movmemsi_8reg
;
15030 else if (TARGET_STRING
15031 && bytes
> 16 /* move up to 24 bytes at a time */
15037 && ! fixed_regs
[10])
15039 move_bytes
= (bytes
> 24) ? 24 : bytes
;
15040 gen_func
.movmemsi
= gen_movmemsi_6reg
;
15042 else if (TARGET_STRING
15043 && bytes
> 8 /* move up to 16 bytes at a time */
15047 && ! fixed_regs
[8])
15049 move_bytes
= (bytes
> 16) ? 16 : bytes
;
15050 gen_func
.movmemsi
= gen_movmemsi_4reg
;
15052 else if (bytes
>= 8 && TARGET_POWERPC64
15053 /* 64-bit loads and stores require word-aligned
15055 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
15059 gen_func
.mov
= gen_movdi
;
15061 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
15062 { /* move up to 8 bytes at a time */
15063 move_bytes
= (bytes
> 8) ? 8 : bytes
;
15064 gen_func
.movmemsi
= gen_movmemsi_2reg
;
15066 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15067 { /* move 4 bytes */
15070 gen_func
.mov
= gen_movsi
;
15072 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15073 { /* move 2 bytes */
15076 gen_func
.mov
= gen_movhi
;
15078 else if (TARGET_STRING
&& bytes
> 1)
15079 { /* move up to 4 bytes at a time */
15080 move_bytes
= (bytes
> 4) ? 4 : bytes
;
15081 gen_func
.movmemsi
= gen_movmemsi_1reg
;
15083 else /* move 1 byte at a time */
15087 gen_func
.mov
= gen_movqi
;
15090 src
= adjust_address (orig_src
, mode
, offset
);
15091 dest
= adjust_address (orig_dest
, mode
, offset
);
15093 if (mode
!= BLKmode
)
15095 rtx tmp_reg
= gen_reg_rtx (mode
);
15097 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
15098 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
15101 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
15104 for (i
= 0; i
< num_reg
; i
++)
15105 emit_insn (stores
[i
]);
15109 if (mode
== BLKmode
)
15111 /* Move the address into scratch registers. The movmemsi
15112 patterns require zero offset. */
15113 if (!REG_P (XEXP (src
, 0)))
15115 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
15116 src
= replace_equiv_address (src
, src_reg
);
15118 set_mem_size (src
, move_bytes
);
15120 if (!REG_P (XEXP (dest
, 0)))
15122 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
15123 dest
= replace_equiv_address (dest
, dest_reg
);
15125 set_mem_size (dest
, move_bytes
);
15127 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
15128 GEN_INT (move_bytes
& 31),
15137 /* Return a string to perform a load_multiple operation.
15138 operands[0] is the vector.
15139 operands[1] is the source address.
15140 operands[2] is the first destination register. */
15143 rs6000_output_load_multiple (rtx operands
[3])
15145 /* We have to handle the case where the pseudo used to contain the address
15146 is assigned to one of the output registers. */
15148 int words
= XVECLEN (operands
[0], 0);
15151 if (XVECLEN (operands
[0], 0) == 1)
15152 return "lwz %2,0(%1)";
15154 for (i
= 0; i
< words
; i
++)
15155 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
15156 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
15160 xop
[0] = GEN_INT (4 * (words
-1));
15161 xop
[1] = operands
[1];
15162 xop
[2] = operands
[2];
15163 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
15168 xop
[0] = GEN_INT (4 * (words
-1));
15169 xop
[1] = operands
[1];
15170 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
15171 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
15176 for (j
= 0; j
< words
; j
++)
15179 xop
[0] = GEN_INT (j
* 4);
15180 xop
[1] = operands
[1];
15181 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
15182 output_asm_insn ("lwz %2,%0(%1)", xop
);
15184 xop
[0] = GEN_INT (i
* 4);
15185 xop
[1] = operands
[1];
15186 output_asm_insn ("lwz %1,%0(%1)", xop
);
15191 return "lswi %2,%1,%N0";
15195 /* A validation routine: say whether CODE, a condition code, and MODE
15196 match. The other alternatives either don't make sense or should
15197 never be generated. */
15200 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
15202 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
15203 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
15204 && GET_MODE_CLASS (mode
) == MODE_CC
);
15206 /* These don't make sense. */
15207 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
15208 || mode
!= CCUNSmode
);
15210 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
15211 || mode
== CCUNSmode
);
15213 gcc_assert (mode
== CCFPmode
15214 || (code
!= ORDERED
&& code
!= UNORDERED
15215 && code
!= UNEQ
&& code
!= LTGT
15216 && code
!= UNGT
&& code
!= UNLT
15217 && code
!= UNGE
&& code
!= UNLE
));
15219 /* These should never be generated except for
15220 flag_finite_math_only. */
15221 gcc_assert (mode
!= CCFPmode
15222 || flag_finite_math_only
15223 || (code
!= LE
&& code
!= GE
15224 && code
!= UNEQ
&& code
!= LTGT
15225 && code
!= UNGT
&& code
!= UNLT
));
15227 /* These are invalid; the information is not there. */
15228 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
15232 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
15233 mask required to convert the result of a rotate insn into a shift
15234 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
15237 includes_lshift_p (rtx shiftop
, rtx andop
)
15239 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15241 shift_mask
<<= INTVAL (shiftop
);
15243 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15246 /* Similar, but for right shift. */
15249 includes_rshift_p (rtx shiftop
, rtx andop
)
15251 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15253 shift_mask
>>= INTVAL (shiftop
);
15255 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15258 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
15259 to perform a left shift. It must have exactly SHIFTOP least
15260 significant 0's, then one or more 1's, then zero or more 0's. */
15263 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
15265 if (GET_CODE (andop
) == CONST_INT
)
15267 HOST_WIDE_INT c
, lsb
, shift_mask
;
15269 c
= INTVAL (andop
);
15270 if (c
== 0 || c
== ~0)
15274 shift_mask
<<= INTVAL (shiftop
);
15276 /* Find the least significant one bit. */
15279 /* It must coincide with the LSB of the shift mask. */
15280 if (-lsb
!= shift_mask
)
15283 /* Invert to look for the next transition (if any). */
15286 /* Remove the low group of ones (originally low group of zeros). */
15289 /* Again find the lsb, and check we have all 1's above. */
15297 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
15298 to perform a left shift. It must have SHIFTOP or more least
15299 significant 0's, with the remainder of the word 1's. */
15302 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
15304 if (GET_CODE (andop
) == CONST_INT
)
15306 HOST_WIDE_INT c
, lsb
, shift_mask
;
15309 shift_mask
<<= INTVAL (shiftop
);
15310 c
= INTVAL (andop
);
15312 /* Find the least significant one bit. */
15315 /* It must be covered by the shift mask.
15316 This test also rejects c == 0. */
15317 if ((lsb
& shift_mask
) == 0)
15320 /* Check we have all 1's above the transition, and reject all 1's. */
15321 return c
== -lsb
&& lsb
!= 1;
15327 /* Return 1 if operands will generate a valid arguments to rlwimi
15328 instruction for insert with right shift in 64-bit mode. The mask may
15329 not start on the first bit or stop on the last bit because wrap-around
15330 effects of instruction do not correspond to semantics of RTL insn. */
15333 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
15335 if (INTVAL (startop
) > 32
15336 && INTVAL (startop
) < 64
15337 && INTVAL (sizeop
) > 1
15338 && INTVAL (sizeop
) + INTVAL (startop
) < 64
15339 && INTVAL (shiftop
) > 0
15340 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
15341 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
15347 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
15348 for lfq and stfq insns iff the registers are hard registers. */
15351 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
15353 /* We might have been passed a SUBREG. */
15354 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
15357 /* We might have been passed non floating point registers. */
15358 if (!FP_REGNO_P (REGNO (reg1
))
15359 || !FP_REGNO_P (REGNO (reg2
)))
15362 return (REGNO (reg1
) == REGNO (reg2
) - 1);
15365 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
15366 addr1 and addr2 must be in consecutive memory locations
15367 (addr2 == addr1 + 8). */
15370 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
15373 unsigned int reg1
, reg2
;
15374 int offset1
, offset2
;
15376 /* The mems cannot be volatile. */
15377 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
15380 addr1
= XEXP (mem1
, 0);
15381 addr2
= XEXP (mem2
, 0);
15383 /* Extract an offset (if used) from the first addr. */
15384 if (GET_CODE (addr1
) == PLUS
)
15386 /* If not a REG, return zero. */
15387 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
15391 reg1
= REGNO (XEXP (addr1
, 0));
15392 /* The offset must be constant! */
15393 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
15395 offset1
= INTVAL (XEXP (addr1
, 1));
15398 else if (GET_CODE (addr1
) != REG
)
15402 reg1
= REGNO (addr1
);
15403 /* This was a simple (mem (reg)) expression. Offset is 0. */
15407 /* And now for the second addr. */
15408 if (GET_CODE (addr2
) == PLUS
)
15410 /* If not a REG, return zero. */
15411 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
15415 reg2
= REGNO (XEXP (addr2
, 0));
15416 /* The offset must be constant. */
15417 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
15419 offset2
= INTVAL (XEXP (addr2
, 1));
15422 else if (GET_CODE (addr2
) != REG
)
15426 reg2
= REGNO (addr2
);
15427 /* This was a simple (mem (reg)) expression. Offset is 0. */
15431 /* Both of these must have the same base register. */
15435 /* The offset for the second addr must be 8 more than the first addr. */
15436 if (offset2
!= offset1
+ 8)
15439 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
15446 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
15448 static bool eliminated
= false;
15451 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
15452 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
15455 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
15456 gcc_assert (mem
!= NULL_RTX
);
15460 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
15461 cfun
->machine
->sdmode_stack_slot
= mem
;
15467 if (TARGET_DEBUG_ADDR
)
15469 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
15470 GET_MODE_NAME (mode
));
15472 fprintf (stderr
, "\tNULL_RTX\n");
15480 /* Return the mode to be used for memory when a secondary memory
15481 location is needed. For SDmode values we need to use DDmode, in
15482 all other cases we can use the same mode. */
15484 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
15486 if (mode
== SDmode
)
15492 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
15494 /* Don't walk into types. */
15495 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
15497 *walk_subtrees
= 0;
15501 switch (TREE_CODE (*tp
))
15510 case VIEW_CONVERT_EXPR
:
15511 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
15521 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
15522 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
15523 only work on the traditional altivec registers, note if an altivec register
15526 static enum rs6000_reg_type
15527 register_to_reg_type (rtx reg
, bool *is_altivec
)
15529 HOST_WIDE_INT regno
;
15530 enum reg_class rclass
;
15532 if (GET_CODE (reg
) == SUBREG
)
15533 reg
= SUBREG_REG (reg
);
15536 return NO_REG_TYPE
;
15538 regno
= REGNO (reg
);
15539 if (regno
>= FIRST_PSEUDO_REGISTER
)
15541 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
15542 return PSEUDO_REG_TYPE
;
15544 regno
= true_regnum (reg
);
15545 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15546 return PSEUDO_REG_TYPE
;
15549 gcc_assert (regno
>= 0);
15551 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
15552 *is_altivec
= true;
15554 rclass
= rs6000_regno_regclass
[regno
];
15555 return reg_class_to_reg_type
[(int)rclass
];
15558 /* Helper function for rs6000_secondary_reload to return true if a move to a
15559 different register classe is really a simple move. */
15562 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
15563 enum rs6000_reg_type from_type
,
15564 enum machine_mode mode
)
15568 /* Add support for various direct moves available. In this function, we only
15569 look at cases where we don't need any extra registers, and one or more
15570 simple move insns are issued. At present, 32-bit integers are not allowed
15571 in FPR/VSX registers. Single precision binary floating is not a simple
15572 move because we need to convert to the single precision memory layout.
15573 The 4-byte SDmode can be moved. */
15574 size
= GET_MODE_SIZE (mode
);
15575 if (TARGET_DIRECT_MOVE
15576 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
15577 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15578 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15581 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
15582 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
15583 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15586 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
15587 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
15588 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15594 /* Power8 helper function for rs6000_secondary_reload, handle all of the
15595 special direct moves that involve allocating an extra register, return the
15596 insn code of the helper function if there is such a function or
15597 CODE_FOR_nothing if not. */
15600 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
15601 enum rs6000_reg_type from_type
,
15602 enum machine_mode mode
,
15603 secondary_reload_info
*sri
,
15607 enum insn_code icode
= CODE_FOR_nothing
;
15609 int size
= GET_MODE_SIZE (mode
);
15611 if (TARGET_POWERPC64
)
15615 /* Handle moving 128-bit values from GPRs to VSX point registers on
15616 power8 when running in 64-bit mode using XXPERMDI to glue the two
15617 64-bit values back together. */
15618 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15620 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15621 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15624 /* Handle moving 128-bit values from VSX point registers to GPRs on
15625 power8 when running in 64-bit mode using XXPERMDI to get access to the
15626 bottom 64-bit value. */
15627 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15629 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15630 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15634 else if (mode
== SFmode
)
15636 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15638 cost
= 3; /* xscvdpspn, mfvsrd, and. */
15639 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15642 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15644 cost
= 2; /* mtvsrz, xscvspdpn. */
15645 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15650 if (TARGET_POWERPC64
&& size
== 16)
15652 /* Handle moving 128-bit values from GPRs to VSX point registers on
15653 power8 when running in 64-bit mode using XXPERMDI to glue the two
15654 64-bit values back together. */
15655 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15657 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15658 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15661 /* Handle moving 128-bit values from VSX point registers to GPRs on
15662 power8 when running in 64-bit mode using XXPERMDI to get access to the
15663 bottom 64-bit value. */
15664 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15666 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15667 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15671 else if (!TARGET_POWERPC64
&& size
== 8)
15673 /* Handle moving 64-bit values from GPRs to floating point registers on
15674 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
15675 values back together. Altivec register classes must be handled
15676 specially since a different instruction is used, and the secondary
15677 reload support requires a single instruction class in the scratch
15678 register constraint. However, right now TFmode is not allowed in
15679 Altivec registers, so the pattern will never match. */
15680 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
15682 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
15683 icode
= reg_addr
[mode
].reload_fpr_gpr
;
15687 if (icode
!= CODE_FOR_nothing
)
15692 sri
->icode
= icode
;
15693 sri
->extra_cost
= cost
;
15700 /* Return whether a move between two register classes can be done either
15701 directly (simple move) or via a pattern that uses a single extra temporary
15702 (using power8's direct move in this case. */
15705 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
15706 enum rs6000_reg_type from_type
,
15707 enum machine_mode mode
,
15708 secondary_reload_info
*sri
,
15711 /* Fall back to load/store reloads if either type is not a register. */
15712 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
15715 /* If we haven't allocated registers yet, assume the move can be done for the
15716 standard register types. */
15717 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
15718 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
15719 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
15722 /* Moves to the same set of registers is a simple move for non-specialized
15724 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
15727 /* Check whether a simple move can be done directly. */
15728 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
15732 sri
->icode
= CODE_FOR_nothing
;
15733 sri
->extra_cost
= 0;
15738 /* Now check if we can do it in a few steps. */
15739 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
15743 /* Inform reload about cases where moving X with a mode MODE to a register in
15744 RCLASS requires an extra scratch or immediate register. Return the class
15745 needed for the immediate register.
15747 For VSX and Altivec, we may need a register to convert sp+offset into
15750 For misaligned 64-bit gpr loads and stores we need a register to
15751 convert an offset address to indirect. */
15754 rs6000_secondary_reload (bool in_p
,
15756 reg_class_t rclass_i
,
15757 enum machine_mode mode
,
15758 secondary_reload_info
*sri
)
15760 enum reg_class rclass
= (enum reg_class
) rclass_i
;
15761 reg_class_t ret
= ALL_REGS
;
15762 enum insn_code icode
;
15763 bool default_p
= false;
15765 sri
->icode
= CODE_FOR_nothing
;
15767 ? reg_addr
[mode
].reload_load
15768 : reg_addr
[mode
].reload_store
);
15770 if (REG_P (x
) || register_operand (x
, mode
))
15772 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
15773 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
15774 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
15778 enum rs6000_reg_type exchange
= to_type
;
15779 to_type
= from_type
;
15780 from_type
= exchange
;
15783 /* Can we do a direct move of some sort? */
15784 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
15787 icode
= (enum insn_code
)sri
->icode
;
15793 /* Handle vector moves with reload helper functions. */
15794 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
15797 sri
->icode
= CODE_FOR_nothing
;
15798 sri
->extra_cost
= 0;
15800 if (GET_CODE (x
) == MEM
)
15802 rtx addr
= XEXP (x
, 0);
15804 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
15805 an extra register in that case, but it would need an extra
15806 register if the addressing is reg+reg or (reg+reg)&(-16). Special
15807 case load/store quad. */
15808 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
15810 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
15811 && GET_MODE_SIZE (mode
) == 16
15812 && quad_memory_operand (x
, mode
))
15814 sri
->icode
= icode
;
15815 sri
->extra_cost
= 2;
15818 else if (!legitimate_indirect_address_p (addr
, false)
15819 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15822 sri
->icode
= icode
;
15823 /* account for splitting the loads, and converting the
15824 address from reg+reg to reg. */
15825 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
15826 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
15829 /* Allow scalar loads to/from the traditional floating point
15830 registers, even if VSX memory is set. */
15831 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15832 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
15833 && (legitimate_indirect_address_p (addr
, false)
15834 || legitimate_indirect_address_p (addr
, false)
15835 || rs6000_legitimate_offset_address_p (mode
, addr
,
15839 /* Loads to and stores from vector registers can only do reg+reg
15840 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
15841 scalar modes loading up the traditional floating point registers
15842 to use offset addresses. */
15843 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
15844 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15846 if (!VECTOR_MEM_ALTIVEC_P (mode
)
15847 && GET_CODE (addr
) == AND
15848 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15849 && INTVAL (XEXP (addr
, 1)) == -16
15850 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
15851 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
15853 sri
->icode
= icode
;
15854 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
15857 else if (!legitimate_indirect_address_p (addr
, false)
15858 && (rclass
== NO_REGS
15859 || !legitimate_indexed_address_p (addr
, false)))
15861 sri
->icode
= icode
;
15862 sri
->extra_cost
= 1;
15865 icode
= CODE_FOR_nothing
;
15867 /* Any other loads, including to pseudo registers which haven't been
15868 assigned to a register yet, default to require a scratch
15872 sri
->icode
= icode
;
15873 sri
->extra_cost
= 2;
15876 else if (REG_P (x
))
15878 int regno
= true_regnum (x
);
15880 icode
= CODE_FOR_nothing
;
15881 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15885 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
15886 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
15887 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
15889 /* If memory is needed, use default_secondary_reload to create the
15891 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
15900 else if (TARGET_POWERPC64
15901 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15903 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
15905 rtx addr
= XEXP (x
, 0);
15906 rtx off
= address_offset (addr
);
15908 if (off
!= NULL_RTX
)
15910 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15911 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15913 /* We need a secondary reload when our legitimate_address_p
15914 says the address is good (as otherwise the entire address
15915 will be reloaded), and the offset is not a multiple of
15916 four or we have an address wrap. Address wrap will only
15917 occur for LO_SUMs since legitimate_offset_address_p
15918 rejects addresses for 16-byte mems that will wrap. */
15919 if (GET_CODE (addr
) == LO_SUM
15920 ? (1 /* legitimate_address_p allows any offset for lo_sum */
15921 && ((offset
& 3) != 0
15922 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
15923 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
15924 && (offset
& 3) != 0))
15927 sri
->icode
= CODE_FOR_reload_di_load
;
15929 sri
->icode
= CODE_FOR_reload_di_store
;
15930 sri
->extra_cost
= 2;
15939 else if (!TARGET_POWERPC64
15940 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15942 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
15944 rtx addr
= XEXP (x
, 0);
15945 rtx off
= address_offset (addr
);
15947 if (off
!= NULL_RTX
)
15949 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15950 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15952 /* We need a secondary reload when our legitimate_address_p
15953 says the address is good (as otherwise the entire address
15954 will be reloaded), and we have a wrap.
15956 legitimate_lo_sum_address_p allows LO_SUM addresses to
15957 have any offset so test for wrap in the low 16 bits.
15959 legitimate_offset_address_p checks for the range
15960 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
15961 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
15962 [0x7ff4,0x7fff] respectively, so test for the
15963 intersection of these ranges, [0x7ffc,0x7fff] and
15964 [0x7ff4,0x7ff7] respectively.
15966 Note that the address we see here may have been
15967 manipulated by legitimize_reload_address. */
15968 if (GET_CODE (addr
) == LO_SUM
15969 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
15970 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
15973 sri
->icode
= CODE_FOR_reload_si_load
;
15975 sri
->icode
= CODE_FOR_reload_si_store
;
15976 sri
->extra_cost
= 2;
15989 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
15991 gcc_assert (ret
!= ALL_REGS
);
15993 if (TARGET_DEBUG_ADDR
)
15996 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
15998 reg_class_names
[ret
],
15999 in_p
? "true" : "false",
16000 reg_class_names
[rclass
],
16001 GET_MODE_NAME (mode
));
16004 fprintf (stderr
, ", default secondary reload");
16006 if (sri
->icode
!= CODE_FOR_nothing
)
16007 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
16008 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
16010 fprintf (stderr
, "\n");
16018 /* Better tracing for rs6000_secondary_reload_inner. */
16021 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
16026 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
16028 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
16029 store_p
? "store" : "load");
16032 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
16034 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
16036 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16037 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
16041 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
16044 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
16045 gcc_unreachable ();
16048 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
16049 to SP+reg addressing. */
16052 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16054 int regno
= true_regnum (reg
);
16055 enum machine_mode mode
= GET_MODE (reg
);
16056 enum reg_class rclass
;
16058 rtx and_op2
= NULL_RTX
;
16061 rtx scratch_or_premodify
= scratch
;
16065 if (TARGET_DEBUG_ADDR
)
16066 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
16068 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16069 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16071 if (GET_CODE (mem
) != MEM
)
16072 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16074 rclass
= REGNO_REG_CLASS (regno
);
16075 addr
= XEXP (mem
, 0);
16079 /* GPRs can handle reg + small constant, all other addresses need to use
16080 the scratch register. */
16083 if (GET_CODE (addr
) == AND
)
16085 and_op2
= XEXP (addr
, 1);
16086 addr
= XEXP (addr
, 0);
16089 if (GET_CODE (addr
) == PRE_MODIFY
)
16091 scratch_or_premodify
= XEXP (addr
, 0);
16092 if (!REG_P (scratch_or_premodify
))
16093 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16095 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
16096 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16098 addr
= XEXP (addr
, 1);
16101 if (GET_CODE (addr
) == PLUS
16102 && (and_op2
!= NULL_RTX
16103 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16106 addr_op1
= XEXP (addr
, 0);
16107 addr_op2
= XEXP (addr
, 1);
16108 if (!legitimate_indirect_address_p (addr_op1
, false))
16109 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16111 if (!REG_P (addr_op2
)
16112 && (GET_CODE (addr_op2
) != CONST_INT
16113 || !satisfies_constraint_I (addr_op2
)))
16115 if (TARGET_DEBUG_ADDR
)
16118 "\nMove plus addr to register %s, mode = %s: ",
16119 rs6000_reg_names
[REGNO (scratch
)],
16120 GET_MODE_NAME (mode
));
16121 debug_rtx (addr_op2
);
16123 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16124 addr_op2
= scratch
;
16127 emit_insn (gen_rtx_SET (VOIDmode
,
16128 scratch_or_premodify
,
16129 gen_rtx_PLUS (Pmode
,
16133 addr
= scratch_or_premodify
;
16134 scratch_or_premodify
= scratch
;
16136 else if (!legitimate_indirect_address_p (addr
, false)
16137 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16140 if (TARGET_DEBUG_ADDR
)
16142 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16143 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16144 GET_MODE_NAME (mode
));
16147 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16148 addr
= scratch_or_premodify
;
16149 scratch_or_premodify
= scratch
;
16153 /* Float registers can do offset+reg addressing for scalar types. */
16155 if (legitimate_indirect_address_p (addr
, false) /* reg */
16156 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16157 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16158 && and_op2
== NULL_RTX
16159 && scratch_or_premodify
== scratch
16160 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
16163 /* If this isn't a legacy floating point load/store, fall through to the
16166 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
16167 addresses into a scratch register. */
16171 /* With float regs, we need to handle the AND ourselves, since we can't
16172 use the Altivec instruction with an implicit AND -16. Allow scalar
16173 loads to float registers to use reg+offset even if VSX. */
16174 if (GET_CODE (addr
) == AND
16175 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
16176 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
16177 || INTVAL (XEXP (addr
, 1)) != -16
16178 || !VECTOR_MEM_ALTIVEC_P (mode
)))
16180 and_op2
= XEXP (addr
, 1);
16181 addr
= XEXP (addr
, 0);
16184 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
16185 as the address later. */
16186 if (GET_CODE (addr
) == PRE_MODIFY
16187 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
16188 && (rclass
!= FLOAT_REGS
16189 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
16190 || and_op2
!= NULL_RTX
16191 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
16193 scratch_or_premodify
= XEXP (addr
, 0);
16194 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
16195 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16197 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
16198 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16200 addr
= XEXP (addr
, 1);
16203 if (legitimate_indirect_address_p (addr
, false) /* reg */
16204 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16205 || (GET_CODE (addr
) == AND
/* Altivec memory */
16206 && rclass
== ALTIVEC_REGS
16207 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16208 && INTVAL (XEXP (addr
, 1)) == -16
16209 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16210 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
16213 else if (GET_CODE (addr
) == PLUS
)
16215 addr_op1
= XEXP (addr
, 0);
16216 addr_op2
= XEXP (addr
, 1);
16217 if (!REG_P (addr_op1
))
16218 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16220 if (TARGET_DEBUG_ADDR
)
16222 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
16223 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16224 debug_rtx (addr_op2
);
16226 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16227 emit_insn (gen_rtx_SET (VOIDmode
,
16228 scratch_or_premodify
,
16229 gen_rtx_PLUS (Pmode
,
16232 addr
= scratch_or_premodify
;
16233 scratch_or_premodify
= scratch
;
16236 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
16237 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
16240 if (TARGET_DEBUG_ADDR
)
16242 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16243 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16244 GET_MODE_NAME (mode
));
16248 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16249 addr
= scratch_or_premodify
;
16250 scratch_or_premodify
= scratch
;
16254 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16259 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16262 /* If the original address involved a pre-modify that we couldn't use the VSX
16263 memory instruction with update, and we haven't taken care of already,
16264 store the address in the pre-modify register and use that as the
16266 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
16268 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
16269 addr
= scratch_or_premodify
;
16272 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
16273 memory instruction, recreate the AND now, including the clobber which is
16274 generated by the general ANDSI3/ANDDI3 patterns for the
16275 andi. instruction. */
16276 if (and_op2
!= NULL_RTX
)
16278 if (! legitimate_indirect_address_p (addr
, false))
16280 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
16284 if (TARGET_DEBUG_ADDR
)
16286 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
16287 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16288 debug_rtx (and_op2
);
16291 and_rtx
= gen_rtx_SET (VOIDmode
,
16293 gen_rtx_AND (Pmode
,
16297 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
16298 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
16299 gen_rtvec (2, and_rtx
, cc_clobber
)));
16303 /* Adjust the address if it changed. */
16304 if (addr
!= XEXP (mem
, 0))
16306 mem
= replace_equiv_address_nv (mem
, addr
);
16307 if (TARGET_DEBUG_ADDR
)
16308 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
16311 /* Now create the move. */
16313 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16315 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16320 /* Convert reloads involving 64-bit gprs and misaligned offset
16321 addressing, or multiple 32-bit gprs and offsets that are too large,
16322 to use indirect addressing. */
16325 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16327 int regno
= true_regnum (reg
);
16328 enum reg_class rclass
;
16330 rtx scratch_or_premodify
= scratch
;
16332 if (TARGET_DEBUG_ADDR
)
16334 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
16335 store_p
? "store" : "load");
16336 fprintf (stderr
, "reg:\n");
16338 fprintf (stderr
, "mem:\n");
16340 fprintf (stderr
, "scratch:\n");
16341 debug_rtx (scratch
);
16344 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
16345 gcc_assert (GET_CODE (mem
) == MEM
);
16346 rclass
= REGNO_REG_CLASS (regno
);
16347 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
16348 addr
= XEXP (mem
, 0);
16350 if (GET_CODE (addr
) == PRE_MODIFY
)
16352 scratch_or_premodify
= XEXP (addr
, 0);
16353 gcc_assert (REG_P (scratch_or_premodify
));
16354 addr
= XEXP (addr
, 1);
16356 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
16358 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16360 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
16362 /* Now create the move. */
16364 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16366 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16371 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
16372 this function has any SDmode references. If we are on a power7 or later, we
16373 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
16374 can load/store the value. */
16377 rs6000_alloc_sdmode_stack_slot (void)
16381 gimple_stmt_iterator gsi
;
16383 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
16384 /* We use a different approach for dealing with the secondary
16389 if (TARGET_NO_SDMODE_STACK
)
16393 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
16395 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
16398 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16399 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16405 /* Check for any SDmode parameters of the function. */
16406 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
16408 if (TREE_TYPE (t
) == error_mark_node
)
16411 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
16412 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
16414 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16415 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16423 rs6000_instantiate_decls (void)
16425 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
16426 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
16429 /* Given an rtx X being reloaded into a reg required to be
16430 in class CLASS, return the class of reg to actually use.
16431 In general this is just CLASS; but on some machines
16432 in some cases it is preferable to use a more restrictive class.
16434 On the RS/6000, we have to return NO_REGS when we want to reload a
16435 floating-point CONST_DOUBLE to force it to be copied to memory.
16437 We also don't want to reload integer values into floating-point
16438 registers if we can at all help it. In fact, this can
16439 cause reload to die, if it tries to generate a reload of CTR
16440 into a FP register and discovers it doesn't have the memory location
16443 ??? Would it be a good idea to have reload do the converse, that is
16444 try to reload floating modes into FP registers if possible?
16447 static enum reg_class
16448 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
16450 enum machine_mode mode
= GET_MODE (x
);
16452 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
16455 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
16456 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
16457 && easy_vector_constant (x
, mode
))
16458 return ALTIVEC_REGS
;
16460 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
16463 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
16464 return GENERAL_REGS
;
16466 /* For VSX, prefer the traditional registers for 64-bit values because we can
16467 use the non-VSX loads. Prefer the Altivec registers if Altivec is
16468 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
16469 prefer Altivec loads.. */
16470 if (rclass
== VSX_REGS
)
16472 if (GET_MODE_SIZE (mode
) <= 8)
16475 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
16476 return ALTIVEC_REGS
;
16484 /* Debug version of rs6000_preferred_reload_class. */
16485 static enum reg_class
16486 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
16488 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
16491 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
16493 reg_class_names
[ret
], reg_class_names
[rclass
],
16494 GET_MODE_NAME (GET_MODE (x
)));
16500 /* If we are copying between FP or AltiVec registers and anything else, we need
16501 a memory location. The exception is when we are targeting ppc64 and the
16502 move to/from fpr to gpr instructions are available. Also, under VSX, you
16503 can copy vector registers from the FP register set to the Altivec register
16504 set and vice versa. */
16507 rs6000_secondary_memory_needed (enum reg_class from_class
,
16508 enum reg_class to_class
,
16509 enum machine_mode mode
)
16511 enum rs6000_reg_type from_type
, to_type
;
16512 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
16513 || (to_class
== ALTIVEC_REGS
));
16515 /* If a simple/direct move is available, we don't need secondary memory */
16516 from_type
= reg_class_to_reg_type
[(int)from_class
];
16517 to_type
= reg_class_to_reg_type
[(int)to_class
];
16519 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
16520 (secondary_reload_info
*)0, altivec_p
))
16523 /* If we have a floating point or vector register class, we need to use
16524 memory to transfer the data. */
16525 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
16531 /* Debug version of rs6000_secondary_memory_needed. */
16533 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
16534 enum reg_class to_class
,
16535 enum machine_mode mode
)
16537 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
16540 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
16541 "to_class = %s, mode = %s\n",
16542 ret
? "true" : "false",
16543 reg_class_names
[from_class
],
16544 reg_class_names
[to_class
],
16545 GET_MODE_NAME (mode
));
16550 /* Return the register class of a scratch register needed to copy IN into
16551 or out of a register in RCLASS in MODE. If it can be done directly,
16552 NO_REGS is returned. */
16554 static enum reg_class
16555 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
16560 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
16562 && MACHOPIC_INDIRECT
16566 /* We cannot copy a symbolic operand directly into anything
16567 other than BASE_REGS for TARGET_ELF. So indicate that a
16568 register from BASE_REGS is needed as an intermediate
16571 On Darwin, pic addresses require a load from memory, which
16572 needs a base register. */
16573 if (rclass
!= BASE_REGS
16574 && (GET_CODE (in
) == SYMBOL_REF
16575 || GET_CODE (in
) == HIGH
16576 || GET_CODE (in
) == LABEL_REF
16577 || GET_CODE (in
) == CONST
))
16581 if (GET_CODE (in
) == REG
)
16583 regno
= REGNO (in
);
16584 if (regno
>= FIRST_PSEUDO_REGISTER
)
16586 regno
= true_regnum (in
);
16587 if (regno
>= FIRST_PSEUDO_REGISTER
)
16591 else if (GET_CODE (in
) == SUBREG
)
16593 regno
= true_regnum (in
);
16594 if (regno
>= FIRST_PSEUDO_REGISTER
)
16600 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
16602 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
16603 || (regno
>= 0 && INT_REGNO_P (regno
)))
16606 /* Constants, memory, and FP registers can go into FP registers. */
16607 if ((regno
== -1 || FP_REGNO_P (regno
))
16608 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
16609 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
16611 /* Memory, and FP/altivec registers can go into fp/altivec registers under
16612 VSX. However, for scalar variables, use the traditional floating point
16613 registers so that we can use offset+register addressing. */
16615 && (regno
== -1 || VSX_REGNO_P (regno
))
16616 && VSX_REG_CLASS_P (rclass
))
16618 if (GET_MODE_SIZE (mode
) < 16)
16624 /* Memory, and AltiVec registers can go into AltiVec registers. */
16625 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
16626 && rclass
== ALTIVEC_REGS
)
16629 /* We can copy among the CR registers. */
16630 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
16631 && regno
>= 0 && CR_REGNO_P (regno
))
16634 /* Otherwise, we need GENERAL_REGS. */
16635 return GENERAL_REGS
;
16638 /* Debug version of rs6000_secondary_reload_class. */
16639 static enum reg_class
16640 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
16641 enum machine_mode mode
, rtx in
)
16643 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
16645 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
16646 "mode = %s, input rtx:\n",
16647 reg_class_names
[ret
], reg_class_names
[rclass
],
16648 GET_MODE_NAME (mode
));
16654 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
16657 rs6000_cannot_change_mode_class (enum machine_mode from
,
16658 enum machine_mode to
,
16659 enum reg_class rclass
)
16661 unsigned from_size
= GET_MODE_SIZE (from
);
16662 unsigned to_size
= GET_MODE_SIZE (to
);
16664 if (from_size
!= to_size
)
16666 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
16668 if (reg_classes_intersect_p (xclass
, rclass
))
16670 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
16671 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
16673 /* Don't allow 64-bit types to overlap with 128-bit types that take a
16674 single register under VSX because the scalar part of the register
16675 is in the upper 64-bits, and not the lower 64-bits. Types like
16676 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
16677 IEEE floating point can't overlap, and neither can small
16680 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
16683 if (from_size
< 8 || to_size
< 8)
16686 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
16689 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
16698 if (TARGET_E500_DOUBLE
16699 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
16700 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
16701 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
16702 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
16703 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
16706 /* Since the VSX register set includes traditional floating point registers
16707 and altivec registers, just check for the size being different instead of
16708 trying to check whether the modes are vector modes. Otherwise it won't
16709 allow say DF and DI to change classes. For types like TFmode and TDmode
16710 that take 2 64-bit registers, rather than a single 128-bit register, don't
16711 allow subregs of those types to other 128 bit types. */
16712 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
16714 unsigned num_regs
= (from_size
+ 15) / 16;
16715 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
16716 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
16719 return (from_size
!= 8 && from_size
!= 16);
16722 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
16723 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
16726 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
16727 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
16733 /* Debug version of rs6000_cannot_change_mode_class. */
16735 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
16736 enum machine_mode to
,
16737 enum reg_class rclass
)
16739 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
16742 "rs6000_cannot_change_mode_class, return %s, from = %s, "
16743 "to = %s, rclass = %s\n",
16744 ret
? "true" : "false",
16745 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
16746 reg_class_names
[rclass
]);
16751 /* Return a string to do a move operation of 128 bits of data. */
16754 rs6000_output_move_128bit (rtx operands
[])
16756 rtx dest
= operands
[0];
16757 rtx src
= operands
[1];
16758 enum machine_mode mode
= GET_MODE (dest
);
16761 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
16762 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
16766 dest_regno
= REGNO (dest
);
16767 dest_gpr_p
= INT_REGNO_P (dest_regno
);
16768 dest_fp_p
= FP_REGNO_P (dest_regno
);
16769 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
16770 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
16775 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
16780 src_regno
= REGNO (src
);
16781 src_gpr_p
= INT_REGNO_P (src_regno
);
16782 src_fp_p
= FP_REGNO_P (src_regno
);
16783 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
16784 src_vsx_p
= src_fp_p
| src_vmx_p
;
16789 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
16792 /* Register moves. */
16793 if (dest_regno
>= 0 && src_regno
>= 0)
16800 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
16804 else if (TARGET_VSX
&& dest_vsx_p
)
16807 return "xxlor %x0,%x1,%x1";
16809 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
16813 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
16814 return "vor %0,%1,%1";
16816 else if (dest_fp_p
&& src_fp_p
)
16821 else if (dest_regno
>= 0 && MEM_P (src
))
16825 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16831 else if (TARGET_ALTIVEC
&& dest_vmx_p
16832 && altivec_indexed_or_indirect_operand (src
, mode
))
16833 return "lvx %0,%y1";
16835 else if (TARGET_VSX
&& dest_vsx_p
)
16837 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16838 return "lxvw4x %x0,%y1";
16840 return "lxvd2x %x0,%y1";
16843 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16844 return "lvx %0,%y1";
16846 else if (dest_fp_p
)
16851 else if (src_regno
>= 0 && MEM_P (dest
))
16855 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16856 return "stq %1,%0";
16861 else if (TARGET_ALTIVEC
&& src_vmx_p
16862 && altivec_indexed_or_indirect_operand (src
, mode
))
16863 return "stvx %1,%y0";
16865 else if (TARGET_VSX
&& src_vsx_p
)
16867 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16868 return "stxvw4x %x1,%y0";
16870 return "stxvd2x %x1,%y0";
16873 else if (TARGET_ALTIVEC
&& src_vmx_p
)
16874 return "stvx %1,%y0";
16881 else if (dest_regno
>= 0
16882 && (GET_CODE (src
) == CONST_INT
16883 || GET_CODE (src
) == CONST_DOUBLE
16884 || GET_CODE (src
) == CONST_VECTOR
))
16889 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
16890 return "xxlxor %x0,%x0,%x0";
16892 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16893 return output_vec_const_move (operands
);
16896 if (TARGET_DEBUG_ADDR
)
16898 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
16899 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
16902 gcc_unreachable ();
16906 /* Given a comparison operation, return the bit number in CCR to test. We
16907 know this is a valid comparison.
16909 SCC_P is 1 if this is for an scc. That means that %D will have been
16910 used instead of %C, so the bits will be in different places.
16912 Return -1 if OP isn't a valid comparison for some reason. */
16915 ccr_bit (rtx op
, int scc_p
)
16917 enum rtx_code code
= GET_CODE (op
);
16918 enum machine_mode cc_mode
;
16923 if (!COMPARISON_P (op
))
16926 reg
= XEXP (op
, 0);
16928 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
16930 cc_mode
= GET_MODE (reg
);
16931 cc_regnum
= REGNO (reg
);
16932 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
16934 validate_condition_mode (code
, cc_mode
);
16936 /* When generating a sCOND operation, only positive conditions are
16939 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
16940 || code
== GTU
|| code
== LTU
);
16945 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
16947 return base_bit
+ 2;
16948 case GT
: case GTU
: case UNLE
:
16949 return base_bit
+ 1;
16950 case LT
: case LTU
: case UNGE
:
16952 case ORDERED
: case UNORDERED
:
16953 return base_bit
+ 3;
16956 /* If scc, we will have done a cror to put the bit in the
16957 unordered position. So test that bit. For integer, this is ! LT
16958 unless this is an scc insn. */
16959 return scc_p
? base_bit
+ 3 : base_bit
;
16962 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
16965 gcc_unreachable ();
16969 /* Return the GOT register. */
16972 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
16974 /* The second flow pass currently (June 1999) can't update
16975 regs_ever_live without disturbing other parts of the compiler, so
16976 update it here to make the prolog/epilogue code happy. */
16977 if (!can_create_pseudo_p ()
16978 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
16979 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
16981 crtl
->uses_pic_offset_table
= 1;
16983 return pic_offset_table_rtx
;
16986 static rs6000_stack_t stack_info
;
16988 /* Function to init struct machine_function.
16989 This will be called, via a pointer variable,
16990 from push_function_context. */
16992 static struct machine_function
*
16993 rs6000_init_machine_status (void)
16995 stack_info
.reload_completed
= 0;
16996 return ggc_alloc_cleared_machine_function ();
16999 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
17002 extract_MB (rtx op
)
17005 unsigned long val
= INTVAL (op
);
17007 /* If the high bit is zero, the value is the first 1 bit we find
17009 if ((val
& 0x80000000) == 0)
17011 gcc_assert (val
& 0xffffffff);
17014 while (((val
<<= 1) & 0x80000000) == 0)
17019 /* If the high bit is set and the low bit is not, or the mask is all
17020 1's, the value is zero. */
17021 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
17024 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17027 while (((val
>>= 1) & 1) != 0)
17034 extract_ME (rtx op
)
17037 unsigned long val
= INTVAL (op
);
17039 /* If the low bit is zero, the value is the first 1 bit we find from
17041 if ((val
& 1) == 0)
17043 gcc_assert (val
& 0xffffffff);
17046 while (((val
>>= 1) & 1) == 0)
17052 /* If the low bit is set and the high bit is not, or the mask is all
17053 1's, the value is 31. */
17054 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
17057 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17060 while (((val
<<= 1) & 0x80000000) != 0)
17066 /* Locate some local-dynamic symbol still in use by this function
17067 so that we can print its name in some tls_ld pattern. */
17069 static const char *
17070 rs6000_get_some_local_dynamic_name (void)
17074 if (cfun
->machine
->some_ld_name
)
17075 return cfun
->machine
->some_ld_name
;
17077 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17079 && for_each_rtx (&PATTERN (insn
),
17080 rs6000_get_some_local_dynamic_name_1
, 0))
17081 return cfun
->machine
->some_ld_name
;
17083 gcc_unreachable ();
17086 /* Helper function for rs6000_get_some_local_dynamic_name. */
17089 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
17093 if (GET_CODE (x
) == SYMBOL_REF
)
17095 const char *str
= XSTR (x
, 0);
17096 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
17098 cfun
->machine
->some_ld_name
= str
;
17106 /* Write out a function code label. */
17109 rs6000_output_function_entry (FILE *file
, const char *fname
)
17111 if (fname
[0] != '.')
17113 switch (DEFAULT_ABI
)
17116 gcc_unreachable ();
17122 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
17132 RS6000_OUTPUT_BASENAME (file
, fname
);
17135 /* Print an operand. Recognize special options, documented below. */
17138 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
17139 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
17141 #define SMALL_DATA_RELOC "sda21"
17142 #define SMALL_DATA_REG 0
17146 print_operand (FILE *file
, rtx x
, int code
)
17149 unsigned HOST_WIDE_INT uval
;
17153 /* %a is output_address. */
17156 /* If constant, low-order 16 bits of constant, unsigned.
17157 Otherwise, write normally. */
17159 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
17161 print_operand (file
, x
, 0);
17165 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
17166 for 64-bit mask direction. */
17167 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
17170 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
17174 /* Like 'J' but get to the GT bit only. */
17175 gcc_assert (REG_P (x
));
17177 /* Bit 1 is GT bit. */
17178 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
17180 /* Add one for shift count in rlinm for scc. */
17181 fprintf (file
, "%d", i
+ 1);
17185 /* X is a CR register. Print the number of the EQ bit of the CR */
17186 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17187 output_operand_lossage ("invalid %%E value");
17189 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
17193 /* X is a CR register. Print the shift count needed to move it
17194 to the high-order four bits. */
17195 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17196 output_operand_lossage ("invalid %%f value");
17198 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
17202 /* Similar, but print the count for the rotate in the opposite
17204 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17205 output_operand_lossage ("invalid %%F value");
17207 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
17211 /* X is a constant integer. If it is negative, print "m",
17212 otherwise print "z". This is to make an aze or ame insn. */
17213 if (GET_CODE (x
) != CONST_INT
)
17214 output_operand_lossage ("invalid %%G value");
17215 else if (INTVAL (x
) >= 0)
17222 /* If constant, output low-order five bits. Otherwise, write
17225 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
17227 print_operand (file
, x
, 0);
17231 /* If constant, output low-order six bits. Otherwise, write
17234 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
17236 print_operand (file
, x
, 0);
17240 /* Print `i' if this is a constant, else nothing. */
17246 /* Write the bit number in CCR for jump. */
17247 i
= ccr_bit (x
, 0);
17249 output_operand_lossage ("invalid %%j code");
17251 fprintf (file
, "%d", i
);
17255 /* Similar, but add one for shift count in rlinm for scc and pass
17256 scc flag to `ccr_bit'. */
17257 i
= ccr_bit (x
, 1);
17259 output_operand_lossage ("invalid %%J code");
17261 /* If we want bit 31, write a shift count of zero, not 32. */
17262 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17266 /* X must be a constant. Write the 1's complement of the
17269 output_operand_lossage ("invalid %%k value");
17271 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
17275 /* X must be a symbolic constant on ELF. Write an
17276 expression suitable for an 'addi' that adds in the low 16
17277 bits of the MEM. */
17278 if (GET_CODE (x
) == CONST
)
17280 if (GET_CODE (XEXP (x
, 0)) != PLUS
17281 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
17282 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
17283 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
17284 output_operand_lossage ("invalid %%K value");
17286 print_operand_address (file
, x
);
17287 fputs ("@l", file
);
17290 /* %l is output_asm_label. */
17293 /* Write second word of DImode or DFmode reference. Works on register
17294 or non-indexed memory only. */
17296 fputs (reg_names
[REGNO (x
) + 1], file
);
17297 else if (MEM_P (x
))
17299 /* Handle possible auto-increment. Since it is pre-increment and
17300 we have already done it, we can just use an offset of word. */
17301 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17302 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17303 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17305 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17306 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17309 output_address (XEXP (adjust_address_nv (x
, SImode
,
17313 if (small_data_operand (x
, GET_MODE (x
)))
17314 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17315 reg_names
[SMALL_DATA_REG
]);
17320 /* MB value for a mask operand. */
17321 if (! mask_operand (x
, SImode
))
17322 output_operand_lossage ("invalid %%m value");
17324 fprintf (file
, "%d", extract_MB (x
));
17328 /* ME value for a mask operand. */
17329 if (! mask_operand (x
, SImode
))
17330 output_operand_lossage ("invalid %%M value");
17332 fprintf (file
, "%d", extract_ME (x
));
17335 /* %n outputs the negative of its operand. */
17338 /* Write the number of elements in the vector times 4. */
17339 if (GET_CODE (x
) != PARALLEL
)
17340 output_operand_lossage ("invalid %%N value");
17342 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
17346 /* Similar, but subtract 1 first. */
17347 if (GET_CODE (x
) != PARALLEL
)
17348 output_operand_lossage ("invalid %%O value");
17350 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
17354 /* X is a CONST_INT that is a power of two. Output the logarithm. */
17357 || (i
= exact_log2 (INTVAL (x
))) < 0)
17358 output_operand_lossage ("invalid %%p value");
17360 fprintf (file
, "%d", i
);
17364 /* The operand must be an indirect memory reference. The result
17365 is the register name. */
17366 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
17367 || REGNO (XEXP (x
, 0)) >= 32)
17368 output_operand_lossage ("invalid %%P value");
17370 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
17374 /* This outputs the logical code corresponding to a boolean
17375 expression. The expression may have one or both operands
17376 negated (if one, only the first one). For condition register
17377 logical operations, it will also treat the negated
17378 CR codes as NOTs, but not handle NOTs of them. */
17380 const char *const *t
= 0;
17382 enum rtx_code code
= GET_CODE (x
);
17383 static const char * const tbl
[3][3] = {
17384 { "and", "andc", "nor" },
17385 { "or", "orc", "nand" },
17386 { "xor", "eqv", "xor" } };
17390 else if (code
== IOR
)
17392 else if (code
== XOR
)
17395 output_operand_lossage ("invalid %%q value");
17397 if (GET_CODE (XEXP (x
, 0)) != NOT
)
17401 if (GET_CODE (XEXP (x
, 1)) == NOT
)
17412 if (! TARGET_MFCRF
)
17418 /* X is a CR register. Print the mask for `mtcrf'. */
17419 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17420 output_operand_lossage ("invalid %%R value");
17422 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
17426 /* Low 5 bits of 32 - value */
17428 output_operand_lossage ("invalid %%s value");
17430 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
17434 /* PowerPC64 mask position. All 0's is excluded.
17435 CONST_INT 32-bit mask is considered sign-extended so any
17436 transition must occur within the CONST_INT, not on the boundary. */
17437 if (! mask64_operand (x
, DImode
))
17438 output_operand_lossage ("invalid %%S value");
17442 if (uval
& 1) /* Clear Left */
17444 #if HOST_BITS_PER_WIDE_INT > 64
17445 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17449 else /* Clear Right */
17452 #if HOST_BITS_PER_WIDE_INT > 64
17453 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17459 gcc_assert (i
>= 0);
17460 fprintf (file
, "%d", i
);
17464 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
17465 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
17467 /* Bit 3 is OV bit. */
17468 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
17470 /* If we want bit 31, write a shift count of zero, not 32. */
17471 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17475 /* Print the symbolic name of a branch target register. */
17476 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
17477 && REGNO (x
) != CTR_REGNO
))
17478 output_operand_lossage ("invalid %%T value");
17479 else if (REGNO (x
) == LR_REGNO
)
17480 fputs ("lr", file
);
17482 fputs ("ctr", file
);
17486 /* High-order 16 bits of constant for use in unsigned operand. */
17488 output_operand_lossage ("invalid %%u value");
17490 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17491 (INTVAL (x
) >> 16) & 0xffff);
17495 /* High-order 16 bits of constant for use in signed operand. */
17497 output_operand_lossage ("invalid %%v value");
17499 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17500 (INTVAL (x
) >> 16) & 0xffff);
17504 /* Print `u' if this has an auto-increment or auto-decrement. */
17506 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
17507 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
17508 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
17513 /* Print the trap code for this operand. */
17514 switch (GET_CODE (x
))
17517 fputs ("eq", file
); /* 4 */
17520 fputs ("ne", file
); /* 24 */
17523 fputs ("lt", file
); /* 16 */
17526 fputs ("le", file
); /* 20 */
17529 fputs ("gt", file
); /* 8 */
17532 fputs ("ge", file
); /* 12 */
17535 fputs ("llt", file
); /* 2 */
17538 fputs ("lle", file
); /* 6 */
17541 fputs ("lgt", file
); /* 1 */
17544 fputs ("lge", file
); /* 5 */
17547 gcc_unreachable ();
17552 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
17555 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
17556 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
17558 print_operand (file
, x
, 0);
17562 /* MB value for a PowerPC64 rldic operand. */
17563 i
= clz_hwi (INTVAL (x
));
17565 fprintf (file
, "%d", i
);
17569 /* X is a FPR or Altivec register used in a VSX context. */
17570 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
17571 output_operand_lossage ("invalid %%x value");
17574 int reg
= REGNO (x
);
17575 int vsx_reg
= (FP_REGNO_P (reg
)
17577 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
17579 #ifdef TARGET_REGNAMES
17580 if (TARGET_REGNAMES
)
17581 fprintf (file
, "%%vs%d", vsx_reg
);
17584 fprintf (file
, "%d", vsx_reg
);
17590 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
17591 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
17592 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
17597 /* Like 'L', for third word of TImode/PTImode */
17599 fputs (reg_names
[REGNO (x
) + 2], file
);
17600 else if (MEM_P (x
))
17602 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17603 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17604 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17605 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17606 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17608 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
17609 if (small_data_operand (x
, GET_MODE (x
)))
17610 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17611 reg_names
[SMALL_DATA_REG
]);
17616 /* X is a SYMBOL_REF. Write out the name preceded by a
17617 period and without any trailing data in brackets. Used for function
17618 names. If we are configured for System V (or the embedded ABI) on
17619 the PowerPC, do not emit the period, since those systems do not use
17620 TOCs and the like. */
17621 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
17623 /* For macho, check to see if we need a stub. */
17626 const char *name
= XSTR (x
, 0);
17628 if (darwin_emit_branch_islands
17629 && MACHOPIC_INDIRECT
17630 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
17631 name
= machopic_indirection_name (x
, /*stub_p=*/true);
17633 assemble_name (file
, name
);
17635 else if (!DOT_SYMBOLS
)
17636 assemble_name (file
, XSTR (x
, 0));
17638 rs6000_output_function_entry (file
, XSTR (x
, 0));
17642 /* Like 'L', for last word of TImode/PTImode. */
17644 fputs (reg_names
[REGNO (x
) + 3], file
);
17645 else if (MEM_P (x
))
17647 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17648 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17649 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17650 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17651 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17653 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
17654 if (small_data_operand (x
, GET_MODE (x
)))
17655 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17656 reg_names
[SMALL_DATA_REG
]);
17660 /* Print AltiVec or SPE memory operand. */
17665 gcc_assert (MEM_P (x
));
17669 /* Ugly hack because %y is overloaded. */
17670 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
17671 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
17672 || GET_MODE (x
) == TFmode
17673 || GET_MODE (x
) == TImode
17674 || GET_MODE (x
) == PTImode
))
17676 /* Handle [reg]. */
17679 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
17682 /* Handle [reg+UIMM]. */
17683 else if (GET_CODE (tmp
) == PLUS
&&
17684 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
17688 gcc_assert (REG_P (XEXP (tmp
, 0)));
17690 x
= INTVAL (XEXP (tmp
, 1));
17691 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
17695 /* Fall through. Must be [reg+reg]. */
17697 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
17698 && GET_CODE (tmp
) == AND
17699 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
17700 && INTVAL (XEXP (tmp
, 1)) == -16)
17701 tmp
= XEXP (tmp
, 0);
17702 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
17703 && GET_CODE (tmp
) == PRE_MODIFY
)
17704 tmp
= XEXP (tmp
, 1);
17706 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
17709 if (!GET_CODE (tmp
) == PLUS
17710 || !REG_P (XEXP (tmp
, 0))
17711 || !REG_P (XEXP (tmp
, 1)))
17713 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
17717 if (REGNO (XEXP (tmp
, 0)) == 0)
17718 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
17719 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
17721 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
17722 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
17729 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
17730 else if (MEM_P (x
))
17732 /* We need to handle PRE_INC and PRE_DEC here, since we need to
17733 know the width from the mode. */
17734 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
17735 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
17736 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17737 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17738 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
17739 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17740 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17741 output_address (XEXP (XEXP (x
, 0), 1));
17743 output_address (XEXP (x
, 0));
17747 if (toc_relative_expr_p (x
, false))
17748 /* This hack along with a corresponding hack in
17749 rs6000_output_addr_const_extra arranges to output addends
17750 where the assembler expects to find them. eg.
17751 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
17752 without this hack would be output as "x@toc+4". We
17754 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17756 output_addr_const (file
, x
);
17761 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
17765 output_operand_lossage ("invalid %%xn code");
17769 /* Print the address of an operand. */
17772 print_operand_address (FILE *file
, rtx x
)
17775 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
17776 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
17777 || GET_CODE (x
) == LABEL_REF
)
17779 output_addr_const (file
, x
);
17780 if (small_data_operand (x
, GET_MODE (x
)))
17781 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17782 reg_names
[SMALL_DATA_REG
]);
17784 gcc_assert (!TARGET_TOC
);
17786 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17787 && REG_P (XEXP (x
, 1)))
17789 if (REGNO (XEXP (x
, 0)) == 0)
17790 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
17791 reg_names
[ REGNO (XEXP (x
, 0)) ]);
17793 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
17794 reg_names
[ REGNO (XEXP (x
, 1)) ]);
17796 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17797 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
17798 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
17799 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
17801 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17802 && CONSTANT_P (XEXP (x
, 1)))
17804 fprintf (file
, "lo16(");
17805 output_addr_const (file
, XEXP (x
, 1));
17806 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17810 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17811 && CONSTANT_P (XEXP (x
, 1)))
17813 output_addr_const (file
, XEXP (x
, 1));
17814 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17817 else if (toc_relative_expr_p (x
, false))
17819 /* This hack along with a corresponding hack in
17820 rs6000_output_addr_const_extra arranges to output addends
17821 where the assembler expects to find them. eg.
17823 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
17824 without this hack would be output as "x@toc+8@l(9)". We
17825 want "x+8@toc@l(9)". */
17826 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17827 if (GET_CODE (x
) == LO_SUM
)
17828 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
17830 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
17833 gcc_unreachable ();
17836 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
17839 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
17841 if (GET_CODE (x
) == UNSPEC
)
17842 switch (XINT (x
, 1))
17844 case UNSPEC_TOCREL
:
17845 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
17846 && REG_P (XVECEXP (x
, 0, 1))
17847 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
17848 output_addr_const (file
, XVECEXP (x
, 0, 0));
17849 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
17851 if (INTVAL (tocrel_offset
) >= 0)
17852 fprintf (file
, "+");
17853 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
17855 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
17858 assemble_name (file
, toc_label_name
);
17860 else if (TARGET_ELF
)
17861 fputs ("@toc", file
);
17865 case UNSPEC_MACHOPIC_OFFSET
:
17866 output_addr_const (file
, XVECEXP (x
, 0, 0));
17868 machopic_output_function_base_name (file
);
17875 /* Target hook for assembling integer objects. The PowerPC version has
17876 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
17877 is defined. It also needs to handle DI-mode objects on 64-bit
17881 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
17883 #ifdef RELOCATABLE_NEEDS_FIXUP
17884 /* Special handling for SI values. */
17885 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
17887 static int recurse
= 0;
17889 /* For -mrelocatable, we mark all addresses that need to be fixed up in
17890 the .fixup section. Since the TOC section is already relocated, we
17891 don't need to mark it here. We used to skip the text section, but it
17892 should never be valid for relocated addresses to be placed in the text
17894 if (TARGET_RELOCATABLE
17895 && in_section
!= toc_section
17897 && GET_CODE (x
) != CONST_INT
17898 && GET_CODE (x
) != CONST_DOUBLE
17904 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
17906 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
17907 fprintf (asm_out_file
, "\t.long\t(");
17908 output_addr_const (asm_out_file
, x
);
17909 fprintf (asm_out_file
, ")@fixup\n");
17910 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
17911 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
17912 fprintf (asm_out_file
, "\t.long\t");
17913 assemble_name (asm_out_file
, buf
);
17914 fprintf (asm_out_file
, "\n\t.previous\n");
17918 /* Remove initial .'s to turn a -mcall-aixdesc function
17919 address into the address of the descriptor, not the function
17921 else if (GET_CODE (x
) == SYMBOL_REF
17922 && XSTR (x
, 0)[0] == '.'
17923 && DEFAULT_ABI
== ABI_AIX
)
17925 const char *name
= XSTR (x
, 0);
17926 while (*name
== '.')
17929 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
17933 #endif /* RELOCATABLE_NEEDS_FIXUP */
17934 return default_assemble_integer (x
, size
, aligned_p
);
17937 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
17938 /* Emit an assembler directive to set symbol visibility for DECL to
17939 VISIBILITY_TYPE. */
17942 rs6000_assemble_visibility (tree decl
, int vis
)
17947 /* Functions need to have their entry point symbol visibility set as
17948 well as their descriptor symbol visibility. */
17949 if (DEFAULT_ABI
== ABI_AIX
17951 && TREE_CODE (decl
) == FUNCTION_DECL
)
17953 static const char * const visibility_types
[] = {
17954 NULL
, "internal", "hidden", "protected"
17957 const char *name
, *type
;
17959 name
= ((* targetm
.strip_name_encoding
)
17960 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
17961 type
= visibility_types
[vis
];
17963 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
17964 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
17967 default_assemble_visibility (decl
, vis
);
17972 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
17974 /* Reversal of FP compares takes care -- an ordered compare
17975 becomes an unordered compare and vice versa. */
17976 if (mode
== CCFPmode
17977 && (!flag_finite_math_only
17978 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
17979 || code
== UNEQ
|| code
== LTGT
))
17980 return reverse_condition_maybe_unordered (code
);
17982 return reverse_condition (code
);
17985 /* Generate a compare for CODE. Return a brand-new rtx that
17986 represents the result of the compare. */
17989 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
17991 enum machine_mode comp_mode
;
17992 rtx compare_result
;
17993 enum rtx_code code
= GET_CODE (cmp
);
17994 rtx op0
= XEXP (cmp
, 0);
17995 rtx op1
= XEXP (cmp
, 1);
17997 if (FLOAT_MODE_P (mode
))
17998 comp_mode
= CCFPmode
;
17999 else if (code
== GTU
|| code
== LTU
18000 || code
== GEU
|| code
== LEU
)
18001 comp_mode
= CCUNSmode
;
18002 else if ((code
== EQ
|| code
== NE
)
18003 && unsigned_reg_p (op0
)
18004 && (unsigned_reg_p (op1
)
18005 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
18006 /* These are unsigned values, perhaps there will be a later
18007 ordering compare that can be shared with this one. */
18008 comp_mode
= CCUNSmode
;
18010 comp_mode
= CCmode
;
18012 /* If we have an unsigned compare, make sure we don't have a signed value as
18014 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
18015 && INTVAL (op1
) < 0)
18017 op0
= copy_rtx_if_shared (op0
);
18018 op1
= force_reg (GET_MODE (op0
), op1
);
18019 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
18022 /* First, the compare. */
18023 compare_result
= gen_reg_rtx (comp_mode
);
18025 /* E500 FP compare instructions on the GPRs. Yuck! */
18026 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18027 && FLOAT_MODE_P (mode
))
18029 rtx cmp
, or_result
, compare_result2
;
18030 enum machine_mode op_mode
= GET_MODE (op0
);
18033 if (op_mode
== VOIDmode
)
18034 op_mode
= GET_MODE (op1
);
18036 /* First reverse the condition codes that aren't directly supported. */
18044 code
= reverse_condition_maybe_unordered (code
);
18057 gcc_unreachable ();
18060 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
18061 This explains the following mess. */
18069 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18070 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
18071 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
18075 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18076 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
18077 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
18081 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18082 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
18083 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
18087 gcc_unreachable ();
18096 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18097 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
18098 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
18102 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18103 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
18104 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
18108 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18109 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
18110 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
18114 gcc_unreachable ();
18123 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18124 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
18125 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
18129 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18130 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
18131 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
18135 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18136 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
18137 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
18141 gcc_unreachable ();
18146 gcc_unreachable ();
18149 /* Synthesize LE and GE from LT/GT || EQ. */
18150 if (code
== LE
|| code
== GE
)
18154 compare_result2
= gen_reg_rtx (CCFPmode
);
18160 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18161 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
18162 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
18166 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18167 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
18168 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
18172 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18173 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
18174 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
18178 gcc_unreachable ();
18183 /* OR them together. */
18184 or_result
= gen_reg_rtx (CCFPmode
);
18185 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
18187 compare_result
= or_result
;
18190 code
= reverse_p
? NE
: EQ
;
18196 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
18197 CLOBBERs to match cmptf_internal2 pattern. */
18198 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
18199 && GET_MODE (op0
) == TFmode
18200 && !TARGET_IEEEQUAD
18201 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
18202 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
18204 gen_rtx_SET (VOIDmode
,
18206 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
18207 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18208 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18209 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18210 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18211 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18212 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18213 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18214 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18215 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
18216 else if (GET_CODE (op1
) == UNSPEC
18217 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
18219 rtx op1b
= XVECEXP (op1
, 0, 0);
18220 comp_mode
= CCEQmode
;
18221 compare_result
= gen_reg_rtx (CCEQmode
);
18223 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
18225 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
18228 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
18229 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
18232 /* Some kinds of FP comparisons need an OR operation;
18233 under flag_finite_math_only we don't bother. */
18234 if (FLOAT_MODE_P (mode
)
18235 && !flag_finite_math_only
18236 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
18237 && (code
== LE
|| code
== GE
18238 || code
== UNEQ
|| code
== LTGT
18239 || code
== UNGT
|| code
== UNLT
))
18241 enum rtx_code or1
, or2
;
18242 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
18243 rtx or_result
= gen_reg_rtx (CCEQmode
);
18247 case LE
: or1
= LT
; or2
= EQ
; break;
18248 case GE
: or1
= GT
; or2
= EQ
; break;
18249 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
18250 case LTGT
: or1
= LT
; or2
= GT
; break;
18251 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
18252 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
18253 default: gcc_unreachable ();
18255 validate_condition_mode (or1
, comp_mode
);
18256 validate_condition_mode (or2
, comp_mode
);
18257 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
18258 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
18259 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
18260 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
18262 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
18264 compare_result
= or_result
;
18268 validate_condition_mode (code
, GET_MODE (compare_result
));
18270 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
18274 /* Emit the RTL for an sISEL pattern. */
18277 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
18279 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
18283 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
18286 enum machine_mode op_mode
;
18287 enum rtx_code cond_code
;
18288 rtx result
= operands
[0];
18290 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
18292 rs6000_emit_sISEL (mode
, operands
);
18296 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
18297 cond_code
= GET_CODE (condition_rtx
);
18299 if (FLOAT_MODE_P (mode
)
18300 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18304 PUT_MODE (condition_rtx
, SImode
);
18305 t
= XEXP (condition_rtx
, 0);
18307 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
18309 if (cond_code
== NE
)
18310 emit_insn (gen_e500_flip_gt_bit (t
, t
));
18312 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
18316 if (cond_code
== NE
18317 || cond_code
== GE
|| cond_code
== LE
18318 || cond_code
== GEU
|| cond_code
== LEU
18319 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
18321 rtx not_result
= gen_reg_rtx (CCEQmode
);
18322 rtx not_op
, rev_cond_rtx
;
18323 enum machine_mode cc_mode
;
18325 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
18327 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
18328 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
18329 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
18330 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
18331 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
18334 op_mode
= GET_MODE (XEXP (operands
[1], 0));
18335 if (op_mode
== VOIDmode
)
18336 op_mode
= GET_MODE (XEXP (operands
[1], 1));
18338 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
18340 PUT_MODE (condition_rtx
, DImode
);
18341 convert_move (result
, condition_rtx
, 0);
18345 PUT_MODE (condition_rtx
, SImode
);
18346 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
18350 /* Emit a branch of kind CODE to location LOC. */
18353 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
18355 rtx condition_rtx
, loc_ref
;
18357 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
18358 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
18359 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
18360 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
18361 loc_ref
, pc_rtx
)));
18364 /* Return the string to output a conditional branch to LABEL, which is
18365 the operand template of the label, or NULL if the branch is really a
18366 conditional return.
18368 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
18369 condition code register and its mode specifies what kind of
18370 comparison we made.
18372 REVERSED is nonzero if we should reverse the sense of the comparison.
18374 INSN is the insn. */
18377 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
18379 static char string
[64];
18380 enum rtx_code code
= GET_CODE (op
);
18381 rtx cc_reg
= XEXP (op
, 0);
18382 enum machine_mode mode
= GET_MODE (cc_reg
);
18383 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
18384 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
18385 int really_reversed
= reversed
^ need_longbranch
;
18391 validate_condition_mode (code
, mode
);
18393 /* Work out which way this really branches. We could use
18394 reverse_condition_maybe_unordered here always but this
18395 makes the resulting assembler clearer. */
18396 if (really_reversed
)
18398 /* Reversal of FP compares takes care -- an ordered compare
18399 becomes an unordered compare and vice versa. */
18400 if (mode
== CCFPmode
)
18401 code
= reverse_condition_maybe_unordered (code
);
18403 code
= reverse_condition (code
);
18406 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
18408 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
18413 /* Opposite of GT. */
18422 gcc_unreachable ();
18428 /* Not all of these are actually distinct opcodes, but
18429 we distinguish them for clarity of the resulting assembler. */
18430 case NE
: case LTGT
:
18431 ccode
= "ne"; break;
18432 case EQ
: case UNEQ
:
18433 ccode
= "eq"; break;
18435 ccode
= "ge"; break;
18436 case GT
: case GTU
: case UNGT
:
18437 ccode
= "gt"; break;
18439 ccode
= "le"; break;
18440 case LT
: case LTU
: case UNLT
:
18441 ccode
= "lt"; break;
18442 case UNORDERED
: ccode
= "un"; break;
18443 case ORDERED
: ccode
= "nu"; break;
18444 case UNGE
: ccode
= "nl"; break;
18445 case UNLE
: ccode
= "ng"; break;
18447 gcc_unreachable ();
18450 /* Maybe we have a guess as to how likely the branch is. */
18452 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
18453 if (note
!= NULL_RTX
)
18455 /* PROB is the difference from 50%. */
18456 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
18458 /* Only hint for highly probable/improbable branches on newer
18459 cpus as static prediction overrides processor dynamic
18460 prediction. For older cpus we may as well always hint, but
18461 assume not taken for branches that are very close to 50% as a
18462 mispredicted taken branch is more expensive than a
18463 mispredicted not-taken branch. */
18464 if (rs6000_always_hint
18465 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
18466 && br_prob_note_reliable_p (note
)))
18468 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
18469 && ((prob
> 0) ^ need_longbranch
))
18477 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
18479 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
18481 /* We need to escape any '%' characters in the reg_names string.
18482 Assume they'd only be the first character.... */
18483 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
18485 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
18489 /* If the branch distance was too far, we may have to use an
18490 unconditional branch to go the distance. */
18491 if (need_longbranch
)
18492 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
18494 s
+= sprintf (s
, ",%s", label
);
18500 /* Return the string to flip the GT bit on a CR. */
18502 output_e500_flip_gt_bit (rtx dst
, rtx src
)
18504 static char string
[64];
18507 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
18508 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
18511 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
18512 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
18514 sprintf (string
, "crnot %d,%d", a
, b
);
18518 /* Return insn for VSX or Altivec comparisons. */
18521 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
18524 enum machine_mode mode
= GET_MODE (op0
);
18532 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
18542 mask
= gen_reg_rtx (mode
);
18543 emit_insn (gen_rtx_SET (VOIDmode
,
18545 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
18552 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
18553 DMODE is expected destination mode. This is a recursive function. */
18556 rs6000_emit_vector_compare (enum rtx_code rcode
,
18558 enum machine_mode dmode
)
18561 bool swap_operands
= false;
18562 bool try_again
= false;
18564 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
18565 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
18567 /* See if the comparison works as is. */
18568 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18576 swap_operands
= true;
18581 swap_operands
= true;
18589 /* Invert condition and try again.
18590 e.g., A != B becomes ~(A==B). */
18592 enum rtx_code rev_code
;
18593 enum insn_code nor_code
;
18596 rev_code
= reverse_condition_maybe_unordered (rcode
);
18597 if (rev_code
== UNKNOWN
)
18600 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
18601 if (nor_code
== CODE_FOR_nothing
)
18604 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
18608 mask
= gen_reg_rtx (dmode
);
18609 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
18617 /* Try GT/GTU/LT/LTU OR EQ */
18620 enum insn_code ior_code
;
18621 enum rtx_code new_code
;
18642 gcc_unreachable ();
18645 ior_code
= optab_handler (ior_optab
, dmode
);
18646 if (ior_code
== CODE_FOR_nothing
)
18649 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
18653 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
18657 mask
= gen_reg_rtx (dmode
);
18658 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
18676 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18681 /* You only get two chances. */
18685 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
18686 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
18687 operands for the relation operation COND. */
18690 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
18691 rtx cond
, rtx cc_op0
, rtx cc_op1
)
18693 enum machine_mode dest_mode
= GET_MODE (dest
);
18694 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
18695 enum rtx_code rcode
= GET_CODE (cond
);
18696 enum machine_mode cc_mode
= CCmode
;
18700 bool invert_move
= false;
18702 if (VECTOR_UNIT_NONE_P (dest_mode
))
18705 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
18706 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
18710 /* Swap operands if we can, and fall back to doing the operation as
18711 specified, and doing a NOR to invert the test. */
18717 /* Invert condition and try again.
18718 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
18719 invert_move
= true;
18720 rcode
= reverse_condition_maybe_unordered (rcode
);
18721 if (rcode
== UNKNOWN
)
18725 /* Mark unsigned tests with CCUNSmode. */
18730 cc_mode
= CCUNSmode
;
18737 /* Get the vector mask for the given relational operations. */
18738 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
18746 op_true
= op_false
;
18750 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
18751 CONST0_RTX (dest_mode
));
18752 emit_insn (gen_rtx_SET (VOIDmode
,
18754 gen_rtx_IF_THEN_ELSE (dest_mode
,
18761 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
18762 operands of the last comparison is nonzero/true, FALSE_COND if it
18763 is zero/false. Return 0 if the hardware has no such operation. */
18766 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18768 enum rtx_code code
= GET_CODE (op
);
18769 rtx op0
= XEXP (op
, 0);
18770 rtx op1
= XEXP (op
, 1);
18771 REAL_VALUE_TYPE c1
;
18772 enum machine_mode compare_mode
= GET_MODE (op0
);
18773 enum machine_mode result_mode
= GET_MODE (dest
);
18775 bool is_against_zero
;
18777 /* These modes should always match. */
18778 if (GET_MODE (op1
) != compare_mode
18779 /* In the isel case however, we can use a compare immediate, so
18780 op1 may be a small constant. */
18781 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
18783 if (GET_MODE (true_cond
) != result_mode
)
18785 if (GET_MODE (false_cond
) != result_mode
)
18788 /* Don't allow using floating point comparisons for integer results for
18790 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
18793 /* First, work out if the hardware can do this at all, or
18794 if it's too slow.... */
18795 if (!FLOAT_MODE_P (compare_mode
))
18798 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
18801 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
18802 && SCALAR_FLOAT_MODE_P (compare_mode
))
18805 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
18807 /* A floating-point subtract might overflow, underflow, or produce
18808 an inexact result, thus changing the floating-point flags, so it
18809 can't be generated if we care about that. It's safe if one side
18810 of the construct is zero, since then no subtract will be
18812 if (SCALAR_FLOAT_MODE_P (compare_mode
)
18813 && flag_trapping_math
&& ! is_against_zero
)
18816 /* Eliminate half of the comparisons by switching operands, this
18817 makes the remaining code simpler. */
18818 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
18819 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
18821 code
= reverse_condition_maybe_unordered (code
);
18823 true_cond
= false_cond
;
18827 /* UNEQ and LTGT take four instructions for a comparison with zero,
18828 it'll probably be faster to use a branch here too. */
18829 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
18832 if (GET_CODE (op1
) == CONST_DOUBLE
)
18833 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
18835 /* We're going to try to implement comparisons by performing
18836 a subtract, then comparing against zero. Unfortunately,
18837 Inf - Inf is NaN which is not zero, and so if we don't
18838 know that the operand is finite and the comparison
18839 would treat EQ different to UNORDERED, we can't do it. */
18840 if (HONOR_INFINITIES (compare_mode
)
18841 && code
!= GT
&& code
!= UNGE
18842 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
18843 /* Constructs of the form (a OP b ? a : b) are safe. */
18844 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
18845 || (! rtx_equal_p (op0
, true_cond
)
18846 && ! rtx_equal_p (op1
, true_cond
))))
18849 /* At this point we know we can use fsel. */
18851 /* Reduce the comparison to a comparison against zero. */
18852 if (! is_against_zero
)
18854 temp
= gen_reg_rtx (compare_mode
);
18855 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18856 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
18858 op1
= CONST0_RTX (compare_mode
);
18861 /* If we don't care about NaNs we can reduce some of the comparisons
18862 down to faster ones. */
18863 if (! HONOR_NANS (compare_mode
))
18869 true_cond
= false_cond
;
18882 /* Now, reduce everything down to a GE. */
18889 temp
= gen_reg_rtx (compare_mode
);
18890 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18895 temp
= gen_reg_rtx (compare_mode
);
18896 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
18901 temp
= gen_reg_rtx (compare_mode
);
18902 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18903 gen_rtx_NEG (compare_mode
,
18904 gen_rtx_ABS (compare_mode
, op0
))));
18909 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
18910 temp
= gen_reg_rtx (result_mode
);
18911 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18912 gen_rtx_IF_THEN_ELSE (result_mode
,
18913 gen_rtx_GE (VOIDmode
,
18915 true_cond
, false_cond
)));
18916 false_cond
= true_cond
;
18919 temp
= gen_reg_rtx (compare_mode
);
18920 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18925 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
18926 temp
= gen_reg_rtx (result_mode
);
18927 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18928 gen_rtx_IF_THEN_ELSE (result_mode
,
18929 gen_rtx_GE (VOIDmode
,
18931 true_cond
, false_cond
)));
18932 true_cond
= false_cond
;
18935 temp
= gen_reg_rtx (compare_mode
);
18936 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18941 gcc_unreachable ();
18944 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
18945 gen_rtx_IF_THEN_ELSE (result_mode
,
18946 gen_rtx_GE (VOIDmode
,
18948 true_cond
, false_cond
)));
18952 /* Same as above, but for ints (isel). */
18955 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18957 rtx condition_rtx
, cr
;
18958 enum machine_mode mode
= GET_MODE (dest
);
18959 enum rtx_code cond_code
;
18960 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
18963 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
18966 /* We still have to do the compare, because isel doesn't do a
18967 compare, it just looks at the CRx bits set by a previous compare
18969 condition_rtx
= rs6000_generate_compare (op
, mode
);
18970 cond_code
= GET_CODE (condition_rtx
);
18971 cr
= XEXP (condition_rtx
, 0);
18972 signedp
= GET_MODE (cr
) == CCmode
;
18974 isel_func
= (mode
== SImode
18975 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
18976 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
18980 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
18981 /* isel handles these directly. */
18985 /* We need to swap the sense of the comparison. */
18988 true_cond
= false_cond
;
18990 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
18995 false_cond
= force_reg (mode
, false_cond
);
18996 if (true_cond
!= const0_rtx
)
18997 true_cond
= force_reg (mode
, true_cond
);
18999 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
19005 output_isel (rtx
*operands
)
19007 enum rtx_code code
;
19009 code
= GET_CODE (operands
[1]);
19011 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
19013 gcc_assert (GET_CODE (operands
[2]) == REG
19014 && GET_CODE (operands
[3]) == REG
);
19015 PUT_CODE (operands
[1], reverse_condition (code
));
19016 return "isel %0,%3,%2,%j1";
19019 return "isel %0,%2,%3,%j1";
19023 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
19025 enum machine_mode mode
= GET_MODE (op0
);
19029 /* VSX/altivec have direct min/max insns. */
19030 if ((code
== SMAX
|| code
== SMIN
)
19031 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
19032 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
19034 emit_insn (gen_rtx_SET (VOIDmode
,
19036 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19040 if (code
== SMAX
|| code
== SMIN
)
19045 if (code
== SMAX
|| code
== UMAX
)
19046 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19047 op0
, op1
, mode
, 0);
19049 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19050 op1
, op0
, mode
, 0);
19051 gcc_assert (target
);
19052 if (target
!= dest
)
19053 emit_move_insn (dest
, target
);
19056 /* A subroutine of the atomic operation splitters. Jump to LABEL if
19057 COND is true. Mark the jump as unlikely to be taken. */
19060 emit_unlikely_jump (rtx cond
, rtx label
)
19062 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
19065 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
19066 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
19067 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
19070 /* A subroutine of the atomic operation splitters. Emit a load-locked
19071 instruction in MODE. For QI/HImode, possibly use a pattern than includes
19072 the zero_extend operation. */
19075 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
19077 rtx (*fn
) (rtx
, rtx
) = NULL
;
19082 fn
= gen_load_lockedqi
;
19085 fn
= gen_load_lockedhi
;
19088 if (GET_MODE (mem
) == QImode
)
19089 fn
= gen_load_lockedqi_si
;
19090 else if (GET_MODE (mem
) == HImode
)
19091 fn
= gen_load_lockedhi_si
;
19093 fn
= gen_load_lockedsi
;
19096 fn
= gen_load_lockeddi
;
19099 fn
= gen_load_lockedti
;
19102 gcc_unreachable ();
19104 emit_insn (fn (reg
, mem
));
19107 /* A subroutine of the atomic operation splitters. Emit a store-conditional
19108 instruction in MODE. */
19111 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
19113 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
19118 fn
= gen_store_conditionalqi
;
19121 fn
= gen_store_conditionalhi
;
19124 fn
= gen_store_conditionalsi
;
19127 fn
= gen_store_conditionaldi
;
19130 fn
= gen_store_conditionalti
;
19133 gcc_unreachable ();
19136 /* Emit sync before stwcx. to address PPC405 Erratum. */
19137 if (PPC405_ERRATUM77
)
19138 emit_insn (gen_hwsync ());
19140 emit_insn (fn (res
, mem
, val
));
19143 /* Expand barriers before and after a load_locked/store_cond sequence. */
19146 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
19148 rtx addr
= XEXP (mem
, 0);
19149 int strict_p
= (reload_in_progress
|| reload_completed
);
19151 if (!legitimate_indirect_address_p (addr
, strict_p
)
19152 && !legitimate_indexed_address_p (addr
, strict_p
))
19154 addr
= force_reg (Pmode
, addr
);
19155 mem
= replace_equiv_address_nv (mem
, addr
);
19160 case MEMMODEL_RELAXED
:
19161 case MEMMODEL_CONSUME
:
19162 case MEMMODEL_ACQUIRE
:
19164 case MEMMODEL_RELEASE
:
19165 case MEMMODEL_ACQ_REL
:
19166 emit_insn (gen_lwsync ());
19168 case MEMMODEL_SEQ_CST
:
19169 emit_insn (gen_hwsync ());
19172 gcc_unreachable ();
19178 rs6000_post_atomic_barrier (enum memmodel model
)
19182 case MEMMODEL_RELAXED
:
19183 case MEMMODEL_CONSUME
:
19184 case MEMMODEL_RELEASE
:
19186 case MEMMODEL_ACQUIRE
:
19187 case MEMMODEL_ACQ_REL
:
19188 case MEMMODEL_SEQ_CST
:
19189 emit_insn (gen_isync ());
19192 gcc_unreachable ();
19196 /* A subroutine of the various atomic expanders. For sub-word operations,
19197 we must adjust things to operate on SImode. Given the original MEM,
19198 return a new aligned memory. Also build and return the quantities by
19199 which to shift and mask. */
19202 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
19204 rtx addr
, align
, shift
, mask
, mem
;
19205 HOST_WIDE_INT shift_mask
;
19206 enum machine_mode mode
= GET_MODE (orig_mem
);
19208 /* For smaller modes, we have to implement this via SImode. */
19209 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
19211 addr
= XEXP (orig_mem
, 0);
19212 addr
= force_reg (GET_MODE (addr
), addr
);
19214 /* Aligned memory containing subword. Generate a new memory. We
19215 do not want any of the existing MEM_ATTR data, as we're now
19216 accessing memory outside the original object. */
19217 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
19218 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19219 mem
= gen_rtx_MEM (SImode
, align
);
19220 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
19221 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
19222 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
19224 /* Shift amount for subword relative to aligned word. */
19225 shift
= gen_reg_rtx (SImode
);
19226 addr
= gen_lowpart (SImode
, addr
);
19227 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
19228 if (WORDS_BIG_ENDIAN
)
19229 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
19230 shift
, 1, OPTAB_LIB_WIDEN
);
19233 /* Mask for insertion. */
19234 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
19235 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19241 /* A subroutine of the various atomic expanders. For sub-word operands,
19242 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
19245 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
19249 x
= gen_reg_rtx (SImode
);
19250 emit_insn (gen_rtx_SET (VOIDmode
, x
,
19251 gen_rtx_AND (SImode
,
19252 gen_rtx_NOT (SImode
, mask
),
19255 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
19260 /* A subroutine of the various atomic expanders. For sub-word operands,
19261 extract WIDE to NARROW via SHIFT. */
19264 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
19266 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
19267 wide
, 1, OPTAB_LIB_WIDEN
);
19268 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
19271 /* Expand an atomic compare and swap operation. */
19274 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
19276 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
19277 rtx label1
, label2
, x
, mask
, shift
;
19278 enum machine_mode mode
, orig_mode
;
19279 enum memmodel mod_s
, mod_f
;
19282 boolval
= operands
[0];
19283 retval
= operands
[1];
19285 oldval
= operands
[3];
19286 newval
= operands
[4];
19287 is_weak
= (INTVAL (operands
[5]) != 0);
19288 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
19289 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
19290 orig_mode
= mode
= GET_MODE (mem
);
19292 mask
= shift
= NULL_RTX
;
19293 if (mode
== QImode
|| mode
== HImode
)
19295 /* Before power8, we didn't have access to lbarx/lharx, so generate a
19296 lwarx and shift/mask operations. With power8, we need to do the
19297 comparison in SImode, but the store is still done in QI/HImode. */
19298 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
19300 if (!TARGET_SYNC_HI_QI
)
19302 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19304 /* Shift and mask OLDVAL into position with the word. */
19305 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
19306 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19308 /* Shift and mask NEWVAL into position within the word. */
19309 newval
= convert_modes (SImode
, mode
, newval
, 1);
19310 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
19311 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19314 /* Prepare to adjust the return value. */
19315 retval
= gen_reg_rtx (SImode
);
19318 else if (reg_overlap_mentioned_p (retval
, oldval
))
19319 oldval
= copy_to_reg (oldval
);
19321 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
19326 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19327 emit_label (XEXP (label1
, 0));
19329 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19331 emit_load_locked (mode
, retval
, mem
);
19336 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
19337 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19340 cond
= gen_reg_rtx (CCmode
);
19341 /* If we have TImode, synthesize a comparison. */
19342 if (mode
!= TImode
)
19343 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
19346 rtx xor1_result
= gen_reg_rtx (DImode
);
19347 rtx xor2_result
= gen_reg_rtx (DImode
);
19348 rtx or_result
= gen_reg_rtx (DImode
);
19349 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
19350 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
19351 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
19352 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
19354 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
19355 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
19356 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
19357 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
19360 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
19362 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19363 emit_unlikely_jump (x
, label2
);
19367 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
19369 emit_store_conditional (orig_mode
, cond
, mem
, x
);
19373 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19374 emit_unlikely_jump (x
, label1
);
19377 if (mod_f
!= MEMMODEL_RELAXED
)
19378 emit_label (XEXP (label2
, 0));
19380 rs6000_post_atomic_barrier (mod_s
);
19382 if (mod_f
== MEMMODEL_RELAXED
)
19383 emit_label (XEXP (label2
, 0));
19386 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
19387 else if (mode
!= GET_MODE (operands
[1]))
19388 convert_move (operands
[1], retval
, 1);
19390 /* In all cases, CR0 contains EQ on success, and NE on failure. */
19391 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
19392 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
19395 /* Expand an atomic exchange operation. */
19398 rs6000_expand_atomic_exchange (rtx operands
[])
19400 rtx retval
, mem
, val
, cond
;
19401 enum machine_mode mode
;
19402 enum memmodel model
;
19403 rtx label
, x
, mask
, shift
;
19405 retval
= operands
[0];
19408 model
= (enum memmodel
) INTVAL (operands
[3]);
19409 mode
= GET_MODE (mem
);
19411 mask
= shift
= NULL_RTX
;
19412 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
19414 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19416 /* Shift and mask VAL into position with the word. */
19417 val
= convert_modes (SImode
, mode
, val
, 1);
19418 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19419 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19421 /* Prepare to adjust the return value. */
19422 retval
= gen_reg_rtx (SImode
);
19426 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19428 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19429 emit_label (XEXP (label
, 0));
19431 emit_load_locked (mode
, retval
, mem
);
19435 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
19437 cond
= gen_reg_rtx (CCmode
);
19438 emit_store_conditional (mode
, cond
, mem
, x
);
19440 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19441 emit_unlikely_jump (x
, label
);
19443 rs6000_post_atomic_barrier (model
);
19446 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
19449 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
19450 to perform. MEM is the memory on which to operate. VAL is the second
19451 operand of the binary operator. BEFORE and AFTER are optional locations to
19452 return the value of MEM either before of after the operation. MODEL_RTX
19453 is a CONST_INT containing the memory model to use. */
19456 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
19457 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
19459 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
19460 enum machine_mode mode
= GET_MODE (mem
);
19461 enum machine_mode store_mode
= mode
;
19462 rtx label
, x
, cond
, mask
, shift
;
19463 rtx before
= orig_before
, after
= orig_after
;
19465 mask
= shift
= NULL_RTX
;
19466 /* On power8, we want to use SImode for the operation. On previous systems,
19467 use the operation in a subword and shift/mask to get the proper byte or
19469 if (mode
== QImode
|| mode
== HImode
)
19471 if (TARGET_SYNC_HI_QI
)
19473 val
= convert_modes (SImode
, mode
, val
, 1);
19475 /* Prepare to adjust the return value. */
19476 before
= gen_reg_rtx (SImode
);
19478 after
= gen_reg_rtx (SImode
);
19483 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19485 /* Shift and mask VAL into position with the word. */
19486 val
= convert_modes (SImode
, mode
, val
, 1);
19487 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19488 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19494 /* We've already zero-extended VAL. That is sufficient to
19495 make certain that it does not affect other bits. */
19500 /* If we make certain that all of the other bits in VAL are
19501 set, that will be sufficient to not affect other bits. */
19502 x
= gen_rtx_NOT (SImode
, mask
);
19503 x
= gen_rtx_IOR (SImode
, x
, val
);
19504 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
19511 /* These will all affect bits outside the field and need
19512 adjustment via MASK within the loop. */
19516 gcc_unreachable ();
19519 /* Prepare to adjust the return value. */
19520 before
= gen_reg_rtx (SImode
);
19522 after
= gen_reg_rtx (SImode
);
19523 store_mode
= mode
= SImode
;
19527 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19529 label
= gen_label_rtx ();
19530 emit_label (label
);
19531 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
19533 if (before
== NULL_RTX
)
19534 before
= gen_reg_rtx (mode
);
19536 emit_load_locked (mode
, before
, mem
);
19540 x
= expand_simple_binop (mode
, AND
, before
, val
,
19541 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19542 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
19546 after
= expand_simple_binop (mode
, code
, before
, val
,
19547 after
, 1, OPTAB_LIB_WIDEN
);
19553 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
19554 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19555 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
19557 else if (store_mode
!= mode
)
19558 x
= convert_modes (store_mode
, mode
, x
, 1);
19560 cond
= gen_reg_rtx (CCmode
);
19561 emit_store_conditional (store_mode
, cond
, mem
, x
);
19563 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19564 emit_unlikely_jump (x
, label
);
19566 rs6000_post_atomic_barrier (model
);
19570 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
19571 then do the calcuations in a SImode register. */
19573 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
19575 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
19577 else if (store_mode
!= mode
)
19579 /* QImode/HImode on machines with lbarx/lharx where we do the native
19580 operation and then do the calcuations in a SImode register. */
19582 convert_move (orig_before
, before
, 1);
19584 convert_move (orig_after
, after
, 1);
19586 else if (orig_after
&& after
!= orig_after
)
19587 emit_move_insn (orig_after
, after
);
19590 /* Emit instructions to move SRC to DST. Called by splitters for
19591 multi-register moves. It will emit at most one instruction for
19592 each register that is accessed; that is, it won't emit li/lis pairs
19593 (or equivalent for 64-bit code). One of SRC or DST must be a hard
19597 rs6000_split_multireg_move (rtx dst
, rtx src
)
19599 /* The register number of the first register being moved. */
19601 /* The mode that is to be moved. */
19602 enum machine_mode mode
;
19603 /* The mode that the move is being done in, and its size. */
19604 enum machine_mode reg_mode
;
19606 /* The number of registers that will be moved. */
19609 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
19610 mode
= GET_MODE (dst
);
19611 nregs
= hard_regno_nregs
[reg
][mode
];
19612 if (FP_REGNO_P (reg
))
19613 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
19614 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
19615 else if (ALTIVEC_REGNO_P (reg
))
19616 reg_mode
= V16QImode
;
19617 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
19620 reg_mode
= word_mode
;
19621 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
19623 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
19625 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
19627 /* Move register range backwards, if we might have destructive
19630 for (i
= nregs
- 1; i
>= 0; i
--)
19631 emit_insn (gen_rtx_SET (VOIDmode
,
19632 simplify_gen_subreg (reg_mode
, dst
, mode
,
19633 i
* reg_mode_size
),
19634 simplify_gen_subreg (reg_mode
, src
, mode
,
19635 i
* reg_mode_size
)));
19641 bool used_update
= false;
19642 rtx restore_basereg
= NULL_RTX
;
19644 if (MEM_P (src
) && INT_REGNO_P (reg
))
19648 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
19649 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
19652 breg
= XEXP (XEXP (src
, 0), 0);
19653 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
19654 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
19655 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
19656 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19657 src
= replace_equiv_address (src
, breg
);
19659 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
19661 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
19663 rtx basereg
= XEXP (XEXP (src
, 0), 0);
19666 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
19667 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
19668 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
19669 used_update
= true;
19672 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19673 XEXP (XEXP (src
, 0), 1)));
19674 src
= replace_equiv_address (src
, basereg
);
19678 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
19679 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
19680 src
= replace_equiv_address (src
, basereg
);
19684 breg
= XEXP (src
, 0);
19685 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
19686 breg
= XEXP (breg
, 0);
19688 /* If the base register we are using to address memory is
19689 also a destination reg, then change that register last. */
19691 && REGNO (breg
) >= REGNO (dst
)
19692 && REGNO (breg
) < REGNO (dst
) + nregs
)
19693 j
= REGNO (breg
) - REGNO (dst
);
19695 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
19699 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19700 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
19703 breg
= XEXP (XEXP (dst
, 0), 0);
19704 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19705 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
19706 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
19708 /* We have to update the breg before doing the store.
19709 Use store with update, if available. */
19713 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19714 emit_insn (TARGET_32BIT
19715 ? (TARGET_POWERPC64
19716 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
19717 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
19718 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
19719 used_update
= true;
19722 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19723 dst
= replace_equiv_address (dst
, breg
);
19725 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
19726 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19728 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
19730 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19733 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19734 emit_insn (gen_rtx_SET (VOIDmode
,
19735 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
19736 used_update
= true;
19739 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19740 XEXP (XEXP (dst
, 0), 1)));
19741 dst
= replace_equiv_address (dst
, basereg
);
19745 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19746 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
19747 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
19749 && REG_P (offsetreg
)
19750 && REGNO (basereg
) != REGNO (offsetreg
));
19751 if (REGNO (basereg
) == 0)
19753 rtx tmp
= offsetreg
;
19754 offsetreg
= basereg
;
19757 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
19758 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
19759 dst
= replace_equiv_address (dst
, basereg
);
19762 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19763 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
19766 for (i
= 0; i
< nregs
; i
++)
19768 /* Calculate index to next subword. */
19773 /* If compiler already emitted move of first word by
19774 store with update, no need to do anything. */
19775 if (j
== 0 && used_update
)
19778 emit_insn (gen_rtx_SET (VOIDmode
,
19779 simplify_gen_subreg (reg_mode
, dst
, mode
,
19780 j
* reg_mode_size
),
19781 simplify_gen_subreg (reg_mode
, src
, mode
,
19782 j
* reg_mode_size
)));
19784 if (restore_basereg
!= NULL_RTX
)
19785 emit_insn (restore_basereg
);
19790 /* This page contains routines that are used to determine what the
19791 function prologue and epilogue code will do and write them out. */
19796 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
19799 /* Return the first fixed-point register that is required to be
19800 saved. 32 if none. */
19803 first_reg_to_save (void)
19807 /* Find lowest numbered live register. */
19808 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
19809 if (save_reg_p (first_reg
))
19812 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
19813 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
19814 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
19815 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
19816 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
19817 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
19821 && crtl
->uses_pic_offset_table
19822 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
19823 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
19829 /* Similar, for FP regs. */
19832 first_fp_reg_to_save (void)
19836 /* Find lowest numbered live register. */
19837 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
19838 if (save_reg_p (first_reg
))
19844 /* Similar, for AltiVec regs. */
19847 first_altivec_reg_to_save (void)
19851 /* Stack frame remains as is unless we are in AltiVec ABI. */
19852 if (! TARGET_ALTIVEC_ABI
)
19853 return LAST_ALTIVEC_REGNO
+ 1;
19855 /* On Darwin, the unwind routines are compiled without
19856 TARGET_ALTIVEC, and use save_world to save/restore the
19857 altivec registers when necessary. */
19858 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19859 && ! TARGET_ALTIVEC
)
19860 return FIRST_ALTIVEC_REGNO
+ 20;
19862 /* Find lowest numbered live register. */
19863 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19864 if (save_reg_p (i
))
19870 /* Return a 32-bit mask of the AltiVec registers we need to set in
19871 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
19872 the 32-bit word is 0. */
19874 static unsigned int
19875 compute_vrsave_mask (void)
19877 unsigned int i
, mask
= 0;
19879 /* On Darwin, the unwind routines are compiled without
19880 TARGET_ALTIVEC, and use save_world to save/restore the
19881 call-saved altivec registers when necessary. */
19882 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19883 && ! TARGET_ALTIVEC
)
19886 /* First, find out if we use _any_ altivec registers. */
19887 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19888 if (df_regs_ever_live_p (i
))
19889 mask
|= ALTIVEC_REG_BIT (i
);
19894 /* Next, remove the argument registers from the set. These must
19895 be in the VRSAVE mask set by the caller, so we don't need to add
19896 them in again. More importantly, the mask we compute here is
19897 used to generate CLOBBERs in the set_vrsave insn, and we do not
19898 wish the argument registers to die. */
19899 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
19900 mask
&= ~ALTIVEC_REG_BIT (i
);
19902 /* Similarly, remove the return value from the set. */
19905 diddle_return_value (is_altivec_return_reg
, &yes
);
19907 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
19913 /* For a very restricted set of circumstances, we can cut down the
19914 size of prologues/epilogues by calling our own save/restore-the-world
19918 compute_save_world_info (rs6000_stack_t
*info_ptr
)
19920 info_ptr
->world_save_p
= 1;
19921 info_ptr
->world_save_p
19922 = (WORLD_SAVE_P (info_ptr
)
19923 && DEFAULT_ABI
== ABI_DARWIN
19924 && !cfun
->has_nonlocal_label
19925 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
19926 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
19927 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
19928 && info_ptr
->cr_save_p
);
19930 /* This will not work in conjunction with sibcalls. Make sure there
19931 are none. (This check is expensive, but seldom executed.) */
19932 if (WORLD_SAVE_P (info_ptr
))
19935 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
19936 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
19938 info_ptr
->world_save_p
= 0;
19943 if (WORLD_SAVE_P (info_ptr
))
19945 /* Even if we're not touching VRsave, make sure there's room on the
19946 stack for it, if it looks like we're calling SAVE_WORLD, which
19947 will attempt to save it. */
19948 info_ptr
->vrsave_size
= 4;
19950 /* If we are going to save the world, we need to save the link register too. */
19951 info_ptr
->lr_save_p
= 1;
19953 /* "Save" the VRsave register too if we're saving the world. */
19954 if (info_ptr
->vrsave_mask
== 0)
19955 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
19957 /* Because the Darwin register save/restore routines only handle
19958 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
19960 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
19961 && (info_ptr
->first_altivec_reg_save
19962 >= FIRST_SAVED_ALTIVEC_REGNO
));
19969 is_altivec_return_reg (rtx reg
, void *xyes
)
19971 bool *yes
= (bool *) xyes
;
19972 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
19977 /* Look for user-defined global regs in the range FIRST to LAST-1.
19978 We should not restore these, and so cannot use lmw or out-of-line
19979 restore functions if there are any. We also can't save them
19980 (well, emit frame notes for them), because frame unwinding during
19981 exception handling will restore saved registers. */
19984 global_regs_p (unsigned first
, unsigned last
)
19986 while (first
< last
)
19987 if (global_regs
[first
++])
19992 /* Determine the strategy for savings/restoring registers. */
19995 SAVRES_MULTIPLE
= 0x1,
19996 SAVE_INLINE_FPRS
= 0x2,
19997 SAVE_INLINE_GPRS
= 0x4,
19998 REST_INLINE_FPRS
= 0x8,
19999 REST_INLINE_GPRS
= 0x10,
20000 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
20001 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
20002 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
20003 SAVE_INLINE_VRS
= 0x100,
20004 REST_INLINE_VRS
= 0x200
20008 rs6000_savres_strategy (rs6000_stack_t
*info
,
20009 bool using_static_chain_p
)
20014 if (TARGET_MULTIPLE
20015 && !TARGET_POWERPC64
20016 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
20017 && info
->first_gp_reg_save
< 31
20018 && !global_regs_p (info
->first_gp_reg_save
, 32))
20019 strategy
|= SAVRES_MULTIPLE
;
20021 if (crtl
->calls_eh_return
20022 || cfun
->machine
->ra_need_lr
)
20023 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
20024 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
20025 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20027 if (info
->first_fp_reg_save
== 64
20028 /* The out-of-line FP routines use double-precision stores;
20029 we can't use those routines if we don't have such stores. */
20030 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
20031 || global_regs_p (info
->first_fp_reg_save
, 64))
20032 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20034 if (info
->first_gp_reg_save
== 32
20035 || (!(strategy
& SAVRES_MULTIPLE
)
20036 && global_regs_p (info
->first_gp_reg_save
, 32)))
20037 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20039 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
20040 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
20041 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20043 /* Define cutoff for using out-of-line functions to save registers. */
20044 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
20046 if (!optimize_size
)
20048 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20049 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20050 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20054 /* Prefer out-of-line restore if it will exit. */
20055 if (info
->first_fp_reg_save
> 61)
20056 strategy
|= SAVE_INLINE_FPRS
;
20057 if (info
->first_gp_reg_save
> 29)
20059 if (info
->first_fp_reg_save
== 64)
20060 strategy
|= SAVE_INLINE_GPRS
;
20062 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20064 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
20065 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20068 else if (DEFAULT_ABI
== ABI_DARWIN
)
20070 if (info
->first_fp_reg_save
> 60)
20071 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20072 if (info
->first_gp_reg_save
> 29)
20073 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20074 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20078 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
20079 if (info
->first_fp_reg_save
> 61)
20080 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20081 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20082 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20085 /* Don't bother to try to save things out-of-line if r11 is occupied
20086 by the static chain. It would require too much fiddling and the
20087 static chain is rarely used anyway. FPRs are saved w.r.t the stack
20088 pointer on Darwin, and AIX uses r1 or r12. */
20089 if (using_static_chain_p
20090 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
20091 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
20093 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20095 /* We can only use the out-of-line routines to restore if we've
20096 saved all the registers from first_fp_reg_save in the prologue.
20097 Otherwise, we risk loading garbage. */
20098 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
20102 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
20103 if (!save_reg_p (i
))
20105 strategy
|= REST_INLINE_FPRS
;
20110 /* If we are going to use store multiple, then don't even bother
20111 with the out-of-line routines, since the store-multiple
20112 instruction will always be smaller. */
20113 if ((strategy
& SAVRES_MULTIPLE
))
20114 strategy
|= SAVE_INLINE_GPRS
;
20116 /* info->lr_save_p isn't yet set if the only reason lr needs to be
20117 saved is an out-of-line save or restore. Set up the value for
20118 the next test (excluding out-of-line gpr restore). */
20119 lr_save_p
= (info
->lr_save_p
20120 || !(strategy
& SAVE_INLINE_GPRS
)
20121 || !(strategy
& SAVE_INLINE_FPRS
)
20122 || !(strategy
& SAVE_INLINE_VRS
)
20123 || !(strategy
& REST_INLINE_FPRS
)
20124 || !(strategy
& REST_INLINE_VRS
));
20126 /* The situation is more complicated with load multiple. We'd
20127 prefer to use the out-of-line routines for restores, since the
20128 "exit" out-of-line routines can handle the restore of LR and the
20129 frame teardown. However if doesn't make sense to use the
20130 out-of-line routine if that is the only reason we'd need to save
20131 LR, and we can't use the "exit" out-of-line gpr restore if we
20132 have saved some fprs; In those cases it is advantageous to use
20133 load multiple when available. */
20134 if ((strategy
& SAVRES_MULTIPLE
)
20136 || info
->first_fp_reg_save
!= 64))
20137 strategy
|= REST_INLINE_GPRS
;
20139 /* Saving CR interferes with the exit routines used on the SPE, so
20142 && info
->spe_64bit_regs_used
20143 && info
->cr_save_p
)
20144 strategy
|= REST_INLINE_GPRS
;
20146 /* We can only use load multiple or the out-of-line routines to
20147 restore if we've used store multiple or out-of-line routines
20148 in the prologue, i.e. if we've saved all the registers from
20149 first_gp_reg_save. Otherwise, we risk loading garbage. */
20150 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
20151 == SAVE_INLINE_GPRS
)
20155 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
20156 if (!save_reg_p (i
))
20158 strategy
|= REST_INLINE_GPRS
;
20163 if (TARGET_ELF
&& TARGET_64BIT
)
20165 if (!(strategy
& SAVE_INLINE_FPRS
))
20166 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20167 else if (!(strategy
& SAVE_INLINE_GPRS
)
20168 && info
->first_fp_reg_save
== 64)
20169 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
20171 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
20172 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
20174 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
20175 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20180 /* Calculate the stack information for the current function. This is
20181 complicated by having two separate calling sequences, the AIX calling
20182 sequence and the V.4 calling sequence.
20184 AIX (and Darwin/Mac OS X) stack frames look like:
20186 SP----> +---------------------------------------+
20187 | back chain to caller | 0 0
20188 +---------------------------------------+
20189 | saved CR | 4 8 (8-11)
20190 +---------------------------------------+
20192 +---------------------------------------+
20193 | reserved for compilers | 12 24
20194 +---------------------------------------+
20195 | reserved for binders | 16 32
20196 +---------------------------------------+
20197 | saved TOC pointer | 20 40
20198 +---------------------------------------+
20199 | Parameter save area (P) | 24 48
20200 +---------------------------------------+
20201 | Alloca space (A) | 24+P etc.
20202 +---------------------------------------+
20203 | Local variable space (L) | 24+P+A
20204 +---------------------------------------+
20205 | Float/int conversion temporary (X) | 24+P+A+L
20206 +---------------------------------------+
20207 | Save area for AltiVec registers (W) | 24+P+A+L+X
20208 +---------------------------------------+
20209 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
20210 +---------------------------------------+
20211 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
20212 +---------------------------------------+
20213 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
20214 +---------------------------------------+
20215 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
20216 +---------------------------------------+
20217 old SP->| back chain to caller's caller |
20218 +---------------------------------------+
20220 The required alignment for AIX configurations is two words (i.e., 8
20223 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
20225 SP----> +---------------------------------------+
20226 | Back chain to caller | 0
20227 +---------------------------------------+
20228 | Save area for CR | 8
20229 +---------------------------------------+
20231 +---------------------------------------+
20232 | Saved TOC pointer | 24
20233 +---------------------------------------+
20234 | Parameter save area (P) | 32
20235 +---------------------------------------+
20236 | Alloca space (A) | 32+P
20237 +---------------------------------------+
20238 | Local variable space (L) | 32+P+A
20239 +---------------------------------------+
20240 | Save area for AltiVec registers (W) | 32+P+A+L
20241 +---------------------------------------+
20242 | AltiVec alignment padding (Y) | 32+P+A+L+W
20243 +---------------------------------------+
20244 | Save area for GP registers (G) | 32+P+A+L+W+Y
20245 +---------------------------------------+
20246 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
20247 +---------------------------------------+
20248 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
20249 +---------------------------------------+
20252 V.4 stack frames look like:
20254 SP----> +---------------------------------------+
20255 | back chain to caller | 0
20256 +---------------------------------------+
20257 | caller's saved LR | 4
20258 +---------------------------------------+
20259 | Parameter save area (P) | 8
20260 +---------------------------------------+
20261 | Alloca space (A) | 8+P
20262 +---------------------------------------+
20263 | Varargs save area (V) | 8+P+A
20264 +---------------------------------------+
20265 | Local variable space (L) | 8+P+A+V
20266 +---------------------------------------+
20267 | Float/int conversion temporary (X) | 8+P+A+V+L
20268 +---------------------------------------+
20269 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
20270 +---------------------------------------+
20271 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
20272 +---------------------------------------+
20273 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
20274 +---------------------------------------+
20275 | SPE: area for 64-bit GP registers |
20276 +---------------------------------------+
20277 | SPE alignment padding |
20278 +---------------------------------------+
20279 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
20280 +---------------------------------------+
20281 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
20282 +---------------------------------------+
20283 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
20284 +---------------------------------------+
20285 old SP->| back chain to caller's caller |
20286 +---------------------------------------+
20288 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
20289 given. (But note below and in sysv4.h that we require only 8 and
20290 may round up the size of our stack frame anyways. The historical
20291 reason is early versions of powerpc-linux which didn't properly
20292 align the stack at program startup. A happy side-effect is that
20293 -mno-eabi libraries can be used with -meabi programs.)
20295 The EABI configuration defaults to the V.4 layout. However,
20296 the stack alignment requirements may differ. If -mno-eabi is not
20297 given, the required stack alignment is 8 bytes; if -mno-eabi is
20298 given, the required alignment is 16 bytes. (But see V.4 comment
20301 #ifndef ABI_STACK_BOUNDARY
20302 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
20305 static rs6000_stack_t
*
20306 rs6000_stack_info (void)
20308 rs6000_stack_t
*info_ptr
= &stack_info
;
20309 int reg_size
= TARGET_32BIT
? 4 : 8;
20314 HOST_WIDE_INT non_fixed_size
;
20315 bool using_static_chain_p
;
20317 if (reload_completed
&& info_ptr
->reload_completed
)
20320 memset (info_ptr
, 0, sizeof (*info_ptr
));
20321 info_ptr
->reload_completed
= reload_completed
;
20325 /* Cache value so we don't rescan instruction chain over and over. */
20326 if (cfun
->machine
->insn_chain_scanned_p
== 0)
20327 cfun
->machine
->insn_chain_scanned_p
20328 = spe_func_has_64bit_regs_p () + 1;
20329 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
20332 /* Select which calling sequence. */
20333 info_ptr
->abi
= DEFAULT_ABI
;
20335 /* Calculate which registers need to be saved & save area size. */
20336 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
20337 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
20338 even if it currently looks like we won't. Reload may need it to
20339 get at a constant; if so, it will have already created a constant
20340 pool entry for it. */
20341 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
20342 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
20343 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
20344 && crtl
->uses_const_pool
20345 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20346 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20348 first_gp
= info_ptr
->first_gp_reg_save
;
20350 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
20352 /* For the SPE, we have an additional upper 32-bits on each GPR.
20353 Ideally we should save the entire 64-bits only when the upper
20354 half is used in SIMD instructions. Since we only record
20355 registers live (not the size they are used in), this proves
20356 difficult because we'd have to traverse the instruction chain at
20357 the right time, taking reload into account. This is a real pain,
20358 so we opt to save the GPRs in 64-bits always if but one register
20359 gets used in 64-bits. Otherwise, all the registers in the frame
20360 get saved in 32-bits.
20362 So... since when we save all GPRs (except the SP) in 64-bits, the
20363 traditional GP save area will be empty. */
20364 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20365 info_ptr
->gp_size
= 0;
20367 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
20368 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
20370 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
20371 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
20372 - info_ptr
->first_altivec_reg_save
);
20374 /* Does this function call anything? */
20375 info_ptr
->calls_p
= (! crtl
->is_leaf
20376 || cfun
->machine
->ra_needs_full_frame
);
20378 /* Determine if we need to save the condition code registers. */
20379 if (df_regs_ever_live_p (CR2_REGNO
)
20380 || df_regs_ever_live_p (CR3_REGNO
)
20381 || df_regs_ever_live_p (CR4_REGNO
))
20383 info_ptr
->cr_save_p
= 1;
20384 if (DEFAULT_ABI
== ABI_V4
)
20385 info_ptr
->cr_size
= reg_size
;
20388 /* If the current function calls __builtin_eh_return, then we need
20389 to allocate stack space for registers that will hold data for
20390 the exception handler. */
20391 if (crtl
->calls_eh_return
)
20394 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
20397 /* SPE saves EH registers in 64-bits. */
20398 ehrd_size
= i
* (TARGET_SPE_ABI
20399 && info_ptr
->spe_64bit_regs_used
!= 0
20400 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
20405 /* In the ELFv2 ABI, we also need to allocate space for separate
20406 CR field save areas if the function calls __builtin_eh_return. */
20407 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
20409 /* This hard-codes that we have three call-saved CR fields. */
20410 ehcr_size
= 3 * reg_size
;
20411 /* We do *not* use the regular CR save mechanism. */
20412 info_ptr
->cr_save_p
= 0;
20417 /* Determine various sizes. */
20418 info_ptr
->reg_size
= reg_size
;
20419 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
20420 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
20421 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
20422 TARGET_ALTIVEC
? 16 : 8);
20423 if (FRAME_GROWS_DOWNWARD
)
20424 info_ptr
->vars_size
20425 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
20426 + info_ptr
->parm_size
,
20427 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
20428 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
20429 + info_ptr
->parm_size
);
20431 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20432 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
20434 info_ptr
->spe_gp_size
= 0;
20436 if (TARGET_ALTIVEC_ABI
)
20437 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20439 info_ptr
->vrsave_mask
= 0;
20441 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
20442 info_ptr
->vrsave_size
= 4;
20444 info_ptr
->vrsave_size
= 0;
20446 compute_save_world_info (info_ptr
);
20448 /* Calculate the offsets. */
20449 switch (DEFAULT_ABI
)
20453 gcc_unreachable ();
20458 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
20459 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
20461 if (TARGET_ALTIVEC_ABI
)
20463 info_ptr
->vrsave_save_offset
20464 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
20466 /* Align stack so vector save area is on a quadword boundary.
20467 The padding goes above the vectors. */
20468 if (info_ptr
->altivec_size
!= 0)
20469 info_ptr
->altivec_padding_size
20470 = info_ptr
->vrsave_save_offset
& 0xF;
20472 info_ptr
->altivec_padding_size
= 0;
20474 info_ptr
->altivec_save_offset
20475 = info_ptr
->vrsave_save_offset
20476 - info_ptr
->altivec_padding_size
20477 - info_ptr
->altivec_size
;
20478 gcc_assert (info_ptr
->altivec_size
== 0
20479 || info_ptr
->altivec_save_offset
% 16 == 0);
20481 /* Adjust for AltiVec case. */
20482 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
20485 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
20487 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
20488 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
20489 info_ptr
->lr_save_offset
= 2*reg_size
;
20493 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
20494 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
20495 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
20497 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20499 /* Align stack so SPE GPR save area is aligned on a
20500 double-word boundary. */
20501 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
20502 info_ptr
->spe_padding_size
20503 = 8 - (-info_ptr
->cr_save_offset
% 8);
20505 info_ptr
->spe_padding_size
= 0;
20507 info_ptr
->spe_gp_save_offset
20508 = info_ptr
->cr_save_offset
20509 - info_ptr
->spe_padding_size
20510 - info_ptr
->spe_gp_size
;
20512 /* Adjust for SPE case. */
20513 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
20515 else if (TARGET_ALTIVEC_ABI
)
20517 info_ptr
->vrsave_save_offset
20518 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
20520 /* Align stack so vector save area is on a quadword boundary. */
20521 if (info_ptr
->altivec_size
!= 0)
20522 info_ptr
->altivec_padding_size
20523 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
20525 info_ptr
->altivec_padding_size
= 0;
20527 info_ptr
->altivec_save_offset
20528 = info_ptr
->vrsave_save_offset
20529 - info_ptr
->altivec_padding_size
20530 - info_ptr
->altivec_size
;
20532 /* Adjust for AltiVec case. */
20533 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
20536 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
20537 info_ptr
->ehrd_offset
-= ehrd_size
;
20538 info_ptr
->lr_save_offset
= reg_size
;
20542 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
20543 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
20544 + info_ptr
->gp_size
20545 + info_ptr
->altivec_size
20546 + info_ptr
->altivec_padding_size
20547 + info_ptr
->spe_gp_size
20548 + info_ptr
->spe_padding_size
20551 + info_ptr
->cr_size
20552 + info_ptr
->vrsave_size
,
20555 non_fixed_size
= (info_ptr
->vars_size
20556 + info_ptr
->parm_size
20557 + info_ptr
->save_size
);
20559 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
20560 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
20562 /* Determine if we need to save the link register. */
20563 if (info_ptr
->calls_p
20564 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
20566 && !TARGET_PROFILE_KERNEL
)
20567 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
20568 #ifdef TARGET_RELOCATABLE
20569 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
20571 || rs6000_ra_ever_killed ())
20572 info_ptr
->lr_save_p
= 1;
20574 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
20575 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
20576 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
20577 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
20578 using_static_chain_p
);
20580 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
20581 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
20582 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
20583 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
20584 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
20585 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
20586 info_ptr
->lr_save_p
= 1;
20588 if (info_ptr
->lr_save_p
)
20589 df_set_regs_ever_live (LR_REGNO
, true);
20591 /* Determine if we need to allocate any stack frame:
20593 For AIX we need to push the stack if a frame pointer is needed
20594 (because the stack might be dynamically adjusted), if we are
20595 debugging, if we make calls, or if the sum of fp_save, gp_save,
20596 and local variables are more than the space needed to save all
20597 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
20598 + 18*8 = 288 (GPR13 reserved).
20600 For V.4 we don't have the stack cushion that AIX uses, but assume
20601 that the debugger can handle stackless frames. */
20603 if (info_ptr
->calls_p
)
20604 info_ptr
->push_p
= 1;
20606 else if (DEFAULT_ABI
== ABI_V4
)
20607 info_ptr
->push_p
= non_fixed_size
!= 0;
20609 else if (frame_pointer_needed
)
20610 info_ptr
->push_p
= 1;
20612 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
20613 info_ptr
->push_p
= 1;
20616 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
20618 /* Zero offsets if we're not saving those registers. */
20619 if (info_ptr
->fp_size
== 0)
20620 info_ptr
->fp_save_offset
= 0;
20622 if (info_ptr
->gp_size
== 0)
20623 info_ptr
->gp_save_offset
= 0;
20625 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
20626 info_ptr
->altivec_save_offset
= 0;
20628 /* Zero VRSAVE offset if not saved and restored. */
20629 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
20630 info_ptr
->vrsave_save_offset
= 0;
20632 if (! TARGET_SPE_ABI
20633 || info_ptr
->spe_64bit_regs_used
== 0
20634 || info_ptr
->spe_gp_size
== 0)
20635 info_ptr
->spe_gp_save_offset
= 0;
20637 if (! info_ptr
->lr_save_p
)
20638 info_ptr
->lr_save_offset
= 0;
20640 if (! info_ptr
->cr_save_p
)
20641 info_ptr
->cr_save_offset
= 0;
20646 /* Return true if the current function uses any GPRs in 64-bit SIMD
20650 spe_func_has_64bit_regs_p (void)
20654 /* Functions that save and restore all the call-saved registers will
20655 need to save/restore the registers in 64-bits. */
20656 if (crtl
->calls_eh_return
20657 || cfun
->calls_setjmp
20658 || crtl
->has_nonlocal_goto
)
20661 insns
= get_insns ();
20663 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
20669 /* FIXME: This should be implemented with attributes...
20671 (set_attr "spe64" "true")....then,
20672 if (get_spe64(insn)) return true;
20674 It's the only reliable way to do the stuff below. */
20676 i
= PATTERN (insn
);
20677 if (GET_CODE (i
) == SET
)
20679 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
20681 if (SPE_VECTOR_MODE (mode
))
20683 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
20693 debug_stack_info (rs6000_stack_t
*info
)
20695 const char *abi_string
;
20698 info
= rs6000_stack_info ();
20700 fprintf (stderr
, "\nStack information for function %s:\n",
20701 ((current_function_decl
&& DECL_NAME (current_function_decl
))
20702 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
20707 default: abi_string
= "Unknown"; break;
20708 case ABI_NONE
: abi_string
= "NONE"; break;
20709 case ABI_AIX
: abi_string
= "AIX"; break;
20710 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
20711 case ABI_DARWIN
: abi_string
= "Darwin"; break;
20712 case ABI_V4
: abi_string
= "V.4"; break;
20715 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
20717 if (TARGET_ALTIVEC_ABI
)
20718 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
20720 if (TARGET_SPE_ABI
)
20721 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
20723 if (info
->first_gp_reg_save
!= 32)
20724 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
20726 if (info
->first_fp_reg_save
!= 64)
20727 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
20729 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
20730 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
20731 info
->first_altivec_reg_save
);
20733 if (info
->lr_save_p
)
20734 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
20736 if (info
->cr_save_p
)
20737 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
20739 if (info
->vrsave_mask
)
20740 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
20743 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
20746 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
20748 if (info
->gp_save_offset
)
20749 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
20751 if (info
->fp_save_offset
)
20752 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
20754 if (info
->altivec_save_offset
)
20755 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
20756 info
->altivec_save_offset
);
20758 if (info
->spe_gp_save_offset
)
20759 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
20760 info
->spe_gp_save_offset
);
20762 if (info
->vrsave_save_offset
)
20763 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
20764 info
->vrsave_save_offset
);
20766 if (info
->lr_save_offset
)
20767 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
20769 if (info
->cr_save_offset
)
20770 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
20772 if (info
->varargs_save_offset
)
20773 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
20775 if (info
->total_size
)
20776 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20779 if (info
->vars_size
)
20780 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20783 if (info
->parm_size
)
20784 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
20786 if (info
->fixed_size
)
20787 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
20790 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
20792 if (info
->spe_gp_size
)
20793 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
20796 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
20798 if (info
->altivec_size
)
20799 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
20801 if (info
->vrsave_size
)
20802 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
20804 if (info
->altivec_padding_size
)
20805 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
20806 info
->altivec_padding_size
);
20808 if (info
->spe_padding_size
)
20809 fprintf (stderr
, "\tspe_padding_size = %5d\n",
20810 info
->spe_padding_size
);
20813 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
20815 if (info
->save_size
)
20816 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
20818 if (info
->reg_size
!= 4)
20819 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
20821 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
20823 fprintf (stderr
, "\n");
20827 rs6000_return_addr (int count
, rtx frame
)
20829 /* Currently we don't optimize very well between prolog and body
20830 code and for PIC code the code can be actually quite bad, so
20831 don't try to be too clever here. */
20833 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
20835 cfun
->machine
->ra_needs_full_frame
= 1;
20842 plus_constant (Pmode
,
20844 (gen_rtx_MEM (Pmode
,
20845 memory_address (Pmode
, frame
))),
20846 RETURN_ADDRESS_OFFSET
)));
20849 cfun
->machine
->ra_need_lr
= 1;
20850 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
20853 /* Say whether a function is a candidate for sibcall handling or not. */
20856 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
20861 fntype
= TREE_TYPE (decl
);
20863 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
20865 /* We can't do it if the called function has more vector parameters
20866 than the current function; there's nowhere to put the VRsave code. */
20867 if (TARGET_ALTIVEC_ABI
20868 && TARGET_ALTIVEC_VRSAVE
20869 && !(decl
&& decl
== current_function_decl
))
20871 function_args_iterator args_iter
;
20875 /* Functions with vector parameters are required to have a
20876 prototype, so the argument type info must be available
20878 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
20879 if (TREE_CODE (type
) == VECTOR_TYPE
20880 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20883 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
20884 if (TREE_CODE (type
) == VECTOR_TYPE
20885 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20892 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
20893 functions, because the callee may have a different TOC pointer to
20894 the caller and there's no way to ensure we restore the TOC when
20895 we return. With the secure-plt SYSV ABI we can't make non-local
20896 calls when -fpic/PIC because the plt call stubs use r30. */
20897 if (DEFAULT_ABI
== ABI_DARWIN
20898 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
20900 && !DECL_EXTERNAL (decl
)
20901 && (*targetm
.binds_local_p
) (decl
))
20902 || (DEFAULT_ABI
== ABI_V4
20903 && (!TARGET_SECURE_PLT
20906 && (*targetm
.binds_local_p
) (decl
)))))
20908 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
20910 if (!lookup_attribute ("longcall", attr_list
)
20911 || lookup_attribute ("shortcall", attr_list
))
20919 rs6000_ra_ever_killed (void)
20925 if (cfun
->is_thunk
)
20928 if (cfun
->machine
->lr_save_state
)
20929 return cfun
->machine
->lr_save_state
- 1;
20931 /* regs_ever_live has LR marked as used if any sibcalls are present,
20932 but this should not force saving and restoring in the
20933 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
20934 clobbers LR, so that is inappropriate. */
20936 /* Also, the prologue can generate a store into LR that
20937 doesn't really count, like this:
20940 bcl to set PIC register
20944 When we're called from the epilogue, we need to avoid counting
20945 this as a store. */
20947 push_topmost_sequence ();
20948 top
= get_insns ();
20949 pop_topmost_sequence ();
20950 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
20952 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
20958 if (!SIBLING_CALL_P (insn
))
20961 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
20963 else if (set_of (reg
, insn
) != NULL_RTX
20964 && !prologue_epilogue_contains (insn
))
20971 /* Emit instructions needed to load the TOC register.
20972 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
20973 a constant pool; or for SVR4 -fpic. */
20976 rs6000_emit_load_toc_table (int fromprolog
)
20979 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
20981 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
20984 rtx lab
, tmp1
, tmp2
, got
;
20986 lab
= gen_label_rtx ();
20987 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
20988 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20990 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
20992 got
= rs6000_got_sym ();
20993 tmp1
= tmp2
= dest
;
20996 tmp1
= gen_reg_rtx (Pmode
);
20997 tmp2
= gen_reg_rtx (Pmode
);
20999 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
21000 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
21001 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
21002 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
21004 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
21006 emit_insn (gen_load_toc_v4_pic_si ());
21007 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21009 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
21012 rtx temp0
= (fromprolog
21013 ? gen_rtx_REG (Pmode
, 0)
21014 : gen_reg_rtx (Pmode
));
21020 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21021 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21023 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
21024 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21026 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
21027 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21028 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
21034 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21035 lab
= gen_label_rtx ();
21036 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
21037 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21038 if (TARGET_LINK_STACK
)
21039 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
21040 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
21042 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
21044 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
21046 /* This is for AIX code running in non-PIC ELF32. */
21049 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21050 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21052 emit_insn (gen_elf_high (dest
, realsym
));
21053 emit_insn (gen_elf_low (dest
, dest
, realsym
));
21057 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21060 emit_insn (gen_load_toc_aix_si (dest
));
21062 emit_insn (gen_load_toc_aix_di (dest
));
21066 /* Emit instructions to restore the link register after determining where
21067 its value has been stored. */
21070 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
21072 rs6000_stack_t
*info
= rs6000_stack_info ();
21075 operands
[0] = source
;
21076 operands
[1] = scratch
;
21078 if (info
->lr_save_p
)
21080 rtx frame_rtx
= stack_pointer_rtx
;
21081 HOST_WIDE_INT sp_offset
= 0;
21084 if (frame_pointer_needed
21085 || cfun
->calls_alloca
21086 || info
->total_size
> 32767)
21088 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
21089 emit_move_insn (operands
[1], tmp
);
21090 frame_rtx
= operands
[1];
21092 else if (info
->push_p
)
21093 sp_offset
= info
->total_size
;
21095 tmp
= plus_constant (Pmode
, frame_rtx
,
21096 info
->lr_save_offset
+ sp_offset
);
21097 tmp
= gen_frame_mem (Pmode
, tmp
);
21098 emit_move_insn (tmp
, operands
[0]);
21101 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
21103 /* Freeze lr_save_p. We've just emitted rtl that depends on the
21104 state of lr_save_p so any change from here on would be a bug. In
21105 particular, stop rs6000_ra_ever_killed from considering the SET
21106 of lr we may have added just above. */
21107 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
21110 static GTY(()) alias_set_type set
= -1;
21113 get_TOC_alias_set (void)
21116 set
= new_alias_set ();
21120 /* This returns nonzero if the current function uses the TOC. This is
21121 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
21122 is generated by the ABI_V4 load_toc_* patterns. */
21129 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
21132 rtx pat
= PATTERN (insn
);
21135 if (GET_CODE (pat
) == PARALLEL
)
21136 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
21138 rtx sub
= XVECEXP (pat
, 0, i
);
21139 if (GET_CODE (sub
) == USE
)
21141 sub
= XEXP (sub
, 0);
21142 if (GET_CODE (sub
) == UNSPEC
21143 && XINT (sub
, 1) == UNSPEC_TOC
)
21153 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
21155 rtx tocrel
, tocreg
, hi
;
21157 if (TARGET_DEBUG_ADDR
)
21159 if (GET_CODE (symbol
) == SYMBOL_REF
)
21160 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
21164 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
21165 GET_RTX_NAME (GET_CODE (symbol
)));
21166 debug_rtx (symbol
);
21170 if (!can_create_pseudo_p ())
21171 df_set_regs_ever_live (TOC_REGISTER
, true);
21173 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
21174 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
21175 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
21178 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
21179 if (largetoc_reg
!= NULL
)
21181 emit_move_insn (largetoc_reg
, hi
);
21184 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
21187 /* Issue assembly directives that create a reference to the given DWARF
21188 FRAME_TABLE_LABEL from the current function section. */
21190 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
21192 fprintf (asm_out_file
, "\t.ref %s\n",
21193 (* targetm
.strip_name_encoding
) (frame_table_label
));
21196 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
21197 and the change to the stack pointer. */
21200 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
21207 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21208 if (hard_frame_needed
)
21209 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
21210 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
21211 || (hard_frame_needed
21212 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
21215 p
= rtvec_alloc (i
);
21218 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
21219 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
21222 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
21225 /* Emit the correct code for allocating stack space, as insns.
21226 If COPY_REG, make sure a copy of the old frame is left there.
21227 The generated code may use hard register 0 as a temporary. */
21230 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
21233 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21234 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
21235 rtx todec
= gen_int_mode (-size
, Pmode
);
21238 if (INTVAL (todec
) != -size
)
21240 warning (0, "stack frame too large");
21241 emit_insn (gen_trap ());
21245 if (crtl
->limit_stack
)
21247 if (REG_P (stack_limit_rtx
)
21248 && REGNO (stack_limit_rtx
) > 1
21249 && REGNO (stack_limit_rtx
) <= 31)
21251 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
21252 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21255 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
21257 && DEFAULT_ABI
== ABI_V4
)
21259 rtx toload
= gen_rtx_CONST (VOIDmode
,
21260 gen_rtx_PLUS (Pmode
,
21264 emit_insn (gen_elf_high (tmp_reg
, toload
));
21265 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
21266 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21270 warning (0, "stack limit expression is not supported");
21276 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
21278 emit_move_insn (copy_reg
, stack_reg
);
21283 /* Need a note here so that try_split doesn't get confused. */
21284 if (get_last_insn () == NULL_RTX
)
21285 emit_note (NOTE_INSN_DELETED
);
21286 insn
= emit_move_insn (tmp_reg
, todec
);
21287 try_split (PATTERN (insn
), insn
, 0);
21291 insn
= emit_insn (TARGET_32BIT
21292 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
21294 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
21295 todec
, stack_reg
));
21296 /* Since we didn't use gen_frame_mem to generate the MEM, grab
21297 it now and set the alias set/attributes. The above gen_*_update
21298 calls will generate a PARALLEL with the MEM set being the first
21300 par
= PATTERN (insn
);
21301 gcc_assert (GET_CODE (par
) == PARALLEL
);
21302 set
= XVECEXP (par
, 0, 0);
21303 gcc_assert (GET_CODE (set
) == SET
);
21304 mem
= SET_DEST (set
);
21305 gcc_assert (MEM_P (mem
));
21306 MEM_NOTRAP_P (mem
) = 1;
21307 set_mem_alias_set (mem
, get_frame_alias_set ());
21309 RTX_FRAME_RELATED_P (insn
) = 1;
21310 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
21311 gen_rtx_SET (VOIDmode
, stack_reg
,
21312 gen_rtx_PLUS (Pmode
, stack_reg
,
21313 GEN_INT (-size
))));
21316 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
21318 #if PROBE_INTERVAL > 32768
21319 #error Cannot use indexed addressing mode for stack probing
21322 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
21323 inclusive. These are offsets from the current stack pointer. */
21326 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
21328 /* See if we have a constant small number of probes to generate. If so,
21329 that's the easy case. */
21330 if (first
+ size
<= 32768)
21334 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
21335 it exceeds SIZE. If only one probe is needed, this will not
21336 generate any code. Then probe at FIRST + SIZE. */
21337 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
21338 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21341 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21345 /* Otherwise, do the same as above, but in a loop. Note that we must be
21346 extra careful with variables wrapping around because we might be at
21347 the very top (or the very bottom) of the address space and we have
21348 to be able to handle this case properly; in particular, we use an
21349 equality test for the loop condition. */
21352 HOST_WIDE_INT rounded_size
;
21353 rtx r12
= gen_rtx_REG (Pmode
, 12);
21354 rtx r0
= gen_rtx_REG (Pmode
, 0);
21356 /* Sanity check for the addressing mode we're going to use. */
21357 gcc_assert (first
<= 32768);
21359 /* Step 1: round SIZE to the previous multiple of the interval. */
21361 rounded_size
= size
& -PROBE_INTERVAL
;
21364 /* Step 2: compute initial and final value of the loop counter. */
21366 /* TEST_ADDR = SP + FIRST. */
21367 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
21368 plus_constant (Pmode
, stack_pointer_rtx
,
21371 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
21372 if (rounded_size
> 32768)
21374 emit_move_insn (r0
, GEN_INT (-rounded_size
));
21375 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21376 gen_rtx_PLUS (Pmode
, r12
, r0
)));
21379 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21380 plus_constant (Pmode
, r12
, -rounded_size
)));
21383 /* Step 3: the loop
21385 while (TEST_ADDR != LAST_ADDR)
21387 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
21391 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
21392 until it is equal to ROUNDED_SIZE. */
21395 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
21397 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
21400 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
21401 that SIZE is equal to ROUNDED_SIZE. */
21403 if (size
!= rounded_size
)
21404 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
21408 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
21409 absolute addresses. */
21412 output_probe_stack_range (rtx reg1
, rtx reg2
)
21414 static int labelno
= 0;
21415 char loop_lab
[32], end_lab
[32];
21418 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
21419 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
21421 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
21423 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
21427 output_asm_insn ("cmpd 0,%0,%1", xops
);
21429 output_asm_insn ("cmpw 0,%0,%1", xops
);
21431 fputs ("\tbeq 0,", asm_out_file
);
21432 assemble_name_raw (asm_out_file
, end_lab
);
21433 fputc ('\n', asm_out_file
);
21435 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
21436 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
21437 output_asm_insn ("addi %0,%0,%1", xops
);
21439 /* Probe at TEST_ADDR and branch. */
21440 xops
[1] = gen_rtx_REG (Pmode
, 0);
21441 output_asm_insn ("stw %1,0(%0)", xops
);
21442 fprintf (asm_out_file
, "\tb ");
21443 assemble_name_raw (asm_out_file
, loop_lab
);
21444 fputc ('\n', asm_out_file
);
21446 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
21451 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
21452 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
21453 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
21454 deduce these equivalences by itself so it wasn't necessary to hold
21455 its hand so much. Don't be tempted to always supply d2_f_d_e with
21456 the actual cfa register, ie. r31 when we are using a hard frame
21457 pointer. That fails when saving regs off r1, and sched moves the
21458 r31 setup past the reg saves. */
21461 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
21462 rtx reg2
, rtx rreg
, rtx split_reg
)
21466 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
21468 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
21471 gcc_checking_assert (val
== 0);
21472 real
= PATTERN (insn
);
21473 if (GET_CODE (real
) == PARALLEL
)
21474 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
21475 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
21477 rtx set
= XVECEXP (real
, 0, i
);
21479 RTX_FRAME_RELATED_P (set
) = 1;
21481 RTX_FRAME_RELATED_P (insn
) = 1;
21485 /* copy_rtx will not make unique copies of registers, so we need to
21486 ensure we don't have unwanted sharing here. */
21488 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
21491 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
21493 real
= copy_rtx (PATTERN (insn
));
21495 if (reg2
!= NULL_RTX
)
21496 real
= replace_rtx (real
, reg2
, rreg
);
21498 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
21499 gcc_checking_assert (val
== 0);
21501 real
= replace_rtx (real
, reg
,
21502 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
21503 STACK_POINTER_REGNUM
),
21506 /* We expect that 'real' is either a SET or a PARALLEL containing
21507 SETs (and possibly other stuff). In a PARALLEL, all the SETs
21508 are important so they all have to be marked RTX_FRAME_RELATED_P. */
21510 if (GET_CODE (real
) == SET
)
21514 temp
= simplify_rtx (SET_SRC (set
));
21516 SET_SRC (set
) = temp
;
21517 temp
= simplify_rtx (SET_DEST (set
));
21519 SET_DEST (set
) = temp
;
21520 if (GET_CODE (SET_DEST (set
)) == MEM
)
21522 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
21524 XEXP (SET_DEST (set
), 0) = temp
;
21531 gcc_assert (GET_CODE (real
) == PARALLEL
);
21532 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
21533 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
21535 rtx set
= XVECEXP (real
, 0, i
);
21537 temp
= simplify_rtx (SET_SRC (set
));
21539 SET_SRC (set
) = temp
;
21540 temp
= simplify_rtx (SET_DEST (set
));
21542 SET_DEST (set
) = temp
;
21543 if (GET_CODE (SET_DEST (set
)) == MEM
)
21545 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
21547 XEXP (SET_DEST (set
), 0) = temp
;
21549 RTX_FRAME_RELATED_P (set
) = 1;
21553 /* If a store insn has been split into multiple insns, the
21554 true source register is given by split_reg. */
21555 if (split_reg
!= NULL_RTX
)
21556 real
= gen_rtx_SET (VOIDmode
, SET_DEST (real
), split_reg
);
21558 RTX_FRAME_RELATED_P (insn
) = 1;
21559 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
21564 /* Returns an insn that has a vrsave set operation with the
21565 appropriate CLOBBERs. */
21568 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
21571 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
21572 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
21575 = gen_rtx_SET (VOIDmode
,
21577 gen_rtx_UNSPEC_VOLATILE (SImode
,
21578 gen_rtvec (2, reg
, vrsave
),
21579 UNSPECV_SET_VRSAVE
));
21583 /* We need to clobber the registers in the mask so the scheduler
21584 does not move sets to VRSAVE before sets of AltiVec registers.
21586 However, if the function receives nonlocal gotos, reload will set
21587 all call saved registers live. We will end up with:
21589 (set (reg 999) (mem))
21590 (parallel [ (set (reg vrsave) (unspec blah))
21591 (clobber (reg 999))])
21593 The clobber will cause the store into reg 999 to be dead, and
21594 flow will attempt to delete an epilogue insn. In this case, we
21595 need an unspec use/set of the register. */
21597 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21598 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21600 if (!epiloguep
|| call_used_regs
[i
])
21601 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
21602 gen_rtx_REG (V4SImode
, i
));
21605 rtx reg
= gen_rtx_REG (V4SImode
, i
);
21608 = gen_rtx_SET (VOIDmode
,
21610 gen_rtx_UNSPEC (V4SImode
,
21611 gen_rtvec (1, reg
), 27));
21615 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
21617 for (i
= 0; i
< nclobs
; ++i
)
21618 XVECEXP (insn
, 0, i
) = clobs
[i
];
21624 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
21628 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
21629 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
21630 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
21634 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
21636 return gen_frame_set (reg
, frame_reg
, offset
, false);
21640 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
21642 return gen_frame_set (reg
, frame_reg
, offset
, true);
21645 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
21646 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
21649 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
21650 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
21654 /* Some cases that need register indexed addressing. */
21655 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
21656 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
21657 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
21659 && SPE_VECTOR_MODE (mode
)
21660 && !SPE_CONST_OFFSET_OK (offset
))));
21662 reg
= gen_rtx_REG (mode
, regno
);
21663 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
21664 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
21665 NULL_RTX
, NULL_RTX
, NULL_RTX
);
21668 /* Emit an offset memory reference suitable for a frame store, while
21669 converting to a valid addressing mode. */
21672 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
21674 rtx int_rtx
, offset_rtx
;
21676 int_rtx
= GEN_INT (offset
);
21678 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
21679 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
21681 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
21682 emit_move_insn (offset_rtx
, int_rtx
);
21685 offset_rtx
= int_rtx
;
21687 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
21690 #ifndef TARGET_FIX_AND_CONTINUE
21691 #define TARGET_FIX_AND_CONTINUE 0
21694 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
21695 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
21696 #define LAST_SAVRES_REGISTER 31
21697 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
21708 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
21710 /* Temporary holding space for an out-of-line register save/restore
21712 static char savres_routine_name
[30];
21714 /* Return the name for an out-of-line register save/restore routine.
21715 We are saving/restoring GPRs if GPR is true. */
21718 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
21720 const char *prefix
= "";
21721 const char *suffix
= "";
21723 /* Different targets are supposed to define
21724 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
21725 routine name could be defined with:
21727 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
21729 This is a nice idea in practice, but in reality, things are
21730 complicated in several ways:
21732 - ELF targets have save/restore routines for GPRs.
21734 - SPE targets use different prefixes for 32/64-bit registers, and
21735 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
21737 - PPC64 ELF targets have routines for save/restore of GPRs that
21738 differ in what they do with the link register, so having a set
21739 prefix doesn't work. (We only use one of the save routines at
21740 the moment, though.)
21742 - PPC32 elf targets have "exit" versions of the restore routines
21743 that restore the link register and can save some extra space.
21744 These require an extra suffix. (There are also "tail" versions
21745 of the restore routines and "GOT" versions of the save routines,
21746 but we don't generate those at present. Same problems apply,
21749 We deal with all this by synthesizing our own prefix/suffix and
21750 using that for the simple sprintf call shown above. */
21753 /* No floating point saves on the SPE. */
21754 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
21756 if ((sel
& SAVRES_SAVE
))
21757 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
21759 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
21761 if ((sel
& SAVRES_LR
))
21764 else if (DEFAULT_ABI
== ABI_V4
)
21769 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21770 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
21771 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21772 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
21773 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21774 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21778 if ((sel
& SAVRES_LR
))
21781 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21783 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
21784 /* No out-of-line save/restore routines for GPRs on AIX. */
21785 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
21789 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21790 prefix
= ((sel
& SAVRES_SAVE
)
21791 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
21792 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
21793 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21795 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
21796 if ((sel
& SAVRES_LR
))
21797 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
21801 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
21802 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
21805 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21806 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21811 if (DEFAULT_ABI
== ABI_DARWIN
)
21813 /* The Darwin approach is (slightly) different, in order to be
21814 compatible with code generated by the system toolchain. There is a
21815 single symbol for the start of save sequence, and the code here
21816 embeds an offset into that code on the basis of the first register
21818 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
21819 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21820 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
21821 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
21822 (regno
- 13) * 4, prefix
, regno
);
21823 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21824 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
21825 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
21826 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21827 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
21828 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
21833 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
21835 return savres_routine_name
;
21838 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
21839 We are saving/restoring GPRs if GPR is true. */
21842 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
21844 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21845 ? info
->first_gp_reg_save
21846 : (sel
& SAVRES_REG
) == SAVRES_FPR
21847 ? info
->first_fp_reg_save
- 32
21848 : (sel
& SAVRES_REG
) == SAVRES_VR
21849 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
21854 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
21855 versions of the gpr routines. */
21856 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
21857 && info
->spe_64bit_regs_used
)
21858 select
^= SAVRES_FPR
^ SAVRES_GPR
;
21860 /* Don't generate bogus routine names. */
21861 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
21862 && regno
<= LAST_SAVRES_REGISTER
21863 && select
>= 0 && select
<= 12);
21865 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
21871 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21873 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
21874 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
21875 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
21881 /* Emit a sequence of insns, including a stack tie if needed, for
21882 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
21883 reset the stack pointer, but move the base of the frame into
21884 reg UPDT_REGNO for use by out-of-line register restore routines. */
21887 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
21888 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
21889 unsigned updt_regno
)
21893 /* This blockage is needed so that sched doesn't decide to move
21894 the sp change before the register restores. */
21895 if (DEFAULT_ABI
== ABI_V4
21897 && info
->spe_64bit_regs_used
!= 0
21898 && info
->first_gp_reg_save
!= 32))
21899 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
21901 /* If we are restoring registers out-of-line, we will be using the
21902 "exit" variants of the restore routines, which will reset the
21903 stack for us. But we do need to point updt_reg into the
21904 right place for those routines. */
21905 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
21907 if (frame_off
!= 0)
21908 return emit_insn (gen_add3_insn (updt_reg_rtx
,
21909 frame_reg_rtx
, GEN_INT (frame_off
)));
21910 else if (REGNO (frame_reg_rtx
) != updt_regno
)
21911 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
21916 /* Return the register number used as a pointer by out-of-line
21917 save/restore functions. */
21919 static inline unsigned
21920 ptr_regno_for_savres (int sel
)
21922 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21923 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
21924 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
21927 /* Construct a parallel rtx describing the effect of a call to an
21928 out-of-line register save/restore routine, and emit the insn
21929 or jump_insn as appropriate. */
21932 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
21933 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
21934 enum machine_mode reg_mode
, int sel
)
21937 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
21938 int reg_size
= GET_MODE_SIZE (reg_mode
);
21944 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21945 ? info
->first_gp_reg_save
21946 : (sel
& SAVRES_REG
) == SAVRES_FPR
21947 ? info
->first_fp_reg_save
21948 : (sel
& SAVRES_REG
) == SAVRES_VR
21949 ? info
->first_altivec_reg_save
21951 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21953 : (sel
& SAVRES_REG
) == SAVRES_FPR
21955 : (sel
& SAVRES_REG
) == SAVRES_VR
21956 ? LAST_ALTIVEC_REGNO
+ 1
21958 n_regs
= end_reg
- start_reg
;
21959 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
21960 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
21963 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21964 RTVEC_ELT (p
, offset
++) = ret_rtx
;
21966 RTVEC_ELT (p
, offset
++)
21967 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
21969 sym
= rs6000_savres_routine_sym (info
, sel
);
21970 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
21972 use_reg
= ptr_regno_for_savres (sel
);
21973 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21975 /* Vector regs are saved/restored using [reg+reg] addressing. */
21976 RTVEC_ELT (p
, offset
++)
21977 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21978 RTVEC_ELT (p
, offset
++)
21979 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
21982 RTVEC_ELT (p
, offset
++)
21983 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21985 for (i
= 0; i
< end_reg
- start_reg
; i
++)
21986 RTVEC_ELT (p
, i
+ offset
)
21987 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
21988 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
21989 (sel
& SAVRES_SAVE
) != 0);
21991 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21992 RTVEC_ELT (p
, i
+ offset
)
21993 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
21995 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
21997 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21999 insn
= emit_jump_insn (par
);
22000 JUMP_LABEL (insn
) = ret_rtx
;
22003 insn
= emit_insn (par
);
22007 /* Emit code to store CR fields that need to be saved into REG. */
22010 rs6000_emit_move_from_cr (rtx reg
)
22012 /* Only the ELFv2 ABI allows storing only selected fields. */
22013 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
22015 int i
, cr_reg
[8], count
= 0;
22017 /* Collect CR fields that must be saved. */
22018 for (i
= 0; i
< 8; i
++)
22019 if (save_reg_p (CR0_REGNO
+ i
))
22020 cr_reg
[count
++] = i
;
22022 /* If it's just a single one, use mfcrf. */
22025 rtvec p
= rtvec_alloc (1);
22026 rtvec r
= rtvec_alloc (2);
22027 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
22028 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
22030 = gen_rtx_SET (VOIDmode
, reg
,
22031 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
22033 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22037 /* ??? It might be better to handle count == 2 / 3 cases here
22038 as well, using logical operations to combine the values. */
22041 emit_insn (gen_movesi_from_cr (reg
));
22044 /* Determine whether the gp REG is really used. */
22047 rs6000_reg_live_or_pic_offset_p (int reg
)
22049 /* If the function calls eh_return, claim used all the registers that would
22050 be checked for liveness otherwise. This is required for the PIC offset
22051 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
22052 register allocation purposes in this case. */
22054 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22055 && (!call_used_regs
[reg
]
22056 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22057 && !TARGET_SINGLE_PIC_BASE
22058 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
22059 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22060 && !TARGET_SINGLE_PIC_BASE
22061 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22062 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
22065 /* Emit function prologue as insns. */
22068 rs6000_emit_prologue (void)
22070 rs6000_stack_t
*info
= rs6000_stack_info ();
22071 enum machine_mode reg_mode
= Pmode
;
22072 int reg_size
= TARGET_32BIT
? 4 : 8;
22073 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22074 rtx frame_reg_rtx
= sp_reg_rtx
;
22075 unsigned int cr_save_regno
;
22076 rtx cr_save_rtx
= NULL_RTX
;
22079 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22080 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22081 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22082 /* Offset to top of frame for frame_reg and sp respectively. */
22083 HOST_WIDE_INT frame_off
= 0;
22084 HOST_WIDE_INT sp_off
= 0;
22086 #ifdef ENABLE_CHECKING
22087 /* Track and check usage of r0, r11, r12. */
22088 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
22089 #define START_USE(R) do \
22091 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22092 reg_inuse |= 1 << (R); \
22094 #define END_USE(R) do \
22096 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
22097 reg_inuse &= ~(1 << (R)); \
22099 #define NOT_INUSE(R) do \
22101 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22104 #define START_USE(R) do {} while (0)
22105 #define END_USE(R) do {} while (0)
22106 #define NOT_INUSE(R) do {} while (0)
22109 if (DEFAULT_ABI
== ABI_ELFv2
)
22111 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
22113 /* With -mminimal-toc we may generate an extra use of r2 below. */
22114 if (!TARGET_SINGLE_PIC_BASE
22115 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22116 cfun
->machine
->r2_setup_needed
= true;
22120 if (flag_stack_usage_info
)
22121 current_function_static_stack_size
= info
->total_size
;
22123 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
22125 HOST_WIDE_INT size
= info
->total_size
;
22127 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
22129 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
22130 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
22131 size
- STACK_CHECK_PROTECT
);
22134 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
22137 if (TARGET_FIX_AND_CONTINUE
)
22139 /* gdb on darwin arranges to forward a function from the old
22140 address by modifying the first 5 instructions of the function
22141 to branch to the overriding function. This is necessary to
22142 permit function pointers that point to the old function to
22143 actually forward to the new function. */
22144 emit_insn (gen_nop ());
22145 emit_insn (gen_nop ());
22146 emit_insn (gen_nop ());
22147 emit_insn (gen_nop ());
22148 emit_insn (gen_nop ());
22151 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22153 reg_mode
= V2SImode
;
22157 /* Handle world saves specially here. */
22158 if (WORLD_SAVE_P (info
))
22165 /* save_world expects lr in r0. */
22166 reg0
= gen_rtx_REG (Pmode
, 0);
22167 if (info
->lr_save_p
)
22169 insn
= emit_move_insn (reg0
,
22170 gen_rtx_REG (Pmode
, LR_REGNO
));
22171 RTX_FRAME_RELATED_P (insn
) = 1;
22174 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
22175 assumptions about the offsets of various bits of the stack
22177 gcc_assert (info
->gp_save_offset
== -220
22178 && info
->fp_save_offset
== -144
22179 && info
->lr_save_offset
== 8
22180 && info
->cr_save_offset
== 4
22183 && (!crtl
->calls_eh_return
22184 || info
->ehrd_offset
== -432)
22185 && info
->vrsave_save_offset
== -224
22186 && info
->altivec_save_offset
== -416);
22188 treg
= gen_rtx_REG (SImode
, 11);
22189 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
22191 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
22192 in R11. It also clobbers R12, so beware! */
22194 /* Preserve CR2 for save_world prologues */
22196 sz
+= 32 - info
->first_gp_reg_save
;
22197 sz
+= 64 - info
->first_fp_reg_save
;
22198 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
22199 p
= rtvec_alloc (sz
);
22201 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
22202 gen_rtx_REG (SImode
,
22204 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22205 gen_rtx_SYMBOL_REF (Pmode
,
22207 /* We do floats first so that the instruction pattern matches
22209 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22211 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22213 info
->first_fp_reg_save
+ i
),
22215 info
->fp_save_offset
+ frame_off
+ 8 * i
);
22216 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22218 = gen_frame_store (gen_rtx_REG (V4SImode
,
22219 info
->first_altivec_reg_save
+ i
),
22221 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
22222 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22224 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22226 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22228 /* CR register traditionally saved as CR2. */
22230 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
22231 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
22232 /* Explain about use of R0. */
22233 if (info
->lr_save_p
)
22235 = gen_frame_store (reg0
,
22236 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22237 /* Explain what happens to the stack pointer. */
22239 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
22240 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
22243 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22244 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22245 treg
, GEN_INT (-info
->total_size
), NULL_RTX
);
22246 sp_off
= frame_off
= info
->total_size
;
22249 strategy
= info
->savres_strategy
;
22251 /* For V.4, update stack before we do any saving and set back pointer. */
22252 if (! WORLD_SAVE_P (info
)
22254 && (DEFAULT_ABI
== ABI_V4
22255 || crtl
->calls_eh_return
))
22257 bool need_r11
= (TARGET_SPE
22258 ? (!(strategy
& SAVE_INLINE_GPRS
)
22259 && info
->spe_64bit_regs_used
== 0)
22260 : (!(strategy
& SAVE_INLINE_FPRS
)
22261 || !(strategy
& SAVE_INLINE_GPRS
)
22262 || !(strategy
& SAVE_INLINE_VRS
)));
22263 int ptr_regno
= -1;
22264 rtx ptr_reg
= NULL_RTX
;
22267 if (info
->total_size
< 32767)
22268 frame_off
= info
->total_size
;
22271 else if (info
->cr_save_p
22273 || info
->first_fp_reg_save
< 64
22274 || info
->first_gp_reg_save
< 32
22275 || info
->altivec_size
!= 0
22276 || info
->vrsave_mask
!= 0
22277 || crtl
->calls_eh_return
)
22281 /* The prologue won't be saving any regs so there is no need
22282 to set up a frame register to access any frame save area.
22283 We also won't be using frame_off anywhere below, but set
22284 the correct value anyway to protect against future
22285 changes to this function. */
22286 frame_off
= info
->total_size
;
22288 if (ptr_regno
!= -1)
22290 /* Set up the frame offset to that needed by the first
22291 out-of-line save function. */
22292 START_USE (ptr_regno
);
22293 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22294 frame_reg_rtx
= ptr_reg
;
22295 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
22296 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
22297 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
22298 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
22299 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
22300 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22301 frame_off
= -ptr_off
;
22303 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22304 sp_off
= info
->total_size
;
22305 if (frame_reg_rtx
!= sp_reg_rtx
)
22306 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22309 /* If we use the link register, get it into r0. */
22310 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
22312 rtx addr
, reg
, mem
;
22314 reg
= gen_rtx_REG (Pmode
, 0);
22316 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22317 RTX_FRAME_RELATED_P (insn
) = 1;
22319 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
22320 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
22322 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22323 GEN_INT (info
->lr_save_offset
+ frame_off
));
22324 mem
= gen_rtx_MEM (Pmode
, addr
);
22325 /* This should not be of rs6000_sr_alias_set, because of
22326 __builtin_return_address. */
22328 insn
= emit_move_insn (mem
, reg
);
22329 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22330 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22335 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
22336 r12 will be needed by out-of-line gpr restore. */
22337 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22338 && !(strategy
& (SAVE_INLINE_GPRS
22339 | SAVE_NOINLINE_GPRS_SAVES_LR
))
22341 if (!WORLD_SAVE_P (info
)
22343 && REGNO (frame_reg_rtx
) != cr_save_regno
22344 && !(using_static_chain_p
&& cr_save_regno
== 11))
22346 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
22347 START_USE (cr_save_regno
);
22348 rs6000_emit_move_from_cr (cr_save_rtx
);
22351 /* Do any required saving of fpr's. If only one or two to save, do
22352 it ourselves. Otherwise, call function. */
22353 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
22356 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22357 if (save_reg_p (info
->first_fp_reg_save
+ i
))
22358 emit_frame_save (frame_reg_rtx
,
22359 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22360 ? DFmode
: SFmode
),
22361 info
->first_fp_reg_save
+ i
,
22362 info
->fp_save_offset
+ frame_off
+ 8 * i
,
22363 sp_off
- frame_off
);
22365 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
22367 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
22368 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22369 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22370 rtx ptr_reg
= frame_reg_rtx
;
22372 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22373 gcc_checking_assert (frame_off
== 0);
22376 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22377 NOT_INUSE (ptr_regno
);
22378 emit_insn (gen_add3_insn (ptr_reg
,
22379 frame_reg_rtx
, GEN_INT (frame_off
)));
22381 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
22382 info
->fp_save_offset
,
22383 info
->lr_save_offset
,
22385 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
22386 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22391 /* Save GPRs. This is done as a PARALLEL if we are using
22392 the store-multiple instructions. */
22393 if (!WORLD_SAVE_P (info
)
22395 && info
->spe_64bit_regs_used
!= 0
22396 && info
->first_gp_reg_save
!= 32)
22399 rtx spe_save_area_ptr
;
22400 HOST_WIDE_INT save_off
;
22401 int ool_adjust
= 0;
22403 /* Determine whether we can address all of the registers that need
22404 to be saved with an offset from frame_reg_rtx that fits in
22405 the small const field for SPE memory instructions. */
22406 int spe_regs_addressable
22407 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
22408 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
22409 && (strategy
& SAVE_INLINE_GPRS
));
22411 if (spe_regs_addressable
)
22413 spe_save_area_ptr
= frame_reg_rtx
;
22414 save_off
= frame_off
;
22418 /* Make r11 point to the start of the SPE save area. We need
22419 to be careful here if r11 is holding the static chain. If
22420 it is, then temporarily save it in r0. */
22421 HOST_WIDE_INT offset
;
22423 if (!(strategy
& SAVE_INLINE_GPRS
))
22424 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
22425 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
22426 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
22427 save_off
= frame_off
- offset
;
22429 if (using_static_chain_p
)
22431 rtx r0
= gen_rtx_REG (Pmode
, 0);
22434 gcc_assert (info
->first_gp_reg_save
> 11);
22436 emit_move_insn (r0
, spe_save_area_ptr
);
22438 else if (REGNO (frame_reg_rtx
) != 11)
22441 emit_insn (gen_addsi3 (spe_save_area_ptr
,
22442 frame_reg_rtx
, GEN_INT (offset
)));
22443 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
22444 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
22447 if ((strategy
& SAVE_INLINE_GPRS
))
22449 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22450 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22451 emit_frame_save (spe_save_area_ptr
, reg_mode
,
22452 info
->first_gp_reg_save
+ i
,
22453 (info
->spe_gp_save_offset
+ save_off
22455 sp_off
- save_off
);
22459 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
22460 info
->spe_gp_save_offset
+ save_off
,
22462 SAVRES_SAVE
| SAVRES_GPR
);
22464 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
22465 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22468 /* Move the static chain pointer back. */
22469 if (!spe_regs_addressable
)
22471 if (using_static_chain_p
)
22473 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
22476 else if (REGNO (frame_reg_rtx
) != 11)
22480 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
22482 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
22483 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
22484 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22485 rtx ptr_reg
= frame_reg_rtx
;
22486 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
22487 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
22491 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22493 /* Need to adjust r11 (r12) if we saved any FPRs. */
22494 if (end_save
+ frame_off
!= 0)
22496 rtx offset
= GEN_INT (end_save
+ frame_off
);
22499 frame_off
= -end_save
;
22501 NOT_INUSE (ptr_regno
);
22502 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22504 else if (!ptr_set_up
)
22506 NOT_INUSE (ptr_regno
);
22507 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22509 ptr_off
= -end_save
;
22510 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
22511 info
->gp_save_offset
+ ptr_off
,
22512 info
->lr_save_offset
+ ptr_off
,
22514 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
22515 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22519 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
22523 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
22524 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22526 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22528 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22529 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22530 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22531 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22533 else if (!WORLD_SAVE_P (info
))
22536 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22537 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22538 emit_frame_save (frame_reg_rtx
, reg_mode
,
22539 info
->first_gp_reg_save
+ i
,
22540 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
22541 sp_off
- frame_off
);
22544 if (crtl
->calls_eh_return
)
22551 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
22552 if (regno
== INVALID_REGNUM
)
22556 p
= rtvec_alloc (i
);
22560 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
22561 if (regno
== INVALID_REGNUM
)
22565 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
22567 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
22568 RTVEC_ELT (p
, i
) = insn
;
22569 RTX_FRAME_RELATED_P (insn
) = 1;
22572 insn
= emit_insn (gen_blockage ());
22573 RTX_FRAME_RELATED_P (insn
) = 1;
22574 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
22577 /* In AIX ABI we need to make sure r2 is really saved. */
22578 if (TARGET_AIX
&& crtl
->calls_eh_return
)
22580 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
22581 rtx save_insn
, join_insn
, note
;
22582 long toc_restore_insn
;
22584 tmp_reg
= gen_rtx_REG (Pmode
, 11);
22585 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
22586 if (using_static_chain_p
)
22589 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
22593 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22594 /* Peek at instruction to which this function returns. If it's
22595 restoring r2, then we know we've already saved r2. We can't
22596 unconditionally save r2 because the value we have will already
22597 be updated if we arrived at this function via a plt call or
22598 toc adjusting stub. */
22599 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
22600 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
22601 + RS6000_TOC_SAVE_SLOT
);
22602 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
22603 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
22604 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
22605 validate_condition_mode (EQ
, CCUNSmode
);
22606 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
22607 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
22608 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
22609 toc_save_done
= gen_label_rtx ();
22610 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
22611 gen_rtx_EQ (VOIDmode
, compare_result
,
22613 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
22615 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
22616 JUMP_LABEL (jump
) = toc_save_done
;
22617 LABEL_NUSES (toc_save_done
) += 1;
22619 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
22620 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
22621 sp_off
- frame_off
);
22623 emit_label (toc_save_done
);
22625 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
22626 have a CFG that has different saves along different paths.
22627 Move the note to a dummy blockage insn, which describes that
22628 R2 is unconditionally saved after the label. */
22629 /* ??? An alternate representation might be a special insn pattern
22630 containing both the branch and the store. That might let the
22631 code that minimizes the number of DW_CFA_advance opcodes better
22632 freedom in placing the annotations. */
22633 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
22635 remove_note (save_insn
, note
);
22637 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
22638 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
22639 RTX_FRAME_RELATED_P (save_insn
) = 0;
22641 join_insn
= emit_insn (gen_blockage ());
22642 REG_NOTES (join_insn
) = note
;
22643 RTX_FRAME_RELATED_P (join_insn
) = 1;
22645 if (using_static_chain_p
)
22647 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
22654 /* Save CR if we use any that must be preserved. */
22655 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
22657 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22658 GEN_INT (info
->cr_save_offset
+ frame_off
));
22659 rtx mem
= gen_frame_mem (SImode
, addr
);
22661 /* If we didn't copy cr before, do so now using r0. */
22662 if (cr_save_rtx
== NULL_RTX
)
22665 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
22666 rs6000_emit_move_from_cr (cr_save_rtx
);
22669 /* Saving CR requires a two-instruction sequence: one instruction
22670 to move the CR to a general-purpose register, and a second
22671 instruction that stores the GPR to memory.
22673 We do not emit any DWARF CFI records for the first of these,
22674 because we cannot properly represent the fact that CR is saved in
22675 a register. One reason is that we cannot express that multiple
22676 CR fields are saved; another reason is that on 64-bit, the size
22677 of the CR register in DWARF (4 bytes) differs from the size of
22678 a general-purpose register.
22680 This means if any intervening instruction were to clobber one of
22681 the call-saved CR fields, we'd have incorrect CFI. To prevent
22682 this from happening, we mark the store to memory as a use of
22683 those CR fields, which prevents any such instruction from being
22684 scheduled in between the two instructions. */
22689 crsave_v
[n_crsave
++] = gen_rtx_SET (VOIDmode
, mem
, cr_save_rtx
);
22690 for (i
= 0; i
< 8; i
++)
22691 if (save_reg_p (CR0_REGNO
+ i
))
22692 crsave_v
[n_crsave
++]
22693 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
22695 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22696 gen_rtvec_v (n_crsave
, crsave_v
)));
22697 END_USE (REGNO (cr_save_rtx
));
22699 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
22700 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
22701 so we need to construct a frame expression manually. */
22702 RTX_FRAME_RELATED_P (insn
) = 1;
22704 /* Update address to be stack-pointer relative, like
22705 rs6000_frame_related would do. */
22706 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
22707 GEN_INT (info
->cr_save_offset
+ sp_off
));
22708 mem
= gen_frame_mem (SImode
, addr
);
22710 if (DEFAULT_ABI
== ABI_ELFv2
)
22712 /* In the ELFv2 ABI we generate separate CFI records for each
22713 CR field that was actually saved. They all point to the
22714 same 32-bit stack slot. */
22718 for (i
= 0; i
< 8; i
++)
22719 if (save_reg_p (CR0_REGNO
+ i
))
22722 = gen_rtx_SET (VOIDmode
, mem
,
22723 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
22725 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
22729 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22730 gen_rtx_PARALLEL (VOIDmode
,
22731 gen_rtvec_v (n_crframe
, crframe
)));
22735 /* In other ABIs, by convention, we use a single CR regnum to
22736 represent the fact that all call-saved CR fields are saved.
22737 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
22738 rtx set
= gen_rtx_SET (VOIDmode
, mem
,
22739 gen_rtx_REG (SImode
, CR2_REGNO
));
22740 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
22744 /* In the ELFv2 ABI we need to save all call-saved CR fields into
22745 *separate* slots if the routine calls __builtin_eh_return, so
22746 that they can be independently restored by the unwinder. */
22747 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
22749 int i
, cr_off
= info
->ehcr_offset
;
22752 /* ??? We might get better performance by using multiple mfocrf
22754 crsave
= gen_rtx_REG (SImode
, 0);
22755 emit_insn (gen_movesi_from_cr (crsave
));
22757 for (i
= 0; i
< 8; i
++)
22758 if (!call_used_regs
[CR0_REGNO
+ i
])
22760 rtvec p
= rtvec_alloc (2);
22762 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
22764 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
22766 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22768 RTX_FRAME_RELATED_P (insn
) = 1;
22769 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22770 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
22771 sp_reg_rtx
, cr_off
+ sp_off
));
22773 cr_off
+= reg_size
;
22777 /* Update stack and set back pointer unless this is V.4,
22778 for which it was done previously. */
22779 if (!WORLD_SAVE_P (info
) && info
->push_p
22780 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
22782 rtx ptr_reg
= NULL
;
22785 /* If saving altivec regs we need to be able to address all save
22786 locations using a 16-bit offset. */
22787 if ((strategy
& SAVE_INLINE_VRS
) == 0
22788 || (info
->altivec_size
!= 0
22789 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
22790 + info
->total_size
- frame_off
) > 32767)
22791 || (info
->vrsave_size
!= 0
22792 && (info
->vrsave_save_offset
22793 + info
->total_size
- frame_off
) > 32767))
22795 int sel
= SAVRES_SAVE
| SAVRES_VR
;
22796 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22798 if (using_static_chain_p
22799 && ptr_regno
== STATIC_CHAIN_REGNUM
)
22801 if (REGNO (frame_reg_rtx
) != ptr_regno
)
22802 START_USE (ptr_regno
);
22803 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22804 frame_reg_rtx
= ptr_reg
;
22805 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22806 frame_off
= -ptr_off
;
22808 else if (REGNO (frame_reg_rtx
) == 1)
22809 frame_off
= info
->total_size
;
22810 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22811 sp_off
= info
->total_size
;
22812 if (frame_reg_rtx
!= sp_reg_rtx
)
22813 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22816 /* Set frame pointer, if needed. */
22817 if (frame_pointer_needed
)
22819 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
22821 RTX_FRAME_RELATED_P (insn
) = 1;
22824 /* Save AltiVec registers if needed. Save here because the red zone does
22825 not always include AltiVec registers. */
22826 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22827 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
22829 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22831 /* Oddly, the vector save/restore functions point r0 at the end
22832 of the save area, then use r11 or r12 to load offsets for
22833 [reg+reg] addressing. */
22834 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22835 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
22836 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22838 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
22840 if (end_save
+ frame_off
!= 0)
22842 rtx offset
= GEN_INT (end_save
+ frame_off
);
22844 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22847 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22849 ptr_off
= -end_save
;
22850 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22851 info
->altivec_save_offset
+ ptr_off
,
22852 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
22853 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
22854 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22855 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
22857 /* The oddity mentioned above clobbered our frame reg. */
22858 emit_move_insn (frame_reg_rtx
, ptr_reg
);
22859 frame_off
= ptr_off
;
22862 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22863 && info
->altivec_size
!= 0)
22867 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22868 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22870 rtx areg
, savereg
, mem
, split_reg
;
22873 offset
= (info
->altivec_save_offset
+ frame_off
22874 + 16 * (i
- info
->first_altivec_reg_save
));
22876 savereg
= gen_rtx_REG (V4SImode
, i
);
22879 areg
= gen_rtx_REG (Pmode
, 0);
22880 emit_move_insn (areg
, GEN_INT (offset
));
22882 /* AltiVec addressing mode is [reg+reg]. */
22883 mem
= gen_frame_mem (V4SImode
,
22884 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
22886 insn
= emit_move_insn (mem
, savereg
);
22888 /* When we split a VSX store into two insns, we need to make
22889 sure the DWARF info knows which register we are storing.
22890 Pass it in to be used on the appropriate note. */
22891 if (!BYTES_BIG_ENDIAN
22892 && GET_CODE (PATTERN (insn
)) == SET
22893 && GET_CODE (SET_SRC (PATTERN (insn
))) == VEC_SELECT
)
22894 split_reg
= savereg
;
22896 split_reg
= NULL_RTX
;
22898 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22899 areg
, GEN_INT (offset
), split_reg
);
22903 /* VRSAVE is a bit vector representing which AltiVec registers
22904 are used. The OS uses this to determine which vector
22905 registers to save on a context switch. We need to save
22906 VRSAVE on the stack frame, add whatever AltiVec registers we
22907 used in this function, and do the corresponding magic in the
22910 if (!WORLD_SAVE_P (info
)
22912 && TARGET_ALTIVEC_VRSAVE
22913 && info
->vrsave_mask
!= 0)
22919 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
22920 be using r12 as frame_reg_rtx and r11 as the static chain
22921 pointer for nested functions. */
22923 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22924 && !using_static_chain_p
)
22926 else if (REGNO (frame_reg_rtx
) == 12)
22929 if (using_static_chain_p
)
22933 NOT_INUSE (save_regno
);
22934 reg
= gen_rtx_REG (SImode
, save_regno
);
22935 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22937 emit_insn (gen_get_vrsave_internal (reg
));
22939 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
22942 offset
= info
->vrsave_save_offset
+ frame_off
;
22943 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
22945 /* Include the registers in the mask. */
22946 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
22948 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
22951 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
22952 if (!TARGET_SINGLE_PIC_BASE
22953 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22954 || (DEFAULT_ABI
== ABI_V4
22955 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
22956 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
22958 /* If emit_load_toc_table will use the link register, we need to save
22959 it. We use R12 for this purpose because emit_load_toc_table
22960 can use register 0. This allows us to use a plain 'blr' to return
22961 from the procedure more often. */
22962 int save_LR_around_toc_setup
= (TARGET_ELF
22963 && DEFAULT_ABI
== ABI_V4
22965 && ! info
->lr_save_p
22966 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
22967 if (save_LR_around_toc_setup
)
22969 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22970 rtx tmp
= gen_rtx_REG (Pmode
, 12);
22972 insn
= emit_move_insn (tmp
, lr
);
22973 RTX_FRAME_RELATED_P (insn
) = 1;
22975 rs6000_emit_load_toc_table (TRUE
);
22977 insn
= emit_move_insn (lr
, tmp
);
22978 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
22979 RTX_FRAME_RELATED_P (insn
) = 1;
22982 rs6000_emit_load_toc_table (TRUE
);
22986 if (!TARGET_SINGLE_PIC_BASE
22987 && DEFAULT_ABI
== ABI_DARWIN
22988 && flag_pic
&& crtl
->uses_pic_offset_table
)
22990 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22991 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
22993 /* Save and restore LR locally around this call (in R0). */
22994 if (!info
->lr_save_p
)
22995 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
22997 emit_insn (gen_load_macho_picbase (src
));
22999 emit_move_insn (gen_rtx_REG (Pmode
,
23000 RS6000_PIC_OFFSET_TABLE_REGNUM
),
23003 if (!info
->lr_save_p
)
23004 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
23008 /* If we need to, save the TOC register after doing the stack setup.
23009 Do not emit eh frame info for this save. The unwinder wants info,
23010 conceptually attached to instructions in this function, about
23011 register values in the caller of this function. This R2 may have
23012 already been changed from the value in the caller.
23013 We don't attempt to write accurate DWARF EH frame info for R2
23014 because code emitted by gcc for a (non-pointer) function call
23015 doesn't save and restore R2. Instead, R2 is managed out-of-line
23016 by a linker generated plt call stub when the function resides in
23017 a shared library. This behaviour is costly to describe in DWARF,
23018 both in terms of the size of DWARF info and the time taken in the
23019 unwinder to interpret it. R2 changes, apart from the
23020 calls_eh_return case earlier in this function, are handled by
23021 linux-unwind.h frob_update_context. */
23022 if (rs6000_save_toc_in_prologue_p ())
23024 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
23025 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
23029 /* Write function prologue. */
23032 rs6000_output_function_prologue (FILE *file
,
23033 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23035 rs6000_stack_t
*info
= rs6000_stack_info ();
23037 if (TARGET_DEBUG_STACK
)
23038 debug_stack_info (info
);
23040 /* Write .extern for any function we will call to save and restore
23042 if (info
->first_fp_reg_save
< 64
23047 int regno
= info
->first_fp_reg_save
- 32;
23049 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
23051 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23052 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23053 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23054 fprintf (file
, "\t.extern %s\n", name
);
23056 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
23058 bool lr
= (info
->savres_strategy
23059 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23060 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23061 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23062 fprintf (file
, "\t.extern %s\n", name
);
23066 /* ELFv2 ABI r2 setup code and local entry point. This must follow
23067 immediately after the global entry point label. */
23068 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
23070 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23072 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
23073 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
23075 fputs ("\t.localentry\t", file
);
23076 assemble_name (file
, name
);
23077 fputs (",.-", file
);
23078 assemble_name (file
, name
);
23079 fputs ("\n", file
);
23082 /* Output -mprofile-kernel code. This needs to be done here instead of
23083 in output_function_profile since it must go after the ELFv2 ABI
23084 local entry point. */
23085 if (TARGET_PROFILE_KERNEL
)
23087 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23088 gcc_assert (!TARGET_32BIT
);
23090 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23091 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23093 /* In the ELFv2 ABI we have no compiler stack word. It must be
23094 the resposibility of _mcount to preserve the static chain
23095 register if required. */
23096 if (DEFAULT_ABI
!= ABI_ELFv2
23097 && cfun
->static_chain_decl
!= NULL
)
23099 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23100 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23101 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23102 asm_fprintf (file
, "\tld %s,24(%s)\n",
23103 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23106 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23109 rs6000_pic_labelno
++;
23112 /* Non-zero if vmx regs are restored before the frame pop, zero if
23113 we restore after the pop when possible. */
23114 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
23116 /* Restoring cr is a two step process: loading a reg from the frame
23117 save, then moving the reg to cr. For ABI_V4 we must let the
23118 unwinder know that the stack location is no longer valid at or
23119 before the stack deallocation, but we can't emit a cfa_restore for
23120 cr at the stack deallocation like we do for other registers.
23121 The trouble is that it is possible for the move to cr to be
23122 scheduled after the stack deallocation. So say exactly where cr
23123 is located on each of the two insns. */
23126 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
23128 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
23129 rtx reg
= gen_rtx_REG (SImode
, regno
);
23130 rtx insn
= emit_move_insn (reg
, mem
);
23132 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
23134 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23135 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
23137 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
23138 RTX_FRAME_RELATED_P (insn
) = 1;
23143 /* Reload CR from REG. */
23146 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
23151 if (using_mfcr_multiple
)
23153 for (i
= 0; i
< 8; i
++)
23154 if (save_reg_p (CR0_REGNO
+ i
))
23156 gcc_assert (count
);
23159 if (using_mfcr_multiple
&& count
> 1)
23165 p
= rtvec_alloc (count
);
23168 for (i
= 0; i
< 8; i
++)
23169 if (save_reg_p (CR0_REGNO
+ i
))
23171 rtvec r
= rtvec_alloc (2);
23172 RTVEC_ELT (r
, 0) = reg
;
23173 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
23174 RTVEC_ELT (p
, ndx
) =
23175 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
23176 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
23179 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23180 gcc_assert (ndx
== count
);
23182 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23183 CR field separately. */
23184 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23186 for (i
= 0; i
< 8; i
++)
23187 if (save_reg_p (CR0_REGNO
+ i
))
23188 add_reg_note (insn
, REG_CFA_RESTORE
,
23189 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23191 RTX_FRAME_RELATED_P (insn
) = 1;
23195 for (i
= 0; i
< 8; i
++)
23196 if (save_reg_p (CR0_REGNO
+ i
))
23198 rtx insn
= emit_insn (gen_movsi_to_cr_one
23199 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23201 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23202 CR field separately, attached to the insn that in fact
23203 restores this particular CR field. */
23204 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23206 add_reg_note (insn
, REG_CFA_RESTORE
,
23207 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23209 RTX_FRAME_RELATED_P (insn
) = 1;
23213 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
23214 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
23215 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23217 rtx insn
= get_last_insn ();
23218 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23220 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
23221 RTX_FRAME_RELATED_P (insn
) = 1;
23225 /* Like cr, the move to lr instruction can be scheduled after the
23226 stack deallocation, but unlike cr, its stack frame save is still
23227 valid. So we only need to emit the cfa_restore on the correct
23231 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
23233 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
23234 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23236 emit_move_insn (reg
, mem
);
23240 restore_saved_lr (int regno
, bool exit_func
)
23242 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23243 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23244 rtx insn
= emit_move_insn (lr
, reg
);
23246 if (!exit_func
&& flag_shrink_wrap
)
23248 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23249 RTX_FRAME_RELATED_P (insn
) = 1;
23254 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
23256 if (DEFAULT_ABI
== ABI_ELFv2
)
23259 for (i
= 0; i
< 8; i
++)
23260 if (save_reg_p (CR0_REGNO
+ i
))
23262 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
23263 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
23267 else if (info
->cr_save_p
)
23268 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23269 gen_rtx_REG (SImode
, CR2_REGNO
),
23272 if (info
->lr_save_p
)
23273 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23274 gen_rtx_REG (Pmode
, LR_REGNO
),
23276 return cfa_restores
;
23279 /* Return true if OFFSET from stack pointer can be clobbered by signals.
23280 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
23281 below stack pointer not cloberred by signals. */
23284 offset_below_red_zone_p (HOST_WIDE_INT offset
)
23286 return offset
< (DEFAULT_ABI
== ABI_V4
23288 : TARGET_32BIT
? -220 : -288);
23291 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
23294 emit_cfa_restores (rtx cfa_restores
)
23296 rtx insn
= get_last_insn ();
23297 rtx
*loc
= ®_NOTES (insn
);
23300 loc
= &XEXP (*loc
, 1);
23301 *loc
= cfa_restores
;
23302 RTX_FRAME_RELATED_P (insn
) = 1;
23305 /* Emit function epilogue as insns. */
23308 rs6000_emit_epilogue (int sibcall
)
23310 rs6000_stack_t
*info
;
23311 int restoring_GPRs_inline
;
23312 int restoring_FPRs_inline
;
23313 int using_load_multiple
;
23314 int using_mtcr_multiple
;
23315 int use_backchain_to_restore_sp
;
23318 HOST_WIDE_INT frame_off
= 0;
23319 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
23320 rtx frame_reg_rtx
= sp_reg_rtx
;
23321 rtx cfa_restores
= NULL_RTX
;
23323 rtx cr_save_reg
= NULL_RTX
;
23324 enum machine_mode reg_mode
= Pmode
;
23325 int reg_size
= TARGET_32BIT
? 4 : 8;
23328 unsigned ptr_regno
;
23330 info
= rs6000_stack_info ();
23332 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
23334 reg_mode
= V2SImode
;
23338 strategy
= info
->savres_strategy
;
23339 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
23340 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
23341 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
23342 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
23343 || rs6000_cpu
== PROCESSOR_PPC603
23344 || rs6000_cpu
== PROCESSOR_PPC750
23346 /* Restore via the backchain when we have a large frame, since this
23347 is more efficient than an addis, addi pair. The second condition
23348 here will not trigger at the moment; We don't actually need a
23349 frame pointer for alloca, but the generic parts of the compiler
23350 give us one anyway. */
23351 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
23352 || (cfun
->calls_alloca
23353 && !frame_pointer_needed
));
23354 restore_lr
= (info
->lr_save_p
23355 && (restoring_FPRs_inline
23356 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
23357 && (restoring_GPRs_inline
23358 || info
->first_fp_reg_save
< 64));
23360 if (WORLD_SAVE_P (info
))
23364 const char *alloc_rname
;
23367 /* eh_rest_world_r10 will return to the location saved in the LR
23368 stack slot (which is not likely to be our caller.)
23369 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
23370 rest_world is similar, except any R10 parameter is ignored.
23371 The exception-handling stuff that was here in 2.95 is no
23372 longer necessary. */
23376 + 32 - info
->first_gp_reg_save
23377 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
23378 + 63 + 1 - info
->first_fp_reg_save
);
23380 strcpy (rname
, ((crtl
->calls_eh_return
) ?
23381 "*eh_rest_world_r10" : "*rest_world"));
23382 alloc_rname
= ggc_strdup (rname
);
23385 RTVEC_ELT (p
, j
++) = ret_rtx
;
23386 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
23387 gen_rtx_REG (Pmode
,
23390 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
23391 /* The instruction pattern requires a clobber here;
23392 it is shared with the restVEC helper. */
23394 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
23397 /* CR register traditionally saved as CR2. */
23398 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
23400 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
23401 if (flag_shrink_wrap
)
23403 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23404 gen_rtx_REG (Pmode
, LR_REGNO
),
23406 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23410 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23412 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23414 = gen_frame_load (reg
,
23415 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
23416 if (flag_shrink_wrap
)
23417 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23419 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
23421 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
23423 = gen_frame_load (reg
,
23424 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
23425 if (flag_shrink_wrap
)
23426 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23428 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
23430 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23431 ? DFmode
: SFmode
),
23432 info
->first_fp_reg_save
+ i
);
23434 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
23435 if (flag_shrink_wrap
)
23436 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23439 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
23441 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
23443 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
23445 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
23447 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
23448 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23450 if (flag_shrink_wrap
)
23452 REG_NOTES (insn
) = cfa_restores
;
23453 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23454 RTX_FRAME_RELATED_P (insn
) = 1;
23459 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
23461 frame_off
= info
->total_size
;
23463 /* Restore AltiVec registers if we must do so before adjusting the
23465 if (TARGET_ALTIVEC_ABI
23466 && info
->altivec_size
!= 0
23467 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23468 || (DEFAULT_ABI
!= ABI_V4
23469 && offset_below_red_zone_p (info
->altivec_save_offset
))))
23472 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
23474 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
23475 if (use_backchain_to_restore_sp
)
23477 int frame_regno
= 11;
23479 if ((strategy
& REST_INLINE_VRS
) == 0)
23481 /* Of r11 and r12, select the one not clobbered by an
23482 out-of-line restore function for the frame register. */
23483 frame_regno
= 11 + 12 - scratch_regno
;
23485 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
23486 emit_move_insn (frame_reg_rtx
,
23487 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23490 else if (frame_pointer_needed
)
23491 frame_reg_rtx
= hard_frame_pointer_rtx
;
23493 if ((strategy
& REST_INLINE_VRS
) == 0)
23495 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23497 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23498 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23500 if (end_save
+ frame_off
!= 0)
23502 rtx offset
= GEN_INT (end_save
+ frame_off
);
23504 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23507 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23509 ptr_off
= -end_save
;
23510 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23511 info
->altivec_save_offset
+ ptr_off
,
23512 0, V4SImode
, SAVRES_VR
);
23516 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23517 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23519 rtx addr
, areg
, mem
, reg
;
23521 areg
= gen_rtx_REG (Pmode
, 0);
23523 (areg
, GEN_INT (info
->altivec_save_offset
23525 + 16 * (i
- info
->first_altivec_reg_save
)));
23527 /* AltiVec addressing mode is [reg+reg]. */
23528 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
23529 mem
= gen_frame_mem (V4SImode
, addr
);
23531 reg
= gen_rtx_REG (V4SImode
, i
);
23532 emit_move_insn (reg
, mem
);
23536 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23537 if (((strategy
& REST_INLINE_VRS
) == 0
23538 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
23539 && (flag_shrink_wrap
23540 || (offset_below_red_zone_p
23541 (info
->altivec_save_offset
23542 + 16 * (i
- info
->first_altivec_reg_save
)))))
23544 rtx reg
= gen_rtx_REG (V4SImode
, i
);
23545 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23549 /* Restore VRSAVE if we must do so before adjusting the stack. */
23551 && TARGET_ALTIVEC_VRSAVE
23552 && info
->vrsave_mask
!= 0
23553 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23554 || (DEFAULT_ABI
!= ABI_V4
23555 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
23559 if (frame_reg_rtx
== sp_reg_rtx
)
23561 if (use_backchain_to_restore_sp
)
23563 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23564 emit_move_insn (frame_reg_rtx
,
23565 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23568 else if (frame_pointer_needed
)
23569 frame_reg_rtx
= hard_frame_pointer_rtx
;
23572 reg
= gen_rtx_REG (SImode
, 12);
23573 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23574 info
->vrsave_save_offset
+ frame_off
));
23576 emit_insn (generate_set_vrsave (reg
, info
, 1));
23580 /* If we have a large stack frame, restore the old stack pointer
23581 using the backchain. */
23582 if (use_backchain_to_restore_sp
)
23584 if (frame_reg_rtx
== sp_reg_rtx
)
23586 /* Under V.4, don't reset the stack pointer until after we're done
23587 loading the saved registers. */
23588 if (DEFAULT_ABI
== ABI_V4
)
23589 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23591 insn
= emit_move_insn (frame_reg_rtx
,
23592 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23595 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23596 && DEFAULT_ABI
== ABI_V4
)
23597 /* frame_reg_rtx has been set up by the altivec restore. */
23601 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
23602 frame_reg_rtx
= sp_reg_rtx
;
23605 /* If we have a frame pointer, we can restore the old stack pointer
23607 else if (frame_pointer_needed
)
23609 frame_reg_rtx
= sp_reg_rtx
;
23610 if (DEFAULT_ABI
== ABI_V4
)
23611 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23612 /* Prevent reordering memory accesses against stack pointer restore. */
23613 else if (cfun
->calls_alloca
23614 || offset_below_red_zone_p (-info
->total_size
))
23615 rs6000_emit_stack_tie (frame_reg_rtx
, true);
23617 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
23618 GEN_INT (info
->total_size
)));
23621 else if (info
->push_p
23622 && DEFAULT_ABI
!= ABI_V4
23623 && !crtl
->calls_eh_return
)
23625 /* Prevent reordering memory accesses against stack pointer restore. */
23626 if (cfun
->calls_alloca
23627 || offset_below_red_zone_p (-info
->total_size
))
23628 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23629 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
23630 GEN_INT (info
->total_size
)));
23633 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
23637 REG_NOTES (insn
) = cfa_restores
;
23638 cfa_restores
= NULL_RTX
;
23640 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23641 RTX_FRAME_RELATED_P (insn
) = 1;
23644 /* Restore AltiVec registers if we have not done so already. */
23645 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23646 && TARGET_ALTIVEC_ABI
23647 && info
->altivec_size
!= 0
23648 && (DEFAULT_ABI
== ABI_V4
23649 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
23653 if ((strategy
& REST_INLINE_VRS
) == 0)
23655 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23657 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23658 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
23659 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23661 if (end_save
+ frame_off
!= 0)
23663 rtx offset
= GEN_INT (end_save
+ frame_off
);
23665 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23668 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23670 ptr_off
= -end_save
;
23671 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23672 info
->altivec_save_offset
+ ptr_off
,
23673 0, V4SImode
, SAVRES_VR
);
23674 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
23676 /* Frame reg was clobbered by out-of-line save. Restore it
23677 from ptr_reg, and if we are calling out-of-line gpr or
23678 fpr restore set up the correct pointer and offset. */
23679 unsigned newptr_regno
= 1;
23680 if (!restoring_GPRs_inline
)
23682 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
23683 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23684 newptr_regno
= ptr_regno_for_savres (sel
);
23685 end_save
= info
->gp_save_offset
+ info
->gp_size
;
23687 else if (!restoring_FPRs_inline
)
23689 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
23690 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23691 newptr_regno
= ptr_regno_for_savres (sel
);
23692 end_save
= info
->gp_save_offset
+ info
->gp_size
;
23695 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
23696 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
23698 if (end_save
+ ptr_off
!= 0)
23700 rtx offset
= GEN_INT (end_save
+ ptr_off
);
23702 frame_off
= -end_save
;
23703 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
23707 frame_off
= ptr_off
;
23708 emit_move_insn (frame_reg_rtx
, ptr_reg
);
23714 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23715 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23717 rtx addr
, areg
, mem
, reg
;
23719 areg
= gen_rtx_REG (Pmode
, 0);
23721 (areg
, GEN_INT (info
->altivec_save_offset
23723 + 16 * (i
- info
->first_altivec_reg_save
)));
23725 /* AltiVec addressing mode is [reg+reg]. */
23726 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
23727 mem
= gen_frame_mem (V4SImode
, addr
);
23729 reg
= gen_rtx_REG (V4SImode
, i
);
23730 emit_move_insn (reg
, mem
);
23734 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23735 if (((strategy
& REST_INLINE_VRS
) == 0
23736 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
23737 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23739 rtx reg
= gen_rtx_REG (V4SImode
, i
);
23740 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23744 /* Restore VRSAVE if we have not done so already. */
23745 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23747 && TARGET_ALTIVEC_VRSAVE
23748 && info
->vrsave_mask
!= 0
23749 && (DEFAULT_ABI
== ABI_V4
23750 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
23754 reg
= gen_rtx_REG (SImode
, 12);
23755 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23756 info
->vrsave_save_offset
+ frame_off
));
23758 emit_insn (generate_set_vrsave (reg
, info
, 1));
23761 /* If we exit by an out-of-line restore function on ABI_V4 then that
23762 function will deallocate the stack, so we don't need to worry
23763 about the unwinder restoring cr from an invalid stack frame
23765 exit_func
= (!restoring_FPRs_inline
23766 || (!restoring_GPRs_inline
23767 && info
->first_fp_reg_save
== 64));
23769 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
23770 *separate* slots if the routine calls __builtin_eh_return, so
23771 that they can be independently restored by the unwinder. */
23772 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23774 int i
, cr_off
= info
->ehcr_offset
;
23776 for (i
= 0; i
< 8; i
++)
23777 if (!call_used_regs
[CR0_REGNO
+ i
])
23779 rtx reg
= gen_rtx_REG (SImode
, 0);
23780 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23781 cr_off
+ frame_off
));
23783 insn
= emit_insn (gen_movsi_to_cr_one
23784 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23786 if (!exit_func
&& flag_shrink_wrap
)
23788 add_reg_note (insn
, REG_CFA_RESTORE
,
23789 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23791 RTX_FRAME_RELATED_P (insn
) = 1;
23794 cr_off
+= reg_size
;
23798 /* Get the old lr if we saved it. If we are restoring registers
23799 out-of-line, then the out-of-line routines can do this for us. */
23800 if (restore_lr
&& restoring_GPRs_inline
)
23801 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
23803 /* Get the old cr if we saved it. */
23804 if (info
->cr_save_p
)
23806 unsigned cr_save_regno
= 12;
23808 if (!restoring_GPRs_inline
)
23810 /* Ensure we don't use the register used by the out-of-line
23811 gpr register restore below. */
23812 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
23813 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23814 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
23816 if (gpr_ptr_regno
== 12)
23817 cr_save_regno
= 11;
23818 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
23820 else if (REGNO (frame_reg_rtx
) == 12)
23821 cr_save_regno
= 11;
23823 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
23824 info
->cr_save_offset
+ frame_off
,
23828 /* Set LR here to try to overlap restores below. */
23829 if (restore_lr
&& restoring_GPRs_inline
)
23830 restore_saved_lr (0, exit_func
);
23832 /* Load exception handler data registers, if needed. */
23833 if (crtl
->calls_eh_return
)
23835 unsigned int i
, regno
;
23839 rtx reg
= gen_rtx_REG (reg_mode
, 2);
23840 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23841 frame_off
+ RS6000_TOC_SAVE_SLOT
));
23848 regno
= EH_RETURN_DATA_REGNO (i
);
23849 if (regno
== INVALID_REGNUM
)
23852 /* Note: possible use of r0 here to address SPE regs. */
23853 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
23854 info
->ehrd_offset
+ frame_off
23855 + reg_size
* (int) i
);
23857 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
23861 /* Restore GPRs. This is done as a PARALLEL if we are using
23862 the load-multiple instructions. */
23864 && info
->spe_64bit_regs_used
23865 && info
->first_gp_reg_save
!= 32)
23867 /* Determine whether we can address all of the registers that need
23868 to be saved with an offset from frame_reg_rtx that fits in
23869 the small const field for SPE memory instructions. */
23870 int spe_regs_addressable
23871 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23872 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23873 && restoring_GPRs_inline
);
23875 if (!spe_regs_addressable
)
23877 int ool_adjust
= 0;
23878 rtx old_frame_reg_rtx
= frame_reg_rtx
;
23879 /* Make r11 point to the start of the SPE save area. We worried about
23880 not clobbering it when we were saving registers in the prologue.
23881 There's no need to worry here because the static chain is passed
23882 anew to every function. */
23884 if (!restoring_GPRs_inline
)
23885 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23886 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23887 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
23888 GEN_INT (info
->spe_gp_save_offset
23891 /* Keep the invariant that frame_reg_rtx + frame_off points
23892 at the top of the stack frame. */
23893 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23896 if (restoring_GPRs_inline
)
23898 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
23900 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23901 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23903 rtx offset
, addr
, mem
, reg
;
23905 /* We're doing all this to ensure that the immediate offset
23906 fits into the immediate field of 'evldd'. */
23907 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
23909 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
23910 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
23911 mem
= gen_rtx_MEM (V2SImode
, addr
);
23912 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23914 emit_move_insn (reg
, mem
);
23918 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
23919 info
->spe_gp_save_offset
+ frame_off
,
23920 info
->lr_save_offset
+ frame_off
,
23922 SAVRES_GPR
| SAVRES_LR
);
23924 else if (!restoring_GPRs_inline
)
23926 /* We are jumping to an out-of-line function. */
23928 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23929 bool can_use_exit
= end_save
== 0;
23930 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
23933 /* Emit stack reset code if we need it. */
23934 ptr_regno
= ptr_regno_for_savres (sel
);
23935 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23937 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
23938 else if (end_save
+ frame_off
!= 0)
23939 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
23940 GEN_INT (end_save
+ frame_off
)));
23941 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
23942 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23943 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23944 frame_off
= -end_save
;
23946 if (can_use_exit
&& info
->cr_save_p
)
23947 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
23949 ptr_off
= -end_save
;
23950 rs6000_emit_savres_rtx (info
, ptr_reg
,
23951 info
->gp_save_offset
+ ptr_off
,
23952 info
->lr_save_offset
+ ptr_off
,
23955 else if (using_load_multiple
)
23958 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23959 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23961 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23963 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23964 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23968 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23969 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23970 emit_insn (gen_frame_load
23971 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23973 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
23976 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
23978 /* If the frame pointer was used then we can't delay emitting
23979 a REG_CFA_DEF_CFA note. This must happen on the insn that
23980 restores the frame pointer, r31. We may have already emitted
23981 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
23982 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
23983 be harmless if emitted. */
23984 if (frame_pointer_needed
)
23986 insn
= get_last_insn ();
23987 add_reg_note (insn
, REG_CFA_DEF_CFA
,
23988 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
23989 RTX_FRAME_RELATED_P (insn
) = 1;
23992 /* Set up cfa_restores. We always need these when
23993 shrink-wrapping. If not shrink-wrapping then we only need
23994 the cfa_restore when the stack location is no longer valid.
23995 The cfa_restores must be emitted on or before the insn that
23996 invalidates the stack, and of course must not be emitted
23997 before the insn that actually does the restore. The latter
23998 is why it is a bad idea to emit the cfa_restores as a group
23999 on the last instruction here that actually does a restore:
24000 That insn may be reordered with respect to others doing
24002 if (flag_shrink_wrap
24003 && !restoring_GPRs_inline
24004 && info
->first_fp_reg_save
== 64)
24005 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24007 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
24008 if (!restoring_GPRs_inline
24009 || using_load_multiple
24010 || rs6000_reg_live_or_pic_offset_p (i
))
24012 rtx reg
= gen_rtx_REG (reg_mode
, i
);
24014 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24018 if (!restoring_GPRs_inline
24019 && info
->first_fp_reg_save
== 64)
24021 /* We are jumping to an out-of-line function. */
24023 emit_cfa_restores (cfa_restores
);
24027 if (restore_lr
&& !restoring_GPRs_inline
)
24029 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24030 restore_saved_lr (0, exit_func
);
24033 /* Restore fpr's if we need to do it without calling a function. */
24034 if (restoring_FPRs_inline
)
24035 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24036 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24038 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24039 ? DFmode
: SFmode
),
24040 info
->first_fp_reg_save
+ i
);
24041 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24042 info
->fp_save_offset
+ frame_off
+ 8 * i
));
24043 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24044 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24047 /* If we saved cr, restore it here. Just those that were used. */
24048 if (info
->cr_save_p
)
24049 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
24051 /* If this is V.4, unwind the stack pointer after all of the loads
24052 have been done, or set up r11 if we are restoring fp out of line. */
24054 if (!restoring_FPRs_inline
)
24056 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24057 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24058 ptr_regno
= ptr_regno_for_savres (sel
);
24061 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24062 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24065 if (insn
&& restoring_FPRs_inline
)
24069 REG_NOTES (insn
) = cfa_restores
;
24070 cfa_restores
= NULL_RTX
;
24072 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24073 RTX_FRAME_RELATED_P (insn
) = 1;
24076 if (crtl
->calls_eh_return
)
24078 rtx sa
= EH_RETURN_STACKADJ_RTX
;
24079 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
24085 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24086 if (! restoring_FPRs_inline
)
24088 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
24089 RTVEC_ELT (p
, 0) = ret_rtx
;
24095 /* We can't hang the cfa_restores off a simple return,
24096 since the shrink-wrap code sometimes uses an existing
24097 return. This means there might be a path from
24098 pre-prologue code to this return, and dwarf2cfi code
24099 wants the eh_frame unwinder state to be the same on
24100 all paths to any point. So we need to emit the
24101 cfa_restores before the return. For -m64 we really
24102 don't need epilogue cfa_restores at all, except for
24103 this irritating dwarf2cfi with shrink-wrap
24104 requirement; The stack red-zone means eh_frame info
24105 from the prologue telling the unwinder to restore
24106 from the stack is perfectly good right to the end of
24108 emit_insn (gen_blockage ());
24109 emit_cfa_restores (cfa_restores
);
24110 cfa_restores
= NULL_RTX
;
24112 p
= rtvec_alloc (2);
24113 RTVEC_ELT (p
, 0) = simple_return_rtx
;
24116 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
24117 ? gen_rtx_USE (VOIDmode
,
24118 gen_rtx_REG (Pmode
, LR_REGNO
))
24119 : gen_rtx_CLOBBER (VOIDmode
,
24120 gen_rtx_REG (Pmode
, LR_REGNO
)));
24122 /* If we have to restore more than two FP registers, branch to the
24123 restore function. It will return to our caller. */
24124 if (! restoring_FPRs_inline
)
24130 if (flag_shrink_wrap
)
24131 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24133 sym
= rs6000_savres_routine_sym (info
,
24134 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
24135 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
24136 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
24137 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
24139 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24141 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
24143 RTVEC_ELT (p
, i
+ 4)
24144 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24145 if (flag_shrink_wrap
)
24146 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
24151 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24157 /* Ensure the cfa_restores are hung off an insn that won't
24158 be reordered above other restores. */
24159 emit_insn (gen_blockage ());
24161 emit_cfa_restores (cfa_restores
);
24165 /* Write function epilogue. */
24168 rs6000_output_function_epilogue (FILE *file
,
24169 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
24172 macho_branch_islands ();
24173 /* Mach-O doesn't support labels at the end of objects, so if
24174 it looks like we might want one, insert a NOP. */
24176 rtx insn
= get_last_insn ();
24177 rtx deleted_debug_label
= NULL_RTX
;
24180 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
24182 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
24183 notes only, instead set their CODE_LABEL_NUMBER to -1,
24184 otherwise there would be code generation differences
24185 in between -g and -g0. */
24186 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24187 deleted_debug_label
= insn
;
24188 insn
= PREV_INSN (insn
);
24193 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
24194 fputs ("\tnop\n", file
);
24195 else if (deleted_debug_label
)
24196 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
24197 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24198 CODE_LABEL_NUMBER (insn
) = -1;
24202 /* Output a traceback table here. See /usr/include/sys/debug.h for info
24205 We don't output a traceback table if -finhibit-size-directive was
24206 used. The documentation for -finhibit-size-directive reads
24207 ``don't output a @code{.size} assembler directive, or anything
24208 else that would cause trouble if the function is split in the
24209 middle, and the two halves are placed at locations far apart in
24210 memory.'' The traceback table has this property, since it
24211 includes the offset from the start of the function to the
24212 traceback table itself.
24214 System V.4 Powerpc's (and the embedded ABI derived from it) use a
24215 different traceback table. */
24216 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24217 && ! flag_inhibit_size_directive
24218 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
24220 const char *fname
= NULL
;
24221 const char *language_string
= lang_hooks
.name
;
24222 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
24224 int optional_tbtab
;
24225 rs6000_stack_t
*info
= rs6000_stack_info ();
24227 if (rs6000_traceback
== traceback_full
)
24228 optional_tbtab
= 1;
24229 else if (rs6000_traceback
== traceback_part
)
24230 optional_tbtab
= 0;
24232 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
24234 if (optional_tbtab
)
24236 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24237 while (*fname
== '.') /* V.4 encodes . in the name */
24240 /* Need label immediately before tbtab, so we can compute
24241 its offset from the function start. */
24242 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24243 ASM_OUTPUT_LABEL (file
, fname
);
24246 /* The .tbtab pseudo-op can only be used for the first eight
24247 expressions, since it can't handle the possibly variable
24248 length fields that follow. However, if you omit the optional
24249 fields, the assembler outputs zeros for all optional fields
24250 anyways, giving each variable length field is minimum length
24251 (as defined in sys/debug.h). Thus we can not use the .tbtab
24252 pseudo-op at all. */
24254 /* An all-zero word flags the start of the tbtab, for debuggers
24255 that have to find it by searching forward from the entry
24256 point or from the current pc. */
24257 fputs ("\t.long 0\n", file
);
24259 /* Tbtab format type. Use format type 0. */
24260 fputs ("\t.byte 0,", file
);
24262 /* Language type. Unfortunately, there does not seem to be any
24263 official way to discover the language being compiled, so we
24264 use language_string.
24265 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
24266 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
24267 a number, so for now use 9. LTO, Go, and UPC aren't assigned numbers
24268 either, so for now use 0. */
24269 if (! strcmp (language_string
, "GNU C")
24270 || ! strcmp (language_string
, "GNU GIMPLE")
24271 || ! strcmp (language_string
, "GNU Go")
24272 || ! strcmp (language_string
, "GNU UPC"))
24274 else if (! strcmp (language_string
, "GNU F77")
24275 || ! strcmp (language_string
, "GNU Fortran"))
24277 else if (! strcmp (language_string
, "GNU Pascal"))
24279 else if (! strcmp (language_string
, "GNU Ada"))
24281 else if (! strcmp (language_string
, "GNU C++")
24282 || ! strcmp (language_string
, "GNU Objective-C++"))
24284 else if (! strcmp (language_string
, "GNU Java"))
24286 else if (! strcmp (language_string
, "GNU Objective-C"))
24289 gcc_unreachable ();
24290 fprintf (file
, "%d,", i
);
24292 /* 8 single bit fields: global linkage (not set for C extern linkage,
24293 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
24294 from start of procedure stored in tbtab, internal function, function
24295 has controlled storage, function has no toc, function uses fp,
24296 function logs/aborts fp operations. */
24297 /* Assume that fp operations are used if any fp reg must be saved. */
24298 fprintf (file
, "%d,",
24299 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
24301 /* 6 bitfields: function is interrupt handler, name present in
24302 proc table, function calls alloca, on condition directives
24303 (controls stack walks, 3 bits), saves condition reg, saves
24305 /* The `function calls alloca' bit seems to be set whenever reg 31 is
24306 set up as a frame pointer, even when there is no alloca call. */
24307 fprintf (file
, "%d,",
24308 ((optional_tbtab
<< 6)
24309 | ((optional_tbtab
& frame_pointer_needed
) << 5)
24310 | (info
->cr_save_p
<< 1)
24311 | (info
->lr_save_p
)));
24313 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
24315 fprintf (file
, "%d,",
24316 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
24318 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
24319 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
24321 if (optional_tbtab
)
24323 /* Compute the parameter info from the function decl argument
24326 int next_parm_info_bit
= 31;
24328 for (decl
= DECL_ARGUMENTS (current_function_decl
);
24329 decl
; decl
= DECL_CHAIN (decl
))
24331 rtx parameter
= DECL_INCOMING_RTL (decl
);
24332 enum machine_mode mode
= GET_MODE (parameter
);
24334 if (GET_CODE (parameter
) == REG
)
24336 if (SCALAR_FLOAT_MODE_P (mode
))
24357 gcc_unreachable ();
24360 /* If only one bit will fit, don't or in this entry. */
24361 if (next_parm_info_bit
> 0)
24362 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
24363 next_parm_info_bit
-= 2;
24367 fixed_parms
+= ((GET_MODE_SIZE (mode
)
24368 + (UNITS_PER_WORD
- 1))
24370 next_parm_info_bit
-= 1;
24376 /* Number of fixed point parameters. */
24377 /* This is actually the number of words of fixed point parameters; thus
24378 an 8 byte struct counts as 2; and thus the maximum value is 8. */
24379 fprintf (file
, "%d,", fixed_parms
);
24381 /* 2 bitfields: number of floating point parameters (7 bits), parameters
24383 /* This is actually the number of fp registers that hold parameters;
24384 and thus the maximum value is 13. */
24385 /* Set parameters on stack bit if parameters are not in their original
24386 registers, regardless of whether they are on the stack? Xlc
24387 seems to set the bit when not optimizing. */
24388 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
24390 if (! optional_tbtab
)
24393 /* Optional fields follow. Some are variable length. */
24395 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
24396 11 double float. */
24397 /* There is an entry for each parameter in a register, in the order that
24398 they occur in the parameter list. Any intervening arguments on the
24399 stack are ignored. If the list overflows a long (max possible length
24400 34 bits) then completely leave off all elements that don't fit. */
24401 /* Only emit this long if there was at least one parameter. */
24402 if (fixed_parms
|| float_parms
)
24403 fprintf (file
, "\t.long %d\n", parm_info
);
24405 /* Offset from start of code to tb table. */
24406 fputs ("\t.long ", file
);
24407 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24408 RS6000_OUTPUT_BASENAME (file
, fname
);
24410 rs6000_output_function_entry (file
, fname
);
24413 /* Interrupt handler mask. */
24414 /* Omit this long, since we never set the interrupt handler bit
24417 /* Number of CTL (controlled storage) anchors. */
24418 /* Omit this long, since the has_ctl bit is never set above. */
24420 /* Displacement into stack of each CTL anchor. */
24421 /* Omit this list of longs, because there are no CTL anchors. */
24423 /* Length of function name. */
24426 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
24428 /* Function name. */
24429 assemble_string (fname
, strlen (fname
));
24431 /* Register for alloca automatic storage; this is always reg 31.
24432 Only emit this if the alloca bit was set above. */
24433 if (frame_pointer_needed
)
24434 fputs ("\t.byte 31\n", file
);
24436 fputs ("\t.align 2\n", file
);
24440 /* A C compound statement that outputs the assembler code for a thunk
24441 function, used to implement C++ virtual function calls with
24442 multiple inheritance. The thunk acts as a wrapper around a virtual
24443 function, adjusting the implicit object parameter before handing
24444 control off to the real function.
24446 First, emit code to add the integer DELTA to the location that
24447 contains the incoming first argument. Assume that this argument
24448 contains a pointer, and is the one used to pass the `this' pointer
24449 in C++. This is the incoming argument *before* the function
24450 prologue, e.g. `%o0' on a sparc. The addition must preserve the
24451 values of all other incoming arguments.
24453 After the addition, emit code to jump to FUNCTION, which is a
24454 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
24455 not touch the return address. Hence returning from FUNCTION will
24456 return to whoever called the current `thunk'.
24458 The effect must be as if FUNCTION had been called directly with the
24459 adjusted first argument. This macro is responsible for emitting
24460 all of the code for a thunk function; output_function_prologue()
24461 and output_function_epilogue() are not invoked.
24463 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
24464 been extracted from it.) It might possibly be useful on some
24465 targets, but probably not.
24467 If you do not define this macro, the target-independent code in the
24468 C++ frontend will generate a less efficient heavyweight thunk that
24469 calls FUNCTION instead of jumping to it. The generic approach does
24470 not support varargs. */
24473 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
24474 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
24477 rtx this_rtx
, insn
, funexp
;
24479 reload_completed
= 1;
24480 epilogue_completed
= 1;
24482 /* Mark the end of the (empty) prologue. */
24483 emit_note (NOTE_INSN_PROLOGUE_END
);
24485 /* Find the "this" pointer. If the function returns a structure,
24486 the structure return pointer is in r3. */
24487 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
24488 this_rtx
= gen_rtx_REG (Pmode
, 4);
24490 this_rtx
= gen_rtx_REG (Pmode
, 3);
24492 /* Apply the constant offset, if required. */
24494 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
24496 /* Apply the offset from the vtable, if required. */
24499 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
24500 rtx tmp
= gen_rtx_REG (Pmode
, 12);
24502 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
24503 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
24505 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
24506 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
24510 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
24512 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
24514 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
24517 /* Generate a tail call to the target function. */
24518 if (!TREE_USED (function
))
24520 assemble_external (function
);
24521 TREE_USED (function
) = 1;
24523 funexp
= XEXP (DECL_RTL (function
), 0);
24524 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
24527 if (MACHOPIC_INDIRECT
)
24528 funexp
= machopic_indirect_call_target (funexp
);
24531 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
24532 generate sibcall RTL explicitly. */
24533 insn
= emit_call_insn (
24534 gen_rtx_PARALLEL (VOIDmode
,
24536 gen_rtx_CALL (VOIDmode
,
24537 funexp
, const0_rtx
),
24538 gen_rtx_USE (VOIDmode
, const0_rtx
),
24539 gen_rtx_USE (VOIDmode
,
24540 gen_rtx_REG (SImode
,
24542 simple_return_rtx
)));
24543 SIBLING_CALL_P (insn
) = 1;
24546 /* Ensure we have a global entry point for the thunk. ??? We could
24547 avoid that if the target routine doesn't need a global entry point,
24548 but we do not know whether this is the case at this point. */
24549 if (DEFAULT_ABI
== ABI_ELFv2
)
24550 cfun
->machine
->r2_setup_needed
= true;
24552 /* Run just enough of rest_of_compilation to get the insns emitted.
24553 There's not really enough bulk here to make other passes such as
24554 instruction scheduling worth while. Note that use_thunk calls
24555 assemble_start_function and assemble_end_function. */
24556 insn
= get_insns ();
24557 shorten_branches (insn
);
24558 final_start_function (insn
, file
, 1);
24559 final (insn
, file
, 1);
24560 final_end_function ();
24562 reload_completed
= 0;
24563 epilogue_completed
= 0;
24566 /* A quick summary of the various types of 'constant-pool tables'
24569 Target Flags Name One table per
24570 AIX (none) AIX TOC object file
24571 AIX -mfull-toc AIX TOC object file
24572 AIX -mminimal-toc AIX minimal TOC translation unit
24573 SVR4/EABI (none) SVR4 SDATA object file
24574 SVR4/EABI -fpic SVR4 pic object file
24575 SVR4/EABI -fPIC SVR4 PIC translation unit
24576 SVR4/EABI -mrelocatable EABI TOC function
24577 SVR4/EABI -maix AIX TOC object file
24578 SVR4/EABI -maix -mminimal-toc
24579 AIX minimal TOC translation unit
24581 Name Reg. Set by entries contains:
24582 made by addrs? fp? sum?
24584 AIX TOC 2 crt0 as Y option option
24585 AIX minimal TOC 30 prolog gcc Y Y option
24586 SVR4 SDATA 13 crt0 gcc N Y N
24587 SVR4 pic 30 prolog ld Y not yet N
24588 SVR4 PIC 30 prolog gcc Y option option
24589 EABI TOC 30 prolog gcc Y option option
24593 /* Hash functions for the hash table. */
24596 rs6000_hash_constant (rtx k
)
24598 enum rtx_code code
= GET_CODE (k
);
24599 enum machine_mode mode
= GET_MODE (k
);
24600 unsigned result
= (code
<< 3) ^ mode
;
24601 const char *format
;
24604 format
= GET_RTX_FORMAT (code
);
24605 flen
= strlen (format
);
24611 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
24614 if (mode
!= VOIDmode
)
24615 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
24627 for (; fidx
< flen
; fidx
++)
24628 switch (format
[fidx
])
24633 const char *str
= XSTR (k
, fidx
);
24634 len
= strlen (str
);
24635 result
= result
* 613 + len
;
24636 for (i
= 0; i
< len
; i
++)
24637 result
= result
* 613 + (unsigned) str
[i
];
24642 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
24646 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
24649 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
24650 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
24654 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
24655 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
24662 gcc_unreachable ();
24669 toc_hash_function (const void *hash_entry
)
24671 const struct toc_hash_struct
*thc
=
24672 (const struct toc_hash_struct
*) hash_entry
;
24673 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
24676 /* Compare H1 and H2 for equivalence. */
24679 toc_hash_eq (const void *h1
, const void *h2
)
24681 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
24682 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
24684 if (((const struct toc_hash_struct
*) h1
)->key_mode
24685 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
24688 return rtx_equal_p (r1
, r2
);
24691 /* These are the names given by the C++ front-end to vtables, and
24692 vtable-like objects. Ideally, this logic should not be here;
24693 instead, there should be some programmatic way of inquiring as
24694 to whether or not an object is a vtable. */
24696 #define VTABLE_NAME_P(NAME) \
24697 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
24698 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
24699 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
24700 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
24701 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
24703 #ifdef NO_DOLLAR_IN_LABEL
24704 /* Return a GGC-allocated character string translating dollar signs in
24705 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
24708 rs6000_xcoff_strip_dollar (const char *name
)
24714 q
= (const char *) strchr (name
, '$');
24716 if (q
== 0 || q
== name
)
24719 len
= strlen (name
);
24720 strip
= XALLOCAVEC (char, len
+ 1);
24721 strcpy (strip
, name
);
24722 p
= strip
+ (q
- name
);
24726 p
= strchr (p
+ 1, '$');
24729 return ggc_alloc_string (strip
, len
);
24734 rs6000_output_symbol_ref (FILE *file
, rtx x
)
24736 /* Currently C++ toc references to vtables can be emitted before it
24737 is decided whether the vtable is public or private. If this is
24738 the case, then the linker will eventually complain that there is
24739 a reference to an unknown section. Thus, for vtables only,
24740 we emit the TOC reference to reference the symbol and not the
24742 const char *name
= XSTR (x
, 0);
24744 if (VTABLE_NAME_P (name
))
24746 RS6000_OUTPUT_BASENAME (file
, name
);
24749 assemble_name (file
, name
);
24752 /* Output a TOC entry. We derive the entry name from what is being
24756 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
24759 const char *name
= buf
;
24761 HOST_WIDE_INT offset
= 0;
24763 gcc_assert (!TARGET_NO_TOC
);
24765 /* When the linker won't eliminate them, don't output duplicate
24766 TOC entries (this happens on AIX if there is any kind of TOC,
24767 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
24769 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
24771 struct toc_hash_struct
*h
;
24774 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
24775 time because GGC is not initialized at that point. */
24776 if (toc_hash_table
== NULL
)
24777 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
24778 toc_hash_eq
, NULL
);
24780 h
= ggc_alloc_toc_hash_struct ();
24782 h
->key_mode
= mode
;
24783 h
->labelno
= labelno
;
24785 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
24786 if (*found
== NULL
)
24788 else /* This is indeed a duplicate.
24789 Set this label equal to that label. */
24791 fputs ("\t.set ", file
);
24792 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24793 fprintf (file
, "%d,", labelno
);
24794 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24795 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24799 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
24800 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
24801 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
24803 fputs ("\t.set ", file
);
24804 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24805 fprintf (file
, "%d,", labelno
);
24806 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24807 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24815 /* If we're going to put a double constant in the TOC, make sure it's
24816 aligned properly when strict alignment is on. */
24817 if (GET_CODE (x
) == CONST_DOUBLE
24818 && STRICT_ALIGNMENT
24819 && GET_MODE_BITSIZE (mode
) >= 64
24820 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
24821 ASM_OUTPUT_ALIGN (file
, 3);
24824 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
24826 /* Handle FP constants specially. Note that if we have a minimal
24827 TOC, things we put here aren't actually in the TOC, so we can allow
24829 if (GET_CODE (x
) == CONST_DOUBLE
&&
24830 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
24832 REAL_VALUE_TYPE rv
;
24835 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24836 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24837 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
24839 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
24843 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24844 fputs (DOUBLE_INT_ASM_OP
, file
);
24846 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24847 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24848 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24849 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
24850 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24851 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
24852 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
24853 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
24858 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24859 fputs ("\t.long ", file
);
24861 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24862 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24863 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24864 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
24865 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24866 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24870 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24871 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
24873 REAL_VALUE_TYPE rv
;
24876 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24878 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24879 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
24881 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
24885 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24886 fputs (DOUBLE_INT_ASM_OP
, file
);
24888 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24889 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24890 fprintf (file
, "0x%lx%08lx\n",
24891 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24892 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
24897 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24898 fputs ("\t.long ", file
);
24900 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24901 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24902 fprintf (file
, "0x%lx,0x%lx\n",
24903 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24907 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24908 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
24910 REAL_VALUE_TYPE rv
;
24913 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24914 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24915 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
24917 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
24921 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24922 fputs (DOUBLE_INT_ASM_OP
, file
);
24924 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24925 if (WORDS_BIG_ENDIAN
)
24926 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
24928 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24933 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24934 fputs ("\t.long ", file
);
24936 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24937 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24941 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
24943 unsigned HOST_WIDE_INT low
;
24944 HOST_WIDE_INT high
;
24946 low
= INTVAL (x
) & 0xffffffff;
24947 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
24949 /* TOC entries are always Pmode-sized, so when big-endian
24950 smaller integer constants in the TOC need to be padded.
24951 (This is still a win over putting the constants in
24952 a separate constant pool, because then we'd have
24953 to have both a TOC entry _and_ the actual constant.)
24955 For a 32-bit target, CONST_INT values are loaded and shifted
24956 entirely within `low' and can be stored in one TOC entry. */
24958 /* It would be easy to make this work, but it doesn't now. */
24959 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
24961 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
24964 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
24965 high
= (HOST_WIDE_INT
) low
>> 32;
24971 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24972 fputs (DOUBLE_INT_ASM_OP
, file
);
24974 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
24975 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24976 fprintf (file
, "0x%lx%08lx\n",
24977 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24982 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
24984 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24985 fputs ("\t.long ", file
);
24987 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
24988 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24989 fprintf (file
, "0x%lx,0x%lx\n",
24990 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24994 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24995 fputs ("\t.long ", file
);
24997 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
24998 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
25004 if (GET_CODE (x
) == CONST
)
25006 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
25007 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
25009 base
= XEXP (XEXP (x
, 0), 0);
25010 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
25013 switch (GET_CODE (base
))
25016 name
= XSTR (base
, 0);
25020 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
25021 CODE_LABEL_NUMBER (XEXP (base
, 0)));
25025 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
25029 gcc_unreachable ();
25032 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25033 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
25036 fputs ("\t.tc ", file
);
25037 RS6000_OUTPUT_BASENAME (file
, name
);
25040 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
25042 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
25044 /* Mark large TOC symbols on AIX with [TE] so they are mapped
25045 after other TOC symbols, reducing overflow of small TOC access
25046 to [TC] symbols. */
25047 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
25048 ? "[TE]," : "[TC],", file
);
25051 /* Currently C++ toc references to vtables can be emitted before it
25052 is decided whether the vtable is public or private. If this is
25053 the case, then the linker will eventually complain that there is
25054 a TOC reference to an unknown section. Thus, for vtables only,
25055 we emit the TOC reference to reference the symbol and not the
25057 if (VTABLE_NAME_P (name
))
25059 RS6000_OUTPUT_BASENAME (file
, name
);
25061 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
25062 else if (offset
> 0)
25063 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
25066 output_addr_const (file
, x
);
25069 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
25070 && SYMBOL_REF_TLS_MODEL (base
) != 0)
25072 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
25073 fputs ("@le", file
);
25074 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
25075 fputs ("@ie", file
);
25076 /* Use global-dynamic for local-dynamic. */
25077 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
25078 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
25081 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
25082 fputs ("\t.tc .", file
);
25083 RS6000_OUTPUT_BASENAME (file
, name
);
25084 fputs ("[TC],", file
);
25085 output_addr_const (file
, x
);
25086 fputs ("@m", file
);
25094 /* Output an assembler pseudo-op to write an ASCII string of N characters
25095 starting at P to FILE.
25097 On the RS/6000, we have to do this using the .byte operation and
25098 write out special characters outside the quoted string.
25099 Also, the assembler is broken; very long strings are truncated,
25100 so we must artificially break them up early. */
25103 output_ascii (FILE *file
, const char *p
, int n
)
25106 int i
, count_string
;
25107 const char *for_string
= "\t.byte \"";
25108 const char *for_decimal
= "\t.byte ";
25109 const char *to_close
= NULL
;
25112 for (i
= 0; i
< n
; i
++)
25115 if (c
>= ' ' && c
< 0177)
25118 fputs (for_string
, file
);
25121 /* Write two quotes to get one. */
25129 for_decimal
= "\"\n\t.byte ";
25133 if (count_string
>= 512)
25135 fputs (to_close
, file
);
25137 for_string
= "\t.byte \"";
25138 for_decimal
= "\t.byte ";
25146 fputs (for_decimal
, file
);
25147 fprintf (file
, "%d", c
);
25149 for_string
= "\n\t.byte \"";
25150 for_decimal
= ", ";
25156 /* Now close the string if we have written one. Then end the line. */
25158 fputs (to_close
, file
);
25161 /* Generate a unique section name for FILENAME for a section type
25162 represented by SECTION_DESC. Output goes into BUF.
25164 SECTION_DESC can be any string, as long as it is different for each
25165 possible section type.
25167 We name the section in the same manner as xlc. The name begins with an
25168 underscore followed by the filename (after stripping any leading directory
25169 names) with the last period replaced by the string SECTION_DESC. If
25170 FILENAME does not contain a period, SECTION_DESC is appended to the end of
25174 rs6000_gen_section_name (char **buf
, const char *filename
,
25175 const char *section_desc
)
25177 const char *q
, *after_last_slash
, *last_period
= 0;
25181 after_last_slash
= filename
;
25182 for (q
= filename
; *q
; q
++)
25185 after_last_slash
= q
+ 1;
25186 else if (*q
== '.')
25190 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
25191 *buf
= (char *) xmalloc (len
);
25196 for (q
= after_last_slash
; *q
; q
++)
25198 if (q
== last_period
)
25200 strcpy (p
, section_desc
);
25201 p
+= strlen (section_desc
);
25205 else if (ISALNUM (*q
))
25209 if (last_period
== 0)
25210 strcpy (p
, section_desc
);
25215 /* Emit profile function. */
25218 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
25220 /* Non-standard profiling for kernels, which just saves LR then calls
25221 _mcount without worrying about arg saves. The idea is to change
25222 the function prologue as little as possible as it isn't easy to
25223 account for arg save/restore code added just for _mcount. */
25224 if (TARGET_PROFILE_KERNEL
)
25227 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25229 #ifndef NO_PROFILE_COUNTERS
25230 # define NO_PROFILE_COUNTERS 0
25232 if (NO_PROFILE_COUNTERS
)
25233 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25234 LCT_NORMAL
, VOIDmode
, 0);
25238 const char *label_name
;
25241 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25242 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
25243 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
25245 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25246 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
25249 else if (DEFAULT_ABI
== ABI_DARWIN
)
25251 const char *mcount_name
= RS6000_MCOUNT
;
25252 int caller_addr_regno
= LR_REGNO
;
25254 /* Be conservative and always set this, at least for now. */
25255 crtl
->uses_pic_offset_table
= 1;
25258 /* For PIC code, set up a stub and collect the caller's address
25259 from r0, which is where the prologue puts it. */
25260 if (MACHOPIC_INDIRECT
25261 && crtl
->uses_pic_offset_table
)
25262 caller_addr_regno
= 0;
25264 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
25265 LCT_NORMAL
, VOIDmode
, 1,
25266 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
25270 /* Write function profiler code. */
25273 output_function_profiler (FILE *file
, int labelno
)
25277 switch (DEFAULT_ABI
)
25280 gcc_unreachable ();
25285 warning (0, "no profiling of 64-bit code for this ABI");
25288 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25289 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
25290 if (NO_PROFILE_COUNTERS
)
25292 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25293 reg_names
[0], reg_names
[1]);
25295 else if (TARGET_SECURE_PLT
&& flag_pic
)
25297 if (TARGET_LINK_STACK
)
25300 get_ppc476_thunk_name (name
);
25301 asm_fprintf (file
, "\tbl %s\n", name
);
25304 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
25305 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25306 reg_names
[0], reg_names
[1]);
25307 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25308 asm_fprintf (file
, "\taddis %s,%s,",
25309 reg_names
[12], reg_names
[12]);
25310 assemble_name (file
, buf
);
25311 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
25312 assemble_name (file
, buf
);
25313 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
25315 else if (flag_pic
== 1)
25317 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
25318 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25319 reg_names
[0], reg_names
[1]);
25320 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25321 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
25322 assemble_name (file
, buf
);
25323 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
25325 else if (flag_pic
> 1)
25327 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25328 reg_names
[0], reg_names
[1]);
25329 /* Now, we need to get the address of the label. */
25330 if (TARGET_LINK_STACK
)
25333 get_ppc476_thunk_name (name
);
25334 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
25335 assemble_name (file
, buf
);
25336 fputs ("-.\n1:", file
);
25337 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25338 asm_fprintf (file
, "\taddi %s,%s,4\n",
25339 reg_names
[11], reg_names
[11]);
25343 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
25344 assemble_name (file
, buf
);
25345 fputs ("-.\n1:", file
);
25346 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25348 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
25349 reg_names
[0], reg_names
[11]);
25350 asm_fprintf (file
, "\tadd %s,%s,%s\n",
25351 reg_names
[0], reg_names
[0], reg_names
[11]);
25355 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
25356 assemble_name (file
, buf
);
25357 fputs ("@ha\n", file
);
25358 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25359 reg_names
[0], reg_names
[1]);
25360 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
25361 assemble_name (file
, buf
);
25362 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
25365 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
25366 fprintf (file
, "\tbl %s%s\n",
25367 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
25373 /* Don't do anything, done in output_profile_hook (). */
25380 /* The following variable value is the last issued insn. */
25382 static rtx last_scheduled_insn
;
25384 /* The following variable helps to balance issuing of load and
25385 store instructions */
25387 static int load_store_pendulum
;
25389 /* Power4 load update and store update instructions are cracked into a
25390 load or store and an integer insn which are executed in the same cycle.
25391 Branches have their own dispatch slot which does not count against the
25392 GCC issue rate, but it changes the program flow so there are no other
25393 instructions to issue in this cycle. */
25396 rs6000_variable_issue_1 (rtx insn
, int more
)
25398 last_scheduled_insn
= insn
;
25399 if (GET_CODE (PATTERN (insn
)) == USE
25400 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25402 cached_can_issue_more
= more
;
25403 return cached_can_issue_more
;
25406 if (insn_terminates_group_p (insn
, current_group
))
25408 cached_can_issue_more
= 0;
25409 return cached_can_issue_more
;
25412 /* If no reservation, but reach here */
25413 if (recog_memoized (insn
) < 0)
25416 if (rs6000_sched_groups
)
25418 if (is_microcoded_insn (insn
))
25419 cached_can_issue_more
= 0;
25420 else if (is_cracked_insn (insn
))
25421 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
25423 cached_can_issue_more
= more
- 1;
25425 return cached_can_issue_more
;
25428 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
25431 cached_can_issue_more
= more
- 1;
25432 return cached_can_issue_more
;
25436 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
25438 int r
= rs6000_variable_issue_1 (insn
, more
);
25440 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
25444 /* Adjust the cost of a scheduling dependency. Return the new cost of
25445 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
25448 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
25450 enum attr_type attr_type
;
25452 if (! recog_memoized (insn
))
25455 switch (REG_NOTE_KIND (link
))
25459 /* Data dependency; DEP_INSN writes a register that INSN reads
25460 some cycles later. */
25462 /* Separate a load from a narrower, dependent store. */
25463 if (rs6000_sched_groups
25464 && GET_CODE (PATTERN (insn
)) == SET
25465 && GET_CODE (PATTERN (dep_insn
)) == SET
25466 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
25467 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
25468 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
25469 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
25472 attr_type
= get_attr_type (insn
);
25477 /* Tell the first scheduling pass about the latency between
25478 a mtctr and bctr (and mtlr and br/blr). The first
25479 scheduling pass will not know about this latency since
25480 the mtctr instruction, which has the latency associated
25481 to it, will be generated by reload. */
25484 /* Leave some extra cycles between a compare and its
25485 dependent branch, to inhibit expensive mispredicts. */
25486 if ((rs6000_cpu_attr
== CPU_PPC603
25487 || rs6000_cpu_attr
== CPU_PPC604
25488 || rs6000_cpu_attr
== CPU_PPC604E
25489 || rs6000_cpu_attr
== CPU_PPC620
25490 || rs6000_cpu_attr
== CPU_PPC630
25491 || rs6000_cpu_attr
== CPU_PPC750
25492 || rs6000_cpu_attr
== CPU_PPC7400
25493 || rs6000_cpu_attr
== CPU_PPC7450
25494 || rs6000_cpu_attr
== CPU_PPCE5500
25495 || rs6000_cpu_attr
== CPU_PPCE6500
25496 || rs6000_cpu_attr
== CPU_POWER4
25497 || rs6000_cpu_attr
== CPU_POWER5
25498 || rs6000_cpu_attr
== CPU_POWER7
25499 || rs6000_cpu_attr
== CPU_POWER8
25500 || rs6000_cpu_attr
== CPU_CELL
)
25501 && recog_memoized (dep_insn
)
25502 && (INSN_CODE (dep_insn
) >= 0))
25504 switch (get_attr_type (dep_insn
))
25508 case TYPE_DELAYED_COMPARE
:
25509 case TYPE_IMUL_COMPARE
:
25510 case TYPE_LMUL_COMPARE
:
25511 case TYPE_FPCOMPARE
:
25512 case TYPE_CR_LOGICAL
:
25513 case TYPE_DELAYED_CR
:
25522 case TYPE_STORE_UX
:
25524 case TYPE_FPSTORE_U
:
25525 case TYPE_FPSTORE_UX
:
25526 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25527 && recog_memoized (dep_insn
)
25528 && (INSN_CODE (dep_insn
) >= 0))
25531 if (GET_CODE (PATTERN (insn
)) != SET
)
25532 /* If this happens, we have to extend this to schedule
25533 optimally. Return default for now. */
25536 /* Adjust the cost for the case where the value written
25537 by a fixed point operation is used as the address
25538 gen value on a store. */
25539 switch (get_attr_type (dep_insn
))
25546 if (! store_data_bypass_p (dep_insn
, insn
))
25550 case TYPE_LOAD_EXT
:
25551 case TYPE_LOAD_EXT_U
:
25552 case TYPE_LOAD_EXT_UX
:
25553 case TYPE_VAR_SHIFT_ROTATE
:
25554 case TYPE_VAR_DELAYED_COMPARE
:
25556 if (! store_data_bypass_p (dep_insn
, insn
))
25562 case TYPE_FAST_COMPARE
:
25565 case TYPE_INSERT_WORD
:
25566 case TYPE_INSERT_DWORD
:
25567 case TYPE_FPLOAD_U
:
25568 case TYPE_FPLOAD_UX
:
25570 case TYPE_STORE_UX
:
25571 case TYPE_FPSTORE_U
:
25572 case TYPE_FPSTORE_UX
:
25574 if (! store_data_bypass_p (dep_insn
, insn
))
25582 case TYPE_IMUL_COMPARE
:
25583 case TYPE_LMUL_COMPARE
:
25585 if (! store_data_bypass_p (dep_insn
, insn
))
25591 if (! store_data_bypass_p (dep_insn
, insn
))
25597 if (! store_data_bypass_p (dep_insn
, insn
))
25610 case TYPE_LOAD_EXT
:
25611 case TYPE_LOAD_EXT_U
:
25612 case TYPE_LOAD_EXT_UX
:
25613 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25614 && recog_memoized (dep_insn
)
25615 && (INSN_CODE (dep_insn
) >= 0))
25618 /* Adjust the cost for the case where the value written
25619 by a fixed point instruction is used within the address
25620 gen portion of a subsequent load(u)(x) */
25621 switch (get_attr_type (dep_insn
))
25628 if (set_to_load_agen (dep_insn
, insn
))
25632 case TYPE_LOAD_EXT
:
25633 case TYPE_LOAD_EXT_U
:
25634 case TYPE_LOAD_EXT_UX
:
25635 case TYPE_VAR_SHIFT_ROTATE
:
25636 case TYPE_VAR_DELAYED_COMPARE
:
25638 if (set_to_load_agen (dep_insn
, insn
))
25644 case TYPE_FAST_COMPARE
:
25647 case TYPE_INSERT_WORD
:
25648 case TYPE_INSERT_DWORD
:
25649 case TYPE_FPLOAD_U
:
25650 case TYPE_FPLOAD_UX
:
25652 case TYPE_STORE_UX
:
25653 case TYPE_FPSTORE_U
:
25654 case TYPE_FPSTORE_UX
:
25656 if (set_to_load_agen (dep_insn
, insn
))
25664 case TYPE_IMUL_COMPARE
:
25665 case TYPE_LMUL_COMPARE
:
25667 if (set_to_load_agen (dep_insn
, insn
))
25673 if (set_to_load_agen (dep_insn
, insn
))
25679 if (set_to_load_agen (dep_insn
, insn
))
25690 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25691 && recog_memoized (dep_insn
)
25692 && (INSN_CODE (dep_insn
) >= 0)
25693 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
25700 /* Fall out to return default cost. */
25704 case REG_DEP_OUTPUT
:
25705 /* Output dependency; DEP_INSN writes a register that INSN writes some
25707 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25708 && recog_memoized (dep_insn
)
25709 && (INSN_CODE (dep_insn
) >= 0))
25711 attr_type
= get_attr_type (insn
);
25716 if (get_attr_type (dep_insn
) == TYPE_FP
)
25720 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
25728 /* Anti dependency; DEP_INSN reads a register that INSN writes some
25733 gcc_unreachable ();
25739 /* Debug version of rs6000_adjust_cost. */
25742 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
25744 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
25750 switch (REG_NOTE_KIND (link
))
25752 default: dep
= "unknown depencency"; break;
25753 case REG_DEP_TRUE
: dep
= "data dependency"; break;
25754 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
25755 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
25759 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
25760 "%s, insn:\n", ret
, cost
, dep
);
25768 /* The function returns a true if INSN is microcoded.
25769 Return false otherwise. */
25772 is_microcoded_insn (rtx insn
)
25774 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25775 || GET_CODE (PATTERN (insn
)) == USE
25776 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25779 if (rs6000_cpu_attr
== CPU_CELL
)
25780 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
25782 if (rs6000_sched_groups
25783 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25785 enum attr_type type
= get_attr_type (insn
);
25786 if (type
== TYPE_LOAD_EXT_U
25787 || type
== TYPE_LOAD_EXT_UX
25788 || type
== TYPE_LOAD_UX
25789 || type
== TYPE_STORE_UX
25790 || type
== TYPE_MFCR
)
25797 /* The function returns true if INSN is cracked into 2 instructions
25798 by the processor (and therefore occupies 2 issue slots). */
25801 is_cracked_insn (rtx insn
)
25803 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25804 || GET_CODE (PATTERN (insn
)) == USE
25805 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25808 if (rs6000_sched_groups
25809 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25811 enum attr_type type
= get_attr_type (insn
);
25812 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
25813 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
25814 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
25815 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
25816 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
25817 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
25818 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
25819 || type
== TYPE_INSERT_WORD
)
25826 /* The function returns true if INSN can be issued only from
25827 the branch slot. */
25830 is_branch_slot_insn (rtx insn
)
25832 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25833 || GET_CODE (PATTERN (insn
)) == USE
25834 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25837 if (rs6000_sched_groups
)
25839 enum attr_type type
= get_attr_type (insn
);
25840 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
25848 /* The function returns true if out_inst sets a value that is
25849 used in the address generation computation of in_insn */
25851 set_to_load_agen (rtx out_insn
, rtx in_insn
)
25853 rtx out_set
, in_set
;
25855 /* For performance reasons, only handle the simple case where
25856 both loads are a single_set. */
25857 out_set
= single_set (out_insn
);
25860 in_set
= single_set (in_insn
);
25862 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
25868 /* Try to determine base/offset/size parts of the given MEM.
25869 Return true if successful, false if all the values couldn't
25872 This function only looks for REG or REG+CONST address forms.
25873 REG+REG address form will return false. */
25876 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
25877 HOST_WIDE_INT
*size
)
25880 if MEM_SIZE_KNOWN_P (mem
)
25881 *size
= MEM_SIZE (mem
);
25885 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
25886 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
25888 addr_rtx
= (XEXP (mem
, 0));
25890 if (GET_CODE (addr_rtx
) == REG
)
25895 else if (GET_CODE (addr_rtx
) == PLUS
25896 && CONST_INT_P (XEXP (addr_rtx
, 1)))
25898 *base
= XEXP (addr_rtx
, 0);
25899 *offset
= INTVAL (XEXP (addr_rtx
, 1));
25907 /* The function returns true if the target storage location of
25908 mem1 is adjacent to the target storage location of mem2 */
25909 /* Return 1 if memory locations are adjacent. */
25912 adjacent_mem_locations (rtx mem1
, rtx mem2
)
25915 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25917 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25918 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25919 return ((REGNO (reg1
) == REGNO (reg2
))
25920 && ((off1
+ size1
== off2
)
25921 || (off2
+ size2
== off1
)));
25926 /* This function returns true if it can be determined that the two MEM
25927 locations overlap by at least 1 byte based on base reg/offset/size. */
25930 mem_locations_overlap (rtx mem1
, rtx mem2
)
25933 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25935 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25936 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25937 return ((REGNO (reg1
) == REGNO (reg2
))
25938 && (((off1
<= off2
) && (off1
+ size1
> off2
))
25939 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
25944 /* A C statement (sans semicolon) to update the integer scheduling
25945 priority INSN_PRIORITY (INSN). Increase the priority to execute the
25946 INSN earlier, reduce the priority to execute INSN later. Do not
25947 define this macro if you do not need to adjust the scheduling
25948 priorities of insns. */
25951 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
25953 rtx load_mem
, str_mem
;
25954 /* On machines (like the 750) which have asymmetric integer units,
25955 where one integer unit can do multiply and divides and the other
25956 can't, reduce the priority of multiply/divide so it is scheduled
25957 before other integer operations. */
25960 if (! INSN_P (insn
))
25963 if (GET_CODE (PATTERN (insn
)) == USE
)
25966 switch (rs6000_cpu_attr
) {
25968 switch (get_attr_type (insn
))
25975 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
25976 priority
, priority
);
25977 if (priority
>= 0 && priority
< 0x01000000)
25984 if (insn_must_be_first_in_group (insn
)
25985 && reload_completed
25986 && current_sched_info
->sched_max_insns_priority
25987 && rs6000_sched_restricted_insns_priority
)
25990 /* Prioritize insns that can be dispatched only in the first
25992 if (rs6000_sched_restricted_insns_priority
== 1)
25993 /* Attach highest priority to insn. This means that in
25994 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
25995 precede 'priority' (critical path) considerations. */
25996 return current_sched_info
->sched_max_insns_priority
;
25997 else if (rs6000_sched_restricted_insns_priority
== 2)
25998 /* Increase priority of insn by a minimal amount. This means that in
25999 haifa-sched.c:ready_sort(), only 'priority' (critical path)
26000 considerations precede dispatch-slot restriction considerations. */
26001 return (priority
+ 1);
26004 if (rs6000_cpu
== PROCESSOR_POWER6
26005 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
26006 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
26007 /* Attach highest priority to insn if the scheduler has just issued two
26008 stores and this instruction is a load, or two loads and this instruction
26009 is a store. Power6 wants loads and stores scheduled alternately
26011 return current_sched_info
->sched_max_insns_priority
;
26016 /* Return true if the instruction is nonpipelined on the Cell. */
26018 is_nonpipeline_insn (rtx insn
)
26020 enum attr_type type
;
26021 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26022 || GET_CODE (PATTERN (insn
)) == USE
26023 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26026 type
= get_attr_type (insn
);
26027 if (type
== TYPE_IMUL
26028 || type
== TYPE_IMUL2
26029 || type
== TYPE_IMUL3
26030 || type
== TYPE_LMUL
26031 || type
== TYPE_IDIV
26032 || type
== TYPE_LDIV
26033 || type
== TYPE_SDIV
26034 || type
== TYPE_DDIV
26035 || type
== TYPE_SSQRT
26036 || type
== TYPE_DSQRT
26037 || type
== TYPE_MFCR
26038 || type
== TYPE_MFCRF
26039 || type
== TYPE_MFJMPR
)
26047 /* Return how many instructions the machine can issue per cycle. */
26050 rs6000_issue_rate (void)
26052 /* Unless scheduling for register pressure, use issue rate of 1 for
26053 first scheduling pass to decrease degradation. */
26054 if (!reload_completed
&& !flag_sched_pressure
)
26057 switch (rs6000_cpu_attr
) {
26059 case CPU_PPC601
: /* ? */
26069 case CPU_PPCE300C2
:
26070 case CPU_PPCE300C3
:
26071 case CPU_PPCE500MC
:
26072 case CPU_PPCE500MC64
:
26095 /* Return how many instructions to look ahead for better insn
26099 rs6000_use_sched_lookahead (void)
26101 switch (rs6000_cpu_attr
)
26108 return (reload_completed
? 8 : 0);
26115 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
26117 rs6000_use_sched_lookahead_guard (rtx insn
)
26119 if (rs6000_cpu_attr
!= CPU_CELL
)
26122 if (insn
== NULL_RTX
|| !INSN_P (insn
))
26125 if (!reload_completed
26126 || is_nonpipeline_insn (insn
)
26127 || is_microcoded_insn (insn
))
26133 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
26134 and return true. */
26137 find_mem_ref (rtx pat
, rtx
*mem_ref
)
26142 /* stack_tie does not produce any real memory traffic. */
26143 if (tie_operand (pat
, VOIDmode
))
26146 if (GET_CODE (pat
) == MEM
)
26152 /* Recursively process the pattern. */
26153 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
26155 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
26159 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
26162 else if (fmt
[i
] == 'E')
26163 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
26165 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
26173 /* Determine if PAT is a PATTERN of a load insn. */
26176 is_load_insn1 (rtx pat
, rtx
*load_mem
)
26178 if (!pat
|| pat
== NULL_RTX
)
26181 if (GET_CODE (pat
) == SET
)
26182 return find_mem_ref (SET_SRC (pat
), load_mem
);
26184 if (GET_CODE (pat
) == PARALLEL
)
26188 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26189 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
26196 /* Determine if INSN loads from memory. */
26199 is_load_insn (rtx insn
, rtx
*load_mem
)
26201 if (!insn
|| !INSN_P (insn
))
26207 return is_load_insn1 (PATTERN (insn
), load_mem
);
26210 /* Determine if PAT is a PATTERN of a store insn. */
26213 is_store_insn1 (rtx pat
, rtx
*str_mem
)
26215 if (!pat
|| pat
== NULL_RTX
)
26218 if (GET_CODE (pat
) == SET
)
26219 return find_mem_ref (SET_DEST (pat
), str_mem
);
26221 if (GET_CODE (pat
) == PARALLEL
)
26225 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26226 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
26233 /* Determine if INSN stores to memory. */
26236 is_store_insn (rtx insn
, rtx
*str_mem
)
26238 if (!insn
|| !INSN_P (insn
))
26241 return is_store_insn1 (PATTERN (insn
), str_mem
);
26244 /* Returns whether the dependence between INSN and NEXT is considered
26245 costly by the given target. */
26248 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
26252 rtx load_mem
, str_mem
;
26254 /* If the flag is not enabled - no dependence is considered costly;
26255 allow all dependent insns in the same group.
26256 This is the most aggressive option. */
26257 if (rs6000_sched_costly_dep
== no_dep_costly
)
26260 /* If the flag is set to 1 - a dependence is always considered costly;
26261 do not allow dependent instructions in the same group.
26262 This is the most conservative option. */
26263 if (rs6000_sched_costly_dep
== all_deps_costly
)
26266 insn
= DEP_PRO (dep
);
26267 next
= DEP_CON (dep
);
26269 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
26270 && is_load_insn (next
, &load_mem
)
26271 && is_store_insn (insn
, &str_mem
))
26272 /* Prevent load after store in the same group. */
26275 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
26276 && is_load_insn (next
, &load_mem
)
26277 && is_store_insn (insn
, &str_mem
)
26278 && DEP_TYPE (dep
) == REG_DEP_TRUE
26279 && mem_locations_overlap(str_mem
, load_mem
))
26280 /* Prevent load after store in the same group if it is a true
26284 /* The flag is set to X; dependences with latency >= X are considered costly,
26285 and will not be scheduled in the same group. */
26286 if (rs6000_sched_costly_dep
<= max_dep_latency
26287 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
26293 /* Return the next insn after INSN that is found before TAIL is reached,
26294 skipping any "non-active" insns - insns that will not actually occupy
26295 an issue slot. Return NULL_RTX if such an insn is not found. */
26298 get_next_active_insn (rtx insn
, rtx tail
)
26300 if (insn
== NULL_RTX
|| insn
== tail
)
26305 insn
= NEXT_INSN (insn
);
26306 if (insn
== NULL_RTX
|| insn
== tail
)
26310 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
26311 || (NONJUMP_INSN_P (insn
)
26312 && GET_CODE (PATTERN (insn
)) != USE
26313 && GET_CODE (PATTERN (insn
)) != CLOBBER
26314 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
26320 /* We are about to begin issuing insns for this clock cycle. */
26323 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
26324 rtx
*ready ATTRIBUTE_UNUSED
,
26325 int *pn_ready ATTRIBUTE_UNUSED
,
26326 int clock_var ATTRIBUTE_UNUSED
)
26328 int n_ready
= *pn_ready
;
26331 fprintf (dump
, "// rs6000_sched_reorder :\n");
26333 /* Reorder the ready list, if the second to last ready insn
26334 is a nonepipeline insn. */
26335 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
26337 if (is_nonpipeline_insn (ready
[n_ready
- 1])
26338 && (recog_memoized (ready
[n_ready
- 2]) > 0))
26339 /* Simply swap first two insns. */
26341 rtx tmp
= ready
[n_ready
- 1];
26342 ready
[n_ready
- 1] = ready
[n_ready
- 2];
26343 ready
[n_ready
- 2] = tmp
;
26347 if (rs6000_cpu
== PROCESSOR_POWER6
)
26348 load_store_pendulum
= 0;
26350 return rs6000_issue_rate ();
26353 /* Like rs6000_sched_reorder, but called after issuing each insn. */
26356 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
26357 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
26360 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
26362 /* For Power6, we need to handle some special cases to try and keep the
26363 store queue from overflowing and triggering expensive flushes.
26365 This code monitors how load and store instructions are being issued
26366 and skews the ready list one way or the other to increase the likelihood
26367 that a desired instruction is issued at the proper time.
26369 A couple of things are done. First, we maintain a "load_store_pendulum"
26370 to track the current state of load/store issue.
26372 - If the pendulum is at zero, then no loads or stores have been
26373 issued in the current cycle so we do nothing.
26375 - If the pendulum is 1, then a single load has been issued in this
26376 cycle and we attempt to locate another load in the ready list to
26379 - If the pendulum is -2, then two stores have already been
26380 issued in this cycle, so we increase the priority of the first load
26381 in the ready list to increase it's likelihood of being chosen first
26384 - If the pendulum is -1, then a single store has been issued in this
26385 cycle and we attempt to locate another store in the ready list to
26386 issue with it, preferring a store to an adjacent memory location to
26387 facilitate store pairing in the store queue.
26389 - If the pendulum is 2, then two loads have already been
26390 issued in this cycle, so we increase the priority of the first store
26391 in the ready list to increase it's likelihood of being chosen first
26394 - If the pendulum < -2 or > 2, then do nothing.
26396 Note: This code covers the most common scenarios. There exist non
26397 load/store instructions which make use of the LSU and which
26398 would need to be accounted for to strictly model the behavior
26399 of the machine. Those instructions are currently unaccounted
26400 for to help minimize compile time overhead of this code.
26402 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
26406 rtx tmp
, load_mem
, str_mem
;
26408 if (is_store_insn (last_scheduled_insn
, &str_mem
))
26409 /* Issuing a store, swing the load_store_pendulum to the left */
26410 load_store_pendulum
--;
26411 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
26412 /* Issuing a load, swing the load_store_pendulum to the right */
26413 load_store_pendulum
++;
26415 return cached_can_issue_more
;
26417 /* If the pendulum is balanced, or there is only one instruction on
26418 the ready list, then all is well, so return. */
26419 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
26420 return cached_can_issue_more
;
26422 if (load_store_pendulum
== 1)
26424 /* A load has been issued in this cycle. Scan the ready list
26425 for another load to issue with it */
26430 if (is_load_insn (ready
[pos
], &load_mem
))
26432 /* Found a load. Move it to the head of the ready list,
26433 and adjust it's priority so that it is more likely to
26436 for (i
=pos
; i
<*pn_ready
-1; i
++)
26437 ready
[i
] = ready
[i
+ 1];
26438 ready
[*pn_ready
-1] = tmp
;
26440 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26441 INSN_PRIORITY (tmp
)++;
26447 else if (load_store_pendulum
== -2)
26449 /* Two stores have been issued in this cycle. Increase the
26450 priority of the first load in the ready list to favor it for
26451 issuing in the next cycle. */
26456 if (is_load_insn (ready
[pos
], &load_mem
)
26458 && INSN_PRIORITY_KNOWN (ready
[pos
]))
26460 INSN_PRIORITY (ready
[pos
])++;
26462 /* Adjust the pendulum to account for the fact that a load
26463 was found and increased in priority. This is to prevent
26464 increasing the priority of multiple loads */
26465 load_store_pendulum
--;
26472 else if (load_store_pendulum
== -1)
26474 /* A store has been issued in this cycle. Scan the ready list for
26475 another store to issue with it, preferring a store to an adjacent
26477 int first_store_pos
= -1;
26483 if (is_store_insn (ready
[pos
], &str_mem
))
26486 /* Maintain the index of the first store found on the
26488 if (first_store_pos
== -1)
26489 first_store_pos
= pos
;
26491 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
26492 && adjacent_mem_locations (str_mem
, str_mem2
))
26494 /* Found an adjacent store. Move it to the head of the
26495 ready list, and adjust it's priority so that it is
26496 more likely to stay there */
26498 for (i
=pos
; i
<*pn_ready
-1; i
++)
26499 ready
[i
] = ready
[i
+ 1];
26500 ready
[*pn_ready
-1] = tmp
;
26502 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26503 INSN_PRIORITY (tmp
)++;
26505 first_store_pos
= -1;
26513 if (first_store_pos
>= 0)
26515 /* An adjacent store wasn't found, but a non-adjacent store was,
26516 so move the non-adjacent store to the front of the ready
26517 list, and adjust its priority so that it is more likely to
26519 tmp
= ready
[first_store_pos
];
26520 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
26521 ready
[i
] = ready
[i
+ 1];
26522 ready
[*pn_ready
-1] = tmp
;
26523 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26524 INSN_PRIORITY (tmp
)++;
26527 else if (load_store_pendulum
== 2)
26529 /* Two loads have been issued in this cycle. Increase the priority
26530 of the first store in the ready list to favor it for issuing in
26536 if (is_store_insn (ready
[pos
], &str_mem
)
26538 && INSN_PRIORITY_KNOWN (ready
[pos
]))
26540 INSN_PRIORITY (ready
[pos
])++;
26542 /* Adjust the pendulum to account for the fact that a store
26543 was found and increased in priority. This is to prevent
26544 increasing the priority of multiple stores */
26545 load_store_pendulum
++;
26554 return cached_can_issue_more
;
26557 /* Return whether the presence of INSN causes a dispatch group termination
26558 of group WHICH_GROUP.
26560 If WHICH_GROUP == current_group, this function will return true if INSN
26561 causes the termination of the current group (i.e, the dispatch group to
26562 which INSN belongs). This means that INSN will be the last insn in the
26563 group it belongs to.
26565 If WHICH_GROUP == previous_group, this function will return true if INSN
26566 causes the termination of the previous group (i.e, the dispatch group that
26567 precedes the group to which INSN belongs). This means that INSN will be
26568 the first insn in the group it belongs to). */
26571 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
26578 first
= insn_must_be_first_in_group (insn
);
26579 last
= insn_must_be_last_in_group (insn
);
26584 if (which_group
== current_group
)
26586 else if (which_group
== previous_group
)
26594 insn_must_be_first_in_group (rtx insn
)
26596 enum attr_type type
;
26600 || DEBUG_INSN_P (insn
)
26601 || GET_CODE (PATTERN (insn
)) == USE
26602 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26605 switch (rs6000_cpu
)
26607 case PROCESSOR_POWER5
:
26608 if (is_cracked_insn (insn
))
26610 case PROCESSOR_POWER4
:
26611 if (is_microcoded_insn (insn
))
26614 if (!rs6000_sched_groups
)
26617 type
= get_attr_type (insn
);
26624 case TYPE_DELAYED_CR
:
26625 case TYPE_CR_LOGICAL
:
26639 case PROCESSOR_POWER6
:
26640 type
= get_attr_type (insn
);
26644 case TYPE_INSERT_DWORD
:
26648 case TYPE_VAR_SHIFT_ROTATE
:
26655 case TYPE_INSERT_WORD
:
26656 case TYPE_DELAYED_COMPARE
:
26657 case TYPE_IMUL_COMPARE
:
26658 case TYPE_LMUL_COMPARE
:
26659 case TYPE_FPCOMPARE
:
26670 case TYPE_LOAD_EXT_UX
:
26672 case TYPE_STORE_UX
:
26673 case TYPE_FPLOAD_U
:
26674 case TYPE_FPLOAD_UX
:
26675 case TYPE_FPSTORE_U
:
26676 case TYPE_FPSTORE_UX
:
26682 case PROCESSOR_POWER7
:
26683 type
= get_attr_type (insn
);
26687 case TYPE_CR_LOGICAL
:
26694 case TYPE_DELAYED_COMPARE
:
26695 case TYPE_VAR_DELAYED_COMPARE
:
26701 case TYPE_LOAD_EXT
:
26702 case TYPE_LOAD_EXT_U
:
26703 case TYPE_LOAD_EXT_UX
:
26705 case TYPE_STORE_UX
:
26706 case TYPE_FPLOAD_U
:
26707 case TYPE_FPLOAD_UX
:
26708 case TYPE_FPSTORE_U
:
26709 case TYPE_FPSTORE_UX
:
26717 case PROCESSOR_POWER8
:
26718 type
= get_attr_type (insn
);
26722 case TYPE_CR_LOGICAL
:
26723 case TYPE_DELAYED_CR
:
26728 case TYPE_DELAYED_COMPARE
:
26729 case TYPE_VAR_DELAYED_COMPARE
:
26730 case TYPE_IMUL_COMPARE
:
26731 case TYPE_LMUL_COMPARE
:
26738 case TYPE_LOAD_EXT
:
26739 case TYPE_LOAD_EXT_U
:
26740 case TYPE_LOAD_EXT_UX
:
26741 case TYPE_STORE_UX
:
26742 case TYPE_VECSTORE
:
26758 insn_must_be_last_in_group (rtx insn
)
26760 enum attr_type type
;
26764 || DEBUG_INSN_P (insn
)
26765 || GET_CODE (PATTERN (insn
)) == USE
26766 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26769 switch (rs6000_cpu
) {
26770 case PROCESSOR_POWER4
:
26771 case PROCESSOR_POWER5
:
26772 if (is_microcoded_insn (insn
))
26775 if (is_branch_slot_insn (insn
))
26779 case PROCESSOR_POWER6
:
26780 type
= get_attr_type (insn
);
26787 case TYPE_VAR_SHIFT_ROTATE
:
26794 case TYPE_DELAYED_COMPARE
:
26795 case TYPE_IMUL_COMPARE
:
26796 case TYPE_LMUL_COMPARE
:
26797 case TYPE_FPCOMPARE
:
26811 case PROCESSOR_POWER7
:
26812 type
= get_attr_type (insn
);
26820 case TYPE_LOAD_EXT_U
:
26821 case TYPE_LOAD_EXT_UX
:
26822 case TYPE_STORE_UX
:
26828 case PROCESSOR_POWER8
:
26829 type
= get_attr_type (insn
);
26839 case TYPE_LOAD_EXT_U
:
26840 case TYPE_LOAD_EXT_UX
:
26841 case TYPE_STORE_UX
:
26854 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
26855 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
26858 is_costly_group (rtx
*group_insns
, rtx next_insn
)
26861 int issue_rate
= rs6000_issue_rate ();
26863 for (i
= 0; i
< issue_rate
; i
++)
26865 sd_iterator_def sd_it
;
26867 rtx insn
= group_insns
[i
];
26872 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
26874 rtx next
= DEP_CON (dep
);
26876 if (next
== next_insn
26877 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
26885 /* Utility of the function redefine_groups.
26886 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
26887 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
26888 to keep it "far" (in a separate group) from GROUP_INSNS, following
26889 one of the following schemes, depending on the value of the flag
26890 -minsert_sched_nops = X:
26891 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
26892 in order to force NEXT_INSN into a separate group.
26893 (2) X < sched_finish_regroup_exact: insert exactly X nops.
26894 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
26895 insertion (has a group just ended, how many vacant issue slots remain in the
26896 last group, and how many dispatch groups were encountered so far). */
26899 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
26900 rtx next_insn
, bool *group_end
, int can_issue_more
,
26905 int issue_rate
= rs6000_issue_rate ();
26906 bool end
= *group_end
;
26909 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
26910 return can_issue_more
;
26912 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
26913 return can_issue_more
;
26915 force
= is_costly_group (group_insns
, next_insn
);
26917 return can_issue_more
;
26919 if (sched_verbose
> 6)
26920 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
26921 *group_count
,can_issue_more
);
26923 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
26926 can_issue_more
= 0;
26928 /* Since only a branch can be issued in the last issue_slot, it is
26929 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
26930 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
26931 in this case the last nop will start a new group and the branch
26932 will be forced to the new group. */
26933 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
26936 /* Do we have a special group ending nop? */
26937 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
26938 || rs6000_cpu_attr
== CPU_POWER8
)
26940 nop
= gen_group_ending_nop ();
26941 emit_insn_before (nop
, next_insn
);
26942 can_issue_more
= 0;
26945 while (can_issue_more
> 0)
26948 emit_insn_before (nop
, next_insn
);
26956 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
26958 int n_nops
= rs6000_sched_insert_nops
;
26960 /* Nops can't be issued from the branch slot, so the effective
26961 issue_rate for nops is 'issue_rate - 1'. */
26962 if (can_issue_more
== 0)
26963 can_issue_more
= issue_rate
;
26965 if (can_issue_more
== 0)
26967 can_issue_more
= issue_rate
- 1;
26970 for (i
= 0; i
< issue_rate
; i
++)
26972 group_insns
[i
] = 0;
26979 emit_insn_before (nop
, next_insn
);
26980 if (can_issue_more
== issue_rate
- 1) /* new group begins */
26983 if (can_issue_more
== 0)
26985 can_issue_more
= issue_rate
- 1;
26988 for (i
= 0; i
< issue_rate
; i
++)
26990 group_insns
[i
] = 0;
26996 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
26999 /* Is next_insn going to start a new group? */
27002 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27003 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27004 || (can_issue_more
< issue_rate
&&
27005 insn_terminates_group_p (next_insn
, previous_group
)));
27006 if (*group_end
&& end
)
27009 if (sched_verbose
> 6)
27010 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
27011 *group_count
, can_issue_more
);
27012 return can_issue_more
;
27015 return can_issue_more
;
27018 /* This function tries to synch the dispatch groups that the compiler "sees"
27019 with the dispatch groups that the processor dispatcher is expected to
27020 form in practice. It tries to achieve this synchronization by forcing the
27021 estimated processor grouping on the compiler (as opposed to the function
27022 'pad_goups' which tries to force the scheduler's grouping on the processor).
27024 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
27025 examines the (estimated) dispatch groups that will be formed by the processor
27026 dispatcher. It marks these group boundaries to reflect the estimated
27027 processor grouping, overriding the grouping that the scheduler had marked.
27028 Depending on the value of the flag '-minsert-sched-nops' this function can
27029 force certain insns into separate groups or force a certain distance between
27030 them by inserting nops, for example, if there exists a "costly dependence"
27033 The function estimates the group boundaries that the processor will form as
27034 follows: It keeps track of how many vacant issue slots are available after
27035 each insn. A subsequent insn will start a new group if one of the following
27037 - no more vacant issue slots remain in the current dispatch group.
27038 - only the last issue slot, which is the branch slot, is vacant, but the next
27039 insn is not a branch.
27040 - only the last 2 or less issue slots, including the branch slot, are vacant,
27041 which means that a cracked insn (which occupies two issue slots) can't be
27042 issued in this group.
27043 - less than 'issue_rate' slots are vacant, and the next insn always needs to
27044 start a new group. */
27047 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27049 rtx insn
, next_insn
;
27051 int can_issue_more
;
27054 int group_count
= 0;
27058 issue_rate
= rs6000_issue_rate ();
27059 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
27060 for (i
= 0; i
< issue_rate
; i
++)
27062 group_insns
[i
] = 0;
27064 can_issue_more
= issue_rate
;
27066 insn
= get_next_active_insn (prev_head_insn
, tail
);
27069 while (insn
!= NULL_RTX
)
27071 slot
= (issue_rate
- can_issue_more
);
27072 group_insns
[slot
] = insn
;
27074 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27075 if (insn_terminates_group_p (insn
, current_group
))
27076 can_issue_more
= 0;
27078 next_insn
= get_next_active_insn (insn
, tail
);
27079 if (next_insn
== NULL_RTX
)
27080 return group_count
+ 1;
27082 /* Is next_insn going to start a new group? */
27084 = (can_issue_more
== 0
27085 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27086 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27087 || (can_issue_more
< issue_rate
&&
27088 insn_terminates_group_p (next_insn
, previous_group
)));
27090 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
27091 next_insn
, &group_end
, can_issue_more
,
27097 can_issue_more
= 0;
27098 for (i
= 0; i
< issue_rate
; i
++)
27100 group_insns
[i
] = 0;
27104 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
27105 PUT_MODE (next_insn
, VOIDmode
);
27106 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
27107 PUT_MODE (next_insn
, TImode
);
27110 if (can_issue_more
== 0)
27111 can_issue_more
= issue_rate
;
27114 return group_count
;
27117 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
27118 dispatch group boundaries that the scheduler had marked. Pad with nops
27119 any dispatch groups which have vacant issue slots, in order to force the
27120 scheduler's grouping on the processor dispatcher. The function
27121 returns the number of dispatch groups found. */
27124 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27126 rtx insn
, next_insn
;
27129 int can_issue_more
;
27131 int group_count
= 0;
27133 /* Initialize issue_rate. */
27134 issue_rate
= rs6000_issue_rate ();
27135 can_issue_more
= issue_rate
;
27137 insn
= get_next_active_insn (prev_head_insn
, tail
);
27138 next_insn
= get_next_active_insn (insn
, tail
);
27140 while (insn
!= NULL_RTX
)
27143 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27145 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
27147 if (next_insn
== NULL_RTX
)
27152 /* If the scheduler had marked group termination at this location
27153 (between insn and next_insn), and neither insn nor next_insn will
27154 force group termination, pad the group with nops to force group
27157 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27158 && !insn_terminates_group_p (insn
, current_group
)
27159 && !insn_terminates_group_p (next_insn
, previous_group
))
27161 if (!is_branch_slot_insn (next_insn
))
27164 while (can_issue_more
)
27167 emit_insn_before (nop
, next_insn
);
27172 can_issue_more
= issue_rate
;
27177 next_insn
= get_next_active_insn (insn
, tail
);
27180 return group_count
;
27183 /* We're beginning a new block. Initialize data structures as necessary. */
27186 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
27187 int sched_verbose ATTRIBUTE_UNUSED
,
27188 int max_ready ATTRIBUTE_UNUSED
)
27190 last_scheduled_insn
= NULL_RTX
;
27191 load_store_pendulum
= 0;
27194 /* The following function is called at the end of scheduling BB.
27195 After reload, it inserts nops at insn group bundling. */
27198 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
27203 fprintf (dump
, "=== Finishing schedule.\n");
27205 if (reload_completed
&& rs6000_sched_groups
)
27207 /* Do not run sched_finish hook when selective scheduling enabled. */
27208 if (sel_sched_p ())
27211 if (rs6000_sched_insert_nops
== sched_finish_none
)
27214 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27215 n_groups
= pad_groups (dump
, sched_verbose
,
27216 current_sched_info
->prev_head
,
27217 current_sched_info
->next_tail
);
27219 n_groups
= redefine_groups (dump
, sched_verbose
,
27220 current_sched_info
->prev_head
,
27221 current_sched_info
->next_tail
);
27223 if (sched_verbose
>= 6)
27225 fprintf (dump
, "ngroups = %d\n", n_groups
);
27226 print_rtl (dump
, current_sched_info
->prev_head
);
27227 fprintf (dump
, "Done finish_sched\n");
27232 struct _rs6000_sched_context
27234 short cached_can_issue_more
;
27235 rtx last_scheduled_insn
;
27236 int load_store_pendulum
;
27239 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
27240 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
27242 /* Allocate store for new scheduling context. */
27244 rs6000_alloc_sched_context (void)
27246 return xmalloc (sizeof (rs6000_sched_context_def
));
27249 /* If CLEAN_P is true then initializes _SC with clean data,
27250 and from the global context otherwise. */
27252 rs6000_init_sched_context (void *_sc
, bool clean_p
)
27254 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27258 sc
->cached_can_issue_more
= 0;
27259 sc
->last_scheduled_insn
= NULL_RTX
;
27260 sc
->load_store_pendulum
= 0;
27264 sc
->cached_can_issue_more
= cached_can_issue_more
;
27265 sc
->last_scheduled_insn
= last_scheduled_insn
;
27266 sc
->load_store_pendulum
= load_store_pendulum
;
27270 /* Sets the global scheduling context to the one pointed to by _SC. */
27272 rs6000_set_sched_context (void *_sc
)
27274 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27276 gcc_assert (sc
!= NULL
);
27278 cached_can_issue_more
= sc
->cached_can_issue_more
;
27279 last_scheduled_insn
= sc
->last_scheduled_insn
;
27280 load_store_pendulum
= sc
->load_store_pendulum
;
27285 rs6000_free_sched_context (void *_sc
)
27287 gcc_assert (_sc
!= NULL
);
27293 /* Length in units of the trampoline for entering a nested function. */
27296 rs6000_trampoline_size (void)
27300 switch (DEFAULT_ABI
)
27303 gcc_unreachable ();
27306 ret
= (TARGET_32BIT
) ? 12 : 24;
27310 gcc_assert (!TARGET_32BIT
);
27316 ret
= (TARGET_32BIT
) ? 40 : 48;
27323 /* Emit RTL insns to initialize the variable parts of a trampoline.
27324 FNADDR is an RTX for the address of the function's pure code.
27325 CXT is an RTX for the static chain value for the function. */
27328 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
27330 int regsize
= (TARGET_32BIT
) ? 4 : 8;
27331 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
27332 rtx ctx_reg
= force_reg (Pmode
, cxt
);
27333 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
27335 switch (DEFAULT_ABI
)
27338 gcc_unreachable ();
27340 /* Under AIX, just build the 3 word function descriptor */
27343 rtx fnmem
, fn_reg
, toc_reg
;
27345 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
27346 error ("You cannot take the address of a nested function if you use "
27347 "the -mno-pointers-to-nested-functions option.");
27349 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
27350 fn_reg
= gen_reg_rtx (Pmode
);
27351 toc_reg
= gen_reg_rtx (Pmode
);
27353 /* Macro to shorten the code expansions below. */
27354 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
27356 m_tramp
= replace_equiv_address (m_tramp
, addr
);
27358 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
27359 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
27360 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
27361 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
27362 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
27368 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
27372 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
27373 LCT_NORMAL
, VOIDmode
, 4,
27375 GEN_INT (rs6000_trampoline_size ()), SImode
,
27383 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
27384 identifier as an argument, so the front end shouldn't look it up. */
27387 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
27389 return is_attribute_p ("altivec", attr_id
);
27392 /* Handle the "altivec" attribute. The attribute may have
27393 arguments as follows:
27395 __attribute__((altivec(vector__)))
27396 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
27397 __attribute__((altivec(bool__))) (always followed by 'unsigned')
27399 and may appear more than once (e.g., 'vector bool char') in a
27400 given declaration. */
27403 rs6000_handle_altivec_attribute (tree
*node
,
27404 tree name ATTRIBUTE_UNUSED
,
27406 int flags ATTRIBUTE_UNUSED
,
27407 bool *no_add_attrs
)
27409 tree type
= *node
, result
= NULL_TREE
;
27410 enum machine_mode mode
;
27413 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
27414 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
27415 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
27418 while (POINTER_TYPE_P (type
)
27419 || TREE_CODE (type
) == FUNCTION_TYPE
27420 || TREE_CODE (type
) == METHOD_TYPE
27421 || TREE_CODE (type
) == ARRAY_TYPE
)
27422 type
= TREE_TYPE (type
);
27424 mode
= TYPE_MODE (type
);
27426 /* Check for invalid AltiVec type qualifiers. */
27427 if (type
== long_double_type_node
)
27428 error ("use of %<long double%> in AltiVec types is invalid");
27429 else if (type
== boolean_type_node
)
27430 error ("use of boolean types in AltiVec types is invalid");
27431 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
27432 error ("use of %<complex%> in AltiVec types is invalid");
27433 else if (DECIMAL_FLOAT_MODE_P (mode
))
27434 error ("use of decimal floating point types in AltiVec types is invalid");
27435 else if (!TARGET_VSX
)
27437 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
27440 error ("use of %<long%> in AltiVec types is invalid for "
27441 "64-bit code without -mvsx");
27442 else if (rs6000_warn_altivec_long
)
27443 warning (0, "use of %<long%> in AltiVec types is deprecated; "
27446 else if (type
== long_long_unsigned_type_node
27447 || type
== long_long_integer_type_node
)
27448 error ("use of %<long long%> in AltiVec types is invalid without "
27450 else if (type
== double_type_node
)
27451 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
27454 switch (altivec_type
)
27457 unsigned_p
= TYPE_UNSIGNED (type
);
27461 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
27464 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
27467 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
27470 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
27472 case SFmode
: result
= V4SF_type_node
; break;
27473 case DFmode
: result
= V2DF_type_node
; break;
27474 /* If the user says 'vector int bool', we may be handed the 'bool'
27475 attribute _before_ the 'vector' attribute, and so select the
27476 proper type in the 'b' case below. */
27477 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
27478 case V2DImode
: case V2DFmode
:
27486 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
27487 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
27488 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
27489 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
27496 case V8HImode
: result
= pixel_V8HI_type_node
;
27502 /* Propagate qualifiers attached to the element type
27503 onto the vector type. */
27504 if (result
&& result
!= type
&& TYPE_QUALS (type
))
27505 result
= build_qualified_type (result
, TYPE_QUALS (type
));
27507 *no_add_attrs
= true; /* No need to hang on to the attribute. */
27510 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
27515 /* AltiVec defines four built-in scalar types that serve as vector
27516 elements; we must teach the compiler how to mangle them. */
27518 static const char *
27519 rs6000_mangle_type (const_tree type
)
27521 type
= TYPE_MAIN_VARIANT (type
);
27523 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
27524 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
27527 if (type
== bool_char_type_node
) return "U6__boolc";
27528 if (type
== bool_short_type_node
) return "U6__bools";
27529 if (type
== pixel_type_node
) return "u7__pixel";
27530 if (type
== bool_int_type_node
) return "U6__booli";
27531 if (type
== bool_long_type_node
) return "U6__booll";
27533 /* Mangle IBM extended float long double as `g' (__float128) on
27534 powerpc*-linux where long-double-64 previously was the default. */
27535 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
27537 && TARGET_LONG_DOUBLE_128
27538 && !TARGET_IEEEQUAD
)
27541 /* For all other types, use normal C++ mangling. */
27545 /* Handle a "longcall" or "shortcall" attribute; arguments as in
27546 struct attribute_spec.handler. */
27549 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
27550 tree args ATTRIBUTE_UNUSED
,
27551 int flags ATTRIBUTE_UNUSED
,
27552 bool *no_add_attrs
)
27554 if (TREE_CODE (*node
) != FUNCTION_TYPE
27555 && TREE_CODE (*node
) != FIELD_DECL
27556 && TREE_CODE (*node
) != TYPE_DECL
)
27558 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
27560 *no_add_attrs
= true;
27566 /* Set longcall attributes on all functions declared when
27567 rs6000_default_long_calls is true. */
27569 rs6000_set_default_type_attributes (tree type
)
27571 if (rs6000_default_long_calls
27572 && (TREE_CODE (type
) == FUNCTION_TYPE
27573 || TREE_CODE (type
) == METHOD_TYPE
))
27574 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
27576 TYPE_ATTRIBUTES (type
));
27579 darwin_set_default_type_attributes (type
);
27583 /* Return a reference suitable for calling a function with the
27584 longcall attribute. */
27587 rs6000_longcall_ref (rtx call_ref
)
27589 const char *call_name
;
27592 if (GET_CODE (call_ref
) != SYMBOL_REF
)
27595 /* System V adds '.' to the internal name, so skip them. */
27596 call_name
= XSTR (call_ref
, 0);
27597 if (*call_name
== '.')
27599 while (*call_name
== '.')
27602 node
= get_identifier (call_name
);
27603 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
27606 return force_reg (Pmode
, call_ref
);
27609 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
27610 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
27613 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27614 struct attribute_spec.handler. */
27616 rs6000_handle_struct_attribute (tree
*node
, tree name
,
27617 tree args ATTRIBUTE_UNUSED
,
27618 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
27621 if (DECL_P (*node
))
27623 if (TREE_CODE (*node
) == TYPE_DECL
)
27624 type
= &TREE_TYPE (*node
);
27629 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
27630 || TREE_CODE (*type
) == UNION_TYPE
)))
27632 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
27633 *no_add_attrs
= true;
27636 else if ((is_attribute_p ("ms_struct", name
)
27637 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
27638 || ((is_attribute_p ("gcc_struct", name
)
27639 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
27641 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
27643 *no_add_attrs
= true;
27650 rs6000_ms_bitfield_layout_p (const_tree record_type
)
27652 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
27653 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
27654 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
27657 #ifdef USING_ELFOS_H
27659 /* A get_unnamed_section callback, used for switching to toc_section. */
27662 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
27664 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27665 && TARGET_MINIMAL_TOC
27666 && !TARGET_RELOCATABLE
)
27668 if (!toc_initialized
)
27670 toc_initialized
= 1;
27671 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
27672 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
27673 fprintf (asm_out_file
, "\t.tc ");
27674 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
27675 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27676 fprintf (asm_out_file
, "\n");
27678 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27679 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27680 fprintf (asm_out_file
, " = .+32768\n");
27683 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27685 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27686 && !TARGET_RELOCATABLE
)
27687 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
27690 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27691 if (!toc_initialized
)
27693 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27694 fprintf (asm_out_file
, " = .+32768\n");
27695 toc_initialized
= 1;
27700 /* Implement TARGET_ASM_INIT_SECTIONS. */
27703 rs6000_elf_asm_init_sections (void)
27706 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
27709 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
27710 SDATA2_SECTION_ASM_OP
);
27713 /* Implement TARGET_SELECT_RTX_SECTION. */
27716 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
27717 unsigned HOST_WIDE_INT align
)
27719 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
27720 return toc_section
;
27722 return default_elf_select_rtx_section (mode
, x
, align
);
27725 /* For a SYMBOL_REF, set generic flags and then perform some
27726 target-specific processing.
27728 When the AIX ABI is requested on a non-AIX system, replace the
27729 function name with the real name (with a leading .) rather than the
27730 function descriptor name. This saves a lot of overriding code to
27731 read the prefixes. */
27733 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
27735 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
27737 default_encode_section_info (decl
, rtl
, first
);
27740 && TREE_CODE (decl
) == FUNCTION_DECL
27742 && DEFAULT_ABI
== ABI_AIX
)
27744 rtx sym_ref
= XEXP (rtl
, 0);
27745 size_t len
= strlen (XSTR (sym_ref
, 0));
27746 char *str
= XALLOCAVEC (char, len
+ 2);
27748 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
27749 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
27754 compare_section_name (const char *section
, const char *templ
)
27758 len
= strlen (templ
);
27759 return (strncmp (section
, templ
, len
) == 0
27760 && (section
[len
] == 0 || section
[len
] == '.'));
27764 rs6000_elf_in_small_data_p (const_tree decl
)
27766 if (rs6000_sdata
== SDATA_NONE
)
27769 /* We want to merge strings, so we never consider them small data. */
27770 if (TREE_CODE (decl
) == STRING_CST
)
27773 /* Functions are never in the small data area. */
27774 if (TREE_CODE (decl
) == FUNCTION_DECL
)
27777 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
27779 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
27780 if (compare_section_name (section
, ".sdata")
27781 || compare_section_name (section
, ".sdata2")
27782 || compare_section_name (section
, ".gnu.linkonce.s")
27783 || compare_section_name (section
, ".sbss")
27784 || compare_section_name (section
, ".sbss2")
27785 || compare_section_name (section
, ".gnu.linkonce.sb")
27786 || strcmp (section
, ".PPC.EMB.sdata0") == 0
27787 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
27792 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
27795 && size
<= g_switch_value
27796 /* If it's not public, and we're not going to reference it there,
27797 there's no need to put it in the small data section. */
27798 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
27805 #endif /* USING_ELFOS_H */
27807 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
27810 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
27812 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
27815 /* Do not place thread-local symbols refs in the object blocks. */
27818 rs6000_use_blocks_for_decl_p (const_tree decl
)
27820 return !DECL_THREAD_LOCAL_P (decl
);
27823 /* Return a REG that occurs in ADDR with coefficient 1.
27824 ADDR can be effectively incremented by incrementing REG.
27826 r0 is special and we must not select it as an address
27827 register by this routine since our caller will try to
27828 increment the returned register via an "la" instruction. */
27831 find_addr_reg (rtx addr
)
27833 while (GET_CODE (addr
) == PLUS
)
27835 if (GET_CODE (XEXP (addr
, 0)) == REG
27836 && REGNO (XEXP (addr
, 0)) != 0)
27837 addr
= XEXP (addr
, 0);
27838 else if (GET_CODE (XEXP (addr
, 1)) == REG
27839 && REGNO (XEXP (addr
, 1)) != 0)
27840 addr
= XEXP (addr
, 1);
27841 else if (CONSTANT_P (XEXP (addr
, 0)))
27842 addr
= XEXP (addr
, 1);
27843 else if (CONSTANT_P (XEXP (addr
, 1)))
27844 addr
= XEXP (addr
, 0);
27846 gcc_unreachable ();
27848 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
27853 rs6000_fatal_bad_address (rtx op
)
27855 fatal_insn ("bad address", op
);
27860 typedef struct branch_island_d
{
27861 tree function_name
;
27867 static vec
<branch_island
, va_gc
> *branch_islands
;
27869 /* Remember to generate a branch island for far calls to the given
27873 add_compiler_branch_island (tree label_name
, tree function_name
,
27876 branch_island bi
= {function_name
, label_name
, line_number
};
27877 vec_safe_push (branch_islands
, bi
);
27880 /* Generate far-jump branch islands for everything recorded in
27881 branch_islands. Invoked immediately after the last instruction of
27882 the epilogue has been emitted; the branch islands must be appended
27883 to, and contiguous with, the function body. Mach-O stubs are
27884 generated in machopic_output_stub(). */
27887 macho_branch_islands (void)
27891 while (!vec_safe_is_empty (branch_islands
))
27893 branch_island
*bi
= &branch_islands
->last ();
27894 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
27895 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
27896 char name_buf
[512];
27897 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
27898 if (name
[0] == '*' || name
[0] == '&')
27899 strcpy (name_buf
, name
+1);
27903 strcpy (name_buf
+1, name
);
27905 strcpy (tmp_buf
, "\n");
27906 strcat (tmp_buf
, label
);
27907 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
27908 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
27909 dbxout_stabd (N_SLINE
, bi
->line_number
);
27910 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
27913 if (TARGET_LINK_STACK
)
27916 get_ppc476_thunk_name (name
);
27917 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
27918 strcat (tmp_buf
, name
);
27919 strcat (tmp_buf
, "\n");
27920 strcat (tmp_buf
, label
);
27921 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27925 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
27926 strcat (tmp_buf
, label
);
27927 strcat (tmp_buf
, "_pic\n");
27928 strcat (tmp_buf
, label
);
27929 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27932 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
27933 strcat (tmp_buf
, name_buf
);
27934 strcat (tmp_buf
, " - ");
27935 strcat (tmp_buf
, label
);
27936 strcat (tmp_buf
, "_pic)\n");
27938 strcat (tmp_buf
, "\tmtlr r0\n");
27940 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
27941 strcat (tmp_buf
, name_buf
);
27942 strcat (tmp_buf
, " - ");
27943 strcat (tmp_buf
, label
);
27944 strcat (tmp_buf
, "_pic)\n");
27946 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
27950 strcat (tmp_buf
, ":\nlis r12,hi16(");
27951 strcat (tmp_buf
, name_buf
);
27952 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
27953 strcat (tmp_buf
, name_buf
);
27954 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
27956 output_asm_insn (tmp_buf
, 0);
27957 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
27958 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
27959 dbxout_stabd (N_SLINE
, bi
->line_number
);
27960 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
27961 branch_islands
->pop ();
27965 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
27966 already there or not. */
27969 no_previous_def (tree function_name
)
27974 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
27975 if (function_name
== bi
->function_name
)
27980 /* GET_PREV_LABEL gets the label name from the previous definition of
27984 get_prev_label (tree function_name
)
27989 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
27990 if (function_name
== bi
->function_name
)
27991 return bi
->label_name
;
27995 /* INSN is either a function call or a millicode call. It may have an
27996 unconditional jump in its delay slot.
27998 CALL_DEST is the routine we are calling. */
28001 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
28002 int cookie_operand_number
)
28004 static char buf
[256];
28005 if (darwin_emit_branch_islands
28006 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
28007 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
28010 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
28012 if (no_previous_def (funname
))
28014 rtx label_rtx
= gen_label_rtx ();
28015 char *label_buf
, temp_buf
[256];
28016 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
28017 CODE_LABEL_NUMBER (label_rtx
));
28018 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
28019 labelname
= get_identifier (label_buf
);
28020 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
28023 labelname
= get_prev_label (funname
);
28025 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
28026 instruction will reach 'foo', otherwise link as 'bl L42'".
28027 "L42" should be a 'branch island', that will do a far jump to
28028 'foo'. Branch islands are generated in
28029 macho_branch_islands(). */
28030 sprintf (buf
, "jbsr %%z%d,%.246s",
28031 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
28034 sprintf (buf
, "bl %%z%d", dest_operand_number
);
28038 /* Generate PIC and indirect symbol stubs. */
28041 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
28043 unsigned int length
;
28044 char *symbol_name
, *lazy_ptr_name
;
28045 char *local_label_0
;
28046 static int label
= 0;
28048 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
28049 symb
= (*targetm
.strip_name_encoding
) (symb
);
28052 length
= strlen (symb
);
28053 symbol_name
= XALLOCAVEC (char, length
+ 32);
28054 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
28056 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
28057 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
28060 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
28062 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
28066 fprintf (file
, "\t.align 5\n");
28068 fprintf (file
, "%s:\n", stub
);
28069 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28072 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
28073 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
28075 fprintf (file
, "\tmflr r0\n");
28076 if (TARGET_LINK_STACK
)
28079 get_ppc476_thunk_name (name
);
28080 fprintf (file
, "\tbl %s\n", name
);
28081 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28085 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
28086 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28088 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
28089 lazy_ptr_name
, local_label_0
);
28090 fprintf (file
, "\tmtlr r0\n");
28091 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
28092 (TARGET_64BIT
? "ldu" : "lwzu"),
28093 lazy_ptr_name
, local_label_0
);
28094 fprintf (file
, "\tmtctr r12\n");
28095 fprintf (file
, "\tbctr\n");
28099 fprintf (file
, "\t.align 4\n");
28101 fprintf (file
, "%s:\n", stub
);
28102 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28104 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
28105 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
28106 (TARGET_64BIT
? "ldu" : "lwzu"),
28108 fprintf (file
, "\tmtctr r12\n");
28109 fprintf (file
, "\tbctr\n");
28112 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
28113 fprintf (file
, "%s:\n", lazy_ptr_name
);
28114 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28115 fprintf (file
, "%sdyld_stub_binding_helper\n",
28116 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
28119 /* Legitimize PIC addresses. If the address is already
28120 position-independent, we return ORIG. Newly generated
28121 position-independent addresses go into a reg. This is REG if non
28122 zero, otherwise we allocate register(s) as necessary. */
28124 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
28127 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
28132 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
28133 reg
= gen_reg_rtx (Pmode
);
28135 if (GET_CODE (orig
) == CONST
)
28139 if (GET_CODE (XEXP (orig
, 0)) == PLUS
28140 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
28143 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
28145 /* Use a different reg for the intermediate value, as
28146 it will be marked UNCHANGING. */
28147 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
28148 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
28151 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
28154 if (GET_CODE (offset
) == CONST_INT
)
28156 if (SMALL_INT (offset
))
28157 return plus_constant (Pmode
, base
, INTVAL (offset
));
28158 else if (! reload_in_progress
&& ! reload_completed
)
28159 offset
= force_reg (Pmode
, offset
);
28162 rtx mem
= force_const_mem (Pmode
, orig
);
28163 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
28166 return gen_rtx_PLUS (Pmode
, base
, offset
);
28169 /* Fall back on generic machopic code. */
28170 return machopic_legitimize_pic_address (orig
, mode
, reg
);
28173 /* Output a .machine directive for the Darwin assembler, and call
28174 the generic start_file routine. */
28177 rs6000_darwin_file_start (void)
28179 static const struct
28183 HOST_WIDE_INT if_set
;
28185 { "ppc64", "ppc64", MASK_64BIT
},
28186 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
28187 { "power4", "ppc970", 0 },
28188 { "G5", "ppc970", 0 },
28189 { "7450", "ppc7450", 0 },
28190 { "7400", "ppc7400", MASK_ALTIVEC
},
28191 { "G4", "ppc7400", 0 },
28192 { "750", "ppc750", 0 },
28193 { "740", "ppc750", 0 },
28194 { "G3", "ppc750", 0 },
28195 { "604e", "ppc604e", 0 },
28196 { "604", "ppc604", 0 },
28197 { "603e", "ppc603", 0 },
28198 { "603", "ppc603", 0 },
28199 { "601", "ppc601", 0 },
28200 { NULL
, "ppc", 0 } };
28201 const char *cpu_id
= "";
28204 rs6000_file_start ();
28205 darwin_file_start ();
28207 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
28209 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
28210 cpu_id
= rs6000_default_cpu
;
28212 if (global_options_set
.x_rs6000_cpu_index
)
28213 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
28215 /* Look through the mapping array. Pick the first name that either
28216 matches the argument, has a bit set in IF_SET that is also set
28217 in the target flags, or has a NULL name. */
28220 while (mapping
[i
].arg
!= NULL
28221 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
28222 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
28225 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
28228 #endif /* TARGET_MACHO */
28232 rs6000_elf_reloc_rw_mask (void)
28236 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28242 /* Record an element in the table of global constructors. SYMBOL is
28243 a SYMBOL_REF of the function to be called; PRIORITY is a number
28244 between 0 and MAX_INIT_PRIORITY.
28246 This differs from default_named_section_asm_out_constructor in
28247 that we have special handling for -mrelocatable. */
28249 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
28251 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
28253 const char *section
= ".ctors";
28256 if (priority
!= DEFAULT_INIT_PRIORITY
)
28258 sprintf (buf
, ".ctors.%.5u",
28259 /* Invert the numbering so the linker puts us in the proper
28260 order; constructors are run from right to left, and the
28261 linker sorts in increasing order. */
28262 MAX_INIT_PRIORITY
- priority
);
28266 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28267 assemble_align (POINTER_SIZE
);
28269 if (TARGET_RELOCATABLE
)
28271 fputs ("\t.long (", asm_out_file
);
28272 output_addr_const (asm_out_file
, symbol
);
28273 fputs (")@fixup\n", asm_out_file
);
28276 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28279 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
28281 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
28283 const char *section
= ".dtors";
28286 if (priority
!= DEFAULT_INIT_PRIORITY
)
28288 sprintf (buf
, ".dtors.%.5u",
28289 /* Invert the numbering so the linker puts us in the proper
28290 order; constructors are run from right to left, and the
28291 linker sorts in increasing order. */
28292 MAX_INIT_PRIORITY
- priority
);
28296 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28297 assemble_align (POINTER_SIZE
);
28299 if (TARGET_RELOCATABLE
)
28301 fputs ("\t.long (", asm_out_file
);
28302 output_addr_const (asm_out_file
, symbol
);
28303 fputs (")@fixup\n", asm_out_file
);
28306 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28310 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
28312 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
28314 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
28315 ASM_OUTPUT_LABEL (file
, name
);
28316 fputs (DOUBLE_INT_ASM_OP
, file
);
28317 rs6000_output_function_entry (file
, name
);
28318 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
28321 fputs ("\t.size\t", file
);
28322 assemble_name (file
, name
);
28323 fputs (",24\n\t.type\t.", file
);
28324 assemble_name (file
, name
);
28325 fputs (",@function\n", file
);
28326 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
28328 fputs ("\t.globl\t.", file
);
28329 assemble_name (file
, name
);
28334 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28335 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28336 rs6000_output_function_entry (file
, name
);
28337 fputs (":\n", file
);
28341 if (TARGET_RELOCATABLE
28342 && !TARGET_SECURE_PLT
28343 && (get_pool_size () != 0 || crtl
->profile
)
28348 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
28350 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
28351 fprintf (file
, "\t.long ");
28352 assemble_name (file
, buf
);
28354 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
28355 assemble_name (file
, buf
);
28359 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28360 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28362 if (DEFAULT_ABI
== ABI_AIX
)
28364 const char *desc_name
, *orig_name
;
28366 orig_name
= (*targetm
.strip_name_encoding
) (name
);
28367 desc_name
= orig_name
;
28368 while (*desc_name
== '.')
28371 if (TREE_PUBLIC (decl
))
28372 fprintf (file
, "\t.globl %s\n", desc_name
);
28374 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28375 fprintf (file
, "%s:\n", desc_name
);
28376 fprintf (file
, "\t.long %s\n", orig_name
);
28377 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
28378 fputs ("\t.long 0\n", file
);
28379 fprintf (file
, "\t.previous\n");
28381 ASM_OUTPUT_LABEL (file
, name
);
28384 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
28386 rs6000_elf_file_end (void)
28388 #ifdef HAVE_AS_GNU_ATTRIBUTE
28389 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
28391 if (rs6000_passes_float
)
28392 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
28393 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
28394 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
28396 if (rs6000_passes_vector
)
28397 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
28398 (TARGET_ALTIVEC_ABI
? 2
28399 : TARGET_SPE_ABI
? 3
28401 if (rs6000_returns_struct
)
28402 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
28403 aix_struct_return
? 2 : 1);
28406 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
28407 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
28408 file_end_indicate_exec_stack ();
28415 rs6000_xcoff_asm_output_anchor (rtx symbol
)
28419 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
28420 SYMBOL_REF_BLOCK_OFFSET (symbol
));
28421 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
28425 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
28427 fputs (GLOBAL_ASM_OP
, stream
);
28428 RS6000_OUTPUT_BASENAME (stream
, name
);
28429 putc ('\n', stream
);
28432 /* A get_unnamed_decl callback, used for read-only sections. PTR
28433 points to the section string variable. */
28436 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
28438 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
28439 *(const char *const *) directive
,
28440 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28443 /* Likewise for read-write sections. */
28446 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
28448 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
28449 *(const char *const *) directive
,
28450 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28454 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
28456 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
28457 *(const char *const *) directive
,
28458 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28461 /* A get_unnamed_section callback, used for switching to toc_section. */
28464 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
28466 if (TARGET_MINIMAL_TOC
)
28468 /* toc_section is always selected at least once from
28469 rs6000_xcoff_file_start, so this is guaranteed to
28470 always be defined once and only once in each file. */
28471 if (!toc_initialized
)
28473 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
28474 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
28475 toc_initialized
= 1;
28477 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
28478 (TARGET_32BIT
? "" : ",3"));
28481 fputs ("\t.toc\n", asm_out_file
);
28484 /* Implement TARGET_ASM_INIT_SECTIONS. */
28487 rs6000_xcoff_asm_init_sections (void)
28489 read_only_data_section
28490 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
28491 &xcoff_read_only_section_name
);
28493 private_data_section
28494 = get_unnamed_section (SECTION_WRITE
,
28495 rs6000_xcoff_output_readwrite_section_asm_op
,
28496 &xcoff_private_data_section_name
);
28499 = get_unnamed_section (SECTION_TLS
,
28500 rs6000_xcoff_output_tls_section_asm_op
,
28501 &xcoff_tls_data_section_name
);
28503 tls_private_data_section
28504 = get_unnamed_section (SECTION_TLS
,
28505 rs6000_xcoff_output_tls_section_asm_op
,
28506 &xcoff_private_data_section_name
);
28508 read_only_private_data_section
28509 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
28510 &xcoff_private_data_section_name
);
28513 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
28515 readonly_data_section
= read_only_data_section
;
28516 exception_section
= data_section
;
28520 rs6000_xcoff_reloc_rw_mask (void)
28526 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
28527 tree decl ATTRIBUTE_UNUSED
)
28530 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
28532 if (flags
& SECTION_CODE
)
28534 else if (flags
& SECTION_TLS
)
28536 else if (flags
& SECTION_WRITE
)
28541 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
28542 (flags
& SECTION_CODE
) ? "." : "",
28543 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
28547 rs6000_xcoff_select_section (tree decl
, int reloc
,
28548 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
28550 if (decl_readonly_section (decl
, reloc
))
28552 if (TREE_PUBLIC (decl
))
28553 return read_only_data_section
;
28555 return read_only_private_data_section
;
28560 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
28562 if (TREE_PUBLIC (decl
))
28563 return tls_data_section
;
28564 else if (bss_initializer_p (decl
))
28566 /* Convert to COMMON to emit in BSS. */
28567 DECL_COMMON (decl
) = 1;
28568 return tls_comm_section
;
28571 return tls_private_data_section
;
28575 if (TREE_PUBLIC (decl
))
28576 return data_section
;
28578 return private_data_section
;
28583 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
28587 /* Use select_section for private and uninitialized data. */
28588 if (!TREE_PUBLIC (decl
)
28589 || DECL_COMMON (decl
)
28590 || DECL_INITIAL (decl
) == NULL_TREE
28591 || DECL_INITIAL (decl
) == error_mark_node
28592 || (flag_zero_initialized_in_bss
28593 && initializer_zerop (DECL_INITIAL (decl
))))
28596 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
28597 name
= (*targetm
.strip_name_encoding
) (name
);
28598 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
28601 /* Select section for constant in constant pool.
28603 On RS/6000, all constants are in the private read-only data area.
28604 However, if this is being placed in the TOC it must be output as a
28608 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
28609 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
28611 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
28612 return toc_section
;
28614 return read_only_private_data_section
;
28617 /* Remove any trailing [DS] or the like from the symbol name. */
28619 static const char *
28620 rs6000_xcoff_strip_name_encoding (const char *name
)
28625 len
= strlen (name
);
28626 if (name
[len
- 1] == ']')
28627 return ggc_alloc_string (name
, len
- 4);
28632 /* Section attributes. AIX is always PIC. */
28634 static unsigned int
28635 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
28637 unsigned int align
;
28638 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
28640 /* Align to at least UNIT size. */
28641 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
28642 align
= MIN_UNITS_PER_WORD
;
28644 /* Increase alignment of large objects if not already stricter. */
28645 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
28646 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
28647 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
28649 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
28652 /* Output at beginning of assembler file.
28654 Initialize the section names for the RS/6000 at this point.
28656 Specify filename, including full path, to assembler.
28658 We want to go into the TOC section so at least one .toc will be emitted.
28659 Also, in order to output proper .bs/.es pairs, we need at least one static
28660 [RW] section emitted.
28662 Finally, declare mcount when profiling to make the assembler happy. */
28665 rs6000_xcoff_file_start (void)
28667 rs6000_gen_section_name (&xcoff_bss_section_name
,
28668 main_input_filename
, ".bss_");
28669 rs6000_gen_section_name (&xcoff_private_data_section_name
,
28670 main_input_filename
, ".rw_");
28671 rs6000_gen_section_name (&xcoff_read_only_section_name
,
28672 main_input_filename
, ".ro_");
28673 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
28674 main_input_filename
, ".tls_");
28675 rs6000_gen_section_name (&xcoff_tbss_section_name
,
28676 main_input_filename
, ".tbss_[UL]");
28678 fputs ("\t.file\t", asm_out_file
);
28679 output_quoted_string (asm_out_file
, main_input_filename
);
28680 fputc ('\n', asm_out_file
);
28681 if (write_symbols
!= NO_DEBUG
)
28682 switch_to_section (private_data_section
);
28683 switch_to_section (text_section
);
28685 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
28686 rs6000_file_start ();
28689 /* Output at end of assembler file.
28690 On the RS/6000, referencing data should automatically pull in text. */
28693 rs6000_xcoff_file_end (void)
28695 switch_to_section (text_section
);
28696 fputs ("_section_.text:\n", asm_out_file
);
28697 switch_to_section (data_section
);
28698 fputs (TARGET_32BIT
28699 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
28705 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
28710 default_encode_section_info (decl
, rtl
, first
);
28712 /* Careful not to prod global register variables. */
28715 symbol
= XEXP (rtl
, 0);
28716 if (GET_CODE (symbol
) != SYMBOL_REF
)
28719 flags
= SYMBOL_REF_FLAGS (symbol
);
28721 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
28722 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
28724 SYMBOL_REF_FLAGS (symbol
) = flags
;
28726 #endif /* HAVE_AS_TLS */
28727 #endif /* TARGET_XCOFF */
28729 /* Compute a (partial) cost for rtx X. Return true if the complete
28730 cost has been computed, and false if subexpressions should be
28731 scanned. In either case, *TOTAL contains the cost result. */
28734 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
28735 int *total
, bool speed
)
28737 enum machine_mode mode
= GET_MODE (x
);
28741 /* On the RS/6000, if it is valid in the insn, it is free. */
28743 if (((outer_code
== SET
28744 || outer_code
== PLUS
28745 || outer_code
== MINUS
)
28746 && (satisfies_constraint_I (x
)
28747 || satisfies_constraint_L (x
)))
28748 || (outer_code
== AND
28749 && (satisfies_constraint_K (x
)
28751 ? satisfies_constraint_L (x
)
28752 : satisfies_constraint_J (x
))
28753 || mask_operand (x
, mode
)
28755 && mask64_operand (x
, DImode
))))
28756 || ((outer_code
== IOR
|| outer_code
== XOR
)
28757 && (satisfies_constraint_K (x
)
28759 ? satisfies_constraint_L (x
)
28760 : satisfies_constraint_J (x
))))
28761 || outer_code
== ASHIFT
28762 || outer_code
== ASHIFTRT
28763 || outer_code
== LSHIFTRT
28764 || outer_code
== ROTATE
28765 || outer_code
== ROTATERT
28766 || outer_code
== ZERO_EXTRACT
28767 || (outer_code
== MULT
28768 && satisfies_constraint_I (x
))
28769 || ((outer_code
== DIV
|| outer_code
== UDIV
28770 || outer_code
== MOD
|| outer_code
== UMOD
)
28771 && exact_log2 (INTVAL (x
)) >= 0)
28772 || (outer_code
== COMPARE
28773 && (satisfies_constraint_I (x
)
28774 || satisfies_constraint_K (x
)))
28775 || ((outer_code
== EQ
|| outer_code
== NE
)
28776 && (satisfies_constraint_I (x
)
28777 || satisfies_constraint_K (x
)
28779 ? satisfies_constraint_L (x
)
28780 : satisfies_constraint_J (x
))))
28781 || (outer_code
== GTU
28782 && satisfies_constraint_I (x
))
28783 || (outer_code
== LTU
28784 && satisfies_constraint_P (x
)))
28789 else if ((outer_code
== PLUS
28790 && reg_or_add_cint_operand (x
, VOIDmode
))
28791 || (outer_code
== MINUS
28792 && reg_or_sub_cint_operand (x
, VOIDmode
))
28793 || ((outer_code
== SET
28794 || outer_code
== IOR
28795 || outer_code
== XOR
)
28797 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
28799 *total
= COSTS_N_INSNS (1);
28809 /* When optimizing for size, MEM should be slightly more expensive
28810 than generating address, e.g., (plus (reg) (const)).
28811 L1 cache latency is about two instructions. */
28812 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
28821 if (FLOAT_MODE_P (mode
))
28822 *total
= rs6000_cost
->fp
;
28824 *total
= COSTS_N_INSNS (1);
28828 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28829 && satisfies_constraint_I (XEXP (x
, 1)))
28831 if (INTVAL (XEXP (x
, 1)) >= -256
28832 && INTVAL (XEXP (x
, 1)) <= 255)
28833 *total
= rs6000_cost
->mulsi_const9
;
28835 *total
= rs6000_cost
->mulsi_const
;
28837 else if (mode
== SFmode
)
28838 *total
= rs6000_cost
->fp
;
28839 else if (FLOAT_MODE_P (mode
))
28840 *total
= rs6000_cost
->dmul
;
28841 else if (mode
== DImode
)
28842 *total
= rs6000_cost
->muldi
;
28844 *total
= rs6000_cost
->mulsi
;
28848 if (mode
== SFmode
)
28849 *total
= rs6000_cost
->fp
;
28851 *total
= rs6000_cost
->dmul
;
28856 if (FLOAT_MODE_P (mode
))
28858 *total
= mode
== DFmode
? rs6000_cost
->ddiv
28859 : rs6000_cost
->sdiv
;
28866 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28867 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
28869 if (code
== DIV
|| code
== MOD
)
28871 *total
= COSTS_N_INSNS (2);
28874 *total
= COSTS_N_INSNS (1);
28878 if (GET_MODE (XEXP (x
, 1)) == DImode
)
28879 *total
= rs6000_cost
->divdi
;
28881 *total
= rs6000_cost
->divsi
;
28883 /* Add in shift and subtract for MOD. */
28884 if (code
== MOD
|| code
== UMOD
)
28885 *total
+= COSTS_N_INSNS (2);
28890 *total
= COSTS_N_INSNS (4);
28894 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
28898 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
28902 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
28914 *total
= COSTS_N_INSNS (1);
28922 /* Handle mul_highpart. */
28923 if (outer_code
== TRUNCATE
28924 && GET_CODE (XEXP (x
, 0)) == MULT
)
28926 if (mode
== DImode
)
28927 *total
= rs6000_cost
->muldi
;
28929 *total
= rs6000_cost
->mulsi
;
28932 else if (outer_code
== AND
)
28935 *total
= COSTS_N_INSNS (1);
28940 if (GET_CODE (XEXP (x
, 0)) == MEM
)
28943 *total
= COSTS_N_INSNS (1);
28949 if (!FLOAT_MODE_P (mode
))
28951 *total
= COSTS_N_INSNS (1);
28957 case UNSIGNED_FLOAT
:
28960 case FLOAT_TRUNCATE
:
28961 *total
= rs6000_cost
->fp
;
28965 if (mode
== DFmode
)
28968 *total
= rs6000_cost
->fp
;
28972 switch (XINT (x
, 1))
28975 *total
= rs6000_cost
->fp
;
28987 *total
= COSTS_N_INSNS (1);
28990 else if (FLOAT_MODE_P (mode
)
28991 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28993 *total
= rs6000_cost
->fp
;
29001 /* Carry bit requires mode == Pmode.
29002 NEG or PLUS already counted so only add one. */
29004 && (outer_code
== NEG
|| outer_code
== PLUS
))
29006 *total
= COSTS_N_INSNS (1);
29009 if (outer_code
== SET
)
29011 if (XEXP (x
, 1) == const0_rtx
)
29013 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29014 *total
= COSTS_N_INSNS (8);
29016 *total
= COSTS_N_INSNS (2);
29019 else if (mode
== Pmode
)
29021 *total
= COSTS_N_INSNS (3);
29030 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
29032 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29033 *total
= COSTS_N_INSNS (8);
29035 *total
= COSTS_N_INSNS (2);
29039 if (outer_code
== COMPARE
)
29053 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
29056 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
29059 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
29062 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
29063 "opno = %d, total = %d, speed = %s, x:\n",
29064 ret
? "complete" : "scan inner",
29065 GET_RTX_NAME (code
),
29066 GET_RTX_NAME (outer_code
),
29069 speed
? "true" : "false");
29076 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
29079 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
29080 addr_space_t as
, bool speed
)
29082 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
29084 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
29085 ret
, speed
? "true" : "false");
29092 /* A C expression returning the cost of moving data from a register of class
29093 CLASS1 to one of CLASS2. */
29096 rs6000_register_move_cost (enum machine_mode mode
,
29097 reg_class_t from
, reg_class_t to
)
29101 if (TARGET_DEBUG_COST
)
29104 /* Moves from/to GENERAL_REGS. */
29105 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
29106 || reg_classes_intersect_p (from
, GENERAL_REGS
))
29108 reg_class_t rclass
= from
;
29110 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
29113 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
29114 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
29115 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
29117 /* It's more expensive to move CR_REGS than CR0_REGS because of the
29119 else if (rclass
== CR_REGS
)
29122 /* For those processors that have slow LR/CTR moves, make them more
29123 expensive than memory in order to bias spills to memory .*/
29124 else if ((rs6000_cpu
== PROCESSOR_POWER6
29125 || rs6000_cpu
== PROCESSOR_POWER7
29126 || rs6000_cpu
== PROCESSOR_POWER8
)
29127 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
29128 ret
= 6 * hard_regno_nregs
[0][mode
];
29131 /* A move will cost one instruction per GPR moved. */
29132 ret
= 2 * hard_regno_nregs
[0][mode
];
29135 /* If we have VSX, we can easily move between FPR or Altivec registers. */
29136 else if (VECTOR_MEM_VSX_P (mode
)
29137 && reg_classes_intersect_p (to
, VSX_REGS
)
29138 && reg_classes_intersect_p (from
, VSX_REGS
))
29139 ret
= 2 * hard_regno_nregs
[32][mode
];
29141 /* Moving between two similar registers is just one instruction. */
29142 else if (reg_classes_intersect_p (to
, from
))
29143 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
29145 /* Everything else has to go through GENERAL_REGS. */
29147 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
29148 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
29150 if (TARGET_DEBUG_COST
)
29152 if (dbg_cost_ctrl
== 1)
29154 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
29155 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
29156 reg_class_names
[to
]);
29163 /* A C expressions returning the cost of moving data of MODE from a register to
29167 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
29168 bool in ATTRIBUTE_UNUSED
)
29172 if (TARGET_DEBUG_COST
)
29175 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
29176 ret
= 4 * hard_regno_nregs
[0][mode
];
29177 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
29178 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
29179 ret
= 4 * hard_regno_nregs
[32][mode
];
29180 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
29181 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
29183 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
29185 if (TARGET_DEBUG_COST
)
29187 if (dbg_cost_ctrl
== 1)
29189 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
29190 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
29197 /* Returns a code for a target-specific builtin that implements
29198 reciprocal of the function, or NULL_TREE if not available. */
29201 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
29202 bool sqrt ATTRIBUTE_UNUSED
)
29204 if (optimize_insn_for_size_p ())
29210 case VSX_BUILTIN_XVSQRTDP
:
29211 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
29214 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
29216 case VSX_BUILTIN_XVSQRTSP
:
29217 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
29220 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
29229 case BUILT_IN_SQRT
:
29230 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
29233 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
29235 case BUILT_IN_SQRTF
:
29236 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
29239 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
29246 /* Load up a constant. If the mode is a vector mode, splat the value across
29247 all of the vector elements. */
29250 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
29254 if (mode
== SFmode
|| mode
== DFmode
)
29256 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
29257 reg
= force_reg (mode
, d
);
29259 else if (mode
== V4SFmode
)
29261 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
29262 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
29263 reg
= gen_reg_rtx (mode
);
29264 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29266 else if (mode
== V2DFmode
)
29268 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
29269 rtvec v
= gen_rtvec (2, d
, d
);
29270 reg
= gen_reg_rtx (mode
);
29271 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29274 gcc_unreachable ();
29279 /* Generate an FMA instruction. */
29282 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
29284 enum machine_mode mode
= GET_MODE (target
);
29287 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29288 gcc_assert (dst
!= NULL
);
29291 emit_move_insn (target
, dst
);
29294 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
29297 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
29299 enum machine_mode mode
= GET_MODE (target
);
29302 /* Altivec does not support fms directly;
29303 generate in terms of fma in that case. */
29304 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
29305 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
29308 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
29309 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29311 gcc_assert (dst
!= NULL
);
29314 emit_move_insn (target
, dst
);
29317 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
29320 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
29322 enum machine_mode mode
= GET_MODE (dst
);
29325 /* This is a tad more complicated, since the fnma_optab is for
29326 a different expression: fma(-m1, m2, a), which is the same
29327 thing except in the case of signed zeros.
29329 Fortunately we know that if FMA is supported that FNMSUB is
29330 also supported in the ISA. Just expand it directly. */
29332 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
29334 r
= gen_rtx_NEG (mode
, a
);
29335 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
29336 r
= gen_rtx_NEG (mode
, r
);
29337 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
29340 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
29341 add a reg_note saying that this was a division. Support both scalar and
29342 vector divide. Assumes no trapping math and finite arguments. */
29345 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
29347 enum machine_mode mode
= GET_MODE (dst
);
29348 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
29351 /* Low precision estimates guarantee 5 bits of accuracy. High
29352 precision estimates guarantee 14 bits of accuracy. SFmode
29353 requires 23 bits of accuracy. DFmode requires 52 bits of
29354 accuracy. Each pass at least doubles the accuracy, leading
29355 to the following. */
29356 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29357 if (mode
== DFmode
|| mode
== V2DFmode
)
29360 enum insn_code code
= optab_handler (smul_optab
, mode
);
29361 insn_gen_fn gen_mul
= GEN_FCN (code
);
29363 gcc_assert (code
!= CODE_FOR_nothing
);
29365 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
29367 /* x0 = 1./d estimate */
29368 x0
= gen_reg_rtx (mode
);
29369 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
29370 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
29373 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
29376 /* e0 = 1. - d * x0 */
29377 e0
= gen_reg_rtx (mode
);
29378 rs6000_emit_nmsub (e0
, d
, x0
, one
);
29380 /* x1 = x0 + e0 * x0 */
29381 x1
= gen_reg_rtx (mode
);
29382 rs6000_emit_madd (x1
, e0
, x0
, x0
);
29384 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
29385 ++i
, xprev
= xnext
, eprev
= enext
) {
29387 /* enext = eprev * eprev */
29388 enext
= gen_reg_rtx (mode
);
29389 emit_insn (gen_mul (enext
, eprev
, eprev
));
29391 /* xnext = xprev + enext * xprev */
29392 xnext
= gen_reg_rtx (mode
);
29393 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
29399 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
29401 /* u = n * xprev */
29402 u
= gen_reg_rtx (mode
);
29403 emit_insn (gen_mul (u
, n
, xprev
));
29405 /* v = n - (d * u) */
29406 v
= gen_reg_rtx (mode
);
29407 rs6000_emit_nmsub (v
, d
, u
, n
);
29409 /* dst = (v * xprev) + u */
29410 rs6000_emit_madd (dst
, v
, xprev
, u
);
29413 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
29416 /* Newton-Raphson approximation of single/double-precision floating point
29417 rsqrt. Assumes no trapping math and finite arguments. */
29420 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
29422 enum machine_mode mode
= GET_MODE (src
);
29423 rtx x0
= gen_reg_rtx (mode
);
29424 rtx y
= gen_reg_rtx (mode
);
29426 /* Low precision estimates guarantee 5 bits of accuracy. High
29427 precision estimates guarantee 14 bits of accuracy. SFmode
29428 requires 23 bits of accuracy. DFmode requires 52 bits of
29429 accuracy. Each pass at least doubles the accuracy, leading
29430 to the following. */
29431 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29432 if (mode
== DFmode
|| mode
== V2DFmode
)
29435 REAL_VALUE_TYPE dconst3_2
;
29438 enum insn_code code
= optab_handler (smul_optab
, mode
);
29439 insn_gen_fn gen_mul
= GEN_FCN (code
);
29441 gcc_assert (code
!= CODE_FOR_nothing
);
29443 /* Load up the constant 1.5 either as a scalar, or as a vector. */
29444 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
29445 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
29447 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
29449 /* x0 = rsqrt estimate */
29450 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
29451 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
29454 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
29455 rs6000_emit_msub (y
, src
, halfthree
, src
);
29457 for (i
= 0; i
< passes
; i
++)
29459 rtx x1
= gen_reg_rtx (mode
);
29460 rtx u
= gen_reg_rtx (mode
);
29461 rtx v
= gen_reg_rtx (mode
);
29463 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
29464 emit_insn (gen_mul (u
, x0
, x0
));
29465 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
29466 emit_insn (gen_mul (x1
, x0
, v
));
29470 emit_move_insn (dst
, x0
);
29474 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
29475 (Power7) targets. DST is the target, and SRC is the argument operand. */
29478 rs6000_emit_popcount (rtx dst
, rtx src
)
29480 enum machine_mode mode
= GET_MODE (dst
);
29483 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
29484 if (TARGET_POPCNTD
)
29486 if (mode
== SImode
)
29487 emit_insn (gen_popcntdsi2 (dst
, src
));
29489 emit_insn (gen_popcntddi2 (dst
, src
));
29493 tmp1
= gen_reg_rtx (mode
);
29495 if (mode
== SImode
)
29497 emit_insn (gen_popcntbsi2 (tmp1
, src
));
29498 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
29500 tmp2
= force_reg (SImode
, tmp2
);
29501 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
29505 emit_insn (gen_popcntbdi2 (tmp1
, src
));
29506 tmp2
= expand_mult (DImode
, tmp1
,
29507 GEN_INT ((HOST_WIDE_INT
)
29508 0x01010101 << 32 | 0x01010101),
29510 tmp2
= force_reg (DImode
, tmp2
);
29511 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
29516 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
29517 target, and SRC is the argument operand. */
29520 rs6000_emit_parity (rtx dst
, rtx src
)
29522 enum machine_mode mode
= GET_MODE (dst
);
29525 tmp
= gen_reg_rtx (mode
);
29527 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
29530 if (mode
== SImode
)
29532 emit_insn (gen_popcntbsi2 (tmp
, src
));
29533 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
29537 emit_insn (gen_popcntbdi2 (tmp
, src
));
29538 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
29543 if (mode
== SImode
)
29545 /* Is mult+shift >= shift+xor+shift+xor? */
29546 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
29548 rtx tmp1
, tmp2
, tmp3
, tmp4
;
29550 tmp1
= gen_reg_rtx (SImode
);
29551 emit_insn (gen_popcntbsi2 (tmp1
, src
));
29553 tmp2
= gen_reg_rtx (SImode
);
29554 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
29555 tmp3
= gen_reg_rtx (SImode
);
29556 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
29558 tmp4
= gen_reg_rtx (SImode
);
29559 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
29560 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
29563 rs6000_emit_popcount (tmp
, src
);
29564 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
29568 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
29569 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
29571 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
29573 tmp1
= gen_reg_rtx (DImode
);
29574 emit_insn (gen_popcntbdi2 (tmp1
, src
));
29576 tmp2
= gen_reg_rtx (DImode
);
29577 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
29578 tmp3
= gen_reg_rtx (DImode
);
29579 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
29581 tmp4
= gen_reg_rtx (DImode
);
29582 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
29583 tmp5
= gen_reg_rtx (DImode
);
29584 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
29586 tmp6
= gen_reg_rtx (DImode
);
29587 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
29588 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
29591 rs6000_emit_popcount (tmp
, src
);
29592 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
29596 /* Expand an Altivec constant permutation for little endian mode.
29597 There are two issues: First, the two input operands must be
29598 swapped so that together they form a double-wide array in LE
29599 order. Second, the vperm instruction has surprising behavior
29600 in LE mode: it interprets the elements of the source vectors
29601 in BE mode ("left to right") and interprets the elements of
29602 the destination vector in LE mode ("right to left"). To
29603 correct for this, we must subtract each element of the permute
29604 control vector from 31.
29606 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
29607 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
29608 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
29609 serve as the permute control vector. Then, in BE mode,
29613 places the desired result in vr9. However, in LE mode the
29614 vector contents will be
29616 vr10 = 00000003 00000002 00000001 00000000
29617 vr11 = 00000007 00000006 00000005 00000004
29619 The result of the vperm using the same permute control vector is
29621 vr9 = 05000000 07000000 01000000 03000000
29623 That is, the leftmost 4 bytes of vr10 are interpreted as the
29624 source for the rightmost 4 bytes of vr9, and so on.
29626 If we change the permute control vector to
29628 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
29636 vr9 = 00000006 00000004 00000002 00000000. */
29639 altivec_expand_vec_perm_const_le (rtx operands
[4])
29643 rtx constv
, unspec
;
29644 rtx target
= operands
[0];
29645 rtx op0
= operands
[1];
29646 rtx op1
= operands
[2];
29647 rtx sel
= operands
[3];
29649 /* Unpack and adjust the constant selector. */
29650 for (i
= 0; i
< 16; ++i
)
29652 rtx e
= XVECEXP (sel
, 0, i
);
29653 unsigned int elt
= 31 - (INTVAL (e
) & 31);
29654 perm
[i
] = GEN_INT (elt
);
29657 /* Expand to a permute, swapping the inputs and using the
29658 adjusted selector. */
29660 op0
= force_reg (V16QImode
, op0
);
29662 op1
= force_reg (V16QImode
, op1
);
29664 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
29665 constv
= force_reg (V16QImode
, constv
);
29666 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
29668 if (!REG_P (target
))
29670 rtx tmp
= gen_reg_rtx (V16QImode
);
29671 emit_move_insn (tmp
, unspec
);
29675 emit_move_insn (target
, unspec
);
29678 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
29679 permute control vector. But here it's not a constant, so we must
29680 generate a vector splat/subtract to do the adjustment. */
29683 altivec_expand_vec_perm_le (rtx operands
[4])
29686 rtx target
= operands
[0];
29687 rtx op0
= operands
[1];
29688 rtx op1
= operands
[2];
29689 rtx sel
= operands
[3];
29692 /* Get everything in regs so the pattern matches. */
29694 op0
= force_reg (V16QImode
, op0
);
29696 op1
= force_reg (V16QImode
, op1
);
29698 sel
= force_reg (V16QImode
, sel
);
29699 if (!REG_P (target
))
29700 tmp
= gen_reg_rtx (V16QImode
);
29702 /* SEL = splat(31) - SEL. */
29703 /* We want to subtract from 31, but we can't vspltisb 31 since
29704 it's out of range. -1 works as well because only the low-order
29705 five bits of the permute control vector elements are used. */
29706 splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
29707 gen_rtx_CONST_INT (QImode
, -1));
29708 emit_move_insn (tmp
, splat
);
29709 sel
= gen_rtx_MINUS (V16QImode
, tmp
, sel
);
29710 emit_move_insn (tmp
, sel
);
29712 /* Permute with operands reversed and adjusted selector. */
29713 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, tmp
),
29716 /* Copy into target, possibly by way of a register. */
29717 if (!REG_P (target
))
29719 emit_move_insn (tmp
, unspec
);
29723 emit_move_insn (target
, unspec
);
29726 /* Expand an Altivec constant permutation. Return true if we match
29727 an efficient implementation; false to fall back to VPERM. */
29730 altivec_expand_vec_perm_const (rtx operands
[4])
29732 struct altivec_perm_insn
{
29733 HOST_WIDE_INT mask
;
29734 enum insn_code impl
;
29735 unsigned char perm
[16];
29737 static const struct altivec_perm_insn patterns
[] = {
29738 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
,
29739 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
29740 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
,
29741 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
29742 { OPTION_MASK_ALTIVEC
,
29743 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb
: CODE_FOR_altivec_vmrglb
,
29744 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
29745 { OPTION_MASK_ALTIVEC
,
29746 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh
: CODE_FOR_altivec_vmrglh
,
29747 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
29748 { OPTION_MASK_ALTIVEC
,
29749 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw
: CODE_FOR_altivec_vmrglw
,
29750 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
29751 { OPTION_MASK_ALTIVEC
,
29752 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb
: CODE_FOR_altivec_vmrghb
,
29753 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
29754 { OPTION_MASK_ALTIVEC
,
29755 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh
: CODE_FOR_altivec_vmrghh
,
29756 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
29757 { OPTION_MASK_ALTIVEC
,
29758 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw
: CODE_FOR_altivec_vmrghw
,
29759 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
29760 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
29761 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
29762 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
29763 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
29766 unsigned int i
, j
, elt
, which
;
29767 unsigned char perm
[16];
29768 rtx target
, op0
, op1
, sel
, x
;
29771 target
= operands
[0];
29776 /* Unpack the constant selector. */
29777 for (i
= which
= 0; i
< 16; ++i
)
29779 rtx e
= XVECEXP (sel
, 0, i
);
29780 elt
= INTVAL (e
) & 31;
29781 which
|= (elt
< 16 ? 1 : 2);
29785 /* Simplify the constant selector based on operands. */
29789 gcc_unreachable ();
29793 if (!rtx_equal_p (op0
, op1
))
29798 for (i
= 0; i
< 16; ++i
)
29810 /* Look for splat patterns. */
29815 for (i
= 0; i
< 16; ++i
)
29816 if (perm
[i
] != elt
)
29820 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
29826 for (i
= 0; i
< 16; i
+= 2)
29827 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
29831 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
29832 x
= gen_reg_rtx (V8HImode
);
29833 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
29835 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29842 for (i
= 0; i
< 16; i
+= 4)
29844 || perm
[i
+ 1] != elt
+ 1
29845 || perm
[i
+ 2] != elt
+ 2
29846 || perm
[i
+ 3] != elt
+ 3)
29850 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
29851 x
= gen_reg_rtx (V4SImode
);
29852 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
29854 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29860 /* Look for merge and pack patterns. */
29861 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
29865 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
29868 elt
= patterns
[j
].perm
[0];
29869 if (perm
[0] == elt
)
29871 else if (perm
[0] == elt
+ 16)
29875 for (i
= 1; i
< 16; ++i
)
29877 elt
= patterns
[j
].perm
[i
];
29879 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
29880 else if (one_vec
&& elt
>= 16)
29882 if (perm
[i
] != elt
)
29887 enum insn_code icode
= patterns
[j
].impl
;
29888 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
29889 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
29891 /* For little-endian, don't use vpkuwum and vpkuhum if the
29892 underlying vector type is not V4SI and V8HI, respectively.
29893 For example, using vpkuwum with a V8HI picks up the even
29894 halfwords (BE numbering) when the even halfwords (LE
29895 numbering) are what we need. */
29896 if (!BYTES_BIG_ENDIAN
29897 && icode
== CODE_FOR_altivec_vpkuwum
29898 && ((GET_CODE (op0
) == REG
29899 && GET_MODE (op0
) != V4SImode
)
29900 || (GET_CODE (op0
) == SUBREG
29901 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
29903 if (!BYTES_BIG_ENDIAN
29904 && icode
== CODE_FOR_altivec_vpkuhum
29905 && ((GET_CODE (op0
) == REG
29906 && GET_MODE (op0
) != V8HImode
)
29907 || (GET_CODE (op0
) == SUBREG
29908 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
29911 /* For little-endian, the two input operands must be swapped
29912 (or swapped back) to ensure proper right-to-left numbering
29914 if (swapped
^ !BYTES_BIG_ENDIAN
)
29915 x
= op0
, op0
= op1
, op1
= x
;
29916 if (imode
!= V16QImode
)
29918 op0
= gen_lowpart (imode
, op0
);
29919 op1
= gen_lowpart (imode
, op1
);
29921 if (omode
== V16QImode
)
29924 x
= gen_reg_rtx (omode
);
29925 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
29926 if (omode
!= V16QImode
)
29927 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29932 if (!BYTES_BIG_ENDIAN
)
29934 altivec_expand_vec_perm_const_le (operands
);
29941 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
29942 Return true if we match an efficient implementation. */
29945 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
29946 unsigned char perm0
, unsigned char perm1
)
29950 /* If both selectors come from the same operand, fold to single op. */
29951 if ((perm0
& 2) == (perm1
& 2))
29958 /* If both operands are equal, fold to simpler permutation. */
29959 if (rtx_equal_p (op0
, op1
))
29962 perm1
= (perm1
& 1) + 2;
29964 /* If the first selector comes from the second operand, swap. */
29965 else if (perm0
& 2)
29971 x
= op0
, op0
= op1
, op1
= x
;
29973 /* If the second selector does not come from the second operand, fail. */
29974 else if ((perm1
& 2) == 0)
29978 if (target
!= NULL
)
29980 enum machine_mode vmode
, dmode
;
29983 vmode
= GET_MODE (target
);
29984 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
29985 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
29987 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
29988 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
29989 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
29990 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
29996 rs6000_expand_vec_perm_const (rtx operands
[4])
29998 rtx target
, op0
, op1
, sel
;
29999 unsigned char perm0
, perm1
;
30001 target
= operands
[0];
30006 /* Unpack the constant selector. */
30007 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
30008 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
30010 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
30013 /* Test whether a constant permutation is supported. */
30016 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
30017 const unsigned char *sel
)
30019 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
30020 if (TARGET_ALTIVEC
)
30023 /* Check for ps_merge* or evmerge* insns. */
30024 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
30025 || (TARGET_SPE
&& vmode
== V2SImode
))
30027 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
30028 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
30029 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
30035 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
30038 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
30039 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
30041 enum machine_mode imode
;
30045 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
30047 imode
= GET_MODE_INNER (vmode
);
30048 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
30049 imode
= mode_for_vector (imode
, nelt
);
30052 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
30053 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
30055 emit_move_insn (target
, x
);
30058 /* Expand an extract even operation. */
30061 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
30063 enum machine_mode vmode
= GET_MODE (target
);
30064 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
30067 for (i
= 0; i
< nelt
; i
++)
30068 perm
[i
] = GEN_INT (i
* 2);
30070 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30073 /* Expand a vector interleave operation. */
30076 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
30078 enum machine_mode vmode
= GET_MODE (target
);
30079 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
30082 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
30083 for (i
= 0; i
< nelt
/ 2; i
++)
30085 perm
[i
* 2] = GEN_INT (i
+ high
);
30086 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
30089 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30092 /* Return an RTX representing where to find the function value of a
30093 function returning MODE. */
30095 rs6000_complex_function_value (enum machine_mode mode
)
30097 unsigned int regno
;
30099 enum machine_mode inner
= GET_MODE_INNER (mode
);
30100 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
30102 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30103 regno
= FP_ARG_RETURN
;
30106 regno
= GP_ARG_RETURN
;
30108 /* 32-bit is OK since it'll go in r3/r4. */
30109 if (TARGET_32BIT
&& inner_bytes
>= 4)
30110 return gen_rtx_REG (mode
, regno
);
30113 if (inner_bytes
>= 8)
30114 return gen_rtx_REG (mode
, regno
);
30116 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
30118 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
30119 GEN_INT (inner_bytes
));
30120 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
30123 /* Target hook for TARGET_FUNCTION_VALUE.
30125 On the SPE, both FPs and vectors are returned in r3.
30127 On RS/6000 an integer value is in r3 and a floating-point value is in
30128 fp1, unless -msoft-float. */
30131 rs6000_function_value (const_tree valtype
,
30132 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
30133 bool outgoing ATTRIBUTE_UNUSED
)
30135 enum machine_mode mode
;
30136 unsigned int regno
;
30137 enum machine_mode elt_mode
;
30140 /* Special handling for structs in darwin64. */
30142 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
30144 CUMULATIVE_ARGS valcum
;
30148 valcum
.fregno
= FP_ARG_MIN_REG
;
30149 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
30150 /* Do a trial code generation as if this were going to be passed as
30151 an argument; if any part goes in memory, we return NULL. */
30152 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
30155 /* Otherwise fall through to standard ABI rules. */
30158 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
30159 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype
), valtype
,
30160 &elt_mode
, &n_elts
))
30162 int first_reg
, n_regs
, i
;
30165 if (SCALAR_FLOAT_MODE_P (elt_mode
))
30167 /* _Decimal128 must use even/odd register pairs. */
30168 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30169 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
30173 first_reg
= ALTIVEC_ARG_RETURN
;
30177 par
= gen_rtx_PARALLEL (TYPE_MODE (valtype
), rtvec_alloc (n_elts
));
30178 for (i
= 0; i
< n_elts
; i
++)
30180 rtx r
= gen_rtx_REG (elt_mode
, first_reg
+ i
* n_regs
);
30181 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
30182 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
30188 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
30190 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30191 return gen_rtx_PARALLEL (DImode
,
30193 gen_rtx_EXPR_LIST (VOIDmode
,
30194 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30196 gen_rtx_EXPR_LIST (VOIDmode
,
30197 gen_rtx_REG (SImode
,
30198 GP_ARG_RETURN
+ 1),
30201 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
30203 return gen_rtx_PARALLEL (DCmode
,
30205 gen_rtx_EXPR_LIST (VOIDmode
,
30206 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30208 gen_rtx_EXPR_LIST (VOIDmode
,
30209 gen_rtx_REG (SImode
,
30210 GP_ARG_RETURN
+ 1),
30212 gen_rtx_EXPR_LIST (VOIDmode
,
30213 gen_rtx_REG (SImode
,
30214 GP_ARG_RETURN
+ 2),
30216 gen_rtx_EXPR_LIST (VOIDmode
,
30217 gen_rtx_REG (SImode
,
30218 GP_ARG_RETURN
+ 3),
30222 mode
= TYPE_MODE (valtype
);
30223 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
30224 || (POINTER_TYPE_P (valtype
) && !upc_shared_type_p (TREE_TYPE (valtype
))))
30225 mode
= TARGET_32BIT
? SImode
: DImode
;
30227 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30228 /* _Decimal128 must use an even/odd register pair. */
30229 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30230 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
30231 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
30232 regno
= FP_ARG_RETURN
;
30233 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
30234 && targetm
.calls
.split_complex_arg
)
30235 return rs6000_complex_function_value (mode
);
30236 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30237 return register is used in both cases, and we won't see V2DImode/V2DFmode
30238 for pure altivec, combine the two cases. */
30239 else if (TREE_CODE (valtype
) == VECTOR_TYPE
30240 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
30241 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
30242 regno
= ALTIVEC_ARG_RETURN
;
30243 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30244 && (mode
== DFmode
|| mode
== DCmode
30245 || mode
== TFmode
|| mode
== TCmode
))
30246 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30248 regno
= GP_ARG_RETURN
;
30250 return gen_rtx_REG (mode
, regno
);
30253 /* Define how to find the value returned by a library function
30254 assuming the value has mode MODE. */
30256 rs6000_libcall_value (enum machine_mode mode
)
30258 unsigned int regno
;
30260 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
30262 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30263 return gen_rtx_PARALLEL (DImode
,
30265 gen_rtx_EXPR_LIST (VOIDmode
,
30266 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30268 gen_rtx_EXPR_LIST (VOIDmode
,
30269 gen_rtx_REG (SImode
,
30270 GP_ARG_RETURN
+ 1),
30274 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30275 /* _Decimal128 must use an even/odd register pair. */
30276 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30277 else if (SCALAR_FLOAT_MODE_P (mode
)
30278 && TARGET_HARD_FLOAT
&& TARGET_FPRS
30279 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
30280 regno
= FP_ARG_RETURN
;
30281 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30282 return register is used in both cases, and we won't see V2DImode/V2DFmode
30283 for pure altivec, combine the two cases. */
30284 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
30285 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
30286 regno
= ALTIVEC_ARG_RETURN
;
30287 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
30288 return rs6000_complex_function_value (mode
);
30289 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30290 && (mode
== DFmode
|| mode
== DCmode
30291 || mode
== TFmode
|| mode
== TCmode
))
30292 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30294 regno
= GP_ARG_RETURN
;
30296 return gen_rtx_REG (mode
, regno
);
30300 /* Return true if we use LRA instead of reload pass. */
30302 rs6000_lra_p (void)
30304 return rs6000_lra_flag
;
30307 /* Given FROM and TO register numbers, say whether this elimination is allowed.
30308 Frame pointer elimination is automatically handled.
30310 For the RS/6000, if frame pointer elimination is being done, we would like
30311 to convert ap into fp, not sp.
30313 We need r30 if -mminimal-toc was specified, and there are constant pool
30317 rs6000_can_eliminate (const int from
, const int to
)
30319 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
30320 ? ! frame_pointer_needed
30321 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
30322 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
30326 /* Define the offset between two registers, FROM to be eliminated and its
30327 replacement TO, at the start of a routine. */
30329 rs6000_initial_elimination_offset (int from
, int to
)
30331 rs6000_stack_t
*info
= rs6000_stack_info ();
30332 HOST_WIDE_INT offset
;
30334 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30335 offset
= info
->push_p
? 0 : -info
->total_size
;
30336 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30338 offset
= info
->push_p
? 0 : -info
->total_size
;
30339 if (FRAME_GROWS_DOWNWARD
)
30340 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
30342 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30343 offset
= FRAME_GROWS_DOWNWARD
30344 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
30346 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30347 offset
= info
->total_size
;
30348 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30349 offset
= info
->push_p
? info
->total_size
: 0;
30350 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
30353 gcc_unreachable ();
30359 rs6000_dwarf_register_span (rtx reg
)
30363 unsigned regno
= REGNO (reg
);
30364 enum machine_mode mode
= GET_MODE (reg
);
30368 && (SPE_VECTOR_MODE (GET_MODE (reg
))
30369 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
30370 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
30375 regno
= REGNO (reg
);
30377 /* The duality of the SPE register size wreaks all kinds of havoc.
30378 This is a way of distinguishing r0 in 32-bits from r0 in
30380 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
30381 gcc_assert (words
<= 4);
30382 for (i
= 0; i
< words
; i
++, regno
++)
30384 if (BYTES_BIG_ENDIAN
)
30386 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
30387 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
30391 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
30392 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
30396 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
30399 /* Fill in sizes for SPE register high parts in table used by unwinder. */
30402 rs6000_init_dwarf_reg_sizes_extra (tree address
)
30407 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30408 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30409 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30410 rtx value
= gen_int_mode (4, mode
);
30412 for (i
= 1201; i
< 1232; i
++)
30414 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30415 HOST_WIDE_INT offset
30416 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30418 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
30422 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
30425 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30426 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30427 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30428 rtx value
= gen_int_mode (16, mode
);
30430 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
30431 The unwinder still needs to know the size of Altivec registers. */
30433 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
30435 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30436 HOST_WIDE_INT offset
30437 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30439 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
30444 /* Map internal gcc register numbers to DWARF2 register numbers. */
30447 rs6000_dbx_register_number (unsigned int regno
)
30449 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
30451 if (regno
== LR_REGNO
)
30453 if (regno
== CTR_REGNO
)
30455 if (CR_REGNO_P (regno
))
30456 return regno
- CR0_REGNO
+ 86;
30457 if (regno
== CA_REGNO
)
30458 return 101; /* XER */
30459 if (ALTIVEC_REGNO_P (regno
))
30460 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
30461 if (regno
== VRSAVE_REGNO
)
30463 if (regno
== VSCR_REGNO
)
30465 if (regno
== SPE_ACC_REGNO
)
30467 if (regno
== SPEFSCR_REGNO
)
30469 /* SPE high reg number. We get these values of regno from
30470 rs6000_dwarf_register_span. */
30471 gcc_assert (regno
>= 1200 && regno
< 1232);
30475 /* target hook eh_return_filter_mode */
30476 static enum machine_mode
30477 rs6000_eh_return_filter_mode (void)
30479 return TARGET_32BIT
? SImode
: word_mode
;
30482 /* Target hook for scalar_mode_supported_p. */
30484 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
30486 if (DECIMAL_FLOAT_MODE_P (mode
))
30487 return default_decimal_float_supported_p ();
30489 return default_scalar_mode_supported_p (mode
);
30492 /* Target hook for vector_mode_supported_p. */
30494 rs6000_vector_mode_supported_p (enum machine_mode mode
)
30497 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
30500 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
30503 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
30510 /* Target hook for invalid_arg_for_unprototyped_fn. */
30511 static const char *
30512 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
30514 return (!rs6000_darwin64_abi
30516 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
30517 && (funcdecl
== NULL_TREE
30518 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
30519 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
30520 ? N_("AltiVec argument passed to unprototyped function")
30524 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
30525 setup by using __stack_chk_fail_local hidden function instead of
30526 calling __stack_chk_fail directly. Otherwise it is better to call
30527 __stack_chk_fail directly. */
30529 static tree ATTRIBUTE_UNUSED
30530 rs6000_stack_protect_fail (void)
30532 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
30533 ? default_hidden_stack_protect_fail ()
30534 : default_external_stack_protect_fail ();
30538 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
30539 int num_operands ATTRIBUTE_UNUSED
)
30541 if (rs6000_warn_cell_microcode
)
30544 int insn_code_number
= recog_memoized (insn
);
30545 location_t location
= INSN_LOCATION (insn
);
30547 /* Punt on insns we cannot recognize. */
30548 if (insn_code_number
< 0)
30551 temp
= get_insn_template (insn_code_number
, insn
);
30553 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
30554 warning_at (location
, OPT_mwarn_cell_microcode
,
30555 "emitting microcode insn %s\t[%s] #%d",
30556 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
30557 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
30558 warning_at (location
, OPT_mwarn_cell_microcode
,
30559 "emitting conditional microcode insn %s\t[%s] #%d",
30560 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
30564 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
30567 static unsigned HOST_WIDE_INT
30568 rs6000_asan_shadow_offset (void)
30570 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
30574 /* Mask options that we want to support inside of attribute((target)) and
30575 #pragma GCC target operations. Note, we do not include things like
30576 64/32-bit, endianess, hard/soft floating point, etc. that would have
30577 different calling sequences. */
30579 struct rs6000_opt_mask
{
30580 const char *name
; /* option name */
30581 HOST_WIDE_INT mask
; /* mask to set */
30582 bool invert
; /* invert sense of mask */
30583 bool valid_target
; /* option is a target option */
30586 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
30588 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
30589 { "cmpb", OPTION_MASK_CMPB
, false, true },
30590 { "crypto", OPTION_MASK_CRYPTO
, false, true },
30591 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
30592 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
30593 { "fprnd", OPTION_MASK_FPRND
, false, true },
30594 { "hard-dfp", OPTION_MASK_DFP
, false, true },
30595 { "htm", OPTION_MASK_HTM
, false, true },
30596 { "isel", OPTION_MASK_ISEL
, false, true },
30597 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
30598 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
30599 { "mulhw", OPTION_MASK_MULHW
, false, true },
30600 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
30601 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
30602 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
30603 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
30604 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
30605 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
30606 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
30607 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
30608 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
30609 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
30610 { "string", OPTION_MASK_STRING
, false, true },
30611 { "update", OPTION_MASK_NO_UPDATE
, true , true },
30612 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
30613 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
30614 { "vsx", OPTION_MASK_VSX
, false, true },
30615 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
30616 #ifdef OPTION_MASK_64BIT
30618 { "aix64", OPTION_MASK_64BIT
, false, false },
30619 { "aix32", OPTION_MASK_64BIT
, true, false },
30621 { "64", OPTION_MASK_64BIT
, false, false },
30622 { "32", OPTION_MASK_64BIT
, true, false },
30625 #ifdef OPTION_MASK_EABI
30626 { "eabi", OPTION_MASK_EABI
, false, false },
30628 #ifdef OPTION_MASK_LITTLE_ENDIAN
30629 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
30630 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
30632 #ifdef OPTION_MASK_RELOCATABLE
30633 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
30635 #ifdef OPTION_MASK_STRICT_ALIGN
30636 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
30638 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
30639 { "string", OPTION_MASK_STRING
, false, false },
30642 /* Builtin mask mapping for printing the flags. */
30643 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
30645 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
30646 { "vsx", RS6000_BTM_VSX
, false, false },
30647 { "spe", RS6000_BTM_SPE
, false, false },
30648 { "paired", RS6000_BTM_PAIRED
, false, false },
30649 { "fre", RS6000_BTM_FRE
, false, false },
30650 { "fres", RS6000_BTM_FRES
, false, false },
30651 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
30652 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
30653 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
30654 { "cell", RS6000_BTM_CELL
, false, false },
30655 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
30656 { "crypto", RS6000_BTM_CRYPTO
, false, false },
30657 { "htm", RS6000_BTM_HTM
, false, false },
30660 /* Option variables that we want to support inside attribute((target)) and
30661 #pragma GCC target operations. */
30663 struct rs6000_opt_var
{
30664 const char *name
; /* option name */
30665 size_t global_offset
; /* offset of the option in global_options. */
30666 size_t target_offset
; /* offset of the option in target optiosn. */
30669 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
30672 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
30673 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
30674 { "avoid-indexed-addresses",
30675 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
30676 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
30678 offsetof (struct gcc_options
, x_rs6000_paired_float
),
30679 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
30681 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
30682 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
30685 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
30686 parsing. Return true if there were no errors. */
30689 rs6000_inner_target_options (tree args
, bool attr_p
)
30693 if (args
== NULL_TREE
)
30696 else if (TREE_CODE (args
) == STRING_CST
)
30698 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
30701 while ((q
= strtok (p
, ",")) != NULL
)
30703 bool error_p
= false;
30704 bool not_valid_p
= false;
30705 const char *cpu_opt
= NULL
;
30708 if (strncmp (q
, "cpu=", 4) == 0)
30710 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
30711 if (cpu_index
>= 0)
30712 rs6000_cpu_index
= cpu_index
;
30719 else if (strncmp (q
, "tune=", 5) == 0)
30721 int tune_index
= rs6000_cpu_name_lookup (q
+5);
30722 if (tune_index
>= 0)
30723 rs6000_tune_index
= tune_index
;
30733 bool invert
= false;
30737 if (strncmp (r
, "no-", 3) == 0)
30743 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
30744 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
30746 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
30748 if (!rs6000_opt_masks
[i
].valid_target
)
30749 not_valid_p
= true;
30753 rs6000_isa_flags_explicit
|= mask
;
30755 /* VSX needs altivec, so -mvsx automagically sets
30757 if (mask
== OPTION_MASK_VSX
&& !invert
)
30758 mask
|= OPTION_MASK_ALTIVEC
;
30760 if (rs6000_opt_masks
[i
].invert
)
30764 rs6000_isa_flags
&= ~mask
;
30766 rs6000_isa_flags
|= mask
;
30771 if (error_p
&& !not_valid_p
)
30773 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
30774 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
30776 size_t j
= rs6000_opt_vars
[i
].global_offset
;
30777 *((int *) ((char *)&global_options
+ j
)) = !invert
;
30786 const char *eprefix
, *esuffix
;
30791 eprefix
= "__attribute__((__target__(";
30796 eprefix
= "#pragma GCC target ";
30801 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
30803 else if (not_valid_p
)
30804 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
30806 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
30811 else if (TREE_CODE (args
) == TREE_LIST
)
30815 tree value
= TREE_VALUE (args
);
30818 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
30822 args
= TREE_CHAIN (args
);
30824 while (args
!= NULL_TREE
);
30828 gcc_unreachable ();
30833 /* Print out the target options as a list for -mdebug=target. */
30836 rs6000_debug_target_options (tree args
, const char *prefix
)
30838 if (args
== NULL_TREE
)
30839 fprintf (stderr
, "%s<NULL>", prefix
);
30841 else if (TREE_CODE (args
) == STRING_CST
)
30843 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
30846 while ((q
= strtok (p
, ",")) != NULL
)
30849 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
30854 else if (TREE_CODE (args
) == TREE_LIST
)
30858 tree value
= TREE_VALUE (args
);
30861 rs6000_debug_target_options (value
, prefix
);
30864 args
= TREE_CHAIN (args
);
30866 while (args
!= NULL_TREE
);
30870 gcc_unreachable ();
30876 /* Hook to validate attribute((target("..."))). */
30879 rs6000_valid_attribute_p (tree fndecl
,
30880 tree
ARG_UNUSED (name
),
30884 struct cl_target_option cur_target
;
30886 tree old_optimize
= build_optimization_node (&global_options
);
30887 tree new_target
, new_optimize
;
30888 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30890 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
30892 if (TARGET_DEBUG_TARGET
)
30894 tree tname
= DECL_NAME (fndecl
);
30895 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
30897 fprintf (stderr
, "function: %.*s\n",
30898 (int) IDENTIFIER_LENGTH (tname
),
30899 IDENTIFIER_POINTER (tname
));
30901 fprintf (stderr
, "function: unknown\n");
30903 fprintf (stderr
, "args:");
30904 rs6000_debug_target_options (args
, " ");
30905 fprintf (stderr
, "\n");
30908 fprintf (stderr
, "flags: 0x%x\n", flags
);
30910 fprintf (stderr
, "--------------------\n");
30913 old_optimize
= build_optimization_node (&global_options
);
30914 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30916 /* If the function changed the optimization levels as well as setting target
30917 options, start with the optimizations specified. */
30918 if (func_optimize
&& func_optimize
!= old_optimize
)
30919 cl_optimization_restore (&global_options
,
30920 TREE_OPTIMIZATION (func_optimize
));
30922 /* The target attributes may also change some optimization flags, so update
30923 the optimization options if necessary. */
30924 cl_target_option_save (&cur_target
, &global_options
);
30925 rs6000_cpu_index
= rs6000_tune_index
= -1;
30926 ret
= rs6000_inner_target_options (args
, true);
30928 /* Set up any additional state. */
30931 ret
= rs6000_option_override_internal (false);
30932 new_target
= build_target_option_node (&global_options
);
30937 new_optimize
= build_optimization_node (&global_options
);
30944 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
30946 if (old_optimize
!= new_optimize
)
30947 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
30950 cl_target_option_restore (&global_options
, &cur_target
);
30952 if (old_optimize
!= new_optimize
)
30953 cl_optimization_restore (&global_options
,
30954 TREE_OPTIMIZATION (old_optimize
));
30960 /* Hook to validate the current #pragma GCC target and set the state, and
30961 update the macros based on what was changed. If ARGS is NULL, then
30962 POP_TARGET is used to reset the options. */
30965 rs6000_pragma_target_parse (tree args
, tree pop_target
)
30967 tree prev_tree
= build_target_option_node (&global_options
);
30969 struct cl_target_option
*prev_opt
, *cur_opt
;
30970 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
30971 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
30973 if (TARGET_DEBUG_TARGET
)
30975 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
30976 fprintf (stderr
, "args:");
30977 rs6000_debug_target_options (args
, " ");
30978 fprintf (stderr
, "\n");
30982 fprintf (stderr
, "pop_target:\n");
30983 debug_tree (pop_target
);
30986 fprintf (stderr
, "pop_target: <NULL>\n");
30988 fprintf (stderr
, "--------------------\n");
30993 cur_tree
= ((pop_target
)
30995 : target_option_default_node
);
30996 cl_target_option_restore (&global_options
,
30997 TREE_TARGET_OPTION (cur_tree
));
31001 rs6000_cpu_index
= rs6000_tune_index
= -1;
31002 if (!rs6000_inner_target_options (args
, false)
31003 || !rs6000_option_override_internal (false)
31004 || (cur_tree
= build_target_option_node (&global_options
))
31007 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
31008 fprintf (stderr
, "invalid pragma\n");
31014 target_option_current_node
= cur_tree
;
31016 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
31017 change the macros that are defined. */
31018 if (rs6000_target_modify_macros_ptr
)
31020 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
31021 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
31022 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
31024 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
31025 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
31026 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
31028 diff_bumask
= (prev_bumask
^ cur_bumask
);
31029 diff_flags
= (prev_flags
^ cur_flags
);
31031 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
31033 /* Delete old macros. */
31034 rs6000_target_modify_macros_ptr (false,
31035 prev_flags
& diff_flags
,
31036 prev_bumask
& diff_bumask
);
31038 /* Define new macros. */
31039 rs6000_target_modify_macros_ptr (true,
31040 cur_flags
& diff_flags
,
31041 cur_bumask
& diff_bumask
);
31049 /* Remember the last target of rs6000_set_current_function. */
31050 static GTY(()) tree rs6000_previous_fndecl
;
31052 /* Establish appropriate back-end context for processing the function
31053 FNDECL. The argument might be NULL to indicate processing at top
31054 level, outside of any function scope. */
31056 rs6000_set_current_function (tree fndecl
)
31058 tree old_tree
= (rs6000_previous_fndecl
31059 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
31062 tree new_tree
= (fndecl
31063 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
31066 if (TARGET_DEBUG_TARGET
)
31068 bool print_final
= false;
31069 fprintf (stderr
, "\n==================== rs6000_set_current_function");
31072 fprintf (stderr
, ", fndecl %s (%p)",
31073 (DECL_NAME (fndecl
)
31074 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
31075 : "<unknown>"), (void *)fndecl
);
31077 if (rs6000_previous_fndecl
)
31078 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
31080 fprintf (stderr
, "\n");
31083 fprintf (stderr
, "\nnew fndecl target specific options:\n");
31084 debug_tree (new_tree
);
31085 print_final
= true;
31090 fprintf (stderr
, "\nold fndecl target specific options:\n");
31091 debug_tree (old_tree
);
31092 print_final
= true;
31096 fprintf (stderr
, "--------------------\n");
31099 /* Only change the context if the function changes. This hook is called
31100 several times in the course of compiling a function, and we don't want to
31101 slow things down too much or call target_reinit when it isn't safe. */
31102 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
31104 rs6000_previous_fndecl
= fndecl
;
31105 if (old_tree
== new_tree
)
31110 cl_target_option_restore (&global_options
,
31111 TREE_TARGET_OPTION (new_tree
));
31117 struct cl_target_option
*def
31118 = TREE_TARGET_OPTION (target_option_current_node
);
31120 cl_target_option_restore (&global_options
, def
);
31127 /* Save the current options */
31130 rs6000_function_specific_save (struct cl_target_option
*ptr
,
31131 struct gcc_options
*opts
)
31133 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
31134 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
31137 /* Restore the current options */
31140 rs6000_function_specific_restore (struct gcc_options
*opts
,
31141 struct cl_target_option
*ptr
)
31144 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
31145 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
31146 (void) rs6000_option_override_internal (false);
31149 /* Print the current options */
31152 rs6000_function_specific_print (FILE *file
, int indent
,
31153 struct cl_target_option
*ptr
)
31155 rs6000_print_isa_options (file
, indent
, "Isa options set",
31156 ptr
->x_rs6000_isa_flags
);
31158 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
31159 ptr
->x_rs6000_isa_flags_explicit
);
31162 /* Helper function to print the current isa or misc options on a line. */
31165 rs6000_print_options_internal (FILE *file
,
31167 const char *string
,
31168 HOST_WIDE_INT flags
,
31169 const char *prefix
,
31170 const struct rs6000_opt_mask
*opts
,
31171 size_t num_elements
)
31174 size_t start_column
= 0;
31176 size_t max_column
= 76;
31177 const char *comma
= "";
31180 start_column
+= fprintf (file
, "%*s", indent
, "");
31184 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
31188 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
31190 /* Print the various mask options. */
31191 cur_column
= start_column
;
31192 for (i
= 0; i
< num_elements
; i
++)
31194 if ((flags
& opts
[i
].mask
) != 0)
31196 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
31197 size_t len
= (strlen (comma
)
31200 + strlen (rs6000_opt_masks
[i
].name
));
31203 if (cur_column
> max_column
)
31205 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
31206 cur_column
= start_column
+ len
;
31210 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
31211 rs6000_opt_masks
[i
].name
);
31212 flags
&= ~ opts
[i
].mask
;
31217 fputs ("\n", file
);
31220 /* Helper function to print the current isa options on a line. */
31223 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
31224 HOST_WIDE_INT flags
)
31226 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
31227 &rs6000_opt_masks
[0],
31228 ARRAY_SIZE (rs6000_opt_masks
));
31232 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
31233 HOST_WIDE_INT flags
)
31235 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
31236 &rs6000_builtin_mask_names
[0],
31237 ARRAY_SIZE (rs6000_builtin_mask_names
));
31241 /* Hook to determine if one function can safely inline another. */
31244 rs6000_can_inline_p (tree caller
, tree callee
)
31247 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
31248 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
31250 /* If callee has no option attributes, then it is ok to inline. */
31254 /* If caller has no option attributes, but callee does then it is not ok to
31256 else if (!caller_tree
)
31261 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
31262 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
31264 /* Callee's options should a subset of the caller's, i.e. a vsx function
31265 can inline an altivec function but a non-vsx function can't inline a
31267 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
31268 == callee_opts
->x_rs6000_isa_flags
)
31272 if (TARGET_DEBUG_TARGET
)
31273 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
31274 (DECL_NAME (caller
)
31275 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
31277 (DECL_NAME (callee
)
31278 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
31280 (ret
? "can" : "cannot"));
31285 /* Allocate a stack temp and fixup the address so it meets the particular
31286 memory requirements (either offetable or REG+REG addressing). */
31289 rs6000_allocate_stack_temp (enum machine_mode mode
,
31290 bool offsettable_p
,
31293 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
31294 rtx addr
= XEXP (stack
, 0);
31295 int strict_p
= (reload_in_progress
|| reload_completed
);
31297 if (!legitimate_indirect_address_p (addr
, strict_p
))
31300 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
31301 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31303 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
31304 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31310 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
31311 to such a form to deal with memory reference instructions like STFIWX that
31312 only take reg+reg addressing. */
31315 rs6000_address_for_fpconvert (rtx x
)
31317 int strict_p
= (reload_in_progress
|| reload_completed
);
31320 gcc_assert (MEM_P (x
));
31321 addr
= XEXP (x
, 0);
31322 if (! legitimate_indirect_address_p (addr
, strict_p
)
31323 && ! legitimate_indexed_address_p (addr
, strict_p
))
31325 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
31327 rtx reg
= XEXP (addr
, 0);
31328 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
31329 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
31330 gcc_assert (REG_P (reg
));
31331 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
31334 else if (GET_CODE (addr
) == PRE_MODIFY
)
31336 rtx reg
= XEXP (addr
, 0);
31337 rtx expr
= XEXP (addr
, 1);
31338 gcc_assert (REG_P (reg
));
31339 gcc_assert (GET_CODE (expr
) == PLUS
);
31340 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
31344 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
31350 /* Given a memory reference, if it is not in the form for altivec memory
31351 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
31352 convert to the altivec format. */
31355 rs6000_address_for_altivec (rtx x
)
31357 gcc_assert (MEM_P (x
));
31358 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
31360 rtx addr
= XEXP (x
, 0);
31361 int strict_p
= (reload_in_progress
|| reload_completed
);
31363 if (!legitimate_indexed_address_p (addr
, strict_p
)
31364 && !legitimate_indirect_address_p (addr
, strict_p
))
31365 addr
= copy_to_mode_reg (Pmode
, addr
);
31367 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
31368 x
= change_address (x
, GET_MODE (x
), addr
);
31374 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
31376 On the RS/6000, all integer constants are acceptable, most won't be valid
31377 for particular insns, though. Only easy FP constants are acceptable. */
31380 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
31382 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
31385 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
31386 || GET_MODE (x
) == VOIDmode
31387 || (TARGET_POWERPC64
&& mode
== DImode
)
31388 || easy_fp_constant (x
, mode
)
31389 || easy_vector_constant (x
, mode
));
31394 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
31397 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
31399 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
31400 rtx toc_load
= NULL_RTX
;
31401 rtx toc_restore
= NULL_RTX
;
31403 rtx abi_reg
= NULL_RTX
;
31408 /* Handle longcall attributes. */
31409 if (INTVAL (cookie
) & CALL_LONG
)
31410 func_desc
= rs6000_longcall_ref (func_desc
);
31412 /* Handle indirect calls. */
31413 if (GET_CODE (func_desc
) != SYMBOL_REF
31414 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
31416 /* Save the TOC into its reserved slot before the call,
31417 and prepare to restore it after the call. */
31418 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
31419 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
31420 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
31421 gen_rtx_PLUS (Pmode
, stack_ptr
,
31422 stack_toc_offset
));
31423 toc_restore
= gen_rtx_SET (VOIDmode
, toc_reg
, stack_toc_mem
);
31425 /* Can we optimize saving the TOC in the prologue or
31426 do we need to do it at every call? */
31427 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
31428 cfun
->machine
->save_toc_in_prologue
= true;
31431 MEM_VOLATILE_P (stack_toc_mem
) = 1;
31432 emit_move_insn (stack_toc_mem
, toc_reg
);
31435 if (DEFAULT_ABI
== ABI_ELFv2
)
31437 /* A function pointer in the ELFv2 ABI is just a plain address, but
31438 the ABI requires it to be loaded into r12 before the call. */
31439 func_addr
= gen_rtx_REG (Pmode
, 12);
31440 emit_move_insn (func_addr
, func_desc
);
31441 abi_reg
= func_addr
;
31445 /* A function pointer under AIX is a pointer to a data area whose
31446 first word contains the actual address of the function, whose
31447 second word contains a pointer to its TOC, and whose third word
31448 contains a value to place in the static chain register (r11).
31449 Note that if we load the static chain, our "trampoline" need
31450 not have any executable code. */
31452 /* Load up address of the actual function. */
31453 func_desc
= force_reg (Pmode
, func_desc
);
31454 func_addr
= gen_reg_rtx (Pmode
);
31455 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
31457 /* Prepare to load the TOC of the called function. Note that the
31458 TOC load must happen immediately before the actual call so
31459 that unwinding the TOC registers works correctly. See the
31460 comment in frob_update_context. */
31461 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
31462 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
31463 gen_rtx_PLUS (Pmode
, func_desc
,
31465 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
31467 /* If we have a static chain, load it up. */
31468 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
31470 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
31471 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
31472 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
31473 gen_rtx_PLUS (Pmode
, func_desc
,
31475 emit_move_insn (sc_reg
, func_sc_mem
);
31482 /* Direct calls use the TOC: for local calls, the callee will
31483 assume the TOC register is set; for non-local calls, the
31484 PLT stub needs the TOC register. */
31486 func_addr
= func_desc
;
31489 /* Create the call. */
31490 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
31491 if (value
!= NULL_RTX
)
31492 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
31496 call
[n_call
++] = toc_load
;
31498 call
[n_call
++] = toc_restore
;
31500 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
31502 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
31503 insn
= emit_call_insn (insn
);
31505 /* Mention all registers defined by the ABI to hold information
31506 as uses in CALL_INSN_FUNCTION_USAGE. */
31508 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
31511 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
31514 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
31519 gcc_assert (INTVAL (cookie
) == 0);
31521 /* Create the call. */
31522 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
31523 if (value
!= NULL_RTX
)
31524 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
31526 call
[1] = simple_return_rtx
;
31528 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
31529 insn
= emit_call_insn (insn
);
31531 /* Note use of the TOC register. */
31532 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
31533 /* We need to also mark a use of the link register since the function we
31534 sibling-call to will use it to return to our caller. */
31535 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
31538 /* Return whether we need to always update the saved TOC pointer when we update
31539 the stack pointer. */
31542 rs6000_save_toc_in_prologue_p (void)
31544 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
31547 #ifdef HAVE_GAS_HIDDEN
31548 # define USE_HIDDEN_LINKONCE 1
31550 # define USE_HIDDEN_LINKONCE 0
31553 /* Fills in the label name that should be used for a 476 link stack thunk. */
31556 get_ppc476_thunk_name (char name
[32])
31558 gcc_assert (TARGET_LINK_STACK
);
31560 if (USE_HIDDEN_LINKONCE
)
31561 sprintf (name
, "__ppc476.get_thunk");
31563 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
31566 /* This function emits the simple thunk routine that is used to preserve
31567 the link stack on the 476 cpu. */
31569 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
31571 rs6000_code_end (void)
31576 if (!TARGET_LINK_STACK
)
31579 get_ppc476_thunk_name (name
);
31581 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
31582 build_function_type_list (void_type_node
, NULL_TREE
));
31583 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
31584 NULL_TREE
, void_type_node
);
31585 TREE_PUBLIC (decl
) = 1;
31586 TREE_STATIC (decl
) = 1;
31589 if (USE_HIDDEN_LINKONCE
)
31591 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
31592 targetm
.asm_out
.unique_section (decl
, 0);
31593 switch_to_section (get_named_section (decl
, NULL
, 0));
31594 DECL_WEAK (decl
) = 1;
31595 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
31596 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
31597 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
31598 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
31603 switch_to_section (text_section
);
31604 ASM_OUTPUT_LABEL (asm_out_file
, name
);
31607 DECL_INITIAL (decl
) = make_node (BLOCK
);
31608 current_function_decl
= decl
;
31609 init_function_start (decl
);
31610 first_function_block_is_cold
= false;
31611 /* Make sure unwind info is emitted for the thunk if needed. */
31612 final_start_function (emit_barrier (), asm_out_file
, 1);
31614 fputs ("\tblr\n", asm_out_file
);
31616 final_end_function ();
31617 init_insn_lengths ();
31618 free_after_compilation (cfun
);
31620 current_function_decl
= NULL
;
31623 /* Add r30 to hard reg set if the prologue sets it up and it is not
31624 pic_offset_table_rtx. */
31627 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
31629 if (!TARGET_SINGLE_PIC_BASE
31631 && TARGET_MINIMAL_TOC
31632 && get_pool_size () != 0)
31633 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
31637 /* Helper function for rs6000_split_logical to emit a logical instruction after
31638 spliting the operation to single GPR registers.
31640 DEST is the destination register.
31641 OP1 and OP2 are the input source registers.
31642 CODE is the base operation (AND, IOR, XOR, NOT).
31643 MODE is the machine mode.
31644 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31645 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31646 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31647 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31648 formation of the AND instructions. */
31651 rs6000_split_logical_inner (rtx dest
,
31654 enum rtx_code code
,
31655 enum machine_mode mode
,
31656 bool complement_final_p
,
31657 bool complement_op1_p
,
31658 bool complement_op2_p
,
31664 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
31665 if (op2
&& GET_CODE (op2
) == CONST_INT
31666 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
31667 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
31669 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
31670 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
31672 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
31677 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
31681 else if (value
== mask
)
31683 if (!rtx_equal_p (dest
, op1
))
31684 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
31689 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
31690 into separate ORI/ORIS or XORI/XORIS instrucitons. */
31691 else if (code
== IOR
|| code
== XOR
)
31695 if (!rtx_equal_p (dest
, op1
))
31696 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
31702 if (complement_op1_p
)
31703 op1
= gen_rtx_NOT (mode
, op1
);
31705 if (complement_op2_p
)
31706 op2
= gen_rtx_NOT (mode
, op2
);
31708 bool_rtx
= ((code
== NOT
)
31709 ? gen_rtx_NOT (mode
, op1
)
31710 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
31712 if (complement_final_p
)
31713 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
31715 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
31717 /* Is this AND with an explicit clobber? */
31720 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
31721 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
31724 emit_insn (set_rtx
);
31728 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
31729 operations are split immediately during RTL generation to allow for more
31730 optimizations of the AND/IOR/XOR.
31732 OPERANDS is an array containing the destination and two input operands.
31733 CODE is the base operation (AND, IOR, XOR, NOT).
31734 MODE is the machine mode.
31735 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31736 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31737 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31738 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31739 formation of the AND instructions. */
31742 rs6000_split_logical_di (rtx operands
[3],
31743 enum rtx_code code
,
31744 bool complement_final_p
,
31745 bool complement_op1_p
,
31746 bool complement_op2_p
,
31749 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
31750 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
31751 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
31752 enum hi_lo
{ hi
= 0, lo
= 1 };
31753 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
31756 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
31757 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
31758 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
31759 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
31762 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
31765 if (GET_CODE (operands
[2]) != CONST_INT
)
31767 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
31768 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
31772 HOST_WIDE_INT value
= INTVAL (operands
[2]);
31773 HOST_WIDE_INT value_hi_lo
[2];
31775 gcc_assert (!complement_final_p
);
31776 gcc_assert (!complement_op1_p
);
31777 gcc_assert (!complement_op2_p
);
31779 value_hi_lo
[hi
] = value
>> 32;
31780 value_hi_lo
[lo
] = value
& lower_32bits
;
31782 for (i
= 0; i
< 2; i
++)
31784 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
31786 if (sub_value
& sign_bit
)
31787 sub_value
|= upper_32bits
;
31789 op2_hi_lo
[i
] = GEN_INT (sub_value
);
31791 /* If this is an AND instruction, check to see if we need to load
31792 the value in a register. */
31793 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
31794 && !and_operand (op2_hi_lo
[i
], SImode
))
31795 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
31800 for (i
= 0; i
< 2; i
++)
31802 /* Split large IOR/XOR operations. */
31803 if ((code
== IOR
|| code
== XOR
)
31804 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
31805 && !complement_final_p
31806 && !complement_op1_p
31807 && !complement_op2_p
31808 && clobber_reg
== NULL_RTX
31809 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
31811 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
31812 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
31813 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
31814 rtx tmp
= gen_reg_rtx (SImode
);
31816 /* Make sure the constant is sign extended. */
31817 if ((hi_16bits
& sign_bit
) != 0)
31818 hi_16bits
|= upper_32bits
;
31820 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
31821 code
, SImode
, false, false, false,
31824 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
31825 code
, SImode
, false, false, false,
31829 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
31830 code
, SImode
, complement_final_p
,
31831 complement_op1_p
, complement_op2_p
,
31838 /* Split the insns that make up boolean operations operating on multiple GPR
31839 registers. The boolean MD patterns ensure that the inputs either are
31840 exactly the same as the output registers, or there is no overlap.
31842 OPERANDS is an array containing the destination and two input operands.
31843 CODE is the base operation (AND, IOR, XOR, NOT).
31844 MODE is the machine mode.
31845 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31846 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31847 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31848 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31849 formation of the AND instructions. */
31852 rs6000_split_logical (rtx operands
[3],
31853 enum rtx_code code
,
31854 bool complement_final_p
,
31855 bool complement_op1_p
,
31856 bool complement_op2_p
,
31859 enum machine_mode mode
= GET_MODE (operands
[0]);
31860 enum machine_mode sub_mode
;
31862 int sub_size
, regno0
, regno1
, nregs
, i
;
31864 /* If this is DImode, use the specialized version that can run before
31865 register allocation. */
31866 if (mode
== DImode
&& !TARGET_POWERPC64
)
31868 rs6000_split_logical_di (operands
, code
, complement_final_p
,
31869 complement_op1_p
, complement_op2_p
,
31876 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
31877 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
31878 sub_size
= GET_MODE_SIZE (sub_mode
);
31879 regno0
= REGNO (op0
);
31880 regno1
= REGNO (op1
);
31882 gcc_assert (reload_completed
);
31883 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31884 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31886 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
31887 gcc_assert (nregs
> 1);
31889 if (op2
&& REG_P (op2
))
31890 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31892 for (i
= 0; i
< nregs
; i
++)
31894 int offset
= i
* sub_size
;
31895 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
31896 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
31897 rtx sub_op2
= ((code
== NOT
)
31899 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
31901 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
31902 complement_final_p
, complement_op1_p
,
31903 complement_op2_p
, clobber_reg
);
31910 /* Return true if the peephole2 can combine a load involving a combination of
31911 an addis instruction and a load with an offset that can be fused together on
31915 operands[0] register set with addis
31916 operands[1] value set via addis
31917 operands[2] target register being loaded
31918 operands[3] D-form memory reference using operands[0].
31920 In addition, we are passed a boolean that is true if this is a peephole2,
31921 and we can use see if the addis_reg is dead after the insn and can be
31922 replaced by the target register. */
31925 fusion_gpr_load_p (rtx
*operands
, bool peep2_p
)
31927 rtx addis_reg
= operands
[0];
31928 rtx addis_value
= operands
[1];
31929 rtx target
= operands
[2];
31930 rtx mem
= operands
[3];
31934 /* Validate arguments. */
31935 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
31938 if (!base_reg_operand (target
, GET_MODE (target
)))
31941 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
31944 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
31947 /* Allow sign/zero extension. */
31948 if (GET_CODE (mem
) == ZERO_EXTEND
31949 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
31950 mem
= XEXP (mem
, 0);
31955 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
31956 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
31959 /* Validate that the register used to load the high value is either the
31960 register being loaded, or we can safely replace its use in a peephole2.
31962 If this is a peephole2, we assume that there are 2 instructions in the
31963 peephole (addis and load), so we want to check if the target register was
31964 not used in the memory address and the register to hold the addis result
31965 is dead after the peephole. */
31966 if (REGNO (addis_reg
) != REGNO (target
))
31971 if (reg_mentioned_p (target
, mem
))
31974 if (!peep2_reg_dead_p (2, addis_reg
))
31978 base_reg
= XEXP (addr
, 0);
31979 return REGNO (addis_reg
) == REGNO (base_reg
);
31982 /* During the peephole2 pass, adjust and expand the insns for a load fusion
31983 sequence. We adjust the addis register to use the target register. If the
31984 load sign extends, we adjust the code to do the zero extending load, and an
31985 explicit sign extension later since the fusion only covers zero extending
31989 operands[0] register set with addis (to be replaced with target)
31990 operands[1] value set via addis
31991 operands[2] target register being loaded
31992 operands[3] D-form memory reference using operands[0]. */
31995 expand_fusion_gpr_load (rtx
*operands
)
31997 rtx addis_value
= operands
[1];
31998 rtx target
= operands
[2];
31999 rtx orig_mem
= operands
[3];
32000 rtx new_addr
, new_mem
, orig_addr
, offset
;
32001 enum rtx_code plus_or_lo_sum
;
32002 enum machine_mode target_mode
= GET_MODE (target
);
32003 enum machine_mode extend_mode
= target_mode
;
32004 enum machine_mode ptr_mode
= Pmode
;
32005 enum rtx_code extend
= UNKNOWN
;
32006 rtx addis_reg
= ((ptr_mode
== target_mode
)
32008 : simplify_subreg (ptr_mode
, target
, target_mode
, 0));
32010 if (GET_CODE (orig_mem
) == ZERO_EXTEND
32011 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
32013 extend
= GET_CODE (orig_mem
);
32014 orig_mem
= XEXP (orig_mem
, 0);
32015 target_mode
= GET_MODE (orig_mem
);
32018 gcc_assert (MEM_P (orig_mem
));
32020 orig_addr
= XEXP (orig_mem
, 0);
32021 plus_or_lo_sum
= GET_CODE (orig_addr
);
32022 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
32024 offset
= XEXP (orig_addr
, 1);
32025 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_reg
, offset
);
32026 new_mem
= change_address (orig_mem
, target_mode
, new_addr
);
32028 if (extend
!= UNKNOWN
)
32029 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
32031 emit_insn (gen_rtx_SET (VOIDmode
, addis_reg
, addis_value
));
32032 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
32034 if (extend
== SIGN_EXTEND
)
32036 int sub_off
= ((BYTES_BIG_ENDIAN
)
32037 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
32040 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
32042 emit_insn (gen_rtx_SET (VOIDmode
, target
,
32043 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
32049 /* Return a string to fuse an addis instruction with a gpr load to the same
32050 register that we loaded up the addis instruction. The code is complicated,
32051 so we call output_asm_insn directly, and just return "".
32054 operands[0] register set with addis (must be same reg as target).
32055 operands[1] value set via addis
32056 operands[2] target register being loaded
32057 operands[3] D-form memory reference using operands[0]. */
32060 emit_fusion_gpr_load (rtx
*operands
)
32062 rtx addis_reg
= operands
[0];
32063 rtx addis_value
= operands
[1];
32064 rtx target
= operands
[2];
32065 rtx mem
= operands
[3];
32069 const char *addis_str
= NULL
;
32070 const char *load_str
= NULL
;
32071 const char *extend_insn
= NULL
;
32072 const char *mode_name
= NULL
;
32073 char insn_template
[80];
32074 enum machine_mode mode
;
32075 const char *comment_str
= ASM_COMMENT_START
;
32076 bool sign_p
= false;
32078 gcc_assert (REG_P (addis_reg
) && REG_P (target
));
32079 gcc_assert (REGNO (addis_reg
) == REGNO (target
));
32081 if (*comment_str
== ' ')
32084 /* Allow sign/zero extension. */
32085 if (GET_CODE (mem
) == ZERO_EXTEND
)
32086 mem
= XEXP (mem
, 0);
32088 else if (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
)
32091 mem
= XEXP (mem
, 0);
32094 gcc_assert (MEM_P (mem
));
32095 addr
= XEXP (mem
, 0);
32096 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32097 gcc_unreachable ();
32099 load_offset
= XEXP (addr
, 1);
32101 /* Now emit the load instruction to the same register. */
32102 mode
= GET_MODE (mem
);
32106 mode_name
= "char";
32108 extend_insn
= "extsb %0,%0";
32112 mode_name
= "short";
32114 extend_insn
= "extsh %0,%0";
32120 extend_insn
= "extsw %0,%0";
32124 if (TARGET_POWERPC64
)
32126 mode_name
= "long";
32130 gcc_unreachable ();
32134 gcc_unreachable ();
32137 /* Emit the addis instruction. */
32138 fuse_ops
[0] = target
;
32139 if (satisfies_constraint_L (addis_value
))
32141 fuse_ops
[1] = addis_value
;
32142 addis_str
= "lis %0,%v1";
32145 else if (GET_CODE (addis_value
) == PLUS
)
32147 rtx op0
= XEXP (addis_value
, 0);
32148 rtx op1
= XEXP (addis_value
, 1);
32150 if (REG_P (op0
) && CONST_INT_P (op1
)
32151 && satisfies_constraint_L (op1
))
32155 addis_str
= "addis %0,%1,%v2";
32159 else if (GET_CODE (addis_value
) == HIGH
)
32161 rtx value
= XEXP (addis_value
, 0);
32162 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
32164 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
32165 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
32167 addis_str
= "addis %0,%2,%1@toc@ha";
32169 else if (TARGET_XCOFF
)
32170 addis_str
= "addis %0,%1@u(%2)";
32173 gcc_unreachable ();
32176 else if (GET_CODE (value
) == PLUS
)
32178 rtx op0
= XEXP (value
, 0);
32179 rtx op1
= XEXP (value
, 1);
32181 if (GET_CODE (op0
) == UNSPEC
32182 && XINT (op0
, 1) == UNSPEC_TOCREL
32183 && CONST_INT_P (op1
))
32185 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
32186 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
32189 addis_str
= "addis %0,%2,%1+%3@toc@ha";
32191 else if (TARGET_XCOFF
)
32192 addis_str
= "addis %0,%1+%3@u(%2)";
32195 gcc_unreachable ();
32199 else if (satisfies_constraint_L (value
))
32201 fuse_ops
[1] = value
;
32202 addis_str
= "lis %0,%v1";
32205 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
32207 fuse_ops
[1] = value
;
32208 addis_str
= "lis %0,%1@ha";
32213 fatal_insn ("Could not generate addis value for fusion", addis_value
);
32215 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
32216 comment_str
, mode_name
);
32217 output_asm_insn (insn_template
, fuse_ops
);
32219 /* Emit the D-form load instruction. */
32220 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
32222 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
32223 fuse_ops
[1] = load_offset
;
32224 output_asm_insn (insn_template
, fuse_ops
);
32227 else if (GET_CODE (load_offset
) == UNSPEC
32228 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
32231 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
32233 else if (TARGET_XCOFF
)
32234 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32237 gcc_unreachable ();
32239 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
32240 output_asm_insn (insn_template
, fuse_ops
);
32243 else if (GET_CODE (load_offset
) == PLUS
32244 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
32245 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
32246 && CONST_INT_P (XEXP (load_offset
, 1)))
32248 rtx tocrel_unspec
= XEXP (load_offset
, 0);
32250 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
32252 else if (TARGET_XCOFF
)
32253 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
32256 gcc_unreachable ();
32258 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
32259 fuse_ops
[2] = XEXP (load_offset
, 1);
32260 output_asm_insn (insn_template
, fuse_ops
);
32263 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
32265 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32267 fuse_ops
[1] = load_offset
;
32268 output_asm_insn (insn_template
, fuse_ops
);
32272 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
32274 /* Handle sign extension. The peephole2 pass generates this as a separate
32275 insn, but we handle it just in case it got reattached. */
32278 gcc_assert (extend_insn
!= NULL
);
32279 output_asm_insn (extend_insn
, fuse_ops
);
32286 struct gcc_target targetm
= TARGET_INITIALIZER
;
32288 #include "gt-rs6000.h"