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1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS has a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The SPARC always has a branch delay slot, but its effects can be
43 annulled when the branch is not taken. This means that failing to
44 find other sources of insns, we can hoist an insn from the branch
45 target that would only be safe to execute knowing that the branch
46 is taken.
48 The HP-PA always has a branch delay slot. For unconditional branches
49 its effects can be annulled when the branch is taken. The effects
50 of the delay slot in a conditional branch can be nullified for forward
51 taken branches, or for untaken backward branches. This means
52 we can hoist insns from the fall-through path for forward branches or
53 steal insns from the target of backward branches.
55 The TMS320C3x and C4x have three branch delay slots. When the three
56 slots are filled, the branch penalty is zero. Most insns can fill the
57 delay slots except jump insns.
59 Three techniques for filling delay slots have been implemented so far:
61 (1) `fill_simple_delay_slots' is the simplest, most efficient way
62 to fill delay slots. This pass first looks for insns which come
63 from before the branch and which are safe to execute after the
64 branch. Then it searches after the insn requiring delay slots or,
65 in the case of a branch, for insns that are after the point at
66 which the branch merges into the fallthrough code, if such a point
67 exists. When such insns are found, the branch penalty decreases
68 and no code expansion takes place.
70 (2) `fill_eager_delay_slots' is more complicated: it is used for
71 scheduling conditional jumps, or for scheduling jumps which cannot
72 be filled using (1). A machine need not have annulled jumps to use
73 this strategy, but it helps (by keeping more options open).
74 `fill_eager_delay_slots' tries to guess the direction the branch
75 will go; if it guesses right 100% of the time, it can reduce the
76 branch penalty as much as `fill_simple_delay_slots' does. If it
77 guesses wrong 100% of the time, it might as well schedule nops. When
78 `fill_eager_delay_slots' takes insns from the fall-through path of
79 the jump, usually there is no code expansion; when it takes insns
80 from the branch target, there is code expansion if it is not the
81 only way to reach that target.
83 (3) `relax_delay_slots' uses a set of rules to simplify code that
84 has been reorganized by (1) and (2). It finds cases where
85 conditional test can be eliminated, jumps can be threaded, extra
86 insns can be eliminated, etc. It is the job of (1) and (2) to do a
87 good job of scheduling locally; `relax_delay_slots' takes care of
88 making the various individual schedules work well together. It is
89 especially tuned to handle the control flow interactions of branch
90 insns. It does nothing for insns with delay slots that do not
91 branch.
93 On machines that use CC0, we are very conservative. We will not make
94 a copy of an insn involving CC0 since we want to maintain a 1-1
95 correspondence between the insn that sets and uses CC0. The insns are
96 allowed to be separated by placing an insn that sets CC0 (but not an insn
97 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
98 delay slot. In that case, we point each insn at the other with REG_CC_USER
99 and REG_CC_SETTER notes. Note that these restrictions affect very few
100 machines because most RISC machines with delay slots will not use CC0
101 (the RT is the only known exception at this point). */
121 \f
122 /* First, some functions that were used before GCC got a control flow graph.
123 These functions are now only used here in reorg.c, and have therefore
124 been moved here to avoid inadvertent misuse elsewhere in the compiler. */
126 /* Return the last label to mark the same position as LABEL. Return LABEL
127 itself if it is null or any return rtx. */
129 static rtx
131 {
144 }
146 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
147 and REG_CC_USER notes so we can find it. */
149 static void
151 {
159 }
160 \f
161 /* Insns which have delay slots that have not yet been filled. */
166 /* Define macros to refer to the first and last slot containing unfilled
167 insns. These are used because the list may move and its address
168 should be recomputed at each use. */
170 #define unfilled_slots_base \
171 ((rtx_insn **) obstack_base (&unfilled_slots_obstack))
173 #define unfilled_slots_next \
174 ((rtx_insn **) obstack_next_free (&unfilled_slots_obstack))
176 /* Points to the label before the end of the function, or before a
177 return insn. */
179 /* Likewise for a simple_return. */
182 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
183 not always monotonically increase. */
186 /* Highest valid index in `uid_to_ruid'. */
214 rtx *);
236 \f
237 /* A wrapper around next_active_insn which takes care to return ret_rtx
238 unchanged. */
240 static rtx
242 {
246 }
247 \f
248 /* Return true iff INSN is a simplejump, or any kind of return insn. */
250 static bool
252 {
256 }
257 \f
258 /* Return TRUE if this insn should stop the search for insn to fill delay
259 slots. LABELS_P indicates that labels should terminate the search.
260 In all cases, jumps terminate the search. */
262 static int
264 {
268 /* If the insn can throw an exception that is caught within the function,
269 it may effectively perform a jump from the viewpoint of the function.
270 Therefore act like for a jump. */
275 {
288 /* OK unless it contains a delay slot or is an `asm' insn of some type.
289 We don't know anything about these. */
296 }
297 }
298 \f
299 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
300 resource set contains a volatile memory reference. Otherwise, return FALSE. */
302 static int
304 {
310 }
312 /* Return TRUE if any resource marked in RES, a `struct resources', is
313 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
314 routine is using those resources.
316 We compute this by computing all the resources referenced by INSN and
317 seeing if this conflicts with RES. It might be faster to directly check
318 ourselves, and this is the way it used to work, but it means duplicating
319 a large block of complex code. */
321 static int
324 {
330 }
332 /* Return TRUE if INSN modifies resources that are marked in RES.
333 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
334 included. CC0 is only modified if it is explicitly set; see comments
335 in front of mark_set_resources for details. */
337 static int
340 {
345 (include_delayed_effects
346 ? MARK_SRC_DEST_CALL
349 }
350 \f
351 /* Find a label at the end of the function or before a RETURN. If there
352 is none, try to make one. If that fails, returns 0.
354 The property of such a label is that it is placed just before the
355 epilogue or a bare RETURN insn, so that another bare RETURN can be
356 turned into a jump to the label unconditionally. In particular, the
357 label cannot be placed before a RETURN insn with a filled delay slot.
359 ??? There may be a problem with the current implementation. Suppose
360 we start with a bare RETURN insn and call find_end_label. It may set
361 function_return_label just before the RETURN. Suppose the machinery
362 is able to fill the delay slot of the RETURN insn afterwards. Then
363 function_return_label is no longer valid according to the property
364 described above and find_end_label will still return it unmodified.
365 Note that this is probably mitigated by the following observation:
366 once function_return_label is made, it is very likely the target of
367 a jump, so filling the delay slot of the RETURN will be much more
368 difficult.
369 KIND is either simple_return_rtx or ret_rtx, indicating which type of
370 return we're looking for. */
374 {
380 else
381 {
384 }
386 /* If we found one previously, return it. */
390 /* Otherwise, see if there is a label at the end of the function. If there
391 is, it must be that RETURN insns aren't needed, so that is our return
392 label and we don't have to do anything else. */
401 /* When a target threads its epilogue we might already have a
402 suitable return insn. If so put a label before it for the
403 function_return_label. */
407 {
412 /* Put the label before any USE insns that may precede the RETURN
413 insn. */
419 }
423 else
424 {
427 /* If the basic block reorder pass moves the return insn to
428 some other place try to locate it again and put our
429 function_return_label there. */
433 {
436 /* Put the label before any USE insns that may precede the
437 RETURN insn. */
442 }
443 else
444 {
446 /* The RETURN insn has its delay slot filled so we cannot
447 emit the label just before it. Since we already have
448 an epilogue and cannot emit a new RETURN, we cannot
449 emit the label at all. */
452 /* Otherwise, make a new label and emit a RETURN and BARRIER,
453 if needed. */
456 {
457 /* The return we make may have delay slots too. */
464 }
465 }
467 }
469 /* Show one additional use for this label so it won't go away until
470 we are done. */
474 }
475 \f
476 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
477 the pattern of INSN with the SEQUENCE.
479 Returns the insn containing the SEQUENCE that replaces INSN. */
483 {
484 /* Allocate the rtvec to hold the insns and the SEQUENCE. */
489 /* If DELAY_INSN has a location, use it for SEQ_INSN. If DELAY_INSN does
490 not have a location, but one of the delayed insns does, we pick up a
491 location from there later. */
494 /* Unlink INSN from the insn chain, so that we can put it into
495 the SEQUENCE. Remember where we want to emit SEQUENCE in AFTER. */
500 /* Build our SEQUENCE and rebuild the insn chain. */
507 {
511 /* Show that this copy of the insn isn't deleted. */
514 /* Unlink insn from its original place, and re-emit it into
515 the sequence. */
519 /* SPARC assembler, for instance, emit warning when debug info is output
520 into the delay slot. */
526 {
529 {
531 /* Remove any REG_DEAD notes because we can't rely on them now
532 that the insn has been moved. */
538 /* Keep the label reference count up to date. */
545 }
546 }
547 }
550 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
554 }
556 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
557 be in the order in which the insns are to be executed. */
559 static void
561 {
562 /* If INSN has its block number recorded, clear it since we may
563 be moving the insn to a new block. */
566 }
567 \f
568 /* Delete INSN from the delay slot of the insn that it is in, which may
569 produce an insn with no delay slots. Return the new insn. */
573 {
579 /* We first must find the insn containing the SEQUENCE with INSN in its
580 delay slot. Do this by finding an insn, TRIAL, where
581 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
586 ;
594 /* Create a delay list consisting of all the insns other than the one
595 we are deleting (unless we were the only one). */
602 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
603 list, and rebuild the delay list if non-empty. */
609 /* If there was a barrier after the old SEQUENCE, remit it. */
613 /* If there are any delay insns, remit them. Otherwise clear the
614 annul flag. */
622 /* Show we need to fill this insn again. */
626 }
627 \f
628 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
629 the insn that sets CC0 for it and delete it too. */
631 static void
633 {
634 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
635 delete the insn that sets the condition code, but it is hard to find it.
636 Since this case is rare anyway, don't bother trying; there would likely
637 be other insns that became dead anyway, which we wouldn't know to
638 delete. */
641 {
644 /* If a reg-note was found, it points to an insn to set CC0. This
645 insn is in the delay list of some other insn. So delete it from
646 the delay list it was in. */
648 {
652 }
653 else
654 {
655 /* The insn setting CC0 is our previous insn, but it may be in
656 a delay slot. It will be the last insn in the delay slot, if
657 it is. */
666 else
668 }
669 }
672 }
673 \f
674 /* Counters for delay-slot filling. */
676 #define NUM_REORG_FUNCTIONS 2
677 #define MAX_DELAY_HISTOGRAM 3
678 #define MAX_REORG_PASSES 2
686 static void
688 {
693 }
694 \f
695 /* Optimize the following cases:
697 1. When a conditional branch skips over only one instruction,
698 use an annulling branch and put that insn in the delay slot.
699 Use either a branch that annuls when the condition if true or
700 invert the test with a branch that annuls when the condition is
701 false. This saves insns, since otherwise we must copy an insn
702 from the L1 target.
704 (orig) (skip) (otherwise)
705 Bcc.n L1 Bcc',a L1 Bcc,a L1'
706 insn insn insn2
707 L1: L1: L1:
708 insn2 insn2 insn2
709 insn3 insn3 L1':
710 insn3
712 2. When a conditional branch skips over only one instruction,
713 and after that, it unconditionally branches somewhere else,
714 perform the similar optimization. This saves executing the
715 second branch in the case where the inverted condition is true.
717 Bcc.n L1 Bcc',a L2
718 insn insn
719 L1: L1:
720 Bra L2 Bra L2
722 INSN is a JUMP_INSN.
724 This should be expanded to skip over N insns, where N is the number
725 of delay slots required. */
727 static void
729 {
745 /* There are two cases where we are just executing one insn (we assume
746 here that a branch requires only one insn; this should be generalized
747 at some point): Where the branch goes around a single insn or where
748 we have one insn followed by a branch to the same label we branch to.
749 In both of these cases, inverting the jump and annulling the delay
750 slot give the same effect in fewer insns. */
755 {
757 {
762 }
769 /* Also, if we are targeting an unconditional
770 branch, thread our jump to the target of that branch. Don't
771 change this into a RETURN here, because it may not accept what
772 we have in the delay slot. We'll fix this up later. */
774 {
780 {
781 /* Recompute the flags based on TARGET_LABEL since threading
782 the jump to TARGET_LABEL may change the direction of the
783 jump (which may change the circumstances in which the
784 delay slot is nullified). */
788 }
789 }
792 }
793 }
794 \f
795 /* Encode and return branch direction and prediction information for
796 INSN assuming it will jump to LABEL.
798 Non conditional branches return no direction information and
799 are predicted as very likely taken. */
801 static int
803 {
806 /* get_jump_flags can be passed any insn with delay slots, these may
807 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
808 direction information, and only if they are conditional jumps.
810 If LABEL is a return, then there is no way to determine the branch
811 direction. */
817 flags
820 /* No valid direction information. */
821 else
825 }
827 /* Return truth value of the statement that this branch
828 is mostly taken. If we think that the branch is extremely likely
829 to be taken, we return 2. If the branch is slightly more likely to be
830 taken, return 1. If the branch is slightly less likely to be taken,
831 return 0 and if the branch is highly unlikely to be taken, return -1. */
833 static int
835 {
836 /* If branch probabilities are available, then use that number since it
837 always gives a correct answer. */
840 {
849 else
851 }
853 /* If there is no note, assume branches are not taken.
854 This should be rare. */
856 }
858 /* Return the condition under which INSN will branch to TARGET. If TARGET
859 is zero, return the condition under which INSN will return. If INSN is
860 an unconditional branch, return const_true_rtx. If INSN isn't a simple
861 type of jump, or it doesn't go to TARGET, return 0. */
863 static rtx
865 {
867 rtx src;
894 {
901 }
904 }
906 /* Return nonzero if CONDITION is more strict than the condition of
907 INSN, i.e., if INSN will always branch if CONDITION is true. */
909 static int
911 {
930 }
932 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
933 any insns already in the delay slot of JUMP. */
935 static int
937 {
941 /* Make sure all the delay slots of this jump would still
942 be valid after threading the jump. If they are still
943 valid, then return nonzero. */
948 #if ANNUL_IFFALSE_SLOTS
952 #endif
953 #if ANNUL_IFTRUE_SLOTS
957 #endif
962 }
964 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
965 any insns we wish to place in the delay slot of JUMP. */
967 static int
970 {
971 /* Make sure all the insns in DELAY_LIST would still be
972 valid after threading the jump. If they are still
973 valid, then return nonzero. */
980 #if ANNUL_IFFALSE_SLOTS
984 #endif
985 #if ANNUL_IFTRUE_SLOTS
989 #endif
994 }
996 /* DELAY_LIST is a list of insns that have already been placed into delay
997 slots. See if all of them have the same annulling status as ANNUL_TRUE_P.
998 If not, return 0; otherwise return 1. */
1000 static int
1003 {
1012 }
1013 \f
1014 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1015 the condition tested by INSN is CONDITION and the resources shown in
1016 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1017 from SEQ's delay list, in addition to whatever insns it may execute
1018 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1019 needed while searching for delay slot insns. Return the concatenated
1020 delay list if possible, otherwise, return 0.
1022 SLOTS_TO_FILL is the total number of slots required by INSN, and
1023 PSLOTS_FILLED points to the number filled so far (also the number of
1024 insns in DELAY_LIST). It is updated with the number that have been
1025 filled from the SEQUENCE, if any.
1027 PANNUL_P points to a nonzero value if we already know that we need
1028 to annul INSN. If this routine determines that annulling is needed,
1029 it may set that value nonzero.
1031 PNEW_THREAD points to a location that is to receive the place at which
1032 execution should continue. */
1034 static void
1041 {
1051 /* We can't do anything if there are more delay slots in SEQ than we
1052 can handle, or if we don't know that it will be a taken branch.
1053 We know that it will be a taken branch if it is either an unconditional
1054 branch or a conditional branch with a stricter branch condition.
1056 Also, exit if the branch has more than one set, since then it is computing
1057 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1058 ??? It may be possible to move other sets into INSN in addition to
1059 moving the instructions in the delay slots.
1061 We can not steal the delay list if one of the instructions in the
1062 current delay_list modifies the condition codes and the jump in the
1063 sequence is a conditional jump. We can not do this because we can
1064 not change the direction of the jump because the condition codes
1065 will effect the direction of the jump in the sequence. */
1071 {
1075 }
1082 /* On some targets, branches with delay slots can have a limited
1083 displacement. Give the back end a chance to tell us we can't do
1084 this. */
1090 {
1097 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1098 delay list. */
1100 /* If TRIAL is from the fallthrough code of an annulled branch insn
1101 in SEQ, we cannot use it. */
1106 /* If this insn was already done (usually in a previous delay slot),
1107 pretend we put it in our delay slot. */
1112 /* We will end up re-vectoring this branch, so compute flags
1113 based on jumping to the new label. */
1127 {
1133 total_slots_filled++;
1137 }
1138 else
1140 }
1142 /* Record the effect of the instructions that were redundant and which
1143 we therefore decided not to copy. */
1148 /* Show the place to which we will be branching. */
1151 /* Add any new insns to the delay list and update the count of the
1152 number of slots filled. */
1160 }
1161 \f
1162 /* Similar to steal_delay_list_from_target except that SEQ is on the
1163 fallthrough path of INSN. Here we only do something if the delay insn
1164 of SEQ is an unconditional branch. In that case we steal its delay slot
1165 for INSN since unconditional branches are much easier to fill. */
1167 static void
1176 {
1184 /* We can't do anything if SEQ's delay insn isn't an
1185 unconditional branch. */
1191 {
1194 /* If TRIAL sets CC0, stealing it will move it too far from the use
1195 of CC0. */
1203 /* If this insn was already done, we don't need it. */
1205 {
1209 }
1219 {
1227 }
1228 else
1230 }
1234 }
1235 \f
1236 /* Try merging insns starting at THREAD which match exactly the insns in
1237 INSN's delay list.
1239 If all insns were matched and the insn was previously annulling, the
1240 annul bit will be cleared.
1242 For each insn that is merged, if the branch is or will be non-annulling,
1243 we delete the merged insn. */
1245 static void
1247 {
1264 /* If this is not an annulling branch, take into account anything needed in
1265 INSN's delay slot. This prevents two increments from being incorrectly
1266 folded into one. If we are annulling, this would be the correct
1267 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1268 will essentially disable this optimization. This method is somewhat of
1269 a kludge, but I don't see a better way.) */
1277 {
1283 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1289 /* We can't share an insn that sets cc0. */
1295 /* Update next_trial, in case try_split succeeded. */
1297 /* Likewise THREAD. */
1300 /* Have to test this condition if annul condition is different
1301 from (and less restrictive than) non-annulling one. */
1303 {
1306 {
1313 }
1314 else
1321 }
1325 }
1327 /* See if we stopped on a filled insn. If we did, try to see if its
1328 delay slots match. */
1334 {
1338 /* Account for resources set/needed by the filled insn. */
1343 {
1347 /* Account for resources set by the insn following NEXT_TO_MATCH
1348 inside INSN's delay list. */
1352 /* Account for resources set by the insn before DTRIAL and inside
1353 TRIAL's delay list. */
1362 /* Check that DTRIAL and NEXT_TO_MATCH does not reference a
1363 resource modified between them (only dtrial is checked because
1364 next_to_match and dtrial shall to be equal in order to hit
1365 this line) */
1368 {
1370 {
1378 }
1379 else
1381 merged_insns);
1387 }
1388 else
1389 {
1390 /* Keep track of the set/referenced resources for the delay
1391 slots of any trial insns we encounter. */
1394 }
1395 }
1396 }
1398 /* If all insns in the delay slot have been matched and we were previously
1399 annulling the branch, we need not any more. In that case delete all the
1400 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn in
1401 the delay list so that we know that it isn't only being used at the
1402 target. */
1404 {
1406 {
1408 {
1415 }
1416 else
1417 {
1420 }
1421 }
1427 }
1428 }
1429 \f
1430 /* See if INSN is redundant with an insn in front of TARGET. Often this
1431 is called when INSN is a candidate for a delay slot of TARGET.
1432 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1433 of INSN. Often INSN will be redundant with an insn in a delay slot of
1434 some previous insn. This happens when we have a series of branches to the
1435 same label; in that case the first insn at the target might want to go
1436 into each of the delay slots.
1438 If we are not careful, this routine can take up a significant fraction
1439 of the total compilation time (4%), but only wins rarely. Hence we
1440 speed this routine up by making two passes. The first pass goes back
1441 until it hits a label and sees if it finds an insn with an identical
1442 pattern. Only in this (relatively rare) event does it check for
1443 data conflicts.
1445 We do not split insns we encounter. This could cause us not to find a
1446 redundant insn, but the cost of splitting seems greater than the possible
1447 gain in rare cases. */
1449 static rtx
1451 {
1455 rtx pat;
1460 /* If INSN has any REG_UNUSED notes, it can't match anything since we
1461 are allowed to not actually assign to such a register. */
1465 /* Scan backwards looking for a match. */
1470 {
1471 /* (use (insn))s can come immediately after a barrier if the
1472 label that used to precede them has been deleted as dead.
1473 See delete_related_insns. */
1486 {
1487 /* Stop for a CALL and its delay slots because it is difficult to
1488 track its resource needs correctly. */
1492 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1493 slots because it is difficult to track its resource needs
1494 correctly. */
1502 /* See if any of the insns in the delay slot match, updating
1503 resource requirements as we go. */
1510 /* If found a match, exit this loop early. */
1513 }
1518 }
1520 /* If we didn't find an insn that matches, return 0. */
1524 /* See what resources this insn sets and needs. If they overlap, or
1525 if this insn references CC0, it can't be redundant. */
1532 /* If TARGET is a SEQUENCE, get the main insn. */
1538 /* The insn requiring the delay may not set anything needed or set by
1539 INSN. */
1544 /* Insns we pass may not set either NEEDED or SET, so merge them for
1545 simpler tests. */
1549 /* This insn isn't redundant if it conflicts with an insn that either is
1550 or will be in a delay slot of TARGET. */
1564 /* Scan backwards until we reach a label or an insn that uses something
1565 INSN sets or sets something insn uses or sets. */
1571 {
1581 {
1585 /* If this is a CALL_INSN and its delay slots, it is hard to track
1586 the resource needs properly, so give up. */
1590 /* If this is an INSN or JUMP_INSN with delayed effects, it
1591 is hard to track the resource needs properly, so give up. */
1602 /* See if any of the insns in the delay slot match, updating
1603 resource requirements as we go. */
1605 {
1608 /* If an insn will be annulled if the branch is false, it isn't
1609 considered as a possible duplicate insn. */
1612 {
1613 /* Show that this insn will be used in the sequel. */
1616 }
1618 /* Unless this is an annulled insn from the target of a branch,
1619 we must stop if it sets anything needed or set by INSN. */
1623 }
1625 /* If the insn requiring the delay slot conflicts with INSN, we
1626 must stop. */
1629 }
1630 else
1631 {
1632 /* See if TRIAL is the same as INSN. */
1637 /* Can't go any further if TRIAL conflicts with INSN. */
1640 }
1641 }
1644 }
1645 \f
1646 /* Return 1 if THREAD can only be executed in one way. If LABEL is nonzero,
1647 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
1648 is nonzero, we are allowed to fall into this thread; otherwise, we are
1649 not.
1651 If LABEL is used more than one or we pass a label other than LABEL before
1652 finding an active insn, we do not own this thread. */
1654 static int
1656 {
1660 /* We don't own the function end. */
1664 /* We have a non-NULL insn. */
1667 /* Get the first active insn, or THREAD_INSN, if it is an active insn. */
1678 /* Ensure that we reach a BARRIER before any insn or label. */
1690 }
1691 \f
1692 /* Called when INSN is being moved from a location near the target of a jump.
1693 We leave a marker of the form (use (INSN)) immediately in front
1694 of WHERE for mark_target_live_regs. These markers will be deleted when
1695 reorg finishes.
1697 We used to try to update the live status of registers if WHERE is at
1698 the start of a basic block, but that can't work since we may remove a
1699 BARRIER in relax_delay_slots. */
1701 static void
1703 {
1704 /* Ignore if this was in a delay slot and it came from the target of
1705 a branch. */
1711 /* INSN might be making a value live in a block where it didn't use to
1712 be. So recompute liveness information for this block. */
1715 }
1717 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
1718 the basic block containing the jump. */
1720 static int
1722 {
1725 }
1727 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
1728 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
1729 that reference values used in INSN. If we find one, then we move the
1730 REG_DEAD note to INSN.
1732 This is needed to handle the case where a later insn (after INSN) has a
1733 REG_DEAD note for a register used by INSN, and this later insn subsequently
1734 gets moved before a CODE_LABEL because it is a redundant insn. In this
1735 case, mark_target_live_regs may be confused into thinking the register
1736 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
1738 static void
1740 {
1747 {
1755 {
1756 /* Move the REG_DEAD note from P to INSN. */
1760 }
1761 }
1762 }
1764 /* Called when an insn redundant with start_insn is deleted. If there
1765 is a REG_DEAD note for the target of start_insn between start_insn
1766 and stop_insn, then the REG_DEAD note needs to be deleted since the
1767 value no longer dies there.
1769 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
1770 confused into thinking the register is dead. */
1772 static void
1774 {
1781 {
1789 {
1792 }
1793 }
1794 }
1796 /* Delete any REG_UNUSED notes that exist on INSN but not on REDUNDANT_INSN.
1798 This handles the case of udivmodXi4 instructions which optimize their
1799 output depending on whether any REG_UNUSED notes are present.
1800 we must make sure that INSN calculates as many results as REDUNDANT_INSN
1801 does. */
1803 static void
1805 {
1809 {
1819 }
1820 }
1821 \f
1824 /* Return the label before INSN, or put a new label there. If SIBLING is
1825 non-zero, it is another label associated with the new label (if any),
1826 typically the former target of the jump that will be redirected to
1827 the new label. */
1831 {
1834 /* Find an existing label at this point
1835 or make a new one if there is none. */
1839 {
1846 {
1849 }
1850 }
1852 }
1854 /* Scan a function looking for insns that need a delay slot and find insns to
1855 put into the delay slot.
1857 NON_JUMPS_P is nonzero if we are to only try to fill non-jump insns (such
1858 as calls). We do these first since we don't want jump insns (that are
1859 easier to fill) to get the only insns that could be used for non-jump insns.
1860 When it is zero, only try to fill JUMP_INSNs.
1862 When slots are filled in this manner, the insns (including the
1863 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
1864 it is possible to tell whether a delay slot has really been filled
1865 or not. `final' knows how to deal with this, by communicating
1866 through FINAL_SEQUENCE. */
1868 static void
1870 {
1872 rtx pat;
1880 {
1882 /* Get the next insn to fill. If it has already had any slots assigned,
1883 we can't do anything with it. Maybe we'll improve this later. */
1894 /* It may have been that this insn used to need delay slots, but
1895 now doesn't; ignore in that case. This can happen, for example,
1896 on the HP PA RISC, where the number of delay slots depends on
1897 what insns are nearby. */
1900 /* Some machine description have defined instructions to have
1901 delay slots only in certain circumstances which may depend on
1902 nearby insns (which change due to reorg's actions).
1904 For example, the PA port normally has delay slots for unconditional
1905 jumps.
1907 However, the PA port claims such jumps do not have a delay slot
1908 if they are immediate successors of certain CALL_INSNs. This
1909 allows the port to favor filling the delay slot of the call with
1910 the unconditional jump. */
1914 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
1915 says how many. After initialization, first try optimizing
1917 call _foo call _foo
1918 nop add %o7,.-L1,%o7
1919 b,a L1
1920 nop
1922 If this case applies, the delay slot of the call is filled with
1923 the unconditional jump. This is done first to avoid having the
1924 delay slot of the call filled in the backward scan. Also, since
1925 the unconditional jump is likely to also have a delay slot, that
1926 insn must exist when it is subsequently scanned.
1928 This is tried on each insn with delay slots as some machines
1929 have insns which perform calls, but are not represented as
1930 CALL_INSNs. */
1937 else
1946 {
1948 slots_filled++;
1951 /* TRIAL may have had its delay slot filled, then unfilled. When
1952 the delay slot is unfilled, TRIAL is placed back on the unfilled
1953 slots obstack. Unfortunately, it is placed on the end of the
1954 obstack, not in its original location. Therefore, we must search
1955 from entry i + 1 to the end of the unfilled slots obstack to
1956 try and find TRIAL. */
1959 tmp++;
1961 /* Remove the unconditional jump from consideration for delay slot
1962 filling and unthread it. */
1965 {
1972 }
1973 }
1975 /* Now, scan backwards from the insn to search for a potential
1976 delay-slot candidate. Stop searching when a label or jump is hit.
1978 For each candidate, if it is to go into the delay slot (moved
1979 forward in execution sequence), it must not need or set any resources
1980 that were set by later insns and must not set any resources that
1981 are needed for those insns.
1983 The delay slot insn itself sets resources unless it is a call
1984 (in which case the called routine, not the insn itself, is doing
1985 the setting). */
1988 {
1989 /* If the flags register is dead after the insn, then we want to be
1990 able to accept a candidate that clobbers it. For this purpose,
1991 we need to filter the flags register during life analysis, so
1992 that it doesn't create RAW and WAW dependencies, while still
1993 creating the necessary WAR dependencies. */
1994 bool filter_flags
2003 {
2006 }
2011 {
2014 /* This must be an INSN or CALL_INSN. */
2017 /* Stand-alone USE and CLOBBER are just for flow. */
2021 /* Check for resource conflict first, to avoid unnecessary
2022 splitting. */
2028 /* Can't separate set of cc0 from its use. */
2031 {
2035 {
2036 /* In this case, we are searching backward, so if we
2037 find insns to put on the delay list, we want
2038 to put them at the head, rather than the
2039 tail, of the list. */
2048 }
2049 }
2053 {
2055 /* If the flags register is set, then it doesn't create RAW
2056 dependencies any longer and it also doesn't create WAW
2057 dependencies since it's dead after the original insn. */
2059 {
2062 }
2063 }
2065 }
2066 }
2068 /* If all needed slots haven't been filled, we come here. */
2070 /* Try to optimize case of jumping around a single insn. */
2077 {
2081 }
2083 /* Try to get insns from beyond the insn needing the delay slot.
2084 These insns can neither set or reference resources set in insns being
2085 skipped, cannot set resources in the insn being skipped, and, if this
2086 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2087 call might not return).
2089 There used to be code which continued past the target label if
2090 we saw all uses of the target label. This code did not work,
2091 because it failed to account for some instructions which were
2092 both annulled and marked as from the target. This can happen as a
2093 result of optimize_skip. Since this code was redundant with
2094 fill_eager_delay_slots anyways, it was just deleted. */
2097 /* If this instruction could throw an exception which is
2098 caught in the same function, then it's not safe to fill
2099 the delay slot with an instruction from beyond this
2100 point. For example, consider:
2102 int i = 2;
2104 try {
2105 f();
2106 i = 3;
2107 } catch (...) {}
2109 return i;
2111 Even though `i' is a local variable, we must be sure not
2112 to put `i = 3' in the delay slot if `f' might throw an
2113 exception.
2115 Presumably, we should also check to see if we could get
2116 back to this function via `setjmp'. */
2119 {
2133 {
2136 /* This must be an INSN or CALL_INSN. */
2139 /* Stand-alone USE and CLOBBER are just for flow. */
2143 /* If this already has filled delay slots, get the insn needing
2144 the delay slots. */
2147 else
2150 /* Stop our search when seeing a jump. */
2154 /* See if we have a resource problem before we try to split. */
2164 {
2174 }
2179 /* Ensure we don't put insns between the setting of cc and the
2180 comparison by moving a setting of cc into an earlier delay
2181 slot since these insns could clobber the condition code. */
2184 /* If this is a call, we might not get here. */
2187 }
2189 /* If there are slots left to fill and our search was stopped by an
2190 unconditional branch, try the insn at the branch target. We can
2191 redirect the branch if it works.
2193 Don't do this if the insn at the branch target is a branch. */
2195 && trial
2210 {
2211 /* See comment in relax_delay_slots about necessity of using
2212 next_real_insn here. */
2217 else
2221 {
2224 slots_filled++;
2226 new_label);
2227 }
2228 }
2229 }
2231 /* If this is an unconditional jump, then try to get insns from the
2232 target of the jump. */
2251 }
2252 }
2253 \f
2254 /* Follow any unconditional jump at LABEL, for the purpose of redirecting JUMP;
2255 return the ultimate label reached by any such chain of jumps.
2256 Return a suitable return rtx if the chain ultimately leads to a
2257 return instruction.
2258 If LABEL is not followed by a jump, return LABEL.
2259 If the chain loops or we can't find end, return LABEL,
2260 since that tells caller to avoid changing the insn.
2261 If the returned label is obtained by following a crossing jump,
2262 set *CROSSING to true, otherwise set it to false. */
2264 static rtx
2266 {
2286 depth++)
2287 {
2290 /* If we have found a cycle, make the insn jump to itself. */
2294 /* Cannot follow returns and cannot look through tablejumps. */
2308 }
2312 }
2314 /* Try to find insns to place in delay slots.
2316 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
2317 or is an unconditional branch if CONDITION is const_true_rtx.
2318 *PSLOTS_FILLED is updated with the number of slots that we have filled.
2320 THREAD is a flow-of-control, either the insns to be executed if the
2321 branch is true or if the branch is false, THREAD_IF_TRUE says which.
2323 OPPOSITE_THREAD is the thread in the opposite direction. It is used
2324 to see if any potential delay slot insns set things needed there.
2326 LIKELY is nonzero if it is extremely likely that the branch will be
2327 taken and THREAD_IF_TRUE is set. This is used for the branch at the
2328 end of a loop back up to the top.
2330 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
2331 thread. I.e., it is the fallthrough code of our jump or the target of the
2332 jump when we are the only jump going there.
2334 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
2335 case, we can only take insns from the head of the thread for our delay
2336 slot. We then adjust the jump to point after the insns we have taken. */
2338 static void
2343 {
2344 rtx new_thread;
2351 /* Validate our arguments. */
2357 /* If our thread is the end of subroutine, we can't get any delay
2358 insns from that. */
2364 /* If this is an unconditional branch, nothing is needed at the
2365 opposite thread. Otherwise, compute what is needed there. */
2368 else
2371 /* If the insn at THREAD can be split, do it here to avoid having to
2372 update THREAD and NEW_THREAD if it is done in the loop below. Also
2373 initialize NEW_THREAD. */
2377 /* Scan insns at THREAD. We are looking for an insn that can be removed
2378 from THREAD (it neither sets nor references resources that were set
2379 ahead of it and it doesn't set anything needs by the insns ahead of
2380 it) and that either can be placed in an annulling insn or aren't
2381 needed at OPPOSITE_THREAD. */
2386 /* If we do not own this thread, we must stop as soon as we find
2387 something that we can't put in a delay slot, since all we can do
2388 is branch into THREAD at a later point. Therefore, labels stop
2389 the search if this is not the `true' thread. */
2394 {
2397 /* If we have passed a label, we no longer own this thread. */
2399 {
2402 }
2408 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
2409 don't separate or copy insns that set and use CC0. */
2416 {
2417 rtx prior_insn;
2419 /* If TRIAL is redundant with some insn before INSN, we don't
2420 actually need to add it to the delay list; we can merely pretend
2421 we did. */
2423 {
2426 {
2429 {
2433 }
2436 }
2437 else
2438 {
2441 }
2444 }
2446 /* There are two ways we can win: If TRIAL doesn't set anything
2447 needed at the opposite thread and can't trap, or if it can
2448 go into an annulled delay slot. But we want neither to copy
2449 nor to speculate frame-related insns. */
2456 {
2466 }
2470 {
2483 {
2487 winner:
2492 /* If we own this thread, delete the insn. If this is the
2493 destination of a branch, show that a basic block status
2494 may have been updated. In any case, mark the new
2495 starting point of this thread. */
2497 {
2498 rtx note;
2502 {
2506 }
2508 /* We are moving this insn, not deleting it. We must
2509 temporarily increment the use count on any referenced
2510 label lest it be deleted by delete_related_insns. */
2516 {
2517 /* REG_LABEL_OPERAND could be
2518 NOTE_INSN_DELETED_LABEL too. */
2521 else
2524 }
2535 {
2536 /* REG_LABEL_OPERAND could be
2537 NOTE_INSN_DELETED_LABEL too. */
2540 else
2543 }
2546 }
2547 else
2557 {
2558 /* Even though we have filled all the slots, we
2559 may be branching to a location that has a
2560 redundant insn. Skip any if so. */
2567 && (prior_insn
2570 {
2571 /* We know we do not own the thread, so no need
2572 to call update_block and delete_insn. */
2576 }
2578 }
2581 }
2582 }
2583 }
2585 /* This insn can't go into a delay slot. */
2590 /* Ensure we don't put insns between the setting of cc and the comparison
2591 by moving a setting of cc into an earlier delay slot since these insns
2592 could clobber the condition code. */
2595 /* If this insn is a register-register copy and the next insn has
2596 a use of our destination, change it to use our source. That way,
2597 it will become a candidate for our delay slot the next time
2598 through this loop. This case occurs commonly in loops that
2599 scan a list.
2601 We could check for more complex cases than those tested below,
2602 but it doesn't seem worth it. It might also be a good idea to try
2603 to swap the two insns. That might do better.
2605 We can't do this if the next insn modifies our destination, because
2606 that would make the replacement into the insn invalid. We also can't
2607 do this if it modifies our source, because it might be an earlyclobber
2608 operand. This latter test also prevents updating the contents of
2609 a PRE_INC. We also can't do this if there's overlap of source and
2610 destination. Overlap may happen for larger-than-register-size modes. */
2616 {
2626 }
2627 }
2629 /* If we stopped on a branch insn that has delay slots, see if we can
2630 steal some of the insns in those slots. */
2634 {
2636 /* If this is the `true' thread, we will want to follow the jump,
2637 so we can only do this if we have taken everything up to here. */
2639 {
2645 /* If we owned the thread and are told that it branched
2646 elsewhere, make sure we own the thread at the new location. */
2649 }
2655 }
2657 /* If we haven't found anything for this delay slot and it is very
2658 likely that the branch will be taken, see if the insn at our target
2659 increments or decrements a register with an increment that does not
2660 depend on the destination register. If so, try to place the opposite
2661 arithmetic insn after the jump insn and put the arithmetic insn in the
2662 delay slot. If we can't do this, return. */
2669 {
2671 rtx dest;
2672 rtx src;
2674 /* We know "new_thread" is an insn due to NONJUMP_INSN_P (new_thread)
2675 above. */
2692 {
2694 rtx new_arith;
2697 /* If this is a constant adjustment, use the same code with
2698 the negated constant. Otherwise, reverse the sense of the
2699 arithmetic. */
2703 else
2712 {
2715 }
2718 {
2721 {
2725 }
2727 }
2728 else
2737 }
2738 }
2743 /* If we are to branch into the middle of this thread, find an appropriate
2744 label or make a new one if none, and redirect INSN to it. If we hit the
2745 end of the function, use the end-of-function label. */
2747 {
2748 rtx label;
2764 else
2769 {
2773 }
2774 }
2775 }
2776 \f
2777 /* Make another attempt to find insns to place in delay slots.
2779 We previously looked for insns located in front of the delay insn
2780 and, for non-jump delay insns, located behind the delay insn.
2782 Here only try to schedule jump insns and try to move insns from either
2783 the target or the following insns into the delay slot. If annulling is
2784 supported, we will be likely to do this. Otherwise, we can do this only
2785 if safe. */
2787 static void
2789 {
2795 {
2796 rtx condition;
2813 /* Some machine description have defined instructions to have
2814 delay slots only in certain circumstances which may depend on
2815 nearby insns (which change due to reorg's actions).
2817 For example, the PA port normally has delay slots for unconditional
2818 jumps.
2820 However, the PA port claims such jumps do not have a delay slot
2821 if they are immediate successors of certain CALL_INSNs. This
2822 allows the port to favor filling the delay slot of the call with
2823 the unconditional jump. */
2834 /* Get the next active fallthrough and target insns and see if we own
2835 them. Then see whether the branch is likely true. We don't need
2836 to do a lot of this for unconditional branches. */
2842 {
2846 }
2847 else
2848 {
2852 }
2854 /* If this insn is expected to branch, first try to get insns from our
2855 target, then our fallthrough insns. If it is not expected to branch,
2856 try the other order. */
2859 {
2862 own_target,
2866 {
2867 /* Even though we didn't find anything for delay slots,
2868 we might have found a redundant insn which we deleted
2869 from the thread that was filled. So we have to recompute
2870 the next insn at the target. */
2878 }
2879 }
2880 else
2881 {
2891 }
2901 }
2902 }
2903 \f
2906 /* Recursively delete prior insns that compute the value (used only by INSN
2907 which the caller is deleting) stored in the register mentioned by NOTE
2908 which is a REG_DEAD note associated with INSN. */
2910 static void
2912 {
2913 rtx our_prev;
2920 {
2923 /* If we reach a CALL which is not calling a const function
2924 or the callee pops the arguments, then give up. */
2930 /* If we reach a SEQUENCE, it is too complex to try to
2931 do anything with it, so give up. We can be run during
2932 and after reorg, so SEQUENCE rtl can legitimately show
2933 up here. */
2939 /* reorg creates USEs that look like this. We leave them
2940 alone because reorg needs them for its own purposes. */
2944 {
2949 {
2950 /* If we find a SET of something else, we can't
2951 delete the insn. */
2956 {
2962 }
2966 }
2969 {
2979 /* We may have a multi-word hard register and some, but not
2980 all, of the words of the register are needed in subsequent
2981 insns. Write REG_UNUSED notes for those parts that were not
2982 needed. */
2985 {
2996 }
2997 }
3000 }
3002 /* If PAT references the register that dies here, it is an
3003 additional use. Hence any prior SET isn't dead. However, this
3004 insn becomes the new place for the REG_DEAD note. */
3006 {
3010 }
3011 }
3012 }
3014 /* Delete INSN and recursively delete insns that compute values used only
3015 by INSN. This uses the REG_DEAD notes computed during flow analysis.
3017 Look at all our REG_DEAD notes. If a previous insn does nothing other
3018 than set a register that dies in this insn, we can delete that insn
3019 as well.
3021 On machines with CC0, if CC0 is used in this insn, we may be able to
3022 delete the insn that set it. */
3024 static void
3026 {
3030 {
3032 /* We assume that at this stage
3033 CC's are always set explicitly
3034 and always immediately before the jump that
3035 will use them. So if the previous insn
3036 exists to set the CC's, delete it
3037 (unless it performs auto-increments, etc.). */
3040 {
3044 else
3045 /* Otherwise, show that cc0 won't be used. */
3047 }
3048 }
3051 {
3055 /* Verify that the REG_NOTE is legitimate. */
3060 }
3063 }
3065 /* If all INSN does is set the pc, delete it,
3066 and delete the insn that set the condition codes for it
3067 if that's what the previous thing was. */
3069 static void
3071 {
3076 }
3080 {
3083 {
3089 }
3091 }
3093 /* Return TRUE if there is a NOTE_INSN_SWITCH_TEXT_SECTIONS note in between
3094 BEG and END. */
3096 static bool
3098 {
3104 }
3106 \f
3107 /* Once we have tried two ways to fill a delay slot, make a pass over the
3108 code to try to improve the results and to do such things as more jump
3109 threading. */
3111 static void
3113 {
3116 rtx trial;
3118 rtx target_label;
3120 /* Look at every JUMP_INSN and see if we can improve it. */
3122 {
3128 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3129 the next insn, or jumps to a label that is not the last of a
3130 group of consecutive labels. */
3134 {
3136 target_label
3145 {
3148 }
3151 {
3155 }
3157 /* See if this jump conditionally branches around an unconditional
3158 jump. If so, invert this jump and point it to the target of the
3159 second jump. Check if it's possible on the target. */
3162 && target_label
3166 {
3169 /* Be careful how we do this to avoid deleting code or
3170 labels that are momentarily dead. See similar optimization
3171 in jump.c.
3173 We also need to ensure we properly handle the case when
3174 invert_jump fails. */
3181 {
3184 }
3193 }
3194 }
3196 /* If this is an unconditional jump and the previous insn is a
3197 conditional jump, try reversing the condition of the previous
3198 insn and swapping our targets. The next pass might be able to
3199 fill the slots.
3201 Don't do this if we expect the conditional branch to be true, because
3202 we would then be making the more common case longer. */
3209 {
3215 }
3217 /* Now look only at cases where we have a filled delay slot. */
3224 /* See if the first insn in the delay slot is redundant with some
3225 previous insn. Remove it from the delay slot if so; then set up
3226 to reprocess this insn. */
3228 {
3233 }
3235 /* See if we have a RETURN insn with a filled delay slot followed
3236 by a RETURN insn with an unfilled a delay slot. If so, we can delete
3237 the first RETURN (but not its delay insn). This gives the same
3238 effect in fewer instructions.
3240 Only do so if optimizing for size since this results in slower, but
3241 smaller code. */
3244 && next
3247 {
3251 /* Delete the RETURN and just execute the delay list insns.
3253 We do this by deleting the INSN containing the SEQUENCE, then
3254 re-emitting the insns separately, and then deleting the RETURN.
3255 This allows the count of the jump target to be properly
3256 decremented.
3258 Note that we need to change the INSN_UID of the re-emitted insns
3259 since it is used to hash the insns for mark_target_live_regs and
3260 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3262 Clear the from target bit, since these insns are no longer
3263 in delay slots. */
3276 }
3278 /* Now look only at the cases where we have a filled JUMP_INSN. */
3289 /* If this jump goes to another unconditional jump, thread it, but
3290 don't convert a jump into a RETURN here. */
3292 delay_jump_insn,
3299 {
3304 }
3306 /* If the first insn at TARGET_LABEL is redundant with a previous
3307 insn, redirect the jump to the following insn and process again.
3308 We use next_real_insn instead of next_active_insn so we
3309 don't skip USE-markers, or we'll end up with incorrect
3310 liveness info. */
3315 {
3316 /* Figure out where to emit the special USE insn so we don't
3317 later incorrectly compute register live/death info. */
3323 {
3324 /* Insert the special USE insn and update dataflow info.
3325 We know "trial" is an insn here as it is the output of
3326 next_real_insn () above. */
3329 /* Now emit a label before the special USE insn, and
3330 redirect our jump to the new label. */
3335 }
3336 }
3338 /* Similarly, if it is an unconditional jump with one insn in its
3339 delay list and that insn is redundant, thread the jump. */
3347 {
3355 {
3360 }
3361 }
3363 /* See if we have a simple (conditional) jump that is useless. */
3368 /* If the last insn in the delay slot sets CC0 for some insn,
3369 various code assumes that it is in a delay slot. We could
3370 put it back where it belonged and delete the register notes,
3371 but it doesn't seem worthwhile in this uncommon case. */
3372 && (!HAVE_cc0
3375 {
3379 /* All this insn does is execute its delay list and jump to the
3380 following insn. So delete the jump and just execute the delay
3381 list insns.
3383 We do this by deleting the INSN containing the SEQUENCE, then
3384 re-emitting the insns separately, and then deleting the jump.
3385 This allows the count of the jump target to be properly
3386 decremented.
3388 Note that we need to change the INSN_UID of the re-emitted insns
3389 since it is used to hash the insns for mark_target_live_regs and
3390 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3392 Clear the from target bit, since these insns are no longer
3393 in delay slots. */
3406 }
3408 /* See if this is an unconditional jump around a single insn which is
3409 identical to the one in its delay slot. In this case, we can just
3410 delete the branch and the insn in its delay slot. */
3416 {
3419 }
3421 /* See if this jump (with its delay slots) conditionally branches
3422 around an unconditional jump (without delay slots). If so, invert
3423 this jump and point it to the target of the second jump. We cannot
3424 do this for annulled jumps, though. Again, don't convert a jump to
3425 a RETURN here. */
3431 {
3438 /* find_end_label can generate a new label. Check this first. */
3443 {
3444 /* Be careful how we do this to avoid deleting code or labels
3445 that are momentarily dead. See similar optimization in
3446 jump.c */
3451 {
3454 /* Must update the INSN_FROM_TARGET_P bits now that
3455 the branch is reversed, so that mark_target_live_regs
3456 will handle the delay slot insn correctly. */
3458 {
3461 }
3465 }
3470 }
3471 }
3473 /* If we own the thread opposite the way this insn branches, see if we
3474 can merge its delay slots with following insns. */
3482 /* If we get here, we haven't deleted INSN. But we may have deleted
3483 NEXT, so recompute it. */
3485 }
3486 }
3487 \f
3489 /* Look for filled jumps to the end of function label. We can try to convert
3490 them into RETURN insns if the insns in the delay slot are valid for the
3491 RETURN as well. */
3493 static void
3495 {
3502 /* See if there is a RETURN insn in the function other than the one we
3503 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3504 into a RETURN to jump to it. */
3507 {
3511 else
3514 }
3516 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3517 was equal to END_OF_FUNCTION_LABEL. */
3523 /* Clear the list of insns to fill so we can use it. */
3527 {
3531 /* Only look at filled JUMP_INSNs that go to the end of function
3532 label. */
3545 {
3548 }
3550 {
3553 }
3554 else
3559 /* If we can't make the jump into a RETURN, try to redirect it to the best
3560 RETURN and go on to the next insn. */
3562 {
3563 /* Make sure redirecting the jump will not invalidate the delay
3564 slot insns. */
3568 }
3570 /* See if this RETURN can accept the insns current in its delay slot.
3571 It can if it has more or an equal number of slots and the contents
3572 of each is valid. */
3577 {
3580 #if ANNUL_IFFALSE_SLOTS
3585 #endif
3586 #if ANNUL_IFTRUE_SLOTS
3591 #endif
3595 }
3596 else
3602 /* We have to do something with this insn. If it is an unconditional
3603 RETURN, delete the SEQUENCE and output the individual insns,
3604 followed by the RETURN. Then set things up so we try to find
3605 insns for its delay slots, if it needs some. */
3607 {
3619 }
3620 else
3621 /* It is probably more efficient to keep this with its current
3622 delay slot as a branch to a RETURN. */
3624 }
3626 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3627 new delay slots we have created. */
3636 }
3637 \f
3638 /* Try to find insns to place in delay slots. */
3640 static void
3642 {
3647 /* If the current function has no insns other than the prologue and
3648 epilogue, then do not try to fill any delay slots. */
3652 /* Find the highest INSN_UID and allocate and initialize our map from
3653 INSN_UID's to position in code. */
3655 {
3661 }
3667 /* Initialize the list of insns that need filling. */
3669 {
3672 }
3675 {
3676 rtx target;
3678 /* Skip vector tables. We can't get attributes for them. */
3689 /* Ensure all jumps go to the last of a set of consecutive labels. */
3696 }
3700 /* Show we haven't computed an end-of-function label yet. */
3703 /* Initialize the statistics for this function. */
3707 /* Now do the delay slot filling. Try everything twice in case earlier
3708 changes make more slots fillable. */
3712 reorg_pass_number++)
3713 {
3719 }
3721 /* If we made an end of function label, indicate that it is now
3722 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
3723 If it is now unused, delete it. */
3737 /* Delete any USE insns made by update_block; subsequent passes don't need
3738 them or know how to deal with them. */
3740 {
3746 }
3750 /* It is not clear why the line below is needed, but it does seem to be. */
3754 {
3761 reorg_pass_number++)
3762 {
3765 {
3774 {
3780 }
3782 }
3783 }
3787 {
3792 {
3794 {
3795 rtx control;
3802 else
3804 }
3807 }
3808 }
3812 {
3814 {
3819 }
3820 }
3824 {
3828 {
3830 {
3835 }
3836 }
3838 }
3841 }
3844 {
3847 }
3852 }
3853 \f
3854 /* Run delay slot optimization. */
3855 static unsigned int
3857 {
3862 }
3867 {
3877 };
3880 {
3884 {}
3886 /* opt_pass methods: */
3889 {
3891 }
3895 bool
3897 {
3898 /* At -O0 dataflow info isn't updated after RA. */
3903 }
3907 rtl_opt_pass *
3909 {
3911 }
3913 /* Machine dependent reorg pass. */
3918 {
3928 };
3931 {
3935 {}
3937 /* opt_pass methods: */
3939 {
3941 }
3944 {
3947 }
3953 rtl_opt_pass *
3955 {
3957 }