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re PR target/31975 (segfault in try_split on mips during bootstrap)
[official-gcc.git] / gcc / config / mips / mips.c
blobddab40c1ffef32082c43d2e459cf0deff7cc72ce
1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
25
26 #include "config.h"
27 #include "system.h"
28 #include "coretypes.h"
29 #include "tm.h"
30 #include <signal.h>
31 #include "rtl.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "output.h"
41 #include "tree.h"
42 #include "function.h"
43 #include "expr.h"
44 #include "optabs.h"
45 #include "flags.h"
46 #include "reload.h"
47 #include "tm_p.h"
48 #include "ggc.h"
49 #include "gstab.h"
50 #include "hashtab.h"
51 #include "debug.h"
52 #include "target.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
59 #include "bitmap.h"
60
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
69 XVECEXP (X, 0, 0)
70
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
77
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
81
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
85
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
88 (INSN_P (INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
93
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
99 : (INSN))
100
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
105 : (INSN))
106
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
113
114 /* Classifies an address.
115
116 ADDRESS_REG
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
119
120 ADDRESS_LO_SUM
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
123
124 ADDRESS_CONST_INT
125 A signed 16-bit constant address.
126
127 ADDRESS_SYMBOLIC:
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
130 ADDRESS_REG,
131 ADDRESS_LO_SUM,
132 ADDRESS_CONST_INT,
133 ADDRESS_SYMBOLIC
134 };
135
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
138 {
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
148 MIPS_SF_FTYPE_V2SF,
149 MIPS_SF_FTYPE_SF,
150 MIPS_SF_FTYPE_SF_SF,
151 MIPS_DF_FTYPE_DF,
152 MIPS_DF_FTYPE_DF_DF,
153
154 /* For MIPS DSP ASE */
155 MIPS_DI_FTYPE_DI_SI,
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
159 MIPS_SI_FTYPE_DI_SI,
160 MIPS_SI_FTYPE_PTR_SI,
161 MIPS_SI_FTYPE_SI,
162 MIPS_SI_FTYPE_SI_SI,
163 MIPS_SI_FTYPE_V2HI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
165 MIPS_SI_FTYPE_V4QI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
167 MIPS_SI_FTYPE_VOID,
168 MIPS_V2HI_FTYPE_SI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
175 MIPS_V4QI_FTYPE_SI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
182
183 /* For MIPS DSP REV 2 ASE. */
184 MIPS_V4QI_FTYPE_V4QI,
185 MIPS_SI_FTYPE_SI_SI_SI,
186 MIPS_DI_FTYPE_DI_USI_USI,
187 MIPS_DI_FTYPE_SI_SI,
188 MIPS_DI_FTYPE_USI_USI,
189 MIPS_V2HI_FTYPE_SI_SI_SI,
190
191 /* The last type. */
192 MIPS_MAX_FTYPE_MAX
193 };
194
195 /* Specifies how a builtin function should be converted into rtl. */
196 enum mips_builtin_type
197 {
198 /* The builtin corresponds directly to an .md pattern. The return
199 value is mapped to operand 0 and the arguments are mapped to
200 operands 1 and above. */
201 MIPS_BUILTIN_DIRECT,
202
203 /* The builtin corresponds directly to an .md pattern. There is no return
204 value and the arguments are mapped to operands 0 and above. */
205 MIPS_BUILTIN_DIRECT_NO_TARGET,
206
207 /* The builtin corresponds to a comparison instruction followed by
208 a mips_cond_move_tf_ps pattern. The first two arguments are the
209 values to compare and the second two arguments are the vector
210 operands for the movt.ps or movf.ps instruction (in assembly order). */
211 MIPS_BUILTIN_MOVF,
212 MIPS_BUILTIN_MOVT,
213
214 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
215 of this instruction is the result of the comparison, which has mode
216 CCV2 or CCV4. The function arguments are mapped to operands 1 and
217 above. The function's return value is an SImode boolean that is
218 true under the following conditions:
219
220 MIPS_BUILTIN_CMP_ANY: one of the registers is true
221 MIPS_BUILTIN_CMP_ALL: all of the registers are true
222 MIPS_BUILTIN_CMP_LOWER: the first register is true
223 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
224 MIPS_BUILTIN_CMP_ANY,
225 MIPS_BUILTIN_CMP_ALL,
226 MIPS_BUILTIN_CMP_UPPER,
227 MIPS_BUILTIN_CMP_LOWER,
228
229 /* As above, but the instruction only sets a single $fcc register. */
230 MIPS_BUILTIN_CMP_SINGLE,
231
232 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
233 MIPS_BUILTIN_BPOSGE32
234 };
235
236 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
237 #define MIPS_FP_CONDITIONS(MACRO) \
238 MACRO (f), \
239 MACRO (un), \
240 MACRO (eq), \
241 MACRO (ueq), \
242 MACRO (olt), \
243 MACRO (ult), \
244 MACRO (ole), \
245 MACRO (ule), \
246 MACRO (sf), \
247 MACRO (ngle), \
248 MACRO (seq), \
249 MACRO (ngl), \
250 MACRO (lt), \
251 MACRO (nge), \
252 MACRO (le), \
253 MACRO (ngt)
254
255 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
256 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
257 enum mips_fp_condition {
258 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
259 };
260
261 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
262 #define STRINGIFY(X) #X
263 static const char *const mips_fp_conditions[] = {
264 MIPS_FP_CONDITIONS (STRINGIFY)
265 };
266
267 /* A function to save or store a register. The first argument is the
268 register and the second is the stack slot. */
269 typedef void (*mips_save_restore_fn) (rtx, rtx);
270
271 struct mips16_constant;
272 struct mips_arg_info;
273 struct mips_address_info;
274 struct mips_integer_op;
275 struct mips_sim;
276
277 static enum mips_symbol_type mips_classify_symbol (rtx);
278 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
279 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
280 static bool mips_classify_address (struct mips_address_info *, rtx,
281 enum machine_mode, int);
282 static bool mips_cannot_force_const_mem (rtx);
283 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
284 static int mips_symbol_insns (enum mips_symbol_type);
285 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
286 static rtx mips_force_temporary (rtx, rtx);
287 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
288 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
289 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
290 static unsigned int mips_build_lower (struct mips_integer_op *,
291 unsigned HOST_WIDE_INT);
292 static unsigned int mips_build_integer (struct mips_integer_op *,
293 unsigned HOST_WIDE_INT);
294 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
295 static int m16_check_op (rtx, int, int, int);
296 static bool mips_rtx_costs (rtx, int, int, int *);
297 static int mips_address_cost (rtx);
298 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
299 static void mips_load_call_address (rtx, rtx, int);
300 static bool mips_function_ok_for_sibcall (tree, tree);
301 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
302 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
303 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
304 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
305 tree, int, struct mips_arg_info *);
306 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
307 static void mips_set_architecture (const struct mips_cpu_info *);
308 static void mips_set_tune (const struct mips_cpu_info *);
309 static bool mips_handle_option (size_t, const char *, int);
310 static struct machine_function *mips_init_machine_status (void);
311 static void print_operand_reloc (FILE *, rtx, const char **);
312 static void mips_file_start (void);
313 static bool mips_rewrite_small_data_p (rtx);
314 static int mips_small_data_pattern_1 (rtx *, void *);
315 static int mips_rewrite_small_data_1 (rtx *, void *);
316 static bool mips_function_has_gp_insn (void);
317 static unsigned int mips_global_pointer (void);
318 static bool mips_save_reg_p (unsigned int);
319 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
320 mips_save_restore_fn);
321 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
322 static void mips_output_cplocal (void);
323 static void mips_emit_loadgp (void);
324 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
325 static void mips_set_frame_expr (rtx);
326 static rtx mips_frame_set (rtx, rtx);
327 static void mips_save_reg (rtx, rtx);
328 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
329 static void mips_restore_reg (rtx, rtx);
330 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
331 HOST_WIDE_INT, tree);
332 static int symbolic_expression_p (rtx);
333 static section *mips_select_rtx_section (enum machine_mode, rtx,
334 unsigned HOST_WIDE_INT);
335 static section *mips_function_rodata_section (tree);
336 static bool mips_in_small_data_p (tree);
337 static bool mips_use_anchors_for_symbol_p (rtx);
338 static int mips_fpr_return_fields (tree, tree *);
339 static bool mips_return_in_msb (tree);
340 static rtx mips_return_fpr_pair (enum machine_mode mode,
341 enum machine_mode mode1, HOST_WIDE_INT,
342 enum machine_mode mode2, HOST_WIDE_INT);
343 static rtx mips16_gp_pseudo_reg (void);
344 static void mips16_fp_args (FILE *, int, int);
345 static void build_mips16_function_stub (FILE *);
346 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
347 static void dump_constants (struct mips16_constant *, rtx);
348 static int mips16_insn_length (rtx);
349 static int mips16_rewrite_pool_refs (rtx *, void *);
350 static void mips16_lay_out_constants (void);
351 static void mips_sim_reset (struct mips_sim *);
352 static void mips_sim_init (struct mips_sim *, state_t);
353 static void mips_sim_next_cycle (struct mips_sim *);
354 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
355 static int mips_sim_wait_regs_2 (rtx *, void *);
356 static void mips_sim_wait_regs_1 (rtx *, void *);
357 static void mips_sim_wait_regs (struct mips_sim *, rtx);
358 static void mips_sim_wait_units (struct mips_sim *, rtx);
359 static void mips_sim_wait_insn (struct mips_sim *, rtx);
360 static void mips_sim_record_set (rtx, rtx, void *);
361 static void mips_sim_issue_insn (struct mips_sim *, rtx);
362 static void mips_sim_issue_nop (struct mips_sim *);
363 static void mips_sim_finish_insn (struct mips_sim *, rtx);
364 static void vr4130_avoid_branch_rt_conflict (rtx);
365 static void vr4130_align_insns (void);
366 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
367 static void mips_avoid_hazards (void);
368 static void mips_reorg (void);
369 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
370 static bool mips_matching_cpu_name_p (const char *, const char *);
371 static const struct mips_cpu_info *mips_parse_cpu (const char *);
372 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
373 static bool mips_return_in_memory (tree, tree);
374 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
375 static void mips_macc_chains_record (rtx);
376 static void mips_macc_chains_reorder (rtx *, int);
377 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
378 static bool vr4130_true_reg_dependence_p (rtx);
379 static bool vr4130_swap_insns_p (rtx, rtx);
380 static void vr4130_reorder (rtx *, int);
381 static void mips_promote_ready (rtx *, int, int);
382 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
383 static int mips_variable_issue (FILE *, int, rtx, int);
384 static int mips_adjust_cost (rtx, rtx, rtx, int);
385 static int mips_issue_rate (void);
386 static int mips_multipass_dfa_lookahead (void);
387 static void mips_init_libfuncs (void);
388 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
389 tree, int *, int);
390 static tree mips_build_builtin_va_list (void);
391 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
392 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
393 tree, bool);
394 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
395 tree, bool);
396 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
397 tree, bool);
398 static bool mips_valid_pointer_mode (enum machine_mode);
399 static bool mips_vector_mode_supported_p (enum machine_mode);
400 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
401 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
402 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
403 static void mips_init_builtins (void);
404 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
405 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
406 enum insn_code, enum mips_fp_condition,
407 rtx, tree);
408 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
409 enum insn_code, enum mips_fp_condition,
410 rtx, tree);
411 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
412 static void mips_encode_section_info (tree, rtx, int);
413 static void mips_extra_live_on_entry (bitmap);
414 static int mips_comp_type_attributes (tree, tree);
415 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
416 static bool mips_offset_within_alignment_p (rtx, HOST_WIDE_INT);
417
418 /* Structure to be filled in by compute_frame_size with register
419 save masks, and offsets for the current function. */
420
421 struct mips_frame_info GTY(())
422 {
423 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
424 HOST_WIDE_INT var_size; /* # bytes that variables take up */
425 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
426 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
427 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
428 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
429 unsigned int mask; /* mask of saved gp registers */
430 unsigned int fmask; /* mask of saved fp registers */
431 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
432 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
433 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
434 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
435 bool initialized; /* true if frame size already calculated */
436 int num_gp; /* number of gp registers saved */
437 int num_fp; /* number of fp registers saved */
438 };
439
440 struct machine_function GTY(()) {
441 /* Pseudo-reg holding the value of $28 in a mips16 function which
442 refers to GP relative global variables. */
443 rtx mips16_gp_pseudo_rtx;
444
445 /* The number of extra stack bytes taken up by register varargs.
446 This area is allocated by the callee at the very top of the frame. */
447 int varargs_size;
448
449 /* Current frame information, calculated by compute_frame_size. */
450 struct mips_frame_info frame;
451
452 /* The register to use as the global pointer within this function. */
453 unsigned int global_pointer;
454
455 /* True if mips_adjust_insn_length should ignore an instruction's
456 hazard attribute. */
457 bool ignore_hazard_length_p;
458
459 /* True if the whole function is suitable for .set noreorder and
460 .set nomacro. */
461 bool all_noreorder_p;
462
463 /* True if the function is known to have an instruction that needs $gp. */
464 bool has_gp_insn_p;
465 };
466
467 /* Information about a single argument. */
468 struct mips_arg_info
469 {
470 /* True if the argument is passed in a floating-point register, or
471 would have been if we hadn't run out of registers. */
472 bool fpr_p;
473
474 /* The number of words passed in registers, rounded up. */
475 unsigned int reg_words;
476
477 /* For EABI, the offset of the first register from GP_ARG_FIRST or
478 FP_ARG_FIRST. For other ABIs, the offset of the first register from
479 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
480 comment for details).
481
482 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
483 on the stack. */
484 unsigned int reg_offset;
485
486 /* The number of words that must be passed on the stack, rounded up. */
487 unsigned int stack_words;
488
489 /* The offset from the start of the stack overflow area of the argument's
490 first stack word. Only meaningful when STACK_WORDS is nonzero. */
491 unsigned int stack_offset;
492 };
493
494
495 /* Information about an address described by mips_address_type.
496
497 ADDRESS_CONST_INT
498 No fields are used.
499
500 ADDRESS_REG
501 REG is the base register and OFFSET is the constant offset.
502
503 ADDRESS_LO_SUM
504 REG is the register that contains the high part of the address,
505 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
506 is the type of OFFSET's symbol.
507
508 ADDRESS_SYMBOLIC
509 SYMBOL_TYPE is the type of symbol being referenced. */
510
511 struct mips_address_info
512 {
513 enum mips_address_type type;
514 rtx reg;
515 rtx offset;
516 enum mips_symbol_type symbol_type;
517 };
518
519
520 /* One stage in a constant building sequence. These sequences have
521 the form:
522
523 A = VALUE[0]
524 A = A CODE[1] VALUE[1]
525 A = A CODE[2] VALUE[2]
526 ...
527
528 where A is an accumulator, each CODE[i] is a binary rtl operation
529 and each VALUE[i] is a constant integer. */
530 struct mips_integer_op {
531 enum rtx_code code;
532 unsigned HOST_WIDE_INT value;
533 };
534
535
536 /* The largest number of operations needed to load an integer constant.
537 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
538 When the lowest bit is clear, we can try, but reject a sequence with
539 an extra SLL at the end. */
540 #define MIPS_MAX_INTEGER_OPS 7
541
542
543 /* Global variables for machine-dependent things. */
544
545 /* Threshold for data being put into the small data/bss area, instead
546 of the normal data area. */
547 int mips_section_threshold = -1;
548
549 /* Count the number of .file directives, so that .loc is up to date. */
550 int num_source_filenames = 0;
551
552 /* Count the number of sdb related labels are generated (to find block
553 start and end boundaries). */
554 int sdb_label_count = 0;
555
556 /* Next label # for each statement for Silicon Graphics IRIS systems. */
557 int sym_lineno = 0;
558
559 /* Name of the file containing the current function. */
560 const char *current_function_file = "";
561
562 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
563 int set_noreorder;
564 int set_noat;
565 int set_nomacro;
566 int set_volatile;
567
568 /* The next branch instruction is a branch likely, not branch normal. */
569 int mips_branch_likely;
570
571 /* The operands passed to the last cmpMM expander. */
572 rtx cmp_operands[2];
573
574 /* The target cpu for code generation. */
575 enum processor_type mips_arch;
576 const struct mips_cpu_info *mips_arch_info;
577
578 /* The target cpu for optimization and scheduling. */
579 enum processor_type mips_tune;
580 const struct mips_cpu_info *mips_tune_info;
581
582 /* Which instruction set architecture to use. */
583 int mips_isa;
584
585 /* Which ABI to use. */
586 int mips_abi = MIPS_ABI_DEFAULT;
587
588 /* Cost information to use. */
589 const struct mips_rtx_cost_data *mips_cost;
590
591 /* Whether we are generating mips16 hard float code. In mips16 mode
592 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
593 -msoft-float was not specified by the user, which means that we
594 should arrange to call mips32 hard floating point code. */
595 int mips16_hard_float;
596
597 /* The architecture selected by -mipsN. */
598 static const struct mips_cpu_info *mips_isa_info;
599
600 /* If TRUE, we split addresses into their high and low parts in the RTL. */
601 int mips_split_addresses;
602
603 /* Mode used for saving/restoring general purpose registers. */
604 static enum machine_mode gpr_mode;
605
606 /* Array giving truth value on whether or not a given hard register
607 can support a given mode. */
608 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
609
610 /* List of all MIPS punctuation characters used by print_operand. */
611 char mips_print_operand_punct[256];
612
613 /* Map GCC register number to debugger register number. */
614 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
615
616 /* A copy of the original flag_delayed_branch: see override_options. */
617 static int mips_flag_delayed_branch;
618
619 static GTY (()) int mips_output_filename_first_time = 1;
620
621 /* mips_split_p[X] is true if symbols of type X can be split by
622 mips_split_symbol(). */
623 bool mips_split_p[NUM_SYMBOL_TYPES];
624
625 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
626 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
627 if they are matched by a special .md file pattern. */
628 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
629
630 /* Likewise for HIGHs. */
631 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
632
633 /* Map hard register number to register class */
634 const enum reg_class mips_regno_to_class[] =
635 {
636 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
637 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
638 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
639 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
640 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
641 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
642 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
643 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
644 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
645 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
646 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
647 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
648 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
649 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
650 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
651 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
652 HI_REG, LO_REG, NO_REGS, ST_REGS,
653 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
654 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
655 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
656 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
657 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
658 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
659 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
660 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
661 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
662 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
663 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
664 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
665 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
666 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
667 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
668 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
669 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
670 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
671 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
672 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
673 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
674 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
675 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
676 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
677 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
678 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
679 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
680 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
681 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
682 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
683 };
684
685 /* Table of machine dependent attributes. */
686 const struct attribute_spec mips_attribute_table[] =
687 {
688 { "long_call", 0, 0, false, true, true, NULL },
689 { "far", 0, 0, false, true, true, NULL },
690 { "near", 0, 0, false, true, true, NULL },
691 { NULL, 0, 0, false, false, false, NULL }
692 };
693 \f
694 /* A table describing all the processors gcc knows about. Names are
695 matched in the order listed. The first mention of an ISA level is
696 taken as the canonical name for that ISA.
697
698 To ease comparison, please keep this table in the same order as
699 gas's mips_cpu_info_table[]. */
700 const struct mips_cpu_info mips_cpu_info_table[] = {
701 /* Entries for generic ISAs */
702 { "mips1", PROCESSOR_R3000, 1 },
703 { "mips2", PROCESSOR_R6000, 2 },
704 { "mips3", PROCESSOR_R4000, 3 },
705 { "mips4", PROCESSOR_R8000, 4 },
706 { "mips32", PROCESSOR_4KC, 32 },
707 { "mips32r2", PROCESSOR_M4K, 33 },
708 { "mips64", PROCESSOR_5KC, 64 },
709
710 /* MIPS I */
711 { "r3000", PROCESSOR_R3000, 1 },
712 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
713 { "r3900", PROCESSOR_R3900, 1 },
714
715 /* MIPS II */
716 { "r6000", PROCESSOR_R6000, 2 },
717
718 /* MIPS III */
719 { "r4000", PROCESSOR_R4000, 3 },
720 { "vr4100", PROCESSOR_R4100, 3 },
721 { "vr4111", PROCESSOR_R4111, 3 },
722 { "vr4120", PROCESSOR_R4120, 3 },
723 { "vr4130", PROCESSOR_R4130, 3 },
724 { "vr4300", PROCESSOR_R4300, 3 },
725 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
726 { "r4600", PROCESSOR_R4600, 3 },
727 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
728 { "r4650", PROCESSOR_R4650, 3 },
729
730 /* MIPS IV */
731 { "r8000", PROCESSOR_R8000, 4 },
732 { "vr5000", PROCESSOR_R5000, 4 },
733 { "vr5400", PROCESSOR_R5400, 4 },
734 { "vr5500", PROCESSOR_R5500, 4 },
735 { "rm7000", PROCESSOR_R7000, 4 },
736 { "rm9000", PROCESSOR_R9000, 4 },
737
738 /* MIPS32 */
739 { "4kc", PROCESSOR_4KC, 32 },
740 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
741 { "4kp", PROCESSOR_4KP, 32 },
742
743 /* MIPS32 Release 2 */
744 { "m4k", PROCESSOR_M4K, 33 },
745 { "4kec", PROCESSOR_4KC, 33 },
746 { "4kem", PROCESSOR_4KC, 33 },
747 { "4kep", PROCESSOR_4KP, 33 },
748 { "24kc", PROCESSOR_24KC, 33 }, /* 24K no FPU */
749 { "24kf", PROCESSOR_24KF, 33 }, /* 24K 1:2 FPU */
750 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
751 { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
752 { "24kef", PROCESSOR_24KF, 33 },
753 { "24kex", PROCESSOR_24KX, 33 },
754 { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
755 { "34kf", PROCESSOR_24KF, 33 },
756 { "34kx", PROCESSOR_24KX, 33 },
757 { "74kc", PROCESSOR_74KC, 33 },
758 { "74kf", PROCESSOR_74KF, 33 },
759 { "74kx", PROCESSOR_74KX, 33 },
760
761 /* MIPS64 */
762 { "5kc", PROCESSOR_5KC, 64 },
763 { "5kf", PROCESSOR_5KF, 64 },
764 { "20kc", PROCESSOR_20KC, 64 },
765 { "sb1", PROCESSOR_SB1, 64 },
766 { "sb1a", PROCESSOR_SB1A, 64 },
767 { "sr71000", PROCESSOR_SR71000, 64 },
768
769 /* End marker */
770 { 0, 0, 0 }
771 };
772
773 /* Default costs. If these are used for a processor we should look
774 up the actual costs. */
775 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
776 COSTS_N_INSNS (7), /* fp_mult_sf */ \
777 COSTS_N_INSNS (8), /* fp_mult_df */ \
778 COSTS_N_INSNS (23), /* fp_div_sf */ \
779 COSTS_N_INSNS (36), /* fp_div_df */ \
780 COSTS_N_INSNS (10), /* int_mult_si */ \
781 COSTS_N_INSNS (10), /* int_mult_di */ \
782 COSTS_N_INSNS (69), /* int_div_si */ \
783 COSTS_N_INSNS (69), /* int_div_di */ \
784 2, /* branch_cost */ \
785 4 /* memory_latency */
786
787 /* Need to replace these with the costs of calling the appropriate
788 libgcc routine. */
789 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
790 COSTS_N_INSNS (256), /* fp_mult_sf */ \
791 COSTS_N_INSNS (256), /* fp_mult_df */ \
792 COSTS_N_INSNS (256), /* fp_div_sf */ \
793 COSTS_N_INSNS (256) /* fp_div_df */
794
795 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
796 {
797 COSTS_N_INSNS (1), /* fp_add */
798 COSTS_N_INSNS (1), /* fp_mult_sf */
799 COSTS_N_INSNS (1), /* fp_mult_df */
800 COSTS_N_INSNS (1), /* fp_div_sf */
801 COSTS_N_INSNS (1), /* fp_div_df */
802 COSTS_N_INSNS (1), /* int_mult_si */
803 COSTS_N_INSNS (1), /* int_mult_di */
804 COSTS_N_INSNS (1), /* int_div_si */
805 COSTS_N_INSNS (1), /* int_div_di */
806 2, /* branch_cost */
807 4 /* memory_latency */
808 };
809
810 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
811 {
812 { /* R3000 */
813 COSTS_N_INSNS (2), /* fp_add */
814 COSTS_N_INSNS (4), /* fp_mult_sf */
815 COSTS_N_INSNS (5), /* fp_mult_df */
816 COSTS_N_INSNS (12), /* fp_div_sf */
817 COSTS_N_INSNS (19), /* fp_div_df */
818 COSTS_N_INSNS (12), /* int_mult_si */
819 COSTS_N_INSNS (12), /* int_mult_di */
820 COSTS_N_INSNS (35), /* int_div_si */
821 COSTS_N_INSNS (35), /* int_div_di */
822 1, /* branch_cost */
823 4 /* memory_latency */
824
825 },
826 { /* 4KC */
827 SOFT_FP_COSTS,
828 COSTS_N_INSNS (6), /* int_mult_si */
829 COSTS_N_INSNS (6), /* int_mult_di */
830 COSTS_N_INSNS (36), /* int_div_si */
831 COSTS_N_INSNS (36), /* int_div_di */
832 1, /* branch_cost */
833 4 /* memory_latency */
834 },
835 { /* 4KP */
836 SOFT_FP_COSTS,
837 COSTS_N_INSNS (36), /* int_mult_si */
838 COSTS_N_INSNS (36), /* int_mult_di */
839 COSTS_N_INSNS (37), /* int_div_si */
840 COSTS_N_INSNS (37), /* int_div_di */
841 1, /* branch_cost */
842 4 /* memory_latency */
843 },
844 { /* 5KC */
845 SOFT_FP_COSTS,
846 COSTS_N_INSNS (4), /* int_mult_si */
847 COSTS_N_INSNS (11), /* int_mult_di */
848 COSTS_N_INSNS (36), /* int_div_si */
849 COSTS_N_INSNS (68), /* int_div_di */
850 1, /* branch_cost */
851 4 /* memory_latency */
852 },
853 { /* 5KF */
854 COSTS_N_INSNS (4), /* fp_add */
855 COSTS_N_INSNS (4), /* fp_mult_sf */
856 COSTS_N_INSNS (5), /* fp_mult_df */
857 COSTS_N_INSNS (17), /* fp_div_sf */
858 COSTS_N_INSNS (32), /* fp_div_df */
859 COSTS_N_INSNS (4), /* int_mult_si */
860 COSTS_N_INSNS (11), /* int_mult_di */
861 COSTS_N_INSNS (36), /* int_div_si */
862 COSTS_N_INSNS (68), /* int_div_di */
863 1, /* branch_cost */
864 4 /* memory_latency */
865 },
866 { /* 20KC */
867 DEFAULT_COSTS
868 },
869 { /* 24KC */
870 SOFT_FP_COSTS,
871 COSTS_N_INSNS (5), /* int_mult_si */
872 COSTS_N_INSNS (5), /* int_mult_di */
873 COSTS_N_INSNS (41), /* int_div_si */
874 COSTS_N_INSNS (41), /* int_div_di */
875 1, /* branch_cost */
876 4 /* memory_latency */
877 },
878 { /* 24KF */
879 COSTS_N_INSNS (8), /* fp_add */
880 COSTS_N_INSNS (8), /* fp_mult_sf */
881 COSTS_N_INSNS (10), /* fp_mult_df */
882 COSTS_N_INSNS (34), /* fp_div_sf */
883 COSTS_N_INSNS (64), /* fp_div_df */
884 COSTS_N_INSNS (5), /* int_mult_si */
885 COSTS_N_INSNS (5), /* int_mult_di */
886 COSTS_N_INSNS (41), /* int_div_si */
887 COSTS_N_INSNS (41), /* int_div_di */
888 1, /* branch_cost */
889 4 /* memory_latency */
890 },
891 { /* 24KX */
892 COSTS_N_INSNS (4), /* fp_add */
893 COSTS_N_INSNS (4), /* fp_mult_sf */
894 COSTS_N_INSNS (5), /* fp_mult_df */
895 COSTS_N_INSNS (17), /* fp_div_sf */
896 COSTS_N_INSNS (32), /* fp_div_df */
897 COSTS_N_INSNS (5), /* int_mult_si */
898 COSTS_N_INSNS (5), /* int_mult_di */
899 COSTS_N_INSNS (41), /* int_div_si */
900 COSTS_N_INSNS (41), /* int_div_di */
901 1, /* branch_cost */
902 4 /* memory_latency */
903 },
904 { /* 74KC */
905 SOFT_FP_COSTS,
906 COSTS_N_INSNS (5), /* int_mult_si */
907 COSTS_N_INSNS (5), /* int_mult_di */
908 COSTS_N_INSNS (41), /* int_div_si */
909 COSTS_N_INSNS (41), /* int_div_di */
910 1, /* branch_cost */
911 4 /* memory_latency */
912 },
913 { /* 74KF */
914 COSTS_N_INSNS (8), /* fp_add */
915 COSTS_N_INSNS (8), /* fp_mult_sf */
916 COSTS_N_INSNS (10), /* fp_mult_df */
917 COSTS_N_INSNS (34), /* fp_div_sf */
918 COSTS_N_INSNS (64), /* fp_div_df */
919 COSTS_N_INSNS (5), /* int_mult_si */
920 COSTS_N_INSNS (5), /* int_mult_di */
921 COSTS_N_INSNS (41), /* int_div_si */
922 COSTS_N_INSNS (41), /* int_div_di */
923 1, /* branch_cost */
924 4 /* memory_latency */
925 },
926 { /* 74KX */
927 COSTS_N_INSNS (4), /* fp_add */
928 COSTS_N_INSNS (4), /* fp_mult_sf */
929 COSTS_N_INSNS (5), /* fp_mult_df */
930 COSTS_N_INSNS (17), /* fp_div_sf */
931 COSTS_N_INSNS (32), /* fp_div_df */
932 COSTS_N_INSNS (5), /* int_mult_si */
933 COSTS_N_INSNS (5), /* int_mult_di */
934 COSTS_N_INSNS (41), /* int_div_si */
935 COSTS_N_INSNS (41), /* int_div_di */
936 1, /* branch_cost */
937 4 /* memory_latency */
938 },
939 { /* M4k */
940 DEFAULT_COSTS
941 },
942 { /* R3900 */
943 COSTS_N_INSNS (2), /* fp_add */
944 COSTS_N_INSNS (4), /* fp_mult_sf */
945 COSTS_N_INSNS (5), /* fp_mult_df */
946 COSTS_N_INSNS (12), /* fp_div_sf */
947 COSTS_N_INSNS (19), /* fp_div_df */
948 COSTS_N_INSNS (2), /* int_mult_si */
949 COSTS_N_INSNS (2), /* int_mult_di */
950 COSTS_N_INSNS (35), /* int_div_si */
951 COSTS_N_INSNS (35), /* int_div_di */
952 1, /* branch_cost */
953 4 /* memory_latency */
954 },
955 { /* R6000 */
956 COSTS_N_INSNS (3), /* fp_add */
957 COSTS_N_INSNS (5), /* fp_mult_sf */
958 COSTS_N_INSNS (6), /* fp_mult_df */
959 COSTS_N_INSNS (15), /* fp_div_sf */
960 COSTS_N_INSNS (16), /* fp_div_df */
961 COSTS_N_INSNS (17), /* int_mult_si */
962 COSTS_N_INSNS (17), /* int_mult_di */
963 COSTS_N_INSNS (38), /* int_div_si */
964 COSTS_N_INSNS (38), /* int_div_di */
965 2, /* branch_cost */
966 6 /* memory_latency */
967 },
968 { /* R4000 */
969 COSTS_N_INSNS (6), /* fp_add */
970 COSTS_N_INSNS (7), /* fp_mult_sf */
971 COSTS_N_INSNS (8), /* fp_mult_df */
972 COSTS_N_INSNS (23), /* fp_div_sf */
973 COSTS_N_INSNS (36), /* fp_div_df */
974 COSTS_N_INSNS (10), /* int_mult_si */
975 COSTS_N_INSNS (10), /* int_mult_di */
976 COSTS_N_INSNS (69), /* int_div_si */
977 COSTS_N_INSNS (69), /* int_div_di */
978 2, /* branch_cost */
979 6 /* memory_latency */
980 },
981 { /* R4100 */
982 DEFAULT_COSTS
983 },
984 { /* R4111 */
985 DEFAULT_COSTS
986 },
987 { /* R4120 */
988 DEFAULT_COSTS
989 },
990 { /* R4130 */
991 /* The only costs that appear to be updated here are
992 integer multiplication. */
993 SOFT_FP_COSTS,
994 COSTS_N_INSNS (4), /* int_mult_si */
995 COSTS_N_INSNS (6), /* int_mult_di */
996 COSTS_N_INSNS (69), /* int_div_si */
997 COSTS_N_INSNS (69), /* int_div_di */
998 1, /* branch_cost */
999 4 /* memory_latency */
1000 },
1001 { /* R4300 */
1002 DEFAULT_COSTS
1003 },
1004 { /* R4600 */
1005 DEFAULT_COSTS
1006 },
1007 { /* R4650 */
1008 DEFAULT_COSTS
1009 },
1010 { /* R5000 */
1011 COSTS_N_INSNS (6), /* fp_add */
1012 COSTS_N_INSNS (4), /* fp_mult_sf */
1013 COSTS_N_INSNS (5), /* fp_mult_df */
1014 COSTS_N_INSNS (23), /* fp_div_sf */
1015 COSTS_N_INSNS (36), /* fp_div_df */
1016 COSTS_N_INSNS (5), /* int_mult_si */
1017 COSTS_N_INSNS (5), /* int_mult_di */
1018 COSTS_N_INSNS (36), /* int_div_si */
1019 COSTS_N_INSNS (36), /* int_div_di */
1020 1, /* branch_cost */
1021 4 /* memory_latency */
1022 },
1023 { /* R5400 */
1024 COSTS_N_INSNS (6), /* fp_add */
1025 COSTS_N_INSNS (5), /* fp_mult_sf */
1026 COSTS_N_INSNS (6), /* fp_mult_df */
1027 COSTS_N_INSNS (30), /* fp_div_sf */
1028 COSTS_N_INSNS (59), /* fp_div_df */
1029 COSTS_N_INSNS (3), /* int_mult_si */
1030 COSTS_N_INSNS (4), /* int_mult_di */
1031 COSTS_N_INSNS (42), /* int_div_si */
1032 COSTS_N_INSNS (74), /* int_div_di */
1033 1, /* branch_cost */
1034 4 /* memory_latency */
1035 },
1036 { /* R5500 */
1037 COSTS_N_INSNS (6), /* fp_add */
1038 COSTS_N_INSNS (5), /* fp_mult_sf */
1039 COSTS_N_INSNS (6), /* fp_mult_df */
1040 COSTS_N_INSNS (30), /* fp_div_sf */
1041 COSTS_N_INSNS (59), /* fp_div_df */
1042 COSTS_N_INSNS (5), /* int_mult_si */
1043 COSTS_N_INSNS (9), /* int_mult_di */
1044 COSTS_N_INSNS (42), /* int_div_si */
1045 COSTS_N_INSNS (74), /* int_div_di */
1046 1, /* branch_cost */
1047 4 /* memory_latency */
1048 },
1049 { /* R7000 */
1050 /* The only costs that are changed here are
1051 integer multiplication. */
1052 COSTS_N_INSNS (6), /* fp_add */
1053 COSTS_N_INSNS (7), /* fp_mult_sf */
1054 COSTS_N_INSNS (8), /* fp_mult_df */
1055 COSTS_N_INSNS (23), /* fp_div_sf */
1056 COSTS_N_INSNS (36), /* fp_div_df */
1057 COSTS_N_INSNS (5), /* int_mult_si */
1058 COSTS_N_INSNS (9), /* int_mult_di */
1059 COSTS_N_INSNS (69), /* int_div_si */
1060 COSTS_N_INSNS (69), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1063 },
1064 { /* R8000 */
1065 DEFAULT_COSTS
1066 },
1067 { /* R9000 */
1068 /* The only costs that are changed here are
1069 integer multiplication. */
1070 COSTS_N_INSNS (6), /* fp_add */
1071 COSTS_N_INSNS (7), /* fp_mult_sf */
1072 COSTS_N_INSNS (8), /* fp_mult_df */
1073 COSTS_N_INSNS (23), /* fp_div_sf */
1074 COSTS_N_INSNS (36), /* fp_div_df */
1075 COSTS_N_INSNS (3), /* int_mult_si */
1076 COSTS_N_INSNS (8), /* int_mult_di */
1077 COSTS_N_INSNS (69), /* int_div_si */
1078 COSTS_N_INSNS (69), /* int_div_di */
1079 1, /* branch_cost */
1080 4 /* memory_latency */
1081 },
1082 { /* SB1 */
1083 /* These costs are the same as the SB-1A below. */
1084 COSTS_N_INSNS (4), /* fp_add */
1085 COSTS_N_INSNS (4), /* fp_mult_sf */
1086 COSTS_N_INSNS (4), /* fp_mult_df */
1087 COSTS_N_INSNS (24), /* fp_div_sf */
1088 COSTS_N_INSNS (32), /* fp_div_df */
1089 COSTS_N_INSNS (3), /* int_mult_si */
1090 COSTS_N_INSNS (4), /* int_mult_di */
1091 COSTS_N_INSNS (36), /* int_div_si */
1092 COSTS_N_INSNS (68), /* int_div_di */
1093 1, /* branch_cost */
1094 4 /* memory_latency */
1095 },
1096 { /* SB1-A */
1097 /* These costs are the same as the SB-1 above. */
1098 COSTS_N_INSNS (4), /* fp_add */
1099 COSTS_N_INSNS (4), /* fp_mult_sf */
1100 COSTS_N_INSNS (4), /* fp_mult_df */
1101 COSTS_N_INSNS (24), /* fp_div_sf */
1102 COSTS_N_INSNS (32), /* fp_div_df */
1103 COSTS_N_INSNS (3), /* int_mult_si */
1104 COSTS_N_INSNS (4), /* int_mult_di */
1105 COSTS_N_INSNS (36), /* int_div_si */
1106 COSTS_N_INSNS (68), /* int_div_di */
1107 1, /* branch_cost */
1108 4 /* memory_latency */
1109 },
1110 { /* SR71000 */
1111 DEFAULT_COSTS
1112 },
1113 };
1114
1115 \f
1116 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1117 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1118 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1119 #endif
1120 \f
1121 /* Initialize the GCC target structure. */
1122 #undef TARGET_ASM_ALIGNED_HI_OP
1123 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1124 #undef TARGET_ASM_ALIGNED_SI_OP
1125 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1126 #undef TARGET_ASM_ALIGNED_DI_OP
1127 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1128
1129 #undef TARGET_ASM_FUNCTION_PROLOGUE
1130 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1131 #undef TARGET_ASM_FUNCTION_EPILOGUE
1132 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1133 #undef TARGET_ASM_SELECT_RTX_SECTION
1134 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1135 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1136 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1137
1138 #undef TARGET_SCHED_REORDER
1139 #define TARGET_SCHED_REORDER mips_sched_reorder
1140 #undef TARGET_SCHED_VARIABLE_ISSUE
1141 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1142 #undef TARGET_SCHED_ADJUST_COST
1143 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1144 #undef TARGET_SCHED_ISSUE_RATE
1145 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1146 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1147 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1148 mips_multipass_dfa_lookahead
1149
1150 #undef TARGET_DEFAULT_TARGET_FLAGS
1151 #define TARGET_DEFAULT_TARGET_FLAGS \
1152 (TARGET_DEFAULT \
1153 | TARGET_CPU_DEFAULT \
1154 | TARGET_ENDIAN_DEFAULT \
1155 | TARGET_FP_EXCEPTIONS_DEFAULT \
1156 | MASK_CHECK_ZERO_DIV \
1157 | MASK_FUSED_MADD)
1158 #undef TARGET_HANDLE_OPTION
1159 #define TARGET_HANDLE_OPTION mips_handle_option
1160
1161 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1162 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1163
1164 #undef TARGET_VALID_POINTER_MODE
1165 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1166 #undef TARGET_RTX_COSTS
1167 #define TARGET_RTX_COSTS mips_rtx_costs
1168 #undef TARGET_ADDRESS_COST
1169 #define TARGET_ADDRESS_COST mips_address_cost
1170
1171 #undef TARGET_IN_SMALL_DATA_P
1172 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1173
1174 #undef TARGET_MACHINE_DEPENDENT_REORG
1175 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1176
1177 #undef TARGET_ASM_FILE_START
1178 #define TARGET_ASM_FILE_START mips_file_start
1179 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1180 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1181
1182 #undef TARGET_INIT_LIBFUNCS
1183 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1184
1185 #undef TARGET_BUILD_BUILTIN_VA_LIST
1186 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1187 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1188 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1189
1190 #undef TARGET_PROMOTE_FUNCTION_ARGS
1191 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1192 #undef TARGET_PROMOTE_FUNCTION_RETURN
1193 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1194 #undef TARGET_PROMOTE_PROTOTYPES
1195 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1196
1197 #undef TARGET_RETURN_IN_MEMORY
1198 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1199 #undef TARGET_RETURN_IN_MSB
1200 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1201
1202 #undef TARGET_ASM_OUTPUT_MI_THUNK
1203 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1204 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1205 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1206
1207 #undef TARGET_SETUP_INCOMING_VARARGS
1208 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1209 #undef TARGET_STRICT_ARGUMENT_NAMING
1210 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1211 #undef TARGET_MUST_PASS_IN_STACK
1212 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1213 #undef TARGET_PASS_BY_REFERENCE
1214 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1215 #undef TARGET_CALLEE_COPIES
1216 #define TARGET_CALLEE_COPIES mips_callee_copies
1217 #undef TARGET_ARG_PARTIAL_BYTES
1218 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1219
1220 #undef TARGET_MODE_REP_EXTENDED
1221 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1222
1223 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1224 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1225
1226 #undef TARGET_INIT_BUILTINS
1227 #define TARGET_INIT_BUILTINS mips_init_builtins
1228 #undef TARGET_EXPAND_BUILTIN
1229 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1230
1231 #undef TARGET_HAVE_TLS
1232 #define TARGET_HAVE_TLS HAVE_AS_TLS
1233
1234 #undef TARGET_CANNOT_FORCE_CONST_MEM
1235 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1236
1237 #undef TARGET_ENCODE_SECTION_INFO
1238 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1239
1240 #undef TARGET_ATTRIBUTE_TABLE
1241 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1242
1243 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1244 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1245
1246 #undef TARGET_MIN_ANCHOR_OFFSET
1247 #define TARGET_MIN_ANCHOR_OFFSET -32768
1248 #undef TARGET_MAX_ANCHOR_OFFSET
1249 #define TARGET_MAX_ANCHOR_OFFSET 32767
1250 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1251 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1252 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1253 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1254
1255 #undef TARGET_COMP_TYPE_ATTRIBUTES
1256 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
1257
1258 struct gcc_target targetm = TARGET_INITIALIZER;
1259
1260
1261 /* Predicates to test for presence of "near" and "far"/"long_call"
1262 attributes on the given TYPE. */
1263
1264 static bool
1265 mips_near_type_p (tree type)
1266 {
1267 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1268 }
1269
1270 static bool
1271 mips_far_type_p (tree type)
1272 {
1273 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1274 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1275 }
1276
1277
1278 /* Return 0 if the attributes for two types are incompatible, 1 if they
1279 are compatible, and 2 if they are nearly compatible (which causes a
1280 warning to be generated). */
1281
1282 static int
1283 mips_comp_type_attributes (tree type1, tree type2)
1284 {
1285 /* Check for mismatch of non-default calling convention. */
1286 if (TREE_CODE (type1) != FUNCTION_TYPE)
1287 return 1;
1288
1289 /* Disallow mixed near/far attributes. */
1290 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1291 return 0;
1292 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1293 return 0;
1294
1295 return 1;
1296 }
1297 \f
1298 /* Return true if SYMBOL_REF X is associated with a global symbol
1299 (in the STB_GLOBAL sense). */
1300
1301 static bool
1302 mips_global_symbol_p (rtx x)
1303 {
1304 tree decl;
1305
1306 decl = SYMBOL_REF_DECL (x);
1307 if (!decl)
1308 return !SYMBOL_REF_LOCAL_P (x);
1309
1310 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1311 or weak symbols. Relocations in the object file will be against
1312 the target symbol, so it's that symbol's binding that matters here. */
1313 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1314 }
1315
1316 /* Return true if SYMBOL_REF X binds locally. */
1317
1318 static bool
1319 mips_symbol_binds_local_p (rtx x)
1320 {
1321 return (SYMBOL_REF_DECL (x)
1322 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1323 : SYMBOL_REF_LOCAL_P (x));
1324 }
1325
1326 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1327
1328 static enum mips_symbol_type
1329 mips_classify_symbol (rtx x)
1330 {
1331 if (TARGET_RTP_PIC)
1332 return SYMBOL_GOT_DISP;
1333
1334 if (GET_CODE (x) == LABEL_REF)
1335 {
1336 if (TARGET_MIPS16)
1337 return SYMBOL_CONSTANT_POOL;
1338 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1339 return SYMBOL_GOT_PAGE_OFST;
1340 return SYMBOL_GENERAL;
1341 }
1342
1343 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1344
1345 if (SYMBOL_REF_TLS_MODEL (x))
1346 return SYMBOL_TLS;
1347
1348 if (CONSTANT_POOL_ADDRESS_P (x))
1349 {
1350 if (TARGET_MIPS16)
1351 return SYMBOL_CONSTANT_POOL;
1352
1353 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1354 return SYMBOL_SMALL_DATA;
1355 }
1356
1357 /* Do not use small-data accesses for weak symbols; they may end up
1358 being zero. */
1359 if (SYMBOL_REF_SMALL_P (x)
1360 && !SYMBOL_REF_WEAK (x))
1361 return SYMBOL_SMALL_DATA;
1362
1363 if (TARGET_ABICALLS)
1364 {
1365 /* Don't use GOT accesses for locally-binding symbols; we can use
1366 %hi and %lo instead. */
1367 if (TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))
1368 return SYMBOL_GENERAL;
1369
1370 /* There are three cases to consider:
1371
1372 - o32 PIC (either with or without explicit relocs)
1373 - n32/n64 PIC without explicit relocs
1374 - n32/n64 PIC with explicit relocs
1375
1376 In the first case, both local and global accesses will use an
1377 R_MIPS_GOT16 relocation. We must correctly predict which of
1378 the two semantics (local or global) the assembler and linker
1379 will apply. The choice depends on the symbol's binding rather
1380 than its visibility.
1381
1382 In the second case, the assembler will not use R_MIPS_GOT16
1383 relocations, but it chooses between local and global accesses
1384 in the same way as for o32 PIC.
1385
1386 In the third case we have more freedom since both forms of
1387 access will work for any kind of symbol. However, there seems
1388 little point in doing things differently. */
1389 if (mips_global_symbol_p (x))
1390 return SYMBOL_GOT_DISP;
1391
1392 return SYMBOL_GOT_PAGE_OFST;
1393 }
1394
1395 return SYMBOL_GENERAL;
1396 }
1397
1398 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1399 is the alignment (in bytes) of SYMBOL_REF X. */
1400
1401 static bool
1402 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1403 {
1404 /* If for some reason we can't get the alignment for the
1405 symbol, initializing this to one means we will only accept
1406 a zero offset. */
1407 HOST_WIDE_INT align = 1;
1408 tree t;
1409
1410 /* Get the alignment of the symbol we're referring to. */
1411 t = SYMBOL_REF_DECL (x);
1412 if (t)
1413 align = DECL_ALIGN_UNIT (t);
1414
1415 return offset >= 0 && offset < align;
1416 }
1417
1418 /* Return true if X is a symbolic constant that can be calculated in
1419 the same way as a bare symbol. If it is, store the type of the
1420 symbol in *SYMBOL_TYPE. */
1421
1422 bool
1423 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1424 {
1425 rtx offset;
1426
1427 split_const (x, &x, &offset);
1428 if (UNSPEC_ADDRESS_P (x))
1429 {
1430 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1431 x = UNSPEC_ADDRESS (x);
1432 }
1433 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1434 {
1435 *symbol_type = mips_classify_symbol (x);
1436 if (*symbol_type == SYMBOL_TLS)
1437 return false;
1438 }
1439 else
1440 return false;
1441
1442 if (offset == const0_rtx)
1443 return true;
1444
1445 /* Check whether a nonzero offset is valid for the underlying
1446 relocations. */
1447 switch (*symbol_type)
1448 {
1449 case SYMBOL_GENERAL:
1450 case SYMBOL_64_HIGH:
1451 case SYMBOL_64_MID:
1452 case SYMBOL_64_LOW:
1453 /* If the target has 64-bit pointers and the object file only
1454 supports 32-bit symbols, the values of those symbols will be
1455 sign-extended. In this case we can't allow an arbitrary offset
1456 in case the 32-bit value X + OFFSET has a different sign from X. */
1457 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1458 return offset_within_block_p (x, INTVAL (offset));
1459
1460 /* In other cases the relocations can handle any offset. */
1461 return true;
1462
1463 case SYMBOL_CONSTANT_POOL:
1464 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1465 In this case, we no longer have access to the underlying constant,
1466 but the original symbol-based access was known to be valid. */
1467 if (GET_CODE (x) == LABEL_REF)
1468 return true;
1469
1470 /* Fall through. */
1471
1472 case SYMBOL_SMALL_DATA:
1473 /* Make sure that the offset refers to something within the
1474 same object block. This should guarantee that the final
1475 PC- or GP-relative offset is within the 16-bit limit. */
1476 return offset_within_block_p (x, INTVAL (offset));
1477
1478 case SYMBOL_GOT_PAGE_OFST:
1479 case SYMBOL_GOTOFF_PAGE:
1480 /* If the symbol is global, the GOT entry will contain the symbol's
1481 address, and we will apply a 16-bit offset after loading it.
1482 If the symbol is local, the linker should provide enough local
1483 GOT entries for a 16-bit offset, but larger offsets may lead
1484 to GOT overflow. */
1485 return SMALL_INT (offset);
1486
1487 case SYMBOL_TPREL:
1488 case SYMBOL_DTPREL:
1489 /* There is no carry between the HI and LO REL relocations, so the
1490 offset is only valid if we know it won't lead to such a carry. */
1491 return mips_offset_within_alignment_p (x, INTVAL (offset));
1492
1493 case SYMBOL_GOT_DISP:
1494 case SYMBOL_GOTOFF_DISP:
1495 case SYMBOL_GOTOFF_CALL:
1496 case SYMBOL_GOTOFF_LOADGP:
1497 case SYMBOL_TLSGD:
1498 case SYMBOL_TLSLDM:
1499 case SYMBOL_GOTTPREL:
1500 case SYMBOL_TLS:
1501 case SYMBOL_HALF:
1502 return false;
1503 }
1504 gcc_unreachable ();
1505 }
1506
1507
1508 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1509
1510 int
1511 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1512 {
1513 if (!HARD_REGISTER_NUM_P (regno))
1514 {
1515 if (!strict)
1516 return true;
1517 regno = reg_renumber[regno];
1518 }
1519
1520 /* These fake registers will be eliminated to either the stack or
1521 hard frame pointer, both of which are usually valid base registers.
1522 Reload deals with the cases where the eliminated form isn't valid. */
1523 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1524 return true;
1525
1526 /* In mips16 mode, the stack pointer can only address word and doubleword
1527 values, nothing smaller. There are two problems here:
1528
1529 (a) Instantiating virtual registers can introduce new uses of the
1530 stack pointer. If these virtual registers are valid addresses,
1531 the stack pointer should be too.
1532
1533 (b) Most uses of the stack pointer are not made explicit until
1534 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1535 We don't know until that stage whether we'll be eliminating to the
1536 stack pointer (which needs the restriction) or the hard frame
1537 pointer (which doesn't).
1538
1539 All in all, it seems more consistent to only enforce this restriction
1540 during and after reload. */
1541 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1542 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1543
1544 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1545 }
1546
1547
1548 /* Return true if X is a valid base register for the given mode.
1549 Allow only hard registers if STRICT. */
1550
1551 static bool
1552 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1553 {
1554 if (!strict && GET_CODE (x) == SUBREG)
1555 x = SUBREG_REG (x);
1556
1557 return (REG_P (x)
1558 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1559 }
1560
1561
1562 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1563 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1564
1565 static bool
1566 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1567 enum machine_mode mode)
1568 {
1569 switch (symbol_type)
1570 {
1571 case SYMBOL_GENERAL:
1572 return !TARGET_MIPS16;
1573
1574 case SYMBOL_SMALL_DATA:
1575 return true;
1576
1577 case SYMBOL_CONSTANT_POOL:
1578 /* PC-relative addressing is only available for lw and ld. */
1579 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1580
1581 case SYMBOL_GOT_PAGE_OFST:
1582 return true;
1583
1584 case SYMBOL_GOT_DISP:
1585 /* The address will have to be loaded from the GOT first. */
1586 return false;
1587
1588 case SYMBOL_GOTOFF_PAGE:
1589 case SYMBOL_GOTOFF_DISP:
1590 case SYMBOL_GOTOFF_CALL:
1591 case SYMBOL_GOTOFF_LOADGP:
1592 case SYMBOL_TLS:
1593 case SYMBOL_TLSGD:
1594 case SYMBOL_TLSLDM:
1595 case SYMBOL_DTPREL:
1596 case SYMBOL_GOTTPREL:
1597 case SYMBOL_TPREL:
1598 case SYMBOL_64_HIGH:
1599 case SYMBOL_64_MID:
1600 case SYMBOL_64_LOW:
1601 case SYMBOL_HALF:
1602 return true;
1603 }
1604 gcc_unreachable ();
1605 }
1606
1607
1608 /* Return true if X is a valid address for machine mode MODE. If it is,
1609 fill in INFO appropriately. STRICT is true if we should only accept
1610 hard base registers. */
1611
1612 static bool
1613 mips_classify_address (struct mips_address_info *info, rtx x,
1614 enum machine_mode mode, int strict)
1615 {
1616 switch (GET_CODE (x))
1617 {
1618 case REG:
1619 case SUBREG:
1620 info->type = ADDRESS_REG;
1621 info->reg = x;
1622 info->offset = const0_rtx;
1623 return mips_valid_base_register_p (info->reg, mode, strict);
1624
1625 case PLUS:
1626 info->type = ADDRESS_REG;
1627 info->reg = XEXP (x, 0);
1628 info->offset = XEXP (x, 1);
1629 return (mips_valid_base_register_p (info->reg, mode, strict)
1630 && const_arith_operand (info->offset, VOIDmode));
1631
1632 case LO_SUM:
1633 info->type = ADDRESS_LO_SUM;
1634 info->reg = XEXP (x, 0);
1635 info->offset = XEXP (x, 1);
1636 return (mips_valid_base_register_p (info->reg, mode, strict)
1637 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1638 && mips_symbolic_address_p (info->symbol_type, mode)
1639 && mips_lo_relocs[info->symbol_type] != 0);
1640
1641 case CONST_INT:
1642 /* Small-integer addresses don't occur very often, but they
1643 are legitimate if $0 is a valid base register. */
1644 info->type = ADDRESS_CONST_INT;
1645 return !TARGET_MIPS16 && SMALL_INT (x);
1646
1647 case CONST:
1648 case LABEL_REF:
1649 case SYMBOL_REF:
1650 info->type = ADDRESS_SYMBOLIC;
1651 return (mips_symbolic_constant_p (x, &info->symbol_type)
1652 && mips_symbolic_address_p (info->symbol_type, mode)
1653 && !mips_split_p[info->symbol_type]);
1654
1655 default:
1656 return false;
1657 }
1658 }
1659
1660 /* Return true if X is a thread-local symbol. */
1661
1662 static bool
1663 mips_tls_operand_p (rtx x)
1664 {
1665 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1666 }
1667
1668 /* Return true if X can not be forced into a constant pool. */
1669
1670 static int
1671 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1672 {
1673 return mips_tls_operand_p (*x);
1674 }
1675
1676 /* Return true if X can not be forced into a constant pool. */
1677
1678 static bool
1679 mips_cannot_force_const_mem (rtx x)
1680 {
1681 rtx base, offset;
1682
1683 if (!TARGET_MIPS16)
1684 {
1685 /* As an optimization, reject constants that mips_legitimize_move
1686 can expand inline.
1687
1688 Suppose we have a multi-instruction sequence that loads constant C
1689 into register R. If R does not get allocated a hard register, and
1690 R is used in an operand that allows both registers and memory
1691 references, reload will consider forcing C into memory and using
1692 one of the instruction's memory alternatives. Returning false
1693 here will force it to use an input reload instead. */
1694 if (GET_CODE (x) == CONST_INT)
1695 return true;
1696
1697 split_const (x, &base, &offset);
1698 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1699 return true;
1700 }
1701
1702 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1703 return true;
1704
1705 return false;
1706 }
1707
1708 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1709 constant pools, but normal-mode code doesn't need to. */
1710
1711 static bool
1712 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1713 rtx x ATTRIBUTE_UNUSED)
1714 {
1715 return !TARGET_MIPS16;
1716 }
1717 \f
1718 /* Return the number of instructions needed to load a symbol of the
1719 given type into a register. If valid in an address, the same number
1720 of instructions are needed for loads and stores. Treat extended
1721 mips16 instructions as two instructions. */
1722
1723 static int
1724 mips_symbol_insns (enum mips_symbol_type type)
1725 {
1726 switch (type)
1727 {
1728 case SYMBOL_GENERAL:
1729 /* In mips16 code, general symbols must be fetched from the
1730 constant pool. */
1731 if (TARGET_MIPS16)
1732 return 0;
1733
1734 /* When using 64-bit symbols, we need 5 preparatory instructions,
1735 such as:
1736
1737 lui $at,%highest(symbol)
1738 daddiu $at,$at,%higher(symbol)
1739 dsll $at,$at,16
1740 daddiu $at,$at,%hi(symbol)
1741 dsll $at,$at,16
1742
1743 The final address is then $at + %lo(symbol). With 32-bit
1744 symbols we just need a preparatory lui. */
1745 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1746
1747 case SYMBOL_SMALL_DATA:
1748 case SYMBOL_HALF:
1749 return 1;
1750
1751 case SYMBOL_CONSTANT_POOL:
1752 /* This case is for mips16 only. Assume we'll need an
1753 extended instruction. */
1754 return 2;
1755
1756 case SYMBOL_GOT_PAGE_OFST:
1757 case SYMBOL_GOT_DISP:
1758 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1759 the local/global classification is accurate. See override_options
1760 for details.
1761
1762 The worst cases are:
1763
1764 (1) For local symbols when generating o32 or o64 code. The assembler
1765 will use:
1766
1767 lw $at,%got(symbol)
1768 nop
1769
1770 ...and the final address will be $at + %lo(symbol).
1771
1772 (2) For global symbols when -mxgot. The assembler will use:
1773
1774 lui $at,%got_hi(symbol)
1775 (d)addu $at,$at,$gp
1776
1777 ...and the final address will be $at + %got_lo(symbol). */
1778 return 3;
1779
1780 case SYMBOL_GOTOFF_PAGE:
1781 case SYMBOL_GOTOFF_DISP:
1782 case SYMBOL_GOTOFF_CALL:
1783 case SYMBOL_GOTOFF_LOADGP:
1784 case SYMBOL_64_HIGH:
1785 case SYMBOL_64_MID:
1786 case SYMBOL_64_LOW:
1787 case SYMBOL_TLSGD:
1788 case SYMBOL_TLSLDM:
1789 case SYMBOL_DTPREL:
1790 case SYMBOL_GOTTPREL:
1791 case SYMBOL_TPREL:
1792 /* Check whether the offset is a 16- or 32-bit value. */
1793 return mips_split_p[type] ? 2 : 1;
1794
1795 case SYMBOL_TLS:
1796 /* We don't treat a bare TLS symbol as a constant. */
1797 return 0;
1798 }
1799 gcc_unreachable ();
1800 }
1801
1802 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1803
1804 bool
1805 mips_stack_address_p (rtx x, enum machine_mode mode)
1806 {
1807 struct mips_address_info addr;
1808
1809 return (mips_classify_address (&addr, x, mode, false)
1810 && addr.type == ADDRESS_REG
1811 && addr.reg == stack_pointer_rtx);
1812 }
1813
1814 /* Return true if a value at OFFSET bytes from BASE can be accessed
1815 using an unextended mips16 instruction. MODE is the mode of the
1816 value.
1817
1818 Usually the offset in an unextended instruction is a 5-bit field.
1819 The offset is unsigned and shifted left once for HIs, twice
1820 for SIs, and so on. An exception is SImode accesses off the
1821 stack pointer, which have an 8-bit immediate field. */
1822
1823 static bool
1824 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1825 {
1826 if (TARGET_MIPS16
1827 && GET_CODE (offset) == CONST_INT
1828 && INTVAL (offset) >= 0
1829 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1830 {
1831 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1832 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1833 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1834 }
1835 return false;
1836 }
1837
1838
1839 /* Return the number of instructions needed to load or store a value
1840 of mode MODE at X. Return 0 if X isn't valid for MODE.
1841
1842 For mips16 code, count extended instructions as two instructions. */
1843
1844 int
1845 mips_address_insns (rtx x, enum machine_mode mode)
1846 {
1847 struct mips_address_info addr;
1848 int factor;
1849
1850 if (mode == BLKmode)
1851 /* BLKmode is used for single unaligned loads and stores. */
1852 factor = 1;
1853 else
1854 /* Each word of a multi-word value will be accessed individually. */
1855 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1856
1857 if (mips_classify_address (&addr, x, mode, false))
1858 switch (addr.type)
1859 {
1860 case ADDRESS_REG:
1861 if (TARGET_MIPS16
1862 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1863 return factor * 2;
1864 return factor;
1865
1866 case ADDRESS_LO_SUM:
1867 return (TARGET_MIPS16 ? factor * 2 : factor);
1868
1869 case ADDRESS_CONST_INT:
1870 return factor;
1871
1872 case ADDRESS_SYMBOLIC:
1873 return factor * mips_symbol_insns (addr.symbol_type);
1874 }
1875 return 0;
1876 }
1877
1878
1879 /* Likewise for constant X. */
1880
1881 int
1882 mips_const_insns (rtx x)
1883 {
1884 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1885 enum mips_symbol_type symbol_type;
1886 rtx offset;
1887
1888 switch (GET_CODE (x))
1889 {
1890 case HIGH:
1891 if (TARGET_MIPS16
1892 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1893 || !mips_split_p[symbol_type])
1894 return 0;
1895
1896 return 1;
1897
1898 case CONST_INT:
1899 if (TARGET_MIPS16)
1900 /* Unsigned 8-bit constants can be loaded using an unextended
1901 LI instruction. Unsigned 16-bit constants can be loaded
1902 using an extended LI. Negative constants must be loaded
1903 using LI and then negated. */
1904 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1905 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1906 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1907 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1908 : 0);
1909
1910 return mips_build_integer (codes, INTVAL (x));
1911
1912 case CONST_DOUBLE:
1913 case CONST_VECTOR:
1914 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1915
1916 case CONST:
1917 if (CONST_GP_P (x))
1918 return 1;
1919
1920 /* See if we can refer to X directly. */
1921 if (mips_symbolic_constant_p (x, &symbol_type))
1922 return mips_symbol_insns (symbol_type);
1923
1924 /* Otherwise try splitting the constant into a base and offset.
1925 16-bit offsets can be added using an extra addiu. Larger offsets
1926 must be calculated separately and then added to the base. */
1927 split_const (x, &x, &offset);
1928 if (offset != 0)
1929 {
1930 int n = mips_const_insns (x);
1931 if (n != 0)
1932 {
1933 if (SMALL_INT (offset))
1934 return n + 1;
1935 else
1936 return n + 1 + mips_build_integer (codes, INTVAL (offset));
1937 }
1938 }
1939 return 0;
1940
1941 case SYMBOL_REF:
1942 case LABEL_REF:
1943 return mips_symbol_insns (mips_classify_symbol (x));
1944
1945 default:
1946 return 0;
1947 }
1948 }
1949
1950
1951 /* Return the number of instructions needed for memory reference X.
1952 Count extended mips16 instructions as two instructions. */
1953
1954 int
1955 mips_fetch_insns (rtx x)
1956 {
1957 gcc_assert (MEM_P (x));
1958 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1959 }
1960
1961
1962 /* Return the number of instructions needed for an integer division. */
1963
1964 int
1965 mips_idiv_insns (void)
1966 {
1967 int count;
1968
1969 count = 1;
1970 if (TARGET_CHECK_ZERO_DIV)
1971 {
1972 if (GENERATE_DIVIDE_TRAPS)
1973 count++;
1974 else
1975 count += 2;
1976 }
1977
1978 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1979 count++;
1980 return count;
1981 }
1982 \f
1983 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1984 returns a nonzero value if X is a legitimate address for a memory
1985 operand of the indicated MODE. STRICT is nonzero if this function
1986 is called during reload. */
1987
1988 bool
1989 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1990 {
1991 struct mips_address_info addr;
1992
1993 return mips_classify_address (&addr, x, mode, strict);
1994 }
1995
1996
1997 /* Copy VALUE to a register and return that register. If new psuedos
1998 are allowed, copy it into a new register, otherwise use DEST. */
1999
2000 static rtx
2001 mips_force_temporary (rtx dest, rtx value)
2002 {
2003 if (!no_new_pseudos)
2004 return force_reg (Pmode, value);
2005 else
2006 {
2007 emit_move_insn (copy_rtx (dest), value);
2008 return dest;
2009 }
2010 }
2011
2012
2013 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
2014 and is used to load the high part into a register. */
2015
2016 rtx
2017 mips_split_symbol (rtx temp, rtx addr)
2018 {
2019 rtx high;
2020
2021 if (!TARGET_MIPS16)
2022 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
2023 else if (no_new_pseudos)
2024 {
2025 emit_insn (gen_load_const_gp (copy_rtx (temp)));
2026 high = temp;
2027 }
2028 else
2029 high = mips16_gp_pseudo_reg ();
2030 return gen_rtx_LO_SUM (Pmode, high, addr);
2031 }
2032
2033
2034 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2035 type SYMBOL_TYPE. */
2036
2037 rtx
2038 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2039 {
2040 rtx base, offset;
2041
2042 split_const (address, &base, &offset);
2043 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2044 UNSPEC_ADDRESS_FIRST + symbol_type);
2045 if (offset != const0_rtx)
2046 base = gen_rtx_PLUS (Pmode, base, offset);
2047 return gen_rtx_CONST (Pmode, base);
2048 }
2049
2050
2051 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2052 high part to BASE and return the result. Just return BASE otherwise.
2053 TEMP is available as a temporary register if needed.
2054
2055 The returned expression can be used as the first operand to a LO_SUM. */
2056
2057 static rtx
2058 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2059 enum mips_symbol_type symbol_type)
2060 {
2061 if (mips_split_p[symbol_type])
2062 {
2063 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2064 addr = mips_force_temporary (temp, addr);
2065 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2066 }
2067 return base;
2068 }
2069
2070
2071 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2072 mips_force_temporary; it is only needed when OFFSET is not a
2073 SMALL_OPERAND. */
2074
2075 static rtx
2076 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2077 {
2078 if (!SMALL_OPERAND (offset))
2079 {
2080 rtx high;
2081 if (TARGET_MIPS16)
2082 {
2083 /* Load the full offset into a register so that we can use
2084 an unextended instruction for the address itself. */
2085 high = GEN_INT (offset);
2086 offset = 0;
2087 }
2088 else
2089 {
2090 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2091 high = GEN_INT (CONST_HIGH_PART (offset));
2092 offset = CONST_LOW_PART (offset);
2093 }
2094 high = mips_force_temporary (temp, high);
2095 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2096 }
2097 return plus_constant (reg, offset);
2098 }
2099
2100 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2101 referencing, and TYPE is the symbol type to use (either global
2102 dynamic or local dynamic). V0 is an RTX for the return value
2103 location. The entire insn sequence is returned. */
2104
2105 static GTY(()) rtx mips_tls_symbol;
2106
2107 static rtx
2108 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2109 {
2110 rtx insn, loc, tga, a0;
2111
2112 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2113
2114 if (!mips_tls_symbol)
2115 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2116
2117 loc = mips_unspec_address (sym, type);
2118
2119 start_sequence ();
2120
2121 emit_insn (gen_rtx_SET (Pmode, a0,
2122 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2123 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2124 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2125 CONST_OR_PURE_CALL_P (insn) = 1;
2126 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2127 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2128 insn = get_insns ();
2129
2130 end_sequence ();
2131
2132 return insn;
2133 }
2134
2135 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2136 return value will be a valid address and move_operand (either a REG
2137 or a LO_SUM). */
2138
2139 static rtx
2140 mips_legitimize_tls_address (rtx loc)
2141 {
2142 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2143 enum tls_model model;
2144
2145 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2146 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2147
2148 model = SYMBOL_REF_TLS_MODEL (loc);
2149 /* Only TARGET_ABICALLS code can have more than one module; other
2150 code must be be static and should not use a GOT. All TLS models
2151 reduce to local exec in this situation. */
2152 if (!TARGET_ABICALLS)
2153 model = TLS_MODEL_LOCAL_EXEC;
2154
2155 switch (model)
2156 {
2157 case TLS_MODEL_GLOBAL_DYNAMIC:
2158 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2159 dest = gen_reg_rtx (Pmode);
2160 emit_libcall_block (insn, dest, v0, loc);
2161 break;
2162
2163 case TLS_MODEL_LOCAL_DYNAMIC:
2164 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2165 tmp1 = gen_reg_rtx (Pmode);
2166
2167 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2168 share the LDM result with other LD model accesses. */
2169 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2170 UNSPEC_TLS_LDM);
2171 emit_libcall_block (insn, tmp1, v0, eqv);
2172
2173 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2174 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2175 mips_unspec_address (loc, SYMBOL_DTPREL));
2176 break;
2177
2178 case TLS_MODEL_INITIAL_EXEC:
2179 tmp1 = gen_reg_rtx (Pmode);
2180 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2181 if (Pmode == DImode)
2182 {
2183 emit_insn (gen_tls_get_tp_di (v1));
2184 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2185 }
2186 else
2187 {
2188 emit_insn (gen_tls_get_tp_si (v1));
2189 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2190 }
2191 dest = gen_reg_rtx (Pmode);
2192 emit_insn (gen_add3_insn (dest, tmp1, v1));
2193 break;
2194
2195 case TLS_MODEL_LOCAL_EXEC:
2196 if (Pmode == DImode)
2197 emit_insn (gen_tls_get_tp_di (v1));
2198 else
2199 emit_insn (gen_tls_get_tp_si (v1));
2200
2201 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2202 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2203 mips_unspec_address (loc, SYMBOL_TPREL));
2204 break;
2205
2206 default:
2207 gcc_unreachable ();
2208 }
2209
2210 return dest;
2211 }
2212
2213 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2214 be legitimized in a way that the generic machinery might not expect,
2215 put the new address in *XLOC and return true. MODE is the mode of
2216 the memory being accessed. */
2217
2218 bool
2219 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2220 {
2221 enum mips_symbol_type symbol_type;
2222
2223 if (mips_tls_operand_p (*xloc))
2224 {
2225 *xloc = mips_legitimize_tls_address (*xloc);
2226 return true;
2227 }
2228
2229 /* See if the address can split into a high part and a LO_SUM. */
2230 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2231 && mips_symbolic_address_p (symbol_type, mode)
2232 && mips_split_p[symbol_type])
2233 {
2234 *xloc = mips_split_symbol (0, *xloc);
2235 return true;
2236 }
2237
2238 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2239 {
2240 /* Handle REG + CONSTANT using mips_add_offset. */
2241 rtx reg;
2242
2243 reg = XEXP (*xloc, 0);
2244 if (!mips_valid_base_register_p (reg, mode, 0))
2245 reg = copy_to_mode_reg (Pmode, reg);
2246 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2247 return true;
2248 }
2249
2250 return false;
2251 }
2252
2253
2254 /* Subroutine of mips_build_integer (with the same interface).
2255 Assume that the final action in the sequence should be a left shift. */
2256
2257 static unsigned int
2258 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2259 {
2260 unsigned int i, shift;
2261
2262 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2263 since signed numbers are easier to load than unsigned ones. */
2264 shift = 0;
2265 while ((value & 1) == 0)
2266 value /= 2, shift++;
2267
2268 i = mips_build_integer (codes, value);
2269 codes[i].code = ASHIFT;
2270 codes[i].value = shift;
2271 return i + 1;
2272 }
2273
2274
2275 /* As for mips_build_shift, but assume that the final action will be
2276 an IOR or PLUS operation. */
2277
2278 static unsigned int
2279 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2280 {
2281 unsigned HOST_WIDE_INT high;
2282 unsigned int i;
2283
2284 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2285 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2286 {
2287 /* The constant is too complex to load with a simple lui/ori pair
2288 so our goal is to clear as many trailing zeros as possible.
2289 In this case, we know bit 16 is set and that the low 16 bits
2290 form a negative number. If we subtract that number from VALUE,
2291 we will clear at least the lowest 17 bits, maybe more. */
2292 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2293 codes[i].code = PLUS;
2294 codes[i].value = CONST_LOW_PART (value);
2295 }
2296 else
2297 {
2298 i = mips_build_integer (codes, high);
2299 codes[i].code = IOR;
2300 codes[i].value = value & 0xffff;
2301 }
2302 return i + 1;
2303 }
2304
2305
2306 /* Fill CODES with a sequence of rtl operations to load VALUE.
2307 Return the number of operations needed. */
2308
2309 static unsigned int
2310 mips_build_integer (struct mips_integer_op *codes,
2311 unsigned HOST_WIDE_INT value)
2312 {
2313 if (SMALL_OPERAND (value)
2314 || SMALL_OPERAND_UNSIGNED (value)
2315 || LUI_OPERAND (value))
2316 {
2317 /* The value can be loaded with a single instruction. */
2318 codes[0].code = UNKNOWN;
2319 codes[0].value = value;
2320 return 1;
2321 }
2322 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2323 {
2324 /* Either the constant is a simple LUI/ORI combination or its
2325 lowest bit is set. We don't want to shift in this case. */
2326 return mips_build_lower (codes, value);
2327 }
2328 else if ((value & 0xffff) == 0)
2329 {
2330 /* The constant will need at least three actions. The lowest
2331 16 bits are clear, so the final action will be a shift. */
2332 return mips_build_shift (codes, value);
2333 }
2334 else
2335 {
2336 /* The final action could be a shift, add or inclusive OR.
2337 Rather than use a complex condition to select the best
2338 approach, try both mips_build_shift and mips_build_lower
2339 and pick the one that gives the shortest sequence.
2340 Note that this case is only used once per constant. */
2341 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2342 unsigned int cost, alt_cost;
2343
2344 cost = mips_build_shift (codes, value);
2345 alt_cost = mips_build_lower (alt_codes, value);
2346 if (alt_cost < cost)
2347 {
2348 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2349 cost = alt_cost;
2350 }
2351 return cost;
2352 }
2353 }
2354
2355
2356 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2357
2358 void
2359 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2360 {
2361 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2362 enum machine_mode mode;
2363 unsigned int i, cost;
2364 rtx x;
2365
2366 mode = GET_MODE (dest);
2367 cost = mips_build_integer (codes, value);
2368
2369 /* Apply each binary operation to X. Invariant: X is a legitimate
2370 source operand for a SET pattern. */
2371 x = GEN_INT (codes[0].value);
2372 for (i = 1; i < cost; i++)
2373 {
2374 if (no_new_pseudos)
2375 {
2376 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2377 x = temp;
2378 }
2379 else
2380 x = force_reg (mode, x);
2381 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2382 }
2383
2384 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2385 }
2386
2387
2388 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2389 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2390 move_operand. */
2391
2392 static void
2393 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2394 {
2395 rtx base, offset;
2396
2397 /* Split moves of big integers into smaller pieces. */
2398 if (splittable_const_int_operand (src, mode))
2399 {
2400 mips_move_integer (dest, dest, INTVAL (src));
2401 return;
2402 }
2403
2404 /* Split moves of symbolic constants into high/low pairs. */
2405 if (splittable_symbolic_operand (src, mode))
2406 {
2407 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2408 return;
2409 }
2410
2411 if (mips_tls_operand_p (src))
2412 {
2413 emit_move_insn (dest, mips_legitimize_tls_address (src));
2414 return;
2415 }
2416
2417 /* If we have (const (plus symbol offset)), load the symbol first
2418 and then add in the offset. This is usually better than forcing
2419 the constant into memory, at least in non-mips16 code. */
2420 split_const (src, &base, &offset);
2421 if (!TARGET_MIPS16
2422 && offset != const0_rtx
2423 && (!no_new_pseudos || SMALL_INT (offset)))
2424 {
2425 base = mips_force_temporary (dest, base);
2426 emit_move_insn (dest, mips_add_offset (0, base, INTVAL (offset)));
2427 return;
2428 }
2429
2430 src = force_const_mem (mode, src);
2431
2432 /* When using explicit relocs, constant pool references are sometimes
2433 not legitimate addresses. */
2434 if (!memory_operand (src, VOIDmode))
2435 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2436 emit_move_insn (dest, src);
2437 }
2438
2439
2440 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2441 sequence that is valid. */
2442
2443 bool
2444 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2445 {
2446 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2447 {
2448 emit_move_insn (dest, force_reg (mode, src));
2449 return true;
2450 }
2451
2452 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2453 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2454 && REG_P (src) && MD_REG_P (REGNO (src))
2455 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2456 {
2457 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2458 if (GET_MODE_SIZE (mode) <= 4)
2459 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2460 gen_rtx_REG (SImode, REGNO (src)),
2461 gen_rtx_REG (SImode, other_regno)));
2462 else
2463 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2464 gen_rtx_REG (DImode, REGNO (src)),
2465 gen_rtx_REG (DImode, other_regno)));
2466 return true;
2467 }
2468
2469 /* We need to deal with constants that would be legitimate
2470 immediate_operands but not legitimate move_operands. */
2471 if (CONSTANT_P (src) && !move_operand (src, mode))
2472 {
2473 mips_legitimize_const_move (mode, dest, src);
2474 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2475 return true;
2476 }
2477 return false;
2478 }
2479 \f
2480 /* We need a lot of little routines to check constant values on the
2481 mips16. These are used to figure out how long the instruction will
2482 be. It would be much better to do this using constraints, but
2483 there aren't nearly enough letters available. */
2484
2485 static int
2486 m16_check_op (rtx op, int low, int high, int mask)
2487 {
2488 return (GET_CODE (op) == CONST_INT
2489 && INTVAL (op) >= low
2490 && INTVAL (op) <= high
2491 && (INTVAL (op) & mask) == 0);
2492 }
2493
2494 int
2495 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2496 {
2497 return m16_check_op (op, 0x1, 0x8, 0);
2498 }
2499
2500 int
2501 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2502 {
2503 return m16_check_op (op, - 0x8, 0x7, 0);
2504 }
2505
2506 int
2507 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2508 {
2509 return m16_check_op (op, - 0x7, 0x8, 0);
2510 }
2511
2512 int
2513 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2514 {
2515 return m16_check_op (op, - 0x10, 0xf, 0);
2516 }
2517
2518 int
2519 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2520 {
2521 return m16_check_op (op, - 0xf, 0x10, 0);
2522 }
2523
2524 int
2525 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2526 {
2527 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2528 }
2529
2530 int
2531 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2532 {
2533 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2534 }
2535
2536 int
2537 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2538 {
2539 return m16_check_op (op, - 0x80, 0x7f, 0);
2540 }
2541
2542 int
2543 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2544 {
2545 return m16_check_op (op, - 0x7f, 0x80, 0);
2546 }
2547
2548 int
2549 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2550 {
2551 return m16_check_op (op, 0x0, 0xff, 0);
2552 }
2553
2554 int
2555 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2556 {
2557 return m16_check_op (op, - 0xff, 0x0, 0);
2558 }
2559
2560 int
2561 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2562 {
2563 return m16_check_op (op, - 0x1, 0xfe, 0);
2564 }
2565
2566 int
2567 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2568 {
2569 return m16_check_op (op, 0x0, 0xff << 2, 3);
2570 }
2571
2572 int
2573 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2574 {
2575 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2576 }
2577
2578 int
2579 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2580 {
2581 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2582 }
2583
2584 int
2585 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2586 {
2587 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2588 }
2589 \f
2590 static bool
2591 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2592 {
2593 enum machine_mode mode = GET_MODE (x);
2594 bool float_mode_p = FLOAT_MODE_P (mode);
2595
2596 switch (code)
2597 {
2598 case CONST_INT:
2599 if (TARGET_MIPS16)
2600 {
2601 /* A number between 1 and 8 inclusive is efficient for a shift.
2602 Otherwise, we will need an extended instruction. */
2603 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2604 || (outer_code) == LSHIFTRT)
2605 {
2606 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2607 *total = 0;
2608 else
2609 *total = COSTS_N_INSNS (1);
2610 return true;
2611 }
2612
2613 /* We can use cmpi for an xor with an unsigned 16-bit value. */
2614 if ((outer_code) == XOR
2615 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2616 {
2617 *total = 0;
2618 return true;
2619 }
2620
2621 /* We may be able to use slt or sltu for a comparison with a
2622 signed 16-bit value. (The boundary conditions aren't quite
2623 right, but this is just a heuristic anyhow.) */
2624 if (((outer_code) == LT || (outer_code) == LE
2625 || (outer_code) == GE || (outer_code) == GT
2626 || (outer_code) == LTU || (outer_code) == LEU
2627 || (outer_code) == GEU || (outer_code) == GTU)
2628 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2629 {
2630 *total = 0;
2631 return true;
2632 }
2633
2634 /* Equality comparisons with 0 are cheap. */
2635 if (((outer_code) == EQ || (outer_code) == NE)
2636 && INTVAL (x) == 0)
2637 {
2638 *total = 0;
2639 return true;
2640 }
2641
2642 /* Constants in the range 0...255 can be loaded with an unextended
2643 instruction. They are therefore as cheap as a register move.
2644
2645 Given the choice between "li R1,0...255" and "move R1,R2"
2646 (where R2 is a known constant), it is usually better to use "li",
2647 since we do not want to unnecessarily extend the lifetime
2648 of R2. */
2649 if (outer_code == SET
2650 && INTVAL (x) >= 0
2651 && INTVAL (x) < 256)
2652 {
2653 *total = 0;
2654 return true;
2655 }
2656 }
2657 else
2658 {
2659 /* These can be used anywhere. */
2660 *total = 0;
2661 return true;
2662 }
2663
2664 /* Otherwise fall through to the handling below because
2665 we'll need to construct the constant. */
2666
2667 case CONST:
2668 case SYMBOL_REF:
2669 case LABEL_REF:
2670 case CONST_DOUBLE:
2671 if (LEGITIMATE_CONSTANT_P (x))
2672 {
2673 *total = COSTS_N_INSNS (1);
2674 return true;
2675 }
2676 else
2677 {
2678 /* The value will need to be fetched from the constant pool. */
2679 *total = CONSTANT_POOL_COST;
2680 return true;
2681 }
2682
2683 case MEM:
2684 {
2685 /* If the address is legitimate, return the number of
2686 instructions it needs, otherwise use the default handling. */
2687 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2688 if (n > 0)
2689 {
2690 *total = COSTS_N_INSNS (n + 1);
2691 return true;
2692 }
2693 return false;
2694 }
2695
2696 case FFS:
2697 *total = COSTS_N_INSNS (6);
2698 return true;
2699
2700 case NOT:
2701 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2702 return true;
2703
2704 case AND:
2705 case IOR:
2706 case XOR:
2707 if (mode == DImode && !TARGET_64BIT)
2708 {
2709 *total = COSTS_N_INSNS (2);
2710 return true;
2711 }
2712 return false;
2713
2714 case ASHIFT:
2715 case ASHIFTRT:
2716 case LSHIFTRT:
2717 if (mode == DImode && !TARGET_64BIT)
2718 {
2719 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2720 ? 4 : 12);
2721 return true;
2722 }
2723 return false;
2724
2725 case ABS:
2726 if (float_mode_p)
2727 *total = COSTS_N_INSNS (1);
2728 else
2729 *total = COSTS_N_INSNS (4);
2730 return true;
2731
2732 case LO_SUM:
2733 *total = COSTS_N_INSNS (1);
2734 return true;
2735
2736 case PLUS:
2737 case MINUS:
2738 if (float_mode_p)
2739 {
2740 *total = mips_cost->fp_add;
2741 return true;
2742 }
2743
2744 else if (mode == DImode && !TARGET_64BIT)
2745 {
2746 *total = COSTS_N_INSNS (4);
2747 return true;
2748 }
2749 return false;
2750
2751 case NEG:
2752 if (mode == DImode && !TARGET_64BIT)
2753 {
2754 *total = COSTS_N_INSNS (4);
2755 return true;
2756 }
2757 return false;
2758
2759 case MULT:
2760 if (mode == SFmode)
2761 *total = mips_cost->fp_mult_sf;
2762
2763 else if (mode == DFmode)
2764 *total = mips_cost->fp_mult_df;
2765
2766 else if (mode == SImode)
2767 *total = mips_cost->int_mult_si;
2768
2769 else
2770 *total = mips_cost->int_mult_di;
2771
2772 return true;
2773
2774 case DIV:
2775 case MOD:
2776 if (float_mode_p)
2777 {
2778 if (mode == SFmode)
2779 *total = mips_cost->fp_div_sf;
2780 else
2781 *total = mips_cost->fp_div_df;
2782
2783 return true;
2784 }
2785 /* Fall through. */
2786
2787 case UDIV:
2788 case UMOD:
2789 if (mode == DImode)
2790 *total = mips_cost->int_div_di;
2791 else
2792 *total = mips_cost->int_div_si;
2793
2794 return true;
2795
2796 case SIGN_EXTEND:
2797 /* A sign extend from SImode to DImode in 64-bit mode is often
2798 zero instructions, because the result can often be used
2799 directly by another instruction; we'll call it one. */
2800 if (TARGET_64BIT && mode == DImode
2801 && GET_MODE (XEXP (x, 0)) == SImode)
2802 *total = COSTS_N_INSNS (1);
2803 else
2804 *total = COSTS_N_INSNS (2);
2805 return true;
2806
2807 case ZERO_EXTEND:
2808 if (TARGET_64BIT && mode == DImode
2809 && GET_MODE (XEXP (x, 0)) == SImode)
2810 *total = COSTS_N_INSNS (2);
2811 else
2812 *total = COSTS_N_INSNS (1);
2813 return true;
2814
2815 case FLOAT:
2816 case UNSIGNED_FLOAT:
2817 case FIX:
2818 case FLOAT_EXTEND:
2819 case FLOAT_TRUNCATE:
2820 case SQRT:
2821 *total = mips_cost->fp_add;
2822 return true;
2823
2824 default:
2825 return false;
2826 }
2827 }
2828
2829 /* Provide the costs of an addressing mode that contains ADDR.
2830 If ADDR is not a valid address, its cost is irrelevant. */
2831
2832 static int
2833 mips_address_cost (rtx addr)
2834 {
2835 return mips_address_insns (addr, SImode);
2836 }
2837 \f
2838 /* Return one word of double-word value OP, taking into account the fixed
2839 endianness of certain registers. HIGH_P is true to select the high part,
2840 false to select the low part. */
2841
2842 rtx
2843 mips_subword (rtx op, int high_p)
2844 {
2845 unsigned int byte;
2846 enum machine_mode mode;
2847
2848 mode = GET_MODE (op);
2849 if (mode == VOIDmode)
2850 mode = DImode;
2851
2852 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2853 byte = UNITS_PER_WORD;
2854 else
2855 byte = 0;
2856
2857 if (REG_P (op))
2858 {
2859 if (FP_REG_P (REGNO (op)))
2860 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2861 if (ACC_HI_REG_P (REGNO (op)))
2862 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2863 }
2864
2865 if (MEM_P (op))
2866 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2867
2868 return simplify_gen_subreg (word_mode, op, mode, byte);
2869 }
2870
2871
2872 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2873
2874 bool
2875 mips_split_64bit_move_p (rtx dest, rtx src)
2876 {
2877 if (TARGET_64BIT)
2878 return false;
2879
2880 /* FP->FP moves can be done in a single instruction. */
2881 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2882 return false;
2883
2884 /* Check for floating-point loads and stores. They can be done using
2885 ldc1 and sdc1 on MIPS II and above. */
2886 if (mips_isa > 1)
2887 {
2888 if (FP_REG_RTX_P (dest) && MEM_P (src))
2889 return false;
2890 if (FP_REG_RTX_P (src) && MEM_P (dest))
2891 return false;
2892 }
2893 return true;
2894 }
2895
2896
2897 /* Split a 64-bit move from SRC to DEST assuming that
2898 mips_split_64bit_move_p holds.
2899
2900 Moves into and out of FPRs cause some difficulty here. Such moves
2901 will always be DFmode, since paired FPRs are not allowed to store
2902 DImode values. The most natural representation would be two separate
2903 32-bit moves, such as:
2904
2905 (set (reg:SI $f0) (mem:SI ...))
2906 (set (reg:SI $f1) (mem:SI ...))
2907
2908 However, the second insn is invalid because odd-numbered FPRs are
2909 not allowed to store independent values. Use the patterns load_df_low,
2910 load_df_high and store_df_high instead. */
2911
2912 void
2913 mips_split_64bit_move (rtx dest, rtx src)
2914 {
2915 if (FP_REG_RTX_P (dest))
2916 {
2917 /* Loading an FPR from memory or from GPRs. */
2918 if (ISA_HAS_MXHC1)
2919 {
2920 dest = gen_lowpart (DFmode, dest);
2921 emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
2922 emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
2923 copy_rtx (dest)));
2924 }
2925 else
2926 {
2927 emit_insn (gen_load_df_low (copy_rtx (dest),
2928 mips_subword (src, 0)));
2929 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2930 copy_rtx (dest)));
2931 }
2932 }
2933 else if (FP_REG_RTX_P (src))
2934 {
2935 /* Storing an FPR into memory or GPRs. */
2936 if (ISA_HAS_MXHC1)
2937 {
2938 src = gen_lowpart (DFmode, src);
2939 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2940 emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
2941 }
2942 else
2943 {
2944 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2945 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2946 }
2947 }
2948 else
2949 {
2950 /* The operation can be split into two normal moves. Decide in
2951 which order to do them. */
2952 rtx low_dest;
2953
2954 low_dest = mips_subword (dest, 0);
2955 if (REG_P (low_dest)
2956 && reg_overlap_mentioned_p (low_dest, src))
2957 {
2958 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2959 emit_move_insn (low_dest, mips_subword (src, 0));
2960 }
2961 else
2962 {
2963 emit_move_insn (low_dest, mips_subword (src, 0));
2964 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2965 }
2966 }
2967 }
2968 \f
2969 /* Return the appropriate instructions to move SRC into DEST. Assume
2970 that SRC is operand 1 and DEST is operand 0. */
2971
2972 const char *
2973 mips_output_move (rtx dest, rtx src)
2974 {
2975 enum rtx_code dest_code, src_code;
2976 bool dbl_p;
2977
2978 dest_code = GET_CODE (dest);
2979 src_code = GET_CODE (src);
2980 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2981
2982 if (dbl_p && mips_split_64bit_move_p (dest, src))
2983 return "#";
2984
2985 if ((src_code == REG && GP_REG_P (REGNO (src)))
2986 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2987 {
2988 if (dest_code == REG)
2989 {
2990 if (GP_REG_P (REGNO (dest)))
2991 return "move\t%0,%z1";
2992
2993 if (MD_REG_P (REGNO (dest)))
2994 return "mt%0\t%z1";
2995
2996 if (DSP_ACC_REG_P (REGNO (dest)))
2997 {
2998 static char retval[] = "mt__\t%z1,%q0";
2999 retval[2] = reg_names[REGNO (dest)][4];
3000 retval[3] = reg_names[REGNO (dest)][5];
3001 return retval;
3002 }
3003
3004 if (FP_REG_P (REGNO (dest)))
3005 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3006
3007 if (ALL_COP_REG_P (REGNO (dest)))
3008 {
3009 static char retval[] = "dmtc_\t%z1,%0";
3010
3011 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3012 return (dbl_p ? retval : retval + 1);
3013 }
3014 }
3015 if (dest_code == MEM)
3016 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
3017 }
3018 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3019 {
3020 if (src_code == REG)
3021 {
3022 if (DSP_ACC_REG_P (REGNO (src)))
3023 {
3024 static char retval[] = "mf__\t%0,%q1";
3025 retval[2] = reg_names[REGNO (src)][4];
3026 retval[3] = reg_names[REGNO (src)][5];
3027 return retval;
3028 }
3029
3030 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3031 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3032
3033 if (FP_REG_P (REGNO (src)))
3034 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3035
3036 if (ALL_COP_REG_P (REGNO (src)))
3037 {
3038 static char retval[] = "dmfc_\t%0,%1";
3039
3040 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3041 return (dbl_p ? retval : retval + 1);
3042 }
3043 }
3044
3045 if (src_code == MEM)
3046 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
3047
3048 if (src_code == CONST_INT)
3049 {
3050 /* Don't use the X format, because that will give out of
3051 range numbers for 64-bit hosts and 32-bit targets. */
3052 if (!TARGET_MIPS16)
3053 return "li\t%0,%1\t\t\t# %X1";
3054
3055 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3056 return "li\t%0,%1";
3057
3058 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3059 return "#";
3060 }
3061
3062 if (src_code == HIGH)
3063 return "lui\t%0,%h1";
3064
3065 if (CONST_GP_P (src))
3066 return "move\t%0,%1";
3067
3068 if (symbolic_operand (src, VOIDmode))
3069 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
3070 }
3071 if (src_code == REG && FP_REG_P (REGNO (src)))
3072 {
3073 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3074 {
3075 if (GET_MODE (dest) == V2SFmode)
3076 return "mov.ps\t%0,%1";
3077 else
3078 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3079 }
3080
3081 if (dest_code == MEM)
3082 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3083 }
3084 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3085 {
3086 if (src_code == MEM)
3087 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3088 }
3089 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3090 {
3091 static char retval[] = "l_c_\t%0,%1";
3092
3093 retval[1] = (dbl_p ? 'd' : 'w');
3094 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3095 return retval;
3096 }
3097 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3098 {
3099 static char retval[] = "s_c_\t%1,%0";
3100
3101 retval[1] = (dbl_p ? 'd' : 'w');
3102 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3103 return retval;
3104 }
3105 gcc_unreachable ();
3106 }
3107 \f
3108 /* Restore $gp from its save slot. Valid only when using o32 or
3109 o64 abicalls. */
3110
3111 void
3112 mips_restore_gp (void)
3113 {
3114 rtx address, slot;
3115
3116 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
3117
3118 address = mips_add_offset (pic_offset_table_rtx,
3119 frame_pointer_needed
3120 ? hard_frame_pointer_rtx
3121 : stack_pointer_rtx,
3122 current_function_outgoing_args_size);
3123 slot = gen_rtx_MEM (Pmode, address);
3124
3125 emit_move_insn (pic_offset_table_rtx, slot);
3126 if (!TARGET_EXPLICIT_RELOCS)
3127 emit_insn (gen_blockage ());
3128 }
3129 \f
3130 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3131
3132 static void
3133 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3134 {
3135 emit_insn (gen_rtx_SET (VOIDmode, target,
3136 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3137 }
3138
3139 /* Return true if CMP1 is a suitable second operand for relational
3140 operator CODE. See also the *sCC patterns in mips.md. */
3141
3142 static bool
3143 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3144 {
3145 switch (code)
3146 {
3147 case GT:
3148 case GTU:
3149 return reg_or_0_operand (cmp1, VOIDmode);
3150
3151 case GE:
3152 case GEU:
3153 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3154
3155 case LT:
3156 case LTU:
3157 return arith_operand (cmp1, VOIDmode);
3158
3159 case LE:
3160 return sle_operand (cmp1, VOIDmode);
3161
3162 case LEU:
3163 return sleu_operand (cmp1, VOIDmode);
3164
3165 default:
3166 gcc_unreachable ();
3167 }
3168 }
3169
3170 /* Canonicalize LE or LEU comparisons into LT comparisons when
3171 possible to avoid extra instructions or inverting the
3172 comparison. */
3173
3174 static bool
3175 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3176 enum machine_mode mode)
3177 {
3178 HOST_WIDE_INT original, plus_one;
3179
3180 if (GET_CODE (*cmp1) != CONST_INT)
3181 return false;
3182
3183 original = INTVAL (*cmp1);
3184 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3185
3186 switch (*code)
3187 {
3188 case LE:
3189 if (original < plus_one)
3190 {
3191 *code = LT;
3192 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3193 return true;
3194 }
3195 break;
3196
3197 case LEU:
3198 if (plus_one != 0)
3199 {
3200 *code = LTU;
3201 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3202 return true;
3203 }
3204 break;
3205
3206 default:
3207 return false;
3208 }
3209
3210 return false;
3211
3212 }
3213
3214 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3215 result in TARGET. CMP0 and TARGET are register_operands that have
3216 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3217 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3218
3219 static void
3220 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3221 rtx target, rtx cmp0, rtx cmp1)
3222 {
3223 /* First see if there is a MIPS instruction that can do this operation
3224 with CMP1 in its current form. If not, try to canonicalize the
3225 comparison to LT. If that fails, try doing the same for the
3226 inverse operation. If that also fails, force CMP1 into a register
3227 and try again. */
3228 if (mips_relational_operand_ok_p (code, cmp1))
3229 mips_emit_binary (code, target, cmp0, cmp1);
3230 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3231 mips_emit_binary (code, target, cmp0, cmp1);
3232 else
3233 {
3234 enum rtx_code inv_code = reverse_condition (code);
3235 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3236 {
3237 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3238 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3239 }
3240 else if (invert_ptr == 0)
3241 {
3242 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3243 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3244 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3245 }
3246 else
3247 {
3248 *invert_ptr = !*invert_ptr;
3249 mips_emit_binary (inv_code, target, cmp0, cmp1);
3250 }
3251 }
3252 }
3253
3254 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3255 The register will have the same mode as CMP0. */
3256
3257 static rtx
3258 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3259 {
3260 if (cmp1 == const0_rtx)
3261 return cmp0;
3262
3263 if (uns_arith_operand (cmp1, VOIDmode))
3264 return expand_binop (GET_MODE (cmp0), xor_optab,
3265 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3266
3267 return expand_binop (GET_MODE (cmp0), sub_optab,
3268 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3269 }
3270
3271 /* Convert *CODE into a code that can be used in a floating-point
3272 scc instruction (c.<cond>.<fmt>). Return true if the values of
3273 the condition code registers will be inverted, with 0 indicating
3274 that the condition holds. */
3275
3276 static bool
3277 mips_reverse_fp_cond_p (enum rtx_code *code)
3278 {
3279 switch (*code)
3280 {
3281 case NE:
3282 case LTGT:
3283 case ORDERED:
3284 *code = reverse_condition_maybe_unordered (*code);
3285 return true;
3286
3287 default:
3288 return false;
3289 }
3290 }
3291
3292 /* Convert a comparison into something that can be used in a branch or
3293 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3294 being compared and *CODE is the code used to compare them.
3295
3296 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3297 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3298 otherwise any standard branch condition can be used. The standard branch
3299 conditions are:
3300
3301 - EQ/NE between two registers.
3302 - any comparison between a register and zero. */
3303
3304 static void
3305 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3306 {
3307 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3308 {
3309 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3310 {
3311 *op0 = cmp_operands[0];
3312 *op1 = cmp_operands[1];
3313 }
3314 else if (*code == EQ || *code == NE)
3315 {
3316 if (need_eq_ne_p)
3317 {
3318 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3319 *op1 = const0_rtx;
3320 }
3321 else
3322 {
3323 *op0 = cmp_operands[0];
3324 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3325 }
3326 }
3327 else
3328 {
3329 /* The comparison needs a separate scc instruction. Store the
3330 result of the scc in *OP0 and compare it against zero. */
3331 bool invert = false;
3332 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3333 *op1 = const0_rtx;
3334 mips_emit_int_relational (*code, &invert, *op0,
3335 cmp_operands[0], cmp_operands[1]);
3336 *code = (invert ? EQ : NE);
3337 }
3338 }
3339 else
3340 {
3341 enum rtx_code cmp_code;
3342
3343 /* Floating-point tests use a separate c.cond.fmt comparison to
3344 set a condition code register. The branch or conditional move
3345 will then compare that register against zero.
3346
3347 Set CMP_CODE to the code of the comparison instruction and
3348 *CODE to the code that the branch or move should use. */
3349 cmp_code = *code;
3350 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3351 *op0 = (ISA_HAS_8CC
3352 ? gen_reg_rtx (CCmode)
3353 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3354 *op1 = const0_rtx;
3355 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3356 }
3357 }
3358 \f
3359 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3360 Store the result in TARGET and return true if successful.
3361
3362 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3363
3364 bool
3365 mips_emit_scc (enum rtx_code code, rtx target)
3366 {
3367 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3368 return false;
3369
3370 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3371 if (code == EQ || code == NE)
3372 {
3373 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3374 mips_emit_binary (code, target, zie, const0_rtx);
3375 }
3376 else
3377 mips_emit_int_relational (code, 0, target,
3378 cmp_operands[0], cmp_operands[1]);
3379 return true;
3380 }
3381
3382 /* Emit the common code for doing conditional branches.
3383 operand[0] is the label to jump to.
3384 The comparison operands are saved away by cmp{si,di,sf,df}. */
3385
3386 void
3387 gen_conditional_branch (rtx *operands, enum rtx_code code)
3388 {
3389 rtx op0, op1, condition;
3390
3391 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3392 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3393 emit_jump_insn (gen_condjump (condition, operands[0]));
3394 }
3395
3396 /* Implement:
3397
3398 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3399 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3400
3401 void
3402 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3403 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3404 {
3405 rtx cmp_result;
3406 bool reversed_p;
3407
3408 reversed_p = mips_reverse_fp_cond_p (&cond);
3409 cmp_result = gen_reg_rtx (CCV2mode);
3410 emit_insn (gen_scc_ps (cmp_result,
3411 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3412 if (reversed_p)
3413 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3414 cmp_result));
3415 else
3416 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3417 cmp_result));
3418 }
3419
3420 /* Emit the common code for conditional moves. OPERANDS is the array
3421 of operands passed to the conditional move define_expand. */
3422
3423 void
3424 gen_conditional_move (rtx *operands)
3425 {
3426 enum rtx_code code;
3427 rtx op0, op1;
3428
3429 code = GET_CODE (operands[1]);
3430 mips_emit_compare (&code, &op0, &op1, true);
3431 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3432 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3433 gen_rtx_fmt_ee (code,
3434 GET_MODE (op0),
3435 op0, op1),
3436 operands[2], operands[3])));
3437 }
3438
3439 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3440 the conditional_trap expander. */
3441
3442 void
3443 mips_gen_conditional_trap (rtx *operands)
3444 {
3445 rtx op0, op1;
3446 enum rtx_code cmp_code = GET_CODE (operands[0]);
3447 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3448
3449 /* MIPS conditional trap machine instructions don't have GT or LE
3450 flavors, so we must invert the comparison and convert to LT and
3451 GE, respectively. */
3452 switch (cmp_code)
3453 {
3454 case GT: cmp_code = LT; break;
3455 case LE: cmp_code = GE; break;
3456 case GTU: cmp_code = LTU; break;
3457 case LEU: cmp_code = GEU; break;
3458 default: break;
3459 }
3460 if (cmp_code == GET_CODE (operands[0]))
3461 {
3462 op0 = cmp_operands[0];
3463 op1 = cmp_operands[1];
3464 }
3465 else
3466 {
3467 op0 = cmp_operands[1];
3468 op1 = cmp_operands[0];
3469 }
3470 op0 = force_reg (mode, op0);
3471 if (!arith_operand (op1, mode))
3472 op1 = force_reg (mode, op1);
3473
3474 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3475 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3476 operands[1]));
3477 }
3478 \f
3479 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
3480
3481 static bool
3482 mips_ok_for_lazy_binding_p (rtx x)
3483 {
3484 return (TARGET_USE_GOT
3485 && GET_CODE (x) == SYMBOL_REF
3486 && !mips_symbol_binds_local_p (x));
3487 }
3488
3489 /* Load function address ADDR into register DEST. SIBCALL_P is true
3490 if the address is needed for a sibling call. */
3491
3492 static void
3493 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3494 {
3495 /* If we're generating PIC, and this call is to a global function,
3496 try to allow its address to be resolved lazily. This isn't
3497 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
3498 to the stub would be our caller's gp, not ours. */
3499 if (TARGET_EXPLICIT_RELOCS
3500 && !(sibcall_p && TARGET_CALL_SAVED_GP)
3501 && mips_ok_for_lazy_binding_p (addr))
3502 {
3503 rtx high, lo_sum_symbol;
3504
3505 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3506 addr, SYMBOL_GOTOFF_CALL);
3507 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3508 if (Pmode == SImode)
3509 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3510 else
3511 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3512 }
3513 else
3514 emit_move_insn (dest, addr);
3515 }
3516
3517
3518 /* Expand a call or call_value instruction. RESULT is where the
3519 result will go (null for calls), ADDR is the address of the
3520 function, ARGS_SIZE is the size of the arguments and AUX is
3521 the value passed to us by mips_function_arg. SIBCALL_P is true
3522 if we are expanding a sibling call, false if we're expanding
3523 a normal call. */
3524
3525 void
3526 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3527 {
3528 rtx orig_addr, pattern, insn;
3529
3530 orig_addr = addr;
3531 if (!call_insn_operand (addr, VOIDmode))
3532 {
3533 addr = gen_reg_rtx (Pmode);
3534 mips_load_call_address (addr, orig_addr, sibcall_p);
3535 }
3536
3537 if (mips16_hard_float
3538 && build_mips16_call_stub (result, addr, args_size,
3539 aux == 0 ? 0 : (int) GET_MODE (aux)))
3540 return;
3541
3542 if (result == 0)
3543 pattern = (sibcall_p
3544 ? gen_sibcall_internal (addr, args_size)
3545 : gen_call_internal (addr, args_size));
3546 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3547 {
3548 rtx reg1, reg2;
3549
3550 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3551 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3552 pattern =
3553 (sibcall_p
3554 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3555 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3556 }
3557 else
3558 pattern = (sibcall_p
3559 ? gen_sibcall_value_internal (result, addr, args_size)
3560 : gen_call_value_internal (result, addr, args_size));
3561
3562 insn = emit_call_insn (pattern);
3563
3564 /* Lazy-binding stubs require $gp to be valid on entry. */
3565 if (mips_ok_for_lazy_binding_p (orig_addr))
3566 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3567 }
3568
3569
3570 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3571
3572 static bool
3573 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3574 tree exp ATTRIBUTE_UNUSED)
3575 {
3576 return TARGET_SIBCALLS;
3577 }
3578 \f
3579 /* Emit code to move general operand SRC into condition-code
3580 register DEST. SCRATCH is a scratch TFmode float register.
3581 The sequence is:
3582
3583 FP1 = SRC
3584 FP2 = 0.0f
3585 DEST = FP2 < FP1
3586
3587 where FP1 and FP2 are single-precision float registers
3588 taken from SCRATCH. */
3589
3590 void
3591 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3592 {
3593 rtx fp1, fp2;
3594
3595 /* Change the source to SFmode. */
3596 if (MEM_P (src))
3597 src = adjust_address (src, SFmode, 0);
3598 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3599 src = gen_rtx_REG (SFmode, true_regnum (src));
3600
3601 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3602 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
3603
3604 emit_move_insn (copy_rtx (fp1), src);
3605 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3606 emit_insn (gen_slt_sf (dest, fp2, fp1));
3607 }
3608 \f
3609 /* Emit code to change the current function's return address to
3610 ADDRESS. SCRATCH is available as a scratch register, if needed.
3611 ADDRESS and SCRATCH are both word-mode GPRs. */
3612
3613 void
3614 mips_set_return_address (rtx address, rtx scratch)
3615 {
3616 rtx slot_address;
3617
3618 compute_frame_size (get_frame_size ());
3619 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3620 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3621 cfun->machine->frame.gp_sp_offset);
3622
3623 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3624 }
3625 \f
3626 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3627 Assume that the areas do not overlap. */
3628
3629 static void
3630 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3631 {
3632 HOST_WIDE_INT offset, delta;
3633 unsigned HOST_WIDE_INT bits;
3634 int i;
3635 enum machine_mode mode;
3636 rtx *regs;
3637
3638 /* Work out how many bits to move at a time. If both operands have
3639 half-word alignment, it is usually better to move in half words.
3640 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3641 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3642 Otherwise move word-sized chunks. */
3643 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3644 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3645 bits = BITS_PER_WORD / 2;
3646 else
3647 bits = BITS_PER_WORD;
3648
3649 mode = mode_for_size (bits, MODE_INT, 0);
3650 delta = bits / BITS_PER_UNIT;
3651
3652 /* Allocate a buffer for the temporary registers. */
3653 regs = alloca (sizeof (rtx) * length / delta);
3654
3655 /* Load as many BITS-sized chunks as possible. Use a normal load if
3656 the source has enough alignment, otherwise use left/right pairs. */
3657 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3658 {
3659 regs[i] = gen_reg_rtx (mode);
3660 if (MEM_ALIGN (src) >= bits)
3661 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3662 else
3663 {
3664 rtx part = adjust_address (src, BLKmode, offset);
3665 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3666 gcc_unreachable ();
3667 }
3668 }
3669
3670 /* Copy the chunks to the destination. */
3671 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3672 if (MEM_ALIGN (dest) >= bits)
3673 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3674 else
3675 {
3676 rtx part = adjust_address (dest, BLKmode, offset);
3677 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3678 gcc_unreachable ();
3679 }
3680
3681 /* Mop up any left-over bytes. */
3682 if (offset < length)
3683 {
3684 src = adjust_address (src, BLKmode, offset);
3685 dest = adjust_address (dest, BLKmode, offset);
3686 move_by_pieces (dest, src, length - offset,
3687 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3688 }
3689 }
3690 \f
3691 #define MAX_MOVE_REGS 4
3692 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3693
3694
3695 /* Helper function for doing a loop-based block operation on memory
3696 reference MEM. Each iteration of the loop will operate on LENGTH
3697 bytes of MEM.
3698
3699 Create a new base register for use within the loop and point it to
3700 the start of MEM. Create a new memory reference that uses this
3701 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3702
3703 static void
3704 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3705 rtx *loop_reg, rtx *loop_mem)
3706 {
3707 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3708
3709 /* Although the new mem does not refer to a known location,
3710 it does keep up to LENGTH bytes of alignment. */
3711 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3712 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3713 }
3714
3715
3716 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3717 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3718 memory regions do not overlap. */
3719
3720 static void
3721 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3722 {
3723 rtx label, src_reg, dest_reg, final_src;
3724 HOST_WIDE_INT leftover;
3725
3726 leftover = length % MAX_MOVE_BYTES;
3727 length -= leftover;
3728
3729 /* Create registers and memory references for use within the loop. */
3730 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3731 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3732
3733 /* Calculate the value that SRC_REG should have after the last iteration
3734 of the loop. */
3735 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3736 0, 0, OPTAB_WIDEN);
3737
3738 /* Emit the start of the loop. */
3739 label = gen_label_rtx ();
3740 emit_label (label);
3741
3742 /* Emit the loop body. */
3743 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3744
3745 /* Move on to the next block. */
3746 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3747 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3748
3749 /* Emit the loop condition. */
3750 if (Pmode == DImode)
3751 emit_insn (gen_cmpdi (src_reg, final_src));
3752 else
3753 emit_insn (gen_cmpsi (src_reg, final_src));
3754 emit_jump_insn (gen_bne (label));
3755
3756 /* Mop up any left-over bytes. */
3757 if (leftover)
3758 mips_block_move_straight (dest, src, leftover);
3759 }
3760 \f
3761 /* Expand a movmemsi instruction. */
3762
3763 bool
3764 mips_expand_block_move (rtx dest, rtx src, rtx length)
3765 {
3766 if (GET_CODE (length) == CONST_INT)
3767 {
3768 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3769 {
3770 mips_block_move_straight (dest, src, INTVAL (length));
3771 return true;
3772 }
3773 else if (optimize)
3774 {
3775 mips_block_move_loop (dest, src, INTVAL (length));
3776 return true;
3777 }
3778 }
3779 return false;
3780 }
3781 \f
3782 /* Argument support functions. */
3783
3784 /* Initialize CUMULATIVE_ARGS for a function. */
3785
3786 void
3787 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3788 rtx libname ATTRIBUTE_UNUSED)
3789 {
3790 static CUMULATIVE_ARGS zero_cum;
3791 tree param, next_param;
3792
3793 *cum = zero_cum;
3794 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3795
3796 /* Determine if this function has variable arguments. This is
3797 indicated by the last argument being 'void_type_mode' if there
3798 are no variable arguments. The standard MIPS calling sequence
3799 passes all arguments in the general purpose registers in this case. */
3800
3801 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3802 param != 0; param = next_param)
3803 {
3804 next_param = TREE_CHAIN (param);
3805 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3806 cum->gp_reg_found = 1;
3807 }
3808 }
3809
3810
3811 /* Fill INFO with information about a single argument. CUM is the
3812 cumulative state for earlier arguments. MODE is the mode of this
3813 argument and TYPE is its type (if known). NAMED is true if this
3814 is a named (fixed) argument rather than a variable one. */
3815
3816 static void
3817 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3818 tree type, int named, struct mips_arg_info *info)
3819 {
3820 bool doubleword_aligned_p;
3821 unsigned int num_bytes, num_words, max_regs;
3822
3823 /* Work out the size of the argument. */
3824 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3825 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3826
3827 /* Decide whether it should go in a floating-point register, assuming
3828 one is free. Later code checks for availability.
3829
3830 The checks against UNITS_PER_FPVALUE handle the soft-float and
3831 single-float cases. */
3832 switch (mips_abi)
3833 {
3834 case ABI_EABI:
3835 /* The EABI conventions have traditionally been defined in terms
3836 of TYPE_MODE, regardless of the actual type. */
3837 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3838 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3839 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3840 break;
3841
3842 case ABI_32:
3843 case ABI_O64:
3844 /* Only leading floating-point scalars are passed in
3845 floating-point registers. We also handle vector floats the same
3846 say, which is OK because they are not covered by the standard ABI. */
3847 info->fpr_p = (!cum->gp_reg_found
3848 && cum->arg_number < 2
3849 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3850 || VECTOR_FLOAT_TYPE_P (type))
3851 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3852 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3853 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3854 break;
3855
3856 case ABI_N32:
3857 case ABI_64:
3858 /* Scalar and complex floating-point types are passed in
3859 floating-point registers. */
3860 info->fpr_p = (named
3861 && (type == 0 || FLOAT_TYPE_P (type))
3862 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3863 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3864 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3865 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3866
3867 /* ??? According to the ABI documentation, the real and imaginary
3868 parts of complex floats should be passed in individual registers.
3869 The real and imaginary parts of stack arguments are supposed
3870 to be contiguous and there should be an extra word of padding
3871 at the end.
3872
3873 This has two problems. First, it makes it impossible to use a
3874 single "void *" va_list type, since register and stack arguments
3875 are passed differently. (At the time of writing, MIPSpro cannot
3876 handle complex float varargs correctly.) Second, it's unclear
3877 what should happen when there is only one register free.
3878
3879 For now, we assume that named complex floats should go into FPRs
3880 if there are two FPRs free, otherwise they should be passed in the
3881 same way as a struct containing two floats. */
3882 if (info->fpr_p
3883 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3884 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3885 {
3886 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3887 info->fpr_p = false;
3888 else
3889 num_words = 2;
3890 }
3891 break;
3892
3893 default:
3894 gcc_unreachable ();
3895 }
3896
3897 /* See whether the argument has doubleword alignment. */
3898 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3899
3900 /* Set REG_OFFSET to the register count we're interested in.
3901 The EABI allocates the floating-point registers separately,
3902 but the other ABIs allocate them like integer registers. */
3903 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3904 ? cum->num_fprs
3905 : cum->num_gprs);
3906
3907 /* Advance to an even register if the argument is doubleword-aligned. */
3908 if (doubleword_aligned_p)
3909 info->reg_offset += info->reg_offset & 1;
3910
3911 /* Work out the offset of a stack argument. */
3912 info->stack_offset = cum->stack_words;
3913 if (doubleword_aligned_p)
3914 info->stack_offset += info->stack_offset & 1;
3915
3916 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3917
3918 /* Partition the argument between registers and stack. */
3919 info->reg_words = MIN (num_words, max_regs);
3920 info->stack_words = num_words - info->reg_words;
3921 }
3922
3923
3924 /* INFO describes an argument that is passed in a single-register value.
3925 Return the register it uses, assuming that FPRs are available if
3926 HARD_FLOAT_P. */
3927
3928 static unsigned int
3929 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
3930 {
3931 if (!info->fpr_p || !hard_float_p)
3932 return GP_ARG_FIRST + info->reg_offset;
3933 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
3934 /* In o32, the second argument is always passed in $f14
3935 for TARGET_DOUBLE_FLOAT, regardless of whether the
3936 first argument was a word or doubleword. */
3937 return FP_ARG_FIRST + 2;
3938 else
3939 return FP_ARG_FIRST + info->reg_offset;
3940 }
3941
3942 /* Implement FUNCTION_ARG_ADVANCE. */
3943
3944 void
3945 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3946 tree type, int named)
3947 {
3948 struct mips_arg_info info;
3949
3950 mips_arg_info (cum, mode, type, named, &info);
3951
3952 if (!info.fpr_p)
3953 cum->gp_reg_found = true;
3954
3955 /* See the comment above the cumulative args structure in mips.h
3956 for an explanation of what this code does. It assumes the O32
3957 ABI, which passes at most 2 arguments in float registers. */
3958 if (cum->arg_number < 2 && info.fpr_p)
3959 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
3960
3961 if (mips_abi != ABI_EABI || !info.fpr_p)
3962 cum->num_gprs = info.reg_offset + info.reg_words;
3963 else if (info.reg_words > 0)
3964 cum->num_fprs += MAX_FPRS_PER_FMT;
3965
3966 if (info.stack_words > 0)
3967 cum->stack_words = info.stack_offset + info.stack_words;
3968
3969 cum->arg_number++;
3970 }
3971
3972 /* Implement FUNCTION_ARG. */
3973
3974 struct rtx_def *
3975 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3976 tree type, int named)
3977 {
3978 struct mips_arg_info info;
3979
3980 /* We will be called with a mode of VOIDmode after the last argument
3981 has been seen. Whatever we return will be passed to the call
3982 insn. If we need a mips16 fp_code, return a REG with the code
3983 stored as the mode. */
3984 if (mode == VOIDmode)
3985 {
3986 if (TARGET_MIPS16 && cum->fp_code != 0)
3987 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3988
3989 else
3990 return 0;
3991 }
3992
3993 mips_arg_info (cum, mode, type, named, &info);
3994
3995 /* Return straight away if the whole argument is passed on the stack. */
3996 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3997 return 0;
3998
3999 if (type != 0
4000 && TREE_CODE (type) == RECORD_TYPE
4001 && TARGET_NEWABI
4002 && TYPE_SIZE_UNIT (type)
4003 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4004 && named)
4005 {
4006 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4007 structure contains a double in its entirety, then that 64-bit
4008 chunk is passed in a floating point register. */
4009 tree field;
4010
4011 /* First check to see if there is any such field. */
4012 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4013 if (TREE_CODE (field) == FIELD_DECL
4014 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4015 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4016 && host_integerp (bit_position (field), 0)
4017 && int_bit_position (field) % BITS_PER_WORD == 0)
4018 break;
4019
4020 if (field != 0)
4021 {
4022 /* Now handle the special case by returning a PARALLEL
4023 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4024 chunks are passed in registers. */
4025 unsigned int i;
4026 HOST_WIDE_INT bitpos;
4027 rtx ret;
4028
4029 /* assign_parms checks the mode of ENTRY_PARM, so we must
4030 use the actual mode here. */
4031 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4032
4033 bitpos = 0;
4034 field = TYPE_FIELDS (type);
4035 for (i = 0; i < info.reg_words; i++)
4036 {
4037 rtx reg;
4038
4039 for (; field; field = TREE_CHAIN (field))
4040 if (TREE_CODE (field) == FIELD_DECL
4041 && int_bit_position (field) >= bitpos)
4042 break;
4043
4044 if (field
4045 && int_bit_position (field) == bitpos
4046 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4047 && !TARGET_SOFT_FLOAT
4048 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4049 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4050 else
4051 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4052
4053 XVECEXP (ret, 0, i)
4054 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4055 GEN_INT (bitpos / BITS_PER_UNIT));
4056
4057 bitpos += BITS_PER_WORD;
4058 }
4059 return ret;
4060 }
4061 }
4062
4063 /* Handle the n32/n64 conventions for passing complex floating-point
4064 arguments in FPR pairs. The real part goes in the lower register
4065 and the imaginary part goes in the upper register. */
4066 if (TARGET_NEWABI
4067 && info.fpr_p
4068 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4069 {
4070 rtx real, imag;
4071 enum machine_mode inner;
4072 int reg;
4073
4074 inner = GET_MODE_INNER (mode);
4075 reg = FP_ARG_FIRST + info.reg_offset;
4076 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4077 {
4078 /* Real part in registers, imaginary part on stack. */
4079 gcc_assert (info.stack_words == info.reg_words);
4080 return gen_rtx_REG (inner, reg);
4081 }
4082 else
4083 {
4084 gcc_assert (info.stack_words == 0);
4085 real = gen_rtx_EXPR_LIST (VOIDmode,
4086 gen_rtx_REG (inner, reg),
4087 const0_rtx);
4088 imag = gen_rtx_EXPR_LIST (VOIDmode,
4089 gen_rtx_REG (inner,
4090 reg + info.reg_words / 2),
4091 GEN_INT (GET_MODE_SIZE (inner)));
4092 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4093 }
4094 }
4095
4096 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4097 }
4098
4099
4100 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4101
4102 static int
4103 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4104 enum machine_mode mode, tree type, bool named)
4105 {
4106 struct mips_arg_info info;
4107
4108 mips_arg_info (cum, mode, type, named, &info);
4109 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4110 }
4111
4112
4113 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4114 PARM_BOUNDARY bits of alignment, but will be given anything up
4115 to STACK_BOUNDARY bits if the type requires it. */
4116
4117 int
4118 function_arg_boundary (enum machine_mode mode, tree type)
4119 {
4120 unsigned int alignment;
4121
4122 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4123 if (alignment < PARM_BOUNDARY)
4124 alignment = PARM_BOUNDARY;
4125 if (alignment > STACK_BOUNDARY)
4126 alignment = STACK_BOUNDARY;
4127 return alignment;
4128 }
4129
4130 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4131 upward rather than downward. In other words, return true if the
4132 first byte of the stack slot has useful data, false if the last
4133 byte does. */
4134
4135 bool
4136 mips_pad_arg_upward (enum machine_mode mode, tree type)
4137 {
4138 /* On little-endian targets, the first byte of every stack argument
4139 is passed in the first byte of the stack slot. */
4140 if (!BYTES_BIG_ENDIAN)
4141 return true;
4142
4143 /* Otherwise, integral types are padded downward: the last byte of a
4144 stack argument is passed in the last byte of the stack slot. */
4145 if (type != 0
4146 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
4147 : GET_MODE_CLASS (mode) == MODE_INT)
4148 return false;
4149
4150 /* Big-endian o64 pads floating-point arguments downward. */
4151 if (mips_abi == ABI_O64)
4152 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4153 return false;
4154
4155 /* Other types are padded upward for o32, o64, n32 and n64. */
4156 if (mips_abi != ABI_EABI)
4157 return true;
4158
4159 /* Arguments smaller than a stack slot are padded downward. */
4160 if (mode != BLKmode)
4161 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4162 else
4163 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4164 }
4165
4166
4167 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4168 if the least significant byte of the register has useful data. Return
4169 the opposite if the most significant byte does. */
4170
4171 bool
4172 mips_pad_reg_upward (enum machine_mode mode, tree type)
4173 {
4174 /* No shifting is required for floating-point arguments. */
4175 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4176 return !BYTES_BIG_ENDIAN;
4177
4178 /* Otherwise, apply the same padding to register arguments as we do
4179 to stack arguments. */
4180 return mips_pad_arg_upward (mode, type);
4181 }
4182 \f
4183 static void
4184 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4185 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4186 int no_rtl)
4187 {
4188 CUMULATIVE_ARGS local_cum;
4189 int gp_saved, fp_saved;
4190
4191 /* The caller has advanced CUM up to, but not beyond, the last named
4192 argument. Advance a local copy of CUM past the last "real" named
4193 argument, to find out how many registers are left over. */
4194
4195 local_cum = *cum;
4196 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4197
4198 /* Found out how many registers we need to save. */
4199 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4200 fp_saved = (EABI_FLOAT_VARARGS_P
4201 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4202 : 0);
4203
4204 if (!no_rtl)
4205 {
4206 if (gp_saved > 0)
4207 {
4208 rtx ptr, mem;
4209
4210 ptr = plus_constant (virtual_incoming_args_rtx,
4211 REG_PARM_STACK_SPACE (cfun->decl)
4212 - gp_saved * UNITS_PER_WORD);
4213 mem = gen_rtx_MEM (BLKmode, ptr);
4214 set_mem_alias_set (mem, get_varargs_alias_set ());
4215
4216 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4217 mem, gp_saved);
4218 }
4219 if (fp_saved > 0)
4220 {
4221 /* We can't use move_block_from_reg, because it will use
4222 the wrong mode. */
4223 enum machine_mode mode;
4224 int off, i;
4225
4226 /* Set OFF to the offset from virtual_incoming_args_rtx of
4227 the first float register. The FP save area lies below
4228 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4229 off = -gp_saved * UNITS_PER_WORD;
4230 off &= ~(UNITS_PER_FPVALUE - 1);
4231 off -= fp_saved * UNITS_PER_FPREG;
4232
4233 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4234
4235 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4236 i += MAX_FPRS_PER_FMT)
4237 {
4238 rtx ptr, mem;
4239
4240 ptr = plus_constant (virtual_incoming_args_rtx, off);
4241 mem = gen_rtx_MEM (mode, ptr);
4242 set_mem_alias_set (mem, get_varargs_alias_set ());
4243 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4244 off += UNITS_PER_HWFPVALUE;
4245 }
4246 }
4247 }
4248 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4249 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4250 + fp_saved * UNITS_PER_FPREG);
4251 }
4252
4253 /* Create the va_list data type.
4254 We keep 3 pointers, and two offsets.
4255 Two pointers are to the overflow area, which starts at the CFA.
4256 One of these is constant, for addressing into the GPR save area below it.
4257 The other is advanced up the stack through the overflow region.
4258 The third pointer is to the GPR save area. Since the FPR save area
4259 is just below it, we can address FPR slots off this pointer.
4260 We also keep two one-byte offsets, which are to be subtracted from the
4261 constant pointers to yield addresses in the GPR and FPR save areas.
4262 These are downcounted as float or non-float arguments are used,
4263 and when they get to zero, the argument must be obtained from the
4264 overflow region.
4265 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4266 pointer is enough. It's started at the GPR save area, and is
4267 advanced, period.
4268 Note that the GPR save area is not constant size, due to optimization
4269 in the prologue. Hence, we can't use a design with two pointers
4270 and two offsets, although we could have designed this with two pointers
4271 and three offsets. */
4272
4273 static tree
4274 mips_build_builtin_va_list (void)
4275 {
4276 if (EABI_FLOAT_VARARGS_P)
4277 {
4278 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4279 tree array, index;
4280
4281 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4282
4283 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4284 ptr_type_node);
4285 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4286 ptr_type_node);
4287 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4288 ptr_type_node);
4289 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4290 unsigned_char_type_node);
4291 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4292 unsigned_char_type_node);
4293 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4294 warn on every user file. */
4295 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4296 array = build_array_type (unsigned_char_type_node,
4297 build_index_type (index));
4298 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4299
4300 DECL_FIELD_CONTEXT (f_ovfl) = record;
4301 DECL_FIELD_CONTEXT (f_gtop) = record;
4302 DECL_FIELD_CONTEXT (f_ftop) = record;
4303 DECL_FIELD_CONTEXT (f_goff) = record;
4304 DECL_FIELD_CONTEXT (f_foff) = record;
4305 DECL_FIELD_CONTEXT (f_res) = record;
4306
4307 TYPE_FIELDS (record) = f_ovfl;
4308 TREE_CHAIN (f_ovfl) = f_gtop;
4309 TREE_CHAIN (f_gtop) = f_ftop;
4310 TREE_CHAIN (f_ftop) = f_goff;
4311 TREE_CHAIN (f_goff) = f_foff;
4312 TREE_CHAIN (f_foff) = f_res;
4313
4314 layout_type (record);
4315 return record;
4316 }
4317 else if (TARGET_IRIX && TARGET_IRIX6)
4318 /* On IRIX 6, this type is 'char *'. */
4319 return build_pointer_type (char_type_node);
4320 else
4321 /* Otherwise, we use 'void *'. */
4322 return ptr_type_node;
4323 }
4324
4325 /* Implement va_start. */
4326
4327 void
4328 mips_va_start (tree valist, rtx nextarg)
4329 {
4330 if (EABI_FLOAT_VARARGS_P)
4331 {
4332 const CUMULATIVE_ARGS *cum;
4333 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4334 tree ovfl, gtop, ftop, goff, foff;
4335 tree t;
4336 int gpr_save_area_size;
4337 int fpr_save_area_size;
4338 int fpr_offset;
4339
4340 cum = &current_function_args_info;
4341 gpr_save_area_size
4342 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4343 fpr_save_area_size
4344 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4345
4346 f_ovfl = TYPE_FIELDS (va_list_type_node);
4347 f_gtop = TREE_CHAIN (f_ovfl);
4348 f_ftop = TREE_CHAIN (f_gtop);
4349 f_goff = TREE_CHAIN (f_ftop);
4350 f_foff = TREE_CHAIN (f_goff);
4351
4352 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4353 NULL_TREE);
4354 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4355 NULL_TREE);
4356 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4357 NULL_TREE);
4358 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4359 NULL_TREE);
4360 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4361 NULL_TREE);
4362
4363 /* Emit code to initialize OVFL, which points to the next varargs
4364 stack argument. CUM->STACK_WORDS gives the number of stack
4365 words used by named arguments. */
4366 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4367 if (cum->stack_words > 0)
4368 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4369 build_int_cst (NULL_TREE,
4370 cum->stack_words * UNITS_PER_WORD));
4371 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4372 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4373
4374 /* Emit code to initialize GTOP, the top of the GPR save area. */
4375 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4376 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4377 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4378
4379 /* Emit code to initialize FTOP, the top of the FPR save area.
4380 This address is gpr_save_area_bytes below GTOP, rounded
4381 down to the next fp-aligned boundary. */
4382 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4383 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4384 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4385 if (fpr_offset)
4386 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4387 build_int_cst (NULL_TREE, -fpr_offset));
4388 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4389 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4390
4391 /* Emit code to initialize GOFF, the offset from GTOP of the
4392 next GPR argument. */
4393 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4394 build_int_cst (NULL_TREE, gpr_save_area_size));
4395 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4396
4397 /* Likewise emit code to initialize FOFF, the offset from FTOP
4398 of the next FPR argument. */
4399 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4400 build_int_cst (NULL_TREE, fpr_save_area_size));
4401 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4402 }
4403 else
4404 {
4405 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4406 std_expand_builtin_va_start (valist, nextarg);
4407 }
4408 }
4409 \f
4410 /* Implement va_arg. */
4411
4412 static tree
4413 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4414 {
4415 HOST_WIDE_INT size, rsize;
4416 tree addr;
4417 bool indirect;
4418
4419 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4420
4421 if (indirect)
4422 type = build_pointer_type (type);
4423
4424 size = int_size_in_bytes (type);
4425 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4426
4427 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4428 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4429 else
4430 {
4431 /* Not a simple merged stack. */
4432
4433 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4434 tree ovfl, top, off, align;
4435 HOST_WIDE_INT osize;
4436 tree t, u;
4437
4438 f_ovfl = TYPE_FIELDS (va_list_type_node);
4439 f_gtop = TREE_CHAIN (f_ovfl);
4440 f_ftop = TREE_CHAIN (f_gtop);
4441 f_goff = TREE_CHAIN (f_ftop);
4442 f_foff = TREE_CHAIN (f_goff);
4443
4444 /* We maintain separate pointers and offsets for floating-point
4445 and integer arguments, but we need similar code in both cases.
4446 Let:
4447
4448 TOP be the top of the register save area;
4449 OFF be the offset from TOP of the next register;
4450 ADDR_RTX be the address of the argument;
4451 RSIZE be the number of bytes used to store the argument
4452 when it's in the register save area;
4453 OSIZE be the number of bytes used to store it when it's
4454 in the stack overflow area; and
4455 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4456
4457 The code we want is:
4458
4459 1: off &= -rsize; // round down
4460 2: if (off != 0)
4461 3: {
4462 4: addr_rtx = top - off;
4463 5: off -= rsize;
4464 6: }
4465 7: else
4466 8: {
4467 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4468 10: addr_rtx = ovfl + PADDING;
4469 11: ovfl += osize;
4470 14: }
4471
4472 [1] and [9] can sometimes be optimized away. */
4473
4474 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4475 NULL_TREE);
4476
4477 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4478 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4479 {
4480 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4481 NULL_TREE);
4482 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4483 NULL_TREE);
4484
4485 /* When floating-point registers are saved to the stack,
4486 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4487 of the float's precision. */
4488 rsize = UNITS_PER_HWFPVALUE;
4489
4490 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4491 (= PARM_BOUNDARY bits). This can be different from RSIZE
4492 in two cases:
4493
4494 (1) On 32-bit targets when TYPE is a structure such as:
4495
4496 struct s { float f; };
4497
4498 Such structures are passed in paired FPRs, so RSIZE
4499 will be 8 bytes. However, the structure only takes
4500 up 4 bytes of memory, so OSIZE will only be 4.
4501
4502 (2) In combinations such as -mgp64 -msingle-float
4503 -fshort-double. Doubles passed in registers
4504 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4505 but those passed on the stack take up
4506 UNITS_PER_WORD bytes. */
4507 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4508 }
4509 else
4510 {
4511 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4512 NULL_TREE);
4513 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4514 NULL_TREE);
4515 if (rsize > UNITS_PER_WORD)
4516 {
4517 /* [1] Emit code for: off &= -rsize. */
4518 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4519 build_int_cst (NULL_TREE, -rsize));
4520 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4521 gimplify_and_add (t, pre_p);
4522 }
4523 osize = rsize;
4524 }
4525
4526 /* [2] Emit code to branch if off == 0. */
4527 t = build2 (NE_EXPR, boolean_type_node, off,
4528 build_int_cst (TREE_TYPE (off), 0));
4529 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4530
4531 /* [5] Emit code for: off -= rsize. We do this as a form of
4532 post-increment not available to C. Also widen for the
4533 coming pointer arithmetic. */
4534 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4535 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4536 t = fold_convert (sizetype, t);
4537 t = fold_convert (TREE_TYPE (top), t);
4538
4539 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4540 the argument has RSIZE - SIZE bytes of leading padding. */
4541 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4542 if (BYTES_BIG_ENDIAN && rsize > size)
4543 {
4544 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4545 rsize - size));
4546 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4547 }
4548 COND_EXPR_THEN (addr) = t;
4549
4550 if (osize > UNITS_PER_WORD)
4551 {
4552 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4553 u = fold_convert (TREE_TYPE (ovfl),
4554 build_int_cst (NULL_TREE, osize - 1));
4555 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4556 u = fold_convert (TREE_TYPE (ovfl),
4557 build_int_cst (NULL_TREE, -osize));
4558 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4559 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4560 }
4561 else
4562 align = NULL;
4563
4564 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4565 post-increment ovfl by osize. On big-endian machines,
4566 the argument has OSIZE - SIZE bytes of leading padding. */
4567 u = fold_convert (TREE_TYPE (ovfl),
4568 build_int_cst (NULL_TREE, osize));
4569 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4570 if (BYTES_BIG_ENDIAN && osize > size)
4571 {
4572 u = fold_convert (TREE_TYPE (t),
4573 build_int_cst (NULL_TREE, osize - size));
4574 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4575 }
4576
4577 /* String [9] and [10,11] together. */
4578 if (align)
4579 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4580 COND_EXPR_ELSE (addr) = t;
4581
4582 addr = fold_convert (build_pointer_type (type), addr);
4583 addr = build_va_arg_indirect_ref (addr);
4584 }
4585
4586 if (indirect)
4587 addr = build_va_arg_indirect_ref (addr);
4588
4589 return addr;
4590 }
4591 \f
4592 /* Return true if it is possible to use left/right accesses for a
4593 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4594 returning true, update *OP, *LEFT and *RIGHT as follows:
4595
4596 *OP is a BLKmode reference to the whole field.
4597
4598 *LEFT is a QImode reference to the first byte if big endian or
4599 the last byte if little endian. This address can be used in the
4600 left-side instructions (lwl, swl, ldl, sdl).
4601
4602 *RIGHT is a QImode reference to the opposite end of the field and
4603 can be used in the patterning right-side instruction. */
4604
4605 static bool
4606 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4607 rtx *left, rtx *right)
4608 {
4609 rtx first, last;
4610
4611 /* Check that the operand really is a MEM. Not all the extv and
4612 extzv predicates are checked. */
4613 if (!MEM_P (*op))
4614 return false;
4615
4616 /* Check that the size is valid. */
4617 if (width != 32 && (!TARGET_64BIT || width != 64))
4618 return false;
4619
4620 /* We can only access byte-aligned values. Since we are always passed
4621 a reference to the first byte of the field, it is not necessary to
4622 do anything with BITPOS after this check. */
4623 if (bitpos % BITS_PER_UNIT != 0)
4624 return false;
4625
4626 /* Reject aligned bitfields: we want to use a normal load or store
4627 instead of a left/right pair. */
4628 if (MEM_ALIGN (*op) >= width)
4629 return false;
4630
4631 /* Adjust *OP to refer to the whole field. This also has the effect
4632 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4633 *op = adjust_address (*op, BLKmode, 0);
4634 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4635
4636 /* Get references to both ends of the field. We deliberately don't
4637 use the original QImode *OP for FIRST since the new BLKmode one
4638 might have a simpler address. */
4639 first = adjust_address (*op, QImode, 0);
4640 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4641
4642 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4643 be the upper word and RIGHT the lower word. */
4644 if (TARGET_BIG_ENDIAN)
4645 *left = first, *right = last;
4646 else
4647 *left = last, *right = first;
4648
4649 return true;
4650 }
4651
4652
4653 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4654 Return true on success. We only handle cases where zero_extract is
4655 equivalent to sign_extract. */
4656
4657 bool
4658 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4659 {
4660 rtx left, right, temp;
4661
4662 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4663 paradoxical word_mode subreg. This is the only case in which
4664 we allow the destination to be larger than the source. */
4665 if (GET_CODE (dest) == SUBREG
4666 && GET_MODE (dest) == DImode
4667 && SUBREG_BYTE (dest) == 0
4668 && GET_MODE (SUBREG_REG (dest)) == SImode)
4669 dest = SUBREG_REG (dest);
4670
4671 /* After the above adjustment, the destination must be the same
4672 width as the source. */
4673 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4674 return false;
4675
4676 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4677 return false;
4678
4679 temp = gen_reg_rtx (GET_MODE (dest));
4680 if (GET_MODE (dest) == DImode)
4681 {
4682 emit_insn (gen_mov_ldl (temp, src, left));
4683 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4684 }
4685 else
4686 {
4687 emit_insn (gen_mov_lwl (temp, src, left));
4688 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4689 }
4690 return true;
4691 }
4692
4693
4694 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4695 true on success. */
4696
4697 bool
4698 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4699 {
4700 rtx left, right;
4701 enum machine_mode mode;
4702
4703 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4704 return false;
4705
4706 mode = mode_for_size (width, MODE_INT, 0);
4707 src = gen_lowpart (mode, src);
4708
4709 if (mode == DImode)
4710 {
4711 emit_insn (gen_mov_sdl (dest, src, left));
4712 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4713 }
4714 else
4715 {
4716 emit_insn (gen_mov_swl (dest, src, left));
4717 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4718 }
4719 return true;
4720 }
4721
4722 /* Return true if X is a MEM with the same size as MODE. */
4723
4724 bool
4725 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4726 {
4727 rtx size;
4728
4729 if (!MEM_P (x))
4730 return false;
4731
4732 size = MEM_SIZE (x);
4733 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4734 }
4735
4736 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4737 source of an "ext" instruction or the destination of an "ins"
4738 instruction. OP must be a register operand and the following
4739 conditions must hold:
4740
4741 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4742 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4743 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4744
4745 Also reject lengths equal to a word as they are better handled
4746 by the move patterns. */
4747
4748 bool
4749 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4750 {
4751 HOST_WIDE_INT len, pos;
4752
4753 if (!ISA_HAS_EXT_INS
4754 || !register_operand (op, VOIDmode)
4755 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4756 return false;
4757
4758 len = INTVAL (size);
4759 pos = INTVAL (position);
4760
4761 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4762 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4763 return false;
4764
4765 return true;
4766 }
4767
4768 /* Set up globals to generate code for the ISA or processor
4769 described by INFO. */
4770
4771 static void
4772 mips_set_architecture (const struct mips_cpu_info *info)
4773 {
4774 if (info != 0)
4775 {
4776 mips_arch_info = info;
4777 mips_arch = info->cpu;
4778 mips_isa = info->isa;
4779 }
4780 }
4781
4782
4783 /* Likewise for tuning. */
4784
4785 static void
4786 mips_set_tune (const struct mips_cpu_info *info)
4787 {
4788 if (info != 0)
4789 {
4790 mips_tune_info = info;
4791 mips_tune = info->cpu;
4792 }
4793 }
4794
4795 /* Implement TARGET_HANDLE_OPTION. */
4796
4797 static bool
4798 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4799 {
4800 switch (code)
4801 {
4802 case OPT_mabi_:
4803 if (strcmp (arg, "32") == 0)
4804 mips_abi = ABI_32;
4805 else if (strcmp (arg, "o64") == 0)
4806 mips_abi = ABI_O64;
4807 else if (strcmp (arg, "n32") == 0)
4808 mips_abi = ABI_N32;
4809 else if (strcmp (arg, "64") == 0)
4810 mips_abi = ABI_64;
4811 else if (strcmp (arg, "eabi") == 0)
4812 mips_abi = ABI_EABI;
4813 else
4814 return false;
4815 return true;
4816
4817 case OPT_march_:
4818 case OPT_mtune_:
4819 return mips_parse_cpu (arg) != 0;
4820
4821 case OPT_mips:
4822 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4823 return mips_isa_info != 0;
4824
4825 case OPT_mno_flush_func:
4826 mips_cache_flush_func = NULL;
4827 return true;
4828
4829 default:
4830 return true;
4831 }
4832 }
4833
4834 /* Set up the threshold for data to go into the small data area, instead
4835 of the normal data area, and detect any conflicts in the switches. */
4836
4837 void
4838 override_options (void)
4839 {
4840 int i, start, regno;
4841 enum machine_mode mode;
4842
4843 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4844 SUBTARGET_OVERRIDE_OPTIONS;
4845 #endif
4846
4847 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4848
4849 /* The following code determines the architecture and register size.
4850 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4851 The GAS and GCC code should be kept in sync as much as possible. */
4852
4853 if (mips_arch_string != 0)
4854 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4855
4856 if (mips_isa_info != 0)
4857 {
4858 if (mips_arch_info == 0)
4859 mips_set_architecture (mips_isa_info);
4860 else if (mips_arch_info->isa != mips_isa_info->isa)
4861 error ("-%s conflicts with the other architecture options, "
4862 "which specify a %s processor",
4863 mips_isa_info->name,
4864 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4865 }
4866
4867 if (mips_arch_info == 0)
4868 {
4869 #ifdef MIPS_CPU_STRING_DEFAULT
4870 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4871 #else
4872 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4873 #endif
4874 }
4875
4876 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4877 error ("-march=%s is not compatible with the selected ABI",
4878 mips_arch_info->name);
4879
4880 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4881 if (mips_tune_string != 0)
4882 mips_set_tune (mips_parse_cpu (mips_tune_string));
4883
4884 if (mips_tune_info == 0)
4885 mips_set_tune (mips_arch_info);
4886
4887 /* Set cost structure for the processor. */
4888 if (optimize_size)
4889 mips_cost = &mips_rtx_cost_optimize_size;
4890 else
4891 mips_cost = &mips_rtx_cost_data[mips_tune];
4892
4893 if ((target_flags_explicit & MASK_64BIT) != 0)
4894 {
4895 /* The user specified the size of the integer registers. Make sure
4896 it agrees with the ABI and ISA. */
4897 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4898 error ("-mgp64 used with a 32-bit processor");
4899 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4900 error ("-mgp32 used with a 64-bit ABI");
4901 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4902 error ("-mgp64 used with a 32-bit ABI");
4903 }
4904 else
4905 {
4906 /* Infer the integer register size from the ABI and processor.
4907 Restrict ourselves to 32-bit registers if that's all the
4908 processor has, or if the ABI cannot handle 64-bit registers. */
4909 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4910 target_flags &= ~MASK_64BIT;
4911 else
4912 target_flags |= MASK_64BIT;
4913 }
4914
4915 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4916 {
4917 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4918 only one right answer here. */
4919 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4920 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4921 else if (!TARGET_64BIT && TARGET_FLOAT64
4922 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
4923 error ("-mgp32 and -mfp64 can only be combined if the target"
4924 " supports the mfhc1 and mthc1 instructions");
4925 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4926 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4927 }
4928 else
4929 {
4930 /* -msingle-float selects 32-bit float registers. Otherwise the
4931 float registers should be the same size as the integer ones. */
4932 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4933 target_flags |= MASK_FLOAT64;
4934 else
4935 target_flags &= ~MASK_FLOAT64;
4936 }
4937
4938 /* End of code shared with GAS. */
4939
4940 if ((target_flags_explicit & MASK_LONG64) == 0)
4941 {
4942 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4943 target_flags |= MASK_LONG64;
4944 else
4945 target_flags &= ~MASK_LONG64;
4946 }
4947
4948 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4949 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4950 {
4951 /* For some configurations, it is useful to have -march control
4952 the default setting of MASK_SOFT_FLOAT. */
4953 switch ((int) mips_arch)
4954 {
4955 case PROCESSOR_R4100:
4956 case PROCESSOR_R4111:
4957 case PROCESSOR_R4120:
4958 case PROCESSOR_R4130:
4959 target_flags |= MASK_SOFT_FLOAT;
4960 break;
4961
4962 default:
4963 target_flags &= ~MASK_SOFT_FLOAT;
4964 break;
4965 }
4966 }
4967
4968 if (!TARGET_OLDABI)
4969 flag_pcc_struct_return = 0;
4970
4971 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4972 {
4973 /* If neither -mbranch-likely nor -mno-branch-likely was given
4974 on the command line, set MASK_BRANCHLIKELY based on the target
4975 architecture.
4976
4977 By default, we enable use of Branch Likely instructions on
4978 all architectures which support them with the following
4979 exceptions: when creating MIPS32 or MIPS64 code, and when
4980 tuning for architectures where their use tends to hurt
4981 performance.
4982
4983 The MIPS32 and MIPS64 architecture specifications say "Software
4984 is strongly encouraged to avoid use of Branch Likely
4985 instructions, as they will be removed from a future revision
4986 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4987 issue those instructions unless instructed to do so by
4988 -mbranch-likely. */
4989 if (ISA_HAS_BRANCHLIKELY
4990 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4991 && !(TUNE_MIPS5500 || TUNE_SB1))
4992 target_flags |= MASK_BRANCHLIKELY;
4993 else
4994 target_flags &= ~MASK_BRANCHLIKELY;
4995 }
4996 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4997 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4998
4999 /* The effect of -mabicalls isn't defined for the EABI. */
5000 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
5001 {
5002 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
5003 target_flags &= ~MASK_ABICALLS;
5004 }
5005
5006 if (TARGET_ABICALLS)
5007 {
5008 /* We need to set flag_pic for executables as well as DSOs
5009 because we may reference symbols that are not defined in
5010 the final executable. (MIPS does not use things like
5011 copy relocs, for example.)
5012
5013 Also, there is a body of code that uses __PIC__ to distinguish
5014 between -mabicalls and -mno-abicalls code. */
5015 flag_pic = 1;
5016 if (mips_section_threshold > 0)
5017 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
5018 }
5019
5020 if (TARGET_VXWORKS_RTP && mips_section_threshold > 0)
5021 warning (0, "-G and -mrtp are incompatible");
5022
5023 /* mips_split_addresses is a half-way house between explicit
5024 relocations and the traditional assembler macros. It can
5025 split absolute 32-bit symbolic constants into a high/lo_sum
5026 pair but uses macros for other sorts of access.
5027
5028 Like explicit relocation support for REL targets, it relies
5029 on GNU extensions in the assembler and the linker.
5030
5031 Although this code should work for -O0, it has traditionally
5032 been treated as an optimization. */
5033 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
5034 && optimize && !flag_pic
5035 && !ABI_HAS_64BIT_SYMBOLS)
5036 mips_split_addresses = 1;
5037 else
5038 mips_split_addresses = 0;
5039
5040 /* -mvr4130-align is a "speed over size" optimization: it usually produces
5041 faster code, but at the expense of more nops. Enable it at -O3 and
5042 above. */
5043 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
5044 target_flags |= MASK_VR4130_ALIGN;
5045
5046 /* When compiling for the mips16, we cannot use floating point. We
5047 record the original hard float value in mips16_hard_float. */
5048 if (TARGET_MIPS16)
5049 {
5050 if (TARGET_SOFT_FLOAT)
5051 mips16_hard_float = 0;
5052 else
5053 mips16_hard_float = 1;
5054 target_flags |= MASK_SOFT_FLOAT;
5055
5056 /* Don't run the scheduler before reload, since it tends to
5057 increase register pressure. */
5058 flag_schedule_insns = 0;
5059
5060 /* Don't do hot/cold partitioning. The constant layout code expects
5061 the whole function to be in a single section. */
5062 flag_reorder_blocks_and_partition = 0;
5063
5064 /* Silently disable -mexplicit-relocs since it doesn't apply
5065 to mips16 code. Even so, it would overly pedantic to warn
5066 about "-mips16 -mexplicit-relocs", especially given that
5067 we use a %gprel() operator. */
5068 target_flags &= ~MASK_EXPLICIT_RELOCS;
5069 }
5070
5071 /* When using explicit relocs, we call dbr_schedule from within
5072 mips_reorg. */
5073 if (TARGET_EXPLICIT_RELOCS)
5074 {
5075 mips_flag_delayed_branch = flag_delayed_branch;
5076 flag_delayed_branch = 0;
5077 }
5078
5079 #ifdef MIPS_TFMODE_FORMAT
5080 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
5081 #endif
5082
5083 /* Make sure that the user didn't turn off paired single support when
5084 MIPS-3D support is requested. */
5085 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
5086 && !TARGET_PAIRED_SINGLE_FLOAT)
5087 error ("-mips3d requires -mpaired-single");
5088
5089 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
5090 if (TARGET_MIPS3D)
5091 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
5092
5093 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
5094 and TARGET_HARD_FLOAT are both true. */
5095 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
5096 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
5097
5098 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
5099 enabled. */
5100 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
5101 error ("-mips3d/-mpaired-single must be used with -mips64");
5102
5103 /* If TARGET_DSPR2, enable MASK_DSP. */
5104 if (TARGET_DSPR2)
5105 target_flags |= MASK_DSP;
5106
5107 if (TARGET_MIPS16 && TARGET_DSP)
5108 error ("-mips16 and -mdsp cannot be used together");
5109
5110 mips_print_operand_punct['?'] = 1;
5111 mips_print_operand_punct['#'] = 1;
5112 mips_print_operand_punct['/'] = 1;
5113 mips_print_operand_punct['&'] = 1;
5114 mips_print_operand_punct['!'] = 1;
5115 mips_print_operand_punct['*'] = 1;
5116 mips_print_operand_punct['@'] = 1;
5117 mips_print_operand_punct['.'] = 1;
5118 mips_print_operand_punct['('] = 1;
5119 mips_print_operand_punct[')'] = 1;
5120 mips_print_operand_punct['['] = 1;
5121 mips_print_operand_punct[']'] = 1;
5122 mips_print_operand_punct['<'] = 1;
5123 mips_print_operand_punct['>'] = 1;
5124 mips_print_operand_punct['{'] = 1;
5125 mips_print_operand_punct['}'] = 1;
5126 mips_print_operand_punct['^'] = 1;
5127 mips_print_operand_punct['$'] = 1;
5128 mips_print_operand_punct['+'] = 1;
5129 mips_print_operand_punct['~'] = 1;
5130
5131 /* Set up array to map GCC register number to debug register number.
5132 Ignore the special purpose register numbers. */
5133
5134 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5135 mips_dbx_regno[i] = -1;
5136
5137 start = GP_DBX_FIRST - GP_REG_FIRST;
5138 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5139 mips_dbx_regno[i] = i + start;
5140
5141 start = FP_DBX_FIRST - FP_REG_FIRST;
5142 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5143 mips_dbx_regno[i] = i + start;
5144
5145 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5146 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5147
5148 /* Set up array giving whether a given register can hold a given mode. */
5149
5150 for (mode = VOIDmode;
5151 mode != MAX_MACHINE_MODE;
5152 mode = (enum machine_mode) ((int)mode + 1))
5153 {
5154 register int size = GET_MODE_SIZE (mode);
5155 register enum mode_class class = GET_MODE_CLASS (mode);
5156
5157 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5158 {
5159 register int temp;
5160
5161 if (mode == CCV2mode)
5162 temp = (ISA_HAS_8CC
5163 && ST_REG_P (regno)
5164 && (regno - ST_REG_FIRST) % 2 == 0);
5165
5166 else if (mode == CCV4mode)
5167 temp = (ISA_HAS_8CC
5168 && ST_REG_P (regno)
5169 && (regno - ST_REG_FIRST) % 4 == 0);
5170
5171 else if (mode == CCmode)
5172 {
5173 if (! ISA_HAS_8CC)
5174 temp = (regno == FPSW_REGNUM);
5175 else
5176 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5177 || FP_REG_P (regno));
5178 }
5179
5180 else if (GP_REG_P (regno))
5181 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5182
5183 else if (FP_REG_P (regno))
5184 temp = ((((regno % MAX_FPRS_PER_FMT) == 0)
5185 || (MIN_FPRS_PER_FMT == 1
5186 && size <= UNITS_PER_FPREG))
5187 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5188 || class == MODE_VECTOR_FLOAT)
5189 && size <= UNITS_PER_FPVALUE)
5190 /* Allow integer modes that fit into a single
5191 register. We need to put integers into FPRs
5192 when using instructions like cvt and trunc.
5193 We can't allow sizes smaller than a word,
5194 the FPU has no appropriate load/store
5195 instructions for those. */
5196 || (class == MODE_INT
5197 && size >= MIN_UNITS_PER_WORD
5198 && size <= UNITS_PER_FPREG)
5199 /* Allow TFmode for CCmode reloads. */
5200 || (ISA_HAS_8CC && mode == TFmode)));
5201
5202 else if (ACC_REG_P (regno))
5203 temp = (INTEGRAL_MODE_P (mode)
5204 && (size <= UNITS_PER_WORD
5205 || (ACC_HI_REG_P (regno)
5206 && size == 2 * UNITS_PER_WORD)));
5207
5208 else if (ALL_COP_REG_P (regno))
5209 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5210 else
5211 temp = 0;
5212
5213 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5214 }
5215 }
5216
5217 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5218 initialized yet, so we can't use that here. */
5219 gpr_mode = TARGET_64BIT ? DImode : SImode;
5220
5221 /* Provide default values for align_* for 64-bit targets. */
5222 if (TARGET_64BIT && !TARGET_MIPS16)
5223 {
5224 if (align_loops == 0)
5225 align_loops = 8;
5226 if (align_jumps == 0)
5227 align_jumps = 8;
5228 if (align_functions == 0)
5229 align_functions = 8;
5230 }
5231
5232 /* Function to allocate machine-dependent function status. */
5233 init_machine_status = &mips_init_machine_status;
5234
5235 if (ABI_HAS_64BIT_SYMBOLS)
5236 {
5237 if (TARGET_EXPLICIT_RELOCS)
5238 {
5239 mips_split_p[SYMBOL_64_HIGH] = true;
5240 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5241 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5242
5243 mips_split_p[SYMBOL_64_MID] = true;
5244 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5245 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5246
5247 mips_split_p[SYMBOL_64_LOW] = true;
5248 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5249 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5250
5251 mips_split_p[SYMBOL_GENERAL] = true;
5252 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5253 }
5254 }
5255 else
5256 {
5257 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5258 {
5259 mips_split_p[SYMBOL_GENERAL] = true;
5260 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5261 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5262 }
5263 }
5264
5265 if (TARGET_MIPS16)
5266 {
5267 /* The high part is provided by a pseudo copy of $gp. */
5268 mips_split_p[SYMBOL_SMALL_DATA] = true;
5269 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5270 }
5271
5272 if (TARGET_EXPLICIT_RELOCS)
5273 {
5274 /* Small data constants are kept whole until after reload,
5275 then lowered by mips_rewrite_small_data. */
5276 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5277
5278 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
5279 if (TARGET_NEWABI)
5280 {
5281 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5282 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
5283 }
5284 else
5285 {
5286 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5287 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
5288 }
5289
5290 if (TARGET_XGOT)
5291 {
5292 /* The HIGH and LO_SUM are matched by special .md patterns. */
5293 mips_split_p[SYMBOL_GOT_DISP] = true;
5294
5295 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
5296 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
5297 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
5298
5299 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5300 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5301 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5302 }
5303 else
5304 {
5305 if (TARGET_NEWABI)
5306 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
5307 else
5308 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
5309 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5310 }
5311 }
5312
5313 if (TARGET_NEWABI)
5314 {
5315 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5316 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5317 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5318 }
5319
5320 /* Thread-local relocation operators. */
5321 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5322 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5323 mips_split_p[SYMBOL_DTPREL] = 1;
5324 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5325 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5326 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5327 mips_split_p[SYMBOL_TPREL] = 1;
5328 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5329 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5330
5331 mips_lo_relocs[SYMBOL_HALF] = "%half(";
5332
5333 /* We don't have a thread pointer access instruction on MIPS16, or
5334 appropriate TLS relocations. */
5335 if (TARGET_MIPS16)
5336 targetm.have_tls = false;
5337
5338 /* Default to working around R4000 errata only if the processor
5339 was selected explicitly. */
5340 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5341 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5342 target_flags |= MASK_FIX_R4000;
5343
5344 /* Default to working around R4400 errata only if the processor
5345 was selected explicitly. */
5346 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5347 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5348 target_flags |= MASK_FIX_R4400;
5349 }
5350
5351 /* Implement CONDITIONAL_REGISTER_USAGE. */
5352
5353 void
5354 mips_conditional_register_usage (void)
5355 {
5356 if (!TARGET_DSP)
5357 {
5358 int regno;
5359
5360 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5361 fixed_regs[regno] = call_used_regs[regno] = 1;
5362 }
5363 if (!TARGET_HARD_FLOAT)
5364 {
5365 int regno;
5366
5367 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5368 fixed_regs[regno] = call_used_regs[regno] = 1;
5369 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5370 fixed_regs[regno] = call_used_regs[regno] = 1;
5371 }
5372 else if (! ISA_HAS_8CC)
5373 {
5374 int regno;
5375
5376 /* We only have a single condition code register. We
5377 implement this by hiding all the condition code registers,
5378 and generating RTL that refers directly to ST_REG_FIRST. */
5379 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5380 fixed_regs[regno] = call_used_regs[regno] = 1;
5381 }
5382 /* In mips16 mode, we permit the $t temporary registers to be used
5383 for reload. We prohibit the unused $s registers, since they
5384 are caller saved, and saving them via a mips16 register would
5385 probably waste more time than just reloading the value. */
5386 if (TARGET_MIPS16)
5387 {
5388 fixed_regs[18] = call_used_regs[18] = 1;
5389 fixed_regs[19] = call_used_regs[19] = 1;
5390 fixed_regs[20] = call_used_regs[20] = 1;
5391 fixed_regs[21] = call_used_regs[21] = 1;
5392 fixed_regs[22] = call_used_regs[22] = 1;
5393 fixed_regs[23] = call_used_regs[23] = 1;
5394 fixed_regs[26] = call_used_regs[26] = 1;
5395 fixed_regs[27] = call_used_regs[27] = 1;
5396 fixed_regs[30] = call_used_regs[30] = 1;
5397 }
5398 /* fp20-23 are now caller saved. */
5399 if (mips_abi == ABI_64)
5400 {
5401 int regno;
5402 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5403 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5404 }
5405 /* Odd registers from fp21 to fp31 are now caller saved. */
5406 if (mips_abi == ABI_N32)
5407 {
5408 int regno;
5409 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5410 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5411 }
5412 }
5413
5414 /* Allocate a chunk of memory for per-function machine-dependent data. */
5415 static struct machine_function *
5416 mips_init_machine_status (void)
5417 {
5418 return ((struct machine_function *)
5419 ggc_alloc_cleared (sizeof (struct machine_function)));
5420 }
5421
5422 /* On the mips16, we want to allocate $24 (T_REG) before other
5423 registers for instructions for which it is possible. This helps
5424 avoid shuffling registers around in order to set up for an xor,
5425 encouraging the compiler to use a cmp instead. */
5426
5427 void
5428 mips_order_regs_for_local_alloc (void)
5429 {
5430 register int i;
5431
5432 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5433 reg_alloc_order[i] = i;
5434
5435 if (TARGET_MIPS16)
5436 {
5437 /* It really doesn't matter where we put register 0, since it is
5438 a fixed register anyhow. */
5439 reg_alloc_order[0] = 24;
5440 reg_alloc_order[24] = 0;
5441 }
5442 }
5443
5444 \f
5445 /* The MIPS debug format wants all automatic variables and arguments
5446 to be in terms of the virtual frame pointer (stack pointer before
5447 any adjustment in the function), while the MIPS 3.0 linker wants
5448 the frame pointer to be the stack pointer after the initial
5449 adjustment. So, we do the adjustment here. The arg pointer (which
5450 is eliminated) points to the virtual frame pointer, while the frame
5451 pointer (which may be eliminated) points to the stack pointer after
5452 the initial adjustments. */
5453
5454 HOST_WIDE_INT
5455 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5456 {
5457 rtx offset2 = const0_rtx;
5458 rtx reg = eliminate_constant_term (addr, &offset2);
5459
5460 if (offset == 0)
5461 offset = INTVAL (offset2);
5462
5463 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5464 || reg == hard_frame_pointer_rtx)
5465 {
5466 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5467 ? compute_frame_size (get_frame_size ())
5468 : cfun->machine->frame.total_size;
5469
5470 /* MIPS16 frame is smaller */
5471 if (frame_pointer_needed && TARGET_MIPS16)
5472 frame_size -= cfun->machine->frame.args_size;
5473
5474 offset = offset - frame_size;
5475 }
5476
5477 /* sdbout_parms does not want this to crash for unrecognized cases. */
5478 #if 0
5479 else if (reg != arg_pointer_rtx)
5480 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5481 addr);
5482 #endif
5483
5484 return offset;
5485 }
5486 \f
5487 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5488
5489 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5490 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5491 'h' OP is HIGH, prints %hi(X),
5492 'd' output integer constant in decimal,
5493 'z' if the operand is 0, use $0 instead of normal operand.
5494 'D' print second part of double-word register or memory operand.
5495 'L' print low-order register of double-word register operand.
5496 'M' print high-order register of double-word register operand.
5497 'C' print part of opcode for a branch condition.
5498 'F' print part of opcode for a floating-point branch condition.
5499 'N' print part of opcode for a branch condition, inverted.
5500 'W' print part of opcode for a floating-point branch condition, inverted.
5501 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5502 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5503 't' like 'T', but with the EQ/NE cases reversed
5504 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5505 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5506 'R' print the reloc associated with LO_SUM
5507 'q' print DSP accumulator registers
5508
5509 The punctuation characters are:
5510
5511 '(' Turn on .set noreorder
5512 ')' Turn on .set reorder
5513 '[' Turn on .set noat
5514 ']' Turn on .set at
5515 '<' Turn on .set nomacro
5516 '>' Turn on .set macro
5517 '{' Turn on .set volatile (not GAS)
5518 '}' Turn on .set novolatile (not GAS)
5519 '&' Turn on .set noreorder if filling delay slots
5520 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5521 '!' Turn on .set nomacro if filling delay slots
5522 '#' Print nop if in a .set noreorder section.
5523 '/' Like '#', but does nothing within a delayed branch sequence
5524 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5525 '@' Print the name of the assembler temporary register (at or $1).
5526 '.' Print the name of the register with a hard-wired zero (zero or $0).
5527 '^' Print the name of the pic call-through register (t9 or $25).
5528 '$' Print the name of the stack pointer register (sp or $29).
5529 '+' Print the name of the gp register (usually gp or $28).
5530 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5531
5532 void
5533 print_operand (FILE *file, rtx op, int letter)
5534 {
5535 register enum rtx_code code;
5536
5537 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5538 {
5539 switch (letter)
5540 {
5541 case '?':
5542 if (mips_branch_likely)
5543 putc ('l', file);
5544 break;
5545
5546 case '@':
5547 fputs (reg_names [GP_REG_FIRST + 1], file);
5548 break;
5549
5550 case '^':
5551 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5552 break;
5553
5554 case '.':
5555 fputs (reg_names [GP_REG_FIRST + 0], file);
5556 break;
5557
5558 case '$':
5559 fputs (reg_names[STACK_POINTER_REGNUM], file);
5560 break;
5561
5562 case '+':
5563 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5564 break;
5565
5566 case '&':
5567 if (final_sequence != 0 && set_noreorder++ == 0)
5568 fputs (".set\tnoreorder\n\t", file);
5569 break;
5570
5571 case '*':
5572 if (final_sequence != 0)
5573 {
5574 if (set_noreorder++ == 0)
5575 fputs (".set\tnoreorder\n\t", file);
5576
5577 if (set_nomacro++ == 0)
5578 fputs (".set\tnomacro\n\t", file);
5579 }
5580 break;
5581
5582 case '!':
5583 if (final_sequence != 0 && set_nomacro++ == 0)
5584 fputs ("\n\t.set\tnomacro", file);
5585 break;
5586
5587 case '#':
5588 if (set_noreorder != 0)
5589 fputs ("\n\tnop", file);
5590 break;
5591
5592 case '/':
5593 /* Print an extra newline so that the delayed insn is separated
5594 from the following ones. This looks neater and is consistent
5595 with non-nop delayed sequences. */
5596 if (set_noreorder != 0 && final_sequence == 0)
5597 fputs ("\n\tnop\n", file);
5598 break;
5599
5600 case '(':
5601 if (set_noreorder++ == 0)
5602 fputs (".set\tnoreorder\n\t", file);
5603 break;
5604
5605 case ')':
5606 if (set_noreorder == 0)
5607 error ("internal error: %%) found without a %%( in assembler pattern");
5608
5609 else if (--set_noreorder == 0)
5610 fputs ("\n\t.set\treorder", file);
5611
5612 break;
5613
5614 case '[':
5615 if (set_noat++ == 0)
5616 fputs (".set\tnoat\n\t", file);
5617 break;
5618
5619 case ']':
5620 if (set_noat == 0)
5621 error ("internal error: %%] found without a %%[ in assembler pattern");
5622 else if (--set_noat == 0)
5623 fputs ("\n\t.set\tat", file);
5624
5625 break;
5626
5627 case '<':
5628 if (set_nomacro++ == 0)
5629 fputs (".set\tnomacro\n\t", file);
5630 break;
5631
5632 case '>':
5633 if (set_nomacro == 0)
5634 error ("internal error: %%> found without a %%< in assembler pattern");
5635 else if (--set_nomacro == 0)
5636 fputs ("\n\t.set\tmacro", file);
5637
5638 break;
5639
5640 case '{':
5641 if (set_volatile++ == 0)
5642 fputs ("#.set\tvolatile\n\t", file);
5643 break;
5644
5645 case '}':
5646 if (set_volatile == 0)
5647 error ("internal error: %%} found without a %%{ in assembler pattern");
5648 else if (--set_volatile == 0)
5649 fputs ("\n\t#.set\tnovolatile", file);
5650
5651 break;
5652
5653 case '~':
5654 {
5655 if (align_labels_log > 0)
5656 ASM_OUTPUT_ALIGN (file, align_labels_log);
5657 }
5658 break;
5659
5660 default:
5661 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5662 break;
5663 }
5664
5665 return;
5666 }
5667
5668 if (! op)
5669 {
5670 error ("PRINT_OPERAND null pointer");
5671 return;
5672 }
5673
5674 code = GET_CODE (op);
5675
5676 if (letter == 'C')
5677 switch (code)
5678 {
5679 case EQ: fputs ("eq", file); break;
5680 case NE: fputs ("ne", file); break;
5681 case GT: fputs ("gt", file); break;
5682 case GE: fputs ("ge", file); break;
5683 case LT: fputs ("lt", file); break;
5684 case LE: fputs ("le", file); break;
5685 case GTU: fputs ("gtu", file); break;
5686 case GEU: fputs ("geu", file); break;
5687 case LTU: fputs ("ltu", file); break;
5688 case LEU: fputs ("leu", file); break;
5689 default:
5690 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5691 }
5692
5693 else if (letter == 'N')
5694 switch (code)
5695 {
5696 case EQ: fputs ("ne", file); break;
5697 case NE: fputs ("eq", file); break;
5698 case GT: fputs ("le", file); break;
5699 case GE: fputs ("lt", file); break;
5700 case LT: fputs ("ge", file); break;
5701 case LE: fputs ("gt", file); break;
5702 case GTU: fputs ("leu", file); break;
5703 case GEU: fputs ("ltu", file); break;
5704 case LTU: fputs ("geu", file); break;
5705 case LEU: fputs ("gtu", file); break;
5706 default:
5707 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5708 }
5709
5710 else if (letter == 'F')
5711 switch (code)
5712 {
5713 case EQ: fputs ("c1f", file); break;
5714 case NE: fputs ("c1t", file); break;
5715 default:
5716 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5717 }
5718
5719 else if (letter == 'W')
5720 switch (code)
5721 {
5722 case EQ: fputs ("c1t", file); break;
5723 case NE: fputs ("c1f", file); break;
5724 default:
5725 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5726 }
5727
5728 else if (letter == 'h')
5729 {
5730 if (GET_CODE (op) == HIGH)
5731 op = XEXP (op, 0);
5732
5733 print_operand_reloc (file, op, mips_hi_relocs);
5734 }
5735
5736 else if (letter == 'R')
5737 print_operand_reloc (file, op, mips_lo_relocs);
5738
5739 else if (letter == 'Y')
5740 {
5741 if (GET_CODE (op) == CONST_INT
5742 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5743 < ARRAY_SIZE (mips_fp_conditions)))
5744 fputs (mips_fp_conditions[INTVAL (op)], file);
5745 else
5746 output_operand_lossage ("invalid %%Y value");
5747 }
5748
5749 else if (letter == 'Z')
5750 {
5751 if (ISA_HAS_8CC)
5752 {
5753 print_operand (file, op, 0);
5754 fputc (',', file);
5755 }
5756 }
5757
5758 else if (letter == 'q')
5759 {
5760 int regnum;
5761
5762 if (code != REG)
5763 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5764
5765 regnum = REGNO (op);
5766 if (MD_REG_P (regnum))
5767 fprintf (file, "$ac0");
5768 else if (DSP_ACC_REG_P (regnum))
5769 fprintf (file, "$ac%c", reg_names[regnum][3]);
5770 else
5771 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5772 }
5773
5774 else if (code == REG || code == SUBREG)
5775 {
5776 register int regnum;
5777
5778 if (code == REG)
5779 regnum = REGNO (op);
5780 else
5781 regnum = true_regnum (op);
5782
5783 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5784 || (letter == 'L' && WORDS_BIG_ENDIAN)
5785 || letter == 'D')
5786 regnum++;
5787
5788 fprintf (file, "%s", reg_names[regnum]);
5789 }
5790
5791 else if (code == MEM)
5792 {
5793 if (letter == 'D')
5794 output_address (plus_constant (XEXP (op, 0), 4));
5795 else
5796 output_address (XEXP (op, 0));
5797 }
5798
5799 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5800 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5801
5802 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5803 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5804
5805 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5806 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5807
5808 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5809 fputs (reg_names[GP_REG_FIRST], file);
5810
5811 else if (letter == 'd' || letter == 'x' || letter == 'X')
5812 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5813
5814 else if (letter == 'T' || letter == 't')
5815 {
5816 int truth = (code == NE) == (letter == 'T');
5817 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5818 }
5819
5820 else if (CONST_GP_P (op))
5821 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5822
5823 else
5824 output_addr_const (file, op);
5825 }
5826
5827
5828 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5829 RELOCS is the array of relocations to use. */
5830
5831 static void
5832 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5833 {
5834 enum mips_symbol_type symbol_type;
5835 const char *p;
5836 rtx base, offset;
5837
5838 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5839 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5840
5841 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5842 split_const (op, &base, &offset);
5843 if (UNSPEC_ADDRESS_P (base))
5844 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
5845
5846 fputs (relocs[symbol_type], file);
5847 output_addr_const (file, op);
5848 for (p = relocs[symbol_type]; *p != 0; p++)
5849 if (*p == '(')
5850 fputc (')', file);
5851 }
5852 \f
5853 /* Output address operand X to FILE. */
5854
5855 void
5856 print_operand_address (FILE *file, rtx x)
5857 {
5858 struct mips_address_info addr;
5859
5860 if (mips_classify_address (&addr, x, word_mode, true))
5861 switch (addr.type)
5862 {
5863 case ADDRESS_REG:
5864 print_operand (file, addr.offset, 0);
5865 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5866 return;
5867
5868 case ADDRESS_LO_SUM:
5869 print_operand (file, addr.offset, 'R');
5870 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5871 return;
5872
5873 case ADDRESS_CONST_INT:
5874 output_addr_const (file, x);
5875 fprintf (file, "(%s)", reg_names[0]);
5876 return;
5877
5878 case ADDRESS_SYMBOLIC:
5879 output_addr_const (file, x);
5880 return;
5881 }
5882 gcc_unreachable ();
5883 }
5884 \f
5885 /* When using assembler macros, keep track of all of small-data externs
5886 so that mips_file_end can emit the appropriate declarations for them.
5887
5888 In most cases it would be safe (though pointless) to emit .externs
5889 for other symbols too. One exception is when an object is within
5890 the -G limit but declared by the user to be in a section other
5891 than .sbss or .sdata. */
5892
5893 void
5894 mips_output_external (FILE *file, tree decl, const char *name)
5895 {
5896 default_elf_asm_output_external (file, decl, name);
5897
5898 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
5899 set in order to avoid putting out names that are never really
5900 used. */
5901 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
5902 {
5903 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5904 {
5905 fputs ("\t.extern\t", file);
5906 assemble_name (file, name);
5907 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
5908 int_size_in_bytes (TREE_TYPE (decl)));
5909 }
5910 else if (TARGET_IRIX
5911 && mips_abi == ABI_32
5912 && TREE_CODE (decl) == FUNCTION_DECL)
5913 {
5914 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5915 `.global name .text' directive for every used but
5916 undefined function. If we don't, the linker may perform
5917 an optimization (skipping over the insns that set $gp)
5918 when it is unsafe. */
5919 fputs ("\t.globl ", file);
5920 assemble_name (file, name);
5921 fputs (" .text\n", file);
5922 }
5923 }
5924 }
5925 \f
5926 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5927 put out a MIPS ECOFF file and a stab. */
5928
5929 void
5930 mips_output_filename (FILE *stream, const char *name)
5931 {
5932
5933 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5934 directives. */
5935 if (write_symbols == DWARF2_DEBUG)
5936 return;
5937 else if (mips_output_filename_first_time)
5938 {
5939 mips_output_filename_first_time = 0;
5940 num_source_filenames += 1;
5941 current_function_file = name;
5942 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5943 output_quoted_string (stream, name);
5944 putc ('\n', stream);
5945 }
5946
5947 /* If we are emitting stabs, let dbxout.c handle this (except for
5948 the mips_output_filename_first_time case). */
5949 else if (write_symbols == DBX_DEBUG)
5950 return;
5951
5952 else if (name != current_function_file
5953 && strcmp (name, current_function_file) != 0)
5954 {
5955 num_source_filenames += 1;
5956 current_function_file = name;
5957 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5958 output_quoted_string (stream, name);
5959 putc ('\n', stream);
5960 }
5961 }
5962 \f
5963 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5964 that should be written before the opening quote, such as "\t.ascii\t"
5965 for real string data or "\t# " for a comment. */
5966
5967 void
5968 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5969 const char *prefix)
5970 {
5971 size_t i;
5972 int cur_pos = 17;
5973 register const unsigned char *string =
5974 (const unsigned char *)string_param;
5975
5976 fprintf (stream, "%s\"", prefix);
5977 for (i = 0; i < len; i++)
5978 {
5979 register int c = string[i];
5980
5981 if (ISPRINT (c))
5982 {
5983 if (c == '\\' || c == '\"')
5984 {
5985 putc ('\\', stream);
5986 cur_pos++;
5987 }
5988 putc (c, stream);
5989 cur_pos++;
5990 }
5991 else
5992 {
5993 fprintf (stream, "\\%03o", c);
5994 cur_pos += 4;
5995 }
5996
5997 if (cur_pos > 72 && i+1 < len)
5998 {
5999 cur_pos = 17;
6000 fprintf (stream, "\"\n%s\"", prefix);
6001 }
6002 }
6003 fprintf (stream, "\"\n");
6004 }
6005 \f
6006 /* Implement TARGET_ASM_FILE_START. */
6007
6008 static void
6009 mips_file_start (void)
6010 {
6011 default_file_start ();
6012
6013 if (!TARGET_IRIX)
6014 {
6015 /* Generate a special section to describe the ABI switches used to
6016 produce the resultant binary. This used to be done by the assembler
6017 setting bits in the ELF header's flags field, but we have run out of
6018 bits. GDB needs this information in order to be able to correctly
6019 debug these binaries. See the function mips_gdbarch_init() in
6020 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6021 causes unnecessary IRIX 6 ld warnings. */
6022 const char * abi_string = NULL;
6023
6024 switch (mips_abi)
6025 {
6026 case ABI_32: abi_string = "abi32"; break;
6027 case ABI_N32: abi_string = "abiN32"; break;
6028 case ABI_64: abi_string = "abi64"; break;
6029 case ABI_O64: abi_string = "abiO64"; break;
6030 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6031 default:
6032 gcc_unreachable ();
6033 }
6034 /* Note - we use fprintf directly rather than calling switch_to_section
6035 because in this way we can avoid creating an allocated section. We
6036 do not want this section to take up any space in the running
6037 executable. */
6038 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
6039
6040 /* There is no ELF header flag to distinguish long32 forms of the
6041 EABI from long64 forms. Emit a special section to help tools
6042 such as GDB. Do the same for o64, which is sometimes used with
6043 -mlong64. */
6044 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
6045 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
6046 TARGET_LONG64 ? 64 : 32);
6047
6048 /* Restore the default section. */
6049 fprintf (asm_out_file, "\t.previous\n");
6050 }
6051
6052 /* Generate the pseudo ops that System V.4 wants. */
6053 if (TARGET_ABICALLS)
6054 fprintf (asm_out_file, "\t.abicalls\n");
6055
6056 if (TARGET_MIPS16)
6057 fprintf (asm_out_file, "\t.set\tmips16\n");
6058
6059 if (flag_verbose_asm)
6060 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6061 ASM_COMMENT_START,
6062 mips_section_threshold, mips_arch_info->name, mips_isa);
6063 }
6064
6065 #ifdef BSS_SECTION_ASM_OP
6066 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6067 in the use of sbss. */
6068
6069 void
6070 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
6071 unsigned HOST_WIDE_INT size, int align)
6072 {
6073 extern tree last_assemble_variable_decl;
6074
6075 if (mips_in_small_data_p (decl))
6076 switch_to_section (get_named_section (NULL, ".sbss", 0));
6077 else
6078 switch_to_section (bss_section);
6079 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6080 last_assemble_variable_decl = decl;
6081 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
6082 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
6083 }
6084 #endif
6085 \f
6086 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
6087 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6088
6089 void
6090 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6091 unsigned HOST_WIDE_INT size,
6092 unsigned int align)
6093 {
6094 /* If the target wants uninitialized const declarations in
6095 .rdata then don't put them in .comm. */
6096 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6097 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6098 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6099 {
6100 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6101 targetm.asm_out.globalize_label (stream, name);
6102
6103 switch_to_section (readonly_data_section);
6104 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6105 mips_declare_object (stream, name, "",
6106 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6107 size);
6108 }
6109 else
6110 mips_declare_common_object (stream, name, "\n\t.comm\t",
6111 size, align, true);
6112 }
6113
6114 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6115 NAME is the name of the object and ALIGN is the required alignment
6116 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6117 alignment argument. */
6118
6119 void
6120 mips_declare_common_object (FILE *stream, const char *name,
6121 const char *init_string,
6122 unsigned HOST_WIDE_INT size,
6123 unsigned int align, bool takes_alignment_p)
6124 {
6125 if (!takes_alignment_p)
6126 {
6127 size += (align / BITS_PER_UNIT) - 1;
6128 size -= size % (align / BITS_PER_UNIT);
6129 mips_declare_object (stream, name, init_string,
6130 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6131 }
6132 else
6133 mips_declare_object (stream, name, init_string,
6134 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6135 size, align / BITS_PER_UNIT);
6136 }
6137
6138 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6139 macros, mark the symbol as written so that mips_file_end won't emit an
6140 .extern for it. STREAM is the output file, NAME is the name of the
6141 symbol, INIT_STRING is the string that should be written before the
6142 symbol and FINAL_STRING is the string that should be written after it.
6143 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6144
6145 void
6146 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6147 const char *final_string, ...)
6148 {
6149 va_list ap;
6150
6151 fputs (init_string, stream);
6152 assemble_name (stream, name);
6153 va_start (ap, final_string);
6154 vfprintf (stream, final_string, ap);
6155 va_end (ap);
6156
6157 if (!TARGET_EXPLICIT_RELOCS)
6158 {
6159 tree name_tree = get_identifier (name);
6160 TREE_ASM_WRITTEN (name_tree) = 1;
6161 }
6162 }
6163
6164 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6165 extern int size_directive_output;
6166
6167 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6168 definitions except that it uses mips_declare_object() to emit the label. */
6169
6170 void
6171 mips_declare_object_name (FILE *stream, const char *name,
6172 tree decl ATTRIBUTE_UNUSED)
6173 {
6174 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6175 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6176 #endif
6177
6178 size_directive_output = 0;
6179 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6180 {
6181 HOST_WIDE_INT size;
6182
6183 size_directive_output = 1;
6184 size = int_size_in_bytes (TREE_TYPE (decl));
6185 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6186 }
6187
6188 mips_declare_object (stream, name, "", ":\n");
6189 }
6190
6191 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6192
6193 void
6194 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6195 {
6196 const char *name;
6197
6198 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6199 if (!flag_inhibit_size_directive
6200 && DECL_SIZE (decl) != 0
6201 && !at_end && top_level
6202 && DECL_INITIAL (decl) == error_mark_node
6203 && !size_directive_output)
6204 {
6205 HOST_WIDE_INT size;
6206
6207 size_directive_output = 1;
6208 size = int_size_in_bytes (TREE_TYPE (decl));
6209 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6210 }
6211 }
6212 #endif
6213 \f
6214 /* Return true if X is a small data address that can be rewritten
6215 as a LO_SUM. */
6216
6217 static bool
6218 mips_rewrite_small_data_p (rtx x)
6219 {
6220 enum mips_symbol_type symbol_type;
6221
6222 return (TARGET_EXPLICIT_RELOCS
6223 && mips_symbolic_constant_p (x, &symbol_type)
6224 && symbol_type == SYMBOL_SMALL_DATA);
6225 }
6226
6227
6228 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6229
6230 static int
6231 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6232 {
6233 if (GET_CODE (*loc) == LO_SUM)
6234 return -1;
6235
6236 return mips_rewrite_small_data_p (*loc);
6237 }
6238
6239 /* Return true if OP refers to small data symbols directly, not through
6240 a LO_SUM. */
6241
6242 bool
6243 mips_small_data_pattern_p (rtx op)
6244 {
6245 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6246 }
6247 \f
6248 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6249
6250 static int
6251 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6252 {
6253 if (mips_rewrite_small_data_p (*loc))
6254 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6255
6256 if (GET_CODE (*loc) == LO_SUM)
6257 return -1;
6258
6259 return 0;
6260 }
6261
6262 /* If possible, rewrite OP so that it refers to small data using
6263 explicit relocations. */
6264
6265 rtx
6266 mips_rewrite_small_data (rtx op)
6267 {
6268 op = copy_insn (op);
6269 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6270 return op;
6271 }
6272 \f
6273 /* Return true if the current function has an insn that implicitly
6274 refers to $gp. */
6275
6276 static bool
6277 mips_function_has_gp_insn (void)
6278 {
6279 /* Don't bother rechecking if we found one last time. */
6280 if (!cfun->machine->has_gp_insn_p)
6281 {
6282 rtx insn;
6283
6284 push_topmost_sequence ();
6285 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6286 if (INSN_P (insn)
6287 && GET_CODE (PATTERN (insn)) != USE
6288 && GET_CODE (PATTERN (insn)) != CLOBBER
6289 && (get_attr_got (insn) != GOT_UNSET
6290 || small_data_pattern (PATTERN (insn), VOIDmode)))
6291 break;
6292 pop_topmost_sequence ();
6293
6294 cfun->machine->has_gp_insn_p = (insn != 0);
6295 }
6296 return cfun->machine->has_gp_insn_p;
6297 }
6298
6299
6300 /* Return the register that should be used as the global pointer
6301 within this function. Return 0 if the function doesn't need
6302 a global pointer. */
6303
6304 static unsigned int
6305 mips_global_pointer (void)
6306 {
6307 unsigned int regno;
6308
6309 /* $gp is always available unless we're using a GOT. */
6310 if (!TARGET_USE_GOT)
6311 return GLOBAL_POINTER_REGNUM;
6312
6313 /* We must always provide $gp when it is used implicitly. */
6314 if (!TARGET_EXPLICIT_RELOCS)
6315 return GLOBAL_POINTER_REGNUM;
6316
6317 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6318 a valid gp. */
6319 if (current_function_profile)
6320 return GLOBAL_POINTER_REGNUM;
6321
6322 /* If the function has a nonlocal goto, $gp must hold the correct
6323 global pointer for the target function. */
6324 if (current_function_has_nonlocal_goto)
6325 return GLOBAL_POINTER_REGNUM;
6326
6327 /* If the gp is never referenced, there's no need to initialize it.
6328 Note that reload can sometimes introduce constant pool references
6329 into a function that otherwise didn't need them. For example,
6330 suppose we have an instruction like:
6331
6332 (set (reg:DF R1) (float:DF (reg:SI R2)))
6333
6334 If R2 turns out to be constant such as 1, the instruction may have a
6335 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6336 using this constant if R2 doesn't get allocated to a register.
6337
6338 In cases like these, reload will have added the constant to the pool
6339 but no instruction will yet refer to it. */
6340 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6341 && !current_function_uses_const_pool
6342 && !mips_function_has_gp_insn ())
6343 return 0;
6344
6345 /* We need a global pointer, but perhaps we can use a call-clobbered
6346 register instead of $gp. */
6347 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
6348 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6349 if (!regs_ever_live[regno]
6350 && call_used_regs[regno]
6351 && !fixed_regs[regno]
6352 && regno != PIC_FUNCTION_ADDR_REGNUM)
6353 return regno;
6354
6355 return GLOBAL_POINTER_REGNUM;
6356 }
6357
6358
6359 /* Return true if the function return value MODE will get returned in a
6360 floating-point register. */
6361
6362 static bool
6363 mips_return_mode_in_fpr_p (enum machine_mode mode)
6364 {
6365 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
6366 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
6367 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6368 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
6369 }
6370
6371 /* Return a two-character string representing a function floating-point
6372 return mode, used to name MIPS16 function stubs. */
6373
6374 static const char *
6375 mips16_call_stub_mode_suffix (enum machine_mode mode)
6376 {
6377 if (mode == SFmode)
6378 return "sf";
6379 else if (mode == DFmode)
6380 return "df";
6381 else if (mode == SCmode)
6382 return "sc";
6383 else if (mode == DCmode)
6384 return "dc";
6385 else if (mode == V2SFmode)
6386 return "df";
6387 else
6388 gcc_unreachable ();
6389 }
6390
6391 /* Return true if the current function returns its value in a floating-point
6392 register in MIPS16 mode. */
6393
6394 static bool
6395 mips16_cfun_returns_in_fpr_p (void)
6396 {
6397 tree return_type = DECL_RESULT (current_function_decl);
6398 return (mips16_hard_float
6399 && !aggregate_value_p (return_type, current_function_decl)
6400 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
6401 }
6402
6403
6404 /* Return true if the current function must save REGNO. */
6405
6406 static bool
6407 mips_save_reg_p (unsigned int regno)
6408 {
6409 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
6410 if we have not chosen a call-clobbered substitute. */
6411 if (regno == GLOBAL_POINTER_REGNUM)
6412 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
6413
6414 /* Check call-saved registers. */
6415 if (regs_ever_live[regno] && !call_used_regs[regno])
6416 return true;
6417
6418 /* Save both registers in an FPR pair if either one is used. This is
6419 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
6420 register to be used without the even register. */
6421 if (FP_REG_P (regno)
6422 && MAX_FPRS_PER_FMT == 2
6423 && regs_ever_live[regno + 1]
6424 && !call_used_regs[regno + 1])
6425 return true;
6426
6427 /* We need to save the old frame pointer before setting up a new one. */
6428 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6429 return true;
6430
6431 /* We need to save the incoming return address if it is ever clobbered
6432 within the function. */
6433 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6434 return true;
6435
6436 if (TARGET_MIPS16)
6437 {
6438 /* $18 is a special case in mips16 code. It may be used to call
6439 a function which returns a floating point value, but it is
6440 marked in call_used_regs. */
6441 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6442 return true;
6443
6444 /* $31 is also a special case. It will be used to copy a return
6445 value into the floating point registers if the return value is
6446 floating point. */
6447 if (regno == GP_REG_FIRST + 31
6448 && mips16_cfun_returns_in_fpr_p ())
6449 return true;
6450 }
6451
6452 return false;
6453 }
6454
6455
6456 /* Return the bytes needed to compute the frame pointer from the current
6457 stack pointer. SIZE is the size (in bytes) of the local variables.
6458
6459 MIPS stack frames look like:
6460
6461 Before call After call
6462 +-----------------------+ +-----------------------+
6463 high | | | |
6464 mem. | | | |
6465 | caller's temps. | | caller's temps. |
6466 | | | |
6467 +-----------------------+ +-----------------------+
6468 | | | |
6469 | arguments on stack. | | arguments on stack. |
6470 | | | |
6471 +-----------------------+ +-----------------------+
6472 | 4 words to save | | 4 words to save |
6473 | arguments passed | | arguments passed |
6474 | in registers, even | | in registers, even |
6475 SP->| if not passed. | VFP->| if not passed. |
6476 +-----------------------+ +-----------------------+
6477 | |
6478 | fp register save |
6479 | |
6480 +-----------------------+
6481 | |
6482 | gp register save |
6483 | |
6484 +-----------------------+
6485 | |
6486 | local variables |
6487 | |
6488 +-----------------------+
6489 | |
6490 | alloca allocations |
6491 | |
6492 +-----------------------+
6493 | |
6494 | GP save for V.4 abi |
6495 | |
6496 +-----------------------+
6497 | |
6498 | arguments on stack |
6499 | |
6500 +-----------------------+
6501 | 4 words to save |
6502 | arguments passed |
6503 | in registers, even |
6504 low SP->| if not passed. |
6505 memory +-----------------------+
6506
6507 */
6508
6509 HOST_WIDE_INT
6510 compute_frame_size (HOST_WIDE_INT size)
6511 {
6512 unsigned int regno;
6513 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6514 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6515 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6516 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6517 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6518 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6519 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6520 unsigned int mask; /* mask of saved gp registers */
6521 unsigned int fmask; /* mask of saved fp registers */
6522
6523 cfun->machine->global_pointer = mips_global_pointer ();
6524
6525 gp_reg_size = 0;
6526 fp_reg_size = 0;
6527 mask = 0;
6528 fmask = 0;
6529 var_size = MIPS_STACK_ALIGN (size);
6530 args_size = current_function_outgoing_args_size;
6531 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6532
6533 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6534 functions. If the function has local variables, we're committed
6535 to allocating it anyway. Otherwise reclaim it here. */
6536 if (var_size == 0 && current_function_is_leaf)
6537 cprestore_size = args_size = 0;
6538
6539 /* The MIPS 3.0 linker does not like functions that dynamically
6540 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6541 looks like we are trying to create a second frame pointer to the
6542 function, so allocate some stack space to make it happy. */
6543
6544 if (args_size == 0 && current_function_calls_alloca)
6545 args_size = 4 * UNITS_PER_WORD;
6546
6547 total_size = var_size + args_size + cprestore_size;
6548
6549 /* Calculate space needed for gp registers. */
6550 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6551 if (mips_save_reg_p (regno))
6552 {
6553 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6554 mask |= 1 << (regno - GP_REG_FIRST);
6555 }
6556
6557 /* We need to restore these for the handler. */
6558 if (current_function_calls_eh_return)
6559 {
6560 unsigned int i;
6561 for (i = 0; ; ++i)
6562 {
6563 regno = EH_RETURN_DATA_REGNO (i);
6564 if (regno == INVALID_REGNUM)
6565 break;
6566 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6567 mask |= 1 << (regno - GP_REG_FIRST);
6568 }
6569 }
6570
6571 /* This loop must iterate over the same space as its companion in
6572 mips_for_each_saved_reg. */
6573 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6574 regno >= FP_REG_FIRST;
6575 regno -= MAX_FPRS_PER_FMT)
6576 {
6577 if (mips_save_reg_p (regno))
6578 {
6579 fp_reg_size += MAX_FPRS_PER_FMT * UNITS_PER_FPREG;
6580 fmask |= ((1 << MAX_FPRS_PER_FMT) - 1) << (regno - FP_REG_FIRST);
6581 }
6582 }
6583
6584 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6585 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6586
6587 /* Add in the space required for saving incoming register arguments. */
6588 total_size += current_function_pretend_args_size;
6589 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6590
6591 /* Save other computed information. */
6592 cfun->machine->frame.total_size = total_size;
6593 cfun->machine->frame.var_size = var_size;
6594 cfun->machine->frame.args_size = args_size;
6595 cfun->machine->frame.cprestore_size = cprestore_size;
6596 cfun->machine->frame.gp_reg_size = gp_reg_size;
6597 cfun->machine->frame.fp_reg_size = fp_reg_size;
6598 cfun->machine->frame.mask = mask;
6599 cfun->machine->frame.fmask = fmask;
6600 cfun->machine->frame.initialized = reload_completed;
6601 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6602 cfun->machine->frame.num_fp = (fp_reg_size
6603 / (MAX_FPRS_PER_FMT * UNITS_PER_FPREG));
6604
6605 if (mask)
6606 {
6607 HOST_WIDE_INT offset;
6608
6609 offset = (args_size + cprestore_size + var_size
6610 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6611 cfun->machine->frame.gp_sp_offset = offset;
6612 cfun->machine->frame.gp_save_offset = offset - total_size;
6613 }
6614 else
6615 {
6616 cfun->machine->frame.gp_sp_offset = 0;
6617 cfun->machine->frame.gp_save_offset = 0;
6618 }
6619
6620 if (fmask)
6621 {
6622 HOST_WIDE_INT offset;
6623
6624 offset = (args_size + cprestore_size + var_size
6625 + gp_reg_rounded + fp_reg_size
6626 - MAX_FPRS_PER_FMT * UNITS_PER_FPREG);
6627 cfun->machine->frame.fp_sp_offset = offset;
6628 cfun->machine->frame.fp_save_offset = offset - total_size;
6629 }
6630 else
6631 {
6632 cfun->machine->frame.fp_sp_offset = 0;
6633 cfun->machine->frame.fp_save_offset = 0;
6634 }
6635
6636 /* Ok, we're done. */
6637 return total_size;
6638 }
6639 \f
6640 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6641 pointer or argument pointer. TO is either the stack pointer or
6642 hard frame pointer. */
6643
6644 HOST_WIDE_INT
6645 mips_initial_elimination_offset (int from, int to)
6646 {
6647 HOST_WIDE_INT offset;
6648
6649 compute_frame_size (get_frame_size ());
6650
6651 /* Set OFFSET to the offset from the stack pointer. */
6652 switch (from)
6653 {
6654 case FRAME_POINTER_REGNUM:
6655 offset = 0;
6656 break;
6657
6658 case ARG_POINTER_REGNUM:
6659 offset = (cfun->machine->frame.total_size
6660 - current_function_pretend_args_size);
6661 break;
6662
6663 default:
6664 gcc_unreachable ();
6665 }
6666
6667 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6668 offset -= cfun->machine->frame.args_size;
6669
6670 return offset;
6671 }
6672 \f
6673 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6674 back to a previous frame. */
6675 rtx
6676 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6677 {
6678 if (count != 0)
6679 return const0_rtx;
6680
6681 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6682 }
6683 \f
6684 /* Use FN to save or restore register REGNO. MODE is the register's
6685 mode and OFFSET is the offset of its save slot from the current
6686 stack pointer. */
6687
6688 static void
6689 mips_save_restore_reg (enum machine_mode mode, int regno,
6690 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6691 {
6692 rtx mem;
6693
6694 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6695
6696 fn (gen_rtx_REG (mode, regno), mem);
6697 }
6698
6699
6700 /* Call FN for each register that is saved by the current function.
6701 SP_OFFSET is the offset of the current stack pointer from the start
6702 of the frame. */
6703
6704 static void
6705 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6706 {
6707 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6708
6709 enum machine_mode fpr_mode;
6710 HOST_WIDE_INT offset;
6711 int regno;
6712
6713 /* Save registers starting from high to low. The debuggers prefer at least
6714 the return register be stored at func+4, and also it allows us not to
6715 need a nop in the epilogue if at least one register is reloaded in
6716 addition to return address. */
6717 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6718 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6719 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6720 {
6721 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6722 offset -= GET_MODE_SIZE (gpr_mode);
6723 }
6724
6725 /* This loop must iterate over the same space as its companion in
6726 compute_frame_size. */
6727 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6728 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6729 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6730 regno >= FP_REG_FIRST;
6731 regno -= MAX_FPRS_PER_FMT)
6732 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6733 {
6734 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6735 offset -= GET_MODE_SIZE (fpr_mode);
6736 }
6737 #undef BITSET_P
6738 }
6739 \f
6740 /* If we're generating n32 or n64 abicalls, and the current function
6741 does not use $28 as its global pointer, emit a cplocal directive.
6742 Use pic_offset_table_rtx as the argument to the directive. */
6743
6744 static void
6745 mips_output_cplocal (void)
6746 {
6747 if (!TARGET_EXPLICIT_RELOCS
6748 && cfun->machine->global_pointer > 0
6749 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6750 output_asm_insn (".cplocal %+", 0);
6751 }
6752
6753 /* Return the style of GP load sequence that is being used for the
6754 current function. */
6755
6756 enum mips_loadgp_style
6757 mips_current_loadgp_style (void)
6758 {
6759 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
6760 return LOADGP_NONE;
6761
6762 if (TARGET_RTP_PIC)
6763 return LOADGP_RTP;
6764
6765 if (TARGET_ABSOLUTE_ABICALLS)
6766 return LOADGP_ABSOLUTE;
6767
6768 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6769 }
6770
6771 /* The __gnu_local_gp symbol. */
6772
6773 static GTY(()) rtx mips_gnu_local_gp;
6774
6775 /* If we're generating n32 or n64 abicalls, emit instructions
6776 to set up the global pointer. */
6777
6778 static void
6779 mips_emit_loadgp (void)
6780 {
6781 rtx addr, offset, incoming_address, base, index;
6782
6783 switch (mips_current_loadgp_style ())
6784 {
6785 case LOADGP_ABSOLUTE:
6786 if (mips_gnu_local_gp == NULL)
6787 {
6788 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6789 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6790 }
6791 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
6792 break;
6793
6794 case LOADGP_NEWABI:
6795 addr = XEXP (DECL_RTL (current_function_decl), 0);
6796 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6797 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6798 emit_insn (gen_loadgp_newabi (offset, incoming_address));
6799 if (!TARGET_EXPLICIT_RELOCS)
6800 emit_insn (gen_loadgp_blockage ());
6801 break;
6802
6803 case LOADGP_RTP:
6804 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
6805 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
6806 emit_insn (gen_loadgp_rtp (base, index));
6807 if (!TARGET_EXPLICIT_RELOCS)
6808 emit_insn (gen_loadgp_blockage ());
6809 break;
6810
6811 default:
6812 break;
6813 }
6814 }
6815
6816 /* Set up the stack and frame (if desired) for the function. */
6817
6818 static void
6819 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6820 {
6821 const char *fnname;
6822 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6823
6824 #ifdef SDB_DEBUGGING_INFO
6825 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6826 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6827 #endif
6828
6829 /* In mips16 mode, we may need to generate a 32 bit to handle
6830 floating point arguments. The linker will arrange for any 32-bit
6831 functions to call this stub, which will then jump to the 16-bit
6832 function proper. */
6833 if (mips16_hard_float
6834 && current_function_args_info.fp_code != 0)
6835 build_mips16_function_stub (file);
6836
6837 if (!FUNCTION_NAME_ALREADY_DECLARED)
6838 {
6839 /* Get the function name the same way that toplev.c does before calling
6840 assemble_start_function. This is needed so that the name used here
6841 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6842 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6843
6844 if (!flag_inhibit_size_directive)
6845 {
6846 fputs ("\t.ent\t", file);
6847 assemble_name (file, fnname);
6848 fputs ("\n", file);
6849 }
6850
6851 assemble_name (file, fnname);
6852 fputs (":\n", file);
6853 }
6854
6855 /* Stop mips_file_end from treating this function as external. */
6856 if (TARGET_IRIX && mips_abi == ABI_32)
6857 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6858
6859 if (!flag_inhibit_size_directive)
6860 {
6861 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6862 fprintf (file,
6863 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6864 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6865 ", args= " HOST_WIDE_INT_PRINT_DEC
6866 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6867 (reg_names[(frame_pointer_needed)
6868 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6869 ((frame_pointer_needed && TARGET_MIPS16)
6870 ? tsize - cfun->machine->frame.args_size
6871 : tsize),
6872 reg_names[GP_REG_FIRST + 31],
6873 cfun->machine->frame.var_size,
6874 cfun->machine->frame.num_gp,
6875 cfun->machine->frame.num_fp,
6876 cfun->machine->frame.args_size,
6877 cfun->machine->frame.cprestore_size);
6878
6879 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6880 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6881 cfun->machine->frame.mask,
6882 cfun->machine->frame.gp_save_offset);
6883 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6884 cfun->machine->frame.fmask,
6885 cfun->machine->frame.fp_save_offset);
6886
6887 /* Require:
6888 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6889 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6890 }
6891
6892 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6893 {
6894 /* Handle the initialization of $gp for SVR4 PIC. */
6895 if (!cfun->machine->all_noreorder_p)
6896 output_asm_insn ("%(.cpload\t%^%)", 0);
6897 else
6898 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6899 }
6900 else if (cfun->machine->all_noreorder_p)
6901 output_asm_insn ("%(%<", 0);
6902
6903 /* Tell the assembler which register we're using as the global
6904 pointer. This is needed for thunks, since they can use either
6905 explicit relocs or assembler macros. */
6906 mips_output_cplocal ();
6907 }
6908 \f
6909 /* Make the last instruction frame related and note that it performs
6910 the operation described by FRAME_PATTERN. */
6911
6912 static void
6913 mips_set_frame_expr (rtx frame_pattern)
6914 {
6915 rtx insn;
6916
6917 insn = get_last_insn ();
6918 RTX_FRAME_RELATED_P (insn) = 1;
6919 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6920 frame_pattern,
6921 REG_NOTES (insn));
6922 }
6923
6924
6925 /* Return a frame-related rtx that stores REG at MEM.
6926 REG must be a single register. */
6927
6928 static rtx
6929 mips_frame_set (rtx mem, rtx reg)
6930 {
6931 rtx set;
6932
6933 /* If we're saving the return address register and the dwarf return
6934 address column differs from the hard register number, adjust the
6935 note reg to refer to the former. */
6936 if (REGNO (reg) == GP_REG_FIRST + 31
6937 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6938 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6939
6940 set = gen_rtx_SET (VOIDmode, mem, reg);
6941 RTX_FRAME_RELATED_P (set) = 1;
6942
6943 return set;
6944 }
6945
6946
6947 /* Save register REG to MEM. Make the instruction frame-related. */
6948
6949 static void
6950 mips_save_reg (rtx reg, rtx mem)
6951 {
6952 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6953 {
6954 rtx x1, x2;
6955
6956 if (mips_split_64bit_move_p (mem, reg))
6957 mips_split_64bit_move (mem, reg);
6958 else
6959 emit_move_insn (mem, reg);
6960
6961 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6962 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6963 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6964 }
6965 else
6966 {
6967 if (TARGET_MIPS16
6968 && REGNO (reg) != GP_REG_FIRST + 31
6969 && !M16_REG_P (REGNO (reg)))
6970 {
6971 /* Save a non-mips16 register by moving it through a temporary.
6972 We don't need to do this for $31 since there's a special
6973 instruction for it. */
6974 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6975 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6976 }
6977 else
6978 emit_move_insn (mem, reg);
6979
6980 mips_set_frame_expr (mips_frame_set (mem, reg));
6981 }
6982 }
6983
6984
6985 /* Expand the prologue into a bunch of separate insns. */
6986
6987 void
6988 mips_expand_prologue (void)
6989 {
6990 HOST_WIDE_INT size;
6991
6992 if (cfun->machine->global_pointer > 0)
6993 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6994
6995 size = compute_frame_size (get_frame_size ());
6996
6997 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6998 bytes beforehand; this is enough to cover the register save area
6999 without going out of range. */
7000 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7001 {
7002 HOST_WIDE_INT step1;
7003
7004 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
7005 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
7006 stack_pointer_rtx,
7007 GEN_INT (-step1)))) = 1;
7008 size -= step1;
7009 mips_for_each_saved_reg (size, mips_save_reg);
7010 }
7011
7012 /* Allocate the rest of the frame. */
7013 if (size > 0)
7014 {
7015 if (SMALL_OPERAND (-size))
7016 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
7017 stack_pointer_rtx,
7018 GEN_INT (-size)))) = 1;
7019 else
7020 {
7021 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
7022 if (TARGET_MIPS16)
7023 {
7024 /* There are no instructions to add or subtract registers
7025 from the stack pointer, so use the frame pointer as a
7026 temporary. We should always be using a frame pointer
7027 in this case anyway. */
7028 gcc_assert (frame_pointer_needed);
7029 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7030 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
7031 hard_frame_pointer_rtx,
7032 MIPS_PROLOGUE_TEMP (Pmode)));
7033 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7034 }
7035 else
7036 emit_insn (gen_sub3_insn (stack_pointer_rtx,
7037 stack_pointer_rtx,
7038 MIPS_PROLOGUE_TEMP (Pmode)));
7039
7040 /* Describe the combined effect of the previous instructions. */
7041 mips_set_frame_expr
7042 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7043 plus_constant (stack_pointer_rtx, -size)));
7044 }
7045 }
7046
7047 /* Set up the frame pointer, if we're using one. In mips16 code,
7048 we point the frame pointer ahead of the outgoing argument area.
7049 This should allow more variables & incoming arguments to be
7050 accessed with unextended instructions. */
7051 if (frame_pointer_needed)
7052 {
7053 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
7054 {
7055 rtx offset = GEN_INT (cfun->machine->frame.args_size);
7056 if (SMALL_OPERAND (cfun->machine->frame.args_size))
7057 RTX_FRAME_RELATED_P
7058 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7059 stack_pointer_rtx,
7060 offset))) = 1;
7061 else
7062 {
7063 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
7064 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7065 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7066 hard_frame_pointer_rtx,
7067 MIPS_PROLOGUE_TEMP (Pmode)));
7068 mips_set_frame_expr
7069 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
7070 plus_constant (stack_pointer_rtx,
7071 cfun->machine->frame.args_size)));
7072 }
7073 }
7074 else
7075 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
7076 stack_pointer_rtx)) = 1;
7077 }
7078
7079 mips_emit_loadgp ();
7080
7081 /* If generating o32/o64 abicalls, save $gp on the stack. */
7082 if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
7083 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
7084
7085 /* If we are profiling, make sure no instructions are scheduled before
7086 the call to mcount. */
7087
7088 if (current_function_profile)
7089 emit_insn (gen_blockage ());
7090 }
7091 \f
7092 /* Do any necessary cleanup after a function to restore stack, frame,
7093 and regs. */
7094
7095 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7096
7097 static void
7098 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7099 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7100 {
7101 /* Reinstate the normal $gp. */
7102 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
7103 mips_output_cplocal ();
7104
7105 if (cfun->machine->all_noreorder_p)
7106 {
7107 /* Avoid using %>%) since it adds excess whitespace. */
7108 output_asm_insn (".set\tmacro", 0);
7109 output_asm_insn (".set\treorder", 0);
7110 set_noreorder = set_nomacro = 0;
7111 }
7112
7113 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
7114 {
7115 const char *fnname;
7116
7117 /* Get the function name the same way that toplev.c does before calling
7118 assemble_start_function. This is needed so that the name used here
7119 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7120 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7121 fputs ("\t.end\t", file);
7122 assemble_name (file, fnname);
7123 fputs ("\n", file);
7124 }
7125 }
7126 \f
7127 /* Emit instructions to restore register REG from slot MEM. */
7128
7129 static void
7130 mips_restore_reg (rtx reg, rtx mem)
7131 {
7132 /* There's no mips16 instruction to load $31 directly. Load into
7133 $7 instead and adjust the return insn appropriately. */
7134 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
7135 reg = gen_rtx_REG (GET_MODE (reg), 7);
7136
7137 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
7138 {
7139 /* Can't restore directly; move through a temporary. */
7140 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
7141 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
7142 }
7143 else
7144 emit_move_insn (reg, mem);
7145 }
7146
7147
7148 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
7149 if this epilogue precedes a sibling call, false if it is for a normal
7150 "epilogue" pattern. */
7151
7152 void
7153 mips_expand_epilogue (int sibcall_p)
7154 {
7155 HOST_WIDE_INT step1, step2;
7156 rtx base, target;
7157
7158 if (!sibcall_p && mips_can_use_return_insn ())
7159 {
7160 emit_jump_insn (gen_return ());
7161 return;
7162 }
7163
7164 /* In mips16 mode, if the return value should go into a floating-point
7165 register, we need to call a helper routine to copy it over. */
7166 if (mips16_cfun_returns_in_fpr_p ())
7167 {
7168 char *name;
7169 rtx func;
7170 rtx insn;
7171 rtx retval;
7172 rtx call;
7173 tree id;
7174 tree return_type;
7175 enum machine_mode return_mode;
7176
7177 return_type = DECL_RESULT (current_function_decl);
7178 return_mode = DECL_MODE (return_type);
7179
7180 name = ACONCAT (("__mips16_ret_",
7181 mips16_call_stub_mode_suffix (return_mode),
7182 NULL));
7183 id = get_identifier (name);
7184 func = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7185 retval = gen_rtx_REG (return_mode, GP_RETURN);
7186 call = gen_call_value_internal (retval, func, const0_rtx);
7187 insn = emit_call_insn (call);
7188 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
7189 }
7190
7191 /* Split the frame into two. STEP1 is the amount of stack we should
7192 deallocate before restoring the registers. STEP2 is the amount we
7193 should deallocate afterwards.
7194
7195 Start off by assuming that no registers need to be restored. */
7196 step1 = cfun->machine->frame.total_size;
7197 step2 = 0;
7198
7199 /* Work out which register holds the frame address. Account for the
7200 frame pointer offset used by mips16 code. */
7201 if (!frame_pointer_needed)
7202 base = stack_pointer_rtx;
7203 else
7204 {
7205 base = hard_frame_pointer_rtx;
7206 if (TARGET_MIPS16)
7207 step1 -= cfun->machine->frame.args_size;
7208 }
7209
7210 /* If we need to restore registers, deallocate as much stack as
7211 possible in the second step without going out of range. */
7212 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7213 {
7214 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7215 step1 -= step2;
7216 }
7217
7218 /* Set TARGET to BASE + STEP1. */
7219 target = base;
7220 if (step1 > 0)
7221 {
7222 rtx adjust;
7223
7224 /* Get an rtx for STEP1 that we can add to BASE. */
7225 adjust = GEN_INT (step1);
7226 if (!SMALL_OPERAND (step1))
7227 {
7228 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7229 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7230 }
7231
7232 /* Normal mode code can copy the result straight into $sp. */
7233 if (!TARGET_MIPS16)
7234 target = stack_pointer_rtx;
7235
7236 emit_insn (gen_add3_insn (target, base, adjust));
7237 }
7238
7239 /* Copy TARGET into the stack pointer. */
7240 if (target != stack_pointer_rtx)
7241 emit_move_insn (stack_pointer_rtx, target);
7242
7243 /* If we're using addressing macros, $gp is implicitly used by all
7244 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
7245 from the stack. */
7246 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
7247 emit_insn (gen_blockage ());
7248
7249 /* Restore the registers. */
7250 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7251 mips_restore_reg);
7252
7253 /* Deallocate the final bit of the frame. */
7254 if (step2 > 0)
7255 emit_insn (gen_add3_insn (stack_pointer_rtx,
7256 stack_pointer_rtx,
7257 GEN_INT (step2)));
7258
7259 /* Add in the __builtin_eh_return stack adjustment. We need to
7260 use a temporary in mips16 code. */
7261 if (current_function_calls_eh_return)
7262 {
7263 if (TARGET_MIPS16)
7264 {
7265 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7266 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7267 MIPS_EPILOGUE_TEMP (Pmode),
7268 EH_RETURN_STACKADJ_RTX));
7269 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7270 }
7271 else
7272 emit_insn (gen_add3_insn (stack_pointer_rtx,
7273 stack_pointer_rtx,
7274 EH_RETURN_STACKADJ_RTX));
7275 }
7276
7277 if (!sibcall_p)
7278 {
7279 /* The mips16 loads the return address into $7, not $31. */
7280 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7281 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7282 GP_REG_FIRST + 7)));
7283 else
7284 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7285 GP_REG_FIRST + 31)));
7286 }
7287 }
7288 \f
7289 /* Return nonzero if this function is known to have a null epilogue.
7290 This allows the optimizer to omit jumps to jumps if no stack
7291 was created. */
7292
7293 int
7294 mips_can_use_return_insn (void)
7295 {
7296 if (! reload_completed)
7297 return 0;
7298
7299 if (regs_ever_live[31] || current_function_profile)
7300 return 0;
7301
7302 /* In mips16 mode, a function that returns a floating point value
7303 needs to arrange to copy the return value into the floating point
7304 registers. */
7305 if (mips16_cfun_returns_in_fpr_p ())
7306 return 0;
7307
7308 if (cfun->machine->frame.initialized)
7309 return cfun->machine->frame.total_size == 0;
7310
7311 return compute_frame_size (get_frame_size ()) == 0;
7312 }
7313 \f
7314 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7315 in order to avoid duplicating too much logic from elsewhere. */
7316
7317 static void
7318 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7319 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7320 tree function)
7321 {
7322 rtx this, temp1, temp2, insn, fnaddr;
7323
7324 /* Pretend to be a post-reload pass while generating rtl. */
7325 no_new_pseudos = 1;
7326 reload_completed = 1;
7327
7328 /* Mark the end of the (empty) prologue. */
7329 emit_note (NOTE_INSN_PROLOGUE_END);
7330
7331 /* Pick a global pointer. Use a call-clobbered register if
7332 TARGET_CALL_SAVED_GP, so that we can use a sibcall. */
7333 if (TARGET_USE_GOT)
7334 cfun->machine->global_pointer
7335 = REGNO (pic_offset_table_rtx)
7336 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
7337
7338 /* Set up the global pointer for n32 or n64 abicalls. */
7339 mips_emit_loadgp ();
7340
7341 /* We need two temporary registers in some cases. */
7342 temp1 = gen_rtx_REG (Pmode, 2);
7343 temp2 = gen_rtx_REG (Pmode, 3);
7344
7345 /* Find out which register contains the "this" pointer. */
7346 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7347 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7348 else
7349 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7350
7351 /* Add DELTA to THIS. */
7352 if (delta != 0)
7353 {
7354 rtx offset = GEN_INT (delta);
7355 if (!SMALL_OPERAND (delta))
7356 {
7357 emit_move_insn (temp1, offset);
7358 offset = temp1;
7359 }
7360 emit_insn (gen_add3_insn (this, this, offset));
7361 }
7362
7363 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7364 if (vcall_offset != 0)
7365 {
7366 rtx addr;
7367
7368 /* Set TEMP1 to *THIS. */
7369 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7370
7371 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7372 addr = mips_add_offset (temp2, temp1, vcall_offset);
7373
7374 /* Load the offset and add it to THIS. */
7375 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7376 emit_insn (gen_add3_insn (this, this, temp1));
7377 }
7378
7379 /* Jump to the target function. Use a sibcall if direct jumps are
7380 allowed, otherwise load the address into a register first. */
7381 fnaddr = XEXP (DECL_RTL (function), 0);
7382 if (TARGET_MIPS16 || TARGET_USE_GOT || SYMBOL_REF_LONG_CALL_P (fnaddr))
7383 {
7384 /* This is messy. gas treats "la $25,foo" as part of a call
7385 sequence and may allow a global "foo" to be lazily bound.
7386 The general move patterns therefore reject this combination.
7387
7388 In this context, lazy binding would actually be OK
7389 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
7390 TARGET_CALL_SAVED_GP; see mips_load_call_address.
7391 We must therefore load the address via a temporary
7392 register if mips_dangerous_for_la25_p.
7393
7394 If we jump to the temporary register rather than $25, the assembler
7395 can use the move insn to fill the jump's delay slot. */
7396 if (TARGET_USE_PIC_FN_ADDR_REG
7397 && !mips_dangerous_for_la25_p (fnaddr))
7398 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7399 mips_load_call_address (temp1, fnaddr, true);
7400
7401 if (TARGET_USE_PIC_FN_ADDR_REG
7402 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7403 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7404 emit_jump_insn (gen_indirect_jump (temp1));
7405 }
7406 else
7407 {
7408 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7409 SIBLING_CALL_P (insn) = 1;
7410 }
7411
7412 /* Run just enough of rest_of_compilation. This sequence was
7413 "borrowed" from alpha.c. */
7414 insn = get_insns ();
7415 insn_locators_alloc ();
7416 split_all_insns_noflow ();
7417 if (TARGET_MIPS16)
7418 mips16_lay_out_constants ();
7419 shorten_branches (insn);
7420 final_start_function (insn, file, 1);
7421 final (insn, file, 1);
7422 final_end_function ();
7423
7424 /* Clean up the vars set above. Note that final_end_function resets
7425 the global pointer for us. */
7426 reload_completed = 0;
7427 no_new_pseudos = 0;
7428 }
7429 \f
7430 /* Returns nonzero if X contains a SYMBOL_REF. */
7431
7432 static int
7433 symbolic_expression_p (rtx x)
7434 {
7435 if (GET_CODE (x) == SYMBOL_REF)
7436 return 1;
7437
7438 if (GET_CODE (x) == CONST)
7439 return symbolic_expression_p (XEXP (x, 0));
7440
7441 if (UNARY_P (x))
7442 return symbolic_expression_p (XEXP (x, 0));
7443
7444 if (ARITHMETIC_P (x))
7445 return (symbolic_expression_p (XEXP (x, 0))
7446 || symbolic_expression_p (XEXP (x, 1)));
7447
7448 return 0;
7449 }
7450
7451 /* Choose the section to use for the constant rtx expression X that has
7452 mode MODE. */
7453
7454 static section *
7455 mips_select_rtx_section (enum machine_mode mode, rtx x,
7456 unsigned HOST_WIDE_INT align)
7457 {
7458 if (TARGET_MIPS16)
7459 {
7460 /* In mips16 mode, the constant table always goes in the same section
7461 as the function, so that constants can be loaded using PC relative
7462 addressing. */
7463 return function_section (current_function_decl);
7464 }
7465 else if (TARGET_EMBEDDED_DATA)
7466 {
7467 /* For embedded applications, always put constants in read-only data,
7468 in order to reduce RAM usage. */
7469 return mergeable_constant_section (mode, align, 0);
7470 }
7471 else
7472 {
7473 /* For hosted applications, always put constants in small data if
7474 possible, as this gives the best performance. */
7475 /* ??? Consider using mergeable small data sections. */
7476
7477 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7478 && mips_section_threshold > 0)
7479 return get_named_section (NULL, ".sdata", 0);
7480 else if (flag_pic && symbolic_expression_p (x))
7481 return get_named_section (NULL, ".data.rel.ro", 3);
7482 else
7483 return mergeable_constant_section (mode, align, 0);
7484 }
7485 }
7486
7487 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7488
7489 The complication here is that, with the combination TARGET_ABICALLS
7490 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7491 therefore not be included in the read-only part of a DSO. Handle such
7492 cases by selecting a normal data section instead of a read-only one.
7493 The logic apes that in default_function_rodata_section. */
7494
7495 static section *
7496 mips_function_rodata_section (tree decl)
7497 {
7498 if (!TARGET_ABICALLS || TARGET_GPWORD)
7499 return default_function_rodata_section (decl);
7500
7501 if (decl && DECL_SECTION_NAME (decl))
7502 {
7503 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7504 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7505 {
7506 char *rname = ASTRDUP (name);
7507 rname[14] = 'd';
7508 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7509 }
7510 else if (flag_function_sections && flag_data_sections
7511 && strncmp (name, ".text.", 6) == 0)
7512 {
7513 char *rname = ASTRDUP (name);
7514 memcpy (rname + 1, "data", 4);
7515 return get_section (rname, SECTION_WRITE, decl);
7516 }
7517 }
7518 return data_section;
7519 }
7520
7521 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
7522 locally-defined objects go in a small data section. It also controls
7523 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7524 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
7525
7526 static bool
7527 mips_in_small_data_p (tree decl)
7528 {
7529 HOST_WIDE_INT size;
7530
7531 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7532 return false;
7533
7534 /* We don't yet generate small-data references for -mabicalls or
7535 VxWorks RTP code. See the related -G handling in override_options. */
7536 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7537 return false;
7538
7539 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7540 {
7541 const char *name;
7542
7543 /* Reject anything that isn't in a known small-data section. */
7544 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7545 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7546 return false;
7547
7548 /* If a symbol is defined externally, the assembler will use the
7549 usual -G rules when deciding how to implement macros. */
7550 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7551 return true;
7552 }
7553 else if (TARGET_EMBEDDED_DATA)
7554 {
7555 /* Don't put constants into the small data section: we want them
7556 to be in ROM rather than RAM. */
7557 if (TREE_CODE (decl) != VAR_DECL)
7558 return false;
7559
7560 if (TREE_READONLY (decl)
7561 && !TREE_SIDE_EFFECTS (decl)
7562 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7563 return false;
7564 }
7565
7566 size = int_size_in_bytes (TREE_TYPE (decl));
7567 return (size > 0 && size <= mips_section_threshold);
7568 }
7569
7570 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7571 anchors for small data: the GP register acts as an anchor in that
7572 case. We also don't want to use them for PC-relative accesses,
7573 where the PC acts as an anchor. */
7574
7575 static bool
7576 mips_use_anchors_for_symbol_p (rtx symbol)
7577 {
7578 switch (mips_classify_symbol (symbol))
7579 {
7580 case SYMBOL_CONSTANT_POOL:
7581 case SYMBOL_SMALL_DATA:
7582 return false;
7583
7584 default:
7585 return true;
7586 }
7587 }
7588 \f
7589 /* See whether VALTYPE is a record whose fields should be returned in
7590 floating-point registers. If so, return the number of fields and
7591 list them in FIELDS (which should have two elements). Return 0
7592 otherwise.
7593
7594 For n32 & n64, a structure with one or two fields is returned in
7595 floating-point registers as long as every field has a floating-point
7596 type. */
7597
7598 static int
7599 mips_fpr_return_fields (tree valtype, tree *fields)
7600 {
7601 tree field;
7602 int i;
7603
7604 if (!TARGET_NEWABI)
7605 return 0;
7606
7607 if (TREE_CODE (valtype) != RECORD_TYPE)
7608 return 0;
7609
7610 i = 0;
7611 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7612 {
7613 if (TREE_CODE (field) != FIELD_DECL)
7614 continue;
7615
7616 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7617 return 0;
7618
7619 if (i == 2)
7620 return 0;
7621
7622 fields[i++] = field;
7623 }
7624 return i;
7625 }
7626
7627
7628 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7629 a value in the most significant part of $2/$3 if:
7630
7631 - the target is big-endian;
7632
7633 - the value has a structure or union type (we generalize this to
7634 cover aggregates from other languages too); and
7635
7636 - the structure is not returned in floating-point registers. */
7637
7638 static bool
7639 mips_return_in_msb (tree valtype)
7640 {
7641 tree fields[2];
7642
7643 return (TARGET_NEWABI
7644 && TARGET_BIG_ENDIAN
7645 && AGGREGATE_TYPE_P (valtype)
7646 && mips_fpr_return_fields (valtype, fields) == 0);
7647 }
7648
7649
7650 /* Return a composite value in a pair of floating-point registers.
7651 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7652 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7653 complete value.
7654
7655 For n32 & n64, $f0 always holds the first value and $f2 the second.
7656 Otherwise the values are packed together as closely as possible. */
7657
7658 static rtx
7659 mips_return_fpr_pair (enum machine_mode mode,
7660 enum machine_mode mode1, HOST_WIDE_INT offset1,
7661 enum machine_mode mode2, HOST_WIDE_INT offset2)
7662 {
7663 int inc;
7664
7665 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
7666 return gen_rtx_PARALLEL
7667 (mode,
7668 gen_rtvec (2,
7669 gen_rtx_EXPR_LIST (VOIDmode,
7670 gen_rtx_REG (mode1, FP_RETURN),
7671 GEN_INT (offset1)),
7672 gen_rtx_EXPR_LIST (VOIDmode,
7673 gen_rtx_REG (mode2, FP_RETURN + inc),
7674 GEN_INT (offset2))));
7675
7676 }
7677
7678
7679 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7680 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7681 VALTYPE is null and MODE is the mode of the return value. */
7682
7683 rtx
7684 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7685 enum machine_mode mode)
7686 {
7687 if (valtype)
7688 {
7689 tree fields[2];
7690 int unsignedp;
7691
7692 mode = TYPE_MODE (valtype);
7693 unsignedp = TYPE_UNSIGNED (valtype);
7694
7695 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7696 true, we must promote the mode just as PROMOTE_MODE does. */
7697 mode = promote_mode (valtype, mode, &unsignedp, 1);
7698
7699 /* Handle structures whose fields are returned in $f0/$f2. */
7700 switch (mips_fpr_return_fields (valtype, fields))
7701 {
7702 case 1:
7703 return gen_rtx_REG (mode, FP_RETURN);
7704
7705 case 2:
7706 return mips_return_fpr_pair (mode,
7707 TYPE_MODE (TREE_TYPE (fields[0])),
7708 int_byte_position (fields[0]),
7709 TYPE_MODE (TREE_TYPE (fields[1])),
7710 int_byte_position (fields[1]));
7711 }
7712
7713 /* If a value is passed in the most significant part of a register, see
7714 whether we have to round the mode up to a whole number of words. */
7715 if (mips_return_in_msb (valtype))
7716 {
7717 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7718 if (size % UNITS_PER_WORD != 0)
7719 {
7720 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7721 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7722 }
7723 }
7724
7725 /* For EABI, the class of return register depends entirely on MODE.
7726 For example, "struct { some_type x; }" and "union { some_type x; }"
7727 are returned in the same way as a bare "some_type" would be.
7728 Other ABIs only use FPRs for scalar, complex or vector types. */
7729 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7730 return gen_rtx_REG (mode, GP_RETURN);
7731 }
7732
7733 if (!TARGET_MIPS16)
7734 {
7735 /* Handle long doubles for n32 & n64. */
7736 if (mode == TFmode)
7737 return mips_return_fpr_pair (mode,
7738 DImode, 0,
7739 DImode, GET_MODE_SIZE (mode) / 2);
7740
7741 if (mips_return_mode_in_fpr_p (mode))
7742 {
7743 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7744 return mips_return_fpr_pair (mode,
7745 GET_MODE_INNER (mode), 0,
7746 GET_MODE_INNER (mode),
7747 GET_MODE_SIZE (mode) / 2);
7748 else
7749 return gen_rtx_REG (mode, FP_RETURN);
7750 }
7751 }
7752
7753 return gen_rtx_REG (mode, GP_RETURN);
7754 }
7755
7756 /* Return nonzero when an argument must be passed by reference. */
7757
7758 static bool
7759 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7760 enum machine_mode mode, tree type,
7761 bool named ATTRIBUTE_UNUSED)
7762 {
7763 if (mips_abi == ABI_EABI)
7764 {
7765 int size;
7766
7767 /* ??? How should SCmode be handled? */
7768 if (mode == DImode || mode == DFmode)
7769 return 0;
7770
7771 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
7772 return size == -1 || size > UNITS_PER_WORD;
7773 }
7774 else
7775 {
7776 /* If we have a variable-sized parameter, we have no choice. */
7777 return targetm.calls.must_pass_in_stack (mode, type);
7778 }
7779 }
7780
7781 static bool
7782 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7783 enum machine_mode mode ATTRIBUTE_UNUSED,
7784 tree type ATTRIBUTE_UNUSED, bool named)
7785 {
7786 return mips_abi == ABI_EABI && named;
7787 }
7788
7789 /* Return true if registers of class CLASS cannot change from mode FROM
7790 to mode TO. */
7791
7792 bool
7793 mips_cannot_change_mode_class (enum machine_mode from,
7794 enum machine_mode to, enum reg_class class)
7795 {
7796 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7797 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7798 {
7799 if (TARGET_BIG_ENDIAN)
7800 {
7801 /* When a multi-word value is stored in paired floating-point
7802 registers, the first register always holds the low word.
7803 We therefore can't allow FPRs to change between single-word
7804 and multi-word modes. */
7805 if (MAX_FPRS_PER_FMT > 1 && reg_classes_intersect_p (FP_REGS, class))
7806 return true;
7807 }
7808 else
7809 {
7810 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7811 in LO and HI, the high word always comes first. We therefore
7812 can't allow values stored in HI to change between single-word
7813 and multi-word modes.
7814 This rule applies to both the original HI/LO pair and the new
7815 DSP accumulators. */
7816 if (reg_classes_intersect_p (ACC_REGS, class))
7817 return true;
7818 }
7819 }
7820
7821 /* gcc assumes that each word of a multiword register can be accessed
7822 individually using SUBREGs. This is not true for floating-point
7823 registers if they are bigger than a word. */
7824 if (UNITS_PER_FPREG > UNITS_PER_WORD
7825 && GET_MODE_SIZE (from) > UNITS_PER_WORD
7826 && GET_MODE_SIZE (to) < UNITS_PER_FPREG
7827 && reg_classes_intersect_p (FP_REGS, class))
7828 return true;
7829
7830 /* Loading a 32-bit value into a 64-bit floating-point register
7831 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7832 We can't allow 64-bit float registers to change from SImode to
7833 to a wider mode. */
7834 if (TARGET_64BIT
7835 && TARGET_FLOAT64
7836 && from == SImode
7837 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7838 && reg_classes_intersect_p (FP_REGS, class))
7839 return true;
7840
7841 return false;
7842 }
7843
7844 /* Return true if X should not be moved directly into register $25.
7845 We need this because many versions of GAS will treat "la $25,foo" as
7846 part of a call sequence and so allow a global "foo" to be lazily bound. */
7847
7848 bool
7849 mips_dangerous_for_la25_p (rtx x)
7850 {
7851 return (!TARGET_EXPLICIT_RELOCS
7852 && TARGET_USE_GOT
7853 && GET_CODE (x) == SYMBOL_REF
7854 && mips_global_symbol_p (x));
7855 }
7856
7857 /* Implement PREFERRED_RELOAD_CLASS. */
7858
7859 enum reg_class
7860 mips_preferred_reload_class (rtx x, enum reg_class class)
7861 {
7862 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7863 return LEA_REGS;
7864
7865 if (TARGET_HARD_FLOAT
7866 && FLOAT_MODE_P (GET_MODE (x))
7867 && reg_class_subset_p (FP_REGS, class))
7868 return FP_REGS;
7869
7870 if (reg_class_subset_p (GR_REGS, class))
7871 class = GR_REGS;
7872
7873 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7874 class = M16_REGS;
7875
7876 return class;
7877 }
7878
7879 /* This function returns the register class required for a secondary
7880 register when copying between one of the registers in CLASS, and X,
7881 using MODE. If IN_P is nonzero, the copy is going from X to the
7882 register, otherwise the register is the source. A return value of
7883 NO_REGS means that no secondary register is required. */
7884
7885 enum reg_class
7886 mips_secondary_reload_class (enum reg_class class,
7887 enum machine_mode mode, rtx x, int in_p)
7888 {
7889 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7890 int regno = -1;
7891 int gp_reg_p;
7892
7893 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7894 regno = true_regnum (x);
7895
7896 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7897
7898 if (mips_dangerous_for_la25_p (x))
7899 {
7900 gr_regs = LEA_REGS;
7901 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7902 return gr_regs;
7903 }
7904
7905 /* Copying from HI or LO to anywhere other than a general register
7906 requires a general register.
7907 This rule applies to both the original HI/LO pair and the new
7908 DSP accumulators. */
7909 if (reg_class_subset_p (class, ACC_REGS))
7910 {
7911 if (TARGET_MIPS16 && in_p)
7912 {
7913 /* We can't really copy to HI or LO at all in mips16 mode. */
7914 return M16_REGS;
7915 }
7916 return gp_reg_p ? NO_REGS : gr_regs;
7917 }
7918 if (ACC_REG_P (regno))
7919 {
7920 if (TARGET_MIPS16 && ! in_p)
7921 {
7922 /* We can't really copy to HI or LO at all in mips16 mode. */
7923 return M16_REGS;
7924 }
7925 return class == gr_regs ? NO_REGS : gr_regs;
7926 }
7927
7928 /* We can only copy a value to a condition code register from a
7929 floating point register, and even then we require a scratch
7930 floating point register. We can only copy a value out of a
7931 condition code register into a general register. */
7932 if (class == ST_REGS)
7933 {
7934 if (in_p)
7935 return FP_REGS;
7936 return gp_reg_p ? NO_REGS : gr_regs;
7937 }
7938 if (ST_REG_P (regno))
7939 {
7940 if (! in_p)
7941 return FP_REGS;
7942 return class == gr_regs ? NO_REGS : gr_regs;
7943 }
7944
7945 if (class == FP_REGS)
7946 {
7947 if (MEM_P (x))
7948 {
7949 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7950 return NO_REGS;
7951 }
7952 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7953 {
7954 /* We can use the l.s and l.d macros to load floating-point
7955 constants. ??? For l.s, we could probably get better
7956 code by returning GR_REGS here. */
7957 return NO_REGS;
7958 }
7959 else if (gp_reg_p || x == CONST0_RTX (mode))
7960 {
7961 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7962 return NO_REGS;
7963 }
7964 else if (FP_REG_P (regno))
7965 {
7966 /* In this case we can use mov.s or mov.d. */
7967 return NO_REGS;
7968 }
7969 else
7970 {
7971 /* Otherwise, we need to reload through an integer register. */
7972 return gr_regs;
7973 }
7974 }
7975
7976 /* In mips16 mode, going between memory and anything but M16_REGS
7977 requires an M16_REG. */
7978 if (TARGET_MIPS16)
7979 {
7980 if (class != M16_REGS && class != M16_NA_REGS)
7981 {
7982 if (gp_reg_p)
7983 return NO_REGS;
7984 return M16_REGS;
7985 }
7986 if (! gp_reg_p)
7987 {
7988 if (class == M16_REGS || class == M16_NA_REGS)
7989 return NO_REGS;
7990 return M16_REGS;
7991 }
7992 }
7993
7994 return NO_REGS;
7995 }
7996
7997 /* Implement CLASS_MAX_NREGS.
7998
7999 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
8000
8001 - ST_REGS are always hold CCmode values, and CCmode values are
8002 considered to be 4 bytes wide.
8003
8004 All other register classes are covered by UNITS_PER_WORD. Note that
8005 this is true even for unions of integer and float registers when the
8006 latter are smaller than the former. The only supported combination
8007 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
8008 words but 32-bit float registers. A word-based calculation is correct
8009 in that case since -msingle-float disallows multi-FPR values. */
8010
8011 int
8012 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
8013 enum machine_mode mode)
8014 {
8015 if (class == ST_REGS)
8016 return (GET_MODE_SIZE (mode) + 3) / 4;
8017 else if (class == FP_REGS)
8018 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8019 else
8020 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8021 }
8022
8023 static bool
8024 mips_valid_pointer_mode (enum machine_mode mode)
8025 {
8026 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8027 }
8028
8029 /* Target hook for vector_mode_supported_p. */
8030
8031 static bool
8032 mips_vector_mode_supported_p (enum machine_mode mode)
8033 {
8034 switch (mode)
8035 {
8036 case V2SFmode:
8037 return TARGET_PAIRED_SINGLE_FLOAT;
8038
8039 case V2HImode:
8040 case V4QImode:
8041 return TARGET_DSP;
8042
8043 default:
8044 return false;
8045 }
8046 }
8047 \f
8048 /* If we can access small data directly (using gp-relative relocation
8049 operators) return the small data pointer, otherwise return null.
8050
8051 For each mips16 function which refers to GP relative symbols, we
8052 use a pseudo register, initialized at the start of the function, to
8053 hold the $gp value. */
8054
8055 static rtx
8056 mips16_gp_pseudo_reg (void)
8057 {
8058 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8059 {
8060 rtx insn, scan;
8061
8062 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8063
8064 /* We want to initialize this to a value which gcc will believe
8065 is constant. */
8066 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
8067
8068 push_topmost_sequence ();
8069 /* We need to emit the initialization after the FUNCTION_BEG
8070 note, so that it will be integrated. */
8071 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8072 if (NOTE_P (scan)
8073 && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
8074 break;
8075 if (scan == NULL_RTX)
8076 scan = get_insns ();
8077 insn = emit_insn_after (insn, scan);
8078 pop_topmost_sequence ();
8079 }
8080
8081 return cfun->machine->mips16_gp_pseudo_rtx;
8082 }
8083
8084 /* Write out code to move floating point arguments in or out of
8085 general registers. Output the instructions to FILE. FP_CODE is
8086 the code describing which arguments are present (see the comment at
8087 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
8088 we are copying from the floating point registers. */
8089
8090 static void
8091 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
8092 {
8093 const char *s;
8094 int gparg, fparg;
8095 unsigned int f;
8096 CUMULATIVE_ARGS cum;
8097
8098 /* This code only works for the original 32-bit ABI and the O64 ABI. */
8099 gcc_assert (TARGET_OLDABI);
8100
8101 if (from_fp_p)
8102 s = "mfc1";
8103 else
8104 s = "mtc1";
8105
8106 init_cumulative_args (&cum, NULL, NULL);
8107
8108 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8109 {
8110 enum machine_mode mode;
8111 struct mips_arg_info info;
8112
8113 if ((f & 3) == 1)
8114 mode = SFmode;
8115 else if ((f & 3) == 2)
8116 mode = DFmode;
8117 else
8118 gcc_unreachable ();
8119
8120 mips_arg_info (&cum, mode, NULL, true, &info);
8121 gparg = mips_arg_regno (&info, false);
8122 fparg = mips_arg_regno (&info, true);
8123
8124 if (mode == SFmode)
8125 fprintf (file, "\t%s\t%s,%s\n", s,
8126 reg_names[gparg], reg_names[fparg]);
8127 else if (TARGET_64BIT)
8128 fprintf (file, "\td%s\t%s,%s\n", s,
8129 reg_names[gparg], reg_names[fparg]);
8130 else if (ISA_HAS_MXHC1)
8131 /* -mips32r2 -mfp64 */
8132 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n",
8133 s,
8134 reg_names[gparg + (WORDS_BIG_ENDIAN ? 1 : 0)],
8135 reg_names[fparg],
8136 from_fp_p ? "mfhc1" : "mthc1",
8137 reg_names[gparg + (WORDS_BIG_ENDIAN ? 0 : 1)],
8138 reg_names[fparg]);
8139 else if (TARGET_BIG_ENDIAN)
8140 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8141 reg_names[gparg], reg_names[fparg + 1], s,
8142 reg_names[gparg + 1], reg_names[fparg]);
8143 else
8144 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8145 reg_names[gparg], reg_names[fparg], s,
8146 reg_names[gparg + 1], reg_names[fparg + 1]);
8147
8148 function_arg_advance (&cum, mode, NULL, true);
8149 }
8150 }
8151
8152 /* Build a mips16 function stub. This is used for functions which
8153 take arguments in the floating point registers. It is 32-bit code
8154 that moves the floating point args into the general registers, and
8155 then jumps to the 16-bit code. */
8156
8157 static void
8158 build_mips16_function_stub (FILE *file)
8159 {
8160 const char *fnname;
8161 char *secname, *stubname;
8162 tree stubid, stubdecl;
8163 int need_comma;
8164 unsigned int f;
8165
8166 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8167 secname = (char *) alloca (strlen (fnname) + 20);
8168 sprintf (secname, ".mips16.fn.%s", fnname);
8169 stubname = (char *) alloca (strlen (fnname) + 20);
8170 sprintf (stubname, "__fn_stub_%s", fnname);
8171 stubid = get_identifier (stubname);
8172 stubdecl = build_decl (FUNCTION_DECL, stubid,
8173 build_function_type (void_type_node, NULL_TREE));
8174 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8175 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
8176
8177 fprintf (file, "\t# Stub function for %s (", current_function_name ());
8178 need_comma = 0;
8179 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8180 {
8181 fprintf (file, "%s%s",
8182 need_comma ? ", " : "",
8183 (f & 3) == 1 ? "float" : "double");
8184 need_comma = 1;
8185 }
8186 fprintf (file, ")\n");
8187
8188 fprintf (file, "\t.set\tnomips16\n");
8189 switch_to_section (function_section (stubdecl));
8190 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8191
8192 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8193 within a .ent, and we cannot emit another .ent. */
8194 if (!FUNCTION_NAME_ALREADY_DECLARED)
8195 {
8196 fputs ("\t.ent\t", file);
8197 assemble_name (file, stubname);
8198 fputs ("\n", file);
8199 }
8200
8201 assemble_name (file, stubname);
8202 fputs (":\n", file);
8203
8204 /* We don't want the assembler to insert any nops here. */
8205 fprintf (file, "\t.set\tnoreorder\n");
8206
8207 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8208
8209 fprintf (asm_out_file, "\t.set\tnoat\n");
8210 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8211 assemble_name (file, fnname);
8212 fprintf (file, "\n");
8213 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8214 fprintf (asm_out_file, "\t.set\tat\n");
8215
8216 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8217 with one of the mfc1 instructions, because the result is not
8218 available for one instruction, so if the very first instruction
8219 in the function refers to the register, it will see the wrong
8220 value. */
8221 fprintf (file, "\tnop\n");
8222
8223 fprintf (file, "\t.set\treorder\n");
8224
8225 if (!FUNCTION_NAME_ALREADY_DECLARED)
8226 {
8227 fputs ("\t.end\t", file);
8228 assemble_name (file, stubname);
8229 fputs ("\n", file);
8230 }
8231
8232 fprintf (file, "\t.set\tmips16\n");
8233
8234 switch_to_section (function_section (current_function_decl));
8235 }
8236
8237 /* We keep a list of functions for which we have already built stubs
8238 in build_mips16_call_stub. */
8239
8240 struct mips16_stub
8241 {
8242 struct mips16_stub *next;
8243 char *name;
8244 int fpret;
8245 };
8246
8247 static struct mips16_stub *mips16_stubs;
8248
8249 /* Emit code to return a double value from a mips16 stub. GPREG is the
8250 first GP reg to use, FPREG is the first FP reg to use. */
8251
8252 static void
8253 mips16_fpret_double (int gpreg, int fpreg)
8254 {
8255 if (TARGET_64BIT)
8256 fprintf (asm_out_file, "\tdmfc1\t%s,%s\n",
8257 reg_names[gpreg], reg_names[fpreg]);
8258 else if (TARGET_FLOAT64)
8259 {
8260 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8261 reg_names[gpreg + WORDS_BIG_ENDIAN],
8262 reg_names[fpreg]);
8263 fprintf (asm_out_file, "\tmfhc1\t%s,%s\n",
8264 reg_names[gpreg + !WORDS_BIG_ENDIAN],
8265 reg_names[fpreg]);
8266 }
8267 else
8268 {
8269 if (TARGET_BIG_ENDIAN)
8270 {
8271 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8272 reg_names[gpreg + 0],
8273 reg_names[fpreg + 1]);
8274 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8275 reg_names[gpreg + 1],
8276 reg_names[fpreg + 0]);
8277 }
8278 else
8279 {
8280 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8281 reg_names[gpreg + 0],
8282 reg_names[fpreg + 0]);
8283 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8284 reg_names[gpreg + 1],
8285 reg_names[fpreg + 1]);
8286 }
8287 }
8288 }
8289
8290 /* Build a call stub for a mips16 call. A stub is needed if we are
8291 passing any floating point values which should go into the floating
8292 point registers. If we are, and the call turns out to be to a
8293 32-bit function, the stub will be used to move the values into the
8294 floating point registers before calling the 32-bit function. The
8295 linker will magically adjust the function call to either the 16-bit
8296 function or the 32-bit stub, depending upon where the function call
8297 is actually defined.
8298
8299 Similarly, we need a stub if the return value might come back in a
8300 floating point register.
8301
8302 RETVAL is the location of the return value, or null if this is
8303 a call rather than a call_value. FN is the address of the
8304 function and ARG_SIZE is the size of the arguments. FP_CODE
8305 is the code built by function_arg. This function returns a nonzero
8306 value if it builds the call instruction itself. */
8307
8308 int
8309 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8310 {
8311 int fpret = 0;
8312 const char *fnname;
8313 char *secname, *stubname;
8314 struct mips16_stub *l;
8315 tree stubid, stubdecl;
8316 int need_comma;
8317 unsigned int f;
8318
8319 /* We don't need to do anything if we aren't in mips16 mode, or if
8320 we were invoked with the -msoft-float option. */
8321 if (!mips16_hard_float)
8322 return 0;
8323
8324 /* Figure out whether the value might come back in a floating point
8325 register. */
8326 if (retval)
8327 fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
8328
8329 /* We don't need to do anything if there were no floating point
8330 arguments and the value will not be returned in a floating point
8331 register. */
8332 if (fp_code == 0 && ! fpret)
8333 return 0;
8334
8335 /* We don't need to do anything if this is a call to a special
8336 mips16 support function. */
8337 if (GET_CODE (fn) == SYMBOL_REF
8338 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8339 return 0;
8340
8341 /* This code will only work for o32 and o64 abis. The other ABI's
8342 require more sophisticated support. */
8343 gcc_assert (TARGET_OLDABI);
8344
8345 /* If we're calling via a function pointer, then we must always call
8346 via a stub. There are magic stubs provided in libgcc.a for each
8347 of the required cases. Each of them expects the function address
8348 to arrive in register $2. */
8349
8350 if (GET_CODE (fn) != SYMBOL_REF)
8351 {
8352 char buf[30];
8353 tree id;
8354 rtx stub_fn, insn;
8355
8356 /* ??? If this code is modified to support other ABI's, we need
8357 to handle PARALLEL return values here. */
8358
8359 if (fpret)
8360 sprintf (buf, "__mips16_call_stub_%s_%d",
8361 mips16_call_stub_mode_suffix (GET_MODE (retval)),
8362 fp_code);
8363 else
8364 sprintf (buf, "__mips16_call_stub_%d",
8365 fp_code);
8366
8367 id = get_identifier (buf);
8368 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8369
8370 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8371
8372 if (retval == NULL_RTX)
8373 insn = gen_call_internal (stub_fn, arg_size);
8374 else
8375 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8376 insn = emit_call_insn (insn);
8377
8378 /* Put the register usage information on the CALL. */
8379 CALL_INSN_FUNCTION_USAGE (insn) =
8380 gen_rtx_EXPR_LIST (VOIDmode,
8381 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8382 CALL_INSN_FUNCTION_USAGE (insn));
8383
8384 /* If we are handling a floating point return value, we need to
8385 save $18 in the function prologue. Putting a note on the
8386 call will mean that regs_ever_live[$18] will be true if the
8387 call is not eliminated, and we can check that in the prologue
8388 code. */
8389 if (fpret)
8390 CALL_INSN_FUNCTION_USAGE (insn) =
8391 gen_rtx_EXPR_LIST (VOIDmode,
8392 gen_rtx_USE (VOIDmode,
8393 gen_rtx_REG (word_mode, 18)),
8394 CALL_INSN_FUNCTION_USAGE (insn));
8395
8396 /* Return 1 to tell the caller that we've generated the call
8397 insn. */
8398 return 1;
8399 }
8400
8401 /* We know the function we are going to call. If we have already
8402 built a stub, we don't need to do anything further. */
8403
8404 fnname = XSTR (fn, 0);
8405 for (l = mips16_stubs; l != NULL; l = l->next)
8406 if (strcmp (l->name, fnname) == 0)
8407 break;
8408
8409 if (l == NULL)
8410 {
8411 /* Build a special purpose stub. When the linker sees a
8412 function call in mips16 code, it will check where the target
8413 is defined. If the target is a 32-bit call, the linker will
8414 search for the section defined here. It can tell which
8415 symbol this section is associated with by looking at the
8416 relocation information (the name is unreliable, since this
8417 might be a static function). If such a section is found, the
8418 linker will redirect the call to the start of the magic
8419 section.
8420
8421 If the function does not return a floating point value, the
8422 special stub section is named
8423 .mips16.call.FNNAME
8424
8425 If the function does return a floating point value, the stub
8426 section is named
8427 .mips16.call.fp.FNNAME
8428 */
8429
8430 secname = (char *) alloca (strlen (fnname) + 40);
8431 sprintf (secname, ".mips16.call.%s%s",
8432 fpret ? "fp." : "",
8433 fnname);
8434 stubname = (char *) alloca (strlen (fnname) + 20);
8435 sprintf (stubname, "__call_stub_%s%s",
8436 fpret ? "fp_" : "",
8437 fnname);
8438 stubid = get_identifier (stubname);
8439 stubdecl = build_decl (FUNCTION_DECL, stubid,
8440 build_function_type (void_type_node, NULL_TREE));
8441 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8442 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
8443
8444 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8445 (fpret
8446 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8447 : ""),
8448 fnname);
8449 need_comma = 0;
8450 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8451 {
8452 fprintf (asm_out_file, "%s%s",
8453 need_comma ? ", " : "",
8454 (f & 3) == 1 ? "float" : "double");
8455 need_comma = 1;
8456 }
8457 fprintf (asm_out_file, ")\n");
8458
8459 fprintf (asm_out_file, "\t.set\tnomips16\n");
8460 assemble_start_function (stubdecl, stubname);
8461
8462 if (!FUNCTION_NAME_ALREADY_DECLARED)
8463 {
8464 fputs ("\t.ent\t", asm_out_file);
8465 assemble_name (asm_out_file, stubname);
8466 fputs ("\n", asm_out_file);
8467
8468 assemble_name (asm_out_file, stubname);
8469 fputs (":\n", asm_out_file);
8470 }
8471
8472 /* We build the stub code by hand. That's the only way we can
8473 do it, since we can't generate 32-bit code during a 16-bit
8474 compilation. */
8475
8476 /* We don't want the assembler to insert any nops here. */
8477 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8478
8479 mips16_fp_args (asm_out_file, fp_code, 0);
8480
8481 if (! fpret)
8482 {
8483 fprintf (asm_out_file, "\t.set\tnoat\n");
8484 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8485 fnname);
8486 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8487 fprintf (asm_out_file, "\t.set\tat\n");
8488 /* Unfortunately, we can't fill the jump delay slot. We
8489 can't fill with one of the mtc1 instructions, because the
8490 result is not available for one instruction, so if the
8491 very first instruction in the function refers to the
8492 register, it will see the wrong value. */
8493 fprintf (asm_out_file, "\tnop\n");
8494 }
8495 else
8496 {
8497 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8498 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8499 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8500 /* As above, we can't fill the delay slot. */
8501 fprintf (asm_out_file, "\tnop\n");
8502 if (GET_MODE (retval) == SFmode)
8503 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8504 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8505 else if (GET_MODE (retval) == SCmode)
8506 {
8507 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8508 reg_names[GP_REG_FIRST + 2],
8509 reg_names[FP_REG_FIRST + 0]);
8510 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8511 reg_names[GP_REG_FIRST + 3],
8512 reg_names[FP_REG_FIRST + MAX_FPRS_PER_FMT]);
8513 }
8514 else if (GET_MODE (retval) == DFmode
8515 || GET_MODE (retval) == V2SFmode)
8516 {
8517 mips16_fpret_double (GP_REG_FIRST + 2, FP_REG_FIRST + 0);
8518 }
8519 else if (GET_MODE (retval) == DCmode)
8520 {
8521 mips16_fpret_double (GP_REG_FIRST + 2,
8522 FP_REG_FIRST + 0);
8523 mips16_fpret_double (GP_REG_FIRST + 4,
8524 FP_REG_FIRST + MAX_FPRS_PER_FMT);
8525 }
8526 else
8527 {
8528 if (TARGET_BIG_ENDIAN)
8529 {
8530 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8531 reg_names[GP_REG_FIRST + 2],
8532 reg_names[FP_REG_FIRST + 1]);
8533 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8534 reg_names[GP_REG_FIRST + 3],
8535 reg_names[FP_REG_FIRST + 0]);
8536 }
8537 else
8538 {
8539 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8540 reg_names[GP_REG_FIRST + 2],
8541 reg_names[FP_REG_FIRST + 0]);
8542 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8543 reg_names[GP_REG_FIRST + 3],
8544 reg_names[FP_REG_FIRST + 1]);
8545 }
8546 }
8547 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8548 /* As above, we can't fill the delay slot. */
8549 fprintf (asm_out_file, "\tnop\n");
8550 }
8551
8552 fprintf (asm_out_file, "\t.set\treorder\n");
8553
8554 #ifdef ASM_DECLARE_FUNCTION_SIZE
8555 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8556 #endif
8557
8558 if (!FUNCTION_NAME_ALREADY_DECLARED)
8559 {
8560 fputs ("\t.end\t", asm_out_file);
8561 assemble_name (asm_out_file, stubname);
8562 fputs ("\n", asm_out_file);
8563 }
8564
8565 fprintf (asm_out_file, "\t.set\tmips16\n");
8566
8567 /* Record this stub. */
8568 l = (struct mips16_stub *) xmalloc (sizeof *l);
8569 l->name = xstrdup (fnname);
8570 l->fpret = fpret;
8571 l->next = mips16_stubs;
8572 mips16_stubs = l;
8573 }
8574
8575 /* If we expect a floating point return value, but we've built a
8576 stub which does not expect one, then we're in trouble. We can't
8577 use the existing stub, because it won't handle the floating point
8578 value. We can't build a new stub, because the linker won't know
8579 which stub to use for the various calls in this object file.
8580 Fortunately, this case is illegal, since it means that a function
8581 was declared in two different ways in a single compilation. */
8582 if (fpret && ! l->fpret)
8583 error ("cannot handle inconsistent calls to %qs", fnname);
8584
8585 /* If we are calling a stub which handles a floating point return
8586 value, we need to arrange to save $18 in the prologue. We do
8587 this by marking the function call as using the register. The
8588 prologue will later see that it is used, and emit code to save
8589 it. */
8590
8591 if (l->fpret)
8592 {
8593 rtx insn;
8594
8595 if (retval == NULL_RTX)
8596 insn = gen_call_internal (fn, arg_size);
8597 else
8598 insn = gen_call_value_internal (retval, fn, arg_size);
8599 insn = emit_call_insn (insn);
8600
8601 CALL_INSN_FUNCTION_USAGE (insn) =
8602 gen_rtx_EXPR_LIST (VOIDmode,
8603 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8604 CALL_INSN_FUNCTION_USAGE (insn));
8605
8606 /* Return 1 to tell the caller that we've generated the call
8607 insn. */
8608 return 1;
8609 }
8610
8611 /* Return 0 to let the caller generate the call insn. */
8612 return 0;
8613 }
8614
8615 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8616 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8617
8618 struct mips16_constant {
8619 struct mips16_constant *next;
8620 rtx value;
8621 rtx label;
8622 enum machine_mode mode;
8623 };
8624
8625 /* Information about an incomplete mips16 constant pool. FIRST is the
8626 first constant, HIGHEST_ADDRESS is the highest address that the first
8627 byte of the pool can have, and INSN_ADDRESS is the current instruction
8628 address. */
8629
8630 struct mips16_constant_pool {
8631 struct mips16_constant *first;
8632 int highest_address;
8633 int insn_address;
8634 };
8635
8636 /* Add constant VALUE to POOL and return its label. MODE is the
8637 value's mode (used for CONST_INTs, etc.). */
8638
8639 static rtx
8640 add_constant (struct mips16_constant_pool *pool,
8641 rtx value, enum machine_mode mode)
8642 {
8643 struct mips16_constant **p, *c;
8644 bool first_of_size_p;
8645
8646 /* See whether the constant is already in the pool. If so, return the
8647 existing label, otherwise leave P pointing to the place where the
8648 constant should be added.
8649
8650 Keep the pool sorted in increasing order of mode size so that we can
8651 reduce the number of alignments needed. */
8652 first_of_size_p = true;
8653 for (p = &pool->first; *p != 0; p = &(*p)->next)
8654 {
8655 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8656 return (*p)->label;
8657 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8658 break;
8659 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8660 first_of_size_p = false;
8661 }
8662
8663 /* In the worst case, the constant needed by the earliest instruction
8664 will end up at the end of the pool. The entire pool must then be
8665 accessible from that instruction.
8666
8667 When adding the first constant, set the pool's highest address to
8668 the address of the first out-of-range byte. Adjust this address
8669 downwards each time a new constant is added. */
8670 if (pool->first == 0)
8671 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8672 is the address of the instruction with the lowest two bits clear.
8673 The base PC value for ld has the lowest three bits clear. Assume
8674 the worst case here. */
8675 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8676 pool->highest_address -= GET_MODE_SIZE (mode);
8677 if (first_of_size_p)
8678 /* Take into account the worst possible padding due to alignment. */
8679 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8680
8681 /* Create a new entry. */
8682 c = (struct mips16_constant *) xmalloc (sizeof *c);
8683 c->value = value;
8684 c->mode = mode;
8685 c->label = gen_label_rtx ();
8686 c->next = *p;
8687 *p = c;
8688
8689 return c->label;
8690 }
8691
8692 /* Output constant VALUE after instruction INSN and return the last
8693 instruction emitted. MODE is the mode of the constant. */
8694
8695 static rtx
8696 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8697 {
8698 switch (GET_MODE_CLASS (mode))
8699 {
8700 case MODE_INT:
8701 {
8702 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8703 return emit_insn_after (gen_consttable_int (value, size), insn);
8704 }
8705
8706 case MODE_FLOAT:
8707 return emit_insn_after (gen_consttable_float (value), insn);
8708
8709 case MODE_VECTOR_FLOAT:
8710 case MODE_VECTOR_INT:
8711 {
8712 int i;
8713 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8714 insn = dump_constants_1 (GET_MODE_INNER (mode),
8715 CONST_VECTOR_ELT (value, i), insn);
8716 return insn;
8717 }
8718
8719 default:
8720 gcc_unreachable ();
8721 }
8722 }
8723
8724
8725 /* Dump out the constants in CONSTANTS after INSN. */
8726
8727 static void
8728 dump_constants (struct mips16_constant *constants, rtx insn)
8729 {
8730 struct mips16_constant *c, *next;
8731 int align;
8732
8733 align = 0;
8734 for (c = constants; c != NULL; c = next)
8735 {
8736 /* If necessary, increase the alignment of PC. */
8737 if (align < GET_MODE_SIZE (c->mode))
8738 {
8739 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8740 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8741 }
8742 align = GET_MODE_SIZE (c->mode);
8743
8744 insn = emit_label_after (c->label, insn);
8745 insn = dump_constants_1 (c->mode, c->value, insn);
8746
8747 next = c->next;
8748 free (c);
8749 }
8750
8751 emit_barrier_after (insn);
8752 }
8753
8754 /* Return the length of instruction INSN. */
8755
8756 static int
8757 mips16_insn_length (rtx insn)
8758 {
8759 if (JUMP_P (insn))
8760 {
8761 rtx body = PATTERN (insn);
8762 if (GET_CODE (body) == ADDR_VEC)
8763 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8764 if (GET_CODE (body) == ADDR_DIFF_VEC)
8765 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8766 }
8767 return get_attr_length (insn);
8768 }
8769
8770 /* Rewrite *X so that constant pool references refer to the constant's
8771 label instead. DATA points to the constant pool structure. */
8772
8773 static int
8774 mips16_rewrite_pool_refs (rtx *x, void *data)
8775 {
8776 struct mips16_constant_pool *pool = data;
8777 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8778 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8779 get_pool_constant (*x),
8780 get_pool_mode (*x)));
8781 return 0;
8782 }
8783
8784 /* Build MIPS16 constant pools. */
8785
8786 static void
8787 mips16_lay_out_constants (void)
8788 {
8789 struct mips16_constant_pool pool;
8790 rtx insn, barrier;
8791
8792 barrier = 0;
8793 memset (&pool, 0, sizeof (pool));
8794 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8795 {
8796 /* Rewrite constant pool references in INSN. */
8797 if (INSN_P (insn))
8798 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8799
8800 pool.insn_address += mips16_insn_length (insn);
8801
8802 if (pool.first != NULL)
8803 {
8804 /* If there are no natural barriers between the first user of
8805 the pool and the highest acceptable address, we'll need to
8806 create a new instruction to jump around the constant pool.
8807 In the worst case, this instruction will be 4 bytes long.
8808
8809 If it's too late to do this transformation after INSN,
8810 do it immediately before INSN. */
8811 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8812 {
8813 rtx label, jump;
8814
8815 label = gen_label_rtx ();
8816
8817 jump = emit_jump_insn_before (gen_jump (label), insn);
8818 JUMP_LABEL (jump) = label;
8819 LABEL_NUSES (label) = 1;
8820 barrier = emit_barrier_after (jump);
8821
8822 emit_label_after (label, barrier);
8823 pool.insn_address += 4;
8824 }
8825
8826 /* See whether the constant pool is now out of range of the first
8827 user. If so, output the constants after the previous barrier.
8828 Note that any instructions between BARRIER and INSN (inclusive)
8829 will use negative offsets to refer to the pool. */
8830 if (pool.insn_address > pool.highest_address)
8831 {
8832 dump_constants (pool.first, barrier);
8833 pool.first = NULL;
8834 barrier = 0;
8835 }
8836 else if (BARRIER_P (insn))
8837 barrier = insn;
8838 }
8839 }
8840 dump_constants (pool.first, get_last_insn ());
8841 }
8842 \f
8843 /* A temporary variable used by for_each_rtx callbacks, etc. */
8844 static rtx mips_sim_insn;
8845
8846 /* A structure representing the state of the processor pipeline.
8847 Used by the mips_sim_* family of functions. */
8848 struct mips_sim {
8849 /* The maximum number of instructions that can be issued in a cycle.
8850 (Caches mips_issue_rate.) */
8851 unsigned int issue_rate;
8852
8853 /* The current simulation time. */
8854 unsigned int time;
8855
8856 /* How many more instructions can be issued in the current cycle. */
8857 unsigned int insns_left;
8858
8859 /* LAST_SET[X].INSN is the last instruction to set register X.
8860 LAST_SET[X].TIME is the time at which that instruction was issued.
8861 INSN is null if no instruction has yet set register X. */
8862 struct {
8863 rtx insn;
8864 unsigned int time;
8865 } last_set[FIRST_PSEUDO_REGISTER];
8866
8867 /* The pipeline's current DFA state. */
8868 state_t dfa_state;
8869 };
8870
8871 /* Reset STATE to the initial simulation state. */
8872
8873 static void
8874 mips_sim_reset (struct mips_sim *state)
8875 {
8876 state->time = 0;
8877 state->insns_left = state->issue_rate;
8878 memset (&state->last_set, 0, sizeof (state->last_set));
8879 state_reset (state->dfa_state);
8880 }
8881
8882 /* Initialize STATE before its first use. DFA_STATE points to an
8883 allocated but uninitialized DFA state. */
8884
8885 static void
8886 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8887 {
8888 state->issue_rate = mips_issue_rate ();
8889 state->dfa_state = dfa_state;
8890 mips_sim_reset (state);
8891 }
8892
8893 /* Advance STATE by one clock cycle. */
8894
8895 static void
8896 mips_sim_next_cycle (struct mips_sim *state)
8897 {
8898 state->time++;
8899 state->insns_left = state->issue_rate;
8900 state_transition (state->dfa_state, 0);
8901 }
8902
8903 /* Advance simulation state STATE until instruction INSN can read
8904 register REG. */
8905
8906 static void
8907 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8908 {
8909 unsigned int i;
8910
8911 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8912 if (state->last_set[REGNO (reg) + i].insn != 0)
8913 {
8914 unsigned int t;
8915
8916 t = state->last_set[REGNO (reg) + i].time;
8917 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8918 while (state->time < t)
8919 mips_sim_next_cycle (state);
8920 }
8921 }
8922
8923 /* A for_each_rtx callback. If *X is a register, advance simulation state
8924 DATA until mips_sim_insn can read the register's value. */
8925
8926 static int
8927 mips_sim_wait_regs_2 (rtx *x, void *data)
8928 {
8929 if (REG_P (*x))
8930 mips_sim_wait_reg (data, mips_sim_insn, *x);
8931 return 0;
8932 }
8933
8934 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8935
8936 static void
8937 mips_sim_wait_regs_1 (rtx *x, void *data)
8938 {
8939 for_each_rtx (x, mips_sim_wait_regs_2, data);
8940 }
8941
8942 /* Advance simulation state STATE until all of INSN's register
8943 dependencies are satisfied. */
8944
8945 static void
8946 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8947 {
8948 mips_sim_insn = insn;
8949 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8950 }
8951
8952 /* Advance simulation state STATE until the units required by
8953 instruction INSN are available. */
8954
8955 static void
8956 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8957 {
8958 state_t tmp_state;
8959
8960 tmp_state = alloca (state_size ());
8961 while (state->insns_left == 0
8962 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8963 state_transition (tmp_state, insn) >= 0))
8964 mips_sim_next_cycle (state);
8965 }
8966
8967 /* Advance simulation state STATE until INSN is ready to issue. */
8968
8969 static void
8970 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8971 {
8972 mips_sim_wait_regs (state, insn);
8973 mips_sim_wait_units (state, insn);
8974 }
8975
8976 /* mips_sim_insn has just set X. Update the LAST_SET array
8977 in simulation state DATA. */
8978
8979 static void
8980 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8981 {
8982 struct mips_sim *state;
8983 unsigned int i;
8984
8985 state = data;
8986 if (REG_P (x))
8987 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8988 {
8989 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8990 state->last_set[REGNO (x) + i].time = state->time;
8991 }
8992 }
8993
8994 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8995 can issue immediately (i.e., that mips_sim_wait_insn has already
8996 been called). */
8997
8998 static void
8999 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
9000 {
9001 state_transition (state->dfa_state, insn);
9002 state->insns_left--;
9003
9004 mips_sim_insn = insn;
9005 note_stores (PATTERN (insn), mips_sim_record_set, state);
9006 }
9007
9008 /* Simulate issuing a NOP in state STATE. */
9009
9010 static void
9011 mips_sim_issue_nop (struct mips_sim *state)
9012 {
9013 if (state->insns_left == 0)
9014 mips_sim_next_cycle (state);
9015 state->insns_left--;
9016 }
9017
9018 /* Update simulation state STATE so that it's ready to accept the instruction
9019 after INSN. INSN should be part of the main rtl chain, not a member of a
9020 SEQUENCE. */
9021
9022 static void
9023 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
9024 {
9025 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
9026 if (JUMP_P (insn))
9027 mips_sim_issue_nop (state);
9028
9029 switch (GET_CODE (SEQ_BEGIN (insn)))
9030 {
9031 case CODE_LABEL:
9032 case CALL_INSN:
9033 /* We can't predict the processor state after a call or label. */
9034 mips_sim_reset (state);
9035 break;
9036
9037 case JUMP_INSN:
9038 /* The delay slots of branch likely instructions are only executed
9039 when the branch is taken. Therefore, if the caller has simulated
9040 the delay slot instruction, STATE does not really reflect the state
9041 of the pipeline for the instruction after the delay slot. Also,
9042 branch likely instructions tend to incur a penalty when not taken,
9043 so there will probably be an extra delay between the branch and
9044 the instruction after the delay slot. */
9045 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
9046 mips_sim_reset (state);
9047 break;
9048
9049 default:
9050 break;
9051 }
9052 }
9053 \f
9054 /* The VR4130 pipeline issues aligned pairs of instructions together,
9055 but it stalls the second instruction if it depends on the first.
9056 In order to cut down the amount of logic required, this dependence
9057 check is not based on a full instruction decode. Instead, any non-SPECIAL
9058 instruction is assumed to modify the register specified by bits 20-16
9059 (which is usually the "rt" field).
9060
9061 In beq, beql, bne and bnel instructions, the rt field is actually an
9062 input, so we can end up with a false dependence between the branch
9063 and its delay slot. If this situation occurs in instruction INSN,
9064 try to avoid it by swapping rs and rt. */
9065
9066 static void
9067 vr4130_avoid_branch_rt_conflict (rtx insn)
9068 {
9069 rtx first, second;
9070
9071 first = SEQ_BEGIN (insn);
9072 second = SEQ_END (insn);
9073 if (JUMP_P (first)
9074 && NONJUMP_INSN_P (second)
9075 && GET_CODE (PATTERN (first)) == SET
9076 && GET_CODE (SET_DEST (PATTERN (first))) == PC
9077 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
9078 {
9079 /* Check for the right kind of condition. */
9080 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
9081 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
9082 && REG_P (XEXP (cond, 0))
9083 && REG_P (XEXP (cond, 1))
9084 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
9085 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
9086 {
9087 /* SECOND mentions the rt register but not the rs register. */
9088 rtx tmp = XEXP (cond, 0);
9089 XEXP (cond, 0) = XEXP (cond, 1);
9090 XEXP (cond, 1) = tmp;
9091 }
9092 }
9093 }
9094
9095 /* Implement -mvr4130-align. Go through each basic block and simulate the
9096 processor pipeline. If we find that a pair of instructions could execute
9097 in parallel, and the first of those instruction is not 8-byte aligned,
9098 insert a nop to make it aligned. */
9099
9100 static void
9101 vr4130_align_insns (void)
9102 {
9103 struct mips_sim state;
9104 rtx insn, subinsn, last, last2, next;
9105 bool aligned_p;
9106
9107 dfa_start ();
9108
9109 /* LAST is the last instruction before INSN to have a nonzero length.
9110 LAST2 is the last such instruction before LAST. */
9111 last = 0;
9112 last2 = 0;
9113
9114 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
9115 aligned_p = true;
9116
9117 mips_sim_init (&state, alloca (state_size ()));
9118 for (insn = get_insns (); insn != 0; insn = next)
9119 {
9120 unsigned int length;
9121
9122 next = NEXT_INSN (insn);
9123
9124 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
9125 This isn't really related to the alignment pass, but we do it on
9126 the fly to avoid a separate instruction walk. */
9127 vr4130_avoid_branch_rt_conflict (insn);
9128
9129 if (USEFUL_INSN_P (insn))
9130 FOR_EACH_SUBINSN (subinsn, insn)
9131 {
9132 mips_sim_wait_insn (&state, subinsn);
9133
9134 /* If we want this instruction to issue in parallel with the
9135 previous one, make sure that the previous instruction is
9136 aligned. There are several reasons why this isn't worthwhile
9137 when the second instruction is a call:
9138
9139 - Calls are less likely to be performance critical,
9140 - There's a good chance that the delay slot can execute
9141 in parallel with the call.
9142 - The return address would then be unaligned.
9143
9144 In general, if we're going to insert a nop between instructions
9145 X and Y, it's better to insert it immediately after X. That
9146 way, if the nop makes Y aligned, it will also align any labels
9147 between X and Y. */
9148 if (state.insns_left != state.issue_rate
9149 && !CALL_P (subinsn))
9150 {
9151 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
9152 {
9153 /* SUBINSN is the first instruction in INSN and INSN is
9154 aligned. We want to align the previous instruction
9155 instead, so insert a nop between LAST2 and LAST.
9156
9157 Note that LAST could be either a single instruction
9158 or a branch with a delay slot. In the latter case,
9159 LAST, like INSN, is already aligned, but the delay
9160 slot must have some extra delay that stops it from
9161 issuing at the same time as the branch. We therefore
9162 insert a nop before the branch in order to align its
9163 delay slot. */
9164 emit_insn_after (gen_nop (), last2);
9165 aligned_p = false;
9166 }
9167 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
9168 {
9169 /* SUBINSN is the delay slot of INSN, but INSN is
9170 currently unaligned. Insert a nop between
9171 LAST and INSN to align it. */
9172 emit_insn_after (gen_nop (), last);
9173 aligned_p = true;
9174 }
9175 }
9176 mips_sim_issue_insn (&state, subinsn);
9177 }
9178 mips_sim_finish_insn (&state, insn);
9179
9180 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
9181 length = get_attr_length (insn);
9182 if (length > 0)
9183 {
9184 /* If the instruction is an asm statement or multi-instruction
9185 mips.md patern, the length is only an estimate. Insert an
9186 8 byte alignment after it so that the following instructions
9187 can be handled correctly. */
9188 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
9189 && (recog_memoized (insn) < 0 || length >= 8))
9190 {
9191 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
9192 next = NEXT_INSN (next);
9193 mips_sim_next_cycle (&state);
9194 aligned_p = true;
9195 }
9196 else if (length & 4)
9197 aligned_p = !aligned_p;
9198 last2 = last;
9199 last = insn;
9200 }
9201
9202 /* See whether INSN is an aligned label. */
9203 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
9204 aligned_p = true;
9205 }
9206 dfa_finish ();
9207 }
9208 \f
9209 /* Subroutine of mips_reorg. If there is a hazard between INSN
9210 and a previous instruction, avoid it by inserting nops after
9211 instruction AFTER.
9212
9213 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
9214 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
9215 before using the value of that register. *HILO_DELAY counts the
9216 number of instructions since the last hilo hazard (that is,
9217 the number of instructions since the last mflo or mfhi).
9218
9219 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
9220 for the next instruction.
9221
9222 LO_REG is an rtx for the LO register, used in dependence checking. */
9223
9224 static void
9225 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
9226 rtx *delayed_reg, rtx lo_reg)
9227 {
9228 rtx pattern, set;
9229 int nops, ninsns;
9230
9231 if (!INSN_P (insn))
9232 return;
9233
9234 pattern = PATTERN (insn);
9235
9236 /* Do not put the whole function in .set noreorder if it contains
9237 an asm statement. We don't know whether there will be hazards
9238 between the asm statement and the gcc-generated code. */
9239 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
9240 cfun->machine->all_noreorder_p = false;
9241
9242 /* Ignore zero-length instructions (barriers and the like). */
9243 ninsns = get_attr_length (insn) / 4;
9244 if (ninsns == 0)
9245 return;
9246
9247 /* Work out how many nops are needed. Note that we only care about
9248 registers that are explicitly mentioned in the instruction's pattern.
9249 It doesn't matter that calls use the argument registers or that they
9250 clobber hi and lo. */
9251 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
9252 nops = 2 - *hilo_delay;
9253 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
9254 nops = 1;
9255 else
9256 nops = 0;
9257
9258 /* Insert the nops between this instruction and the previous one.
9259 Each new nop takes us further from the last hilo hazard. */
9260 *hilo_delay += nops;
9261 while (nops-- > 0)
9262 emit_insn_after (gen_hazard_nop (), after);
9263
9264 /* Set up the state for the next instruction. */
9265 *hilo_delay += ninsns;
9266 *delayed_reg = 0;
9267 if (INSN_CODE (insn) >= 0)
9268 switch (get_attr_hazard (insn))
9269 {
9270 case HAZARD_NONE:
9271 break;
9272
9273 case HAZARD_HILO:
9274 *hilo_delay = 0;
9275 break;
9276
9277 case HAZARD_DELAY:
9278 set = single_set (insn);
9279 gcc_assert (set != 0);
9280 *delayed_reg = SET_DEST (set);
9281 break;
9282 }
9283 }
9284
9285
9286 /* Go through the instruction stream and insert nops where necessary.
9287 See if the whole function can then be put into .set noreorder &
9288 .set nomacro. */
9289
9290 static void
9291 mips_avoid_hazards (void)
9292 {
9293 rtx insn, last_insn, lo_reg, delayed_reg;
9294 int hilo_delay, i;
9295
9296 /* Force all instructions to be split into their final form. */
9297 split_all_insns_noflow ();
9298
9299 /* Recalculate instruction lengths without taking nops into account. */
9300 cfun->machine->ignore_hazard_length_p = true;
9301 shorten_branches (get_insns ());
9302
9303 cfun->machine->all_noreorder_p = true;
9304
9305 /* Profiled functions can't be all noreorder because the profiler
9306 support uses assembler macros. */
9307 if (current_function_profile)
9308 cfun->machine->all_noreorder_p = false;
9309
9310 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9311 we rely on the assembler to work around some errata. */
9312 if (TARGET_FIX_VR4120)
9313 cfun->machine->all_noreorder_p = false;
9314
9315 /* The same is true for -mfix-vr4130 if we might generate mflo or
9316 mfhi instructions. Note that we avoid using mflo and mfhi if
9317 the VR4130 macc and dmacc instructions are available instead;
9318 see the *mfhilo_{si,di}_macc patterns. */
9319 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9320 cfun->machine->all_noreorder_p = false;
9321
9322 last_insn = 0;
9323 hilo_delay = 2;
9324 delayed_reg = 0;
9325 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9326
9327 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9328 if (INSN_P (insn))
9329 {
9330 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9331 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9332 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9333 &hilo_delay, &delayed_reg, lo_reg);
9334 else
9335 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9336 &delayed_reg, lo_reg);
9337
9338 last_insn = insn;
9339 }
9340 }
9341
9342
9343 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9344
9345 static void
9346 mips_reorg (void)
9347 {
9348 if (TARGET_MIPS16)
9349 mips16_lay_out_constants ();
9350 else if (TARGET_EXPLICIT_RELOCS)
9351 {
9352 if (mips_flag_delayed_branch)
9353 dbr_schedule (get_insns ());
9354 mips_avoid_hazards ();
9355 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9356 vr4130_align_insns ();
9357 }
9358 }
9359
9360 /* This function does three things:
9361
9362 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9363 - Register the mips16 hardware floating point stubs.
9364 - Register the gofast functions if selected using --enable-gofast. */
9365
9366 #include "config/gofast.h"
9367
9368 static void
9369 mips_init_libfuncs (void)
9370 {
9371 if (TARGET_FIX_VR4120)
9372 {
9373 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9374 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9375 }
9376
9377 if (mips16_hard_float)
9378 {
9379 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9380 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9381 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9382 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9383
9384 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9385 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9386 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9387 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9388 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9389 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9390
9391 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9392 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9393
9394 if (TARGET_DOUBLE_FLOAT)
9395 {
9396 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9397 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9398 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9399 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9400
9401 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9402 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9403 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9404 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9405 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9406 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9407
9408 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9409 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9410
9411 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9412 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9413 }
9414 }
9415 else
9416 gofast_maybe_init_libfuncs ();
9417 }
9418
9419 /* Return a number assessing the cost of moving a register in class
9420 FROM to class TO. The classes are expressed using the enumeration
9421 values such as `GENERAL_REGS'. A value of 2 is the default; other
9422 values are interpreted relative to that.
9423
9424 It is not required that the cost always equal 2 when FROM is the
9425 same as TO; on some machines it is expensive to move between
9426 registers if they are not general registers.
9427
9428 If reload sees an insn consisting of a single `set' between two
9429 hard registers, and if `REGISTER_MOVE_COST' applied to their
9430 classes returns a value of 2, reload does not check to ensure that
9431 the constraints of the insn are met. Setting a cost of other than
9432 2 will allow reload to verify that the constraints are met. You
9433 should do this if the `movM' pattern's constraints do not allow
9434 such copying.
9435
9436 ??? We make the cost of moving from HI/LO into general
9437 registers the same as for one of moving general registers to
9438 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9439 pseudo to HI/LO. This might hurt optimizations though, it
9440 isn't clear if it is wise. And it might not work in all cases. We
9441 could solve the DImode LO reg problem by using a multiply, just
9442 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9443 problem by using divide instructions. divu puts the remainder in
9444 the HI reg, so doing a divide by -1 will move the value in the HI
9445 reg for all values except -1. We could handle that case by using a
9446 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9447 a compare/branch to test the input value to see which instruction
9448 we need to use. This gets pretty messy, but it is feasible. */
9449
9450 int
9451 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9452 enum reg_class to, enum reg_class from)
9453 {
9454 if (from == M16_REGS && GR_REG_CLASS_P (to))
9455 return 2;
9456 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9457 return 2;
9458 else if (GR_REG_CLASS_P (from))
9459 {
9460 if (to == M16_REGS)
9461 return 2;
9462 else if (to == M16_NA_REGS)
9463 return 2;
9464 else if (GR_REG_CLASS_P (to))
9465 {
9466 if (TARGET_MIPS16)
9467 return 4;
9468 else
9469 return 2;
9470 }
9471 else if (to == FP_REGS)
9472 return 4;
9473 else if (reg_class_subset_p (to, ACC_REGS))
9474 {
9475 if (TARGET_MIPS16)
9476 return 12;
9477 else
9478 return 6;
9479 }
9480 else if (COP_REG_CLASS_P (to))
9481 {
9482 return 5;
9483 }
9484 }
9485 else if (from == FP_REGS)
9486 {
9487 if (GR_REG_CLASS_P (to))
9488 return 4;
9489 else if (to == FP_REGS)
9490 return 2;
9491 else if (to == ST_REGS)
9492 return 8;
9493 }
9494 else if (reg_class_subset_p (from, ACC_REGS))
9495 {
9496 if (GR_REG_CLASS_P (to))
9497 {
9498 if (TARGET_MIPS16)
9499 return 12;
9500 else
9501 return 6;
9502 }
9503 }
9504 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9505 return 4;
9506 else if (COP_REG_CLASS_P (from))
9507 {
9508 return 5;
9509 }
9510
9511 /* Fall through.
9512 ??? What cases are these? Shouldn't we return 2 here? */
9513
9514 return 12;
9515 }
9516
9517 /* Return the length of INSN. LENGTH is the initial length computed by
9518 attributes in the machine-description file. */
9519
9520 int
9521 mips_adjust_insn_length (rtx insn, int length)
9522 {
9523 /* A unconditional jump has an unfilled delay slot if it is not part
9524 of a sequence. A conditional jump normally has a delay slot, but
9525 does not on MIPS16. */
9526 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9527 length += 4;
9528
9529 /* See how many nops might be needed to avoid hardware hazards. */
9530 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9531 switch (get_attr_hazard (insn))
9532 {
9533 case HAZARD_NONE:
9534 break;
9535
9536 case HAZARD_DELAY:
9537 length += 4;
9538 break;
9539
9540 case HAZARD_HILO:
9541 length += 8;
9542 break;
9543 }
9544
9545 /* All MIPS16 instructions are a measly two bytes. */
9546 if (TARGET_MIPS16)
9547 length /= 2;
9548
9549 return length;
9550 }
9551
9552
9553 /* Return an asm sequence to start a noat block and load the address
9554 of a label into $1. */
9555
9556 const char *
9557 mips_output_load_label (void)
9558 {
9559 if (TARGET_EXPLICIT_RELOCS)
9560 switch (mips_abi)
9561 {
9562 case ABI_N32:
9563 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9564
9565 case ABI_64:
9566 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9567
9568 default:
9569 if (ISA_HAS_LOAD_DELAY)
9570 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9571 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9572 }
9573 else
9574 {
9575 if (Pmode == DImode)
9576 return "%[dla\t%@,%0";
9577 else
9578 return "%[la\t%@,%0";
9579 }
9580 }
9581
9582 /* Return the assembly code for INSN, which has the operands given by
9583 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9584 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9585 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9586 version of BRANCH_IF_TRUE. */
9587
9588 const char *
9589 mips_output_conditional_branch (rtx insn, rtx *operands,
9590 const char *branch_if_true,
9591 const char *branch_if_false)
9592 {
9593 unsigned int length;
9594 rtx taken, not_taken;
9595
9596 length = get_attr_length (insn);
9597 if (length <= 8)
9598 {
9599 /* Just a simple conditional branch. */
9600 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9601 return branch_if_true;
9602 }
9603
9604 /* Generate a reversed branch around a direct jump. This fallback does
9605 not use branch-likely instructions. */
9606 mips_branch_likely = false;
9607 not_taken = gen_label_rtx ();
9608 taken = operands[1];
9609
9610 /* Generate the reversed branch to NOT_TAKEN. */
9611 operands[1] = not_taken;
9612 output_asm_insn (branch_if_false, operands);
9613
9614 /* If INSN has a delay slot, we must provide delay slots for both the
9615 branch to NOT_TAKEN and the conditional jump. We must also ensure
9616 that INSN's delay slot is executed in the appropriate cases. */
9617 if (final_sequence)
9618 {
9619 /* This first delay slot will always be executed, so use INSN's
9620 delay slot if is not annulled. */
9621 if (!INSN_ANNULLED_BRANCH_P (insn))
9622 {
9623 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9624 asm_out_file, optimize, 1, NULL);
9625 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9626 }
9627 else
9628 output_asm_insn ("nop", 0);
9629 fprintf (asm_out_file, "\n");
9630 }
9631
9632 /* Output the unconditional branch to TAKEN. */
9633 if (length <= 16)
9634 output_asm_insn ("j\t%0%/", &taken);
9635 else
9636 {
9637 output_asm_insn (mips_output_load_label (), &taken);
9638 output_asm_insn ("jr\t%@%]%/", 0);
9639 }
9640
9641 /* Now deal with its delay slot; see above. */
9642 if (final_sequence)
9643 {
9644 /* This delay slot will only be executed if the branch is taken.
9645 Use INSN's delay slot if is annulled. */
9646 if (INSN_ANNULLED_BRANCH_P (insn))
9647 {
9648 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9649 asm_out_file, optimize, 1, NULL);
9650 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9651 }
9652 else
9653 output_asm_insn ("nop", 0);
9654 fprintf (asm_out_file, "\n");
9655 }
9656
9657 /* Output NOT_TAKEN. */
9658 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9659 CODE_LABEL_NUMBER (not_taken));
9660 return "";
9661 }
9662
9663 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9664 if some ordered condition is true. The condition is given by
9665 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9666 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9667 its second is always zero. */
9668
9669 const char *
9670 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9671 {
9672 const char *branch[2];
9673
9674 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9675 Make BRANCH[0] branch on the inverse condition. */
9676 switch (GET_CODE (operands[0]))
9677 {
9678 /* These cases are equivalent to comparisons against zero. */
9679 case LEU:
9680 inverted_p = !inverted_p;
9681 /* Fall through. */
9682 case GTU:
9683 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9684 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9685 break;
9686
9687 /* These cases are always true or always false. */
9688 case LTU:
9689 inverted_p = !inverted_p;
9690 /* Fall through. */
9691 case GEU:
9692 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9693 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9694 break;
9695
9696 default:
9697 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9698 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9699 break;
9700 }
9701 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9702 }
9703 \f
9704 /* Used to output div or ddiv instruction DIVISION, which has the operands
9705 given by OPERANDS. Add in a divide-by-zero check if needed.
9706
9707 When working around R4000 and R4400 errata, we need to make sure that
9708 the division is not immediately followed by a shift[1][2]. We also
9709 need to stop the division from being put into a branch delay slot[3].
9710 The easiest way to avoid both problems is to add a nop after the
9711 division. When a divide-by-zero check is needed, this nop can be
9712 used to fill the branch delay slot.
9713
9714 [1] If a double-word or a variable shift executes immediately
9715 after starting an integer division, the shift may give an
9716 incorrect result. See quotations of errata #16 and #28 from
9717 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9718 in mips.md for details.
9719
9720 [2] A similar bug to [1] exists for all revisions of the
9721 R4000 and the R4400 when run in an MC configuration.
9722 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9723
9724 "19. In this following sequence:
9725
9726 ddiv (or ddivu or div or divu)
9727 dsll32 (or dsrl32, dsra32)
9728
9729 if an MPT stall occurs, while the divide is slipping the cpu
9730 pipeline, then the following double shift would end up with an
9731 incorrect result.
9732
9733 Workaround: The compiler needs to avoid generating any
9734 sequence with divide followed by extended double shift."
9735
9736 This erratum is also present in "MIPS R4400MC Errata, Processor
9737 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9738 & 3.0" as errata #10 and #4, respectively.
9739
9740 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9741 (also valid for MIPS R4000MC processors):
9742
9743 "52. R4000SC: This bug does not apply for the R4000PC.
9744
9745 There are two flavors of this bug:
9746
9747 1) If the instruction just after divide takes an RF exception
9748 (tlb-refill, tlb-invalid) and gets an instruction cache
9749 miss (both primary and secondary) and the line which is
9750 currently in secondary cache at this index had the first
9751 data word, where the bits 5..2 are set, then R4000 would
9752 get a wrong result for the div.
9753
9754 ##1
9755 nop
9756 div r8, r9
9757 ------------------- # end-of page. -tlb-refill
9758 nop
9759 ##2
9760 nop
9761 div r8, r9
9762 ------------------- # end-of page. -tlb-invalid
9763 nop
9764
9765 2) If the divide is in the taken branch delay slot, where the
9766 target takes RF exception and gets an I-cache miss for the
9767 exception vector or where I-cache miss occurs for the
9768 target address, under the above mentioned scenarios, the
9769 div would get wrong results.
9770
9771 ##1
9772 j r2 # to next page mapped or unmapped
9773 div r8,r9 # this bug would be there as long
9774 # as there is an ICache miss and
9775 nop # the "data pattern" is present
9776
9777 ##2
9778 beq r0, r0, NextPage # to Next page
9779 div r8,r9
9780 nop
9781
9782 This bug is present for div, divu, ddiv, and ddivu
9783 instructions.
9784
9785 Workaround: For item 1), OS could make sure that the next page
9786 after the divide instruction is also mapped. For item 2), the
9787 compiler could make sure that the divide instruction is not in
9788 the branch delay slot."
9789
9790 These processors have PRId values of 0x00004220 and 0x00004300 for
9791 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9792
9793 const char *
9794 mips_output_division (const char *division, rtx *operands)
9795 {
9796 const char *s;
9797
9798 s = division;
9799 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9800 {
9801 output_asm_insn (s, operands);
9802 s = "nop";
9803 }
9804 if (TARGET_CHECK_ZERO_DIV)
9805 {
9806 if (TARGET_MIPS16)
9807 {
9808 output_asm_insn (s, operands);
9809 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9810 }
9811 else if (GENERATE_DIVIDE_TRAPS)
9812 {
9813 output_asm_insn (s, operands);
9814 s = "teq\t%2,%.,7";
9815 }
9816 else
9817 {
9818 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9819 output_asm_insn (s, operands);
9820 s = "break\t7%)\n1:";
9821 }
9822 }
9823 return s;
9824 }
9825 \f
9826 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9827 with a final "000" replaced by "k". Ignore case.
9828
9829 Note: this function is shared between GCC and GAS. */
9830
9831 static bool
9832 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9833 {
9834 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9835 given++, canonical++;
9836
9837 return ((*given == 0 && *canonical == 0)
9838 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9839 }
9840
9841
9842 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9843 CPU name. We've traditionally allowed a lot of variation here.
9844
9845 Note: this function is shared between GCC and GAS. */
9846
9847 static bool
9848 mips_matching_cpu_name_p (const char *canonical, const char *given)
9849 {
9850 /* First see if the name matches exactly, or with a final "000"
9851 turned into "k". */
9852 if (mips_strict_matching_cpu_name_p (canonical, given))
9853 return true;
9854
9855 /* If not, try comparing based on numerical designation alone.
9856 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9857 if (TOLOWER (*given) == 'r')
9858 given++;
9859 if (!ISDIGIT (*given))
9860 return false;
9861
9862 /* Skip over some well-known prefixes in the canonical name,
9863 hoping to find a number there too. */
9864 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9865 canonical += 2;
9866 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9867 canonical += 2;
9868 else if (TOLOWER (canonical[0]) == 'r')
9869 canonical += 1;
9870
9871 return mips_strict_matching_cpu_name_p (canonical, given);
9872 }
9873
9874
9875 /* Return the mips_cpu_info entry for the processor or ISA given
9876 by CPU_STRING. Return null if the string isn't recognized.
9877
9878 A similar function exists in GAS. */
9879
9880 static const struct mips_cpu_info *
9881 mips_parse_cpu (const char *cpu_string)
9882 {
9883 const struct mips_cpu_info *p;
9884 const char *s;
9885
9886 /* In the past, we allowed upper-case CPU names, but it doesn't
9887 work well with the multilib machinery. */
9888 for (s = cpu_string; *s != 0; s++)
9889 if (ISUPPER (*s))
9890 {
9891 warning (0, "the cpu name must be lower case");
9892 break;
9893 }
9894
9895 /* 'from-abi' selects the most compatible architecture for the given
9896 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9897 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9898 version. Look first at the -mgp options, if given, otherwise base
9899 the choice on MASK_64BIT in TARGET_DEFAULT. */
9900 if (strcasecmp (cpu_string, "from-abi") == 0)
9901 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9902 : ABI_NEEDS_64BIT_REGS ? 3
9903 : (TARGET_64BIT ? 3 : 1));
9904
9905 /* 'default' has traditionally been a no-op. Probably not very useful. */
9906 if (strcasecmp (cpu_string, "default") == 0)
9907 return 0;
9908
9909 for (p = mips_cpu_info_table; p->name != 0; p++)
9910 if (mips_matching_cpu_name_p (p->name, cpu_string))
9911 return p;
9912
9913 return 0;
9914 }
9915
9916
9917 /* Return the processor associated with the given ISA level, or null
9918 if the ISA isn't valid. */
9919
9920 static const struct mips_cpu_info *
9921 mips_cpu_info_from_isa (int isa)
9922 {
9923 const struct mips_cpu_info *p;
9924
9925 for (p = mips_cpu_info_table; p->name != 0; p++)
9926 if (p->isa == isa)
9927 return p;
9928
9929 return 0;
9930 }
9931 \f
9932 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9933 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9934 they only hold condition code modes, and CCmode is always considered to
9935 be 4 bytes wide. All other registers are word sized. */
9936
9937 unsigned int
9938 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9939 {
9940 if (ST_REG_P (regno))
9941 return ((GET_MODE_SIZE (mode) + 3) / 4);
9942 else if (! FP_REG_P (regno))
9943 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9944 else
9945 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9946 }
9947
9948 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9949 all BLKmode objects are returned in memory. Under the new (N32 and
9950 64-bit MIPS ABIs) small structures are returned in a register.
9951 Objects with varying size must still be returned in memory, of
9952 course. */
9953
9954 static bool
9955 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9956 {
9957 if (TARGET_OLDABI)
9958 return (TYPE_MODE (type) == BLKmode);
9959 else
9960 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9961 || (int_size_in_bytes (type) == -1));
9962 }
9963
9964 static bool
9965 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9966 {
9967 return !TARGET_OLDABI;
9968 }
9969 \f
9970 /* Return true if INSN is a multiply-add or multiply-subtract
9971 instruction and PREV assigns to the accumulator operand. */
9972
9973 bool
9974 mips_linked_madd_p (rtx prev, rtx insn)
9975 {
9976 rtx x;
9977
9978 x = single_set (insn);
9979 if (x == 0)
9980 return false;
9981
9982 x = SET_SRC (x);
9983
9984 if (GET_CODE (x) == PLUS
9985 && GET_CODE (XEXP (x, 0)) == MULT
9986 && reg_set_p (XEXP (x, 1), prev))
9987 return true;
9988
9989 if (GET_CODE (x) == MINUS
9990 && GET_CODE (XEXP (x, 1)) == MULT
9991 && reg_set_p (XEXP (x, 0), prev))
9992 return true;
9993
9994 return false;
9995 }
9996 \f
9997 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9998 that may clobber hi or lo. */
9999
10000 static rtx mips_macc_chains_last_hilo;
10001
10002 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10003 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10004
10005 static void
10006 mips_macc_chains_record (rtx insn)
10007 {
10008 if (get_attr_may_clobber_hilo (insn))
10009 mips_macc_chains_last_hilo = insn;
10010 }
10011
10012 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10013 has NREADY elements, looking for a multiply-add or multiply-subtract
10014 instruction that is cumulative with mips_macc_chains_last_hilo.
10015 If there is one, promote it ahead of anything else that might
10016 clobber hi or lo. */
10017
10018 static void
10019 mips_macc_chains_reorder (rtx *ready, int nready)
10020 {
10021 int i, j;
10022
10023 if (mips_macc_chains_last_hilo != 0)
10024 for (i = nready - 1; i >= 0; i--)
10025 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10026 {
10027 for (j = nready - 1; j > i; j--)
10028 if (recog_memoized (ready[j]) >= 0
10029 && get_attr_may_clobber_hilo (ready[j]))
10030 {
10031 mips_promote_ready (ready, i, j);
10032 break;
10033 }
10034 break;
10035 }
10036 }
10037 \f
10038 /* The last instruction to be scheduled. */
10039
10040 static rtx vr4130_last_insn;
10041
10042 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10043 points to an rtx that is initially an instruction. Nullify the rtx
10044 if the instruction uses the value of register X. */
10045
10046 static void
10047 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
10048 {
10049 rtx *insn_ptr = data;
10050 if (REG_P (x)
10051 && *insn_ptr != 0
10052 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10053 *insn_ptr = 0;
10054 }
10055
10056 /* Return true if there is true register dependence between vr4130_last_insn
10057 and INSN. */
10058
10059 static bool
10060 vr4130_true_reg_dependence_p (rtx insn)
10061 {
10062 note_stores (PATTERN (vr4130_last_insn),
10063 vr4130_true_reg_dependence_p_1, &insn);
10064 return insn == 0;
10065 }
10066
10067 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10068 the ready queue and that INSN2 is the instruction after it, return
10069 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10070 in which INSN1 and INSN2 can probably issue in parallel, but for
10071 which (INSN2, INSN1) should be less sensitive to instruction
10072 alignment than (INSN1, INSN2). See 4130.md for more details. */
10073
10074 static bool
10075 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10076 {
10077 dep_link_t dep;
10078
10079 /* Check for the following case:
10080
10081 1) there is some other instruction X with an anti dependence on INSN1;
10082 2) X has a higher priority than INSN2; and
10083 3) X is an arithmetic instruction (and thus has no unit restrictions).
10084
10085 If INSN1 is the last instruction blocking X, it would better to
10086 choose (INSN1, X) over (INSN2, INSN1). */
10087 FOR_EACH_DEP_LINK (dep, INSN_FORW_DEPS (insn1))
10088 if (DEP_LINK_KIND (dep) == REG_DEP_ANTI
10089 && INSN_PRIORITY (DEP_LINK_CON (dep)) > INSN_PRIORITY (insn2)
10090 && recog_memoized (DEP_LINK_CON (dep)) >= 0
10091 && get_attr_vr4130_class (DEP_LINK_CON (dep)) == VR4130_CLASS_ALU)
10092 return false;
10093
10094 if (vr4130_last_insn != 0
10095 && recog_memoized (insn1) >= 0
10096 && recog_memoized (insn2) >= 0)
10097 {
10098 /* See whether INSN1 and INSN2 use different execution units,
10099 or if they are both ALU-type instructions. If so, they can
10100 probably execute in parallel. */
10101 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10102 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10103 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10104 {
10105 /* If only one of the instructions has a dependence on
10106 vr4130_last_insn, prefer to schedule the other one first. */
10107 bool dep1 = vr4130_true_reg_dependence_p (insn1);
10108 bool dep2 = vr4130_true_reg_dependence_p (insn2);
10109 if (dep1 != dep2)
10110 return dep1;
10111
10112 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10113 is not an ALU-type instruction and if INSN1 uses the same
10114 execution unit. (Note that if this condition holds, we already
10115 know that INSN2 uses a different execution unit.) */
10116 if (class1 != VR4130_CLASS_ALU
10117 && recog_memoized (vr4130_last_insn) >= 0
10118 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10119 return true;
10120 }
10121 }
10122 return false;
10123 }
10124
10125 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10126 queue with at least two instructions. Swap the first two if
10127 vr4130_swap_insns_p says that it could be worthwhile. */
10128
10129 static void
10130 vr4130_reorder (rtx *ready, int nready)
10131 {
10132 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10133 mips_promote_ready (ready, nready - 2, nready - 1);
10134 }
10135 \f
10136 /* Remove the instruction at index LOWER from ready queue READY and
10137 reinsert it in front of the instruction at index HIGHER. LOWER must
10138 be <= HIGHER. */
10139
10140 static void
10141 mips_promote_ready (rtx *ready, int lower, int higher)
10142 {
10143 rtx new_head;
10144 int i;
10145
10146 new_head = ready[lower];
10147 for (i = lower; i < higher; i++)
10148 ready[i] = ready[i + 1];
10149 ready[i] = new_head;
10150 }
10151
10152 /* Implement TARGET_SCHED_REORDER. */
10153
10154 static int
10155 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10156 rtx *ready, int *nreadyp, int cycle)
10157 {
10158 if (!reload_completed && TUNE_MACC_CHAINS)
10159 {
10160 if (cycle == 0)
10161 mips_macc_chains_last_hilo = 0;
10162 if (*nreadyp > 0)
10163 mips_macc_chains_reorder (ready, *nreadyp);
10164 }
10165 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
10166 {
10167 if (cycle == 0)
10168 vr4130_last_insn = 0;
10169 if (*nreadyp > 1)
10170 vr4130_reorder (ready, *nreadyp);
10171 }
10172 return mips_issue_rate ();
10173 }
10174
10175 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10176
10177 static int
10178 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10179 rtx insn, int more)
10180 {
10181 switch (GET_CODE (PATTERN (insn)))
10182 {
10183 case USE:
10184 case CLOBBER:
10185 /* Don't count USEs and CLOBBERs against the issue rate. */
10186 break;
10187
10188 default:
10189 more--;
10190 if (!reload_completed && TUNE_MACC_CHAINS)
10191 mips_macc_chains_record (insn);
10192 vr4130_last_insn = insn;
10193 break;
10194 }
10195 return more;
10196 }
10197 \f
10198 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10199 dependencies have no cost. */
10200
10201 static int
10202 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10203 rtx dep ATTRIBUTE_UNUSED, int cost)
10204 {
10205 if (REG_NOTE_KIND (link) != 0)
10206 return 0;
10207 return cost;
10208 }
10209
10210 /* Return the number of instructions that can be issued per cycle. */
10211
10212 static int
10213 mips_issue_rate (void)
10214 {
10215 switch (mips_tune)
10216 {
10217 case PROCESSOR_74KC:
10218 case PROCESSOR_74KF:
10219 case PROCESSOR_74KX:
10220 case PROCESSOR_R4130:
10221 case PROCESSOR_R5400:
10222 case PROCESSOR_R5500:
10223 case PROCESSOR_R7000:
10224 case PROCESSOR_R9000:
10225 return 2;
10226
10227 case PROCESSOR_SB1:
10228 case PROCESSOR_SB1A:
10229 /* This is actually 4, but we get better performance if we claim 3.
10230 This is partly because of unwanted speculative code motion with the
10231 larger number, and partly because in most common cases we can't
10232 reach the theoretical max of 4. */
10233 return 3;
10234
10235 default:
10236 return 1;
10237 }
10238 }
10239
10240 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10241 be as wide as the scheduling freedom in the DFA. */
10242
10243 static int
10244 mips_multipass_dfa_lookahead (void)
10245 {
10246 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10247 if (TUNE_SB1)
10248 return 4;
10249
10250 return 0;
10251 }
10252
10253 /* Implements a store data bypass check. We need this because the cprestore
10254 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
10255 default routine to abort. We just return false for that case. */
10256 /* ??? Should try to give a better result here than assuming false. */
10257
10258 int
10259 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10260 {
10261 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10262 return false;
10263
10264 return ! store_data_bypass_p (out_insn, in_insn);
10265 }
10266 \f
10267 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10268 return the first operand of the associated "pref" or "prefx" insn. */
10269
10270 rtx
10271 mips_prefetch_cookie (rtx write, rtx locality)
10272 {
10273 /* store_streamed / load_streamed. */
10274 if (INTVAL (locality) <= 0)
10275 return GEN_INT (INTVAL (write) + 4);
10276
10277 /* store / load. */
10278 if (INTVAL (locality) <= 2)
10279 return write;
10280
10281 /* store_retained / load_retained. */
10282 return GEN_INT (INTVAL (write) + 6);
10283 }
10284 \f
10285 /* MIPS builtin function support. */
10286
10287 struct builtin_description
10288 {
10289 /* The code of the main .md file instruction. See mips_builtin_type
10290 for more information. */
10291 enum insn_code icode;
10292
10293 /* The floating-point comparison code to use with ICODE, if any. */
10294 enum mips_fp_condition cond;
10295
10296 /* The name of the builtin function. */
10297 const char *name;
10298
10299 /* Specifies how the function should be expanded. */
10300 enum mips_builtin_type builtin_type;
10301
10302 /* The function's prototype. */
10303 enum mips_function_type function_type;
10304
10305 /* The target flags required for this function. */
10306 int target_flags;
10307 };
10308
10309 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10310 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10311 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10312 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10313 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10314
10315 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10316 TARGET_FLAGS. */
10317 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10318 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10319 "__builtin_mips_" #INSN "_" #COND "_s", \
10320 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10321 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10322 "__builtin_mips_" #INSN "_" #COND "_d", \
10323 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10324
10325 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10326 The lower and upper forms require TARGET_FLAGS while the any and all
10327 forms require MASK_MIPS3D. */
10328 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10329 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10330 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10331 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10332 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10333 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10334 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10335 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10336 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10337 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10338 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10339 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10340 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10341
10342 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10343 require MASK_MIPS3D. */
10344 #define CMP_4S_BUILTINS(INSN, COND) \
10345 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10346 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10347 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10348 MASK_MIPS3D }, \
10349 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10350 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10351 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10352 MASK_MIPS3D }
10353
10354 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10355 instruction requires TARGET_FLAGS. */
10356 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10357 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10358 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10359 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10360 TARGET_FLAGS }, \
10361 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10362 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10363 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10364 TARGET_FLAGS }
10365
10366 /* Define all the builtins related to c.cond.fmt condition COND. */
10367 #define CMP_BUILTINS(COND) \
10368 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10369 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10370 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10371 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10372 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10373 CMP_4S_BUILTINS (c, COND), \
10374 CMP_4S_BUILTINS (cabs, COND)
10375
10376 static const struct builtin_description mips_bdesc[] =
10377 {
10378 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10379 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10380 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10381 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10382 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10383 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10384 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10385 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10386
10387 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10388 MASK_PAIRED_SINGLE_FLOAT),
10389 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10390 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10391 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10392 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10393
10394 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10395 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10396 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10397 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10398 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10399 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10400
10401 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10402 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10403 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10404 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10405 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10406 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10407
10408 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10409 };
10410
10411 /* Builtin functions for the SB-1 processor. */
10412
10413 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10414
10415 static const struct builtin_description sb1_bdesc[] =
10416 {
10417 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10418 };
10419
10420 /* Builtin functions for DSP ASE. */
10421
10422 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10423 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10424 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10425 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10426 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10427
10428 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10429 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10430 builtin_description fields. */
10431 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10432 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10433 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10434
10435 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10436 branch instruction. TARGET_FLAGS is a builtin_description field. */
10437 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10438 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10439 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10440
10441 static const struct builtin_description dsp_bdesc[] =
10442 {
10443 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10444 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10445 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10446 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10447 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10448 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10449 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10450 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10451 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10452 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10453 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10454 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10455 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10456 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10457 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10458 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10459 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10460 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10461 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10462 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10463 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10464 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10465 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10466 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10467 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10468 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10469 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10470 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10471 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10472 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10473 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10474 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10475 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10476 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10477 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10478 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10479 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10480 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10481 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10482 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10483 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10484 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10485 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10486 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10487 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10488 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10489 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10490 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10491 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10492 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10493 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10494 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10495 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10496 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10497 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10498 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10499 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10500 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10501 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10502 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10503 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10504 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10505 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10506 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10507 BPOSGE_BUILTIN (32, MASK_DSP),
10508
10509 /* The following are for the MIPS DSP ASE REV 2. */
10510 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
10511 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10512 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10513 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10514 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10515 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10516 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10517 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10518 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10519 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10520 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10521 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10522 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10523 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10524 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10525 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10526 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10527 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10528 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10529 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10530 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10531 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
10532 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10533 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10534 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10535 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10536 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10537 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10538 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10539 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10540 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10541 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10542 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10543 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
10544 };
10545
10546 static const struct builtin_description dsp_32only_bdesc[] =
10547 {
10548 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10549 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10550 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10551 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10552 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10553 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10554 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10555 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10556 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10557 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10558 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10559 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10560 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10561 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10562 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10563 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10564 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10565 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10566 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10567 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10568 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10569
10570 /* The following are for the MIPS DSP ASE REV 2. */
10571 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10572 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10573 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10574 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10575 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10576 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10577 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10578 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
10579 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
10580 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10581 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10582 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10583 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10584 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10585 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
10586 };
10587
10588 /* This helps provide a mapping from builtin function codes to bdesc
10589 arrays. */
10590
10591 struct bdesc_map
10592 {
10593 /* The builtin function table that this entry describes. */
10594 const struct builtin_description *bdesc;
10595
10596 /* The number of entries in the builtin function table. */
10597 unsigned int size;
10598
10599 /* The target processor that supports these builtin functions.
10600 PROCESSOR_MAX means we enable them for all processors. */
10601 enum processor_type proc;
10602
10603 /* If the target has these flags, this builtin function table
10604 will not be supported. */
10605 int unsupported_target_flags;
10606 };
10607
10608 static const struct bdesc_map bdesc_arrays[] =
10609 {
10610 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
10611 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
10612 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
10613 { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
10614 MASK_64BIT }
10615 };
10616
10617 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
10618 suitable for input operand OP of instruction ICODE. Return the value. */
10619
10620 static rtx
10621 mips_prepare_builtin_arg (enum insn_code icode,
10622 unsigned int op, tree exp, unsigned int argnum)
10623 {
10624 rtx value;
10625 enum machine_mode mode;
10626
10627 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
10628 mode = insn_data[icode].operand[op].mode;
10629 if (!insn_data[icode].operand[op].predicate (value, mode))
10630 {
10631 value = copy_to_mode_reg (mode, value);
10632 /* Check the predicate again. */
10633 if (!insn_data[icode].operand[op].predicate (value, mode))
10634 {
10635 error ("invalid argument to builtin function");
10636 return const0_rtx;
10637 }
10638 }
10639
10640 return value;
10641 }
10642
10643 /* Return an rtx suitable for output operand OP of instruction ICODE.
10644 If TARGET is non-null, try to use it where possible. */
10645
10646 static rtx
10647 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10648 {
10649 enum machine_mode mode;
10650
10651 mode = insn_data[icode].operand[op].mode;
10652 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10653 target = gen_reg_rtx (mode);
10654
10655 return target;
10656 }
10657
10658 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10659
10660 rtx
10661 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10662 enum machine_mode mode ATTRIBUTE_UNUSED,
10663 int ignore ATTRIBUTE_UNUSED)
10664 {
10665 enum insn_code icode;
10666 enum mips_builtin_type type;
10667 tree fndecl;
10668 unsigned int fcode;
10669 const struct builtin_description *bdesc;
10670 const struct bdesc_map *m;
10671
10672 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10673 fcode = DECL_FUNCTION_CODE (fndecl);
10674
10675 bdesc = NULL;
10676 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10677 {
10678 if (fcode < m->size)
10679 {
10680 bdesc = m->bdesc;
10681 icode = bdesc[fcode].icode;
10682 type = bdesc[fcode].builtin_type;
10683 break;
10684 }
10685 fcode -= m->size;
10686 }
10687 if (bdesc == NULL)
10688 return 0;
10689
10690 switch (type)
10691 {
10692 case MIPS_BUILTIN_DIRECT:
10693 return mips_expand_builtin_direct (icode, target, exp, true);
10694
10695 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10696 return mips_expand_builtin_direct (icode, target, exp, false);
10697
10698 case MIPS_BUILTIN_MOVT:
10699 case MIPS_BUILTIN_MOVF:
10700 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10701 target, exp);
10702
10703 case MIPS_BUILTIN_CMP_ANY:
10704 case MIPS_BUILTIN_CMP_ALL:
10705 case MIPS_BUILTIN_CMP_UPPER:
10706 case MIPS_BUILTIN_CMP_LOWER:
10707 case MIPS_BUILTIN_CMP_SINGLE:
10708 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10709 target, exp);
10710
10711 case MIPS_BUILTIN_BPOSGE32:
10712 return mips_expand_builtin_bposge (type, target);
10713
10714 default:
10715 return 0;
10716 }
10717 }
10718
10719 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10720
10721 void
10722 mips_init_builtins (void)
10723 {
10724 const struct builtin_description *d;
10725 const struct bdesc_map *m;
10726 tree types[(int) MIPS_MAX_FTYPE_MAX];
10727 tree V2SF_type_node;
10728 tree V2HI_type_node;
10729 tree V4QI_type_node;
10730 unsigned int offset;
10731
10732 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10733 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10734 return;
10735
10736 if (TARGET_PAIRED_SINGLE_FLOAT)
10737 {
10738 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10739
10740 types[MIPS_V2SF_FTYPE_V2SF]
10741 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10742
10743 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10744 = build_function_type_list (V2SF_type_node,
10745 V2SF_type_node, V2SF_type_node, NULL_TREE);
10746
10747 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10748 = build_function_type_list (V2SF_type_node,
10749 V2SF_type_node, V2SF_type_node,
10750 integer_type_node, NULL_TREE);
10751
10752 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10753 = build_function_type_list (V2SF_type_node,
10754 V2SF_type_node, V2SF_type_node,
10755 V2SF_type_node, V2SF_type_node, NULL_TREE);
10756
10757 types[MIPS_V2SF_FTYPE_SF_SF]
10758 = build_function_type_list (V2SF_type_node,
10759 float_type_node, float_type_node, NULL_TREE);
10760
10761 types[MIPS_INT_FTYPE_V2SF_V2SF]
10762 = build_function_type_list (integer_type_node,
10763 V2SF_type_node, V2SF_type_node, NULL_TREE);
10764
10765 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10766 = build_function_type_list (integer_type_node,
10767 V2SF_type_node, V2SF_type_node,
10768 V2SF_type_node, V2SF_type_node, NULL_TREE);
10769
10770 types[MIPS_INT_FTYPE_SF_SF]
10771 = build_function_type_list (integer_type_node,
10772 float_type_node, float_type_node, NULL_TREE);
10773
10774 types[MIPS_INT_FTYPE_DF_DF]
10775 = build_function_type_list (integer_type_node,
10776 double_type_node, double_type_node, NULL_TREE);
10777
10778 types[MIPS_SF_FTYPE_V2SF]
10779 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10780
10781 types[MIPS_SF_FTYPE_SF]
10782 = build_function_type_list (float_type_node,
10783 float_type_node, NULL_TREE);
10784
10785 types[MIPS_SF_FTYPE_SF_SF]
10786 = build_function_type_list (float_type_node,
10787 float_type_node, float_type_node, NULL_TREE);
10788
10789 types[MIPS_DF_FTYPE_DF]
10790 = build_function_type_list (double_type_node,
10791 double_type_node, NULL_TREE);
10792
10793 types[MIPS_DF_FTYPE_DF_DF]
10794 = build_function_type_list (double_type_node,
10795 double_type_node, double_type_node, NULL_TREE);
10796 }
10797
10798 if (TARGET_DSP)
10799 {
10800 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10801 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10802
10803 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10804 = build_function_type_list (V2HI_type_node,
10805 V2HI_type_node, V2HI_type_node,
10806 NULL_TREE);
10807
10808 types[MIPS_SI_FTYPE_SI_SI]
10809 = build_function_type_list (intSI_type_node,
10810 intSI_type_node, intSI_type_node,
10811 NULL_TREE);
10812
10813 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10814 = build_function_type_list (V4QI_type_node,
10815 V4QI_type_node, V4QI_type_node,
10816 NULL_TREE);
10817
10818 types[MIPS_SI_FTYPE_V4QI]
10819 = build_function_type_list (intSI_type_node,
10820 V4QI_type_node,
10821 NULL_TREE);
10822
10823 types[MIPS_V2HI_FTYPE_V2HI]
10824 = build_function_type_list (V2HI_type_node,
10825 V2HI_type_node,
10826 NULL_TREE);
10827
10828 types[MIPS_SI_FTYPE_SI]
10829 = build_function_type_list (intSI_type_node,
10830 intSI_type_node,
10831 NULL_TREE);
10832
10833 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10834 = build_function_type_list (V4QI_type_node,
10835 V2HI_type_node, V2HI_type_node,
10836 NULL_TREE);
10837
10838 types[MIPS_V2HI_FTYPE_SI_SI]
10839 = build_function_type_list (V2HI_type_node,
10840 intSI_type_node, intSI_type_node,
10841 NULL_TREE);
10842
10843 types[MIPS_SI_FTYPE_V2HI]
10844 = build_function_type_list (intSI_type_node,
10845 V2HI_type_node,
10846 NULL_TREE);
10847
10848 types[MIPS_V2HI_FTYPE_V4QI]
10849 = build_function_type_list (V2HI_type_node,
10850 V4QI_type_node,
10851 NULL_TREE);
10852
10853 types[MIPS_V4QI_FTYPE_V4QI_SI]
10854 = build_function_type_list (V4QI_type_node,
10855 V4QI_type_node, intSI_type_node,
10856 NULL_TREE);
10857
10858 types[MIPS_V2HI_FTYPE_V2HI_SI]
10859 = build_function_type_list (V2HI_type_node,
10860 V2HI_type_node, intSI_type_node,
10861 NULL_TREE);
10862
10863 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10864 = build_function_type_list (V2HI_type_node,
10865 V4QI_type_node, V2HI_type_node,
10866 NULL_TREE);
10867
10868 types[MIPS_SI_FTYPE_V2HI_V2HI]
10869 = build_function_type_list (intSI_type_node,
10870 V2HI_type_node, V2HI_type_node,
10871 NULL_TREE);
10872
10873 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10874 = build_function_type_list (intDI_type_node,
10875 intDI_type_node, V4QI_type_node, V4QI_type_node,
10876 NULL_TREE);
10877
10878 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10879 = build_function_type_list (intDI_type_node,
10880 intDI_type_node, V2HI_type_node, V2HI_type_node,
10881 NULL_TREE);
10882
10883 types[MIPS_DI_FTYPE_DI_SI_SI]
10884 = build_function_type_list (intDI_type_node,
10885 intDI_type_node, intSI_type_node, intSI_type_node,
10886 NULL_TREE);
10887
10888 types[MIPS_V4QI_FTYPE_SI]
10889 = build_function_type_list (V4QI_type_node,
10890 intSI_type_node,
10891 NULL_TREE);
10892
10893 types[MIPS_V2HI_FTYPE_SI]
10894 = build_function_type_list (V2HI_type_node,
10895 intSI_type_node,
10896 NULL_TREE);
10897
10898 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10899 = build_function_type_list (void_type_node,
10900 V4QI_type_node, V4QI_type_node,
10901 NULL_TREE);
10902
10903 types[MIPS_SI_FTYPE_V4QI_V4QI]
10904 = build_function_type_list (intSI_type_node,
10905 V4QI_type_node, V4QI_type_node,
10906 NULL_TREE);
10907
10908 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10909 = build_function_type_list (void_type_node,
10910 V2HI_type_node, V2HI_type_node,
10911 NULL_TREE);
10912
10913 types[MIPS_SI_FTYPE_DI_SI]
10914 = build_function_type_list (intSI_type_node,
10915 intDI_type_node, intSI_type_node,
10916 NULL_TREE);
10917
10918 types[MIPS_DI_FTYPE_DI_SI]
10919 = build_function_type_list (intDI_type_node,
10920 intDI_type_node, intSI_type_node,
10921 NULL_TREE);
10922
10923 types[MIPS_VOID_FTYPE_SI_SI]
10924 = build_function_type_list (void_type_node,
10925 intSI_type_node, intSI_type_node,
10926 NULL_TREE);
10927
10928 types[MIPS_SI_FTYPE_PTR_SI]
10929 = build_function_type_list (intSI_type_node,
10930 ptr_type_node, intSI_type_node,
10931 NULL_TREE);
10932
10933 types[MIPS_SI_FTYPE_VOID]
10934 = build_function_type (intSI_type_node, void_list_node);
10935
10936 if (TARGET_DSPR2)
10937 {
10938 types[MIPS_V4QI_FTYPE_V4QI]
10939 = build_function_type_list (V4QI_type_node,
10940 V4QI_type_node,
10941 NULL_TREE);
10942
10943 types[MIPS_SI_FTYPE_SI_SI_SI]
10944 = build_function_type_list (intSI_type_node,
10945 intSI_type_node, intSI_type_node,
10946 intSI_type_node, NULL_TREE);
10947
10948 types[MIPS_DI_FTYPE_DI_USI_USI]
10949 = build_function_type_list (intDI_type_node,
10950 intDI_type_node,
10951 unsigned_intSI_type_node,
10952 unsigned_intSI_type_node, NULL_TREE);
10953
10954 types[MIPS_DI_FTYPE_SI_SI]
10955 = build_function_type_list (intDI_type_node,
10956 intSI_type_node, intSI_type_node,
10957 NULL_TREE);
10958
10959 types[MIPS_DI_FTYPE_USI_USI]
10960 = build_function_type_list (intDI_type_node,
10961 unsigned_intSI_type_node,
10962 unsigned_intSI_type_node, NULL_TREE);
10963
10964 types[MIPS_V2HI_FTYPE_SI_SI_SI]
10965 = build_function_type_list (V2HI_type_node,
10966 intSI_type_node, intSI_type_node,
10967 intSI_type_node, NULL_TREE);
10968
10969 }
10970 }
10971
10972 /* Iterate through all of the bdesc arrays, initializing all of the
10973 builtin functions. */
10974
10975 offset = 0;
10976 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10977 {
10978 if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10979 && (m->unsupported_target_flags & target_flags) == 0)
10980 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10981 if ((d->target_flags & target_flags) == d->target_flags)
10982 add_builtin_function (d->name, types[d->function_type],
10983 d - m->bdesc + offset,
10984 BUILT_IN_MD, NULL, NULL);
10985 offset += m->size;
10986 }
10987 }
10988
10989 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10990 .md pattern and CALL is the function expr with arguments. TARGET,
10991 if nonnull, suggests a good place to put the result.
10992 HAS_TARGET indicates the function must return something. */
10993
10994 static rtx
10995 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
10996 bool has_target)
10997 {
10998 rtx ops[MAX_RECOG_OPERANDS];
10999 int i = 0;
11000 int j = 0;
11001
11002 if (has_target)
11003 {
11004 /* We save target to ops[0]. */
11005 ops[0] = mips_prepare_builtin_target (icode, 0, target);
11006 i = 1;
11007 }
11008
11009 /* We need to test if the arglist is not zero. Some instructions have extra
11010 clobber registers. */
11011 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
11012 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11013
11014 switch (i)
11015 {
11016 case 2:
11017 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11018 break;
11019
11020 case 3:
11021 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11022 break;
11023
11024 case 4:
11025 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11026 break;
11027
11028 default:
11029 gcc_unreachable ();
11030 }
11031 return target;
11032 }
11033
11034 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
11035 function (TYPE says which). EXP is the tree for the function
11036 function, ICODE is the instruction that should be used to compare
11037 the first two arguments, and COND is the condition it should test.
11038 TARGET, if nonnull, suggests a good place to put the result. */
11039
11040 static rtx
11041 mips_expand_builtin_movtf (enum mips_builtin_type type,
11042 enum insn_code icode, enum mips_fp_condition cond,
11043 rtx target, tree exp)
11044 {
11045 rtx cmp_result, op0, op1;
11046
11047 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11048 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11049 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11050 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11051
11052 icode = CODE_FOR_mips_cond_move_tf_ps;
11053 target = mips_prepare_builtin_target (icode, 0, target);
11054 if (type == MIPS_BUILTIN_MOVT)
11055 {
11056 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11057 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11058 }
11059 else
11060 {
11061 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11062 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11063 }
11064 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11065 return target;
11066 }
11067
11068 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11069 into TARGET otherwise. Return TARGET. */
11070
11071 static rtx
11072 mips_builtin_branch_and_move (rtx condition, rtx target,
11073 rtx value_if_true, rtx value_if_false)
11074 {
11075 rtx true_label, done_label;
11076
11077 true_label = gen_label_rtx ();
11078 done_label = gen_label_rtx ();
11079
11080 /* First assume that CONDITION is false. */
11081 emit_move_insn (target, value_if_false);
11082
11083 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11084 emit_jump_insn (gen_condjump (condition, true_label));
11085 emit_jump_insn (gen_jump (done_label));
11086 emit_barrier ();
11087
11088 /* Fix TARGET if CONDITION is true. */
11089 emit_label (true_label);
11090 emit_move_insn (target, value_if_true);
11091
11092 emit_label (done_label);
11093 return target;
11094 }
11095
11096 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
11097 of the comparison instruction and COND is the condition it should test.
11098 EXP is the function call and arguments and TARGET, if nonnull,
11099 suggests a good place to put the boolean result. */
11100
11101 static rtx
11102 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11103 enum insn_code icode, enum mips_fp_condition cond,
11104 rtx target, tree exp)
11105 {
11106 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
11107 int i;
11108 int j = 0;
11109
11110 if (target == 0 || GET_MODE (target) != SImode)
11111 target = gen_reg_rtx (SImode);
11112
11113 /* Prepare the operands to the comparison. */
11114 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11115 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
11116 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11117
11118 switch (insn_data[icode].n_operands)
11119 {
11120 case 4:
11121 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
11122 break;
11123
11124 case 6:
11125 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
11126 ops[3], ops[4], GEN_INT (cond)));
11127 break;
11128
11129 default:
11130 gcc_unreachable ();
11131 }
11132
11133 /* If the comparison sets more than one register, we define the result
11134 to be 0 if all registers are false and -1 if all registers are true.
11135 The value of the complete result is indeterminate otherwise. */
11136 switch (builtin_type)
11137 {
11138 case MIPS_BUILTIN_CMP_ALL:
11139 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11140 return mips_builtin_branch_and_move (condition, target,
11141 const0_rtx, const1_rtx);
11142
11143 case MIPS_BUILTIN_CMP_UPPER:
11144 case MIPS_BUILTIN_CMP_LOWER:
11145 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11146 condition = gen_single_cc (cmp_result, offset);
11147 return mips_builtin_branch_and_move (condition, target,
11148 const1_rtx, const0_rtx);
11149
11150 default:
11151 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11152 return mips_builtin_branch_and_move (condition, target,
11153 const1_rtx, const0_rtx);
11154 }
11155 }
11156
11157 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
11158 suggests a good place to put the boolean result. */
11159
11160 static rtx
11161 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11162 {
11163 rtx condition, cmp_result;
11164 int cmp_value;
11165
11166 if (target == 0 || GET_MODE (target) != SImode)
11167 target = gen_reg_rtx (SImode);
11168
11169 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11170
11171 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11172 cmp_value = 32;
11173 else
11174 gcc_assert (0);
11175
11176 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11177 return mips_builtin_branch_and_move (condition, target,
11178 const1_rtx, const0_rtx);
11179 }
11180 \f
11181 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
11182 FIRST is true if this is the first time handling this decl. */
11183
11184 static void
11185 mips_encode_section_info (tree decl, rtx rtl, int first)
11186 {
11187 default_encode_section_info (decl, rtl, first);
11188
11189 if (TREE_CODE (decl) == FUNCTION_DECL)
11190 {
11191 rtx symbol = XEXP (rtl, 0);
11192
11193 if ((TARGET_LONG_CALLS && !mips_near_type_p (TREE_TYPE (decl)))
11194 || mips_far_type_p (TREE_TYPE (decl)))
11195 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
11196 }
11197 }
11198
11199 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
11200 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
11201
11202 static void
11203 mips_extra_live_on_entry (bitmap regs)
11204 {
11205 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
11206 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
11207 }
11208
11209 /* SImode values are represented as sign-extended to DImode. */
11210
11211 int
11212 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11213 {
11214 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11215 return SIGN_EXTEND;
11216
11217 return UNKNOWN;
11218 }
11219 \f
11220 #include "gt-mips.h"
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