| blob | 4be3131275c88039f8696c9d73b50e88b5cf92a0 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
70 /* This file should be included last. */
73 /* Defined for convenience. */
74 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
76 /* Classifies an address.
78 ADDRESS_REG_IMM
79 A simple base register plus immediate offset.
81 ADDRESS_REG_WB
82 A base register indexed by immediate offset with writeback.
84 ADDRESS_REG_REG
85 A base register indexed by (optionally scaled) register.
87 ADDRESS_REG_UXTW
88 A base register indexed by (optionally scaled) zero-extended register.
90 ADDRESS_REG_SXTW
91 A base register indexed by (optionally scaled) sign-extended register.
93 ADDRESS_LO_SUM
94 A LO_SUM rtx with a base register and "LO12" symbol relocation.
96 ADDRESS_SYMBOLIC:
97 A constant symbolic address, in pc-relative literal pool. */
100 ADDRESS_REG_IMM,
101 ADDRESS_REG_WB,
102 ADDRESS_REG_REG,
103 ADDRESS_REG_UXTW,
104 ADDRESS_REG_SXTW,
105 ADDRESS_LO_SUM,
106 ADDRESS_SYMBOLIC
107 };
111 rtx base;
112 rtx offset;
115 };
117 struct simd_immediate_info
118 {
119 rtx value;
124 };
126 /* The current code model. */
129 #ifdef HAVE_AS_TLS
130 #undef TARGET_HAVE_TLS
131 #define TARGET_HAVE_TLS 1
132 #endif
136 const_tree,
147 const_tree type,
151 /* Major revision number of the ARM Architecture implemented by the target. */
154 /* The processor for which instructions should be scheduled. */
157 /* Mask to specify which instruction scheduling options should be used. */
160 /* Global flag for PC relative loads. */
163 /* Support for command line parsing of boolean flags in the tuning
164 structures. */
165 struct aarch64_flag_desc
166 {
169 };
171 #define AARCH64_FUSION_PAIR(name, internal_name) \
172 { name, AARCH64_FUSE_##internal_name },
174 {
179 };
181 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
182 { name, AARCH64_EXTRA_TUNE_##internal_name },
184 {
189 };
191 /* Tuning parameters. */
194 {
195 {
200 },
207 };
210 {
211 {
216 },
223 };
226 {
227 {
232 },
239 };
242 {
243 {
248 },
255 };
258 {
259 {
264 },
271 };
274 {
275 {
280 },
287 };
290 {
292 /* Avoid the use of slow int<->fp moves for spilling by setting
293 their cost higher than memmov_cost. */
297 };
300 {
302 /* Avoid the use of slow int<->fp moves for spilling by setting
303 their cost higher than memmov_cost. */
307 };
310 {
312 /* Avoid the use of slow int<->fp moves for spilling by setting
313 their cost higher than memmov_cost. */
317 };
320 {
322 /* Avoid the use of slow int<->fp moves for spilling by setting
323 their cost higher than memmov_cost (actual, 4 and 9). */
327 };
330 {
335 };
338 {
340 /* Avoid the use of slow int<->fp moves for spilling by setting
341 their cost higher than memmov_cost. */
345 };
348 {
350 /* Avoid the use of int<->fp moves for spilling. */
354 };
357 {
359 /* Avoid the use of int<->fp moves for spilling. */
363 };
365 /* Generic costs for vector insn classes. */
367 {
383 };
385 /* ThunderX costs for vector insn classes. */
387 {
403 };
405 /* Generic costs for vector insn classes. */
407 {
423 };
426 {
442 };
444 /* Generic costs for vector insn classes. */
446 {
462 };
464 /* Costs for vector insn classes for Vulcan. */
466 {
482 };
484 /* Generic costs for branch instructions. */
486 {
489 };
491 /* Branch costs for Cortex-A57. */
493 {
496 };
498 /* Branch costs for Vulcan. */
500 {
503 };
505 /* Generic approximation modes. */
507 {
510 AARCH64_APPROX_NONE /* recip_sqrt */
511 };
513 /* Approximation modes for Exynos M1. */
515 {
518 AARCH64_APPROX_ALL /* recip_sqrt */
519 };
521 /* Approximation modes for X-Gene 1. */
523 {
526 AARCH64_APPROX_ALL /* recip_sqrt */
527 };
530 {
552 };
555 {
578 };
581 {
604 };
607 {
630 };
633 {
656 };
659 {
682 };
685 {
707 };
710 {
732 };
735 {
757 };
760 {
783 };
786 {
808 };
810 /* Support for fine-grained override of the tuning structures. */
811 struct aarch64_tuning_override_function
812 {
815 };
820 static const struct aarch64_tuning_override_function
821 aarch64_tuning_override_functions[] =
822 {
826 };
828 /* A processor implementing AArch64. */
829 struct processor
830 {
838 };
840 /* Architectures implementing AArch64. */
842 {
843 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
844 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
847 };
849 /* Processor cores implementing AArch64. */
851 {
852 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
853 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
854 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
855 FLAGS, &COSTS##_tunings},
860 };
863 /* Target specification. These are populated by the -march, -mtune, -mcpu
864 handling code or by target attributes. */
869 /* The current tuning set. */
872 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
874 /* An ISA extension in the co-processor and main instruction set space. */
875 struct aarch64_option_extension
876 {
880 };
883 {
887 }
888 aarch64_cc;
890 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
892 /* The condition codes of the processor, and the inverse function. */
894 {
897 };
899 /* Generate code to enable conditional branches in functions over 1 MiB. */
903 {
920 }
922 void
924 {
928 else
930 }
932 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
933 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
934 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
935 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
936 cost (in this case the best class is the lowest cost one). Using ALL_REGS
937 irrespectively of its cost results in bad allocations with many redundant
938 int<->FP moves which are expensive on various cores.
939 To avoid this we don't allow ALL_REGS as the allocno class, but force a
940 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
941 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
942 Otherwise set the allocno class depending on the mode.
943 The result of this is that it is no longer inefficient to have a higher
944 memory move cost than the register move cost.
945 */
947 static reg_class_t
949 reg_class_t best_class)
950 {
961 }
963 static unsigned int
965 {
969 }
971 static int
974 {
982 }
984 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
985 unsigned
987 {
995 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
996 equivalent DWARF register. */
998 }
1000 /* Return TRUE if MODE is any of the large INT modes. */
1001 static bool
1003 {
1005 }
1007 /* Return TRUE if MODE is any of the vector modes. */
1008 static bool
1010 {
1013 }
1015 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1016 static bool
1019 {
1027 }
1029 /* Implement HARD_REGNO_NREGS. */
1031 int
1033 {
1035 {
1041 }
1043 }
1045 /* Implement HARD_REGNO_MODE_OK. */
1047 int
1049 {
1054 /* The purpose of comparing with ptr_mode is to support the
1055 global register variable associated with the stack pointer
1056 register via the syntax of asm ("wsp") in ILP32. */
1066 {
1068 return
1070 else
1072 }
1075 }
1077 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1078 machine_mode
1080 machine_mode mode)
1081 {
1082 /* Handle modes that fit within single registers. */
1084 {
1087 else
1089 }
1090 /* Fall back to generic for multi-reg and very large modes. */
1091 else
1093 }
1095 /* Return true if calls to DECL should be treated as
1096 long-calls (ie called via a register). */
1097 static bool
1099 {
1101 }
1103 /* Return true if calls to symbol-ref SYM should be treated as
1104 long-calls (ie called via a register). */
1105 bool
1107 {
1109 }
1111 /* Return true if calls to symbol-ref SYM should not go through
1112 plt stubs. */
1114 bool
1116 {
1120 && decl
1121 && (!flag_plt
1127 }
1129 /* Return true if the offsets to a zero/sign-extract operation
1130 represent an expression that matches an extend operation. The
1131 operands represent the paramters from
1133 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1134 bool
1136 rtx extract_imm)
1137 {
1154 }
1156 /* Emit an insn that's a simple single-set. Both the operands must be
1157 known to be valid. */
1160 {
1162 }
1164 /* X and Y are two things to compare using CODE. Emit the compare insn and
1165 return the rtx for register 0 in the proper mode. */
1166 rtx
1168 {
1174 }
1176 /* Build the SYMBOL_REF for __tls_get_addr. */
1180 rtx
1182 {
1186 }
1188 /* Return the TLS model to use for ADDR. */
1190 static enum tls_model
1192 {
1197 {
1201 }
1206 }
1208 /* We'll allow lo_sum's in addresses in our legitimate addresses
1209 so that combine would take care of combining addresses where
1210 necessary, but for generation purposes, we'll generate the address
1211 as :
1212 RTL Absolute
1213 tmp = hi (symbol_ref); adrp x1, foo
1214 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1215 nop
1217 PIC TLS
1218 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1219 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1220 bl __tls_get_addr
1221 nop
1223 Load TLS symbol, depending on TLS mechanism and TLS access model.
1225 Global Dynamic - Traditional TLS:
1226 adrp tmp, :tlsgd:imm
1227 add dest, tmp, #:tlsgd_lo12:imm
1228 bl __tls_get_addr
1230 Global Dynamic - TLS Descriptors:
1231 adrp dest, :tlsdesc:imm
1232 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1233 add dest, dest, #:tlsdesc_lo12:imm
1234 blr tmp
1235 mrs tp, tpidr_el0
1236 add dest, dest, tp
1238 Initial Exec:
1239 mrs tp, tpidr_el0
1240 adrp tmp, :gottprel:imm
1241 ldr dest, [tmp, #:gottprel_lo12:imm]
1242 add dest, dest, tp
1244 Local Exec:
1245 mrs tp, tpidr_el0
1246 add t0, tp, #:tprel_hi12:imm, lsl #12
1247 add t0, t0, #:tprel_lo12_nc:imm
1248 */
1250 static void
1253 {
1255 {
1257 {
1258 /* In ILP32, the mode of dest can be either SImode or DImode. */
1270 }
1277 {
1280 rtx insn;
1281 rtx mem;
1283 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1284 here before rtl expand. Tree IVOPT will generate rtl pattern to
1285 decide rtx costs, in which case pic_offset_table_rtx is not
1286 initialized. For that case no need to generate the first adrp
1287 instruction as the final cost for global variable access is
1288 one instruction. */
1290 {
1291 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1292 using the page base as GOT base, the first page may be wasted,
1293 in the worst scenario, there is only 28K space for GOT).
1295 The generate instruction sequence for accessing global variable
1296 is:
1298 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1300 Only one instruction needed. But we must initialize
1301 pic_offset_table_rtx properly. We generate initialize insn for
1302 every global access, and allow CSE to remove all redundant.
1304 The final instruction sequences will look like the following
1305 for multiply global variables access.
1307 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1309 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1310 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1311 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1312 ... */
1321 }
1324 {
1327 else
1331 }
1332 else
1333 {
1338 }
1340 /* The operand is expected to be MEM. Whenever the related insn
1341 pattern changed, above code which calculate mem should be
1342 updated. */
1348 }
1351 {
1352 /* In ILP32, the mode of dest can be either SImode or DImode,
1353 while the got entry is always of SImode size. The mode of
1354 dest depends on how dest is used: if dest is assigned to a
1355 pointer (e.g. in the memory), it has SImode; it may have
1356 DImode if dest is dereferenced to access the memeory.
1357 This is why we have to handle three different ldr_got_small
1358 patterns here (two patterns for ILP32). */
1360 rtx insn;
1361 rtx mem;
1370 {
1373 else
1377 }
1378 else
1379 {
1384 }
1391 }
1394 {
1402 else
1410 }
1413 {
1416 rtx tp;
1420 /* In ILP32, the got entry is always of SImode size. Unlike
1421 small GOT, the dest is fixed at reg 0. */
1424 else
1434 }
1437 {
1438 /* In ILP32, the mode of dest can be either SImode or DImode,
1439 while the got entry is always of SImode size. The mode of
1440 dest depends on how dest is used: if dest is assigned to a
1441 pointer (e.g. in the memory), it has SImode; it may have
1442 DImode if dest is dereferenced to access the memeory.
1443 This is why we have to handle three different tlsie_small
1444 patterns here (two patterns for ILP32). */
1450 {
1453 else
1454 {
1457 }
1458 }
1459 else
1460 {
1463 }
1468 }
1474 {
1482 {
1505 }
1509 }
1516 {
1521 {
1524 else
1525 {
1528 }
1529 }
1530 else
1531 {
1534 }
1538 }
1542 }
1543 }
1545 /* Emit a move from SRC to DEST. Assume that the move expanders can
1546 handle all moves if !can_create_pseudo_p (). The distinction is
1547 important because, unlike emit_move_insn, the move expanders know
1548 how to force Pmode objects into the constant pool even when the
1549 constant pool address is not itself legitimate. */
1550 static rtx
1552 {
1556 }
1558 /* Split a 128-bit move operation into two 64-bit move operations,
1559 taking care to handle partial overlap of register to register
1560 copies. Special cases are needed when moving between GP regs and
1561 FP regs. SRC can be a register, constant or memory; DST a register
1562 or memory. If either operand is memory it must not have any side
1563 effects. */
1564 void
1566 {
1577 {
1581 /* Handle FP <-> GP regs. */
1583 {
1588 {
1591 }
1592 else
1593 {
1596 }
1598 }
1600 {
1605 {
1608 }
1609 else
1610 {
1613 }
1615 }
1616 }
1623 /* At most one pairing may overlap. */
1625 {
1628 }
1629 else
1630 {
1633 }
1634 }
1636 bool
1638 {
1641 }
1643 /* Split a complex SIMD combine. */
1645 void
1647 {
1654 {
1658 {
1682 }
1686 }
1687 }
1689 /* Split a complex SIMD move. */
1691 void
1693 {
1700 {
1706 {
1730 }
1734 }
1735 }
1737 bool
1740 {
1744 }
1747 static rtx
1749 {
1752 else
1753 {
1756 }
1757 }
1760 static rtx
1762 {
1764 {
1765 rtx high;
1766 /* Load the full offset into a register. This
1767 might be improvable in the future. */
1773 }
1775 }
1777 static int
1779 machine_mode mode)
1780 {
1789 {
1793 }
1796 {
1798 {
1803 else
1806 }
1808 }
1810 /* Remaining cases are all for DImode. */
1819 {
1820 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1821 For a 64-bit bitmask try whether changing 16 bits to all ones or
1822 zeroes creates a valid bitmask. To check any repeated bitmask,
1823 try using 16 bits from the other 32-bit half of val. */
1826 {
1837 }
1839 {
1841 {
1845 }
1847 }
1848 }
1850 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1851 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1852 otherwise skip zero bits. */
1864 {
1870 num_insns ++;
1871 }
1874 }
1877 void
1879 {
1884 /* Check on what type of symbol it is. */
1888 {
1892 /* If we have (const (plus symbol offset)), separate out the offset
1893 before we start classifying the symbol. */
1898 {
1902 {
1908 }
1913 /* If we aren't generating PC relative literals, then
1914 we need to expand the literal pool access carefully.
1915 This is something that needs to be done in a number
1916 of places, so could well live as a separate function. */
1918 {
1923 }
1940 {
1946 }
1947 /* FALLTHRU */
1960 }
1961 }
1964 {
1967 else
1968 {
1972 }
1975 }
1978 }
1980 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1981 temporary value if necessary. FRAME_RELATED_P should be true if
1982 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1983 to the generated instructions. If SCRATCHREG is known to hold
1984 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
1985 immediate again.
1987 Since this function may be used to adjust the stack pointer, we must
1988 ensure that it cannot cause transient stack deallocation (for example
1989 by first incrementing SP and then decrementing when adjusting by a
1990 large immediate). */
1992 static void
1996 {
2004 /* Single instruction adjustment. */
2006 {
2010 }
2012 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2013 Only do this if mdelta is not a 16-bit move as adjusting using a move
2014 is better. */
2016 {
2025 }
2027 /* Emit a move immediate if required and an addition/subtraction. */
2034 {
2038 }
2039 }
2043 HOST_WIDE_INT delta)
2044 {
2046 }
2050 {
2053 }
2057 {
2060 }
2062 static bool
2064 tree exp ATTRIBUTE_UNUSED)
2065 {
2066 /* Currently, always true. */
2068 }
2070 /* Implement TARGET_PASS_BY_REFERENCE. */
2072 static bool
2074 machine_mode mode,
2075 const_tree type,
2077 {
2078 HOST_WIDE_INT size;
2079 machine_mode dummymode;
2082 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2086 /* Aggregates are passed by reference based on their size. */
2088 {
2090 }
2092 /* Variable sized arguments are always returned by reference. */
2096 /* Can this be a candidate to be passed in fp/simd register(s)? */
2099 NULL))
2102 /* Arguments which are variable sized or larger than 2 registers are
2103 passed by reference unless they are a homogenous floating point
2104 aggregate. */
2106 }
2108 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2109 static bool
2111 {
2112 machine_mode dummy_mode;
2115 /* Never happens in little-endian mode. */
2119 /* Only composite types smaller than or equal to 16 bytes can
2120 be potentially returned in registers. */
2126 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2127 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2128 is always passed/returned in the least significant bits of fp/simd
2129 register(s). */
2135 }
2137 /* Implement TARGET_FUNCTION_VALUE.
2138 Define how to find the value returned by a function. */
2140 static rtx
2143 {
2144 machine_mode mode;
2147 machine_mode ag_mode;
2154 {
2158 {
2161 }
2162 }
2166 {
2168 {
2171 }
2172 else
2173 {
2175 rtx par;
2179 {
2184 }
2186 }
2187 }
2188 else
2190 }
2192 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2193 Return true if REGNO is the number of a hard register in which the values
2194 of called function may come back. */
2196 static bool
2198 {
2199 /* Maximum of 16 bytes can be returned in the general registers. Examples
2200 of 16-byte return values are: 128-bit integers and 16-byte small
2201 structures (excluding homogeneous floating-point aggregates). */
2205 /* Up to four fp/simd registers can return a function value, e.g. a
2206 homogeneous floating-point aggregate having four members. */
2211 }
2213 /* Implement TARGET_RETURN_IN_MEMORY.
2215 If the type T of the result of a function is such that
2216 void func (T arg)
2217 would require that arg be passed as a value in a register (or set of
2218 registers) according to the parameter passing rules, then the result
2219 is returned in the same registers as would be used for such an
2220 argument. */
2222 static bool
2224 {
2225 HOST_WIDE_INT size;
2226 machine_mode ag_mode;
2232 /* Simple scalar types always returned in registers. */
2236 type,
2239 NULL))
2242 /* Types larger than 2 registers returned in memory. */
2245 }
2247 static bool
2250 {
2253 type,
2255 nregs,
2256 NULL);
2257 }
2259 /* Given MODE and TYPE of a function argument, return the alignment in
2260 bits. The idea is to suppress any stronger alignment requested by
2261 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2262 This is a helper function for local use only. */
2264 static unsigned int
2266 {
2286 }
2288 /* Layout a function argument according to the AAPCS64 rules. The rule
2289 numbers refer to the rule numbers in the AAPCS64. */
2291 static void
2293 const_tree type,
2295 {
2299 HOST_WIDE_INT size;
2301 /* We need to do this once per argument. */
2307 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2308 size
2310 UNITS_PER_WORD);
2314 mode,
2315 type,
2318 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2319 The following code thus handles passing by SIMD/FP registers first. */
2323 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2324 and homogenous short-vector aggregates (HVA). */
2326 {
2331 {
2334 {
2337 }
2338 else
2339 {
2340 rtx par;
2344 {
2347 tmp = gen_rtx_EXPR_LIST
2351 }
2353 }
2355 }
2356 else
2357 {
2358 /* C.3 NSRN is set to 8. */
2361 }
2362 }
2367 /* C6 - C9. though the sign and zero extension semantics are
2368 handled elsewhere. This is the case where the argument fits
2369 entirely general registers. */
2371 {
2376 /* C.8 if the argument has an alignment of 16 then the NGRN is
2377 rounded up to the next even number. */
2379 {
2382 }
2383 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2384 A reg is still generated for it, but the caller should be smart
2385 enough not to use it. */
2387 {
2389 }
2390 else
2391 {
2392 rtx par;
2397 {
2402 }
2404 }
2408 }
2410 /* C.11 */
2413 /* The argument is passed on stack; record the needed number of words for
2414 this argument and align the total size if necessary. */
2415 on_stack:
2421 }
2423 /* Implement TARGET_FUNCTION_ARG. */
2425 static rtx
2428 {
2437 }
2439 void
2441 const_tree fntype ATTRIBUTE_UNUSED,
2442 rtx libname ATTRIBUTE_UNUSED,
2443 const_tree fndecl ATTRIBUTE_UNUSED,
2445 {
2459 {
2466 }
2468 }
2470 static void
2472 machine_mode mode,
2473 const_tree type,
2475 {
2478 {
2488 }
2489 }
2491 bool
2493 {
2496 }
2498 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2499 PARM_BOUNDARY bits of alignment, but will be given anything up
2500 to STACK_BOUNDARY bits if the type requires it. This makes sure
2501 that both before and after the layout of each argument, the Next
2502 Stacked Argument Address (NSAA) will have a minimum alignment of
2503 8 bytes. */
2505 static unsigned int
2507 {
2515 }
2517 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2519 Return true if an argument passed on the stack should be padded upwards,
2520 i.e. if the least-significant byte of the stack slot has useful data.
2522 Small aggregate types are placed in the lowest memory address.
2524 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2526 bool
2528 {
2529 /* On little-endian targets, the least significant byte of every stack
2530 argument is passed at the lowest byte address of the stack slot. */
2534 /* Otherwise, integral, floating-point and pointer types are padded downward:
2535 the least significant byte of a stack argument is passed at the highest
2536 byte address of the stack slot. */
2543 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2545 }
2547 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2549 It specifies padding for the last (may also be the only)
2550 element of a block move between registers and memory. If
2551 assuming the block is in the memory, padding upward means that
2552 the last element is padded after its highest significant byte,
2553 while in downward padding, the last element is padded at the
2554 its least significant byte side.
2556 Small aggregates and small complex types are always padded
2557 upwards.
2559 We don't need to worry about homogeneous floating-point or
2560 short-vector aggregates; their move is not affected by the
2561 padding direction determined here. Regardless of endianness,
2562 each element of such an aggregate is put in the least
2563 significant bits of a fp/simd register.
2565 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2566 register has useful data, and return the opposite if the most
2567 significant byte does. */
2569 bool
2572 {
2574 /* Small composite types are always padded upward. */
2576 {
2581 }
2583 /* Otherwise, use the default padding. */
2585 }
2587 static machine_mode
2589 {
2591 }
2593 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2595 /* We use the 12-bit shifted immediate arithmetic instructions so values
2596 must be multiple of (1 << 12), i.e. 4096. */
2597 #define ARITH_FACTOR 4096
2599 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2600 #error Cannot use simple address calculation for stack probing
2601 #endif
2603 /* The pair of scratch registers used for stack probing. */
2604 #define PROBE_STACK_FIRST_REG 9
2605 #define PROBE_STACK_SECOND_REG 10
2607 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2608 inclusive. These are offsets from the current stack pointer. */
2610 static void
2612 {
2615 /* See the same assertion on PROBE_INTERVAL above. */
2618 /* See if we have a constant small number of probes to generate. If so,
2619 that's the easy case. */
2621 {
2628 }
2630 /* The run-time loop is made up of 8 insns in the generic case while the
2631 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2633 {
2638 stack_pointer_rtx,
2642 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2643 it exceeds SIZE. If only two probes are needed, this will not
2644 generate any code. Then probe at FIRST + SIZE. */
2646 {
2650 }
2654 {
2659 }
2660 else
2662 }
2664 /* Otherwise, do the same as above, but in a loop. Note that we must be
2665 extra careful with variables wrapping around because we might be at
2666 the very top (or the very bottom) of the address space and we have
2667 to be able to handle this case properly; in particular, we use an
2668 equality test for the loop condition. */
2669 else
2670 {
2673 /* Step 1: round SIZE to the previous multiple of the interval. */
2678 /* Step 2: compute initial and final value of the loop counter. */
2680 /* TEST_ADDR = SP + FIRST. */
2684 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2690 /* Step 3: the loop
2692 do
2693 {
2694 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2695 probe at TEST_ADDR
2696 }
2697 while (TEST_ADDR != LAST_ADDR)
2699 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2700 until it is equal to ROUNDED_SIZE. */
2704 else
2708 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2709 that SIZE is equal to ROUNDED_SIZE. */
2712 {
2716 {
2721 }
2722 else
2724 }
2725 }
2727 /* Make sure nothing is scheduled before we are done. */
2729 }
2731 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2732 absolute addresses. */
2736 {
2743 /* Loop. */
2746 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2751 /* Probe at TEST_ADDR. */
2754 /* Test if TEST_ADDR == LAST_ADDR. */
2758 /* Branch. */
2764 }
2766 static bool
2768 {
2769 /* In aarch64_override_options_after_change
2770 flag_omit_leaf_frame_pointer turns off the frame pointer by
2771 default. Turn it back on now if we've not got a leaf
2772 function. */
2777 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2782 }
2784 /* Mark the registers that need to be saved by the callee and calculate
2785 the size of the callee-saved registers area and frame record (both FP
2786 and LR may be omitted). */
2787 static void
2789 {
2796 #define SLOT_NOT_REQUIRED (-2)
2797 #define SLOT_REQUIRED (-1)
2802 /* First mark all the registers that really need to be saved... */
2809 /* ... that includes the eh data registers (if needed)... */
2815 /* ... and any callee saved register that dataflow says is live. */
2825 {
2828 }
2831 {
2832 /* FP and LR are placed in the linkage record. */
2838 }
2840 /* Now assign stack slots for them. */
2843 {
2850 }
2858 {
2859 /* If there is an alignment gap between integer and fp callee-saves,
2860 allocate the last fp register to it if possible. */
2862 {
2865 }
2874 }
2880 HOST_WIDE_INT varargs_and_saved_regs_size
2907 {
2908 /* Simple, small frame with no outgoing arguments:
2909 stp reg1, reg2, [sp, -frame_size]!
2910 stp reg3, reg4, [sp, 16] */
2912 }
2917 {
2918 /* Frame with small outgoing arguments:
2919 sub sp, sp, frame_size
2920 stp reg1, reg2, [sp, outgoing_args_size]
2921 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2925 }
2927 {
2928 /* Frame with large outgoing arguments but a small local area:
2929 stp reg1, reg2, [sp, -hard_fp_offset]!
2930 stp reg3, reg4, [sp, 16]
2931 sub sp, sp, outgoing_args_size */
2935 }
2938 {
2939 /* Frame with large local area and outgoing arguments (this pushes the
2940 callee-saves first, followed by the locals and outgoing area):
2941 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2942 stp reg3, reg4, [sp, 16]
2943 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2949 }
2950 else
2951 {
2952 /* Frame with large local area and outgoing arguments using frame pointer:
2953 sub sp, sp, hard_fp_offset
2954 stp x29, x30, [sp, 0]
2955 add x29, sp, 0
2956 stp reg3, reg4, [sp, 16]
2957 sub sp, sp, outgoing_args_size */
2961 }
2964 }
2966 /* Return true if the register REGNO is saved on entry to
2967 the current function. */
2969 static bool
2971 {
2973 }
2975 /* Return the next register up from REGNO up to LIMIT for the callee
2976 to save. */
2978 static unsigned
2980 {
2982 regno ++;
2984 }
2986 /* Push the register number REGNO of mode MODE to the stack with write-back
2987 adjusting the stack by ADJUSTMENT. */
2989 static void
2991 HOST_WIDE_INT adjustment)
2992 {
3003 }
3005 /* Generate and return an instruction to store the pair of registers
3006 REG and REG2 of mode MODE to location BASE with write-back adjusting
3007 the stack location BASE by ADJUSTMENT. */
3009 static rtx
3011 HOST_WIDE_INT adjustment)
3012 {
3014 {
3025 }
3026 }
3028 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3029 stack pointer by ADJUSTMENT. */
3031 static void
3033 {
3048 }
3050 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3051 adjusting it by ADJUSTMENT afterwards. */
3053 static rtx
3055 HOST_WIDE_INT adjustment)
3056 {
3058 {
3067 }
3068 }
3070 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3071 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3072 into CFI_OPS. */
3074 static void
3077 {
3084 {
3088 }
3089 else
3090 {
3095 }
3096 }
3098 /* Generate and return a store pair instruction of mode MODE to store
3099 register REG1 to MEM1 and register REG2 to MEM2. */
3101 static rtx
3103 rtx reg2)
3104 {
3106 {
3115 }
3116 }
3118 /* Generate and regurn a load pair isntruction of mode MODE to load register
3119 REG1 from MEM1 and register REG2 from MEM2. */
3121 static rtx
3123 rtx mem2)
3124 {
3126 {
3135 }
3136 }
3138 /* Return TRUE if return address signing should be enabled for the current
3139 function, otherwise return FALSE. */
3141 bool
3143 {
3144 /* This function should only be called after frame laid out. */
3147 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3148 if it's LR is pushed onto stack. */
3152 }
3154 /* Emit code to save the callee-saved registers from register number START
3155 to LIMIT to the stack at the location starting at offset START_OFFSET,
3156 skipping any write-back candidates if SKIP_WB is true. */
3158 static void
3161 {
3171 {
3173 HOST_WIDE_INT offset;
3186 offset));
3195 {
3197 rtx mem2;
3201 offset));
3203 reg2));
3205 /* The first part of a frame-related parallel insn is
3206 always assumed to be relevant to the frame
3207 calculations; subsequent parts, are only
3208 frame-related if explicitly marked. */
3211 }
3212 else
3216 }
3217 }
3219 /* Emit code to restore the callee registers of mode MODE from register
3220 number START up to and including LIMIT. Restore from the stack offset
3221 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3222 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3224 static void
3228 {
3234 HOST_WIDE_INT offset;
3239 {
3260 {
3262 rtx mem2;
3270 }
3271 else
3274 }
3275 }
3279 HOST_WIDE_INT offset)
3280 {
3282 }
3286 {
3290 }
3292 bool
3294 {
3298 }
3300 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3302 static sbitmap
3304 {
3310 /* The registers we need saved to the frame. */
3313 {
3318 /* Check that we can access the stack slot of the register with one
3319 direct load with no adjustments needed. */
3322 }
3324 /* Don't mess with the hard frame pointer. */
3330 /* If aarch64_layout_frame has chosen registers to store/restore with
3331 writeback don't interfere with them to avoid having to output explicit
3332 stack adjustment instructions. */
3342 }
3344 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3346 static sbitmap
3348 {
3356 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3365 }
3367 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3368 Nothing to do for aarch64. */
3370 static void
3372 {
3373 }
3375 /* Return the next set bit in BMP from START onwards. Return the total number
3376 of bits in BMP if no set bit is found at or after START. */
3378 static unsigned int
3380 {
3391 }
3393 /* Do the work for aarch64_emit_prologue_components and
3394 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3395 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3396 for these components or the epilogue sequence. That is, it determines
3397 whether we should emit stores or loads and what kind of CFA notes to attach
3398 to the insns. Otherwise the logic for the two sequences is very
3399 similar. */
3401 static void
3403 {
3405 ? HARD_FRAME_POINTER_REGNUM
3413 {
3414 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3415 so DFmode for the vector registers is enough. */
3427 /* No more registers to handle after REGNO.
3428 Emit a single save/restore and exit. */
3430 {
3435 else
3438 }
3441 /* The next register is not of the same class or its offset is not
3442 mergeable with the current one into a pair. */
3447 {
3452 else
3457 }
3459 /* REGNO2 can be saved/restored in a pair with REGNO. */
3471 else
3476 {
3479 }
3480 else
3481 {
3484 }
3487 }
3488 }
3490 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3492 static void
3494 {
3496 }
3498 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3500 static void
3502 {
3504 }
3506 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3508 static void
3510 {
3514 }
3516 /* AArch64 stack frames generated by this compiler look like:
3518 +-------------------------------+
3519 | |
3520 | incoming stack arguments |
3521 | |
3522 +-------------------------------+
3523 | | <-- incoming stack pointer (aligned)
3524 | callee-allocated save area |
3525 | for register varargs |
3526 | |
3527 +-------------------------------+
3528 | local variables | <-- frame_pointer_rtx
3529 | |
3530 +-------------------------------+
3531 | padding0 | \
3532 +-------------------------------+ |
3533 | callee-saved registers | | frame.saved_regs_size
3534 +-------------------------------+ |
3535 | LR' | |
3536 +-------------------------------+ |
3537 | FP' | / <- hard_frame_pointer_rtx (aligned)
3538 +-------------------------------+
3539 | dynamic allocation |
3540 +-------------------------------+
3541 | padding |
3542 +-------------------------------+
3543 | outgoing stack arguments | <-- arg_pointer
3544 | |
3545 +-------------------------------+
3546 | | <-- stack_pointer_rtx (aligned)
3548 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3549 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3550 unchanged. */
3552 /* Generate the prologue instructions for entry into a function.
3553 Establish the stack frame by decreasing the stack pointer with a
3554 properly calculated size and, if necessary, create a frame record
3555 filled with the values of LR and previous frame pointer. The
3556 current FP is also set up if it is in use. */
3558 void
3560 {
3572 /* Sign return address for functions. */
3574 {
3578 }
3584 {
3586 {
3590 }
3593 }
3601 {
3606 stack_pointer_rtx,
3610 }
3617 }
3619 /* Return TRUE if we can use a simple_return insn.
3621 This function checks whether the callee saved stack is empty, which
3622 means no restore actions are need. The pro_and_epilogue will use
3623 this to check whether shrink-wrapping opt is feasible. */
3625 bool
3627 {
3637 }
3639 /* Generate the epilogue instructions for returning from a function.
3640 This is almost exactly the reverse of the prolog sequence, except
3641 that we need to insert barriers to avoid scheduling loads that read
3642 from a deallocated stack, and we optimize the unwind records by
3643 emitting them all together if possible. */
3644 void
3646 {
3658 /* We need to add memory barrier to prevent read from deallocated stack. */
3662 /* Emit a barrier to prevent loads from a deallocated stack. */
3665 {
3668 }
3670 /* Restore the stack pointer from the frame pointer if it may not
3671 be the same as the stack pointer. */
3673 {
3675 hard_frame_pointer_rtx,
3677 /* If writeback is used when restoring callee-saves, the CFA
3678 is restored on the instruction doing the writeback. */
3680 }
3681 else
3696 {
3697 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3703 }
3708 {
3709 /* Emit delayed restores and reset the CFA to be SP. */
3714 }
3716 /* We prefer to emit the combined return/authenticate instruction RETAA,
3717 however there are three cases in which we must instead emit an explicit
3718 authentication instruction.
3720 1) Sibcalls don't return in a normal way, so if we're about to call one
3721 we must authenticate.
3723 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3724 generating code for !TARGET_ARMV8_3 we can't use it and must
3725 explicitly authenticate.
3727 3) On an eh_return path we make extra stack adjustments to update the
3728 canonical frame address to be the exception handler's CFA. We want
3729 to authenticate using the CFA of the function which calls eh_return.
3730 */
3733 {
3737 }
3739 /* Stack adjustment for exception handler. */
3741 {
3742 /* We need to unwind the stack by the offset computed by
3743 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3744 to be SP; letting the CFA move during this adjustment
3745 is just as correct as retaining the CFA from the body
3746 of the function. Therefore, do nothing special. */
3748 }
3753 }
3755 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3756 normally or return to a previous frame after unwinding.
3758 An EH return uses a single shared return sequence. The epilogue is
3759 exactly like a normal epilogue except that it has an extra input
3760 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3761 that must be applied after the frame has been destroyed. An extra label
3762 is inserted before the epilogue which initializes this register to zero,
3763 and this is the entry point for a normal return.
3765 An actual EH return updates the return address, initializes the stack
3766 adjustment and jumps directly into the epilogue (bypassing the zeroing
3767 of the adjustment). Since the return address is typically saved on the
3768 stack when a function makes a call, the saved LR must be updated outside
3769 the epilogue.
3771 This poses problems as the store is generated well before the epilogue,
3772 so the offset of LR is not known yet. Also optimizations will remove the
3773 store as it appears dead, even after the epilogue is generated (as the
3774 base or offset for loading LR is different in many cases).
3776 To avoid these problems this implementation forces the frame pointer
3777 in eh_return functions so that the location of LR is fixed and known early.
3778 It also marks the store volatile, so no optimization is permitted to
3779 remove the store. */
3780 rtx
3782 {
3786 /* Mark the store volatile, so no optimization is permitted to remove it. */
3789 }
3791 /* Output code to add DELTA to the first argument, and then jump
3792 to FUNCTION. Used for C++ multiple inheritance. */
3793 static void
3795 HOST_WIDE_INT delta,
3796 HOST_WIDE_INT vcall_offset,
3797 tree function)
3798 {
3799 /* The this pointer is always in x0. Note that this differs from
3800 Arm where the this pointer maybe bumped to r1 if r0 is required
3801 to return a pointer to an aggregate. On AArch64 a result value
3802 pointer will be in x8. */
3812 else
3813 {
3822 {
3826 else
3828 }
3832 else
3839 else
3840 {
3842 Pmode);
3844 }
3848 else
3854 }
3856 /* Generate a tail call to the target function. */
3858 {
3861 }
3873 /* Stop pretending to be a post-reload pass. */
3875 }
3877 static bool
3879 {
3884 {
3888 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3889 TLS offsets, not real symbol references. */
3892 }
3894 }
3897 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3898 a left shift of 0 or 12 bits. */
3899 bool
3901 {
3904 );
3905 }
3908 /* Return true if val is an immediate that can be loaded into a
3909 register by a MOVZ instruction. */
3910 static bool
3912 {
3914 {
3918 }
3919 else
3920 {
3921 /* Ignore sign extension. */
3923 }
3926 }
3928 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3931 {
3937 };
3940 /* Return true if val is a valid bitmask immediate. */
3942 bool
3944 {
3948 /* Check for a single sequence of one bits and return quickly if so.
3949 The special cases of all ones and all zeroes returns false. */
3956 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3960 /* Invert if the immediate doesn't start with a zero bit - this means we
3961 only need to search for sequences of one bits. */
3965 /* Find the first set bit and set tmp to val with the first sequence of one
3966 bits removed. Return success if there is a single sequence of ones. */
3973 /* Find the next set bit and compute the difference in bit position. */
3978 /* Check the bit position difference is a power of 2, and that the first
3979 sequence of one bits fits within 'bits' bits. */
3983 /* Check the sequence of one bits is repeated 64/bits times. */
3985 }
3987 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
3988 Assumed precondition: VAL_IN Is not zero. */
3990 unsigned HOST_WIDE_INT
3992 {
3999 }
4001 /* Create constant where bits outside of lowest bit set to highest bit set
4002 are set to 1. */
4004 unsigned HOST_WIDE_INT
4006 {
4008 }
4010 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4012 bool
4014 {
4024 }
4026 /* Return true if val is an immediate that can be loaded into a
4027 register in a single instruction. */
4028 bool
4030 {
4034 }
4036 static bool
4038 {
4046 {
4050 else
4051 /* Avoid generating a 64-bit relocation in ILP32; leave
4052 to aarch64_expand_mov_immediate to handle it properly. */
4054 }
4057 }
4059 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4060 The expansion for a table switch is quite expensive due to the number
4061 of instructions, the table lookup and hard to predict indirect jump.
4062 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4063 set, otherwise use tables for > 16 cases as a tradeoff between size and
4064 performance. When optimizing for size, use the default setting. */
4066 static unsigned int
4068 {
4069 /* Use the specified limit for the number of cases before using jump
4070 tables at higher optimization levels. */
4074 else
4076 }
4078 /* Return true if register REGNO is a valid index register.
4079 STRICT_P is true if REG_OK_STRICT is in effect. */
4081 bool
4083 {
4085 {
4093 }
4095 }
4097 /* Return true if register REGNO is a valid base register for mode MODE.
4098 STRICT_P is true if REG_OK_STRICT is in effect. */
4100 bool
4102 {
4104 {
4112 }
4114 /* The fake registers will be eliminated to either the stack or
4115 hard frame pointer, both of which are usually valid base registers.
4116 Reload deals with the cases where the eliminated form isn't valid. */
4121 }
4123 /* Return true if X is a valid base register for mode MODE.
4124 STRICT_P is true if REG_OK_STRICT is in effect. */
4126 static bool
4128 {
4133 }
4135 /* Return true if address offset is a valid index. If it is, fill in INFO
4136 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4138 static bool
4141 {
4143 rtx index;
4146 /* (reg:P) */
4149 {
4153 }
4154 /* (sign_extend:DI (reg:SI)) */
4159 {
4164 }
4165 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4172 {
4177 }
4178 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4185 {
4190 }
4191 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4198 {
4206 }
4207 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4208 (const_int 0xffffffff<<shift)) */
4215 {
4221 }
4222 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4229 {
4237 }
4238 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4239 (const_int 0xffffffff<<shift)) */
4246 {
4252 }
4253 /* (mult:P (reg:P) (const_int scale)) */
4258 {
4262 }
4263 /* (ashift:P (reg:P) (const_int shift)) */
4268 {
4272 }
4273 else
4284 {
4289 }
4292 }
4294 /* Return true if MODE is one of the modes for which we
4295 support LDP/STP operations. */
4297 static bool
4299 {
4304 }
4306 /* Return true if REGNO is a virtual pointer register, or an eliminable
4307 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4308 include stack_pointer or hard_frame_pointer. */
4309 static bool
4311 {
4316 }
4318 /* Return true if X is a valid address for machine mode MODE. If it is,
4319 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4320 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4322 static bool
4326 {
4330 /* On BE, we use load/store pair for all large int mode load/stores.
4331 TI/TFmode may also use a load/store pair. */
4335 || (BYTES_BIG_ENDIAN
4339 !load_store_pair_p
4343 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4344 REG addressing. */
4350 {
4366 {
4372 }
4377 {
4384 /* TImode and TFmode values are allowed in both pairs of X
4385 registers and individual Q registers. The available
4386 address modes are:
4387 X,X: 7-bit signed scaled offset
4388 Q: 9-bit signed offset
4389 We conservatively require an offset representable in either mode.
4390 When performing the check for pairs of X registers i.e. LDP/STP
4391 pass down DImode since that is the natural size of the LDP/STP
4392 instruction memory accesses. */
4398 /* A 7bit offset check because OImode will emit a ldp/stp
4399 instruction (only big endian will get here).
4400 For ldp/stp instructions, the offset is scaled for the size of a
4401 single element of the pair. */
4405 /* Three 9/12 bit offsets checks because CImode will emit three
4406 ldr/str instructions (only big endian will get here). */
4413 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4414 instructions (only big endian will get here). */
4423 else
4426 }
4429 {
4430 /* Look for base + (scaled/extended) index register. */
4433 {
4436 }
4439 {
4442 }
4443 }
4464 {
4465 HOST_WIDE_INT offset;
4469 /* TImode and TFmode values are allowed in both pairs of X
4470 registers and individual Q registers. The available
4471 address modes are:
4472 X,X: 7-bit signed scaled offset
4473 Q: 9-bit signed offset
4474 We conservatively require an offset representable in either mode.
4475 */
4483 else
4485 }
4491 /* load literal: pc-relative constant pool entry. Only supported
4492 for SI mode or larger. */
4496 {
4504 }
4513 {
4518 {
4519 /* The symbol and offset must be aligned to the access size. */
4526 {
4530 }
4536 else
4545 }
4546 }
4551 }
4552 }
4554 bool
4556 {
4557 rtx offset;
4561 }
4563 /* Classify the base of symbolic expression X. */
4565 enum aarch64_symbol_type
4567 {
4568 rtx offset;
4572 }
4575 /* Return TRUE if X is a legitimate address for accessing memory in
4576 mode MODE. */
4577 static bool
4579 {
4583 }
4585 /* Return TRUE if X is a legitimate address for accessing memory in
4586 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4587 pair operation. */
4588 bool
4591 {
4595 }
4597 /* Split an out-of-range address displacement into a base and offset.
4598 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4599 to increase opportunities for sharing the base address of different sizes.
4600 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4601 static bool
4603 {
4614 }
4616 /* Return TRUE if rtx X is immediate constant 0.0 */
4617 bool
4619 {
4626 }
4628 /* Return the fixed registers used for condition codes. */
4630 static bool
4632 {
4636 }
4638 /* Emit call insn with PAT and do aarch64-specific handling. */
4640 void
4642 {
4648 }
4650 machine_mode
4652 {
4653 /* All floating point compares return CCFP if it is an equality
4654 comparison, and CCFPE otherwise. */
4656 {
4658 {
4679 }
4680 }
4682 /* Equality comparisons of short modes against zero can be performed
4683 using the TST instruction with the appropriate bitmask. */
4689 /* Similarly, comparisons of zero_extends from shorter modes can
4690 be performed using an ANDS with an immediate mask. */
4706 /* A compare with a shifted operand. Because of canonicalization,
4707 the comparison will have to be swapped when we emit the assembly
4708 code. */
4716 /* Similarly for a negated operand, but we can only do this for
4717 equalities. */
4724 /* A test for unsigned overflow. */
4731 /* For everything else, return CCmode. */
4733 }
4735 static int
4738 int
4740 {
4747 }
4749 static int
4751 {
4753 {
4757 {
4771 }
4776 {
4788 }
4793 {
4805 }
4810 {
4816 }
4821 {
4825 }
4830 {
4834 }
4839 }
4842 }
4844 bool
4846 HOST_WIDE_INT minval,
4847 HOST_WIDE_INT maxval)
4848 {
4849 HOST_WIDE_INT firstval;
4866 }
4868 bool
4870 {
4872 }
4875 /* N Z C V. */
4876 #define AARCH64_CC_V 1
4877 #define AARCH64_CC_C (1 << 1)
4878 #define AARCH64_CC_Z (1 << 2)
4879 #define AARCH64_CC_N (1 << 3)
4881 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4883 {
4900 };
4902 static void
4904 {
4906 {
4907 /* An integer or symbol address without a preceding # sign. */
4910 {
4922 {
4925 }
4926 /* Fall through. */
4930 }
4934 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4935 {
4940 {
4943 }
4946 {
4959 }
4960 }
4964 {
4967 /* Print N such that 2^N == X. */
4969 {
4972 }
4975 }
4979 /* Print the number of non-zero bits in X (a const_int). */
4981 {
4984 }
4990 /* Print the higher numbered register of a pair (TImode) of regs. */
4992 {
4995 }
5002 {
5004 /* Print a condition (eq, ne, etc) or its inverse. */
5006 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5008 {
5012 }
5015 {
5018 }
5025 }
5033 /* Print a scalar FP/SIMD register name. */
5035 {
5036 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5038 }
5046 /* Print the first FP/SIMD register name in a list. */
5048 {
5049 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5051 }
5056 /* Print a scalar FP/SIMD register name + 1. */
5058 {
5059 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5061 }
5066 /* Print bottom 16 bits of integer constant in hex. */
5068 {
5071 }
5077 /* Print a general register name or the zero register (32-bit or
5078 64-bit). */
5081 {
5084 }
5087 {
5090 }
5093 {
5096 }
5098 /* Fall through */
5101 /* Print a normal operand, if it's a general register, then we
5102 assume DImode. */
5104 {
5107 }
5110 {
5131 {
5134 HOST_WIDE_INT_MIN,
5135 HOST_WIDE_INT_MAX));
5137 }
5139 {
5141 }
5142 else
5147 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5148 be getting CONST_DOUBLEs holding integers. */
5151 {
5154 }
5156 {
5157 #define buf_size 20
5165 #undef buf_size
5166 }
5172 }
5180 {
5207 }
5213 {
5248 }
5255 {
5261 }
5266 {
5267 HOST_WIDE_INT cond_code;
5268 /* Print nzcv. */
5271 {
5274 }
5279 }
5285 }
5286 }
5288 static void
5290 {
5295 {
5299 else
5308 else
5317 else
5326 else
5333 {
5360 }
5371 }
5374 }
5376 bool
5378 {
5385 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5386 referencing instruction, but they are constant offsets, not
5387 symbols. */
5393 {
5395 {
5401 }
5404 }
5407 }
5409 /* Implement REGNO_REG_CLASS. */
5411 enum reg_class
5413 {
5428 }
5430 static rtx
5432 {
5433 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5434 where mask is selected by alignment and size of the offset.
5435 We try to pick as large a range for the offset as possible to
5436 maximize the chance of a CSE. However, for aligned addresses
5437 we limit the range to 4k so that structures with different sized
5438 elements are likely to use the same base. We need to be careful
5439 not to split a CONST for some forms of address expression, otherwise
5440 it will generate sub-optimal code. */
5443 {
5449 {
5453 /* Force any scaling into a temp for CSE. */
5457 /* Let the pointer register be in op0. */
5461 /* If the pointer is virtual or frame related, then we know that
5462 virtual register instantiation or register elimination is going
5463 to apply a second constant. We want the two constants folded
5464 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5466 {
5470 }
5472 /* Otherwise, in order to encourage CSE (and thence loop strength
5473 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5477 }
5479 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5480 HOST_WIDE_INT base_offset;
5483 /* For offsets aren't a multiple of the access size, the limit is
5484 -256...255. */
5486 {
5489 /* BLKmode typically uses LDP of X-registers. */
5492 }
5493 /* Small negative offsets are supported. */
5498 /* Use 12-bit offset by access size. */
5499 else
5503 {
5507 }
5508 }
5511 }
5513 /* Return the reload icode required for a constant pool in mode. */
5514 static enum insn_code
5516 {
5518 {
5554 }
5557 }
5558 static reg_class_t
5560 reg_class_t rclass,
5561 machine_mode mode,
5563 {
5565 /* If we have to disable direct literal pool loads and stores because the
5566 function is too big, then we need a scratch register. */
5571 {
5574 }
5576 /* Without the TARGET_SIMD instructions we cannot move a Q register
5577 to a Q register directly. We need a scratch. */
5581 {
5587 }
5589 /* A TFmode or TImode memory access should be handled via an FP_REGS
5590 because AArch64 has richer addressing modes for LDR/STR instructions
5591 than LDP/STP instructions. */
5600 }
5602 static bool
5604 {
5605 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5606 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5609 {
5621 }
5622 else
5623 {
5624 /* If we decided that we didn't need a leaf frame pointer but then used
5625 LR in the function, then we'll want a frame pointer after all, so
5626 prevent this elimination to ensure a frame pointer is used. */
5628 && flag_omit_leaf_frame_pointer
5631 }
5634 }
5636 HOST_WIDE_INT
5638 {
5642 {
5649 }
5652 {
5656 }
5659 }
5661 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5662 previous frame. */
5664 rtx
5666 {
5670 }
5673 static void
5675 {
5677 {
5680 }
5681 else
5682 {
5685 }
5690 }
5692 static void
5694 {
5698 /* Don't need to copy the trailing D-words, we fill those in below. */
5710 /* XXX We should really define a "clear_cache" pattern and use
5711 gen_clear_cache(). */
5716 ptr_mode);
5717 }
5719 static unsigned char
5721 {
5723 {
5730 return
5742 }
5744 }
5746 static reg_class_t
5748 {
5753 {
5759 }
5761 /* If it's an integer immediate that MOVI can't handle, then
5762 FP_REGS is not an option, so we return NO_REGS instead. */
5767 /* Register eliminiation can result in a request for
5768 SP+constant->FP_REGS. We cannot support such operations which
5769 use SP as source and an FP_REG as destination, so reject out
5770 right now. */
5772 {
5775 /* Look through a possible SUBREG introduced by ILP32. */
5781 POINTER_REGS));
5783 }
5786 }
5788 void
5790 {
5792 }
5794 static void
5796 {
5799 else
5800 {
5802 /* While priority is known to be in range [0, 65535], so 18 bytes
5803 would be enough, the compiler might not know that. To avoid
5804 -Wformat-truncation false positive, use a larger size. */
5811 }
5812 }
5814 static void
5816 {
5819 else
5820 {
5822 /* While priority is known to be in range [0, 65535], so 18 bytes
5823 would be enough, the compiler might not know that. To avoid
5824 -Wformat-truncation false positive, use a larger size. */
5831 }
5832 }
5836 {
5842 {
5843 {
5846 },
5847 {
5850 },
5851 {
5854 },
5855 /* We assume that DImode is only generated when not optimizing and
5856 that we don't really need 64-bit address offsets. That would
5857 imply an object file with 8GB of code in a single function! */
5858 {
5861 }
5862 };
5870 /* Need to implement table size reduction, by chaning the code below. */
5880 }
5883 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5884 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5885 operator. */
5887 int
5889 {
5891 {
5894 {
5898 }
5899 }
5901 }
5903 /* Constant pools are per function only when PC relative
5904 literal loads are true or we are in the large memory
5905 model. */
5909 {
5912 }
5914 static bool
5916 {
5917 /* Fixme:: In an ideal world this would work similar
5918 to the logic in aarch64_select_rtx_section but this
5919 breaks bootstrap in gcc go. For now we workaround
5920 this by returning false here. */
5922 }
5924 /* Select appropriate section for constants depending
5925 on where we place literal pools. */
5929 rtx x,
5931 {
5936 }
5938 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5939 void
5941 HOST_WIDE_INT offset)
5942 {
5943 /* When using per-function literal pools, we must ensure that any code
5944 section is aligned to the minimal instruction length, lest we get
5945 errors from the assembler re "unaligned instructions". */
5948 }
5950 /* Costs. */
5952 /* Helper function for rtx cost calculation. Strip a shift expression
5953 from X. Returns the inner operand if successful, or the original
5954 expression on failure. */
5955 static rtx
5957 {
5960 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5961 we can convert both to ROR during final output. */
5976 }
5978 /* Helper function for rtx cost calculation. Strip an extend
5979 expression from X. Returns the inner operand if successful, or the
5980 original expression on failure. We deal with a number of possible
5981 canonicalization variations here. */
5982 static rtx
5984 {
5987 /* Zero and sign extraction of a widened value. */
5995 /* It can also be represented (for zero-extend) as an AND with an
5996 immediate. */
6005 /* Now handle extended register, as this may also have an optional
6006 left shift by 1..4. */
6020 }
6022 /* Return true iff CODE is a shift supported in combination
6023 with arithmetic instructions. */
6025 static bool
6027 {
6029 }
6031 /* Helper function for rtx cost calculation. Calculate the cost of
6032 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6033 Return the calculated cost of the expression, recursing manually in to
6034 operands where needed. */
6036 static int
6038 {
6054 /* Integer multiply/fma. */
6056 {
6057 /* The multiply will be canonicalized as a shift, cost it as such. */
6061 {
6065 {
6067 {
6069 /* ARITH + shift-by-register. */
6072 /* ARITH + extended register. We don't have a cost field
6073 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6075 else
6076 /* ARITH + shift-by-immediate. */
6078 }
6079 else
6080 /* LSL (immediate). */
6083 }
6084 /* Strip extends as we will have costed them in the case above. */
6091 }
6093 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6094 compound and let the below cases handle it. After all, MNEG is a
6095 special-case alias of MSUB. */
6097 {
6100 }
6102 /* Integer multiplies or FMAs have zero/sign extending variants. */
6107 {
6112 {
6114 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6116 else
6117 /* MUL/SMULL/UMULL. */
6119 }
6122 }
6124 /* This is either an integer multiply or a MADD. In both cases
6125 we want to recurse and cost the operands. */
6130 {
6132 /* MADD/MSUB. */
6134 else
6135 /* MUL. */
6137 }
6140 }
6141 else
6142 {
6144 {
6145 /* Floating-point FMA/FMUL can also support negations of the
6146 operands, unless the rounding mode is upward or downward in
6147 which case FNMUL is different than FMUL with operand negation. */
6151 {
6156 }
6159 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6161 else
6162 /* FMUL/FNMUL. */
6164 }
6169 }
6170 }
6172 static int
6174 machine_mode mode,
6175 addr_space_t as ATTRIBUTE_UNUSED,
6177 {
6185 {
6187 {
6188 /* This is a CONST or SYMBOL ref which will be split
6189 in a different way depending on the code model in use.
6190 Cost it through the generic infrastructure. */
6192 /* Divide through by the cost of one instruction to
6193 bring it to the same units as the address costs. */
6195 /* The cost is then the cost of preparing the address,
6196 followed by an immediate (possibly 0) offset. */
6198 }
6199 else
6200 {
6201 /* This is most likely a jump table from a case
6202 statement. */
6204 }
6205 }
6208 {
6220 else
6239 }
6243 {
6244 /* For the sake of calculating the cost of the shifted register
6245 component, we can treat same sized modes in the same way. */
6247 {
6260 /* We can't tell, or this is a 128-bit vector. */
6264 }
6265 }
6268 }
6270 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6271 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6272 to be taken. */
6274 int
6276 {
6277 /* When optimizing for speed, use the cost of unpredictable branches. */
6283 else
6285 }
6287 /* Return true if the RTX X in mode MODE is a zero or sign extract
6288 usable in an ADD or SUB (extended register) instruction. */
6289 static bool
6291 {
6292 /* Catch add with a sign extract.
6293 This is add_<optab><mode>_multp2. */
6296 {
6307 op1))
6308 {
6310 }
6311 }
6312 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6313 No shift. */
6319 }
6321 static bool
6323 {
6325 {
6337 }
6338 }
6340 /* Return true iff X is an rtx that will match an extr instruction
6341 i.e. as described in the *extr<mode>5_insn family of patterns.
6342 OP0 and OP1 will be set to the operands of the shifts involved
6343 on success and will be NULL_RTX otherwise. */
6345 static bool
6347 {
6362 {
6363 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6375 {
6379 }
6380 }
6383 }
6385 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6386 storing it in *COST. Result is true if the total cost of the operation
6387 has now been calculated. */
6388 static bool
6390 {
6391 rtx inner;
6392 rtx comparator;
6396 {
6400 }
6401 else
6402 {
6406 }
6409 {
6410 /* Conditional branch. */
6413 else
6414 {
6416 {
6418 {
6419 /* TBZ/TBNZ/CBZ/CBNZ. */
6421 /* TBZ/TBNZ. */
6424 else
6425 /* CBZ/CBNZ. */
6429 }
6430 }
6432 {
6433 /* TBZ/TBNZ. */
6436 }
6437 }
6438 }
6440 {
6441 /* CCMP. */
6443 {
6444 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6448 {
6455 else
6457 }
6459 }
6461 /* It's a conditional operation based on the status flags,
6462 so it must be some flavor of CSEL. */
6464 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6470 {
6471 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6474 }
6479 }
6481 /* We don't know what this is, cost all operands. */
6483 }
6485 /* Check whether X is a bitfield operation of the form shift + extend that
6486 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6487 operand to which the bitfield operation is applied. Otherwise return
6488 NULL_RTX. */
6490 static rtx
6492 {
6506 {
6524 }
6527 }
6529 /* Return true if the mask and a shift amount from an RTX of the form
6530 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6531 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6533 bool
6535 {
6540 }
6542 /* Calculate the cost of calculating X, storing it in *COST. Result
6543 is true if the total cost of the operation has now been calculated. */
6544 static bool
6547 {
6553 /* By default, assume that everything has equivalent cost to the
6554 cheapest instruction. Any additional costs are applied as a delta
6555 above this default. */
6559 {
6561 /* The cost depends entirely on the operands to SET. */
6567 {
6570 {
6584 }
6593 /* Fall through. */
6595 /* The cost is one per vector-register copied. */
6597 {
6601 }
6602 /* const0_rtx is in general free, but we will use an
6603 instruction to set a register to 0. */
6605 {
6606 /* The cost is 1 per register copied. */
6610 }
6611 else
6612 /* Cost is just the cost of the RHS of the set. */
6618 /* Bit-field insertion. Strip any redundant widening of
6619 the RHS to meet the width of the target. */
6630 {
6631 /* MOV immediate is assumed to always be cheap. */
6633 }
6634 else
6635 {
6636 /* BFM. */
6640 }
6645 /* We can't make sense of this, assume default cost. */
6648 }
6652 /* If an instruction can incorporate a constant within the
6653 instruction, the instruction's expression avoids calling
6654 rtx_cost() on the constant. If rtx_cost() is called on a
6655 constant, then it is usually because the constant must be
6656 moved into a register by one or more instructions.
6658 The exception is constant 0, which can be expressed
6659 as XZR/WZR and is therefore free. The exception to this is
6660 if we have (set (reg) (const0_rtx)) in which case we must cost
6661 the move. However, we can catch that when we cost the SET, so
6662 we don't need to consider that here. */
6665 else
6666 {
6667 /* To an approximation, building any other constant is
6668 proportionally expensive to the number of instructions
6669 required to build that constant. This is true whether we
6670 are compiling for SPEED or otherwise. */
6673 }
6678 {
6679 /* mov[df,sf]_aarch64. */
6681 /* FMOV (scalar immediate). */
6684 {
6685 /* This will be a load from memory. */
6688 else
6690 }
6691 else
6692 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6693 or MOV v0.s[0], wzr - neither of which are modeled by the
6694 cost tables. Just use the default cost. */
6695 {
6696 }
6697 }
6703 {
6704 /* For loads we want the base cost of a load, plus an
6705 approximation for the additional cost of the addressing
6706 mode. */
6720 }
6728 {
6730 {
6731 /* FNEG. */
6733 }
6735 }
6738 {
6741 {
6742 /* CSETM. */
6745 }
6747 /* Cost this as SUB wzr, X. */
6751 }
6754 {
6755 /* Support (neg(fma...)) as a single instruction only if
6756 sign of zeros is unimportant. This matches the decision
6757 making in aarch64.md. */
6759 {
6760 /* FNMADD. */
6763 }
6765 {
6766 /* FNMUL. */
6769 }
6771 /* FNEG. */
6774 }
6781 {
6784 else
6786 }
6796 {
6800 }
6803 {
6804 /* TODO: A write to the CC flags possibly costs extra, this
6805 needs encoding in the cost tables. */
6808 /* ANDS. */
6810 {
6813 }
6816 {
6817 /* ADDS (and CMN alias). */
6820 }
6823 {
6824 /* SUBS. */
6827 }
6832 {
6833 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6834 Handle it here directly rather than going to cost_logic
6835 since we know the immediate generated for the TST is valid
6836 so we can avoid creating an intermediate rtx for it only
6837 for costing purposes. */
6844 }
6847 {
6848 /* CMN. */
6855 }
6857 /* CMP.
6859 Compare can freely swap the order of operands, and
6860 canonicalization puts the more complex operation first.
6861 But the integer MINUS logic expects the shift/extend
6862 operation in op1. */
6865 {
6868 }
6870 }
6873 {
6874 /* FCMP. */
6879 {
6881 /* FCMP supports constant 0.0 for no extra cost. */
6883 }
6885 }
6888 {
6889 /* Vector compare. */
6894 {
6895 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6896 cost. */
6898 }
6900 }
6904 {
6908 cost_minus:
6911 /* Detect valid immediates. */
6917 {
6919 /* SUB(S) (immediate). */
6922 }
6924 /* Look for SUB (extended register). */
6926 {
6934 }
6938 /* Cost this as an FMA-alike operation. */
6942 {
6945 speed);
6947 }
6952 {
6954 {
6955 /* Vector SUB. */
6957 }
6959 {
6960 /* SUB(S). */
6962 }
6964 {
6965 /* FSUB. */
6967 }
6968 }
6970 }
6973 {
6974 rtx new_op0;
6979 cost_plus:
6982 {
6983 /* CSINC. */
6987 }
6992 {
6996 /* ADD (immediate). */
6999 }
7003 /* Look for ADD (extended register). */
7005 {
7013 }
7015 /* Strip any extend, leave shifts behind as we will
7016 cost them through mult_cost. */
7021 {
7023 speed);
7025 }
7030 {
7032 {
7033 /* Vector ADD. */
7035 }
7037 {
7038 /* ADD. */
7040 }
7042 {
7043 /* FADD. */
7045 }
7046 }
7048 }
7054 {
7057 else
7059 }
7064 {
7068 {
7071 else
7073 }
7075 }
7078 {
7085 }
7086 /* Fall through. */
7089 cost_logic:
7094 {
7098 }
7106 {
7107 /* This is a UBFM/SBFM. */
7112 }
7115 {
7117 {
7118 /* We have a mask + shift version of a UBFIZ
7119 i.e. the *andim_ashift<mode>_bfiz pattern. */
7123 {
7130 }
7132 {
7133 /* We possibly get the immediate for free, this is not
7134 modelled. */
7140 }
7141 }
7142 else
7143 {
7146 /* Handle ORN, EON, or BIC. */
7152 /* If we had a shift on op0 then this is a logical-shift-
7153 by-register/immediate operation. Otherwise, this is just
7154 a logical operation. */
7156 {
7158 {
7159 /* Shift by immediate. */
7162 else
7164 }
7165 else
7167 }
7169 /* In both cases we want to cost both operands. */
7174 }
7175 }
7183 {
7184 /* Vector NOT. */
7187 }
7189 /* MVN-shifted-reg. */
7191 {
7198 }
7199 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7200 Handle the second form here taking care that 'a' in the above can
7201 be a shift. */
7203 {
7212 {
7215 else
7217 }
7220 }
7221 /* MVN. */
7230 /* If a value is written in SI mode, then zero extended to DI
7231 mode, the operation will in general be free as a write to
7232 a 'w' register implicitly zeroes the upper bits of an 'x'
7233 register. However, if this is
7235 (set (reg) (zero_extend (reg)))
7237 we must cost the explicit register move. */
7241 {
7244 /* If OP_COST is non-zero, then the cost of the zero extend
7245 is effectively the cost of the inner operation. Otherwise
7246 we have a MOV instruction and we take the cost from the MOV
7247 itself. This is true independently of whether we are
7248 optimizing for space or time. */
7253 }
7255 {
7256 /* All loads can zero extend to any size for free. */
7259 }
7263 {
7268 }
7271 {
7273 {
7274 /* UMOV. */
7276 }
7277 else
7278 {
7279 /* We generate an AND instead of UXTB/UXTH. */
7281 }
7282 }
7287 {
7288 /* LDRSH. */
7290 {
7297 }
7299 }
7303 {
7308 }
7311 {
7314 else
7316 }
7324 {
7326 {
7328 {
7329 /* Vector shift (immediate). */
7331 }
7332 else
7333 {
7334 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7335 aliases. */
7337 }
7338 }
7340 /* We can incorporate zero/sign extend for free. */
7347 }
7348 else
7349 {
7351 {
7353 {
7354 /* Vector shift (register). */
7356 }
7357 else
7358 {
7359 /* LSLV. */
7361 }
7362 }
7364 }
7374 {
7375 /* ASR (immediate) and friends. */
7377 {
7380 else
7382 }
7386 }
7387 else
7388 {
7390 /* ASR (register) and friends. */
7392 {
7395 else
7397 }
7399 }
7405 {
7406 /* LDR. */
7409 }
7412 {
7413 /* ADRP, followed by ADD. */
7417 }
7420 {
7421 /* ADR. */
7424 }
7427 {
7428 /* One extra load instruction, after accessing the GOT. */
7432 }
7437 /* ADRP/ADD (immediate). */
7444 /* UBFX/SBFX. */
7446 {
7449 else
7451 }
7453 /* We can trust that the immediates used will be correct (there
7454 are no by-register forms), so we need only cost op0. */
7460 /* aarch64_rtx_mult_cost always handles recursion to its
7461 operands. */
7465 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7466 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7467 an unconditional negate. This case should only ever be reached through
7468 the set_smod_pow2_cheap check in expmed.c. */
7472 {
7473 /* We expand to 4 instructions. Reset the baseline. */
7481 }
7483 /* Fall-through. */
7486 {
7498 }
7505 {
7509 /* There is no integer SQRT, so only DIV and UDIV can get
7510 here. */
7512 else
7514 }
7540 {
7543 else
7545 }
7547 /* FMSUB, FNMADD, and FNMSUB are free. */
7554 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7555 and the by-element operand as operand 0. */
7559 /* Catch vector-by-element operations. The by-element operand can
7560 either be (vec_duplicate (vec_select (x))) or just
7561 (vec_select (x)), depending on whether we are multiplying by
7562 a vector or a scalar.
7564 Canonicalization is not very good in these cases, FMA4 will put the
7565 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7576 /* If the remaining parameters are not registers,
7577 get the cost to put them into registers. */
7591 {
7593 {
7594 /*Vector truncate. */
7596 }
7597 else
7599 }
7604 {
7606 {
7607 /*Vector conversion. */
7609 }
7610 else
7612 }
7618 /* Strip the rounding part. They will all be implemented
7619 by the fcvt* family of instructions anyway. */
7621 {
7630 }
7633 {
7636 else
7638 }
7640 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7641 fixed-point fcvt. */
7646 {
7650 }
7657 {
7658 /* ABS (vector). */
7661 }
7663 {
7666 /* FABD, which is analogous to FADD. */
7668 {
7675 }
7676 /* Simple FABS is analogous to FNEG. */
7679 }
7680 else
7681 {
7682 /* Integer ABS will either be split to
7683 two arithmetic instructions, or will be an ABS
7684 (scalar), which we don't model. */
7688 }
7694 {
7697 else
7698 {
7699 /* FMAXNM/FMINNM/FMAX/FMIN.
7700 TODO: This may not be accurate for all implementations, but
7701 we do not model this in the cost tables. */
7703 }
7704 }
7708 /* The floating point round to integer frint* instructions. */
7710 {
7715 }
7718 {
7723 }
7728 /* Decompose <su>muldi3_highpart. */
7730 mode == DImode
7731 /* (lshiftrt:TI */
7734 /* (mult:TI */
7736 /* (ANY_EXTEND:TI (reg:DI))
7737 (ANY_EXTEND:TI (reg:DI))) */
7744 /* (const_int 64) */
7747 {
7748 /* UMULH/SMULH. */
7756 }
7758 /* Fall through. */
7761 }
7769 }
7771 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7772 calculated for X. This cost is stored in *COST. Returns true
7773 if the total cost of X was calculated. */
7774 static bool
7777 {
7782 {
7787 }
7790 }
7792 static int
7795 {
7801 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7808 /* Moving between GPR and stack cost is the same as GP2GP. */
7813 /* To/From the stack register, we move via the gprs. */
7819 {
7820 /* 128-bit operations on general registers require 2 instructions. */
7828 /* When AdvSIMD instructions are disabled it is not possible to move
7829 a 128-bit value directly between Q registers. This is handled in
7830 secondary reload. A general register is used as a scratch to move
7831 the upper DI value and the lower DI value is moved directly,
7832 hence the cost is the sum of three moves. */
7837 }
7847 }
7849 static int
7851 reg_class_t rclass ATTRIBUTE_UNUSED,
7853 {
7855 }
7857 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7858 to optimize 1.0/sqrt. */
7860 static bool
7862 {
7864 && flag_unsafe_math_optimizations
7868 }
7870 /* Function to decide when to use the approximate reciprocal square root
7871 builtin. */
7873 static tree
7875 {
7881 }
7885 /* Select reciprocal square root initial estimate insn depending on machine
7886 mode. */
7888 static rsqrte_type
7890 {
7892 {
7899 }
7900 }
7904 /* Select reciprocal square root series step insn depending on machine mode. */
7906 static rsqrts_type
7908 {
7910 {
7917 }
7918 }
7920 /* Emit instruction sequence to compute either the approximate square root
7921 or its approximate reciprocal, depending on the flag RECP, and return
7922 whether the sequence was emitted or not. */
7924 bool
7926 {
7932 machine_mode mmsk = mode_for_vector
7936 && (flag_mlow_precision_sqrt
7940 && (flag_mrecip_low_precision_sqrt
7945 || flag_trapping_math
7946 || !flag_unsafe_math_optimizations
7953 /* When calculating the approximate square root, compare the argument with
7954 0.0 and create a mask. */
7958 /* Estimate the approximate reciprocal square root. */
7962 /* Iterate over the series twice for SF and thrice for DF. */
7965 /* Optionally iterate over the series once less for faster performance
7966 while sacrificing the accuracy. */
7969 iterations--;
7971 /* Iterate over the series to calculate the approximate reciprocal square
7972 root. */
7975 {
7983 }
7986 {
7987 /* Qualify the approximate reciprocal square root when the argument is
7988 0.0 by squashing the intermediary result to 0.0. */
7994 /* Calculate the approximate square root. */
7996 }
7998 /* Finalize the approximation. */
8002 }
8006 /* Select reciprocal initial estimate insn depending on machine mode. */
8008 static recpe_type
8010 {
8012 {
8019 }
8020 }
8024 /* Select reciprocal series step insn depending on machine mode. */
8026 static recps_type
8028 {
8030 {
8037 }
8038 }
8040 /* Emit the instruction sequence to compute the approximation for the division
8041 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8043 bool
8045 {
8056 || flag_trapping_math
8057 || !flag_unsafe_math_optimizations
8062 /* Estimate the approximate reciprocal. */
8066 /* Iterate over the series twice for SF and thrice for DF. */
8069 /* Optionally iterate over the series once less for faster performance,
8070 while sacrificing the accuracy. */
8072 iterations--;
8074 /* Iterate over the series to calculate the approximate reciprocal. */
8077 {
8082 }
8085 {
8086 /* As the approximate reciprocal of DEN is already calculated, only
8087 calculate the approximate division when NUM is not 1.0. */
8090 }
8092 /* Finalize the approximation. */
8095 }
8097 /* Return the number of instructions that can be issued per cycle. */
8098 static int
8100 {
8102 }
8104 static int
8106 {
8110 }
8113 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8114 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8115 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8117 static int
8120 {
8122 }
8125 /* Vectorizer cost model target hooks. */
8127 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8128 static int
8130 tree vectype,
8132 {
8141 {
8190 }
8191 }
8193 /* Implement targetm.vectorize.add_stmt_cost. */
8194 static unsigned
8198 {
8203 {
8208 /* Statements in an inner loop relative to the loop being
8209 vectorized are weighted more heavily. The value here is
8210 arbitrary and could potentially be improved with analysis. */
8216 }
8219 }
8223 /* Parse the TO_PARSE string and put the architecture struct that it
8224 selects into RES and the architectural features into ISA_FLAGS.
8225 Return an aarch64_parse_opt_result describing the parse result.
8226 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8228 static enum aarch64_parse_opt_result
8231 {
8243 else
8250 /* Loop through the list of supported ARCHes to find a match. */
8252 {
8254 {
8258 {
8259 /* TO_PARSE string contains at least one extension. */
8260 enum aarch64_parse_opt_result ext_res
8265 }
8266 /* Extension parsing was successful. Confirm the result
8267 arch and ISA flags. */
8271 }
8272 }
8274 /* ARCH name not found in list. */
8276 }
8278 /* Parse the TO_PARSE string and put the result tuning in RES and the
8279 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8280 describing the parse result. If there is an error parsing, RES and
8281 ISA_FLAGS are left unchanged. */
8283 static enum aarch64_parse_opt_result
8286 {
8298 else
8305 /* Loop through the list of supported CPUs to find a match. */
8307 {
8309 {
8314 {
8315 /* TO_PARSE string contains at least one extension. */
8316 enum aarch64_parse_opt_result ext_res
8321 }
8322 /* Extension parsing was successfull. Confirm the result
8323 cpu and ISA flags. */
8327 }
8328 }
8330 /* CPU name not found in list. */
8332 }
8334 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8335 Return an aarch64_parse_opt_result describing the parse result.
8336 If the parsing fails the RES does not change. */
8338 static enum aarch64_parse_opt_result
8340 {
8346 /* Loop through the list of supported CPUs to find a match. */
8348 {
8350 {
8353 }
8354 }
8356 /* CPU name not found in list. */
8358 }
8360 /* Parse TOKEN, which has length LENGTH to see if it is an option
8361 described in FLAG. If it is, return the index bit for that fusion type.
8362 If not, error (printing OPTION_NAME) and return zero. */
8364 static unsigned int
8369 {
8371 {
8375 }
8379 }
8381 /* Parse OPTION which is a comma-separated list of flags to enable.
8382 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8383 default state we inherit from the CPU tuning structures. OPTION_NAME
8384 gives the top-level option we are parsing in the -moverride string,
8385 for use in error messages. */
8387 static unsigned int
8392 {
8399 {
8402 token_length,
8403 flags,
8404 option_name);
8405 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8406 in the token stream, reset the supported operations. So:
8408 adrp+add.cmp+branch.none.adrp+add
8410 would have the result of turning on only adrp+add fusion. */
8416 }
8418 /* We ended with a comma, print something. */
8420 {
8423 }
8425 /* We still have one more token to parse. */
8428 token_length,
8429 flags,
8430 option_name);
8436 }
8438 /* Support for overriding instruction fusion. */
8440 static void
8443 {
8445 aarch64_fusible_pairs,
8448 }
8450 /* Support for overriding other tuning flags. */
8452 static void
8455 {
8456 tune->extra_tuning_flags
8458 aarch64_tuning_flags,
8461 }
8463 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8464 we understand. If it is, extract the option string and handoff to
8465 the appropriate function. */
8467 void
8471 {
8477 {
8480 }
8482 /* Get the length of the option name. */
8484 /* Skip the '=' to get to the option string. */
8485 option_part++;
8488 {
8490 {
8493 }
8494 }
8498 }
8500 /* A checking mechanism for the implementation of the tls size. */
8502 static void
8504 {
8509 {
8511 /* Both the default and maximum TLS size allowed under tiny is 1M which
8512 needs two instructions to address, so we clamp the size to 24. */
8517 /* The maximum TLS size allowed under small is 4G. */
8522 /* The maximum TLS size allowed under large is 16E.
8523 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8529 }
8532 }
8534 /* Parse STRING looking for options in the format:
8535 string :: option:string
8536 option :: name=substring
8537 name :: {a-z}
8538 substring :: defined by option. */
8540 static void
8543 {
8554 {
8556 /* Make this substring look like a string. */
8560 }
8562 /* One last option to parse. */
8565 }
8568 static void
8570 {
8571 /* The logic here is that if we are disabling all frame pointer generation
8572 then we do not need to disable leaf frame pointer generation as a
8573 separate operation. But if we are *only* disabling leaf frame pointer
8574 generation then we set flag_omit_frame_pointer to true, but in
8575 aarch64_frame_pointer_required we return false only for leaf functions.
8577 PR 70044: We have to be careful about being called multiple times for the
8578 same function. Once we have decided to set flag_omit_frame_pointer just
8579 so that we can omit leaf frame pointers, we must then not interpret a
8580 second call as meaning that all frame pointer generation should be
8581 omitted. We do this by setting flag_omit_frame_pointer to a special,
8582 non-zero value. */
8591 /* If not optimizing for size, set the default
8592 alignment to what the target wants. */
8594 {
8601 }
8603 /* We default to no pc-relative literal loads. */
8607 /* If -mpc-relative-literal-loads is set on the command line, this
8608 implies that the user asked for PC relative literal loads. */
8612 /* This is PR70113. When building the Linux kernel with
8613 CONFIG_ARM64_ERRATUM_843419, support for relocations
8614 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8615 removed from the kernel to avoid loading objects with possibly
8616 offending sequences. Without -mpc-relative-literal-loads we would
8617 generate such relocations, preventing the kernel build from
8618 succeeding. */
8623 /* In the tiny memory model it makes no sense to disallow PC relative
8624 literal pool loads. */
8629 /* When enabling the lower precision Newton series for the square root, also
8630 enable it for the reciprocal square root, since the latter is an
8631 intermediary step for the former. */
8634 }
8636 /* 'Unpack' up the internal tuning structs and update the options
8637 in OPTS. The caller must have set up selected_tune and selected_arch
8638 as all the other target-specific codegen decisions are
8639 derived from them. */
8641 void
8643 {
8646 /* Make a copy of the tuning parameters attached to the core, which
8647 we may later overwrite. */
8655 /* This target defaults to strict volatile bitfields. */
8664 {
8676 }
8678 /* We don't mind passing in global_options_set here as we don't use
8679 the *options_set structs anyway. */
8681 queue_depth,
8685 /* Set the L1 cache line size. */
8693 }
8695 /* Print a hint with a suggestion for a core or architecture name that
8696 most closely resembles what the user passed in STR. ARCH is true if
8697 the user is asking for an architecture name. ARCH is false if the user
8698 is asking for a core name. */
8700 static void
8702 {
8713 }
8715 /* Print a hint with a suggestion for a core name that most closely resembles
8716 what the user passed in STR. */
8720 {
8722 }
8724 /* Print a hint with a suggestion for an architecture name that most closely
8725 resembles what the user passed in STR. */
8729 {
8731 }
8733 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8734 specified in STR and throw errors if appropriate. Put the results if
8735 they are valid in RES and ISA_FLAGS. Return whether the option is
8736 valid. */
8738 static bool
8741 {
8742 enum aarch64_parse_opt_result parse_res
8749 {
8762 }
8765 }
8767 /* Validate a command-line -march option. Parse the arch and extensions
8768 (if any) specified in STR and throw errors if appropriate. Put the
8769 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8770 option is valid. */
8772 static bool
8775 {
8776 enum aarch64_parse_opt_result parse_res
8783 {
8796 }
8799 }
8801 /* Validate a command-line -mtune option. Parse the cpu
8802 specified in STR and throw errors if appropriate. Put the
8803 result, if it is valid, in RES. Return whether the option is
8804 valid. */
8806 static bool
8808 {
8809 enum aarch64_parse_opt_result parse_res
8816 {
8826 }
8828 }
8830 /* Return the CPU corresponding to the enum CPU.
8831 If it doesn't specify a cpu, return the default. */
8835 {
8839 /* The & 0x3f is to extract the bottom 6 bits that encode the
8840 default cpu as selected by the --with-cpu GCC configure option
8841 in config.gcc.
8842 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8843 flags mechanism should be reworked to make it more sane. */
8845 }
8847 /* Return the architecture corresponding to the enum ARCH.
8848 If it doesn't specify a valid architecture, return the default. */
8852 {
8859 }
8861 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8862 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8863 tuning structs. In particular it must set selected_tune and
8864 aarch64_isa_flags that define the available ISA features and tuning
8865 decisions. It must also set selected_arch as this will be used to
8866 output the .arch asm tags for each function. */
8868 static void
8870 {
8883 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8884 If either of -march or -mtune is given, they override their
8885 respective component of -mcpu. */
8897 /* If the user did not specify a processor, choose the default
8898 one for them. This will be the CPU set during configuration using
8899 --with-cpu, otherwise it is "generic". */
8901 {
8903 {
8907 }
8908 else
8909 {
8910 /* Get default configure-time CPU. */
8913 }
8917 }
8918 /* If both -mcpu and -march are specified check that they are architecturally
8919 compatible, warn if they're not and prefer the -march ISA flags. */
8921 {
8923 {
8927 }
8932 }
8933 else
8934 {
8935 /* -mcpu but no -march. */
8942 }
8944 /* Set the arch as well as we will need it when outputing
8945 the .arch directive in assembly. */
8947 {
8950 }
8955 #ifndef HAVE_AS_MABI_OPTION
8956 /* The compiler may have been configured with 2.23.* binutils, which does
8957 not have support for ILP32. */
8960 #endif
8965 /* Make sure we properly set up the explicit options. */
8976 /* Save these options as the default ones in case we push and pop them later
8977 while processing functions with potential target attributes. */
8978 target_option_default_node = target_option_current_node
8980 }
8982 /* Implement targetm.override_options_after_change. */
8984 static void
8986 {
8988 }
8992 {
8996 }
8998 void
9000 {
9002 }
9004 /* A checking mechanism for the implementation of the various code models. */
9005 static void
9007 {
9009 {
9011 {
9016 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9018 ? AARCH64_CMODEL_SMALL_PIC
9020 #else
9022 #endif
9030 }
9031 }
9032 else
9034 }
9036 /* Implement TARGET_OPTION_SAVE. */
9038 static void
9040 {
9042 }
9044 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9045 using the information saved in PTR. */
9047 static void
9049 {
9057 }
9059 /* Implement TARGET_OPTION_PRINT. */
9061 static void
9063 {
9074 }
9078 void
9080 {
9082 }
9084 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9085 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9086 make sure optab availability predicates are recomputed when necessary. */
9088 void
9090 {
9095 else
9097 }
9099 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9100 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9101 of the function, if such exists. This function may be called multiple
9102 times on a single function so use aarch64_previous_fndecl to avoid
9103 setting up identical state. */
9105 static void
9107 {
9111 tree old_tree = (aarch64_previous_fndecl
9117 /* If current function has no attributes but the previous one did,
9118 use the default node. */
9122 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9123 the default have been handled by aarch64_save_restore_target_globals from
9124 aarch64_pragma_target_parse. */
9130 /* First set the target options. */
9134 }
9136 /* Enum describing the various ways we can handle attributes.
9137 In many cases we can reuse the generic option handling machinery. */
9139 enum aarch64_attr_opt_type
9140 {
9144 aarch64_attr_custom /* Attribute requires a custom handling function. */
9145 };
9147 /* All the information needed to handle a target attribute.
9148 NAME is the name of the attribute.
9149 ATTR_TYPE specifies the type of behavior of the attribute as described
9150 in the definition of enum aarch64_attr_opt_type.
9151 ALLOW_NEG is true if the attribute supports a "no-" form.
9152 HANDLER is the function that takes the attribute string and whether
9153 it is a pragma or attribute and handles the option. It is needed only
9154 when the ATTR_TYPE is aarch64_attr_custom.
9155 OPT_NUM is the enum specifying the option that the attribute modifies.
9156 This is needed for attributes that mirror the behavior of a command-line
9157 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9158 aarch64_attr_enum. */
9160 struct aarch64_attribute_info
9161 {
9167 };
9169 /* Handle the ARCH_STR argument to the arch= target attribute.
9170 PRAGMA_OR_ATTR is used in potential error messages. */
9172 static bool
9174 {
9176 enum aarch64_parse_opt_result parse_res
9180 {
9185 }
9188 {
9202 }
9205 }
9207 /* Handle the argument CPU_STR to the cpu= target attribute.
9208 PRAGMA_OR_ATTR is used in potential error messages. */
9210 static bool
9212 {
9214 enum aarch64_parse_opt_result parse_res
9218 {
9226 }
9229 {
9243 }
9246 }
9248 /* Handle the argument STR to the tune= target attribute.
9249 PRAGMA_OR_ATTR is used in potential error messages. */
9251 static bool
9253 {
9255 enum aarch64_parse_opt_result parse_res
9259 {
9264 }
9267 {
9274 }
9277 }
9279 /* Parse an architecture extensions target attribute string specified in STR.
9280 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9281 if successful. Update aarch64_isa_flags to reflect the ISA features
9282 modified.
9283 PRAGMA_OR_ATTR is used in potential error messages. */
9285 static bool
9287 {
9291 /* We allow "+nothing" in the beginning to clear out all architectural
9292 features if the user wants to handpick specific features. */
9294 {
9297 }
9302 {
9305 }
9308 {
9321 }
9324 }
9326 /* The target attributes that we support. On top of these we also support just
9327 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9328 handled explicitly in aarch64_process_one_target_attr. */
9331 {
9333 OPT_mgeneral_regs_only },
9335 OPT_mfix_cortex_a53_835769 },
9337 OPT_mfix_cortex_a53_843419 },
9341 OPT_momit_leaf_frame_pointer },
9344 OPT_march_ },
9347 OPT_mtune_ },
9349 OPT_msign_return_address_ },
9351 };
9353 /* Parse ARG_STR which contains the definition of one target attribute.
9354 Show appropriate errors if any or return true if the attribute is valid.
9355 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9356 we're processing a target attribute or pragma. */
9358 static bool
9360 {
9366 {
9369 }
9374 /* Skip leading whitespace. */
9376 str_to_check++;
9378 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9379 It is easier to detect and handle it explicitly here rather than going
9380 through the machinery for the rest of the target attributes in this
9381 function. */
9386 {
9389 }
9392 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9393 and point ARG to "foo". */
9395 {
9397 arg++;
9398 }
9402 {
9403 /* If the names don't match up, or the user has given an argument
9404 to an attribute that doesn't accept one, or didn't give an argument
9405 to an attribute that expects one, fail to match. */
9414 {
9418 }
9420 /* If the name matches but the attribute does not allow "no-" versions
9421 then we can't match. */
9423 {
9427 }
9430 {
9431 /* Has a custom handler registered.
9432 For example, cpu=, arch=, tune=. */
9439 /* Either set or unset a boolean option. */
9441 {
9449 }
9450 /* Set or unset a bit in the target_flags. aarch64_handle_option
9451 should know what mask to apply given the option number. */
9453 {
9455 /* We only need to specify the option number.
9456 aarch64_handle_option will know which mask to apply. */
9462 }
9463 /* Use the option setting machinery to set an option to an enum. */
9465 {
9472 {
9475 global_dc);
9476 }
9477 else
9478 {
9481 }
9483 }
9486 }
9487 }
9489 /* If we reached here we either have found an attribute and validated
9490 it or didn't match any. If we matched an attribute but its arguments
9491 were malformed we will have returned false already. */
9493 }
9495 /* Count how many times the character C appears in
9496 NULL-terminated string STR. */
9498 static unsigned int
9500 {
9503 {
9505 res++;
9507 str++;
9508 }
9511 }
9513 /* Parse the tree in ARGS that contains the target attribute information
9514 and update the global target options space. PRAGMA_OR_ATTR is a string
9515 to be used in error messages, specifying whether this is processing
9516 a target attribute or a target pragma. */
9518 bool
9520 {
9522 {
9523 do
9524 {
9527 {
9530 }
9535 }
9536 /* We expect to find a string to parse. */
9544 {
9547 }
9549 /* Used to catch empty spaces between commas i.e.
9550 attribute ((target ("attr1,,attr2"))). */
9553 /* Handle multiple target attributes separated by ','. */
9558 {
9559 num_attrs++;
9561 {
9564 }
9567 }
9570 {
9574 }
9577 }
9579 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9580 process attribute ((target ("..."))). */
9582 static bool
9584 {
9587 tree old_optimize;
9591 /* If what we're processing is the current pragma string then the
9592 target option node is already stored in target_option_current_node
9593 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9594 having to re-parse the string. This is especially useful to keep
9595 arm_neon.h compile times down since that header contains a lot
9596 of intrinsics enclosed in pragmas. */
9598 {
9601 }
9607 /* If the function changed the optimization levels as well as setting
9608 target options, start with the optimizations specified. */
9613 /* Save the current target options to restore at the end. */
9616 /* If fndecl already has some target attributes applied to it, unpack
9617 them so that we add this attribute on top of them, rather than
9618 overwriting them. */
9620 {
9626 }
9627 else
9634 /* Set up any additional state. */
9636 {
9638 /* Initialize SIMD builtins if we haven't already.
9639 Set current_target_pragma to NULL for the duration so that
9640 the builtin initialization code doesn't try to tag the functions
9641 being built with the attributes specified by any current pragma, thus
9642 going into an infinite recursion. */
9644 {
9649 }
9651 }
9652 else
9658 {
9663 }
9671 }
9673 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9674 tri-bool options (yes, no, don't care) and the default value is
9675 DEF, determine whether to reject inlining. */
9677 static bool
9680 {
9681 /* If the callee doesn't care, always allow inlining. */
9685 /* If the caller doesn't care, always allow inlining. */
9689 /* Otherwise, allow inlining if either the callee and caller values
9690 agree, or if the callee is using the default value. */
9692 }
9694 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9695 to inline CALLEE into CALLER based on target-specific info.
9696 Make sure that the caller and callee have compatible architectural
9697 features. Then go through the other possible target attributes
9698 and see if they can block inlining. Try not to reject always_inline
9699 callees unless they are incompatible architecturally. */
9701 static bool
9703 {
9707 /* If callee has no option attributes, then it is ok to inline. */
9718 /* Callee's ISA flags should be a subset of the caller's. */
9723 /* Allow non-strict aligned functions inlining into strict
9724 aligned ones. */
9734 /* If the architectural features match up and the callee is always_inline
9735 then the other attributes don't matter. */
9747 /* Honour explicit requests to workaround errata. */
9760 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9761 caller and calle and they don't match up, reject inlining. */
9768 /* If the callee has specific tuning overrides, respect them. */
9773 /* If the user specified tuning override strings for the
9774 caller and callee and they don't match up, reject inlining.
9775 We just do a string compare here, we don't analyze the meaning
9776 of the string, as it would be too costly for little gain. */
9784 }
9786 /* Return true if SYMBOL_REF X binds locally. */
9788 static bool
9790 {
9794 }
9796 /* Return true if SYMBOL_REF X is thread local */
9797 static bool
9799 {
9807 }
9809 /* Classify a TLS symbol into one of the TLS kinds. */
9810 enum aarch64_symbol_type
9812 {
9816 {
9823 {
9829 }
9840 else
9849 }
9850 }
9852 /* Return the method that should be used to access SYMBOL_REF or
9853 LABEL_REF X. */
9855 enum aarch64_symbol_type
9857 {
9859 {
9861 {
9876 }
9877 }
9880 {
9885 {
9887 /* When we retrieve symbol + offset address, we have to make sure
9888 the offset does not cause overflow of the final address. But
9889 we have no way of knowing the address of symbol at compile time
9890 so we can't accurately say if the distance between the PC and
9891 symbol + offset is outside the addressible range of +/-1M in the
9892 TINY code model. So we rely on images not being greater than
9893 1M and cap the offset at 1M and anything beyond 1M will have to
9894 be loaded using an alternative mechanism. Furthermore if the
9895 symbol is a weak reference to something that isn't known to
9896 resolve to a symbol in this module, then force to memory. */
9904 /* Same reasoning as the tiny code model, but the offset cap here is
9905 4G. */
9926 /* This is alright even in PIC code as the constant
9927 pool reference is always PC relative and within
9928 the same translation unit. */
9931 else
9936 }
9937 }
9939 /* By default push everything into the constant pool. */
9941 }
9943 bool
9945 {
9947 }
9949 bool
9951 {
9959 }
9961 /* Return true if X holds either a quarter-precision or
9962 floating-point +0.0 constant. */
9963 static bool
9965 {
9972 /* We only handle moving 0.0 to a TFmode register. */
9977 }
9979 static bool
9981 {
9982 /* Do not allow vector struct mode constants. We could support
9983 0 and -1 easily, but they need support in aarch64-simd.md. */
9987 /* This could probably go away because
9988 we now decompose CONST_INTs according to expand_mov_immediate. */
9999 }
10001 rtx
10003 {
10009 /* Can return in any reg. */
10012 }
10014 /* On AAPCS systems, this is the "struct __va_list". */
10017 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10018 Return the type to use as __builtin_va_list.
10020 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10022 struct __va_list
10023 {
10024 void *__stack;
10025 void *__gr_top;
10026 void *__vr_top;
10027 int __gr_offs;
10028 int __vr_offs;
10029 }; */
10031 static tree
10033 {
10034 tree va_list_name;
10037 /* Create the type. */
10039 /* Give it the required name. */
10041 TYPE_DECL,
10043 va_list_type);
10048 /* Create the fields. */
10051 ptr_type_node);
10054 ptr_type_node);
10057 ptr_type_node);
10060 integer_type_node);
10063 integer_type_node);
10065 /* Tell tree-stdarg pass about our internal offset fields.
10066 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10067 purpose to identify whether the code is updating va_list internal
10068 offset fields through irregular way. */
10090 /* Compute its layout. */
10094 }
10096 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10097 static void
10099 {
10103 tree t;
10117 {
10120 }
10129 NULL_TREE);
10131 NULL_TREE);
10133 NULL_TREE);
10135 NULL_TREE);
10137 NULL_TREE);
10139 /* Emit code to initialize STACK, which points to the next varargs stack
10140 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10141 by named arguments. STACK is 8-byte aligned. */
10148 /* Emit code to initialize GRTOP, the top of the GR save area.
10149 virtual_incoming_args_rtx should have been 16 byte aligned. */
10154 /* Emit code to initialize VRTOP, the top of the VR save area.
10155 This address is gr_save_area_bytes below GRTOP, rounded
10156 down to the next 16-byte boundary. */
10166 /* Emit code to initialize GROFF, the offset from GRTOP of the
10167 next GPR argument. */
10172 /* Likewise emit code to initialize VROFF, the offset from FTOP
10173 of the next VR argument. */
10177 }
10179 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10181 static tree
10184 {
10185 tree addr;
10191 machine_mode mode;
10218 type,
10222 {
10223 /* TYPE passed in fp/simd registers. */
10235 {
10238 }
10241 {
10243 }
10244 }
10245 else
10246 {
10247 /* TYPE passed in general registers. */
10260 {
10262 }
10263 }
10265 /* Get a local temporary for the field value. */
10268 /* Emit code to branch if off >= 0. */
10274 {
10275 /* Emit: offs = (offs + 15) & -16. */
10281 }
10282 else
10285 /* Update ap.__[g|v]r_offs */
10290 /* String up. */
10294 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10299 /* String up: make sure the assignment happens before the use. */
10303 /* Prepare the trees handling the argument that is passed on the stack;
10304 the top level node will store in ON_STACK. */
10307 {
10308 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10316 }
10317 else
10319 /* Advance ap.__stack */
10327 /* String up roundup and advance. */
10330 /* String up with arg */
10332 /* Big-endianness related address adjustment. */
10335 {
10339 }
10344 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10354 {
10355 /* type ha; // treat as "struct {ftype field[n];}"
10356 ... [computing offs]
10357 for (i = 0; i <nregs; ++i, offs += 16)
10358 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10359 return ha; */
10363 /* Declare a local variable. */
10367 /* Establish the base type. */
10369 {
10388 {
10392 }
10396 }
10398 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10406 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10408 {
10418 }
10422 }
10432 }
10434 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10436 static void
10440 {
10442 CUMULATIVE_ARGS local_cum;
10446 /* The caller has advanced CUM up to, but not beyond, the last named
10447 argument. Advance a local copy of CUM past the last "real" named
10448 argument, to find out how many registers are left over. */
10452 /* Found out how many registers we need to save.
10453 Honor tree-stdvar analysis results. */
10462 {
10465 }
10468 {
10470 {
10473 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10481 }
10483 {
10484 /* We can't use move_block_from_reg, because it will use
10485 the wrong mode, storing D regs only. */
10489 /* Set OFF to the offset from virtual_incoming_args_rtx of
10490 the first vector register. The VR save area lies below
10491 the GR one, and is aligned to 16 bytes. */
10498 {
10506 }
10507 }
10508 }
10510 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10511 any complication of having crtl->args.pretend_args_size changed. */
10516 }
10518 static void
10520 {
10523 {
10525 {
10528 }
10529 }
10530 }
10532 /* Walk down the type tree of TYPE counting consecutive base elements.
10533 If *MODEP is VOIDmode, then set it to the first valid floating point
10534 type. If a non-floating point type is found, or if a floating point
10535 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10536 otherwise return the count in the sub-tree. */
10537 static int
10539 {
10540 machine_mode mode;
10541 HOST_WIDE_INT size;
10544 {
10574 /* Use V2SImode and V4SImode as representatives of all 64-bit
10575 and 128-bit vector types. */
10578 {
10587 }
10592 /* Vector modes are considered to be opaque: two vectors are
10593 equivalent for the purposes of being homogeneous aggregates
10594 if they are the same size. */
10601 {
10605 /* Can't handle incomplete types nor sizes that are not
10606 fixed. */
10613 || !index
10624 /* There must be no padding. */
10629 }
10632 {
10635 tree field;
10637 /* Can't handle incomplete types nor sizes that are not
10638 fixed. */
10644 {
10652 }
10654 /* There must be no padding. */
10659 }
10663 {
10664 /* These aren't very interesting except in a degenerate case. */
10667 tree field;
10669 /* Can't handle incomplete types nor sizes that are not
10670 fixed. */
10676 {
10684 }
10686 /* There must be no padding. */
10691 }
10695 }
10698 }
10700 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10701 type as described in AAPCS64 \S 4.1.2.
10703 See the comment above aarch64_composite_type_p for the notes on MODE. */
10705 static bool
10707 machine_mode mode)
10708 {
10718 }
10720 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10721 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10722 array types. The C99 floating-point complex types are also considered
10723 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10724 types, which are GCC extensions and out of the scope of AAPCS64, are
10725 treated as composite types here as well.
10727 Note that MODE itself is not sufficient in determining whether a type
10728 is such a composite type or not. This is because
10729 stor-layout.c:compute_record_mode may have already changed the MODE
10730 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10731 structure with only one field may have its MODE set to the mode of the
10732 field. Also an integer mode whose size matches the size of the
10733 RECORD_TYPE type may be used to substitute the original mode
10734 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10735 solely relied on. */
10737 static bool
10739 machine_mode mode)
10740 {
10753 }
10755 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10756 shall be passed or returned in simd/fp register(s) (providing these
10757 parameter passing registers are available).
10759 Upon successful return, *COUNT returns the number of needed registers,
10760 *BASE_MODE returns the mode of the individual register and when IS_HAF
10761 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10762 floating-point aggregate or a homogeneous short-vector aggregate. */
10764 static bool
10766 const_tree type,
10770 {
10778 {
10781 }
10783 {
10787 }
10789 {
10793 {
10796 }
10797 else
10799 }
10800 else
10805 }
10807 /* Implement TARGET_STRUCT_VALUE_RTX. */
10809 static rtx
10812 {
10814 }
10816 /* Implements target hook vector_mode_supported_p. */
10817 static bool
10819 {
10831 }
10833 /* Return appropriate SIMD container
10834 for MODE within a vector of WIDTH bits. */
10835 static machine_mode
10837 {
10840 {
10843 {
10858 }
10859 else
10861 {
10872 }
10873 }
10875 }
10877 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10878 static machine_mode
10880 {
10882 }
10884 /* Return the bitmask of possible vector sizes for the vectorizer
10885 to iterate over. */
10886 static unsigned int
10888 {
10890 }
10892 /* Implement TARGET_MANGLE_TYPE. */
10896 {
10897 /* The AArch64 ABI documents say that "__va_list" has to be
10898 managled as if it is in the "std" namespace. */
10902 /* Half-precision float. */
10906 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10907 builtin types. */
10911 /* Use the default mangling. */
10913 }
10915 /* Find the first rtx_insn before insn that will generate an assembly
10916 instruction. */
10920 {
10924 do
10925 {
10927 }
10931 }
10933 static bool
10935 {
10937 /* A number of these may be AArch32 only. */
10942 };
10945 {
10948 }
10951 }
10953 /* Check if there is a register dependency between a load and the insn
10954 for which we hold recog_data. */
10956 static bool
10958 {
10959 rtx load_reg;
10969 {
10975 }
10977 }
10980 /* When working around the Cortex-A53 erratum 835769,
10981 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10982 instruction and has a preceding memory instruction such that a NOP
10983 should be inserted between them. */
10985 bool
10987 {
10990 rtx body;
11003 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11004 Restore recog state to INSN to avoid state corruption. */
11012 /* If the previous insn is a memory op and there is no dependency between
11013 it and the DImode madd, emit a NOP between them. If body is NULL then we
11014 have a complex memory operation, probably a load/store pair.
11015 Be conservative for now and emit a NOP. */
11022 }
11025 /* Implement FINAL_PRESCAN_INSN. */
11027 void
11029 {
11032 }
11035 /* Return the equivalent letter for size. */
11036 static char
11038 {
11040 {
11046 }
11047 }
11049 /* Return true iff x is a uniform vector of floating-point
11050 constants, and the constant can be represented in
11051 quarter-precision form. Note, as aarch64_float_const_representable
11052 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11053 static bool
11055 {
11056 rtx elt;
11060 }
11062 /* Return true for valid and false for invalid. */
11063 bool
11066 {
11067 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11068 matches = 1; \
11069 for (i = 0; i < idx; i += (STRIDE)) \
11070 if (!(TEST)) \
11071 matches = 0; \
11072 if (matches) \
11073 { \
11074 immtype = (CLASS); \
11075 elsize = (ELSIZE); \
11076 eshift = (SHIFT); \
11077 emvn = (NEG); \
11078 break; \
11079 }
11089 {
11095 {
11100 }
11103 }
11105 /* Splat vector constant out into a byte vector. */
11107 {
11108 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11109 it must be laid out in the vector register in reverse order. */
11117 {
11120 }
11122 }
11124 /* Sanity check. */
11127 do
11128 {
11177 }
11184 {
11194 /* Un-invert bytes of recognized vector, if necessary. */
11200 {
11201 /* FIXME: Broken on 32-bit H_W_I hosts. */
11210 }
11211 else
11212 {
11216 /* Construct 'abcdefgh' because the assembler cannot handle
11217 generic constants. */
11222 }
11223 }
11226 #undef CHECK
11227 }
11229 /* Check of immediate shift constants are within range. */
11230 bool
11232 {
11236 else
11238 }
11240 /* Return true if X is a uniform vector where all elements
11241 are either the floating-point constant 0.0 or the
11242 integer constant 0. */
11243 bool
11245 {
11247 }
11250 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11251 operation of width WIDTH at bit position POS. */
11253 rtx
11255 {
11259 unsigned HOST_WIDE_INT mask
11262 }
11264 bool
11266 {
11271 {
11276 }
11279 }
11281 bool
11283 {
11296 }
11298 /* Return a const_int vector of VAL. */
11299 rtx
11301 {
11312 }
11314 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11316 bool
11318 {
11319 machine_mode vmode;
11325 }
11327 /* Construct and return a PARALLEL RTX vector with elements numbering the
11328 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11329 the vector - from the perspective of the architecture. This does not
11330 line up with GCC's perspective on lane numbers, so we end up with
11331 different masks depending on our target endian-ness. The diagram
11332 below may help. We must draw the distinction when building masks
11333 which select one half of the vector. An instruction selecting
11334 architectural low-lanes for a big-endian target, must be described using
11335 a mask selecting GCC high-lanes.
11337 Big-Endian Little-Endian
11339 GCC 0 1 2 3 3 2 1 0
11340 | x | x | x | x | | x | x | x | x |
11341 Architecture 3 2 1 0 3 2 1 0
11343 Low Mask: { 2, 3 } { 0, 1 }
11344 High Mask: { 0, 1 } { 2, 3 }
11345 */
11347 rtx
11349 {
11355 rtx t1;
11360 else
11368 }
11370 /* Check OP for validity as a PARALLEL RTX vector with elements
11371 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11372 from the perspective of the architecture. See the diagram above
11373 aarch64_simd_vect_par_cnst_half for more details. */
11375 bool
11378 {
11391 {
11398 }
11400 }
11402 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11403 HIGH (exclusive). */
11404 void
11406 const_tree exp)
11407 {
11408 HOST_WIDE_INT lane;
11413 {
11416 else
11418 }
11419 }
11421 /* Return TRUE if OP is a valid vector addressing mode. */
11422 bool
11424 {
11427 }
11429 /* Emit a register copy from operand to operand, taking care not to
11430 early-clobber source registers in the process.
11432 COUNT is the number of components into which the copy needs to be
11433 decomposed. */
11434 void
11437 {
11447 else
11451 }
11453 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11454 one of VSTRUCT modes: OI, CI, or XI. */
11455 int
11457 {
11459 }
11461 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11462 alignment of a vector to 128 bits. */
11463 static HOST_WIDE_INT
11465 {
11468 }
11470 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11471 static bool
11473 {
11477 /* We guarantee alignment for vectors up to 128-bits. */
11482 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11484 }
11486 /* Return true if the vector misalignment factor is supported by the
11487 target. */
11488 static bool
11492 {
11494 {
11495 /* Return if movmisalign pattern is not supported for this mode. */
11500 {
11501 /* Misalignment factor is unknown at compile time but we know
11502 it's word aligned. */
11504 {
11509 }
11511 }
11512 }
11514 is_packed);
11515 }
11517 /* If VALS is a vector constant that can be loaded into a register
11518 using DUP, generate instructions to do so and return an RTX to
11519 assign to the register. Otherwise return NULL_RTX. */
11520 static rtx
11522 {
11525 rtx x;
11530 /* We can load this constant by using DUP and a constant in a
11531 single ARM register. This will be cheaper than a vector
11532 load. */
11535 }
11538 /* Generate code to load VALS, which is a PARALLEL containing only
11539 constants (for vec_init) or CONST_VECTOR, efficiently into a
11540 register. Returns an RTX to copy into the register, or NULL_RTX
11541 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11542 static rtx
11544 {
11546 rtx const_dup;
11555 {
11556 /* A CONST_VECTOR must contain only CONST_INTs and
11557 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11558 Only store valid constants in a CONST_VECTOR. */
11560 {
11563 n_const++;
11564 }
11567 }
11568 else
11573 /* Load using MOVI/MVNI. */
11576 /* Loaded using DUP. */
11579 /* Load from constant pool. We can not take advantage of single-cycle
11580 LD1 because we need a PC-relative addressing mode. */
11582 else
11583 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11584 We can not construct an initializer. */
11586 }
11588 /* Expand a vector initialisation sequence, such that TARGET is
11589 initialised to contain VALS. */
11591 void
11593 {
11596 /* The number of vector elements. */
11598 /* The number of vector elements which are not constant. */
11601 /* The first element of vals. */
11605 /* Count the number of variable elements to initialise. */
11607 {
11611 else
11615 }
11617 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11618 how best to handle this. */
11620 {
11623 {
11626 }
11627 }
11629 /* Splat a single non-constant element if we can. */
11631 {
11635 }
11637 /* Initialise a vector which is part-variable. We want to first try
11638 to build those lanes which are constant in the most efficient way we
11639 can. */
11641 {
11644 /* Load constant part of vector. We really don't care what goes into the
11645 parts we will overwrite, but we're more likely to be able to load the
11646 constant efficiently if it has fewer, larger, repeating parts
11647 (see aarch64_simd_valid_immediate). */
11649 {
11655 {
11656 /* Look in the copied vector, as more elements are const. */
11659 {
11662 }
11663 }
11665 }
11667 }
11669 /* Insert the variable lanes directly. */
11675 {
11681 }
11682 }
11684 static unsigned HOST_WIDE_INT
11686 {
11687 return
11688 (!SHIFT_COUNT_TRUNCATED
11691 }
11693 /* Select a format to encode pointers in exception handling data. */
11694 int
11696 {
11699 {
11705 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11706 for everything. */
11710 /* No assumptions here. 8-byte relocs required. */
11713 }
11715 }
11717 /* The last .arch and .tune assembly strings that we printed. */
11721 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11722 by the function fndecl. */
11724 void
11726 tree fndecl)
11727 {
11733 else
11744 /* Only update the assembler .arch string if it is distinct from the last
11745 such string we printed. */
11748 {
11751 }
11753 /* Print the cpu name we're tuning for in the comments, might be
11754 useful to readers of the generated asm. Do it only when it changes
11755 from function to function and verbose assembly is requested. */
11760 {
11764 }
11766 /* Don't forget the type directive for ELF. */
11769 }
11771 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11773 static void
11775 {
11792 }
11794 /* Emit load exclusive. */
11796 static void
11799 {
11803 {
11810 }
11813 }
11815 /* Emit store exclusive. */
11817 static void
11820 {
11824 {
11831 }
11834 }
11836 /* Mark the previous jump instruction as unlikely. */
11838 static void
11840 {
11845 }
11847 /* Expand a compare and swap pattern. */
11849 void
11851 {
11856 gen_cas_fn gen;
11858 {
11859 gen_aarch64_compare_and_swapqi,
11860 gen_aarch64_compare_and_swaphi,
11861 gen_aarch64_compare_and_swapsi,
11862 gen_aarch64_compare_and_swapdi
11863 };
11865 {
11866 gen_aarch64_compare_and_swapqi_lse,
11867 gen_aarch64_compare_and_swaphi_lse,
11868 gen_aarch64_compare_and_swapsi_lse,
11869 gen_aarch64_compare_and_swapdi_lse
11870 };
11883 /* Normally the succ memory model must be stronger than fail, but in the
11884 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11885 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11892 {
11895 /* For short modes, we're going to perform the comparison in SImode,
11896 so do the zero-extension now. */
11900 /* Fall through. */
11904 /* Force the value into a register if needed. */
11911 }
11914 {
11921 }
11924 else
11935 }
11937 /* Test whether the target supports using a atomic load-operate instruction.
11938 CODE is the operation and AFTER is TRUE if the data in memory after the
11939 operation should be returned and FALSE if the data before the operation
11940 should be returned. Returns FALSE if the operation isn't supported by the
11941 architecture. */
11943 bool
11945 {
11950 {
11960 }
11961 }
11963 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11964 sequence implementing an atomic operation. */
11966 static void
11968 {
11975 {
11977 }
11978 }
11980 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11981 for the data in memory. EXPECTED is the value expected to be in memory.
11982 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11983 is the memory ordering to use. */
11985 void
11988 rtx model)
11989 {
11991 machine_mode mode;
11996 {
12003 }
12005 /* Move the expected value into the CAS destination register. */
12008 /* Emit the CAS. */
12011 /* Compare the expected value with the value loaded by the CAS, to establish
12012 whether the swap was made. */
12014 }
12016 /* Split a compare and swap pattern. */
12018 void
12020 {
12022 machine_mode mode;
12027 rtx model_rtx;
12041 {
12044 }
12047 /* The initial load can be relaxed for a __sync operation since a final
12048 barrier will be emitted to stop code hoisting. */
12052 else
12064 {
12069 }
12070 else
12071 {
12075 }
12079 /* Emit any final barrier needed for a __sync operation. */
12082 }
12084 /* Emit a BIC instruction. */
12086 static void
12088 {
12093 {
12098 }
12101 }
12103 /* Emit an atomic swap. */
12105 static void
12108 {
12112 {
12119 }
12122 }
12124 /* Operations supported by aarch64_emit_atomic_load_op. */
12126 enum aarch64_atomic_load_op_code
12127 {
12131 AARCH64_LDOP_BIC /* A & ~B */
12132 };
12134 /* Emit an atomic load-operate. */
12136 static void
12140 {
12143 {
12144 gen_aarch64_atomic_loadaddqi,
12145 gen_aarch64_atomic_loadaddhi,
12146 gen_aarch64_atomic_loadaddsi,
12147 gen_aarch64_atomic_loadadddi
12148 };
12150 {
12151 gen_aarch64_atomic_loadeorqi,
12152 gen_aarch64_atomic_loadeorhi,
12153 gen_aarch64_atomic_loadeorsi,
12154 gen_aarch64_atomic_loadeordi
12155 };
12157 {
12158 gen_aarch64_atomic_loadsetqi,
12159 gen_aarch64_atomic_loadsethi,
12160 gen_aarch64_atomic_loadsetsi,
12161 gen_aarch64_atomic_loadsetdi
12162 };
12164 {
12165 gen_aarch64_atomic_loadclrqi,
12166 gen_aarch64_atomic_loadclrhi,
12167 gen_aarch64_atomic_loadclrsi,
12168 gen_aarch64_atomic_loadclrdi
12169 };
12170 aarch64_atomic_load_op_fn gen;
12174 {
12181 }
12184 {
12191 }
12194 }
12196 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12197 location to store the data read from memory. OUT_RESULT is the location to
12198 store the result of the operation. MEM is the memory location to read and
12199 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12200 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12201 be NULL. */
12203 void
12206 {
12210 aarch64_atomic_load_op_code ldop_code;
12211 rtx src;
12212 rtx x;
12220 /* Make sure the value is in a register, putting it into a destination
12221 register if it needs to be manipulated. */
12224 {
12227 }
12228 else
12232 /* Preprocess the data for the operation as necessary. If the operation is
12233 a SET then emit a swap instruction and finish. */
12235 {
12241 /* Negate the value and treat it as a PLUS. */
12242 {
12243 rtx neg_src;
12245 /* Resize the value if necessary. */
12254 }
12255 /* Fall-through. */
12269 {
12270 rtx not_src;
12272 /* Resize the value if necessary. */
12281 }
12286 /* The operation can't be done with atomic instructions. */
12288 }
12292 /* If necessary, calculate the data in memory after the update by redoing the
12293 operation from values in registers. */
12298 {
12302 }
12307 {
12323 }
12328 }
12330 /* Split an atomic operation. */
12332 void
12335 {
12341 rtx x;
12343 /* Split the atomic operation into a sequence. */
12351 else
12355 /* The initial load can be relaxed for a __sync operation since a final
12356 barrier will be emitted to stop code hoisting. */
12360 else
12364 {
12378 {
12381 }
12382 /* Fall through. */
12388 }
12398 /* Emit any final barrier needed for a __sync operation. */
12401 }
12403 static void
12405 {
12406 /* Half-precision float operations. The compiler handles all operations
12407 with NULL libfuncs by converting to SFmode. */
12409 /* Conversions. */
12413 /* Arithmetic. */
12420 /* Comparisons. */
12428 }
12430 /* Target hook for c_mode_for_suffix. */
12431 static machine_mode
12433 {
12438 }
12440 /* We can only represent floating point constants which will fit in
12441 "quarter-precision" values. These values are characterised by
12442 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12443 by:
12445 (-1)^s * (n/16) * 2^r
12447 Where:
12448 's' is the sign bit.
12449 'n' is an integer in the range 16 <= n <= 31.
12450 'r' is an integer in the range -3 <= r <= 4. */
12452 /* Return true iff X can be represented by a quarter-precision
12453 floating point immediate operand X. Note, we cannot represent 0.0. */
12454 bool
12456 {
12457 /* This represents our current view of how many bits
12458 make up the mantissa. */
12468 /* We don't support HFmode constants yet. */
12474 /* We cannot represent infinities, NaNs or +/-zero. We won't
12475 know if we have +zero until we analyse the mantissa, but we
12476 can reject the other invalid values. */
12481 /* Extract exponent. */
12485 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12486 highest (sign) bit, with a fixed binary point at bit point_pos.
12487 m1 holds the low part of the mantissa, m2 the high part.
12488 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12489 bits for the mantissa, this can fail (low bits will be lost). */
12493 /* If the low part of the mantissa has bits set we cannot represent
12494 the value. */
12497 /* We have rejected the lower HOST_WIDE_INT, so update our
12498 understanding of how many bits lie in the mantissa and
12499 look only at the high HOST_WIDE_INT. */
12503 /* We can only represent values with a mantissa of the form 1.xxxx. */
12508 /* Having filtered unrepresentable values, we may now remove all
12509 but the highest 5 bits. */
12512 /* We cannot represent the value 0.0, so reject it. This is handled
12513 elsewhere. */
12517 /* Then, as bit 4 is always set, we can mask it off, leaving
12518 the mantissa in the range [0, 15]. */
12522 /* GCC internally does not use IEEE754-like encoding (where normalized
12523 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12524 Our mantissa values are shifted 4 places to the left relative to
12525 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12526 by 5 places to correct for GCC's representation. */
12530 }
12534 machine_mode mode,
12536 {
12546 /* This will return true to show const_vector is legal for use as either
12547 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12548 also update INFO to show how the immediate should be generated. */
12557 {
12559 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12560 move immediate path. */
12563 else
12564 {
12573 else
12577 }
12578 }
12591 else
12595 }
12599 machine_mode mode)
12600 {
12601 machine_mode vmode;
12607 }
12609 /* Split operands into moves from op[1] + op[2] into op[0]. */
12611 void
12613 {
12624 {
12625 /* No-op move. Can't split to nothing; emit something. */
12628 }
12630 /* Preserve register attributes for variable tracking. */
12635 /* Special case of reversed high/low parts. */
12638 {
12642 }
12644 {
12645 /* Try to avoid unnecessary moves if part of the result
12646 is in the right place already. */
12651 }
12652 else
12653 {
12658 }
12659 }
12661 /* vec_perm support. */
12663 #define MAX_VECT_LEN 16
12665 struct expand_vec_perm_d
12666 {
12669 machine_mode vmode;
12673 };
12675 /* Generate a variable permutation. */
12677 static void
12679 {
12690 {
12692 {
12693 /* Expand the argument to a V16QI mode by duplicating it. */
12697 }
12698 else
12699 {
12701 }
12702 }
12703 else
12704 {
12705 rtx pair;
12708 {
12712 }
12713 else
12714 {
12718 }
12719 }
12720 }
12722 void
12724 {
12728 rtx mask;
12730 /* The TBL instruction does not use a modulo index, so we must take care
12731 of that ourselves. */
12736 /* For big-endian, we also need to reverse the index within the vector
12737 (but not which vector). */
12739 {
12740 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12745 }
12747 }
12749 /* Recognize patterns suitable for the TRN instructions. */
12750 static bool
12752 {
12761 /* Note that these are little-endian tests.
12762 We correct for big-endian later. */
12767 else
12772 {
12777 }
12779 /* Success! */
12786 {
12789 }
12793 {
12795 {
12810 }
12811 }
12812 else
12813 {
12815 {
12830 }
12831 }
12835 }
12837 /* Recognize patterns suitable for the UZP instructions. */
12838 static bool
12840 {
12849 /* Note that these are little-endian tests.
12850 We correct for big-endian later. */
12855 else
12860 {
12864 }
12866 /* Success! */
12873 {
12876 }
12880 {
12882 {
12897 }
12898 }
12899 else
12900 {
12902 {
12917 }
12918 }
12922 }
12924 /* Recognize patterns suitable for the ZIP instructions. */
12925 static bool
12927 {
12936 /* Note that these are little-endian tests.
12937 We correct for big-endian later. */
12940 /* Do Nothing. */
12941 ;
12944 else
12949 {
12956 }
12958 /* Success! */
12965 {
12968 }
12972 {
12974 {
12989 }
12990 }
12991 else
12992 {
12994 {
13009 }
13010 }
13014 }
13016 /* Recognize patterns for the EXT insn. */
13018 static bool
13020 {
13023 rtx offset;
13027 /* Check if the extracted indices are increasing by one. */
13029 {
13032 {
13033 /* We'll pass the same vector in twice, so allow indices to wrap. */
13035 }
13038 }
13041 {
13056 }
13058 /* Success! */
13062 /* The case where (location == 0) is a no-op for both big- and little-endian,
13063 and is removed by the mid-end at optimization levels -O1 and higher. */
13066 {
13067 /* After setup, we want the high elements of the first vector (stored
13068 at the LSB end of the register), and the low elements of the second
13069 vector (stored at the MSB end of the register). So swap. */
13071 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13073 }
13078 }
13080 /* Recognize patterns for the REV insns. */
13082 static bool
13084 {
13093 {
13096 {
13101 }
13105 {
13112 }
13116 {
13129 }
13133 }
13137 {
13138 /* This is guaranteed to be true as the value of diff
13139 is 7, 3, 1 and we should have enough elements in the
13140 queue to generate this. Getting a vector mask with a
13141 value of diff other than these values implies that
13142 something is wrong by the time we get here. */
13146 }
13148 /* Success! */
13154 }
13156 static bool
13158 {
13161 rtx in0;
13164 rtx lane;
13168 {
13171 }
13173 /* The generic preparation in aarch64_expand_vec_perm_const_1
13174 swaps the operand order and the permute indices if it finds
13175 d->perm[0] to be in the second operand. Thus, we can always
13176 use d->op0 and need not do any extra arithmetic to get the
13177 correct lane number. */
13182 {
13197 }
13201 }
13203 static bool
13205 {
13213 /* Generic code will try constant permutation twice. Once with the
13214 original mode and again with the elements lowered to QImode.
13215 So wait and don't do the selector expansion ourselves. */
13220 {
13223 /* If big-endian and two vectors we end up with a weird mixed-endian
13224 mode on NEON. Reverse the index within each word but not the word
13225 itself. */
13228 }
13234 }
13236 static bool
13238 {
13239 /* The pattern matching functions above are written to look for a small
13240 number to begin the sequence (0, 1, N/2). If we begin with an index
13241 from the second operand, we can swap the operands. */
13243 {
13251 }
13254 {
13268 }
13270 }
13272 /* Expand a vec_perm_const pattern. */
13274 bool
13276 {
13290 {
13295 }
13298 {
13307 /* The elements of PERM do not suggest that only the first operand
13308 is used, but both operands are identical. Allow easier matching
13309 of the permutation by folding the permutation into the single
13310 input vector. */
13311 /* Fall Through. */
13323 }
13326 }
13328 static bool
13331 {
13341 /* Calculate whether all elements are in one vector. */
13343 {
13347 }
13349 /* If all elements are from the second vector, reindex as if from the
13350 first vector. */
13355 /* Check whether the mask can be applied to a single vector. */
13368 }
13370 rtx
13372 {
13373 /* We have to reverse each vector because we dont have
13374 a permuted load that can reverse-load according to ABI rules. */
13375 rtx mask;
13389 }
13391 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13392 However due to issues with register allocation it is preferable to avoid
13393 tieing integer scalar and FP scalar modes. Executing integer operations
13394 in general registers is better than treating them as scalar vector
13395 operations. This reduces latency and avoids redundant int<->FP moves.
13396 So tie modes if they are either the same class, or vector modes with
13397 other vector modes, vector structs or any scalar mode.
13398 */
13400 bool
13402 {
13406 /* We specifically want to allow elements of "structure" modes to
13407 be tieable to the structure. This more general condition allows
13408 other rarer situations too. */
13412 /* Also allow any scalar modes with vectors. */
13418 }
13420 /* Return a new RTX holding the result of moving POINTER forward by
13421 AMOUNT bytes. */
13423 static rtx
13425 {
13430 }
13432 /* Return a new RTX holding the result of moving POINTER forward by the
13433 size of the mode it points to. */
13435 static rtx
13437 {
13441 }
13443 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13444 MODE bytes. */
13446 static void
13448 machine_mode mode)
13449 {
13452 /* "Cast" the pointers to the correct mode. */
13455 /* Emit the memcpy. */
13458 /* Move the pointers forward. */
13461 }
13463 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13464 we succeed, otherwise return false. */
13466 bool
13468 {
13472 rtx base;
13475 /* When optimizing for size, give a better estimate of the length of a
13476 memcpy call, but use the default otherwise. */
13479 /* We can't do anything smart if the amount to copy is not constant. */
13485 /* Try to keep the number of instructions low. For cases below 16 bytes we
13486 need to make at most two moves. For cases above 16 bytes it will be one
13487 move for each 16 byte chunk, then at most two additional moves. */
13497 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13498 1-byte chunk. */
13500 {
13502 {
13505 }
13511 }
13513 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13514 4-byte chunk, partially overlapping with the previously copied chunk. */
13516 {
13520 {
13526 }
13528 }
13530 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13531 them, then (if applicable) an 8-byte chunk. */
13533 {
13535 {
13538 }
13539 else
13540 {
13543 }
13544 }
13546 /* Finish the final bytes of the copy. We can always do this in one
13547 instruction. We either copy the exact amount we need, or partially
13548 overlap with the previous chunk we copied and copy 8-bytes. */
13557 else
13558 {
13560 {
13564 }
13565 else
13566 {
13572 }
13573 }
13576 }
13578 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13579 SImode stores. Handle the case when the constant has identical
13580 bottom and top halves. This is beneficial when the two stores can be
13581 merged into an STP and we avoid synthesising potentially expensive
13582 immediates twice. Return true if such a split is possible. */
13584 bool
13586 {
13595 unsigned int orig_cost
13597 unsigned int lo_cost
13600 /* We want to transform:
13601 MOV x1, 49370
13602 MOVK x1, 0x140, lsl 16
13603 MOVK x1, 0xc0da, lsl 32
13604 MOVK x1, 0x140, lsl 48
13605 STR x1, [x0]
13606 into:
13607 MOV w1, 49370
13608 MOVK w1, 0x140, lsl 16
13609 STP w1, w1, [x0]
13610 So we want to perform this only when we save two instructions
13611 or more. When optimizing for size, however, accept any code size
13612 savings we can. */
13627 /* Don't emit an explicit store pair as this may not be always profitable.
13628 Let the sched-fusion logic decide whether to merge them. */
13633 }
13635 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13637 static unsigned HOST_WIDE_INT
13639 {
13641 }
13643 static bool
13648 {
13649 /* STORE_BY_PIECES can be used when copying a constant string, but
13650 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13651 For now we always fail this and let the move_by_pieces code copy
13652 the string from read-only memory. */
13657 }
13659 static rtx
13662 {
13666 insn_code icode;
13677 {
13705 }
13710 {
13713 }
13722 {
13725 }
13731 }
13733 static rtx
13736 {
13740 insn_code icode;
13752 {
13780 }
13785 {
13788 }
13796 {
13801 }
13812 {
13815 }
13821 }
13823 #undef TARGET_GEN_CCMP_FIRST
13824 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13826 #undef TARGET_GEN_CCMP_NEXT
13827 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13829 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13830 instruction fusion of some sort. */
13832 static bool
13834 {
13836 }
13839 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13840 should be kept together during scheduling. */
13842 static bool
13844 {
13845 rtx set_dest;
13848 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13855 {
13856 /* We are trying to match:
13857 prev (mov) == (set (reg r0) (const_int imm16))
13858 curr (movk) == (set (zero_extract (reg r0)
13859 (const_int 16)
13860 (const_int 16))
13861 (const_int imm16_1)) */
13873 {
13875 }
13876 }
13879 {
13881 /* We're trying to match:
13882 prev (adrp) == (set (reg r1)
13883 (high (symbol_ref ("SYM"))))
13884 curr (add) == (set (reg r0)
13885 (lo_sum (reg r1)
13886 (symbol_ref ("SYM"))))
13887 Note that r0 need not necessarily be the same as r1, especially
13888 during pre-regalloc scheduling. */
13892 {
13900 }
13901 }
13904 {
13906 /* We're trying to match:
13907 prev (movk) == (set (zero_extract (reg r0)
13908 (const_int 16)
13909 (const_int 32))
13910 (const_int imm16_1))
13911 curr (movk) == (set (zero_extract (reg r0)
13912 (const_int 16)
13913 (const_int 48))
13914 (const_int imm16_2)) */
13930 }
13932 {
13933 /* We're trying to match:
13934 prev (adrp) == (set (reg r0)
13935 (high (symbol_ref ("SYM"))))
13936 curr (ldr) == (set (reg r1)
13937 (mem (lo_sum (reg r0)
13938 (symbol_ref ("SYM")))))
13939 or
13940 curr (ldr) == (set (reg r1)
13941 (zero_extend (mem
13942 (lo_sum (reg r0)
13943 (symbol_ref ("SYM")))))) */
13946 {
13959 }
13960 }
13968 {
13971 /* FIXME: this misses some which is considered simple arthematic
13972 instructions for ThunderX. Simple shifts are missed here. */
13978 }
13981 }
13983 /* Return true iff the instruction fusion described by OP is enabled. */
13985 bool
13987 {
13989 }
13991 /* If MEM is in the form of [base+offset], extract the two parts
13992 of address and set to BASE and OFFSET, otherwise return false
13993 after clearing BASE and OFFSET. */
13995 bool
13997 {
13998 rtx addr;
14005 {
14009 }
14013 {
14017 }
14023 }
14025 /* Types for scheduling fusion. */
14026 enum sched_fusion_type
14027 {
14029 SCHED_FUSION_LD_SIGN_EXTEND,
14030 SCHED_FUSION_LD_ZERO_EXTEND,
14031 SCHED_FUSION_LD,
14032 SCHED_FUSION_ST,
14033 SCHED_FUSION_NUM
14034 };
14036 /* If INSN is a load or store of address in the form of [base+offset],
14037 extract the two parts and set to BASE and OFFSET. Return scheduling
14038 fusion type this INSN is. */
14040 static enum sched_fusion_type
14042 {
14060 {
14065 }
14067 {
14072 }
14077 {
14080 }
14081 else
14088 }
14090 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14092 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14093 and PRI are only calculated for these instructions. For other instruction,
14094 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14095 type instruction fusion can be added by returning different priorities.
14097 It's important that irrelevant instructions get the largest FUSION_PRI. */
14099 static void
14102 {
14112 {
14116 }
14118 /* Set FUSION_PRI according to fusion type and base register. */
14121 /* Calculate PRI. */
14124 /* INSN with smaller offset goes first. */
14128 else
14133 }
14135 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14136 Adjust priority of sha1h instructions so they are scheduled before
14137 other SHA1 instructions. */
14139 static int
14141 {
14145 {
14150 }
14153 }
14155 /* Given OPERANDS of consecutive load/store, check if we can merge
14156 them into ldp/stp. LOAD is true if they are load instructions.
14157 MODE is the mode of memory operands. */
14159 bool
14162 {
14168 {
14176 }
14177 else
14178 {
14183 }
14185 /* The mems cannot be volatile. */
14189 /* If we have SImode and slow unaligned ldp,
14190 check the alignment to be at least 8 byte. */
14194 && !optimize_size
14198 /* Check if the addresses are in the form of [base+offset]. */
14206 /* Check if the bases are same. */
14213 /* Check if the offsets are consecutive. */
14217 /* Check if the addresses are clobbered by load. */
14219 {
14223 /* In increasing order, the last load can clobber the address. */
14226 }
14230 else
14235 else
14238 /* Check if the registers are of same class. */
14243 }
14245 /* Given OPERANDS of consecutive load/store, check if we can merge
14246 them into ldp/stp by adjusting the offset. LOAD is true if they
14247 are load instructions. MODE is the mode of memory operands.
14249 Given below consecutive stores:
14251 str w1, [xb, 0x100]
14252 str w1, [xb, 0x104]
14253 str w1, [xb, 0x108]
14254 str w1, [xb, 0x10c]
14256 Though the offsets are out of the range supported by stp, we can
14257 still pair them after adjusting the offset, like:
14259 add scratch, xb, 0x100
14260 stp w1, w1, [scratch]
14261 stp w1, w1, [scratch, 0x8]
14263 The peephole patterns detecting this opportunity should guarantee
14264 the scratch register is avaliable. */
14266 bool
14269 {
14276 {
14289 }
14290 else
14291 {
14300 }
14301 /* Skip if memory operand is by itslef valid for ldp/stp. */
14305 /* The mems cannot be volatile. */
14310 /* Check if the addresses are in the form of [base+offset]. */
14324 /* Check if the bases are same. */
14335 /* Check if the offsets are consecutive. */
14344 /* Check if the addresses are clobbered by load. */
14346 {
14352 /* In increasing order, the last load can clobber the address. */
14355 }
14357 /* If we have SImode and slow unaligned ldp,
14358 check the alignment to be at least 8 byte. */
14362 && !optimize_size
14368 else
14373 else
14378 else
14383 else
14386 /* Check if the registers are of same class. */
14391 }
14393 /* Given OPERANDS of consecutive load/store, this function pairs them
14394 into ldp/stp after adjusting the offset. It depends on the fact
14395 that addresses of load/store instructions are in increasing order.
14396 MODE is the mode of memory operands. CODE is the rtl operator
14397 which should be applied to all memory operands, it's SIGN_EXTEND,
14398 ZERO_EXTEND or UNKNOWN. */
14400 bool
14403 {
14409 {
14414 }
14415 else
14416 {
14422 }
14427 /* Adjust offset thus it can fit in ldp/stp instruction. */
14435 /* Further adjust to make sure all offsets are OK. */
14437 {
14440 }
14442 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14447 {
14450 }
14452 /* Create new memory references. */
14456 /* Check if the adjusted address is OK for ldp/stp. */
14475 {
14480 }
14482 {
14487 }
14490 {
14495 }
14496 else
14497 {
14502 }
14504 /* Emit adjusting instruction. */
14506 /* Emit ldp/stp instructions. */
14514 }
14516 /* Return 1 if pseudo register should be created and used to hold
14517 GOT address for PIC code. */
14519 bool
14521 {
14523 }
14525 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14527 static int
14529 {
14531 {
14538 }
14541 }
14544 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14545 return the log2 of that value. Otherwise return -1. */
14547 int
14549 {
14564 }
14566 /* If X is a vector of equal CONST_DOUBLE values and that value is
14567 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14569 int
14571 {
14587 }
14589 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
14590 to float.
14592 __fp16 always promotes through this hook.
14593 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
14594 through the generic excess precision logic rather than here. */
14596 static tree
14598 {
14604 }
14606 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
14608 static bool
14610 optimization_type opt_type)
14611 {
14613 {
14619 }
14620 }
14622 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
14623 if MODE is HFmode, and punt to the generic implementation otherwise. */
14625 static bool
14627 {
14631 }
14633 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
14634 if MODE is HFmode, and punt to the generic implementation otherwise. */
14636 static bool
14638 {
14642 }
14644 /* Set the value of FLT_EVAL_METHOD.
14645 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
14647 0: evaluate all operations and constants, whose semantic type has at
14648 most the range and precision of type float, to the range and
14649 precision of float; evaluate all other operations and constants to
14650 the range and precision of the semantic type;
14652 N, where _FloatN is a supported interchange floating type
14653 evaluate all operations and constants, whose semantic type has at
14654 most the range and precision of _FloatN type, to the range and
14655 precision of the _FloatN type; evaluate all other operations and
14656 constants to the range and precision of the semantic type;
14658 If we have the ARMv8.2-A extensions then we support _Float16 in native
14659 precision, so we should set this to 16. Otherwise, we support the type,
14660 but want to evaluate expressions in float precision, so set this to
14661 0. */
14663 static enum flt_eval_method
14665 {
14667 {
14670 /* We can calculate either in 16-bit range and precision or
14671 32-bit range and precision. Make that decision based on whether
14672 we have native support for the ARMv8.2-A 16-bit floating-point
14673 instructions or not. */
14675 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
14681 }
14683 }
14685 /* Target-specific selftests. */
14687 #if CHECKING_P
14691 /* Selftest for the RTL loader.
14692 Verify that the RTL loader copes with a dump from
14693 print_rtx_function. This is essentially just a test that class
14694 function_reader can handle a real dump, but it also verifies
14695 that lookup_reg_by_dump_name correctly handles hard regs.
14696 The presence of hard reg names in the dump means that the test is
14697 target-specific, hence it is in this file. */
14699 static void
14701 {
14713 /* Verify crtl->return_rtx. */
14717 }
14719 /* Run all target-specific selftests. */
14721 static void
14723 {
14725 }
14731 #undef TARGET_ADDRESS_COST
14732 #define TARGET_ADDRESS_COST aarch64_address_cost
14734 /* This hook will determines whether unnamed bitfields affect the alignment
14735 of the containing structure. The hook returns true if the structure
14736 should inherit the alignment requirements of an unnamed bitfield's
14737 type. */
14738 #undef TARGET_ALIGN_ANON_BITFIELD
14739 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14741 #undef TARGET_ASM_ALIGNED_DI_OP
14744 #undef TARGET_ASM_ALIGNED_HI_OP
14747 #undef TARGET_ASM_ALIGNED_SI_OP
14750 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14751 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14752 hook_bool_const_tree_hwi_hwi_const_tree_true
14754 #undef TARGET_ASM_FILE_START
14755 #define TARGET_ASM_FILE_START aarch64_start_file
14757 #undef TARGET_ASM_OUTPUT_MI_THUNK
14758 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14760 #undef TARGET_ASM_SELECT_RTX_SECTION
14761 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14763 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14764 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14766 #undef TARGET_BUILD_BUILTIN_VA_LIST
14767 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14769 #undef TARGET_CALLEE_COPIES
14770 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14772 #undef TARGET_CAN_ELIMINATE
14773 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14775 #undef TARGET_CAN_INLINE_P
14776 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14778 #undef TARGET_CANNOT_FORCE_CONST_MEM
14779 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14781 #undef TARGET_CASE_VALUES_THRESHOLD
14782 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14784 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14785 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14787 /* Only the least significant bit is used for initialization guard
14788 variables. */
14789 #undef TARGET_CXX_GUARD_MASK_BIT
14790 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14792 #undef TARGET_C_MODE_FOR_SUFFIX
14793 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14795 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14796 #undef TARGET_DEFAULT_TARGET_FLAGS
14797 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14798 #endif
14800 #undef TARGET_CLASS_MAX_NREGS
14801 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14803 #undef TARGET_BUILTIN_DECL
14804 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14806 #undef TARGET_BUILTIN_RECIPROCAL
14807 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14809 #undef TARGET_C_EXCESS_PRECISION
14810 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
14812 #undef TARGET_EXPAND_BUILTIN
14813 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14815 #undef TARGET_EXPAND_BUILTIN_VA_START
14816 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14818 #undef TARGET_FOLD_BUILTIN
14819 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14821 #undef TARGET_FUNCTION_ARG
14822 #define TARGET_FUNCTION_ARG aarch64_function_arg
14824 #undef TARGET_FUNCTION_ARG_ADVANCE
14825 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14827 #undef TARGET_FUNCTION_ARG_BOUNDARY
14828 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14830 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14831 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14833 #undef TARGET_FUNCTION_VALUE
14834 #define TARGET_FUNCTION_VALUE aarch64_function_value
14836 #undef TARGET_FUNCTION_VALUE_REGNO_P
14837 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14839 #undef TARGET_FRAME_POINTER_REQUIRED
14840 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14842 #undef TARGET_GIMPLE_FOLD_BUILTIN
14843 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14845 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14846 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14848 #undef TARGET_INIT_BUILTINS
14849 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14851 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14852 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14853 aarch64_ira_change_pseudo_allocno_class
14855 #undef TARGET_LEGITIMATE_ADDRESS_P
14856 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14858 #undef TARGET_LEGITIMATE_CONSTANT_P
14859 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14861 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
14862 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
14863 aarch64_legitimize_address_displacement
14865 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14866 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14868 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
14869 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
14870 aarch64_libgcc_floating_mode_supported_p
14872 #undef TARGET_MANGLE_TYPE
14873 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14875 #undef TARGET_MEMORY_MOVE_COST
14876 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14878 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14879 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14881 #undef TARGET_MUST_PASS_IN_STACK
14882 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14884 /* This target hook should return true if accesses to volatile bitfields
14885 should use the narrowest mode possible. It should return false if these
14886 accesses should use the bitfield container type. */
14887 #undef TARGET_NARROW_VOLATILE_BITFIELD
14888 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14890 #undef TARGET_OPTION_OVERRIDE
14891 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14893 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14894 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14895 aarch64_override_options_after_change
14897 #undef TARGET_OPTION_SAVE
14898 #define TARGET_OPTION_SAVE aarch64_option_save
14900 #undef TARGET_OPTION_RESTORE
14901 #define TARGET_OPTION_RESTORE aarch64_option_restore
14903 #undef TARGET_OPTION_PRINT
14904 #define TARGET_OPTION_PRINT aarch64_option_print
14906 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14907 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14909 #undef TARGET_SET_CURRENT_FUNCTION
14910 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14912 #undef TARGET_PASS_BY_REFERENCE
14913 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14915 #undef TARGET_PREFERRED_RELOAD_CLASS
14916 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14918 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14919 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14921 #undef TARGET_PROMOTED_TYPE
14922 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14924 #undef TARGET_SECONDARY_RELOAD
14925 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14927 #undef TARGET_SHIFT_TRUNCATION_MASK
14928 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14930 #undef TARGET_SETUP_INCOMING_VARARGS
14931 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14933 #undef TARGET_STRUCT_VALUE_RTX
14934 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14936 #undef TARGET_REGISTER_MOVE_COST
14937 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14939 #undef TARGET_RETURN_IN_MEMORY
14940 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14942 #undef TARGET_RETURN_IN_MSB
14943 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14945 #undef TARGET_RTX_COSTS
14946 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14948 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14949 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
14951 #undef TARGET_SCHED_ISSUE_RATE
14952 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14954 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14955 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14956 aarch64_sched_first_cycle_multipass_dfa_lookahead
14958 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14959 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14960 aarch64_first_cycle_multipass_dfa_lookahead_guard
14962 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
14963 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
14964 aarch64_get_separate_components
14966 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
14967 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
14968 aarch64_components_for_bb
14970 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
14971 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
14972 aarch64_disqualify_components
14974 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
14975 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
14976 aarch64_emit_prologue_components
14978 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
14979 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
14980 aarch64_emit_epilogue_components
14982 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
14983 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
14984 aarch64_set_handled_components
14986 #undef TARGET_TRAMPOLINE_INIT
14987 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14989 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14990 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14992 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14993 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14995 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
14996 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
14997 aarch64_builtin_support_vector_misalignment
14999 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15000 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15002 #undef TARGET_VECTORIZE_ADD_STMT_COST
15003 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15005 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15006 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15007 aarch64_builtin_vectorization_cost
15009 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15010 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15012 #undef TARGET_VECTORIZE_BUILTINS
15013 #define TARGET_VECTORIZE_BUILTINS
15015 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15016 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15017 aarch64_builtin_vectorized_function
15019 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15020 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15021 aarch64_autovectorize_vector_sizes
15023 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15024 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15025 aarch64_atomic_assign_expand_fenv
15027 /* Section anchor support. */
15029 #undef TARGET_MIN_ANCHOR_OFFSET
15030 #define TARGET_MIN_ANCHOR_OFFSET -256
15032 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15033 byte offset; we can do much more for larger data types, but have no way
15034 to determine the size of the access. We assume accesses are aligned. */
15035 #undef TARGET_MAX_ANCHOR_OFFSET
15036 #define TARGET_MAX_ANCHOR_OFFSET 4095
15038 #undef TARGET_VECTOR_ALIGNMENT
15039 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15041 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15042 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15043 aarch64_simd_vector_alignment_reachable
15045 /* vec_perm support. */
15047 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15048 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15049 aarch64_vectorize_vec_perm_const_ok
15051 #undef TARGET_INIT_LIBFUNCS
15052 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15054 #undef TARGET_FIXED_CONDITION_CODE_REGS
15055 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15057 #undef TARGET_FLAGS_REGNUM
15058 #define TARGET_FLAGS_REGNUM CC_REGNUM
15060 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15061 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15063 #undef TARGET_ASAN_SHADOW_OFFSET
15064 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15066 #undef TARGET_LEGITIMIZE_ADDRESS
15067 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15069 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15070 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15071 aarch64_use_by_pieces_infrastructure_p
15073 #undef TARGET_CAN_USE_DOLOOP_P
15074 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15076 #undef TARGET_SCHED_ADJUST_PRIORITY
15077 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15079 #undef TARGET_SCHED_MACRO_FUSION_P
15080 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15082 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15083 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15085 #undef TARGET_SCHED_FUSION_PRIORITY
15086 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15088 #undef TARGET_UNSPEC_MAY_TRAP_P
15089 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15091 #undef TARGET_USE_PSEUDO_PIC_REG
15092 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15094 #undef TARGET_PRINT_OPERAND
15095 #define TARGET_PRINT_OPERAND aarch64_print_operand
15097 #undef TARGET_PRINT_OPERAND_ADDRESS
15098 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15100 #undef TARGET_OPTAB_SUPPORTED_P
15101 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15103 #undef TARGET_OMIT_STRUCT_RETURN_REG
15104 #define TARGET_OMIT_STRUCT_RETURN_REG true
15106 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15107 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15108 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15110 #if CHECKING_P
15111 #undef TARGET_RUN_TARGET_SELFTESTS
15112 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests