| blob | 321580d7f6a1aa58202b8aedddb396ce7f4421c3 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2023 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
23 #define INCLUDE_STRING
24 #define INCLUDE_ALGORITHM
88 /* This file should be included last. */
91 /* Defined for convenience. */
92 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
94 /* Information about a legitimate vector immediate operand. */
95 struct simd_immediate_info
96 {
108 /* The mode of the elements. */
109 scalar_mode elt_mode;
111 /* The instruction to use to move the immediate into a vector. */
112 insn_type insn;
114 union
115 {
116 /* For MOV and MVN. */
117 struct
118 {
119 /* The value of each element. */
120 rtx value;
122 /* The kind of shift modifier to use, and the number of bits to shift.
123 This is (LSL, 0) if no shift is needed. */
124 modifier_type modifier;
128 /* For INDEX. */
129 struct
130 {
131 /* The value of the first element and the step to be added for each
132 subsequent element. */
136 /* For PTRUE. */
137 aarch64_svpattern pattern;
139 };
141 /* Construct a floating-point immediate in which each element has mode
142 ELT_MODE_IN and value VALUE_IN. */
143 inline simd_immediate_info
146 {
150 }
152 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
153 and value VALUE_IN. The other parameters are as for the structure
154 fields. */
155 inline simd_immediate_info
161 {
165 }
167 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
168 and where element I is equal to BASE_IN + I * STEP_IN. */
169 inline simd_immediate_info
172 {
175 }
177 /* Construct a predicate that controls elements of mode ELT_MODE_IN
178 and has PTRUE pattern PATTERN_IN. */
179 inline simd_immediate_info
181 aarch64_svpattern pattern_in)
183 {
185 }
189 /* Describes types that map to Pure Scalable Types (PSTs) in the AAPCS64. */
190 class pure_scalable_type_info
191 {
193 /* Represents the result of analyzing a type. All values are nonzero,
194 in the possibly forlorn hope that accidental conversions to bool
195 trigger a warning. */
196 enum analysis_result
197 {
198 /* The type does not have an ABI identity; i.e. it doesn't contain
199 at least one object whose type is a Fundamental Data Type. */
202 /* The type is definitely a Pure Scalable Type. */
203 IS_PST,
205 /* The type is definitely not a Pure Scalable Type. */
206 ISNT_PST,
208 /* It doesn't matter for PCS purposes whether the type is a Pure
209 Scalable Type or not, since the type will be handled the same
210 way regardless.
212 Specifically, this means that if the type is a Pure Scalable Type,
213 there aren't enough argument registers to hold it, and so it will
214 need to be passed or returned in memory. If the type isn't a
215 Pure Scalable Type, it's too big to be passed or returned in core
216 or SIMD&FP registers, and so again will need to go in memory. */
217 DOESNT_MATTER
218 };
220 /* Aggregates of 17 bytes or more are normally passed and returned
221 in memory, so aggregates of that size can safely be analyzed as
222 DOESNT_MATTER. We need to be able to collect enough pieces to
223 represent a PST that is smaller than that. Since predicates are
224 2 bytes in size for -msve-vector-bits=128, that means we need to be
225 able to store at least 8 pieces.
227 We also need to be able to store enough pieces to represent
228 a single vector in each vector argument register and a single
229 predicate in each predicate argument register. This means that
230 we need at least 12 pieces. */
234 /* Describes one piece of a PST. Each piece is one of:
236 - a single Scalable Vector Type (SVT)
237 - a single Scalable Predicate Type (SPT)
238 - a PST containing 2, 3 or 4 SVTs, with no padding
240 It either represents a single built-in type or a PST formed from
241 multiple homogeneous built-in types. */
242 struct piece
243 {
246 /* The number of vector and predicate registers that the piece
247 occupies. One of the two is always zero. */
251 /* The mode of the registers described above. */
252 machine_mode mode;
254 /* If this piece is formed from multiple homogeneous built-in types,
255 this is the mode of the built-in types, otherwise it is MODE. */
256 machine_mode orig_mode;
258 /* The offset in bytes of the piece from the start of the type. */
259 poly_uint64_pod offset;
260 };
262 /* Divides types analyzed as IS_PST into individual pieces. The pieces
263 are in memory order. */
278 };
279 }
281 /* The current code model. */
284 /* The number of 64-bit elements in an SVE vector. */
285 poly_uint16 aarch64_sve_vg;
287 #ifdef HAVE_AS_TLS
288 #undef TARGET_HAVE_TLS
289 #define TARGET_HAVE_TLS 1
290 #endif
295 const_tree,
304 const_tree type,
309 aarch64_addr_query_type);
311 /* The processor for which instructions should be scheduled. */
314 /* Mask to specify which instruction scheduling options should be used. */
317 /* Global flag for PC relative loads. */
320 /* Global flag for whether frame pointer is enabled. */
325 /* Support for command line parsing of boolean flags in the tuning
326 structures. */
327 struct aarch64_flag_desc
328 {
331 };
333 #define AARCH64_FUSION_PAIR(name, internal_name) \
334 { name, AARCH64_FUSE_##internal_name },
336 {
341 };
343 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
344 { name, AARCH64_EXTRA_TUNE_##internal_name },
346 {
351 };
353 /* Tuning parameters. */
356 {
357 {
362 },
371 };
374 {
375 {
380 },
389 };
392 {
393 {
398 },
407 };
410 {
411 {
416 },
425 };
428 {
429 {
434 },
443 };
446 {
447 {
452 },
461 };
464 {
465 {
470 },
479 };
482 {
483 {
488 },
497 };
500 {
501 {
506 },
515 };
518 {
519 {
524 },
533 };
536 {
537 {
542 },
551 };
554 {
556 /* Avoid the use of slow int<->fp moves for spilling by setting
557 their cost higher than memmov_cost. */
561 };
564 {
566 /* Avoid the use of slow int<->fp moves for spilling by setting
567 their cost higher than memmov_cost. */
571 };
574 {
576 /* Avoid the use of slow int<->fp moves for spilling by setting
577 their cost higher than memmov_cost. */
581 };
584 {
586 /* Avoid the use of slow int<->fp moves for spilling by setting
587 their cost higher than memmov_cost (actual, 4 and 9). */
591 };
594 {
599 };
602 {
604 /* Avoid the use of slow int<->fp moves for spilling by setting
605 their cost higher than memmov_cost. */
609 };
612 {
614 /* Avoid the use of int<->fp moves for spilling. */
618 };
621 {
623 /* Avoid the use of int<->fp moves for spilling. */
627 };
630 {
632 /* Avoid the use of int<->fp moves for spilling. */
636 };
639 {
641 /* Avoid the use of slow int<->fp moves for spilling by setting
642 their cost higher than memmov_cost. */
646 };
649 {
651 /* Avoid the use of slow int<->fp moves for spilling by setting
652 their cost higher than memmov_cost. */
656 };
659 {
661 /* Spilling to int<->fp instead of memory is recommended so set
662 realistic costs compared to memmov_cost. */
666 };
669 {
671 /* Spilling to int<->fp instead of memory is recommended so set
672 realistic costs compared to memmov_cost. */
676 };
679 {
681 /* Spilling to int<->fp instead of memory is recommended so set
682 realistic costs compared to memmov_cost. */
686 };
688 /* Generic costs for Advanced SIMD vector operations. */
690 {
711 };
713 /* Generic costs for SVE vector operations. */
715 {
716 {
737 },
745 };
747 /* Generic costs for vector insn classes. */
749 {
759 };
762 {
783 };
786 {
787 {
808 },
816 };
819 {
829 };
832 {
853 };
855 /* QDF24XX costs for vector insn classes. */
857 {
867 };
871 {
892 };
894 /* ThunderX costs for vector insn classes. */
896 {
906 };
909 {
930 };
933 {
943 };
946 {
967 };
969 /* Cortex-A57 costs for vector insn classes. */
971 {
981 };
984 {
1005 };
1008 {
1018 };
1021 {
1042 };
1044 /* Generic costs for vector insn classes. */
1046 {
1056 };
1059 {
1080 };
1082 /* Costs for vector insn classes for Vulcan. */
1084 {
1094 };
1097 {
1118 };
1121 {
1131 };
1134 {
1155 };
1157 /* Ampere-1 costs for vector insn classes. */
1159 {
1169 };
1171 /* Generic costs for branch instructions. */
1173 {
1176 };
1178 /* Generic approximation modes. */
1180 {
1183 AARCH64_APPROX_NONE /* recip_sqrt */
1184 };
1186 /* Approximation modes for Exynos M1. */
1188 {
1191 AARCH64_APPROX_ALL /* recip_sqrt */
1192 };
1194 /* Approximation modes for X-Gene 1. */
1196 {
1199 AARCH64_APPROX_ALL /* recip_sqrt */
1200 };
1202 /* Generic prefetch settings (which disable prefetch). */
1204 {
1212 };
1215 {
1223 };
1226 {
1234 };
1237 {
1245 };
1248 {
1256 };
1259 {
1267 };
1270 {
1278 };
1281 {
1289 };
1292 {
1300 };
1303 {
1311 };
1314 {
1322 };
1325 {
1353 /* Enabling AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS significantly benefits
1354 Neoverse V1. It does not have a noticeable effect on A64FX and should
1355 have at most a very minor effect on SVE2 cores. */
1357 &generic_prefetch_tune
1358 };
1361 {
1391 &generic_prefetch_tune
1392 };
1395 {
1425 &generic_prefetch_tune
1426 };
1429 {
1459 &generic_prefetch_tune
1460 };
1463 {
1493 &generic_prefetch_tune
1494 };
1497 {
1527 &generic_prefetch_tune
1528 };
1533 {
1562 &exynosm1_prefetch_tune
1563 };
1566 {
1595 &thunderxt88_prefetch_tune
1596 };
1599 {
1627 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
1629 &thunderx_prefetch_tune
1630 };
1633 {
1663 &tsv110_prefetch_tune
1664 };
1667 {
1696 &xgene1_prefetch_tune
1697 };
1700 {
1707 SVE_NOT_IMPLEMENTED,
1729 &xgene1_prefetch_tune
1730 };
1733 {
1763 &qdf24xx_prefetch_tune
1764 };
1766 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
1767 for now. */
1769 {
1799 &generic_prefetch_tune
1800 };
1803 {
1833 &thunderx2t99_prefetch_tune
1834 };
1837 {
1867 &thunderx3t110_prefetch_tune
1868 };
1871 {
1900 &generic_prefetch_tune
1901 };
1904 {
1923 AARCH64_FUSE_CMP_BRANCH),
1924 /* fusible_ops */
1937 &ere1_prefetch_tune
1938 };
1941 {
1961 AARCH64_FUSE_ADDSUB_2REG_CONST1),
1962 /* fusible_ops */
1975 &ere1_prefetch_tune
1976 };
1979 {
1994 /* This value is just inherited from the Cortex-A57 table. */
1996 /* This depends very much on what the scalar value is and
1997 where it comes from. E.g. some constants take two dependent
1998 instructions or a load, while others might be moved from a GPR.
1999 4 seems to be a reasonable compromise in practice. */
2003 /* Although stores have a latency of 2 and compete for the
2004 vector pipes, in practice it's better not to model that. */
2007 };
2010 {
2011 {
2018 /* Theoretically, a reduction involving 31 scalar ADDs could
2019 complete in ~9 cycles and would have a cost of 31. [SU]ADDV
2020 completes in 14 cycles, so give it a cost of 31 + 5. */
2022 /* Likewise for 15 scalar ADDs (~5 cycles) vs. 12: 15 + 7. */
2024 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 10: 7 + 7. */
2026 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 10: 3 + 8. */
2028 /* Theoretically, a reduction involving 15 scalar FADDs could
2029 complete in ~9 cycles and would have a cost of 30. FADDV
2030 completes in 13 cycles, so give it a cost of 30 + 4. */
2032 /* Likewise for 7 scalar FADDs (~6 cycles) vs. 11: 14 + 5. */
2034 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 9: 6 + 5. */
2037 /* This value is just inherited from the Cortex-A57 table. */
2039 /* See the comment above the Advanced SIMD versions. */
2043 /* Although stores have a latency of 2 and compete for the
2044 vector pipes, in practice it's better not to model that. */
2047 },
2055 };
2058 {
2064 };
2067 {
2068 {
2074 },
2078 };
2081 {
2082 {
2083 {
2089 },
2093 },
2100 };
2103 {
2106 &neoversev1_sve_issue_info
2107 };
2109 /* Neoverse V1 costs for vector insn classes. */
2111 {
2121 };
2124 {
2152 (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2153 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2154 | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT
2156 &generic_prefetch_tune
2157 };
2160 {
2161 {
2168 /* Theoretically, a reduction involving 15 scalar ADDs could
2169 complete in ~5 cycles and would have a cost of 15. Assume that
2170 [SU]ADDV completes in 11 cycles and so give it a cost of 15 + 6. */
2172 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */
2174 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */
2176 /* Likewise for 1 scalar ADD (1 cycle) vs. 8: 1 + 7. */
2178 /* Theoretically, a reduction involving 7 scalar FADDs could
2179 complete in ~6 cycles and would have a cost of 14. Assume that
2180 FADDV completes in 8 cycles and so give it a cost of 14 + 2. */
2182 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
2184 /* Likewise for 1 scalar FADD (2 cycles) vs. 4: 2 + 2. */
2187 /* This value is just inherited from the Cortex-A57 table. */
2189 /* This depends very much on what the scalar value is and
2190 where it comes from. E.g. some constants take two dependent
2191 instructions or a load, while others might be moved from a GPR.
2192 4 seems to be a reasonable compromise in practice. */
2196 /* Although stores generally have a latency of 2 and compete for the
2197 vector pipes, in practice it's better not to model that. */
2200 },
2205 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2206 (6 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2207 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2208 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2209 (cost 2) to that, to avoid the difference being lost in rounding.
2211 There is no easy comparison between a strided Advanced SIMD x32 load
2212 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2213 operation more than a 64-bit gather. */
2217 };
2220 {
2221 {
2222 {
2228 },
2232 },
2239 };
2242 {
2245 &neoverse512tvb_sve_issue_info
2246 };
2249 {
2259 };
2262 {
2290 (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2291 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2293 &generic_prefetch_tune
2294 };
2297 {
2312 /* This value is just inherited from the Cortex-A57 table. */
2314 /* This depends very much on what the scalar value is and
2315 where it comes from. E.g. some constants take two dependent
2316 instructions or a load, while others might be moved from a GPR.
2317 4 seems to be a reasonable compromise in practice. */
2321 /* Although stores have a latency of 2 and compete for the
2322 vector pipes, in practice it's better not to model that. */
2325 };
2328 {
2329 {
2336 /* Theoretically, a reduction involving 15 scalar ADDs could
2337 complete in ~5 cycles and would have a cost of 15. [SU]ADDV
2338 completes in 11 cycles, so give it a cost of 15 + 6. */
2340 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */
2342 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */
2344 /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */
2346 /* Theoretically, a reduction involving 7 scalar FADDs could
2347 complete in ~8 cycles and would have a cost of 14. FADDV
2348 completes in 6 cycles, so give it a cost of 14 - 2. */
2350 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 4: 6 - 0. */
2352 /* Likewise for 1 scalar FADD (~2 cycles) vs. 2: 2 - 0. */
2355 /* This value is just inherited from the Cortex-A57 table. */
2357 /* See the comment above the Advanced SIMD versions. */
2361 /* Although stores have a latency of 2 and compete for the
2362 vector pipes, in practice it's better not to model that. */
2365 },
2370 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2371 (8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2372 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2373 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2374 (cost 2) to that, to avoid the difference being lost in rounding.
2376 There is no easy comparison between a strided Advanced SIMD x32 load
2377 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2378 operation more than a 64-bit gather. */
2382 };
2385 {
2391 };
2394 {
2395 {
2401 },
2405 };
2408 {
2409 {
2410 {
2416 },
2420 },
2427 };
2430 {
2433 &neoversen2_sve_issue_info
2434 };
2436 /* Neoverse N2 costs for vector insn classes. */
2438 {
2448 };
2451 {
2479 (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
2480 | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2481 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2483 &generic_prefetch_tune
2484 };
2487 {
2502 /* This value is just inherited from the Cortex-A57 table. */
2504 /* This depends very much on what the scalar value is and
2505 where it comes from. E.g. some constants take two dependent
2506 instructions or a load, while others might be moved from a GPR.
2507 4 seems to be a reasonable compromise in practice. */
2511 /* Although stores have a latency of 2 and compete for the
2512 vector pipes, in practice it's better not to model that. */
2515 };
2518 {
2519 {
2526 /* Theoretically, a reduction involving 15 scalar ADDs could
2527 complete in ~3 cycles and would have a cost of 15. [SU]ADDV
2528 completes in 11 cycles, so give it a cost of 15 + 8. */
2530 /* Likewise for 7 scalar ADDs (~2 cycles) vs. 9: 7 + 7. */
2532 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 4. */
2534 /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */
2536 /* Theoretically, a reduction involving 7 scalar FADDs could
2537 complete in ~6 cycles and would have a cost of 14. FADDV
2538 completes in 8 cycles, so give it a cost of 14 + 2. */
2540 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
2542 /* Likewise for 1 scalar FADD (~2 cycles) vs. 4: 2 + 2. */
2545 /* This value is just inherited from the Cortex-A57 table. */
2547 /* See the comment above the Advanced SIMD versions. */
2551 /* Although stores have a latency of 2 and compete for the
2552 vector pipes, in practice it's better not to model that. */
2555 },
2560 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2561 (8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2562 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2563 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2564 (cost 2) to that, to avoid the difference being lost in rounding.
2566 There is no easy comparison between a strided Advanced SIMD x32 load
2567 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2568 operation more than a 64-bit gather. */
2572 };
2575 {
2581 };
2584 {
2585 {
2591 },
2595 };
2598 {
2599 {
2600 {
2606 },
2610 },
2617 };
2620 {
2623 &neoversev2_sve_issue_info
2624 };
2626 /* Demeter costs for vector insn classes. */
2628 {
2638 };
2641 {
2669 (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
2670 | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2671 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2673 &generic_prefetch_tune
2674 };
2677 {
2706 &a64fx_prefetch_tune
2707 };
2709 /* Support for fine-grained override of the tuning structures. */
2710 struct aarch64_tuning_override_function
2711 {
2714 };
2720 static const struct aarch64_tuning_override_function
2721 aarch64_tuning_override_functions[] =
2722 {
2727 };
2729 /* A processor implementing AArch64. */
2730 struct processor
2731 {
2733 aarch64_processor ident;
2734 aarch64_processor sched_core;
2735 aarch64_arch arch;
2736 aarch64_feature_flags flags;
2738 };
2740 /* Architectures implementing AArch64. */
2742 {
2743 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, D, E) \
2744 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, \
2745 feature_deps::ARCH_IDENT ().enable, NULL},
2748 };
2750 /* Processor cores implementing AArch64. */
2752 {
2753 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, E, COSTS, G, H, I) \
2754 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
2755 feature_deps::cpu_##IDENT, &COSTS##_tunings},
2760 };
2762 /* The current tuning set. */
2765 /* Check whether an 'aarch64_vector_pcs' attribute is valid. */
2767 static tree
2770 {
2771 /* Since we set fn_type_req to true, the caller should have checked
2772 this for us. */
2775 {
2782 name);
2789 }
2791 }
2793 /* Table of machine attributes. */
2795 {
2796 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
2797 affects_type_identity, handler, exclude } */
2802 NULL },
2807 };
2810 {
2814 }
2815 aarch64_cc;
2817 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
2820 /* The condition codes of the processor, and the inverse function. */
2822 {
2825 };
2827 /* The preferred condition codes for SVE conditions. */
2829 {
2832 };
2834 /* Return the assembly token for svpattern value VALUE. */
2838 {
2840 {
2841 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
2843 #undef CASE
2846 }
2848 }
2850 /* Return the location of a piece that is known to be passed or returned
2851 in registers. FIRST_ZR is the first unused vector argument register
2852 and FIRST_PR is the first unused predicate argument register. */
2854 rtx
2857 {
2869 }
2871 /* Return the total number of vector registers required by the PST. */
2873 unsigned int
2875 {
2880 }
2882 /* Return the total number of predicate registers required by the PST. */
2884 unsigned int
2886 {
2891 }
2893 /* Return the location of a PST that is known to be passed or returned
2894 in registers. FIRST_ZR is the first unused vector argument register
2895 and FIRST_PR is the first unused predicate argument register. */
2897 rtx
2901 {
2902 /* Try to return a single REG if possible. This leads to better
2903 code generation; it isn't required for correctness. */
2905 {
2908 }
2910 /* Build up a PARALLEL that contains the individual pieces. */
2913 {
2919 }
2921 }
2923 /* Analyze whether TYPE is a Pure Scalable Type according to the rules
2924 in the AAPCS64. */
2928 {
2929 /* Prevent accidental reuse. */
2932 /* No code will be generated for erroneous types, so we won't establish
2933 an ABI mapping. */
2937 /* Zero-sized types disappear in the language->ABI mapping. */
2941 /* Check for SVTs, SPTs, and built-in tuple types that map to PSTs. */
2942 piece p = {};
2944 {
2952 }
2954 /* Check for user-defined PSTs. */
2961 }
2963 /* Analyze a type that is known not to be passed or returned in memory.
2964 Return true if it has an ABI identity and is a Pure Scalable Type. */
2966 bool
2968 {
2972 }
2974 /* Subroutine of analyze for handling ARRAY_TYPEs. */
2978 {
2979 /* Analyze the element type. */
2980 pure_scalable_type_info element_info;
2985 /* An array of unknown, flexible or variable length will be passed and
2986 returned by reference whatever we do. */
2991 /* Likewise if the array is constant-sized but too big to be interesting.
2992 The double checks against MAX_PIECES are to protect against overflow. */
3000 /* The above checks should have weeded out elements of unknown size. */
3001 poly_uint64 element_bytes;
3005 /* Build up the list of individual vectors and predicates. */
3009 {
3013 }
3015 }
3017 /* Subroutine of analyze for handling RECORD_TYPEs. */
3021 {
3023 {
3027 /* Zero-sized fields disappear in the language->ABI mapping. */
3031 /* All fields with an ABI identity must be PSTs for the record as
3032 a whole to be a PST. If any individual field is too big to be
3033 interesting then the record is too. */
3034 pure_scalable_type_info field_info;
3041 /* Since all previous fields are PSTs, we ought to be able to track
3042 the field offset using poly_ints. */
3046 /* For the same reason, it shouldn't be possible to create a PST field
3047 whose offset isn't byte-aligned. */
3049 BITS_PER_UNIT);
3051 /* Punt if the record is too big to be interesting. */
3052 poly_uint64 bytepos;
3057 /* Add the individual vectors and predicates in the field to the
3058 record's list. */
3061 {
3065 }
3066 }
3067 /* Empty structures disappear in the language->ABI mapping. */
3069 }
3071 /* Add P to the list of pieces in the type. */
3073 void
3075 {
3076 /* Try to fold the new piece into the previous one to form a
3077 single-mode PST. For example, if we see three consecutive vectors
3078 of the same mode, we can represent them using the corresponding
3079 3-tuple mode.
3081 This is purely an optimization. */
3083 {
3095 {
3099 }
3100 }
3102 }
3104 /* Return true if at least one possible value of type TYPE includes at
3105 least one object of Pure Scalable Type, in the sense of the AAPCS64.
3107 This is a relatively expensive test for some types, so it should
3108 generally be made as late as possible. */
3110 static bool
3112 {
3129 }
3131 /* Return the descriptor of the SIMD ABI. */
3135 {
3138 {
3139 HARD_REG_SET full_reg_clobbers
3145 }
3147 }
3149 /* Return the descriptor of the SVE PCS. */
3153 {
3156 {
3157 HARD_REG_SET full_reg_clobbers
3164 }
3166 }
3168 /* If X is an UNSPEC_SALT_ADDR expression, return the address that it
3169 wraps, otherwise return X itself. */
3171 static rtx
3173 {
3180 }
3182 /* Like strip_offset, but also strip any UNSPEC_SALT_ADDR from the
3183 expression. */
3185 static rtx
3187 {
3189 }
3191 /* Generate code to enable conditional branches in functions over 1 MiB. */
3195 {
3212 }
3214 void
3216 {
3221 else
3224 else
3228 else
3231 }
3233 /* Report when we try to do something that requires SVE when SVE is disabled.
3234 This is an error of last resort and isn't very high-quality. It usually
3235 involves attempts to measure the vector length in some way. */
3236 static void
3238 {
3241 /* Avoid reporting a slew of messages for a single oversight. */
3247 " option %<-march%>, or by using the %<target%>"
3250 }
3252 /* Return true if REGNO is P0-P15 or one of the special FFR-related
3253 registers. */
3256 {
3258 }
3260 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
3261 The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and
3262 GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much
3263 higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS
3264 and GENERAL_REGS is lower than the memory cost (in this case the best class
3265 is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its
3266 cost results in bad allocations with many redundant int<->FP moves which
3267 are expensive on various cores.
3268 To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but
3269 force a decision between FP_REGS and GENERAL_REGS. We use the allocno class
3270 if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't
3271 POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.
3272 The result of this is that it is no longer inefficient to have a higher
3273 memory move cost than the register move cost.
3274 */
3276 static reg_class_t
3278 reg_class_t best_class)
3279 {
3280 machine_mode mode;
3292 }
3294 static unsigned int
3296 {
3300 }
3302 /* Return the reassociation width of treeop OPC with mode MODE. */
3303 static int
3305 {
3310 /* Reassociation reduces the number of FMAs which may result in worse
3311 performance. Use a per-CPU setting for FMA reassociation which allows
3312 narrow CPUs with few FP pipes to switch it off (value of 1), and wider
3313 CPUs with many FP pipes to enable reassociation.
3314 Since the reassociation pass doesn't understand FMA at all, assume
3315 that any FP addition might turn into FMA. */
3320 }
3322 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
3323 unsigned
3325 {
3337 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
3338 equivalent DWARF register. */
3340 }
3342 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
3343 static machine_mode
3345 {
3346 /* Predicate registers are call-clobbered in the EH ABI (which is
3347 ARM_PCS_AAPCS64), so they should not be described by CFI.
3348 Their size changes as VL changes, so any values computed by
3349 __builtin_init_dwarf_reg_size_table might not be valid for
3350 all frames. */
3354 }
3356 /* If X is a CONST_DOUBLE, return its bit representation as a constant
3357 integer, otherwise return X unmodified. */
3358 static rtx
3360 {
3364 }
3366 /* Return an estimate for the number of quadwords in an SVE vector. This is
3367 equivalent to the number of Advanced SIMD vectors in an SVE vector. */
3368 static unsigned int
3370 {
3372 }
3374 /* Return true if MODE is an SVE predicate mode. */
3375 static bool
3377 {
3383 }
3385 /* Three mutually-exclusive flags describing a vector or predicate type. */
3389 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
3390 a structure of 2, 3 or 4 vectors. */
3392 /* Can be used in combination with VEC_SVE_DATA to indicate that the
3393 vector has fewer significant bytes than a full SVE vector. */
3395 /* Useful combinations of the above. */
3399 /* Return a set of flags describing the vector properties of mode MODE.
3400 Ignore modes that are not supported by the current target. */
3401 static unsigned int
3403 {
3407 /* Make the decision based on the mode's enum value rather than its
3408 properties, so that we keep the correct classification regardless
3409 of -msve-vector-bits. */
3411 {
3412 /* Partial SVE QI vectors. */
3416 /* Partial SVE HI vectors. */
3419 /* Partial SVE SI vector. */
3421 /* Partial SVE HF vectors. */
3424 /* Partial SVE BF vectors. */
3427 /* Partial SVE SF vector. */
3441 /* x2 SVE vectors. */
3450 /* x3 SVE vectors. */
3459 /* x4 SVE vectors. */
3475 /* Structures of 64-bit Advanced SIMD vectors. */
3502 /* Structures of 128-bit Advanced SIMD vectors. */
3529 /* 64-bit Advanced SIMD vectors. */
3538 /* 128-bit Advanced SIMD vectors. */
3551 }
3552 }
3554 /* Return true if MODE is any of the Advanced SIMD structure modes. */
3555 bool
3557 {
3560 }
3562 /* Return true if MODE is an Advanced SIMD D-register structure mode. */
3563 static bool
3565 {
3568 }
3570 /* Return true if MODE is an Advanced SIMD Q-register structure mode. */
3571 static bool
3573 {
3575 }
3577 /* Return true if MODE is any of the data vector modes, including
3578 structure modes. */
3579 static bool
3581 {
3583 }
3585 /* Return true if MODE is any form of SVE mode, including predicates,
3586 vectors and structures. */
3587 bool
3589 {
3591 }
3593 /* Return true if MODE is an SVE data vector mode; either a single vector
3594 or a structure of vectors. */
3595 static bool
3597 {
3599 }
3601 /* Return the number of defined bytes in one constituent vector of
3602 SVE mode MODE, which has vector flags VEC_FLAGS. */
3603 static poly_int64
3605 {
3607 /* A single partial vector. */
3611 /* A single vector or a tuple. */
3614 /* A single predicate. */
3617 }
3619 /* If MODE holds an array of vectors, return the number of vectors
3620 in the array, otherwise return 1. */
3622 static unsigned int
3624 {
3634 }
3636 /* Given an Advanced SIMD vector mode MODE and a tuple size NELEMS, return the
3637 corresponding vector structure mode. */
3638 static opt_machine_mode
3641 {
3646 machine_mode struct_mode;
3654 }
3656 /* Return the SVE vector mode that has NUNITS elements of mode INNER_MODE. */
3658 opt_machine_mode
3660 {
3663 machine_mode mode;
3670 }
3672 /* Implement target hook TARGET_ARRAY_MODE. */
3673 static opt_machine_mode
3675 {
3685 }
3687 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
3688 static bool
3691 {
3699 }
3701 /* MODE is some form of SVE vector mode. For data modes, return the number
3702 of vector register bits that each element of MODE occupies, such as 64
3703 for both VNx2DImode and VNx2SImode (where each 32-bit value is stored
3704 in a 64-bit container). For predicate modes, return the number of
3705 data bits controlled by each significant predicate bit. */
3707 static unsigned int
3709 {
3712 ? BITS_PER_SVE_VECTOR
3715 }
3717 /* Return the SVE predicate mode to use for elements that have
3718 ELEM_NBYTES bytes, if such a mode exists. */
3720 opt_machine_mode
3722 {
3724 {
3733 }
3735 }
3737 /* Return the SVE predicate mode that should be used to control
3738 SVE mode MODE. */
3740 machine_mode
3742 {
3745 }
3747 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
3749 static opt_machine_mode
3751 {
3757 }
3759 /* Return the integer element mode associated with SVE mode MODE. */
3761 static scalar_int_mode
3763 {
3765 ? BITS_PER_SVE_VECTOR
3770 }
3772 /* Return an integer element mode that contains exactly
3773 aarch64_sve_container_bits (MODE) bits. This is wider than
3774 aarch64_sve_element_int_mode if MODE is a partial vector,
3775 otherwise it's the same. */
3777 static scalar_int_mode
3779 {
3781 }
3783 /* Return the integer vector mode associated with SVE mode MODE.
3784 Unlike related_int_vector_mode, this can handle the case in which
3785 MODE is a predicate (and thus has a different total size). */
3787 machine_mode
3789 {
3792 }
3794 /* Implement TARGET_VECTORIZE_RELATED_MODE. */
3796 static opt_machine_mode
3798 scalar_mode element_mode,
3799 poly_uint64 nunits)
3800 {
3803 /* If we're operating on SVE vectors, try to return an SVE mode. */
3804 poly_uint64 sve_nunits;
3808 {
3809 machine_mode sve_mode;
3811 {
3812 /* Try to find a full or partial SVE mode with exactly
3813 NUNITS units. */
3818 }
3819 else
3820 {
3821 /* Take the preferred number of units from the number of bytes
3822 that fit in VECTOR_MODE. We always start by "autodetecting"
3823 a full vector mode with preferred_simd_mode, so vectors
3824 chosen here will also be full vector modes. Then
3825 autovectorize_vector_modes tries smaller starting modes
3826 and thus smaller preferred numbers of units. */
3831 }
3832 }
3834 /* Prefer to use 1 128-bit vector instead of 2 64-bit vectors. */
3841 {
3845 }
3848 }
3850 /* Implement TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT. */
3852 static bool
3854 {
3861 }
3863 /* Implement TARGET_PREFERRED_ELSE_VALUE. For binary operations,
3864 prefer to use the first arithmetic operand as the else value if
3865 the else value doesn't matter, since that exactly matches the SVE
3866 destructive merging form. For ternary operations we could either
3867 pick the first operand and use FMAD-like instructions or the last
3868 operand and use FMLA-like instructions; the latter seems more
3869 natural. */
3871 static tree
3873 {
3875 }
3877 /* Implement TARGET_HARD_REGNO_NREGS. */
3879 static unsigned int
3881 {
3882 /* ??? Logically we should only need to provide a value when
3883 HARD_REGNO_MODE_OK says that the combination is valid,
3884 but at the moment we need to handle all modes. Just ignore
3885 any runtime parts for registers that can't store them. */
3888 {
3892 {
3900 }
3909 }
3911 }
3913 /* Implement TARGET_HARD_REGNO_MODE_OK. */
3915 static bool
3917 {
3926 /* This must have the same size as _Unwind_Word. */
3937 /* The purpose of comparing with ptr_mode is to support the
3938 global register variable associated with the stack pointer
3939 register via the syntax of asm ("wsp") in ILP32. */
3946 {
3953 }
3955 {
3958 else
3960 }
3963 }
3965 /* Return true if a function with type FNTYPE returns its value in
3966 SVE vector or predicate registers. */
3968 static bool
3970 {
3973 pure_scalable_type_info pst_info;
3975 {
3987 }
3989 }
3991 /* Return true if a function with type FNTYPE takes arguments in
3992 SVE vector or predicate registers. */
3994 static bool
3996 {
3997 CUMULATIVE_ARGS args_so_far_v;
4005 {
4012 pure_scalable_type_info pst_info;
4014 {
4019 }
4022 }
4024 }
4026 /* Implement TARGET_FNTYPE_ABI. */
4030 {
4039 }
4041 /* Implement TARGET_COMPATIBLE_VECTOR_TYPES_P. */
4043 static bool
4045 {
4048 }
4050 /* Return true if we should emit CFI for register REGNO. */
4052 static bool
4054 {
4057 }
4059 /* Return the mode we should use to save and restore register REGNO. */
4061 static machine_mode
4063 {
4069 {
4071 /* Only the low 64 bits are saved by the base PCS. */
4075 /* The vector PCS saves the low 128 bits (which is the full
4076 register on non-SVE targets). */
4080 /* Use vectors of DImode for registers that need frame
4081 information, so that the first 64 bytes of the save slot
4082 are always the equivalent of what storing D<n> would give. */
4086 /* Use vectors of bytes otherwise, so that the layout is
4087 endian-agnostic, and so that we can use LDR and STR for
4088 big-endian targets. */
4094 }
4097 /* Save the full predicate register. */
4101 }
4103 /* Implement TARGET_INSN_CALLEE_ABI. */
4107 {
4114 }
4116 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
4117 the lower 64 bits of a 128-bit register. Tell the compiler the callee
4118 clobbers the top 64 bits when restoring the bottom 64 bits. */
4120 static bool
4123 machine_mode mode)
4124 {
4126 {
4134 }
4136 }
4138 /* Implement REGMODE_NATURAL_SIZE. */
4139 poly_uint64
4141 {
4142 /* The natural size for SVE data modes is one SVE data vector,
4143 and similarly for predicates. We can't independently modify
4144 anything smaller than that. */
4145 /* ??? For now, only do this for variable-width SVE registers.
4146 Doing it for constant-sized registers breaks lower-subreg.cc. */
4147 /* ??? And once that's fixed, we should probably have similar
4148 code for Advanced SIMD. */
4150 {
4156 }
4158 }
4160 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
4161 machine_mode
4163 machine_mode mode)
4164 {
4165 /* The predicate mode determines which bits are significant and
4166 which are "don't care". Decreasing the number of lanes would
4167 lose data while increasing the number of lanes would make bits
4168 unnecessarily significant. */
4173 else
4175 }
4177 /* Return true if I's bits are consecutive ones from the MSB. */
4178 bool
4180 {
4182 }
4184 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
4185 that strcpy from constants will be faster. */
4187 static HOST_WIDE_INT
4189 {
4193 }
4195 /* Return true if calls to DECL should be treated as
4196 long-calls (ie called via a register). */
4197 static bool
4199 {
4201 }
4203 /* Return true if calls to symbol-ref SYM should be treated as
4204 long-calls (ie called via a register). */
4205 bool
4207 {
4209 }
4211 /* Return true if calls to symbol-ref SYM should not go through
4212 plt stubs. */
4214 bool
4216 {
4220 && decl
4221 && (!flag_plt
4227 }
4229 /* Emit an insn that's a simple single-set. Both the operands must be
4230 known to be valid. */
4233 {
4235 }
4237 /* X and Y are two things to compare using CODE. Emit the compare insn and
4238 return the rtx for register 0 in the proper mode. */
4239 rtx
4241 {
4243 machine_mode cc_mode;
4244 rtx cc_reg;
4247 {
4262 }
4263 else
4264 {
4268 }
4270 }
4272 /* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */
4274 static rtx
4276 machine_mode y_mode)
4277 {
4279 {
4281 {
4284 }
4285 else
4286 {
4288 machine_mode cc_mode;
4296 }
4297 }
4303 }
4305 /* Consider the operation:
4307 OPERANDS[0] = CODE (OPERANDS[1], OPERANDS[2]) + OPERANDS[3]
4309 where:
4311 - CODE is [SU]MAX or [SU]MIN
4312 - OPERANDS[2] and OPERANDS[3] are constant integers
4313 - OPERANDS[3] is a positive or negative shifted 12-bit immediate
4314 - all operands have mode MODE
4316 Decide whether it is possible to implement the operation using:
4318 SUBS <tmp>, OPERANDS[1], -OPERANDS[3]
4319 or
4320 ADDS <tmp>, OPERANDS[1], OPERANDS[3]
4322 followed by:
4324 <insn> OPERANDS[0], <tmp>, [wx]zr, <cond>
4326 where <insn> is one of CSEL, CSINV or CSINC. Return true if so.
4327 If GENERATE_P is true, also update OPERANDS as follows:
4329 OPERANDS[4] = -OPERANDS[3]
4330 OPERANDS[5] = the rtl condition representing <cond>
4331 OPERANDS[6] = <tmp>
4332 OPERANDS[7] = 0 for CSEL, -1 for CSINV or 1 for CSINC. */
4333 bool
4335 {
4342 /* max (x, y) - z == (x >= y + 1 ? x : y) - z
4343 == (x >= y ? x : y) - z
4344 == (x > y ? x : y) - z
4345 == (x > y - 1 ? x : y) - z
4347 min (x, y) - z == (x <= y - 1 ? x : y) - z
4348 == (x <= y ? x : y) - z
4349 == (x < y ? x : y) - z
4350 == (x < y + 1 ? x : y) - z
4352 Check whether z is in { y - 1, y, y + 1 } and pick the form(s) for
4353 which x is compared with z. Set DIFF to y - z. Thus the supported
4354 combinations are as follows, with DIFF being the value after the ":":
4356 max (x, y) - z == x >= y + 1 ? x - (y + 1) : -1 [z == y + 1]
4357 == x >= y ? x - y : 0 [z == y]
4358 == x > y ? x - y : 0 [z == y]
4359 == x > y - 1 ? x - (y - 1) : 1 [z == y - 1]
4361 min (x, y) - z == x <= y - 1 ? x - (y - 1) : 1 [z == y - 1]
4362 == x <= y ? x - y : 0 [z == y]
4363 == x < y ? x - y : 0 [z == y]
4364 == x < y + 1 ? x - (y + 1) : -1 [z == y + 1]. */
4377 rtx_code cmp;
4379 {
4394 }
4401 else
4406 }
4409 /* Build the SYMBOL_REF for __tls_get_addr. */
4413 rtx
4415 {
4419 }
4421 /* Return the TLS model to use for ADDR. */
4423 static enum tls_model
4425 {
4427 poly_int64 offset;
4433 }
4435 /* We'll allow lo_sum's in addresses in our legitimate addresses
4436 so that combine would take care of combining addresses where
4437 necessary, but for generation purposes, we'll generate the address
4438 as :
4439 RTL Absolute
4440 tmp = hi (symbol_ref); adrp x1, foo
4441 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
4442 nop
4444 PIC TLS
4445 adrp x1, :got:foo adrp tmp, :tlsgd:foo
4446 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
4447 bl __tls_get_addr
4448 nop
4450 Load TLS symbol, depending on TLS mechanism and TLS access model.
4452 Global Dynamic - Traditional TLS:
4453 adrp tmp, :tlsgd:imm
4454 add dest, tmp, #:tlsgd_lo12:imm
4455 bl __tls_get_addr
4457 Global Dynamic - TLS Descriptors:
4458 adrp dest, :tlsdesc:imm
4459 ldr tmp, [dest, #:tlsdesc_lo12:imm]
4460 add dest, dest, #:tlsdesc_lo12:imm
4461 blr tmp
4462 mrs tp, tpidr_el0
4463 add dest, dest, tp
4465 Initial Exec:
4466 mrs tp, tpidr_el0
4467 adrp tmp, :gottprel:imm
4468 ldr dest, [tmp, #:gottprel_lo12:imm]
4469 add dest, dest, tp
4471 Local Exec:
4472 mrs tp, tpidr_el0
4473 add t0, tp, #:tprel_hi12:imm, lsl #12
4474 add t0, t0, #:tprel_lo12_nc:imm
4475 */
4477 static void
4480 {
4482 {
4484 {
4485 /* In ILP32, the mode of dest can be either SImode or DImode. */
4497 }
4504 {
4507 rtx insn;
4508 rtx mem;
4510 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
4511 here before rtl expand. Tree IVOPT will generate rtl pattern to
4512 decide rtx costs, in which case pic_offset_table_rtx is not
4513 initialized. For that case no need to generate the first adrp
4514 instruction as the final cost for global variable access is
4515 one instruction. */
4517 {
4518 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
4519 using the page base as GOT base, the first page may be wasted,
4520 in the worst scenario, there is only 28K space for GOT).
4522 The generate instruction sequence for accessing global variable
4523 is:
4525 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
4527 Only one instruction needed. But we must initialize
4528 pic_offset_table_rtx properly. We generate initialize insn for
4529 every global access, and allow CSE to remove all redundant.
4531 The final instruction sequences will look like the following
4532 for multiply global variables access.
4534 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
4536 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
4537 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
4538 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
4539 ... */
4548 }
4551 {
4554 else
4558 }
4559 else
4560 {
4565 }
4567 /* The operand is expected to be MEM. Whenever the related insn
4568 pattern changed, above code which calculate mem should be
4569 updated. */
4575 }
4582 {
4584 /* The return type of __tls_get_addr is the C pointer type
4585 so use ptr_mode. */
4595 else
4602 /* Convert back to the mode of the dest adding a zero_extend
4603 from SImode (ptr_mode) to DImode (Pmode). */
4607 }
4610 {
4613 rtx tp;
4617 /* In ILP32, the got entry is always of SImode size. Unlike
4618 small GOT, the dest is fixed at reg 0. */
4621 else
4632 }
4635 {
4636 /* In ILP32, the mode of dest can be either SImode or DImode,
4637 while the got entry is always of SImode size. The mode of
4638 dest depends on how dest is used: if dest is assigned to a
4639 pointer (e.g. in the memory), it has SImode; it may have
4640 DImode if dest is dereferenced to access the memeory.
4641 This is why we have to handle three different tlsie_small
4642 patterns here (two patterns for ILP32). */
4648 {
4651 else
4652 {
4655 }
4656 }
4657 else
4658 {
4661 }
4667 }
4673 {
4681 {
4704 }
4709 }
4712 {
4713 rtx insn;
4718 else
4719 {
4722 }
4726 }
4729 {
4734 {
4737 else
4738 {
4741 }
4742 }
4743 else
4744 {
4747 }
4752 }
4756 }
4757 }
4759 /* Emit a move from SRC to DEST. Assume that the move expanders can
4760 handle all moves if !can_create_pseudo_p (). The distinction is
4761 important because, unlike emit_move_insn, the move expanders know
4762 how to force Pmode objects into the constant pool even when the
4763 constant pool address is not itself legitimate. */
4764 static rtx
4766 {
4770 }
4772 /* Apply UNOPTAB to OP and store the result in DEST. */
4774 static void
4776 {
4780 }
4782 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
4784 static void
4786 {
4788 OPTAB_DIRECT);
4791 }
4793 /* Split a 128-bit move operation into two 64-bit move operations,
4794 taking care to handle partial overlap of register to register
4795 copies. Special cases are needed when moving between GP regs and
4796 FP regs. SRC can be a register, constant or memory; DST a register
4797 or memory. If either operand is memory it must not have any side
4798 effects. */
4799 void
4801 {
4812 {
4816 /* Handle FP <-> GP regs. */
4818 {
4825 }
4827 {
4834 }
4835 }
4842 /* At most one pairing may overlap. */
4844 {
4847 }
4848 else
4849 {
4852 }
4853 }
4855 /* Return true if we should split a move from 128-bit value SRC
4856 to 128-bit register DEST. */
4858 bool
4860 {
4863 /* All moves to GPRs need to be split. */
4865 }
4867 /* Split a complex SIMD move. */
4869 void
4871 {
4878 {
4881 }
4882 }
4884 bool
4887 {
4891 }
4893 /* Return TARGET if it is nonnull and a register of mode MODE.
4894 Otherwise, return a fresh register of mode MODE if we can,
4895 or TARGET reinterpreted as MODE if we can't. */
4897 static rtx
4899 {
4903 {
4906 }
4908 }
4910 /* Return a register that contains the constant in BUILDER, given that
4911 the constant is a legitimate move operand. Use TARGET as the register
4912 if it is nonnull and convenient. */
4914 static rtx
4916 {
4921 }
4923 static rtx
4925 {
4928 else
4929 {
4933 }
4934 }
4936 /* Return true if predicate value X is a constant in which every element
4937 is a CONST_INT. When returning true, describe X in BUILDER as a VNx16BI
4938 value, i.e. as a predicate in which all bits are significant. */
4940 static bool
4942 {
4954 {
4962 }
4965 }
4967 /* BUILDER contains a predicate constant of mode VNx16BI. Return the
4968 widest predicate element size it can have (that is, the largest size
4969 for which each element would still be 0 or 1). */
4971 unsigned int
4973 {
4974 /* Start with the most optimistic assumption: that we only need
4975 one bit per pattern. This is what we will use if only the first
4976 bit in each pattern is ever set. */
4980 /* Look for set bits. */
4984 {
4988 }
4990 }
4992 /* If VNx16BImode rtx X is a canonical PTRUE for a predicate mode,
4993 return that predicate mode, otherwise return opt_machine_mode (). */
4995 opt_machine_mode
4997 {
5011 }
5013 /* BUILDER is a predicate constant of mode VNx16BI. Consider the value
5014 that the constant would have with predicate element size ELT_SIZE
5015 (ignoring the upper bits in each element) and return:
5017 * -1 if all bits are set
5018 * N if the predicate has N leading set bits followed by all clear bits
5019 * 0 if the predicate does not have any of these forms. */
5021 int
5024 {
5025 /* If nelts_per_pattern is 3, we have set bits followed by clear bits
5026 followed by set bits. */
5030 /* Skip over leading set bits. */
5038 /* Check for the all-true case. */
5042 /* If nelts_per_pattern is 1, then either VL is zero, or we have a
5043 repeating pattern of set bits followed by clear bits. */
5047 /* We have a "foreground" value and a duplicated "background" value.
5048 If the background might repeat and the last set bit belongs to it,
5049 we might have set bits followed by clear bits followed by set bits. */
5053 /* Make sure that the rest are all clear. */
5059 }
5061 /* See if there is an svpattern that encodes an SVE predicate of mode
5062 PRED_MODE in which the first VL bits are set and the rest are clear.
5063 Return the pattern if so, otherwise return AARCH64_NUM_SVPATTERNS.
5064 A VL of -1 indicates an all-true vector. */
5066 aarch64_svpattern
5068 {
5083 {
5086 /* These would only trigger for non-power-of-2 lengths. */
5093 }
5095 }
5097 /* Return a VNx16BImode constant in which every sequence of ELT_SIZE
5098 bits has the lowest bit set and the upper bits clear. This is the
5099 VNx16BImode equivalent of a PTRUE for controlling elements of
5100 ELT_SIZE bytes. However, because the constant is VNx16BImode,
5101 all bits are significant, even the upper zeros. */
5103 rtx
5105 {
5111 }
5113 /* Return an all-true predicate register of mode MODE. */
5115 rtx
5117 {
5121 }
5123 /* Return an all-false predicate register of mode MODE. */
5125 rtx
5127 {
5131 }
5133 /* PRED1[0] is a PTEST predicate and PRED1[1] is an aarch64_sve_ptrue_flag
5134 for it. PRED2[0] is the predicate for the instruction whose result
5135 is tested by the PTEST and PRED2[1] is again an aarch64_sve_ptrue_flag
5136 for it. Return true if we can prove that the two predicates are
5137 equivalent for PTEST purposes; that is, if we can replace PRED2[0]
5138 with PRED1[0] without changing behavior. */
5140 bool
5142 {
5154 }
5156 /* Emit a comparison CMP between OP0 and OP1, both of which have mode
5157 DATA_MODE, and return the result in a predicate of mode PRED_MODE.
5158 Use TARGET as the target register if nonnull and convenient. */
5160 static rtx
5163 {
5173 }
5175 /* Use a comparison to convert integer vector SRC into MODE, which is
5176 the corresponding SVE predicate mode. Use TARGET for the result
5177 if it's nonnull and convenient. */
5179 rtx
5181 {
5185 }
5187 /* Return the assembly token for svprfop value PRFOP. */
5191 {
5193 {
5194 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
5196 #undef CASE
5199 }
5201 }
5203 /* Return the assembly string for an SVE prefetch operation with
5204 mnemonic MNEMONIC, given that PRFOP_RTX is the prefetch operation
5205 and that SUFFIX is the format for the remaining operands. */
5210 {
5217 }
5219 /* Check whether we can calculate the number of elements in PATTERN
5220 at compile time, given that there are NELTS_PER_VQ elements per
5221 128-bit block. Return the value if so, otherwise return -1. */
5223 HOST_WIDE_INT
5225 {
5232 {
5233 /* There are two vector granules per quadword. */
5236 {
5242 }
5243 }
5244 else
5247 /* There are two vector granules per quadword. */
5252 /* Requesting more elements than are available results in a PFALSE. */
5257 }
5259 /* Return true if we can move VALUE into a register using a single
5260 CNT[BHWD] instruction. */
5262 static bool
5264 {
5266 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
5271 }
5273 /* Likewise for rtx X. */
5275 bool
5277 {
5278 poly_int64 value;
5280 }
5282 /* Return the asm string for an instruction with a CNT-like vector size
5283 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5284 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5285 first part of the operands template (the part that comes before the
5286 vector size itself). PATTERN is the pattern to use. FACTOR is the
5287 number of quadwords. NELTS_PER_VQ, if nonzero, is the number of elements
5288 in each quadword. If it is zero, we can use any element size. */
5292 aarch64_svpattern pattern,
5295 {
5299 /* There is some overlap in the ranges of the four CNT instructions.
5300 Here we always use the smallest possible element size, so that the
5301 multiplier is 1 whereever possible. */
5315 else
5318 factor);
5321 }
5323 /* Return the asm string for an instruction with a CNT-like vector size
5324 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5325 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5326 first part of the operands template (the part that comes before the
5327 vector size itself). X is the value of the vector size operand,
5328 as a polynomial integer rtx; we need to convert this into an "all"
5329 pattern with a multiplier. */
5333 rtx x)
5334 {
5339 }
5341 /* Return the asm string for an instruction with a CNT-like vector size
5342 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5343 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5344 first part of the operands template (the part that comes before the
5345 vector size itself). CNT_PAT[0..2] are the operands of the
5346 UNSPEC_SVE_CNT_PAT; see aarch64_sve_cnt_pat for details. */
5351 {
5357 }
5359 /* Return true if we can add X using a single SVE INC or DEC instruction. */
5361 bool
5363 {
5364 poly_int64 value;
5368 }
5370 /* Return the asm string for adding SVE INC/DEC immediate OFFSET to
5371 operand 0. */
5375 {
5381 else
5384 }
5386 /* Return true if we can add VALUE to a register using a single ADDVL
5387 or ADDPL instruction. */
5389 static bool
5391 {
5395 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
5396 and a value of 16 is one vector width. */
5399 }
5401 /* Likewise for rtx X. */
5403 bool
5405 {
5406 poly_int64 value;
5409 }
5411 /* Return the asm string for adding ADDVL or ADDPL immediate OFFSET
5412 to operand 1 and storing the result in operand 0. */
5416 {
5424 else
5427 }
5429 /* Return true if X is a valid immediate for an SVE vector INC or DEC
5430 instruction. If it is, store the number of elements in each vector
5431 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
5432 factor in *FACTOR_OUT (if nonnull). */
5434 bool
5437 {
5438 rtx elt;
5439 poly_int64 value;
5447 /* There's no vector INCB. */
5454 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
5464 }
5466 /* Return true if X is a valid immediate for an SVE vector INC or DEC
5467 instruction. */
5469 bool
5471 {
5473 }
5475 /* Return the asm template for an SVE vector INC or DEC instruction.
5476 OPERANDS gives the operands before the vector count and X is the
5477 value of the vector count operand itself. */
5481 {
5489 else
5492 }
5494 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
5497 {
5503 };
5507 /* Return true if 64-bit VAL is a valid bitmask immediate. */
5508 static bool
5510 {
5514 /* Check for a single sequence of one bits and return quickly if so.
5515 The special cases of all ones and all zeroes returns false. */
5521 /* Invert if the immediate doesn't start with a zero bit - this means we
5522 only need to search for sequences of one bits. */
5526 /* Find the first set bit and set tmp to val with the first sequence of one
5527 bits removed. Return success if there is a single sequence of ones. */
5534 /* Find the next set bit and compute the difference in bit position. */
5539 /* Check the bit position difference is a power of 2, and that the first
5540 sequence of one bits fits within 'bits' bits. */
5544 /* Check the sequence of one bits is repeated 64/bits times. */
5546 }
5549 /* Return true if VAL is a valid bitmask immediate for MODE. */
5550 bool
5552 {
5559 /* Replicate small immediates to fit 64 bits. */
5565 }
5568 /* Return true if the immediate VAL can be a bitfield immediate
5569 by changing the given MASK bits in VAL to zeroes, ones or bits
5570 from the other half of VAL. Return the new immediate in VAL2. */
5575 {
5590 }
5593 /* Return true if VAL is a valid MOVZ immediate. */
5596 {
5598 }
5601 /* Return true if immediate VAL can be created by a 64-bit MOVI/MOVN/MOVZ. */
5602 bool
5604 {
5607 }
5610 /* Return true if VAL is an immediate that can be created by a single
5611 MOV instruction. */
5612 bool
5614 {
5628 }
5631 static int
5633 machine_mode mode)
5634 {
5645 {
5649 }
5652 {
5654 {
5659 else
5662 }
5664 }
5666 /* Remaining cases are all for DImode. */
5674 /* Try a bitmask immediate and a movk to generate the immediate
5675 in 2 instructions. */
5678 {
5680 {
5687 }
5690 {
5692 {
5696 }
5698 }
5699 }
5701 /* Try a bitmask plus 2 movk to generate the immediate in 3 instructions. */
5703 {
5707 {
5709 {
5715 }
5717 }
5718 }
5720 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
5721 are emitted by the initial mov. If one_match > zero_match, skip set bits,
5722 otherwise skip zero bits. */
5734 {
5740 num_insns ++;
5741 }
5744 }
5746 /* Return whether imm is a 128-bit immediate which is simple enough to
5747 expand inline. */
5748 bool
5750 {
5761 }
5764 /* Return true if val can be encoded as a 12-bit unsigned immediate with
5765 a left shift of 0 or 12 bits. */
5766 bool
5768 {
5770 }
5772 /* Returns the nearest value to VAL that will fit as a 12-bit unsigned immediate
5773 that can be created with a left shift of 0 or 12. */
5774 static HOST_WIDE_INT
5776 {
5777 /* Check to see if the value fits in 24 bits, as that is the maximum we can
5778 handle correctly. */
5785 }
5788 /* Test whether:
5790 X = (X & AND_VAL) | IOR_VAL;
5792 can be implemented using:
5794 MOVK X, #(IOR_VAL >> shift), LSL #shift
5796 Return the shift if so, otherwise return -1. */
5797 int
5800 {
5804 {
5808 }
5810 }
5812 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
5813 Assumed precondition: VAL_IN Is not zero. */
5815 unsigned HOST_WIDE_INT
5817 {
5824 }
5826 /* Create constant where bits outside of lowest bit set to highest bit set
5827 are set to 1. */
5829 unsigned HOST_WIDE_INT
5831 {
5833 }
5835 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
5837 bool
5839 {
5840 scalar_int_mode int_mode;
5853 }
5855 /* Return the number of temporary registers that aarch64_add_offset_1
5856 would need to add OFFSET to a register. */
5858 static unsigned int
5860 {
5862 }
5864 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
5865 a non-polynomial OFFSET. MODE is the mode of the addition.
5866 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
5867 be set and CFA adjustments added to the generated instructions.
5869 TEMP1, if nonnull, is a register of mode MODE that can be used as a
5870 temporary if register allocation is already complete. This temporary
5871 register may overlap DEST but must not overlap SRC. If TEMP1 is known
5872 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
5873 the immediate again.
5875 Since this function may be used to adjust the stack pointer, we must
5876 ensure that it cannot cause transient stack deallocation (for example
5877 by first incrementing SP and then decrementing when adjusting by a
5878 large immediate). */
5880 static void
5884 {
5892 {
5894 {
5897 }
5899 }
5901 /* Single instruction adjustment. */
5903 {
5907 }
5909 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
5910 and either:
5912 a) the offset cannot be loaded by a 16-bit move or
5913 b) there is no spare register into which we can move it. */
5917 {
5926 }
5928 /* Emit a move immediate if required and an addition/subtraction. */
5930 {
5934 }
5939 {
5943 }
5944 }
5946 /* Return the number of temporary registers that aarch64_add_offset
5947 would need to move OFFSET into a register or add OFFSET to a register;
5948 ADD_P is true if we want the latter rather than the former. */
5950 static unsigned int
5952 {
5953 /* This follows the same structure as aarch64_add_offset. */
5962 /* Need one register for the ADDVL/ADDPL result. */
5965 {
5968 /* Need one register for the CNT result and one for the multiplication
5969 factor. If necessary, the second temporary can be reused for the
5970 constant part of the offset. */
5972 /* Need one register for the CNT result (which might then
5973 be shifted). */
5975 }
5977 }
5979 /* If X can be represented as a poly_int64, return the number
5980 of temporaries that are required to add it to a register.
5981 Return -1 otherwise. */
5983 int
5985 {
5986 poly_int64 offset;
5990 }
5992 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
5993 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
5994 be set and CFA adjustments added to the generated instructions.
5996 TEMP1, if nonnull, is a register of mode MODE that can be used as a
5997 temporary if register allocation is already complete. This temporary
5998 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
5999 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
6000 false to avoid emitting the immediate again.
6002 TEMP2, if nonnull, is a second temporary register that doesn't
6003 overlap either DEST or REG.
6005 Since this function may be used to adjust the stack pointer, we must
6006 ensure that it cannot cause transient stack deallocation (for example
6007 by first incrementing SP and then decrementing when adjusting by a
6008 large immediate). */
6010 static void
6014 {
6018 || !frame_related_p
6022 /* Try using ADDVL or ADDPL to add the whole value. */
6024 {
6029 }
6031 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
6032 SVE vector register, over and above the minimum size of 128 bits.
6033 This is equivalent to half the value returned by CNTD with a
6034 vector shape of ALL. */
6038 /* Try using ADDVL or ADDPL to add the VG-based part. */
6042 {
6045 {
6049 }
6050 else
6051 {
6056 }
6057 }
6058 /* Otherwise use a CNT-based sequence. */
6060 {
6061 /* Use a subtraction if we have a negative factor. */
6064 {
6067 }
6069 /* Calculate CNTD * FACTOR / 2. First try to fold the division
6070 into the multiplication. */
6071 rtx val;
6074 /* Use a right shift by 1. */
6076 else
6080 {
6082 {
6083 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
6084 the value with the minimum multiplier and shift it into
6085 position. */
6089 }
6091 }
6092 else
6093 {
6094 /* Base the factor on LOW_BIT if we can calculate LOW_BIT
6095 directly, since that should increase the chances of being
6096 able to use a shift and add sequence. If LOW_BIT itself
6097 is out of range, just use CNTD. */
6100 else
6107 {
6110 }
6111 else
6112 {
6113 /* Go back to using a negative multiplication factor if we have
6114 no register from which to subtract. */
6116 {
6119 }
6123 }
6124 }
6127 {
6128 /* Multiply by 1 << SHIFT. */
6131 }
6133 {
6134 /* Divide by 2. */
6137 }
6139 /* Calculate SRC +/- CNTD * FACTOR / 2. */
6141 {
6144 }
6146 {
6149 }
6152 {
6155 {
6159 poly_offset)));
6160 }
6164 }
6165 else
6166 {
6170 }
6173 }
6177 }
6179 /* Like aarch64_add_offset, but the offset is given as an rtx rather
6180 than a poly_int64. */
6182 void
6185 {
6188 }
6190 /* Add DELTA to the stack pointer, marking the instructions frame-related.
6191 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
6192 if TEMP1 already contains abs (DELTA). */
6196 {
6199 }
6201 /* Subtract DELTA from the stack pointer, marking the instructions
6202 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
6203 if nonnull. */
6208 {
6211 }
6213 /* Set DEST to (vec_series BASE STEP). */
6215 static void
6217 {
6221 /* Each operand can be a register or an immediate in the range [-16, 15]. */
6228 }
6230 /* Duplicate 128-bit Advanced SIMD vector SRC so that it fills an SVE
6231 register of mode MODE. Use TARGET for the result if it's nonnull
6232 and convenient.
6234 The two vector modes must have the same element mode. The behavior
6235 is to duplicate architectural lane N of SRC into architectural lanes
6236 N + I * STEP of the result. On big-endian targets, architectural
6237 lane 0 of an Advanced SIMD vector is the last element of the vector
6238 in memory layout, so for big-endian targets this operation has the
6239 effect of reversing SRC before duplicating it. Callers need to
6240 account for this. */
6242 rtx
6244 {
6247 insn_code icode = (BYTES_BIG_ENDIAN
6256 {
6257 /* Create a PARALLEL describing the reversal of SRC. */
6262 }
6265 }
6267 /* Try to force 128-bit vector value SRC into memory and use LD1RQ to fetch
6268 the memory image into DEST. Return true on success. */
6270 static bool
6272 {
6277 /* Make sure that the address is legitimate. */
6279 {
6282 }
6289 }
6291 /* SRC is an SVE CONST_VECTOR that contains N "foreground" values followed
6292 by N "background" values. Try to move it into TARGET using:
6294 PTRUE PRED.<T>, VL<N>
6295 MOV TRUE.<T>, #<foreground>
6296 MOV FALSE.<T>, #<background>
6297 SEL TARGET.<T>, PRED.<T>, TRUE.<T>, FALSE.<T>
6299 The PTRUE is always a single instruction but the MOVs might need a
6300 longer sequence. If the background value is zero (as it often is),
6301 the sequence can sometimes collapse to a PTRUE followed by a
6302 zero-predicated move.
6304 Return the target on success, otherwise return null. */
6306 static rtx
6308 {
6311 /* Make sure that the PTRUE is valid. */
6323 {
6326 }
6328 {
6331 }
6339 }
6341 /* Return a register containing CONST_VECTOR SRC, given that SRC has an
6342 SVE data mode and isn't a legitimate constant. Use TARGET for the
6343 result if convenient.
6345 The returned register can have whatever mode seems most natural
6346 given the contents of SRC. */
6348 static rtx
6350 {
6362 {
6363 /* We have a partial vector mode and a constant whose full-vector
6364 equivalent would occupy a repeating 128-bit sequence. Build that
6365 full-vector equivalent instead, so that we have the option of
6366 using LD1RQ and Advanced SIMD operations. */
6375 }
6378 {
6379 /* The constant is a duplicated quadword but can't be narrowed
6380 beyond a quadword. Get the memory image of the first quadword
6381 as a 128-bit vector and try using LD1RQ to load it from memory.
6383 The effect for both endiannesses is to load memory lane N into
6384 architectural lanes N + I * STEP of the result. On big-endian
6385 targets, the layout of the 128-bit vector in an Advanced SIMD
6386 register would be different from its layout in an SVE register,
6387 but this 128-bit vector is a memory value only. */
6392 }
6395 {
6396 /* The vector is a repeating sequence of 64 bits or fewer.
6397 See if we can load them using an Advanced SIMD move and then
6398 duplicate it to fill a vector. This is better than using a GPR
6399 move because it keeps everything in the same register file. */
6403 {
6404 /* We want memory lane N to go into architectural lane N,
6405 so reverse for big-endian targets. The DUP .Q pattern
6406 has a compensating reverse built-in. */
6409 }
6412 {
6415 }
6417 /* Get an integer representation of the repeating part of Advanced
6418 SIMD vector VQ_SRC. This preserves the endianness of VQ_SRC,
6419 which for big-endian targets is lane-swapped wrt a normal
6420 Advanced SIMD vector. This means that for both endiannesses,
6421 memory lane N of SVE vector SRC corresponds to architectural
6422 lane N of a register holding VQ_SRC. This in turn means that
6423 memory lane 0 of SVE vector SRC is in the lsb of VQ_SRC (viewed
6424 as a single 128-bit value) and thus that memory lane 0 of SRC is
6425 in the lsb of the integer. Duplicating the integer therefore
6426 ensures that memory lane N of SRC goes into architectural lane
6427 N + I * INDEX of the SVE register. */
6431 {
6432 /* Pretend that we had a vector of INT_MODE to start with. */
6436 /* If the integer can be moved into a general register by a
6437 single instruction, do that and duplicate the result. */
6441 {
6444 }
6445 }
6447 /* We're duplicating a single value, but can't do better than
6448 force it to memory and load from there. This handles things
6449 like symbolic constants. */
6453 {
6454 /* Load the element from memory if we can, otherwise move it into
6455 a register and use a DUP. */
6460 }
6461 }
6463 /* Try using INDEX. */
6466 {
6469 }
6471 /* From here on, it's better to force the whole constant to memory
6472 if we can. */
6480 /* Expand each pattern individually. */
6482 rtx_vector_builder builder;
6485 {
6490 }
6492 /* Use permutes to interleave the separate vectors. */
6494 {
6497 {
6502 }
6503 }
6506 }
6508 /* Use WHILE to set a predicate register of mode MODE in which the first
6509 VL bits are set and the rest are clear. Use TARGET for the register
6510 if it's nonnull and convenient. */
6512 static rtx
6515 {
6521 }
6523 static rtx
6526 /* BUILDER is a constant predicate in which the index of every set bit
6527 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
6528 by inverting every element at a multiple of ELT_SIZE and EORing the
6529 result with an ELT_SIZE PTRUE.
6531 Return a register that contains the constant on success, otherwise
6532 return null. Use TARGET as the register if it is nonnull and
6533 convenient. */
6535 static rtx
6538 {
6539 /* Invert every element at a multiple of ELT_SIZE, keeping the
6540 other bits zero. */
6546 else
6550 /* See if we can load the constant cheaply. */
6555 /* EOR the result with an ELT_SIZE PTRUE. */
6562 }
6564 /* BUILDER is a constant predicate in which the index of every set bit
6565 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
6566 using a TRN1 of size PERMUTE_SIZE, which is >= ELT_SIZE. Return the
6567 register on success, otherwise return null. Use TARGET as the register
6568 if nonnull and convenient. */
6570 static rtx
6574 {
6575 /* We're going to split the constant into two new constants A and B,
6576 with element I of BUILDER going into A if (I & PERMUTE_SIZE) == 0
6577 and into B otherwise. E.g. for PERMUTE_SIZE == 4 && ELT_SIZE == 1:
6579 A: { 0, 1, 2, 3, _, _, _, _, 8, 9, 10, 11, _, _, _, _ }
6580 B: { 4, 5, 6, 7, _, _, _, _, 12, 13, 14, 15, _, _, _, _ }
6582 where _ indicates elements that will be discarded by the permute.
6584 First calculate the ELT_SIZEs for A and B. */
6589 {
6592 else
6594 }
6598 /* Now construct the vectors themselves. */
6606 {
6609 }
6611 {
6612 /* The A and B elements are significant. */
6615 }
6616 else
6617 {
6618 /* The A and B elements are going to be discarded, so pick whatever
6619 is likely to give a nice constant. We are targeting element
6620 sizes A_ELT_SIZE and B_ELT_SIZE for A and B respectively,
6621 with the aim of each being a sequence of ones followed by
6622 a sequence of zeros. So:
6624 * if X_ELT_SIZE <= PERMUTE_SIZE, the best approach is to
6625 duplicate the last X_ELT_SIZE element, to extend the
6626 current sequence of ones or zeros.
6628 * if X_ELT_SIZE > PERMUTE_SIZE, the best approach is to add a
6629 zero, so that the constant really does have X_ELT_SIZE and
6630 not a smaller size. */
6633 else
6637 else
6639 }
6643 /* Try loading A into a register. */
6649 /* Try loading B into a register. */
6652 {
6655 {
6658 }
6659 }
6661 /* Emit the TRN1 itself. We emit a TRN that operates on VNx16BI
6662 operands but permutes them as though they had mode MODE. */
6668 }
6670 /* Subroutine of aarch64_expand_sve_const_pred. Try to load the VNx16BI
6671 constant in BUILDER into an SVE predicate register. Return the register
6672 on success, otherwise return null. Use TARGET for the register if
6673 nonnull and convenient.
6675 ALLOW_RECURSE_P is true if we can use methods that would call this
6676 function recursively. */
6678 static rtx
6681 {
6683 /* A PFALSE or a PTRUE .B ALL. */
6688 {
6689 /* If we can load the constant using PTRUE, use it as-is. */
6694 /* Otherwise use WHILE to set the first VL bits. */
6696 }
6701 /* Try inverting the vector in element size ELT_SIZE and then EORing
6702 the result with an ELT_SIZE PTRUE. */
6705 elt_size))
6708 /* Try using TRN1 to permute two simpler constants. */
6715 }
6717 /* Return an SVE predicate register that contains the VNx16BImode
6718 constant in BUILDER, without going through the move expanders.
6720 The returned register can have whatever mode seems most natural
6721 given the contents of BUILDER. Use TARGET for the result if
6722 convenient. */
6724 static rtx
6726 {
6727 /* Try loading the constant using pure predicate operations. */
6731 /* Try forcing the constant to memory. */
6734 {
6738 }
6740 /* The last resort is to load the constant as an integer and then
6741 compare it against zero. Use -1 for set bits in order to increase
6742 the changes of using SVE DUPM or an Advanced SIMD byte mask. */
6750 }
6752 /* Set DEST to immediate IMM. */
6754 void
6756 {
6759 /* Check on what type of symbol it is. */
6760 scalar_int_mode int_mode;
6766 {
6767 rtx mem;
6768 poly_int64 offset;
6769 HOST_WIDE_INT const_offset;
6772 /* If we have (const (plus symbol offset)), separate out the offset
6773 before we start classifying the symbol. */
6776 /* We must always add an offset involving VL separately, rather than
6777 folding it into the relocation. */
6779 {
6781 {
6784 }
6787 else
6788 {
6789 /* Do arithmetic on 32-bit values if the result is smaller
6790 than that. */
6792 {
6793 /* It is invalid to do symbol calculations in modes
6794 narrower than SImode. */
6798 }
6800 {
6804 }
6805 else
6808 }
6810 }
6814 {
6821 {
6827 }
6832 /* If we aren't generating PC relative literals, then
6833 we need to expand the literal pool access carefully.
6834 This is something that needs to be done in a number
6835 of places, so could well live as a separate function. */
6837 {
6844 }
6861 {
6867 }
6868 /* FALLTHRU */
6881 }
6882 }
6885 {
6887 {
6888 /* Only the low bit of each .H, .S and .D element is defined,
6889 so we can set the upper bits to whatever we like. If the
6890 predicate is all-true in MODE, prefer to set all the undefined
6891 bits as well, so that we can share a single .B predicate for
6892 all modes. */
6896 /* All methods for constructing predicate modes wider than VNx16BI
6897 will set the upper bits of each element to zero. Expose this
6898 by moving such constants as a VNx16BI, so that all bits are
6899 significant and so that constants for different modes can be
6900 shared. The wider constant will still be available as a
6901 REG_EQUAL note. */
6902 rtx_vector_builder builder;
6904 {
6909 }
6910 }
6914 {
6917 }
6921 {
6925 }
6931 }
6934 }
6936 /* Return the MEM rtx that provides the canary value that should be used
6937 for stack-smashing protection. MODE is the mode of the memory.
6938 For SSP_GLOBAL, DECL_RTL is the MEM rtx for the canary variable
6939 (__stack_chk_guard), otherwise it has no useful value. SALT_TYPE
6940 indicates whether the caller is performing a SET or a TEST operation. */
6942 rtx
6944 aarch64_salt_type salt_type)
6945 {
6946 rtx addr;
6948 {
6951 poly_int64 offset;
6960 }
6961 else
6962 {
6963 /* Calculate the address from the system register. */
6968 else
6969 {
6972 }
6974 }
6976 }
6978 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
6979 that is known to contain PTRUE. */
6981 void
6983 {
6991 }
6993 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
6994 operand is in memory. In this case we need to use the predicated LD1
6995 and ST1 instead of LDR and STR, both for correctness on big-endian
6996 targets and because LD1 and ST1 support a wider range of addressing modes.
6997 PRED_MODE is the mode of the predicate.
6999 See the comment at the head of aarch64-sve.md for details about the
7000 big-endian handling. */
7002 void
7004 {
7009 {
7013 else
7016 }
7018 }
7020 /* Called only on big-endian targets. See whether an SVE vector move
7021 from SRC to DEST is effectively a REV[BHW] instruction, because at
7022 least one operand is a subreg of an SVE vector that has wider or
7023 narrower elements. Return true and emit the instruction if so.
7025 For example:
7027 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
7029 represents a VIEW_CONVERT between the following vectors, viewed
7030 in memory order:
7032 R2: { [0].high, [0].low, [1].high, [1].low, ... }
7033 R1: { [0], [1], [2], [3], ... }
7035 The high part of lane X in R2 should therefore correspond to lane X*2
7036 of R1, but the register representations are:
7038 msb lsb
7039 R2: ...... [1].high [1].low [0].high [0].low
7040 R1: ...... [3] [2] [1] [0]
7042 where the low part of lane X in R2 corresponds to lane X*2 in R1.
7043 We therefore need a reverse operation to swap the high and low values
7044 around.
7046 This is purely an optimization. Without it we would spill the
7047 subreg operand to the stack in one mode and reload it in the
7048 other mode, which has the same effect as the REV. */
7050 bool
7052 {
7055 /* Do not try to optimize subregs that LRA has created for matched
7056 reloads. These subregs only exist as a temporary measure to make
7057 the RTL well-formed, but they are exempt from the usual
7058 TARGET_CAN_CHANGE_MODE_CLASS rules.
7060 For example, if we have:
7062 (set (reg:VNx8HI R1) (foo:VNx8HI (reg:VNx4SI R2)))
7064 and the constraints require R1 and R2 to be in the same register,
7065 LRA may need to create RTL such as:
7067 (set (subreg:VNx4SI (reg:VNx8HI TMP) 0) (reg:VNx4SI R2))
7068 (set (reg:VNx8HI TMP) (foo:VNx8HI (subreg:VNx4SI (reg:VNx8HI TMP) 0)))
7069 (set (reg:VNx8HI R1) (reg:VNx8HI TMP))
7071 which forces both the input and output of the original instruction
7072 to use the same hard register. But for this to work, the normal
7073 rules have to be suppressed on the subreg input, otherwise LRA
7074 would need to reload that input too, meaning that the process
7075 would never terminate. To compensate for this, the normal rules
7076 are also suppressed for the subreg output of the first move.
7077 Ignoring the special case and handling the first move normally
7078 would therefore generate wrong code: we would reverse the elements
7079 for the first subreg but not reverse them back for the second subreg. */
7085 /* The optimization handles two single SVE REGs with different element
7086 sizes. */
7095 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
7098 UNSPEC_REV_SUBREG);
7101 }
7103 /* Return a copy of X with mode MODE, without changing its other
7104 attributes. Unlike gen_lowpart, this doesn't care whether the
7105 mode change is valid. */
7107 rtx
7109 {
7116 }
7118 /* Return the SVE REV[BHW] unspec for reversing quantites of mode MODE
7119 stored in wider integer containers. */
7121 static unsigned int
7123 {
7125 {
7129 }
7131 }
7133 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
7134 operands. */
7136 void
7138 {
7139 /* Decide which REV operation we need. The mode with wider elements
7140 determines the mode of the operands and the mode with the narrower
7141 elements determines the reverse width. */
7151 /* Get the operands in the appropriate modes and emit the instruction. */
7157 }
7159 static bool
7161 {
7166 }
7168 /* Subroutine of aarch64_pass_by_reference for arguments that are not
7169 passed in SVE registers. */
7171 static bool
7174 {
7175 HOST_WIDE_INT size;
7176 machine_mode dummymode;
7179 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
7182 else
7183 /* No frontends can create types with variable-sized modes, so we
7184 shouldn't be asked to pass or return them. */
7187 /* Aggregates are passed by reference based on their size. */
7191 /* Variable sized arguments are always returned by reference. */
7195 /* Can this be a candidate to be passed in fp/simd register(s)? */
7201 /* Arguments which are variable sized or larger than 2 registers are
7202 passed by reference unless they are a homogenous floating point
7203 aggregate. */
7205 }
7207 /* Implement TARGET_PASS_BY_REFERENCE. */
7209 static bool
7212 {
7218 pure_scalable_type_info pst_info;
7220 {
7223 /* We can't gracefully recover at this point, so make this a
7224 fatal error. */
7228 /* Variadic SVE types are passed by reference. Normal non-variadic
7229 arguments are too if we've run out of registers. */
7241 }
7243 }
7245 /* Return TRUE if VALTYPE is padded to its least significant bits. */
7246 static bool
7248 {
7249 machine_mode dummy_mode;
7252 /* Never happens in little-endian mode. */
7256 /* Only composite types smaller than or equal to 16 bytes can
7257 be potentially returned in registers. */
7263 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
7264 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
7265 is always passed/returned in the least significant bits of fp/simd
7266 register(s). */
7272 /* Likewise pure scalable types for SVE vector and predicate registers. */
7273 pure_scalable_type_info pst_info;
7278 }
7280 /* Implement TARGET_FUNCTION_VALUE.
7281 Define how to find the value returned by a function. */
7283 static rtx
7286 {
7287 machine_mode mode;
7294 pure_scalable_type_info pst_info;
7298 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
7299 are returned in memory, not by value. */
7304 {
7308 {
7311 }
7312 }
7315 machine_mode ag_mode;
7318 {
7321 {
7324 }
7331 else
7332 {
7334 rtx par;
7338 {
7343 }
7345 }
7346 }
7347 else
7348 {
7350 {
7351 /* Vector types can acquire a partial SVE mode using things like
7352 __attribute__((vector_size(N))), and this is potentially useful.
7353 However, the choice of mode doesn't affect the type's ABI
7354 identity, so we should treat the types as though they had
7355 the associated integer mode, just like they did before SVE
7356 was introduced.
7358 We know that the vector must be 128 bits or smaller,
7359 otherwise we'd have returned it in memory instead. */
7368 }
7370 }
7371 }
7373 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
7374 Return true if REGNO is the number of a hard register in which the values
7375 of called function may come back. */
7377 static bool
7379 {
7380 /* Maximum of 16 bytes can be returned in the general registers. Examples
7381 of 16-byte return values are: 128-bit integers and 16-byte small
7382 structures (excluding homogeneous floating-point aggregates). */
7386 /* Up to four fp/simd registers can return a function value, e.g. a
7387 homogeneous floating-point aggregate having four members. */
7395 }
7397 /* Subroutine for aarch64_return_in_memory for types that are not returned
7398 in SVE registers. */
7400 static bool
7402 {
7403 HOST_WIDE_INT size;
7404 machine_mode ag_mode;
7410 /* Simple scalar types always returned in registers. */
7417 /* Types larger than 2 registers returned in memory. */
7420 }
7422 /* Implement TARGET_RETURN_IN_MEMORY.
7424 If the type T of the result of a function is such that
7425 void func (T arg)
7426 would require that arg be passed as a value in a register (or set of
7427 registers) according to the parameter passing rules, then the result
7428 is returned in the same registers as would be used for such an
7429 argument. */
7431 static bool
7433 {
7434 pure_scalable_type_info pst_info;
7436 {
7448 }
7450 }
7452 static bool
7455 {
7460 }
7462 /* Given MODE and TYPE of a function argument, return the alignment in
7463 bits. The idea is to suppress any stronger alignment requested by
7464 the user and opt for the natural alignment (specified in AAPCS64 \S
7465 4.1). ABI_BREAK is set to the old alignment if the alignment was
7466 incorrectly calculated in versions of GCC prior to GCC-9.
7467 ABI_BREAK_PACKED is set to the old alignment if it was incorrectly
7468 calculated in versions between GCC-9 and GCC-13. This is a helper
7469 function for local use only. */
7471 static unsigned int
7475 {
7487 {
7488 /* The ABI alignment is the natural alignment of the type, without
7489 any attributes applied. Normally this is the alignment of the
7490 TYPE_MAIN_VARIANT, but not always; see PR108910 for a counterexample.
7491 For now we just handle the known exceptions explicitly. */
7494 {
7497 }
7500 }
7510 {
7511 /* Note that we explicitly consider zero-sized fields here,
7512 even though they don't map to AAPCS64 machine types.
7513 For example, in:
7515 struct __attribute__((aligned(8))) empty {};
7517 struct s {
7518 [[no_unique_address]] empty e;
7519 int x;
7520 };
7522 "s" contains only one Fundamental Data Type (the int field)
7523 but gains 8-byte alignment and size thanks to "e". */
7526 {
7527 /* Take the bit-field type's alignment into account only
7528 if the user didn't reduce this field's alignment with
7529 the packed attribute. */
7531 bitfield_alignment
7535 /* Compute the alignment even if the bit-field is
7536 packed, so that we can emit a warning in case the
7537 alignment changed between GCC versions. */
7538 bitfield_alignment_with_packed
7541 }
7542 }
7544 /* Emit a warning if the alignment is different when taking the
7545 'packed' attribute into account. */
7551 {
7554 }
7557 }
7559 /* Layout a function argument according to the AAPCS64 rules. The rule
7560 numbers refer to the rule numbers in the AAPCS64. ORIG_MODE is the
7561 mode that was originally given to us by the target hook, whereas the
7562 mode in ARG might be the result of replacing partial SVE modes with
7563 the equivalent integer mode. */
7565 static void
7567 {
7573 HOST_WIDE_INT size;
7577 /* We need to do this once per argument. */
7581 bool warn_pcs_change
7582 = (warn_psabi
7584 && (currently_expanding_function_start
7587 /* HFAs and HVAs can have an alignment greater than 16 bytes. For example:
7589 typedef struct foo {
7590 __Int8x16_t foo[2] __attribute__((aligned(32)));
7591 } foo;
7593 is still a HVA despite its larger-than-normal alignment.
7594 However, such over-aligned HFAs and HVAs are guaranteed to have
7595 no padding.
7597 If we exclude HFAs and HVAs from the discussion below, then there
7598 are several things to note:
7600 - Both the C and AAPCS64 interpretations of a type's alignment should
7601 give a value that is no greater than the type's size.
7603 - Types bigger than 16 bytes are passed indirectly.
7605 - If an argument of type T is passed indirectly, TYPE and MODE describe
7606 a pointer to T rather than T iself.
7608 It follows that the AAPCS64 alignment of TYPE must be no greater
7609 than 16 bytes.
7611 Versions prior to GCC 9.1 ignored a bitfield's underlying type
7612 and so could calculate an alignment that was too small. If this
7613 happened for TYPE then ABI_BREAK is this older, too-small alignment.
7615 Although GCC 9.1 fixed that bug, it introduced a different one:
7616 it would consider the alignment of a bitfield's underlying type even
7617 if the field was packed (which should have the effect of overriding
7618 the alignment of the underlying type). This was fixed in GCC 13.1.
7620 As a result of this bug, GCC 9 to GCC 12 could calculate an alignment
7621 that was too big. If this happened for TYPE, ABI_BREAK_PACKED is
7622 this older, too-big alignment.
7624 Also, the fact that GCC 9 to GCC 12 considered irrelevant
7625 alignments meant they could calculate type alignments that were
7626 bigger than the type's size, contrary to the assumption above.
7627 The handling of register arguments was nevertheless (and justifiably)
7628 written to follow the assumption that the alignment can never be
7629 greater than the size. The same was not true for stack arguments;
7630 their alignment was instead handled by MIN bounds in
7631 aarch64_function_arg_boundary.
7633 The net effect is that, if GCC 9 to GCC 12 incorrectly calculated
7634 an alignment of more than 16 bytes for TYPE then:
7636 - If the argument was passed in registers, these GCC versions
7637 would treat the alignment as though it was *less than* 16 bytes.
7639 - If the argument was passed on the stack, these GCC versions
7640 would treat the alignment as though it was *equal to* 16 bytes.
7642 Both behaviors were wrong, but in different cases. */
7646 pure_scalable_type_info pst_info;
7648 {
7649 /* aarch64_function_arg_alignment has never had an effect on
7650 this case. */
7652 /* The PCS says that it is invalid to pass an SVE value to an
7653 unprototyped function. There is no ABI-defined location we
7654 can return in this case, so we have no real choice but to raise
7655 an error immediately, even though this is only a query function. */
7657 {
7661 /* Avoid repeating the message, and avoid tripping the assert
7662 below. */
7664 }
7666 /* We would have converted the argument into pass-by-reference
7667 form if it didn't fit in registers. */
7677 }
7679 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
7680 are passed by reference, not by value. */
7684 /* Vector types can acquire a partial SVE mode using things like
7685 __attribute__((vector_size(N))), and this is potentially useful.
7686 However, the choice of mode doesn't affect the type's ABI
7687 identity, so we should treat the types as though they had
7688 the associated integer mode, just like they did before SVE
7689 was introduced.
7691 We know that the vector must be 128 bits or smaller,
7692 otherwise we'd have passed it in memory instead. */
7697 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
7700 else
7701 /* No frontends can create types with variable-sized modes, so we
7702 shouldn't be asked to pass or return them. */
7708 mode,
7709 type,
7713 unsigned int alignment
7721 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
7722 The following code thus handles passing by SIMD/FP registers first. */
7726 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
7727 and homogenous short-vector aggregates (HVA). */
7729 {
7730 /* aarch64_function_arg_alignment has never had an effect on
7731 this case. */
7736 {
7739 {
7742 }
7749 else
7750 {
7751 rtx par;
7755 {
7758 rtx offset = gen_int_mode
7762 }
7764 }
7766 }
7767 else
7768 {
7769 /* C.3 NSRN is set to 8. */
7772 }
7773 }
7778 /* C6 - C9. though the sign and zero extension semantics are
7779 handled elsewhere. This is the case where the argument fits
7780 entirely general registers. */
7782 {
7785 /* C.8 if the argument has an alignment of 16 then the NGRN is
7786 rounded up to the next even number. */
7789 {
7790 /* Emit a warning if the alignment changed when taking the
7791 'packed' attribute into account. */
7793 && abi_break_packed
7799 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
7800 comparison is there because for > 16 * BITS_PER_UNIT
7801 alignment nregs should be > 2 and therefore it should be
7802 passed by reference rather than value. */
7804 {
7810 }
7811 }
7813 /* If an argument with an SVE mode needs to be shifted up to the
7814 high part of the register, treat it as though it had an integer mode.
7815 Using the normal (parallel [...]) would suppress the shifting. */
7817 && BYTES_BIG_ENDIAN
7820 {
7823 }
7825 /* NREGS can be 0 when e.g. an empty structure is to be passed.
7826 A reg is still generated for it, but the caller should be smart
7827 enough not to use it. */
7832 else
7833 {
7834 rtx par;
7839 {
7847 }
7849 }
7853 }
7855 /* C.11 */
7858 /* The argument is passed on stack; record the needed number of words for
7859 this argument and align the total size if necessary. */
7860 on_stack:
7864 && abi_break_packed
7871 {
7874 {
7879 }
7880 }
7882 }
7884 /* Implement TARGET_FUNCTION_ARG. */
7886 static rtx
7888 {
7899 }
7901 void
7903 const_tree fntype,
7904 rtx libname ATTRIBUTE_UNUSED,
7905 const_tree fndecl ATTRIBUTE_UNUSED,
7908 {
7917 else
7926 && !TARGET_FLOAT
7928 {
7935 }
7938 && !TARGET_SVE
7940 {
7941 /* We can't gracefully recover at this point, so make this a
7942 fatal error. */
7945 fndecl);
7946 else
7949 }
7950 }
7952 static void
7955 {
7960 {
7971 }
7972 }
7974 bool
7976 {
7980 }
7982 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
7983 PARM_BOUNDARY bits of alignment, but will be given anything up
7984 to STACK_BOUNDARY bits if the type requires it. This makes sure
7985 that both before and after the layout of each argument, the Next
7986 Stacked Argument Address (NSAA) will have a minimum alignment of
7987 8 bytes. */
7989 static unsigned int
7991 {
7997 /* We rely on aarch64_layout_arg and aarch64_gimplify_va_arg_expr
7998 to emit warnings about ABI incompatibility. */
8001 }
8003 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
8005 static fixed_size_mode
8007 {
8009 /* Don't use the SVE part of the register for __builtin_apply and
8010 __builtin_return. The SVE registers aren't used by the normal PCS,
8011 so using them there would be a waste of time. The PCS extensions
8012 for SVE types are fundamentally incompatible with the
8013 __builtin_return/__builtin_apply interface. */
8016 /* For SVE PR regs, indicate that they should be ignored for
8017 __builtin_apply/__builtin_return. */
8020 }
8022 /* Implement TARGET_FUNCTION_ARG_PADDING.
8024 Small aggregate types are placed in the lowest memory address.
8026 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
8028 static pad_direction
8030 {
8031 /* On little-endian targets, the least significant byte of every stack
8032 argument is passed at the lowest byte address of the stack slot. */
8036 /* Otherwise, integral, floating-point and pointer types are padded downward:
8037 the least significant byte of a stack argument is passed at the highest
8038 byte address of the stack slot. */
8045 /* Everything else padded upward, i.e. data in first byte of stack slot. */
8047 }
8049 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
8051 It specifies padding for the last (may also be the only)
8052 element of a block move between registers and memory. If
8053 assuming the block is in the memory, padding upward means that
8054 the last element is padded after its highest significant byte,
8055 while in downward padding, the last element is padded at the
8056 its least significant byte side.
8058 Small aggregates and small complex types are always padded
8059 upwards.
8061 We don't need to worry about homogeneous floating-point or
8062 short-vector aggregates; their move is not affected by the
8063 padding direction determined here. Regardless of endianness,
8064 each element of such an aggregate is put in the least
8065 significant bits of a fp/simd register.
8067 Return !BYTES_BIG_ENDIAN if the least significant byte of the
8068 register has useful data, and return the opposite if the most
8069 significant byte does. */
8071 bool
8074 {
8076 /* Aside from pure scalable types, small composite types are always
8077 padded upward. */
8079 {
8080 HOST_WIDE_INT size;
8083 else
8084 /* No frontends can create types with variable-sized modes, so we
8085 shouldn't be asked to pass or return them. */
8088 {
8089 pure_scalable_type_info pst_info;
8093 }
8094 }
8096 /* Otherwise, use the default padding. */
8098 }
8100 static scalar_int_mode
8102 {
8104 }
8106 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
8108 /* We use the 12-bit shifted immediate arithmetic instructions so values
8109 must be multiple of (1 << 12), i.e. 4096. */
8110 #define ARITH_FACTOR 4096
8112 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
8113 #error Cannot use simple address calculation for stack probing
8114 #endif
8116 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
8117 inclusive. These are offsets from the current stack pointer. */
8119 static void
8121 {
8122 HOST_WIDE_INT size;
8124 {
8127 }
8131 /* See the same assertion on PROBE_INTERVAL above. */
8134 /* See if we have a constant small number of probes to generate. If so,
8135 that's the easy case. */
8137 {
8144 }
8146 /* The run-time loop is made up of 8 insns in the generic case while the
8147 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
8149 {
8154 stack_pointer_rtx,
8158 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
8159 it exceeds SIZE. If only two probes are needed, this will not
8160 generate any code. Then probe at FIRST + SIZE. */
8162 {
8166 }
8170 {
8175 }
8176 else
8178 }
8180 /* Otherwise, do the same as above, but in a loop. Note that we must be
8181 extra careful with variables wrapping around because we might be at
8182 the very top (or the very bottom) of the address space and we have
8183 to be able to handle this case properly; in particular, we use an
8184 equality test for the loop condition. */
8185 else
8186 {
8189 /* Step 1: round SIZE to the previous multiple of the interval. */
8194 /* Step 2: compute initial and final value of the loop counter. */
8196 /* TEST_ADDR = SP + FIRST. */
8200 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
8203 {
8207 }
8208 else
8212 /* Step 3: the loop
8214 do
8215 {
8216 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
8217 probe at TEST_ADDR
8218 }
8219 while (TEST_ADDR != LAST_ADDR)
8221 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
8222 until it is equal to ROUNDED_SIZE. */
8227 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
8228 that SIZE is equal to ROUNDED_SIZE. */
8231 {
8235 {
8240 }
8241 else
8243 }
8244 }
8246 /* Make sure nothing is scheduled before we are done. */
8248 }
8250 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
8251 absolute addresses. */
8255 {
8262 /* Loop. */
8265 HOST_WIDE_INT stack_clash_probe_interval
8268 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
8270 HOST_WIDE_INT interval;
8273 else
8281 /* If doing stack clash protection then we probe up by the ABI specified
8282 amount. We do this because we're dropping full pages at a time in the
8283 loop. But if we're doing non-stack clash probing, probe at SP 0. */
8286 else
8289 /* Probe at TEST_ADDR. If we're inside the loop it is always safe to probe
8290 by this amount for each iteration. */
8293 /* Test if TEST_ADDR == LAST_ADDR. */
8297 /* Branch. */
8303 }
8305 /* Emit the probe loop for doing stack clash probes and stack adjustments for
8306 SVE. This emits probes from BASE to BASE - ADJUSTMENT based on a guard size
8307 of GUARD_SIZE. When a probe is emitted it is done at most
8308 MIN_PROBE_THRESHOLD bytes from the current BASE at an interval of
8309 at most MIN_PROBE_THRESHOLD. By the end of this function
8310 BASE = BASE - ADJUSTMENT. */
8315 {
8316 /* This function is not allowed to use any instruction generation function
8317 like gen_ and friends. If you do you'll likely ICE during CFG validation,
8318 so instead emit the code you want using output_asm_insn. */
8323 /* The minimum required allocation before the residual requires probing. */
8326 /* Clamp the value down to the nearest value that can be used with a cmp. */
8341 /* Emit loop start label. */
8344 /* ADJUSTMENT < RESIDUAL_PROBE_GUARD. */
8349 /* Branch to end if not enough adjustment to probe. */
8354 /* BASE = BASE - RESIDUAL_PROBE_GUARD. */
8359 /* Probe at BASE. */
8363 /* ADJUSTMENT = ADJUSTMENT - RESIDUAL_PROBE_GUARD. */
8368 /* Branch to start if still more bytes to allocate. */
8373 /* No probe leave. */
8376 /* BASE = BASE - ADJUSTMENT. */
8381 }
8383 /* Determine whether a frame chain needs to be generated. */
8384 static bool
8386 {
8387 /* Force a frame chain for EH returns so the return address is at FP+8. */
8391 /* A leaf function cannot have calls or write LR. */
8394 /* Don't use a frame chain in leaf functions if leaf frame pointers
8395 are disabled. */
8400 }
8402 /* Mark the registers that need to be saved by the callee and calculate
8403 the size of the callee-saved registers area and frame record (both FP
8404 and LR may be omitted). */
8405 static void
8407 {
8417 /* Adjust the outgoing arguments size if required. Keep it in sync with what
8418 the mid-end is doing. */
8421 #define SLOT_NOT_REQUIRED (-2)
8422 #define SLOT_REQUIRED (-1)
8428 /* First mark all the registers that really need to be saved... */
8432 /* ... that includes the eh data registers (if needed)... */
8437 /* ... and any callee saved register that dataflow says is live. */
8449 {
8454 }
8456 /* Big-endian SVE frames need a spare predicate register in order
8457 to save Z8-Z15. Decide which register they should use. Prefer
8458 an unused argument register if possible, so that we don't force P4
8459 to be saved unnecessarily. */
8463 {
8472 }
8480 /* With stack-clash, LR must be saved in non-leaf functions. The saving of
8481 LR counts as an implicit probe which allows us to maintain the invariant
8482 described in the comment at expand_prologue. */
8486 /* Now assign stack slots for the registers. Start with the predicate
8487 registers, since predicate LDR and STR have a relatively small
8488 offset range. These saves happen below the hard frame pointer. */
8491 {
8494 }
8497 {
8498 /* If we have any vector registers to save above the predicate registers,
8499 the offset of the vector register save slots need to be a multiple
8500 of the vector size. This lets us use the immediate forms of LDR/STR
8501 (or LD1/ST1 for big-endian).
8503 A vector register is 8 times the size of a predicate register,
8504 and we need to save a maximum of 12 predicate registers, so the
8505 first vector register will be at either #1, MUL VL or #2, MUL VL.
8507 If we don't have any vector registers to save, and we know how
8508 big the predicate save area is, we can just round it up to the
8509 next 16-byte boundary. */
8512 else
8513 {
8518 else
8520 }
8521 }
8523 /* If we need to save any SVE vector registers, add them next. */
8527 {
8530 }
8532 /* OFFSET is now the offset of the hard frame pointer from the bottom
8533 of the callee save area. */
8537 {
8538 /* FP and LR are placed in the linkage record. */
8544 }
8548 {
8555 }
8563 {
8564 /* If there is an alignment gap between integer and fp callee-saves,
8565 allocate the last fp register to it if possible. */
8567 && has_align_gap
8570 {
8573 }
8582 }
8590 poly_int64 above_outgoing_args
8595 frame.hard_fp_offset
8598 /* Both these values are already aligned. */
8614 /* Shadow call stack only deals with functions where the LR is pushed
8615 onto the stack and without specifying the "no_sanitize" attribute
8616 with the argument "shadow-call-stack". */
8617 frame.is_scs_enabled
8622 /* When shadow call stack is enabled, the scs_pop in the epilogue will
8623 restore x30, and we don't need to pop x30 again in the traditional
8624 way. Pop candidates record the registers that need to be popped
8625 eventually. */
8627 {
8632 }
8634 /* If candidate2 is INVALID_REGNUM, we need to adjust max_push_offset to
8635 256 to ensure that the offset meets the requirements of emit_move_insn.
8636 Similarly, if candidate1 is INVALID_REGNUM, we need to set
8637 max_push_offset to 0, because no registers are popped at this time,
8638 so callee_adjust cannot be adjusted. */
8646 HOST_WIDE_INT const_saved_regs_size;
8650 {
8651 /* Simple, small frame with no outgoing arguments:
8653 stp reg1, reg2, [sp, -frame_size]!
8654 stp reg3, reg4, [sp, 16] */
8656 }
8660 /* We could handle this case even with outgoing args, provided
8661 that the number of args left us with valid offsets for all
8662 predicate and vector save slots. It's such a rare case that
8663 it hardly seems worth the effort though. */
8668 {
8669 /* Frame with small outgoing arguments:
8671 sub sp, sp, frame_size
8672 stp reg1, reg2, [sp, outgoing_args_size]
8673 stp reg3, reg4, [sp, outgoing_args_size + 16] */
8676 }
8680 {
8681 /* Frame in which all saves are SVE saves:
8683 sub sp, sp, hard_fp_offset + below_hard_fp_saved_regs_size
8684 save SVE registers relative to SP
8685 sub sp, sp, outgoing_args_size */
8689 }
8692 {
8693 /* Frame with large outgoing arguments or SVE saves, but with
8694 a small local area:
8696 stp reg1, reg2, [sp, -hard_fp_offset]!
8697 stp reg3, reg4, [sp, 16]
8698 [sub sp, sp, below_hard_fp_saved_regs_size]
8699 [save SVE registers relative to SP]
8700 sub sp, sp, outgoing_args_size */
8704 }
8705 else
8706 {
8707 /* Frame with large local area and outgoing arguments or SVE saves,
8708 using frame pointer:
8710 sub sp, sp, hard_fp_offset
8711 stp x29, x30, [sp, 0]
8712 add x29, sp, 0
8713 stp reg3, reg4, [sp, 16]
8714 [sub sp, sp, below_hard_fp_saved_regs_size]
8715 [save SVE registers relative to SP]
8716 sub sp, sp, outgoing_args_size */
8720 }
8722 /* Make sure the individual adjustments add up to the full frame size. */
8729 {
8730 /* We've decided not to associate any register saves with the initial
8731 stack allocation. */
8734 }
8737 }
8739 /* Return true if the register REGNO is saved on entry to
8740 the current function. */
8742 static bool
8744 {
8746 }
8748 /* Return the next register up from REGNO up to LIMIT for the callee
8749 to save. */
8751 static unsigned
8753 {
8755 regno ++;
8757 }
8759 /* Push the register number REGNO of mode MODE to the stack with write-back
8760 adjusting the stack by ADJUSTMENT. */
8762 static void
8764 HOST_WIDE_INT adjustment)
8765 {
8776 }
8778 /* Generate and return an instruction to store the pair of registers
8779 REG and REG2 of mode MODE to location BASE with write-back adjusting
8780 the stack location BASE by ADJUSTMENT. */
8782 static rtx
8784 HOST_WIDE_INT adjustment)
8785 {
8787 {
8802 }
8803 }
8805 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
8806 stack pointer by ADJUSTMENT. */
8808 static void
8810 {
8825 }
8827 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
8828 adjusting it by ADJUSTMENT afterwards. */
8830 static rtx
8832 HOST_WIDE_INT adjustment)
8833 {
8835 {
8847 }
8848 }
8850 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
8851 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
8852 into CFI_OPS. */
8854 static void
8857 {
8864 {
8868 }
8869 else
8870 {
8875 }
8876 }
8878 /* Generate and return a store pair instruction of mode MODE to store
8879 register REG1 to MEM1 and register REG2 to MEM2. */
8881 static rtx
8883 rtx reg2)
8884 {
8886 {
8904 }
8905 }
8907 /* Generate and regurn a load pair isntruction of mode MODE to load register
8908 REG1 from MEM1 and register REG2 from MEM2. */
8910 static rtx
8912 rtx mem2)
8913 {
8915 {
8930 }
8931 }
8933 /* Return TRUE if return address signing should be enabled for the current
8934 function, otherwise return FALSE. */
8936 bool
8938 {
8939 /* This function should only be called after frame laid out. */
8942 /* Turn return address signing off in any function that uses
8943 __builtin_eh_return. The address passed to __builtin_eh_return
8944 is not signed so either it has to be signed (with original sp)
8945 or the code path that uses it has to avoid authenticating it.
8946 Currently eh return introduces a return to anywhere gadget, no
8947 matter what we do here since it uses ret with user provided
8948 address. An ideal fix for that is to use indirect branch which
8949 can be protected with BTI j (to some extent). */
8953 /* If signing scope is AARCH_FUNCTION_NON_LEAF, we only sign a leaf function
8954 if its LR is pushed onto stack. */
8958 }
8960 /* Only used by the arm backend. */
8962 {}
8964 /* Return TRUE if Branch Target Identification Mechanism is enabled. */
8965 bool
8967 {
8969 }
8971 /* Check if INSN is a BTI J insn. */
8972 bool
8974 {
8980 }
8982 /* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */
8983 bool
8985 {
8991 {
8994 {
8997 {
9004 }
9006 }
9007 }
9009 }
9012 {
9014 }
9017 {
9019 }
9021 /* The caller is going to use ST1D or LD1D to save or restore an SVE
9022 register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in
9023 the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by:
9025 (1) updating BASE_RTX + OFFSET so that it is a legitimate ST1D
9026 or LD1D address
9028 (2) setting PRED to a valid predicate register for the ST1D or LD1D,
9029 if the variable isn't already nonnull
9031 (1) is needed when OFFSET is in the range [8, 16] * GET_MODE_SIZE (MODE).
9032 Handle this case using a temporary base register that is suitable for
9033 all offsets in that range. Use ANCHOR_REG as this base register if it
9034 is nonnull, otherwise create a new register and store it in ANCHOR_REG. */
9040 {
9042 {
9043 /* This is the maximum valid offset of the anchor from the base.
9044 Lower values would be valid too. */
9047 {
9051 }
9054 }
9056 {
9061 }
9062 }
9064 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
9065 is saved at BASE + OFFSET. */
9067 static void
9070 {
9074 }
9076 /* Emit code to save the callee-saved registers from register number START
9077 to LIMIT to the stack at the location starting at offset START_OFFSET,
9078 skipping any write-back candidates if SKIP_WB is true. HARD_FP_VALID_P
9079 is true if the hard frame pointer has been set up. */
9081 static void
9085 {
9094 {
9096 poly_int64 offset;
9113 HOST_WIDE_INT const_offset;
9119 {
9121 poly_int64 fp_offset
9125 else
9126 {
9128 {
9132 }
9134 }
9136 }
9146 {
9148 rtx mem2;
9153 reg2));
9155 /* The first part of a frame-related parallel insn is
9156 always assumed to be relevant to the frame
9157 calculations; subsequent parts, are only
9158 frame-related if explicitly marked. */
9160 {
9164 else
9166 }
9169 }
9171 {
9174 }
9177 else
9183 }
9184 }
9186 /* Emit code to restore the callee registers from register number START
9187 up to and including LIMIT. Restore from the stack offset START_OFFSET,
9188 skipping any write-back candidates if SKIP_WB is true. Write the
9189 appropriate REG_CFA_RESTORE notes into CFI_OPS. */
9191 static void
9194 {
9197 poly_int64 offset;
9203 {
9230 {
9232 rtx mem2;
9240 }
9245 else
9249 }
9250 }
9252 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
9253 of MODE. */
9257 {
9258 HOST_WIDE_INT multiple;
9261 }
9263 /* Return true if OFFSET is a signed 6-bit value multiplied by the size
9264 of MODE. */
9268 {
9269 HOST_WIDE_INT multiple;
9272 }
9274 /* Return true if OFFSET is an unsigned 6-bit value multiplied by the size
9275 of MODE. */
9279 {
9280 HOST_WIDE_INT multiple;
9283 }
9285 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
9286 of MODE. */
9288 bool
9290 {
9291 HOST_WIDE_INT multiple;
9294 }
9296 /* Return true if OFFSET is a signed 9-bit value. */
9298 bool
9300 poly_int64 offset)
9301 {
9302 HOST_WIDE_INT const_offset;
9305 }
9307 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
9308 of MODE. */
9312 {
9313 HOST_WIDE_INT multiple;
9316 }
9318 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
9319 of MODE. */
9323 {
9324 HOST_WIDE_INT multiple;
9327 }
9329 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
9331 static sbitmap
9333 {
9337 /* The registers we need saved to the frame. */
9340 {
9341 /* Punt on saves and restores that use ST1D and LD1D. We could
9342 try to be smarter, but it would involve making sure that the
9343 spare predicate register itself is safe to use at the save
9344 and restore points. Also, when a frame pointer is being used,
9345 the slots are often out of reach of ST1D and LD1D anyway. */
9352 /* If the register is saved in the first SVE save slot, we use
9353 it as a stack probe for -fstack-clash-protection. */
9359 /* Get the offset relative to the register we'll use. */
9362 else
9365 /* Check that we can access the stack slot of the register with one
9366 direct load with no adjustments needed. */
9371 }
9373 /* Don't mess with the hard frame pointer. */
9377 /* If the spare predicate register used by big-endian SVE code
9378 is call-preserved, it must be saved in the main prologue
9379 before any saves that use it. */
9385 /* If registers have been chosen to be stored/restored with
9386 writeback don't interfere with them to avoid having to output explicit
9387 stack adjustment instructions. */
9397 }
9399 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
9401 static sbitmap
9403 {
9411 /* Clobbered registers don't generate values in any meaningful sense,
9412 since nothing after the clobber can rely on their value. And we can't
9413 say that partially-clobbered registers are unconditionally killed,
9414 because whether they're killed or not depends on the mode of the
9415 value they're holding. Thus partially call-clobbered registers
9416 appear in neither the kill set nor the gen set.
9418 Check manually for any calls that clobber more of a register than the
9419 current function can. */
9420 function_abi_aggregator callee_abis;
9427 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
9435 {
9438 /* If there is a callee-save at an adjacent offset, add it too
9439 to increase the use of LDP/STP. */
9444 {
9450 }
9451 }
9454 }
9456 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
9457 Nothing to do for aarch64. */
9459 static void
9461 {
9462 }
9464 /* Return the next set bit in BMP from START onwards. Return the total number
9465 of bits in BMP if no set bit is found at or after START. */
9467 static unsigned int
9469 {
9480 }
9482 /* Do the work for aarch64_emit_prologue_components and
9483 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
9484 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
9485 for these components or the epilogue sequence. That is, it determines
9486 whether we should emit stores or loads and what kind of CFA notes to attach
9487 to the insns. Otherwise the logic for the two sequences is very
9488 similar. */
9490 static void
9492 {
9494 ? HARD_FRAME_POINTER_REGNUM
9502 {
9510 else
9518 /* No more registers to handle after REGNO.
9519 Emit a single save/restore and exit. */
9521 {
9524 {
9528 else
9530 }
9532 }
9535 /* The next register is not of the same class or its offset is not
9536 mergeable with the current one into a pair. */
9543 {
9546 {
9550 else
9552 }
9556 }
9560 /* REGNO2 can be saved/restored in a pair with REGNO. */
9564 else
9573 else
9577 {
9580 {
9585 }
9586 else
9587 {
9592 }
9593 }
9596 }
9597 }
9599 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
9601 static void
9603 {
9605 }
9607 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
9609 static void
9611 {
9613 }
9615 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
9617 static void
9619 {
9623 }
9625 /* On AArch64 we have an ABI defined safe buffer. This constant is used to
9626 determining the probe offset for alloca. */
9628 static HOST_WIDE_INT
9630 {
9632 }
9635 /* Allocate POLY_SIZE bytes of stack space using TEMP1 and TEMP2 as scratch
9636 registers. If POLY_SIZE is not large enough to require a probe this function
9637 will only adjust the stack. When allocating the stack space
9638 FRAME_RELATED_P is then used to indicate if the allocation is frame related.
9639 FINAL_ADJUSTMENT_P indicates whether we are allocating the outgoing
9640 arguments. If we are then we ensure that any allocation larger than the ABI
9641 defined buffer needs a probe so that the invariant of having a 1KB buffer is
9642 maintained.
9644 We emit barriers after each stack adjustment to prevent optimizations from
9645 breaking the invariant that we never drop the stack more than a page. This
9646 invariant is needed to make it easier to correctly handle asynchronous
9647 events, e.g. if we were to allow the stack to be dropped by more than a page
9648 and then have multiple probes up and we take a signal somewhere in between
9649 then the signal handler doesn't know the state of the stack and can make no
9650 assumptions about which pages have been probed. */
9652 static void
9654 poly_int64 poly_size,
9657 {
9658 HOST_WIDE_INT guard_size
9661 HOST_WIDE_INT min_probe_threshold
9662 = (final_adjustment_p
9663 ? guard_used_by_caller
9665 /* When doing the final adjustment for the outgoing arguments, take into
9666 account any unprobed space there is above the current SP. There are
9667 two cases:
9669 - When saving SVE registers below the hard frame pointer, we force
9670 the lowest save to take place in the prologue before doing the final
9671 adjustment (i.e. we don't allow the save to be shrink-wrapped).
9672 This acts as a probe at SP, so there is no unprobed space.
9674 - When there are no SVE register saves, we use the store of the link
9675 register as a probe. We can't assume that LR was saved at position 0
9676 though, so treat any space below it as unprobed. */
9679 {
9683 else
9685 }
9689 /* We should always have a positive probe threshold. */
9693 {
9699 {
9701 }
9705 {
9707 }
9708 }
9710 /* If SIZE is not large enough to require probing, just adjust the stack and
9711 exit. */
9714 {
9717 }
9719 HOST_WIDE_INT size;
9720 /* Handle the SVE non-constant case first. */
9722 {
9724 {
9728 }
9730 /* First calculate the amount of bytes we're actually spilling. */
9737 {
9738 /* This is done to provide unwinding information for the stack
9739 adjustments we're about to do, however to prevent the optimizers
9740 from removing the R11 move and leaving the CFA note (which would be
9741 very wrong) we tie the old and new stack pointer together.
9742 The tie will expand to nothing but the optimizers will not touch
9743 the instruction. */
9748 /* We want the CFA independent of the stack pointer for the
9749 duration of the loop. */
9752 }
9761 /* Now reset the CFA register if needed. */
9763 {
9768 }
9771 }
9775 "Stack clash AArch64 prologue: " HOST_WIDE_INT_PRINT_DEC
9778 /* Round size to the nearest multiple of guard_size, and calculate the
9779 residual as the difference between the original size and the rounded
9780 size. */
9784 /* We can handle a small number of allocations/probes inline. Otherwise
9785 punt to a loop. */
9787 {
9789 {
9792 guard_used_by_caller));
9794 }
9796 }
9797 else
9798 {
9799 /* Compute the ending address. */
9804 /* For the initial allocation, we don't have a frame pointer
9805 set up, so we always need CFI notes. If we're doing the
9806 final allocation, then we may have a frame pointer, in which
9807 case it is the CFA, otherwise we need CFI notes.
9809 We can determine which allocation we are doing by looking at
9810 the value of FRAME_RELATED_P since the final allocations are not
9811 frame related. */
9813 {
9814 /* We want the CFA independent of the stack pointer for the
9815 duration of the loop. */
9819 }
9821 /* This allocates and probes the stack. Note that this re-uses some of
9822 the existing Ada stack protection code. However we are guaranteed not
9823 to enter the non loop or residual branches of that code.
9825 The non-loop part won't be entered because if our allocation amount
9826 doesn't require a loop, the case above would handle it.
9828 The residual amount won't be entered because TEMP1 is a mutliple of
9829 the allocation size. The residual will always be 0. As such, the only
9830 part we are actually using from that code is the loop setup. The
9831 actual probing is done in aarch64_output_probe_stack_range. */
9835 /* Now reset the CFA register if needed. */
9837 {
9841 }
9845 }
9847 /* Handle any residuals. Residuals of at least MIN_PROBE_THRESHOLD have to
9848 be probed. This maintains the requirement that each page is probed at
9849 least once. For initial probing we probe only if the allocation is
9850 more than GUARD_SIZE - buffer, and for the outgoing arguments we probe
9851 if the amount is larger than buffer. GUARD_SIZE - buffer + buffer ==
9852 GUARD_SIZE. This works that for any allocation that is large enough to
9853 trigger a probe here, we'll have at least one, and if they're not large
9854 enough for this code to emit anything for them, The page would have been
9855 probed by the saving of FP/LR either by this function or any callees. If
9856 we don't have any callees then we won't have more stack adjustments and so
9857 are still safe. */
9859 {
9861 /* If we're doing final adjustments, and we've done any full page
9862 allocations then any residual needs to be probed. */
9865 /* If doing a small final adjustment, we always probe at offset 0.
9866 This is done to avoid issues when LR is not at position 0 or when
9867 the final adjustment is smaller than the probing offset. */
9873 {
9876 "Stack clash AArch64 prologue residuals: "
9877 HOST_WIDE_INT_PRINT_DEC " bytes, probing will be required."
9881 residual_probe_offset));
9883 }
9884 }
9885 }
9887 /* Return 1 if the register is used by the epilogue. We need to say the
9888 return register is used, but only after epilogue generation is complete.
9889 Note that in the case of sibcalls, the values "used by the epilogue" are
9890 considered live at the start of the called function.
9892 For SIMD functions we need to return 1 for FP registers that are saved and
9893 restored by a function but are not zero in call_used_regs. If we do not do
9894 this optimizations may remove the restore of the register. */
9896 int
9898 {
9900 {
9903 }
9905 }
9907 /* AArch64 stack frames generated by this compiler look like:
9909 +-------------------------------+
9910 | |
9911 | incoming stack arguments |
9912 | |
9913 +-------------------------------+
9914 | | <-- incoming stack pointer (aligned)
9915 | callee-allocated save area |
9916 | for register varargs |
9917 | |
9918 +-------------------------------+
9919 | local variables | <-- frame_pointer_rtx
9920 | |
9921 +-------------------------------+
9922 | padding | \
9923 +-------------------------------+ |
9924 | callee-saved registers | | frame.saved_regs_size
9925 +-------------------------------+ |
9926 | LR' | |
9927 +-------------------------------+ |
9928 | FP' | |
9929 +-------------------------------+ |<- hard_frame_pointer_rtx (aligned)
9930 | SVE vector registers | | \
9931 +-------------------------------+ | | below_hard_fp_saved_regs_size
9932 | SVE predicate registers | / /
9933 +-------------------------------+
9934 | dynamic allocation |
9935 +-------------------------------+
9936 | padding |
9937 +-------------------------------+
9938 | outgoing stack arguments | <-- arg_pointer
9939 | |
9940 +-------------------------------+
9941 | | <-- stack_pointer_rtx (aligned)
9943 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
9944 but leave frame_pointer_rtx and hard_frame_pointer_rtx
9945 unchanged.
9947 By default for stack-clash we assume the guard is at least 64KB, but this
9948 value is configurable to either 4KB or 64KB. We also force the guard size to
9949 be the same as the probing interval and both values are kept in sync.
9951 With those assumptions the callee can allocate up to 63KB (or 3KB depending
9952 on the guard size) of stack space without probing.
9954 When probing is needed, we emit a probe at the start of the prologue
9955 and every PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE bytes thereafter.
9957 We have to track how much space has been allocated and the only stores
9958 to the stack we track as implicit probes are the FP/LR stores.
9960 For outgoing arguments we probe if the size is larger than 1KB, such that
9961 the ABI specified buffer is maintained for the next callee.
9963 The following registers are reserved during frame layout and should not be
9964 used for any other purpose:
9966 - r11: Used by stack clash protection when SVE is enabled, and also
9967 as an anchor register when saving and restoring registers
9968 - r12(EP0) and r13(EP1): Used as temporaries for stack adjustment.
9969 - r14 and r15: Used for speculation tracking.
9970 - r16(IP0), r17(IP1): Used by indirect tailcalls.
9971 - r30(LR), r29(FP): Used by standard frame layout.
9973 These registers must be avoided in frame layout related code unless the
9974 explicit intention is to interact with one of the features listed above. */
9976 /* Generate the prologue instructions for entry into a function.
9977 Establish the stack frame by decreasing the stack pointer with a
9978 properly calculated size and, if necessary, create a frame record
9979 filled with the values of LR and previous frame pointer. The
9980 current FP is also set up if it is in use. */
9982 void
9984 {
9991 poly_int64 below_hard_fp_saved_regs_size
9999 {
10000 /* Fold the SVE allocation into the initial allocation.
10001 We don't do this in aarch64_layout_arg to avoid pessimizing
10002 the epilogue code. */
10005 }
10007 /* Sign return address for functions. */
10009 {
10011 {
10020 }
10023 }
10025 /* Push return address to shadow call stack. */
10033 {
10035 {
10039 (frame_size
10041 }
10044 }
10049 /* In theory we should never have both an initial adjustment
10050 and a callee save adjustment. Verify that is the case since the
10051 code below does not handle it for -fstack-clash-protection. */
10054 /* Will only probe if the initial adjustment is larger than the guard
10055 less the amount of the guard reserved for use by the caller's
10056 outgoing args. */
10063 /* The offset of the frame chain record (if any) from the current SP. */
10068 /* The offset of the bottom of the save area from the current SP. */
10072 {
10074 {
10079 }
10080 else
10086 {
10087 /* Variable-sized frames need to describe the save slot
10088 address using DW_CFA_expression rather than DW_CFA_offset.
10089 This means that, without taking further action, the
10090 locations of the registers that we've already saved would
10091 remain based on the stack pointer even after we redefine
10092 the CFA based on the frame pointer. We therefore need new
10093 DW_CFA_expressions to re-express the save slots with addresses
10094 based on the frame pointer. */
10098 /* Add an explicit CFA definition if this was previously
10099 implicit. */
10101 {
10103 callee_offset);
10106 }
10108 /* Change the save slot expressions for the registers that
10109 we've already saved. */
10114 }
10116 }
10120 emit_frame_chain);
10122 {
10126 sve_callee_adjust,
10129 }
10134 emit_frame_chain);
10136 /* We may need to probe the final adjustment if it is larger than the guard
10137 that is assumed by the called. */
10140 }
10142 /* Return TRUE if we can use a simple_return insn.
10144 This function checks whether the callee saved stack is empty, which
10145 means no restore actions are need. The pro_and_epilogue will use
10146 this to check whether shrink-wrapping opt is feasible. */
10148 bool
10150 {
10158 }
10160 /* Generate the epilogue instructions for returning from a function.
10161 This is almost exactly the reverse of the prolog sequence, except
10162 that we need to insert barriers to avoid scheduling loads that read
10163 from a deallocated stack, and we optimize the unwind records by
10164 emitting them all together if possible. */
10165 void
10167 {
10173 poly_int64 below_hard_fp_saved_regs_size
10181 /* A stack clash protection prologue may not have left EP0_REGNUM or
10182 EP1_REGNUM in a usable state. The same is true for allocations
10183 with an SVE component, since we then need both temporary registers
10184 for each allocation. For stack clash we are in a usable state if
10185 the adjustment is less than GUARD_SIZE - GUARD_USED_BY_CALLER. */
10186 HOST_WIDE_INT guard_size
10190 /* We can re-use the registers when:
10192 (a) the deallocation amount is the same as the corresponding
10193 allocation amount (which is false if we combine the initial
10194 and SVE callee save allocations in the prologue); and
10196 (b) the allocation amount doesn't need a probe (which is false
10197 if the amount is guard_size - guard_used_by_caller or greater).
10199 In such situations the register should remain live with the correct
10200 value. */
10203 && (!flag_stack_clash_protection
10208 /* We need to add memory barrier to prevent read from deallocated stack. */
10209 bool need_barrier_p
10213 /* Emit a barrier to prevent loads from a deallocated stack. */
10217 {
10220 }
10222 /* Restore the stack pointer from the frame pointer if it may not
10223 be the same as the stack pointer. */
10228 /* If writeback is used when restoring callee-saves, the CFA
10229 is restored on the instruction doing the writeback. */
10231 hard_frame_pointer_rtx,
10234 else
10235 /* The case where we need to re-use the register here is very rare, so
10236 avoid the complicated condition and just always emit a move if the
10237 immediate doesn't fit. */
10240 /* Restore the vector registers before the predicate registers,
10241 so that we can use P4 as a temporary for big-endian SVE frames. */
10249 /* When shadow call stack is enabled, the scs_pop in the epilogue will
10250 restore x30, we don't need to restore x30 again in the traditional
10251 way. */
10262 /* If we have no register restore information, the CFA must have been
10263 defined in terms of the stack pointer since the end of the prologue. */
10267 {
10268 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
10274 }
10276 /* Liveness of EP0_REGNUM can not be trusted across function calls either, so
10277 add restriction on emit_move optimization to leaf functions. */
10283 {
10284 /* Emit delayed restores and reset the CFA to be SP. */
10289 }
10291 /* Pop return address from shadow call stack. */
10293 {
10300 }
10302 /* We prefer to emit the combined return/authenticate instruction RETAA,
10303 however there are three cases in which we must instead emit an explicit
10304 authentication instruction.
10306 1) Sibcalls don't return in a normal way, so if we're about to call one
10307 we must authenticate.
10309 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
10310 generating code for !TARGET_ARMV8_3 we can't use it and must
10311 explicitly authenticate.
10312 */
10315 {
10317 {
10326 }
10329 }
10331 /* Stack adjustment for exception handler. */
10333 {
10334 /* We need to unwind the stack by the offset computed by
10335 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
10336 to be SP; letting the CFA move during this adjustment
10337 is just as correct as retaining the CFA from the body
10338 of the function. Therefore, do nothing special. */
10340 }
10345 }
10347 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
10348 normally or return to a previous frame after unwinding.
10350 An EH return uses a single shared return sequence. The epilogue is
10351 exactly like a normal epilogue except that it has an extra input
10352 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
10353 that must be applied after the frame has been destroyed. An extra label
10354 is inserted before the epilogue which initializes this register to zero,
10355 and this is the entry point for a normal return.
10357 An actual EH return updates the return address, initializes the stack
10358 adjustment and jumps directly into the epilogue (bypassing the zeroing
10359 of the adjustment). Since the return address is typically saved on the
10360 stack when a function makes a call, the saved LR must be updated outside
10361 the epilogue.
10363 This poses problems as the store is generated well before the epilogue,
10364 so the offset of LR is not known yet. Also optimizations will remove the
10365 store as it appears dead, even after the epilogue is generated (as the
10366 base or offset for loading LR is different in many cases).
10368 To avoid these problems this implementation forces the frame pointer
10369 in eh_return functions so that the location of LR is fixed and known early.
10370 It also marks the store volatile, so no optimization is permitted to
10371 remove the store. */
10372 rtx
10374 {
10378 /* Mark the store volatile, so no optimization is permitted to remove it. */
10381 }
10383 /* Output code to add DELTA to the first argument, and then jump
10384 to FUNCTION. Used for C++ multiple inheritance. */
10385 static void
10387 HOST_WIDE_INT delta,
10388 HOST_WIDE_INT vcall_offset,
10389 tree function)
10390 {
10391 /* The this pointer is always in x0. Note that this differs from
10392 Arm where the this pointer maybe bumped to r1 if r0 is required
10393 to return a pointer to an aggregate. On AArch64 a result value
10394 pointer will be in x8. */
10412 else
10413 {
10418 {
10422 else
10425 }
10429 else
10436 else
10437 {
10439 Pmode);
10441 }
10445 else
10451 }
10453 /* Generate a tail call to the target function. */
10455 {
10458 }
10474 /* Stop pretending to be a post-reload pass. */
10476 }
10478 static bool
10480 {
10485 {
10489 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
10490 TLS offsets, not real symbol references. */
10493 }
10495 }
10498 static bool
10500 {
10504 /* There's no way to calculate VL-based values using relocations. */
10510 poly_int64 offset;
10513 {
10514 /* We checked for POLY_INT_CST offsets above. */
10518 else
10519 /* Avoid generating a 64-bit relocation in ILP32; leave
10520 to aarch64_expand_mov_immediate to handle it properly. */
10522 }
10525 }
10527 /* Implement TARGET_CASE_VALUES_THRESHOLD.
10528 The expansion for a table switch is quite expensive due to the number
10529 of instructions, the table lookup and hard to predict indirect jump.
10530 When optimizing for speed, and -O3 enabled, use the per-core tuning if
10531 set, otherwise use tables for >= 11 cases as a tradeoff between size and
10532 performance. When optimizing for size, use 8 for smallest codesize. */
10534 static unsigned int
10536 {
10537 /* Use the specified limit for the number of cases before using jump
10538 tables at higher optimization levels. */
10542 else
10544 }
10546 /* Return true if register REGNO is a valid index register.
10547 STRICT_P is true if REG_OK_STRICT is in effect. */
10549 bool
10551 {
10553 {
10561 }
10563 }
10565 /* Return true if register REGNO is a valid base register for mode MODE.
10566 STRICT_P is true if REG_OK_STRICT is in effect. */
10568 bool
10570 {
10572 {
10580 }
10582 /* The fake registers will be eliminated to either the stack or
10583 hard frame pointer, both of which are usually valid base registers.
10584 Reload deals with the cases where the eliminated form isn't valid. */
10589 }
10591 /* Return true if X is a valid base register for mode MODE.
10592 STRICT_P is true if REG_OK_STRICT is in effect. */
10594 static bool
10596 {
10603 }
10605 /* Return true if address offset is a valid index. If it is, fill in INFO
10606 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
10608 static bool
10611 {
10613 rtx index;
10616 /* (reg:P) */
10619 {
10623 }
10624 /* (sign_extend:DI (reg:SI)) */
10629 {
10634 }
10635 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
10642 {
10647 }
10648 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
10655 {
10660 }
10661 /* (and:DI (mult:DI (reg:DI) (const_int scale))
10662 (const_int 0xffffffff<<shift)) */
10669 {
10675 }
10676 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
10677 (const_int 0xffffffff<<shift)) */
10684 {
10690 }
10691 /* (mult:P (reg:P) (const_int scale)) */
10696 {
10700 }
10701 /* (ashift:P (reg:P) (const_int shift)) */
10706 {
10710 }
10711 else
10720 {
10724 }
10725 else
10726 {
10731 }
10735 {
10740 }
10743 }
10745 /* Return true if MODE is one of the modes for which we
10746 support LDP/STP operations. */
10748 static bool
10750 {
10759 }
10761 /* Return true if REGNO is a virtual pointer register, or an eliminable
10762 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
10763 include stack_pointer or hard_frame_pointer. */
10764 static bool
10766 {
10771 }
10773 /* Return true if X is a valid address of type TYPE for machine mode MODE.
10774 If it is, fill in INFO appropriately. STRICT_P is true if
10775 REG_OK_STRICT is in effect. */
10777 bool
10780 aarch64_addr_query_type type)
10781 {
10784 poly_int64 offset;
10786 HOST_WIDE_INT const_size;
10788 /* Whether a vector mode is partial doesn't affect address legitimacy.
10789 Partial vectors like VNx8QImode allow the same indexed addressing
10790 mode and MUL VL addressing mode as full vectors like VNx16QImode;
10791 in both cases, MUL VL counts multiples of GET_MODE_SIZE. */
10795 /* On BE, we use load/store pair for all large int mode load/stores.
10796 TI/TF/TDmode may also use a load/store pair. */
10805 /* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode
10806 corresponds to the actual size of the memory being loaded/stored and the
10807 mode of the corresponding addressing mode is half of that. */
10809 {
10814 else
10816 }
10824 /* For SVE, only accept [Rn], [Rn, #offset, MUL VL] and [Rn, Rm, LSL #shift].
10825 The latter is not valid for SVE predicates, and that's rejected through
10826 allow_reg_index_p above. */
10831 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
10832 REG addressing. */
10834 && TARGET_SIMD
10835 && !BYTES_BIG_ENDIAN
10843 {
10860 {
10867 }
10872 {
10878 /* TImode, TFmode and TDmode values are allowed in both pairs of X
10879 registers and individual Q registers. The available
10880 address modes are:
10881 X,X: 7-bit signed scaled offset
10882 Q: 9-bit signed offset
10883 We conservatively require an offset representable in either mode.
10884 When performing the check for pairs of X registers i.e. LDP/STP
10885 pass down DImode since that is the natural size of the LDP/STP
10886 instruction memory accesses. */
10896 /* A 7bit offset check because OImode will emit a ldp/stp
10897 instruction (only !TARGET_SIMD or big endian will get here).
10898 For ldp/stp instructions, the offset is scaled for the size of a
10899 single element of the pair. */
10907 /* Three 9/12 bit offsets checks because CImode will emit three
10908 ldr/str instructions (only !TARGET_SIMD or big endian will
10909 get here). */
10925 /* Two 7bit offsets checks because XImode will emit two ldp/stp
10926 instructions (only big endian will get here). */
10938 /* Make "m" use the LD1 offset range for SVE data modes, so
10939 that pre-RTL optimizers like ivopts will work to that
10940 instead of the wider LDR/STR range. */
10947 {
10948 poly_int64 end_offset = (offset
10955 end_offset)));
10956 }
10966 else
10969 }
10972 {
10973 /* Look for base + (scaled/extended) index register. */
10976 {
10979 }
10982 {
10985 }
10986 }
11007 {
11011 /* TImode, TFmode and TDmode values are allowed in both pairs of X
11012 registers and individual Q registers. The available
11013 address modes are:
11014 X,X: 7-bit signed scaled offset
11015 Q: 9-bit signed offset
11016 We conservatively require an offset representable in either mode.
11017 */
11027 else
11029 }
11035 /* load literal: pc-relative constant pool entry. Only supported
11036 for SI mode or larger. */
11042 {
11043 poly_int64 offset;
11049 }
11058 {
11059 poly_int64 offset;
11060 HOST_WIDE_INT const_offset;
11066 {
11067 /* The symbol and offset must be aligned to the access size. */
11073 {
11077 }
11083 else
11092 }
11093 }
11098 }
11099 }
11101 /* Return true if the address X is valid for a PRFM instruction.
11102 STRICT_P is true if we should do strict checking with
11103 aarch64_classify_address. */
11105 bool
11107 {
11110 /* PRFM accepts the same addresses as DImode... */
11115 /* ... except writeback forms. */
11117 }
11119 bool
11121 {
11122 poly_int64 offset;
11125 }
11127 /* Classify the base of symbolic expression X. */
11129 enum aarch64_symbol_type
11131 {
11132 rtx offset;
11136 }
11139 /* Return TRUE if X is a legitimate address for accessing memory in
11140 mode MODE. */
11141 static bool
11143 {
11147 }
11149 /* Return TRUE if X is a legitimate address of type TYPE for accessing
11150 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
11151 bool
11153 aarch64_addr_query_type type)
11154 {
11158 }
11160 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
11162 static bool
11164 poly_int64 orig_offset,
11165 machine_mode mode)
11166 {
11167 HOST_WIDE_INT size;
11169 {
11172 /* A general SVE offset is A * VQ + B. Remove the A component from
11173 coefficient 0 in order to get the constant B. */
11176 /* Split an out-of-range address displacement into a base and
11177 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
11178 range otherwise to increase opportunities for sharing the base
11179 address of different sizes. Unaligned accesses use the signed
11180 9-bit range, TImode/TFmode/TDmode use the intersection of signed
11181 scaled 7-bit and signed 9-bit offset. */
11186 else
11192 /* Split the offset into second_offset and the rest. */
11196 }
11197 else
11198 {
11199 /* Get the mode we should use as the basis of the range. For structure
11200 modes this is the mode of one vector. */
11202 machine_mode step_mode
11205 /* Get the "mul vl" multiplier we'd like to use. */
11209 /* LDR supports a 9-bit range, but the move patterns for
11210 structure modes require all vectors to be in range of the
11211 same base. The simplest way of accomodating that while still
11212 promoting reuse of anchor points between different modes is
11213 to use an 8-bit range unconditionally. */
11215 else
11216 /* Predicates are only handled singly, so we might as well use
11217 the full range. */
11222 /* Convert the "mul vl" multiplier into a byte offset. */
11227 /* Split the offset into second_offset and the rest. */
11231 }
11232 }
11234 /* Return the binary representation of floating point constant VALUE in INTVAL.
11235 If the value cannot be converted, return false without setting INTVAL.
11236 The conversion is done in the given MODE. */
11237 bool
11239 {
11241 /* We make a general exception for 0. */
11243 {
11246 }
11248 scalar_float_mode mode;
11252 /* Only support up to DF mode. */
11264 {
11268 }
11269 else
11274 }
11276 /* Return TRUE if rtx X is an immediate constant that can be moved using a
11277 single MOV(+MOVK) followed by an FMOV. */
11278 bool
11280 {
11285 /* Determine whether it's cheaper to write float constants as
11286 mov/movk pairs over ldr/adrp pairs. */
11292 {
11297 }
11300 }
11302 /* Return TRUE if rtx X is immediate constant 0.0 (but not in Decimal
11303 Floating Point). */
11304 bool
11306 {
11307 /* 0.0 in Decimal Floating Point cannot be represented by #0 or
11308 zr as our callers expect, so no need to check the actual
11309 value if X is of Decimal Floating Point type. */
11316 }
11318 /* Return TRUE if rtx X is immediate constant that fits in a single
11319 MOVI immediate operation. */
11320 bool
11322 {
11326 machine_mode vmode;
11327 scalar_int_mode imode;
11332 {
11336 /* We make a general exception for 0. */
11341 }
11345 else
11348 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
11349 a 128 bit vector mode. */
11356 }
11359 /* Return the fixed registers used for condition codes. */
11361 static bool
11363 {
11367 }
11369 /* This function is used by the call expanders of the machine description.
11370 RESULT is the register in which the result is returned. It's NULL for
11371 "call" and "sibcall".
11372 MEM is the location of the function call.
11373 CALLEE_ABI is a const_int that gives the arm_pcs of the callee.
11374 SIBCALL indicates whether this function call is normal call or sibling call.
11375 It will generate different pattern accordingly. */
11377 void
11379 {
11381 rtvec vec;
11382 machine_mode mode;
11389 /* Decide if we should generate indirect calls by loading the
11390 address of the callee into a register before performing
11391 the branch-and-link. */
11405 else
11410 UNSPEC_CALLEE_ABI);
11416 }
11418 /* Emit call insn with PAT and do aarch64-specific handling. */
11420 void
11422 {
11428 }
11430 machine_mode
11432 {
11436 /* All floating point compares return CCFP if it is an equality
11437 comparison, and CCFPE otherwise. */
11439 {
11441 {
11462 }
11463 }
11465 /* Equality comparisons of short modes against zero can be performed
11466 using the TST instruction with the appropriate bitmask. */
11472 /* Similarly, comparisons of zero_extends from shorter modes can
11473 be performed using an ANDS with an immediate mask. */
11480 /* Zero extracts support equality comparisons. */
11488 /* ANDS/BICS/TST support equality and all signed comparisons. */
11496 /* ADDS/SUBS correctly set N and Z flags. */
11503 /* A compare with a shifted operand. Because of canonicalization,
11504 the comparison will have to be swapped when we emit the assembly
11505 code. */
11513 /* Similarly for a negated operand, but we can only do this for
11514 equalities. */
11521 /* A test for unsigned overflow from an addition. */
11528 /* A test for unsigned overflow from an add with carry. */
11538 /* A test for signed overflow. */
11545 /* For everything else, return CCmode. */
11547 }
11549 static int
11552 int
11554 {
11561 }
11563 static int
11565 {
11567 {
11571 {
11585 }
11590 {
11602 }
11607 {
11619 }
11624 {
11634 }
11639 {
11647 }
11652 {
11658 }
11663 {
11667 }
11672 {
11676 }
11681 {
11685 }
11690 {
11694 }
11699 }
11702 }
11704 bool
11706 HOST_WIDE_INT minval,
11707 HOST_WIDE_INT maxval)
11708 {
11709 rtx elt;
11713 }
11715 bool
11717 {
11719 }
11721 /* Return true if VEC is a constant in which every element is in the range
11722 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
11724 static bool
11726 HOST_WIDE_INT minval,
11727 HOST_WIDE_INT maxval)
11728 {
11740 {
11745 }
11747 }
11749 /* N Z C V. */
11750 #define AARCH64_CC_V 1
11751 #define AARCH64_CC_C (1 << 1)
11752 #define AARCH64_CC_Z (1 << 2)
11753 #define AARCH64_CC_N (1 << 3)
11755 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
11757 {
11774 };
11776 /* Print floating-point vector immediate operand X to F, negating it
11777 first if NEGATE is true. Return true on success, false if it isn't
11778 a constant we can handle. */
11780 static bool
11782 {
11783 rtx elt;
11792 /* Handle the SVE single-bit immediates specially, since they have a
11793 fixed form in the assembly syntax. */
11802 else
11803 {
11809 }
11812 }
11814 /* Return the equivalent letter for size. */
11815 static char
11817 {
11819 {
11825 }
11826 }
11828 /* Print operand X to file F in a target specific manner according to CODE.
11829 The acceptable formatting commands given by CODE are:
11830 'c': An integer or symbol address without a preceding #
11831 sign.
11832 'C': Take the duplicated element in a vector constant
11833 and print it in hex.
11834 'D': Take the duplicated element in a vector constant
11835 and print it as an unsigned integer, in decimal.
11836 'e': Print the sign/zero-extend size as a character 8->b,
11837 16->h, 32->w. Can also be used for masks:
11838 0xff->b, 0xffff->h, 0xffffffff->w.
11839 'I': If the operand is a duplicated vector constant,
11840 replace it with the duplicated scalar. If the
11841 operand is then a floating-point constant, replace
11842 it with the integer bit representation. Print the
11843 transformed constant as a signed decimal number.
11844 'p': Prints N such that 2^N == X (X must be power of 2 and
11845 const int).
11846 'P': Print the number of non-zero bits in X (a const_int).
11847 'H': Print the higher numbered register of a pair (TImode)
11848 of regs.
11849 'm': Print a condition (eq, ne, etc).
11850 'M': Same as 'm', but invert condition.
11851 'N': Take the duplicated element in a vector constant
11852 and print the negative of it in decimal.
11853 'b/h/s/d/q': Print a scalar FP/SIMD register name.
11854 'S/T/U/V': Print a FP/SIMD register name for a register list.
11855 The register printed is the FP/SIMD register name
11856 of X + 0/1/2/3 for S/T/U/V.
11857 'R': Print a scalar Integer/FP/SIMD register name + 1.
11858 'X': Print bottom 16 bits of integer constant in hex.
11859 'w/x': Print a general register name or the zero register
11860 (32-bit or 64-bit).
11861 '0': Print a normal operand, if it's a general register,
11862 then we assume DImode.
11863 'k': Print NZCV for conditional compare instructions.
11864 'A': Output address constant representing the first
11865 argument of X, specifying a relocation offset
11866 if appropriate.
11867 'L': Output constant address specified by X
11868 with a relocation offset if appropriate.
11869 'G': Prints address of X, specifying a PC relative
11870 relocation mode if appropriate.
11871 'y': Output address of LDP or STP - this is used for
11872 some LDP/STPs which don't use a PARALLEL in their
11873 pattern (so the mode needs to be adjusted).
11874 'z': Output address of a typical LDP or STP. */
11876 static void
11878 {
11879 rtx elt;
11881 {
11885 else
11886 {
11887 poly_int64 offset;
11891 else
11893 }
11897 {
11900 {
11903 }
11912 else
11913 {
11916 }
11917 }
11921 {
11925 {
11928 }
11931 }
11936 {
11939 }
11946 {
11949 }
11952 {
11955 }
11961 {
11965 else
11966 {
11969 }
11971 }
11975 {
11977 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
11979 {
11983 }
11986 {
11989 }
11997 else
11999 }
12004 {
12007 }
12013 ;
12014 else
12015 {
12018 }
12027 {
12028 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
12030 }
12039 {
12040 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
12042 }
12056 else
12058 code);
12063 {
12066 }
12071 {
12072 /* Print a replicated constant in hex. */
12074 {
12077 }
12080 }
12084 {
12085 /* Print a replicated constant in decimal, treating it as
12086 unsigned. */
12088 {
12091 }
12094 }
12101 {
12104 }
12107 {
12110 }
12113 {
12116 }
12118 /* Fall through */
12122 {
12125 }
12128 {
12131 {
12134 else
12135 {
12136 char suffix
12141 }
12142 }
12143 else
12162 {
12165 }
12166 /* fall through */
12170 {
12173 }
12179 ;
12180 else
12181 {
12184 }
12188 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
12189 be getting CONST_DOUBLEs holding integers. */
12192 {
12195 }
12197 {
12198 #define buf_size 20
12206 #undef buf_size
12207 }
12213 }
12221 {
12248 }
12254 {
12289 }
12295 {
12301 }
12306 {
12307 HOST_WIDE_INT cond_code;
12310 {
12313 }
12318 }
12323 {
12330 {
12333 }
12337 ? ADDR_QUERY_LDP_STP_N
12340 }
12346 }
12347 }
12349 /* Print address 'x' of a memory access with mode 'mode'.
12350 'op' is the context required by aarch64_classify_address. It can either be
12351 MEM for a normal memory access or PARALLEL for LDP/STP. */
12352 static bool
12354 aarch64_addr_query_type type)
12355 {
12359 /* Check all addresses are Pmode - including ILP32. */
12363 {
12366 }
12370 {
12373 {
12376 }
12380 {
12381 HOST_WIDE_INT vnum
12387 }
12397 else
12406 else
12415 else
12421 /* Writeback is only supported for fixed-width modes. */
12424 {
12447 }
12459 }
12462 }
12464 /* Print address 'x' of a memory access with mode 'mode'. */
12465 static void
12467 {
12470 }
12472 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
12474 static bool
12476 {
12478 {
12481 }
12483 }
12485 bool
12487 {
12494 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
12495 referencing instruction, but they are constant offsets, not
12496 symbols. */
12502 {
12504 {
12510 }
12513 }
12516 }
12518 /* Implement REGNO_REG_CLASS. */
12520 enum reg_class
12522 {
12547 }
12549 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
12550 If OFFSET is out of range, return an offset of an anchor point
12551 that is in range. Return 0 otherwise. */
12553 static HOST_WIDE_INT
12555 machine_mode mode)
12556 {
12557 /* Does it look like we'll need a 16-byte load/store-pair operation? */
12561 /* For offsets that aren't a multiple of the access size, the limit is
12562 -256...255. */
12564 {
12565 /* BLKmode typically uses LDP of X-registers. */
12569 }
12571 /* Small negative offsets are supported. */
12578 /* Use 12-bit offset by access size. */
12580 }
12582 static rtx
12584 {
12585 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
12586 where mask is selected by alignment and size of the offset.
12587 We try to pick as large a range for the offset as possible to
12588 maximize the chance of a CSE. However, for aligned addresses
12589 we limit the range to 4k so that structures with different sized
12590 elements are likely to use the same base. We need to be careful
12591 not to split a CONST for some forms of address expression, otherwise
12592 it will generate sub-optimal code. */
12595 {
12601 {
12605 /* Force any scaling into a temp for CSE. */
12609 /* Let the pointer register be in op0. */
12613 /* If the pointer is virtual or frame related, then we know that
12614 virtual register instantiation or register elimination is going
12615 to apply a second constant. We want the two constants folded
12616 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
12618 {
12622 }
12624 /* Otherwise, in order to encourage CSE (and thence loop strength
12625 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
12629 }
12631 HOST_WIDE_INT size;
12633 {
12635 mode);
12637 {
12641 }
12642 }
12643 }
12646 }
12648 static reg_class_t
12650 reg_class_t rclass,
12651 machine_mode mode,
12653 {
12654 /* Use aarch64_sve_reload_mem for SVE memory reloads that cannot use
12655 LDR and STR. See the comment at the head of aarch64-sve.md for
12656 more details about the big-endian handling. */
12664 {
12667 }
12669 /* If we have to disable direct literal pool loads and stores because the
12670 function is too big, then we need a scratch register. */
12675 {
12678 }
12680 /* Without the TARGET_SIMD instructions we cannot move a Q register
12681 to a Q register directly. We need a scratch. */
12688 && !TARGET_SIMD
12691 {
12694 }
12696 /* A TFmode, TImode or TDmode memory access should be handled via an FP_REGS
12697 because AArch64 has richer addressing modes for LDR/STR instructions
12698 than LDP/STP instructions. */
12709 }
12711 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. */
12713 static bool
12715 reg_class_t class2)
12716 {
12720 {
12721 /* We can't do a 128-bit FPR-to-FPR move without TARGET_SIMD,
12722 so we can't easily split a move involving tuples of 128-bit
12723 vectors. Force the copy through memory instead.
12725 (Tuples of 64-bit vectors are fine.) */
12729 }
12731 }
12733 static bool
12735 {
12738 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
12739 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
12743 }
12745 poly_int64
12747 {
12749 {
12756 }
12759 {
12763 }
12766 }
12769 /* Get return address without mangling. */
12771 rtx
12773 {
12775 /* Note: aarch64_return_address_signing_enabled only
12776 works after cfun->machine->frame.laid_out is set,
12777 so here we don't know if the return address will
12778 be signed or not. */
12783 }
12786 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
12787 previous frame. */
12789 rtx
12791 {
12795 }
12797 static void
12799 {
12800 /* Even if the current function doesn't have branch protection, some
12801 later function might, so since this template is only generated once
12802 we have to add a BTI just in case. */
12806 {
12809 }
12810 else
12811 {
12814 }
12817 /* We always emit a speculation barrier.
12818 This is because the same trampoline template is used for every nested
12819 function. Since nested functions are not particularly common or
12820 performant we don't worry too much about the extra instructions to copy
12821 around.
12822 This is not yet a problem, since we have not yet implemented function
12823 specific attributes to choose between hardening against straight line
12824 speculation or not, but such function specific attributes are likely to
12825 happen in the future. */
12830 }
12832 static void
12834 {
12838 /* Don't need to copy the trailing D-words, we fill those in below. */
12839 /* We create our own memory address in Pmode so that `emit_block_move` can
12840 use parts of the backend which expect Pmode addresses. */
12854 /* XXX We should really define a "clear_cache" pattern and use
12855 gen_clear_cache(). */
12859 a_tramp,
12860 TRAMPOLINE_SIZE));
12861 }
12863 static unsigned char
12865 {
12866 /* ??? Logically we should only need to provide a value when
12867 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
12868 can hold MODE, but at the moment we need to handle all modes.
12869 Just ignore any runtime parts for registers that can't store them. */
12873 {
12904 }
12906 }
12908 static reg_class_t
12910 {
12915 {
12921 }
12923 /* Register eliminiation can result in a request for
12924 SP+constant->FP_REGS. We cannot support such operations which
12925 use SP as source and an FP_REG as destination, so reject out
12926 right now. */
12928 {
12931 /* Look through a possible SUBREG introduced by ILP32. */
12937 POINTER_REGS));
12939 }
12942 }
12944 void
12946 {
12948 }
12950 static void
12952 {
12955 else
12956 {
12958 /* While priority is known to be in range [0, 65535], so 18 bytes
12959 would be enough, the compiler might not know that. To avoid
12960 -Wformat-truncation false positive, use a larger size. */
12967 }
12968 }
12970 static void
12972 {
12975 else
12976 {
12978 /* While priority is known to be in range [0, 65535], so 18 bytes
12979 would be enough, the compiler might not know that. To avoid
12980 -Wformat-truncation false positive, use a larger size. */
12987 }
12988 }
12992 {
12998 {
12999 {
13002 },
13003 {
13006 },
13007 {
13010 },
13011 /* We assume that DImode is only generated when not optimizing and
13012 that we don't really need 64-bit address offsets. That would
13013 imply an object file with 8GB of code in a single function! */
13014 {
13017 }
13018 };
13027 /* Need to implement table size reduction, by chaning the code below. */
13036 operands);
13039 }
13042 /* Return size in bits of an arithmetic operand which is shifted/scaled and
13043 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
13044 operator. */
13046 int
13048 {
13050 {
13053 {
13057 }
13058 }
13060 }
13062 /* Constant pools are per function only when PC relative
13063 literal loads are true or we are in the large memory
13064 model. */
13068 {
13071 }
13073 static bool
13075 {
13076 /* We can't use blocks for constants when we're using a per-function
13077 constant pool. */
13079 }
13081 /* Select appropriate section for constants depending
13082 on where we place literal pools. */
13086 rtx x,
13088 {
13093 }
13095 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
13096 void
13098 HOST_WIDE_INT offset)
13099 {
13100 /* When using per-function literal pools, we must ensure that any code
13101 section is aligned to the minimal instruction length, lest we get
13102 errors from the assembler re "unaligned instructions". */
13105 }
13107 /* Costs. */
13109 /* Helper function for rtx cost calculation. Strip a shift expression
13110 from X. Returns the inner operand if successful, or the original
13111 expression on failure. */
13112 static rtx
13114 {
13117 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
13118 we can convert both to ROR during final output. */
13133 }
13135 /* Helper function for rtx cost calculation. Strip an extend
13136 expression from X. Returns the inner operand if successful, or the
13137 original expression on failure. We deal with a number of possible
13138 canonicalization variations here. If STRIP_SHIFT is true, then
13139 we can strip off a shift also. */
13140 static rtx
13142 {
13143 scalar_int_mode mode;
13157 /* Now handle extended register, as this may also have an optional
13158 left shift by 1..4. */
13173 }
13175 /* Helper function for rtx cost calculation. Strip extension as well as any
13176 inner VEC_SELECT high-half from X. Returns the inner vector operand if
13177 successful, or the original expression on failure. */
13178 static rtx
13180 {
13182 {
13188 }
13190 }
13192 /* Helper function for rtx cost calculation. Strip VEC_DUPLICATE as well as
13193 any subsequent extend and VEC_SELECT from X. Returns the inner scalar
13194 operand if successful, or the original expression on failure. */
13195 static rtx
13197 {
13200 {
13207 }
13209 }
13211 /* Return true iff CODE is a shift supported in combination
13212 with arithmetic instructions. */
13214 static bool
13216 {
13218 }
13221 /* Return true iff X is a cheap shift without a sign extend. */
13223 static bool
13225 {
13251 }
13253 /* Helper function for rtx cost calculation. Calculate the cost of
13254 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
13255 Return the calculated cost of the expression, recursing manually in to
13256 operands where needed. */
13258 static int
13260 {
13274 {
13277 {
13278 /* The select-operand-high-half versions of the instruction have the
13279 same cost as the three vector version - don't add the costs of the
13280 extension or selection into the costs of the multiply. */
13283 /* The by-element versions of the instruction have the same costs as
13284 the normal 3-vector version. We make an assumption that the input
13285 to the VEC_DUPLICATE is already on the FP & SIMD side. This means
13286 costing of a MUL by element pre RA is a bit optimistic. */
13289 }
13293 {
13296 /* This is to catch the SSRA costing currently flowing here. */
13297 else
13299 }
13301 }
13303 /* Integer multiply/fma. */
13305 {
13306 /* The multiply will be canonicalized as a shift, cost it as such. */
13310 {
13314 {
13316 {
13317 /* If the shift is considered cheap,
13318 then don't add any cost. */
13320 ;
13322 /* ARITH + shift-by-register. */
13325 /* ARITH + extended register. We don't have a cost field
13326 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
13328 else
13329 /* ARITH + shift-by-immediate. */
13331 }
13332 else
13333 /* LSL (immediate). */
13336 }
13337 /* Strip extends as we will have costed them in the case above. */
13344 }
13346 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
13347 compound and let the below cases handle it. After all, MNEG is a
13348 special-case alias of MSUB. */
13350 {
13353 }
13355 /* Integer multiplies or FMAs have zero/sign extending variants. */
13360 {
13365 {
13367 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
13369 else
13370 /* MUL/SMULL/UMULL. */
13372 }
13375 }
13377 /* This is either an integer multiply or a MADD. In both cases
13378 we want to recurse and cost the operands. */
13383 {
13385 /* MADD/MSUB. */
13387 else
13388 /* MUL. */
13390 }
13393 }
13394 else
13395 {
13397 {
13398 /* Floating-point FMA/FMUL can also support negations of the
13399 operands, unless the rounding mode is upward or downward in
13400 which case FNMUL is different than FMUL with operand negation. */
13404 {
13409 }
13412 /* FMADD/FNMADD/FNMSUB/FMSUB. */
13414 else
13415 /* FMUL/FNMUL. */
13417 }
13422 }
13423 }
13425 static int
13427 machine_mode mode,
13428 addr_space_t as ATTRIBUTE_UNUSED,
13430 {
13438 {
13440 {
13441 /* This is a CONST or SYMBOL ref which will be split
13442 in a different way depending on the code model in use.
13443 Cost it through the generic infrastructure. */
13445 /* Divide through by the cost of one instruction to
13446 bring it to the same units as the address costs. */
13448 /* The cost is then the cost of preparing the address,
13449 followed by an immediate (possibly 0) offset. */
13451 }
13452 else
13453 {
13454 /* This is most likely a jump table from a case
13455 statement. */
13457 }
13458 }
13461 {
13472 {
13478 else
13480 }
13481 else
13500 }
13504 {
13505 /* For the sake of calculating the cost of the shifted register
13506 component, we can treat same sized modes in the same way. */
13513 else
13514 /* We can't tell, or this is a 128-bit vector. */
13516 }
13519 }
13521 /* Return the cost of a branch. If SPEED_P is true then the compiler is
13522 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
13523 to be taken. */
13525 int
13527 {
13528 /* When optimizing for speed, use the cost of unpredictable branches. */
13534 else
13536 }
13538 /* Return true if X is a zero or sign extract
13539 usable in an ADD or SUB (extended register) instruction. */
13540 static bool
13542 {
13543 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
13544 No shift. */
13550 }
13552 static bool
13554 {
13556 {
13568 }
13569 }
13571 /* Return true iff X is an rtx that will match an extr instruction
13572 i.e. as described in the *extr<mode>5_insn family of patterns.
13573 OP0 and OP1 will be set to the operands of the shifts involved
13574 on success and will be NULL_RTX otherwise. */
13576 static bool
13578 {
13580 scalar_int_mode mode;
13595 {
13596 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
13608 {
13612 }
13613 }
13616 }
13618 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
13619 storing it in *COST. Result is true if the total cost of the operation
13620 has now been calculated. */
13621 static bool
13623 {
13624 rtx inner;
13625 rtx comparator;
13631 {
13635 }
13636 else
13637 {
13641 }
13644 {
13645 /* Conditional branch. */
13648 else
13649 {
13651 {
13653 {
13654 /* TBZ/TBNZ/CBZ/CBNZ. */
13656 /* TBZ/TBNZ. */
13659 else
13660 /* CBZ/CBNZ. */
13664 }
13667 {
13668 /* SUB and SUBS. */
13673 }
13674 }
13676 {
13677 /* TBZ/TBNZ. */
13680 }
13681 }
13682 }
13684 {
13685 /* CCMP. */
13687 {
13688 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
13692 {
13697 else
13699 }
13701 }
13703 /* It's a conditional operation based on the status flags,
13704 so it must be some flavor of CSEL. */
13706 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
13712 {
13713 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
13716 }
13718 {
13721 /* CSINV/NEG with zero extend + const 0 (*csinv3_uxtw_insn3). */
13723 }
13728 }
13730 /* We don't know what this is, cost all operands. */
13732 }
13734 /* Check whether X is a bitfield operation of the form shift + extend that
13735 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
13736 operand to which the bitfield operation is applied. Otherwise return
13737 NULL_RTX. */
13739 static rtx
13741 {
13755 {
13773 }
13776 }
13778 /* Return true if the mask and a shift amount from an RTX of the form
13779 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
13780 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
13782 bool
13784 rtx shft_amnt)
13785 {
13792 }
13794 /* Return true if the masks and a shift amount from an RTX of the form
13795 ((x & MASK1) | ((y << SHIFT_AMNT) & MASK2)) are valid to combine into
13796 a BFI instruction of mode MODE. See *arch64_bfi patterns. */
13798 bool
13803 {
13806 /* Verify that there is no overlap in what bits are set in the two masks. */
13810 /* Verify that mask2 is not all zeros or ones. */
13814 /* The shift amount should always be less than the mode size. */
13817 /* Verify that the mask being shifted is contiguous and would be in the
13818 least significant bits after shifting by shft_amnt. */
13821 }
13823 /* Calculate the cost of calculating X, storing it in *COST. Result
13824 is true if the total cost of the operation has now been calculated. */
13825 static bool
13828 {
13833 scalar_int_mode int_mode;
13835 /* By default, assume that everything has equivalent cost to the
13836 cheapest instruction. Any additional costs are applied as a delta
13837 above this default. */
13841 {
13843 /* The cost depends entirely on the operands to SET. */
13849 {
13852 {
13866 }
13875 /* Fall through. */
13877 /* The cost is one per vector-register copied. */
13879 {
13882 }
13883 /* const0_rtx is in general free, but we will use an
13884 instruction to set a register to 0. */
13886 {
13887 /* The cost is 1 per register copied. */
13890 }
13891 else
13892 /* Cost is just the cost of the RHS of the set. */
13898 /* Bit-field insertion. Strip any redundant widening of
13899 the RHS to meet the width of the target. */
13910 {
13911 /* MOV immediate is assumed to always be cheap. */
13913 }
13914 else
13915 {
13916 /* BFM. */
13920 }
13925 /* We can't make sense of this, assume default cost. */
13928 }
13932 /* If an instruction can incorporate a constant within the
13933 instruction, the instruction's expression avoids calling
13934 rtx_cost() on the constant. If rtx_cost() is called on a
13935 constant, then it is usually because the constant must be
13936 moved into a register by one or more instructions.
13938 The exception is constant 0, which can be expressed
13939 as XZR/WZR and is therefore free. The exception to this is
13940 if we have (set (reg) (const0_rtx)) in which case we must cost
13941 the move. However, we can catch that when we cost the SET, so
13942 we don't need to consider that here. */
13945 else
13946 {
13947 /* To an approximation, building any other constant is
13948 proportionally expensive to the number of instructions
13949 required to build that constant. This is true whether we
13950 are compiling for SPEED or otherwise. */
13955 }
13960 /* First determine number of instructions to do the move
13961 as an integer constant. */
13965 {
13976 }
13979 {
13980 /* mov[df,sf]_aarch64. */
13982 /* FMOV (scalar immediate). */
13985 {
13986 /* This will be a load from memory. */
13989 else
13991 }
13992 else
13993 /* Otherwise this is +0.0. We get this using MOVI d0, #0
13994 or MOV v0.s[0], wzr - neither of which are modeled by the
13995 cost tables. Just use the default cost. */
13996 {
13997 }
13998 }
14004 {
14005 /* For loads we want the base cost of a load, plus an
14006 approximation for the additional cost of the addressing
14007 mode. */
14021 }
14029 {
14031 {
14032 /* FNEG. */
14034 }
14036 }
14039 {
14042 {
14043 /* CSETM. */
14046 }
14048 /* Cost this as SUB wzr, X. */
14052 }
14055 {
14056 /* Support (neg(fma...)) as a single instruction only if
14057 sign of zeros is unimportant. This matches the decision
14058 making in aarch64.md. */
14060 {
14061 /* FNMADD. */
14064 }
14066 {
14067 /* FNMUL. */
14070 }
14072 /* FNEG. */
14075 }
14082 {
14085 else
14087 }
14104 {
14108 }
14111 {
14112 /* TODO: A write to the CC flags possibly costs extra, this
14113 needs encoding in the cost tables. */
14116 /* ANDS. */
14118 {
14121 }
14124 {
14125 /* ADDS (and CMN alias). */
14128 }
14131 {
14132 /* SUBS. */
14135 }
14140 {
14141 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
14142 Handle it here directly rather than going to cost_logic
14143 since we know the immediate generated for the TST is valid
14144 so we can avoid creating an intermediate rtx for it only
14145 for costing purposes. */
14152 }
14155 {
14156 /* CMN. */
14163 }
14165 /* CMP.
14167 Compare can freely swap the order of operands, and
14168 canonicalization puts the more complex operation first.
14169 But the integer MINUS logic expects the shift/extend
14170 operation in op1. */
14173 {
14176 }
14178 }
14181 {
14182 /* FCMP. */
14187 {
14189 /* FCMP supports constant 0.0 for no extra cost. */
14191 }
14193 }
14196 {
14197 /* Vector compare. */
14202 {
14203 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
14204 cost. */
14206 }
14208 }
14212 {
14216 cost_minus:
14218 {
14219 /* SUBL2 and SUBW2. */
14222 {
14223 /* The select-operand-high-half versions of the sub instruction
14224 have the same cost as the regular three vector version -
14225 don't add the costs of the select into the costs of the sub.
14226 */
14229 }
14230 }
14234 /* Detect valid immediates. */
14240 {
14242 /* SUB(S) (immediate). */
14245 }
14247 /* Look for SUB (extended register). */
14250 {
14258 }
14262 /* Cost this as an FMA-alike operation. */
14266 {
14269 speed);
14271 }
14276 {
14278 {
14279 /* Vector SUB. */
14281 }
14283 {
14284 /* SUB(S). */
14286 }
14288 {
14289 /* FSUB. */
14291 }
14292 }
14294 }
14297 {
14298 rtx new_op0;
14303 cost_plus:
14305 {
14306 /* ADDL2 and ADDW2. */
14309 {
14310 /* The select-operand-high-half versions of the add instruction
14311 have the same cost as the regular three vector version -
14312 don't add the costs of the select into the costs of the add.
14313 */
14316 }
14317 }
14321 {
14322 /* CSINC. */
14326 }
14331 {
14335 {
14336 /* ADD (immediate). */
14339 /* Some tunings prefer to not use the VL-based scalar ops.
14340 Increase the cost of the poly immediate to prevent their
14341 formation. */
14346 }
14348 }
14351 {
14352 /* 24-bit add in 2 instructions or 12-bit shifted add. */
14358 }
14362 /* Look for ADD (extended register). */
14365 {
14373 }
14375 /* Strip any extend, leave shifts behind as we will
14376 cost them through mult_cost. */
14381 {
14383 speed);
14385 }
14390 {
14392 {
14393 /* Vector ADD. */
14395 }
14397 {
14398 /* ADD. */
14400 }
14402 {
14403 /* FADD. */
14405 }
14406 }
14408 }
14414 {
14417 else
14419 }
14424 {
14428 {
14431 else
14433 }
14435 }
14438 {
14445 }
14446 /* Fall through. */
14449 cost_logic:
14454 {
14458 }
14466 {
14467 /* This is a UBFM/SBFM. */
14472 }
14475 {
14477 {
14478 /* We have a mask + shift version of a UBFIZ
14479 i.e. the *andim_ashift<mode>_bfiz pattern. */
14483 {
14490 }
14492 {
14493 /* We possibly get the immediate for free, this is not
14494 modelled. */
14501 }
14502 }
14503 else
14504 {
14507 /* Handle ORN, EON, or BIC. */
14513 /* If we had a shift on op0 then this is a logical-shift-
14514 by-register/immediate operation. Otherwise, this is just
14515 a logical operation. */
14517 {
14519 {
14520 /* Shift by immediate. */
14523 else
14525 }
14526 else
14528 }
14530 /* In both cases we want to cost both operands. */
14537 }
14538 }
14546 {
14547 /* Vector NOT. */
14550 }
14552 /* MVN-shifted-reg. */
14554 {
14561 }
14562 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
14563 Handle the second form here taking care that 'a' in the above can
14564 be a shift. */
14566 {
14575 {
14578 else
14580 }
14583 }
14584 /* MVN. */
14593 /* If a value is written in SI mode, then zero extended to DI
14594 mode, the operation will in general be free as a write to
14595 a 'w' register implicitly zeroes the upper bits of an 'x'
14596 register. However, if this is
14598 (set (reg) (zero_extend (reg)))
14600 we must cost the explicit register move. */
14603 {
14606 /* If OP_COST is non-zero, then the cost of the zero extend
14607 is effectively the cost of the inner operation. Otherwise
14608 we have a MOV instruction and we take the cost from the MOV
14609 itself. This is true independently of whether we are
14610 optimizing for space or time. */
14615 }
14617 {
14618 /* All loads can zero extend to any size for free. */
14621 }
14625 {
14630 }
14633 {
14635 {
14636 /* UMOV. */
14638 }
14639 else
14640 {
14641 /* We generate an AND instead of UXTB/UXTH. */
14643 }
14644 }
14649 {
14650 /* LDRSH. */
14652 {
14659 }
14661 }
14665 {
14670 }
14673 {
14676 else
14678 }
14690 {
14692 {
14694 {
14695 /* Vector shift (immediate). */
14697 }
14698 else
14699 {
14700 /* LSL (immediate), ASR (immediate), UBMF, UBFIZ and friends.
14701 These are all aliases. */
14703 }
14704 }
14706 /* We can incorporate zero/sign extend for free. */
14713 }
14714 else
14715 {
14717 {
14719 /* Vector shift (register). */
14721 }
14722 else
14723 {
14725 /* LSLV, ASRV. */
14728 /* The register shift amount may be in a shorter mode expressed
14729 as a lowpart SUBREG. For costing purposes just look inside. */
14736 {
14738 /* We already demanded XEXP (op1, 0) to be REG_P, so
14739 don't recurse into it. */
14741 }
14742 }
14744 }
14750 {
14751 /* LDR. */
14754 }
14757 {
14758 /* ADRP, followed by ADD. */
14762 }
14765 {
14766 /* ADR. */
14769 }
14772 {
14773 /* One extra load instruction, after accessing the GOT. */
14777 }
14782 /* ADRP/ADD (immediate). */
14789 /* UBFX/SBFX. */
14791 {
14794 else
14796 }
14798 /* We can trust that the immediates used will be correct (there
14799 are no by-register forms), so we need only cost op0. */
14805 /* aarch64_rtx_mult_cost always handles recursion to its
14806 operands. */
14810 /* We can expand signed mod by power of 2 using a NEGS, two parallel
14811 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
14812 an unconditional negate. This case should only ever be reached through
14813 the set_smod_pow2_cheap check in expmed.cc. */
14817 {
14818 /* We expand to 4 instructions. Reset the baseline. */
14826 }
14828 /* Fall-through. */
14831 {
14832 /* Slighly prefer UMOD over SMOD. */
14839 }
14846 {
14850 /* There is no integer SQRT, so only DIV and UDIV can get
14851 here. */
14853 /* Slighly prefer UDIV over SDIV. */
14855 else
14857 }
14883 {
14886 else
14888 }
14890 /* FMSUB, FNMADD, and FNMSUB are free. */
14897 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
14898 and the by-element operand as operand 0. */
14902 /* Catch vector-by-element operations. The by-element operand can
14903 either be (vec_duplicate (vec_select (x))) or just
14904 (vec_select (x)), depending on whether we are multiplying by
14905 a vector or a scalar.
14907 Canonicalization is not very good in these cases, FMA4 will put the
14908 by-element operand as operand 0, FNMA4 will have it as operand 1. */
14919 /* If the remaining parameters are not registers,
14920 get the cost to put them into registers. */
14934 {
14936 {
14937 /*Vector truncate. */
14939 }
14940 else
14942 }
14947 {
14949 {
14950 /*Vector conversion. */
14952 }
14953 else
14955 }
14961 /* Strip the rounding part. They will all be implemented
14962 by the fcvt* family of instructions anyway. */
14964 {
14973 }
14976 {
14979 else
14981 }
14983 /* We can combine fmul by a power of 2 followed by a fcvt into a single
14984 fixed-point fcvt. */
14989 {
14993 }
15000 {
15001 /* ABS (vector). */
15004 }
15006 {
15009 /* FABD, which is analogous to FADD. */
15011 {
15018 }
15019 /* Simple FABS is analogous to FNEG. */
15022 }
15023 else
15024 {
15025 /* Integer ABS will either be split to
15026 two arithmetic instructions, or will be an ABS
15027 (scalar), which we don't model. */
15031 }
15037 {
15040 else
15041 {
15042 /* FMAXNM/FMINNM/FMAX/FMIN.
15043 TODO: This may not be accurate for all implementations, but
15044 we do not model this in the cost tables. */
15046 }
15047 }
15051 /* The floating point round to integer frint* instructions. */
15053 {
15058 }
15061 {
15066 }
15071 /* Decompose <su>muldi3_highpart. */
15073 mode == DImode
15074 /* (lshiftrt:TI */
15077 /* (mult:TI */
15079 /* (ANY_EXTEND:TI (reg:DI))
15080 (ANY_EXTEND:TI (reg:DI))) */
15087 /* (const_int 64) */
15090 {
15091 /* UMULH/SMULH. */
15099 }
15102 {
15103 /* Load using MOVI/MVNI. */
15109 }
15111 /* depending on the operation, either DUP or INS.
15112 For now, keep default costing. */
15115 /* Load using a DUP. */
15119 {
15123 /* cost subreg of 0 as free, otherwise as DUP */
15126 ;
15129 else
15132 }
15135 }
15143 }
15145 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
15146 calculated for X. This cost is stored in *COST. Returns true
15147 if the total cost of X was calculated. */
15148 static bool
15151 {
15156 {
15161 }
15164 }
15166 static int
15169 {
15175 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
15184 /* Make RDFFR very expensive. In particular, if we know that the FFR
15185 contains a PTRUE (e.g. after a SETFFR), we must never use RDFFR
15186 as a way of obtaining a PTRUE. */
15192 /* Moving between GPR and stack cost is the same as GP2GP. */
15197 /* To/From the stack register, we move via the gprs. */
15205 {
15206 /* 128-bit operations on general registers require 2 instructions. */
15214 /* When AdvSIMD instructions are disabled it is not possible to move
15215 a 128-bit value directly between Q registers. This is handled in
15216 secondary reload. A general register is used as a scratch to move
15217 the upper DI value and the lower DI value is moved directly,
15218 hence the cost is the sum of three moves. */
15223 }
15233 {
15234 /* Needs a round-trip through memory, which can use LDP/STP for pairs.
15235 The cost must be greater than 2 units to indicate that direct
15236 moves aren't possible. */
15240 }
15243 }
15245 /* Implements TARGET_MEMORY_MOVE_COST. */
15246 static int
15248 {
15267 }
15269 /* Implement TARGET_INIT_BUILTINS. */
15270 static void
15272 {
15275 #ifdef SUBTARGET_INIT_BUILTINS
15276 SUBTARGET_INIT_BUILTINS;
15277 #endif
15278 }
15280 /* Implement TARGET_FOLD_BUILTIN. */
15281 static tree
15283 {
15288 {
15294 }
15296 }
15298 /* Implement TARGET_GIMPLE_FOLD_BUILTIN. */
15299 static bool
15301 {
15308 {
15316 }
15323 }
15325 /* Implement TARGET_EXPAND_BUILTIN. */
15326 static rtx
15328 {
15333 {
15339 }
15341 }
15343 /* Implement TARGET_BUILTIN_DECL. */
15344 static tree
15346 {
15349 {
15355 }
15357 }
15359 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
15360 to optimize 1.0/sqrt. */
15362 static bool
15364 {
15366 && flag_unsafe_math_optimizations
15370 }
15372 /* Function to decide when to use the approximate reciprocal square root
15373 builtin. */
15375 static tree
15377 {
15385 {
15391 }
15393 }
15395 /* Emit code to perform the floating-point operation:
15397 DST = SRC1 * SRC2
15399 where all three operands are already known to be registers.
15400 If the operation is an SVE one, PTRUE is a suitable all-true
15401 predicate. */
15403 static void
15405 {
15410 else
15412 }
15414 /* Emit instruction sequence to compute either the approximate square root
15415 or its approximate reciprocal, depending on the flag RECP, and return
15416 whether the sequence was emitted or not. */
15418 bool
15420 {
15424 {
15427 }
15430 {
15437 || flag_trapping_math
15438 || !flag_unsafe_math_optimizations
15441 }
15442 else
15443 /* Caller assumes we cannot fail. */
15454 {
15455 /* When calculating the approximate square root, compare the
15456 argument with 0.0 and create a mask. */
15459 {
15464 }
15465 else
15466 {
15471 }
15472 }
15474 /* Estimate the approximate reciprocal square root. */
15478 /* Iterate over the series twice for SF and thrice for DF. */
15481 /* Optionally iterate over the series once less for faster performance
15482 while sacrificing the accuracy. */
15485 iterations--;
15487 /* Iterate over the series to calculate the approximate reciprocal square
15488 root. */
15491 {
15499 }
15502 {
15504 /* Multiply nonzero source values by the corresponding intermediate
15505 result elements, so that the final calculation is the approximate
15506 square root rather than its reciprocal. Select a zero result for
15507 zero source values, to avoid the Inf * 0 -> NaN that we'd get
15508 otherwise. */
15511 else
15512 {
15513 /* Qualify the approximate reciprocal square root when the
15514 argument is 0.0 by squashing the intermediary result to 0.0. */
15520 /* Calculate the approximate square root. */
15522 }
15523 }
15525 /* Finalize the approximation. */
15529 }
15531 /* Emit the instruction sequence to compute the approximation for the division
15532 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
15534 bool
15536 {
15547 || flag_trapping_math
15548 || !flag_unsafe_math_optimizations
15560 /* Estimate the approximate reciprocal. */
15564 /* Iterate over the series twice for SF and thrice for DF. */
15567 /* Optionally iterate over the series less for faster performance,
15568 while sacrificing the accuracy. The default is 2 for DF and 1 for SF. */
15571 ? aarch64_double_recp_precision
15574 /* Iterate over the series to calculate the approximate reciprocal. */
15577 {
15582 }
15585 {
15586 /* As the approximate reciprocal of DEN is already calculated, only
15587 calculate the approximate division when NUM is not 1.0. */
15590 }
15592 /* Finalize the approximation. */
15595 }
15597 /* Return the number of instructions that can be issued per cycle. */
15598 static int
15600 {
15602 }
15604 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
15605 static int
15607 {
15619 }
15621 static int
15623 {
15627 }
15630 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
15631 autopref_multipass_dfa_lookahead_guard from haifa-sched.cc. It only
15632 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
15634 static int
15637 {
15639 }
15642 /* Vectorizer cost model target hooks. */
15644 /* If a vld1 from address ADDR should be recorded in vector_load_decls,
15645 return the decl that should be recorded. Return null otherwise. */
15646 tree
15648 {
15655 }
15657 /* Return true if STMT_INFO accesses a decl that is known to be the
15658 argument to a vld1 in the same function. */
15659 static bool
15661 {
15669 }
15671 /* Information about how the CPU would issue the scalar, Advanced SIMD
15672 or SVE version of a vector loop, using the scheme defined by the
15673 aarch64_base_vec_issue_info hierarchy of structures. */
15674 class aarch64_vec_op_count
15675 {
15695 /* The number of individual "general" operations. See the comments
15696 in aarch64_base_vec_issue_info for details. */
15699 /* The number of load and store operations, under the same scheme
15700 as above. */
15704 /* The minimum number of cycles needed to execute all loop-carried
15705 operations, which in the vector code become associated with
15706 reductions. */
15709 /* The number of individual predicate operations. See the comments
15710 in aarch64_sve_vec_issue_info for details. */
15714 /* The issue information for the core. */
15717 /* - If M_VEC_FLAGS is zero then this structure describes scalar code
15718 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then this structure describes
15719 Advanced SIMD code.
15720 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then this structure describes
15721 SVE code. */
15724 /* Assume that, when the code is executing on the core described
15725 by M_ISSUE_INFO, one iteration of the loop will handle M_VF_FACTOR
15726 times more data than the vectorizer anticipates.
15728 This is only ever different from 1 for SVE. It allows us to consider
15729 what would happen on a 256-bit SVE target even when the -mtune
15730 parameters say that the “likely” SVE length is 128 bits. */
15732 };
15740 {
15741 }
15743 /* Return the base issue information (i.e. the parts that make sense
15744 for both scalar and vector code). Return null if we have no issue
15745 information. */
15748 {
15752 }
15754 /* If the structure describes vector code and we have associated issue
15755 information, return that issue information, otherwise return null. */
15758 {
15764 }
15766 /* If the structure describes SVE code and we have associated issue
15767 information, return that issue information, otherwise return null. */
15770 {
15774 }
15776 /* Estimate the minimum number of cycles per iteration needed to rename
15777 the instructions.
15779 ??? For now this is done inline rather than via cost tables, since it
15780 isn't clear how it should be parameterized for the general case. */
15781 fractional_cost
15783 {
15787 /* + 1 for an addition. We've already counted a general op for each
15788 store, so we don't need to account for stores separately. The branch
15789 reads no registers and so does not need to be counted either.
15791 ??? This value is very much on the pessimistic side, but seems to work
15792 pretty well in practice. */
15796 }
15798 /* Like min_cycles_per_iter, but excluding predicate operations. */
15799 fractional_cost
15801 {
15812 }
15814 /* Like min_cycles_per_iter, but including only the predicate operations. */
15815 fractional_cost
15817 {
15821 }
15823 /* Estimate the minimum number of cycles needed to issue the operations.
15824 This is a very simplistic model! */
15825 fractional_cost
15827 {
15830 }
15832 /* Dump information about the structure. */
15833 void
15835 {
15852 {
15854 " estimated min cycles per iteration"
15858 " estimated min cycles per iteration"
15860 }
15865 }
15867 /* Information about vector code that we're in the process of costing. */
15869 {
15884 aarch64_vec_op_count *);
15893 /* True if we have performed one-time initialization based on the
15894 vec_info. */
15897 /* This loop uses an average operation that is not supported by SVE, but is
15898 supported by Advanced SIMD and SVE2. */
15901 /* True if the vector body contains a store to a decl and if the
15902 function is known to have a vld1 from the same decl.
15904 In the Advanced SIMD ACLE, the recommended endian-agnostic way of
15905 initializing a vector is:
15907 float f[4] = { elts };
15908 float32x4_t x = vld1q_f32(f);
15910 We should strongly prefer vectorization of the initialization of f,
15911 so that the store to f and the load back can be optimized away,
15912 leaving a vectorization of { elts }. */
15915 /* - If M_VEC_FLAGS is zero then we're costing the original scalar code.
15916 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then we're costing Advanced
15917 SIMD code.
15918 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then we're costing SVE code. */
15921 /* At the moment, we do not model LDP and STP in the vector and scalar costs.
15922 This means that code such as:
15924 a[0] = x;
15925 a[1] = x;
15927 will be costed as two scalar instructions and two vector instructions
15928 (a scalar_to_vec and an unaligned_store). For SLP, the vector form
15929 wins if the costs are equal, because of the fact that the vector costs
15930 include constant initializations whereas the scalar costs don't.
15931 We would therefore tend to vectorize the code above, even though
15932 the scalar version can use a single STP.
15934 We should eventually fix this and model LDP and STP in the main costs;
15935 see the comment in aarch64_sve_adjust_stmt_cost for some of the problems.
15936 Until then, we look specifically for code that does nothing more than
15937 STP-like operations. We cost them on that basis in addition to the
15938 normal latency-based costs.
15940 If the scalar or vector code could be a sequence of STPs +
15941 initialization, this variable counts the cost of the sequence,
15942 with 2 units per instruction. The variable is ~0U for other
15943 kinds of code. */
15946 /* On some CPUs, SVE and Advanced SIMD provide the same theoretical vector
15947 throughput, such as 4x128 Advanced SIMD vs. 2x256 SVE. In those
15948 situations, we try to predict whether an Advanced SIMD implementation
15949 of the loop could be completely unrolled and become straight-line code.
15950 If so, it is generally better to use the Advanced SIMD version rather
15951 than length-agnostic SVE, since the SVE loop would execute an unknown
15952 number of times and so could not be completely unrolled in the same way.
15954 If we're applying this heuristic, M_UNROLLED_ADVSIMD_NITERS is the
15955 number of Advanced SIMD loop iterations that would be unrolled and
15956 M_UNROLLED_ADVSIMD_STMTS estimates the total number of statements
15957 in the unrolled loop. Both values are zero if we're not applying
15958 the heuristic. */
15962 /* If we're vectorizing a loop that executes a constant number of times,
15963 this variable gives the number of times that the vector loop would
15964 iterate, otherwise it is zero. */
15967 /* Used only when vectorizing loops. Estimates the number and kind of
15968 operations that would be needed by one iteration of the scalar
15969 or vector loop. There is one entry for each tuning option of
15970 interest. */
15972 };
15979 {
15981 {
15984 {
15987 vf_factor });
15988 }
15989 }
15990 }
15992 /* Implement TARGET_VECTORIZE_CREATE_COSTS. */
15993 vector_costs *
15995 {
15997 }
15999 /* Return true if the current CPU should use the new costs defined
16000 in GCC 11. This should be removed for GCC 12 and above, with the
16001 costs applying to all CPUs instead. */
16002 static bool
16004 {
16007 }
16009 /* Return the appropriate SIMD costs for vectors of type VECTYPE. */
16012 {
16019 }
16021 /* Return the appropriate SIMD costs for vectors with VEC_* flags FLAGS. */
16024 {
16029 }
16031 /* If STMT_INFO is a memory reference, return the scalar memory type,
16032 otherwise return null. */
16033 static tree
16035 {
16039 }
16041 /* Decide whether to use the unrolling heuristic described above
16042 m_unrolled_advsimd_niters, updating that field if so. LOOP_VINFO
16043 describes the loop that we're vectorizing. */
16044 void
16047 {
16048 /* The heuristic only makes sense on targets that have the same
16049 vector throughput for SVE and Advanced SIMD. */
16054 /* We only want to apply the heuristic if LOOP_VINFO is being
16055 vectorized for SVE. */
16059 /* Check whether it is possible in principle to use Advanced SIMD
16060 instead. */
16064 /* We don't want to apply the heuristic to outer loops, since it's
16065 harder to track two levels of unrolling. */
16069 /* Only handle cases in which the number of Advanced SIMD iterations
16070 would be known at compile time but the number of SVE iterations
16071 would not. */
16076 /* Guess how many times the Advanced SIMD loop would iterate and make
16077 sure that it is within the complete unrolling limit. Even if the
16078 number of iterations is small enough, the number of statements might
16079 not be, which is why we need to estimate the number of statements too. */
16082 unsigned HOST_WIDE_INT unrolled_advsimd_niters
16087 /* Record that we're applying the heuristic and should try to estimate
16088 the number of statements in the Advanced SIMD loop. */
16090 }
16092 /* Do one-time initialization of the aarch64_vector_costs given that we're
16093 costing the loop vectorization described by LOOP_VINFO. */
16094 void
16096 {
16097 /* Record the number of times that the vector loop would execute,
16098 if known. */
16102 {
16106 else
16108 }
16110 /* Detect whether we're vectorizing for SVE and should apply the unrolling
16111 heuristic described above m_unrolled_advsimd_niters. */
16114 /* Record the issue information for any SVE WHILE instructions that the
16115 loop needs. */
16117 {
16127 }
16128 }
16130 /* Implement targetm.vectorize.builtin_vectorization_cost. */
16131 static int
16133 tree vectype,
16135 {
16146 {
16199 }
16200 }
16202 /* Return true if an access of kind KIND for STMT_INFO represents one
16203 vector of an LD[234] or ST[234] operation. Return the total number of
16204 vectors (2, 3 or 4) if so, otherwise return a value outside that range. */
16205 static int
16207 {
16213 {
16218 }
16220 }
16222 /* Return true if creating multiple copies of STMT_INFO for Advanced SIMD
16223 vectors would produce a series of LDP or STP operations. KIND is the
16224 kind of statement that STMT_INFO represents. */
16225 static bool
16227 stmt_vec_info stmt_info)
16228 {
16230 {
16239 }
16246 }
16248 /* Return true if STMT_INFO is the second part of a two-statement multiply-add
16249 or multiply-subtract sequence that might be suitable for fusing into a
16250 single instruction. If VEC_FLAGS is zero, analyze the operation as
16251 a scalar one, otherwise analyze it as an operation on vectors with those
16252 VEC_* flags. */
16253 static bool
16256 {
16269 {
16271 /* ??? Should we try to check for a single use as well? */
16284 {
16285 /* Scalar and SVE code can tie the result to any FMLA input (or none,
16286 although that requires a MOVPRFX for SVE). However, Advanced SIMD
16287 only supports MLA forms, so will require a move if the result
16288 cannot be tied to the accumulator. The most important case in
16289 which this is true is when the accumulator input is invariant. */
16297 }
16300 }
16302 }
16304 /* We are considering implementing STMT_INFO using SVE. If STMT_INFO is an
16305 in-loop reduction that SVE supports directly, return its latency in cycles,
16306 otherwise return zero. SVE_COSTS specifies the latencies of the relevant
16307 instructions. */
16308 static unsigned int
16310 stmt_vec_info stmt_info,
16312 {
16314 {
16320 {
16333 }
16335 }
16338 }
16340 /* STMT_INFO describes a loop-carried operation in the original scalar code
16341 that we are considering implementing as a reduction. Return one of the
16342 following values, depending on VEC_FLAGS:
16344 - If VEC_FLAGS is zero, return the loop carry latency of the original
16345 scalar operation.
16347 - If VEC_FLAGS & VEC_ADVSIMD, return the loop carry latency of the
16348 Advanced SIMD implementation.
16350 - If VEC_FLAGS & VEC_ANY_SVE, return the loop carry latency of the
16351 SVE implementation. */
16352 static unsigned int
16355 {
16361 /* If the caller is asking for the SVE latency, check for forms of reduction
16362 that only SVE can handle directly. */
16364 {
16365 unsigned int latency
16369 }
16371 /* Handle scalar costs. */
16374 {
16378 }
16380 /* Otherwise, the loop body just contains normal integer or FP operations,
16381 with a vector reduction outside the loop. */
16387 }
16389 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16390 for STMT_INFO, which has cost kind KIND. If this is a scalar operation,
16391 try to subdivide the target-independent categorization provided by KIND
16392 to get a more accurate cost. */
16393 static fractional_cost
16395 stmt_vec_info stmt_info,
16396 fractional_cost stmt_cost)
16397 {
16398 /* Detect an extension of a loaded value. In general, we'll be able to fuse
16399 the extension with the load. */
16404 }
16406 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16407 for the vectorized form of STMT_INFO, which has cost kind KIND and which
16408 when vectorized would operate on vector type VECTYPE. Try to subdivide
16409 the target-independent categorization provided by KIND to get a more
16410 accurate cost. WHERE specifies where the cost associated with KIND
16411 occurs. */
16412 static fractional_cost
16416 fractional_cost stmt_cost)
16417 {
16423 /* It's generally better to avoid costing inductions, since the induction
16424 will usually be hidden by other operations. This is particularly true
16425 for things like COND_REDUCTIONS. */
16429 /* Detect cases in which vec_to_scalar is describing the extraction of a
16430 vector element in preparation for a scalar store. The store itself is
16431 costed separately. */
16435 /* Detect SVE gather loads, which are costed as a single scalar_load
16436 for each element. We therefore need to divide the full-instruction
16437 cost by the number of elements in the vector. */
16439 && sve_costs
16441 {
16446 }
16448 /* Detect cases in which a scalar_store is really storing one element
16449 in a scatter operation. */
16451 && sve_costs
16455 /* Detect cases in which vec_to_scalar represents an in-loop reduction. */
16459 {
16460 unsigned int latency
16464 }
16466 /* Detect cases in which vec_to_scalar represents a single reduction
16467 instruction like FADDP or MAXV. */
16472 {
16497 }
16499 /* Otherwise stick with the original categorization. */
16501 }
16503 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16504 for STMT_INFO, which has cost kind KIND and which when vectorized would
16505 operate on vector type VECTYPE. Adjust the cost as necessary for SVE
16506 targets. */
16507 static fractional_cost
16510 fractional_cost stmt_cost)
16511 {
16512 /* Unlike vec_promote_demote, vector_stmt conversions do not change the
16513 vector register size or number of units. Integer promotions of this
16514 type therefore map to SXT[BHW] or UXT[BHW].
16516 Most loads have extending forms that can do the sign or zero extension
16517 on the fly. Optimistically assume that a load followed by an extension
16518 will fold to this form during combine, and that the extension therefore
16519 comes for free. */
16523 /* For similar reasons, vector_stmt integer truncations are a no-op,
16524 because we can just ignore the unused upper bits of the source. */
16528 /* Advanced SIMD can load and store pairs of registers using LDP and STP,
16529 but there are no equivalent instructions for SVE. This means that
16530 (all other things being equal) 128-bit SVE needs twice as many load
16531 and store instructions as Advanced SIMD in order to process vector pairs.
16533 Also, scalar code can often use LDP and STP to access pairs of values,
16534 so it is too simplistic to say that one SVE load or store replaces
16535 VF scalar loads and stores.
16537 Ideally we would account for this in the scalar and Advanced SIMD
16538 costs by making suitable load/store pairs as cheap as a single
16539 load/store. However, that would be a very invasive change and in
16540 practice it tends to stress other parts of the cost model too much.
16541 E.g. stores of scalar constants currently count just a store,
16542 whereas stores of vector constants count a store and a vec_init.
16543 This is an artificial distinction for AArch64, where stores of
16544 nonzero scalar constants need the same kind of register invariant
16545 as vector stores.
16547 An alternative would be to double the cost of any SVE loads and stores
16548 that could be paired in Advanced SIMD (and possibly also paired in
16549 scalar code). But this tends to stress other parts of the cost model
16550 in the same way. It also means that we can fall back to Advanced SIMD
16551 even if full-loop predication would have been useful.
16553 Here we go for a more conservative version: double the costs of SVE
16554 loads and stores if one iteration of the scalar loop processes enough
16555 elements for it to use a whole number of Advanced SIMD LDP or STP
16556 instructions. This makes it very likely that the VF would be 1 for
16557 Advanced SIMD, and so no epilogue should be needed. */
16559 {
16566 }
16569 }
16571 /* STMT_COST is the cost calculated for STMT_INFO, which has cost kind KIND
16572 and which when vectorized would operate on vector type VECTYPE. Add the
16573 cost of any embedded operations. */
16574 static fractional_cost
16577 {
16579 {
16582 /* Detect cases in which a vector load or store represents an
16583 LD[234] or ST[234] instruction. */
16585 {
16597 }
16601 {
16604 else
16606 }
16607 }
16611 {
16614 else
16616 }
16619 }
16621 /* COUNT, KIND and STMT_INFO are the same as for vector_costs::add_stmt_cost
16622 and they describe an operation in the body of a vector loop. Record issue
16623 information relating to the vector operation in OPS. */
16624 void
16626 stmt_vec_info stmt_info,
16628 {
16635 /* Calculate the minimum cycles per iteration imposed by a reduction
16636 operation. */
16639 {
16640 unsigned int base
16643 /* ??? Ideally we'd do COUNT reductions in parallel, but unfortunately
16644 that's not yet the case. */
16646 }
16648 /* Assume that multiply-adds will become a single operation. */
16652 /* Count the basic operation cost associated with KIND. */
16654 {
16659 /* We currently don't expect these to be used in a loop body. */
16687 }
16689 /* Add any embedded comparison operations. */
16694 /* COND_REDUCTIONS need two sets of VEC_COND_EXPRs, whereas so far we
16695 have only accounted for one. */
16700 /* Count the predicate operations needed by an SVE comparison. */
16703 {
16708 }
16710 /* Add any extra overhead associated with LD[234] and ST[234] operations. */
16713 {
16725 }
16727 /* Add any overhead associated with gather loads and scatter stores. */
16731 {
16735 }
16736 }
16738 /* Return true if STMT_INFO contains a memory access and if the constant
16739 component of the memory address is aligned to SIZE bytes. */
16740 static bool
16742 poly_uint64 size)
16743 {
16750 /* Needed for gathers & scatters, for example. */
16755 }
16757 /* Check if a scalar or vector stmt could be part of a region of code
16758 that does nothing more than store values to memory, in the scalar
16759 case using STP. Return the cost of the stmt if so, counting 2 for
16760 one instruction. Return ~0U otherwise.
16762 The arguments are a subset of those passed to add_stmt_cost. */
16763 unsigned int
16766 {
16767 /* Code that stores vector constants uses a vector_load to create
16768 the constant. We don't apply the heuristic to that case for two
16769 main reasons:
16771 - At the moment, STPs are only formed via peephole2, and the
16772 constant scalar moves would often come between STRs and so
16773 prevent STP formation.
16775 - The scalar code also has to load the constant somehow, and that
16776 isn't costed. */
16778 {
16780 /* Count 2 insns for a GPR->SIMD dup and 1 insn for a FPR->SIMD dup. */
16785 /* Count 1 insn for the maximum number of FP->SIMD INS
16786 instructions. */
16789 /* Count 2 insns for a GPR->SIMD move and 2 insns for the
16790 maximum number of GPR->SIMD INS instructions. */
16795 /* Count 1 insn per vector if we can't form STP Q pairs. */
16803 {
16804 /* Assume we won't be able to use STP if the constant offset
16805 component of the address is misaligned. ??? This could be
16806 removed if we formed STP pairs earlier, rather than relying
16807 on peephole2. */
16811 }
16816 {
16817 /* Check for a mode in which STP pairs can be formed. */
16822 /* Assume we won't be able to use STP if the constant offset
16823 component of the address is misaligned. ??? This could be
16824 removed if we formed STP pairs earlier, rather than relying
16825 on peephole2. */
16828 }
16833 }
16834 }
16836 unsigned
16840 vect_cost_model_location where)
16841 {
16842 fractional_cost stmt_cost
16846 && stmt_info
16849 /* Do one-time initialization based on the vinfo. */
16852 {
16857 }
16859 /* Apply the heuristic described above m_stp_sequence_cost. */
16861 {
16865 }
16867 /* Try to get a more accurate cost by looking at STMT_INFO instead
16868 of just looking at KIND. */
16870 {
16871 /* If we scalarize a strided store, the vectorizer costs one
16872 vec_to_scalar for each element. However, we can store the first
16873 element using an FP store without a separate extract step. */
16884 }
16886 /* Do any SVE-specific adjustments to the cost. */
16892 {
16893 /* Account for any extra "embedded" costs that apply additively
16894 to the base cost calculated above. */
16896 stmt_cost);
16898 /* If we're recording a nonzero vector loop body cost for the
16899 innermost loop, also estimate the operations that would need
16900 to be issued by all relevant implementations of the loop. */
16908 /* If we're applying the SVE vs. Advanced SIMD unrolling heuristic,
16909 estimate the number of statements in the unrolled Advanced SIMD
16910 loop. For simplicitly, we assume that one iteration of the
16911 Advanced SIMD loop would need the same number of statements
16912 as one iteration of the SVE loop. */
16916 /* Detect the use of an averaging operation. */
16920 {
16922 {
16928 }
16929 }
16930 }
16932 /* If the statement stores to a decl that is known to be the argument
16933 to a vld1 in the same function, ignore the store for costing purposes.
16934 See the comment above m_stores_to_vector_load_decl for more details. */
16938 {
16941 }
16944 }
16946 /* Return true if (a) we're applying the Advanced SIMD vs. SVE unrolling
16947 heuristic described above m_unrolled_advsimd_niters and (b) the heuristic
16948 says that we should prefer the Advanced SIMD loop. */
16949 bool
16951 {
16957 " unrolled Advanced SIMD loop = "
16959 m_unrolled_advsimd_stmts);
16961 /* The balance here is tricky. On the one hand, we can't be sure whether
16962 the code is vectorizable with Advanced SIMD or not. However, even if
16963 it isn't vectorizable with Advanced SIMD, there's a possibility that
16964 the scalar code could also be unrolled. Some of the code might then
16965 benefit from SLP, or from using LDP and STP. We therefore apply
16966 the heuristic regardless of can_use_advsimd_p. */
16968 && (m_unrolled_advsimd_stmts
16970 }
16972 /* Subroutine of adjust_body_cost for handling SVE. Use ISSUE_INFO to work out
16973 how fast the SVE code can be issued and compare it to the equivalent value
16974 for scalar code (SCALAR_CYCLES_PER_ITER). If COULD_USE_ADVSIMD is true,
16975 also compare it to the issue rate of Advanced SIMD code
16976 (ADVSIMD_CYCLES_PER_ITER).
16978 ORIG_BODY_COST is the cost originally passed to adjust_body_cost and
16979 *BODY_COST is the current value of the adjusted cost. *SHOULD_DISPARAGE
16980 is true if we think the loop body is too expensive. */
16982 fractional_cost
16985 fractional_cost scalar_cycles_per_iter,
16988 {
16995 /* If the scalar version of the loop could issue at least as
16996 quickly as the predicate parts of the SVE loop, make the SVE loop
16997 prohibitively expensive. In this case vectorization is adding an
16998 overhead that the original scalar code didn't have.
17000 This is mostly intended to detect cases in which WHILELOs dominate
17001 for very tight loops, which is something that normal latency-based
17002 costs would not model. Adding this kind of cliffedge would be
17003 too drastic for scalar_cycles_per_iter vs. sve_cycles_per_iter;
17004 code in the caller handles that case in a more conservative way. */
17007 {
17008 unsigned int min_cost
17011 {
17014 "Increasing body cost to %d because the"
17015 " scalar code could issue within the limit"
17017 min_cost);
17020 }
17021 }
17024 }
17026 unsigned int
17028 {
17030 /* If we are trying to unroll an Advanced SIMD main loop that contains
17031 an averaging operation that we do not support with SVE and we might use a
17032 predicated epilogue, we need to be conservative and block unrolling as
17033 this might lead to a less optimal loop for the first and only epilogue
17034 using the original loop's vectorization factor.
17035 TODO: Remove this constraint when we add support for multiple epilogue
17036 vectorization. */
17042 {
17047 /* Limit unroll factor to a value adjustable by the user, the default
17048 value is 4. */
17050 unsigned int factor
17054 /* Sanity check, this should never happen. */
17058 /* Check stores. */
17060 {
17064 }
17066 /* Check loads + stores. */
17068 {
17072 }
17074 /* Check general ops. */
17076 {
17080 }
17082 }
17084 /* Make sure unroll factor is power of 2. */
17086 }
17088 /* BODY_COST is the cost of a vector loop body. Adjust the cost as necessary
17089 and return the new cost. */
17090 unsigned int
17095 {
17109 fractional_cost scalar_cycles_per_iter
17115 {
17119 m_num_vector_iterations);
17123 " estimated cycles per vector iteration"
17126 }
17129 {
17132 vector_cycles_per_iter
17137 {
17138 /* Also take Neoverse V1 tuning into account, doubling the
17139 scalar and Advanced SIMD estimates to account for the
17140 doubling in SVE vector length. */
17147 }
17148 }
17149 else
17150 {
17152 {
17156 }
17157 }
17159 /* Decide whether to stick to latency-based costs or whether to try to
17160 take issue rates into account. */
17167 {
17170 "Low iteration count, so using pure latency"
17172 }
17173 /* Increase the cost of the vector code if it looks like the scalar code
17174 could issue more quickly. These values are only rough estimates,
17175 so minor differences should only result in minor changes. */
17177 {
17179 scalar_cycles_per_iter);
17182 "Increasing body cost to %d because scalar code"
17184 }
17185 /* In general, it's expected that the proposed vector code would be able
17186 to issue more quickly than the original scalar code. This should
17187 already be reflected to some extent in the latency-based costs.
17189 However, the latency-based costs effectively assume that the scalar
17190 code and the vector code execute serially, which tends to underplay
17191 one important case: if the real (non-serialized) execution time of
17192 a scalar iteration is dominated by loop-carried dependencies,
17193 and if the vector code is able to reduce both the length of
17194 the loop-carried dependencies *and* the number of cycles needed
17195 to issue the code in general, we can be more confident that the
17196 vector code is an improvement, even if adding the other (non-loop-carried)
17197 latencies tends to hide this saving. We therefore reduce the cost of the
17198 vector loop body in proportion to the saving. */
17203 {
17205 scalar_cycles_per_iter);
17208 "Decreasing body cost to %d account for smaller"
17210 }
17213 }
17215 void
17217 {
17222 && m_vec_flags
17224 {
17228 }
17230 /* Apply the heuristic described above m_stp_sequence_cost. Prefer
17231 the scalar code in the event of a tie, since there is more chance
17232 of scalar code being optimized with surrounding operations.
17234 In addition, if the vector body is a simple store to a decl that
17235 is elsewhere loaded using vld1, strongly prefer the vector form,
17236 to the extent of giving the prologue a zero cost. See the comment
17237 above m_stores_to_vector_load_decl for details. */
17239 && scalar_costs
17241 {
17246 }
17249 }
17251 bool
17254 {
17268 /* Apply the unrolling heuristic described above
17269 m_unrolled_advsimd_niters. */
17272 {
17276 {
17279 "Preferring Advanced SIMD loop because"
17282 }
17283 }
17286 {
17288 {
17300 }
17307 /* If it appears that one loop could process the same amount of data
17308 in fewer cycles, prefer that loop over the other one. */
17309 fractional_cost this_cost
17311 fractional_cost other_cost
17314 {
17323 }
17325 {
17328 "Preferring loop with lower cycles"
17331 }
17333 /* If the issue rate of SVE code is limited by predicate operations
17334 (i.e. if sve_pred_cycles_per_iter > sve_nonpred_cycles_per_iter),
17335 and if Advanced SIMD code could issue within the limit imposed
17336 by the predicate operations, the predicate operations are adding an
17337 overhead that the original code didn't have and so we should prefer
17338 the Advanced SIMD version. */
17341 {
17345 {
17348 "Preferring Advanced SIMD loop since"
17351 }
17353 };
17358 }
17361 }
17365 /* Parse the TO_PARSE string and put the architecture struct that it
17366 selects into RES and the architectural features into ISA_FLAGS.
17367 Return an aarch_parse_opt_result describing the parse result.
17368 If there is an error parsing, RES and ISA_FLAGS are left unchanged.
17369 When the TO_PARSE string contains an invalid extension,
17370 a copy of the string is created and stored to INVALID_EXTENSION. */
17372 static enum aarch_parse_opt_result
17376 {
17385 else
17392 /* Loop through the list of supported ARCHes to find a match. */
17394 {
17397 {
17401 {
17402 /* TO_PARSE string contains at least one extension. */
17403 enum aarch_parse_opt_result ext_res
17408 }
17409 /* Extension parsing was successful. Confirm the result
17410 arch and ISA flags. */
17414 }
17415 }
17417 /* ARCH name not found in list. */
17419 }
17421 /* Parse the TO_PARSE string and put the result tuning in RES and the
17422 architecture flags in ISA_FLAGS. Return an aarch_parse_opt_result
17423 describing the parse result. If there is an error parsing, RES and
17424 ISA_FLAGS are left unchanged.
17425 When the TO_PARSE string contains an invalid extension,
17426 a copy of the string is created and stored to INVALID_EXTENSION. */
17428 static enum aarch_parse_opt_result
17432 {
17441 else
17448 /* Loop through the list of supported CPUs to find a match. */
17450 {
17452 {
17456 {
17457 /* TO_PARSE string contains at least one extension. */
17458 enum aarch_parse_opt_result ext_res
17463 }
17464 /* Extension parsing was successfull. Confirm the result
17465 cpu and ISA flags. */
17469 }
17470 }
17472 /* CPU name not found in list. */
17474 }
17476 /* Parse the TO_PARSE string and put the cpu it selects into RES.
17477 Return an aarch_parse_opt_result describing the parse result.
17478 If the parsing fails the RES does not change. */
17480 static enum aarch_parse_opt_result
17482 {
17485 /* Loop through the list of supported CPUs to find a match. */
17487 {
17489 {
17492 }
17493 }
17495 /* CPU name not found in list. */
17497 }
17499 /* Parse TOKEN, which has length LENGTH to see if it is an option
17500 described in FLAG. If it is, return the index bit for that fusion type.
17501 If not, error (printing OPTION_NAME) and return zero. */
17503 static unsigned int
17508 {
17510 {
17514 }
17518 }
17520 /* Parse OPTION which is a comma-separated list of flags to enable.
17521 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
17522 default state we inherit from the CPU tuning structures. OPTION_NAME
17523 gives the top-level option we are parsing in the -moverride string,
17524 for use in error messages. */
17526 static unsigned int
17531 {
17538 {
17541 token_length,
17542 flags,
17543 option_name);
17544 /* If we find "none" (or, for simplicity's sake, an error) anywhere
17545 in the token stream, reset the supported operations. So:
17547 adrp+add.cmp+branch.none.adrp+add
17549 would have the result of turning on only adrp+add fusion. */
17555 }
17557 /* We ended with a comma, print something. */
17559 {
17562 }
17564 /* We still have one more token to parse. */
17567 token_length,
17568 flags,
17569 option_name);
17575 }
17577 /* Support for overriding instruction fusion. */
17579 static void
17582 {
17584 aarch64_fusible_pairs,
17587 }
17589 /* Support for overriding other tuning flags. */
17591 static void
17594 {
17595 tune->extra_tuning_flags
17597 aarch64_tuning_flags,
17600 }
17602 /* Parse the sve_width tuning moverride string in TUNE_STRING.
17603 Accept the valid SVE vector widths allowed by
17604 aarch64_sve_vector_bits_enum and use it to override sve_width
17605 in TUNE. */
17607 static void
17610 {
17615 {
17618 }
17620 {
17629 }
17631 }
17633 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
17634 we understand. If it is, extract the option string and handoff to
17635 the appropriate function. */
17637 void
17641 {
17647 {
17650 }
17652 /* Get the length of the option name. */
17654 /* Skip the '=' to get to the option string. */
17655 option_part++;
17658 {
17660 {
17663 }
17664 }
17668 }
17670 /* A checking mechanism for the implementation of the tls size. */
17672 static void
17674 {
17679 {
17681 /* Both the default and maximum TLS size allowed under tiny is 1M which
17682 needs two instructions to address, so we clamp the size to 24. */
17687 /* The maximum TLS size allowed under small is 4G. */
17692 /* The maximum TLS size allowed under large is 16E.
17693 FIXME: 16E should be 64bit, we only support 48bit offset now. */
17699 }
17702 }
17704 /* Return the CPU corresponding to the enum CPU. */
17708 {
17712 }
17714 /* Return the architecture corresponding to the enum ARCH. */
17718 {
17722 }
17724 /* Parse STRING looking for options in the format:
17725 string :: option:string
17726 option :: name=substring
17727 name :: {a-z}
17728 substring :: defined by option. */
17730 static void
17733 {
17744 {
17746 /* Make this substring look like a string. */
17750 }
17752 /* One last option to parse. */
17755 }
17757 /* Adjust CURRENT_TUNE (a generic tuning struct) with settings that
17758 are best for a generic target with the currently-enabled architecture
17759 extensions. */
17760 static void
17762 {
17763 /* Neoverse V1 is the only core that is known to benefit from
17764 AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. There is therefore no
17765 point enabling it for SVE2 and above. */
17767 current_tune.extra_tuning_flags
17769 }
17771 static void
17773 {
17775 {
17776 opts->x_aarch64_branch_protection_string
17778 }
17780 /* PR 70044: We have to be careful about being called multiple times for the
17781 same function. This means all changes should be repeatable. */
17783 /* Set aarch64_use_frame_pointer based on -fno-omit-frame-pointer.
17784 Disable the frame pointer flag so the mid-end will not use a frame
17785 pointer in leaf functions in order to support -fomit-leaf-frame-pointer.
17786 Set x_flag_omit_frame_pointer to the special value 2 to differentiate
17787 between -fomit-frame-pointer (1) and -fno-omit-frame-pointer (2). */
17792 /* If not optimizing for size, set the default
17793 alignment to what the target wants. */
17795 {
17802 }
17804 /* We default to no pc-relative literal loads. */
17808 /* If -mpc-relative-literal-loads is set on the command line, this
17809 implies that the user asked for PC relative literal loads. */
17813 /* In the tiny memory model it makes no sense to disallow PC relative
17814 literal pool loads. */
17819 /* When enabling the lower precision Newton series for the square root, also
17820 enable it for the reciprocal square root, since the latter is an
17821 intermediary step for the former. */
17824 }
17826 /* 'Unpack' up the internal tuning structs and update the options
17827 in OPTS. The caller must have set up selected_tune and selected_arch
17828 as all the other target-specific codegen decisions are
17829 derived from them. */
17831 void
17833 {
17837 /* Make a copy of the tuning parameters attached to the core, which
17838 we may later overwrite. */
17847 /* This target defaults to strict volatile bitfields. */
17853 {
17856 aarch64_stack_protector_guard_offset_str);
17857 }
17862 {
17864 "%<-mstack-protector-guard-reg%> must be used "
17866 }
17869 {
17872 }
17875 {
17884 }
17895 {
17907 }
17909 /* We don't mind passing in global_options_set here as we don't use
17910 the *options_set structs anyway. */
17914 /* If using Advanced SIMD only for autovectorization disable SVE vector costs
17915 comparison. */
17920 /* Set up parameters to be used in prefetching algorithm. Do not
17921 override the defaults unless we are tuning for a core we have
17922 researched values for. */
17925 param_simultaneous_prefetches,
17929 param_l1_cache_size,
17933 param_l1_cache_line_size,
17937 {
17939 param_destruct_interfere_size,
17942 param_construct_interfere_size,
17944 }
17945 else
17946 {
17947 /* For a generic AArch64 target, cover the current range of cache line
17948 sizes. */
17950 param_destruct_interfere_size,
17953 param_construct_interfere_size,
17955 }
17959 param_l2_cache_size,
17966 param_prefetch_minimum_stride,
17969 /* Use the alternative scheduling-pressure algorithm by default. */
17971 param_sched_pressure_algorithm,
17972 SCHED_PRESSURE_MODEL);
17974 /* Validate the guard size. */
17982 /* Enforce that interval is the same size as size so the mid-end does the
17983 right thing. */
17985 param_stack_clash_protection_probe_interval,
17986 guard_size);
17988 /* The maybe_set calls won't update the value if the user has explicitly set
17989 one. Which means we need to validate that probing interval and guard size
17990 are equal. */
17991 int probe_interval
17997 /* Enable sw prefetching at specified optimization level for
17998 CPUS that have prefetch. Lower optimization level threshold by 1
17999 when profiling is enabled. */
18007 }
18009 /* Print a hint with a suggestion for a core or architecture name that
18010 most closely resembles what the user passed in STR. ARCH is true if
18011 the user is asking for an architecture name. ARCH is false if the user
18012 is asking for a core name. */
18014 static void
18016 {
18022 #ifdef HAVE_LOCAL_CPU_DETECT
18023 /* Add also "native" as possible value. */
18026 #endif
18033 else
18037 }
18039 /* Print a hint with a suggestion for a core name that most closely resembles
18040 what the user passed in STR. */
18044 {
18046 }
18048 /* Print a hint with a suggestion for an architecture name that most closely
18049 resembles what the user passed in STR. */
18053 {
18055 }
18058 /* Print a hint with a suggestion for an extension name
18059 that most closely resembles what the user passed in STR. */
18061 void
18063 {
18071 else
18075 }
18077 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
18078 specified in STR and throw errors if appropriate. Put the results if
18079 they are valid in RES and ISA_FLAGS. Return whether the option is
18080 valid. */
18082 static bool
18085 {
18087 enum aarch_parse_opt_result parse_res
18094 {
18101 /* A common user error is confusing -march and -mcpu.
18102 If the -mcpu string matches a known architecture then suggest
18103 -march=. */
18115 }
18118 }
18120 /* Straight line speculation indicators. */
18121 enum aarch64_sls_hardening_type
18122 {
18127 };
18130 /* Return whether we should mitigatate Straight Line Speculation for the RET
18131 and BR instructions. */
18132 bool
18134 {
18136 }
18138 /* Return whether we should mitigatate Straight Line Speculation for the BLR
18139 instruction. */
18140 bool
18142 {
18144 }
18146 /* As of yet we only allow setting these options globally, in the future we may
18147 allow setting them per function. */
18148 static void
18150 {
18155 {
18158 }
18160 {
18163 }
18172 {
18178 {
18181 }
18182 else
18183 {
18186 }
18188 }
18191 }
18193 /* Validate a command-line -march option. Parse the arch and extensions
18194 (if any) specified in STR and throw errors if appropriate. Put the
18195 results, if they are valid, in RES and ISA_FLAGS. Return whether the
18196 option is valid. */
18198 static bool
18201 {
18203 enum aarch_parse_opt_result parse_res
18210 {
18217 /* A common user error is confusing -march and -mcpu.
18218 If the -march string matches a known CPU suggest -mcpu. */
18230 }
18233 }
18235 /* Validate a command-line -mtune option. Parse the cpu
18236 specified in STR and throw errors if appropriate. Put the
18237 result, if it is valid, in RES. Return whether the option is
18238 valid. */
18240 static bool
18242 {
18243 enum aarch_parse_opt_result parse_res
18250 {
18260 }
18262 }
18264 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
18266 static poly_uint16
18268 {
18269 /* 128-bit SVE and Advanced SIMD modes use different register layouts
18270 on big-endian targets, so we would need to forbid subregs that convert
18271 from one to the other. By default a reinterpret sequence would then
18272 involve a store to memory in one mode and a load back in the other.
18273 Even if we optimize that sequence using reverse instructions,
18274 it would still be a significant potential overhead.
18276 For now, it seems better to generate length-agnostic code for that
18277 case instead. */
18281 else
18283 }
18285 /* Set the global aarch64_asm_isa_flags to FLAGS and update
18286 aarch64_isa_flags accordingly. */
18288 void
18290 {
18292 }
18294 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
18295 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
18296 tuning structs. In particular it must set selected_tune and
18297 aarch64_asm_isa_flags that define the available ISA features and tuning
18298 decisions. It must also set selected_arch as this will be used to
18299 output the .arch asm tags for each function. */
18301 static void
18303 {
18318 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
18319 If either of -march or -mtune is given, they override their
18320 respective component of -mcpu. */
18330 #ifdef SUBTARGET_OVERRIDE_OPTIONS
18331 SUBTARGET_OVERRIDE_OPTIONS;
18332 #endif
18335 {
18336 /* If both -mcpu and -march are specified, warn if they are not
18337 architecturally compatible and prefer the -march ISA flags. */
18339 {
18341 aarch64_cpu_string,
18342 aarch64_arch_string);
18343 }
18347 }
18349 {
18352 }
18354 {
18358 }
18359 else
18360 {
18361 /* No -mcpu or -march specified, so use the default CPU. */
18365 }
18370 {
18371 #ifdef TARGET_ENABLE_BTI
18373 #else
18375 #endif
18376 }
18378 /* Return address signing is currently not supported for ILP32 targets. For
18379 LP64 targets use the configured option in the absence of a command-line
18380 option for -mbranch-protection. */
18382 {
18383 #ifdef TARGET_ENABLE_PAC_RET
18385 #else
18387 #endif
18388 }
18390 #ifndef HAVE_AS_MABI_OPTION
18391 /* The compiler may have been configured with 2.23.* binutils, which does
18392 not have support for ILP32. */
18395 #endif
18397 /* Convert -msve-vector-bits to a VG count. */
18403 /* The pass to insert speculation tracking runs before
18404 shrink-wrapping and the latter does not know how to update the
18405 tracking status. So disable it in this case. */
18411 /* Save these options as the default ones in case we push and pop them later
18412 while processing functions with potential target attributes. */
18413 target_option_default_node = target_option_current_node
18415 }
18417 /* Implement targetm.override_options_after_change. */
18419 static void
18421 {
18423 }
18425 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
18428 {
18431 else
18433 }
18437 {
18441 }
18443 void
18445 {
18447 }
18449 /* A checking mechanism for the implementation of the various code models. */
18450 static void
18452 {
18455 {
18462 {
18463 #ifdef HAVE_AS_SMALL_PIC_RELOCS
18465 ? AARCH64_CMODEL_SMALL_PIC
18467 #else
18469 #endif
18470 }
18483 }
18484 }
18486 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
18487 using the information saved in PTR. */
18489 static void
18493 {
18495 }
18497 /* Implement TARGET_OPTION_PRINT. */
18499 static void
18501 {
18512 }
18516 void
18518 {
18520 }
18522 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
18523 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
18524 make sure optab availability predicates are recomputed when necessary. */
18526 void
18528 {
18533 else
18535 }
18537 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
18538 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
18539 of the function, if such exists. This function may be called multiple
18540 times on a single function so use aarch64_previous_fndecl to avoid
18541 setting up identical state. */
18543 static void
18545 {
18549 tree old_tree = (aarch64_previous_fndecl
18555 /* If current function has no attributes but the previous one did,
18556 use the default node. */
18560 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
18561 the default have been handled by aarch64_save_restore_target_globals from
18562 aarch64_pragma_target_parse. */
18568 /* First set the target options. */
18573 }
18575 /* Enum describing the various ways we can handle attributes.
18576 In many cases we can reuse the generic option handling machinery. */
18578 enum aarch64_attr_opt_type
18579 {
18583 aarch64_attr_custom /* Attribute requires a custom handling function. */
18584 };
18586 /* All the information needed to handle a target attribute.
18587 NAME is the name of the attribute.
18588 ATTR_TYPE specifies the type of behavior of the attribute as described
18589 in the definition of enum aarch64_attr_opt_type.
18590 ALLOW_NEG is true if the attribute supports a "no-" form.
18591 HANDLER is the function that takes the attribute string as an argument
18592 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
18593 OPT_NUM is the enum specifying the option that the attribute modifies.
18594 This is needed for attributes that mirror the behavior of a command-line
18595 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
18596 aarch64_attr_enum. */
18598 struct aarch64_attribute_info
18599 {
18605 };
18607 /* Handle the ARCH_STR argument to the arch= target attribute. */
18609 static bool
18611 {
18614 aarch64_feature_flags tmp_flags;
18615 enum aarch_parse_opt_result parse_res
18619 {
18624 }
18627 {
18642 }
18645 }
18647 /* Handle the argument CPU_STR to the cpu= target attribute. */
18649 static bool
18651 {
18654 aarch64_feature_flags tmp_flags;
18655 enum aarch_parse_opt_result parse_res
18659 {
18665 }
18668 {
18683 }
18686 }
18688 /* Handle the argument STR to the branch-protection= attribute. */
18690 static bool
18692 {
18698 {
18709 /* Fall through. */
18714 }
18717 }
18719 /* Handle the argument STR to the tune= target attribute. */
18721 static bool
18723 {
18725 enum aarch_parse_opt_result parse_res
18729 {
18733 }
18736 {
18743 }
18746 }
18748 /* Parse an architecture extensions target attribute string specified in STR.
18749 For example "+fp+nosimd". Show any errors if needed. Return TRUE
18750 if successful. Update aarch64_isa_flags to reflect the ISA features
18751 modified. */
18753 static bool
18755 {
18759 /* We allow "+nothing" in the beginning to clear out all architectural
18760 features if the user wants to handpick specific features. */
18762 {
18765 }
18771 {
18774 }
18777 {
18789 }
18792 }
18794 /* The target attributes that we support. On top of these we also support just
18795 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
18796 handled explicitly in aarch64_process_one_target_attr. */
18799 {
18801 OPT_mgeneral_regs_only },
18803 OPT_mfix_cortex_a53_835769 },
18805 OPT_mfix_cortex_a53_843419 },
18809 OPT_momit_leaf_frame_pointer },
18812 OPT_march_ },
18815 OPT_mtune_ },
18819 OPT_msign_return_address_ },
18821 OPT_moutline_atomics},
18823 };
18825 /* Parse ARG_STR which contains the definition of one target attribute.
18826 Show appropriate errors if any or return true if the attribute is valid. */
18828 static bool
18830 {
18836 {
18839 }
18844 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
18845 It is easier to detect and handle it explicitly here rather than going
18846 through the machinery for the rest of the target attributes in this
18847 function. */
18852 {
18855 }
18858 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
18859 and point ARG to "foo". */
18861 {
18863 arg++;
18864 }
18868 {
18869 /* If the names don't match up, or the user has given an argument
18870 to an attribute that doesn't accept one, or didn't give an argument
18871 to an attribute that expects one, fail to match. */
18880 {
18883 }
18885 /* If the name matches but the attribute does not allow "no-" versions
18886 then we can't match. */
18888 {
18891 }
18894 {
18895 /* Has a custom handler registered.
18896 For example, cpu=, arch=, tune=. */
18903 /* Either set or unset a boolean option. */
18905 {
18913 }
18914 /* Set or unset a bit in the target_flags. aarch64_handle_option
18915 should know what mask to apply given the option number. */
18917 {
18919 /* We only need to specify the option number.
18920 aarch64_handle_option will know which mask to apply. */
18926 }
18927 /* Use the option setting machinery to set an option to an enum. */
18929 {
18936 {
18939 global_dc);
18940 }
18941 else
18942 {
18944 }
18946 }
18949 }
18950 }
18952 /* If we reached here we either have found an attribute and validated
18953 it or didn't match any. If we matched an attribute but its arguments
18954 were malformed we will have returned false already. */
18956 }
18958 /* Count how many times the character C appears in
18959 NULL-terminated string STR. */
18961 static unsigned int
18963 {
18966 {
18968 res++;
18970 str++;
18971 }
18974 }
18976 /* Parse the tree in ARGS that contains the target attribute information
18977 and update the global target options space. */
18979 bool
18981 {
18983 {
18984 do
18985 {
18988 {
18991 }
18996 }
18999 {
19002 }
19009 {
19012 }
19014 /* Used to catch empty spaces between commas i.e.
19015 attribute ((target ("attr1,,attr2"))). */
19018 /* Handle multiple target attributes separated by ','. */
19023 {
19024 num_attrs++;
19026 {
19027 /* Check if token is possibly an arch extension without
19028 leading '+'. */
19031 enum aarch_parse_opt_result ext_res
19036 token);
19037 else
19040 }
19043 }
19046 {
19049 }
19052 }
19054 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
19055 process attribute ((target ("..."))). */
19057 static bool
19059 {
19062 tree old_optimize;
19066 /* If what we're processing is the current pragma string then the
19067 target option node is already stored in target_option_current_node
19068 by aarch64_pragma_target_parse in aarch64-c.cc. Use that to avoid
19069 having to re-parse the string. This is especially useful to keep
19070 arm_neon.h compile times down since that header contains a lot
19071 of intrinsics enclosed in pragmas. */
19073 {
19076 }
19079 old_optimize
19083 /* If the function changed the optimization levels as well as setting
19084 target options, start with the optimizations specified. */
19089 /* Save the current target options to restore at the end. */
19092 /* If fndecl already has some target attributes applied to it, unpack
19093 them so that we add this attribute on top of them, rather than
19094 overwriting them. */
19096 {
19102 existing_options);
19103 }
19104 else
19110 /* Set up any additional state. */
19112 {
19116 }
19117 else
19124 {
19129 }
19137 }
19139 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
19140 tri-bool options (yes, no, don't care) and the default value is
19141 DEF, determine whether to reject inlining. */
19143 static bool
19146 {
19147 /* If the callee doesn't care, always allow inlining. */
19151 /* If the caller doesn't care, always allow inlining. */
19155 /* Otherwise, allow inlining if either the callee and caller values
19156 agree, or if the callee is using the default value. */
19158 }
19160 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
19161 to inline CALLEE into CALLER based on target-specific info.
19162 Make sure that the caller and callee have compatible architectural
19163 features. Then go through the other possible target attributes
19164 and see if they can block inlining. Try not to reject always_inline
19165 callees unless they are incompatible architecturally. */
19167 static bool
19169 {
19181 /* Callee's ISA flags should be a subset of the caller's. */
19190 /* Allow non-strict aligned functions inlining into strict
19191 aligned ones. */
19201 /* If the architectural features match up and the callee is always_inline
19202 then the other attributes don't matter. */
19214 /* Honour explicit requests to workaround errata. */
19227 /* If the user explicitly specified -momit-leaf-frame-pointer for the
19228 caller and calle and they don't match up, reject inlining. */
19235 /* If the callee has specific tuning overrides, respect them. */
19240 /* If the user specified tuning override strings for the
19241 caller and callee and they don't match up, reject inlining.
19242 We just do a string compare here, we don't analyze the meaning
19243 of the string, as it would be too costly for little gain. */
19251 }
19253 /* Return the ID of the TLDESC ABI, initializing the descriptor if hasn't
19254 been already. */
19256 unsigned int
19258 {
19261 {
19262 HARD_REG_SET full_reg_clobbers;
19269 }
19271 }
19273 /* Return true if SYMBOL_REF X binds locally. */
19275 static bool
19277 {
19281 }
19283 /* Return true if SYMBOL_REF X is thread local */
19284 static bool
19286 {
19295 }
19297 /* Classify a TLS symbol into one of the TLS kinds. */
19298 enum aarch64_symbol_type
19300 {
19304 {
19311 {
19317 }
19328 else
19337 }
19338 }
19340 /* Return the correct method for accessing X + OFFSET, where X is either
19341 a SYMBOL_REF or LABEL_REF. */
19343 enum aarch64_symbol_type
19345 {
19349 {
19351 {
19366 }
19367 }
19370 {
19375 {
19378 /* With -fPIC non-local symbols use the GOT. For orthogonality
19379 always use the GOT for extern weak symbols. */
19384 /* When we retrieve symbol + offset address, we have to make sure
19385 the offset does not cause overflow of the final address. But
19386 we have no way of knowing the address of symbol at compile time
19387 so we can't accurately say if the distance between the PC and
19388 symbol + offset is outside the addressible range of +/-1MB in the
19389 TINY code model. So we limit the maximum offset to +/-64KB and
19390 assume the offset to the symbol is not larger than +/-(1MB - 64KB).
19391 If offset_within_block_p is true we allow larger offsets. */
19407 /* Same reasoning as the tiny code model, but the offset cap here is
19408 1MB, allowing +/-3.9GB for the offset to the symbol. */
19416 /* This is alright even in PIC code as the constant
19417 pool reference is always PC relative and within
19418 the same translation unit. */
19421 else
19426 }
19427 }
19429 /* By default push everything into the constant pool. */
19431 }
19433 bool
19435 {
19437 }
19439 bool
19441 {
19442 poly_int64 offset;
19448 }
19450 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
19451 that should be rematerialized rather than spilled. */
19453 static bool
19455 {
19456 /* Support CSE and rematerialization of common constants. */
19461 /* Only accept variable-length vector constants if they can be
19462 handled directly.
19464 ??? It would be possible (but complex) to handle rematerialization
19465 of other constants via secondary reloads. */
19469 /* Otherwise, accept any CONST_VECTOR that, if all else fails, can at
19470 least be forced to memory and loaded from there. */
19474 /* Do not allow vector struct mode constants for Advanced SIMD.
19475 We could support 0 and -1 easily, but they need support in
19476 aarch64-simd.md. */
19484 /* Accept polynomial constants that can be calculated by using the
19485 destination of a move as the sole temporary. Constants that
19486 require a second temporary cannot be rematerialized (they can't be
19487 forced to memory and also aren't legitimate constants). */
19488 poly_int64 offset;
19492 /* If an offset is being added to something else, we need to allow the
19493 base to be moved into the destination register, meaning that there
19494 are no free temporaries for the offset. */
19499 /* Do not allow const (plus (anchor_symbol, const_int)). */
19503 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
19504 so spilling them is better than rematerialization. */
19508 /* Label references are always constant. */
19513 }
19515 rtx
19517 {
19523 /* Can return in any reg. */
19526 }
19528 /* On AAPCS systems, this is the "struct __va_list". */
19531 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
19532 Return the type to use as __builtin_va_list.
19534 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
19536 struct __va_list
19537 {
19538 void *__stack;
19539 void *__gr_top;
19540 void *__vr_top;
19541 int __gr_offs;
19542 int __vr_offs;
19543 }; */
19545 static tree
19547 {
19548 tree va_list_name;
19551 /* Create the type. */
19553 /* Give it the required name. */
19555 TYPE_DECL,
19557 va_list_type);
19562 /* Create the fields. */
19565 ptr_type_node);
19568 ptr_type_node);
19571 ptr_type_node);
19574 integer_type_node);
19577 integer_type_node);
19579 /* Tell tree-stdarg pass about our internal offset fields.
19580 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
19581 purpose to identify whether the code is updating va_list internal
19582 offset fields through irregular way. */
19604 /* Compute its layout. */
19608 }
19610 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
19611 static void
19613 {
19617 tree t;
19631 {
19634 }
19643 NULL_TREE);
19645 NULL_TREE);
19647 NULL_TREE);
19649 NULL_TREE);
19651 NULL_TREE);
19653 /* Emit code to initialize STACK, which points to the next varargs stack
19654 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
19655 by named arguments. STACK is 8-byte aligned. */
19662 /* Emit code to initialize GRTOP, the top of the GR save area.
19663 virtual_incoming_args_rtx should have been 16 byte aligned. */
19668 /* Emit code to initialize VRTOP, the top of the VR save area.
19669 This address is gr_save_area_bytes below GRTOP, rounded
19670 down to the next 16-byte boundary. */
19680 /* Emit code to initialize GROFF, the offset from GRTOP of the
19681 next GPR argument. */
19686 /* Likewise emit code to initialize VROFF, the offset from FTOP
19687 of the next VR argument. */
19691 }
19693 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
19695 static tree
19698 {
19699 tree addr;
19705 machine_mode mode;
19730 align
19738 {
19739 /* No frontends can create types with variable-sized modes, so we
19740 shouldn't be asked to pass or return them. */
19743 /* TYPE passed in fp/simd registers. */
19755 {
19758 }
19761 {
19763 }
19764 }
19765 else
19766 {
19767 /* TYPE passed in general registers. */
19780 {
19785 }
19789 {
19791 }
19792 }
19794 /* Get a local temporary for the field value. */
19797 /* Emit code to branch if off >= 0. */
19803 {
19804 /* Emit: offs = (offs + 15) & -16. */
19810 }
19811 else
19814 /* Update ap.__[g|v]r_offs */
19819 /* String up. */
19823 /* [cond2] if (ap.__[g|v]r_offs > 0) */
19828 /* String up: make sure the assignment happens before the use. */
19832 /* Prepare the trees handling the argument that is passed on the stack;
19833 the top level node will store in ON_STACK. */
19836 {
19837 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
19842 }
19843 else
19845 /* Advance ap.__stack */
19850 /* String up roundup and advance. */
19853 /* String up with arg */
19855 /* Big-endianness related address adjustment. */
19858 {
19862 }
19867 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
19877 {
19878 /* type ha; // treat as "struct {ftype field[n];}"
19879 ... [computing offs]
19880 for (i = 0; i <nregs; ++i, offs += 16)
19881 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
19882 return ha; */
19886 /* Declare a local variable. */
19890 /* Establish the base type. */
19892 {
19927 {
19931 }
19935 }
19937 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
19946 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
19948 {
19958 }
19962 }
19972 }
19974 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
19976 static void
19980 {
19982 CUMULATIVE_ARGS local_cum;
19986 /* The caller has advanced CUM up to, but not beyond, the last named
19987 argument. Advance a local copy of CUM past the last "real" named
19988 argument, to find out how many registers are left over. */
19993 /* Found out how many registers we need to save.
19994 Honor tree-stdvar analysis results. */
20003 {
20006 }
20009 {
20011 {
20014 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
20022 }
20024 {
20025 /* We can't use move_block_from_reg, because it will use
20026 the wrong mode, storing D regs only. */
20030 /* Set OFF to the offset from virtual_incoming_args_rtx of
20031 the first vector register. The VR save area lies below
20032 the GR one, and is aligned to 16 bytes. */
20039 {
20047 }
20048 }
20049 }
20051 /* We don't save the size into *PRETEND_SIZE because we want to avoid
20052 any complication of having crtl->args.pretend_args_size changed. */
20057 }
20059 static void
20061 {
20064 {
20066 {
20070 }
20071 }
20074 {
20077 }
20079 /* Only allow the FFR and FFRT to be accessed via special patterns. */
20083 /* When tracking speculation, we need a couple of call-clobbered registers
20084 to track the speculation state. It would be nice to just use
20085 IP0 and IP1, but currently there are numerous places that just
20086 assume these registers are free for other uses (eg pointer
20087 authentication). */
20089 {
20094 }
20095 }
20097 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. */
20099 bool
20101 {
20102 /* For records we're passed a FIELD_DECL, for arrays we're passed
20103 an ARRAY_TYPE. In both cases we're interested in the TREE_TYPE. */
20106 /* Assign BLKmode to anything that contains multiple SVE predicates.
20107 For structures, the "multiple" case is indicated by MODE being
20108 VOIDmode. */
20111 {
20116 }
20119 }
20121 /* Bitmasks that indicate whether earlier versions of GCC would have
20122 taken a different path through the ABI logic. This should result in
20123 a -Wpsabi warning if the earlier path led to a different ABI decision.
20125 WARN_PSABI_EMPTY_CXX17_BASE
20126 Indicates that the type includes an artificial empty C++17 base field
20127 that, prior to GCC 10.1, would prevent the type from being treated as
20128 a HFA or HVA. See PR94383 for details.
20130 WARN_PSABI_NO_UNIQUE_ADDRESS
20131 Indicates that the type includes an empty [[no_unique_address]] field
20132 that, prior to GCC 10.1, would prevent the type from being treated as
20133 a HFA or HVA. */
20138 /* Walk down the type tree of TYPE counting consecutive base elements.
20139 If *MODEP is VOIDmode, then set it to the first valid floating point
20140 type. If a non-floating point type is found, or if a floating point
20141 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
20142 otherwise return the count in the sub-tree.
20144 The WARN_PSABI_FLAGS argument allows the caller to check whether this
20145 function has changed its behavior relative to earlier versions of GCC.
20146 Normally the argument should be nonnull and point to a zero-initialized
20147 variable. The function then records whether the ABI decision might
20148 be affected by a known fix to the ABI logic, setting the associated
20149 WARN_PSABI_* bits if so.
20151 When the argument is instead a null pointer, the function tries to
20152 simulate the behavior of GCC before all such ABI fixes were made.
20153 This is useful to check whether the function returns something
20154 different after the ABI fixes. */
20155 static int
20158 {
20159 machine_mode mode;
20160 HOST_WIDE_INT size;
20166 {
20197 /* Use V2SImode and V4SImode as representatives of all 64-bit
20198 and 128-bit vector types. */
20201 {
20210 }
20215 /* Vector modes are considered to be opaque: two vectors are
20216 equivalent for the purposes of being homogeneous aggregates
20217 if they are the same size. */
20224 {
20228 /* Can't handle incomplete types nor sizes that are not
20229 fixed. */
20235 warn_psabi_flags);
20237 || !index
20248 /* There must be no padding. */
20254 }
20257 {
20260 tree field;
20262 /* Can't handle incomplete types nor sizes that are not
20263 fixed. */
20269 {
20274 {
20275 /* See whether this is something that earlier versions of
20276 GCC failed to ignore. */
20283 else
20284 /* No compatibility problem. */
20287 /* Simulate the old behavior when WARN_PSABI_FLAGS is null. */
20289 {
20292 }
20293 }
20294 /* A zero-width bitfield may affect layout in some
20295 circumstances, but adds no members. The determination
20296 of whether or not a type is an HFA is performed after
20297 layout is complete, so if the type still looks like an
20298 HFA afterwards, it is still classed as one. This is
20299 potentially an ABI break for the hard-float ABI. */
20302 {
20303 /* Prior to GCC-12 these fields were striped early,
20304 hiding them from the back-end entirely and
20305 resulting in the correct behaviour for argument
20306 passing. Simulate that old behaviour without
20307 generating a warning. */
20311 {
20314 }
20315 }
20318 warn_psabi_flags);
20322 }
20324 /* There must be no padding. */
20330 }
20334 {
20335 /* These aren't very interesting except in a degenerate case. */
20338 tree field;
20340 /* Can't handle incomplete types nor sizes that are not
20341 fixed. */
20347 {
20352 warn_psabi_flags);
20356 }
20358 /* There must be no padding. */
20364 }
20368 }
20371 }
20373 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
20374 type as described in AAPCS64 \S 4.1.2.
20376 See the comment above aarch64_composite_type_p for the notes on MODE. */
20378 static bool
20380 machine_mode mode)
20381 {
20385 {
20389 }
20392 {
20393 /* The containing "else if" is too loose: it means that we look at TYPE
20394 if the type is a vector type (good), but that we otherwise ignore TYPE
20395 and look only at the mode. This is wrong because the type describes
20396 the language-level information whereas the mode is purely an internal
20397 GCC concept. We can therefore reach here for types that are not
20398 vectors in the AAPCS64 sense.
20400 We can't "fix" that for the traditional Advanced SIMD vector modes
20401 without breaking backwards compatibility. However, there's no such
20402 baggage for the structure modes, which were introduced in GCC 12. */
20406 /* For similar reasons, rely only on the type, not the mode, when
20407 processing SVE types. */
20409 /* Leave later code to report an error if SVE is disabled. */
20411 else
20413 }
20415 {
20416 /* 64-bit and 128-bit vectors should only acquire an SVE mode if
20417 they are being treated as scalable AAPCS64 types. */
20421 }
20423 }
20425 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
20426 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
20427 array types. The C99 floating-point complex types are also considered
20428 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
20429 types, which are GCC extensions and out of the scope of AAPCS64, are
20430 treated as composite types here as well.
20432 Note that MODE itself is not sufficient in determining whether a type
20433 is such a composite type or not. This is because
20434 stor-layout.cc:compute_record_mode may have already changed the MODE
20435 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
20436 structure with only one field may have its MODE set to the mode of the
20437 field. Also an integer mode whose size matches the size of the
20438 RECORD_TYPE type may be used to substitute the original mode
20439 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
20440 solely relied on. */
20442 static bool
20444 machine_mode mode)
20445 {
20458 }
20460 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
20461 shall be passed or returned in simd/fp register(s) (providing these
20462 parameter passing registers are available).
20464 Upon successful return, *COUNT returns the number of needed registers,
20465 *BASE_MODE returns the mode of the individual register and when IS_HA
20466 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
20467 floating-point aggregate or a homogeneous short-vector aggregate.
20469 SILENT_P is true if the function should refrain from reporting any
20470 diagnostics. This should only be used if the caller is certain that
20471 any ABI decisions would eventually come through this function with
20472 SILENT_P set to false. */
20474 static bool
20476 const_tree type,
20481 {
20491 {
20494 }
20496 {
20500 }
20502 {
20507 {
20512 && warn_psabi
20513 && warn_psabi_flags
20517 {
20524 /* Use TYPE_MAIN_VARIANT to strip any redundant const
20525 qualification. */
20528 "type %qT with %<[[no_unique_address]]%> members "
20533 "type %qT when C++17 is enabled changed to match "
20540 }
20544 }
20545 else
20547 }
20548 else
20554 }
20556 /* Implement TARGET_STRUCT_VALUE_RTX. */
20558 static rtx
20561 {
20563 }
20565 /* Implements target hook vector_mode_supported_p. */
20566 static bool
20568 {
20571 }
20573 /* Return the full-width SVE vector mode for element mode MODE, if one
20574 exists. */
20575 opt_machine_mode
20577 {
20579 {
20598 }
20599 }
20601 /* Return the 128-bit Advanced SIMD vector mode for element mode MODE,
20602 if it exists. */
20603 opt_machine_mode
20605 {
20607 {
20626 }
20627 }
20629 /* Return appropriate SIMD container
20630 for MODE within a vector of WIDTH bits. */
20631 static machine_mode
20633 {
20641 {
20644 else
20646 {
20661 }
20662 }
20664 }
20666 /* Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M
20667 and return whether the SVE mode should be preferred over the
20668 Advanced SIMD one in aarch64_autovectorize_vector_modes. */
20669 static bool
20671 {
20672 /* Take into account the aarch64-autovec-preference param if non-zero. */
20681 /* The preference in case of a tie in costs. */
20687 /* If the CPU information does not have an SVE width registered use the
20688 generic poly_int comparison that prefers SVE. If a preference is
20689 explicitly requested avoid this path. */
20691 && !prefer_asimd
20695 /* Otherwise estimate the runtime width of the modes involved. */
20699 /* Preferring SVE means picking it first unless the Advanced SIMD mode
20700 is clearly wider. */
20703 /* Conversely, preferring Advanced SIMD means picking SVE only if SVE
20704 is clearly wider. */
20708 /* In the default case prefer Advanced SIMD over SVE in case of a tie. */
20710 }
20712 /* Return 128-bit container as the preferred SIMD mode for MODE. */
20713 static machine_mode
20715 {
20716 /* Take into account explicit auto-vectorization ISA preferences through
20717 aarch64_cmp_autovec_modes. */
20723 }
20725 /* Return a list of possible vector sizes for the vectorizer
20726 to iterate over. */
20727 static unsigned int
20729 {
20731 /* Try using full vectors for all element types. */
20732 VNx16QImode,
20734 /* Try using 16-bit containers for 8-bit elements and full vectors
20735 for wider elements. */
20736 VNx8QImode,
20738 /* Try using 32-bit containers for 8-bit and 16-bit elements and
20739 full vectors for wider elements. */
20740 VNx4QImode,
20742 /* Try using 64-bit containers for all element types. */
20743 VNx2QImode
20744 };
20747 /* Try using 128-bit vectors for all element types. */
20748 V16QImode,
20750 /* Try using 64-bit vectors for 8-bit elements and 128-bit vectors
20751 for wider elements. */
20752 V8QImode,
20754 /* Try using 64-bit vectors for 16-bit elements and 128-bit vectors
20755 for wider elements.
20757 TODO: We could support a limited form of V4QImode too, so that
20758 we use 32-bit vectors for 8-bit elements. */
20759 V4HImode,
20761 /* Try using 64-bit vectors for 32-bit elements and 128-bit vectors
20762 for 64-bit elements.
20764 TODO: We could similarly support limited forms of V2QImode and V2HImode
20765 for this case. */
20766 V2SImode
20767 };
20769 /* Try using N-byte SVE modes only after trying N-byte Advanced SIMD mode.
20770 This is because:
20772 - If we can't use N-byte Advanced SIMD vectors then the placement
20773 doesn't matter; we'll just continue as though the Advanced SIMD
20774 entry didn't exist.
20776 - If an SVE main loop with N bytes ends up being cheaper than an
20777 Advanced SIMD main loop with N bytes then by default we'll replace
20778 the Advanced SIMD version with the SVE one.
20780 - If an Advanced SIMD main loop with N bytes ends up being cheaper
20781 than an SVE main loop with N bytes then by default we'll try to
20782 use the SVE loop to vectorize the epilogue instead. */
20791 {
20796 else
20798 }
20803 /* Consider enabling VECT_COMPARE_COSTS for SVE, both so that we
20804 can compare SVE against Advanced SIMD and so that we can compare
20805 multiple SVE vectorization approaches against each other. There's
20806 not really any point doing this for Advanced SIMD only, since the
20807 first mode that works should always be the best. */
20811 }
20813 /* Implement TARGET_MANGLE_TYPE. */
20817 {
20818 /* The AArch64 ABI documents say that "__va_list" has to be
20819 mangled as if it is in the "std" namespace. */
20823 /* Half-precision floating point types. */
20825 {
20830 else
20832 }
20834 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
20835 builtin types. */
20837 {
20842 }
20844 /* Use the default mangling. */
20846 }
20848 /* Implement TARGET_VERIFY_TYPE_CONTEXT. */
20850 static bool
20853 {
20855 }
20857 /* Find the first rtx_insn before insn that will generate an assembly
20858 instruction. */
20862 {
20866 do
20867 {
20869 }
20873 }
20875 static bool
20877 {
20879 /* A number of these may be AArch32 only. */
20884 };
20887 {
20890 }
20893 }
20895 /* Check if there is a register dependency between a load and the insn
20896 for which we hold recog_data. */
20898 static bool
20900 {
20901 rtx load_reg;
20911 {
20917 }
20919 }
20922 /* When working around the Cortex-A53 erratum 835769,
20923 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
20924 instruction and has a preceding memory instruction such that a NOP
20925 should be inserted between them. */
20927 bool
20929 {
20932 rtx body;
20945 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
20946 Restore recog state to INSN to avoid state corruption. */
20954 /* If the previous insn is a memory op and there is no dependency between
20955 it and the DImode madd, emit a NOP between them. If body is NULL then we
20956 have a complex memory operation, probably a load/store pair.
20957 Be conservative for now and emit a NOP. */
20964 }
20967 /* Implement FINAL_PRESCAN_INSN. */
20969 void
20971 {
20974 }
20977 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
20978 instruction. */
20980 bool
20982 {
20985 }
20987 /* Return true if X is a valid immediate for the SVE ADD and SUB instructions
20988 when applied to mode MODE. Negate X first if NEGATE_P is true. */
20990 bool
20992 {
21005 }
21007 /* Return true if X is a valid immediate for the SVE SQADD and SQSUB
21008 instructions when applied to mode MODE. Negate X first if NEGATE_P
21009 is true. */
21011 bool
21013 {
21017 /* After the optional negation, the immediate must be nonnegative.
21018 E.g. a saturating add of -127 must be done via SQSUB Zn.B, Zn.B, #127
21019 instead of SQADD Zn.B, Zn.B, #129. */
21022 }
21024 /* Return true if X is a valid immediate operand for an SVE logical
21025 instruction such as AND. */
21027 bool
21029 {
21030 rtx elt;
21036 }
21038 /* Return true if X is a valid immediate for the SVE DUP and CPY
21039 instructions. */
21041 bool
21043 {
21052 }
21054 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
21055 SIGNED_P says whether the operand is signed rather than unsigned. */
21057 bool
21059 {
21062 && (signed_p
21065 }
21067 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
21068 instruction. Negate X first if NEGATE_P is true. */
21070 bool
21072 {
21073 rtx elt;
21074 REAL_VALUE_TYPE r;
21090 }
21092 /* Return true if X is a valid immediate operand for an SVE FMUL
21093 instruction. */
21095 bool
21097 {
21098 rtx elt;
21104 }
21106 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
21107 for the Advanced SIMD operation described by WHICH and INSN. If INFO
21108 is nonnull, use it to describe valid immediates. */
21109 static bool
21114 {
21115 /* Try a 4-byte immediate with LSL. */
21118 {
21123 }
21125 /* Try a 2-byte immediate with LSL. */
21130 {
21135 }
21137 /* Try a 4-byte immediate with MSL, except for cases that MVN
21138 can handle. */
21141 {
21144 {
21149 }
21150 }
21153 }
21155 /* Return true if replicating VAL64 is a valid immediate for the
21156 Advanced SIMD operation described by WHICH. If INFO is nonnull,
21157 use it to describe valid immediates. */
21158 static bool
21162 {
21168 {
21179 /* Try using a replicated byte. */
21183 {
21187 }
21188 }
21190 /* Try using a bit-to-bytemask. */
21192 {
21195 {
21199 }
21201 {
21205 }
21206 }
21208 }
21210 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
21211 instruction. If INFO is nonnull, use it to describe valid immediates. */
21213 static bool
21216 {
21220 {
21224 {
21229 }
21230 }
21233 {
21234 /* DUP with no shift. */
21238 }
21240 {
21241 /* DUP with LSL #8. */
21245 }
21247 {
21248 /* DUPM. */
21252 }
21254 }
21256 /* Return true if X is an UNSPEC_PTRUE constant of the form:
21258 (const (unspec [PATTERN ZERO] UNSPEC_PTRUE))
21260 where PATTERN is the svpattern as a CONST_INT and where ZERO
21261 is a zero constant of the required PTRUE mode (which can have
21262 fewer elements than X's mode, if zero bits are significant).
21264 If so, and if INFO is nonnull, describe the immediate in INFO. */
21265 bool
21267 {
21276 {
21277 aarch64_svpattern pattern
21282 }
21284 }
21286 /* Return true if X is a valid SVE predicate. If INFO is nonnull, use
21287 it to describe valid immediates. */
21289 static bool
21291 {
21296 {
21300 }
21302 /* Analyze the value as a VNx16BImode. This should be relatively
21303 efficient, since rtx_vector_builder has enough built-in capacity
21304 to store all VLA predicate constants without needing the heap. */
21305 rtx_vector_builder builder;
21311 {
21315 {
21317 {
21320 }
21322 }
21323 }
21325 }
21327 /* Return true if OP is a valid SIMD immediate for the operation
21328 described by WHICH. If INFO is nonnull, use it to describe valid
21329 immediates. */
21330 bool
21333 {
21353 {
21360 {
21361 /* Get the corresponding container mode. E.g. an INDEX on V2SI
21362 should yield two integer values per 128-bit block, meaning
21363 that we need to treat it in the same way as V2DI and then
21364 ignore the upper 32 bits of each element. */
21367 }
21369 }
21373 else
21376 scalar_float_mode elt_float_mode;
21379 {
21383 {
21387 }
21388 }
21390 /* If all elements in an SVE vector have the same value, we have a free
21391 choice between using the element mode and using the container mode.
21392 Using the element mode means that unused parts of the vector are
21393 duplicates of the used elements, while using the container mode means
21394 that the unused parts are an extension of the used elements. Using the
21395 element mode is better for (say) VNx4HI 0x101, since 0x01010101 is valid
21396 for its container mode VNx4SI while 0x00000101 isn't.
21398 If not all elements in an SVE vector have the same value, we need the
21399 transition from one element to the next to occur at container boundaries.
21400 E.g. a fixed-length VNx4HI containing { 1, 2, 3, 4 } should be treated
21401 in the same way as a VNx4SI containing { 1, 2, 3, 4 }. */
21402 scalar_int_mode elt_int_mode;
21405 else
21412 /* Expand the vector constant out into a byte vector, with the least
21413 significant byte of the register first. */
21417 {
21418 /* The vector is provided in gcc endian-neutral fashion.
21419 For aarch64_be Advanced SIMD, it must be laid out in the vector
21420 register in reverse order. */
21432 {
21435 }
21436 }
21438 /* The immediate must repeat every eight bytes. */
21444 /* Get the repeating 8-byte value as an integer. No endian correction
21445 is needed here because bytes is already in lsb-first order. */
21453 else
21455 }
21457 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
21458 has a step in the range of INDEX. Return the index expression if so,
21459 otherwise return null. */
21460 rtx
21462 {
21469 }
21471 /* Check of immediate shift constants are within range. */
21472 bool
21474 {
21481 else
21483 }
21485 /* Return the bitmask CONST_INT to select the bits required by a zero extract
21486 operation of width WIDTH at bit position POS. */
21488 rtx
21490 {
21494 unsigned HOST_WIDE_INT mask
21497 }
21499 bool
21501 {
21510 {
21511 /* Require predicate constants to be VNx16BI before RA, so that we
21512 force everything to have a canonical form. */
21514 && !reload_completed
21520 }
21522 /* Remove UNSPEC_SALT_ADDR before checking symbol reference. */
21525 /* GOT accesses are valid moves. */
21538 }
21540 /* Create a 0 constant that is based on V4SI to allow CSE to optimally share
21541 the constant creation. */
21543 rtx
21545 {
21550 }
21552 /* Return a const_int vector of VAL. */
21553 rtx
21555 {
21558 }
21560 /* Check OP is a legal scalar immediate for the MOVI instruction. */
21562 bool
21564 {
21565 machine_mode vmode;
21570 }
21572 /* Construct and return a PARALLEL RTX vector with elements numbering the
21573 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
21574 the vector - from the perspective of the architecture. This does not
21575 line up with GCC's perspective on lane numbers, so we end up with
21576 different masks depending on our target endian-ness. The diagram
21577 below may help. We must draw the distinction when building masks
21578 which select one half of the vector. An instruction selecting
21579 architectural low-lanes for a big-endian target, must be described using
21580 a mask selecting GCC high-lanes.
21582 Big-Endian Little-Endian
21584 GCC 0 1 2 3 3 2 1 0
21585 | x | x | x | x | | x | x | x | x |
21586 Architecture 3 2 1 0 3 2 1 0
21588 Low Mask: { 2, 3 } { 0, 1 }
21589 High Mask: { 0, 1 } { 2, 3 }
21591 MODE Is the mode of the vector and NUNITS is the number of units in it. */
21593 rtx
21595 {
21600 rtx t1;
21605 else
21613 }
21615 /* Check OP for validity as a PARALLEL RTX vector with elements
21616 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
21617 from the perspective of the architecture. See the diagram above
21618 aarch64_simd_vect_par_cnst_half for more details. */
21620 bool
21623 {
21637 {
21644 }
21646 }
21648 /* Return a PARALLEL containing NELTS elements, with element I equal
21649 to BASE + I * STEP. */
21651 rtx
21653 {
21658 }
21660 /* Return true if OP is a PARALLEL of CONST_INTs that form a linear
21661 series with step STEP. */
21663 bool
21665 {
21676 }
21678 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
21679 HIGH (exclusive). */
21680 void
21682 const_tree exp)
21683 {
21684 HOST_WIDE_INT lane;
21689 {
21693 else
21695 }
21696 }
21698 /* Peform endian correction on lane number N, which indexes a vector
21699 of mode MODE, and return the result as an SImode rtx. */
21701 rtx
21703 {
21705 }
21707 /* Return TRUE if OP is a valid vector addressing mode. */
21709 bool
21711 {
21714 }
21716 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
21718 bool
21720 {
21722 scalar_mode mode;
21729 }
21731 /* Return true if OP is a valid MEM operand for an SVE LD1R{Q,O} instruction
21732 where the size of the read data is specified by `mode` and the size of the
21733 vector elements are specified by `elem_mode`. */
21734 bool
21736 scalar_mode elem_mode)
21737 {
21750 }
21752 /* Return true if OP is a valid MEM operand for an SVE LD1RQ instruction. */
21753 bool
21755 {
21758 }
21760 /* Return true if OP is a valid MEM operand for an SVE LD1RO instruction for
21761 accessing a vector where the element size is specified by `elem_mode`. */
21762 bool
21764 {
21766 }
21768 /* Return true if OP is a valid MEM operand for an SVE LDFF1 instruction. */
21769 bool
21771 {
21783 }
21785 /* Return true if OP is a valid MEM operand for an SVE LDNF1 instruction. */
21786 bool
21788 {
21795 }
21797 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
21798 The conditions for STR are the same. */
21799 bool
21801 {
21808 }
21810 /* Return true if OP is a valid address for an SVE PRF[BHWD] instruction,
21811 addressing memory of mode MODE. */
21812 bool
21814 {
21823 }
21825 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
21826 We need to be able to access the individual pieces, so the range
21827 is different from LD[234] and ST[234]. */
21828 bool
21830 {
21837 ADDR_QUERY_ANY)
21845 }
21847 /* Emit a register copy from operand to operand, taking care not to
21848 early-clobber source registers in the process.
21850 COUNT is the number of components into which the copy needs to be
21851 decomposed. */
21852 void
21855 {
21865 else
21869 }
21871 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
21872 one of VSTRUCT modes: OI, CI, or XI. */
21873 int
21875 {
21876 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
21878 }
21880 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
21881 alignment of a vector to 128 bits. SVE predicates have an alignment of
21882 16 bits. */
21883 static HOST_WIDE_INT
21885 {
21886 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
21887 be set for non-predicate vectors of booleans. Modes are the most
21888 direct way we have of identifying real SVE predicate types. */
21891 widest_int min_size
21894 }
21896 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
21897 static poly_uint64
21899 {
21901 {
21902 /* If the length of the vector is a fixed power of 2, try to align
21903 to that length, otherwise don't try to align at all. */
21904 HOST_WIDE_INT result;
21909 }
21911 }
21913 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
21914 static bool
21916 {
21920 /* For fixed-length vectors, check that the vectorizer will aim for
21921 full-vector alignment. This isn't true for generic GCC vectors
21922 that are wider than the ABI maximum of 128 bits. */
21923 poly_uint64 preferred_alignment =
21927 preferred_alignment))
21930 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
21932 }
21934 /* Return true if the vector misalignment factor is supported by the
21935 target. */
21936 static bool
21940 {
21942 {
21943 /* Return if movmisalign pattern is not supported for this mode. */
21947 /* Misalignment factor is unknown at compile time. */
21950 }
21952 is_packed);
21953 }
21955 /* If VALS is a vector constant that can be loaded into a register
21956 using DUP, generate instructions to do so and return an RTX to
21957 assign to the register. Otherwise return NULL_RTX. */
21958 static rtx
21960 {
21963 rtx x;
21968 /* We can load this constant by using DUP and a constant in a
21969 single ARM register. This will be cheaper than a vector
21970 load. */
21973 }
21976 /* Generate code to load VALS, which is a PARALLEL containing only
21977 constants (for vec_init) or CONST_VECTOR, efficiently into a
21978 register. Returns an RTX to copy into the register, or NULL_RTX
21979 for a PARALLEL that cannot be converted into a CONST_VECTOR. */
21980 static rtx
21982 {
21984 rtx const_dup;
21992 {
21993 /* A CONST_VECTOR must contain only CONST_INTs and
21994 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
21995 Only store valid constants in a CONST_VECTOR. */
21998 {
22001 n_const++;
22002 }
22005 }
22006 else
22011 /* Load using MOVI/MVNI. */
22014 /* Loaded using DUP. */
22017 /* Load from constant pool. We cannot take advantage of single-cycle
22018 LD1 because we need a PC-relative addressing mode. */
22020 else
22021 /* A PARALLEL containing something not valid inside CONST_VECTOR.
22022 We cannot construct an initializer. */
22024 }
22026 /* Expand a vector initialisation sequence, such that TARGET is
22027 initialised to contain VALS. */
22029 void
22031 {
22034 /* The number of vector elements. */
22036 /* The number of vector elements which are not constant. */
22039 /* The first element of vals. */
22043 /* This is a special vec_init<M><N> where N is not an element mode but a
22044 vector mode with half the elements of M. We expect to find two entries
22045 of mode N in VALS and we must put their concatentation into TARGET. */
22047 {
22056 }
22058 /* Count the number of variable elements to initialise. */
22060 {
22064 else
22068 }
22070 /* No variable elements, hand off to aarch64_simd_make_constant which knows
22071 how best to handle this. */
22073 {
22076 {
22079 }
22080 }
22082 /* Splat a single non-constant element if we can. */
22084 {
22088 }
22090 /* Check for interleaving case.
22091 For eg if initializer is (int16x8_t) {x, y, x, y, x, y, x, y}.
22092 Generate following code:
22093 dup v0.h, x
22094 dup v1.h, y
22095 zip1 v0.h, v0.h, v1.h
22096 for "large enough" initializer. */
22099 {
22106 {
22111 {
22114 }
22119 }
22120 }
22125 /* If there are only variable elements, try to optimize
22126 the insertion using dup for the most common element
22127 followed by insertions. */
22129 /* The algorithm will fill matches[*][0] with the earliest matching element,
22130 and matches[X][1] with the count of duplicate elements (if X is the
22131 earliest element which has duplicates). */
22134 {
22137 {
22139 {
22141 {
22145 }
22146 }
22147 }
22152 {
22155 }
22157 /* Create a duplicate of the most common element, unless all elements
22158 are equally useless to us, in which case just immediately set the
22159 vector register using the first element. */
22162 {
22163 /* For vectors of two 64-bit elements, we can do even better. */
22168 {
22171 /* Combine can pick up this case, but handling it directly
22172 here leaves clearer RTL.
22174 This is load_pair_lanes<mode>, and also gives us a clean-up
22175 for store_pair_lanes<mode>. */
22179 {
22180 rtx t;
22183 else
22187 }
22188 }
22189 /* The subreg-move sequence below will move into lane zero of the
22190 vector register. For big-endian we want that position to hold
22191 the last element of VALS. */
22195 }
22196 else
22197 {
22200 }
22202 /* Insert the rest. */
22204 {
22210 }
22212 }
22214 /* Initialise a vector which is part-variable. We want to first try
22215 to build those lanes which are constant in the most efficient way we
22216 can. */
22218 {
22221 /* Load constant part of vector. We really don't care what goes into the
22222 parts we will overwrite, but we're more likely to be able to load the
22223 constant efficiently if it has fewer, larger, repeating parts
22224 (see aarch64_simd_valid_immediate). */
22226 {
22232 {
22233 /* Look in the copied vector, as more elements are const. */
22236 {
22239 }
22240 }
22242 }
22244 }
22246 /* Insert the variable lanes directly. */
22248 {
22254 }
22255 }
22257 /* Emit RTL corresponding to:
22258 insr TARGET, ELEM. */
22260 static void
22262 {
22270 }
22272 /* Subroutine of aarch64_sve_expand_vector_init for handling
22273 trailing constants.
22274 This function works as follows:
22275 (a) Create a new vector consisting of trailing constants.
22276 (b) Initialize TARGET with the constant vector using emit_move_insn.
22277 (c) Insert remaining elements in TARGET using insr.
22278 NELTS is the total number of elements in original vector while
22279 while NELTS_REQD is the number of elements that are actually
22280 significant.
22282 ??? The heuristic used is to do above only if number of constants
22283 is at least half the total number of elements. May need fine tuning. */
22285 static bool
22286 aarch64_sve_expand_vector_init_handle_trailing_constants
22288 {
22295 i--)
22296 n_trailing_constants++;
22299 {
22300 /* Try to use the natural pattern of BUILDER to extend the trailing
22301 constant elements to a full vector. Replace any variables in the
22302 extra elements with zeros.
22304 ??? It would be better if the builders supported "don't care"
22305 elements, with the builder filling in whichever elements
22306 give the most compact encoding. */
22309 {
22314 }
22322 }
22325 }
22327 /* Subroutine of aarch64_sve_expand_vector_init.
22328 Works as follows:
22329 (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
22330 (b) Skip trailing elements from BUILDER, which are the same as
22331 element NELTS_REQD - 1.
22332 (c) Insert earlier elements in reverse order in TARGET using insr. */
22334 static void
22338 {
22353 }
22355 /* Subroutine of aarch64_sve_expand_vector_init to handle case
22356 when all trailing elements of builder are same.
22357 This works as follows:
22358 (a) Use expand_insn interface to broadcast last vector element in TARGET.
22359 (b) Insert remaining elements in TARGET using insr.
22361 ??? The heuristic used is to do above if number of same trailing elements
22362 is at least 3/4 of total number of elements, loosely based on
22363 heuristic from mostly_zeros_p. May need fine-tuning. */
22365 static bool
22366 aarch64_sve_expand_vector_init_handle_trailing_same_elem
22368 {
22371 {
22375 }
22378 }
22380 /* Initialize register TARGET from BUILDER. NELTS is the constant number
22381 of elements in BUILDER.
22383 The function tries to initialize TARGET from BUILDER if it fits one
22384 of the special cases outlined below.
22386 Failing that, the function divides BUILDER into two sub-vectors:
22387 v_even = even elements of BUILDER;
22388 v_odd = odd elements of BUILDER;
22390 and recursively calls itself with v_even and v_odd.
22392 if (recursive call succeeded for v_even or v_odd)
22393 TARGET = zip (v_even, v_odd)
22395 The function returns true if it managed to build TARGET from BUILDER
22396 with one of the special cases, false otherwise.
22398 Example: {a, 1, b, 2, c, 3, d, 4}
22400 The vector gets divided into:
22401 v_even = {a, b, c, d}
22402 v_odd = {1, 2, 3, 4}
22404 aarch64_sve_expand_vector_init(v_odd) hits case 1 and
22405 initialize tmp2 from constant vector v_odd using emit_move_insn.
22407 aarch64_sve_expand_vector_init(v_even) fails since v_even contains
22408 4 elements, so we construct tmp1 from v_even using insr:
22409 tmp1 = dup(d)
22410 insr tmp1, c
22411 insr tmp1, b
22412 insr tmp1, a
22414 And finally:
22415 TARGET = zip (tmp1, tmp2)
22416 which sets TARGET to {a, 1, b, 2, c, 3, d, 4}. */
22418 static bool
22421 {
22424 /* Case 1: Vector contains trailing constants. */
22430 /* Case 2: Vector contains leading constants. */
22439 {
22442 }
22444 /* Case 3: Vector contains trailing same element. */
22450 /* Case 4: Vector contains leading same element. */
22454 {
22457 }
22459 /* Avoid recursing below 4-elements.
22460 ??? The threshold 4 may need fine-tuning. */
22469 {
22472 }
22488 /* Initialize v_even and v_odd using INSR if it didn't match any of the
22489 special cases and zip v_even, v_odd. */
22500 }
22502 /* Initialize register TARGET from the elements in PARALLEL rtx VALS. */
22504 void
22506 {
22515 /* If neither sub-vectors of v could be initialized specially,
22516 then use INSR to insert all elements from v into TARGET.
22517 ??? This might not be optimal for vectors with large
22518 initializers like 16-element or above.
22519 For nelts < 4, it probably isn't useful to handle specially. */
22524 }
22526 /* Check whether VALUE is a vector constant in which every element
22527 is either a power of 2 or a negated power of 2. If so, return
22528 a constant vector of log2s, and flip CODE between PLUS and MINUS
22529 if VALUE contains negated powers of 2. Return NULL_RTX otherwise. */
22531 static rtx
22533 {
22537 rtx_vector_builder builder;
22542 /* 1 if the result of the multiplication must be negated,
22543 0 if it mustn't, or -1 if we don't yet care. */
22547 {
22554 {
22555 /* It matters whether we negate or not. Make that choice,
22556 and make sure that it's consistent with previous elements. */
22562 }
22563 /* POW2 is now the value that we want to be a power of 2. */
22568 }
22570 /* PLUS and MINUS are equivalent; canonicalize on PLUS. */
22575 }
22577 /* Prepare for an integer SVE multiply-add or multiply-subtract pattern;
22578 CODE is PLUS for the former and MINUS for the latter. OPERANDS is the
22579 operands array, in the same order as for fma_optab. Return true if
22580 the function emitted all the necessary instructions, false if the caller
22581 should generate the pattern normally with the new OPERANDS array. */
22583 bool
22585 {
22588 {
22593 OPTAB_DIRECT);
22595 }
22598 }
22600 /* Likewise, but for a conditional pattern. */
22602 bool
22604 {
22607 {
22613 }
22616 }
22618 static unsigned HOST_WIDE_INT
22620 {
22624 }
22626 /* Select a format to encode pointers in exception handling data. */
22627 int
22629 {
22632 {
22638 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
22639 for everything. */
22643 /* No assumptions here. 8-byte relocs required. */
22646 }
22648 }
22650 /* Output .variant_pcs for aarch64_vector_pcs function symbols. */
22652 static void
22654 {
22656 {
22659 {
22663 }
22664 }
22665 }
22667 /* The last .arch and .tune assembly strings that we printed. */
22671 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
22672 by the function fndecl. */
22674 void
22676 tree fndecl)
22677 {
22683 else
22694 /* Only update the assembler .arch string if it is distinct from the last
22695 such string we printed. */
22698 {
22701 }
22703 /* Print the cpu name we're tuning for in the comments, might be
22704 useful to readers of the generated asm. Do it only when it changes
22705 from function to function and verbose assembly is requested. */
22710 {
22714 }
22718 /* Don't forget the type directive for ELF. */
22723 }
22725 /* Implement PRINT_PATCHABLE_FUNCTION_ENTRY. */
22727 void
22731 {
22733 {
22734 /* Emit the patching area before the entry label, if any. */
22736 record_p);
22738 }
22746 {
22747 /* Emit the patchable_area at the beginning of the function. */
22751 }
22758 {
22759 /* Emit a BTI_C. */
22761 }
22763 /* Emit the patchable_area after BTI_C. */
22766 }
22768 /* Output patchable area. */
22770 void
22772 {
22774 record_p);
22775 }
22777 /* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */
22779 void
22781 {
22786 }
22788 /* Implement ASM_OUTPUT_EXTERNAL. Output .variant_pcs for undefined
22789 function symbol references. */
22791 void
22793 {
22796 }
22798 /* Triggered after a .cfi_startproc directive is emitted into the assembly file.
22799 Used to output the .cfi_b_key_frame directive when signing the current
22800 function with the B key. */
22802 void
22804 {
22808 }
22810 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
22812 static void
22814 {
22831 }
22833 /* Emit load exclusive. */
22835 static void
22838 {
22843 else
22845 }
22847 /* Emit store exclusive. */
22849 static void
22852 {
22857 else
22859 }
22861 /* Mark the previous jump instruction as unlikely. */
22863 static void
22865 {
22868 }
22870 /* We store the names of the various atomic helpers in a 5x5 array.
22871 Return the libcall function given MODE, MODEL and NAMES. */
22873 rtx
22876 {
22881 {
22899 }
22902 {
22924 }
22927 VISIBILITY_HIDDEN);
22928 }
22930 #define DEF0(B, N) \
22937 #define DEF4(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
22938 { NULL, NULL, NULL, NULL }
22939 #define DEF5(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
22948 #undef DEF0
22949 #undef DEF4
22950 #undef DEF5
22952 /* Expand a compare and swap pattern. */
22954 void
22956 {
22970 /* Normally the succ memory model must be stronger than fail, but in the
22971 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
22972 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
22979 {
22982 }
22985 {
22986 /* The CAS insn requires oldval and rval overlap, but we need to
22987 have a copy of oldval saved across the operation to tell if
22988 the operation is successful. */
22991 else
22997 }
22999 {
23000 /* Oldval must satisfy compare afterward. */
23008 }
23009 else
23010 {
23011 /* The oldval predicate varies by mode. Test it and force to reg. */
23019 }
23027 }
23029 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
23030 sequence implementing an atomic operation. */
23032 static void
23034 {
23041 {
23043 }
23044 }
23046 /* Split a compare and swap pattern. */
23048 void
23050 {
23051 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
23055 machine_mode mode;
23070 /* When OLDVAL is zero and we want the strong version we can emit a tighter
23071 loop:
23072 .label1:
23073 LD[A]XR rval, [mem]
23074 CBNZ rval, .label2
23075 ST[L]XR scratch, newval, [mem]
23076 CBNZ scratch, .label1
23077 .label2:
23078 CMP rval, 0. */
23084 {
23087 }
23090 /* The initial load can be relaxed for a __sync operation since a final
23091 barrier will be emitted to stop code hoisting. */
23094 else
23099 else
23100 {
23103 }
23111 {
23113 {
23114 /* Emit an explicit compare instruction, so that we can correctly
23115 track the condition codes. */
23118 }
23119 else
23125 }
23126 else
23131 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
23132 to set the condition flags. If this is not used it will be removed by
23133 later passes. */
23137 /* Emit any final barrier needed for a __sync operation. */
23140 }
23142 /* Split an atomic operation. */
23144 void
23147 {
23148 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
23156 rtx x;
23158 /* Split the atomic operation into a sequence. */
23166 else
23170 /* The initial load can be relaxed for a __sync operation since a final
23171 barrier will be emitted to stop code hoisting. */
23175 else
23179 {
23193 {
23196 }
23197 /* Fall through. */
23203 }
23209 {
23210 /* Emit an explicit compare instruction, so that we can correctly
23211 track the condition codes. */
23214 }
23215 else
23222 /* Emit any final barrier needed for a __sync operation. */
23225 }
23227 static void
23229 {
23230 /* Half-precision float operations. The compiler handles all operations
23231 with NULL libfuncs by converting to SFmode. */
23233 /* Conversions. */
23237 /* Arithmetic. */
23244 /* Comparisons. */
23252 }
23254 /* Target hook for c_mode_for_suffix. */
23255 static machine_mode
23257 {
23262 }
23264 /* We can only represent floating point constants which will fit in
23265 "quarter-precision" values. These values are characterised by
23266 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
23267 by:
23269 (-1)^s * (n/16) * 2^r
23271 Where:
23272 's' is the sign bit.
23273 'n' is an integer in the range 16 <= n <= 31.
23274 'r' is an integer in the range -3 <= r <= 4. */
23276 /* Return true iff X can be represented by a quarter-precision
23277 floating point immediate operand X. Note, we cannot represent 0.0. */
23278 bool
23280 {
23281 /* This represents our current view of how many bits
23282 make up the mantissa. */
23299 /* We cannot represent infinities, NaNs or +/-zero. We won't
23300 know if we have +zero until we analyse the mantissa, but we
23301 can reject the other invalid values. */
23306 /* Extract exponent. */
23310 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
23311 highest (sign) bit, with a fixed binary point at bit point_pos.
23312 m1 holds the low part of the mantissa, m2 the high part.
23313 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
23314 bits for the mantissa, this can fail (low bits will be lost). */
23318 /* If the low part of the mantissa has bits set we cannot represent
23319 the value. */
23322 /* We have rejected the lower HOST_WIDE_INT, so update our
23323 understanding of how many bits lie in the mantissa and
23324 look only at the high HOST_WIDE_INT. */
23328 /* We can only represent values with a mantissa of the form 1.xxxx. */
23333 /* Having filtered unrepresentable values, we may now remove all
23334 but the highest 5 bits. */
23337 /* We cannot represent the value 0.0, so reject it. This is handled
23338 elsewhere. */
23342 /* Then, as bit 4 is always set, we can mask it off, leaving
23343 the mantissa in the range [0, 15]. */
23347 /* GCC internally does not use IEEE754-like encoding (where normalized
23348 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc).
23349 Our mantissa values are shifted 4 places to the left relative to
23350 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
23351 by 5 places to correct for GCC's representation. */
23355 }
23357 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
23358 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
23359 output MOVI/MVNI, ORR or BIC immediate. */
23363 {
23373 /* This will return true to show const_vector is legal for use as either
23374 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
23375 It will also update INFO to show how the immediate should be generated.
23376 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
23384 {
23387 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
23388 move immediate path. */
23391 else
23392 {
23401 else
23405 }
23406 }
23411 {
23423 else
23427 }
23428 else
23429 {
23430 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
23437 else
23441 }
23443 }
23447 {
23449 /* If a floating point number was passed and we desire to use it in an
23450 integer mode do the conversion to integer. */
23452 {
23457 }
23459 machine_mode vmode;
23460 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
23461 a 128 bit vector mode. */
23467 }
23469 /* Return the output string to use for moving immediate CONST_VECTOR
23470 into an SVE register. */
23474 {
23486 {
23489 {
23492 }
23493 else
23494 {
23501 else
23504 }
23506 }
23509 {
23515 }
23518 {
23521 else
23522 {
23532 }
23533 }
23538 }
23540 /* Return the asm template for a PTRUES. CONST_UNSPEC is the
23541 aarch64_sve_ptrue_svpattern_immediate that describes the predicate
23542 pattern. */
23546 {
23557 }
23559 /* Split operands into moves from op[1] + op[2] into op[0]. */
23561 void
23563 {
23574 {
23575 /* No-op move. Can't split to nothing; emit something. */
23578 }
23580 /* Preserve register attributes for variable tracking. */
23585 /* Special case of reversed high/low parts. */
23588 {
23592 }
23594 {
23595 /* Try to avoid unnecessary moves if part of the result
23596 is in the right place already. */
23601 }
23602 else
23603 {
23608 }
23609 }
23611 /* vec_perm support. */
23613 struct expand_vec_perm_d
23614 {
23616 vec_perm_indices perm;
23617 machine_mode vmode;
23618 machine_mode op_mode;
23623 };
23627 /* Generate a variable permutation. */
23629 static void
23631 {
23642 {
23644 {
23645 /* Expand the argument to a V16QI mode by duplicating it. */
23649 }
23650 else
23651 {
23653 }
23654 }
23655 else
23656 {
23657 rtx pair;
23660 {
23664 }
23665 else
23666 {
23670 }
23671 }
23672 }
23674 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
23675 NELT is the number of elements in the vector. */
23677 void
23680 {
23683 rtx mask;
23685 /* The TBL instruction does not use a modulo index, so we must take care
23686 of that ourselves. */
23691 /* For big-endian, we also need to reverse the index within the vector
23692 (but not which vector). */
23694 {
23695 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
23700 }
23702 }
23704 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
23706 static void
23708 {
23712 }
23714 /* Expand an SVE vec_perm with the given operands. */
23716 void
23718 {
23721 /* Enforced by the pattern condition. */
23724 /* Note: vec_perm indices are supposed to wrap when they go beyond the
23725 size of the two value vectors, i.e. the upper bits of the indices
23726 are effectively ignored. SVE TBL instead produces 0 for any
23727 out-of-range indices, so we need to modulo all the vec_perm indices
23728 to ensure they are all in range. */
23731 /* Check if the sel only references the first values vector. */
23734 {
23737 }
23739 /* Check if the two values vectors are the same. */
23741 {
23747 }
23749 /* Run TBL on for each value vector and combine the results. */
23756 {
23761 }
23768 else
23770 }
23772 /* Recognize patterns suitable for the TRN instructions. */
23773 static bool
23775 {
23776 HOST_WIDE_INT odd;
23784 /* Note that these are little-endian tests.
23785 We correct for big-endian later. */
23792 /* Success! */
23798 /* We don't need a big-endian lane correction for SVE; see the comment
23799 at the head of aarch64-sve.md for details. */
23801 {
23804 }
23810 }
23812 /* Try to re-encode the PERM constant so it combines odd and even elements.
23813 This rewrites constants such as {0, 1, 4, 5}/V4SF to {0, 2}/V2DI.
23814 We retry with this new constant with the full suite of patterns. */
23815 static bool
23817 {
23818 expand_vec_perm_d newd;
23824 /* Get the new mode. Always twice the size of the inner
23825 and half the elements. */
23834 /* to_constant is safe since this routine is specific to Advanced SIMD
23835 vectors. */
23838 vec_perm_builder newpermconst;
23841 /* Convert the perm constant if we can. Require even, odd as the pairs. */
23843 {
23846 poly_int64 newelt;
23850 }
23865 }
23867 /* Recognize patterns suitable for the UZP instructions. */
23868 static bool
23870 {
23871 HOST_WIDE_INT odd;
23878 /* Note that these are little-endian tests.
23879 We correct for big-endian later. */
23885 /* Success! */
23891 /* We don't need a big-endian lane correction for SVE; see the comment
23892 at the head of aarch64-sve.md for details. */
23894 {
23897 }
23903 }
23905 /* Recognize patterns suitable for the ZIP instructions. */
23906 static bool
23908 {
23917 /* Note that these are little-endian tests.
23918 We correct for big-endian later. */
23926 /* Success! */
23932 /* We don't need a big-endian lane correction for SVE; see the comment
23933 at the head of aarch64-sve.md for details. */
23935 {
23938 }
23944 }
23946 /* Recognize patterns for the EXT insn. */
23948 static bool
23950 {
23951 HOST_WIDE_INT location;
23952 rtx offset;
23954 /* The first element always refers to the first vector.
23955 Check if the extracted indices are increasing by one. */
23961 /* Success! */
23965 /* The case where (location == 0) is a no-op for both big- and little-endian,
23966 and is removed by the mid-end at optimization levels -O1 and higher.
23968 We don't need a big-endian lane correction for SVE; see the comment
23969 at the head of aarch64-sve.md for details. */
23971 {
23972 /* After setup, we want the high elements of the first vector (stored
23973 at the LSB end of the register), and the low elements of the second
23974 vector (stored at the MSB end of the register). So swap. */
23976 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
23977 to_constant () is safe since this is restricted to Advanced SIMD
23978 vectors. */
23980 }
23986 UNSPEC_EXT));
23988 }
23990 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
23991 within each 64-bit, 32-bit or 16-bit granule. */
23993 static bool
23995 {
23996 HOST_WIDE_INT diff;
23998 machine_mode pred_mode;
24008 else
24011 {
24014 }
24016 {
24019 }
24021 {
24024 }
24025 else
24033 /* Success! */
24038 {
24043 }
24047 }
24049 /* Recognize patterns for the REV insn, which reverses elements within
24050 a full vector. */
24052 static bool
24054 {
24063 /* Success! */
24070 }
24072 static bool
24074 {
24076 rtx in0;
24077 HOST_WIDE_INT elt;
24079 rtx lane;
24090 /* Success! */
24094 /* The generic preparation in aarch64_expand_vec_perm_const_1
24095 swaps the operand order and the permute indices if it finds
24096 d->perm[0] to be in the second operand. Thus, we can always
24097 use d->op0 and need not do any extra arithmetic to get the
24098 correct lane number. */
24106 }
24108 static bool
24110 {
24114 /* Make sure that the indices are constant. */
24123 /* Generic code will try constant permutation twice. Once with the
24124 original mode and again with the elements lowered to QImode.
24125 So wait and don't do the selector expansion ourselves. */
24129 /* to_constant is safe since this routine is specific to Advanced SIMD
24130 vectors. */
24133 /* If big-endian and two vectors we end up with a weird mixed-endian
24134 mode on NEON. Reverse the index within each word but not the word
24135 itself. to_constant is safe because we checked is_constant above. */
24145 }
24147 /* Try to implement D using an SVE TBL instruction. */
24149 static bool
24151 {
24154 /* Permuting two variable-length vectors could overflow the
24155 index range. */
24166 else
24169 }
24171 /* Try to implement D using SVE dup instruction. */
24173 static bool
24175 {
24196 }
24198 /* Try to implement D using SVE SEL instruction. */
24200 static bool
24202 {
24228 /* Build a predicate that is true when op0 elements should be used. */
24231 {
24235 }
24239 /* TARGET = PRED ? OP0 : OP1. */
24242 }
24244 /* Recognize patterns suitable for the INS instructions. */
24245 static bool
24247 {
24254 /* to_constant is safe since this routine is specific to Advanced SIMD
24255 vectors. */
24262 {
24263 HOST_WIDE_INT elt;
24269 {
24272 }
24274 }
24277 {
24280 {
24286 }
24290 }
24300 {
24303 }
24316 }
24318 static bool
24320 {
24323 /* The pattern matching functions above are written to look for a small
24324 number to begin the sequence (0, 1, N/2). If we begin with an index
24325 from the second operand, we can swap the operands. */
24328 {
24331 }
24338 {
24340 {
24366 }
24367 else
24368 {
24371 }
24372 }
24374 }
24376 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
24378 static bool
24382 {
24385 /* Check whether the mask can be applied to a single vector. */
24390 {
24393 }
24395 {
24398 }
24399 else
24412 else
24424 }
24425 /* Generate a byte permute mask for a register of mode MODE,
24426 which has NUNITS units. */
24428 rtx
24430 {
24431 /* We have to reverse each vector because we dont have
24432 a permuted load that can reverse-load according to ABI rules. */
24433 rtx mask;
24446 }
24448 /* Expand an SVE integer comparison using the SVE equivalent of:
24450 (set TARGET (CODE OP0 OP1)). */
24452 void
24454 {
24461 }
24463 /* Return the UNSPEC_COND_* code for comparison CODE. */
24465 static unsigned int
24467 {
24469 {
24486 }
24487 }
24489 /* Emit:
24491 (set TARGET (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
24493 where <X> is the operation associated with comparison CODE.
24494 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24496 static void
24499 {
24505 }
24507 /* Emit the SVE equivalent of:
24509 (set TMP1 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X1>))
24510 (set TMP2 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X2>))
24511 (set TARGET (ior:PRED_MODE TMP1 TMP2))
24513 where <Xi> is the operation associated with comparison CODEi.
24514 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24516 static void
24519 {
24526 }
24528 /* Emit the SVE equivalent of:
24530 (set TMP (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
24531 (set TARGET (not TMP))
24533 where <X> is the operation associated with comparison CODE.
24534 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24536 static void
24539 {
24544 }
24546 /* Expand an SVE floating-point comparison using the SVE equivalent of:
24548 (set TARGET (CODE OP0 OP1))
24550 If CAN_INVERT_P is true, the caller can also handle inverted results;
24551 return true if the result is in fact inverted. */
24553 bool
24556 {
24562 {
24564 /* UNORDERED has no immediate form. */
24566 /* fall through */
24573 {
24574 /* There is native support for the comparison. */
24577 }
24580 /* This is a trapping operation (LT or GT). */
24586 {
24587 /* This would trap for signaling NaNs. */
24592 }
24593 /* fall through */
24599 {
24600 /* Work out which elements are ordered. */
24606 /* Test the opposite condition for the ordered elements,
24607 then invert the result. */
24610 else
24613 {
24617 }
24621 }
24625 /* ORDERED has no immediate form. */
24631 }
24633 /* There is native support for the inverse comparison. */
24636 {
24639 }
24642 }
24644 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
24645 of the data being selected and CMP_MODE is the mode of the values being
24646 compared. */
24648 void
24651 {
24655 {
24659 }
24660 else
24665 /* The "false" value can only be zero if the "true" value is a constant. */
24672 }
24674 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
24675 true. However due to issues with register allocation it is preferable
24676 to avoid tieing integer scalar and FP scalar modes. Executing integer
24677 operations in general registers is better than treating them as scalar
24678 vector operations. This reduces latency and avoids redundant int<->FP
24679 moves. So tie modes if they are either the same class, or vector modes
24680 with other vector modes, vector structs or any scalar mode. */
24682 static bool
24684 {
24694 /* We specifically want to allow elements of "structure" modes to
24695 be tieable to the structure. This more general condition allows
24696 other rarer situations too. The reason we don't extend this to
24697 predicate modes is that there are no predicate structure modes
24698 nor any specific instructions for extracting part of a predicate
24699 register. */
24704 /* Also allow any scalar modes with vectors. */
24710 }
24712 /* Return a new RTX holding the result of moving POINTER forward by
24713 AMOUNT bytes. */
24715 static rtx
24717 {
24722 }
24724 /* Return a new RTX holding the result of moving POINTER forward by the
24725 size of the mode it points to. */
24727 static rtx
24729 {
24731 }
24733 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
24734 MODE bytes. */
24736 static void
24738 machine_mode mode)
24739 {
24740 /* Handle 256-bit memcpy separately. We do this by making 2 adjacent memory
24741 address copies using V4SImode so that we can use Q registers. */
24743 {
24747 /* "Cast" the pointers to the correct mode. */
24750 /* Emit the memcpy. */
24755 /* Move the pointers forward. */
24759 }
24763 /* "Cast" the pointers to the correct mode. */
24766 /* Emit the memcpy. */
24769 /* Move the pointers forward. */
24772 }
24774 /* Expand a cpymem using the MOPS extension. OPERANDS are taken
24775 from the cpymem pattern. Return true iff we succeeded. */
24776 static bool
24778 {
24782 /* All three registers are changed by the instruction, so each one
24783 must be a fresh pseudo. */
24792 }
24794 /* Expand cpymem, as if from a __builtin_memcpy. Return true if
24795 we succeed, otherwise return false, indicating that a libcall to
24796 memcpy should be emitted. */
24798 bool
24800 {
24804 rtx base;
24807 /* Variable-sized memcpy can go through the MOPS expansion if available. */
24813 /* Try to inline up to 256 bytes or use the MOPS threshold if available. */
24814 unsigned HOST_WIDE_INT max_copy_size
24819 /* Large constant-sized cpymem should go through MOPS when possible.
24820 It should be a win even for size optimization in the general case.
24821 For speed optimization the choice between MOPS and the SIMD sequence
24822 depends on the size of the copy, rather than number of instructions,
24823 alignment etc. */
24829 /* Default to 256-bit LDP/STP on large copies, however small copies, no SIMD
24830 support or slow 256-bit LDP/STP fall back to 128-bit chunks. */
24832 || !TARGET_SIMD
24837 /* Emit an inline load+store sequence and count the number of operations
24838 involved. We use a simple count of just the loads and stores emitted
24839 rather than rtx_insn count as all the pointer adjustments and reg copying
24840 in this function will get optimized away later in the pipeline. */
24850 /* Convert size to bits to make the rest of the code simpler. */
24854 {
24855 /* Find the largest mode in which to do the copy in without over reading
24856 or writing. */
24857 opt_scalar_int_mode mode_iter;
24866 /* Prefer Q-register accesses for the last bytes. */
24871 /* A single block copy is 1 load + 1 store. */
24875 /* Emit trailing copies using overlapping unaligned accesses
24876 (when !STRICT_ALIGNMENT) - this is smaller and faster. */
24878 {
24885 }
24886 }
24889 /* MOPS sequence requires 3 instructions for the memory copying + 1 to move
24890 the constant size into a register. */
24893 /* If MOPS is available at this point we don't consider the libcall as it's
24894 not a win even on code size. At this point only consider MOPS if
24895 optimizing for size. For speed optimizations we will have chosen between
24896 the two based on copy size already. */
24898 {
24903 }
24905 /* A memcpy libcall in the worst case takes 3 instructions to prepare the
24906 arguments + 1 for the call. When MOPS is not available and we're
24907 optimizing for size a libcall may be preferable. */
24914 }
24916 /* Like aarch64_copy_one_block_and_progress_pointers, except for memset where
24917 SRC is a register we have created with the duplicated value to be set. */
24918 static void
24920 machine_mode mode)
24921 {
24922 /* If we are copying 128bits or 256bits, we can do that straight from
24923 the SIMD register we prepared. */
24925 {
24927 /* "Cast" the *dst to the correct mode. */
24929 /* Emit the memset. */
24933 /* Move the pointers forward. */
24936 }
24938 {
24939 /* "Cast" the *dst to the correct mode. */
24941 /* Emit the memset. */
24943 /* Move the pointers forward. */
24946 }
24947 /* For copying less, we have to extract the right amount from src. */
24950 /* "Cast" the *dst to the correct mode. */
24952 /* Emit the memset. */
24954 /* Move the pointer forward. */
24956 }
24958 /* Expand a setmem using the MOPS instructions. OPERANDS are the same
24959 as for the setmem pattern. Return true iff we succeed. */
24960 static bool
24962 {
24966 /* The first two registers are changed by the instruction, so both
24967 of them must be a fresh pseudo. */
24976 }
24978 /* Expand setmem, as if from a __builtin_memset. Return true if
24979 we succeed, otherwise return false. */
24981 bool
24983 {
24988 rtx base;
24991 /* If we don't have SIMD registers or the size is variable use the MOPS
24992 inlined sequence if possible. */
24998 /* Default the maximum to 256-bytes when considering only libcall vs
24999 SIMD broadcast sequence. */
25007 /* The MOPS sequence takes:
25008 3 instructions for the memory storing
25009 + 1 to move the constant size into a reg
25010 + 1 if VAL is a non-zero constant to move into a reg
25011 (zero constants can use XZR directly). */
25013 /* A libcall to memset in the worst case takes 3 instructions to prepare
25014 the arguments + 1 for the call. */
25017 /* Upper bound check. For large constant-sized setmem use the MOPS sequence
25018 when available. */
25023 /* Attempt a sequence with a vector broadcast followed by stores.
25024 Count the number of operations involved to see if it's worth it
25025 against the alternatives. A simple counter simd_ops on the
25026 algorithmically-relevant operations is used rather than an rtx_insn count
25027 as all the pointer adjusmtents and mode reinterprets will be optimized
25028 away later. */
25035 /* Prepare the val using a DUP/MOVI v0.16B, val. */
25038 simd_ops++;
25039 /* Convert len to bits to make the rest of the code simpler. */
25042 /* Maximum amount to copy in one go. We allow 256-bit chunks based on the
25043 AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS tuning parameter. */
25049 {
25050 /* Find the largest mode in which to do the copy without
25051 over writing. */
25052 opt_scalar_int_mode mode_iter;
25061 simd_ops++;
25064 /* Do certain trailing copies as overlapping if it's going to be
25065 cheaper. i.e. less instructions to do so. For instance doing a 15
25066 byte copy it's more efficient to do two overlapping 8 byte copies than
25067 8 + 4 + 2 + 1. Only do this when -mstrict-align is not supplied. */
25069 {
25075 }
25076 }
25081 {
25082 /* When optimizing for size we have 3 options: the SIMD broadcast sequence,
25083 call to memset or the MOPS expansion. */
25088 /* If MOPS is not available or not shorter pick a libcall if the SIMD
25089 sequence is too long. */
25094 }
25096 /* At this point the SIMD broadcast sequence is the best choice when
25097 optimizing for speed. */
25100 }
25103 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
25104 SImode stores. Handle the case when the constant has identical
25105 bottom and top halves. This is beneficial when the two stores can be
25106 merged into an STP and we avoid synthesising potentially expensive
25107 immediates twice. Return true if such a split is possible. */
25109 bool
25111 {
25120 unsigned int orig_cost
25122 unsigned int lo_cost
25125 /* We want to transform:
25126 MOV x1, 49370
25127 MOVK x1, 0x140, lsl 16
25128 MOVK x1, 0xc0da, lsl 32
25129 MOVK x1, 0x140, lsl 48
25130 STR x1, [x0]
25131 into:
25132 MOV w1, 49370
25133 MOVK w1, 0x140, lsl 16
25134 STP w1, w1, [x0]
25135 So we want to perform this only when we save two instructions
25136 or more. When optimizing for size, however, accept any code size
25137 savings we can. */
25152 /* Don't emit an explicit store pair as this may not be always profitable.
25153 Let the sched-fusion logic decide whether to merge them. */
25158 }
25160 /* Generate RTL for a conditional branch with rtx comparison CODE in
25161 mode CC_MODE. The destination of the unlikely conditional branch
25162 is LABEL_REF. */
25164 void
25166 rtx label_ref)
25167 {
25168 rtx x;
25171 const0_rtx);
25175 pc_rtx);
25177 }
25179 /* Generate DImode scratch registers for 128-bit (TImode) addition.
25181 OP1 represents the TImode destination operand 1
25182 OP2 represents the TImode destination operand 2
25183 LOW_DEST represents the low half (DImode) of TImode operand 0
25184 LOW_IN1 represents the low half (DImode) of TImode operand 1
25185 LOW_IN2 represents the low half (DImode) of TImode operand 2
25186 HIGH_DEST represents the high half (DImode) of TImode operand 0
25187 HIGH_IN1 represents the high half (DImode) of TImode operand 1
25188 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
25190 void
25195 {
25204 }
25206 /* Generate DImode scratch registers for 128-bit (TImode) subtraction.
25208 This function differs from 'arch64_addti_scratch_regs' in that
25209 OP1 can be an immediate constant (zero). We must call
25210 subreg_highpart_offset with DImode and TImode arguments, otherwise
25211 VOIDmode will be used for the const_int which generates an internal
25212 error from subreg_size_highpart_offset which does not expect a size of zero.
25214 OP1 represents the TImode destination operand 1
25215 OP2 represents the TImode destination operand 2
25216 LOW_DEST represents the low half (DImode) of TImode operand 0
25217 LOW_IN1 represents the low half (DImode) of TImode operand 1
25218 LOW_IN2 represents the low half (DImode) of TImode operand 2
25219 HIGH_DEST represents the high half (DImode) of TImode operand 0
25220 HIGH_IN1 represents the high half (DImode) of TImode operand 1
25221 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
25224 void
25229 {
25242 }
25244 /* Generate RTL for 128-bit (TImode) subtraction with overflow.
25246 OP0 represents the TImode destination operand 0
25247 LOW_DEST represents the low half (DImode) of TImode operand 0
25248 LOW_IN1 represents the low half (DImode) of TImode operand 1
25249 LOW_IN2 represents the low half (DImode) of TImode operand 2
25250 HIGH_DEST represents the high half (DImode) of TImode operand 0
25251 HIGH_IN1 represents the high half (DImode) of TImode operand 1
25252 HIGH_IN2 represents the high half (DImode) of TImode operand 2
25253 UNSIGNED_P is true if the operation is being performed on unsigned
25254 values. */
25255 void
25259 {
25261 {
25266 else
25268 }
25269 else
25270 {
25274 else
25275 {
25278 }
25283 else
25285 }
25290 }
25292 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
25294 static unsigned HOST_WIDE_INT
25296 {
25299 else
25301 }
25303 static rtx
25306 {
25310 insn_code icode;
25321 {
25349 }
25354 {
25357 }
25366 {
25369 }
25375 }
25377 static rtx
25380 {
25384 insn_code icode;
25396 {
25420 }
25427 {
25430 }
25438 {
25439 /* Treat the ccmp patterns as canonical and use them where possible,
25440 but fall back to ccmp_rev patterns if there's no other option. */
25449 else
25450 {
25453 }
25455 }
25466 {
25469 }
25475 }
25477 #undef TARGET_GEN_CCMP_FIRST
25478 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
25480 #undef TARGET_GEN_CCMP_NEXT
25481 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
25483 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
25484 instruction fusion of some sort. */
25486 static bool
25488 {
25490 }
25493 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
25494 should be kept together during scheduling. */
25496 static bool
25498 {
25499 rtx set_dest;
25502 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
25509 {
25510 /* We are trying to match:
25511 prev (mov) == (set (reg r0) (const_int imm16))
25512 curr (movk) == (set (zero_extract (reg r0)
25513 (const_int 16)
25514 (const_int 16))
25515 (const_int imm16_1)) */
25527 {
25529 }
25530 }
25533 {
25535 /* We're trying to match:
25536 prev (adrp) == (set (reg r1)
25537 (high (symbol_ref ("SYM"))))
25538 curr (add) == (set (reg r0)
25539 (lo_sum (reg r1)
25540 (symbol_ref ("SYM"))))
25541 Note that r0 need not necessarily be the same as r1, especially
25542 during pre-regalloc scheduling. */
25546 {
25554 }
25555 }
25558 {
25560 /* We're trying to match:
25561 prev (movk) == (set (zero_extract (reg r0)
25562 (const_int 16)
25563 (const_int 32))
25564 (const_int imm16_1))
25565 curr (movk) == (set (zero_extract (reg r0)
25566 (const_int 16)
25567 (const_int 48))
25568 (const_int imm16_2)) */
25584 }
25586 {
25587 /* We're trying to match:
25588 prev (adrp) == (set (reg r0)
25589 (high (symbol_ref ("SYM"))))
25590 curr (ldr) == (set (reg r1)
25591 (mem (lo_sum (reg r0)
25592 (symbol_ref ("SYM")))))
25593 or
25594 curr (ldr) == (set (reg r1)
25595 (zero_extend (mem
25596 (lo_sum (reg r0)
25597 (symbol_ref ("SYM")))))) */
25600 {
25613 }
25614 }
25616 /* Fuse compare (CMP/CMN/TST/BICS) and conditional branch. */
25624 /* Fuse flag-setting ALU instructions and conditional branch. */
25627 {
25629 rtx cc_reg_1;
25634 && prev
25636 {
25639 /* FIXME: this misses some which is considered simple arthematic
25640 instructions for ThunderX. Simple shifts are missed here. */
25646 }
25647 }
25649 /* Fuse ALU instructions and CBZ/CBNZ. */
25651 && curr_set
25654 {
25655 /* We're trying to match:
25656 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
25657 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
25658 (const_int 0))
25659 (label_ref ("SYM"))
25660 (pc)) */
25667 {
25668 /* Fuse ALU operations followed by conditional branch instruction. */
25670 {
25691 }
25692 }
25693 }
25695 /* Fuse A+B+1 and A-B-1 */
25698 {
25699 /* We're trying to match:
25700 prev == (set (r0) (plus (r0) (r1)))
25701 curr == (set (r0) (plus (r0) (const_int 1)))
25702 or:
25703 prev == (set (r0) (minus (r0) (r1)))
25704 curr == (set (r0) (plus (r0) (const_int -1))) */
25721 }
25724 }
25726 /* Return true iff the instruction fusion described by OP is enabled. */
25728 bool
25730 {
25732 }
25734 /* If MEM is in the form of [base+offset], extract the two parts
25735 of address and set to BASE and OFFSET, otherwise return false
25736 after clearing BASE and OFFSET. */
25738 bool
25740 {
25741 rtx addr;
25748 {
25752 }
25756 {
25760 }
25766 }
25768 /* Types for scheduling fusion. */
25769 enum sched_fusion_type
25770 {
25772 SCHED_FUSION_LD_SIGN_EXTEND,
25773 SCHED_FUSION_LD_ZERO_EXTEND,
25774 SCHED_FUSION_LD,
25775 SCHED_FUSION_ST,
25776 SCHED_FUSION_NUM
25777 };
25779 /* If INSN is a load or store of address in the form of [base+offset],
25780 extract the two parts and set to BASE and OFFSET. Return scheduling
25781 fusion type this INSN is. */
25783 static enum sched_fusion_type
25785 {
25803 {
25808 }
25810 {
25815 }
25820 {
25823 }
25824 else
25831 }
25833 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
25835 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
25836 and PRI are only calculated for these instructions. For other instruction,
25837 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
25838 type instruction fusion can be added by returning different priorities.
25840 It's important that irrelevant instructions get the largest FUSION_PRI. */
25842 static void
25845 {
25855 {
25859 }
25861 /* Set FUSION_PRI according to fusion type and base register. */
25864 /* Calculate PRI. */
25867 /* INSN with smaller offset goes first. */
25871 else
25876 }
25878 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
25879 Adjust priority of sha1h instructions so they are scheduled before
25880 other SHA1 instructions. */
25882 static int
25884 {
25888 {
25893 }
25896 }
25898 /* If REVERSED is null, return true if memory reference *MEM2 comes
25899 immediately after memory reference *MEM1. Do not change the references
25900 in this case.
25902 Otherwise, check if *MEM1 and *MEM2 are consecutive memory references and,
25903 if they are, try to make them use constant offsets from the same base
25904 register. Return true on success. When returning true, set *REVERSED
25905 to true if *MEM1 comes after *MEM2, false if *MEM1 comes before *MEM2. */
25906 static bool
25908 {
25926 /* Make sure at least one memory is in base+offset form. */
25930 /* If both mems already use the same base register, just check the
25931 offsets. */
25933 {
25941 {
25944 }
25947 }
25949 /* Otherwise, check whether the MEM_EXPRs and MEM_OFFSETs together
25950 guarantee that the values are consecutive. */
25955 {
25956 poly_int64 expr_offset1;
25957 poly_int64 expr_offset2;
25963 || !expr_base2
25972 ;
25975 else
25979 {
25981 {
25985 }
25986 else
25987 {
25991 }
25992 }
25994 }
25997 }
25999 /* Return true if MEM1 and MEM2 can be combined into a single access
26000 of mode MODE, with the combined access having the same address as MEM1. */
26002 bool
26004 {
26008 }
26010 /* Given OPERANDS of consecutive load/store, check if we can merge
26011 them into ldp/stp. LOAD is true if they are load instructions.
26012 MODE is the mode of memory operands. */
26014 bool
26016 machine_mode mode)
26017 {
26021 /* Allow the tuning structure to disable LDP instruction formation
26022 from combining instructions (e.g., in peephole2).
26023 TODO: Implement fine-grained tuning control for LDP and STP:
26024 1. control policies for load and store separately;
26025 2. support the following policies:
26026 - default (use what is in the tuning structure)
26027 - always
26028 - never
26029 - aligned (only if the compiler can prove that the
26030 load will be aligned to 2 * element_size) */
26036 {
26046 }
26047 else
26048 {
26053 }
26055 /* The mems cannot be volatile. */
26059 /* If we have SImode and slow unaligned ldp,
26060 check the alignment to be at least 8 byte. */
26064 && !optimize_size
26068 /* Check if the addresses are in the form of [base+offset]. */
26073 /* The operands must be of the same size. */
26077 /* One of the memory accesses must be a mempair operand.
26078 If it is not the first one, they need to be swapped by the
26079 peephole. */
26086 else
26091 else
26094 /* Check if the registers are of same class. */
26099 }
26101 /* Given OPERANDS of consecutive load/store that can be merged,
26102 swap them if they are not in ascending order. */
26103 void
26105 {
26113 {
26114 /* Irrespective of whether this is a load or a store,
26115 we do the same swap. */
26118 }
26119 }
26121 /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a
26122 comparison between the two. */
26123 int
26125 {
26128 }
26130 /* Taking X and Y to be pairs of RTX, one pointing to a MEM rtx and the
26131 other pointing to a REG rtx containing an offset, compare the offsets
26132 of the two pairs.
26134 Return:
26136 1 iff offset (X) > offset (Y)
26137 0 iff offset (X) == offset (Y)
26138 -1 iff offset (X) < offset (Y) */
26139 int
26141 {
26148 else
26153 else
26156 /* Extract the offsets. */
26163 }
26165 /* Given OPERANDS of consecutive load/store, check if we can merge
26166 them into ldp/stp by adjusting the offset. LOAD is true if they
26167 are load instructions. MODE is the mode of memory operands.
26169 Given below consecutive stores:
26171 str w1, [xb, 0x100]
26172 str w1, [xb, 0x104]
26173 str w1, [xb, 0x108]
26174 str w1, [xb, 0x10c]
26176 Though the offsets are out of the range supported by stp, we can
26177 still pair them after adjusting the offset, like:
26179 add scratch, xb, 0x100
26180 stp w1, w1, [scratch]
26181 stp w1, w1, [scratch, 0x8]
26183 The peephole patterns detecting this opportunity should guarantee
26184 the scratch register is avaliable. */
26186 bool
26188 machine_mode mode)
26189 {
26196 {
26198 {
26203 }
26205 /* Do not attempt to merge the loads if the loads clobber each other. */
26210 }
26211 else
26213 {
26216 }
26218 /* Skip if memory operand is by itself valid for ldp/stp. */
26223 {
26224 /* The mems cannot be volatile. */
26228 /* Check if the addresses are in the form of [base+offset]. */
26232 }
26234 /* Check if the registers are of same class. */
26240 {
26243 }
26244 else
26245 {
26248 }
26250 /* Only the last register in the order in which they occur
26251 may be clobbered by the load. */
26257 /* Check if the bases are same. */
26267 /* Check if the offsets can be put in the right order to do a ldp/stp. */
26269 aarch64_host_wide_int_compare);
26275 /* Check that offsets are within range of each other. The ldp/stp
26276 instructions have 7 bit immediate offsets, so use 0x80. */
26280 /* The offsets must be aligned with respect to each other. */
26284 /* If we have SImode and slow unaligned ldp,
26285 check the alignment to be at least 8 byte. */
26289 && !optimize_size
26294 }
26296 /* Given OPERANDS of consecutive load/store, this function pairs them
26297 into LDP/STP after adjusting the offset. It depends on the fact
26298 that the operands can be sorted so the offsets are correct for STP.
26299 MODE is the mode of memory operands. CODE is the rtl operator
26300 which should be applied to all memory operands, it's SIGN_EXTEND,
26301 ZERO_EXTEND or UNKNOWN. */
26303 bool
26306 {
26313 /* We make changes on a copy as we may still bail out. */
26317 /* Sort the operands. Note for cases as below:
26318 [base + 0x310] = A
26319 [base + 0x320] = B
26320 [base + 0x330] = C
26321 [base + 0x320] = D
26322 We need stable sorting otherwise wrong data may be store to offset 0x320.
26323 Also note the dead store in above case should be optimized away, but no
26324 guarantees here. */
26326 aarch64_ldrstr_offset_compare);
26328 /* Copy the memory operands so that if we have to bail for some
26329 reason the original addresses are unchanged. */
26331 {
26336 }
26337 else
26338 {
26344 }
26351 /* Adjust offset so it can fit in LDP/STP instruction. */
26359 /* The base offset is optimally half way between the two STP/LDP offsets. */
26362 else
26363 /* However, due to issues with negative LDP/STP offset generation for
26364 larger modes, for DF, DD, DI and vector modes. we must not use negative
26365 addresses smaller than 9 signed unadjusted bits can store. This
26366 provides the most range in this case. */
26369 /* Adjust the base so that it is aligned with the addresses but still
26370 optimal. */
26372 /* Fix the offset, bearing in mind we want to make it bigger not
26373 smaller. */
26376 /* The negative range of LDP/STP is one larger than the positive range. */
26379 /* Check if base offset is too big or too small. We can attempt to resolve
26380 this issue by setting it to the maximum value and seeing if the offsets
26381 still fit. */
26383 {
26385 /* We must still make sure that the base offset is aligned with respect
26386 to the address. But it may not be made any bigger. */
26388 }
26390 /* Likewise for the case where the base is too small. */
26392 {
26395 }
26397 /* Offset of the first STP/LDP. */
26400 /* Offset of the second STP/LDP. */
26403 /* The offsets must be within the range of the LDP/STP instructions. */
26422 {
26427 }
26429 {
26434 }
26437 {
26446 }
26447 else
26448 {
26457 }
26459 /* Emit adjusting instruction. */
26461 /* Emit ldp/stp instructions. */
26469 }
26471 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
26472 it isn't worth branching around empty masked ops (including masked
26473 stores). */
26475 static bool
26477 {
26479 }
26481 /* Return 1 if pseudo register should be created and used to hold
26482 GOT address for PIC code. */
26484 bool
26486 {
26488 }
26490 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
26492 static int
26494 {
26496 {
26503 }
26506 }
26509 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
26510 return the log2 of that value. Otherwise return -1. */
26512 int
26514 {
26529 }
26531 /* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
26532 power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
26533 return n. Otherwise return -1. */
26535 int
26537 {
26538 REAL_VALUE_TYPE r0;
26546 {
26550 }
26552 }
26554 /* If X is a vector of equal CONST_DOUBLE values and that value is
26555 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
26557 int
26559 {
26577 }
26579 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
26580 to float.
26582 __fp16 always promotes through this hook.
26583 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
26584 through the generic excess precision logic rather than here. */
26586 static tree
26588 {
26594 }
26596 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
26598 static bool
26600 optimization_type opt_type)
26601 {
26603 {
26609 }
26610 }
26612 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
26614 static unsigned int
26617 {
26618 /* Polynomial invariant 1 == (VG / 2) - 1. */
26623 }
26625 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
26626 if MODE is [BH]Fmode, and punt to the generic implementation otherwise. */
26628 static bool
26630 {
26634 }
26636 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
26637 if MODE is [BH]Fmode, and punt to the generic implementation otherwise. */
26639 static bool
26641 {
26648 }
26650 /* Set the value of FLT_EVAL_METHOD.
26651 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
26653 0: evaluate all operations and constants, whose semantic type has at
26654 most the range and precision of type float, to the range and
26655 precision of float; evaluate all other operations and constants to
26656 the range and precision of the semantic type;
26658 N, where _FloatN is a supported interchange floating type
26659 evaluate all operations and constants, whose semantic type has at
26660 most the range and precision of _FloatN type, to the range and
26661 precision of the _FloatN type; evaluate all other operations and
26662 constants to the range and precision of the semantic type;
26664 If we have the ARMv8.2-A extensions then we support _Float16 in native
26665 precision, so we should set this to 16. Otherwise, we support the type,
26666 but want to evaluate expressions in float precision, so set this to
26667 0. */
26669 static enum flt_eval_method
26671 {
26673 {
26676 /* We can calculate either in 16-bit range and precision or
26677 32-bit range and precision. Make that decision based on whether
26678 we have native support for the ARMv8.2-A 16-bit floating-point
26679 instructions or not. */
26681 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
26688 }
26690 }
26692 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
26693 scheduled for speculative execution. Reject the long-running division
26694 and square-root instructions. */
26696 static bool
26698 {
26700 {
26718 }
26719 }
26721 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
26723 static int
26725 {
26729 /* PR_REGS isn't a useful pressure class because many predicate pseudo
26730 registers need to go in PR_LO_REGS at some point during their
26731 lifetime. Splitting it into two halves has the effect of making
26732 all predicates count against PR_LO_REGS, so that we try whenever
26733 possible to restrict the number of live predicates to 8. This
26734 greatly reduces the amount of spilling in certain loops. */
26738 }
26740 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
26742 static bool
26745 {
26763 /* Don't allow changes between predicate modes and other modes.
26764 Only predicate registers can hold predicate modes and only
26765 non-predicate registers can hold non-predicate modes, so any
26766 attempt to mix them would require a round trip through memory. */
26770 /* Don't allow changes between partial SVE modes and other modes.
26771 The contents of partial SVE modes are distributed evenly across
26772 the register, whereas GCC expects them to be clustered together. */
26776 /* Similarly reject changes between partial SVE modes that have
26777 different patterns of significant and insignificant bits. */
26783 /* Don't allow changes between partial and other registers only if
26784 one is a normal SIMD register, allow only if not larger than 64-bit. */
26790 {
26791 /* Don't allow changes between SVE modes and other modes that might
26792 be bigger than 128 bits. In particular, OImode, CImode and XImode
26793 divide into 128-bit quantities while SVE modes divide into
26794 BITS_PER_SVE_VECTOR quantities. */
26799 }
26802 {
26803 /* Don't allow changes between SVE data modes and non-SVE modes.
26804 See the comment at the head of aarch64-sve.md for details. */
26808 /* Don't allow changes in element size: lane 0 of the new vector
26809 would not then be lane 0 of the old vector. See the comment
26810 above aarch64_maybe_expand_sve_subreg_move for a more detailed
26811 description.
26813 In the worst case, this forces a register to be spilled in
26814 one mode and reloaded in the other, which handles the
26815 endianness correctly. */
26818 }
26820 }
26822 /* Implement TARGET_EARLY_REMAT_MODES. */
26824 static void
26826 {
26827 /* SVE values are not normally live across a call, so it should be
26828 worth doing early rematerialization even in VL-specific mode. */
26832 }
26834 /* Override the default target speculation_safe_value. */
26835 static rtx
26838 {
26839 /* Maybe we should warn if falling back to hard barriers. They are
26840 likely to be noticably more expensive than the alternative below. */
26852 }
26854 /* Implement TARGET_ESTIMATED_POLY_VALUE.
26855 Look into the tuning structure for an estimate.
26856 KIND specifies the type of requested estimate: min, max or likely.
26857 For cores with a known SVE width all three estimates are the same.
26858 For generic SVE tuning we want to distinguish the maximum estimate from
26859 the minimum and likely ones.
26860 The likely estimate is the same as the minimum in that case to give a
26861 conservative behavior of auto-vectorizing with SVE when it is a win
26862 even for 128-bit SVE.
26863 When SVE width information is available VAL.coeffs[1] is multiplied by
26864 the number of VQ chunks over the initial Advanced SIMD 128 bits. */
26866 static HOST_WIDE_INT
26868 poly_value_estimate_kind kind
26870 {
26873 /* If there is no core-specific information then the minimum and likely
26874 values are based on 128-bit vectors and the maximum is based on
26875 the architectural maximum of 2048 bits. */
26878 {
26884 }
26886 /* Allow sve_width to be a bitmask of different VL, treating the lowest
26887 as likely. This could be made more general if future -mtune options
26888 need it to be. */
26891 else
26894 /* If the core provides width information, use that. */
26897 }
26900 /* Return true for types that could be supported as SIMD return or
26901 argument types. */
26903 static bool
26905 {
26907 {
26910 }
26912 }
26914 /* Return true for types that currently are supported as SIMD return
26915 or argument types. */
26917 static bool
26919 {
26927 }
26929 /* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */
26931 static int
26936 {
26940 poly_uint64 vec_bits;
26945 /* For now, SVE simdclones won't produce illegal simdlen, So only check
26946 const simdlens here. */
26952 {
26957 }
26962 {
26964 ;
26967 "GCC does not currently support mixed size types "
26971 "GCC does not currently support return type %qT "
26973 else
26976 ret_type);
26978 }
26986 {
26991 {
26993 ;
26996 "GCC does not currently support mixed size types "
26998 else
27000 "GCC does not currently support argument type %qT "
27003 }
27004 }
27010 {
27014 }
27015 else
27016 {
27019 /* For now, SVE simdclones won't produce illegal simdlen, So only check
27020 const simdlens here. */
27023 {
27026 "GCC does not currently support simdlen %wd for "
27030 }
27031 }
27035 }
27037 /* Implement TARGET_SIMD_CLONE_ADJUST. */
27039 static void
27041 {
27042 /* Add aarch64_vector_pcs target attribute to SIMD clones so they
27043 use the correct ABI. */
27048 }
27050 /* Implement TARGET_SIMD_CLONE_USABLE. */
27052 static int
27054 {
27056 {
27063 }
27064 }
27066 /* Implement TARGET_COMP_TYPE_ATTRIBUTES */
27068 static int
27070 {
27078 };
27089 }
27091 /* Implement TARGET_GET_MULTILIB_ABI_NAME */
27095 {
27099 }
27101 /* Implement TARGET_STACK_PROTECT_GUARD. In case of a
27102 global variable based guard use the default else
27103 return a null tree. */
27104 static tree
27106 {
27111 }
27113 /* Return the diagnostic message string if the binary operation OP is
27114 not permitted on TYPE1 and TYPE2, NULL otherwise. */
27118 const_tree type2)
27119 {
27128 /* Operation allowed. */
27130 }
27132 /* Implement TARGET_MEMTAG_CAN_TAG_ADDRESSES. Here we tell the rest of the
27133 compiler that we automatically ignore the top byte of our pointers, which
27134 allows using -fsanitize=hwaddress. */
27135 bool
27137 {
27139 }
27141 /* Implement TARGET_ASM_FILE_END for AArch64. This adds the AArch64 GNU NOTE
27142 section at the end if needed. */
27143 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
27144 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
27145 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
27146 void
27148 {
27159 {
27160 /* Generate .note.gnu.property section. */
27164 /* PT_NOTE header: namesz, descsz, type.
27165 namesz = 4 ("GNU\0")
27166 descsz = 16 (Size of the program property array)
27167 [(12 + padding) * Number of array elements]
27168 type = 5 (NT_GNU_PROPERTY_TYPE_0). */
27174 /* PT_NOTE name. */
27177 /* PT_NOTE contents for NT_GNU_PROPERTY_TYPE_0:
27178 type = GNU_PROPERTY_AARCH64_FEATURE_1_AND
27179 datasz = 4
27180 data = feature_1_and. */
27185 /* Pad the size of the note to the required alignment. */
27187 }
27188 }
27189 #undef GNU_PROPERTY_AARCH64_FEATURE_1_PAC
27190 #undef GNU_PROPERTY_AARCH64_FEATURE_1_BTI
27191 #undef GNU_PROPERTY_AARCH64_FEATURE_1_AND
27193 /* Helper function for straight line speculation.
27194 Return what barrier should be emitted for straight line speculation
27195 mitigation.
27196 When not mitigating against straight line speculation this function returns
27197 an empty string.
27198 When mitigating against straight line speculation, use:
27199 * SB when the v8.5-A SB extension is enabled.
27200 * DSB+ISB otherwise. */
27203 {
27204 return mitigation_required
27207 }
27242 };
27244 /* Function to create a BLR thunk. This thunk is used to mitigate straight
27245 line speculation. Instead of a simple BLR that can be speculated past,
27246 we emit a BL to this thunk, and this thunk contains a BR to the relevant
27247 register. These thunks have the relevant speculation barries put after
27248 their indirect branch so that speculation is blocked.
27250 We use such a thunk so the speculation barriers are kept off the
27251 architecturally executed path in order to reduce the performance overhead.
27253 When optimizing for size we use stubs shared by the linked object.
27254 When optimizing for performance we emit stubs for each function in the hope
27255 that the branch predictor can better train on jumps specific for a given
27256 function. */
27257 rtx
27259 {
27262 {
27263 /* For the thunks shared between different functions in this compilation
27264 unit we use a named symbol -- this is just for users to more easily
27265 understand the generated assembly. */
27269 {
27270 /* Build a decl representing this function stub and record it for
27271 later. We build a decl here so we can use the GCC machinery for
27272 handling sections automatically (through `get_named_section` and
27273 `make_decl_one_only`). That saves us a lot of trouble handling
27274 the specifics of different output file formats. */
27278 NULL_TREE));
27288 }
27291 }
27297 }
27299 /* Helper function for aarch64_sls_emit_blr_function_thunks and
27300 aarch64_sls_emit_shared_blr_thunks below. */
27301 static void
27303 {
27304 /* Save in x16 and branch to that function so this transformation does
27305 not prevent jumping to `BTI c` instructions. */
27308 }
27310 /* Emit all BLR stubs for this particular function.
27311 Here we emit all the BLR stubs needed for the current function. Since we
27312 emit these stubs in a consecutive block we know there will be no speculation
27313 gadgets between each stub, and hence we only emit a speculation barrier at
27314 the end of the stub sequences.
27316 This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook. */
27317 void
27319 {
27324 /* We must save and restore the current function section since this assembly
27325 is emitted at the end of the function. This means it can be emitted *just
27326 after* the cold section of a function. That cold part would be emitted in
27327 a different section. That switch would trigger a `.cfi_endproc` directive
27328 to be emitted in the original section and a `.cfi_startproc` directive to
27329 be emitted in the new section. Switching to the original section without
27330 restoring would mean that the `.cfi_endproc` emitted as a function ends
27331 would happen in a different section -- leaving an unmatched
27332 `.cfi_startproc` in the cold text section and an unmatched `.cfi_endproc`
27333 in the standard text section. */
27337 {
27346 }
27348 /* Can use the SB if needs be here, since this stub will only be used
27349 by the current function, and hence for the current target. */
27352 }
27354 /* Emit shared BLR stubs for the current compilation unit.
27355 Over the course of compiling this unit we may have converted some BLR
27356 instructions to a BL to a shared stub function. This is where we emit those
27357 stub functions.
27358 This function is for the stubs shared between different functions in this
27359 compilation unit. We share when optimizing for size instead of speed.
27361 This function is called through the TARGET_ASM_FILE_END hook. */
27362 void
27364 {
27369 {
27378 /* Only emits if the compiler is configured for an assembler that can
27379 handle visibility directives. */
27384 /* Use the most conservative target to ensure it can always be used by any
27385 function in the translation unit. */
27388 }
27389 }
27391 /* Implement TARGET_ASM_FILE_END. */
27392 void
27394 {
27396 /* Since this function will be called for the ASM_FILE_END hook, we ensure
27397 that what would be called otherwise (e.g. `file_end_indicate_exec_stack`
27398 for FreeBSD) still gets called. */
27399 #ifdef TARGET_ASM_FILE_END
27401 #endif
27402 }
27406 {
27409 {
27412 }
27413 else
27416 }
27418 /* Target-specific selftests. */
27420 #if CHECKING_P
27424 /* Selftest for the RTL loader.
27425 Verify that the RTL loader copes with a dump from
27426 print_rtx_function. This is essentially just a test that class
27427 function_reader can handle a real dump, but it also verifies
27428 that lookup_reg_by_dump_name correctly handles hard regs.
27429 The presence of hard reg names in the dump means that the test is
27430 target-specific, hence it is in this file. */
27432 static void
27434 {
27446 /* Verify crtl->return_rtx. */
27450 }
27452 /* Test the fractional_cost class. */
27454 static void
27456 {
27543 }
27545 /* Run all target-specific selftests. */
27547 static void
27549 {
27552 }
27558 #undef TARGET_STACK_PROTECT_GUARD
27559 #define TARGET_STACK_PROTECT_GUARD aarch64_stack_protect_guard
27561 #undef TARGET_ADDRESS_COST
27562 #define TARGET_ADDRESS_COST aarch64_address_cost
27564 /* This hook will determines whether unnamed bitfields affect the alignment
27565 of the containing structure. The hook returns true if the structure
27566 should inherit the alignment requirements of an unnamed bitfield's
27567 type. */
27568 #undef TARGET_ALIGN_ANON_BITFIELD
27569 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
27571 #undef TARGET_ASM_ALIGNED_DI_OP
27574 #undef TARGET_ASM_ALIGNED_HI_OP
27577 #undef TARGET_ASM_ALIGNED_SI_OP
27580 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
27581 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
27582 hook_bool_const_tree_hwi_hwi_const_tree_true
27584 #undef TARGET_ASM_FILE_START
27585 #define TARGET_ASM_FILE_START aarch64_start_file
27587 #undef TARGET_ASM_OUTPUT_MI_THUNK
27588 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
27590 #undef TARGET_ASM_SELECT_RTX_SECTION
27591 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
27593 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
27594 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
27596 #undef TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY
27597 #define TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY aarch64_print_patchable_function_entry
27599 #undef TARGET_BUILD_BUILTIN_VA_LIST
27600 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
27602 #undef TARGET_CALLEE_COPIES
27603 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_arg_info_false
27605 #undef TARGET_CAN_ELIMINATE
27606 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
27608 #undef TARGET_CAN_INLINE_P
27609 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
27611 #undef TARGET_CANNOT_FORCE_CONST_MEM
27612 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
27614 #undef TARGET_CASE_VALUES_THRESHOLD
27615 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
27617 #undef TARGET_CONDITIONAL_REGISTER_USAGE
27618 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
27620 #undef TARGET_MEMBER_TYPE_FORCES_BLK
27621 #define TARGET_MEMBER_TYPE_FORCES_BLK aarch64_member_type_forces_blk
27623 /* Only the least significant bit is used for initialization guard
27624 variables. */
27625 #undef TARGET_CXX_GUARD_MASK_BIT
27626 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
27628 #undef TARGET_C_MODE_FOR_SUFFIX
27629 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
27631 #ifdef TARGET_BIG_ENDIAN_DEFAULT
27632 #undef TARGET_DEFAULT_TARGET_FLAGS
27633 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
27634 #endif
27636 #undef TARGET_CLASS_MAX_NREGS
27637 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
27639 #undef TARGET_BUILTIN_DECL
27640 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
27642 #undef TARGET_BUILTIN_RECIPROCAL
27643 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
27645 #undef TARGET_C_EXCESS_PRECISION
27646 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
27648 #undef TARGET_EXPAND_BUILTIN
27649 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
27651 #undef TARGET_EXPAND_BUILTIN_VA_START
27652 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
27654 #undef TARGET_FOLD_BUILTIN
27655 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
27657 #undef TARGET_FUNCTION_ARG
27658 #define TARGET_FUNCTION_ARG aarch64_function_arg
27660 #undef TARGET_FUNCTION_ARG_ADVANCE
27661 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
27663 #undef TARGET_FUNCTION_ARG_BOUNDARY
27664 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
27666 #undef TARGET_FUNCTION_ARG_PADDING
27667 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
27669 #undef TARGET_GET_RAW_RESULT_MODE
27670 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
27671 #undef TARGET_GET_RAW_ARG_MODE
27672 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
27674 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
27675 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
27677 #undef TARGET_FUNCTION_VALUE
27678 #define TARGET_FUNCTION_VALUE aarch64_function_value
27680 #undef TARGET_FUNCTION_VALUE_REGNO_P
27681 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
27683 #undef TARGET_GIMPLE_FOLD_BUILTIN
27684 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
27686 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
27687 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
27689 #undef TARGET_INIT_BUILTINS
27690 #define TARGET_INIT_BUILTINS aarch64_init_builtins
27692 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
27693 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
27694 aarch64_ira_change_pseudo_allocno_class
27696 #undef TARGET_LEGITIMATE_ADDRESS_P
27697 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
27699 #undef TARGET_LEGITIMATE_CONSTANT_P
27700 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
27702 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
27703 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
27704 aarch64_legitimize_address_displacement
27706 #undef TARGET_LIBGCC_CMP_RETURN_MODE
27707 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
27709 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
27710 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
27711 aarch64_libgcc_floating_mode_supported_p
27713 #undef TARGET_MANGLE_TYPE
27714 #define TARGET_MANGLE_TYPE aarch64_mangle_type
27716 #undef TARGET_INVALID_BINARY_OP
27717 #define TARGET_INVALID_BINARY_OP aarch64_invalid_binary_op
27719 #undef TARGET_VERIFY_TYPE_CONTEXT
27720 #define TARGET_VERIFY_TYPE_CONTEXT aarch64_verify_type_context
27722 #undef TARGET_MEMORY_MOVE_COST
27723 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
27725 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
27726 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
27728 #undef TARGET_MUST_PASS_IN_STACK
27729 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
27731 /* This target hook should return true if accesses to volatile bitfields
27732 should use the narrowest mode possible. It should return false if these
27733 accesses should use the bitfield container type. */
27734 #undef TARGET_NARROW_VOLATILE_BITFIELD
27735 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
27737 #undef TARGET_OPTION_OVERRIDE
27738 #define TARGET_OPTION_OVERRIDE aarch64_override_options
27740 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
27741 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
27742 aarch64_override_options_after_change
27744 #undef TARGET_OFFLOAD_OPTIONS
27745 #define TARGET_OFFLOAD_OPTIONS aarch64_offload_options
27747 #undef TARGET_OPTION_RESTORE
27748 #define TARGET_OPTION_RESTORE aarch64_option_restore
27750 #undef TARGET_OPTION_PRINT
27751 #define TARGET_OPTION_PRINT aarch64_option_print
27753 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
27754 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
27756 #undef TARGET_SET_CURRENT_FUNCTION
27757 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
27759 #undef TARGET_PASS_BY_REFERENCE
27760 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
27762 #undef TARGET_PREFERRED_RELOAD_CLASS
27763 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
27765 #undef TARGET_SCHED_REASSOCIATION_WIDTH
27766 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
27768 #undef TARGET_DWARF_FRAME_REG_MODE
27769 #define TARGET_DWARF_FRAME_REG_MODE aarch64_dwarf_frame_reg_mode
27771 #undef TARGET_PROMOTED_TYPE
27772 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
27774 #undef TARGET_SECONDARY_RELOAD
27775 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
27777 #undef TARGET_SECONDARY_MEMORY_NEEDED
27778 #define TARGET_SECONDARY_MEMORY_NEEDED aarch64_secondary_memory_needed
27780 #undef TARGET_SHIFT_TRUNCATION_MASK
27781 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
27783 #undef TARGET_SETUP_INCOMING_VARARGS
27784 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
27786 #undef TARGET_STRUCT_VALUE_RTX
27787 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
27789 #undef TARGET_REGISTER_MOVE_COST
27790 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
27792 #undef TARGET_RETURN_IN_MEMORY
27793 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
27795 #undef TARGET_RETURN_IN_MSB
27796 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
27798 #undef TARGET_RTX_COSTS
27799 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
27801 #undef TARGET_SCALAR_MODE_SUPPORTED_P
27802 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
27804 #undef TARGET_SCHED_ISSUE_RATE
27805 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
27807 #undef TARGET_SCHED_VARIABLE_ISSUE
27808 #define TARGET_SCHED_VARIABLE_ISSUE aarch64_sched_variable_issue
27810 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
27811 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
27812 aarch64_sched_first_cycle_multipass_dfa_lookahead
27814 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
27815 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
27816 aarch64_first_cycle_multipass_dfa_lookahead_guard
27818 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
27819 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
27820 aarch64_get_separate_components
27822 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
27823 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
27824 aarch64_components_for_bb
27826 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
27827 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
27828 aarch64_disqualify_components
27830 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
27831 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
27832 aarch64_emit_prologue_components
27834 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
27835 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
27836 aarch64_emit_epilogue_components
27838 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
27839 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
27840 aarch64_set_handled_components
27842 #undef TARGET_TRAMPOLINE_INIT
27843 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
27845 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
27846 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
27848 #undef TARGET_VECTOR_MODE_SUPPORTED_P
27849 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
27851 #undef TARGET_COMPATIBLE_VECTOR_TYPES_P
27852 #define TARGET_COMPATIBLE_VECTOR_TYPES_P aarch64_compatible_vector_types_p
27854 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
27855 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
27856 aarch64_builtin_support_vector_misalignment
27858 #undef TARGET_ARRAY_MODE
27859 #define TARGET_ARRAY_MODE aarch64_array_mode
27861 #undef TARGET_ARRAY_MODE_SUPPORTED_P
27862 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
27864 #undef TARGET_VECTORIZE_CREATE_COSTS
27865 #define TARGET_VECTORIZE_CREATE_COSTS aarch64_vectorize_create_costs
27867 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
27868 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
27869 aarch64_builtin_vectorization_cost
27871 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
27872 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
27874 #undef TARGET_VECTORIZE_BUILTINS
27875 #define TARGET_VECTORIZE_BUILTINS
27877 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
27878 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
27879 aarch64_autovectorize_vector_modes
27881 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
27882 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
27883 aarch64_atomic_assign_expand_fenv
27885 /* Section anchor support. */
27887 #undef TARGET_MIN_ANCHOR_OFFSET
27888 #define TARGET_MIN_ANCHOR_OFFSET -256
27890 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
27891 byte offset; we can do much more for larger data types, but have no way
27892 to determine the size of the access. We assume accesses are aligned. */
27893 #undef TARGET_MAX_ANCHOR_OFFSET
27894 #define TARGET_MAX_ANCHOR_OFFSET 4095
27896 #undef TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT
27897 #define TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT \
27898 aarch64_vectorize_preferred_div_as_shifts_over_mult
27900 #undef TARGET_VECTOR_ALIGNMENT
27901 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
27903 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
27904 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
27905 aarch64_vectorize_preferred_vector_alignment
27906 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
27907 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
27908 aarch64_simd_vector_alignment_reachable
27910 /* vec_perm support. */
27912 #undef TARGET_VECTORIZE_VEC_PERM_CONST
27913 #define TARGET_VECTORIZE_VEC_PERM_CONST \
27914 aarch64_vectorize_vec_perm_const
27916 #undef TARGET_VECTORIZE_RELATED_MODE
27917 #define TARGET_VECTORIZE_RELATED_MODE aarch64_vectorize_related_mode
27918 #undef TARGET_VECTORIZE_GET_MASK_MODE
27919 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
27920 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
27921 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
27922 aarch64_empty_mask_is_expensive
27923 #undef TARGET_PREFERRED_ELSE_VALUE
27924 #define TARGET_PREFERRED_ELSE_VALUE \
27925 aarch64_preferred_else_value
27927 #undef TARGET_INIT_LIBFUNCS
27928 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
27930 #undef TARGET_FIXED_CONDITION_CODE_REGS
27931 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
27933 #undef TARGET_FLAGS_REGNUM
27934 #define TARGET_FLAGS_REGNUM CC_REGNUM
27936 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
27937 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
27939 #undef TARGET_ASAN_SHADOW_OFFSET
27940 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
27942 #undef TARGET_LEGITIMIZE_ADDRESS
27943 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
27945 #undef TARGET_SCHED_CAN_SPECULATE_INSN
27946 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
27948 #undef TARGET_CAN_USE_DOLOOP_P
27949 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
27951 #undef TARGET_SCHED_ADJUST_PRIORITY
27952 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
27954 #undef TARGET_SCHED_MACRO_FUSION_P
27955 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
27957 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
27958 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
27960 #undef TARGET_SCHED_FUSION_PRIORITY
27961 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
27963 #undef TARGET_UNSPEC_MAY_TRAP_P
27964 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
27966 #undef TARGET_USE_PSEUDO_PIC_REG
27967 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
27969 #undef TARGET_PRINT_OPERAND
27970 #define TARGET_PRINT_OPERAND aarch64_print_operand
27972 #undef TARGET_PRINT_OPERAND_ADDRESS
27973 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
27975 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
27976 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA aarch64_output_addr_const_extra
27978 #undef TARGET_OPTAB_SUPPORTED_P
27979 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
27981 #undef TARGET_OMIT_STRUCT_RETURN_REG
27982 #define TARGET_OMIT_STRUCT_RETURN_REG true
27984 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
27985 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
27986 aarch64_dwarf_poly_indeterminate_value
27988 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
27989 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
27990 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
27992 #undef TARGET_HARD_REGNO_NREGS
27993 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
27994 #undef TARGET_HARD_REGNO_MODE_OK
27995 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
27997 #undef TARGET_MODES_TIEABLE_P
27998 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
28000 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
28001 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
28002 aarch64_hard_regno_call_part_clobbered
28004 #undef TARGET_INSN_CALLEE_ABI
28005 #define TARGET_INSN_CALLEE_ABI aarch64_insn_callee_abi
28007 #undef TARGET_CONSTANT_ALIGNMENT
28008 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
28010 #undef TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE
28011 #define TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE \
28012 aarch64_stack_clash_protection_alloca_probe_range
28014 #undef TARGET_COMPUTE_PRESSURE_CLASSES
28015 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
28017 #undef TARGET_CAN_CHANGE_MODE_CLASS
28018 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
28020 #undef TARGET_SELECT_EARLY_REMAT_MODES
28021 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
28023 #undef TARGET_SPECULATION_SAFE_VALUE
28024 #define TARGET_SPECULATION_SAFE_VALUE aarch64_speculation_safe_value
28026 #undef TARGET_ESTIMATED_POLY_VALUE
28027 #define TARGET_ESTIMATED_POLY_VALUE aarch64_estimated_poly_value
28029 #undef TARGET_ATTRIBUTE_TABLE
28030 #define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table
28032 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
28033 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
28034 aarch64_simd_clone_compute_vecsize_and_simdlen
28036 #undef TARGET_SIMD_CLONE_ADJUST
28037 #define TARGET_SIMD_CLONE_ADJUST aarch64_simd_clone_adjust
28039 #undef TARGET_SIMD_CLONE_USABLE
28040 #define TARGET_SIMD_CLONE_USABLE aarch64_simd_clone_usable
28042 #undef TARGET_COMP_TYPE_ATTRIBUTES
28043 #define TARGET_COMP_TYPE_ATTRIBUTES aarch64_comp_type_attributes
28045 #undef TARGET_GET_MULTILIB_ABI_NAME
28046 #define TARGET_GET_MULTILIB_ABI_NAME aarch64_get_multilib_abi_name
28048 #undef TARGET_FNTYPE_ABI
28049 #define TARGET_FNTYPE_ABI aarch64_fntype_abi
28051 #undef TARGET_MEMTAG_CAN_TAG_ADDRESSES
28052 #define TARGET_MEMTAG_CAN_TAG_ADDRESSES aarch64_can_tag_addresses
28054 #if CHECKING_P
28055 #undef TARGET_RUN_TARGET_SELFTESTS
28056 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests
28059 #undef TARGET_ASM_POST_CFI_STARTPROC
28060 #define TARGET_ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc
28062 #undef TARGET_STRICT_ARGUMENT_NAMING
28063 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
28065 #undef TARGET_MD_ASM_ADJUST
28066 #define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
28068 #undef TARGET_ASM_FILE_END
28069 #define TARGET_ASM_FILE_END aarch64_asm_file_end
28071 #undef TARGET_ASM_FUNCTION_EPILOGUE
28072 #define TARGET_ASM_FUNCTION_EPILOGUE aarch64_sls_emit_blr_function_thunks
28074 #undef TARGET_HAVE_SHADOW_CALL_STACK
28075 #define TARGET_HAVE_SHADOW_CALL_STACK true
28077 #undef TARGET_CONST_ANCHOR
28078 #define TARGET_CONST_ANCHOR 0x1000000