1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
31 #include "insn-config.h"
36 static void store_fixed_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
37 unsigned HOST_WIDE_INT
,
38 unsigned HOST_WIDE_INT
, rtx
,
40 static void store_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
41 unsigned HOST_WIDE_INT
, rtx
,
43 static rtx extract_fixed_bit_field
PARAMS ((enum machine_mode
, rtx
,
44 unsigned HOST_WIDE_INT
,
45 unsigned HOST_WIDE_INT
,
46 unsigned HOST_WIDE_INT
,
47 rtx
, int, unsigned int));
48 static rtx mask_rtx
PARAMS ((enum machine_mode
, int,
50 static rtx lshift_value
PARAMS ((enum machine_mode
, rtx
,
52 static rtx extract_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
53 unsigned HOST_WIDE_INT
, int,
55 static void do_cmp_and_jump
PARAMS ((rtx
, rtx
, enum rtx_code
,
56 enum machine_mode
, rtx
));
58 /* Non-zero means divides or modulus operations are relatively cheap for
59 powers of two, so don't use branches; emit the operation instead.
60 Usually, this will mean that the MD file will emit non-branch
63 static int sdiv_pow2_cheap
, smod_pow2_cheap
;
65 #ifndef SLOW_UNALIGNED_ACCESS
66 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
69 /* For compilers that support multiple targets with different word sizes,
70 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
71 is the H8/300(H) compiler. */
73 #ifndef MAX_BITS_PER_WORD
74 #define MAX_BITS_PER_WORD BITS_PER_WORD
77 /* Cost of various pieces of RTL. Note that some of these are indexed by
78 shift count and some by mode. */
79 static int add_cost
, negate_cost
, zero_cost
;
80 static int shift_cost
[MAX_BITS_PER_WORD
];
81 static int shiftadd_cost
[MAX_BITS_PER_WORD
];
82 static int shiftsub_cost
[MAX_BITS_PER_WORD
];
83 static int mul_cost
[NUM_MACHINE_MODES
];
84 static int div_cost
[NUM_MACHINE_MODES
];
85 static int mul_widen_cost
[NUM_MACHINE_MODES
];
86 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
91 /* This is "some random pseudo register" for purposes of calling recog
92 to see what insns exist. */
93 rtx reg
= gen_rtx_REG (word_mode
, 10000);
94 rtx shift_insn
, shiftadd_insn
, shiftsub_insn
;
97 enum machine_mode mode
, wider_mode
;
101 reg
= gen_rtx_REG (word_mode
, 10000);
103 zero_cost
= rtx_cost (const0_rtx
, 0);
104 add_cost
= rtx_cost (gen_rtx_PLUS (word_mode
, reg
, reg
), SET
);
106 shift_insn
= emit_insn (gen_rtx_SET (VOIDmode
, reg
,
107 gen_rtx_ASHIFT (word_mode
, reg
,
111 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
112 gen_rtx_PLUS (word_mode
,
113 gen_rtx_MULT (word_mode
,
118 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
119 gen_rtx_MINUS (word_mode
,
120 gen_rtx_MULT (word_mode
,
127 shiftadd_cost
[0] = shiftsub_cost
[0] = add_cost
;
129 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
131 shift_cost
[m
] = shiftadd_cost
[m
] = shiftsub_cost
[m
] = 32000;
133 XEXP (SET_SRC (PATTERN (shift_insn
)), 1) = GEN_INT (m
);
134 if (recog (PATTERN (shift_insn
), shift_insn
, &dummy
) >= 0)
135 shift_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shift_insn
)), SET
);
137 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn
)), 0), 1)
138 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
139 if (recog (PATTERN (shiftadd_insn
), shiftadd_insn
, &dummy
) >= 0)
140 shiftadd_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn
)), SET
);
142 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn
)), 0), 1)
143 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
144 if (recog (PATTERN (shiftsub_insn
), shiftsub_insn
, &dummy
) >= 0)
145 shiftsub_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn
)), SET
);
148 negate_cost
= rtx_cost (gen_rtx_NEG (word_mode
, reg
), SET
);
151 = (rtx_cost (gen_rtx_DIV (word_mode
, reg
, GEN_INT (32)), SET
)
154 = (rtx_cost (gen_rtx_MOD (word_mode
, reg
, GEN_INT (32)), SET
)
157 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
159 mode
= GET_MODE_WIDER_MODE (mode
))
161 reg
= gen_rtx_REG (mode
, 10000);
162 div_cost
[(int) mode
] = rtx_cost (gen_rtx_UDIV (mode
, reg
, reg
), SET
);
163 mul_cost
[(int) mode
] = rtx_cost (gen_rtx_MULT (mode
, reg
, reg
), SET
);
164 wider_mode
= GET_MODE_WIDER_MODE (mode
);
165 if (wider_mode
!= VOIDmode
)
167 mul_widen_cost
[(int) wider_mode
]
168 = rtx_cost (gen_rtx_MULT (wider_mode
,
169 gen_rtx_ZERO_EXTEND (wider_mode
, reg
),
170 gen_rtx_ZERO_EXTEND (wider_mode
, reg
)),
172 mul_highpart_cost
[(int) mode
]
173 = rtx_cost (gen_rtx_TRUNCATE
175 gen_rtx_LSHIFTRT (wider_mode
,
176 gen_rtx_MULT (wider_mode
,
181 GEN_INT (GET_MODE_BITSIZE (mode
)))),
189 /* Return an rtx representing minus the value of X.
190 MODE is the intended mode of the result,
191 useful if X is a CONST_INT. */
195 enum machine_mode mode
;
198 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
201 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
206 /* Generate code to store value from rtx VALUE
207 into a bit-field within structure STR_RTX
208 containing BITSIZE bits starting at bit BITNUM.
209 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
210 ALIGN is the alignment that STR_RTX is known to have.
211 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
213 /* ??? Note that there are two different ideas here for how
214 to determine the size to count bits within, for a register.
215 One is BITS_PER_WORD, and the other is the size of operand 3
218 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
219 else, we use the mode of operand 3. */
222 store_bit_field (str_rtx
, bitsize
, bitnum
, fieldmode
, value
, align
, total_size
)
224 unsigned HOST_WIDE_INT bitsize
;
225 unsigned HOST_WIDE_INT bitnum
;
226 enum machine_mode fieldmode
;
229 HOST_WIDE_INT total_size
;
232 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
233 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
234 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
235 register rtx op0
= str_rtx
;
237 unsigned HOST_WIDE_INT insv_bitsize
;
238 enum machine_mode op_mode
;
240 op_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
241 if (op_mode
== VOIDmode
)
243 insv_bitsize
= GET_MODE_BITSIZE (op_mode
);
246 /* It is wrong to have align==0, since every object is aligned at
247 least at a bit boundary. This usually means a bug elsewhere. */
251 /* Discount the part of the structure before the desired byte.
252 We need to know how many bytes are safe to reference after it. */
254 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
255 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
257 while (GET_CODE (op0
) == SUBREG
)
259 /* The following line once was done only if WORDS_BIG_ENDIAN,
260 but I think that is a mistake. WORDS_BIG_ENDIAN is
261 meaningful at a much higher level; when structures are copied
262 between memory and regs, the higher-numbered regs
263 always get higher addresses. */
264 offset
+= SUBREG_WORD (op0
);
265 /* We used to adjust BITPOS here, but now we do the whole adjustment
266 right after the loop. */
267 op0
= SUBREG_REG (op0
);
270 /* If OP0 is a register, BITPOS must count within a word.
271 But as we have it, it counts within whatever size OP0 now has.
272 On a bigendian machine, these are not the same, so convert. */
274 && GET_CODE (op0
) != MEM
275 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
276 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
278 value
= protect_from_queue (value
, 0);
281 value
= force_not_mem (value
);
283 /* If the target is a register, overwriting the entire object, or storing
284 a full-word or multi-word field can be done with just a SUBREG.
286 If the target is memory, storing any naturally aligned field can be
287 done with a simple store. For targets that support fast unaligned
288 memory, any naturally sized, unit aligned field can be done directly. */
290 if (bitsize
== GET_MODE_BITSIZE (fieldmode
)
291 && (GET_CODE (op0
) != MEM
292 ? (GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
293 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
294 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, align
)
295 || (offset
* BITS_PER_UNIT
% bitsize
== 0
296 && align
% GET_MODE_BITSIZE (fieldmode
) == 0)))
297 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0))
299 if (GET_MODE (op0
) != fieldmode
)
301 if (GET_CODE (op0
) == SUBREG
)
303 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
304 || GET_MODE_CLASS (fieldmode
) == MODE_INT
305 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
306 op0
= SUBREG_REG (op0
);
308 /* Else we've got some float mode source being extracted into
309 a different float mode destination -- this combination of
310 subregs results in Severe Tire Damage. */
313 if (GET_CODE (op0
) == REG
)
314 op0
= gen_rtx_SUBREG (fieldmode
, op0
, offset
);
316 op0
= change_address (op0
, fieldmode
,
317 plus_constant (XEXP (op0
, 0), offset
));
319 emit_move_insn (op0
, value
);
323 /* Make sure we are playing with integral modes. Pun with subregs
324 if we aren't. This must come after the entire register case above,
325 since that case is valid for any mode. The following cases are only
326 valid for integral modes. */
328 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
329 if (imode
!= GET_MODE (op0
))
331 if (GET_CODE (op0
) == MEM
)
332 op0
= change_address (op0
, imode
, NULL_RTX
);
333 else if (imode
!= BLKmode
)
334 op0
= gen_lowpart (imode
, op0
);
340 /* Storing an lsb-aligned field in a register
341 can be done with a movestrict instruction. */
343 if (GET_CODE (op0
) != MEM
344 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
345 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
346 && (movstrict_optab
->handlers
[(int) fieldmode
].insn_code
347 != CODE_FOR_nothing
))
349 int icode
= movstrict_optab
->handlers
[(int) fieldmode
].insn_code
;
351 /* Get appropriate low part of the value being stored. */
352 if (GET_CODE (value
) == CONST_INT
|| GET_CODE (value
) == REG
)
353 value
= gen_lowpart (fieldmode
, value
);
354 else if (!(GET_CODE (value
) == SYMBOL_REF
355 || GET_CODE (value
) == LABEL_REF
356 || GET_CODE (value
) == CONST
))
357 value
= convert_to_mode (fieldmode
, value
, 0);
359 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
360 value
= copy_to_mode_reg (fieldmode
, value
);
362 if (GET_CODE (op0
) == SUBREG
)
364 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
365 || GET_MODE_CLASS (fieldmode
) == MODE_INT
366 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
367 op0
= SUBREG_REG (op0
);
369 /* Else we've got some float mode source being extracted into
370 a different float mode destination -- this combination of
371 subregs results in Severe Tire Damage. */
375 emit_insn (GEN_FCN (icode
)
376 (gen_rtx_SUBREG (fieldmode
, op0
, offset
), value
));
381 /* Handle fields bigger than a word. */
383 if (bitsize
> BITS_PER_WORD
)
385 /* Here we transfer the words of the field
386 in the order least significant first.
387 This is because the most significant word is the one which may
389 However, only do that if the value is not BLKmode. */
391 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
392 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
395 /* This is the mode we must force value to, so that there will be enough
396 subwords to extract. Note that fieldmode will often (always?) be
397 VOIDmode, because that is what store_field uses to indicate that this
398 is a bit field, but passing VOIDmode to operand_subword_force will
399 result in an abort. */
400 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
402 for (i
= 0; i
< nwords
; i
++)
404 /* If I is 0, use the low-order word in both field and target;
405 if I is 1, use the next to lowest word; and so on. */
406 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
407 unsigned int bit_offset
= (backwards
408 ? MAX ((int) bitsize
- ((int) i
+ 1)
411 : (int) i
* BITS_PER_WORD
);
413 store_bit_field (op0
, MIN (BITS_PER_WORD
,
414 bitsize
- i
* BITS_PER_WORD
),
415 bitnum
+ bit_offset
, word_mode
,
416 operand_subword_force (value
, wordnum
,
417 (GET_MODE (value
) == VOIDmode
419 : GET_MODE (value
))),
425 /* From here on we can assume that the field to be stored in is
426 a full-word (whatever type that is), since it is shorter than a word. */
428 /* OFFSET is the number of words or bytes (UNIT says which)
429 from STR_RTX to the first word or byte containing part of the field. */
431 if (GET_CODE (op0
) != MEM
)
434 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
436 if (GET_CODE (op0
) != REG
)
438 /* Since this is a destination (lvalue), we can't copy it to a
439 pseudo. We can trivially remove a SUBREG that does not
440 change the size of the operand. Such a SUBREG may have been
441 added above. Otherwise, abort. */
442 if (GET_CODE (op0
) == SUBREG
443 && (GET_MODE_SIZE (GET_MODE (op0
))
444 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))))
445 op0
= SUBREG_REG (op0
);
449 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
456 op0
= protect_from_queue (op0
, 1);
459 /* If VALUE is a floating-point mode, access it as an integer of the
460 corresponding size. This can occur on a machine with 64 bit registers
461 that uses SFmode for float. This can also occur for unaligned float
463 if (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
)
465 if (GET_CODE (value
) != REG
)
466 value
= copy_to_reg (value
);
467 value
= gen_rtx_SUBREG (word_mode
, value
, 0);
470 /* Now OFFSET is nonzero only if OP0 is memory
471 and is therefore always measured in bytes. */
475 && GET_MODE (value
) != BLKmode
476 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
477 /* Ensure insv's size is wide enough for this field. */
478 && (insv_bitsize
>= bitsize
)
479 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
480 && (bitsize
+ bitpos
> insv_bitsize
)))
482 int xbitpos
= bitpos
;
485 rtx last
= get_last_insn ();
487 enum machine_mode maxmode
;
488 int save_volatile_ok
= volatile_ok
;
490 maxmode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
491 if (maxmode
== VOIDmode
)
496 /* If this machine's insv can only insert into a register, copy OP0
497 into a register and save it back later. */
498 /* This used to check flag_force_mem, but that was a serious
499 de-optimization now that flag_force_mem is enabled by -O2. */
500 if (GET_CODE (op0
) == MEM
501 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
505 enum machine_mode bestmode
;
507 /* Get the mode to use for inserting into this field. If OP0 is
508 BLKmode, get the smallest mode consistent with the alignment. If
509 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
510 mode. Otherwise, use the smallest mode containing the field. */
512 if (GET_MODE (op0
) == BLKmode
513 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
515 = get_best_mode (bitsize
, bitnum
, align
, maxmode
,
516 MEM_VOLATILE_P (op0
));
518 bestmode
= GET_MODE (op0
);
520 if (bestmode
== VOIDmode
521 || (SLOW_UNALIGNED_ACCESS (bestmode
, align
)
522 && GET_MODE_BITSIZE (bestmode
) > align
))
525 /* Adjust address to point to the containing unit of that mode. */
526 unit
= GET_MODE_BITSIZE (bestmode
);
527 /* Compute offset as multiple of this unit, counting in bytes. */
528 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
529 bitpos
= bitnum
% unit
;
530 op0
= change_address (op0
, bestmode
,
531 plus_constant (XEXP (op0
, 0), offset
));
533 /* Fetch that unit, store the bitfield in it, then store
535 tempreg
= copy_to_reg (op0
);
536 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, value
,
538 emit_move_insn (op0
, tempreg
);
541 volatile_ok
= save_volatile_ok
;
543 /* Add OFFSET into OP0's address. */
544 if (GET_CODE (xop0
) == MEM
)
545 xop0
= change_address (xop0
, byte_mode
,
546 plus_constant (XEXP (xop0
, 0), offset
));
548 /* If xop0 is a register, we need it in MAXMODE
549 to make it acceptable to the format of insv. */
550 if (GET_CODE (xop0
) == SUBREG
)
551 /* We can't just change the mode, because this might clobber op0,
552 and we will need the original value of op0 if insv fails. */
553 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_WORD (xop0
));
554 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
555 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
557 /* On big-endian machines, we count bits from the most significant.
558 If the bit field insn does not, we must invert. */
560 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
561 xbitpos
= unit
- bitsize
- xbitpos
;
563 /* We have been counting XBITPOS within UNIT.
564 Count instead within the size of the register. */
565 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
566 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
568 unit
= GET_MODE_BITSIZE (maxmode
);
570 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
572 if (GET_MODE (value
) != maxmode
)
574 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
576 /* Optimization: Don't bother really extending VALUE
577 if it has all the bits we will actually use. However,
578 if we must narrow it, be sure we do it correctly. */
580 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
582 /* Avoid making subreg of a subreg, or of a mem. */
583 if (GET_CODE (value1
) != REG
)
584 value1
= copy_to_reg (value1
);
585 value1
= gen_rtx_SUBREG (maxmode
, value1
, 0);
588 value1
= gen_lowpart (maxmode
, value1
);
590 else if (!CONSTANT_P (value
))
591 /* Parse phase is supposed to make VALUE's data type
592 match that of the component reference, which is a type
593 at least as wide as the field; so VALUE should have
594 a mode that corresponds to that type. */
598 /* If this machine's insv insists on a register,
599 get VALUE1 into a register. */
600 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
602 value1
= force_reg (maxmode
, value1
);
604 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
609 delete_insns_since (last
);
610 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, align
);
616 /* Insv is not available; store using shifts and boolean ops. */
617 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, align
);
621 /* Use shifts and boolean operations to store VALUE
622 into a bit field of width BITSIZE
623 in a memory location specified by OP0 except offset by OFFSET bytes.
624 (OFFSET must be 0 if OP0 is a register.)
625 The field starts at position BITPOS within the byte.
626 (If OP0 is a register, it may be a full word or a narrower mode,
627 but BITPOS still counts within a full word,
628 which is significant on bigendian machines.)
629 STRUCT_ALIGN is the alignment the structure is known to have.
631 Note that protect_from_queue has already been done on OP0 and VALUE. */
634 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, struct_align
)
636 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
638 unsigned int struct_align
;
640 register enum machine_mode mode
;
641 unsigned int total_bits
= BITS_PER_WORD
;
646 if (! SLOW_UNALIGNED_ACCESS (word_mode
, struct_align
))
647 struct_align
= BIGGEST_ALIGNMENT
;
649 /* There is a case not handled here:
650 a structure with a known alignment of just a halfword
651 and a field split across two aligned halfwords within the structure.
652 Or likewise a structure with a known alignment of just a byte
653 and a field split across two bytes.
654 Such cases are not supposed to be able to occur. */
656 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
660 /* Special treatment for a bit field split across two registers. */
661 if (bitsize
+ bitpos
> BITS_PER_WORD
)
663 store_split_bit_field (op0
, bitsize
, bitpos
,
664 value
, BITS_PER_WORD
);
670 /* Get the proper mode to use for this field. We want a mode that
671 includes the entire field. If such a mode would be larger than
672 a word, we won't be doing the extraction the normal way. */
674 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
675 struct_align
, word_mode
,
676 GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
));
678 if (mode
== VOIDmode
)
680 /* The only way this should occur is if the field spans word
682 store_split_bit_field (op0
,
683 bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
684 value
, struct_align
);
688 total_bits
= GET_MODE_BITSIZE (mode
);
690 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
691 be in the range 0 to total_bits-1, and put any excess bytes in
693 if (bitpos
>= total_bits
)
695 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
696 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
700 /* Get ref to an aligned byte, halfword, or word containing the field.
701 Adjust BITPOS to be position within a word,
702 and OFFSET to be the offset of that word.
703 Then alter OP0 to refer to that word. */
704 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
705 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
706 op0
= change_address (op0
, mode
,
707 plus_constant (XEXP (op0
, 0), offset
));
710 mode
= GET_MODE (op0
);
712 /* Now MODE is either some integral mode for a MEM as OP0,
713 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
714 The bit field is contained entirely within OP0.
715 BITPOS is the starting bit number within OP0.
716 (OP0's mode may actually be narrower than MODE.) */
718 if (BYTES_BIG_ENDIAN
)
719 /* BITPOS is the distance between our msb
720 and that of the containing datum.
721 Convert it to the distance from the lsb. */
722 bitpos
= total_bits
- bitsize
- bitpos
;
724 /* Now BITPOS is always the distance between our lsb
727 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
728 we must first convert its mode to MODE. */
730 if (GET_CODE (value
) == CONST_INT
)
732 register HOST_WIDE_INT v
= INTVAL (value
);
734 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
735 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
739 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
740 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
741 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
744 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
748 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
749 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
751 if (GET_MODE (value
) != mode
)
753 if ((GET_CODE (value
) == REG
|| GET_CODE (value
) == SUBREG
)
754 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
755 value
= gen_lowpart (mode
, value
);
757 value
= convert_to_mode (mode
, value
, 1);
761 value
= expand_binop (mode
, and_optab
, value
,
762 mask_rtx (mode
, 0, bitsize
, 0),
763 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
765 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
766 build_int_2 (bitpos
, 0), NULL_RTX
, 1);
769 /* Now clear the chosen bits in OP0,
770 except that if VALUE is -1 we need not bother. */
772 subtarget
= (GET_CODE (op0
) == REG
|| ! flag_force_mem
) ? op0
: 0;
776 temp
= expand_binop (mode
, and_optab
, op0
,
777 mask_rtx (mode
, bitpos
, bitsize
, 1),
778 subtarget
, 1, OPTAB_LIB_WIDEN
);
784 /* Now logical-or VALUE into OP0, unless it is zero. */
787 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
788 subtarget
, 1, OPTAB_LIB_WIDEN
);
790 emit_move_insn (op0
, temp
);
793 /* Store a bit field that is split across multiple accessible memory objects.
795 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
796 BITSIZE is the field width; BITPOS the position of its first bit
798 VALUE is the value to store.
799 ALIGN is the known alignment of OP0.
800 This is also the size of the memory objects to be used.
802 This does not yet handle fields wider than BITS_PER_WORD. */
805 store_split_bit_field (op0
, bitsize
, bitpos
, value
, align
)
807 unsigned HOST_WIDE_INT bitsize
, bitpos
;
812 unsigned int bitsdone
= 0;
814 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
816 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
817 unit
= BITS_PER_WORD
;
819 unit
= MIN (align
, BITS_PER_WORD
);
821 /* If VALUE is a constant other than a CONST_INT, get it into a register in
822 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
823 that VALUE might be a floating-point constant. */
824 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
826 rtx word
= gen_lowpart_common (word_mode
, value
);
828 if (word
&& (value
!= word
))
831 value
= gen_lowpart_common (word_mode
,
832 force_reg (GET_MODE (value
) != VOIDmode
834 : word_mode
, value
));
836 else if (GET_CODE (value
) == ADDRESSOF
)
837 value
= copy_to_reg (value
);
839 while (bitsdone
< bitsize
)
841 unsigned HOST_WIDE_INT thissize
;
843 unsigned HOST_WIDE_INT thispos
;
844 unsigned HOST_WIDE_INT offset
;
846 offset
= (bitpos
+ bitsdone
) / unit
;
847 thispos
= (bitpos
+ bitsdone
) % unit
;
849 /* THISSIZE must not overrun a word boundary. Otherwise,
850 store_fixed_bit_field will call us again, and we will mutually
852 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
853 thissize
= MIN (thissize
, unit
- thispos
);
855 if (BYTES_BIG_ENDIAN
)
859 /* We must do an endian conversion exactly the same way as it is
860 done in extract_bit_field, so that the two calls to
861 extract_fixed_bit_field will have comparable arguments. */
862 if (GET_CODE (value
) != MEM
|| GET_MODE (value
) == BLKmode
)
863 total_bits
= BITS_PER_WORD
;
865 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
867 /* Fetch successively less significant portions. */
868 if (GET_CODE (value
) == CONST_INT
)
869 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
870 >> (bitsize
- bitsdone
- thissize
))
871 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
873 /* The args are chosen so that the last part includes the
874 lsb. Give extract_bit_field the value it needs (with
875 endianness compensation) to fetch the piece we want.
877 ??? We have no idea what the alignment of VALUE is, so
878 we have to use a guess. */
880 = extract_fixed_bit_field
881 (word_mode
, value
, 0, thissize
,
882 total_bits
- bitsize
+ bitsdone
, NULL_RTX
, 1,
883 GET_MODE (value
) == VOIDmode
885 : (GET_MODE (value
) == BLKmode
886 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value
))));
890 /* Fetch successively more significant portions. */
891 if (GET_CODE (value
) == CONST_INT
)
892 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
894 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
897 = extract_fixed_bit_field
898 (word_mode
, value
, 0, thissize
, bitsdone
, NULL_RTX
, 1,
899 GET_MODE (value
) == VOIDmode
901 : (GET_MODE (value
) == BLKmode
902 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value
))));
905 /* If OP0 is a register, then handle OFFSET here.
907 When handling multiword bitfields, extract_bit_field may pass
908 down a word_mode SUBREG of a larger REG for a bitfield that actually
909 crosses a word boundary. Thus, for a SUBREG, we must find
910 the current word starting from the base register. */
911 if (GET_CODE (op0
) == SUBREG
)
913 word
= operand_subword_force (SUBREG_REG (op0
),
914 SUBREG_WORD (op0
) + offset
,
915 GET_MODE (SUBREG_REG (op0
)));
918 else if (GET_CODE (op0
) == REG
)
920 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
926 /* OFFSET is in UNITs, and UNIT is in bits.
927 store_fixed_bit_field wants offset in bytes. */
928 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
,
929 thissize
, thispos
, part
, align
);
930 bitsdone
+= thissize
;
934 /* Generate code to extract a byte-field from STR_RTX
935 containing BITSIZE bits, starting at BITNUM,
936 and put it in TARGET if possible (if TARGET is nonzero).
937 Regardless of TARGET, we return the rtx for where the value is placed.
940 STR_RTX is the structure containing the byte (a REG or MEM).
941 UNSIGNEDP is nonzero if this is an unsigned bit field.
942 MODE is the natural mode of the field value once extracted.
943 TMODE is the mode the caller would like the value to have;
944 but the value may be returned with type MODE instead.
946 ALIGN is the alignment that STR_RTX is known to have.
947 TOTAL_SIZE is the size in bytes of the containing structure,
950 If a TARGET is specified and we can store in it at no extra cost,
951 we do so, and return TARGET.
952 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
953 if they are equally easy. */
956 extract_bit_field (str_rtx
, bitsize
, bitnum
, unsignedp
,
957 target
, mode
, tmode
, align
, total_size
)
959 unsigned HOST_WIDE_INT bitsize
;
960 unsigned HOST_WIDE_INT bitnum
;
963 enum machine_mode mode
, tmode
;
965 HOST_WIDE_INT total_size
;
968 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
969 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
970 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
971 register rtx op0
= str_rtx
;
972 rtx spec_target
= target
;
973 rtx spec_target_subreg
= 0;
974 enum machine_mode int_mode
;
976 unsigned HOST_WIDE_INT extv_bitsize
;
977 enum machine_mode extv_mode
;
980 unsigned HOST_WIDE_INT extzv_bitsize
;
981 enum machine_mode extzv_mode
;
985 extv_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
986 if (extv_mode
== VOIDmode
)
987 extv_mode
= word_mode
;
988 extv_bitsize
= GET_MODE_BITSIZE (extv_mode
);
992 extzv_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
993 if (extzv_mode
== VOIDmode
)
994 extzv_mode
= word_mode
;
995 extzv_bitsize
= GET_MODE_BITSIZE (extzv_mode
);
998 /* Discount the part of the structure before the desired byte.
999 We need to know how many bytes are safe to reference after it. */
1000 if (total_size
>= 0)
1001 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
1002 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
1004 if (tmode
== VOIDmode
)
1006 while (GET_CODE (op0
) == SUBREG
)
1008 int outer_size
= GET_MODE_BITSIZE (GET_MODE (op0
));
1009 int inner_size
= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)));
1011 offset
+= SUBREG_WORD (op0
);
1013 inner_size
= MIN (inner_size
, BITS_PER_WORD
);
1015 if (BYTES_BIG_ENDIAN
&& (outer_size
< inner_size
))
1017 bitpos
+= inner_size
- outer_size
;
1020 offset
+= (bitpos
/ unit
);
1025 op0
= SUBREG_REG (op0
);
1028 if (GET_CODE (op0
) == REG
1029 && mode
== GET_MODE (op0
)
1031 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1033 /* We're trying to extract a full register from itself. */
1037 /* Make sure we are playing with integral modes. Pun with subregs
1040 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1041 if (imode
!= GET_MODE (op0
))
1043 if (GET_CODE (op0
) == MEM
)
1044 op0
= change_address (op0
, imode
, NULL_RTX
);
1045 else if (imode
!= BLKmode
)
1046 op0
= gen_lowpart (imode
, op0
);
1052 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1053 If that's wrong, the solution is to test for it and set TARGET to 0
1056 /* If OP0 is a register, BITPOS must count within a word.
1057 But as we have it, it counts within whatever size OP0 now has.
1058 On a bigendian machine, these are not the same, so convert. */
1059 if (BYTES_BIG_ENDIAN
1060 && GET_CODE (op0
) != MEM
1061 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1062 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1064 /* Extracting a full-word or multi-word value
1065 from a structure in a register or aligned memory.
1066 This can be done with just SUBREG.
1067 So too extracting a subword value in
1068 the least significant part of the register. */
1070 if (((GET_CODE (op0
) != MEM
1071 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1072 GET_MODE_BITSIZE (GET_MODE (op0
))))
1073 || (GET_CODE (op0
) == MEM
1074 && (! SLOW_UNALIGNED_ACCESS (mode
, align
)
1075 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1076 && align
% bitsize
== 0))))
1077 && ((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1078 && bitpos
% BITS_PER_WORD
== 0)
1079 || (mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0) != BLKmode
1080 /* ??? The big endian test here is wrong. This is correct
1081 if the value is in a register, and if mode_for_size is not
1082 the same mode as op0. This causes us to get unnecessarily
1083 inefficient code from the Thumb port when -mbig-endian. */
1084 && (BYTES_BIG_ENDIAN
1085 ? bitpos
+ bitsize
== BITS_PER_WORD
1088 enum machine_mode mode1
1089 = (VECTOR_MODE_P (tmode
) ? mode
1090 : mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0));
1092 if (mode1
!= GET_MODE (op0
))
1094 if (GET_CODE (op0
) == SUBREG
)
1096 if (GET_MODE (SUBREG_REG (op0
)) == mode1
1097 || GET_MODE_CLASS (mode1
) == MODE_INT
1098 || GET_MODE_CLASS (mode1
) == MODE_PARTIAL_INT
)
1099 op0
= SUBREG_REG (op0
);
1101 /* Else we've got some float mode source being extracted into
1102 a different float mode destination -- this combination of
1103 subregs results in Severe Tire Damage. */
1106 if (GET_CODE (op0
) == REG
)
1107 op0
= gen_rtx_SUBREG (mode1
, op0
, offset
);
1109 op0
= change_address (op0
, mode1
,
1110 plus_constant (XEXP (op0
, 0), offset
));
1113 return convert_to_mode (tmode
, op0
, unsignedp
);
1117 /* Handle fields bigger than a word. */
1119 if (bitsize
> BITS_PER_WORD
)
1121 /* Here we transfer the words of the field
1122 in the order least significant first.
1123 This is because the most significant word is the one which may
1124 be less than full. */
1126 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1129 if (target
== 0 || GET_CODE (target
) != REG
)
1130 target
= gen_reg_rtx (mode
);
1132 /* Indicate for flow that the entire target reg is being set. */
1133 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1135 for (i
= 0; i
< nwords
; i
++)
1137 /* If I is 0, use the low-order word in both field and target;
1138 if I is 1, use the next to lowest word; and so on. */
1139 /* Word number in TARGET to use. */
1140 unsigned int wordnum
1142 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1144 /* Offset from start of field in OP0. */
1145 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1146 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1147 * (int) BITS_PER_WORD
))
1148 : (int) i
* BITS_PER_WORD
);
1149 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1151 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1152 bitsize
- i
* BITS_PER_WORD
),
1153 bitnum
+ bit_offset
, 1, target_part
, mode
,
1154 word_mode
, align
, total_size
);
1156 if (target_part
== 0)
1159 if (result_part
!= target_part
)
1160 emit_move_insn (target_part
, result_part
);
1165 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1166 need to be zero'd out. */
1167 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1169 unsigned int i
, total_words
;
1171 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1172 for (i
= nwords
; i
< total_words
; i
++)
1174 int wordnum
= WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
;
1175 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1176 emit_move_insn (target_part
, const0_rtx
);
1182 /* Signed bit field: sign-extend with two arithmetic shifts. */
1183 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1184 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1186 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1187 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1191 /* From here on we know the desired field is smaller than a word. */
1193 /* Check if there is a correspondingly-sized integer field, so we can
1194 safely extract it as one size of integer, if necessary; then
1195 truncate or extend to the size that is wanted; then use SUBREGs or
1196 convert_to_mode to get one of the modes we really wanted. */
1198 int_mode
= int_mode_for_mode (tmode
);
1199 if (int_mode
== BLKmode
)
1200 int_mode
= int_mode_for_mode (mode
);
1201 if (int_mode
== BLKmode
)
1202 abort(); /* Should probably push op0 out to memory and then
1205 /* OFFSET is the number of words or bytes (UNIT says which)
1206 from STR_RTX to the first word or byte containing part of the field. */
1208 if (GET_CODE (op0
) != MEM
)
1211 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1213 if (GET_CODE (op0
) != REG
)
1214 op0
= copy_to_reg (op0
);
1215 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1222 op0
= protect_from_queue (str_rtx
, 1);
1225 /* Now OFFSET is nonzero only for memory operands. */
1231 && (extzv_bitsize
>= bitsize
)
1232 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1233 && (bitsize
+ bitpos
> extzv_bitsize
)))
1235 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1236 rtx bitsize_rtx
, bitpos_rtx
;
1237 rtx last
= get_last_insn ();
1239 rtx xtarget
= target
;
1240 rtx xspec_target
= spec_target
;
1241 rtx xspec_target_subreg
= spec_target_subreg
;
1243 enum machine_mode maxmode
;
1245 maxmode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
1246 if (maxmode
== VOIDmode
)
1247 maxmode
= word_mode
;
1249 if (GET_CODE (xop0
) == MEM
)
1251 int save_volatile_ok
= volatile_ok
;
1254 /* Is the memory operand acceptable? */
1255 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1256 (xop0
, GET_MODE (xop0
))))
1258 /* No, load into a reg and extract from there. */
1259 enum machine_mode bestmode
;
1261 /* Get the mode to use for inserting into this field. If
1262 OP0 is BLKmode, get the smallest mode consistent with the
1263 alignment. If OP0 is a non-BLKmode object that is no
1264 wider than MAXMODE, use its mode. Otherwise, use the
1265 smallest mode containing the field. */
1267 if (GET_MODE (xop0
) == BLKmode
1268 || (GET_MODE_SIZE (GET_MODE (op0
))
1269 > GET_MODE_SIZE (maxmode
)))
1270 bestmode
= get_best_mode (bitsize
, bitnum
, align
, maxmode
,
1271 MEM_VOLATILE_P (xop0
));
1273 bestmode
= GET_MODE (xop0
);
1275 if (bestmode
== VOIDmode
1276 || (SLOW_UNALIGNED_ACCESS (bestmode
, align
)
1277 && GET_MODE_BITSIZE (bestmode
) > align
))
1280 /* Compute offset as multiple of this unit,
1281 counting in bytes. */
1282 unit
= GET_MODE_BITSIZE (bestmode
);
1283 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1284 xbitpos
= bitnum
% unit
;
1285 xop0
= change_address (xop0
, bestmode
,
1286 plus_constant (XEXP (xop0
, 0),
1288 /* Fetch it to a register in that size. */
1289 xop0
= force_reg (bestmode
, xop0
);
1291 /* XBITPOS counts within UNIT, which is what is expected. */
1294 /* Get ref to first byte containing part of the field. */
1295 xop0
= change_address (xop0
, byte_mode
,
1296 plus_constant (XEXP (xop0
, 0), xoffset
));
1298 volatile_ok
= save_volatile_ok
;
1301 /* If op0 is a register, we need it in MAXMODE (which is usually
1302 SImode). to make it acceptable to the format of extzv. */
1303 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1305 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1306 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1308 /* On big-endian machines, we count bits from the most significant.
1309 If the bit field insn does not, we must invert. */
1310 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1311 xbitpos
= unit
- bitsize
- xbitpos
;
1313 /* Now convert from counting within UNIT to counting in MAXMODE. */
1314 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1315 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1317 unit
= GET_MODE_BITSIZE (maxmode
);
1320 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1321 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1323 if (GET_MODE (xtarget
) != maxmode
)
1325 if (GET_CODE (xtarget
) == REG
)
1327 int wider
= (GET_MODE_SIZE (maxmode
)
1328 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1329 xtarget
= gen_lowpart (maxmode
, xtarget
);
1331 xspec_target_subreg
= xtarget
;
1334 xtarget
= gen_reg_rtx (maxmode
);
1337 /* If this machine's extzv insists on a register target,
1338 make sure we have one. */
1339 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1340 (xtarget
, maxmode
)))
1341 xtarget
= gen_reg_rtx (maxmode
);
1343 bitsize_rtx
= GEN_INT (bitsize
);
1344 bitpos_rtx
= GEN_INT (xbitpos
);
1346 pat
= gen_extzv (protect_from_queue (xtarget
, 1),
1347 xop0
, bitsize_rtx
, bitpos_rtx
);
1352 spec_target
= xspec_target
;
1353 spec_target_subreg
= xspec_target_subreg
;
1357 delete_insns_since (last
);
1358 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1359 bitpos
, target
, 1, align
);
1365 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1366 bitpos
, target
, 1, align
);
1372 && (extv_bitsize
>= bitsize
)
1373 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1374 && (bitsize
+ bitpos
> extv_bitsize
)))
1376 int xbitpos
= bitpos
, xoffset
= offset
;
1377 rtx bitsize_rtx
, bitpos_rtx
;
1378 rtx last
= get_last_insn ();
1379 rtx xop0
= op0
, xtarget
= target
;
1380 rtx xspec_target
= spec_target
;
1381 rtx xspec_target_subreg
= spec_target_subreg
;
1383 enum machine_mode maxmode
;
1385 maxmode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
1386 if (maxmode
== VOIDmode
)
1387 maxmode
= word_mode
;
1389 if (GET_CODE (xop0
) == MEM
)
1391 /* Is the memory operand acceptable? */
1392 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1393 (xop0
, GET_MODE (xop0
))))
1395 /* No, load into a reg and extract from there. */
1396 enum machine_mode bestmode
;
1398 /* Get the mode to use for inserting into this field. If
1399 OP0 is BLKmode, get the smallest mode consistent with the
1400 alignment. If OP0 is a non-BLKmode object that is no
1401 wider than MAXMODE, use its mode. Otherwise, use the
1402 smallest mode containing the field. */
1404 if (GET_MODE (xop0
) == BLKmode
1405 || (GET_MODE_SIZE (GET_MODE (op0
))
1406 > GET_MODE_SIZE (maxmode
)))
1407 bestmode
= get_best_mode (bitsize
, bitnum
, align
, maxmode
,
1408 MEM_VOLATILE_P (xop0
));
1410 bestmode
= GET_MODE (xop0
);
1412 if (bestmode
== VOIDmode
1413 || (SLOW_UNALIGNED_ACCESS (bestmode
, align
)
1414 && GET_MODE_BITSIZE (bestmode
) > align
))
1417 /* Compute offset as multiple of this unit,
1418 counting in bytes. */
1419 unit
= GET_MODE_BITSIZE (bestmode
);
1420 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1421 xbitpos
= bitnum
% unit
;
1422 xop0
= change_address (xop0
, bestmode
,
1423 plus_constant (XEXP (xop0
, 0),
1425 /* Fetch it to a register in that size. */
1426 xop0
= force_reg (bestmode
, xop0
);
1428 /* XBITPOS counts within UNIT, which is what is expected. */
1431 /* Get ref to first byte containing part of the field. */
1432 xop0
= change_address (xop0
, byte_mode
,
1433 plus_constant (XEXP (xop0
, 0), xoffset
));
1436 /* If op0 is a register, we need it in MAXMODE (which is usually
1437 SImode) to make it acceptable to the format of extv. */
1438 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1440 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1441 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1443 /* On big-endian machines, we count bits from the most significant.
1444 If the bit field insn does not, we must invert. */
1445 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1446 xbitpos
= unit
- bitsize
- xbitpos
;
1448 /* XBITPOS counts within a size of UNIT.
1449 Adjust to count within a size of MAXMODE. */
1450 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1451 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1453 unit
= GET_MODE_BITSIZE (maxmode
);
1456 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1457 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1459 if (GET_MODE (xtarget
) != maxmode
)
1461 if (GET_CODE (xtarget
) == REG
)
1463 int wider
= (GET_MODE_SIZE (maxmode
)
1464 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1465 xtarget
= gen_lowpart (maxmode
, xtarget
);
1467 xspec_target_subreg
= xtarget
;
1470 xtarget
= gen_reg_rtx (maxmode
);
1473 /* If this machine's extv insists on a register target,
1474 make sure we have one. */
1475 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1476 (xtarget
, maxmode
)))
1477 xtarget
= gen_reg_rtx (maxmode
);
1479 bitsize_rtx
= GEN_INT (bitsize
);
1480 bitpos_rtx
= GEN_INT (xbitpos
);
1482 pat
= gen_extv (protect_from_queue (xtarget
, 1),
1483 xop0
, bitsize_rtx
, bitpos_rtx
);
1488 spec_target
= xspec_target
;
1489 spec_target_subreg
= xspec_target_subreg
;
1493 delete_insns_since (last
);
1494 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1495 bitpos
, target
, 0, align
);
1501 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1502 bitpos
, target
, 0, align
);
1504 if (target
== spec_target
)
1506 if (target
== spec_target_subreg
)
1508 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1510 /* If the target mode is floating-point, first convert to the
1511 integer mode of that size and then access it as a floating-point
1512 value via a SUBREG. */
1513 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1515 target
= convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode
),
1518 if (GET_CODE (target
) != REG
)
1519 target
= copy_to_reg (target
);
1520 return gen_rtx_SUBREG (tmode
, target
, 0);
1523 return convert_to_mode (tmode
, target
, unsignedp
);
1528 /* Extract a bit field using shifts and boolean operations
1529 Returns an rtx to represent the value.
1530 OP0 addresses a register (word) or memory (byte).
1531 BITPOS says which bit within the word or byte the bit field starts in.
1532 OFFSET says how many bytes farther the bit field starts;
1533 it is 0 if OP0 is a register.
1534 BITSIZE says how many bits long the bit field is.
1535 (If OP0 is a register, it may be narrower than a full word,
1536 but BITPOS still counts within a full word,
1537 which is significant on bigendian machines.)
1539 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1540 If TARGET is nonzero, attempts to store the value there
1541 and return TARGET, but this is not guaranteed.
1542 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1544 ALIGN is the alignment that STR_RTX is known to have. */
1547 extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
, bitpos
,
1548 target
, unsignedp
, align
)
1549 enum machine_mode tmode
;
1550 register rtx op0
, target
;
1551 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
1555 unsigned int total_bits
= BITS_PER_WORD
;
1556 enum machine_mode mode
;
1558 if (GET_CODE (op0
) == SUBREG
|| GET_CODE (op0
) == REG
)
1560 /* Special treatment for a bit field split across two registers. */
1561 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1562 return extract_split_bit_field (op0
, bitsize
, bitpos
,
1567 /* Get the proper mode to use for this field. We want a mode that
1568 includes the entire field. If such a mode would be larger than
1569 a word, we won't be doing the extraction the normal way. */
1571 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
, align
,
1573 GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
));
1575 if (mode
== VOIDmode
)
1576 /* The only way this should occur is if the field spans word
1578 return extract_split_bit_field (op0
, bitsize
,
1579 bitpos
+ offset
* BITS_PER_UNIT
,
1582 total_bits
= GET_MODE_BITSIZE (mode
);
1584 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1585 be in the range 0 to total_bits-1, and put any excess bytes in
1587 if (bitpos
>= total_bits
)
1589 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1590 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1594 /* Get ref to an aligned byte, halfword, or word containing the field.
1595 Adjust BITPOS to be position within a word,
1596 and OFFSET to be the offset of that word.
1597 Then alter OP0 to refer to that word. */
1598 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1599 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1600 op0
= change_address (op0
, mode
,
1601 plus_constant (XEXP (op0
, 0), offset
));
1604 mode
= GET_MODE (op0
);
1606 if (BYTES_BIG_ENDIAN
)
1608 /* BITPOS is the distance between our msb and that of OP0.
1609 Convert it to the distance from the lsb. */
1611 bitpos
= total_bits
- bitsize
- bitpos
;
1614 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1615 We have reduced the big-endian case to the little-endian case. */
1621 /* If the field does not already start at the lsb,
1622 shift it so it does. */
1623 tree amount
= build_int_2 (bitpos
, 0);
1624 /* Maybe propagate the target for the shift. */
1625 /* But not if we will return it--could confuse integrate.c. */
1626 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1627 && !REG_FUNCTION_VALUE_P (target
)
1629 if (tmode
!= mode
) subtarget
= 0;
1630 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1632 /* Convert the value to the desired mode. */
1634 op0
= convert_to_mode (tmode
, op0
, 1);
1636 /* Unless the msb of the field used to be the msb when we shifted,
1637 mask out the upper bits. */
1639 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
1641 #ifdef SLOW_ZERO_EXTEND
1642 /* Always generate an `and' if
1643 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1644 will combine fruitfully with the zero-extend. */
1649 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1650 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1651 target
, 1, OPTAB_LIB_WIDEN
);
1655 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1656 then arithmetic-shift its lsb to the lsb of the word. */
1657 op0
= force_reg (mode
, op0
);
1661 /* Find the narrowest integer mode that contains the field. */
1663 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1664 mode
= GET_MODE_WIDER_MODE (mode
))
1665 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1667 op0
= convert_to_mode (mode
, op0
, 0);
1671 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1673 tree amount
= build_int_2 (GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
), 0);
1674 /* Maybe propagate the target for the shift. */
1675 /* But not if we will return the result--could confuse integrate.c. */
1676 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1677 && ! REG_FUNCTION_VALUE_P (target
)
1679 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1682 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1683 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1687 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1688 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1689 complement of that if COMPLEMENT. The mask is truncated if
1690 necessary to the width of mode MODE. The mask is zero-extended if
1691 BITSIZE+BITPOS is too small for MODE. */
1694 mask_rtx (mode
, bitpos
, bitsize
, complement
)
1695 enum machine_mode mode
;
1696 int bitpos
, bitsize
, complement
;
1698 HOST_WIDE_INT masklow
, maskhigh
;
1700 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1701 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1705 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1706 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1707 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1709 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1712 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1714 if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1715 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1716 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1722 maskhigh
= ~maskhigh
;
1726 return immed_double_const (masklow
, maskhigh
, mode
);
1729 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1730 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1733 lshift_value (mode
, value
, bitpos
, bitsize
)
1734 enum machine_mode mode
;
1736 int bitpos
, bitsize
;
1738 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1739 HOST_WIDE_INT low
, high
;
1741 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1742 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1744 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1747 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1752 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1755 return immed_double_const (low
, high
, mode
);
1758 /* Extract a bit field that is split across two words
1759 and return an RTX for the result.
1761 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1762 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1763 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1765 ALIGN is the known alignment of OP0. This is also the size of the
1766 memory objects to be used. */
1769 extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
, align
)
1771 unsigned HOST_WIDE_INT bitsize
, bitpos
;
1776 unsigned int bitsdone
= 0;
1777 rtx result
= NULL_RTX
;
1780 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1782 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1783 unit
= BITS_PER_WORD
;
1785 unit
= MIN (align
, BITS_PER_WORD
);
1787 while (bitsdone
< bitsize
)
1789 unsigned HOST_WIDE_INT thissize
;
1791 unsigned HOST_WIDE_INT thispos
;
1792 unsigned HOST_WIDE_INT offset
;
1794 offset
= (bitpos
+ bitsdone
) / unit
;
1795 thispos
= (bitpos
+ bitsdone
) % unit
;
1797 /* THISSIZE must not overrun a word boundary. Otherwise,
1798 extract_fixed_bit_field will call us again, and we will mutually
1800 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1801 thissize
= MIN (thissize
, unit
- thispos
);
1803 /* If OP0 is a register, then handle OFFSET here.
1805 When handling multiword bitfields, extract_bit_field may pass
1806 down a word_mode SUBREG of a larger REG for a bitfield that actually
1807 crosses a word boundary. Thus, for a SUBREG, we must find
1808 the current word starting from the base register. */
1809 if (GET_CODE (op0
) == SUBREG
)
1811 word
= operand_subword_force (SUBREG_REG (op0
),
1812 SUBREG_WORD (op0
) + offset
,
1813 GET_MODE (SUBREG_REG (op0
)));
1816 else if (GET_CODE (op0
) == REG
)
1818 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1824 /* Extract the parts in bit-counting order,
1825 whose meaning is determined by BYTES_PER_UNIT.
1826 OFFSET is in UNITs, and UNIT is in bits.
1827 extract_fixed_bit_field wants offset in bytes. */
1828 part
= extract_fixed_bit_field (word_mode
, word
,
1829 offset
* unit
/ BITS_PER_UNIT
,
1830 thissize
, thispos
, 0, 1, align
);
1831 bitsdone
+= thissize
;
1833 /* Shift this part into place for the result. */
1834 if (BYTES_BIG_ENDIAN
)
1836 if (bitsize
!= bitsdone
)
1837 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1838 build_int_2 (bitsize
- bitsdone
, 0), 0, 1);
1842 if (bitsdone
!= thissize
)
1843 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1844 build_int_2 (bitsdone
- thissize
, 0), 0, 1);
1850 /* Combine the parts with bitwise or. This works
1851 because we extracted each part as an unsigned bit field. */
1852 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1858 /* Unsigned bit field: we are done. */
1861 /* Signed bit field: sign-extend with two arithmetic shifts. */
1862 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1863 build_int_2 (BITS_PER_WORD
- bitsize
, 0),
1865 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1866 build_int_2 (BITS_PER_WORD
- bitsize
, 0), NULL_RTX
, 0);
1869 /* Add INC into TARGET. */
1872 expand_inc (target
, inc
)
1875 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
1877 target
, 0, OPTAB_LIB_WIDEN
);
1878 if (value
!= target
)
1879 emit_move_insn (target
, value
);
1882 /* Subtract DEC from TARGET. */
1885 expand_dec (target
, dec
)
1888 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
1890 target
, 0, OPTAB_LIB_WIDEN
);
1891 if (value
!= target
)
1892 emit_move_insn (target
, value
);
1895 /* Output a shift instruction for expression code CODE,
1896 with SHIFTED being the rtx for the value to shift,
1897 and AMOUNT the tree for the amount to shift by.
1898 Store the result in the rtx TARGET, if that is convenient.
1899 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1900 Return the rtx for where the value is. */
1903 expand_shift (code
, mode
, shifted
, amount
, target
, unsignedp
)
1904 enum tree_code code
;
1905 register enum machine_mode mode
;
1908 register rtx target
;
1911 register rtx op1
, temp
= 0;
1912 register int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
1913 register int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
1916 /* Previously detected shift-counts computed by NEGATE_EXPR
1917 and shifted in the other direction; but that does not work
1920 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
1922 #ifdef SHIFT_COUNT_TRUNCATED
1923 if (SHIFT_COUNT_TRUNCATED
)
1925 if (GET_CODE (op1
) == CONST_INT
1926 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
1927 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
1928 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
1929 % GET_MODE_BITSIZE (mode
));
1930 else if (GET_CODE (op1
) == SUBREG
1931 && SUBREG_WORD (op1
) == 0)
1932 op1
= SUBREG_REG (op1
);
1936 if (op1
== const0_rtx
)
1939 for (try = 0; temp
== 0 && try < 3; try++)
1941 enum optab_methods methods
;
1944 methods
= OPTAB_DIRECT
;
1946 methods
= OPTAB_WIDEN
;
1948 methods
= OPTAB_LIB_WIDEN
;
1952 /* Widening does not work for rotation. */
1953 if (methods
== OPTAB_WIDEN
)
1955 else if (methods
== OPTAB_LIB_WIDEN
)
1957 /* If we have been unable to open-code this by a rotation,
1958 do it as the IOR of two shifts. I.e., to rotate A
1959 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1960 where C is the bitsize of A.
1962 It is theoretically possible that the target machine might
1963 not be able to perform either shift and hence we would
1964 be making two libcalls rather than just the one for the
1965 shift (similarly if IOR could not be done). We will allow
1966 this extremely unlikely lossage to avoid complicating the
1969 rtx subtarget
= target
== shifted
? 0 : target
;
1971 tree type
= TREE_TYPE (amount
);
1972 tree new_amount
= make_tree (type
, op1
);
1974 = fold (build (MINUS_EXPR
, type
,
1976 build_int_2 (GET_MODE_BITSIZE (mode
),
1980 shifted
= force_reg (mode
, shifted
);
1982 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
1983 mode
, shifted
, new_amount
, subtarget
, 1);
1984 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
1985 mode
, shifted
, other_amount
, 0, 1);
1986 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
1987 unsignedp
, methods
);
1990 temp
= expand_binop (mode
,
1991 left
? rotl_optab
: rotr_optab
,
1992 shifted
, op1
, target
, unsignedp
, methods
);
1994 /* If we don't have the rotate, but we are rotating by a constant
1995 that is in range, try a rotate in the opposite direction. */
1997 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
1998 && INTVAL (op1
) > 0 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
1999 temp
= expand_binop (mode
,
2000 left
? rotr_optab
: rotl_optab
,
2002 GEN_INT (GET_MODE_BITSIZE (mode
)
2004 target
, unsignedp
, methods
);
2007 temp
= expand_binop (mode
,
2008 left
? ashl_optab
: lshr_optab
,
2009 shifted
, op1
, target
, unsignedp
, methods
);
2011 /* Do arithmetic shifts.
2012 Also, if we are going to widen the operand, we can just as well
2013 use an arithmetic right-shift instead of a logical one. */
2014 if (temp
== 0 && ! rotate
2015 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2017 enum optab_methods methods1
= methods
;
2019 /* If trying to widen a log shift to an arithmetic shift,
2020 don't accept an arithmetic shift of the same size. */
2022 methods1
= OPTAB_MUST_WIDEN
;
2024 /* Arithmetic shift */
2026 temp
= expand_binop (mode
,
2027 left
? ashl_optab
: ashr_optab
,
2028 shifted
, op1
, target
, unsignedp
, methods1
);
2031 /* We used to try extzv here for logical right shifts, but that was
2032 only useful for one machine, the VAX, and caused poor code
2033 generation there for lshrdi3, so the code was deleted and a
2034 define_expand for lshrsi3 was added to vax.md. */
2042 enum alg_code
{ alg_zero
, alg_m
, alg_shift
,
2043 alg_add_t_m2
, alg_sub_t_m2
,
2044 alg_add_factor
, alg_sub_factor
,
2045 alg_add_t2_m
, alg_sub_t2_m
,
2046 alg_add
, alg_subtract
, alg_factor
, alg_shiftop
};
2048 /* This structure records a sequence of operations.
2049 `ops' is the number of operations recorded.
2050 `cost' is their total cost.
2051 The operations are stored in `op' and the corresponding
2052 logarithms of the integer coefficients in `log'.
2054 These are the operations:
2055 alg_zero total := 0;
2056 alg_m total := multiplicand;
2057 alg_shift total := total * coeff
2058 alg_add_t_m2 total := total + multiplicand * coeff;
2059 alg_sub_t_m2 total := total - multiplicand * coeff;
2060 alg_add_factor total := total * coeff + total;
2061 alg_sub_factor total := total * coeff - total;
2062 alg_add_t2_m total := total * coeff + multiplicand;
2063 alg_sub_t2_m total := total * coeff - multiplicand;
2065 The first operand must be either alg_zero or alg_m. */
2071 /* The size of the OP and LOG fields are not directly related to the
2072 word size, but the worst-case algorithms will be if we have few
2073 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2074 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2075 in total wordsize operations. */
2076 enum alg_code op
[MAX_BITS_PER_WORD
];
2077 char log
[MAX_BITS_PER_WORD
];
2080 static void synth_mult
PARAMS ((struct algorithm
*,
2081 unsigned HOST_WIDE_INT
,
2083 static unsigned HOST_WIDE_INT choose_multiplier
PARAMS ((unsigned HOST_WIDE_INT
,
2085 unsigned HOST_WIDE_INT
*,
2087 static unsigned HOST_WIDE_INT invert_mod2n
PARAMS ((unsigned HOST_WIDE_INT
,
2089 /* Compute and return the best algorithm for multiplying by T.
2090 The algorithm must cost less than cost_limit
2091 If retval.cost >= COST_LIMIT, no algorithm was found and all
2092 other field of the returned struct are undefined. */
2095 synth_mult (alg_out
, t
, cost_limit
)
2096 struct algorithm
*alg_out
;
2097 unsigned HOST_WIDE_INT t
;
2101 struct algorithm
*alg_in
, *best_alg
;
2103 unsigned HOST_WIDE_INT q
;
2105 /* Indicate that no algorithm is yet found. If no algorithm
2106 is found, this value will be returned and indicate failure. */
2107 alg_out
->cost
= cost_limit
;
2109 if (cost_limit
<= 0)
2112 /* t == 1 can be done in zero cost. */
2117 alg_out
->op
[0] = alg_m
;
2121 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2125 if (zero_cost
>= cost_limit
)
2130 alg_out
->cost
= zero_cost
;
2131 alg_out
->op
[0] = alg_zero
;
2136 /* We'll be needing a couple extra algorithm structures now. */
2138 alg_in
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2139 best_alg
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2141 /* If we have a group of zero bits at the low-order part of T, try
2142 multiplying by the remaining bits and then doing a shift. */
2146 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2147 if (m
< BITS_PER_WORD
)
2150 cost
= shift_cost
[m
];
2151 synth_mult (alg_in
, q
, cost_limit
- cost
);
2153 cost
+= alg_in
->cost
;
2154 if (cost
< cost_limit
)
2156 struct algorithm
*x
;
2157 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2158 best_alg
->log
[best_alg
->ops
] = m
;
2159 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2165 /* If we have an odd number, add or subtract one. */
2168 unsigned HOST_WIDE_INT w
;
2170 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2172 /* If T was -1, then W will be zero after the loop. This is another
2173 case where T ends with ...111. Handling this with (T + 1) and
2174 subtract 1 produces slightly better code and results in algorithm
2175 selection much faster than treating it like the ...0111 case
2179 /* Reject the case where t is 3.
2180 Thus we prefer addition in that case. */
2183 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2186 synth_mult (alg_in
, t
+ 1, cost_limit
- cost
);
2188 cost
+= alg_in
->cost
;
2189 if (cost
< cost_limit
)
2191 struct algorithm
*x
;
2192 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2193 best_alg
->log
[best_alg
->ops
] = 0;
2194 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2200 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2203 synth_mult (alg_in
, t
- 1, cost_limit
- cost
);
2205 cost
+= alg_in
->cost
;
2206 if (cost
< cost_limit
)
2208 struct algorithm
*x
;
2209 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2210 best_alg
->log
[best_alg
->ops
] = 0;
2211 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2217 /* Look for factors of t of the form
2218 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2219 If we find such a factor, we can multiply by t using an algorithm that
2220 multiplies by q, shift the result by m and add/subtract it to itself.
2222 We search for large factors first and loop down, even if large factors
2223 are less probable than small; if we find a large factor we will find a
2224 good sequence quickly, and therefore be able to prune (by decreasing
2225 COST_LIMIT) the search. */
2227 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2229 unsigned HOST_WIDE_INT d
;
2231 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2232 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2234 cost
= MIN (shiftadd_cost
[m
], add_cost
+ shift_cost
[m
]);
2235 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2237 cost
+= alg_in
->cost
;
2238 if (cost
< cost_limit
)
2240 struct algorithm
*x
;
2241 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2242 best_alg
->log
[best_alg
->ops
] = m
;
2243 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2246 /* Other factors will have been taken care of in the recursion. */
2250 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2251 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2253 cost
= MIN (shiftsub_cost
[m
], add_cost
+ shift_cost
[m
]);
2254 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2256 cost
+= alg_in
->cost
;
2257 if (cost
< cost_limit
)
2259 struct algorithm
*x
;
2260 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2261 best_alg
->log
[best_alg
->ops
] = m
;
2262 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2269 /* Try shift-and-add (load effective address) instructions,
2270 i.e. do a*3, a*5, a*9. */
2276 if (m
>= 0 && m
< BITS_PER_WORD
)
2278 cost
= shiftadd_cost
[m
];
2279 synth_mult (alg_in
, (t
- 1) >> m
, cost_limit
- cost
);
2281 cost
+= alg_in
->cost
;
2282 if (cost
< cost_limit
)
2284 struct algorithm
*x
;
2285 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2286 best_alg
->log
[best_alg
->ops
] = m
;
2287 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2295 if (m
>= 0 && m
< BITS_PER_WORD
)
2297 cost
= shiftsub_cost
[m
];
2298 synth_mult (alg_in
, (t
+ 1) >> m
, cost_limit
- cost
);
2300 cost
+= alg_in
->cost
;
2301 if (cost
< cost_limit
)
2303 struct algorithm
*x
;
2304 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2305 best_alg
->log
[best_alg
->ops
] = m
;
2306 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2312 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2313 we have not found any algorithm. */
2314 if (cost_limit
== alg_out
->cost
)
2317 /* If we are getting a too long sequence for `struct algorithm'
2318 to record, make this search fail. */
2319 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2322 /* Copy the algorithm from temporary space to the space at alg_out.
2323 We avoid using structure assignment because the majority of
2324 best_alg is normally undefined, and this is a critical function. */
2325 alg_out
->ops
= best_alg
->ops
+ 1;
2326 alg_out
->cost
= cost_limit
;
2327 memcpy (alg_out
->op
, best_alg
->op
,
2328 alg_out
->ops
* sizeof *alg_out
->op
);
2329 memcpy (alg_out
->log
, best_alg
->log
,
2330 alg_out
->ops
* sizeof *alg_out
->log
);
2333 /* Perform a multiplication and return an rtx for the result.
2334 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2335 TARGET is a suggestion for where to store the result (an rtx).
2337 We check specially for a constant integer as OP1.
2338 If you want this check for OP0 as well, then before calling
2339 you should swap the two operands if OP0 would be constant. */
2342 expand_mult (mode
, op0
, op1
, target
, unsignedp
)
2343 enum machine_mode mode
;
2344 register rtx op0
, op1
, target
;
2347 rtx const_op1
= op1
;
2349 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2350 less than or equal in size to `unsigned int' this doesn't matter.
2351 If the mode is larger than `unsigned int', then synth_mult works only
2352 if the constant value exactly fits in an `unsigned int' without any
2353 truncation. This means that multiplying by negative values does
2354 not work; results are off by 2^32 on a 32 bit machine. */
2356 /* If we are multiplying in DImode, it may still be a win
2357 to try to work with shifts and adds. */
2358 if (GET_CODE (op1
) == CONST_DOUBLE
2359 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
2360 && HOST_BITS_PER_INT
>= BITS_PER_WORD
2361 && CONST_DOUBLE_HIGH (op1
) == 0)
2362 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2363 else if (HOST_BITS_PER_INT
< GET_MODE_BITSIZE (mode
)
2364 && GET_CODE (op1
) == CONST_INT
2365 && INTVAL (op1
) < 0)
2368 /* We used to test optimize here, on the grounds that it's better to
2369 produce a smaller program when -O is not used.
2370 But this causes such a terrible slowdown sometimes
2371 that it seems better to use synth_mult always. */
2373 if (const_op1
&& GET_CODE (const_op1
) == CONST_INT
2374 && (unsignedp
|| ! flag_trapv
))
2376 struct algorithm alg
;
2377 struct algorithm alg2
;
2378 HOST_WIDE_INT val
= INTVAL (op1
);
2379 HOST_WIDE_INT val_so_far
;
2382 enum {basic_variant
, negate_variant
, add_variant
} variant
= basic_variant
;
2384 /* Try to do the computation three ways: multiply by the negative of OP1
2385 and then negate, do the multiplication directly, or do multiplication
2388 mult_cost
= rtx_cost (gen_rtx_MULT (mode
, op0
, op1
), SET
);
2389 mult_cost
= MIN (12 * add_cost
, mult_cost
);
2391 synth_mult (&alg
, val
, mult_cost
);
2393 /* This works only if the inverted value actually fits in an
2395 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2397 synth_mult (&alg2
, - val
,
2398 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - negate_cost
);
2399 if (alg2
.cost
+ negate_cost
< alg
.cost
)
2400 alg
= alg2
, variant
= negate_variant
;
2403 /* This proves very useful for division-by-constant. */
2404 synth_mult (&alg2
, val
- 1,
2405 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - add_cost
);
2406 if (alg2
.cost
+ add_cost
< alg
.cost
)
2407 alg
= alg2
, variant
= add_variant
;
2409 if (alg
.cost
< mult_cost
)
2411 /* We found something cheaper than a multiply insn. */
2414 enum machine_mode nmode
;
2416 op0
= protect_from_queue (op0
, 0);
2418 /* Avoid referencing memory over and over.
2419 For speed, but also for correctness when mem is volatile. */
2420 if (GET_CODE (op0
) == MEM
)
2421 op0
= force_reg (mode
, op0
);
2423 /* ACCUM starts out either as OP0 or as a zero, depending on
2424 the first operation. */
2426 if (alg
.op
[0] == alg_zero
)
2428 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2431 else if (alg
.op
[0] == alg_m
)
2433 accum
= copy_to_mode_reg (mode
, op0
);
2439 for (opno
= 1; opno
< alg
.ops
; opno
++)
2441 int log
= alg
.log
[opno
];
2442 int preserve
= preserve_subexpressions_p ();
2443 rtx shift_subtarget
= preserve
? 0 : accum
;
2445 = (opno
== alg
.ops
- 1 && target
!= 0 && variant
!= add_variant
2448 rtx accum_target
= preserve
? 0 : accum
;
2450 switch (alg
.op
[opno
])
2453 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2454 build_int_2 (log
, 0), NULL_RTX
, 0);
2459 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2460 build_int_2 (log
, 0), NULL_RTX
, 0);
2461 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2463 ? add_target
: accum_target
);
2464 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2468 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2469 build_int_2 (log
, 0), NULL_RTX
, 0);
2470 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2472 ? add_target
: accum_target
);
2473 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2477 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2478 build_int_2 (log
, 0), shift_subtarget
,
2480 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2482 ? add_target
: accum_target
);
2483 val_so_far
= (val_so_far
<< log
) + 1;
2487 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2488 build_int_2 (log
, 0), shift_subtarget
,
2490 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2492 ? add_target
: accum_target
);
2493 val_so_far
= (val_so_far
<< log
) - 1;
2496 case alg_add_factor
:
2497 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2498 build_int_2 (log
, 0), NULL_RTX
, 0);
2499 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2501 ? add_target
: accum_target
);
2502 val_so_far
+= val_so_far
<< log
;
2505 case alg_sub_factor
:
2506 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2507 build_int_2 (log
, 0), NULL_RTX
, 0);
2508 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2509 (add_target
? add_target
2510 : preserve
? 0 : tem
));
2511 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2518 /* Write a REG_EQUAL note on the last insn so that we can cse
2519 multiplication sequences. Note that if ACCUM is a SUBREG,
2520 we've set the inner register and must properly indicate
2523 tem
= op0
, nmode
= mode
;
2524 if (GET_CODE (accum
) == SUBREG
)
2526 nmode
= GET_MODE (SUBREG_REG (accum
));
2527 tem
= gen_lowpart (nmode
, op0
);
2530 insn
= get_last_insn ();
2531 set_unique_reg_note (insn
,
2533 gen_rtx_MULT (nmode
, tem
,
2534 GEN_INT (val_so_far
)));
2537 if (variant
== negate_variant
)
2539 val_so_far
= - val_so_far
;
2540 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2542 else if (variant
== add_variant
)
2544 val_so_far
= val_so_far
+ 1;
2545 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2548 if (val
!= val_so_far
)
2555 /* This used to use umul_optab if unsigned, but for non-widening multiply
2556 there is no difference between signed and unsigned. */
2557 op0
= expand_binop (mode
,
2559 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
2560 ? smulv_optab
: smul_optab
,
2561 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
2567 /* Return the smallest n such that 2**n >= X. */
2571 unsigned HOST_WIDE_INT x
;
2573 return floor_log2 (x
- 1) + 1;
2576 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2577 replace division by D, and put the least significant N bits of the result
2578 in *MULTIPLIER_PTR and return the most significant bit.
2580 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2581 needed precision is in PRECISION (should be <= N).
2583 PRECISION should be as small as possible so this function can choose
2584 multiplier more freely.
2586 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2587 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2589 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2590 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2593 unsigned HOST_WIDE_INT
2594 choose_multiplier (d
, n
, precision
, multiplier_ptr
, post_shift_ptr
, lgup_ptr
)
2595 unsigned HOST_WIDE_INT d
;
2598 unsigned HOST_WIDE_INT
*multiplier_ptr
;
2599 int *post_shift_ptr
;
2602 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
2603 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
2604 int lgup
, post_shift
;
2606 unsigned HOST_WIDE_INT nl
, dummy1
;
2607 HOST_WIDE_INT nh
, dummy2
;
2609 /* lgup = ceil(log2(divisor)); */
2610 lgup
= ceil_log2 (d
);
2616 pow2
= n
+ lgup
- precision
;
2618 if (pow
== 2 * HOST_BITS_PER_WIDE_INT
)
2620 /* We could handle this with some effort, but this case is much better
2621 handled directly with a scc insn, so rely on caller using that. */
2625 /* mlow = 2^(N + lgup)/d */
2626 if (pow
>= HOST_BITS_PER_WIDE_INT
)
2628 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
2634 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
2636 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2637 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
2639 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2640 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
2641 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
2643 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
2644 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2645 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
2647 if (mhigh_hi
&& nh
- d
>= d
)
2649 if (mhigh_hi
> 1 || mlow_hi
> 1)
2651 /* assert that mlow < mhigh. */
2652 if (! (mlow_hi
< mhigh_hi
|| (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
)))
2655 /* If precision == N, then mlow, mhigh exceed 2^N
2656 (but they do not exceed 2^(N+1)). */
2658 /* Reduce to lowest terms */
2659 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
2661 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
2662 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
2672 *post_shift_ptr
= post_shift
;
2674 if (n
< HOST_BITS_PER_WIDE_INT
)
2676 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
2677 *multiplier_ptr
= mhigh_lo
& mask
;
2678 return mhigh_lo
>= mask
;
2682 *multiplier_ptr
= mhigh_lo
;
2687 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2688 congruent to 1 (mod 2**N). */
2690 static unsigned HOST_WIDE_INT
2692 unsigned HOST_WIDE_INT x
;
2695 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2697 /* The algorithm notes that the choice y = x satisfies
2698 x*y == 1 mod 2^3, since x is assumed odd.
2699 Each iteration doubles the number of bits of significance in y. */
2701 unsigned HOST_WIDE_INT mask
;
2702 unsigned HOST_WIDE_INT y
= x
;
2705 mask
= (n
== HOST_BITS_PER_WIDE_INT
2706 ? ~(unsigned HOST_WIDE_INT
) 0
2707 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
2711 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
2717 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2718 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2719 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2720 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2723 The result is put in TARGET if that is convenient.
2725 MODE is the mode of operation. */
2728 expand_mult_highpart_adjust (mode
, adj_operand
, op0
, op1
, target
, unsignedp
)
2729 enum machine_mode mode
;
2730 register rtx adj_operand
, op0
, op1
, target
;
2734 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
2736 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2737 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2739 tem
= expand_and (tem
, op1
, NULL_RTX
);
2741 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2744 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
2745 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2747 tem
= expand_and (tem
, op0
, NULL_RTX
);
2748 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2754 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2755 in TARGET if that is convenient, and return where the result is. If the
2756 operation can not be performed, 0 is returned.
2758 MODE is the mode of operation and result.
2760 UNSIGNEDP nonzero means unsigned multiply.
2762 MAX_COST is the total allowed cost for the expanded RTL. */
2765 expand_mult_highpart (mode
, op0
, cnst1
, target
, unsignedp
, max_cost
)
2766 enum machine_mode mode
;
2767 register rtx op0
, target
;
2768 unsigned HOST_WIDE_INT cnst1
;
2772 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
2773 optab mul_highpart_optab
;
2776 int size
= GET_MODE_BITSIZE (mode
);
2779 /* We can't support modes wider than HOST_BITS_PER_INT. */
2780 if (size
> HOST_BITS_PER_WIDE_INT
)
2783 op1
= GEN_INT (cnst1
);
2785 if (GET_MODE_BITSIZE (wider_mode
) <= HOST_BITS_PER_INT
)
2789 = immed_double_const (cnst1
,
2792 : -(cnst1
>> (HOST_BITS_PER_WIDE_INT
- 1))),
2795 /* expand_mult handles constant multiplication of word_mode
2796 or narrower. It does a poor job for large modes. */
2797 if (size
< BITS_PER_WORD
2798 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2800 /* We have to do this, since expand_binop doesn't do conversion for
2801 multiply. Maybe change expand_binop to handle widening multiply? */
2802 op0
= convert_to_mode (wider_mode
, op0
, unsignedp
);
2804 /* We know that this can't have signed overflow, so pretend this is
2805 an unsigned multiply. */
2806 tem
= expand_mult (wider_mode
, op0
, wide_op1
, NULL_RTX
, 0);
2807 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2808 build_int_2 (size
, 0), NULL_RTX
, 1);
2809 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2813 target
= gen_reg_rtx (mode
);
2815 /* Firstly, try using a multiplication insn that only generates the needed
2816 high part of the product, and in the sign flavor of unsignedp. */
2817 if (mul_highpart_cost
[(int) mode
] < max_cost
)
2819 mul_highpart_optab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
2820 target
= expand_binop (mode
, mul_highpart_optab
,
2821 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2826 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2827 Need to adjust the result after the multiplication. */
2828 if (size
- 1 < BITS_PER_WORD
2829 && (mul_highpart_cost
[(int) mode
] + 2 * shift_cost
[size
-1] + 4 * add_cost
2832 mul_highpart_optab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
2833 target
= expand_binop (mode
, mul_highpart_optab
,
2834 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2836 /* We used the wrong signedness. Adjust the result. */
2837 return expand_mult_highpart_adjust (mode
, target
, op0
,
2838 op1
, target
, unsignedp
);
2841 /* Try widening multiplication. */
2842 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
2843 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2844 && mul_widen_cost
[(int) wider_mode
] < max_cost
)
2846 op1
= force_reg (mode
, op1
);
2850 /* Try widening the mode and perform a non-widening multiplication. */
2851 moptab
= smul_optab
;
2852 if (smul_optab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2853 && size
- 1 < BITS_PER_WORD
2854 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2860 /* Try widening multiplication of opposite signedness, and adjust. */
2861 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
2862 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2863 && size
- 1 < BITS_PER_WORD
2864 && (mul_widen_cost
[(int) wider_mode
]
2865 + 2 * shift_cost
[size
-1] + 4 * add_cost
< max_cost
))
2867 rtx regop1
= force_reg (mode
, op1
);
2868 tem
= expand_binop (wider_mode
, moptab
, op0
, regop1
,
2869 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
2872 /* Extract the high half of the just generated product. */
2873 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2874 build_int_2 (size
, 0), NULL_RTX
, 1);
2875 tem
= convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2876 /* We used the wrong signedness. Adjust the result. */
2877 return expand_mult_highpart_adjust (mode
, tem
, op0
, op1
,
2885 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2886 tem
= expand_binop (wider_mode
, moptab
, op0
, op1
,
2887 NULL_RTX
, unsignedp
, OPTAB_WIDEN
);
2891 /* Extract the high half of the just generated product. */
2892 if (mode
== word_mode
)
2894 return gen_highpart (mode
, tem
);
2898 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2899 build_int_2 (size
, 0), NULL_RTX
, 1);
2900 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2904 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2905 if that is convenient, and returning where the result is.
2906 You may request either the quotient or the remainder as the result;
2907 specify REM_FLAG nonzero to get the remainder.
2909 CODE is the expression code for which kind of division this is;
2910 it controls how rounding is done. MODE is the machine mode to use.
2911 UNSIGNEDP nonzero means do unsigned division. */
2913 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2914 and then correct it by or'ing in missing high bits
2915 if result of ANDI is nonzero.
2916 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2917 This could optimize to a bfexts instruction.
2918 But C doesn't use these operations, so their optimizations are
2920 /* ??? For modulo, we don't actually need the highpart of the first product,
2921 the low part will do nicely. And for small divisors, the second multiply
2922 can also be a low-part only multiply or even be completely left out.
2923 E.g. to calculate the remainder of a division by 3 with a 32 bit
2924 multiply, multiply with 0x55555556 and extract the upper two bits;
2925 the result is exact for inputs up to 0x1fffffff.
2926 The input range can be reduced by using cross-sum rules.
2927 For odd divisors >= 3, the following table gives right shift counts
2928 so that if an number is shifted by an integer multiple of the given
2929 amount, the remainder stays the same:
2930 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
2931 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
2932 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
2933 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
2934 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
2936 Cross-sum rules for even numbers can be derived by leaving as many bits
2937 to the right alone as the divisor has zeros to the right.
2938 E.g. if x is an unsigned 32 bit number:
2939 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
2942 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2945 expand_divmod (rem_flag
, code
, mode
, op0
, op1
, target
, unsignedp
)
2947 enum tree_code code
;
2948 enum machine_mode mode
;
2949 register rtx op0
, op1
, target
;
2952 enum machine_mode compute_mode
;
2953 register rtx tquotient
;
2954 rtx quotient
= 0, remainder
= 0;
2958 optab optab1
, optab2
;
2959 int op1_is_constant
, op1_is_pow2
;
2960 int max_cost
, extra_cost
;
2961 static HOST_WIDE_INT last_div_const
= 0;
2963 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
2964 op1_is_pow2
= (op1_is_constant
2965 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
2966 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
))))));
2969 This is the structure of expand_divmod:
2971 First comes code to fix up the operands so we can perform the operations
2972 correctly and efficiently.
2974 Second comes a switch statement with code specific for each rounding mode.
2975 For some special operands this code emits all RTL for the desired
2976 operation, for other cases, it generates only a quotient and stores it in
2977 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2978 to indicate that it has not done anything.
2980 Last comes code that finishes the operation. If QUOTIENT is set and
2981 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
2982 QUOTIENT is not set, it is computed using trunc rounding.
2984 We try to generate special code for division and remainder when OP1 is a
2985 constant. If |OP1| = 2**n we can use shifts and some other fast
2986 operations. For other values of OP1, we compute a carefully selected
2987 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2990 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2991 half of the product. Different strategies for generating the product are
2992 implemented in expand_mult_highpart.
2994 If what we actually want is the remainder, we generate that by another
2995 by-constant multiplication and a subtraction. */
2997 /* We shouldn't be called with OP1 == const1_rtx, but some of the
2998 code below will malfunction if we are, so check here and handle
2999 the special case if so. */
3000 if (op1
== const1_rtx
)
3001 return rem_flag
? const0_rtx
: op0
;
3003 /* When dividing by -1, we could get an overflow.
3004 negv_optab can handle overflows. */
3005 if (! unsignedp
&& op1
== constm1_rtx
)
3009 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3010 ? negv_optab
: neg_optab
, op0
, target
, 0);
3014 /* Don't use the function value register as a target
3015 since we have to read it as well as write it,
3016 and function-inlining gets confused by this. */
3017 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3018 /* Don't clobber an operand while doing a multi-step calculation. */
3019 || ((rem_flag
|| op1_is_constant
)
3020 && (reg_mentioned_p (target
, op0
)
3021 || (GET_CODE (op0
) == MEM
&& GET_CODE (target
) == MEM
)))
3022 || reg_mentioned_p (target
, op1
)
3023 || (GET_CODE (op1
) == MEM
&& GET_CODE (target
) == MEM
)))
3026 /* Get the mode in which to perform this computation. Normally it will
3027 be MODE, but sometimes we can't do the desired operation in MODE.
3028 If so, pick a wider mode in which we can do the operation. Convert
3029 to that mode at the start to avoid repeated conversions.
3031 First see what operations we need. These depend on the expression
3032 we are evaluating. (We assume that divxx3 insns exist under the
3033 same conditions that modxx3 insns and that these insns don't normally
3034 fail. If these assumptions are not correct, we may generate less
3035 efficient code in some cases.)
3037 Then see if we find a mode in which we can open-code that operation
3038 (either a division, modulus, or shift). Finally, check for the smallest
3039 mode for which we can do the operation with a library call. */
3041 /* We might want to refine this now that we have division-by-constant
3042 optimization. Since expand_mult_highpart tries so many variants, it is
3043 not straightforward to generalize this. Maybe we should make an array
3044 of possible modes in init_expmed? Save this for GCC 2.7. */
3046 optab1
= (op1_is_pow2
? (unsignedp
? lshr_optab
: ashr_optab
)
3047 : (unsignedp
? udiv_optab
: sdiv_optab
));
3048 optab2
= (op1_is_pow2
? optab1
: (unsignedp
? udivmod_optab
: sdivmod_optab
));
3050 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3051 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3052 if (optab1
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
3053 || optab2
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
)
3056 if (compute_mode
== VOIDmode
)
3057 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3058 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3059 if (optab1
->handlers
[(int) compute_mode
].libfunc
3060 || optab2
->handlers
[(int) compute_mode
].libfunc
)
3063 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3065 if (compute_mode
== VOIDmode
)
3066 compute_mode
= mode
;
3068 if (target
&& GET_MODE (target
) == compute_mode
)
3071 tquotient
= gen_reg_rtx (compute_mode
);
3073 size
= GET_MODE_BITSIZE (compute_mode
);
3075 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3076 (mode), and thereby get better code when OP1 is a constant. Do that
3077 later. It will require going over all usages of SIZE below. */
3078 size
= GET_MODE_BITSIZE (mode
);
3081 /* Only deduct something for a REM if the last divide done was
3082 for a different constant. Then set the constant of the last
3084 max_cost
= div_cost
[(int) compute_mode
]
3085 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3086 && INTVAL (op1
) == last_div_const
)
3087 ? mul_cost
[(int) compute_mode
] + add_cost
: 0);
3089 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3091 /* Now convert to the best mode to use. */
3092 if (compute_mode
!= mode
)
3094 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3095 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3097 /* convert_modes may have placed op1 into a register, so we
3098 must recompute the following. */
3099 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3100 op1_is_pow2
= (op1_is_constant
3101 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3103 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3106 /* If one of the operands is a volatile MEM, copy it into a register. */
3108 if (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
))
3109 op0
= force_reg (compute_mode
, op0
);
3110 if (GET_CODE (op1
) == MEM
&& MEM_VOLATILE_P (op1
))
3111 op1
= force_reg (compute_mode
, op1
);
3113 /* If we need the remainder or if OP1 is constant, we need to
3114 put OP0 in a register in case it has any queued subexpressions. */
3115 if (rem_flag
|| op1_is_constant
)
3116 op0
= force_reg (compute_mode
, op0
);
3118 last
= get_last_insn ();
3120 /* Promote floor rounding to trunc rounding for unsigned operations. */
3123 if (code
== FLOOR_DIV_EXPR
)
3124 code
= TRUNC_DIV_EXPR
;
3125 if (code
== FLOOR_MOD_EXPR
)
3126 code
= TRUNC_MOD_EXPR
;
3127 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3128 code
= TRUNC_DIV_EXPR
;
3131 if (op1
!= const0_rtx
)
3134 case TRUNC_MOD_EXPR
:
3135 case TRUNC_DIV_EXPR
:
3136 if (op1_is_constant
)
3140 unsigned HOST_WIDE_INT mh
, ml
;
3141 int pre_shift
, post_shift
;
3143 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3145 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3147 pre_shift
= floor_log2 (d
);
3151 = expand_binop (compute_mode
, and_optab
, op0
,
3152 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3156 return gen_lowpart (mode
, remainder
);
3158 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3159 build_int_2 (pre_shift
, 0),
3162 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3164 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3166 /* Most significant bit of divisor is set; emit an scc
3168 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3169 compute_mode
, 1, 1);
3175 /* Find a suitable multiplier and right shift count
3176 instead of multiplying with D. */
3178 mh
= choose_multiplier (d
, size
, size
,
3179 &ml
, &post_shift
, &dummy
);
3181 /* If the suggested multiplier is more than SIZE bits,
3182 we can do better for even divisors, using an
3183 initial right shift. */
3184 if (mh
!= 0 && (d
& 1) == 0)
3186 pre_shift
= floor_log2 (d
& -d
);
3187 mh
= choose_multiplier (d
>> pre_shift
, size
,
3189 &ml
, &post_shift
, &dummy
);
3200 if (post_shift
- 1 >= BITS_PER_WORD
)
3203 extra_cost
= (shift_cost
[post_shift
- 1]
3204 + shift_cost
[1] + 2 * add_cost
);
3205 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3207 max_cost
- extra_cost
);
3210 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
3213 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3214 build_int_2 (1, 0), NULL_RTX
,1);
3215 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
3219 = expand_shift (RSHIFT_EXPR
, compute_mode
, t4
,
3220 build_int_2 (post_shift
- 1, 0),
3227 if (pre_shift
>= BITS_PER_WORD
3228 || post_shift
>= BITS_PER_WORD
)
3231 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3232 build_int_2 (pre_shift
, 0),
3234 extra_cost
= (shift_cost
[pre_shift
]
3235 + shift_cost
[post_shift
]);
3236 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
3238 max_cost
- extra_cost
);
3242 = expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3243 build_int_2 (post_shift
, 0),
3248 else /* Too wide mode to use tricky code */
3251 insn
= get_last_insn ();
3253 && (set
= single_set (insn
)) != 0
3254 && SET_DEST (set
) == quotient
)
3255 set_unique_reg_note (insn
,
3257 gen_rtx_UDIV (compute_mode
, op0
, op1
));
3259 else /* TRUNC_DIV, signed */
3261 unsigned HOST_WIDE_INT ml
;
3262 int lgup
, post_shift
;
3263 HOST_WIDE_INT d
= INTVAL (op1
);
3264 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
3266 /* n rem d = n rem -d */
3267 if (rem_flag
&& d
< 0)
3270 op1
= GEN_INT (abs_d
);
3276 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
3278 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3280 /* This case is not handled correctly below. */
3281 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
3282 compute_mode
, 1, 1);
3286 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
3287 && (rem_flag
? smod_pow2_cheap
: sdiv_pow2_cheap
))
3289 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
3291 lgup
= floor_log2 (abs_d
);
3292 if (BRANCH_COST
< 1 || (abs_d
!= 2 && BRANCH_COST
< 3))
3294 rtx label
= gen_label_rtx ();
3297 t1
= copy_to_mode_reg (compute_mode
, op0
);
3298 do_cmp_and_jump (t1
, const0_rtx
, GE
,
3299 compute_mode
, label
);
3300 expand_inc (t1
, GEN_INT (abs_d
- 1));
3302 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3303 build_int_2 (lgup
, 0),
3309 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3310 build_int_2 (size
- 1, 0),
3312 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3313 build_int_2 (size
- lgup
, 0),
3315 t3
= force_operand (gen_rtx_PLUS (compute_mode
,
3318 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3319 build_int_2 (lgup
, 0),
3323 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3327 insn
= get_last_insn ();
3329 && (set
= single_set (insn
)) != 0
3330 && SET_DEST (set
) == quotient
3331 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
3332 << (HOST_BITS_PER_WIDE_INT
- 1)))
3333 set_unique_reg_note (insn
,
3335 gen_rtx_DIV (compute_mode
,
3339 quotient
= expand_unop (compute_mode
, neg_optab
,
3340 quotient
, quotient
, 0);
3343 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3345 choose_multiplier (abs_d
, size
, size
- 1,
3346 &ml
, &post_shift
, &lgup
);
3347 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3351 if (post_shift
>= BITS_PER_WORD
3352 || size
- 1 >= BITS_PER_WORD
)
3355 extra_cost
= (shift_cost
[post_shift
]
3356 + shift_cost
[size
- 1] + add_cost
);
3357 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3359 max_cost
- extra_cost
);
3362 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3363 build_int_2 (post_shift
, 0), NULL_RTX
, 0);
3364 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3365 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3368 = force_operand (gen_rtx_MINUS (compute_mode
,
3373 = force_operand (gen_rtx_MINUS (compute_mode
,
3381 if (post_shift
>= BITS_PER_WORD
3382 || size
- 1 >= BITS_PER_WORD
)
3385 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
3386 extra_cost
= (shift_cost
[post_shift
]
3387 + shift_cost
[size
- 1] + 2 * add_cost
);
3388 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3390 max_cost
- extra_cost
);
3393 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
3396 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3397 build_int_2 (post_shift
, 0),
3399 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3400 build_int_2 (size
- 1, 0),
3404 = force_operand (gen_rtx_MINUS (compute_mode
,
3409 = force_operand (gen_rtx_MINUS (compute_mode
,
3414 else /* Too wide mode to use tricky code */
3417 insn
= get_last_insn ();
3419 && (set
= single_set (insn
)) != 0
3420 && SET_DEST (set
) == quotient
)
3421 set_unique_reg_note (insn
,
3423 gen_rtx_DIV (compute_mode
, op0
, op1
));
3428 delete_insns_since (last
);
3431 case FLOOR_DIV_EXPR
:
3432 case FLOOR_MOD_EXPR
:
3433 /* We will come here only for signed operations. */
3434 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3436 unsigned HOST_WIDE_INT mh
, ml
;
3437 int pre_shift
, lgup
, post_shift
;
3438 HOST_WIDE_INT d
= INTVAL (op1
);
3442 /* We could just as easily deal with negative constants here,
3443 but it does not seem worth the trouble for GCC 2.6. */
3444 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3446 pre_shift
= floor_log2 (d
);
3449 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
3450 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3451 remainder
, 0, OPTAB_LIB_WIDEN
);
3453 return gen_lowpart (mode
, remainder
);
3455 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3456 build_int_2 (pre_shift
, 0),
3463 mh
= choose_multiplier (d
, size
, size
- 1,
3464 &ml
, &post_shift
, &lgup
);
3468 if (post_shift
< BITS_PER_WORD
3469 && size
- 1 < BITS_PER_WORD
)
3471 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3472 build_int_2 (size
- 1, 0),
3474 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
3475 NULL_RTX
, 0, OPTAB_WIDEN
);
3476 extra_cost
= (shift_cost
[post_shift
]
3477 + shift_cost
[size
- 1] + 2 * add_cost
);
3478 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
3480 max_cost
- extra_cost
);
3483 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3484 build_int_2 (post_shift
, 0),
3486 quotient
= expand_binop (compute_mode
, xor_optab
,
3487 t4
, t1
, tquotient
, 0,
3495 rtx nsign
, t1
, t2
, t3
, t4
;
3496 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
3497 op0
, constm1_rtx
), NULL_RTX
);
3498 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
3500 nsign
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3501 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3502 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
3504 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
3509 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
3511 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3520 delete_insns_since (last
);
3522 /* Try using an instruction that produces both the quotient and
3523 remainder, using truncation. We can easily compensate the quotient
3524 or remainder to get floor rounding, once we have the remainder.
3525 Notice that we compute also the final remainder value here,
3526 and return the result right away. */
3527 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3528 target
= gen_reg_rtx (compute_mode
);
3533 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3534 quotient
= gen_reg_rtx (compute_mode
);
3539 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3540 remainder
= gen_reg_rtx (compute_mode
);
3543 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
3544 quotient
, remainder
, 0))
3546 /* This could be computed with a branch-less sequence.
3547 Save that for later. */
3549 rtx label
= gen_label_rtx ();
3550 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
3551 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3552 NULL_RTX
, 0, OPTAB_WIDEN
);
3553 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
3554 expand_dec (quotient
, const1_rtx
);
3555 expand_inc (remainder
, op1
);
3557 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3560 /* No luck with division elimination or divmod. Have to do it
3561 by conditionally adjusting op0 *and* the result. */
3563 rtx label1
, label2
, label3
, label4
, label5
;
3567 quotient
= gen_reg_rtx (compute_mode
);
3568 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3569 label1
= gen_label_rtx ();
3570 label2
= gen_label_rtx ();
3571 label3
= gen_label_rtx ();
3572 label4
= gen_label_rtx ();
3573 label5
= gen_label_rtx ();
3574 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3575 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
3576 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3577 quotient
, 0, OPTAB_LIB_WIDEN
);
3578 if (tem
!= quotient
)
3579 emit_move_insn (quotient
, tem
);
3580 emit_jump_insn (gen_jump (label5
));
3582 emit_label (label1
);
3583 expand_inc (adjusted_op0
, const1_rtx
);
3584 emit_jump_insn (gen_jump (label4
));
3586 emit_label (label2
);
3587 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
3588 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3589 quotient
, 0, OPTAB_LIB_WIDEN
);
3590 if (tem
!= quotient
)
3591 emit_move_insn (quotient
, tem
);
3592 emit_jump_insn (gen_jump (label5
));
3594 emit_label (label3
);
3595 expand_dec (adjusted_op0
, const1_rtx
);
3596 emit_label (label4
);
3597 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3598 quotient
, 0, OPTAB_LIB_WIDEN
);
3599 if (tem
!= quotient
)
3600 emit_move_insn (quotient
, tem
);
3601 expand_dec (quotient
, const1_rtx
);
3602 emit_label (label5
);
3610 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
3613 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3614 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3615 build_int_2 (floor_log2 (d
), 0),
3617 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3619 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3620 t3
= gen_reg_rtx (compute_mode
);
3621 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3622 compute_mode
, 1, 1);
3626 lab
= gen_label_rtx ();
3627 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3628 expand_inc (t1
, const1_rtx
);
3633 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3639 /* Try using an instruction that produces both the quotient and
3640 remainder, using truncation. We can easily compensate the
3641 quotient or remainder to get ceiling rounding, once we have the
3642 remainder. Notice that we compute also the final remainder
3643 value here, and return the result right away. */
3644 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3645 target
= gen_reg_rtx (compute_mode
);
3649 remainder
= (GET_CODE (target
) == REG
3650 ? target
: gen_reg_rtx (compute_mode
));
3651 quotient
= gen_reg_rtx (compute_mode
);
3655 quotient
= (GET_CODE (target
) == REG
3656 ? target
: gen_reg_rtx (compute_mode
));
3657 remainder
= gen_reg_rtx (compute_mode
);
3660 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
3663 /* This could be computed with a branch-less sequence.
3664 Save that for later. */
3665 rtx label
= gen_label_rtx ();
3666 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3667 compute_mode
, label
);
3668 expand_inc (quotient
, const1_rtx
);
3669 expand_dec (remainder
, op1
);
3671 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3674 /* No luck with division elimination or divmod. Have to do it
3675 by conditionally adjusting op0 *and* the result. */
3678 rtx adjusted_op0
, tem
;
3680 quotient
= gen_reg_rtx (compute_mode
);
3681 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3682 label1
= gen_label_rtx ();
3683 label2
= gen_label_rtx ();
3684 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
3685 compute_mode
, label1
);
3686 emit_move_insn (quotient
, const0_rtx
);
3687 emit_jump_insn (gen_jump (label2
));
3689 emit_label (label1
);
3690 expand_dec (adjusted_op0
, const1_rtx
);
3691 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
3692 quotient
, 1, OPTAB_LIB_WIDEN
);
3693 if (tem
!= quotient
)
3694 emit_move_insn (quotient
, tem
);
3695 expand_inc (quotient
, const1_rtx
);
3696 emit_label (label2
);
3701 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3702 && INTVAL (op1
) >= 0)
3704 /* This is extremely similar to the code for the unsigned case
3705 above. For 2.7 we should merge these variants, but for
3706 2.6.1 I don't want to touch the code for unsigned since that
3707 get used in C. The signed case will only be used by other
3711 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3712 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3713 build_int_2 (floor_log2 (d
), 0),
3715 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3717 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3718 t3
= gen_reg_rtx (compute_mode
);
3719 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3720 compute_mode
, 1, 1);
3724 lab
= gen_label_rtx ();
3725 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3726 expand_inc (t1
, const1_rtx
);
3731 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3737 /* Try using an instruction that produces both the quotient and
3738 remainder, using truncation. We can easily compensate the
3739 quotient or remainder to get ceiling rounding, once we have the
3740 remainder. Notice that we compute also the final remainder
3741 value here, and return the result right away. */
3742 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3743 target
= gen_reg_rtx (compute_mode
);
3746 remainder
= (GET_CODE (target
) == REG
3747 ? target
: gen_reg_rtx (compute_mode
));
3748 quotient
= gen_reg_rtx (compute_mode
);
3752 quotient
= (GET_CODE (target
) == REG
3753 ? target
: gen_reg_rtx (compute_mode
));
3754 remainder
= gen_reg_rtx (compute_mode
);
3757 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
3760 /* This could be computed with a branch-less sequence.
3761 Save that for later. */
3763 rtx label
= gen_label_rtx ();
3764 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3765 compute_mode
, label
);
3766 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3767 NULL_RTX
, 0, OPTAB_WIDEN
);
3768 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
3769 expand_inc (quotient
, const1_rtx
);
3770 expand_dec (remainder
, op1
);
3772 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3775 /* No luck with division elimination or divmod. Have to do it
3776 by conditionally adjusting op0 *and* the result. */
3778 rtx label1
, label2
, label3
, label4
, label5
;
3782 quotient
= gen_reg_rtx (compute_mode
);
3783 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3784 label1
= gen_label_rtx ();
3785 label2
= gen_label_rtx ();
3786 label3
= gen_label_rtx ();
3787 label4
= gen_label_rtx ();
3788 label5
= gen_label_rtx ();
3789 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3790 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
3791 compute_mode
, label1
);
3792 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3793 quotient
, 0, OPTAB_LIB_WIDEN
);
3794 if (tem
!= quotient
)
3795 emit_move_insn (quotient
, tem
);
3796 emit_jump_insn (gen_jump (label5
));
3798 emit_label (label1
);
3799 expand_dec (adjusted_op0
, const1_rtx
);
3800 emit_jump_insn (gen_jump (label4
));
3802 emit_label (label2
);
3803 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
3804 compute_mode
, label3
);
3805 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3806 quotient
, 0, OPTAB_LIB_WIDEN
);
3807 if (tem
!= quotient
)
3808 emit_move_insn (quotient
, tem
);
3809 emit_jump_insn (gen_jump (label5
));
3811 emit_label (label3
);
3812 expand_inc (adjusted_op0
, const1_rtx
);
3813 emit_label (label4
);
3814 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3815 quotient
, 0, OPTAB_LIB_WIDEN
);
3816 if (tem
!= quotient
)
3817 emit_move_insn (quotient
, tem
);
3818 expand_inc (quotient
, const1_rtx
);
3819 emit_label (label5
);
3824 case EXACT_DIV_EXPR
:
3825 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3827 HOST_WIDE_INT d
= INTVAL (op1
);
3828 unsigned HOST_WIDE_INT ml
;
3832 pre_shift
= floor_log2 (d
& -d
);
3833 ml
= invert_mod2n (d
>> pre_shift
, size
);
3834 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3835 build_int_2 (pre_shift
, 0), NULL_RTX
, unsignedp
);
3836 quotient
= expand_mult (compute_mode
, t1
, GEN_INT (ml
), NULL_RTX
,
3839 insn
= get_last_insn ();
3840 set_unique_reg_note (insn
,
3842 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
3848 case ROUND_DIV_EXPR
:
3849 case ROUND_MOD_EXPR
:
3854 label
= gen_label_rtx ();
3855 quotient
= gen_reg_rtx (compute_mode
);
3856 remainder
= gen_reg_rtx (compute_mode
);
3857 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
3860 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
3861 quotient
, 1, OPTAB_LIB_WIDEN
);
3862 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
3863 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3864 remainder
, 1, OPTAB_LIB_WIDEN
);
3866 tem
= plus_constant (op1
, -1);
3867 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3868 build_int_2 (1, 0), NULL_RTX
, 1);
3869 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
3870 expand_inc (quotient
, const1_rtx
);
3871 expand_dec (remainder
, op1
);
3876 rtx abs_rem
, abs_op1
, tem
, mask
;
3878 label
= gen_label_rtx ();
3879 quotient
= gen_reg_rtx (compute_mode
);
3880 remainder
= gen_reg_rtx (compute_mode
);
3881 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
3884 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
3885 quotient
, 0, OPTAB_LIB_WIDEN
);
3886 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
3887 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3888 remainder
, 0, OPTAB_LIB_WIDEN
);
3890 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
3891 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
3892 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
3893 build_int_2 (1, 0), NULL_RTX
, 1);
3894 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
3895 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3896 NULL_RTX
, 0, OPTAB_WIDEN
);
3897 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3898 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3899 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
3900 NULL_RTX
, 0, OPTAB_WIDEN
);
3901 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3902 NULL_RTX
, 0, OPTAB_WIDEN
);
3903 expand_inc (quotient
, tem
);
3904 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
3905 NULL_RTX
, 0, OPTAB_WIDEN
);
3906 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3907 NULL_RTX
, 0, OPTAB_WIDEN
);
3908 expand_dec (remainder
, tem
);
3911 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3919 if (target
&& GET_MODE (target
) != compute_mode
)
3924 /* Try to produce the remainder without producing the quotient.
3925 If we seem to have a divmod patten that does not require widening,
3926 don't try windening here. We should really have an WIDEN argument
3927 to expand_twoval_binop, since what we'd really like to do here is
3928 1) try a mod insn in compute_mode
3929 2) try a divmod insn in compute_mode
3930 3) try a div insn in compute_mode and multiply-subtract to get
3932 4) try the same things with widening allowed. */
3934 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
3937 ((optab2
->handlers
[(int) compute_mode
].insn_code
3938 != CODE_FOR_nothing
)
3939 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3942 /* No luck there. Can we do remainder and divide at once
3943 without a library call? */
3944 remainder
= gen_reg_rtx (compute_mode
);
3945 if (! expand_twoval_binop ((unsignedp
3949 NULL_RTX
, remainder
, unsignedp
))
3954 return gen_lowpart (mode
, remainder
);
3957 /* Produce the quotient. Try a quotient insn, but not a library call.
3958 If we have a divmod in this mode, use it in preference to widening
3959 the div (for this test we assume it will not fail). Note that optab2
3960 is set to the one of the two optabs that the call below will use. */
3962 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
3963 op0
, op1
, rem_flag
? NULL_RTX
: target
,
3965 ((optab2
->handlers
[(int) compute_mode
].insn_code
3966 != CODE_FOR_nothing
)
3967 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3971 /* No luck there. Try a quotient-and-remainder insn,
3972 keeping the quotient alone. */
3973 quotient
= gen_reg_rtx (compute_mode
);
3974 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
3976 quotient
, NULL_RTX
, unsignedp
))
3980 /* Still no luck. If we are not computing the remainder,
3981 use a library call for the quotient. */
3982 quotient
= sign_expand_binop (compute_mode
,
3983 udiv_optab
, sdiv_optab
,
3985 unsignedp
, OPTAB_LIB_WIDEN
);
3992 if (target
&& GET_MODE (target
) != compute_mode
)
3996 /* No divide instruction either. Use library for remainder. */
3997 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
3999 unsignedp
, OPTAB_LIB_WIDEN
);
4002 /* We divided. Now finish doing X - Y * (X / Y). */
4003 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4004 NULL_RTX
, unsignedp
);
4005 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4006 remainder
, target
, unsignedp
,
4011 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4014 /* Return a tree node with data type TYPE, describing the value of X.
4015 Usually this is an RTL_EXPR, if there is no obvious better choice.
4016 X may be an expression, however we only support those expressions
4017 generated by loop.c. */
4026 switch (GET_CODE (x
))
4029 t
= build_int_2 (INTVAL (x
),
4030 (TREE_UNSIGNED (type
)
4031 && (GET_MODE_BITSIZE (TYPE_MODE (type
)) < HOST_BITS_PER_WIDE_INT
))
4032 || INTVAL (x
) >= 0 ? 0 : -1);
4033 TREE_TYPE (t
) = type
;
4037 if (GET_MODE (x
) == VOIDmode
)
4039 t
= build_int_2 (CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4040 TREE_TYPE (t
) = type
;
4046 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4047 t
= build_real (type
, d
);
4053 return fold (build (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4054 make_tree (type
, XEXP (x
, 1))));
4057 return fold (build (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4058 make_tree (type
, XEXP (x
, 1))));
4061 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
4064 return fold (build (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4065 make_tree (type
, XEXP (x
, 1))));
4068 return fold (build (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4069 make_tree (type
, XEXP (x
, 1))));
4072 return fold (convert (type
,
4073 build (RSHIFT_EXPR
, unsigned_type (type
),
4074 make_tree (unsigned_type (type
),
4076 make_tree (type
, XEXP (x
, 1)))));
4079 return fold (convert (type
,
4080 build (RSHIFT_EXPR
, signed_type (type
),
4081 make_tree (signed_type (type
), XEXP (x
, 0)),
4082 make_tree (type
, XEXP (x
, 1)))));
4085 if (TREE_CODE (type
) != REAL_TYPE
)
4086 t
= signed_type (type
);
4090 return fold (convert (type
,
4091 build (TRUNC_DIV_EXPR
, t
,
4092 make_tree (t
, XEXP (x
, 0)),
4093 make_tree (t
, XEXP (x
, 1)))));
4095 t
= unsigned_type (type
);
4096 return fold (convert (type
,
4097 build (TRUNC_DIV_EXPR
, t
,
4098 make_tree (t
, XEXP (x
, 0)),
4099 make_tree (t
, XEXP (x
, 1)))));
4101 t
= make_node (RTL_EXPR
);
4102 TREE_TYPE (t
) = type
;
4104 #ifdef POINTERS_EXTEND_UNSIGNED
4105 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4106 ptr_mode. So convert. */
4107 if (POINTER_TYPE_P (type
) && GET_MODE (x
) != TYPE_MODE (type
))
4108 x
= convert_memory_address (TYPE_MODE (type
), x
);
4111 RTL_EXPR_RTL (t
) = x
;
4112 /* There are no insns to be output
4113 when this rtl_expr is used. */
4114 RTL_EXPR_SEQUENCE (t
) = 0;
4119 /* Return an rtx representing the value of X * MULT + ADD.
4120 TARGET is a suggestion for where to store the result (an rtx).
4121 MODE is the machine mode for the computation.
4122 X and MULT must have mode MODE. ADD may have a different mode.
4123 So can X (defaults to same as MODE).
4124 UNSIGNEDP is non-zero to do unsigned multiplication.
4125 This may emit insns. */
4128 expand_mult_add (x
, target
, mult
, add
, mode
, unsignedp
)
4129 rtx x
, target
, mult
, add
;
4130 enum machine_mode mode
;
4133 tree type
= type_for_mode (mode
, unsignedp
);
4134 tree add_type
= (GET_MODE (add
) == VOIDmode
4135 ? type
: type_for_mode (GET_MODE (add
), unsignedp
));
4136 tree result
= fold (build (PLUS_EXPR
, type
,
4137 fold (build (MULT_EXPR
, type
,
4138 make_tree (type
, x
),
4139 make_tree (type
, mult
))),
4140 make_tree (add_type
, add
)));
4142 return expand_expr (result
, target
, VOIDmode
, 0);
4145 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4146 and returning TARGET.
4148 If TARGET is 0, a pseudo-register or constant is returned. */
4151 expand_and (op0
, op1
, target
)
4152 rtx op0
, op1
, target
;
4154 enum machine_mode mode
= VOIDmode
;
4157 if (GET_MODE (op0
) != VOIDmode
)
4158 mode
= GET_MODE (op0
);
4159 else if (GET_MODE (op1
) != VOIDmode
)
4160 mode
= GET_MODE (op1
);
4162 if (mode
!= VOIDmode
)
4163 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
4164 else if (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) == CONST_INT
)
4165 tem
= GEN_INT (INTVAL (op0
) & INTVAL (op1
));
4171 else if (tem
!= target
)
4172 emit_move_insn (target
, tem
);
4176 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4177 and storing in TARGET. Normally return TARGET.
4178 Return 0 if that cannot be done.
4180 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4181 it is VOIDmode, they cannot both be CONST_INT.
4183 UNSIGNEDP is for the case where we have to widen the operands
4184 to perform the operation. It says to use zero-extension.
4186 NORMALIZEP is 1 if we should convert the result to be either zero
4187 or one. Normalize is -1 if we should convert the result to be
4188 either zero or -1. If NORMALIZEP is zero, the result will be left
4189 "raw" out of the scc insn. */
4192 emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4196 enum machine_mode mode
;
4201 enum insn_code icode
;
4202 enum machine_mode compare_mode
;
4203 enum machine_mode target_mode
= GET_MODE (target
);
4205 rtx last
= get_last_insn ();
4206 rtx pattern
, comparison
;
4209 code
= unsigned_condition (code
);
4211 /* If one operand is constant, make it the second one. Only do this
4212 if the other operand is not constant as well. */
4214 if ((CONSTANT_P (op0
) && ! CONSTANT_P (op1
))
4215 || (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) != CONST_INT
))
4220 code
= swap_condition (code
);
4223 if (mode
== VOIDmode
)
4224 mode
= GET_MODE (op0
);
4226 /* For some comparisons with 1 and -1, we can convert this to
4227 comparisons with zero. This will often produce more opportunities for
4228 store-flag insns. */
4233 if (op1
== const1_rtx
)
4234 op1
= const0_rtx
, code
= LE
;
4237 if (op1
== constm1_rtx
)
4238 op1
= const0_rtx
, code
= LT
;
4241 if (op1
== const1_rtx
)
4242 op1
= const0_rtx
, code
= GT
;
4245 if (op1
== constm1_rtx
)
4246 op1
= const0_rtx
, code
= GE
;
4249 if (op1
== const1_rtx
)
4250 op1
= const0_rtx
, code
= NE
;
4253 if (op1
== const1_rtx
)
4254 op1
= const0_rtx
, code
= EQ
;
4260 /* If we are comparing a double-word integer with zero, we can convert
4261 the comparison into one involving a single word. */
4262 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
4263 && GET_MODE_CLASS (mode
) == MODE_INT
4264 && op1
== const0_rtx
)
4266 if (code
== EQ
|| code
== NE
)
4268 /* Do a logical OR of the two words and compare the result. */
4269 rtx op0h
= gen_highpart (word_mode
, op0
);
4270 rtx op0l
= gen_lowpart (word_mode
, op0
);
4271 rtx op0both
= expand_binop (word_mode
, ior_optab
, op0h
, op0l
,
4272 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
4274 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
4275 unsignedp
, normalizep
);
4277 else if (code
== LT
|| code
== GE
)
4278 /* If testing the sign bit, can just test on high word. */
4279 return emit_store_flag (target
, code
, gen_highpart (word_mode
, op0
),
4280 op1
, word_mode
, unsignedp
, normalizep
);
4283 /* From now on, we won't change CODE, so set ICODE now. */
4284 icode
= setcc_gen_code
[(int) code
];
4286 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4287 complement of A (for GE) and shifting the sign bit to the low bit. */
4288 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
4289 && GET_MODE_CLASS (mode
) == MODE_INT
4290 && (normalizep
|| STORE_FLAG_VALUE
== 1
4291 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4292 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4293 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
4297 /* If the result is to be wider than OP0, it is best to convert it
4298 first. If it is to be narrower, it is *incorrect* to convert it
4300 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
4302 op0
= protect_from_queue (op0
, 0);
4303 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4307 if (target_mode
!= mode
)
4311 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
4312 ((STORE_FLAG_VALUE
== 1 || normalizep
)
4313 ? 0 : subtarget
), 0);
4315 if (STORE_FLAG_VALUE
== 1 || normalizep
)
4316 /* If we are supposed to produce a 0/1 value, we want to do
4317 a logical shift from the sign bit to the low-order bit; for
4318 a -1/0 value, we do an arithmetic shift. */
4319 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4320 size_int (GET_MODE_BITSIZE (mode
) - 1),
4321 subtarget
, normalizep
!= -1);
4323 if (mode
!= target_mode
)
4324 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4329 if (icode
!= CODE_FOR_nothing
)
4331 insn_operand_predicate_fn pred
;
4333 /* We think we may be able to do this with a scc insn. Emit the
4334 comparison and then the scc insn.
4336 compare_from_rtx may call emit_queue, which would be deleted below
4337 if the scc insn fails. So call it ourselves before setting LAST.
4338 Likewise for do_pending_stack_adjust. */
4341 do_pending_stack_adjust ();
4342 last
= get_last_insn ();
4345 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
, 0);
4346 if (GET_CODE (comparison
) == CONST_INT
)
4347 return (comparison
== const0_rtx
? const0_rtx
4348 : normalizep
== 1 ? const1_rtx
4349 : normalizep
== -1 ? constm1_rtx
4352 /* If the code of COMPARISON doesn't match CODE, something is
4353 wrong; we can no longer be sure that we have the operation.
4354 We could handle this case, but it should not happen. */
4356 if (GET_CODE (comparison
) != code
)
4359 /* Get a reference to the target in the proper mode for this insn. */
4360 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
4362 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
4363 if (preserve_subexpressions_p ()
4364 || ! (*pred
) (subtarget
, compare_mode
))
4365 subtarget
= gen_reg_rtx (compare_mode
);
4367 pattern
= GEN_FCN (icode
) (subtarget
);
4370 emit_insn (pattern
);
4372 /* If we are converting to a wider mode, first convert to
4373 TARGET_MODE, then normalize. This produces better combining
4374 opportunities on machines that have a SIGN_EXTRACT when we are
4375 testing a single bit. This mostly benefits the 68k.
4377 If STORE_FLAG_VALUE does not have the sign bit set when
4378 interpreted in COMPARE_MODE, we can do this conversion as
4379 unsigned, which is usually more efficient. */
4380 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
4382 convert_move (target
, subtarget
,
4383 (GET_MODE_BITSIZE (compare_mode
)
4384 <= HOST_BITS_PER_WIDE_INT
)
4385 && 0 == (STORE_FLAG_VALUE
4386 & ((HOST_WIDE_INT
) 1
4387 << (GET_MODE_BITSIZE (compare_mode
) -1))));
4389 compare_mode
= target_mode
;
4394 /* If we want to keep subexpressions around, don't reuse our
4397 if (preserve_subexpressions_p ())
4400 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4401 we don't have to do anything. */
4402 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
4404 /* STORE_FLAG_VALUE might be the most negative number, so write
4405 the comparison this way to avoid a compiler-time warning. */
4406 else if (- normalizep
== STORE_FLAG_VALUE
)
4407 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
4409 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4410 makes it hard to use a value of just the sign bit due to
4411 ANSI integer constant typing rules. */
4412 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
4413 && (STORE_FLAG_VALUE
4414 & ((HOST_WIDE_INT
) 1
4415 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
4416 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
4417 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
4418 subtarget
, normalizep
== 1);
4419 else if (STORE_FLAG_VALUE
& 1)
4421 op0
= expand_and (op0
, const1_rtx
, subtarget
);
4422 if (normalizep
== -1)
4423 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
4428 /* If we were converting to a smaller mode, do the
4430 if (target_mode
!= compare_mode
)
4432 convert_move (target
, op0
, 0);
4440 delete_insns_since (last
);
4442 /* If expensive optimizations, use different pseudo registers for each
4443 insn, instead of reusing the same pseudo. This leads to better CSE,
4444 but slows down the compiler, since there are more pseudos */
4445 subtarget
= (!flag_expensive_optimizations
4446 && (target_mode
== mode
)) ? target
: NULL_RTX
;
4448 /* If we reached here, we can't do this with a scc insn. However, there
4449 are some comparisons that can be done directly. For example, if
4450 this is an equality comparison of integers, we can try to exclusive-or
4451 (or subtract) the two operands and use a recursive call to try the
4452 comparison with zero. Don't do any of these cases if branches are
4456 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
4457 && op1
!= const0_rtx
)
4459 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
4463 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
4466 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
4467 mode
, unsignedp
, normalizep
);
4469 delete_insns_since (last
);
4473 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4474 the constant zero. Reject all other comparisons at this point. Only
4475 do LE and GT if branches are expensive since they are expensive on
4476 2-operand machines. */
4478 if (BRANCH_COST
== 0
4479 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
4480 || (code
!= EQ
&& code
!= NE
4481 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
4484 /* See what we need to return. We can only return a 1, -1, or the
4487 if (normalizep
== 0)
4489 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4490 normalizep
= STORE_FLAG_VALUE
;
4492 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4493 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4494 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
4500 /* Try to put the result of the comparison in the sign bit. Assume we can't
4501 do the necessary operation below. */
4505 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4506 the sign bit set. */
4510 /* This is destructive, so SUBTARGET can't be OP0. */
4511 if (rtx_equal_p (subtarget
, op0
))
4514 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
4517 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
4521 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4522 number of bits in the mode of OP0, minus one. */
4526 if (rtx_equal_p (subtarget
, op0
))
4529 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4530 size_int (GET_MODE_BITSIZE (mode
) - 1),
4532 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
4536 if (code
== EQ
|| code
== NE
)
4538 /* For EQ or NE, one way to do the comparison is to apply an operation
4539 that converts the operand into a positive number if it is non-zero
4540 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4541 for NE we negate. This puts the result in the sign bit. Then we
4542 normalize with a shift, if needed.
4544 Two operations that can do the above actions are ABS and FFS, so try
4545 them. If that doesn't work, and MODE is smaller than a full word,
4546 we can use zero-extension to the wider mode (an unsigned conversion)
4547 as the operation. */
4549 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4550 that is compensated by the subsequent overflow when subtracting
4553 if (abs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4554 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
4555 else if (ffs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4556 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
4557 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
4559 op0
= protect_from_queue (op0
, 0);
4560 tem
= convert_modes (word_mode
, mode
, op0
, 1);
4567 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
4570 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
4573 /* If we couldn't do it that way, for NE we can "or" the two's complement
4574 of the value with itself. For EQ, we take the one's complement of
4575 that "or", which is an extra insn, so we only handle EQ if branches
4578 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
4580 if (rtx_equal_p (subtarget
, op0
))
4583 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
4584 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
4587 if (tem
&& code
== EQ
)
4588 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
4592 if (tem
&& normalizep
)
4593 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
4594 size_int (GET_MODE_BITSIZE (mode
) - 1),
4595 subtarget
, normalizep
== 1);
4599 if (GET_MODE (tem
) != target_mode
)
4601 convert_move (target
, tem
, 0);
4604 else if (!subtarget
)
4606 emit_move_insn (target
, tem
);
4611 delete_insns_since (last
);
4616 /* Like emit_store_flag, but always succeeds. */
4619 emit_store_flag_force (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4623 enum machine_mode mode
;
4629 /* First see if emit_store_flag can do the job. */
4630 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
4634 if (normalizep
== 0)
4637 /* If this failed, we have to do this with set/compare/jump/set code. */
4639 if (GET_CODE (target
) != REG
4640 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
4641 target
= gen_reg_rtx (GET_MODE (target
));
4643 emit_move_insn (target
, const1_rtx
);
4644 label
= gen_label_rtx ();
4645 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
, 0,
4648 emit_move_insn (target
, const0_rtx
);
4654 /* Perform possibly multi-word comparison and conditional jump to LABEL
4655 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4657 The algorithm is based on the code in expr.c:do_jump.
4659 Note that this does not perform a general comparison. Only variants
4660 generated within expmed.c are correctly handled, others abort (but could
4661 be handled if needed). */
4664 do_cmp_and_jump (arg1
, arg2
, op
, mode
, label
)
4665 rtx arg1
, arg2
, label
;
4667 enum machine_mode mode
;
4669 /* If this mode is an integer too wide to compare properly,
4670 compare word by word. Rely on cse to optimize constant cases. */
4672 if (GET_MODE_CLASS (mode
) == MODE_INT
4673 && ! can_compare_p (op
, mode
, ccp_jump
))
4675 rtx label2
= gen_label_rtx ();
4680 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
4684 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
4688 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
4692 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
4696 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
4699 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4700 that's the only equality operations we do */
4702 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4704 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
4708 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4710 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
4717 emit_label (label2
);
4721 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, 0, label
);