gcc/testsuite/gcc.target/aarch64/vneg_s.c

   1 /* Test vneg works correctly.  */
   2 /* { dg-do run } */
   3 /* { dg-options "-std=gnu99 -O3 -Wno-div-by-zero --save-temps" } */
   4
   5 #include <arm_neon.h>
   6 #include <limits.h>
   7
   8 /* Used to force a variable to a SIMD register.  */
   9 #define force_simd(V1)   asm volatile ("mov %d0, %1.d[0]"       \
  10            : "=w"(V1)                                           \
  11            : "w"(V1)                                            \
  12            : /* No clobbers */);
  13 #define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
  14
  15 #define TEST0 0
  16 #define TEST1 1
  17 #define TEST2 -1
  18 #define TEST3 10
  19 #define TEST4 -10
  20 #define TEST5 0
  21
  22 #define ANSW0 0
  23 #define ANSW1 -1
  24 #define ANSW2 1
  25 #define ANSW3 -10
  26 #define ANSW4 10
  27 #define ANSW5 0
  28
  29 extern void abort (void);
  30
  31 #define CONCAT(a, b) a##b
  32 #define CONCAT1(a, b) CONCAT (a, b)
  33 #define REG_INFEX64 _
  34 #define REG_INFEX128 q_
  35 #define REG_INFEX(reg_len) REG_INFEX##reg_len
  36 #define POSTFIX(reg_len, data_len) \
  37   CONCAT1 (REG_INFEX (reg_len), s##data_len)
  38 #define DATA_TYPE_32 float
  39 #define DATA_TYPE_64 double
  40 #define DATA_TYPE(data_len) DATA_TYPE_##data_len
  41 #define INDEX64_8 [i]
  42 #define INDEX64_16 [i]
  43 #define INDEX64_32 [i]
  44 #define INDEX64_64
  45 #define INDEX128_8 [i]
  46 #define INDEX128_16 [i]
  47 #define INDEX128_32 [i]
  48 #define INDEX128_64 [i]
  49
  50 #define FORCE_SIMD_INST64_8(data)
  51 #define FORCE_SIMD_INST64_16(data)
  52 #define FORCE_SIMD_INST64_32(data)
  53 #define FORCE_SIMD_INST64_64(data) force_simd (data)
  54 #define FORCE_SIMD_INST128_8(data)
  55 #define FORCE_SIMD_INST128_16(data)
  56 #define FORCE_SIMD_INST128_32(data)
  57 #define FORCE_SIMD_INST128_64(data)
  58
  59 #define INDEX(reg_len, data_len) \
  60   CONCAT1 (INDEX, reg_len##_##data_len)
  61 #define FORCE_SIMD_INST(reg_len, data_len, data) \
  62   CONCAT1 (FORCE_SIMD_INST, reg_len##_##data_len) (data)
  63 #define LOAD_INST(reg_len, data_len) \
  64   CONCAT1 (vld1, POSTFIX (reg_len, data_len))
  65 #define NEG_INST(reg_len, data_len) \
  66   CONCAT1 (vneg, POSTFIX (reg_len, data_len))
  67
  68 #define RUN_TEST(test_set, answ_set, reg_len, data_len, n, a, b)        \
  69   {                                                                     \
  70     int i;                                                              \
  71     INHIB_OPTIMIZATION;                                                 \
  72     (a) = LOAD_INST (reg_len, data_len) (test_set);                     \
  73     (b) = LOAD_INST (reg_len, data_len) (answ_set);                     \
  74     FORCE_SIMD_INST (reg_len, data_len, a)                              \
  75     a = NEG_INST (reg_len, data_len) (a);                               \
  76     FORCE_SIMD_INST (reg_len, data_len, a)                              \
  77     for (i = 0; i < n; i++)                                             \
  78       {                                                                 \
  79         INHIB_OPTIMIZATION;                                             \
  80         if (a INDEX (reg_len, data_len)                                 \
  81             != b INDEX (reg_len, data_len))                             \
  82           return 1;                                                     \
  83       }                                                                 \
  84   }
  85
  86 int
  87 test_vneg_s8 ()
  88 {
  89   int8x8_t a;
  90   int8x8_t b;
  91
  92   int8_t test_set0[8] = {
  93     TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SCHAR_MAX, SCHAR_MIN
  94   };
  95   int8_t answ_set0[8] = {
  96     ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SCHAR_MIN + 1, SCHAR_MIN
  97   };
  98
  99   RUN_TEST (test_set0, answ_set0, 64, 8, 8, a, b);
 100
 101   return 0;
 102 }
 103
 104 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
 105
 106 int
 107 test_vneg_s16 ()
 108 {
 109   int16x4_t a;
 110   int16x4_t b;
 111
 112   int16_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
 113   int16_t test_set1[4] = { TEST4, TEST5, SHRT_MAX, SHRT_MIN };
 114
 115   int16_t answ_set0[4] = { ANSW0, ANSW1, ANSW2, ANSW3 };
 116   int16_t answ_set1[4] = { ANSW4, ANSW5, SHRT_MIN + 1, SHRT_MIN };
 117
 118   RUN_TEST (test_set0, answ_set0, 64, 16, 4, a, b);
 119   RUN_TEST (test_set1, answ_set1, 64, 16, 4, a, b);
 120
 121   return 0;
 122 }
 123
 124 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 2 } } */
 125
 126 int
 127 test_vneg_s32 ()
 128 {
 129   int32x2_t a;
 130   int32x2_t b;
 131
 132   int32_t test_set0[2] = { TEST0, TEST1 };
 133   int32_t test_set1[2] = { TEST2, TEST3 };
 134   int32_t test_set2[2] = { TEST4, TEST5 };
 135   int32_t test_set3[2] = { INT_MAX, INT_MIN };
 136
 137   int32_t answ_set0[2] = { ANSW0, ANSW1 };
 138   int32_t answ_set1[2] = { ANSW2, ANSW3 };
 139   int32_t answ_set2[2] = { ANSW4, ANSW5 };
 140   int32_t answ_set3[2] = { INT_MIN + 1, INT_MIN };
 141
 142   RUN_TEST (test_set0, answ_set0, 64, 32, 2, a, b);
 143   RUN_TEST (test_set1, answ_set1, 64, 32, 2, a, b);
 144   RUN_TEST (test_set2, answ_set2, 64, 32, 2, a, b);
 145   RUN_TEST (test_set3, answ_set3, 64, 32, 2, a, b);
 146
 147   return 0;
 148 }
 149
 150 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 4 } } */
 151
 152 int
 153 test_vneg_s64 ()
 154 {
 155   int64x1_t a;
 156   int64x1_t b;
 157
 158   int64_t test_set0[1] = { TEST0 };
 159   int64_t test_set1[1] = { TEST1 };
 160   int64_t test_set2[1] = { TEST2 };
 161   int64_t test_set3[1] = { TEST3 };
 162   int64_t test_set4[1] = { TEST4 };
 163   int64_t test_set5[1] = { TEST5 };
 164   int64_t test_set6[1] = { LLONG_MAX };
 165   int64_t test_set7[1] = { LLONG_MIN };
 166
 167   int64_t answ_set0[1] = { ANSW0 };
 168   int64_t answ_set1[1] = { ANSW1 };
 169   int64_t answ_set2[1] = { ANSW2 };
 170   int64_t answ_set3[1] = { ANSW3 };
 171   int64_t answ_set4[1] = { ANSW4 };
 172   int64_t answ_set5[1] = { ANSW5 };
 173   int64_t answ_set6[1] = { LLONG_MIN + 1 };
 174   int64_t answ_set7[1] = { LLONG_MIN };
 175
 176   RUN_TEST (test_set0, answ_set0, 64, 64, 1, a, b);
 177   RUN_TEST (test_set1, answ_set1, 64, 64, 1, a, b);
 178   RUN_TEST (test_set2, answ_set2, 64, 64, 1, a, b);
 179   RUN_TEST (test_set3, answ_set3, 64, 64, 1, a, b);
 180   RUN_TEST (test_set4, answ_set4, 64, 64, 1, a, b);
 181   RUN_TEST (test_set5, answ_set5, 64, 64, 1, a, b);
 182   RUN_TEST (test_set6, answ_set6, 64, 64, 1, a, b);
 183   RUN_TEST (test_set7, answ_set7, 64, 64, 1, a, b);
 184
 185   return 0;
 186 }
 187
 188 /* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 8 } } */
 189
 190 int
 191 test_vnegq_s8 ()
 192 {
 193   int8x16_t a;
 194   int8x16_t b;
 195
 196   int8_t test_set0[16] = {
 197     TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SCHAR_MAX, SCHAR_MIN,
 198     4, 8, 15, 16, 23, 42, -1, -2
 199   };
 200
 201   int8_t answ_set0[16] = {
 202     ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SCHAR_MIN + 1, SCHAR_MIN,
 203     -4, -8, -15, -16, -23, -42, 1, 2
 204   };
 205
 206   RUN_TEST (test_set0, answ_set0, 128, 8, 8, a, b);
 207
 208   return 0;
 209 }
 210
 211 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
 212
 213 int
 214 test_vnegq_s16 ()
 215 {
 216   int16x8_t a;
 217   int16x8_t b;
 218
 219   int16_t test_set0[8] = {
 220     TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SHRT_MAX, SHRT_MIN
 221   };
 222   int16_t answ_set0[8] = {
 223     ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SHRT_MIN + 1, SHRT_MIN
 224   };
 225
 226   RUN_TEST (test_set0, answ_set0, 128, 16, 8, a, b);
 227
 228   return 0;
 229 }
 230
 231 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
 232
 233 int
 234 test_vnegq_s32 ()
 235 {
 236   int32x4_t a;
 237   int32x4_t b;
 238
 239   int32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
 240   int32_t test_set1[4] = { TEST4, TEST5, INT_MAX, INT_MIN };
 241
 242   int32_t answ_set0[4] = { ANSW0, ANSW1, ANSW2, ANSW3 };
 243   int32_t answ_set1[4] = { ANSW4, ANSW5, INT_MIN + 1, INT_MIN };
 244
 245   RUN_TEST (test_set0, answ_set0, 128, 32, 4, a, b);
 246   RUN_TEST (test_set1, answ_set1, 128, 32, 4, a, b);
 247
 248   return 0;
 249 }
 250
 251 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
 252
 253 int
 254 test_vnegq_s64 ()
 255 {
 256   int64x2_t a;
 257   int64x2_t b;
 258
 259   int64_t test_set0[2] = { TEST0, TEST1 };
 260   int64_t test_set1[2] = { TEST2, TEST3 };
 261   int64_t test_set2[2] = { TEST4, TEST5 };
 262   int64_t test_set3[2] = { LLONG_MAX, LLONG_MIN };
 263
 264   int64_t answ_set0[2] = { ANSW0, ANSW1 };
 265   int64_t answ_set1[2] = { ANSW2, ANSW3 };
 266   int64_t answ_set2[2] = { ANSW4, ANSW5 };
 267   int64_t answ_set3[2] = { LLONG_MIN + 1, LLONG_MIN };
 268
 269   RUN_TEST (test_set0, answ_set0, 128, 64, 2, a, b);
 270   RUN_TEST (test_set1, answ_set1, 128, 64, 2, a, b);
 271   RUN_TEST (test_set2, answ_set2, 128, 64, 2, a, b);
 272   RUN_TEST (test_set3, answ_set3, 128, 64, 2, a, b);
 273
 274   return 0;
 275 }
 276
 277 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 4 } } */
 278
 279 int
 280 main (int argc, char **argv)
 281 {
 282   if (test_vneg_s8 ())
 283     abort ();
 284
 285   if (test_vneg_s16 ())
 286     abort ();
 287
 288   if (test_vneg_s32 ())
 289     abort ();
 290
 291   if (test_vneg_s64 ())
 292     abort ();
 293
 294   if (test_vnegq_s8 ())
 295     abort ();
 296
 297   if (test_vnegq_s16 ())
 298     abort ();
 299
 300   if (test_vnegq_s32 ())
 301     abort ();
 302
 303   if (test_vnegq_s64 ())
 304     abort ();
 305
 306   return 0;
 307 }
 308
 309 /* { dg-final { cleanup-saved-temps } } */