1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
31 #include "insn-config.h"
37 static void store_fixed_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
38 unsigned HOST_WIDE_INT
,
39 unsigned HOST_WIDE_INT
, rtx
,
41 static void store_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
42 unsigned HOST_WIDE_INT
, rtx
,
44 static rtx extract_fixed_bit_field
PARAMS ((enum machine_mode
, rtx
,
45 unsigned HOST_WIDE_INT
,
46 unsigned HOST_WIDE_INT
,
47 unsigned HOST_WIDE_INT
,
48 rtx
, int, unsigned int));
49 static rtx mask_rtx
PARAMS ((enum machine_mode
, int,
51 static rtx lshift_value
PARAMS ((enum machine_mode
, rtx
,
53 static rtx extract_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
54 unsigned HOST_WIDE_INT
, int,
56 static void do_cmp_and_jump
PARAMS ((rtx
, rtx
, enum rtx_code
,
57 enum machine_mode
, rtx
));
59 /* Non-zero means divides or modulus operations are relatively cheap for
60 powers of two, so don't use branches; emit the operation instead.
61 Usually, this will mean that the MD file will emit non-branch
64 static int sdiv_pow2_cheap
, smod_pow2_cheap
;
66 #ifndef SLOW_UNALIGNED_ACCESS
67 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
70 /* For compilers that support multiple targets with different word sizes,
71 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
72 is the H8/300(H) compiler. */
74 #ifndef MAX_BITS_PER_WORD
75 #define MAX_BITS_PER_WORD BITS_PER_WORD
78 /* Cost of various pieces of RTL. Note that some of these are indexed by
79 shift count and some by mode. */
80 static int add_cost
, negate_cost
, zero_cost
;
81 static int shift_cost
[MAX_BITS_PER_WORD
];
82 static int shiftadd_cost
[MAX_BITS_PER_WORD
];
83 static int shiftsub_cost
[MAX_BITS_PER_WORD
];
84 static int mul_cost
[NUM_MACHINE_MODES
];
85 static int div_cost
[NUM_MACHINE_MODES
];
86 static int mul_widen_cost
[NUM_MACHINE_MODES
];
87 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
92 /* This is "some random pseudo register" for purposes of calling recog
93 to see what insns exist. */
94 rtx reg
= gen_rtx_REG (word_mode
, 10000);
95 rtx shift_insn
, shiftadd_insn
, shiftsub_insn
;
98 enum machine_mode mode
, wider_mode
;
102 reg
= gen_rtx_REG (word_mode
, 10000);
104 zero_cost
= rtx_cost (const0_rtx
, 0);
105 add_cost
= rtx_cost (gen_rtx_PLUS (word_mode
, reg
, reg
), SET
);
107 shift_insn
= emit_insn (gen_rtx_SET (VOIDmode
, reg
,
108 gen_rtx_ASHIFT (word_mode
, reg
,
112 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
113 gen_rtx_PLUS (word_mode
,
114 gen_rtx_MULT (word_mode
,
119 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
120 gen_rtx_MINUS (word_mode
,
121 gen_rtx_MULT (word_mode
,
128 shiftadd_cost
[0] = shiftsub_cost
[0] = add_cost
;
130 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
132 shift_cost
[m
] = shiftadd_cost
[m
] = shiftsub_cost
[m
] = 32000;
134 XEXP (SET_SRC (PATTERN (shift_insn
)), 1) = GEN_INT (m
);
135 if (recog (PATTERN (shift_insn
), shift_insn
, &dummy
) >= 0)
136 shift_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shift_insn
)), SET
);
138 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn
)), 0), 1)
139 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
140 if (recog (PATTERN (shiftadd_insn
), shiftadd_insn
, &dummy
) >= 0)
141 shiftadd_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn
)), SET
);
143 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn
)), 0), 1)
144 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
145 if (recog (PATTERN (shiftsub_insn
), shiftsub_insn
, &dummy
) >= 0)
146 shiftsub_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn
)), SET
);
149 negate_cost
= rtx_cost (gen_rtx_NEG (word_mode
, reg
), SET
);
152 = (rtx_cost (gen_rtx_DIV (word_mode
, reg
, GEN_INT (32)), SET
)
155 = (rtx_cost (gen_rtx_MOD (word_mode
, reg
, GEN_INT (32)), SET
)
158 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
160 mode
= GET_MODE_WIDER_MODE (mode
))
162 reg
= gen_rtx_REG (mode
, 10000);
163 div_cost
[(int) mode
] = rtx_cost (gen_rtx_UDIV (mode
, reg
, reg
), SET
);
164 mul_cost
[(int) mode
] = rtx_cost (gen_rtx_MULT (mode
, reg
, reg
), SET
);
165 wider_mode
= GET_MODE_WIDER_MODE (mode
);
166 if (wider_mode
!= VOIDmode
)
168 mul_widen_cost
[(int) wider_mode
]
169 = rtx_cost (gen_rtx_MULT (wider_mode
,
170 gen_rtx_ZERO_EXTEND (wider_mode
, reg
),
171 gen_rtx_ZERO_EXTEND (wider_mode
, reg
)),
173 mul_highpart_cost
[(int) mode
]
174 = rtx_cost (gen_rtx_TRUNCATE
176 gen_rtx_LSHIFTRT (wider_mode
,
177 gen_rtx_MULT (wider_mode
,
182 GEN_INT (GET_MODE_BITSIZE (mode
)))),
190 /* Return an rtx representing minus the value of X.
191 MODE is the intended mode of the result,
192 useful if X is a CONST_INT. */
196 enum machine_mode mode
;
199 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
202 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
207 /* Generate code to store value from rtx VALUE
208 into a bit-field within structure STR_RTX
209 containing BITSIZE bits starting at bit BITNUM.
210 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
211 ALIGN is the alignment that STR_RTX is known to have.
212 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
214 /* ??? Note that there are two different ideas here for how
215 to determine the size to count bits within, for a register.
216 One is BITS_PER_WORD, and the other is the size of operand 3
219 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
220 else, we use the mode of operand 3. */
223 store_bit_field (str_rtx
, bitsize
, bitnum
, fieldmode
, value
, align
, total_size
)
225 unsigned HOST_WIDE_INT bitsize
;
226 unsigned HOST_WIDE_INT bitnum
;
227 enum machine_mode fieldmode
;
230 HOST_WIDE_INT total_size
;
233 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
234 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
235 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
236 register rtx op0
= str_rtx
;
238 unsigned HOST_WIDE_INT insv_bitsize
;
239 enum machine_mode op_mode
;
241 op_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
242 if (op_mode
== VOIDmode
)
244 insv_bitsize
= GET_MODE_BITSIZE (op_mode
);
247 /* It is wrong to have align==0, since every object is aligned at
248 least at a bit boundary. This usually means a bug elsewhere. */
252 /* Discount the part of the structure before the desired byte.
253 We need to know how many bytes are safe to reference after it. */
255 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
256 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
258 while (GET_CODE (op0
) == SUBREG
)
260 /* The following line once was done only if WORDS_BIG_ENDIAN,
261 but I think that is a mistake. WORDS_BIG_ENDIAN is
262 meaningful at a much higher level; when structures are copied
263 between memory and regs, the higher-numbered regs
264 always get higher addresses. */
265 offset
+= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
);
266 /* We used to adjust BITPOS here, but now we do the whole adjustment
267 right after the loop. */
268 op0
= SUBREG_REG (op0
);
271 /* If OP0 is a register, BITPOS must count within a word.
272 But as we have it, it counts within whatever size OP0 now has.
273 On a bigendian machine, these are not the same, so convert. */
275 && GET_CODE (op0
) != MEM
276 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
277 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
279 value
= protect_from_queue (value
, 0);
282 value
= force_not_mem (value
);
284 /* If the target is a register, overwriting the entire object, or storing
285 a full-word or multi-word field can be done with just a SUBREG.
287 If the target is memory, storing any naturally aligned field can be
288 done with a simple store. For targets that support fast unaligned
289 memory, any naturally sized, unit aligned field can be done directly. */
291 if (bitsize
== GET_MODE_BITSIZE (fieldmode
)
292 && (GET_CODE (op0
) != MEM
293 ? (GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
294 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
295 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, align
)
296 || (offset
* BITS_PER_UNIT
% bitsize
== 0
297 && align
% GET_MODE_BITSIZE (fieldmode
) == 0)))
298 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0))
300 if (GET_MODE (op0
) != fieldmode
)
302 if (GET_CODE (op0
) == SUBREG
)
304 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
305 || GET_MODE_CLASS (fieldmode
) == MODE_INT
306 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
307 op0
= SUBREG_REG (op0
);
309 /* Else we've got some float mode source being extracted into
310 a different float mode destination -- this combination of
311 subregs results in Severe Tire Damage. */
314 if (GET_CODE (op0
) == REG
)
315 op0
= gen_rtx_SUBREG (fieldmode
, op0
,
316 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
317 + (offset
* UNITS_PER_WORD
));
319 op0
= adjust_address (op0
, fieldmode
, offset
);
321 emit_move_insn (op0
, value
);
325 /* Make sure we are playing with integral modes. Pun with subregs
326 if we aren't. This must come after the entire register case above,
327 since that case is valid for any mode. The following cases are only
328 valid for integral modes. */
330 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
331 if (imode
!= GET_MODE (op0
))
333 if (GET_CODE (op0
) == MEM
)
334 op0
= adjust_address (op0
, imode
, 0);
335 else if (imode
!= BLKmode
)
336 op0
= gen_lowpart (imode
, op0
);
342 /* Storing an lsb-aligned field in a register
343 can be done with a movestrict instruction. */
345 if (GET_CODE (op0
) != MEM
346 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
347 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
348 && (movstrict_optab
->handlers
[(int) fieldmode
].insn_code
349 != CODE_FOR_nothing
))
351 int icode
= movstrict_optab
->handlers
[(int) fieldmode
].insn_code
;
353 /* Get appropriate low part of the value being stored. */
354 if (GET_CODE (value
) == CONST_INT
|| GET_CODE (value
) == REG
)
355 value
= gen_lowpart (fieldmode
, value
);
356 else if (!(GET_CODE (value
) == SYMBOL_REF
357 || GET_CODE (value
) == LABEL_REF
358 || GET_CODE (value
) == CONST
))
359 value
= convert_to_mode (fieldmode
, value
, 0);
361 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
362 value
= copy_to_mode_reg (fieldmode
, value
);
364 if (GET_CODE (op0
) == SUBREG
)
366 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
367 || GET_MODE_CLASS (fieldmode
) == MODE_INT
368 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
369 op0
= SUBREG_REG (op0
);
371 /* Else we've got some float mode source being extracted into
372 a different float mode destination -- this combination of
373 subregs results in Severe Tire Damage. */
377 emit_insn (GEN_FCN (icode
)
378 (gen_rtx_SUBREG (fieldmode
, op0
,
379 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
380 + (offset
* UNITS_PER_WORD
)),
386 /* Handle fields bigger than a word. */
388 if (bitsize
> BITS_PER_WORD
)
390 /* Here we transfer the words of the field
391 in the order least significant first.
392 This is because the most significant word is the one which may
394 However, only do that if the value is not BLKmode. */
396 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
397 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
400 /* This is the mode we must force value to, so that there will be enough
401 subwords to extract. Note that fieldmode will often (always?) be
402 VOIDmode, because that is what store_field uses to indicate that this
403 is a bit field, but passing VOIDmode to operand_subword_force will
404 result in an abort. */
405 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
407 for (i
= 0; i
< nwords
; i
++)
409 /* If I is 0, use the low-order word in both field and target;
410 if I is 1, use the next to lowest word; and so on. */
411 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
412 unsigned int bit_offset
= (backwards
413 ? MAX ((int) bitsize
- ((int) i
+ 1)
416 : (int) i
* BITS_PER_WORD
);
418 store_bit_field (op0
, MIN (BITS_PER_WORD
,
419 bitsize
- i
* BITS_PER_WORD
),
420 bitnum
+ bit_offset
, word_mode
,
421 operand_subword_force (value
, wordnum
,
422 (GET_MODE (value
) == VOIDmode
424 : GET_MODE (value
))),
430 /* From here on we can assume that the field to be stored in is
431 a full-word (whatever type that is), since it is shorter than a word. */
433 /* OFFSET is the number of words or bytes (UNIT says which)
434 from STR_RTX to the first word or byte containing part of the field. */
436 if (GET_CODE (op0
) != MEM
)
439 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
441 if (GET_CODE (op0
) != REG
)
443 /* Since this is a destination (lvalue), we can't copy it to a
444 pseudo. We can trivially remove a SUBREG that does not
445 change the size of the operand. Such a SUBREG may have been
446 added above. Otherwise, abort. */
447 if (GET_CODE (op0
) == SUBREG
448 && (GET_MODE_SIZE (GET_MODE (op0
))
449 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))))
450 op0
= SUBREG_REG (op0
);
454 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
455 op0
, (offset
* UNITS_PER_WORD
));
461 op0
= protect_from_queue (op0
, 1);
464 /* If VALUE is a floating-point mode, access it as an integer of the
465 corresponding size. This can occur on a machine with 64 bit registers
466 that uses SFmode for float. This can also occur for unaligned float
468 if (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
)
470 if (GET_CODE (value
) != REG
)
471 value
= copy_to_reg (value
);
472 value
= gen_rtx_SUBREG (word_mode
, value
, 0);
475 /* Now OFFSET is nonzero only if OP0 is memory
476 and is therefore always measured in bytes. */
480 && GET_MODE (value
) != BLKmode
481 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
482 /* Ensure insv's size is wide enough for this field. */
483 && (insv_bitsize
>= bitsize
)
484 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
485 && (bitsize
+ bitpos
> insv_bitsize
)))
487 int xbitpos
= bitpos
;
490 rtx last
= get_last_insn ();
492 enum machine_mode maxmode
;
493 int save_volatile_ok
= volatile_ok
;
495 maxmode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
496 if (maxmode
== VOIDmode
)
501 /* If this machine's insv can only insert into a register, copy OP0
502 into a register and save it back later. */
503 /* This used to check flag_force_mem, but that was a serious
504 de-optimization now that flag_force_mem is enabled by -O2. */
505 if (GET_CODE (op0
) == MEM
506 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
510 enum machine_mode bestmode
;
512 /* Get the mode to use for inserting into this field. If OP0 is
513 BLKmode, get the smallest mode consistent with the alignment. If
514 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
515 mode. Otherwise, use the smallest mode containing the field. */
517 if (GET_MODE (op0
) == BLKmode
518 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
520 = get_best_mode (bitsize
, bitnum
, align
, maxmode
,
521 MEM_VOLATILE_P (op0
));
523 bestmode
= GET_MODE (op0
);
525 if (bestmode
== VOIDmode
526 || (SLOW_UNALIGNED_ACCESS (bestmode
, align
)
527 && GET_MODE_BITSIZE (bestmode
) > align
))
530 /* Adjust address to point to the containing unit of that mode. */
531 unit
= GET_MODE_BITSIZE (bestmode
);
532 /* Compute offset as multiple of this unit, counting in bytes. */
533 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
534 bitpos
= bitnum
% unit
;
535 op0
= adjust_address (op0
, bestmode
, offset
);
537 /* Fetch that unit, store the bitfield in it, then store
539 tempreg
= copy_to_reg (op0
);
540 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, value
,
542 emit_move_insn (op0
, tempreg
);
545 volatile_ok
= save_volatile_ok
;
547 /* Add OFFSET into OP0's address. */
548 if (GET_CODE (xop0
) == MEM
)
549 xop0
= adjust_address (xop0
, byte_mode
, offset
);
551 /* If xop0 is a register, we need it in MAXMODE
552 to make it acceptable to the format of insv. */
553 if (GET_CODE (xop0
) == SUBREG
)
554 /* We can't just change the mode, because this might clobber op0,
555 and we will need the original value of op0 if insv fails. */
556 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
557 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
558 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
560 /* On big-endian machines, we count bits from the most significant.
561 If the bit field insn does not, we must invert. */
563 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
564 xbitpos
= unit
- bitsize
- xbitpos
;
566 /* We have been counting XBITPOS within UNIT.
567 Count instead within the size of the register. */
568 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
569 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
571 unit
= GET_MODE_BITSIZE (maxmode
);
573 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
575 if (GET_MODE (value
) != maxmode
)
577 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
579 /* Optimization: Don't bother really extending VALUE
580 if it has all the bits we will actually use. However,
581 if we must narrow it, be sure we do it correctly. */
583 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
585 /* Avoid making subreg of a subreg, or of a mem. */
586 if (GET_CODE (value1
) != REG
)
587 value1
= copy_to_reg (value1
);
588 value1
= gen_rtx_SUBREG (maxmode
, value1
, 0);
591 value1
= gen_lowpart (maxmode
, value1
);
593 else if (GET_CODE (value
) == CONST_INT
)
594 value1
= GEN_INT (trunc_int_for_mode (INTVAL (value
), maxmode
));
595 else if (!CONSTANT_P (value
))
596 /* Parse phase is supposed to make VALUE's data type
597 match that of the component reference, which is a type
598 at least as wide as the field; so VALUE should have
599 a mode that corresponds to that type. */
603 /* If this machine's insv insists on a register,
604 get VALUE1 into a register. */
605 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
607 value1
= force_reg (maxmode
, value1
);
609 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
614 delete_insns_since (last
);
615 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, align
);
621 /* Insv is not available; store using shifts and boolean ops. */
622 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, align
);
626 /* Use shifts and boolean operations to store VALUE
627 into a bit field of width BITSIZE
628 in a memory location specified by OP0 except offset by OFFSET bytes.
629 (OFFSET must be 0 if OP0 is a register.)
630 The field starts at position BITPOS within the byte.
631 (If OP0 is a register, it may be a full word or a narrower mode,
632 but BITPOS still counts within a full word,
633 which is significant on bigendian machines.)
634 STRUCT_ALIGN is the alignment the structure is known to have.
636 Note that protect_from_queue has already been done on OP0 and VALUE. */
639 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
, struct_align
)
641 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
643 unsigned int struct_align
;
645 register enum machine_mode mode
;
646 unsigned int total_bits
= BITS_PER_WORD
;
651 if (! SLOW_UNALIGNED_ACCESS (word_mode
, struct_align
))
652 struct_align
= BIGGEST_ALIGNMENT
;
654 /* There is a case not handled here:
655 a structure with a known alignment of just a halfword
656 and a field split across two aligned halfwords within the structure.
657 Or likewise a structure with a known alignment of just a byte
658 and a field split across two bytes.
659 Such cases are not supposed to be able to occur. */
661 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
665 /* Special treatment for a bit field split across two registers. */
666 if (bitsize
+ bitpos
> BITS_PER_WORD
)
668 store_split_bit_field (op0
, bitsize
, bitpos
,
669 value
, BITS_PER_WORD
);
675 /* Get the proper mode to use for this field. We want a mode that
676 includes the entire field. If such a mode would be larger than
677 a word, we won't be doing the extraction the normal way.
678 We don't want a mode bigger than the destination. */
680 mode
= GET_MODE (op0
);
681 if (GET_MODE_BITSIZE (mode
) == 0
682 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
684 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
686 GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
));
688 if (mode
== VOIDmode
)
690 /* The only way this should occur is if the field spans word
692 store_split_bit_field (op0
,
693 bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
694 value
, struct_align
);
698 total_bits
= GET_MODE_BITSIZE (mode
);
700 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
701 be in the range 0 to total_bits-1, and put any excess bytes in
703 if (bitpos
>= total_bits
)
705 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
706 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
710 /* Get ref to an aligned byte, halfword, or word containing the field.
711 Adjust BITPOS to be position within a word,
712 and OFFSET to be the offset of that word.
713 Then alter OP0 to refer to that word. */
714 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
715 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
716 op0
= adjust_address (op0
, mode
, offset
);
719 mode
= GET_MODE (op0
);
721 /* Now MODE is either some integral mode for a MEM as OP0,
722 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
723 The bit field is contained entirely within OP0.
724 BITPOS is the starting bit number within OP0.
725 (OP0's mode may actually be narrower than MODE.) */
727 if (BYTES_BIG_ENDIAN
)
728 /* BITPOS is the distance between our msb
729 and that of the containing datum.
730 Convert it to the distance from the lsb. */
731 bitpos
= total_bits
- bitsize
- bitpos
;
733 /* Now BITPOS is always the distance between our lsb
736 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
737 we must first convert its mode to MODE. */
739 if (GET_CODE (value
) == CONST_INT
)
741 register HOST_WIDE_INT v
= INTVAL (value
);
743 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
744 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
748 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
749 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
750 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
753 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
757 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
758 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
760 if (GET_MODE (value
) != mode
)
762 if ((GET_CODE (value
) == REG
|| GET_CODE (value
) == SUBREG
)
763 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
764 value
= gen_lowpart (mode
, value
);
766 value
= convert_to_mode (mode
, value
, 1);
770 value
= expand_binop (mode
, and_optab
, value
,
771 mask_rtx (mode
, 0, bitsize
, 0),
772 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
774 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
775 build_int_2 (bitpos
, 0), NULL_RTX
, 1);
778 /* Now clear the chosen bits in OP0,
779 except that if VALUE is -1 we need not bother. */
781 subtarget
= (GET_CODE (op0
) == REG
|| ! flag_force_mem
) ? op0
: 0;
785 temp
= expand_binop (mode
, and_optab
, op0
,
786 mask_rtx (mode
, bitpos
, bitsize
, 1),
787 subtarget
, 1, OPTAB_LIB_WIDEN
);
793 /* Now logical-or VALUE into OP0, unless it is zero. */
796 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
797 subtarget
, 1, OPTAB_LIB_WIDEN
);
799 emit_move_insn (op0
, temp
);
802 /* Store a bit field that is split across multiple accessible memory objects.
804 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
805 BITSIZE is the field width; BITPOS the position of its first bit
807 VALUE is the value to store.
808 ALIGN is the known alignment of OP0.
809 This is also the size of the memory objects to be used.
811 This does not yet handle fields wider than BITS_PER_WORD. */
814 store_split_bit_field (op0
, bitsize
, bitpos
, value
, align
)
816 unsigned HOST_WIDE_INT bitsize
, bitpos
;
821 unsigned int bitsdone
= 0;
823 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
825 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
826 unit
= BITS_PER_WORD
;
828 unit
= MIN (align
, BITS_PER_WORD
);
830 /* If VALUE is a constant other than a CONST_INT, get it into a register in
831 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
832 that VALUE might be a floating-point constant. */
833 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
835 rtx word
= gen_lowpart_common (word_mode
, value
);
837 if (word
&& (value
!= word
))
840 value
= gen_lowpart_common (word_mode
,
841 force_reg (GET_MODE (value
) != VOIDmode
843 : word_mode
, value
));
845 else if (GET_CODE (value
) == ADDRESSOF
)
846 value
= copy_to_reg (value
);
848 while (bitsdone
< bitsize
)
850 unsigned HOST_WIDE_INT thissize
;
852 unsigned HOST_WIDE_INT thispos
;
853 unsigned HOST_WIDE_INT offset
;
855 offset
= (bitpos
+ bitsdone
) / unit
;
856 thispos
= (bitpos
+ bitsdone
) % unit
;
858 /* THISSIZE must not overrun a word boundary. Otherwise,
859 store_fixed_bit_field will call us again, and we will mutually
861 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
862 thissize
= MIN (thissize
, unit
- thispos
);
864 if (BYTES_BIG_ENDIAN
)
868 /* We must do an endian conversion exactly the same way as it is
869 done in extract_bit_field, so that the two calls to
870 extract_fixed_bit_field will have comparable arguments. */
871 if (GET_CODE (value
) != MEM
|| GET_MODE (value
) == BLKmode
)
872 total_bits
= BITS_PER_WORD
;
874 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
876 /* Fetch successively less significant portions. */
877 if (GET_CODE (value
) == CONST_INT
)
878 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
879 >> (bitsize
- bitsdone
- thissize
))
880 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
882 /* The args are chosen so that the last part includes the
883 lsb. Give extract_bit_field the value it needs (with
884 endianness compensation) to fetch the piece we want.
886 ??? We have no idea what the alignment of VALUE is, so
887 we have to use a guess. */
889 = extract_fixed_bit_field
890 (word_mode
, value
, 0, thissize
,
891 total_bits
- bitsize
+ bitsdone
, NULL_RTX
, 1,
892 GET_MODE (value
) == VOIDmode
894 : (GET_MODE (value
) == BLKmode
895 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value
))));
899 /* Fetch successively more significant portions. */
900 if (GET_CODE (value
) == CONST_INT
)
901 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
903 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
906 = extract_fixed_bit_field
907 (word_mode
, value
, 0, thissize
, bitsdone
, NULL_RTX
, 1,
908 GET_MODE (value
) == VOIDmode
910 : (GET_MODE (value
) == BLKmode
911 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value
))));
914 /* If OP0 is a register, then handle OFFSET here.
916 When handling multiword bitfields, extract_bit_field may pass
917 down a word_mode SUBREG of a larger REG for a bitfield that actually
918 crosses a word boundary. Thus, for a SUBREG, we must find
919 the current word starting from the base register. */
920 if (GET_CODE (op0
) == SUBREG
)
922 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
923 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
924 GET_MODE (SUBREG_REG (op0
)));
927 else if (GET_CODE (op0
) == REG
)
929 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
935 /* OFFSET is in UNITs, and UNIT is in bits.
936 store_fixed_bit_field wants offset in bytes. */
937 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
,
938 thissize
, thispos
, part
, align
);
939 bitsdone
+= thissize
;
943 /* Generate code to extract a byte-field from STR_RTX
944 containing BITSIZE bits, starting at BITNUM,
945 and put it in TARGET if possible (if TARGET is nonzero).
946 Regardless of TARGET, we return the rtx for where the value is placed.
949 STR_RTX is the structure containing the byte (a REG or MEM).
950 UNSIGNEDP is nonzero if this is an unsigned bit field.
951 MODE is the natural mode of the field value once extracted.
952 TMODE is the mode the caller would like the value to have;
953 but the value may be returned with type MODE instead.
955 ALIGN is the alignment that STR_RTX is known to have.
956 TOTAL_SIZE is the size in bytes of the containing structure,
959 If a TARGET is specified and we can store in it at no extra cost,
960 we do so, and return TARGET.
961 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
962 if they are equally easy. */
965 extract_bit_field (str_rtx
, bitsize
, bitnum
, unsignedp
,
966 target
, mode
, tmode
, align
, total_size
)
968 unsigned HOST_WIDE_INT bitsize
;
969 unsigned HOST_WIDE_INT bitnum
;
972 enum machine_mode mode
, tmode
;
974 HOST_WIDE_INT total_size
;
977 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
978 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
979 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
980 register rtx op0
= str_rtx
;
981 rtx spec_target
= target
;
982 rtx spec_target_subreg
= 0;
983 enum machine_mode int_mode
;
985 unsigned HOST_WIDE_INT extv_bitsize
;
986 enum machine_mode extv_mode
;
989 unsigned HOST_WIDE_INT extzv_bitsize
;
990 enum machine_mode extzv_mode
;
994 extv_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
995 if (extv_mode
== VOIDmode
)
996 extv_mode
= word_mode
;
997 extv_bitsize
= GET_MODE_BITSIZE (extv_mode
);
1001 extzv_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
1002 if (extzv_mode
== VOIDmode
)
1003 extzv_mode
= word_mode
;
1004 extzv_bitsize
= GET_MODE_BITSIZE (extzv_mode
);
1007 /* Discount the part of the structure before the desired byte.
1008 We need to know how many bytes are safe to reference after it. */
1009 if (total_size
>= 0)
1010 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
1011 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
1013 if (tmode
== VOIDmode
)
1015 while (GET_CODE (op0
) == SUBREG
)
1017 int outer_size
= GET_MODE_BITSIZE (GET_MODE (op0
));
1018 int inner_size
= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)));
1020 offset
+= SUBREG_BYTE (op0
) / UNITS_PER_WORD
;
1022 inner_size
= MIN (inner_size
, BITS_PER_WORD
);
1024 if (BYTES_BIG_ENDIAN
&& (outer_size
< inner_size
))
1026 bitpos
+= inner_size
- outer_size
;
1029 offset
+= (bitpos
/ unit
);
1034 op0
= SUBREG_REG (op0
);
1037 if (GET_CODE (op0
) == REG
1038 && mode
== GET_MODE (op0
)
1040 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1042 /* We're trying to extract a full register from itself. */
1046 /* Make sure we are playing with integral modes. Pun with subregs
1049 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1050 if (imode
!= GET_MODE (op0
))
1052 if (GET_CODE (op0
) == MEM
)
1053 op0
= adjust_address (op0
, imode
, 0);
1054 else if (imode
!= BLKmode
)
1055 op0
= gen_lowpart (imode
, op0
);
1061 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1062 If that's wrong, the solution is to test for it and set TARGET to 0
1065 /* If OP0 is a register, BITPOS must count within a word.
1066 But as we have it, it counts within whatever size OP0 now has.
1067 On a bigendian machine, these are not the same, so convert. */
1068 if (BYTES_BIG_ENDIAN
1069 && GET_CODE (op0
) != MEM
1070 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1071 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1073 /* Extracting a full-word or multi-word value
1074 from a structure in a register or aligned memory.
1075 This can be done with just SUBREG.
1076 So too extracting a subword value in
1077 the least significant part of the register. */
1079 if (((GET_CODE (op0
) != MEM
1080 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1081 GET_MODE_BITSIZE (GET_MODE (op0
))))
1082 || (GET_CODE (op0
) == MEM
1083 && (! SLOW_UNALIGNED_ACCESS (mode
, align
)
1084 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1085 && align
% bitsize
== 0))))
1086 && ((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1087 && bitpos
% BITS_PER_WORD
== 0)
1088 || (mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0) != BLKmode
1089 /* ??? The big endian test here is wrong. This is correct
1090 if the value is in a register, and if mode_for_size is not
1091 the same mode as op0. This causes us to get unnecessarily
1092 inefficient code from the Thumb port when -mbig-endian. */
1093 && (BYTES_BIG_ENDIAN
1094 ? bitpos
+ bitsize
== BITS_PER_WORD
1097 enum machine_mode mode1
1098 = (VECTOR_MODE_P (tmode
) ? mode
1099 : mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0));
1101 if (mode1
!= GET_MODE (op0
))
1103 if (GET_CODE (op0
) == SUBREG
)
1105 if (GET_MODE (SUBREG_REG (op0
)) == mode1
1106 || GET_MODE_CLASS (mode1
) == MODE_INT
1107 || GET_MODE_CLASS (mode1
) == MODE_PARTIAL_INT
)
1108 op0
= SUBREG_REG (op0
);
1110 /* Else we've got some float mode source being extracted into
1111 a different float mode destination -- this combination of
1112 subregs results in Severe Tire Damage. */
1115 if (GET_CODE (op0
) == REG
)
1116 op0
= gen_rtx_SUBREG (mode1
, op0
,
1117 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
1118 + (offset
* UNITS_PER_WORD
));
1120 op0
= adjust_address (op0
, mode1
, offset
);
1123 return convert_to_mode (tmode
, op0
, unsignedp
);
1127 /* Handle fields bigger than a word. */
1129 if (bitsize
> BITS_PER_WORD
)
1131 /* Here we transfer the words of the field
1132 in the order least significant first.
1133 This is because the most significant word is the one which may
1134 be less than full. */
1136 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1139 if (target
== 0 || GET_CODE (target
) != REG
)
1140 target
= gen_reg_rtx (mode
);
1142 /* Indicate for flow that the entire target reg is being set. */
1143 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1145 for (i
= 0; i
< nwords
; i
++)
1147 /* If I is 0, use the low-order word in both field and target;
1148 if I is 1, use the next to lowest word; and so on. */
1149 /* Word number in TARGET to use. */
1150 unsigned int wordnum
1152 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1154 /* Offset from start of field in OP0. */
1155 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1156 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1157 * (int) BITS_PER_WORD
))
1158 : (int) i
* BITS_PER_WORD
);
1159 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1161 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1162 bitsize
- i
* BITS_PER_WORD
),
1163 bitnum
+ bit_offset
, 1, target_part
, mode
,
1164 word_mode
, align
, total_size
);
1166 if (target_part
== 0)
1169 if (result_part
!= target_part
)
1170 emit_move_insn (target_part
, result_part
);
1175 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1176 need to be zero'd out. */
1177 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1179 unsigned int i
, total_words
;
1181 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1182 for (i
= nwords
; i
< total_words
; i
++)
1184 int wordnum
= WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
;
1185 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1186 emit_move_insn (target_part
, const0_rtx
);
1192 /* Signed bit field: sign-extend with two arithmetic shifts. */
1193 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1194 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1196 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1197 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1201 /* From here on we know the desired field is smaller than a word. */
1203 /* Check if there is a correspondingly-sized integer field, so we can
1204 safely extract it as one size of integer, if necessary; then
1205 truncate or extend to the size that is wanted; then use SUBREGs or
1206 convert_to_mode to get one of the modes we really wanted. */
1208 int_mode
= int_mode_for_mode (tmode
);
1209 if (int_mode
== BLKmode
)
1210 int_mode
= int_mode_for_mode (mode
);
1211 if (int_mode
== BLKmode
)
1212 abort(); /* Should probably push op0 out to memory and then
1215 /* OFFSET is the number of words or bytes (UNIT says which)
1216 from STR_RTX to the first word or byte containing part of the field. */
1218 if (GET_CODE (op0
) != MEM
)
1221 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1223 if (GET_CODE (op0
) != REG
)
1224 op0
= copy_to_reg (op0
);
1225 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1226 op0
, (offset
* UNITS_PER_WORD
));
1232 op0
= protect_from_queue (str_rtx
, 1);
1235 /* Now OFFSET is nonzero only for memory operands. */
1241 && (extzv_bitsize
>= bitsize
)
1242 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1243 && (bitsize
+ bitpos
> extzv_bitsize
)))
1245 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1246 rtx bitsize_rtx
, bitpos_rtx
;
1247 rtx last
= get_last_insn ();
1249 rtx xtarget
= target
;
1250 rtx xspec_target
= spec_target
;
1251 rtx xspec_target_subreg
= spec_target_subreg
;
1253 enum machine_mode maxmode
;
1255 maxmode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
1256 if (maxmode
== VOIDmode
)
1257 maxmode
= word_mode
;
1259 if (GET_CODE (xop0
) == MEM
)
1261 int save_volatile_ok
= volatile_ok
;
1264 /* Is the memory operand acceptable? */
1265 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1266 (xop0
, GET_MODE (xop0
))))
1268 /* No, load into a reg and extract from there. */
1269 enum machine_mode bestmode
;
1271 /* Get the mode to use for inserting into this field. If
1272 OP0 is BLKmode, get the smallest mode consistent with the
1273 alignment. If OP0 is a non-BLKmode object that is no
1274 wider than MAXMODE, use its mode. Otherwise, use the
1275 smallest mode containing the field. */
1277 if (GET_MODE (xop0
) == BLKmode
1278 || (GET_MODE_SIZE (GET_MODE (op0
))
1279 > GET_MODE_SIZE (maxmode
)))
1280 bestmode
= get_best_mode (bitsize
, bitnum
, align
, maxmode
,
1281 MEM_VOLATILE_P (xop0
));
1283 bestmode
= GET_MODE (xop0
);
1285 if (bestmode
== VOIDmode
1286 || (SLOW_UNALIGNED_ACCESS (bestmode
, align
)
1287 && GET_MODE_BITSIZE (bestmode
) > align
))
1290 /* Compute offset as multiple of this unit,
1291 counting in bytes. */
1292 unit
= GET_MODE_BITSIZE (bestmode
);
1293 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1294 xbitpos
= bitnum
% unit
;
1295 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1297 /* Fetch it to a register in that size. */
1298 xop0
= force_reg (bestmode
, xop0
);
1300 /* XBITPOS counts within UNIT, which is what is expected. */
1303 /* Get ref to first byte containing part of the field. */
1304 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1306 volatile_ok
= save_volatile_ok
;
1309 /* If op0 is a register, we need it in MAXMODE (which is usually
1310 SImode). to make it acceptable to the format of extzv. */
1311 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1313 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1314 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1316 /* On big-endian machines, we count bits from the most significant.
1317 If the bit field insn does not, we must invert. */
1318 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1319 xbitpos
= unit
- bitsize
- xbitpos
;
1321 /* Now convert from counting within UNIT to counting in MAXMODE. */
1322 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1323 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1325 unit
= GET_MODE_BITSIZE (maxmode
);
1328 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1329 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1331 if (GET_MODE (xtarget
) != maxmode
)
1333 if (GET_CODE (xtarget
) == REG
)
1335 int wider
= (GET_MODE_SIZE (maxmode
)
1336 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1337 xtarget
= gen_lowpart (maxmode
, xtarget
);
1339 xspec_target_subreg
= xtarget
;
1342 xtarget
= gen_reg_rtx (maxmode
);
1345 /* If this machine's extzv insists on a register target,
1346 make sure we have one. */
1347 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1348 (xtarget
, maxmode
)))
1349 xtarget
= gen_reg_rtx (maxmode
);
1351 bitsize_rtx
= GEN_INT (bitsize
);
1352 bitpos_rtx
= GEN_INT (xbitpos
);
1354 pat
= gen_extzv (protect_from_queue (xtarget
, 1),
1355 xop0
, bitsize_rtx
, bitpos_rtx
);
1360 spec_target
= xspec_target
;
1361 spec_target_subreg
= xspec_target_subreg
;
1365 delete_insns_since (last
);
1366 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1367 bitpos
, target
, 1, align
);
1373 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1374 bitpos
, target
, 1, align
);
1380 && (extv_bitsize
>= bitsize
)
1381 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1382 && (bitsize
+ bitpos
> extv_bitsize
)))
1384 int xbitpos
= bitpos
, xoffset
= offset
;
1385 rtx bitsize_rtx
, bitpos_rtx
;
1386 rtx last
= get_last_insn ();
1387 rtx xop0
= op0
, xtarget
= target
;
1388 rtx xspec_target
= spec_target
;
1389 rtx xspec_target_subreg
= spec_target_subreg
;
1391 enum machine_mode maxmode
;
1393 maxmode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
1394 if (maxmode
== VOIDmode
)
1395 maxmode
= word_mode
;
1397 if (GET_CODE (xop0
) == MEM
)
1399 /* Is the memory operand acceptable? */
1400 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1401 (xop0
, GET_MODE (xop0
))))
1403 /* No, load into a reg and extract from there. */
1404 enum machine_mode bestmode
;
1406 /* Get the mode to use for inserting into this field. If
1407 OP0 is BLKmode, get the smallest mode consistent with the
1408 alignment. If OP0 is a non-BLKmode object that is no
1409 wider than MAXMODE, use its mode. Otherwise, use the
1410 smallest mode containing the field. */
1412 if (GET_MODE (xop0
) == BLKmode
1413 || (GET_MODE_SIZE (GET_MODE (op0
))
1414 > GET_MODE_SIZE (maxmode
)))
1415 bestmode
= get_best_mode (bitsize
, bitnum
, align
, maxmode
,
1416 MEM_VOLATILE_P (xop0
));
1418 bestmode
= GET_MODE (xop0
);
1420 if (bestmode
== VOIDmode
1421 || (SLOW_UNALIGNED_ACCESS (bestmode
, align
)
1422 && GET_MODE_BITSIZE (bestmode
) > align
))
1425 /* Compute offset as multiple of this unit,
1426 counting in bytes. */
1427 unit
= GET_MODE_BITSIZE (bestmode
);
1428 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1429 xbitpos
= bitnum
% unit
;
1430 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1432 /* Fetch it to a register in that size. */
1433 xop0
= force_reg (bestmode
, xop0
);
1435 /* XBITPOS counts within UNIT, which is what is expected. */
1438 /* Get ref to first byte containing part of the field. */
1439 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1442 /* If op0 is a register, we need it in MAXMODE (which is usually
1443 SImode) to make it acceptable to the format of extv. */
1444 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1446 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1447 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1449 /* On big-endian machines, we count bits from the most significant.
1450 If the bit field insn does not, we must invert. */
1451 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1452 xbitpos
= unit
- bitsize
- xbitpos
;
1454 /* XBITPOS counts within a size of UNIT.
1455 Adjust to count within a size of MAXMODE. */
1456 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1457 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1459 unit
= GET_MODE_BITSIZE (maxmode
);
1462 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1463 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1465 if (GET_MODE (xtarget
) != maxmode
)
1467 if (GET_CODE (xtarget
) == REG
)
1469 int wider
= (GET_MODE_SIZE (maxmode
)
1470 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1471 xtarget
= gen_lowpart (maxmode
, xtarget
);
1473 xspec_target_subreg
= xtarget
;
1476 xtarget
= gen_reg_rtx (maxmode
);
1479 /* If this machine's extv insists on a register target,
1480 make sure we have one. */
1481 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1482 (xtarget
, maxmode
)))
1483 xtarget
= gen_reg_rtx (maxmode
);
1485 bitsize_rtx
= GEN_INT (bitsize
);
1486 bitpos_rtx
= GEN_INT (xbitpos
);
1488 pat
= gen_extv (protect_from_queue (xtarget
, 1),
1489 xop0
, bitsize_rtx
, bitpos_rtx
);
1494 spec_target
= xspec_target
;
1495 spec_target_subreg
= xspec_target_subreg
;
1499 delete_insns_since (last
);
1500 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1501 bitpos
, target
, 0, align
);
1507 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1508 bitpos
, target
, 0, align
);
1510 if (target
== spec_target
)
1512 if (target
== spec_target_subreg
)
1514 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1516 /* If the target mode is floating-point, first convert to the
1517 integer mode of that size and then access it as a floating-point
1518 value via a SUBREG. */
1519 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1521 target
= convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode
),
1524 if (GET_CODE (target
) != REG
)
1525 target
= copy_to_reg (target
);
1526 return gen_rtx_SUBREG (tmode
, target
, 0);
1529 return convert_to_mode (tmode
, target
, unsignedp
);
1534 /* Extract a bit field using shifts and boolean operations
1535 Returns an rtx to represent the value.
1536 OP0 addresses a register (word) or memory (byte).
1537 BITPOS says which bit within the word or byte the bit field starts in.
1538 OFFSET says how many bytes farther the bit field starts;
1539 it is 0 if OP0 is a register.
1540 BITSIZE says how many bits long the bit field is.
1541 (If OP0 is a register, it may be narrower than a full word,
1542 but BITPOS still counts within a full word,
1543 which is significant on bigendian machines.)
1545 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1546 If TARGET is nonzero, attempts to store the value there
1547 and return TARGET, but this is not guaranteed.
1548 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1550 ALIGN is the alignment that STR_RTX is known to have. */
1553 extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
, bitpos
,
1554 target
, unsignedp
, align
)
1555 enum machine_mode tmode
;
1556 register rtx op0
, target
;
1557 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
1561 unsigned int total_bits
= BITS_PER_WORD
;
1562 enum machine_mode mode
;
1564 if (GET_CODE (op0
) == SUBREG
|| GET_CODE (op0
) == REG
)
1566 /* Special treatment for a bit field split across two registers. */
1567 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1568 return extract_split_bit_field (op0
, bitsize
, bitpos
,
1573 /* Get the proper mode to use for this field. We want a mode that
1574 includes the entire field. If such a mode would be larger than
1575 a word, we won't be doing the extraction the normal way. */
1577 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
, align
,
1579 GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
));
1581 if (mode
== VOIDmode
)
1582 /* The only way this should occur is if the field spans word
1584 return extract_split_bit_field (op0
, bitsize
,
1585 bitpos
+ offset
* BITS_PER_UNIT
,
1588 total_bits
= GET_MODE_BITSIZE (mode
);
1590 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1591 be in the range 0 to total_bits-1, and put any excess bytes in
1593 if (bitpos
>= total_bits
)
1595 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1596 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1600 /* Get ref to an aligned byte, halfword, or word containing the field.
1601 Adjust BITPOS to be position within a word,
1602 and OFFSET to be the offset of that word.
1603 Then alter OP0 to refer to that word. */
1604 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1605 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1606 op0
= adjust_address (op0
, mode
, offset
);
1609 mode
= GET_MODE (op0
);
1611 if (BYTES_BIG_ENDIAN
)
1613 /* BITPOS is the distance between our msb and that of OP0.
1614 Convert it to the distance from the lsb. */
1616 bitpos
= total_bits
- bitsize
- bitpos
;
1619 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1620 We have reduced the big-endian case to the little-endian case. */
1626 /* If the field does not already start at the lsb,
1627 shift it so it does. */
1628 tree amount
= build_int_2 (bitpos
, 0);
1629 /* Maybe propagate the target for the shift. */
1630 /* But not if we will return it--could confuse integrate.c. */
1631 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1632 && !REG_FUNCTION_VALUE_P (target
)
1634 if (tmode
!= mode
) subtarget
= 0;
1635 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1637 /* Convert the value to the desired mode. */
1639 op0
= convert_to_mode (tmode
, op0
, 1);
1641 /* Unless the msb of the field used to be the msb when we shifted,
1642 mask out the upper bits. */
1644 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
1646 #ifdef SLOW_ZERO_EXTEND
1647 /* Always generate an `and' if
1648 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1649 will combine fruitfully with the zero-extend. */
1654 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1655 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1656 target
, 1, OPTAB_LIB_WIDEN
);
1660 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1661 then arithmetic-shift its lsb to the lsb of the word. */
1662 op0
= force_reg (mode
, op0
);
1666 /* Find the narrowest integer mode that contains the field. */
1668 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1669 mode
= GET_MODE_WIDER_MODE (mode
))
1670 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1672 op0
= convert_to_mode (mode
, op0
, 0);
1676 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1678 tree amount
= build_int_2 (GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
), 0);
1679 /* Maybe propagate the target for the shift. */
1680 /* But not if we will return the result--could confuse integrate.c. */
1681 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1682 && ! REG_FUNCTION_VALUE_P (target
)
1684 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1687 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1688 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1692 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1693 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1694 complement of that if COMPLEMENT. The mask is truncated if
1695 necessary to the width of mode MODE. The mask is zero-extended if
1696 BITSIZE+BITPOS is too small for MODE. */
1699 mask_rtx (mode
, bitpos
, bitsize
, complement
)
1700 enum machine_mode mode
;
1701 int bitpos
, bitsize
, complement
;
1703 HOST_WIDE_INT masklow
, maskhigh
;
1705 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1706 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1710 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1711 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1712 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1714 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1717 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1719 if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1720 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1721 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1727 maskhigh
= ~maskhigh
;
1731 return immed_double_const (masklow
, maskhigh
, mode
);
1734 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1735 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1738 lshift_value (mode
, value
, bitpos
, bitsize
)
1739 enum machine_mode mode
;
1741 int bitpos
, bitsize
;
1743 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1744 HOST_WIDE_INT low
, high
;
1746 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1747 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1749 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1752 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1757 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1760 return immed_double_const (low
, high
, mode
);
1763 /* Extract a bit field that is split across two words
1764 and return an RTX for the result.
1766 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1767 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1768 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1770 ALIGN is the known alignment of OP0. This is also the size of the
1771 memory objects to be used. */
1774 extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
, align
)
1776 unsigned HOST_WIDE_INT bitsize
, bitpos
;
1781 unsigned int bitsdone
= 0;
1782 rtx result
= NULL_RTX
;
1785 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1787 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1788 unit
= BITS_PER_WORD
;
1790 unit
= MIN (align
, BITS_PER_WORD
);
1792 while (bitsdone
< bitsize
)
1794 unsigned HOST_WIDE_INT thissize
;
1796 unsigned HOST_WIDE_INT thispos
;
1797 unsigned HOST_WIDE_INT offset
;
1799 offset
= (bitpos
+ bitsdone
) / unit
;
1800 thispos
= (bitpos
+ bitsdone
) % unit
;
1802 /* THISSIZE must not overrun a word boundary. Otherwise,
1803 extract_fixed_bit_field will call us again, and we will mutually
1805 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1806 thissize
= MIN (thissize
, unit
- thispos
);
1808 /* If OP0 is a register, then handle OFFSET here.
1810 When handling multiword bitfields, extract_bit_field may pass
1811 down a word_mode SUBREG of a larger REG for a bitfield that actually
1812 crosses a word boundary. Thus, for a SUBREG, we must find
1813 the current word starting from the base register. */
1814 if (GET_CODE (op0
) == SUBREG
)
1816 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1817 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1818 GET_MODE (SUBREG_REG (op0
)));
1821 else if (GET_CODE (op0
) == REG
)
1823 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1829 /* Extract the parts in bit-counting order,
1830 whose meaning is determined by BYTES_PER_UNIT.
1831 OFFSET is in UNITs, and UNIT is in bits.
1832 extract_fixed_bit_field wants offset in bytes. */
1833 part
= extract_fixed_bit_field (word_mode
, word
,
1834 offset
* unit
/ BITS_PER_UNIT
,
1835 thissize
, thispos
, 0, 1, align
);
1836 bitsdone
+= thissize
;
1838 /* Shift this part into place for the result. */
1839 if (BYTES_BIG_ENDIAN
)
1841 if (bitsize
!= bitsdone
)
1842 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1843 build_int_2 (bitsize
- bitsdone
, 0), 0, 1);
1847 if (bitsdone
!= thissize
)
1848 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1849 build_int_2 (bitsdone
- thissize
, 0), 0, 1);
1855 /* Combine the parts with bitwise or. This works
1856 because we extracted each part as an unsigned bit field. */
1857 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1863 /* Unsigned bit field: we are done. */
1866 /* Signed bit field: sign-extend with two arithmetic shifts. */
1867 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1868 build_int_2 (BITS_PER_WORD
- bitsize
, 0),
1870 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1871 build_int_2 (BITS_PER_WORD
- bitsize
, 0), NULL_RTX
, 0);
1874 /* Add INC into TARGET. */
1877 expand_inc (target
, inc
)
1880 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
1882 target
, 0, OPTAB_LIB_WIDEN
);
1883 if (value
!= target
)
1884 emit_move_insn (target
, value
);
1887 /* Subtract DEC from TARGET. */
1890 expand_dec (target
, dec
)
1893 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
1895 target
, 0, OPTAB_LIB_WIDEN
);
1896 if (value
!= target
)
1897 emit_move_insn (target
, value
);
1900 /* Output a shift instruction for expression code CODE,
1901 with SHIFTED being the rtx for the value to shift,
1902 and AMOUNT the tree for the amount to shift by.
1903 Store the result in the rtx TARGET, if that is convenient.
1904 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1905 Return the rtx for where the value is. */
1908 expand_shift (code
, mode
, shifted
, amount
, target
, unsignedp
)
1909 enum tree_code code
;
1910 register enum machine_mode mode
;
1913 register rtx target
;
1916 register rtx op1
, temp
= 0;
1917 register int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
1918 register int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
1921 /* Previously detected shift-counts computed by NEGATE_EXPR
1922 and shifted in the other direction; but that does not work
1925 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
1927 #ifdef SHIFT_COUNT_TRUNCATED
1928 if (SHIFT_COUNT_TRUNCATED
)
1930 if (GET_CODE (op1
) == CONST_INT
1931 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
1932 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
1933 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
1934 % GET_MODE_BITSIZE (mode
));
1935 else if (GET_CODE (op1
) == SUBREG
1936 && SUBREG_BYTE (op1
) == 0)
1937 op1
= SUBREG_REG (op1
);
1941 if (op1
== const0_rtx
)
1944 for (try = 0; temp
== 0 && try < 3; try++)
1946 enum optab_methods methods
;
1949 methods
= OPTAB_DIRECT
;
1951 methods
= OPTAB_WIDEN
;
1953 methods
= OPTAB_LIB_WIDEN
;
1957 /* Widening does not work for rotation. */
1958 if (methods
== OPTAB_WIDEN
)
1960 else if (methods
== OPTAB_LIB_WIDEN
)
1962 /* If we have been unable to open-code this by a rotation,
1963 do it as the IOR of two shifts. I.e., to rotate A
1964 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1965 where C is the bitsize of A.
1967 It is theoretically possible that the target machine might
1968 not be able to perform either shift and hence we would
1969 be making two libcalls rather than just the one for the
1970 shift (similarly if IOR could not be done). We will allow
1971 this extremely unlikely lossage to avoid complicating the
1974 rtx subtarget
= target
== shifted
? 0 : target
;
1976 tree type
= TREE_TYPE (amount
);
1977 tree new_amount
= make_tree (type
, op1
);
1979 = fold (build (MINUS_EXPR
, type
,
1981 build_int_2 (GET_MODE_BITSIZE (mode
),
1985 shifted
= force_reg (mode
, shifted
);
1987 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
1988 mode
, shifted
, new_amount
, subtarget
, 1);
1989 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
1990 mode
, shifted
, other_amount
, 0, 1);
1991 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
1992 unsignedp
, methods
);
1995 temp
= expand_binop (mode
,
1996 left
? rotl_optab
: rotr_optab
,
1997 shifted
, op1
, target
, unsignedp
, methods
);
1999 /* If we don't have the rotate, but we are rotating by a constant
2000 that is in range, try a rotate in the opposite direction. */
2002 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
2003 && INTVAL (op1
) > 0 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
2004 temp
= expand_binop (mode
,
2005 left
? rotr_optab
: rotl_optab
,
2007 GEN_INT (GET_MODE_BITSIZE (mode
)
2009 target
, unsignedp
, methods
);
2012 temp
= expand_binop (mode
,
2013 left
? ashl_optab
: lshr_optab
,
2014 shifted
, op1
, target
, unsignedp
, methods
);
2016 /* Do arithmetic shifts.
2017 Also, if we are going to widen the operand, we can just as well
2018 use an arithmetic right-shift instead of a logical one. */
2019 if (temp
== 0 && ! rotate
2020 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2022 enum optab_methods methods1
= methods
;
2024 /* If trying to widen a log shift to an arithmetic shift,
2025 don't accept an arithmetic shift of the same size. */
2027 methods1
= OPTAB_MUST_WIDEN
;
2029 /* Arithmetic shift */
2031 temp
= expand_binop (mode
,
2032 left
? ashl_optab
: ashr_optab
,
2033 shifted
, op1
, target
, unsignedp
, methods1
);
2036 /* We used to try extzv here for logical right shifts, but that was
2037 only useful for one machine, the VAX, and caused poor code
2038 generation there for lshrdi3, so the code was deleted and a
2039 define_expand for lshrsi3 was added to vax.md. */
2047 enum alg_code
{ alg_zero
, alg_m
, alg_shift
,
2048 alg_add_t_m2
, alg_sub_t_m2
,
2049 alg_add_factor
, alg_sub_factor
,
2050 alg_add_t2_m
, alg_sub_t2_m
,
2051 alg_add
, alg_subtract
, alg_factor
, alg_shiftop
};
2053 /* This structure records a sequence of operations.
2054 `ops' is the number of operations recorded.
2055 `cost' is their total cost.
2056 The operations are stored in `op' and the corresponding
2057 logarithms of the integer coefficients in `log'.
2059 These are the operations:
2060 alg_zero total := 0;
2061 alg_m total := multiplicand;
2062 alg_shift total := total * coeff
2063 alg_add_t_m2 total := total + multiplicand * coeff;
2064 alg_sub_t_m2 total := total - multiplicand * coeff;
2065 alg_add_factor total := total * coeff + total;
2066 alg_sub_factor total := total * coeff - total;
2067 alg_add_t2_m total := total * coeff + multiplicand;
2068 alg_sub_t2_m total := total * coeff - multiplicand;
2070 The first operand must be either alg_zero or alg_m. */
2076 /* The size of the OP and LOG fields are not directly related to the
2077 word size, but the worst-case algorithms will be if we have few
2078 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2079 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2080 in total wordsize operations. */
2081 enum alg_code op
[MAX_BITS_PER_WORD
];
2082 char log
[MAX_BITS_PER_WORD
];
2085 static void synth_mult
PARAMS ((struct algorithm
*,
2086 unsigned HOST_WIDE_INT
,
2088 static unsigned HOST_WIDE_INT choose_multiplier
PARAMS ((unsigned HOST_WIDE_INT
,
2090 unsigned HOST_WIDE_INT
*,
2092 static unsigned HOST_WIDE_INT invert_mod2n
PARAMS ((unsigned HOST_WIDE_INT
,
2094 /* Compute and return the best algorithm for multiplying by T.
2095 The algorithm must cost less than cost_limit
2096 If retval.cost >= COST_LIMIT, no algorithm was found and all
2097 other field of the returned struct are undefined. */
2100 synth_mult (alg_out
, t
, cost_limit
)
2101 struct algorithm
*alg_out
;
2102 unsigned HOST_WIDE_INT t
;
2106 struct algorithm
*alg_in
, *best_alg
;
2108 unsigned HOST_WIDE_INT q
;
2110 /* Indicate that no algorithm is yet found. If no algorithm
2111 is found, this value will be returned and indicate failure. */
2112 alg_out
->cost
= cost_limit
;
2114 if (cost_limit
<= 0)
2117 /* t == 1 can be done in zero cost. */
2122 alg_out
->op
[0] = alg_m
;
2126 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2130 if (zero_cost
>= cost_limit
)
2135 alg_out
->cost
= zero_cost
;
2136 alg_out
->op
[0] = alg_zero
;
2141 /* We'll be needing a couple extra algorithm structures now. */
2143 alg_in
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2144 best_alg
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2146 /* If we have a group of zero bits at the low-order part of T, try
2147 multiplying by the remaining bits and then doing a shift. */
2151 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2152 if (m
< BITS_PER_WORD
)
2155 cost
= shift_cost
[m
];
2156 synth_mult (alg_in
, q
, cost_limit
- cost
);
2158 cost
+= alg_in
->cost
;
2159 if (cost
< cost_limit
)
2161 struct algorithm
*x
;
2162 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2163 best_alg
->log
[best_alg
->ops
] = m
;
2164 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2170 /* If we have an odd number, add or subtract one. */
2173 unsigned HOST_WIDE_INT w
;
2175 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2177 /* If T was -1, then W will be zero after the loop. This is another
2178 case where T ends with ...111. Handling this with (T + 1) and
2179 subtract 1 produces slightly better code and results in algorithm
2180 selection much faster than treating it like the ...0111 case
2184 /* Reject the case where t is 3.
2185 Thus we prefer addition in that case. */
2188 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2191 synth_mult (alg_in
, t
+ 1, cost_limit
- cost
);
2193 cost
+= alg_in
->cost
;
2194 if (cost
< cost_limit
)
2196 struct algorithm
*x
;
2197 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2198 best_alg
->log
[best_alg
->ops
] = 0;
2199 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2205 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2208 synth_mult (alg_in
, t
- 1, cost_limit
- cost
);
2210 cost
+= alg_in
->cost
;
2211 if (cost
< cost_limit
)
2213 struct algorithm
*x
;
2214 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2215 best_alg
->log
[best_alg
->ops
] = 0;
2216 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2222 /* Look for factors of t of the form
2223 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2224 If we find such a factor, we can multiply by t using an algorithm that
2225 multiplies by q, shift the result by m and add/subtract it to itself.
2227 We search for large factors first and loop down, even if large factors
2228 are less probable than small; if we find a large factor we will find a
2229 good sequence quickly, and therefore be able to prune (by decreasing
2230 COST_LIMIT) the search. */
2232 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2234 unsigned HOST_WIDE_INT d
;
2236 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2237 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2239 cost
= MIN (shiftadd_cost
[m
], add_cost
+ shift_cost
[m
]);
2240 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2242 cost
+= alg_in
->cost
;
2243 if (cost
< cost_limit
)
2245 struct algorithm
*x
;
2246 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2247 best_alg
->log
[best_alg
->ops
] = m
;
2248 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2251 /* Other factors will have been taken care of in the recursion. */
2255 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2256 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2258 cost
= MIN (shiftsub_cost
[m
], add_cost
+ shift_cost
[m
]);
2259 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2261 cost
+= alg_in
->cost
;
2262 if (cost
< cost_limit
)
2264 struct algorithm
*x
;
2265 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2266 best_alg
->log
[best_alg
->ops
] = m
;
2267 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2274 /* Try shift-and-add (load effective address) instructions,
2275 i.e. do a*3, a*5, a*9. */
2281 if (m
>= 0 && m
< BITS_PER_WORD
)
2283 cost
= shiftadd_cost
[m
];
2284 synth_mult (alg_in
, (t
- 1) >> m
, cost_limit
- cost
);
2286 cost
+= alg_in
->cost
;
2287 if (cost
< cost_limit
)
2289 struct algorithm
*x
;
2290 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2291 best_alg
->log
[best_alg
->ops
] = m
;
2292 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2300 if (m
>= 0 && m
< BITS_PER_WORD
)
2302 cost
= shiftsub_cost
[m
];
2303 synth_mult (alg_in
, (t
+ 1) >> m
, cost_limit
- cost
);
2305 cost
+= alg_in
->cost
;
2306 if (cost
< cost_limit
)
2308 struct algorithm
*x
;
2309 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2310 best_alg
->log
[best_alg
->ops
] = m
;
2311 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2317 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2318 we have not found any algorithm. */
2319 if (cost_limit
== alg_out
->cost
)
2322 /* If we are getting a too long sequence for `struct algorithm'
2323 to record, make this search fail. */
2324 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2327 /* Copy the algorithm from temporary space to the space at alg_out.
2328 We avoid using structure assignment because the majority of
2329 best_alg is normally undefined, and this is a critical function. */
2330 alg_out
->ops
= best_alg
->ops
+ 1;
2331 alg_out
->cost
= cost_limit
;
2332 memcpy (alg_out
->op
, best_alg
->op
,
2333 alg_out
->ops
* sizeof *alg_out
->op
);
2334 memcpy (alg_out
->log
, best_alg
->log
,
2335 alg_out
->ops
* sizeof *alg_out
->log
);
2338 /* Perform a multiplication and return an rtx for the result.
2339 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2340 TARGET is a suggestion for where to store the result (an rtx).
2342 We check specially for a constant integer as OP1.
2343 If you want this check for OP0 as well, then before calling
2344 you should swap the two operands if OP0 would be constant. */
2347 expand_mult (mode
, op0
, op1
, target
, unsignedp
)
2348 enum machine_mode mode
;
2349 register rtx op0
, op1
, target
;
2352 rtx const_op1
= op1
;
2354 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2355 less than or equal in size to `unsigned int' this doesn't matter.
2356 If the mode is larger than `unsigned int', then synth_mult works only
2357 if the constant value exactly fits in an `unsigned int' without any
2358 truncation. This means that multiplying by negative values does
2359 not work; results are off by 2^32 on a 32 bit machine. */
2361 /* If we are multiplying in DImode, it may still be a win
2362 to try to work with shifts and adds. */
2363 if (GET_CODE (op1
) == CONST_DOUBLE
2364 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
2365 && HOST_BITS_PER_INT
>= BITS_PER_WORD
2366 && CONST_DOUBLE_HIGH (op1
) == 0)
2367 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2368 else if (HOST_BITS_PER_INT
< GET_MODE_BITSIZE (mode
)
2369 && GET_CODE (op1
) == CONST_INT
2370 && INTVAL (op1
) < 0)
2373 /* We used to test optimize here, on the grounds that it's better to
2374 produce a smaller program when -O is not used.
2375 But this causes such a terrible slowdown sometimes
2376 that it seems better to use synth_mult always. */
2378 if (const_op1
&& GET_CODE (const_op1
) == CONST_INT
2379 && (unsignedp
|| ! flag_trapv
))
2381 struct algorithm alg
;
2382 struct algorithm alg2
;
2383 HOST_WIDE_INT val
= INTVAL (op1
);
2384 HOST_WIDE_INT val_so_far
;
2387 enum {basic_variant
, negate_variant
, add_variant
} variant
= basic_variant
;
2389 /* Try to do the computation three ways: multiply by the negative of OP1
2390 and then negate, do the multiplication directly, or do multiplication
2393 mult_cost
= rtx_cost (gen_rtx_MULT (mode
, op0
, op1
), SET
);
2394 mult_cost
= MIN (12 * add_cost
, mult_cost
);
2396 synth_mult (&alg
, val
, mult_cost
);
2398 /* This works only if the inverted value actually fits in an
2400 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2402 synth_mult (&alg2
, - val
,
2403 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - negate_cost
);
2404 if (alg2
.cost
+ negate_cost
< alg
.cost
)
2405 alg
= alg2
, variant
= negate_variant
;
2408 /* This proves very useful for division-by-constant. */
2409 synth_mult (&alg2
, val
- 1,
2410 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - add_cost
);
2411 if (alg2
.cost
+ add_cost
< alg
.cost
)
2412 alg
= alg2
, variant
= add_variant
;
2414 if (alg
.cost
< mult_cost
)
2416 /* We found something cheaper than a multiply insn. */
2419 enum machine_mode nmode
;
2421 op0
= protect_from_queue (op0
, 0);
2423 /* Avoid referencing memory over and over.
2424 For speed, but also for correctness when mem is volatile. */
2425 if (GET_CODE (op0
) == MEM
)
2426 op0
= force_reg (mode
, op0
);
2428 /* ACCUM starts out either as OP0 or as a zero, depending on
2429 the first operation. */
2431 if (alg
.op
[0] == alg_zero
)
2433 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2436 else if (alg
.op
[0] == alg_m
)
2438 accum
= copy_to_mode_reg (mode
, op0
);
2444 for (opno
= 1; opno
< alg
.ops
; opno
++)
2446 int log
= alg
.log
[opno
];
2447 int preserve
= preserve_subexpressions_p ();
2448 rtx shift_subtarget
= preserve
? 0 : accum
;
2450 = (opno
== alg
.ops
- 1 && target
!= 0 && variant
!= add_variant
2453 rtx accum_target
= preserve
? 0 : accum
;
2455 switch (alg
.op
[opno
])
2458 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2459 build_int_2 (log
, 0), NULL_RTX
, 0);
2464 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2465 build_int_2 (log
, 0), NULL_RTX
, 0);
2466 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2468 ? add_target
: accum_target
);
2469 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2473 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2474 build_int_2 (log
, 0), NULL_RTX
, 0);
2475 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2477 ? add_target
: accum_target
);
2478 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2482 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2483 build_int_2 (log
, 0), shift_subtarget
,
2485 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2487 ? add_target
: accum_target
);
2488 val_so_far
= (val_so_far
<< log
) + 1;
2492 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2493 build_int_2 (log
, 0), shift_subtarget
,
2495 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2497 ? add_target
: accum_target
);
2498 val_so_far
= (val_so_far
<< log
) - 1;
2501 case alg_add_factor
:
2502 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2503 build_int_2 (log
, 0), NULL_RTX
, 0);
2504 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2506 ? add_target
: accum_target
);
2507 val_so_far
+= val_so_far
<< log
;
2510 case alg_sub_factor
:
2511 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2512 build_int_2 (log
, 0), NULL_RTX
, 0);
2513 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2514 (add_target
? add_target
2515 : preserve
? 0 : tem
));
2516 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2523 /* Write a REG_EQUAL note on the last insn so that we can cse
2524 multiplication sequences. Note that if ACCUM is a SUBREG,
2525 we've set the inner register and must properly indicate
2528 tem
= op0
, nmode
= mode
;
2529 if (GET_CODE (accum
) == SUBREG
)
2531 nmode
= GET_MODE (SUBREG_REG (accum
));
2532 tem
= gen_lowpart (nmode
, op0
);
2535 insn
= get_last_insn ();
2536 set_unique_reg_note (insn
,
2538 gen_rtx_MULT (nmode
, tem
,
2539 GEN_INT (val_so_far
)));
2542 if (variant
== negate_variant
)
2544 val_so_far
= - val_so_far
;
2545 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2547 else if (variant
== add_variant
)
2549 val_so_far
= val_so_far
+ 1;
2550 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2553 if (val
!= val_so_far
)
2560 /* This used to use umul_optab if unsigned, but for non-widening multiply
2561 there is no difference between signed and unsigned. */
2562 op0
= expand_binop (mode
,
2564 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
2565 ? smulv_optab
: smul_optab
,
2566 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
2572 /* Return the smallest n such that 2**n >= X. */
2576 unsigned HOST_WIDE_INT x
;
2578 return floor_log2 (x
- 1) + 1;
2581 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2582 replace division by D, and put the least significant N bits of the result
2583 in *MULTIPLIER_PTR and return the most significant bit.
2585 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2586 needed precision is in PRECISION (should be <= N).
2588 PRECISION should be as small as possible so this function can choose
2589 multiplier more freely.
2591 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2592 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2594 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2595 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2598 unsigned HOST_WIDE_INT
2599 choose_multiplier (d
, n
, precision
, multiplier_ptr
, post_shift_ptr
, lgup_ptr
)
2600 unsigned HOST_WIDE_INT d
;
2603 unsigned HOST_WIDE_INT
*multiplier_ptr
;
2604 int *post_shift_ptr
;
2607 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
2608 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
2609 int lgup
, post_shift
;
2611 unsigned HOST_WIDE_INT nl
, dummy1
;
2612 HOST_WIDE_INT nh
, dummy2
;
2614 /* lgup = ceil(log2(divisor)); */
2615 lgup
= ceil_log2 (d
);
2621 pow2
= n
+ lgup
- precision
;
2623 if (pow
== 2 * HOST_BITS_PER_WIDE_INT
)
2625 /* We could handle this with some effort, but this case is much better
2626 handled directly with a scc insn, so rely on caller using that. */
2630 /* mlow = 2^(N + lgup)/d */
2631 if (pow
>= HOST_BITS_PER_WIDE_INT
)
2633 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
2639 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
2641 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2642 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
2644 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2645 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
2646 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
2648 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
2649 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2650 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
2652 if (mhigh_hi
&& nh
- d
>= d
)
2654 if (mhigh_hi
> 1 || mlow_hi
> 1)
2656 /* assert that mlow < mhigh. */
2657 if (! (mlow_hi
< mhigh_hi
|| (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
)))
2660 /* If precision == N, then mlow, mhigh exceed 2^N
2661 (but they do not exceed 2^(N+1)). */
2663 /* Reduce to lowest terms */
2664 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
2666 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
2667 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
2677 *post_shift_ptr
= post_shift
;
2679 if (n
< HOST_BITS_PER_WIDE_INT
)
2681 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
2682 *multiplier_ptr
= mhigh_lo
& mask
;
2683 return mhigh_lo
>= mask
;
2687 *multiplier_ptr
= mhigh_lo
;
2692 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2693 congruent to 1 (mod 2**N). */
2695 static unsigned HOST_WIDE_INT
2697 unsigned HOST_WIDE_INT x
;
2700 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2702 /* The algorithm notes that the choice y = x satisfies
2703 x*y == 1 mod 2^3, since x is assumed odd.
2704 Each iteration doubles the number of bits of significance in y. */
2706 unsigned HOST_WIDE_INT mask
;
2707 unsigned HOST_WIDE_INT y
= x
;
2710 mask
= (n
== HOST_BITS_PER_WIDE_INT
2711 ? ~(unsigned HOST_WIDE_INT
) 0
2712 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
2716 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
2722 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2723 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2724 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2725 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2728 The result is put in TARGET if that is convenient.
2730 MODE is the mode of operation. */
2733 expand_mult_highpart_adjust (mode
, adj_operand
, op0
, op1
, target
, unsignedp
)
2734 enum machine_mode mode
;
2735 register rtx adj_operand
, op0
, op1
, target
;
2739 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
2741 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2742 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2744 tem
= expand_and (tem
, op1
, NULL_RTX
);
2746 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2749 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
2750 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2752 tem
= expand_and (tem
, op0
, NULL_RTX
);
2753 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2759 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2760 in TARGET if that is convenient, and return where the result is. If the
2761 operation can not be performed, 0 is returned.
2763 MODE is the mode of operation and result.
2765 UNSIGNEDP nonzero means unsigned multiply.
2767 MAX_COST is the total allowed cost for the expanded RTL. */
2770 expand_mult_highpart (mode
, op0
, cnst1
, target
, unsignedp
, max_cost
)
2771 enum machine_mode mode
;
2772 register rtx op0
, target
;
2773 unsigned HOST_WIDE_INT cnst1
;
2777 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
2778 optab mul_highpart_optab
;
2781 int size
= GET_MODE_BITSIZE (mode
);
2784 /* We can't support modes wider than HOST_BITS_PER_INT. */
2785 if (size
> HOST_BITS_PER_WIDE_INT
)
2788 op1
= GEN_INT (trunc_int_for_mode (cnst1
, mode
));
2790 if (GET_MODE_BITSIZE (wider_mode
) <= HOST_BITS_PER_INT
)
2794 = immed_double_const (cnst1
,
2797 : -(cnst1
>> (HOST_BITS_PER_WIDE_INT
- 1))),
2800 /* expand_mult handles constant multiplication of word_mode
2801 or narrower. It does a poor job for large modes. */
2802 if (size
< BITS_PER_WORD
2803 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2805 /* We have to do this, since expand_binop doesn't do conversion for
2806 multiply. Maybe change expand_binop to handle widening multiply? */
2807 op0
= convert_to_mode (wider_mode
, op0
, unsignedp
);
2809 /* We know that this can't have signed overflow, so pretend this is
2810 an unsigned multiply. */
2811 tem
= expand_mult (wider_mode
, op0
, wide_op1
, NULL_RTX
, 0);
2812 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2813 build_int_2 (size
, 0), NULL_RTX
, 1);
2814 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2818 target
= gen_reg_rtx (mode
);
2820 /* Firstly, try using a multiplication insn that only generates the needed
2821 high part of the product, and in the sign flavor of unsignedp. */
2822 if (mul_highpart_cost
[(int) mode
] < max_cost
)
2824 mul_highpart_optab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
2825 target
= expand_binop (mode
, mul_highpart_optab
,
2826 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2831 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2832 Need to adjust the result after the multiplication. */
2833 if (size
- 1 < BITS_PER_WORD
2834 && (mul_highpart_cost
[(int) mode
] + 2 * shift_cost
[size
-1] + 4 * add_cost
2837 mul_highpart_optab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
2838 target
= expand_binop (mode
, mul_highpart_optab
,
2839 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2841 /* We used the wrong signedness. Adjust the result. */
2842 return expand_mult_highpart_adjust (mode
, target
, op0
,
2843 op1
, target
, unsignedp
);
2846 /* Try widening multiplication. */
2847 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
2848 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2849 && mul_widen_cost
[(int) wider_mode
] < max_cost
)
2851 op1
= force_reg (mode
, op1
);
2855 /* Try widening the mode and perform a non-widening multiplication. */
2856 moptab
= smul_optab
;
2857 if (smul_optab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2858 && size
- 1 < BITS_PER_WORD
2859 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2865 /* Try widening multiplication of opposite signedness, and adjust. */
2866 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
2867 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2868 && size
- 1 < BITS_PER_WORD
2869 && (mul_widen_cost
[(int) wider_mode
]
2870 + 2 * shift_cost
[size
-1] + 4 * add_cost
< max_cost
))
2872 rtx regop1
= force_reg (mode
, op1
);
2873 tem
= expand_binop (wider_mode
, moptab
, op0
, regop1
,
2874 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
2877 /* Extract the high half of the just generated product. */
2878 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2879 build_int_2 (size
, 0), NULL_RTX
, 1);
2880 tem
= convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2881 /* We used the wrong signedness. Adjust the result. */
2882 return expand_mult_highpart_adjust (mode
, tem
, op0
, op1
,
2890 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2891 tem
= expand_binop (wider_mode
, moptab
, op0
, op1
,
2892 NULL_RTX
, unsignedp
, OPTAB_WIDEN
);
2896 /* Extract the high half of the just generated product. */
2897 if (mode
== word_mode
)
2899 return gen_highpart (mode
, tem
);
2903 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2904 build_int_2 (size
, 0), NULL_RTX
, 1);
2905 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2909 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2910 if that is convenient, and returning where the result is.
2911 You may request either the quotient or the remainder as the result;
2912 specify REM_FLAG nonzero to get the remainder.
2914 CODE is the expression code for which kind of division this is;
2915 it controls how rounding is done. MODE is the machine mode to use.
2916 UNSIGNEDP nonzero means do unsigned division. */
2918 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2919 and then correct it by or'ing in missing high bits
2920 if result of ANDI is nonzero.
2921 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2922 This could optimize to a bfexts instruction.
2923 But C doesn't use these operations, so their optimizations are
2925 /* ??? For modulo, we don't actually need the highpart of the first product,
2926 the low part will do nicely. And for small divisors, the second multiply
2927 can also be a low-part only multiply or even be completely left out.
2928 E.g. to calculate the remainder of a division by 3 with a 32 bit
2929 multiply, multiply with 0x55555556 and extract the upper two bits;
2930 the result is exact for inputs up to 0x1fffffff.
2931 The input range can be reduced by using cross-sum rules.
2932 For odd divisors >= 3, the following table gives right shift counts
2933 so that if an number is shifted by an integer multiple of the given
2934 amount, the remainder stays the same:
2935 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
2936 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
2937 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
2938 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
2939 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
2941 Cross-sum rules for even numbers can be derived by leaving as many bits
2942 to the right alone as the divisor has zeros to the right.
2943 E.g. if x is an unsigned 32 bit number:
2944 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
2947 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2950 expand_divmod (rem_flag
, code
, mode
, op0
, op1
, target
, unsignedp
)
2952 enum tree_code code
;
2953 enum machine_mode mode
;
2954 register rtx op0
, op1
, target
;
2957 enum machine_mode compute_mode
;
2958 register rtx tquotient
;
2959 rtx quotient
= 0, remainder
= 0;
2963 optab optab1
, optab2
;
2964 int op1_is_constant
, op1_is_pow2
;
2965 int max_cost
, extra_cost
;
2966 static HOST_WIDE_INT last_div_const
= 0;
2968 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
2969 op1_is_pow2
= (op1_is_constant
2970 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
2971 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
))))));
2974 This is the structure of expand_divmod:
2976 First comes code to fix up the operands so we can perform the operations
2977 correctly and efficiently.
2979 Second comes a switch statement with code specific for each rounding mode.
2980 For some special operands this code emits all RTL for the desired
2981 operation, for other cases, it generates only a quotient and stores it in
2982 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2983 to indicate that it has not done anything.
2985 Last comes code that finishes the operation. If QUOTIENT is set and
2986 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
2987 QUOTIENT is not set, it is computed using trunc rounding.
2989 We try to generate special code for division and remainder when OP1 is a
2990 constant. If |OP1| = 2**n we can use shifts and some other fast
2991 operations. For other values of OP1, we compute a carefully selected
2992 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2995 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2996 half of the product. Different strategies for generating the product are
2997 implemented in expand_mult_highpart.
2999 If what we actually want is the remainder, we generate that by another
3000 by-constant multiplication and a subtraction. */
3002 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3003 code below will malfunction if we are, so check here and handle
3004 the special case if so. */
3005 if (op1
== const1_rtx
)
3006 return rem_flag
? const0_rtx
: op0
;
3008 /* When dividing by -1, we could get an overflow.
3009 negv_optab can handle overflows. */
3010 if (! unsignedp
&& op1
== constm1_rtx
)
3014 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3015 ? negv_optab
: neg_optab
, op0
, target
, 0);
3019 /* Don't use the function value register as a target
3020 since we have to read it as well as write it,
3021 and function-inlining gets confused by this. */
3022 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3023 /* Don't clobber an operand while doing a multi-step calculation. */
3024 || ((rem_flag
|| op1_is_constant
)
3025 && (reg_mentioned_p (target
, op0
)
3026 || (GET_CODE (op0
) == MEM
&& GET_CODE (target
) == MEM
)))
3027 || reg_mentioned_p (target
, op1
)
3028 || (GET_CODE (op1
) == MEM
&& GET_CODE (target
) == MEM
)))
3031 /* Get the mode in which to perform this computation. Normally it will
3032 be MODE, but sometimes we can't do the desired operation in MODE.
3033 If so, pick a wider mode in which we can do the operation. Convert
3034 to that mode at the start to avoid repeated conversions.
3036 First see what operations we need. These depend on the expression
3037 we are evaluating. (We assume that divxx3 insns exist under the
3038 same conditions that modxx3 insns and that these insns don't normally
3039 fail. If these assumptions are not correct, we may generate less
3040 efficient code in some cases.)
3042 Then see if we find a mode in which we can open-code that operation
3043 (either a division, modulus, or shift). Finally, check for the smallest
3044 mode for which we can do the operation with a library call. */
3046 /* We might want to refine this now that we have division-by-constant
3047 optimization. Since expand_mult_highpart tries so many variants, it is
3048 not straightforward to generalize this. Maybe we should make an array
3049 of possible modes in init_expmed? Save this for GCC 2.7. */
3051 optab1
= (op1_is_pow2
? (unsignedp
? lshr_optab
: ashr_optab
)
3052 : (unsignedp
? udiv_optab
: sdiv_optab
));
3053 optab2
= (op1_is_pow2
? optab1
: (unsignedp
? udivmod_optab
: sdivmod_optab
));
3055 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3056 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3057 if (optab1
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
3058 || optab2
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
)
3061 if (compute_mode
== VOIDmode
)
3062 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3063 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3064 if (optab1
->handlers
[(int) compute_mode
].libfunc
3065 || optab2
->handlers
[(int) compute_mode
].libfunc
)
3068 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3070 if (compute_mode
== VOIDmode
)
3071 compute_mode
= mode
;
3073 if (target
&& GET_MODE (target
) == compute_mode
)
3076 tquotient
= gen_reg_rtx (compute_mode
);
3078 size
= GET_MODE_BITSIZE (compute_mode
);
3080 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3081 (mode), and thereby get better code when OP1 is a constant. Do that
3082 later. It will require going over all usages of SIZE below. */
3083 size
= GET_MODE_BITSIZE (mode
);
3086 /* Only deduct something for a REM if the last divide done was
3087 for a different constant. Then set the constant of the last
3089 max_cost
= div_cost
[(int) compute_mode
]
3090 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3091 && INTVAL (op1
) == last_div_const
)
3092 ? mul_cost
[(int) compute_mode
] + add_cost
: 0);
3094 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3096 /* Now convert to the best mode to use. */
3097 if (compute_mode
!= mode
)
3099 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3100 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3102 /* convert_modes may have placed op1 into a register, so we
3103 must recompute the following. */
3104 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3105 op1_is_pow2
= (op1_is_constant
3106 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3108 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3111 /* If one of the operands is a volatile MEM, copy it into a register. */
3113 if (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
))
3114 op0
= force_reg (compute_mode
, op0
);
3115 if (GET_CODE (op1
) == MEM
&& MEM_VOLATILE_P (op1
))
3116 op1
= force_reg (compute_mode
, op1
);
3118 /* If we need the remainder or if OP1 is constant, we need to
3119 put OP0 in a register in case it has any queued subexpressions. */
3120 if (rem_flag
|| op1_is_constant
)
3121 op0
= force_reg (compute_mode
, op0
);
3123 last
= get_last_insn ();
3125 /* Promote floor rounding to trunc rounding for unsigned operations. */
3128 if (code
== FLOOR_DIV_EXPR
)
3129 code
= TRUNC_DIV_EXPR
;
3130 if (code
== FLOOR_MOD_EXPR
)
3131 code
= TRUNC_MOD_EXPR
;
3132 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3133 code
= TRUNC_DIV_EXPR
;
3136 if (op1
!= const0_rtx
)
3139 case TRUNC_MOD_EXPR
:
3140 case TRUNC_DIV_EXPR
:
3141 if (op1_is_constant
)
3145 unsigned HOST_WIDE_INT mh
, ml
;
3146 int pre_shift
, post_shift
;
3148 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3150 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3152 pre_shift
= floor_log2 (d
);
3156 = expand_binop (compute_mode
, and_optab
, op0
,
3157 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3161 return gen_lowpart (mode
, remainder
);
3163 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3164 build_int_2 (pre_shift
, 0),
3167 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3169 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3171 /* Most significant bit of divisor is set; emit an scc
3173 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3174 compute_mode
, 1, 1);
3180 /* Find a suitable multiplier and right shift count
3181 instead of multiplying with D. */
3183 mh
= choose_multiplier (d
, size
, size
,
3184 &ml
, &post_shift
, &dummy
);
3186 /* If the suggested multiplier is more than SIZE bits,
3187 we can do better for even divisors, using an
3188 initial right shift. */
3189 if (mh
!= 0 && (d
& 1) == 0)
3191 pre_shift
= floor_log2 (d
& -d
);
3192 mh
= choose_multiplier (d
>> pre_shift
, size
,
3194 &ml
, &post_shift
, &dummy
);
3205 if (post_shift
- 1 >= BITS_PER_WORD
)
3208 extra_cost
= (shift_cost
[post_shift
- 1]
3209 + shift_cost
[1] + 2 * add_cost
);
3210 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3212 max_cost
- extra_cost
);
3215 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
3218 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3219 build_int_2 (1, 0), NULL_RTX
,1);
3220 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
3224 = expand_shift (RSHIFT_EXPR
, compute_mode
, t4
,
3225 build_int_2 (post_shift
- 1, 0),
3232 if (pre_shift
>= BITS_PER_WORD
3233 || post_shift
>= BITS_PER_WORD
)
3236 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3237 build_int_2 (pre_shift
, 0),
3239 extra_cost
= (shift_cost
[pre_shift
]
3240 + shift_cost
[post_shift
]);
3241 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
3243 max_cost
- extra_cost
);
3247 = expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3248 build_int_2 (post_shift
, 0),
3253 else /* Too wide mode to use tricky code */
3256 insn
= get_last_insn ();
3258 && (set
= single_set (insn
)) != 0
3259 && SET_DEST (set
) == quotient
)
3260 set_unique_reg_note (insn
,
3262 gen_rtx_UDIV (compute_mode
, op0
, op1
));
3264 else /* TRUNC_DIV, signed */
3266 unsigned HOST_WIDE_INT ml
;
3267 int lgup
, post_shift
;
3268 HOST_WIDE_INT d
= INTVAL (op1
);
3269 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
3271 /* n rem d = n rem -d */
3272 if (rem_flag
&& d
< 0)
3275 op1
= GEN_INT (trunc_int_for_mode (abs_d
, compute_mode
));
3281 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
3283 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3285 /* This case is not handled correctly below. */
3286 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
3287 compute_mode
, 1, 1);
3291 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
3292 && (rem_flag
? smod_pow2_cheap
: sdiv_pow2_cheap
))
3294 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
3296 lgup
= floor_log2 (abs_d
);
3297 if (BRANCH_COST
< 1 || (abs_d
!= 2 && BRANCH_COST
< 3))
3299 rtx label
= gen_label_rtx ();
3302 t1
= copy_to_mode_reg (compute_mode
, op0
);
3303 do_cmp_and_jump (t1
, const0_rtx
, GE
,
3304 compute_mode
, label
);
3305 expand_inc (t1
, GEN_INT (trunc_int_for_mode
3306 (abs_d
- 1, compute_mode
)));
3308 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3309 build_int_2 (lgup
, 0),
3315 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3316 build_int_2 (size
- 1, 0),
3318 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3319 build_int_2 (size
- lgup
, 0),
3321 t3
= force_operand (gen_rtx_PLUS (compute_mode
,
3324 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3325 build_int_2 (lgup
, 0),
3329 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3333 insn
= get_last_insn ();
3335 && (set
= single_set (insn
)) != 0
3336 && SET_DEST (set
) == quotient
3337 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
3338 << (HOST_BITS_PER_WIDE_INT
- 1)))
3339 set_unique_reg_note (insn
,
3341 gen_rtx_DIV (compute_mode
,
3348 quotient
= expand_unop (compute_mode
, neg_optab
,
3349 quotient
, quotient
, 0);
3352 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3354 choose_multiplier (abs_d
, size
, size
- 1,
3355 &ml
, &post_shift
, &lgup
);
3356 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3360 if (post_shift
>= BITS_PER_WORD
3361 || size
- 1 >= BITS_PER_WORD
)
3364 extra_cost
= (shift_cost
[post_shift
]
3365 + shift_cost
[size
- 1] + add_cost
);
3366 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3368 max_cost
- extra_cost
);
3371 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3372 build_int_2 (post_shift
, 0), NULL_RTX
, 0);
3373 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3374 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3377 = force_operand (gen_rtx_MINUS (compute_mode
,
3382 = force_operand (gen_rtx_MINUS (compute_mode
,
3390 if (post_shift
>= BITS_PER_WORD
3391 || size
- 1 >= BITS_PER_WORD
)
3394 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
3395 extra_cost
= (shift_cost
[post_shift
]
3396 + shift_cost
[size
- 1] + 2 * add_cost
);
3397 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3399 max_cost
- extra_cost
);
3402 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
3405 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3406 build_int_2 (post_shift
, 0),
3408 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3409 build_int_2 (size
- 1, 0),
3413 = force_operand (gen_rtx_MINUS (compute_mode
,
3418 = force_operand (gen_rtx_MINUS (compute_mode
,
3423 else /* Too wide mode to use tricky code */
3426 insn
= get_last_insn ();
3428 && (set
= single_set (insn
)) != 0
3429 && SET_DEST (set
) == quotient
)
3430 set_unique_reg_note (insn
,
3432 gen_rtx_DIV (compute_mode
, op0
, op1
));
3437 delete_insns_since (last
);
3440 case FLOOR_DIV_EXPR
:
3441 case FLOOR_MOD_EXPR
:
3442 /* We will come here only for signed operations. */
3443 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3445 unsigned HOST_WIDE_INT mh
, ml
;
3446 int pre_shift
, lgup
, post_shift
;
3447 HOST_WIDE_INT d
= INTVAL (op1
);
3451 /* We could just as easily deal with negative constants here,
3452 but it does not seem worth the trouble for GCC 2.6. */
3453 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3455 pre_shift
= floor_log2 (d
);
3458 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
3459 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3460 remainder
, 0, OPTAB_LIB_WIDEN
);
3462 return gen_lowpart (mode
, remainder
);
3464 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3465 build_int_2 (pre_shift
, 0),
3472 mh
= choose_multiplier (d
, size
, size
- 1,
3473 &ml
, &post_shift
, &lgup
);
3477 if (post_shift
< BITS_PER_WORD
3478 && size
- 1 < BITS_PER_WORD
)
3480 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3481 build_int_2 (size
- 1, 0),
3483 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
3484 NULL_RTX
, 0, OPTAB_WIDEN
);
3485 extra_cost
= (shift_cost
[post_shift
]
3486 + shift_cost
[size
- 1] + 2 * add_cost
);
3487 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
3489 max_cost
- extra_cost
);
3492 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3493 build_int_2 (post_shift
, 0),
3495 quotient
= expand_binop (compute_mode
, xor_optab
,
3496 t4
, t1
, tquotient
, 0,
3504 rtx nsign
, t1
, t2
, t3
, t4
;
3505 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
3506 op0
, constm1_rtx
), NULL_RTX
);
3507 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
3509 nsign
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3510 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3511 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
3513 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
3518 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
3520 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3529 delete_insns_since (last
);
3531 /* Try using an instruction that produces both the quotient and
3532 remainder, using truncation. We can easily compensate the quotient
3533 or remainder to get floor rounding, once we have the remainder.
3534 Notice that we compute also the final remainder value here,
3535 and return the result right away. */
3536 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3537 target
= gen_reg_rtx (compute_mode
);
3542 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3543 quotient
= gen_reg_rtx (compute_mode
);
3548 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3549 remainder
= gen_reg_rtx (compute_mode
);
3552 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
3553 quotient
, remainder
, 0))
3555 /* This could be computed with a branch-less sequence.
3556 Save that for later. */
3558 rtx label
= gen_label_rtx ();
3559 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
3560 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3561 NULL_RTX
, 0, OPTAB_WIDEN
);
3562 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
3563 expand_dec (quotient
, const1_rtx
);
3564 expand_inc (remainder
, op1
);
3566 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3569 /* No luck with division elimination or divmod. Have to do it
3570 by conditionally adjusting op0 *and* the result. */
3572 rtx label1
, label2
, label3
, label4
, label5
;
3576 quotient
= gen_reg_rtx (compute_mode
);
3577 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3578 label1
= gen_label_rtx ();
3579 label2
= gen_label_rtx ();
3580 label3
= gen_label_rtx ();
3581 label4
= gen_label_rtx ();
3582 label5
= gen_label_rtx ();
3583 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3584 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
3585 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3586 quotient
, 0, OPTAB_LIB_WIDEN
);
3587 if (tem
!= quotient
)
3588 emit_move_insn (quotient
, tem
);
3589 emit_jump_insn (gen_jump (label5
));
3591 emit_label (label1
);
3592 expand_inc (adjusted_op0
, const1_rtx
);
3593 emit_jump_insn (gen_jump (label4
));
3595 emit_label (label2
);
3596 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
3597 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3598 quotient
, 0, OPTAB_LIB_WIDEN
);
3599 if (tem
!= quotient
)
3600 emit_move_insn (quotient
, tem
);
3601 emit_jump_insn (gen_jump (label5
));
3603 emit_label (label3
);
3604 expand_dec (adjusted_op0
, const1_rtx
);
3605 emit_label (label4
);
3606 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3607 quotient
, 0, OPTAB_LIB_WIDEN
);
3608 if (tem
!= quotient
)
3609 emit_move_insn (quotient
, tem
);
3610 expand_dec (quotient
, const1_rtx
);
3611 emit_label (label5
);
3619 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
3622 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3623 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3624 build_int_2 (floor_log2 (d
), 0),
3626 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3628 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3629 t3
= gen_reg_rtx (compute_mode
);
3630 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3631 compute_mode
, 1, 1);
3635 lab
= gen_label_rtx ();
3636 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3637 expand_inc (t1
, const1_rtx
);
3642 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3648 /* Try using an instruction that produces both the quotient and
3649 remainder, using truncation. We can easily compensate the
3650 quotient or remainder to get ceiling rounding, once we have the
3651 remainder. Notice that we compute also the final remainder
3652 value here, and return the result right away. */
3653 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3654 target
= gen_reg_rtx (compute_mode
);
3658 remainder
= (GET_CODE (target
) == REG
3659 ? target
: gen_reg_rtx (compute_mode
));
3660 quotient
= gen_reg_rtx (compute_mode
);
3664 quotient
= (GET_CODE (target
) == REG
3665 ? target
: gen_reg_rtx (compute_mode
));
3666 remainder
= gen_reg_rtx (compute_mode
);
3669 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
3672 /* This could be computed with a branch-less sequence.
3673 Save that for later. */
3674 rtx label
= gen_label_rtx ();
3675 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3676 compute_mode
, label
);
3677 expand_inc (quotient
, const1_rtx
);
3678 expand_dec (remainder
, op1
);
3680 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3683 /* No luck with division elimination or divmod. Have to do it
3684 by conditionally adjusting op0 *and* the result. */
3687 rtx adjusted_op0
, tem
;
3689 quotient
= gen_reg_rtx (compute_mode
);
3690 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3691 label1
= gen_label_rtx ();
3692 label2
= gen_label_rtx ();
3693 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
3694 compute_mode
, label1
);
3695 emit_move_insn (quotient
, const0_rtx
);
3696 emit_jump_insn (gen_jump (label2
));
3698 emit_label (label1
);
3699 expand_dec (adjusted_op0
, const1_rtx
);
3700 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
3701 quotient
, 1, OPTAB_LIB_WIDEN
);
3702 if (tem
!= quotient
)
3703 emit_move_insn (quotient
, tem
);
3704 expand_inc (quotient
, const1_rtx
);
3705 emit_label (label2
);
3710 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3711 && INTVAL (op1
) >= 0)
3713 /* This is extremely similar to the code for the unsigned case
3714 above. For 2.7 we should merge these variants, but for
3715 2.6.1 I don't want to touch the code for unsigned since that
3716 get used in C. The signed case will only be used by other
3720 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3721 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3722 build_int_2 (floor_log2 (d
), 0),
3724 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3726 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3727 t3
= gen_reg_rtx (compute_mode
);
3728 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3729 compute_mode
, 1, 1);
3733 lab
= gen_label_rtx ();
3734 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3735 expand_inc (t1
, const1_rtx
);
3740 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3746 /* Try using an instruction that produces both the quotient and
3747 remainder, using truncation. We can easily compensate the
3748 quotient or remainder to get ceiling rounding, once we have the
3749 remainder. Notice that we compute also the final remainder
3750 value here, and return the result right away. */
3751 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3752 target
= gen_reg_rtx (compute_mode
);
3755 remainder
= (GET_CODE (target
) == REG
3756 ? target
: gen_reg_rtx (compute_mode
));
3757 quotient
= gen_reg_rtx (compute_mode
);
3761 quotient
= (GET_CODE (target
) == REG
3762 ? target
: gen_reg_rtx (compute_mode
));
3763 remainder
= gen_reg_rtx (compute_mode
);
3766 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
3769 /* This could be computed with a branch-less sequence.
3770 Save that for later. */
3772 rtx label
= gen_label_rtx ();
3773 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3774 compute_mode
, label
);
3775 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3776 NULL_RTX
, 0, OPTAB_WIDEN
);
3777 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
3778 expand_inc (quotient
, const1_rtx
);
3779 expand_dec (remainder
, op1
);
3781 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3784 /* No luck with division elimination or divmod. Have to do it
3785 by conditionally adjusting op0 *and* the result. */
3787 rtx label1
, label2
, label3
, label4
, label5
;
3791 quotient
= gen_reg_rtx (compute_mode
);
3792 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3793 label1
= gen_label_rtx ();
3794 label2
= gen_label_rtx ();
3795 label3
= gen_label_rtx ();
3796 label4
= gen_label_rtx ();
3797 label5
= gen_label_rtx ();
3798 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3799 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
3800 compute_mode
, label1
);
3801 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3802 quotient
, 0, OPTAB_LIB_WIDEN
);
3803 if (tem
!= quotient
)
3804 emit_move_insn (quotient
, tem
);
3805 emit_jump_insn (gen_jump (label5
));
3807 emit_label (label1
);
3808 expand_dec (adjusted_op0
, const1_rtx
);
3809 emit_jump_insn (gen_jump (label4
));
3811 emit_label (label2
);
3812 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
3813 compute_mode
, label3
);
3814 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3815 quotient
, 0, OPTAB_LIB_WIDEN
);
3816 if (tem
!= quotient
)
3817 emit_move_insn (quotient
, tem
);
3818 emit_jump_insn (gen_jump (label5
));
3820 emit_label (label3
);
3821 expand_inc (adjusted_op0
, const1_rtx
);
3822 emit_label (label4
);
3823 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3824 quotient
, 0, OPTAB_LIB_WIDEN
);
3825 if (tem
!= quotient
)
3826 emit_move_insn (quotient
, tem
);
3827 expand_inc (quotient
, const1_rtx
);
3828 emit_label (label5
);
3833 case EXACT_DIV_EXPR
:
3834 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3836 HOST_WIDE_INT d
= INTVAL (op1
);
3837 unsigned HOST_WIDE_INT ml
;
3841 pre_shift
= floor_log2 (d
& -d
);
3842 ml
= invert_mod2n (d
>> pre_shift
, size
);
3843 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3844 build_int_2 (pre_shift
, 0), NULL_RTX
, unsignedp
);
3845 quotient
= expand_mult (compute_mode
, t1
,
3846 GEN_INT (trunc_int_for_mode
3847 (ml
, compute_mode
)),
3850 insn
= get_last_insn ();
3851 set_unique_reg_note (insn
,
3853 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
3859 case ROUND_DIV_EXPR
:
3860 case ROUND_MOD_EXPR
:
3865 label
= gen_label_rtx ();
3866 quotient
= gen_reg_rtx (compute_mode
);
3867 remainder
= gen_reg_rtx (compute_mode
);
3868 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
3871 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
3872 quotient
, 1, OPTAB_LIB_WIDEN
);
3873 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
3874 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3875 remainder
, 1, OPTAB_LIB_WIDEN
);
3877 tem
= plus_constant (op1
, -1);
3878 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3879 build_int_2 (1, 0), NULL_RTX
, 1);
3880 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
3881 expand_inc (quotient
, const1_rtx
);
3882 expand_dec (remainder
, op1
);
3887 rtx abs_rem
, abs_op1
, tem
, mask
;
3889 label
= gen_label_rtx ();
3890 quotient
= gen_reg_rtx (compute_mode
);
3891 remainder
= gen_reg_rtx (compute_mode
);
3892 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
3895 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
3896 quotient
, 0, OPTAB_LIB_WIDEN
);
3897 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
3898 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3899 remainder
, 0, OPTAB_LIB_WIDEN
);
3901 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
3902 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
3903 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
3904 build_int_2 (1, 0), NULL_RTX
, 1);
3905 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
3906 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3907 NULL_RTX
, 0, OPTAB_WIDEN
);
3908 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3909 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3910 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
3911 NULL_RTX
, 0, OPTAB_WIDEN
);
3912 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3913 NULL_RTX
, 0, OPTAB_WIDEN
);
3914 expand_inc (quotient
, tem
);
3915 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
3916 NULL_RTX
, 0, OPTAB_WIDEN
);
3917 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3918 NULL_RTX
, 0, OPTAB_WIDEN
);
3919 expand_dec (remainder
, tem
);
3922 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3930 if (target
&& GET_MODE (target
) != compute_mode
)
3935 /* Try to produce the remainder without producing the quotient.
3936 If we seem to have a divmod patten that does not require widening,
3937 don't try windening here. We should really have an WIDEN argument
3938 to expand_twoval_binop, since what we'd really like to do here is
3939 1) try a mod insn in compute_mode
3940 2) try a divmod insn in compute_mode
3941 3) try a div insn in compute_mode and multiply-subtract to get
3943 4) try the same things with widening allowed. */
3945 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
3948 ((optab2
->handlers
[(int) compute_mode
].insn_code
3949 != CODE_FOR_nothing
)
3950 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3953 /* No luck there. Can we do remainder and divide at once
3954 without a library call? */
3955 remainder
= gen_reg_rtx (compute_mode
);
3956 if (! expand_twoval_binop ((unsignedp
3960 NULL_RTX
, remainder
, unsignedp
))
3965 return gen_lowpart (mode
, remainder
);
3968 /* Produce the quotient. Try a quotient insn, but not a library call.
3969 If we have a divmod in this mode, use it in preference to widening
3970 the div (for this test we assume it will not fail). Note that optab2
3971 is set to the one of the two optabs that the call below will use. */
3973 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
3974 op0
, op1
, rem_flag
? NULL_RTX
: target
,
3976 ((optab2
->handlers
[(int) compute_mode
].insn_code
3977 != CODE_FOR_nothing
)
3978 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3982 /* No luck there. Try a quotient-and-remainder insn,
3983 keeping the quotient alone. */
3984 quotient
= gen_reg_rtx (compute_mode
);
3985 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
3987 quotient
, NULL_RTX
, unsignedp
))
3991 /* Still no luck. If we are not computing the remainder,
3992 use a library call for the quotient. */
3993 quotient
= sign_expand_binop (compute_mode
,
3994 udiv_optab
, sdiv_optab
,
3996 unsignedp
, OPTAB_LIB_WIDEN
);
4003 if (target
&& GET_MODE (target
) != compute_mode
)
4007 /* No divide instruction either. Use library for remainder. */
4008 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4010 unsignedp
, OPTAB_LIB_WIDEN
);
4013 /* We divided. Now finish doing X - Y * (X / Y). */
4014 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4015 NULL_RTX
, unsignedp
);
4016 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4017 remainder
, target
, unsignedp
,
4022 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4025 /* Return a tree node with data type TYPE, describing the value of X.
4026 Usually this is an RTL_EXPR, if there is no obvious better choice.
4027 X may be an expression, however we only support those expressions
4028 generated by loop.c. */
4037 switch (GET_CODE (x
))
4040 t
= build_int_2 (INTVAL (x
),
4041 (TREE_UNSIGNED (type
)
4042 && (GET_MODE_BITSIZE (TYPE_MODE (type
)) < HOST_BITS_PER_WIDE_INT
))
4043 || INTVAL (x
) >= 0 ? 0 : -1);
4044 TREE_TYPE (t
) = type
;
4048 if (GET_MODE (x
) == VOIDmode
)
4050 t
= build_int_2 (CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4051 TREE_TYPE (t
) = type
;
4057 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4058 t
= build_real (type
, d
);
4064 return fold (build (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4065 make_tree (type
, XEXP (x
, 1))));
4068 return fold (build (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4069 make_tree (type
, XEXP (x
, 1))));
4072 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
4075 return fold (build (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4076 make_tree (type
, XEXP (x
, 1))));
4079 return fold (build (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4080 make_tree (type
, XEXP (x
, 1))));
4083 return fold (convert (type
,
4084 build (RSHIFT_EXPR
, unsigned_type (type
),
4085 make_tree (unsigned_type (type
),
4087 make_tree (type
, XEXP (x
, 1)))));
4090 return fold (convert (type
,
4091 build (RSHIFT_EXPR
, signed_type (type
),
4092 make_tree (signed_type (type
), XEXP (x
, 0)),
4093 make_tree (type
, XEXP (x
, 1)))));
4096 if (TREE_CODE (type
) != REAL_TYPE
)
4097 t
= signed_type (type
);
4101 return fold (convert (type
,
4102 build (TRUNC_DIV_EXPR
, t
,
4103 make_tree (t
, XEXP (x
, 0)),
4104 make_tree (t
, XEXP (x
, 1)))));
4106 t
= unsigned_type (type
);
4107 return fold (convert (type
,
4108 build (TRUNC_DIV_EXPR
, t
,
4109 make_tree (t
, XEXP (x
, 0)),
4110 make_tree (t
, XEXP (x
, 1)))));
4112 t
= make_node (RTL_EXPR
);
4113 TREE_TYPE (t
) = type
;
4115 #ifdef POINTERS_EXTEND_UNSIGNED
4116 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4117 ptr_mode. So convert. */
4118 if (POINTER_TYPE_P (type
) && GET_MODE (x
) != TYPE_MODE (type
))
4119 x
= convert_memory_address (TYPE_MODE (type
), x
);
4122 RTL_EXPR_RTL (t
) = x
;
4123 /* There are no insns to be output
4124 when this rtl_expr is used. */
4125 RTL_EXPR_SEQUENCE (t
) = 0;
4130 /* Return an rtx representing the value of X * MULT + ADD.
4131 TARGET is a suggestion for where to store the result (an rtx).
4132 MODE is the machine mode for the computation.
4133 X and MULT must have mode MODE. ADD may have a different mode.
4134 So can X (defaults to same as MODE).
4135 UNSIGNEDP is non-zero to do unsigned multiplication.
4136 This may emit insns. */
4139 expand_mult_add (x
, target
, mult
, add
, mode
, unsignedp
)
4140 rtx x
, target
, mult
, add
;
4141 enum machine_mode mode
;
4144 tree type
= type_for_mode (mode
, unsignedp
);
4145 tree add_type
= (GET_MODE (add
) == VOIDmode
4146 ? type
: type_for_mode (GET_MODE (add
), unsignedp
));
4147 tree result
= fold (build (PLUS_EXPR
, type
,
4148 fold (build (MULT_EXPR
, type
,
4149 make_tree (type
, x
),
4150 make_tree (type
, mult
))),
4151 make_tree (add_type
, add
)));
4153 return expand_expr (result
, target
, VOIDmode
, 0);
4156 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4157 and returning TARGET.
4159 If TARGET is 0, a pseudo-register or constant is returned. */
4162 expand_and (op0
, op1
, target
)
4163 rtx op0
, op1
, target
;
4165 enum machine_mode mode
= VOIDmode
;
4168 if (GET_MODE (op0
) != VOIDmode
)
4169 mode
= GET_MODE (op0
);
4170 else if (GET_MODE (op1
) != VOIDmode
)
4171 mode
= GET_MODE (op1
);
4173 if (mode
!= VOIDmode
)
4174 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
4175 else if (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) == CONST_INT
)
4176 tem
= GEN_INT (INTVAL (op0
) & INTVAL (op1
));
4182 else if (tem
!= target
)
4183 emit_move_insn (target
, tem
);
4187 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4188 and storing in TARGET. Normally return TARGET.
4189 Return 0 if that cannot be done.
4191 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4192 it is VOIDmode, they cannot both be CONST_INT.
4194 UNSIGNEDP is for the case where we have to widen the operands
4195 to perform the operation. It says to use zero-extension.
4197 NORMALIZEP is 1 if we should convert the result to be either zero
4198 or one. Normalize is -1 if we should convert the result to be
4199 either zero or -1. If NORMALIZEP is zero, the result will be left
4200 "raw" out of the scc insn. */
4203 emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4207 enum machine_mode mode
;
4212 enum insn_code icode
;
4213 enum machine_mode compare_mode
;
4214 enum machine_mode target_mode
= GET_MODE (target
);
4216 rtx last
= get_last_insn ();
4217 rtx pattern
, comparison
;
4220 code
= unsigned_condition (code
);
4222 /* If one operand is constant, make it the second one. Only do this
4223 if the other operand is not constant as well. */
4225 if (swap_commutative_operands_p (op0
, op1
))
4230 code
= swap_condition (code
);
4233 if (mode
== VOIDmode
)
4234 mode
= GET_MODE (op0
);
4236 /* For some comparisons with 1 and -1, we can convert this to
4237 comparisons with zero. This will often produce more opportunities for
4238 store-flag insns. */
4243 if (op1
== const1_rtx
)
4244 op1
= const0_rtx
, code
= LE
;
4247 if (op1
== constm1_rtx
)
4248 op1
= const0_rtx
, code
= LT
;
4251 if (op1
== const1_rtx
)
4252 op1
= const0_rtx
, code
= GT
;
4255 if (op1
== constm1_rtx
)
4256 op1
= const0_rtx
, code
= GE
;
4259 if (op1
== const1_rtx
)
4260 op1
= const0_rtx
, code
= NE
;
4263 if (op1
== const1_rtx
)
4264 op1
= const0_rtx
, code
= EQ
;
4270 /* If we are comparing a double-word integer with zero, we can convert
4271 the comparison into one involving a single word. */
4272 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
4273 && GET_MODE_CLASS (mode
) == MODE_INT
4274 && op1
== const0_rtx
)
4276 if (code
== EQ
|| code
== NE
)
4278 /* Do a logical OR of the two words and compare the result. */
4279 rtx op0h
= gen_highpart (word_mode
, op0
);
4280 rtx op0l
= gen_lowpart (word_mode
, op0
);
4281 rtx op0both
= expand_binop (word_mode
, ior_optab
, op0h
, op0l
,
4282 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
4284 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
4285 unsignedp
, normalizep
);
4287 else if (code
== LT
|| code
== GE
)
4288 /* If testing the sign bit, can just test on high word. */
4289 return emit_store_flag (target
, code
, gen_highpart (word_mode
, op0
),
4290 op1
, word_mode
, unsignedp
, normalizep
);
4293 /* From now on, we won't change CODE, so set ICODE now. */
4294 icode
= setcc_gen_code
[(int) code
];
4296 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4297 complement of A (for GE) and shifting the sign bit to the low bit. */
4298 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
4299 && GET_MODE_CLASS (mode
) == MODE_INT
4300 && (normalizep
|| STORE_FLAG_VALUE
== 1
4301 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4302 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4303 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
4307 /* If the result is to be wider than OP0, it is best to convert it
4308 first. If it is to be narrower, it is *incorrect* to convert it
4310 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
4312 op0
= protect_from_queue (op0
, 0);
4313 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4317 if (target_mode
!= mode
)
4321 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
4322 ((STORE_FLAG_VALUE
== 1 || normalizep
)
4323 ? 0 : subtarget
), 0);
4325 if (STORE_FLAG_VALUE
== 1 || normalizep
)
4326 /* If we are supposed to produce a 0/1 value, we want to do
4327 a logical shift from the sign bit to the low-order bit; for
4328 a -1/0 value, we do an arithmetic shift. */
4329 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4330 size_int (GET_MODE_BITSIZE (mode
) - 1),
4331 subtarget
, normalizep
!= -1);
4333 if (mode
!= target_mode
)
4334 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4339 if (icode
!= CODE_FOR_nothing
)
4341 insn_operand_predicate_fn pred
;
4343 /* We think we may be able to do this with a scc insn. Emit the
4344 comparison and then the scc insn.
4346 compare_from_rtx may call emit_queue, which would be deleted below
4347 if the scc insn fails. So call it ourselves before setting LAST.
4348 Likewise for do_pending_stack_adjust. */
4351 do_pending_stack_adjust ();
4352 last
= get_last_insn ();
4355 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
, 0);
4356 if (GET_CODE (comparison
) == CONST_INT
)
4357 return (comparison
== const0_rtx
? const0_rtx
4358 : normalizep
== 1 ? const1_rtx
4359 : normalizep
== -1 ? constm1_rtx
4362 /* If the code of COMPARISON doesn't match CODE, something is
4363 wrong; we can no longer be sure that we have the operation.
4364 We could handle this case, but it should not happen. */
4366 if (GET_CODE (comparison
) != code
)
4369 /* Get a reference to the target in the proper mode for this insn. */
4370 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
4372 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
4373 if (preserve_subexpressions_p ()
4374 || ! (*pred
) (subtarget
, compare_mode
))
4375 subtarget
= gen_reg_rtx (compare_mode
);
4377 pattern
= GEN_FCN (icode
) (subtarget
);
4380 emit_insn (pattern
);
4382 /* If we are converting to a wider mode, first convert to
4383 TARGET_MODE, then normalize. This produces better combining
4384 opportunities on machines that have a SIGN_EXTRACT when we are
4385 testing a single bit. This mostly benefits the 68k.
4387 If STORE_FLAG_VALUE does not have the sign bit set when
4388 interpreted in COMPARE_MODE, we can do this conversion as
4389 unsigned, which is usually more efficient. */
4390 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
4392 convert_move (target
, subtarget
,
4393 (GET_MODE_BITSIZE (compare_mode
)
4394 <= HOST_BITS_PER_WIDE_INT
)
4395 && 0 == (STORE_FLAG_VALUE
4396 & ((HOST_WIDE_INT
) 1
4397 << (GET_MODE_BITSIZE (compare_mode
) -1))));
4399 compare_mode
= target_mode
;
4404 /* If we want to keep subexpressions around, don't reuse our
4407 if (preserve_subexpressions_p ())
4410 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4411 we don't have to do anything. */
4412 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
4414 /* STORE_FLAG_VALUE might be the most negative number, so write
4415 the comparison this way to avoid a compiler-time warning. */
4416 else if (- normalizep
== STORE_FLAG_VALUE
)
4417 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
4419 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4420 makes it hard to use a value of just the sign bit due to
4421 ANSI integer constant typing rules. */
4422 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
4423 && (STORE_FLAG_VALUE
4424 & ((HOST_WIDE_INT
) 1
4425 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
4426 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
4427 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
4428 subtarget
, normalizep
== 1);
4429 else if (STORE_FLAG_VALUE
& 1)
4431 op0
= expand_and (op0
, const1_rtx
, subtarget
);
4432 if (normalizep
== -1)
4433 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
4438 /* If we were converting to a smaller mode, do the
4440 if (target_mode
!= compare_mode
)
4442 convert_move (target
, op0
, 0);
4450 delete_insns_since (last
);
4452 /* If expensive optimizations, use different pseudo registers for each
4453 insn, instead of reusing the same pseudo. This leads to better CSE,
4454 but slows down the compiler, since there are more pseudos */
4455 subtarget
= (!flag_expensive_optimizations
4456 && (target_mode
== mode
)) ? target
: NULL_RTX
;
4458 /* If we reached here, we can't do this with a scc insn. However, there
4459 are some comparisons that can be done directly. For example, if
4460 this is an equality comparison of integers, we can try to exclusive-or
4461 (or subtract) the two operands and use a recursive call to try the
4462 comparison with zero. Don't do any of these cases if branches are
4466 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
4467 && op1
!= const0_rtx
)
4469 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
4473 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
4476 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
4477 mode
, unsignedp
, normalizep
);
4479 delete_insns_since (last
);
4483 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4484 the constant zero. Reject all other comparisons at this point. Only
4485 do LE and GT if branches are expensive since they are expensive on
4486 2-operand machines. */
4488 if (BRANCH_COST
== 0
4489 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
4490 || (code
!= EQ
&& code
!= NE
4491 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
4494 /* See what we need to return. We can only return a 1, -1, or the
4497 if (normalizep
== 0)
4499 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4500 normalizep
= STORE_FLAG_VALUE
;
4502 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4503 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4504 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
4510 /* Try to put the result of the comparison in the sign bit. Assume we can't
4511 do the necessary operation below. */
4515 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4516 the sign bit set. */
4520 /* This is destructive, so SUBTARGET can't be OP0. */
4521 if (rtx_equal_p (subtarget
, op0
))
4524 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
4527 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
4531 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4532 number of bits in the mode of OP0, minus one. */
4536 if (rtx_equal_p (subtarget
, op0
))
4539 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4540 size_int (GET_MODE_BITSIZE (mode
) - 1),
4542 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
4546 if (code
== EQ
|| code
== NE
)
4548 /* For EQ or NE, one way to do the comparison is to apply an operation
4549 that converts the operand into a positive number if it is non-zero
4550 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4551 for NE we negate. This puts the result in the sign bit. Then we
4552 normalize with a shift, if needed.
4554 Two operations that can do the above actions are ABS and FFS, so try
4555 them. If that doesn't work, and MODE is smaller than a full word,
4556 we can use zero-extension to the wider mode (an unsigned conversion)
4557 as the operation. */
4559 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4560 that is compensated by the subsequent overflow when subtracting
4563 if (abs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4564 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
4565 else if (ffs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4566 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
4567 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
4569 op0
= protect_from_queue (op0
, 0);
4570 tem
= convert_modes (word_mode
, mode
, op0
, 1);
4577 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
4580 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
4583 /* If we couldn't do it that way, for NE we can "or" the two's complement
4584 of the value with itself. For EQ, we take the one's complement of
4585 that "or", which is an extra insn, so we only handle EQ if branches
4588 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
4590 if (rtx_equal_p (subtarget
, op0
))
4593 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
4594 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
4597 if (tem
&& code
== EQ
)
4598 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
4602 if (tem
&& normalizep
)
4603 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
4604 size_int (GET_MODE_BITSIZE (mode
) - 1),
4605 subtarget
, normalizep
== 1);
4609 if (GET_MODE (tem
) != target_mode
)
4611 convert_move (target
, tem
, 0);
4614 else if (!subtarget
)
4616 emit_move_insn (target
, tem
);
4621 delete_insns_since (last
);
4626 /* Like emit_store_flag, but always succeeds. */
4629 emit_store_flag_force (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4633 enum machine_mode mode
;
4639 /* First see if emit_store_flag can do the job. */
4640 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
4644 if (normalizep
== 0)
4647 /* If this failed, we have to do this with set/compare/jump/set code. */
4649 if (GET_CODE (target
) != REG
4650 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
4651 target
= gen_reg_rtx (GET_MODE (target
));
4653 emit_move_insn (target
, const1_rtx
);
4654 label
= gen_label_rtx ();
4655 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
, 0,
4658 emit_move_insn (target
, const0_rtx
);
4664 /* Perform possibly multi-word comparison and conditional jump to LABEL
4665 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4667 The algorithm is based on the code in expr.c:do_jump.
4669 Note that this does not perform a general comparison. Only variants
4670 generated within expmed.c are correctly handled, others abort (but could
4671 be handled if needed). */
4674 do_cmp_and_jump (arg1
, arg2
, op
, mode
, label
)
4675 rtx arg1
, arg2
, label
;
4677 enum machine_mode mode
;
4679 /* If this mode is an integer too wide to compare properly,
4680 compare word by word. Rely on cse to optimize constant cases. */
4682 if (GET_MODE_CLASS (mode
) == MODE_INT
4683 && ! can_compare_p (op
, mode
, ccp_jump
))
4685 rtx label2
= gen_label_rtx ();
4690 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
4694 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
4698 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
4702 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
4706 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
4709 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4710 that's the only equality operations we do */
4712 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4714 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
4718 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4720 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
4727 emit_label (label2
);
4731 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, 0, label
);