1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
86 #include "insn-codes.h"
88 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
90 #include "insn-attr.h"
95 /* It is not safe to use ordinary gen_lowpart in combine.
96 Use gen_lowpart_for_combine instead. See comments there. */
97 #define gen_lowpart dont_use_gen_lowpart_you_dummy
99 /* Number of attempts to combine instructions in this function. */
101 static int combine_attempts
;
103 /* Number of attempts that got as far as substitution in this function. */
105 static int combine_merges
;
107 /* Number of instructions combined with added SETs in this function. */
109 static int combine_extras
;
111 /* Number of instructions combined in this function. */
113 static int combine_successes
;
115 /* Totals over entire compilation. */
117 static int total_attempts
, total_merges
, total_extras
, total_successes
;
120 /* Vector mapping INSN_UIDs to cuids.
121 The cuids are like uids but increase monotonically always.
122 Combine always uses cuids so that it can compare them.
123 But actually renumbering the uids, which we used to do,
124 proves to be a bad idea because it makes it hard to compare
125 the dumps produced by earlier passes with those from later passes. */
127 static int *uid_cuid
;
128 static int max_uid_cuid
;
130 /* Get the cuid of an insn. */
132 #define INSN_CUID(INSN) \
133 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
135 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
136 BITS_PER_WORD would invoke undefined behavior. Work around it. */
138 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
139 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
141 /* Maximum register number, which is the size of the tables below. */
143 static unsigned int combine_max_regno
;
145 /* Record last point of death of (hard or pseudo) register n. */
147 static rtx
*reg_last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
151 static rtx
*reg_last_set
;
153 /* Record the cuid of the last insn that invalidated memory
154 (anything that writes memory, and subroutine calls, but not pushes). */
156 static int mem_last_set
;
158 /* Record the cuid of the last CALL_INSN
159 so we can tell whether a potential combination crosses any calls. */
161 static int last_call_cuid
;
163 /* When `subst' is called, this is the insn that is being modified
164 (by combining in a previous insn). The PATTERN of this insn
165 is still the old pattern partially modified and it should not be
166 looked at, but this may be used to examine the successors of the insn
167 to judge whether a simplification is valid. */
169 static rtx subst_insn
;
171 /* This is an insn that belongs before subst_insn, but is not currently
172 on the insn chain. */
174 static rtx subst_prev_insn
;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid
;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs
;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn
;
196 /* Basic block number of the block in which we are performing combines. */
197 static int this_basic_block
;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks
;
203 static int need_refresh
;
205 /* The next group of arrays allows the recording of the last value assigned
206 to (hard or pseudo) register n. We use this information to see if a
207 operation being processed is redundant given a prior operation performed
208 on the register. For example, an `and' with a constant is redundant if
209 all the zero bits are already known to be turned off.
211 We use an approach similar to that used by cse, but change it in the
214 (1) We do not want to reinitialize at each label.
215 (2) It is useful, but not critical, to know the actual value assigned
216 to a register. Often just its form is helpful.
218 Therefore, we maintain the following arrays:
220 reg_last_set_value the last value assigned
221 reg_last_set_label records the value of label_tick when the
222 register was assigned
223 reg_last_set_table_tick records the value of label_tick when a
224 value using the register is assigned
225 reg_last_set_invalid set to non-zero when it is not valid
226 to use the value of this register in some
229 To understand the usage of these tables, it is important to understand
230 the distinction between the value in reg_last_set_value being valid
231 and the register being validly contained in some other expression in the
234 Entry I in reg_last_set_value is valid if it is non-zero, and either
235 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
237 Register I may validly appear in any expression returned for the value
238 of another register if reg_n_sets[i] is 1. It may also appear in the
239 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
240 reg_last_set_invalid[j] is zero.
242 If an expression is found in the table containing a register which may
243 not validly appear in an expression, the register is replaced by
244 something that won't match, (clobber (const_int 0)).
246 reg_last_set_invalid[i] is set non-zero when register I is being assigned
247 to and reg_last_set_table_tick[i] == label_tick. */
249 /* Record last value assigned to (hard or pseudo) register n. */
251 static rtx
*reg_last_set_value
;
253 /* Record the value of label_tick when the value for register n is placed in
254 reg_last_set_value[n]. */
256 static int *reg_last_set_label
;
258 /* Record the value of label_tick when an expression involving register n
259 is placed in reg_last_set_value. */
261 static int *reg_last_set_table_tick
;
263 /* Set non-zero if references to register n in expressions should not be
266 static char *reg_last_set_invalid
;
268 /* Incremented for each label. */
270 static int label_tick
;
272 /* Some registers that are set more than once and used in more than one
273 basic block are nevertheless always set in similar ways. For example,
274 a QImode register may be loaded from memory in two places on a machine
275 where byte loads zero extend.
277 We record in the following array what we know about the nonzero
278 bits of a register, specifically which bits are known to be zero.
280 If an entry is zero, it means that we don't know anything special. */
282 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
284 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
285 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
287 static enum machine_mode nonzero_bits_mode
;
289 /* Nonzero if we know that a register has some leading bits that are always
290 equal to the sign bit. */
292 static unsigned char *reg_sign_bit_copies
;
294 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
295 It is zero while computing them and after combine has completed. This
296 former test prevents propagating values based on previously set values,
297 which can be incorrect if a variable is modified in a loop. */
299 static int nonzero_sign_valid
;
301 /* These arrays are maintained in parallel with reg_last_set_value
302 and are used to store the mode in which the register was last set,
303 the bits that were known to be zero when it was last set, and the
304 number of sign bits copies it was known to have when it was last set. */
306 static enum machine_mode
*reg_last_set_mode
;
307 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
308 static char *reg_last_set_sign_bit_copies
;
310 /* Record one modification to rtl structure
311 to be undone by storing old_contents into *where.
312 is_int is 1 if the contents are an int. */
318 union {rtx r
; unsigned int i
;} old_contents
;
319 union {rtx
*r
; unsigned int *i
;} where
;
322 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
323 num_undo says how many are currently recorded.
325 other_insn is nonzero if we have modified some other insn in the process
326 of working on subst_insn. It must be verified too. */
335 static struct undobuf undobuf
;
337 /* Number of times the pseudo being substituted for
338 was found and replaced. */
340 static int n_occurrences
;
342 static void do_SUBST
PARAMS ((rtx
*, rtx
));
343 static void do_SUBST_INT
PARAMS ((unsigned int *,
345 static void init_reg_last_arrays
PARAMS ((void));
346 static void setup_incoming_promotions
PARAMS ((void));
347 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
348 static int cant_combine_insn_p
PARAMS ((rtx
));
349 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
350 static int sets_function_arg_p
PARAMS ((rtx
));
351 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
352 static int contains_muldiv
PARAMS ((rtx
));
353 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
354 static void undo_all
PARAMS ((void));
355 static void undo_commit
PARAMS ((void));
356 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
357 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
358 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
359 static rtx simplify_if_then_else
PARAMS ((rtx
));
360 static rtx simplify_set
PARAMS ((rtx
));
361 static rtx simplify_logical
PARAMS ((rtx
, int));
362 static rtx expand_compound_operation
PARAMS ((rtx
));
363 static rtx expand_field_assignment
PARAMS ((rtx
));
364 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
365 rtx
, unsigned HOST_WIDE_INT
, int,
367 static rtx extract_left_shift
PARAMS ((rtx
, int));
368 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
369 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
370 unsigned HOST_WIDE_INT
*));
371 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
372 unsigned HOST_WIDE_INT
, rtx
, int));
373 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
374 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
375 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
376 static rtx make_field_assignment
PARAMS ((rtx
));
377 static rtx apply_distributive_law
PARAMS ((rtx
));
378 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
379 unsigned HOST_WIDE_INT
));
380 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
381 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
382 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
383 enum rtx_code
, HOST_WIDE_INT
,
384 enum machine_mode
, int *));
385 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
387 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
388 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
389 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
391 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
392 static void update_table_tick
PARAMS ((rtx
));
393 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
394 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
395 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
396 static void record_dead_and_set_regs
PARAMS ((rtx
));
397 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
398 static rtx get_last_value
PARAMS ((rtx
));
399 static int use_crosses_set_p
PARAMS ((rtx
, int));
400 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
401 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
402 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
403 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
404 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
405 static void distribute_links
PARAMS ((rtx
));
406 static void mark_used_regs_combine
PARAMS ((rtx
));
407 static int insn_cuid
PARAMS ((rtx
));
408 static void record_promoted_value
PARAMS ((rtx
, rtx
));
409 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
410 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
412 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
413 insn. The substitution can be undone by undo_all. If INTO is already
414 set to NEWVAL, do not record this change. Because computing NEWVAL might
415 also call SUBST, we have to compute it before we put anything into
419 do_SUBST (into
, newval
)
425 if (oldval
== newval
)
429 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
431 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
435 buf
->old_contents
.r
= oldval
;
438 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
441 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
443 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
444 for the value of a HOST_WIDE_INT value (including CONST_INT) is
448 do_SUBST_INT (into
, newval
)
449 unsigned int *into
, newval
;
452 unsigned int oldval
= *into
;
454 if (oldval
== newval
)
458 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
460 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
464 buf
->old_contents
.i
= oldval
;
467 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
470 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
472 /* Main entry point for combiner. F is the first insn of the function.
473 NREGS is the first unused pseudo-reg number.
475 Return non-zero if the combiner has turned an indirect jump
476 instruction into a direct jump. */
478 combine_instructions (f
, nregs
)
482 register rtx insn
, next
;
487 register rtx links
, nextlinks
;
489 int new_direct_jump_p
= 0;
491 combine_attempts
= 0;
494 combine_successes
= 0;
496 combine_max_regno
= nregs
;
498 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
499 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
501 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
503 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
504 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
505 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
506 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
507 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
508 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
510 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
511 reg_last_set_nonzero_bits
512 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
513 reg_last_set_sign_bit_copies
514 = (char *) xmalloc (nregs
* sizeof (char));
516 init_reg_last_arrays ();
518 init_recog_no_volatile ();
520 /* Compute maximum uid value so uid_cuid can be allocated. */
522 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
523 if (INSN_UID (insn
) > i
)
526 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
529 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
531 /* Don't use reg_nonzero_bits when computing it. This can cause problems
532 when, for example, we have j <<= 1 in a loop. */
534 nonzero_sign_valid
= 0;
536 /* Compute the mapping from uids to cuids.
537 Cuids are numbers assigned to insns, like uids,
538 except that cuids increase monotonically through the code.
540 Scan all SETs and see if we can deduce anything about what
541 bits are known to be zero for some registers and how many copies
542 of the sign bit are known to exist for those registers.
544 Also set any known values so that we can use it while searching
545 for what bits are known to be set. */
549 /* We need to initialize it here, because record_dead_and_set_regs may call
551 subst_prev_insn
= NULL_RTX
;
553 setup_incoming_promotions ();
555 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
556 sbitmap_zero (refresh_blocks
);
559 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
561 uid_cuid
[INSN_UID (insn
)] = ++i
;
567 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
569 record_dead_and_set_regs (insn
);
572 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
573 if (REG_NOTE_KIND (links
) == REG_INC
)
574 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
579 if (GET_CODE (insn
) == CODE_LABEL
)
583 nonzero_sign_valid
= 1;
585 /* Now scan all the insns in forward order. */
587 this_basic_block
= -1;
591 init_reg_last_arrays ();
592 setup_incoming_promotions ();
594 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
598 /* If INSN starts a new basic block, update our basic block number. */
599 if (this_basic_block
+ 1 < n_basic_blocks
600 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
603 if (GET_CODE (insn
) == CODE_LABEL
)
606 else if (INSN_P (insn
))
608 /* See if we know about function return values before this
609 insn based upon SUBREG flags. */
610 check_promoted_subreg (insn
, PATTERN (insn
));
612 /* Try this insn with each insn it links back to. */
614 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
615 if ((next
= try_combine (insn
, XEXP (links
, 0),
616 NULL_RTX
, &new_direct_jump_p
)) != 0)
619 /* Try each sequence of three linked insns ending with this one. */
621 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
623 rtx link
= XEXP (links
, 0);
625 /* If the linked insn has been replaced by a note, then there
626 is no point in persuing this chain any further. */
627 if (GET_CODE (link
) == NOTE
)
630 for (nextlinks
= LOG_LINKS (link
);
632 nextlinks
= XEXP (nextlinks
, 1))
633 if ((next
= try_combine (insn
, XEXP (links
, 0),
635 &new_direct_jump_p
)) != 0)
640 /* Try to combine a jump insn that uses CC0
641 with a preceding insn that sets CC0, and maybe with its
642 logical predecessor as well.
643 This is how we make decrement-and-branch insns.
644 We need this special code because data flow connections
645 via CC0 do not get entered in LOG_LINKS. */
647 if (GET_CODE (insn
) == JUMP_INSN
648 && (prev
= prev_nonnote_insn (insn
)) != 0
649 && GET_CODE (prev
) == INSN
650 && sets_cc0_p (PATTERN (prev
)))
652 if ((next
= try_combine (insn
, prev
,
653 NULL_RTX
, &new_direct_jump_p
)) != 0)
656 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
657 nextlinks
= XEXP (nextlinks
, 1))
658 if ((next
= try_combine (insn
, prev
,
660 &new_direct_jump_p
)) != 0)
664 /* Do the same for an insn that explicitly references CC0. */
665 if (GET_CODE (insn
) == INSN
666 && (prev
= prev_nonnote_insn (insn
)) != 0
667 && GET_CODE (prev
) == INSN
668 && sets_cc0_p (PATTERN (prev
))
669 && GET_CODE (PATTERN (insn
)) == SET
670 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
672 if ((next
= try_combine (insn
, prev
,
673 NULL_RTX
, &new_direct_jump_p
)) != 0)
676 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
677 nextlinks
= XEXP (nextlinks
, 1))
678 if ((next
= try_combine (insn
, prev
,
680 &new_direct_jump_p
)) != 0)
684 /* Finally, see if any of the insns that this insn links to
685 explicitly references CC0. If so, try this insn, that insn,
686 and its predecessor if it sets CC0. */
687 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
688 if (GET_CODE (XEXP (links
, 0)) == INSN
689 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
690 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
691 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
692 && GET_CODE (prev
) == INSN
693 && sets_cc0_p (PATTERN (prev
))
694 && (next
= try_combine (insn
, XEXP (links
, 0),
695 prev
, &new_direct_jump_p
)) != 0)
699 /* Try combining an insn with two different insns whose results it
701 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
702 for (nextlinks
= XEXP (links
, 1); nextlinks
;
703 nextlinks
= XEXP (nextlinks
, 1))
704 if ((next
= try_combine (insn
, XEXP (links
, 0),
706 &new_direct_jump_p
)) != 0)
709 if (GET_CODE (insn
) != NOTE
)
710 record_dead_and_set_regs (insn
);
717 delete_noop_moves (f
);
721 compute_bb_for_insn (get_max_uid ());
722 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
727 sbitmap_free (refresh_blocks
);
728 free (reg_nonzero_bits
);
729 free (reg_sign_bit_copies
);
730 free (reg_last_death
);
732 free (reg_last_set_value
);
733 free (reg_last_set_table_tick
);
734 free (reg_last_set_label
);
735 free (reg_last_set_invalid
);
736 free (reg_last_set_mode
);
737 free (reg_last_set_nonzero_bits
);
738 free (reg_last_set_sign_bit_copies
);
742 struct undo
*undo
, *next
;
743 for (undo
= undobuf
.frees
; undo
; undo
= next
)
751 total_attempts
+= combine_attempts
;
752 total_merges
+= combine_merges
;
753 total_extras
+= combine_extras
;
754 total_successes
+= combine_successes
;
756 nonzero_sign_valid
= 0;
758 /* Make recognizer allow volatile MEMs again. */
761 return new_direct_jump_p
;
764 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
767 init_reg_last_arrays ()
769 unsigned int nregs
= combine_max_regno
;
771 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
772 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
773 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
774 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
775 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
776 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
777 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
778 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
779 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
782 /* Set up any promoted values for incoming argument registers. */
785 setup_incoming_promotions ()
787 #ifdef PROMOTE_FUNCTION_ARGS
790 enum machine_mode mode
;
792 rtx first
= get_insns ();
794 #ifndef OUTGOING_REGNO
795 #define OUTGOING_REGNO(N) N
797 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
798 /* Check whether this register can hold an incoming pointer
799 argument. FUNCTION_ARG_REGNO_P tests outgoing register
800 numbers, so translate if necessary due to register windows. */
801 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
802 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
805 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
808 gen_rtx_CLOBBER (mode
, const0_rtx
)));
813 /* Called via note_stores. If X is a pseudo that is narrower than
814 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
816 If we are setting only a portion of X and we can't figure out what
817 portion, assume all bits will be used since we don't know what will
820 Similarly, set how many bits of X are known to be copies of the sign bit
821 at all locations in the function. This is the smallest number implied
825 set_nonzero_bits_and_sign_copies (x
, set
, data
)
828 void *data ATTRIBUTE_UNUSED
;
832 if (GET_CODE (x
) == REG
833 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
834 /* If this register is undefined at the start of the file, we can't
835 say what its contents were. */
836 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
837 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
839 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
841 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
842 reg_sign_bit_copies
[REGNO (x
)] = 1;
846 /* If this is a complex assignment, see if we can convert it into a
847 simple assignment. */
848 set
= expand_field_assignment (set
);
850 /* If this is a simple assignment, or we have a paradoxical SUBREG,
851 set what we know about X. */
853 if (SET_DEST (set
) == x
854 || (GET_CODE (SET_DEST (set
)) == SUBREG
855 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
856 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
857 && SUBREG_REG (SET_DEST (set
)) == x
))
859 rtx src
= SET_SRC (set
);
861 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
862 /* If X is narrower than a word and SRC is a non-negative
863 constant that would appear negative in the mode of X,
864 sign-extend it for use in reg_nonzero_bits because some
865 machines (maybe most) will actually do the sign-extension
866 and this is the conservative approach.
868 ??? For 2.5, try to tighten up the MD files in this regard
869 instead of this kludge. */
871 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
872 && GET_CODE (src
) == CONST_INT
874 && 0 != (INTVAL (src
)
876 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
877 src
= GEN_INT (INTVAL (src
)
878 | ((HOST_WIDE_INT
) (-1)
879 << GET_MODE_BITSIZE (GET_MODE (x
))));
882 reg_nonzero_bits
[REGNO (x
)]
883 |= nonzero_bits (src
, nonzero_bits_mode
);
884 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
885 if (reg_sign_bit_copies
[REGNO (x
)] == 0
886 || reg_sign_bit_copies
[REGNO (x
)] > num
)
887 reg_sign_bit_copies
[REGNO (x
)] = num
;
891 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
892 reg_sign_bit_copies
[REGNO (x
)] = 1;
897 /* See if INSN can be combined into I3. PRED and SUCC are optionally
898 insns that were previously combined into I3 or that will be combined
899 into the merger of INSN and I3.
901 Return 0 if the combination is not allowed for any reason.
903 If the combination is allowed, *PDEST will be set to the single
904 destination of INSN and *PSRC to the single source, and this function
908 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
911 rtx pred ATTRIBUTE_UNUSED
;
916 rtx set
= 0, src
, dest
;
921 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
922 && next_active_insn (succ
) == i3
)
923 : next_active_insn (insn
) == i3
);
925 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
926 or a PARALLEL consisting of such a SET and CLOBBERs.
928 If INSN has CLOBBER parallel parts, ignore them for our processing.
929 By definition, these happen during the execution of the insn. When it
930 is merged with another insn, all bets are off. If they are, in fact,
931 needed and aren't also supplied in I3, they may be added by
932 recog_for_combine. Otherwise, it won't match.
934 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
937 Get the source and destination of INSN. If more than one, can't
940 if (GET_CODE (PATTERN (insn
)) == SET
)
941 set
= PATTERN (insn
);
942 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
943 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
945 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
947 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
949 switch (GET_CODE (elt
))
951 /* This is important to combine floating point insns
954 /* Combining an isolated USE doesn't make sense.
955 We depend here on combinable_i3_pat to reject them. */
956 /* The code below this loop only verifies that the inputs of
957 the SET in INSN do not change. We call reg_set_between_p
958 to verify that the REG in the USE does not change betweeen
960 If the USE in INSN was for a pseudo register, the matching
961 insn pattern will likely match any register; combining this
962 with any other USE would only be safe if we knew that the
963 used registers have identical values, or if there was
964 something to tell them apart, e.g. different modes. For
965 now, we forgo such compilcated tests and simply disallow
966 combining of USES of pseudo registers with any other USE. */
967 if (GET_CODE (XEXP (elt
, 0)) == REG
968 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
970 rtx i3pat
= PATTERN (i3
);
971 int i
= XVECLEN (i3pat
, 0) - 1;
972 unsigned int regno
= REGNO (XEXP (elt
, 0));
976 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
978 if (GET_CODE (i3elt
) == USE
979 && GET_CODE (XEXP (i3elt
, 0)) == REG
980 && (REGNO (XEXP (i3elt
, 0)) == regno
981 ? reg_set_between_p (XEXP (elt
, 0),
982 PREV_INSN (insn
), i3
)
983 : regno
>= FIRST_PSEUDO_REGISTER
))
990 /* We can ignore CLOBBERs. */
995 /* Ignore SETs whose result isn't used but not those that
996 have side-effects. */
997 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
998 && ! side_effects_p (elt
))
1001 /* If we have already found a SET, this is a second one and
1002 so we cannot combine with this insn. */
1010 /* Anything else means we can't combine. */
1016 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1017 so don't do anything with it. */
1018 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1027 set
= expand_field_assignment (set
);
1028 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1030 /* Don't eliminate a store in the stack pointer. */
1031 if (dest
== stack_pointer_rtx
1032 /* If we couldn't eliminate a field assignment, we can't combine. */
1033 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1034 /* Don't combine with an insn that sets a register to itself if it has
1035 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1036 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1037 /* Can't merge an ASM_OPERANDS. */
1038 || GET_CODE (src
) == ASM_OPERANDS
1039 /* Can't merge a function call. */
1040 || GET_CODE (src
) == CALL
1041 /* Don't eliminate a function call argument. */
1042 || (GET_CODE (i3
) == CALL_INSN
1043 && (find_reg_fusage (i3
, USE
, dest
)
1044 || (GET_CODE (dest
) == REG
1045 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1046 && global_regs
[REGNO (dest
)])))
1047 /* Don't substitute into an incremented register. */
1048 || FIND_REG_INC_NOTE (i3
, dest
)
1049 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1051 /* Don't combine the end of a libcall into anything. */
1052 /* ??? This gives worse code, and appears to be unnecessary, since no
1053 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1054 use REG_RETVAL notes for noconflict blocks, but other code here
1055 makes sure that those insns don't disappear. */
1056 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1058 /* Make sure that DEST is not used after SUCC but before I3. */
1059 || (succ
&& ! all_adjacent
1060 && reg_used_between_p (dest
, succ
, i3
))
1061 /* Make sure that the value that is to be substituted for the register
1062 does not use any registers whose values alter in between. However,
1063 If the insns are adjacent, a use can't cross a set even though we
1064 think it might (this can happen for a sequence of insns each setting
1065 the same destination; reg_last_set of that register might point to
1066 a NOTE). If INSN has a REG_EQUIV note, the register is always
1067 equivalent to the memory so the substitution is valid even if there
1068 are intervening stores. Also, don't move a volatile asm or
1069 UNSPEC_VOLATILE across any other insns. */
1071 && (((GET_CODE (src
) != MEM
1072 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1073 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1074 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1075 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1076 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1077 better register allocation by not doing the combine. */
1078 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1079 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1080 /* Don't combine across a CALL_INSN, because that would possibly
1081 change whether the life span of some REGs crosses calls or not,
1082 and it is a pain to update that information.
1083 Exception: if source is a constant, moving it later can't hurt.
1084 Accept that special case, because it helps -fforce-addr a lot. */
1085 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1088 /* DEST must either be a REG or CC0. */
1089 if (GET_CODE (dest
) == REG
)
1091 /* If register alignment is being enforced for multi-word items in all
1092 cases except for parameters, it is possible to have a register copy
1093 insn referencing a hard register that is not allowed to contain the
1094 mode being copied and which would not be valid as an operand of most
1095 insns. Eliminate this problem by not combining with such an insn.
1097 Also, on some machines we don't want to extend the life of a hard
1100 if (GET_CODE (src
) == REG
1101 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1102 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1103 /* Don't extend the life of a hard register unless it is
1104 user variable (if we have few registers) or it can't
1105 fit into the desired register (meaning something special
1107 Also avoid substituting a return register into I3, because
1108 reload can't handle a conflict with constraints of other
1110 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1111 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1114 else if (GET_CODE (dest
) != CC0
)
1117 /* Don't substitute for a register intended as a clobberable operand.
1118 Similarly, don't substitute an expression containing a register that
1119 will be clobbered in I3. */
1120 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1121 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1122 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1123 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1125 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1128 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1129 or not), reject, unless nothing volatile comes between it and I3 */
1131 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1133 /* Make sure succ doesn't contain a volatile reference. */
1134 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1137 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1138 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1142 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1143 to be an explicit register variable, and was chosen for a reason. */
1145 if (GET_CODE (src
) == ASM_OPERANDS
1146 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1149 /* If there are any volatile insns between INSN and I3, reject, because
1150 they might affect machine state. */
1152 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1153 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1156 /* If INSN or I2 contains an autoincrement or autodecrement,
1157 make sure that register is not used between there and I3,
1158 and not already used in I3 either.
1159 Also insist that I3 not be a jump; if it were one
1160 and the incremented register were spilled, we would lose. */
1163 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1164 if (REG_NOTE_KIND (link
) == REG_INC
1165 && (GET_CODE (i3
) == JUMP_INSN
1166 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1167 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1172 /* Don't combine an insn that follows a CC0-setting insn.
1173 An insn that uses CC0 must not be separated from the one that sets it.
1174 We do, however, allow I2 to follow a CC0-setting insn if that insn
1175 is passed as I1; in that case it will be deleted also.
1176 We also allow combining in this case if all the insns are adjacent
1177 because that would leave the two CC0 insns adjacent as well.
1178 It would be more logical to test whether CC0 occurs inside I1 or I2,
1179 but that would be much slower, and this ought to be equivalent. */
1181 p
= prev_nonnote_insn (insn
);
1182 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1187 /* If we get here, we have passed all the tests and the combination is
1196 /* Check if PAT is an insn - or a part of it - used to set up an
1197 argument for a function in a hard register. */
1200 sets_function_arg_p (pat
)
1206 switch (GET_CODE (pat
))
1209 return sets_function_arg_p (PATTERN (pat
));
1212 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1213 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1219 inner_dest
= SET_DEST (pat
);
1220 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1221 || GET_CODE (inner_dest
) == SUBREG
1222 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1223 inner_dest
= XEXP (inner_dest
, 0);
1225 return (GET_CODE (inner_dest
) == REG
1226 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1227 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1236 /* LOC is the location within I3 that contains its pattern or the component
1237 of a PARALLEL of the pattern. We validate that it is valid for combining.
1239 One problem is if I3 modifies its output, as opposed to replacing it
1240 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1241 so would produce an insn that is not equivalent to the original insns.
1245 (set (reg:DI 101) (reg:DI 100))
1246 (set (subreg:SI (reg:DI 101) 0) <foo>)
1248 This is NOT equivalent to:
1250 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1251 (set (reg:DI 101) (reg:DI 100))])
1253 Not only does this modify 100 (in which case it might still be valid
1254 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1256 We can also run into a problem if I2 sets a register that I1
1257 uses and I1 gets directly substituted into I3 (not via I2). In that
1258 case, we would be getting the wrong value of I2DEST into I3, so we
1259 must reject the combination. This case occurs when I2 and I1 both
1260 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1261 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1262 of a SET must prevent combination from occurring.
1264 Before doing the above check, we first try to expand a field assignment
1265 into a set of logical operations.
1267 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1268 we place a register that is both set and used within I3. If more than one
1269 such register is detected, we fail.
1271 Return 1 if the combination is valid, zero otherwise. */
1274 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1280 rtx
*pi3dest_killed
;
1284 if (GET_CODE (x
) == SET
)
1286 rtx set
= expand_field_assignment (x
);
1287 rtx dest
= SET_DEST (set
);
1288 rtx src
= SET_SRC (set
);
1289 rtx inner_dest
= dest
;
1292 rtx inner_src
= src
;
1297 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1298 || GET_CODE (inner_dest
) == SUBREG
1299 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1300 inner_dest
= XEXP (inner_dest
, 0);
1302 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1305 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1306 || GET_CODE (inner_src
) == SUBREG
1307 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1308 inner_src
= XEXP (inner_src
, 0);
1310 /* If it is better that two different modes keep two different pseudos,
1311 avoid combining them. This avoids producing the following pattern
1313 (set (subreg:SI (reg/v:QI 21) 0)
1314 (lshiftrt:SI (reg/v:SI 20)
1316 If that were made, reload could not handle the pair of
1317 reg 20/21, since it would try to get any GENERAL_REGS
1318 but some of them don't handle QImode. */
1320 if (rtx_equal_p (inner_src
, i2dest
)
1321 && GET_CODE (inner_dest
) == REG
1322 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1326 /* Check for the case where I3 modifies its output, as
1328 if ((inner_dest
!= dest
1329 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1330 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1332 /* This is the same test done in can_combine_p except we can't test
1333 all_adjacent; we don't have to, since this instruction will stay
1334 in place, thus we are not considering increasing the lifetime of
1337 Also, if this insn sets a function argument, combining it with
1338 something that might need a spill could clobber a previous
1339 function argument; the all_adjacent test in can_combine_p also
1340 checks this; here, we do a more specific test for this case. */
1342 || (GET_CODE (inner_dest
) == REG
1343 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1344 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1345 GET_MODE (inner_dest
))))
1346 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1349 /* If DEST is used in I3, it is being killed in this insn,
1350 so record that for later.
1351 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1352 STACK_POINTER_REGNUM, since these are always considered to be
1353 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1354 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1355 && reg_referenced_p (dest
, PATTERN (i3
))
1356 && REGNO (dest
) != FRAME_POINTER_REGNUM
1357 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1358 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1360 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1361 && (REGNO (dest
) != ARG_POINTER_REGNUM
1362 || ! fixed_regs
[REGNO (dest
)])
1364 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1366 if (*pi3dest_killed
)
1369 *pi3dest_killed
= dest
;
1373 else if (GET_CODE (x
) == PARALLEL
)
1377 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1378 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1379 i1_not_in_src
, pi3dest_killed
))
1386 /* Return 1 if X is an arithmetic expression that contains a multiplication
1387 and division. We don't count multiplications by powers of two here. */
1393 switch (GET_CODE (x
))
1395 case MOD
: case DIV
: case UMOD
: case UDIV
:
1399 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1400 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1402 switch (GET_RTX_CLASS (GET_CODE (x
)))
1404 case 'c': case '<': case '2':
1405 return contains_muldiv (XEXP (x
, 0))
1406 || contains_muldiv (XEXP (x
, 1));
1409 return contains_muldiv (XEXP (x
, 0));
1417 /* Determine whether INSN can be used in a combination. Return nonzero if
1418 not. This is used in try_combine to detect early some cases where we
1419 can't perform combinations. */
1422 cant_combine_insn_p (insn
)
1428 /* If this isn't really an insn, we can't do anything.
1429 This can occur when flow deletes an insn that it has merged into an
1430 auto-increment address. */
1431 if (! INSN_P (insn
))
1434 /* Never combine loads and stores involving hard regs. The register
1435 allocator can usually handle such reg-reg moves by tying. If we allow
1436 the combiner to make substitutions of hard regs, we risk aborting in
1437 reload on machines that have SMALL_REGISTER_CLASSES.
1438 As an exception, we allow combinations involving fixed regs; these are
1439 not available to the register allocator so there's no risk involved. */
1441 set
= single_set (insn
);
1444 src
= SET_SRC (set
);
1445 dest
= SET_DEST (set
);
1446 if (GET_CODE (src
) == SUBREG
)
1447 src
= SUBREG_REG (src
);
1448 if (GET_CODE (dest
) == SUBREG
)
1449 dest
= SUBREG_REG (dest
);
1450 if (REG_P (src
) && REG_P (dest
)
1451 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1452 && ! fixed_regs
[REGNO (src
)])
1453 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1454 && ! fixed_regs
[REGNO (dest
)])))
1460 /* Try to combine the insns I1 and I2 into I3.
1461 Here I1 and I2 appear earlier than I3.
1462 I1 can be zero; then we combine just I2 into I3.
1464 If we are combining three insns and the resulting insn is not recognized,
1465 try splitting it into two insns. If that happens, I2 and I3 are retained
1466 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1469 Return 0 if the combination does not work. Then nothing is changed.
1470 If we did the combination, return the insn at which combine should
1473 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1474 new direct jump instruction. */
1477 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1478 register rtx i3
, i2
, i1
;
1479 register int *new_direct_jump_p
;
1481 /* New patterns for I3 and I2, respectively. */
1482 rtx newpat
, newi2pat
= 0;
1483 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1484 int added_sets_1
, added_sets_2
;
1485 /* Total number of SETs to put into I3. */
1487 /* Nonzero is I2's body now appears in I3. */
1489 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1490 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1491 /* Contains I3 if the destination of I3 is used in its source, which means
1492 that the old life of I3 is being killed. If that usage is placed into
1493 I2 and not in I3, a REG_DEAD note must be made. */
1494 rtx i3dest_killed
= 0;
1495 /* SET_DEST and SET_SRC of I2 and I1. */
1496 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1497 /* PATTERN (I2), or a copy of it in certain cases. */
1499 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1500 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1501 int i1_feeds_i3
= 0;
1502 /* Notes that must be added to REG_NOTES in I3 and I2. */
1503 rtx new_i3_notes
, new_i2_notes
;
1504 /* Notes that we substituted I3 into I2 instead of the normal case. */
1505 int i3_subst_into_i2
= 0;
1506 /* Notes that I1, I2 or I3 is a MULT operation. */
1514 /* Exit early if one of the insns involved can't be used for
1516 if (cant_combine_insn_p (i3
)
1517 || cant_combine_insn_p (i2
)
1518 || (i1
&& cant_combine_insn_p (i1
))
1519 /* We also can't do anything if I3 has a
1520 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1523 /* ??? This gives worse code, and appears to be unnecessary, since no
1524 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1525 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1531 undobuf
.other_insn
= 0;
1533 /* Reset the hard register usage information. */
1534 CLEAR_HARD_REG_SET (newpat_used_regs
);
1536 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1537 code below, set I1 to be the earlier of the two insns. */
1538 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1539 temp
= i1
, i1
= i2
, i2
= temp
;
1541 added_links_insn
= 0;
1543 /* First check for one important special-case that the code below will
1544 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1545 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1546 we may be able to replace that destination with the destination of I3.
1547 This occurs in the common code where we compute both a quotient and
1548 remainder into a structure, in which case we want to do the computation
1549 directly into the structure to avoid register-register copies.
1551 Note that this case handles both multiple sets in I2 and also
1552 cases where I2 has a number of CLOBBER or PARALLELs.
1554 We make very conservative checks below and only try to handle the
1555 most common cases of this. For example, we only handle the case
1556 where I2 and I3 are adjacent to avoid making difficult register
1559 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1560 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1561 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1562 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1563 && GET_CODE (PATTERN (i2
)) == PARALLEL
1564 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1565 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1566 below would need to check what is inside (and reg_overlap_mentioned_p
1567 doesn't support those codes anyway). Don't allow those destinations;
1568 the resulting insn isn't likely to be recognized anyway. */
1569 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1570 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1571 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1572 SET_DEST (PATTERN (i3
)))
1573 && next_real_insn (i2
) == i3
)
1575 rtx p2
= PATTERN (i2
);
1577 /* Make sure that the destination of I3,
1578 which we are going to substitute into one output of I2,
1579 is not used within another output of I2. We must avoid making this:
1580 (parallel [(set (mem (reg 69)) ...)
1581 (set (reg 69) ...)])
1582 which is not well-defined as to order of actions.
1583 (Besides, reload can't handle output reloads for this.)
1585 The problem can also happen if the dest of I3 is a memory ref,
1586 if another dest in I2 is an indirect memory ref. */
1587 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1588 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1589 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1590 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1591 SET_DEST (XVECEXP (p2
, 0, i
))))
1594 if (i
== XVECLEN (p2
, 0))
1595 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1596 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1597 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1598 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1603 subst_low_cuid
= INSN_CUID (i2
);
1605 added_sets_2
= added_sets_1
= 0;
1606 i2dest
= SET_SRC (PATTERN (i3
));
1608 /* Replace the dest in I2 with our dest and make the resulting
1609 insn the new pattern for I3. Then skip to where we
1610 validate the pattern. Everything was set up above. */
1611 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1612 SET_DEST (PATTERN (i3
)));
1615 i3_subst_into_i2
= 1;
1616 goto validate_replacement
;
1620 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1621 one of those words to another constant, merge them by making a new
1624 && (temp
= single_set (i2
)) != 0
1625 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1626 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1627 && GET_CODE (SET_DEST (temp
)) == REG
1628 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1629 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1630 && GET_CODE (PATTERN (i3
)) == SET
1631 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1632 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1633 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1634 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1635 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1637 HOST_WIDE_INT lo
, hi
;
1639 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1640 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1643 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1644 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1647 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1649 /* We don't handle the case of the target word being wider
1650 than a host wide int. */
1651 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1654 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1655 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1657 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1658 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1659 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1661 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1662 >> (HOST_BITS_PER_WIDE_INT
- 1));
1664 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1665 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1666 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1667 (INTVAL (SET_SRC (PATTERN (i3
)))));
1669 hi
= lo
< 0 ? -1 : 0;
1672 /* We don't handle the case of the higher word not fitting
1673 entirely in either hi or lo. */
1678 subst_low_cuid
= INSN_CUID (i2
);
1679 added_sets_2
= added_sets_1
= 0;
1680 i2dest
= SET_DEST (temp
);
1682 SUBST (SET_SRC (temp
),
1683 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1685 newpat
= PATTERN (i2
);
1686 goto validate_replacement
;
1690 /* If we have no I1 and I2 looks like:
1691 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1693 make up a dummy I1 that is
1696 (set (reg:CC X) (compare:CC Y (const_int 0)))
1698 (We can ignore any trailing CLOBBERs.)
1700 This undoes a previous combination and allows us to match a branch-and-
1703 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1704 && XVECLEN (PATTERN (i2
), 0) >= 2
1705 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1706 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1708 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1709 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1710 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1711 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1712 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1713 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1715 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1716 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1721 /* We make I1 with the same INSN_UID as I2. This gives it
1722 the same INSN_CUID for value tracking. Our fake I1 will
1723 never appear in the insn stream so giving it the same INSN_UID
1724 as I2 will not cause a problem. */
1726 subst_prev_insn
= i1
1727 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1728 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1731 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1732 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1733 SET_DEST (PATTERN (i1
)));
1738 /* Verify that I2 and I1 are valid for combining. */
1739 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1740 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1746 /* Record whether I2DEST is used in I2SRC and similarly for the other
1747 cases. Knowing this will help in register status updating below. */
1748 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1749 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1750 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1752 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1754 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1756 /* Ensure that I3's pattern can be the destination of combines. */
1757 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1758 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1765 /* See if any of the insns is a MULT operation. Unless one is, we will
1766 reject a combination that is, since it must be slower. Be conservative
1768 if (GET_CODE (i2src
) == MULT
1769 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1770 || (GET_CODE (PATTERN (i3
)) == SET
1771 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1774 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1775 We used to do this EXCEPT in one case: I3 has a post-inc in an
1776 output operand. However, that exception can give rise to insns like
1778 which is a famous insn on the PDP-11 where the value of r3 used as the
1779 source was model-dependent. Avoid this sort of thing. */
1782 if (!(GET_CODE (PATTERN (i3
)) == SET
1783 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1784 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1785 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1786 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1787 /* It's not the exception. */
1790 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1791 if (REG_NOTE_KIND (link
) == REG_INC
1792 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1794 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1801 /* See if the SETs in I1 or I2 need to be kept around in the merged
1802 instruction: whenever the value set there is still needed past I3.
1803 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1805 For the SET in I1, we have two cases: If I1 and I2 independently
1806 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1807 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1808 in I1 needs to be kept around unless I1DEST dies or is set in either
1809 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1810 I1DEST. If so, we know I1 feeds into I2. */
1812 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1815 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1816 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1818 /* If the set in I2 needs to be kept around, we must make a copy of
1819 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1820 PATTERN (I2), we are only substituting for the original I1DEST, not into
1821 an already-substituted copy. This also prevents making self-referential
1822 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1825 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1826 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1830 i2pat
= copy_rtx (i2pat
);
1834 /* Substitute in the latest insn for the regs set by the earlier ones. */
1836 maxreg
= max_reg_num ();
1840 /* It is possible that the source of I2 or I1 may be performing an
1841 unneeded operation, such as a ZERO_EXTEND of something that is known
1842 to have the high part zero. Handle that case by letting subst look at
1843 the innermost one of them.
1845 Another way to do this would be to have a function that tries to
1846 simplify a single insn instead of merging two or more insns. We don't
1847 do this because of the potential of infinite loops and because
1848 of the potential extra memory required. However, doing it the way
1849 we are is a bit of a kludge and doesn't catch all cases.
1851 But only do this if -fexpensive-optimizations since it slows things down
1852 and doesn't usually win. */
1854 if (flag_expensive_optimizations
)
1856 /* Pass pc_rtx so no substitutions are done, just simplifications.
1857 The cases that we are interested in here do not involve the few
1858 cases were is_replaced is checked. */
1861 subst_low_cuid
= INSN_CUID (i1
);
1862 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1866 subst_low_cuid
= INSN_CUID (i2
);
1867 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1872 /* Many machines that don't use CC0 have insns that can both perform an
1873 arithmetic operation and set the condition code. These operations will
1874 be represented as a PARALLEL with the first element of the vector
1875 being a COMPARE of an arithmetic operation with the constant zero.
1876 The second element of the vector will set some pseudo to the result
1877 of the same arithmetic operation. If we simplify the COMPARE, we won't
1878 match such a pattern and so will generate an extra insn. Here we test
1879 for this case, where both the comparison and the operation result are
1880 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1881 I2SRC. Later we will make the PARALLEL that contains I2. */
1883 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1884 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1885 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1886 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1888 #ifdef EXTRA_CC_MODES
1890 enum machine_mode compare_mode
;
1893 newpat
= PATTERN (i3
);
1894 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1898 #ifdef EXTRA_CC_MODES
1899 /* See if a COMPARE with the operand we substituted in should be done
1900 with the mode that is currently being used. If not, do the same
1901 processing we do in `subst' for a SET; namely, if the destination
1902 is used only once, try to replace it with a register of the proper
1903 mode and also replace the COMPARE. */
1904 if (undobuf
.other_insn
== 0
1905 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1906 &undobuf
.other_insn
))
1907 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1909 != GET_MODE (SET_DEST (newpat
))))
1911 unsigned int regno
= REGNO (SET_DEST (newpat
));
1912 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1914 if (regno
< FIRST_PSEUDO_REGISTER
1915 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1916 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1918 if (regno
>= FIRST_PSEUDO_REGISTER
)
1919 SUBST (regno_reg_rtx
[regno
], new_dest
);
1921 SUBST (SET_DEST (newpat
), new_dest
);
1922 SUBST (XEXP (*cc_use
, 0), new_dest
);
1923 SUBST (SET_SRC (newpat
),
1924 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1927 undobuf
.other_insn
= 0;
1934 n_occurrences
= 0; /* `subst' counts here */
1936 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1937 need to make a unique copy of I2SRC each time we substitute it
1938 to avoid self-referential rtl. */
1940 subst_low_cuid
= INSN_CUID (i2
);
1941 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1942 ! i1_feeds_i3
&& i1dest_in_i1src
);
1944 /* Record whether i2's body now appears within i3's body. */
1945 i2_is_used
= n_occurrences
;
1948 /* If we already got a failure, don't try to do more. Otherwise,
1949 try to substitute in I1 if we have it. */
1951 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1953 /* Before we can do this substitution, we must redo the test done
1954 above (see detailed comments there) that ensures that I1DEST
1955 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1957 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1965 subst_low_cuid
= INSN_CUID (i1
);
1966 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1969 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1970 to count all the ways that I2SRC and I1SRC can be used. */
1971 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1972 && i2_is_used
+ added_sets_2
> 1)
1973 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1974 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1976 /* Fail if we tried to make a new register (we used to abort, but there's
1977 really no reason to). */
1978 || max_reg_num () != maxreg
1979 /* Fail if we couldn't do something and have a CLOBBER. */
1980 || GET_CODE (newpat
) == CLOBBER
1981 /* Fail if this new pattern is a MULT and we didn't have one before
1982 at the outer level. */
1983 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1990 /* If the actions of the earlier insns must be kept
1991 in addition to substituting them into the latest one,
1992 we must make a new PARALLEL for the latest insn
1993 to hold additional the SETs. */
1995 if (added_sets_1
|| added_sets_2
)
1999 if (GET_CODE (newpat
) == PARALLEL
)
2001 rtvec old
= XVEC (newpat
, 0);
2002 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2003 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2004 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2005 sizeof (old
->elem
[0]) * old
->num_elem
);
2010 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2011 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2012 XVECEXP (newpat
, 0, 0) = old
;
2016 XVECEXP (newpat
, 0, --total_sets
)
2017 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2018 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2022 /* If there is no I1, use I2's body as is. We used to also not do
2023 the subst call below if I2 was substituted into I3,
2024 but that could lose a simplification. */
2026 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2028 /* See comment where i2pat is assigned. */
2029 XVECEXP (newpat
, 0, --total_sets
)
2030 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2034 /* We come here when we are replacing a destination in I2 with the
2035 destination of I3. */
2036 validate_replacement
:
2038 /* Note which hard regs this insn has as inputs. */
2039 mark_used_regs_combine (newpat
);
2041 /* Is the result of combination a valid instruction? */
2042 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2044 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2045 the second SET's destination is a register that is unused. In that case,
2046 we just need the first SET. This can occur when simplifying a divmod
2047 insn. We *must* test for this case here because the code below that
2048 splits two independent SETs doesn't handle this case correctly when it
2049 updates the register status. Also check the case where the first
2050 SET's destination is unused. That would not cause incorrect code, but
2051 does cause an unneeded insn to remain. */
2053 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2054 && XVECLEN (newpat
, 0) == 2
2055 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2056 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2057 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2058 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2059 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2060 && asm_noperands (newpat
) < 0)
2062 newpat
= XVECEXP (newpat
, 0, 0);
2063 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2066 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2067 && XVECLEN (newpat
, 0) == 2
2068 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2069 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2070 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2071 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2072 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2073 && asm_noperands (newpat
) < 0)
2075 newpat
= XVECEXP (newpat
, 0, 1);
2076 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2079 /* If we were combining three insns and the result is a simple SET
2080 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2081 insns. There are two ways to do this. It can be split using a
2082 machine-specific method (like when you have an addition of a large
2083 constant) or by combine in the function find_split_point. */
2085 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2086 && asm_noperands (newpat
) < 0)
2088 rtx m_split
, *split
;
2089 rtx ni2dest
= i2dest
;
2091 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2092 use I2DEST as a scratch register will help. In the latter case,
2093 convert I2DEST to the mode of the source of NEWPAT if we can. */
2095 m_split
= split_insns (newpat
, i3
);
2097 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2098 inputs of NEWPAT. */
2100 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2101 possible to try that as a scratch reg. This would require adding
2102 more code to make it work though. */
2104 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2106 /* If I2DEST is a hard register or the only use of a pseudo,
2107 we can change its mode. */
2108 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2109 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2110 && GET_CODE (i2dest
) == REG
2111 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2112 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2113 && ! REG_USERVAR_P (i2dest
))))
2114 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2117 m_split
= split_insns (gen_rtx_PARALLEL
2119 gen_rtvec (2, newpat
,
2120 gen_rtx_CLOBBER (VOIDmode
,
2123 /* If the split with the mode-changed register didn't work, try
2124 the original register. */
2125 if (! m_split
&& ni2dest
!= i2dest
)
2128 m_split
= split_insns (gen_rtx_PARALLEL
2130 gen_rtvec (2, newpat
,
2131 gen_rtx_CLOBBER (VOIDmode
,
2137 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2139 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2140 if (insn_code_number
>= 0)
2143 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2144 && XVECLEN (m_split
, 0) == 2
2145 && (next_real_insn (i2
) == i3
2146 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2150 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2151 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2153 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2154 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2156 /* In case we changed the mode of I2DEST, replace it in the
2157 pseudo-register table here. We can't do it above in case this
2158 code doesn't get executed and we do a split the other way. */
2160 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2161 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2163 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2165 /* If I2 or I3 has multiple SETs, we won't know how to track
2166 register status, so don't use these insns. If I2's destination
2167 is used between I2 and I3, we also can't use these insns. */
2169 if (i2_code_number
>= 0 && i2set
&& i3set
2170 && (next_real_insn (i2
) == i3
2171 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2172 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2174 if (insn_code_number
>= 0)
2177 /* It is possible that both insns now set the destination of I3.
2178 If so, we must show an extra use of it. */
2180 if (insn_code_number
>= 0)
2182 rtx new_i3_dest
= SET_DEST (i3set
);
2183 rtx new_i2_dest
= SET_DEST (i2set
);
2185 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2186 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2187 || GET_CODE (new_i3_dest
) == SUBREG
)
2188 new_i3_dest
= XEXP (new_i3_dest
, 0);
2190 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2191 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2192 || GET_CODE (new_i2_dest
) == SUBREG
)
2193 new_i2_dest
= XEXP (new_i2_dest
, 0);
2195 if (GET_CODE (new_i3_dest
) == REG
2196 && GET_CODE (new_i2_dest
) == REG
2197 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2198 REG_N_SETS (REGNO (new_i2_dest
))++;
2202 /* If we can split it and use I2DEST, go ahead and see if that
2203 helps things be recognized. Verify that none of the registers
2204 are set between I2 and I3. */
2205 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2207 && GET_CODE (i2dest
) == REG
2209 /* We need I2DEST in the proper mode. If it is a hard register
2210 or the only use of a pseudo, we can change its mode. */
2211 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2212 || GET_MODE (*split
) == VOIDmode
2213 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2214 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2215 && ! REG_USERVAR_P (i2dest
)))
2216 && (next_real_insn (i2
) == i3
2217 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2218 /* We can't overwrite I2DEST if its value is still used by
2220 && ! reg_referenced_p (i2dest
, newpat
))
2222 rtx newdest
= i2dest
;
2223 enum rtx_code split_code
= GET_CODE (*split
);
2224 enum machine_mode split_mode
= GET_MODE (*split
);
2226 /* Get NEWDEST as a register in the proper mode. We have already
2227 validated that we can do this. */
2228 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2230 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2232 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2233 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2236 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2237 an ASHIFT. This can occur if it was inside a PLUS and hence
2238 appeared to be a memory address. This is a kludge. */
2239 if (split_code
== MULT
2240 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2241 && INTVAL (XEXP (*split
, 1)) > 0
2242 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2244 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2245 XEXP (*split
, 0), GEN_INT (i
)));
2246 /* Update split_code because we may not have a multiply
2248 split_code
= GET_CODE (*split
);
2251 #ifdef INSN_SCHEDULING
2252 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2253 be written as a ZERO_EXTEND. */
2254 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2255 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2256 SUBREG_REG (*split
)));
2259 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2260 SUBST (*split
, newdest
);
2261 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2263 /* If the split point was a MULT and we didn't have one before,
2264 don't use one now. */
2265 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2266 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2270 /* Check for a case where we loaded from memory in a narrow mode and
2271 then sign extended it, but we need both registers. In that case,
2272 we have a PARALLEL with both loads from the same memory location.
2273 We can split this into a load from memory followed by a register-register
2274 copy. This saves at least one insn, more if register allocation can
2277 We cannot do this if the destination of the second assignment is
2278 a register that we have already assumed is zero-extended. Similarly
2279 for a SUBREG of such a register. */
2281 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2282 && GET_CODE (newpat
) == PARALLEL
2283 && XVECLEN (newpat
, 0) == 2
2284 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2285 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2286 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2287 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2288 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2289 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2291 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2292 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2293 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2294 (GET_CODE (temp
) == REG
2295 && reg_nonzero_bits
[REGNO (temp
)] != 0
2296 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2297 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2298 && (reg_nonzero_bits
[REGNO (temp
)]
2299 != GET_MODE_MASK (word_mode
))))
2300 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2301 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2302 (GET_CODE (temp
) == REG
2303 && reg_nonzero_bits
[REGNO (temp
)] != 0
2304 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2305 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2306 && (reg_nonzero_bits
[REGNO (temp
)]
2307 != GET_MODE_MASK (word_mode
)))))
2308 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2309 SET_SRC (XVECEXP (newpat
, 0, 1)))
2310 && ! find_reg_note (i3
, REG_UNUSED
,
2311 SET_DEST (XVECEXP (newpat
, 0, 0))))
2315 newi2pat
= XVECEXP (newpat
, 0, 0);
2316 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2317 newpat
= XVECEXP (newpat
, 0, 1);
2318 SUBST (SET_SRC (newpat
),
2319 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2320 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2322 if (i2_code_number
>= 0)
2323 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2325 if (insn_code_number
>= 0)
2330 /* If we will be able to accept this, we have made a change to the
2331 destination of I3. This can invalidate a LOG_LINKS pointing
2332 to I3. No other part of combine.c makes such a transformation.
2334 The new I3 will have a destination that was previously the
2335 destination of I1 or I2 and which was used in i2 or I3. Call
2336 distribute_links to make a LOG_LINK from the next use of
2337 that destination. */
2339 PATTERN (i3
) = newpat
;
2340 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2342 /* I3 now uses what used to be its destination and which is
2343 now I2's destination. That means we need a LOG_LINK from
2344 I3 to I2. But we used to have one, so we still will.
2346 However, some later insn might be using I2's dest and have
2347 a LOG_LINK pointing at I3. We must remove this link.
2348 The simplest way to remove the link is to point it at I1,
2349 which we know will be a NOTE. */
2351 for (insn
= NEXT_INSN (i3
);
2352 insn
&& (this_basic_block
== n_basic_blocks
- 1
2353 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2354 insn
= NEXT_INSN (insn
))
2356 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2358 for (link
= LOG_LINKS (insn
); link
;
2359 link
= XEXP (link
, 1))
2360 if (XEXP (link
, 0) == i3
)
2361 XEXP (link
, 0) = i1
;
2369 /* Similarly, check for a case where we have a PARALLEL of two independent
2370 SETs but we started with three insns. In this case, we can do the sets
2371 as two separate insns. This case occurs when some SET allows two
2372 other insns to combine, but the destination of that SET is still live. */
2374 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2375 && GET_CODE (newpat
) == PARALLEL
2376 && XVECLEN (newpat
, 0) == 2
2377 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2379 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2380 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2381 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2382 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2383 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2385 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2387 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2388 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2389 XVECEXP (newpat
, 0, 0))
2390 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2391 XVECEXP (newpat
, 0, 1))
2392 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2393 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2395 /* Normally, it doesn't matter which of the two is done first,
2396 but it does if one references cc0. In that case, it has to
2399 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2401 newi2pat
= XVECEXP (newpat
, 0, 0);
2402 newpat
= XVECEXP (newpat
, 0, 1);
2407 newi2pat
= XVECEXP (newpat
, 0, 1);
2408 newpat
= XVECEXP (newpat
, 0, 0);
2411 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2413 if (i2_code_number
>= 0)
2414 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2417 /* If it still isn't recognized, fail and change things back the way they
2419 if ((insn_code_number
< 0
2420 /* Is the result a reasonable ASM_OPERANDS? */
2421 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2427 /* If we had to change another insn, make sure it is valid also. */
2428 if (undobuf
.other_insn
)
2430 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2431 rtx new_other_notes
;
2434 CLEAR_HARD_REG_SET (newpat_used_regs
);
2436 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2439 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2445 PATTERN (undobuf
.other_insn
) = other_pat
;
2447 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2448 are still valid. Then add any non-duplicate notes added by
2449 recog_for_combine. */
2450 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2452 next
= XEXP (note
, 1);
2454 if (REG_NOTE_KIND (note
) == REG_UNUSED
2455 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2457 if (GET_CODE (XEXP (note
, 0)) == REG
)
2458 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2460 remove_note (undobuf
.other_insn
, note
);
2464 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2465 if (GET_CODE (XEXP (note
, 0)) == REG
)
2466 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2468 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2469 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2472 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2473 they are adjacent to each other or not. */
2475 rtx p
= prev_nonnote_insn (i3
);
2476 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2477 && sets_cc0_p (newi2pat
))
2485 /* We now know that we can do this combination. Merge the insns and
2486 update the status of registers and LOG_LINKS. */
2489 rtx i3notes
, i2notes
, i1notes
= 0;
2490 rtx i3links
, i2links
, i1links
= 0;
2493 /* Compute which registers we expect to eliminate. newi2pat may be setting
2494 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2495 same as i3dest, in which case newi2pat may be setting i1dest. */
2496 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2497 || i2dest_in_i2src
|| i2dest_in_i1src
2499 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2500 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2503 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2505 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2506 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2508 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2510 /* Ensure that we do not have something that should not be shared but
2511 occurs multiple times in the new insns. Check this by first
2512 resetting all the `used' flags and then copying anything is shared. */
2514 reset_used_flags (i3notes
);
2515 reset_used_flags (i2notes
);
2516 reset_used_flags (i1notes
);
2517 reset_used_flags (newpat
);
2518 reset_used_flags (newi2pat
);
2519 if (undobuf
.other_insn
)
2520 reset_used_flags (PATTERN (undobuf
.other_insn
));
2522 i3notes
= copy_rtx_if_shared (i3notes
);
2523 i2notes
= copy_rtx_if_shared (i2notes
);
2524 i1notes
= copy_rtx_if_shared (i1notes
);
2525 newpat
= copy_rtx_if_shared (newpat
);
2526 newi2pat
= copy_rtx_if_shared (newi2pat
);
2527 if (undobuf
.other_insn
)
2528 reset_used_flags (PATTERN (undobuf
.other_insn
));
2530 INSN_CODE (i3
) = insn_code_number
;
2531 PATTERN (i3
) = newpat
;
2532 if (undobuf
.other_insn
)
2533 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2535 /* We had one special case above where I2 had more than one set and
2536 we replaced a destination of one of those sets with the destination
2537 of I3. In that case, we have to update LOG_LINKS of insns later
2538 in this basic block. Note that this (expensive) case is rare.
2540 Also, in this case, we must pretend that all REG_NOTEs for I2
2541 actually came from I3, so that REG_UNUSED notes from I2 will be
2542 properly handled. */
2544 if (i3_subst_into_i2
)
2546 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2547 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2548 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2549 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2550 && ! find_reg_note (i2
, REG_UNUSED
,
2551 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2552 for (temp
= NEXT_INSN (i2
);
2553 temp
&& (this_basic_block
== n_basic_blocks
- 1
2554 || BLOCK_HEAD (this_basic_block
) != temp
);
2555 temp
= NEXT_INSN (temp
))
2556 if (temp
!= i3
&& INSN_P (temp
))
2557 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2558 if (XEXP (link
, 0) == i2
)
2559 XEXP (link
, 0) = i3
;
2564 while (XEXP (link
, 1))
2565 link
= XEXP (link
, 1);
2566 XEXP (link
, 1) = i2notes
;
2580 INSN_CODE (i2
) = i2_code_number
;
2581 PATTERN (i2
) = newi2pat
;
2585 PUT_CODE (i2
, NOTE
);
2586 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2587 NOTE_SOURCE_FILE (i2
) = 0;
2594 PUT_CODE (i1
, NOTE
);
2595 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2596 NOTE_SOURCE_FILE (i1
) = 0;
2599 /* Get death notes for everything that is now used in either I3 or
2600 I2 and used to die in a previous insn. If we built two new
2601 patterns, move from I1 to I2 then I2 to I3 so that we get the
2602 proper movement on registers that I2 modifies. */
2606 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2607 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2610 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2613 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2615 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2618 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2621 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2624 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2627 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2628 know these are REG_UNUSED and want them to go to the desired insn,
2629 so we always pass it as i3. We have not counted the notes in
2630 reg_n_deaths yet, so we need to do so now. */
2632 if (newi2pat
&& new_i2_notes
)
2634 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2635 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2636 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2638 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2643 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2644 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2645 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2647 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2650 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2651 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2652 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2653 in that case, it might delete I2. Similarly for I2 and I1.
2654 Show an additional death due to the REG_DEAD note we make here. If
2655 we discard it in distribute_notes, we will decrement it again. */
2659 if (GET_CODE (i3dest_killed
) == REG
)
2660 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2662 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2665 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2669 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2673 if (i2dest_in_i2src
)
2675 if (GET_CODE (i2dest
) == REG
)
2676 REG_N_DEATHS (REGNO (i2dest
))++;
2678 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2679 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2680 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2682 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2683 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2684 NULL_RTX
, NULL_RTX
);
2687 if (i1dest_in_i1src
)
2689 if (GET_CODE (i1dest
) == REG
)
2690 REG_N_DEATHS (REGNO (i1dest
))++;
2692 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2693 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2694 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2696 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2697 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2698 NULL_RTX
, NULL_RTX
);
2701 distribute_links (i3links
);
2702 distribute_links (i2links
);
2703 distribute_links (i1links
);
2705 if (GET_CODE (i2dest
) == REG
)
2708 rtx i2_insn
= 0, i2_val
= 0, set
;
2710 /* The insn that used to set this register doesn't exist, and
2711 this life of the register may not exist either. See if one of
2712 I3's links points to an insn that sets I2DEST. If it does,
2713 that is now the last known value for I2DEST. If we don't update
2714 this and I2 set the register to a value that depended on its old
2715 contents, we will get confused. If this insn is used, thing
2716 will be set correctly in combine_instructions. */
2718 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2719 if ((set
= single_set (XEXP (link
, 0))) != 0
2720 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2721 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2723 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2725 /* If the reg formerly set in I2 died only once and that was in I3,
2726 zero its use count so it won't make `reload' do any work. */
2728 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2729 && ! i2dest_in_i2src
)
2731 regno
= REGNO (i2dest
);
2732 REG_N_SETS (regno
)--;
2736 if (i1
&& GET_CODE (i1dest
) == REG
)
2739 rtx i1_insn
= 0, i1_val
= 0, set
;
2741 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2742 if ((set
= single_set (XEXP (link
, 0))) != 0
2743 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2744 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2746 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2748 regno
= REGNO (i1dest
);
2749 if (! added_sets_1
&& ! i1dest_in_i1src
)
2750 REG_N_SETS (regno
)--;
2753 /* Update reg_nonzero_bits et al for any changes that may have been made
2754 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2755 important. Because newi2pat can affect nonzero_bits of newpat */
2757 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2758 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2760 /* Set new_direct_jump_p if a new return or simple jump instruction
2763 If I3 is now an unconditional jump, ensure that it has a
2764 BARRIER following it since it may have initially been a
2765 conditional jump. It may also be the last nonnote insn. */
2767 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2769 *new_direct_jump_p
= 1;
2771 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2772 || GET_CODE (temp
) != BARRIER
)
2773 emit_barrier_after (i3
);
2775 /* An NOOP jump does not need barrier, but it does need cleaning up
2777 if (GET_CODE (newpat
) == SET
2778 && SET_SRC (newpat
) == pc_rtx
2779 && SET_DEST (newpat
) == pc_rtx
)
2780 *new_direct_jump_p
= 1;
2783 combine_successes
++;
2786 /* Clear this here, so that subsequent get_last_value calls are not
2788 subst_prev_insn
= NULL_RTX
;
2790 if (added_links_insn
2791 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2792 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2793 return added_links_insn
;
2795 return newi2pat
? i2
: i3
;
2798 /* Undo all the modifications recorded in undobuf. */
2803 struct undo
*undo
, *next
;
2805 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2809 *undo
->where
.i
= undo
->old_contents
.i
;
2811 *undo
->where
.r
= undo
->old_contents
.r
;
2813 undo
->next
= undobuf
.frees
;
2814 undobuf
.frees
= undo
;
2819 /* Clear this here, so that subsequent get_last_value calls are not
2821 subst_prev_insn
= NULL_RTX
;
2824 /* We've committed to accepting the changes we made. Move all
2825 of the undos to the free list. */
2830 struct undo
*undo
, *next
;
2832 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2835 undo
->next
= undobuf
.frees
;
2836 undobuf
.frees
= undo
;
2842 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2843 where we have an arithmetic expression and return that point. LOC will
2846 try_combine will call this function to see if an insn can be split into
2850 find_split_point (loc
, insn
)
2855 enum rtx_code code
= GET_CODE (x
);
2857 unsigned HOST_WIDE_INT len
= 0;
2858 HOST_WIDE_INT pos
= 0;
2860 rtx inner
= NULL_RTX
;
2862 /* First special-case some codes. */
2866 #ifdef INSN_SCHEDULING
2867 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2869 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2872 return find_split_point (&SUBREG_REG (x
), insn
);
2876 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2877 using LO_SUM and HIGH. */
2878 if (GET_CODE (XEXP (x
, 0)) == CONST
2879 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2882 gen_rtx_LO_SUM (Pmode
,
2883 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2885 return &XEXP (XEXP (x
, 0), 0);
2889 /* If we have a PLUS whose second operand is a constant and the
2890 address is not valid, perhaps will can split it up using
2891 the machine-specific way to split large constants. We use
2892 the first pseudo-reg (one of the virtual regs) as a placeholder;
2893 it will not remain in the result. */
2894 if (GET_CODE (XEXP (x
, 0)) == PLUS
2895 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2896 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2898 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2899 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2902 /* This should have produced two insns, each of which sets our
2903 placeholder. If the source of the second is a valid address,
2904 we can make put both sources together and make a split point
2907 if (seq
&& XVECLEN (seq
, 0) == 2
2908 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2909 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2910 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2911 && ! reg_mentioned_p (reg
,
2912 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2913 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2914 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2915 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2916 && memory_address_p (GET_MODE (x
),
2917 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2919 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2920 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2922 /* Replace the placeholder in SRC2 with SRC1. If we can
2923 find where in SRC2 it was placed, that can become our
2924 split point and we can replace this address with SRC2.
2925 Just try two obvious places. */
2927 src2
= replace_rtx (src2
, reg
, src1
);
2929 if (XEXP (src2
, 0) == src1
)
2930 split
= &XEXP (src2
, 0);
2931 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2932 && XEXP (XEXP (src2
, 0), 0) == src1
)
2933 split
= &XEXP (XEXP (src2
, 0), 0);
2937 SUBST (XEXP (x
, 0), src2
);
2942 /* If that didn't work, perhaps the first operand is complex and
2943 needs to be computed separately, so make a split point there.
2944 This will occur on machines that just support REG + CONST
2945 and have a constant moved through some previous computation. */
2947 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2948 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2949 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2951 return &XEXP (XEXP (x
, 0), 0);
2957 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2958 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2959 we need to put the operand into a register. So split at that
2962 if (SET_DEST (x
) == cc0_rtx
2963 && GET_CODE (SET_SRC (x
)) != COMPARE
2964 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2965 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2966 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2967 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2968 return &SET_SRC (x
);
2971 /* See if we can split SET_SRC as it stands. */
2972 split
= find_split_point (&SET_SRC (x
), insn
);
2973 if (split
&& split
!= &SET_SRC (x
))
2976 /* See if we can split SET_DEST as it stands. */
2977 split
= find_split_point (&SET_DEST (x
), insn
);
2978 if (split
&& split
!= &SET_DEST (x
))
2981 /* See if this is a bitfield assignment with everything constant. If
2982 so, this is an IOR of an AND, so split it into that. */
2983 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2984 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2985 <= HOST_BITS_PER_WIDE_INT
)
2986 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2987 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2988 && GET_CODE (SET_SRC (x
)) == CONST_INT
2989 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2990 + INTVAL (XEXP (SET_DEST (x
), 2)))
2991 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2992 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2994 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2995 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2996 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2997 rtx dest
= XEXP (SET_DEST (x
), 0);
2998 enum machine_mode mode
= GET_MODE (dest
);
2999 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3001 if (BITS_BIG_ENDIAN
)
3002 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3006 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3009 gen_binary (IOR
, mode
,
3010 gen_binary (AND
, mode
, dest
,
3011 GEN_INT (~(mask
<< pos
)
3012 & GET_MODE_MASK (mode
))),
3013 GEN_INT (src
<< pos
)));
3015 SUBST (SET_DEST (x
), dest
);
3017 split
= find_split_point (&SET_SRC (x
), insn
);
3018 if (split
&& split
!= &SET_SRC (x
))
3022 /* Otherwise, see if this is an operation that we can split into two.
3023 If so, try to split that. */
3024 code
= GET_CODE (SET_SRC (x
));
3029 /* If we are AND'ing with a large constant that is only a single
3030 bit and the result is only being used in a context where we
3031 need to know if it is zero or non-zero, replace it with a bit
3032 extraction. This will avoid the large constant, which might
3033 have taken more than one insn to make. If the constant were
3034 not a valid argument to the AND but took only one insn to make,
3035 this is no worse, but if it took more than one insn, it will
3038 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3039 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3040 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3041 && GET_CODE (SET_DEST (x
)) == REG
3042 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*)0)) != 0
3043 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3044 && XEXP (*split
, 0) == SET_DEST (x
)
3045 && XEXP (*split
, 1) == const0_rtx
)
3047 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3048 XEXP (SET_SRC (x
), 0),
3049 pos
, NULL_RTX
, 1, 1, 0, 0);
3050 if (extraction
!= 0)
3052 SUBST (SET_SRC (x
), extraction
);
3053 return find_split_point (loc
, insn
);
3059 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3060 is known to be on, this can be converted into a NEG of a shift. */
3061 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3062 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3063 && 1 <= (pos
= exact_log2
3064 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3065 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3067 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3071 gen_rtx_LSHIFTRT (mode
,
3072 XEXP (SET_SRC (x
), 0),
3075 split
= find_split_point (&SET_SRC (x
), insn
);
3076 if (split
&& split
!= &SET_SRC (x
))
3082 inner
= XEXP (SET_SRC (x
), 0);
3084 /* We can't optimize if either mode is a partial integer
3085 mode as we don't know how many bits are significant
3087 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3088 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3092 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3098 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3099 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3101 inner
= XEXP (SET_SRC (x
), 0);
3102 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3103 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3105 if (BITS_BIG_ENDIAN
)
3106 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3107 unsignedp
= (code
== ZERO_EXTRACT
);
3115 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3117 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3119 /* For unsigned, we have a choice of a shift followed by an
3120 AND or two shifts. Use two shifts for field sizes where the
3121 constant might be too large. We assume here that we can
3122 always at least get 8-bit constants in an AND insn, which is
3123 true for every current RISC. */
3125 if (unsignedp
&& len
<= 8)
3130 (mode
, gen_lowpart_for_combine (mode
, inner
),
3132 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3134 split
= find_split_point (&SET_SRC (x
), insn
);
3135 if (split
&& split
!= &SET_SRC (x
))
3142 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3143 gen_rtx_ASHIFT (mode
,
3144 gen_lowpart_for_combine (mode
, inner
),
3145 GEN_INT (GET_MODE_BITSIZE (mode
)
3147 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3149 split
= find_split_point (&SET_SRC (x
), insn
);
3150 if (split
&& split
!= &SET_SRC (x
))
3155 /* See if this is a simple operation with a constant as the second
3156 operand. It might be that this constant is out of range and hence
3157 could be used as a split point. */
3158 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3159 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3160 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3161 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3162 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3163 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3164 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3166 return &XEXP (SET_SRC (x
), 1);
3168 /* Finally, see if this is a simple operation with its first operand
3169 not in a register. The operation might require this operand in a
3170 register, so return it as a split point. We can always do this
3171 because if the first operand were another operation, we would have
3172 already found it as a split point. */
3173 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3174 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3175 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3177 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3178 return &XEXP (SET_SRC (x
), 0);
3184 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3185 it is better to write this as (not (ior A B)) so we can split it.
3186 Similarly for IOR. */
3187 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3190 gen_rtx_NOT (GET_MODE (x
),
3191 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3193 XEXP (XEXP (x
, 0), 0),
3194 XEXP (XEXP (x
, 1), 0))));
3195 return find_split_point (loc
, insn
);
3198 /* Many RISC machines have a large set of logical insns. If the
3199 second operand is a NOT, put it first so we will try to split the
3200 other operand first. */
3201 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3203 rtx tem
= XEXP (x
, 0);
3204 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3205 SUBST (XEXP (x
, 1), tem
);
3213 /* Otherwise, select our actions depending on our rtx class. */
3214 switch (GET_RTX_CLASS (code
))
3216 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3218 split
= find_split_point (&XEXP (x
, 2), insn
);
3221 /* ... fall through ... */
3225 split
= find_split_point (&XEXP (x
, 1), insn
);
3228 /* ... fall through ... */
3230 /* Some machines have (and (shift ...) ...) insns. If X is not
3231 an AND, but XEXP (X, 0) is, use it as our split point. */
3232 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3233 return &XEXP (x
, 0);
3235 split
= find_split_point (&XEXP (x
, 0), insn
);
3241 /* Otherwise, we don't have a split point. */
3245 /* Throughout X, replace FROM with TO, and return the result.
3246 The result is TO if X is FROM;
3247 otherwise the result is X, but its contents may have been modified.
3248 If they were modified, a record was made in undobuf so that
3249 undo_all will (among other things) return X to its original state.
3251 If the number of changes necessary is too much to record to undo,
3252 the excess changes are not made, so the result is invalid.
3253 The changes already made can still be undone.
3254 undobuf.num_undo is incremented for such changes, so by testing that
3255 the caller can tell whether the result is valid.
3257 `n_occurrences' is incremented each time FROM is replaced.
3259 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3261 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3262 by copying if `n_occurrences' is non-zero. */
3265 subst (x
, from
, to
, in_dest
, unique_copy
)
3266 register rtx x
, from
, to
;
3270 register enum rtx_code code
= GET_CODE (x
);
3271 enum machine_mode op0_mode
= VOIDmode
;
3272 register const char *fmt
;
3273 register int len
, i
;
3276 /* Two expressions are equal if they are identical copies of a shared
3277 RTX or if they are both registers with the same register number
3280 #define COMBINE_RTX_EQUAL_P(X,Y) \
3282 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3283 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3285 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3288 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3291 /* If X and FROM are the same register but different modes, they will
3292 not have been seen as equal above. However, flow.c will make a
3293 LOG_LINKS entry for that case. If we do nothing, we will try to
3294 rerecognize our original insn and, when it succeeds, we will
3295 delete the feeding insn, which is incorrect.
3297 So force this insn not to match in this (rare) case. */
3298 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3299 && REGNO (x
) == REGNO (from
))
3300 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3302 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3303 of which may contain things that can be combined. */
3304 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3307 /* It is possible to have a subexpression appear twice in the insn.
3308 Suppose that FROM is a register that appears within TO.
3309 Then, after that subexpression has been scanned once by `subst',
3310 the second time it is scanned, TO may be found. If we were
3311 to scan TO here, we would find FROM within it and create a
3312 self-referent rtl structure which is completely wrong. */
3313 if (COMBINE_RTX_EQUAL_P (x
, to
))
3316 /* Parallel asm_operands need special attention because all of the
3317 inputs are shared across the arms. Furthermore, unsharing the
3318 rtl results in recognition failures. Failure to handle this case
3319 specially can result in circular rtl.
3321 Solve this by doing a normal pass across the first entry of the
3322 parallel, and only processing the SET_DESTs of the subsequent
3325 if (code
== PARALLEL
3326 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3327 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3329 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3331 /* If this substitution failed, this whole thing fails. */
3332 if (GET_CODE (new) == CLOBBER
3333 && XEXP (new, 0) == const0_rtx
)
3336 SUBST (XVECEXP (x
, 0, 0), new);
3338 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3340 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3342 if (GET_CODE (dest
) != REG
3343 && GET_CODE (dest
) != CC0
3344 && GET_CODE (dest
) != PC
)
3346 new = subst (dest
, from
, to
, 0, unique_copy
);
3348 /* If this substitution failed, this whole thing fails. */
3349 if (GET_CODE (new) == CLOBBER
3350 && XEXP (new, 0) == const0_rtx
)
3353 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3359 len
= GET_RTX_LENGTH (code
);
3360 fmt
= GET_RTX_FORMAT (code
);
3362 /* We don't need to process a SET_DEST that is a register, CC0,
3363 or PC, so set up to skip this common case. All other cases
3364 where we want to suppress replacing something inside a
3365 SET_SRC are handled via the IN_DEST operand. */
3367 && (GET_CODE (SET_DEST (x
)) == REG
3368 || GET_CODE (SET_DEST (x
)) == CC0
3369 || GET_CODE (SET_DEST (x
)) == PC
))
3372 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3375 op0_mode
= GET_MODE (XEXP (x
, 0));
3377 for (i
= 0; i
< len
; i
++)
3382 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3384 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3386 new = (unique_copy
&& n_occurrences
3387 ? copy_rtx (to
) : to
);
3392 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3395 /* If this substitution failed, this whole thing
3397 if (GET_CODE (new) == CLOBBER
3398 && XEXP (new, 0) == const0_rtx
)
3402 SUBST (XVECEXP (x
, i
, j
), new);
3405 else if (fmt
[i
] == 'e')
3407 /* If this is a register being set, ignore it. */
3410 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3411 || code
== ZERO_EXTRACT
)
3413 && GET_CODE (new) == REG
)
3416 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3418 /* In general, don't install a subreg involving two
3419 modes not tieable. It can worsen register
3420 allocation, and can even make invalid reload
3421 insns, since the reg inside may need to be copied
3422 from in the outside mode, and that may be invalid
3423 if it is an fp reg copied in integer mode.
3425 We allow two exceptions to this: It is valid if
3426 it is inside another SUBREG and the mode of that
3427 SUBREG and the mode of the inside of TO is
3428 tieable and it is valid if X is a SET that copies
3431 if (GET_CODE (to
) == SUBREG
3432 && ! MODES_TIEABLE_P (GET_MODE (to
),
3433 GET_MODE (SUBREG_REG (to
)))
3434 && ! (code
== SUBREG
3435 && MODES_TIEABLE_P (GET_MODE (x
),
3436 GET_MODE (SUBREG_REG (to
))))
3438 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3441 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3443 #ifdef CLASS_CANNOT_CHANGE_MODE
3445 && GET_CODE (to
) == REG
3446 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3447 && (TEST_HARD_REG_BIT
3448 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3450 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3452 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3455 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3459 /* If we are in a SET_DEST, suppress most cases unless we
3460 have gone inside a MEM, in which case we want to
3461 simplify the address. We assume here that things that
3462 are actually part of the destination have their inner
3463 parts in the first expression. This is true for SUBREG,
3464 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3465 things aside from REG and MEM that should appear in a
3467 new = subst (XEXP (x
, i
), from
, to
,
3469 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3470 || code
== ZERO_EXTRACT
))
3472 && i
== 0), unique_copy
);
3474 /* If we found that we will have to reject this combination,
3475 indicate that by returning the CLOBBER ourselves, rather than
3476 an expression containing it. This will speed things up as
3477 well as prevent accidents where two CLOBBERs are considered
3478 to be equal, thus producing an incorrect simplification. */
3480 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3483 SUBST (XEXP (x
, i
), new);
3488 /* Try to simplify X. If the simplification changed the code, it is likely
3489 that further simplification will help, so loop, but limit the number
3490 of repetitions that will be performed. */
3492 for (i
= 0; i
< 4; i
++)
3494 /* If X is sufficiently simple, don't bother trying to do anything
3496 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3497 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3499 if (GET_CODE (x
) == code
)
3502 code
= GET_CODE (x
);
3504 /* We no longer know the original mode of operand 0 since we
3505 have changed the form of X) */
3506 op0_mode
= VOIDmode
;
3512 /* Simplify X, a piece of RTL. We just operate on the expression at the
3513 outer level; call `subst' to simplify recursively. Return the new
3516 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3517 will be the iteration even if an expression with a code different from
3518 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3521 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3523 enum machine_mode op0_mode
;
3527 enum rtx_code code
= GET_CODE (x
);
3528 enum machine_mode mode
= GET_MODE (x
);
3533 /* If this is a commutative operation, put a constant last and a complex
3534 expression first. We don't need to do this for comparisons here. */
3535 if (GET_RTX_CLASS (code
) == 'c'
3536 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3539 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3540 SUBST (XEXP (x
, 1), temp
);
3543 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3544 sign extension of a PLUS with a constant, reverse the order of the sign
3545 extension and the addition. Note that this not the same as the original
3546 code, but overflow is undefined for signed values. Also note that the
3547 PLUS will have been partially moved "inside" the sign-extension, so that
3548 the first operand of X will really look like:
3549 (ashiftrt (plus (ashift A C4) C5) C4).
3551 (plus (ashiftrt (ashift A C4) C2) C4)
3552 and replace the first operand of X with that expression. Later parts
3553 of this function may simplify the expression further.
3555 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3556 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3557 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3559 We do this to simplify address expressions. */
3561 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3562 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3563 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3564 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3565 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3566 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3567 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3568 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3569 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3570 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3571 XEXP (XEXP (x
, 0), 1))) != 0)
3574 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3575 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3576 INTVAL (XEXP (XEXP (x
, 0), 1)));
3578 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3579 INTVAL (XEXP (XEXP (x
, 0), 1)));
3581 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3584 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3585 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3586 things. Check for cases where both arms are testing the same
3589 Don't do anything if all operands are very simple. */
3591 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3592 || GET_RTX_CLASS (code
) == '<')
3593 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3594 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3595 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3597 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3598 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3599 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3601 || (GET_RTX_CLASS (code
) == '1'
3602 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3603 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3604 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3607 rtx cond
, true_rtx
, false_rtx
;
3609 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3611 /* If everything is a comparison, what we have is highly unlikely
3612 to be simpler, so don't use it. */
3613 && ! (GET_RTX_CLASS (code
) == '<'
3614 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3615 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3617 rtx cop1
= const0_rtx
;
3618 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3620 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3623 /* Simplify the alternative arms; this may collapse the true and
3624 false arms to store-flag values. */
3625 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3626 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3628 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3629 is unlikely to be simpler. */
3630 if (general_operand (true_rtx
, VOIDmode
)
3631 && general_operand (false_rtx
, VOIDmode
))
3633 /* Restarting if we generate a store-flag expression will cause
3634 us to loop. Just drop through in this case. */
3636 /* If the result values are STORE_FLAG_VALUE and zero, we can
3637 just make the comparison operation. */
3638 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3639 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3640 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
)
3641 x
= gen_binary (reverse_condition (cond_code
),
3644 /* Likewise, we can make the negate of a comparison operation
3645 if the result values are - STORE_FLAG_VALUE and zero. */
3646 else if (GET_CODE (true_rtx
) == CONST_INT
3647 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3648 && false_rtx
== const0_rtx
)
3649 x
= simplify_gen_unary (NEG
, mode
,
3650 gen_binary (cond_code
, mode
, cond
,
3653 else if (GET_CODE (false_rtx
) == CONST_INT
3654 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3655 && true_rtx
== const0_rtx
)
3656 x
= simplify_gen_unary (NEG
, mode
,
3657 gen_binary (reverse_condition
3662 return gen_rtx_IF_THEN_ELSE (mode
,
3663 gen_binary (cond_code
, VOIDmode
,
3665 true_rtx
, false_rtx
);
3667 code
= GET_CODE (x
);
3668 op0_mode
= VOIDmode
;
3673 /* Try to fold this expression in case we have constants that weren't
3676 switch (GET_RTX_CLASS (code
))
3679 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3683 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3684 if (cmp_mode
== VOIDmode
)
3686 cmp_mode
= GET_MODE (XEXP (x
, 1));
3687 if (cmp_mode
== VOIDmode
)
3688 cmp_mode
= op0_mode
;
3690 temp
= simplify_relational_operation (code
, cmp_mode
,
3691 XEXP (x
, 0), XEXP (x
, 1));
3693 #ifdef FLOAT_STORE_FLAG_VALUE
3694 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3696 if (temp
== const0_rtx
)
3697 temp
= CONST0_RTX (mode
);
3699 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3705 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3709 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3710 XEXP (x
, 1), XEXP (x
, 2));
3717 code
= GET_CODE (temp
);
3718 op0_mode
= VOIDmode
;
3719 mode
= GET_MODE (temp
);
3722 /* First see if we can apply the inverse distributive law. */
3723 if (code
== PLUS
|| code
== MINUS
3724 || code
== AND
|| code
== IOR
|| code
== XOR
)
3726 x
= apply_distributive_law (x
);
3727 code
= GET_CODE (x
);
3728 op0_mode
= VOIDmode
;
3731 /* If CODE is an associative operation not otherwise handled, see if we
3732 can associate some operands. This can win if they are constants or
3733 if they are logically related (i.e. (a & b) & a). */
3734 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3735 || code
== AND
|| code
== IOR
|| code
== XOR
3736 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3737 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3738 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3740 if (GET_CODE (XEXP (x
, 0)) == code
)
3742 rtx other
= XEXP (XEXP (x
, 0), 0);
3743 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3744 rtx inner_op1
= XEXP (x
, 1);
3747 /* Make sure we pass the constant operand if any as the second
3748 one if this is a commutative operation. */
3749 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3751 rtx tem
= inner_op0
;
3752 inner_op0
= inner_op1
;
3755 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3756 : code
== DIV
? MULT
3758 mode
, inner_op0
, inner_op1
);
3760 /* For commutative operations, try the other pair if that one
3762 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3764 other
= XEXP (XEXP (x
, 0), 1);
3765 inner
= simplify_binary_operation (code
, mode
,
3766 XEXP (XEXP (x
, 0), 0),
3771 return gen_binary (code
, mode
, other
, inner
);
3775 /* A little bit of algebraic simplification here. */
3779 /* Ensure that our address has any ASHIFTs converted to MULT in case
3780 address-recognizing predicates are called later. */
3781 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3782 SUBST (XEXP (x
, 0), temp
);
3786 if (op0_mode
== VOIDmode
)
3787 op0_mode
= GET_MODE (SUBREG_REG (x
));
3789 /* simplify_subreg can't use gen_lowpart_for_combine. */
3790 if (CONSTANT_P (SUBREG_REG (x
))
3791 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
))
3792 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3796 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3802 /* Note that we cannot do any narrowing for non-constants since
3803 we might have been counting on using the fact that some bits were
3804 zero. We now do this in the SET. */
3809 /* (not (plus X -1)) can become (neg X). */
3810 if (GET_CODE (XEXP (x
, 0)) == PLUS
3811 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3812 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3814 /* Similarly, (not (neg X)) is (plus X -1). */
3815 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3816 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3818 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3819 if (GET_CODE (XEXP (x
, 0)) == XOR
3820 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3821 && (temp
= simplify_unary_operation (NOT
, mode
,
3822 XEXP (XEXP (x
, 0), 1),
3824 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3826 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3827 other than 1, but that is not valid. We could do a similar
3828 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3829 but this doesn't seem common enough to bother with. */
3830 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3831 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3832 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3834 XEXP (XEXP (x
, 0), 1));
3836 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3837 && subreg_lowpart_p (XEXP (x
, 0))
3838 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3839 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3840 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3841 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3843 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3845 x
= gen_rtx_ROTATE (inner_mode
,
3846 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3848 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3849 return gen_lowpart_for_combine (mode
, x
);
3852 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3853 reversing the comparison code if valid. */
3854 if (STORE_FLAG_VALUE
== -1
3855 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3856 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3857 XEXP (XEXP (x
, 0), 1))))
3860 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3861 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3862 perform the above simplification. */
3864 if (STORE_FLAG_VALUE
== -1
3865 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3866 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3867 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3868 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3870 /* Apply De Morgan's laws to reduce number of patterns for machines
3871 with negating logical insns (and-not, nand, etc.). If result has
3872 only one NOT, put it first, since that is how the patterns are
3875 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3877 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3878 enum machine_mode op_mode
;
3880 op_mode
= GET_MODE (in1
);
3881 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3883 op_mode
= GET_MODE (in2
);
3884 if (op_mode
== VOIDmode
)
3886 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3888 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3891 in2
= in1
; in1
= tem
;
3894 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3900 /* (neg (plus X 1)) can become (not X). */
3901 if (GET_CODE (XEXP (x
, 0)) == PLUS
3902 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3903 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
3905 /* Similarly, (neg (not X)) is (plus X 1). */
3906 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3907 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3909 /* (neg (minus X Y)) can become (minus Y X). */
3910 if (GET_CODE (XEXP (x
, 0)) == MINUS
3911 && (! FLOAT_MODE_P (mode
)
3912 /* x-y != -(y-x) with IEEE floating point. */
3913 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3914 || flag_unsafe_math_optimizations
))
3915 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3916 XEXP (XEXP (x
, 0), 0));
3918 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3919 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3920 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3921 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3923 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3924 if we can then eliminate the NEG (e.g.,
3925 if the operand is a constant). */
3927 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3929 temp
= simplify_unary_operation (NEG
, mode
,
3930 XEXP (XEXP (x
, 0), 0), mode
);
3932 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3935 temp
= expand_compound_operation (XEXP (x
, 0));
3937 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3938 replaced by (lshiftrt X C). This will convert
3939 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3941 if (GET_CODE (temp
) == ASHIFTRT
3942 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3943 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3944 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3945 INTVAL (XEXP (temp
, 1)));
3947 /* If X has only a single bit that might be nonzero, say, bit I, convert
3948 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3949 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3950 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3951 or a SUBREG of one since we'd be making the expression more
3952 complex if it was just a register. */
3954 if (GET_CODE (temp
) != REG
3955 && ! (GET_CODE (temp
) == SUBREG
3956 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3957 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3959 rtx temp1
= simplify_shift_const
3960 (NULL_RTX
, ASHIFTRT
, mode
,
3961 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3962 GET_MODE_BITSIZE (mode
) - 1 - i
),
3963 GET_MODE_BITSIZE (mode
) - 1 - i
);
3965 /* If all we did was surround TEMP with the two shifts, we
3966 haven't improved anything, so don't use it. Otherwise,
3967 we are better off with TEMP1. */
3968 if (GET_CODE (temp1
) != ASHIFTRT
3969 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3970 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3976 /* We can't handle truncation to a partial integer mode here
3977 because we don't know the real bitsize of the partial
3979 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3982 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3983 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3984 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3986 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3987 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3989 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3990 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3991 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3992 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3993 return XEXP (XEXP (x
, 0), 0);
3995 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3996 (OP:SI foo:SI) if OP is NEG or ABS. */
3997 if ((GET_CODE (XEXP (x
, 0)) == ABS
3998 || GET_CODE (XEXP (x
, 0)) == NEG
)
3999 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4000 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4001 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4002 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4003 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4005 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4007 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4008 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4009 && subreg_lowpart_p (XEXP (x
, 0)))
4010 return SUBREG_REG (XEXP (x
, 0));
4012 /* If we know that the value is already truncated, we can
4013 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4014 is nonzero for the corresponding modes. But don't do this
4015 for an (LSHIFTRT (MULT ...)) since this will cause problems
4016 with the umulXi3_highpart patterns. */
4017 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4018 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4019 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4020 >= GET_MODE_BITSIZE (mode
) + 1
4021 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4022 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4023 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4025 /* A truncate of a comparison can be replaced with a subreg if
4026 STORE_FLAG_VALUE permits. This is like the previous test,
4027 but it works even if the comparison is done in a mode larger
4028 than HOST_BITS_PER_WIDE_INT. */
4029 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4030 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4031 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4032 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4034 /* Similarly, a truncate of a register whose value is a
4035 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4037 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4038 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4039 && (temp
= get_last_value (XEXP (x
, 0)))
4040 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4041 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4045 case FLOAT_TRUNCATE
:
4046 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4047 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4048 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4049 return XEXP (XEXP (x
, 0), 0);
4051 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4052 (OP:SF foo:SF) if OP is NEG or ABS. */
4053 if ((GET_CODE (XEXP (x
, 0)) == ABS
4054 || GET_CODE (XEXP (x
, 0)) == NEG
)
4055 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4056 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4057 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4058 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4060 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4061 is (float_truncate:SF x). */
4062 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4063 && subreg_lowpart_p (XEXP (x
, 0))
4064 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4065 return SUBREG_REG (XEXP (x
, 0));
4070 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4071 using cc0, in which case we want to leave it as a COMPARE
4072 so we can distinguish it from a register-register-copy. */
4073 if (XEXP (x
, 1) == const0_rtx
)
4076 /* In IEEE floating point, x-0 is not the same as x. */
4077 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4078 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4079 || flag_unsafe_math_optimizations
)
4080 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4086 /* (const (const X)) can become (const X). Do it this way rather than
4087 returning the inner CONST since CONST can be shared with a
4089 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4090 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4095 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4096 can add in an offset. find_split_point will split this address up
4097 again if it doesn't match. */
4098 if (GET_CODE (XEXP (x
, 0)) == HIGH
4099 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4105 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4106 outermost. That's because that's the way indexed addresses are
4107 supposed to appear. This code used to check many more cases, but
4108 they are now checked elsewhere. */
4109 if (GET_CODE (XEXP (x
, 0)) == PLUS
4110 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4111 return gen_binary (PLUS
, mode
,
4112 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4114 XEXP (XEXP (x
, 0), 1));
4116 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4117 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4118 bit-field and can be replaced by either a sign_extend or a
4119 sign_extract. The `and' may be a zero_extend and the two
4120 <c>, -<c> constants may be reversed. */
4121 if (GET_CODE (XEXP (x
, 0)) == XOR
4122 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4123 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4124 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4125 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4126 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4127 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4128 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4129 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4130 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4131 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4132 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4133 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4134 == (unsigned int) i
+ 1))))
4135 return simplify_shift_const
4136 (NULL_RTX
, ASHIFTRT
, mode
,
4137 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4138 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4139 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4140 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4142 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4143 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4144 is 1. This produces better code than the alternative immediately
4146 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4147 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4148 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4149 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4150 XEXP (XEXP (x
, 0), 0),
4151 XEXP (XEXP (x
, 0), 1))))
4153 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4155 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4156 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4157 the bitsize of the mode - 1. This allows simplification of
4158 "a = (b & 8) == 0;" */
4159 if (XEXP (x
, 1) == constm1_rtx
4160 && GET_CODE (XEXP (x
, 0)) != REG
4161 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4162 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4163 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4164 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4165 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4166 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4167 GET_MODE_BITSIZE (mode
) - 1),
4168 GET_MODE_BITSIZE (mode
) - 1);
4170 /* If we are adding two things that have no bits in common, convert
4171 the addition into an IOR. This will often be further simplified,
4172 for example in cases like ((a & 1) + (a & 2)), which can
4175 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4176 && (nonzero_bits (XEXP (x
, 0), mode
)
4177 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4179 /* Try to simplify the expression further. */
4180 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4181 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4183 /* If we could, great. If not, do not go ahead with the IOR
4184 replacement, since PLUS appears in many special purpose
4185 address arithmetic instructions. */
4186 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4192 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4193 by reversing the comparison code if valid. */
4194 if (STORE_FLAG_VALUE
== 1
4195 && XEXP (x
, 0) == const1_rtx
4196 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4197 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4198 XEXP (XEXP (x
, 1), 0),
4199 XEXP (XEXP (x
, 1), 1))))
4202 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4203 (and <foo> (const_int pow2-1)) */
4204 if (GET_CODE (XEXP (x
, 1)) == AND
4205 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4206 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4207 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4208 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4209 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4211 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4213 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4214 return gen_binary (MINUS
, mode
,
4215 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4216 XEXP (XEXP (x
, 1), 0)),
4217 XEXP (XEXP (x
, 1), 1));
4221 /* If we have (mult (plus A B) C), apply the distributive law and then
4222 the inverse distributive law to see if things simplify. This
4223 occurs mostly in addresses, often when unrolling loops. */
4225 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4227 x
= apply_distributive_law
4228 (gen_binary (PLUS
, mode
,
4229 gen_binary (MULT
, mode
,
4230 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4231 gen_binary (MULT
, mode
,
4232 XEXP (XEXP (x
, 0), 1),
4233 copy_rtx (XEXP (x
, 1)))));
4235 if (GET_CODE (x
) != MULT
)
4238 /* Try simplify a*(b/c) as (a*b)/c. */
4239 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4240 && GET_CODE (XEXP (x
, 0)) == DIV
)
4242 rtx tem
= simplify_binary_operation (MULT
, mode
,
4243 XEXP (XEXP (x
, 0), 0),
4246 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4251 /* If this is a divide by a power of two, treat it as a shift if
4252 its first operand is a shift. */
4253 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4254 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4255 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4256 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4257 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4258 || GET_CODE (XEXP (x
, 0)) == ROTATE
4259 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4260 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4264 case GT
: case GTU
: case GE
: case GEU
:
4265 case LT
: case LTU
: case LE
: case LEU
:
4266 case UNEQ
: case LTGT
:
4267 case UNGT
: case UNGE
:
4268 case UNLT
: case UNLE
:
4269 case UNORDERED
: case ORDERED
:
4270 /* If the first operand is a condition code, we can't do anything
4272 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4273 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4275 && XEXP (x
, 0) != cc0_rtx
4279 rtx op0
= XEXP (x
, 0);
4280 rtx op1
= XEXP (x
, 1);
4281 enum rtx_code new_code
;
4283 if (GET_CODE (op0
) == COMPARE
)
4284 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4286 /* Simplify our comparison, if possible. */
4287 new_code
= simplify_comparison (code
, &op0
, &op1
);
4289 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4290 if only the low-order bit is possibly nonzero in X (such as when
4291 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4292 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4293 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4296 Remove any ZERO_EXTRACT we made when thinking this was a
4297 comparison. It may now be simpler to use, e.g., an AND. If a
4298 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4299 the call to make_compound_operation in the SET case. */
4301 if (STORE_FLAG_VALUE
== 1
4302 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4303 && op1
== const0_rtx
4304 && mode
== GET_MODE (op0
)
4305 && nonzero_bits (op0
, mode
) == 1)
4306 return gen_lowpart_for_combine (mode
,
4307 expand_compound_operation (op0
));
4309 else if (STORE_FLAG_VALUE
== 1
4310 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4311 && op1
== const0_rtx
4312 && mode
== GET_MODE (op0
)
4313 && (num_sign_bit_copies (op0
, mode
)
4314 == GET_MODE_BITSIZE (mode
)))
4316 op0
= expand_compound_operation (op0
);
4317 return simplify_gen_unary (NEG
, mode
,
4318 gen_lowpart_for_combine (mode
, op0
),
4322 else if (STORE_FLAG_VALUE
== 1
4323 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4324 && op1
== const0_rtx
4325 && mode
== GET_MODE (op0
)
4326 && nonzero_bits (op0
, mode
) == 1)
4328 op0
= expand_compound_operation (op0
);
4329 return gen_binary (XOR
, mode
,
4330 gen_lowpart_for_combine (mode
, op0
),
4334 else if (STORE_FLAG_VALUE
== 1
4335 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4336 && op1
== const0_rtx
4337 && mode
== GET_MODE (op0
)
4338 && (num_sign_bit_copies (op0
, mode
)
4339 == GET_MODE_BITSIZE (mode
)))
4341 op0
= expand_compound_operation (op0
);
4342 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4345 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4347 if (STORE_FLAG_VALUE
== -1
4348 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4349 && op1
== const0_rtx
4350 && (num_sign_bit_copies (op0
, mode
)
4351 == GET_MODE_BITSIZE (mode
)))
4352 return gen_lowpart_for_combine (mode
,
4353 expand_compound_operation (op0
));
4355 else if (STORE_FLAG_VALUE
== -1
4356 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4357 && op1
== const0_rtx
4358 && mode
== GET_MODE (op0
)
4359 && nonzero_bits (op0
, mode
) == 1)
4361 op0
= expand_compound_operation (op0
);
4362 return simplify_gen_unary (NEG
, mode
,
4363 gen_lowpart_for_combine (mode
, op0
),
4367 else if (STORE_FLAG_VALUE
== -1
4368 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4369 && op1
== const0_rtx
4370 && mode
== GET_MODE (op0
)
4371 && (num_sign_bit_copies (op0
, mode
)
4372 == GET_MODE_BITSIZE (mode
)))
4374 op0
= expand_compound_operation (op0
);
4375 return simplify_gen_unary (NOT
, mode
,
4376 gen_lowpart_for_combine (mode
, op0
),
4380 /* If X is 0/1, (eq X 0) is X-1. */
4381 else if (STORE_FLAG_VALUE
== -1
4382 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4383 && op1
== const0_rtx
4384 && mode
== GET_MODE (op0
)
4385 && nonzero_bits (op0
, mode
) == 1)
4387 op0
= expand_compound_operation (op0
);
4388 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4391 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4392 one bit that might be nonzero, we can convert (ne x 0) to
4393 (ashift x c) where C puts the bit in the sign bit. Remove any
4394 AND with STORE_FLAG_VALUE when we are done, since we are only
4395 going to test the sign bit. */
4396 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4397 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4398 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4399 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4400 && op1
== const0_rtx
4401 && mode
== GET_MODE (op0
)
4402 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4404 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4405 expand_compound_operation (op0
),
4406 GET_MODE_BITSIZE (mode
) - 1 - i
);
4407 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4413 /* If the code changed, return a whole new comparison. */
4414 if (new_code
!= code
)
4415 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4417 /* Otherwise, keep this operation, but maybe change its operands.
4418 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4419 SUBST (XEXP (x
, 0), op0
);
4420 SUBST (XEXP (x
, 1), op1
);
4425 return simplify_if_then_else (x
);
4431 /* If we are processing SET_DEST, we are done. */
4435 return expand_compound_operation (x
);
4438 return simplify_set (x
);
4443 return simplify_logical (x
, last
);
4446 /* (abs (neg <foo>)) -> (abs <foo>) */
4447 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4448 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4450 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4452 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4455 /* If operand is something known to be positive, ignore the ABS. */
4456 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4457 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4458 <= HOST_BITS_PER_WIDE_INT
)
4459 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4460 & ((HOST_WIDE_INT
) 1
4461 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4465 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4466 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4467 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4472 /* (ffs (*_extend <X>)) = (ffs <X>) */
4473 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4474 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4475 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4479 /* (float (sign_extend <X>)) = (float <X>). */
4480 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4481 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4489 /* If this is a shift by a constant amount, simplify it. */
4490 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4491 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4492 INTVAL (XEXP (x
, 1)));
4494 #ifdef SHIFT_COUNT_TRUNCATED
4495 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4497 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4499 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4508 rtx op0
= XEXP (x
, 0);
4509 rtx op1
= XEXP (x
, 1);
4512 if (GET_CODE (op1
) != PARALLEL
)
4514 len
= XVECLEN (op1
, 0);
4516 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4517 && GET_CODE (op0
) == VEC_CONCAT
)
4519 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4521 /* Try to find the element in the VEC_CONCAT. */
4524 if (GET_MODE (op0
) == GET_MODE (x
))
4526 if (GET_CODE (op0
) == VEC_CONCAT
)
4528 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4529 if (op0_size
< offset
)
4530 op0
= XEXP (op0
, 0);
4534 op0
= XEXP (op0
, 1);
4552 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4555 simplify_if_then_else (x
)
4558 enum machine_mode mode
= GET_MODE (x
);
4559 rtx cond
= XEXP (x
, 0);
4560 rtx true_rtx
= XEXP (x
, 1);
4561 rtx false_rtx
= XEXP (x
, 2);
4562 enum rtx_code true_code
= GET_CODE (cond
);
4563 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4566 enum rtx_code false_code
;
4569 /* Simplify storing of the truth value. */
4570 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4571 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4573 /* Also when the truth value has to be reversed. */
4575 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4576 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4580 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4581 in it is being compared against certain values. Get the true and false
4582 comparisons and see if that says anything about the value of each arm. */
4585 && ((false_code
= combine_reversed_comparison_code (cond
))
4587 && GET_CODE (XEXP (cond
, 0)) == REG
)
4590 rtx from
= XEXP (cond
, 0);
4591 rtx true_val
= XEXP (cond
, 1);
4592 rtx false_val
= true_val
;
4595 /* If FALSE_CODE is EQ, swap the codes and arms. */
4597 if (false_code
== EQ
)
4599 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4600 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4603 /* If we are comparing against zero and the expression being tested has
4604 only a single bit that might be nonzero, that is its value when it is
4605 not equal to zero. Similarly if it is known to be -1 or 0. */
4607 if (true_code
== EQ
&& true_val
== const0_rtx
4608 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4609 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4610 else if (true_code
== EQ
&& true_val
== const0_rtx
4611 && (num_sign_bit_copies (from
, GET_MODE (from
))
4612 == GET_MODE_BITSIZE (GET_MODE (from
))))
4613 false_code
= EQ
, false_val
= constm1_rtx
;
4615 /* Now simplify an arm if we know the value of the register in the
4616 branch and it is used in the arm. Be careful due to the potential
4617 of locally-shared RTL. */
4619 if (reg_mentioned_p (from
, true_rtx
))
4620 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4622 pc_rtx
, pc_rtx
, 0, 0);
4623 if (reg_mentioned_p (from
, false_rtx
))
4624 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4626 pc_rtx
, pc_rtx
, 0, 0);
4628 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4629 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4631 true_rtx
= XEXP (x
, 1);
4632 false_rtx
= XEXP (x
, 2);
4633 true_code
= GET_CODE (cond
);
4636 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4637 reversed, do so to avoid needing two sets of patterns for
4638 subtract-and-branch insns. Similarly if we have a constant in the true
4639 arm, the false arm is the same as the first operand of the comparison, or
4640 the false arm is more complicated than the true arm. */
4643 && combine_reversed_comparison_code (cond
) != UNKNOWN
4644 && (true_rtx
== pc_rtx
4645 || (CONSTANT_P (true_rtx
)
4646 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4647 || true_rtx
== const0_rtx
4648 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4649 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4650 || (GET_CODE (true_rtx
) == SUBREG
4651 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4652 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4653 || reg_mentioned_p (true_rtx
, false_rtx
)
4654 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4656 true_code
= reversed_comparison_code (cond
, NULL
);
4658 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4661 SUBST (XEXP (x
, 1), false_rtx
);
4662 SUBST (XEXP (x
, 2), true_rtx
);
4664 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4667 /* It is possible that the conditional has been simplified out. */
4668 true_code
= GET_CODE (cond
);
4669 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4672 /* If the two arms are identical, we don't need the comparison. */
4674 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4677 /* Convert a == b ? b : a to "a". */
4678 if (true_code
== EQ
&& ! side_effects_p (cond
)
4679 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4680 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4681 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4683 else if (true_code
== NE
&& ! side_effects_p (cond
)
4684 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4685 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4686 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4689 /* Look for cases where we have (abs x) or (neg (abs X)). */
4691 if (GET_MODE_CLASS (mode
) == MODE_INT
4692 && GET_CODE (false_rtx
) == NEG
4693 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4695 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4696 && ! side_effects_p (true_rtx
))
4701 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4705 simplify_gen_unary (NEG
, mode
,
4706 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4712 /* Look for MIN or MAX. */
4714 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4716 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4717 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4718 && ! side_effects_p (cond
))
4723 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4726 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4729 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4732 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4737 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4738 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4739 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4740 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4741 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4742 neither 1 or -1, but it isn't worth checking for. */
4744 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4745 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4747 rtx t
= make_compound_operation (true_rtx
, SET
);
4748 rtx f
= make_compound_operation (false_rtx
, SET
);
4749 rtx cond_op0
= XEXP (cond
, 0);
4750 rtx cond_op1
= XEXP (cond
, 1);
4751 enum rtx_code op
= NIL
, extend_op
= NIL
;
4752 enum machine_mode m
= mode
;
4753 rtx z
= 0, c1
= NULL_RTX
;
4755 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4756 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4757 || GET_CODE (t
) == ASHIFT
4758 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4759 && rtx_equal_p (XEXP (t
, 0), f
))
4760 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4762 /* If an identity-zero op is commutative, check whether there
4763 would be a match if we swapped the operands. */
4764 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4765 || GET_CODE (t
) == XOR
)
4766 && rtx_equal_p (XEXP (t
, 1), f
))
4767 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4768 else if (GET_CODE (t
) == SIGN_EXTEND
4769 && (GET_CODE (XEXP (t
, 0)) == PLUS
4770 || GET_CODE (XEXP (t
, 0)) == MINUS
4771 || GET_CODE (XEXP (t
, 0)) == IOR
4772 || GET_CODE (XEXP (t
, 0)) == XOR
4773 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4774 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4775 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4776 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4777 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4778 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4779 && (num_sign_bit_copies (f
, GET_MODE (f
))
4780 > (GET_MODE_BITSIZE (mode
)
4781 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4783 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4784 extend_op
= SIGN_EXTEND
;
4785 m
= GET_MODE (XEXP (t
, 0));
4787 else if (GET_CODE (t
) == SIGN_EXTEND
4788 && (GET_CODE (XEXP (t
, 0)) == PLUS
4789 || GET_CODE (XEXP (t
, 0)) == IOR
4790 || GET_CODE (XEXP (t
, 0)) == XOR
)
4791 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4792 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4793 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4794 && (num_sign_bit_copies (f
, GET_MODE (f
))
4795 > (GET_MODE_BITSIZE (mode
)
4796 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4798 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4799 extend_op
= SIGN_EXTEND
;
4800 m
= GET_MODE (XEXP (t
, 0));
4802 else if (GET_CODE (t
) == ZERO_EXTEND
4803 && (GET_CODE (XEXP (t
, 0)) == PLUS
4804 || GET_CODE (XEXP (t
, 0)) == MINUS
4805 || GET_CODE (XEXP (t
, 0)) == IOR
4806 || GET_CODE (XEXP (t
, 0)) == XOR
4807 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4808 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4809 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4810 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4811 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4812 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4813 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4814 && ((nonzero_bits (f
, GET_MODE (f
))
4815 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4818 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4819 extend_op
= ZERO_EXTEND
;
4820 m
= GET_MODE (XEXP (t
, 0));
4822 else if (GET_CODE (t
) == ZERO_EXTEND
4823 && (GET_CODE (XEXP (t
, 0)) == PLUS
4824 || GET_CODE (XEXP (t
, 0)) == IOR
4825 || GET_CODE (XEXP (t
, 0)) == XOR
)
4826 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4827 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4828 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4829 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4830 && ((nonzero_bits (f
, GET_MODE (f
))
4831 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4834 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4835 extend_op
= ZERO_EXTEND
;
4836 m
= GET_MODE (XEXP (t
, 0));
4841 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4842 pc_rtx
, pc_rtx
, 0, 0);
4843 temp
= gen_binary (MULT
, m
, temp
,
4844 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4845 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4846 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4848 if (extend_op
!= NIL
)
4849 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4855 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4856 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4857 negation of a single bit, we can convert this operation to a shift. We
4858 can actually do this more generally, but it doesn't seem worth it. */
4860 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4861 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4862 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4863 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4864 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4865 == GET_MODE_BITSIZE (mode
))
4866 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4868 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4869 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4874 /* Simplify X, a SET expression. Return the new expression. */
4880 rtx src
= SET_SRC (x
);
4881 rtx dest
= SET_DEST (x
);
4882 enum machine_mode mode
4883 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4887 /* (set (pc) (return)) gets written as (return). */
4888 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4891 /* Now that we know for sure which bits of SRC we are using, see if we can
4892 simplify the expression for the object knowing that we only need the
4895 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4897 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4898 SUBST (SET_SRC (x
), src
);
4901 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4902 the comparison result and try to simplify it unless we already have used
4903 undobuf.other_insn. */
4904 if ((GET_CODE (src
) == COMPARE
4909 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4910 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4911 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4912 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4914 enum rtx_code old_code
= GET_CODE (*cc_use
);
4915 enum rtx_code new_code
;
4917 int other_changed
= 0;
4918 enum machine_mode compare_mode
= GET_MODE (dest
);
4920 if (GET_CODE (src
) == COMPARE
)
4921 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4923 op0
= src
, op1
= const0_rtx
;
4925 /* Simplify our comparison, if possible. */
4926 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4928 #ifdef EXTRA_CC_MODES
4929 /* If this machine has CC modes other than CCmode, check to see if we
4930 need to use a different CC mode here. */
4931 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4932 #endif /* EXTRA_CC_MODES */
4934 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4935 /* If the mode changed, we have to change SET_DEST, the mode in the
4936 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4937 a hard register, just build new versions with the proper mode. If it
4938 is a pseudo, we lose unless it is only time we set the pseudo, in
4939 which case we can safely change its mode. */
4940 if (compare_mode
!= GET_MODE (dest
))
4942 unsigned int regno
= REGNO (dest
);
4943 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4945 if (regno
< FIRST_PSEUDO_REGISTER
4946 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4948 if (regno
>= FIRST_PSEUDO_REGISTER
)
4949 SUBST (regno_reg_rtx
[regno
], new_dest
);
4951 SUBST (SET_DEST (x
), new_dest
);
4952 SUBST (XEXP (*cc_use
, 0), new_dest
);
4960 /* If the code changed, we have to build a new comparison in
4961 undobuf.other_insn. */
4962 if (new_code
!= old_code
)
4964 unsigned HOST_WIDE_INT mask
;
4966 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
4969 /* If the only change we made was to change an EQ into an NE or
4970 vice versa, OP0 has only one bit that might be nonzero, and OP1
4971 is zero, check if changing the user of the condition code will
4972 produce a valid insn. If it won't, we can keep the original code
4973 in that insn by surrounding our operation with an XOR. */
4975 if (((old_code
== NE
&& new_code
== EQ
)
4976 || (old_code
== EQ
&& new_code
== NE
))
4977 && ! other_changed
&& op1
== const0_rtx
4978 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4979 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4981 rtx pat
= PATTERN (other_insn
), note
= 0;
4983 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4984 && ! check_asm_operands (pat
)))
4986 PUT_CODE (*cc_use
, old_code
);
4989 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4997 undobuf
.other_insn
= other_insn
;
5000 /* If we are now comparing against zero, change our source if
5001 needed. If we do not use cc0, we always have a COMPARE. */
5002 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5004 SUBST (SET_SRC (x
), op0
);
5010 /* Otherwise, if we didn't previously have a COMPARE in the
5011 correct mode, we need one. */
5012 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5014 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5019 /* Otherwise, update the COMPARE if needed. */
5020 SUBST (XEXP (src
, 0), op0
);
5021 SUBST (XEXP (src
, 1), op1
);
5026 /* Get SET_SRC in a form where we have placed back any
5027 compound expressions. Then do the checks below. */
5028 src
= make_compound_operation (src
, SET
);
5029 SUBST (SET_SRC (x
), src
);
5032 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5033 and X being a REG or (subreg (reg)), we may be able to convert this to
5034 (set (subreg:m2 x) (op)).
5036 We can always do this if M1 is narrower than M2 because that means that
5037 we only care about the low bits of the result.
5039 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5040 perform a narrower operation than requested since the high-order bits will
5041 be undefined. On machine where it is defined, this transformation is safe
5042 as long as M1 and M2 have the same number of words. */
5044 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5045 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5046 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5048 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5049 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5050 #ifndef WORD_REGISTER_OPERATIONS
5051 && (GET_MODE_SIZE (GET_MODE (src
))
5052 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5054 #ifdef CLASS_CANNOT_CHANGE_MODE
5055 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5056 && (TEST_HARD_REG_BIT
5057 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5059 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5060 GET_MODE (SUBREG_REG (src
))))
5062 && (GET_CODE (dest
) == REG
5063 || (GET_CODE (dest
) == SUBREG
5064 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5066 SUBST (SET_DEST (x
),
5067 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5069 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5071 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5074 #ifdef LOAD_EXTEND_OP
5075 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5076 would require a paradoxical subreg. Replace the subreg with a
5077 zero_extend to avoid the reload that would otherwise be required. */
5079 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5080 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5081 && SUBREG_BYTE (src
) == 0
5082 && (GET_MODE_SIZE (GET_MODE (src
))
5083 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5084 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5087 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5088 GET_MODE (src
), SUBREG_REG (src
)));
5094 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5095 are comparing an item known to be 0 or -1 against 0, use a logical
5096 operation instead. Check for one of the arms being an IOR of the other
5097 arm with some value. We compute three terms to be IOR'ed together. In
5098 practice, at most two will be nonzero. Then we do the IOR's. */
5100 if (GET_CODE (dest
) != PC
5101 && GET_CODE (src
) == IF_THEN_ELSE
5102 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5103 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5104 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5105 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5106 #ifdef HAVE_conditional_move
5107 && ! can_conditionally_move_p (GET_MODE (src
))
5109 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5110 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5111 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5112 && ! side_effects_p (src
))
5114 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5115 ? XEXP (src
, 1) : XEXP (src
, 2));
5116 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5117 ? XEXP (src
, 2) : XEXP (src
, 1));
5118 rtx term1
= const0_rtx
, term2
, term3
;
5120 if (GET_CODE (true_rtx
) == IOR
5121 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5122 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5123 else if (GET_CODE (true_rtx
) == IOR
5124 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5125 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5126 else if (GET_CODE (false_rtx
) == IOR
5127 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5128 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5129 else if (GET_CODE (false_rtx
) == IOR
5130 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5131 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5133 term2
= gen_binary (AND
, GET_MODE (src
),
5134 XEXP (XEXP (src
, 0), 0), true_rtx
);
5135 term3
= gen_binary (AND
, GET_MODE (src
),
5136 simplify_gen_unary (NOT
, GET_MODE (src
),
5137 XEXP (XEXP (src
, 0), 0),
5142 gen_binary (IOR
, GET_MODE (src
),
5143 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5149 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5150 whole thing fail. */
5151 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5153 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5156 /* Convert this into a field assignment operation, if possible. */
5157 return make_field_assignment (x
);
5160 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5161 result. LAST is nonzero if this is the last retry. */
5164 simplify_logical (x
, last
)
5168 enum machine_mode mode
= GET_MODE (x
);
5169 rtx op0
= XEXP (x
, 0);
5170 rtx op1
= XEXP (x
, 1);
5173 switch (GET_CODE (x
))
5176 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5177 insn (and may simplify more). */
5178 if (GET_CODE (op0
) == XOR
5179 && rtx_equal_p (XEXP (op0
, 0), op1
)
5180 && ! side_effects_p (op1
))
5181 x
= gen_binary (AND
, mode
,
5182 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5185 if (GET_CODE (op0
) == XOR
5186 && rtx_equal_p (XEXP (op0
, 1), op1
)
5187 && ! side_effects_p (op1
))
5188 x
= gen_binary (AND
, mode
,
5189 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5192 /* Similarly for (~(A ^ B)) & A. */
5193 if (GET_CODE (op0
) == NOT
5194 && GET_CODE (XEXP (op0
, 0)) == XOR
5195 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5196 && ! side_effects_p (op1
))
5197 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5199 if (GET_CODE (op0
) == NOT
5200 && GET_CODE (XEXP (op0
, 0)) == XOR
5201 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5202 && ! side_effects_p (op1
))
5203 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5205 /* We can call simplify_and_const_int only if we don't lose
5206 any (sign) bits when converting INTVAL (op1) to
5207 "unsigned HOST_WIDE_INT". */
5208 if (GET_CODE (op1
) == CONST_INT
5209 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5210 || INTVAL (op1
) > 0))
5212 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5214 /* If we have (ior (and (X C1) C2)) and the next restart would be
5215 the last, simplify this by making C1 as small as possible
5218 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5219 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5220 && GET_CODE (op1
) == CONST_INT
)
5221 return gen_binary (IOR
, mode
,
5222 gen_binary (AND
, mode
, XEXP (op0
, 0),
5223 GEN_INT (INTVAL (XEXP (op0
, 1))
5224 & ~INTVAL (op1
))), op1
);
5226 if (GET_CODE (x
) != AND
)
5229 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5230 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5231 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5234 /* Convert (A | B) & A to A. */
5235 if (GET_CODE (op0
) == IOR
5236 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5237 || rtx_equal_p (XEXP (op0
, 1), op1
))
5238 && ! side_effects_p (XEXP (op0
, 0))
5239 && ! side_effects_p (XEXP (op0
, 1)))
5242 /* In the following group of tests (and those in case IOR below),
5243 we start with some combination of logical operations and apply
5244 the distributive law followed by the inverse distributive law.
5245 Most of the time, this results in no change. However, if some of
5246 the operands are the same or inverses of each other, simplifications
5249 For example, (and (ior A B) (not B)) can occur as the result of
5250 expanding a bit field assignment. When we apply the distributive
5251 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5252 which then simplifies to (and (A (not B))).
5254 If we have (and (ior A B) C), apply the distributive law and then
5255 the inverse distributive law to see if things simplify. */
5257 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5259 x
= apply_distributive_law
5260 (gen_binary (GET_CODE (op0
), mode
,
5261 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5262 gen_binary (AND
, mode
, XEXP (op0
, 1),
5264 if (GET_CODE (x
) != AND
)
5268 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5269 return apply_distributive_law
5270 (gen_binary (GET_CODE (op1
), mode
,
5271 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5272 gen_binary (AND
, mode
, XEXP (op1
, 1),
5275 /* Similarly, taking advantage of the fact that
5276 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5278 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5279 return apply_distributive_law
5280 (gen_binary (XOR
, mode
,
5281 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5282 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5285 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5286 return apply_distributive_law
5287 (gen_binary (XOR
, mode
,
5288 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5289 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5293 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5294 if (GET_CODE (op1
) == CONST_INT
5295 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5296 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5299 /* Convert (A & B) | A to A. */
5300 if (GET_CODE (op0
) == AND
5301 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5302 || rtx_equal_p (XEXP (op0
, 1), op1
))
5303 && ! side_effects_p (XEXP (op0
, 0))
5304 && ! side_effects_p (XEXP (op0
, 1)))
5307 /* If we have (ior (and A B) C), apply the distributive law and then
5308 the inverse distributive law to see if things simplify. */
5310 if (GET_CODE (op0
) == AND
)
5312 x
= apply_distributive_law
5313 (gen_binary (AND
, mode
,
5314 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5315 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5318 if (GET_CODE (x
) != IOR
)
5322 if (GET_CODE (op1
) == AND
)
5324 x
= apply_distributive_law
5325 (gen_binary (AND
, mode
,
5326 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5327 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5330 if (GET_CODE (x
) != IOR
)
5334 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5335 mode size to (rotate A CX). */
5337 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5338 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5339 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5340 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5341 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5342 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5343 == GET_MODE_BITSIZE (mode
)))
5344 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5345 (GET_CODE (op0
) == ASHIFT
5346 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5348 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5349 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5350 does not affect any of the bits in OP1, it can really be done
5351 as a PLUS and we can associate. We do this by seeing if OP1
5352 can be safely shifted left C bits. */
5353 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5354 && GET_CODE (XEXP (op0
, 0)) == PLUS
5355 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5356 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5357 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5359 int count
= INTVAL (XEXP (op0
, 1));
5360 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5362 if (mask
>> count
== INTVAL (op1
)
5363 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5365 SUBST (XEXP (XEXP (op0
, 0), 1),
5366 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5373 /* If we are XORing two things that have no bits in common,
5374 convert them into an IOR. This helps to detect rotation encoded
5375 using those methods and possibly other simplifications. */
5377 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5378 && (nonzero_bits (op0
, mode
)
5379 & nonzero_bits (op1
, mode
)) == 0)
5380 return (gen_binary (IOR
, mode
, op0
, op1
));
5382 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5383 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5386 int num_negated
= 0;
5388 if (GET_CODE (op0
) == NOT
)
5389 num_negated
++, op0
= XEXP (op0
, 0);
5390 if (GET_CODE (op1
) == NOT
)
5391 num_negated
++, op1
= XEXP (op1
, 0);
5393 if (num_negated
== 2)
5395 SUBST (XEXP (x
, 0), op0
);
5396 SUBST (XEXP (x
, 1), op1
);
5398 else if (num_negated
== 1)
5400 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5404 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5405 correspond to a machine insn or result in further simplifications
5406 if B is a constant. */
5408 if (GET_CODE (op0
) == AND
5409 && rtx_equal_p (XEXP (op0
, 1), op1
)
5410 && ! side_effects_p (op1
))
5411 return gen_binary (AND
, mode
,
5412 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5415 else if (GET_CODE (op0
) == AND
5416 && rtx_equal_p (XEXP (op0
, 0), op1
)
5417 && ! side_effects_p (op1
))
5418 return gen_binary (AND
, mode
,
5419 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5422 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5423 comparison if STORE_FLAG_VALUE is 1. */
5424 if (STORE_FLAG_VALUE
== 1
5425 && op1
== const1_rtx
5426 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5427 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5431 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5432 is (lt foo (const_int 0)), so we can perform the above
5433 simplification if STORE_FLAG_VALUE is 1. */
5435 if (STORE_FLAG_VALUE
== 1
5436 && op1
== const1_rtx
5437 && GET_CODE (op0
) == LSHIFTRT
5438 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5439 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5440 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5442 /* (xor (comparison foo bar) (const_int sign-bit))
5443 when STORE_FLAG_VALUE is the sign bit. */
5444 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5445 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5446 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5447 && op1
== const_true_rtx
5448 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5449 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5462 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5463 operations" because they can be replaced with two more basic operations.
5464 ZERO_EXTEND is also considered "compound" because it can be replaced with
5465 an AND operation, which is simpler, though only one operation.
5467 The function expand_compound_operation is called with an rtx expression
5468 and will convert it to the appropriate shifts and AND operations,
5469 simplifying at each stage.
5471 The function make_compound_operation is called to convert an expression
5472 consisting of shifts and ANDs into the equivalent compound expression.
5473 It is the inverse of this function, loosely speaking. */
5476 expand_compound_operation (x
)
5479 unsigned HOST_WIDE_INT pos
= 0, len
;
5481 unsigned int modewidth
;
5484 switch (GET_CODE (x
))
5489 /* We can't necessarily use a const_int for a multiword mode;
5490 it depends on implicitly extending the value.
5491 Since we don't know the right way to extend it,
5492 we can't tell whether the implicit way is right.
5494 Even for a mode that is no wider than a const_int,
5495 we can't win, because we need to sign extend one of its bits through
5496 the rest of it, and we don't know which bit. */
5497 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5500 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5501 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5502 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5503 reloaded. If not for that, MEM's would very rarely be safe.
5505 Reject MODEs bigger than a word, because we might not be able
5506 to reference a two-register group starting with an arbitrary register
5507 (and currently gen_lowpart might crash for a SUBREG). */
5509 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5512 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5513 /* If the inner object has VOIDmode (the only way this can happen
5514 is if it is a ASM_OPERANDS), we can't do anything since we don't
5515 know how much masking to do. */
5524 /* If the operand is a CLOBBER, just return it. */
5525 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5528 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5529 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5530 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5533 len
= INTVAL (XEXP (x
, 1));
5534 pos
= INTVAL (XEXP (x
, 2));
5536 /* If this goes outside the object being extracted, replace the object
5537 with a (use (mem ...)) construct that only combine understands
5538 and is used only for this purpose. */
5539 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5540 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5542 if (BITS_BIG_ENDIAN
)
5543 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5550 /* Convert sign extension to zero extension, if we know that the high
5551 bit is not set, as this is easier to optimize. It will be converted
5552 back to cheaper alternative in make_extraction. */
5553 if (GET_CODE (x
) == SIGN_EXTEND
5554 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5555 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5556 & ~(((unsigned HOST_WIDE_INT
)
5557 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5561 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5562 return expand_compound_operation (temp
);
5565 /* We can optimize some special cases of ZERO_EXTEND. */
5566 if (GET_CODE (x
) == ZERO_EXTEND
)
5568 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5569 know that the last value didn't have any inappropriate bits
5571 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5572 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5573 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5574 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5575 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5576 return XEXP (XEXP (x
, 0), 0);
5578 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5579 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5580 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5581 && subreg_lowpart_p (XEXP (x
, 0))
5582 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5583 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5584 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5585 return SUBREG_REG (XEXP (x
, 0));
5587 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5588 is a comparison and STORE_FLAG_VALUE permits. This is like
5589 the first case, but it works even when GET_MODE (x) is larger
5590 than HOST_WIDE_INT. */
5591 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5592 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5593 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5594 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5595 <= HOST_BITS_PER_WIDE_INT
)
5596 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5597 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5598 return XEXP (XEXP (x
, 0), 0);
5600 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5601 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5602 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5603 && subreg_lowpart_p (XEXP (x
, 0))
5604 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5605 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5606 <= HOST_BITS_PER_WIDE_INT
)
5607 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5608 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5609 return SUBREG_REG (XEXP (x
, 0));
5613 /* If we reach here, we want to return a pair of shifts. The inner
5614 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5615 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5616 logical depending on the value of UNSIGNEDP.
5618 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5619 converted into an AND of a shift.
5621 We must check for the case where the left shift would have a negative
5622 count. This can happen in a case like (x >> 31) & 255 on machines
5623 that can't shift by a constant. On those machines, we would first
5624 combine the shift with the AND to produce a variable-position
5625 extraction. Then the constant of 31 would be substituted in to produce
5626 a such a position. */
5628 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5629 if (modewidth
+ len
>= pos
)
5630 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5632 simplify_shift_const (NULL_RTX
, ASHIFT
,
5635 modewidth
- pos
- len
),
5638 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5639 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5640 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5643 ((HOST_WIDE_INT
) 1 << len
) - 1);
5645 /* Any other cases we can't handle. */
5648 /* If we couldn't do this for some reason, return the original
5650 if (GET_CODE (tem
) == CLOBBER
)
5656 /* X is a SET which contains an assignment of one object into
5657 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5658 or certain SUBREGS). If possible, convert it into a series of
5661 We half-heartedly support variable positions, but do not at all
5662 support variable lengths. */
5665 expand_field_assignment (x
)
5669 rtx pos
; /* Always counts from low bit. */
5672 enum machine_mode compute_mode
;
5674 /* Loop until we find something we can't simplify. */
5677 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5678 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5680 int byte_offset
= SUBREG_BYTE (XEXP (SET_DEST (x
), 0));
5682 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5683 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5684 pos
= GEN_INT (BITS_PER_WORD
* (byte_offset
/ UNITS_PER_WORD
));
5686 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5687 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5689 inner
= XEXP (SET_DEST (x
), 0);
5690 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5691 pos
= XEXP (SET_DEST (x
), 2);
5693 /* If the position is constant and spans the width of INNER,
5694 surround INNER with a USE to indicate this. */
5695 if (GET_CODE (pos
) == CONST_INT
5696 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5697 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5699 if (BITS_BIG_ENDIAN
)
5701 if (GET_CODE (pos
) == CONST_INT
)
5702 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5704 else if (GET_CODE (pos
) == MINUS
5705 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5706 && (INTVAL (XEXP (pos
, 1))
5707 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5708 /* If position is ADJUST - X, new position is X. */
5709 pos
= XEXP (pos
, 0);
5711 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5712 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5718 /* A SUBREG between two modes that occupy the same numbers of words
5719 can be done by moving the SUBREG to the source. */
5720 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5721 /* We need SUBREGs to compute nonzero_bits properly. */
5722 && nonzero_sign_valid
5723 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5724 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5725 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5726 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5728 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5729 gen_lowpart_for_combine
5730 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5737 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5738 inner
= SUBREG_REG (inner
);
5740 compute_mode
= GET_MODE (inner
);
5742 /* Don't attempt bitwise arithmetic on non-integral modes. */
5743 if (! INTEGRAL_MODE_P (compute_mode
))
5745 enum machine_mode imode
;
5747 /* Something is probably seriously wrong if this matches. */
5748 if (! FLOAT_MODE_P (compute_mode
))
5751 /* Try to find an integral mode to pun with. */
5752 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5753 if (imode
== BLKmode
)
5756 compute_mode
= imode
;
5757 inner
= gen_lowpart_for_combine (imode
, inner
);
5760 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5761 if (len
< HOST_BITS_PER_WIDE_INT
)
5762 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5766 /* Now compute the equivalent expression. Make a copy of INNER
5767 for the SET_DEST in case it is a MEM into which we will substitute;
5768 we don't want shared RTL in that case. */
5770 (VOIDmode
, copy_rtx (inner
),
5771 gen_binary (IOR
, compute_mode
,
5772 gen_binary (AND
, compute_mode
,
5773 simplify_gen_unary (NOT
, compute_mode
,
5779 gen_binary (ASHIFT
, compute_mode
,
5780 gen_binary (AND
, compute_mode
,
5781 gen_lowpart_for_combine
5782 (compute_mode
, SET_SRC (x
)),
5790 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5791 it is an RTX that represents a variable starting position; otherwise,
5792 POS is the (constant) starting bit position (counted from the LSB).
5794 INNER may be a USE. This will occur when we started with a bitfield
5795 that went outside the boundary of the object in memory, which is
5796 allowed on most machines. To isolate this case, we produce a USE
5797 whose mode is wide enough and surround the MEM with it. The only
5798 code that understands the USE is this routine. If it is not removed,
5799 it will cause the resulting insn not to match.
5801 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5804 IN_DEST is non-zero if this is a reference in the destination of a
5805 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5806 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5809 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5810 ZERO_EXTRACT should be built even for bits starting at bit 0.
5812 MODE is the desired mode of the result (if IN_DEST == 0).
5814 The result is an RTX for the extraction or NULL_RTX if the target
5818 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5819 unsignedp
, in_dest
, in_compare
)
5820 enum machine_mode mode
;
5824 unsigned HOST_WIDE_INT len
;
5826 int in_dest
, in_compare
;
5828 /* This mode describes the size of the storage area
5829 to fetch the overall value from. Within that, we
5830 ignore the POS lowest bits, etc. */
5831 enum machine_mode is_mode
= GET_MODE (inner
);
5832 enum machine_mode inner_mode
;
5833 enum machine_mode wanted_inner_mode
= byte_mode
;
5834 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5835 enum machine_mode pos_mode
= word_mode
;
5836 enum machine_mode extraction_mode
= word_mode
;
5837 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5840 rtx orig_pos_rtx
= pos_rtx
;
5841 HOST_WIDE_INT orig_pos
;
5843 /* Get some information about INNER and get the innermost object. */
5844 if (GET_CODE (inner
) == USE
)
5845 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5846 /* We don't need to adjust the position because we set up the USE
5847 to pretend that it was a full-word object. */
5848 spans_byte
= 1, inner
= XEXP (inner
, 0);
5849 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5851 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5852 consider just the QI as the memory to extract from.
5853 The subreg adds or removes high bits; its mode is
5854 irrelevant to the meaning of this extraction,
5855 since POS and LEN count from the lsb. */
5856 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5857 is_mode
= GET_MODE (SUBREG_REG (inner
));
5858 inner
= SUBREG_REG (inner
);
5861 inner_mode
= GET_MODE (inner
);
5863 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5864 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5866 /* See if this can be done without an extraction. We never can if the
5867 width of the field is not the same as that of some integer mode. For
5868 registers, we can only avoid the extraction if the position is at the
5869 low-order bit and this is either not in the destination or we have the
5870 appropriate STRICT_LOW_PART operation available.
5872 For MEM, we can avoid an extract if the field starts on an appropriate
5873 boundary and we can change the mode of the memory reference. However,
5874 we cannot directly access the MEM if we have a USE and the underlying
5875 MEM is not TMODE. This combination means that MEM was being used in a
5876 context where bits outside its mode were being referenced; that is only
5877 valid in bit-field insns. */
5879 if (tmode
!= BLKmode
5880 && ! (spans_byte
&& inner_mode
!= tmode
)
5881 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5882 && GET_CODE (inner
) != MEM
5884 || (GET_CODE (inner
) == REG
5885 && have_insn_for (STRICT_LOW_PART
, tmode
))))
5886 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5888 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5889 : BITS_PER_UNIT
)) == 0
5890 /* We can't do this if we are widening INNER_MODE (it
5891 may not be aligned, for one thing). */
5892 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5893 && (inner_mode
== tmode
5894 || (! mode_dependent_address_p (XEXP (inner
, 0))
5895 && ! MEM_VOLATILE_P (inner
))))))
5897 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5898 field. If the original and current mode are the same, we need not
5899 adjust the offset. Otherwise, we do if bytes big endian.
5901 If INNER is not a MEM, get a piece consisting of just the field
5902 of interest (in this case POS % BITS_PER_WORD must be 0). */
5904 if (GET_CODE (inner
) == MEM
)
5906 HOST_WIDE_INT offset
;
5908 /* POS counts from lsb, but make OFFSET count in memory order. */
5909 if (BYTES_BIG_ENDIAN
)
5910 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5912 offset
= pos
/ BITS_PER_UNIT
;
5914 new = adjust_address_nv (inner
, tmode
, offset
);
5916 else if (GET_CODE (inner
) == REG
)
5918 /* We can't call gen_lowpart_for_combine here since we always want
5919 a SUBREG and it would sometimes return a new hard register. */
5920 if (tmode
!= inner_mode
)
5922 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
5924 if (WORDS_BIG_ENDIAN
5925 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
5926 final_word
= ((GET_MODE_SIZE (inner_mode
)
5927 - GET_MODE_SIZE (tmode
))
5928 / UNITS_PER_WORD
) - final_word
;
5930 final_word
*= UNITS_PER_WORD
;
5931 if (BYTES_BIG_ENDIAN
&&
5932 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
5933 final_word
+= (GET_MODE_SIZE (inner_mode
)
5934 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
5936 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
5942 new = force_to_mode (inner
, tmode
,
5943 len
>= HOST_BITS_PER_WIDE_INT
5944 ? ~(unsigned HOST_WIDE_INT
) 0
5945 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
5948 /* If this extraction is going into the destination of a SET,
5949 make a STRICT_LOW_PART unless we made a MEM. */
5952 return (GET_CODE (new) == MEM
? new
5953 : (GET_CODE (new) != SUBREG
5954 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5955 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
5960 /* If we know that no extraneous bits are set, and that the high
5961 bit is not set, convert the extraction to the cheaper of
5962 sign and zero extension, that are equivalent in these cases. */
5963 if (flag_expensive_optimizations
5964 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
5965 && ((nonzero_bits (new, tmode
)
5966 & ~(((unsigned HOST_WIDE_INT
)
5967 GET_MODE_MASK (tmode
))
5971 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
5972 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
5974 /* Prefer ZERO_EXTENSION, since it gives more information to
5976 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
5981 /* Otherwise, sign- or zero-extend unless we already are in the
5984 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5988 /* Unless this is a COMPARE or we have a funny memory reference,
5989 don't do anything with zero-extending field extracts starting at
5990 the low-order bit since they are simple AND operations. */
5991 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5992 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5995 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5996 we would be spanning bytes or if the position is not a constant and the
5997 length is not 1. In all other cases, we would only be going outside
5998 our object in cases when an original shift would have been
6000 if (! spans_byte
&& GET_CODE (inner
) == MEM
6001 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6002 || (pos_rtx
!= 0 && len
!= 1)))
6005 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6006 and the mode for the result. */
6010 wanted_inner_reg_mode
6011 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
6012 if (wanted_inner_reg_mode
== VOIDmode
)
6013 wanted_inner_reg_mode
= word_mode
;
6015 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
6016 if (pos_mode
== VOIDmode
)
6017 pos_mode
= word_mode
;
6019 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6020 if (extraction_mode
== VOIDmode
)
6021 extraction_mode
= word_mode
;
6026 if (! in_dest
&& unsignedp
)
6028 wanted_inner_reg_mode
6029 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6030 if (wanted_inner_reg_mode
== VOIDmode
)
6031 wanted_inner_reg_mode
= word_mode
;
6033 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6034 if (pos_mode
== VOIDmode
)
6035 pos_mode
= word_mode
;
6037 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6038 if (extraction_mode
== VOIDmode
)
6039 extraction_mode
= word_mode
;
6044 if (! in_dest
&& ! unsignedp
)
6046 wanted_inner_reg_mode
6047 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6048 if (wanted_inner_reg_mode
== VOIDmode
)
6049 wanted_inner_reg_mode
= word_mode
;
6051 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6052 if (pos_mode
== VOIDmode
)
6053 pos_mode
= word_mode
;
6055 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6056 if (extraction_mode
== VOIDmode
)
6057 extraction_mode
= word_mode
;
6061 /* Never narrow an object, since that might not be safe. */
6063 if (mode
!= VOIDmode
6064 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6065 extraction_mode
= mode
;
6067 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6068 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6069 pos_mode
= GET_MODE (pos_rtx
);
6071 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6072 if we have to change the mode of memory and cannot, the desired mode is
6074 if (GET_CODE (inner
) != MEM
)
6075 wanted_inner_mode
= wanted_inner_reg_mode
;
6076 else if (inner_mode
!= wanted_inner_mode
6077 && (mode_dependent_address_p (XEXP (inner
, 0))
6078 || MEM_VOLATILE_P (inner
)))
6079 wanted_inner_mode
= extraction_mode
;
6083 if (BITS_BIG_ENDIAN
)
6085 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6086 BITS_BIG_ENDIAN style. If position is constant, compute new
6087 position. Otherwise, build subtraction.
6088 Note that POS is relative to the mode of the original argument.
6089 If it's a MEM we need to recompute POS relative to that.
6090 However, if we're extracting from (or inserting into) a register,
6091 we want to recompute POS relative to wanted_inner_mode. */
6092 int width
= (GET_CODE (inner
) == MEM
6093 ? GET_MODE_BITSIZE (is_mode
)
6094 : GET_MODE_BITSIZE (wanted_inner_mode
));
6097 pos
= width
- len
- pos
;
6100 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6101 /* POS may be less than 0 now, but we check for that below.
6102 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6105 /* If INNER has a wider mode, make it smaller. If this is a constant
6106 extract, try to adjust the byte to point to the byte containing
6108 if (wanted_inner_mode
!= VOIDmode
6109 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6110 && ((GET_CODE (inner
) == MEM
6111 && (inner_mode
== wanted_inner_mode
6112 || (! mode_dependent_address_p (XEXP (inner
, 0))
6113 && ! MEM_VOLATILE_P (inner
))))))
6117 /* The computations below will be correct if the machine is big
6118 endian in both bits and bytes or little endian in bits and bytes.
6119 If it is mixed, we must adjust. */
6121 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6122 adjust OFFSET to compensate. */
6123 if (BYTES_BIG_ENDIAN
6125 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6126 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6128 /* If this is a constant position, we can move to the desired byte. */
6131 offset
+= pos
/ BITS_PER_UNIT
;
6132 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6135 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6137 && is_mode
!= wanted_inner_mode
)
6138 offset
= (GET_MODE_SIZE (is_mode
)
6139 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6141 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6142 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6145 /* If INNER is not memory, we can always get it into the proper mode. If we
6146 are changing its mode, POS must be a constant and smaller than the size
6148 else if (GET_CODE (inner
) != MEM
)
6150 if (GET_MODE (inner
) != wanted_inner_mode
6152 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6155 inner
= force_to_mode (inner
, wanted_inner_mode
,
6157 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6158 ? ~(unsigned HOST_WIDE_INT
) 0
6159 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6164 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6165 have to zero extend. Otherwise, we can just use a SUBREG. */
6167 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6169 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6171 /* If we know that no extraneous bits are set, and that the high
6172 bit is not set, convert extraction to cheaper one - eighter
6173 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6175 if (flag_expensive_optimizations
6176 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6177 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6178 & ~(((unsigned HOST_WIDE_INT
)
6179 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6183 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6185 /* Prefer ZERO_EXTENSION, since it gives more information to
6187 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6192 else if (pos_rtx
!= 0
6193 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6194 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6196 /* Make POS_RTX unless we already have it and it is correct. If we don't
6197 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6199 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6200 pos_rtx
= orig_pos_rtx
;
6202 else if (pos_rtx
== 0)
6203 pos_rtx
= GEN_INT (pos
);
6205 /* Make the required operation. See if we can use existing rtx. */
6206 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6207 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6209 new = gen_lowpart_for_combine (mode
, new);
6214 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6215 with any other operations in X. Return X without that shift if so. */
6218 extract_left_shift (x
, count
)
6222 enum rtx_code code
= GET_CODE (x
);
6223 enum machine_mode mode
= GET_MODE (x
);
6229 /* This is the shift itself. If it is wide enough, we will return
6230 either the value being shifted if the shift count is equal to
6231 COUNT or a shift for the difference. */
6232 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6233 && INTVAL (XEXP (x
, 1)) >= count
)
6234 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6235 INTVAL (XEXP (x
, 1)) - count
);
6239 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6240 return simplify_gen_unary (code
, mode
, tem
, mode
);
6244 case PLUS
: case IOR
: case XOR
: case AND
:
6245 /* If we can safely shift this constant and we find the inner shift,
6246 make a new operation. */
6247 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6248 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6249 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6250 return gen_binary (code
, mode
, tem
,
6251 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6262 /* Look at the expression rooted at X. Look for expressions
6263 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6264 Form these expressions.
6266 Return the new rtx, usually just X.
6268 Also, for machines like the VAX that don't have logical shift insns,
6269 try to convert logical to arithmetic shift operations in cases where
6270 they are equivalent. This undoes the canonicalizations to logical
6271 shifts done elsewhere.
6273 We try, as much as possible, to re-use rtl expressions to save memory.
6275 IN_CODE says what kind of expression we are processing. Normally, it is
6276 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6277 being kludges), it is MEM. When processing the arguments of a comparison
6278 or a COMPARE against zero, it is COMPARE. */
6281 make_compound_operation (x
, in_code
)
6283 enum rtx_code in_code
;
6285 enum rtx_code code
= GET_CODE (x
);
6286 enum machine_mode mode
= GET_MODE (x
);
6287 int mode_width
= GET_MODE_BITSIZE (mode
);
6289 enum rtx_code next_code
;
6295 /* Select the code to be used in recursive calls. Once we are inside an
6296 address, we stay there. If we have a comparison, set to COMPARE,
6297 but once inside, go back to our default of SET. */
6299 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6300 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6301 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6302 : in_code
== COMPARE
? SET
: in_code
);
6304 /* Process depending on the code of this operation. If NEW is set
6305 non-zero, it will be returned. */
6310 /* Convert shifts by constants into multiplications if inside
6312 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6313 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6314 && INTVAL (XEXP (x
, 1)) >= 0)
6316 new = make_compound_operation (XEXP (x
, 0), next_code
);
6317 new = gen_rtx_MULT (mode
, new,
6318 GEN_INT ((HOST_WIDE_INT
) 1
6319 << INTVAL (XEXP (x
, 1))));
6324 /* If the second operand is not a constant, we can't do anything
6326 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6329 /* If the constant is a power of two minus one and the first operand
6330 is a logical right shift, make an extraction. */
6331 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6332 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6334 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6335 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6336 0, in_code
== COMPARE
);
6339 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6340 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6341 && subreg_lowpart_p (XEXP (x
, 0))
6342 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6343 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6345 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6347 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6348 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6349 0, in_code
== COMPARE
);
6351 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6352 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6353 || GET_CODE (XEXP (x
, 0)) == IOR
)
6354 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6355 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6356 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6358 /* Apply the distributive law, and then try to make extractions. */
6359 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6360 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6362 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6364 new = make_compound_operation (new, in_code
);
6367 /* If we are have (and (rotate X C) M) and C is larger than the number
6368 of bits in M, this is an extraction. */
6370 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6371 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6372 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6373 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6375 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6376 new = make_extraction (mode
, new,
6377 (GET_MODE_BITSIZE (mode
)
6378 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6379 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6382 /* On machines without logical shifts, if the operand of the AND is
6383 a logical shift and our mask turns off all the propagated sign
6384 bits, we can replace the logical shift with an arithmetic shift. */
6385 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6386 && !have_insn_for (LSHIFTRT
, mode
)
6387 && have_insn_for (ASHIFTRT
, mode
)
6388 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6389 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6390 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6391 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6393 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6395 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6396 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6398 gen_rtx_ASHIFTRT (mode
,
6399 make_compound_operation
6400 (XEXP (XEXP (x
, 0), 0), next_code
),
6401 XEXP (XEXP (x
, 0), 1)));
6404 /* If the constant is one less than a power of two, this might be
6405 representable by an extraction even if no shift is present.
6406 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6407 we are in a COMPARE. */
6408 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6409 new = make_extraction (mode
,
6410 make_compound_operation (XEXP (x
, 0),
6412 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6414 /* If we are in a comparison and this is an AND with a power of two,
6415 convert this into the appropriate bit extract. */
6416 else if (in_code
== COMPARE
6417 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6418 new = make_extraction (mode
,
6419 make_compound_operation (XEXP (x
, 0),
6421 i
, NULL_RTX
, 1, 1, 0, 1);
6426 /* If the sign bit is known to be zero, replace this with an
6427 arithmetic shift. */
6428 if (have_insn_for (ASHIFTRT
, mode
)
6429 && ! have_insn_for (LSHIFTRT
, mode
)
6430 && mode_width
<= HOST_BITS_PER_WIDE_INT
6431 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6433 new = gen_rtx_ASHIFTRT (mode
,
6434 make_compound_operation (XEXP (x
, 0),
6440 /* ... fall through ... */
6446 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6447 this is a SIGN_EXTRACT. */
6448 if (GET_CODE (rhs
) == CONST_INT
6449 && GET_CODE (lhs
) == ASHIFT
6450 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6451 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6453 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6454 new = make_extraction (mode
, new,
6455 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6456 NULL_RTX
, mode_width
- INTVAL (rhs
),
6457 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6461 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6462 If so, try to merge the shifts into a SIGN_EXTEND. We could
6463 also do this for some cases of SIGN_EXTRACT, but it doesn't
6464 seem worth the effort; the case checked for occurs on Alpha. */
6466 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6467 && ! (GET_CODE (lhs
) == SUBREG
6468 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6469 && GET_CODE (rhs
) == CONST_INT
6470 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6471 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6472 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6473 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6474 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6479 /* Call ourselves recursively on the inner expression. If we are
6480 narrowing the object and it has a different RTL code from
6481 what it originally did, do this SUBREG as a force_to_mode. */
6483 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6484 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6485 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6486 && subreg_lowpart_p (x
))
6488 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6491 /* If we have something other than a SUBREG, we might have
6492 done an expansion, so rerun outselves. */
6493 if (GET_CODE (newer
) != SUBREG
)
6494 newer
= make_compound_operation (newer
, in_code
);
6499 /* If this is a paradoxical subreg, and the new code is a sign or
6500 zero extension, omit the subreg and widen the extension. If it
6501 is a regular subreg, we can still get rid of the subreg by not
6502 widening so much, or in fact removing the extension entirely. */
6503 if ((GET_CODE (tem
) == SIGN_EXTEND
6504 || GET_CODE (tem
) == ZERO_EXTEND
)
6505 && subreg_lowpart_p (x
))
6507 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6508 || (GET_MODE_SIZE (mode
) >
6509 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6510 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6512 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6523 x
= gen_lowpart_for_combine (mode
, new);
6524 code
= GET_CODE (x
);
6527 /* Now recursively process each operand of this operation. */
6528 fmt
= GET_RTX_FORMAT (code
);
6529 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6532 new = make_compound_operation (XEXP (x
, i
), next_code
);
6533 SUBST (XEXP (x
, i
), new);
6539 /* Given M see if it is a value that would select a field of bits
6540 within an item, but not the entire word. Return -1 if not.
6541 Otherwise, return the starting position of the field, where 0 is the
6544 *PLEN is set to the length of the field. */
6547 get_pos_from_mask (m
, plen
)
6548 unsigned HOST_WIDE_INT m
;
6549 unsigned HOST_WIDE_INT
*plen
;
6551 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6552 int pos
= exact_log2 (m
& -m
);
6558 /* Now shift off the low-order zero bits and see if we have a power of
6560 len
= exact_log2 ((m
>> pos
) + 1);
6569 /* See if X can be simplified knowing that we will only refer to it in
6570 MODE and will only refer to those bits that are nonzero in MASK.
6571 If other bits are being computed or if masking operations are done
6572 that select a superset of the bits in MASK, they can sometimes be
6575 Return a possibly simplified expression, but always convert X to
6576 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6578 Also, if REG is non-zero and X is a register equal in value to REG,
6581 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6582 are all off in X. This is used when X will be complemented, by either
6583 NOT, NEG, or XOR. */
6586 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6588 enum machine_mode mode
;
6589 unsigned HOST_WIDE_INT mask
;
6593 enum rtx_code code
= GET_CODE (x
);
6594 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6595 enum machine_mode op_mode
;
6596 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6599 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6600 code below will do the wrong thing since the mode of such an
6601 expression is VOIDmode.
6603 Also do nothing if X is a CLOBBER; this can happen if X was
6604 the return value from a call to gen_lowpart_for_combine. */
6605 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6608 /* We want to perform the operation is its present mode unless we know
6609 that the operation is valid in MODE, in which case we do the operation
6611 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6612 && have_insn_for (code
, mode
))
6613 ? mode
: GET_MODE (x
));
6615 /* It is not valid to do a right-shift in a narrower mode
6616 than the one it came in with. */
6617 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6618 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6619 op_mode
= GET_MODE (x
);
6621 /* Truncate MASK to fit OP_MODE. */
6623 mask
&= GET_MODE_MASK (op_mode
);
6625 /* When we have an arithmetic operation, or a shift whose count we
6626 do not know, we need to assume that all bit the up to the highest-order
6627 bit in MASK will be needed. This is how we form such a mask. */
6629 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6630 ? GET_MODE_MASK (op_mode
)
6631 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6634 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6636 /* Determine what bits of X are guaranteed to be (non)zero. */
6637 nonzero
= nonzero_bits (x
, mode
);
6639 /* If none of the bits in X are needed, return a zero. */
6640 if (! just_select
&& (nonzero
& mask
) == 0)
6643 /* If X is a CONST_INT, return a new one. Do this here since the
6644 test below will fail. */
6645 if (GET_CODE (x
) == CONST_INT
)
6647 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6648 int width
= GET_MODE_BITSIZE (mode
);
6650 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6651 number, sign extend it. */
6652 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6653 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6654 cval
|= (HOST_WIDE_INT
) -1 << width
;
6656 return GEN_INT (cval
);
6659 /* If X is narrower than MODE and we want all the bits in X's mode, just
6660 get X in the proper mode. */
6661 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6662 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6663 return gen_lowpart_for_combine (mode
, x
);
6665 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6666 MASK are already known to be zero in X, we need not do anything. */
6667 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6673 /* If X is a (clobber (const_int)), return it since we know we are
6674 generating something that won't match. */
6678 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6679 spanned the boundary of the MEM. If we are now masking so it is
6680 within that boundary, we don't need the USE any more. */
6681 if (! BITS_BIG_ENDIAN
6682 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6683 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6690 x
= expand_compound_operation (x
);
6691 if (GET_CODE (x
) != code
)
6692 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6696 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6697 || rtx_equal_p (reg
, get_last_value (x
))))
6702 if (subreg_lowpart_p (x
)
6703 /* We can ignore the effect of this SUBREG if it narrows the mode or
6704 if the constant masks to zero all the bits the mode doesn't
6706 && ((GET_MODE_SIZE (GET_MODE (x
))
6707 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6709 & GET_MODE_MASK (GET_MODE (x
))
6710 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6711 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6715 /* If this is an AND with a constant, convert it into an AND
6716 whose constant is the AND of that constant with MASK. If it
6717 remains an AND of MASK, delete it since it is redundant. */
6719 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6721 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6722 mask
& INTVAL (XEXP (x
, 1)));
6724 /* If X is still an AND, see if it is an AND with a mask that
6725 is just some low-order bits. If so, and it is MASK, we don't
6728 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6729 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6732 /* If it remains an AND, try making another AND with the bits
6733 in the mode mask that aren't in MASK turned on. If the
6734 constant in the AND is wide enough, this might make a
6735 cheaper constant. */
6737 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6738 && GET_MODE_MASK (GET_MODE (x
)) != mask
6739 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6741 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6742 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6743 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6746 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6747 number, sign extend it. */
6748 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6749 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6750 cval
|= (HOST_WIDE_INT
) -1 << width
;
6752 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6753 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6763 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6764 low-order bits (as in an alignment operation) and FOO is already
6765 aligned to that boundary, mask C1 to that boundary as well.
6766 This may eliminate that PLUS and, later, the AND. */
6769 unsigned int width
= GET_MODE_BITSIZE (mode
);
6770 unsigned HOST_WIDE_INT smask
= mask
;
6772 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6773 number, sign extend it. */
6775 if (width
< HOST_BITS_PER_WIDE_INT
6776 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6777 smask
|= (HOST_WIDE_INT
) -1 << width
;
6779 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6780 && exact_log2 (- smask
) >= 0)
6784 && (XEXP (x
, 0) == stack_pointer_rtx
6785 || XEXP (x
, 0) == frame_pointer_rtx
))
6787 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6788 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6790 sp_mask
&= ~(sp_alignment
- 1);
6791 if ((sp_mask
& ~smask
) == 0
6792 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6793 return force_to_mode (plus_constant (XEXP (x
, 0),
6794 ((INTVAL (XEXP (x
, 1)) -
6795 STACK_BIAS
) & smask
)
6797 mode
, smask
, reg
, next_select
);
6800 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6801 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6802 return force_to_mode (plus_constant (XEXP (x
, 0),
6803 (INTVAL (XEXP (x
, 1))
6805 mode
, smask
, reg
, next_select
);
6809 /* ... fall through ... */
6812 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6813 most significant bit in MASK since carries from those bits will
6814 affect the bits we are interested in. */
6819 /* If X is (minus C Y) where C's least set bit is larger than any bit
6820 in the mask, then we may replace with (neg Y). */
6821 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6822 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6823 & -INTVAL (XEXP (x
, 0))))
6826 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6828 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6831 /* Similarly, if C contains every bit in the mask, then we may
6832 replace with (not Y). */
6833 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6834 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6835 == INTVAL (XEXP (x
, 0))))
6837 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6838 XEXP (x
, 1), GET_MODE (x
));
6839 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6847 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6848 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6849 operation which may be a bitfield extraction. Ensure that the
6850 constant we form is not wider than the mode of X. */
6852 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6853 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6854 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6855 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6856 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6857 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6858 + floor_log2 (INTVAL (XEXP (x
, 1))))
6859 < GET_MODE_BITSIZE (GET_MODE (x
)))
6860 && (INTVAL (XEXP (x
, 1))
6861 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6863 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6864 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6865 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6866 XEXP (XEXP (x
, 0), 0), temp
);
6867 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6868 XEXP (XEXP (x
, 0), 1));
6869 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6873 /* For most binary operations, just propagate into the operation and
6874 change the mode if we have an operation of that mode. */
6876 op0
= gen_lowpart_for_combine (op_mode
,
6877 force_to_mode (XEXP (x
, 0), mode
, mask
,
6879 op1
= gen_lowpart_for_combine (op_mode
,
6880 force_to_mode (XEXP (x
, 1), mode
, mask
,
6883 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6884 MASK since OP1 might have been sign-extended but we never want
6885 to turn on extra bits, since combine might have previously relied
6886 on them being off. */
6887 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6888 && (INTVAL (op1
) & mask
) != 0)
6889 op1
= GEN_INT (INTVAL (op1
) & mask
);
6891 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6892 x
= gen_binary (code
, op_mode
, op0
, op1
);
6896 /* For left shifts, do the same, but just for the first operand.
6897 However, we cannot do anything with shifts where we cannot
6898 guarantee that the counts are smaller than the size of the mode
6899 because such a count will have a different meaning in a
6902 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6903 && INTVAL (XEXP (x
, 1)) >= 0
6904 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6905 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6906 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6907 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6910 /* If the shift count is a constant and we can do arithmetic in
6911 the mode of the shift, refine which bits we need. Otherwise, use the
6912 conservative form of the mask. */
6913 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6914 && INTVAL (XEXP (x
, 1)) >= 0
6915 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6916 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6917 mask
>>= INTVAL (XEXP (x
, 1));
6921 op0
= gen_lowpart_for_combine (op_mode
,
6922 force_to_mode (XEXP (x
, 0), op_mode
,
6923 mask
, reg
, next_select
));
6925 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6926 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6930 /* Here we can only do something if the shift count is a constant,
6931 this shift constant is valid for the host, and we can do arithmetic
6934 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6935 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6936 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6938 rtx inner
= XEXP (x
, 0);
6939 unsigned HOST_WIDE_INT inner_mask
;
6941 /* Select the mask of the bits we need for the shift operand. */
6942 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
6944 /* We can only change the mode of the shift if we can do arithmetic
6945 in the mode of the shift and INNER_MASK is no wider than the
6946 width of OP_MODE. */
6947 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6948 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
6949 op_mode
= GET_MODE (x
);
6951 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
6953 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6954 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6957 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6958 shift and AND produces only copies of the sign bit (C2 is one less
6959 than a power of two), we can do this with just a shift. */
6961 if (GET_CODE (x
) == LSHIFTRT
6962 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6963 /* The shift puts one of the sign bit copies in the least significant
6965 && ((INTVAL (XEXP (x
, 1))
6966 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6967 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6968 && exact_log2 (mask
+ 1) >= 0
6969 /* Number of bits left after the shift must be more than the mask
6971 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
6972 <= GET_MODE_BITSIZE (GET_MODE (x
)))
6973 /* Must be more sign bit copies than the mask needs. */
6974 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6975 >= exact_log2 (mask
+ 1)))
6976 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6977 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6978 - exact_log2 (mask
+ 1)));
6983 /* If we are just looking for the sign bit, we don't need this shift at
6984 all, even if it has a variable count. */
6985 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6986 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6987 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6988 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6990 /* If this is a shift by a constant, get a mask that contains those bits
6991 that are not copies of the sign bit. We then have two cases: If
6992 MASK only includes those bits, this can be a logical shift, which may
6993 allow simplifications. If MASK is a single-bit field not within
6994 those bits, we are requesting a copy of the sign bit and hence can
6995 shift the sign bit to the appropriate location. */
6997 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6998 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7002 /* If the considered data is wider then HOST_WIDE_INT, we can't
7003 represent a mask for all its bits in a single scalar.
7004 But we only care about the lower bits, so calculate these. */
7006 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7008 nonzero
= ~(HOST_WIDE_INT
) 0;
7010 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7011 is the number of bits a full-width mask would have set.
7012 We need only shift if these are fewer than nonzero can
7013 hold. If not, we must keep all bits set in nonzero. */
7015 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7016 < HOST_BITS_PER_WIDE_INT
)
7017 nonzero
>>= INTVAL (XEXP (x
, 1))
7018 + HOST_BITS_PER_WIDE_INT
7019 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7023 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7024 nonzero
>>= INTVAL (XEXP (x
, 1));
7027 if ((mask
& ~nonzero
) == 0
7028 || (i
= exact_log2 (mask
)) >= 0)
7030 x
= simplify_shift_const
7031 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7032 i
< 0 ? INTVAL (XEXP (x
, 1))
7033 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7035 if (GET_CODE (x
) != ASHIFTRT
)
7036 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7040 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7041 even if the shift count isn't a constant. */
7043 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7047 /* If this is a zero- or sign-extension operation that just affects bits
7048 we don't care about, remove it. Be sure the call above returned
7049 something that is still a shift. */
7051 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7052 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7053 && INTVAL (XEXP (x
, 1)) >= 0
7054 && (INTVAL (XEXP (x
, 1))
7055 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7056 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7057 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7058 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7059 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7066 /* If the shift count is constant and we can do computations
7067 in the mode of X, compute where the bits we care about are.
7068 Otherwise, we can't do anything. Don't change the mode of
7069 the shift or propagate MODE into the shift, though. */
7070 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7071 && INTVAL (XEXP (x
, 1)) >= 0)
7073 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7074 GET_MODE (x
), GEN_INT (mask
),
7076 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7078 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7079 INTVAL (temp
), reg
, next_select
));
7084 /* If we just want the low-order bit, the NEG isn't needed since it
7085 won't change the low-order bit. */
7087 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7089 /* We need any bits less significant than the most significant bit in
7090 MASK since carries from those bits will affect the bits we are
7096 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7097 same as the XOR case above. Ensure that the constant we form is not
7098 wider than the mode of X. */
7100 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7101 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7102 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7103 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7104 < GET_MODE_BITSIZE (GET_MODE (x
)))
7105 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7107 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7108 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7109 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7111 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7114 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7115 use the full mask inside the NOT. */
7119 op0
= gen_lowpart_for_combine (op_mode
,
7120 force_to_mode (XEXP (x
, 0), mode
, mask
,
7122 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7123 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7127 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7128 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7129 which is equal to STORE_FLAG_VALUE. */
7130 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7131 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7132 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7133 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7138 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7139 written in a narrower mode. We play it safe and do not do so. */
7142 gen_lowpart_for_combine (GET_MODE (x
),
7143 force_to_mode (XEXP (x
, 1), mode
,
7144 mask
, reg
, next_select
)));
7146 gen_lowpart_for_combine (GET_MODE (x
),
7147 force_to_mode (XEXP (x
, 2), mode
,
7148 mask
, reg
,next_select
)));
7155 /* Ensure we return a value of the proper mode. */
7156 return gen_lowpart_for_combine (mode
, x
);
7159 /* Return nonzero if X is an expression that has one of two values depending on
7160 whether some other value is zero or nonzero. In that case, we return the
7161 value that is being tested, *PTRUE is set to the value if the rtx being
7162 returned has a nonzero value, and *PFALSE is set to the other alternative.
7164 If we return zero, we set *PTRUE and *PFALSE to X. */
7167 if_then_else_cond (x
, ptrue
, pfalse
)
7169 rtx
*ptrue
, *pfalse
;
7171 enum machine_mode mode
= GET_MODE (x
);
7172 enum rtx_code code
= GET_CODE (x
);
7173 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7174 unsigned HOST_WIDE_INT nz
;
7176 /* If we are comparing a value against zero, we are done. */
7177 if ((code
== NE
|| code
== EQ
)
7178 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7180 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7181 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7185 /* If this is a unary operation whose operand has one of two values, apply
7186 our opcode to compute those values. */
7187 else if (GET_RTX_CLASS (code
) == '1'
7188 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7190 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7191 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7192 GET_MODE (XEXP (x
, 0)));
7196 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7197 make can't possibly match and would suppress other optimizations. */
7198 else if (code
== COMPARE
)
7201 /* If this is a binary operation, see if either side has only one of two
7202 values. If either one does or if both do and they are conditional on
7203 the same value, compute the new true and false values. */
7204 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7205 || GET_RTX_CLASS (code
) == '<')
7207 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7208 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7210 if ((cond0
!= 0 || cond1
!= 0)
7211 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7213 /* If if_then_else_cond returned zero, then true/false are the
7214 same rtl. We must copy one of them to prevent invalid rtl
7217 true0
= copy_rtx (true0
);
7218 else if (cond1
== 0)
7219 true1
= copy_rtx (true1
);
7221 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7222 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7223 return cond0
? cond0
: cond1
;
7226 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7227 operands is zero when the other is non-zero, and vice-versa,
7228 and STORE_FLAG_VALUE is 1 or -1. */
7230 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7231 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7233 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7235 rtx op0
= XEXP (XEXP (x
, 0), 1);
7236 rtx op1
= XEXP (XEXP (x
, 1), 1);
7238 cond0
= XEXP (XEXP (x
, 0), 0);
7239 cond1
= XEXP (XEXP (x
, 1), 0);
7241 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7242 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7243 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7244 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7245 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7246 || ((swap_condition (GET_CODE (cond0
))
7247 == combine_reversed_comparison_code (cond1
))
7248 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7249 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7250 && ! side_effects_p (x
))
7252 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7253 *pfalse
= gen_binary (MULT
, mode
,
7255 ? simplify_gen_unary (NEG
, mode
, op1
,
7263 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7265 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7266 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7267 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7269 cond0
= XEXP (XEXP (x
, 0), 0);
7270 cond1
= XEXP (XEXP (x
, 1), 0);
7272 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7273 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7274 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7275 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7276 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7277 || ((swap_condition (GET_CODE (cond0
))
7278 == combine_reversed_comparison_code (cond1
))
7279 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7280 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7281 && ! side_effects_p (x
))
7283 *ptrue
= *pfalse
= const0_rtx
;
7289 else if (code
== IF_THEN_ELSE
)
7291 /* If we have IF_THEN_ELSE already, extract the condition and
7292 canonicalize it if it is NE or EQ. */
7293 cond0
= XEXP (x
, 0);
7294 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7295 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7296 return XEXP (cond0
, 0);
7297 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7299 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7300 return XEXP (cond0
, 0);
7306 /* If X is a SUBREG, we can narrow both the true and false values
7307 if the inner expression, if there is a condition. */
7308 else if (code
== SUBREG
7309 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7312 *ptrue
= simplify_gen_subreg (mode
, true0
,
7313 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7314 *pfalse
= simplify_gen_subreg (mode
, false0
,
7315 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7320 /* If X is a constant, this isn't special and will cause confusions
7321 if we treat it as such. Likewise if it is equivalent to a constant. */
7322 else if (CONSTANT_P (x
)
7323 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7326 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7327 will be least confusing to the rest of the compiler. */
7328 else if (mode
== BImode
)
7330 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7334 /* If X is known to be either 0 or -1, those are the true and
7335 false values when testing X. */
7336 else if (x
== constm1_rtx
|| x
== const0_rtx
7337 || (mode
!= VOIDmode
7338 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7340 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7344 /* Likewise for 0 or a single bit. */
7345 else if (mode
!= VOIDmode
7346 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7347 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7349 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7353 /* Otherwise fail; show no condition with true and false values the same. */
7354 *ptrue
= *pfalse
= x
;
7358 /* Return the value of expression X given the fact that condition COND
7359 is known to be true when applied to REG as its first operand and VAL
7360 as its second. X is known to not be shared and so can be modified in
7363 We only handle the simplest cases, and specifically those cases that
7364 arise with IF_THEN_ELSE expressions. */
7367 known_cond (x
, cond
, reg
, val
)
7372 enum rtx_code code
= GET_CODE (x
);
7377 if (side_effects_p (x
))
7380 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7382 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7385 /* If X is (abs REG) and we know something about REG's relationship
7386 with zero, we may be able to simplify this. */
7388 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7391 case GE
: case GT
: case EQ
:
7394 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7396 GET_MODE (XEXP (x
, 0)));
7401 /* The only other cases we handle are MIN, MAX, and comparisons if the
7402 operands are the same as REG and VAL. */
7404 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7406 if (rtx_equal_p (XEXP (x
, 0), val
))
7407 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7409 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7411 if (GET_RTX_CLASS (code
) == '<')
7413 if (comparison_dominates_p (cond
, code
))
7414 return const_true_rtx
;
7416 code
= combine_reversed_comparison_code (x
);
7418 && comparison_dominates_p (cond
, code
))
7423 else if (code
== SMAX
|| code
== SMIN
7424 || code
== UMIN
|| code
== UMAX
)
7426 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7428 /* Do not reverse the condition when it is NE or EQ.
7429 This is because we cannot conclude anything about
7430 the value of 'SMAX (x, y)' when x is not equal to y,
7431 but we can when x equals y. */
7432 if ((code
== SMAX
|| code
== UMAX
)
7433 && ! (cond
== EQ
|| cond
== NE
))
7434 cond
= reverse_condition (cond
);
7439 return unsignedp
? x
: XEXP (x
, 1);
7441 return unsignedp
? x
: XEXP (x
, 0);
7443 return unsignedp
? XEXP (x
, 1) : x
;
7445 return unsignedp
? XEXP (x
, 0) : x
;
7453 fmt
= GET_RTX_FORMAT (code
);
7454 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7457 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7458 else if (fmt
[i
] == 'E')
7459 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7460 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7467 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7468 assignment as a field assignment. */
7471 rtx_equal_for_field_assignment_p (x
, y
)
7475 if (x
== y
|| rtx_equal_p (x
, y
))
7478 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7481 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7482 Note that all SUBREGs of MEM are paradoxical; otherwise they
7483 would have been rewritten. */
7484 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7485 && GET_CODE (SUBREG_REG (y
)) == MEM
7486 && rtx_equal_p (SUBREG_REG (y
),
7487 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7490 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7491 && GET_CODE (SUBREG_REG (x
)) == MEM
7492 && rtx_equal_p (SUBREG_REG (x
),
7493 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7496 /* We used to see if get_last_value of X and Y were the same but that's
7497 not correct. In one direction, we'll cause the assignment to have
7498 the wrong destination and in the case, we'll import a register into this
7499 insn that might have already have been dead. So fail if none of the
7500 above cases are true. */
7504 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7505 Return that assignment if so.
7507 We only handle the most common cases. */
7510 make_field_assignment (x
)
7513 rtx dest
= SET_DEST (x
);
7514 rtx src
= SET_SRC (x
);
7519 unsigned HOST_WIDE_INT len
;
7521 enum machine_mode mode
;
7523 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7524 a clear of a one-bit field. We will have changed it to
7525 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7528 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7529 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7530 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7531 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7533 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7536 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7540 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7541 && subreg_lowpart_p (XEXP (src
, 0))
7542 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7543 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7544 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7545 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7546 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7548 assign
= make_extraction (VOIDmode
, dest
, 0,
7549 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7552 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7556 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7558 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7559 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7560 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7562 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7565 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7569 /* The other case we handle is assignments into a constant-position
7570 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7571 a mask that has all one bits except for a group of zero bits and
7572 OTHER is known to have zeros where C1 has ones, this is such an
7573 assignment. Compute the position and length from C1. Shift OTHER
7574 to the appropriate position, force it to the required mode, and
7575 make the extraction. Check for the AND in both operands. */
7577 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7580 rhs
= expand_compound_operation (XEXP (src
, 0));
7581 lhs
= expand_compound_operation (XEXP (src
, 1));
7583 if (GET_CODE (rhs
) == AND
7584 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7585 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7586 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7587 else if (GET_CODE (lhs
) == AND
7588 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7589 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7590 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7594 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7595 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7596 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7597 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7600 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7604 /* The mode to use for the source is the mode of the assignment, or of
7605 what is inside a possible STRICT_LOW_PART. */
7606 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7607 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7609 /* Shift OTHER right POS places and make it the source, restricting it
7610 to the proper length and mode. */
7612 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7613 GET_MODE (src
), other
, pos
),
7615 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7616 ? ~(unsigned HOST_WIDE_INT
) 0
7617 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7620 return gen_rtx_SET (VOIDmode
, assign
, src
);
7623 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7627 apply_distributive_law (x
)
7630 enum rtx_code code
= GET_CODE (x
);
7631 rtx lhs
, rhs
, other
;
7633 enum rtx_code inner_code
;
7635 /* Distributivity is not true for floating point.
7636 It can change the value. So don't do it.
7637 -- rms and moshier@world.std.com. */
7638 if (FLOAT_MODE_P (GET_MODE (x
)))
7641 /* The outer operation can only be one of the following: */
7642 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7643 && code
!= PLUS
&& code
!= MINUS
)
7646 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7648 /* If either operand is a primitive we can't do anything, so get out
7650 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7651 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7654 lhs
= expand_compound_operation (lhs
);
7655 rhs
= expand_compound_operation (rhs
);
7656 inner_code
= GET_CODE (lhs
);
7657 if (inner_code
!= GET_CODE (rhs
))
7660 /* See if the inner and outer operations distribute. */
7667 /* These all distribute except over PLUS. */
7668 if (code
== PLUS
|| code
== MINUS
)
7673 if (code
!= PLUS
&& code
!= MINUS
)
7678 /* This is also a multiply, so it distributes over everything. */
7682 /* Non-paradoxical SUBREGs distributes over all operations, provided
7683 the inner modes and byte offsets are the same, this is an extraction
7684 of a low-order part, we don't convert an fp operation to int or
7685 vice versa, and we would not be converting a single-word
7686 operation into a multi-word operation. The latter test is not
7687 required, but it prevents generating unneeded multi-word operations.
7688 Some of the previous tests are redundant given the latter test, but
7689 are retained because they are required for correctness.
7691 We produce the result slightly differently in this case. */
7693 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7694 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7695 || ! subreg_lowpart_p (lhs
)
7696 || (GET_MODE_CLASS (GET_MODE (lhs
))
7697 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7698 || (GET_MODE_SIZE (GET_MODE (lhs
))
7699 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7700 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7703 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7704 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7705 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7711 /* Set LHS and RHS to the inner operands (A and B in the example
7712 above) and set OTHER to the common operand (C in the example).
7713 These is only one way to do this unless the inner operation is
7715 if (GET_RTX_CLASS (inner_code
) == 'c'
7716 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7717 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7718 else if (GET_RTX_CLASS (inner_code
) == 'c'
7719 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7720 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7721 else if (GET_RTX_CLASS (inner_code
) == 'c'
7722 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7723 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7724 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7725 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7729 /* Form the new inner operation, seeing if it simplifies first. */
7730 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7732 /* There is one exception to the general way of distributing:
7733 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7734 if (code
== XOR
&& inner_code
== IOR
)
7737 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7740 /* We may be able to continuing distributing the result, so call
7741 ourselves recursively on the inner operation before forming the
7742 outer operation, which we return. */
7743 return gen_binary (inner_code
, GET_MODE (x
),
7744 apply_distributive_law (tem
), other
);
7747 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7750 Return an equivalent form, if different from X. Otherwise, return X. If
7751 X is zero, we are to always construct the equivalent form. */
7754 simplify_and_const_int (x
, mode
, varop
, constop
)
7756 enum machine_mode mode
;
7758 unsigned HOST_WIDE_INT constop
;
7760 unsigned HOST_WIDE_INT nonzero
;
7763 /* Simplify VAROP knowing that we will be only looking at some of the
7765 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7767 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7768 CONST_INT, we are done. */
7769 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7772 /* See what bits may be nonzero in VAROP. Unlike the general case of
7773 a call to nonzero_bits, here we don't care about bits outside
7776 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7777 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7779 /* Turn off all bits in the constant that are known to already be zero.
7780 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7781 which is tested below. */
7785 /* If we don't have any bits left, return zero. */
7789 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7790 a power of two, we can replace this with a ASHIFT. */
7791 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7792 && (i
= exact_log2 (constop
)) >= 0)
7793 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7795 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7796 or XOR, then try to apply the distributive law. This may eliminate
7797 operations if either branch can be simplified because of the AND.
7798 It may also make some cases more complex, but those cases probably
7799 won't match a pattern either with or without this. */
7801 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7803 gen_lowpart_for_combine
7805 apply_distributive_law
7806 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7807 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7808 XEXP (varop
, 0), constop
),
7809 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7810 XEXP (varop
, 1), constop
))));
7812 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7813 if we already had one (just check for the simplest cases). */
7814 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7815 && GET_MODE (XEXP (x
, 0)) == mode
7816 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7817 varop
= XEXP (x
, 0);
7819 varop
= gen_lowpart_for_combine (mode
, varop
);
7821 /* If we can't make the SUBREG, try to return what we were given. */
7822 if (GET_CODE (varop
) == CLOBBER
)
7823 return x
? x
: varop
;
7825 /* If we are only masking insignificant bits, return VAROP. */
7826 if (constop
== nonzero
)
7829 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7830 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7831 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7835 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7836 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7837 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7839 SUBST (XEXP (x
, 0), varop
);
7845 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7846 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7847 is less useful. We can't allow both, because that results in exponential
7848 run time recursion. There is a nullstone testcase that triggered
7849 this. This macro avoids accidental uses of num_sign_bit_copies. */
7850 #define num_sign_bit_copies()
7852 /* Given an expression, X, compute which bits in X can be non-zero.
7853 We don't care about bits outside of those defined in MODE.
7855 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7856 a shift, AND, or zero_extract, we can do better. */
7858 static unsigned HOST_WIDE_INT
7859 nonzero_bits (x
, mode
)
7861 enum machine_mode mode
;
7863 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7864 unsigned HOST_WIDE_INT inner_nz
;
7866 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
7869 /* For floating-point values, assume all bits are needed. */
7870 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7873 /* If X is wider than MODE, use its mode instead. */
7874 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7876 mode
= GET_MODE (x
);
7877 nonzero
= GET_MODE_MASK (mode
);
7878 mode_width
= GET_MODE_BITSIZE (mode
);
7881 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7882 /* Our only callers in this case look for single bit values. So
7883 just return the mode mask. Those tests will then be false. */
7886 #ifndef WORD_REGISTER_OPERATIONS
7887 /* If MODE is wider than X, but both are a single word for both the host
7888 and target machines, we can compute this from which bits of the
7889 object might be nonzero in its own mode, taking into account the fact
7890 that on many CISC machines, accessing an object in a wider mode
7891 causes the high-order bits to become undefined. So they are
7892 not known to be zero. */
7894 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7895 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7896 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7897 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7899 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7900 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
7905 code
= GET_CODE (x
);
7909 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7910 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7911 all the bits above ptr_mode are known to be zero. */
7912 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7914 nonzero
&= GET_MODE_MASK (ptr_mode
);
7917 #ifdef STACK_BOUNDARY
7918 /* If this is the stack pointer, we may know something about its
7919 alignment. If PUSH_ROUNDING is defined, it is possible for the
7920 stack to be momentarily aligned only to that amount, so we pick
7921 the least alignment. */
7923 /* We can't check for arg_pointer_rtx here, because it is not
7924 guaranteed to have as much alignment as the stack pointer.
7925 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7926 alignment but the argument pointer has only 64 bit alignment. */
7928 if ((x
== frame_pointer_rtx
7929 || x
== stack_pointer_rtx
7930 || x
== hard_frame_pointer_rtx
7931 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7932 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7938 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7940 #ifdef PUSH_ROUNDING
7941 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
7942 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7945 /* We must return here, otherwise we may get a worse result from
7946 one of the choices below. There is nothing useful below as
7947 far as the stack pointer is concerned. */
7948 return nonzero
&= ~(sp_alignment
- 1);
7952 /* If X is a register whose nonzero bits value is current, use it.
7953 Otherwise, if X is a register whose value we can find, use that
7954 value. Otherwise, use the previously-computed global nonzero bits
7955 for this register. */
7957 if (reg_last_set_value
[REGNO (x
)] != 0
7958 && reg_last_set_mode
[REGNO (x
)] == mode
7959 && (reg_last_set_label
[REGNO (x
)] == label_tick
7960 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7961 && REG_N_SETS (REGNO (x
)) == 1
7962 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7964 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7965 return reg_last_set_nonzero_bits
[REGNO (x
)];
7967 tem
= get_last_value (x
);
7971 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7972 /* If X is narrower than MODE and TEM is a non-negative
7973 constant that would appear negative in the mode of X,
7974 sign-extend it for use in reg_nonzero_bits because some
7975 machines (maybe most) will actually do the sign-extension
7976 and this is the conservative approach.
7978 ??? For 2.5, try to tighten up the MD files in this regard
7979 instead of this kludge. */
7981 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7982 && GET_CODE (tem
) == CONST_INT
7984 && 0 != (INTVAL (tem
)
7985 & ((HOST_WIDE_INT
) 1
7986 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7987 tem
= GEN_INT (INTVAL (tem
)
7988 | ((HOST_WIDE_INT
) (-1)
7989 << GET_MODE_BITSIZE (GET_MODE (x
))));
7991 return nonzero_bits (tem
, mode
);
7993 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7994 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7999 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8000 /* If X is negative in MODE, sign-extend the value. */
8001 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8002 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8003 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8009 #ifdef LOAD_EXTEND_OP
8010 /* In many, if not most, RISC machines, reading a byte from memory
8011 zeros the rest of the register. Noticing that fact saves a lot
8012 of extra zero-extends. */
8013 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8014 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8019 case UNEQ
: case LTGT
:
8020 case GT
: case GTU
: case UNGT
:
8021 case LT
: case LTU
: case UNLT
:
8022 case GE
: case GEU
: case UNGE
:
8023 case LE
: case LEU
: case UNLE
:
8024 case UNORDERED
: case ORDERED
:
8026 /* If this produces an integer result, we know which bits are set.
8027 Code here used to clear bits outside the mode of X, but that is
8030 if (GET_MODE_CLASS (mode
) == MODE_INT
8031 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8032 nonzero
= STORE_FLAG_VALUE
;
8037 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8038 and num_sign_bit_copies. */
8039 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8040 == GET_MODE_BITSIZE (GET_MODE (x
)))
8044 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8045 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8050 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8051 and num_sign_bit_copies. */
8052 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8053 == GET_MODE_BITSIZE (GET_MODE (x
)))
8059 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8063 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8064 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8065 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8069 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8070 Otherwise, show all the bits in the outer mode but not the inner
8072 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8073 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8075 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8077 & (((HOST_WIDE_INT
) 1
8078 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8079 inner_nz
|= (GET_MODE_MASK (mode
)
8080 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8083 nonzero
&= inner_nz
;
8087 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8088 & nonzero_bits (XEXP (x
, 1), mode
));
8092 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8093 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8094 | nonzero_bits (XEXP (x
, 1), mode
));
8097 case PLUS
: case MINUS
:
8099 case DIV
: case UDIV
:
8100 case MOD
: case UMOD
:
8101 /* We can apply the rules of arithmetic to compute the number of
8102 high- and low-order zero bits of these operations. We start by
8103 computing the width (position of the highest-order non-zero bit)
8104 and the number of low-order zero bits for each value. */
8106 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8107 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8108 int width0
= floor_log2 (nz0
) + 1;
8109 int width1
= floor_log2 (nz1
) + 1;
8110 int low0
= floor_log2 (nz0
& -nz0
);
8111 int low1
= floor_log2 (nz1
& -nz1
);
8112 HOST_WIDE_INT op0_maybe_minusp
8113 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8114 HOST_WIDE_INT op1_maybe_minusp
8115 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8116 unsigned int result_width
= mode_width
;
8124 && (XEXP (x
, 0) == stack_pointer_rtx
8125 || XEXP (x
, 0) == frame_pointer_rtx
)
8126 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8128 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8130 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8131 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8132 width0
= floor_log2 (nz0
) + 1;
8133 width1
= floor_log2 (nz1
) + 1;
8134 low0
= floor_log2 (nz0
& -nz0
);
8135 low1
= floor_log2 (nz1
& -nz1
);
8138 result_width
= MAX (width0
, width1
) + 1;
8139 result_low
= MIN (low0
, low1
);
8142 result_low
= MIN (low0
, low1
);
8145 result_width
= width0
+ width1
;
8146 result_low
= low0
+ low1
;
8151 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8152 result_width
= width0
;
8157 result_width
= width0
;
8162 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8163 result_width
= MIN (width0
, width1
);
8164 result_low
= MIN (low0
, low1
);
8169 result_width
= MIN (width0
, width1
);
8170 result_low
= MIN (low0
, low1
);
8176 if (result_width
< mode_width
)
8177 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8180 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8182 #ifdef POINTERS_EXTEND_UNSIGNED
8183 /* If pointers extend unsigned and this is an addition or subtraction
8184 to a pointer in Pmode, all the bits above ptr_mode are known to be
8186 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8187 && (code
== PLUS
|| code
== MINUS
)
8188 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8189 nonzero
&= GET_MODE_MASK (ptr_mode
);
8195 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8196 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8197 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8201 /* If this is a SUBREG formed for a promoted variable that has
8202 been zero-extended, we know that at least the high-order bits
8203 are zero, though others might be too. */
8205 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8206 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8207 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8209 /* If the inner mode is a single word for both the host and target
8210 machines, we can compute this from which bits of the inner
8211 object might be nonzero. */
8212 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8213 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8214 <= HOST_BITS_PER_WIDE_INT
))
8216 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8218 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8219 /* If this is a typical RISC machine, we only have to worry
8220 about the way loads are extended. */
8221 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8223 & (((unsigned HOST_WIDE_INT
) 1
8224 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8226 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8229 /* On many CISC machines, accessing an object in a wider mode
8230 causes the high-order bits to become undefined. So they are
8231 not known to be zero. */
8232 if (GET_MODE_SIZE (GET_MODE (x
))
8233 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8234 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8235 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8244 /* The nonzero bits are in two classes: any bits within MODE
8245 that aren't in GET_MODE (x) are always significant. The rest of the
8246 nonzero bits are those that are significant in the operand of
8247 the shift when shifted the appropriate number of bits. This
8248 shows that high-order bits are cleared by the right shift and
8249 low-order bits by left shifts. */
8250 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8251 && INTVAL (XEXP (x
, 1)) >= 0
8252 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8254 enum machine_mode inner_mode
= GET_MODE (x
);
8255 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8256 int count
= INTVAL (XEXP (x
, 1));
8257 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8258 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8259 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8260 unsigned HOST_WIDE_INT outer
= 0;
8262 if (mode_width
> width
)
8263 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8265 if (code
== LSHIFTRT
)
8267 else if (code
== ASHIFTRT
)
8271 /* If the sign bit may have been nonzero before the shift, we
8272 need to mark all the places it could have been copied to
8273 by the shift as possibly nonzero. */
8274 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8275 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8277 else if (code
== ASHIFT
)
8280 inner
= ((inner
<< (count
% width
)
8281 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8283 nonzero
&= (outer
| inner
);
8288 /* This is at most the number of bits in the mode. */
8289 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8293 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8294 | nonzero_bits (XEXP (x
, 2), mode
));
8304 /* See the macro definition above. */
8305 #undef num_sign_bit_copies
8307 /* Return the number of bits at the high-order end of X that are known to
8308 be equal to the sign bit. X will be used in mode MODE; if MODE is
8309 VOIDmode, X will be used in its own mode. The returned value will always
8310 be between 1 and the number of bits in MODE. */
8313 num_sign_bit_copies (x
, mode
)
8315 enum machine_mode mode
;
8317 enum rtx_code code
= GET_CODE (x
);
8318 unsigned int bitwidth
;
8319 int num0
, num1
, result
;
8320 unsigned HOST_WIDE_INT nonzero
;
8323 /* If we weren't given a mode, use the mode of X. If the mode is still
8324 VOIDmode, we don't know anything. Likewise if one of the modes is
8327 if (mode
== VOIDmode
)
8328 mode
= GET_MODE (x
);
8330 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8333 bitwidth
= GET_MODE_BITSIZE (mode
);
8335 /* For a smaller object, just ignore the high bits. */
8336 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8338 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8340 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8343 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8345 #ifndef WORD_REGISTER_OPERATIONS
8346 /* If this machine does not do all register operations on the entire
8347 register and MODE is wider than the mode of X, we can say nothing
8348 at all about the high-order bits. */
8351 /* Likewise on machines that do, if the mode of the object is smaller
8352 than a word and loads of that size don't sign extend, we can say
8353 nothing about the high order bits. */
8354 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8355 #ifdef LOAD_EXTEND_OP
8356 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8367 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8368 /* If pointers extend signed and this is a pointer in Pmode, say that
8369 all the bits above ptr_mode are known to be sign bit copies. */
8370 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8372 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8375 if (reg_last_set_value
[REGNO (x
)] != 0
8376 && reg_last_set_mode
[REGNO (x
)] == mode
8377 && (reg_last_set_label
[REGNO (x
)] == label_tick
8378 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8379 && REG_N_SETS (REGNO (x
)) == 1
8380 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8382 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8383 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8385 tem
= get_last_value (x
);
8387 return num_sign_bit_copies (tem
, mode
);
8389 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8390 return reg_sign_bit_copies
[REGNO (x
)];
8394 #ifdef LOAD_EXTEND_OP
8395 /* Some RISC machines sign-extend all loads of smaller than a word. */
8396 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8397 return MAX (1, ((int) bitwidth
8398 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8403 /* If the constant is negative, take its 1's complement and remask.
8404 Then see how many zero bits we have. */
8405 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8406 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8407 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8408 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8410 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8413 /* If this is a SUBREG for a promoted object that is sign-extended
8414 and we are looking at it in a wider mode, we know that at least the
8415 high-order bits are known to be sign bit copies. */
8417 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8419 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8420 return MAX ((int) bitwidth
8421 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8425 /* For a smaller object, just ignore the high bits. */
8426 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8428 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8429 return MAX (1, (num0
8430 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8434 #ifdef WORD_REGISTER_OPERATIONS
8435 #ifdef LOAD_EXTEND_OP
8436 /* For paradoxical SUBREGs on machines where all register operations
8437 affect the entire register, just look inside. Note that we are
8438 passing MODE to the recursive call, so the number of sign bit copies
8439 will remain relative to that mode, not the inner mode. */
8441 /* This works only if loads sign extend. Otherwise, if we get a
8442 reload for the inner part, it may be loaded from the stack, and
8443 then we lose all sign bit copies that existed before the store
8446 if ((GET_MODE_SIZE (GET_MODE (x
))
8447 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8448 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8449 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8455 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8456 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8460 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8461 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8464 /* For a smaller object, just ignore the high bits. */
8465 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8466 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8470 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8472 case ROTATE
: case ROTATERT
:
8473 /* If we are rotating left by a number of bits less than the number
8474 of sign bit copies, we can just subtract that amount from the
8476 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8477 && INTVAL (XEXP (x
, 1)) >= 0
8478 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8480 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8481 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8482 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8487 /* In general, this subtracts one sign bit copy. But if the value
8488 is known to be positive, the number of sign bit copies is the
8489 same as that of the input. Finally, if the input has just one bit
8490 that might be nonzero, all the bits are copies of the sign bit. */
8491 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8492 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8493 return num0
> 1 ? num0
- 1 : 1;
8495 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8500 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8505 case IOR
: case AND
: case XOR
:
8506 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8507 /* Logical operations will preserve the number of sign-bit copies.
8508 MIN and MAX operations always return one of the operands. */
8509 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8510 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8511 return MIN (num0
, num1
);
8513 case PLUS
: case MINUS
:
8514 /* For addition and subtraction, we can have a 1-bit carry. However,
8515 if we are subtracting 1 from a positive number, there will not
8516 be such a carry. Furthermore, if the positive number is known to
8517 be 0 or 1, we know the result is either -1 or 0. */
8519 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8520 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8522 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8523 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8524 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8525 : bitwidth
- floor_log2 (nonzero
) - 1);
8528 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8529 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8530 result
= MAX (1, MIN (num0
, num1
) - 1);
8532 #ifdef POINTERS_EXTEND_UNSIGNED
8533 /* If pointers extend signed and this is an addition or subtraction
8534 to a pointer in Pmode, all the bits above ptr_mode are known to be
8536 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8537 && (code
== PLUS
|| code
== MINUS
)
8538 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8539 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8540 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8546 /* The number of bits of the product is the sum of the number of
8547 bits of both terms. However, unless one of the terms if known
8548 to be positive, we must allow for an additional bit since negating
8549 a negative number can remove one sign bit copy. */
8551 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8552 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8554 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8556 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8557 || (((nonzero_bits (XEXP (x
, 0), mode
)
8558 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8559 && ((nonzero_bits (XEXP (x
, 1), mode
)
8560 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8563 return MAX (1, result
);
8566 /* The result must be <= the first operand. If the first operand
8567 has the high bit set, we know nothing about the number of sign
8569 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8571 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8572 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8575 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8578 /* The result must be <= the scond operand. */
8579 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8582 /* Similar to unsigned division, except that we have to worry about
8583 the case where the divisor is negative, in which case we have
8585 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8587 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8588 || (nonzero_bits (XEXP (x
, 1), mode
)
8589 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8595 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8597 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8598 || (nonzero_bits (XEXP (x
, 1), mode
)
8599 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8605 /* Shifts by a constant add to the number of bits equal to the
8607 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8608 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8609 && INTVAL (XEXP (x
, 1)) > 0)
8610 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8615 /* Left shifts destroy copies. */
8616 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8617 || INTVAL (XEXP (x
, 1)) < 0
8618 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8621 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8622 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8625 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8626 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8627 return MIN (num0
, num1
);
8629 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8630 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8631 case GEU
: case GTU
: case LEU
: case LTU
:
8632 case UNORDERED
: case ORDERED
:
8633 /* If the constant is negative, take its 1's complement and remask.
8634 Then see how many zero bits we have. */
8635 nonzero
= STORE_FLAG_VALUE
;
8636 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8637 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8638 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8640 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8647 /* If we haven't been able to figure it out by one of the above rules,
8648 see if some of the high-order bits are known to be zero. If so,
8649 count those bits and return one less than that amount. If we can't
8650 safely compute the mask for this mode, always return BITWIDTH. */
8652 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8655 nonzero
= nonzero_bits (x
, mode
);
8656 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8657 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8660 /* Return the number of "extended" bits there are in X, when interpreted
8661 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8662 unsigned quantities, this is the number of high-order zero bits.
8663 For signed quantities, this is the number of copies of the sign bit
8664 minus 1. In both case, this function returns the number of "spare"
8665 bits. For example, if two quantities for which this function returns
8666 at least 1 are added, the addition is known not to overflow.
8668 This function will always return 0 unless called during combine, which
8669 implies that it must be called from a define_split. */
8672 extended_count (x
, mode
, unsignedp
)
8674 enum machine_mode mode
;
8677 if (nonzero_sign_valid
== 0)
8681 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8682 ? (GET_MODE_BITSIZE (mode
) - 1
8683 - floor_log2 (nonzero_bits (x
, mode
)))
8685 : num_sign_bit_copies (x
, mode
) - 1);
8688 /* This function is called from `simplify_shift_const' to merge two
8689 outer operations. Specifically, we have already found that we need
8690 to perform operation *POP0 with constant *PCONST0 at the outermost
8691 position. We would now like to also perform OP1 with constant CONST1
8692 (with *POP0 being done last).
8694 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8695 the resulting operation. *PCOMP_P is set to 1 if we would need to
8696 complement the innermost operand, otherwise it is unchanged.
8698 MODE is the mode in which the operation will be done. No bits outside
8699 the width of this mode matter. It is assumed that the width of this mode
8700 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8702 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8703 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8704 result is simply *PCONST0.
8706 If the resulting operation cannot be expressed as one operation, we
8707 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8710 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8711 enum rtx_code
*pop0
;
8712 HOST_WIDE_INT
*pconst0
;
8714 HOST_WIDE_INT const1
;
8715 enum machine_mode mode
;
8718 enum rtx_code op0
= *pop0
;
8719 HOST_WIDE_INT const0
= *pconst0
;
8721 const0
&= GET_MODE_MASK (mode
);
8722 const1
&= GET_MODE_MASK (mode
);
8724 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8728 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8731 if (op1
== NIL
|| op0
== SET
)
8734 else if (op0
== NIL
)
8735 op0
= op1
, const0
= const1
;
8737 else if (op0
== op1
)
8761 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8762 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8765 /* If the two constants aren't the same, we can't do anything. The
8766 remaining six cases can all be done. */
8767 else if (const0
!= const1
)
8775 /* (a & b) | b == b */
8777 else /* op1 == XOR */
8778 /* (a ^ b) | b == a | b */
8784 /* (a & b) ^ b == (~a) & b */
8785 op0
= AND
, *pcomp_p
= 1;
8786 else /* op1 == IOR */
8787 /* (a | b) ^ b == a & ~b */
8788 op0
= AND
, *pconst0
= ~const0
;
8793 /* (a | b) & b == b */
8795 else /* op1 == XOR */
8796 /* (a ^ b) & b) == (~a) & b */
8803 /* Check for NO-OP cases. */
8804 const0
&= GET_MODE_MASK (mode
);
8806 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8808 else if (const0
== 0 && op0
== AND
)
8810 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8814 /* ??? Slightly redundant with the above mask, but not entirely.
8815 Moving this above means we'd have to sign-extend the mode mask
8816 for the final test. */
8817 const0
= trunc_int_for_mode (const0
, mode
);
8825 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8826 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8827 that we started with.
8829 The shift is normally computed in the widest mode we find in VAROP, as
8830 long as it isn't a different number of words than RESULT_MODE. Exceptions
8831 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8834 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8837 enum machine_mode result_mode
;
8841 enum rtx_code orig_code
= code
;
8842 int orig_count
= input_count
;
8845 enum machine_mode mode
= result_mode
;
8846 enum machine_mode shift_mode
, tmode
;
8847 unsigned int mode_words
8848 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8849 /* We form (outer_op (code varop count) (outer_const)). */
8850 enum rtx_code outer_op
= NIL
;
8851 HOST_WIDE_INT outer_const
= 0;
8853 int complement_p
= 0;
8856 /* If we were given an invalid count, don't do anything except exactly
8857 what was requested. */
8859 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8864 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8867 count
= input_count
;
8869 /* Make sure and truncate the "natural" shift on the way in. We don't
8870 want to do this inside the loop as it makes it more difficult to
8872 #ifdef SHIFT_COUNT_TRUNCATED
8873 if (SHIFT_COUNT_TRUNCATED
)
8874 count
%= GET_MODE_BITSIZE (mode
);
8877 /* Unless one of the branches of the `if' in this loop does a `continue',
8878 we will `break' the loop after the `if'. */
8882 /* If we have an operand of (clobber (const_int 0)), just return that
8884 if (GET_CODE (varop
) == CLOBBER
)
8887 /* If we discovered we had to complement VAROP, leave. Making a NOT
8888 here would cause an infinite loop. */
8892 /* Convert ROTATERT to ROTATE. */
8893 if (code
== ROTATERT
)
8894 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8896 /* We need to determine what mode we will do the shift in. If the
8897 shift is a right shift or a ROTATE, we must always do it in the mode
8898 it was originally done in. Otherwise, we can do it in MODE, the
8899 widest mode encountered. */
8901 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8902 ? result_mode
: mode
);
8904 /* Handle cases where the count is greater than the size of the mode
8905 minus 1. For ASHIFT, use the size minus one as the count (this can
8906 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8907 take the count modulo the size. For other shifts, the result is
8910 Since these shifts are being produced by the compiler by combining
8911 multiple operations, each of which are defined, we know what the
8912 result is supposed to be. */
8914 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8916 if (code
== ASHIFTRT
)
8917 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8918 else if (code
== ROTATE
|| code
== ROTATERT
)
8919 count
%= GET_MODE_BITSIZE (shift_mode
);
8922 /* We can't simply return zero because there may be an
8930 /* An arithmetic right shift of a quantity known to be -1 or 0
8932 if (code
== ASHIFTRT
8933 && (num_sign_bit_copies (varop
, shift_mode
)
8934 == GET_MODE_BITSIZE (shift_mode
)))
8940 /* If we are doing an arithmetic right shift and discarding all but
8941 the sign bit copies, this is equivalent to doing a shift by the
8942 bitsize minus one. Convert it into that shift because it will often
8943 allow other simplifications. */
8945 if (code
== ASHIFTRT
8946 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8947 >= GET_MODE_BITSIZE (shift_mode
)))
8948 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8950 /* We simplify the tests below and elsewhere by converting
8951 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8952 `make_compound_operation' will convert it to a ASHIFTRT for
8953 those machines (such as VAX) that don't have a LSHIFTRT. */
8954 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8956 && ((nonzero_bits (varop
, shift_mode
)
8957 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8961 switch (GET_CODE (varop
))
8967 new = expand_compound_operation (varop
);
8976 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8977 minus the width of a smaller mode, we can do this with a
8978 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8979 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8980 && ! mode_dependent_address_p (XEXP (varop
, 0))
8981 && ! MEM_VOLATILE_P (varop
)
8982 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8983 MODE_INT
, 1)) != BLKmode
)
8985 new = adjust_address_nv (varop
, tmode
,
8986 BYTES_BIG_ENDIAN
? 0
8987 : count
/ BITS_PER_UNIT
);
8989 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8990 : ZERO_EXTEND
, mode
, new);
8997 /* Similar to the case above, except that we can only do this if
8998 the resulting mode is the same as that of the underlying
8999 MEM and adjust the address depending on the *bits* endianness
9000 because of the way that bit-field extract insns are defined. */
9001 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9002 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9003 MODE_INT
, 1)) != BLKmode
9004 && tmode
== GET_MODE (XEXP (varop
, 0)))
9006 if (BITS_BIG_ENDIAN
)
9007 new = XEXP (varop
, 0);
9010 new = copy_rtx (XEXP (varop
, 0));
9011 SUBST (XEXP (new, 0),
9012 plus_constant (XEXP (new, 0),
9013 count
/ BITS_PER_UNIT
));
9016 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9017 : ZERO_EXTEND
, mode
, new);
9024 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9025 the same number of words as what we've seen so far. Then store
9026 the widest mode in MODE. */
9027 if (subreg_lowpart_p (varop
)
9028 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9029 > GET_MODE_SIZE (GET_MODE (varop
)))
9030 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9031 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9034 varop
= SUBREG_REG (varop
);
9035 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9036 mode
= GET_MODE (varop
);
9042 /* Some machines use MULT instead of ASHIFT because MULT
9043 is cheaper. But it is still better on those machines to
9044 merge two shifts into one. */
9045 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9046 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9049 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9050 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9056 /* Similar, for when divides are cheaper. */
9057 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9058 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9061 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9062 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9068 /* If we are extracting just the sign bit of an arithmetic
9069 right shift, that shift is not needed. However, the sign
9070 bit of a wider mode may be different from what would be
9071 interpreted as the sign bit in a narrower mode, so, if
9072 the result is narrower, don't discard the shift. */
9073 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9074 && (GET_MODE_BITSIZE (result_mode
)
9075 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9077 varop
= XEXP (varop
, 0);
9081 /* ... fall through ... */
9086 /* Here we have two nested shifts. The result is usually the
9087 AND of a new shift with a mask. We compute the result below. */
9088 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9089 && INTVAL (XEXP (varop
, 1)) >= 0
9090 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9091 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9092 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9094 enum rtx_code first_code
= GET_CODE (varop
);
9095 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9096 unsigned HOST_WIDE_INT mask
;
9099 /* We have one common special case. We can't do any merging if
9100 the inner code is an ASHIFTRT of a smaller mode. However, if
9101 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9102 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9103 we can convert it to
9104 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9105 This simplifies certain SIGN_EXTEND operations. */
9106 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9107 && (GET_MODE_BITSIZE (result_mode
)
9108 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9110 /* C3 has the low-order C1 bits zero. */
9112 mask
= (GET_MODE_MASK (mode
)
9113 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9115 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9116 XEXP (varop
, 0), mask
);
9117 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9119 count
= first_count
;
9124 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9125 than C1 high-order bits equal to the sign bit, we can convert
9126 this to either an ASHIFT or a ASHIFTRT depending on the
9129 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9131 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9132 && GET_MODE (varop
) == shift_mode
9133 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9136 varop
= XEXP (varop
, 0);
9138 signed_count
= count
- first_count
;
9139 if (signed_count
< 0)
9140 count
= -signed_count
, code
= ASHIFT
;
9142 count
= signed_count
;
9147 /* There are some cases we can't do. If CODE is ASHIFTRT,
9148 we can only do this if FIRST_CODE is also ASHIFTRT.
9150 We can't do the case when CODE is ROTATE and FIRST_CODE is
9153 If the mode of this shift is not the mode of the outer shift,
9154 we can't do this if either shift is a right shift or ROTATE.
9156 Finally, we can't do any of these if the mode is too wide
9157 unless the codes are the same.
9159 Handle the case where the shift codes are the same
9162 if (code
== first_code
)
9164 if (GET_MODE (varop
) != result_mode
9165 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9169 count
+= first_count
;
9170 varop
= XEXP (varop
, 0);
9174 if (code
== ASHIFTRT
9175 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9176 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9177 || (GET_MODE (varop
) != result_mode
9178 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9179 || first_code
== ROTATE
9180 || code
== ROTATE
)))
9183 /* To compute the mask to apply after the shift, shift the
9184 nonzero bits of the inner shift the same way the
9185 outer shift will. */
9187 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9190 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9193 /* Give up if we can't compute an outer operation to use. */
9195 || GET_CODE (mask_rtx
) != CONST_INT
9196 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9198 result_mode
, &complement_p
))
9201 /* If the shifts are in the same direction, we add the
9202 counts. Otherwise, we subtract them. */
9203 signed_count
= count
;
9204 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9205 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9206 signed_count
+= first_count
;
9208 signed_count
-= first_count
;
9210 /* If COUNT is positive, the new shift is usually CODE,
9211 except for the two exceptions below, in which case it is
9212 FIRST_CODE. If the count is negative, FIRST_CODE should
9214 if (signed_count
> 0
9215 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9216 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9217 code
= first_code
, count
= signed_count
;
9218 else if (signed_count
< 0)
9219 code
= first_code
, count
= -signed_count
;
9221 count
= signed_count
;
9223 varop
= XEXP (varop
, 0);
9227 /* If we have (A << B << C) for any shift, we can convert this to
9228 (A << C << B). This wins if A is a constant. Only try this if
9229 B is not a constant. */
9231 else if (GET_CODE (varop
) == code
9232 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9234 = simplify_binary_operation (code
, mode
,
9238 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9245 /* Make this fit the case below. */
9246 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9247 GEN_INT (GET_MODE_MASK (mode
)));
9253 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9254 with C the size of VAROP - 1 and the shift is logical if
9255 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9256 we have an (le X 0) operation. If we have an arithmetic shift
9257 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9258 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9260 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9261 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9262 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9263 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9264 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9265 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9268 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9271 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9272 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9277 /* If we have (shift (logical)), move the logical to the outside
9278 to allow it to possibly combine with another logical and the
9279 shift to combine with another shift. This also canonicalizes to
9280 what a ZERO_EXTRACT looks like. Also, some machines have
9281 (and (shift)) insns. */
9283 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9284 && (new = simplify_binary_operation (code
, result_mode
,
9286 GEN_INT (count
))) != 0
9287 && GET_CODE (new) == CONST_INT
9288 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9289 INTVAL (new), result_mode
, &complement_p
))
9291 varop
= XEXP (varop
, 0);
9295 /* If we can't do that, try to simplify the shift in each arm of the
9296 logical expression, make a new logical expression, and apply
9297 the inverse distributive law. */
9299 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9300 XEXP (varop
, 0), count
);
9301 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9302 XEXP (varop
, 1), count
);
9304 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9305 varop
= apply_distributive_law (varop
);
9312 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9313 says that the sign bit can be tested, FOO has mode MODE, C is
9314 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9315 that may be nonzero. */
9316 if (code
== LSHIFTRT
9317 && XEXP (varop
, 1) == const0_rtx
9318 && GET_MODE (XEXP (varop
, 0)) == result_mode
9319 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9320 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9321 && ((STORE_FLAG_VALUE
9322 & ((HOST_WIDE_INT
) 1
9323 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9324 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9325 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9326 (HOST_WIDE_INT
) 1, result_mode
,
9329 varop
= XEXP (varop
, 0);
9336 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9337 than the number of bits in the mode is equivalent to A. */
9338 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9339 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9341 varop
= XEXP (varop
, 0);
9346 /* NEG commutes with ASHIFT since it is multiplication. Move the
9347 NEG outside to allow shifts to combine. */
9349 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9350 (HOST_WIDE_INT
) 0, result_mode
,
9353 varop
= XEXP (varop
, 0);
9359 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9360 is one less than the number of bits in the mode is
9361 equivalent to (xor A 1). */
9362 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9363 && XEXP (varop
, 1) == constm1_rtx
9364 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9365 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9366 (HOST_WIDE_INT
) 1, result_mode
,
9370 varop
= XEXP (varop
, 0);
9374 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9375 that might be nonzero in BAR are those being shifted out and those
9376 bits are known zero in FOO, we can replace the PLUS with FOO.
9377 Similarly in the other operand order. This code occurs when
9378 we are computing the size of a variable-size array. */
9380 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9381 && count
< HOST_BITS_PER_WIDE_INT
9382 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9383 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9384 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9386 varop
= XEXP (varop
, 0);
9389 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9390 && count
< HOST_BITS_PER_WIDE_INT
9391 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9392 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9394 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9395 & nonzero_bits (XEXP (varop
, 1),
9398 varop
= XEXP (varop
, 1);
9402 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9404 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9405 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9407 GEN_INT (count
))) != 0
9408 && GET_CODE (new) == CONST_INT
9409 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9410 INTVAL (new), result_mode
, &complement_p
))
9412 varop
= XEXP (varop
, 0);
9418 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9419 with C the size of VAROP - 1 and the shift is logical if
9420 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9421 we have a (gt X 0) operation. If the shift is arithmetic with
9422 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9423 we have a (neg (gt X 0)) operation. */
9425 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9426 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9427 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9428 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9429 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9430 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9431 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9434 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9437 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9438 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9445 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9446 if the truncate does not affect the value. */
9447 if (code
== LSHIFTRT
9448 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9449 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9450 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9451 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9452 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9454 rtx varop_inner
= XEXP (varop
, 0);
9457 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9458 XEXP (varop_inner
, 0),
9460 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9461 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9474 /* We need to determine what mode to do the shift in. If the shift is
9475 a right shift or ROTATE, we must always do it in the mode it was
9476 originally done in. Otherwise, we can do it in MODE, the widest mode
9477 encountered. The code we care about is that of the shift that will
9478 actually be done, not the shift that was originally requested. */
9480 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9481 ? result_mode
: mode
);
9483 /* We have now finished analyzing the shift. The result should be
9484 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9485 OUTER_OP is non-NIL, it is an operation that needs to be applied
9486 to the result of the shift. OUTER_CONST is the relevant constant,
9487 but we must turn off all bits turned off in the shift.
9489 If we were passed a value for X, see if we can use any pieces of
9490 it. If not, make new rtx. */
9492 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9493 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9494 && INTVAL (XEXP (x
, 1)) == count
)
9495 const_rtx
= XEXP (x
, 1);
9497 const_rtx
= GEN_INT (count
);
9499 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9500 && GET_MODE (XEXP (x
, 0)) == shift_mode
9501 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9502 varop
= XEXP (x
, 0);
9503 else if (GET_MODE (varop
) != shift_mode
)
9504 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9506 /* If we can't make the SUBREG, try to return what we were given. */
9507 if (GET_CODE (varop
) == CLOBBER
)
9508 return x
? x
: varop
;
9510 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9515 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9516 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9518 SUBST (XEXP (x
, 0), varop
);
9519 SUBST (XEXP (x
, 1), const_rtx
);
9522 /* If we have an outer operation and we just made a shift, it is
9523 possible that we could have simplified the shift were it not
9524 for the outer operation. So try to do the simplification
9527 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9528 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9529 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9530 INTVAL (XEXP (x
, 1)));
9532 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9533 turn off all the bits that the shift would have turned off. */
9534 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9535 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9536 GET_MODE_MASK (result_mode
) >> orig_count
);
9538 /* Do the remainder of the processing in RESULT_MODE. */
9539 x
= gen_lowpart_for_combine (result_mode
, x
);
9541 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9544 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9546 if (outer_op
!= NIL
)
9548 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9549 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9551 if (outer_op
== AND
)
9552 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9553 else if (outer_op
== SET
)
9554 /* This means that we have determined that the result is
9555 equivalent to a constant. This should be rare. */
9556 x
= GEN_INT (outer_const
);
9557 else if (GET_RTX_CLASS (outer_op
) == '1')
9558 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9560 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9566 /* Like recog, but we receive the address of a pointer to a new pattern.
9567 We try to match the rtx that the pointer points to.
9568 If that fails, we may try to modify or replace the pattern,
9569 storing the replacement into the same pointer object.
9571 Modifications include deletion or addition of CLOBBERs.
9573 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9574 the CLOBBERs are placed.
9576 The value is the final insn code from the pattern ultimately matched,
9580 recog_for_combine (pnewpat
, insn
, pnotes
)
9585 register rtx pat
= *pnewpat
;
9586 int insn_code_number
;
9587 int num_clobbers_to_add
= 0;
9592 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9593 we use to indicate that something didn't match. If we find such a
9594 thing, force rejection. */
9595 if (GET_CODE (pat
) == PARALLEL
)
9596 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9597 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9598 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9601 /* Remove the old notes prior to trying to recognize the new pattern. */
9602 old_notes
= REG_NOTES (insn
);
9603 REG_NOTES (insn
) = 0;
9605 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9607 /* If it isn't, there is the possibility that we previously had an insn
9608 that clobbered some register as a side effect, but the combined
9609 insn doesn't need to do that. So try once more without the clobbers
9610 unless this represents an ASM insn. */
9612 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9613 && GET_CODE (pat
) == PARALLEL
)
9617 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9618 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9621 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9625 SUBST_INT (XVECLEN (pat
, 0), pos
);
9628 pat
= XVECEXP (pat
, 0, 0);
9630 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9633 /* Recognize all noop sets, these will be killed by followup pass. */
9634 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9635 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9637 REG_NOTES (insn
) = old_notes
;
9639 /* If we had any clobbers to add, make a new pattern than contains
9640 them. Then check to make sure that all of them are dead. */
9641 if (num_clobbers_to_add
)
9643 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9644 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9646 + num_clobbers_to_add
)
9647 : num_clobbers_to_add
+ 1));
9649 if (GET_CODE (pat
) == PARALLEL
)
9650 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9651 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9653 XVECEXP (newpat
, 0, 0) = pat
;
9655 add_clobbers (newpat
, insn_code_number
);
9657 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9658 i
< XVECLEN (newpat
, 0); i
++)
9660 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9661 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9663 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9664 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9672 return insn_code_number
;
9675 /* Like gen_lowpart but for use by combine. In combine it is not possible
9676 to create any new pseudoregs. However, it is safe to create
9677 invalid memory addresses, because combine will try to recognize
9678 them and all they will do is make the combine attempt fail.
9680 If for some reason this cannot do its job, an rtx
9681 (clobber (const_int 0)) is returned.
9682 An insn containing that will not be recognized. */
9687 gen_lowpart_for_combine (mode
, x
)
9688 enum machine_mode mode
;
9693 if (GET_MODE (x
) == mode
)
9696 /* We can only support MODE being wider than a word if X is a
9697 constant integer or has a mode the same size. */
9699 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9700 && ! ((GET_MODE (x
) == VOIDmode
9701 && (GET_CODE (x
) == CONST_INT
9702 || GET_CODE (x
) == CONST_DOUBLE
))
9703 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9704 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9706 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9707 won't know what to do. So we will strip off the SUBREG here and
9708 process normally. */
9709 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9712 if (GET_MODE (x
) == mode
)
9716 result
= gen_lowpart_common (mode
, x
);
9717 #ifdef CLASS_CANNOT_CHANGE_MODE
9719 && GET_CODE (result
) == SUBREG
9720 && GET_CODE (SUBREG_REG (result
)) == REG
9721 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9722 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9723 GET_MODE (SUBREG_REG (result
))))
9724 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9730 if (GET_CODE (x
) == MEM
)
9732 register int offset
= 0;
9734 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9736 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9737 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9739 /* If we want to refer to something bigger than the original memref,
9740 generate a perverse subreg instead. That will force a reload
9741 of the original memref X. */
9742 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9743 return gen_rtx_SUBREG (mode
, x
, 0);
9745 if (WORDS_BIG_ENDIAN
)
9746 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9747 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9749 if (BYTES_BIG_ENDIAN
)
9751 /* Adjust the address so that the address-after-the-data is
9753 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9754 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9757 return adjust_address_nv (x
, mode
, offset
);
9760 /* If X is a comparison operator, rewrite it in a new mode. This
9761 probably won't match, but may allow further simplifications. */
9762 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9763 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9765 /* If we couldn't simplify X any other way, just enclose it in a
9766 SUBREG. Normally, this SUBREG won't match, but some patterns may
9767 include an explicit SUBREG or we may simplify it further in combine. */
9773 offset
= subreg_lowpart_offset (mode
, GET_MODE (x
));
9774 res
= simplify_gen_subreg (mode
, x
, GET_MODE (x
), offset
);
9777 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9781 /* These routines make binary and unary operations by first seeing if they
9782 fold; if not, a new expression is allocated. */
9785 gen_binary (code
, mode
, op0
, op1
)
9787 enum machine_mode mode
;
9793 if (GET_RTX_CLASS (code
) == 'c'
9794 && swap_commutative_operands_p (op0
, op1
))
9795 tem
= op0
, op0
= op1
, op1
= tem
;
9797 if (GET_RTX_CLASS (code
) == '<')
9799 enum machine_mode op_mode
= GET_MODE (op0
);
9801 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9802 just (REL_OP X Y). */
9803 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9805 op1
= XEXP (op0
, 1);
9806 op0
= XEXP (op0
, 0);
9807 op_mode
= GET_MODE (op0
);
9810 if (op_mode
== VOIDmode
)
9811 op_mode
= GET_MODE (op1
);
9812 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9815 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9820 /* Put complex operands first and constants second. */
9821 if (GET_RTX_CLASS (code
) == 'c'
9822 && swap_commutative_operands_p (op0
, op1
))
9823 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9825 /* If we are turning off bits already known off in OP0, we need not do
9827 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9828 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9829 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9832 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9835 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9836 comparison code that will be tested.
9838 The result is a possibly different comparison code to use. *POP0 and
9839 *POP1 may be updated.
9841 It is possible that we might detect that a comparison is either always
9842 true or always false. However, we do not perform general constant
9843 folding in combine, so this knowledge isn't useful. Such tautologies
9844 should have been detected earlier. Hence we ignore all such cases. */
9846 static enum rtx_code
9847 simplify_comparison (code
, pop0
, pop1
)
9856 enum machine_mode mode
, tmode
;
9858 /* Try a few ways of applying the same transformation to both operands. */
9861 #ifndef WORD_REGISTER_OPERATIONS
9862 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9863 so check specially. */
9864 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9865 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9866 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9867 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9868 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9869 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9870 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9871 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9872 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9873 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9874 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9875 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9876 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9877 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9878 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9879 && (INTVAL (XEXP (op0
, 1))
9880 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9882 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9884 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9885 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9889 /* If both operands are the same constant shift, see if we can ignore the
9890 shift. We can if the shift is a rotate or if the bits shifted out of
9891 this shift are known to be zero for both inputs and if the type of
9892 comparison is compatible with the shift. */
9893 if (GET_CODE (op0
) == GET_CODE (op1
)
9894 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9895 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9896 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9897 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9898 || (GET_CODE (op0
) == ASHIFTRT
9899 && (code
!= GTU
&& code
!= LTU
9900 && code
!= GEU
&& code
!= LEU
)))
9901 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9902 && INTVAL (XEXP (op0
, 1)) >= 0
9903 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9904 && XEXP (op0
, 1) == XEXP (op1
, 1))
9906 enum machine_mode mode
= GET_MODE (op0
);
9907 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9908 int shift_count
= INTVAL (XEXP (op0
, 1));
9910 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9911 mask
&= (mask
>> shift_count
) << shift_count
;
9912 else if (GET_CODE (op0
) == ASHIFT
)
9913 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9915 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9916 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9917 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9922 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9923 SUBREGs are of the same mode, and, in both cases, the AND would
9924 be redundant if the comparison was done in the narrower mode,
9925 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9926 and the operand's possibly nonzero bits are 0xffffff01; in that case
9927 if we only care about QImode, we don't need the AND). This case
9928 occurs if the output mode of an scc insn is not SImode and
9929 STORE_FLAG_VALUE == 1 (e.g., the 386).
9931 Similarly, check for a case where the AND's are ZERO_EXTEND
9932 operations from some narrower mode even though a SUBREG is not
9935 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9936 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9937 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9939 rtx inner_op0
= XEXP (op0
, 0);
9940 rtx inner_op1
= XEXP (op1
, 0);
9941 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9942 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9945 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9946 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9947 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9948 && (GET_MODE (SUBREG_REG (inner_op0
))
9949 == GET_MODE (SUBREG_REG (inner_op1
)))
9950 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9951 <= HOST_BITS_PER_WIDE_INT
)
9952 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9953 GET_MODE (SUBREG_REG (inner_op0
)))))
9954 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9955 GET_MODE (SUBREG_REG (inner_op1
))))))
9957 op0
= SUBREG_REG (inner_op0
);
9958 op1
= SUBREG_REG (inner_op1
);
9960 /* The resulting comparison is always unsigned since we masked
9961 off the original sign bit. */
9962 code
= unsigned_condition (code
);
9968 for (tmode
= GET_CLASS_NARROWEST_MODE
9969 (GET_MODE_CLASS (GET_MODE (op0
)));
9970 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9971 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9973 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9974 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9975 code
= unsigned_condition (code
);
9984 /* If both operands are NOT, we can strip off the outer operation
9985 and adjust the comparison code for swapped operands; similarly for
9986 NEG, except that this must be an equality comparison. */
9987 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9988 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9989 && (code
== EQ
|| code
== NE
)))
9990 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9996 /* If the first operand is a constant, swap the operands and adjust the
9997 comparison code appropriately, but don't do this if the second operand
9998 is already a constant integer. */
9999 if (swap_commutative_operands_p (op0
, op1
))
10001 tem
= op0
, op0
= op1
, op1
= tem
;
10002 code
= swap_condition (code
);
10005 /* We now enter a loop during which we will try to simplify the comparison.
10006 For the most part, we only are concerned with comparisons with zero,
10007 but some things may really be comparisons with zero but not start
10008 out looking that way. */
10010 while (GET_CODE (op1
) == CONST_INT
)
10012 enum machine_mode mode
= GET_MODE (op0
);
10013 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10014 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10015 int equality_comparison_p
;
10016 int sign_bit_comparison_p
;
10017 int unsigned_comparison_p
;
10018 HOST_WIDE_INT const_op
;
10020 /* We only want to handle integral modes. This catches VOIDmode,
10021 CCmode, and the floating-point modes. An exception is that we
10022 can handle VOIDmode if OP0 is a COMPARE or a comparison
10025 if (GET_MODE_CLASS (mode
) != MODE_INT
10026 && ! (mode
== VOIDmode
10027 && (GET_CODE (op0
) == COMPARE
10028 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10031 /* Get the constant we are comparing against and turn off all bits
10032 not on in our mode. */
10033 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10034 op1
= GEN_INT (const_op
);
10036 /* If we are comparing against a constant power of two and the value
10037 being compared can only have that single bit nonzero (e.g., it was
10038 `and'ed with that bit), we can replace this with a comparison
10041 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10042 || code
== LT
|| code
== LTU
)
10043 && mode_width
<= HOST_BITS_PER_WIDE_INT
10044 && exact_log2 (const_op
) >= 0
10045 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10047 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10048 op1
= const0_rtx
, const_op
= 0;
10051 /* Similarly, if we are comparing a value known to be either -1 or
10052 0 with -1, change it to the opposite comparison against zero. */
10055 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10056 || code
== GEU
|| code
== LTU
)
10057 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10059 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10060 op1
= const0_rtx
, const_op
= 0;
10063 /* Do some canonicalizations based on the comparison code. We prefer
10064 comparisons against zero and then prefer equality comparisons.
10065 If we can reduce the size of a constant, we will do that too. */
10070 /* < C is equivalent to <= (C - 1) */
10074 op1
= GEN_INT (const_op
);
10076 /* ... fall through to LE case below. */
10082 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10086 op1
= GEN_INT (const_op
);
10090 /* If we are doing a <= 0 comparison on a value known to have
10091 a zero sign bit, we can replace this with == 0. */
10092 else if (const_op
== 0
10093 && mode_width
<= HOST_BITS_PER_WIDE_INT
10094 && (nonzero_bits (op0
, mode
)
10095 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10100 /* >= C is equivalent to > (C - 1). */
10104 op1
= GEN_INT (const_op
);
10106 /* ... fall through to GT below. */
10112 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10116 op1
= GEN_INT (const_op
);
10120 /* If we are doing a > 0 comparison on a value known to have
10121 a zero sign bit, we can replace this with != 0. */
10122 else if (const_op
== 0
10123 && mode_width
<= HOST_BITS_PER_WIDE_INT
10124 && (nonzero_bits (op0
, mode
)
10125 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10130 /* < C is equivalent to <= (C - 1). */
10134 op1
= GEN_INT (const_op
);
10136 /* ... fall through ... */
10139 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10140 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10141 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10143 const_op
= 0, op1
= const0_rtx
;
10151 /* unsigned <= 0 is equivalent to == 0 */
10155 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10156 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10157 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10159 const_op
= 0, op1
= const0_rtx
;
10165 /* >= C is equivalent to < (C - 1). */
10169 op1
= GEN_INT (const_op
);
10171 /* ... fall through ... */
10174 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10175 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10176 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10178 const_op
= 0, op1
= const0_rtx
;
10186 /* unsigned > 0 is equivalent to != 0 */
10190 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10191 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10192 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10194 const_op
= 0, op1
= const0_rtx
;
10203 /* Compute some predicates to simplify code below. */
10205 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10206 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10207 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10210 /* If this is a sign bit comparison and we can do arithmetic in
10211 MODE, say that we will only be needing the sign bit of OP0. */
10212 if (sign_bit_comparison_p
10213 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10214 op0
= force_to_mode (op0
, mode
,
10216 << (GET_MODE_BITSIZE (mode
) - 1)),
10219 /* Now try cases based on the opcode of OP0. If none of the cases
10220 does a "continue", we exit this loop immediately after the
10223 switch (GET_CODE (op0
))
10226 /* If we are extracting a single bit from a variable position in
10227 a constant that has only a single bit set and are comparing it
10228 with zero, we can convert this into an equality comparison
10229 between the position and the location of the single bit. */
10231 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10232 && XEXP (op0
, 1) == const1_rtx
10233 && equality_comparison_p
&& const_op
== 0
10234 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10236 if (BITS_BIG_ENDIAN
)
10239 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10240 if (mode
== VOIDmode
)
10242 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10244 i
= BITS_PER_WORD
- 1 - i
;
10248 op0
= XEXP (op0
, 2);
10252 /* Result is nonzero iff shift count is equal to I. */
10253 code
= reverse_condition (code
);
10257 /* ... fall through ... */
10260 tem
= expand_compound_operation (op0
);
10269 /* If testing for equality, we can take the NOT of the constant. */
10270 if (equality_comparison_p
10271 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10273 op0
= XEXP (op0
, 0);
10278 /* If just looking at the sign bit, reverse the sense of the
10280 if (sign_bit_comparison_p
)
10282 op0
= XEXP (op0
, 0);
10283 code
= (code
== GE
? LT
: GE
);
10289 /* If testing for equality, we can take the NEG of the constant. */
10290 if (equality_comparison_p
10291 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10293 op0
= XEXP (op0
, 0);
10298 /* The remaining cases only apply to comparisons with zero. */
10302 /* When X is ABS or is known positive,
10303 (neg X) is < 0 if and only if X != 0. */
10305 if (sign_bit_comparison_p
10306 && (GET_CODE (XEXP (op0
, 0)) == ABS
10307 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10308 && (nonzero_bits (XEXP (op0
, 0), mode
)
10309 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10311 op0
= XEXP (op0
, 0);
10312 code
= (code
== LT
? NE
: EQ
);
10316 /* If we have NEG of something whose two high-order bits are the
10317 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10318 if (num_sign_bit_copies (op0
, mode
) >= 2)
10320 op0
= XEXP (op0
, 0);
10321 code
= swap_condition (code
);
10327 /* If we are testing equality and our count is a constant, we
10328 can perform the inverse operation on our RHS. */
10329 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10330 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10331 op1
, XEXP (op0
, 1))) != 0)
10333 op0
= XEXP (op0
, 0);
10338 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10339 a particular bit. Convert it to an AND of a constant of that
10340 bit. This will be converted into a ZERO_EXTRACT. */
10341 if (const_op
== 0 && sign_bit_comparison_p
10342 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10343 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10345 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10348 - INTVAL (XEXP (op0
, 1)))));
10349 code
= (code
== LT
? NE
: EQ
);
10353 /* Fall through. */
10356 /* ABS is ignorable inside an equality comparison with zero. */
10357 if (const_op
== 0 && equality_comparison_p
)
10359 op0
= XEXP (op0
, 0);
10365 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10366 to (compare FOO CONST) if CONST fits in FOO's mode and we
10367 are either testing inequality or have an unsigned comparison
10368 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10369 if (! unsigned_comparison_p
10370 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10371 <= HOST_BITS_PER_WIDE_INT
)
10372 && ((unsigned HOST_WIDE_INT
) const_op
10373 < (((unsigned HOST_WIDE_INT
) 1
10374 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10376 op0
= XEXP (op0
, 0);
10382 /* Check for the case where we are comparing A - C1 with C2,
10383 both constants are smaller than 1/2 the maximum positive
10384 value in MODE, and the comparison is equality or unsigned.
10385 In that case, if A is either zero-extended to MODE or has
10386 sufficient sign bits so that the high-order bit in MODE
10387 is a copy of the sign in the inner mode, we can prove that it is
10388 safe to do the operation in the wider mode. This simplifies
10389 many range checks. */
10391 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10392 && subreg_lowpart_p (op0
)
10393 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10394 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10395 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10396 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10397 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10398 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10399 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10400 GET_MODE (SUBREG_REG (op0
)))
10401 & ~GET_MODE_MASK (mode
))
10402 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10403 GET_MODE (SUBREG_REG (op0
)))
10404 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10405 - GET_MODE_BITSIZE (mode
)))))
10407 op0
= SUBREG_REG (op0
);
10411 /* If the inner mode is narrower and we are extracting the low part,
10412 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10413 if (subreg_lowpart_p (op0
)
10414 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10415 /* Fall through */ ;
10419 /* ... fall through ... */
10422 if ((unsigned_comparison_p
|| equality_comparison_p
)
10423 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10424 <= HOST_BITS_PER_WIDE_INT
)
10425 && ((unsigned HOST_WIDE_INT
) const_op
10426 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10428 op0
= XEXP (op0
, 0);
10434 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10435 this for equality comparisons due to pathological cases involving
10437 if (equality_comparison_p
10438 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10439 op1
, XEXP (op0
, 1))))
10441 op0
= XEXP (op0
, 0);
10446 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10447 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10448 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10450 op0
= XEXP (XEXP (op0
, 0), 0);
10451 code
= (code
== LT
? EQ
: NE
);
10457 /* We used to optimize signed comparisons against zero, but that
10458 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10459 arrive here as equality comparisons, or (GEU, LTU) are
10460 optimized away. No need to special-case them. */
10462 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10463 (eq B (minus A C)), whichever simplifies. We can only do
10464 this for equality comparisons due to pathological cases involving
10466 if (equality_comparison_p
10467 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10468 XEXP (op0
, 1), op1
)))
10470 op0
= XEXP (op0
, 0);
10475 if (equality_comparison_p
10476 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10477 XEXP (op0
, 0), op1
)))
10479 op0
= XEXP (op0
, 1);
10484 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10485 of bits in X minus 1, is one iff X > 0. */
10486 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10487 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10488 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10489 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10491 op0
= XEXP (op0
, 1);
10492 code
= (code
== GE
? LE
: GT
);
10498 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10499 if C is zero or B is a constant. */
10500 if (equality_comparison_p
10501 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10502 XEXP (op0
, 1), op1
)))
10504 op0
= XEXP (op0
, 0);
10511 case UNEQ
: case LTGT
:
10512 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10513 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10514 case UNORDERED
: case ORDERED
:
10515 /* We can't do anything if OP0 is a condition code value, rather
10516 than an actual data value. */
10519 || XEXP (op0
, 0) == cc0_rtx
10521 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10524 /* Get the two operands being compared. */
10525 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10526 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10528 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10530 /* Check for the cases where we simply want the result of the
10531 earlier test or the opposite of that result. */
10532 if (code
== NE
|| code
== EQ
10533 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10534 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10535 && (STORE_FLAG_VALUE
10536 & (((HOST_WIDE_INT
) 1
10537 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10538 && (code
== LT
|| code
== GE
)))
10540 enum rtx_code new_code
;
10541 if (code
== LT
|| code
== NE
)
10542 new_code
= GET_CODE (op0
);
10544 new_code
= combine_reversed_comparison_code (op0
);
10546 if (new_code
!= UNKNOWN
)
10557 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10559 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10560 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10561 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10563 op0
= XEXP (op0
, 1);
10564 code
= (code
== GE
? GT
: LE
);
10570 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10571 will be converted to a ZERO_EXTRACT later. */
10572 if (const_op
== 0 && equality_comparison_p
10573 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10574 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10576 op0
= simplify_and_const_int
10577 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10579 XEXP (XEXP (op0
, 0), 1)),
10580 (HOST_WIDE_INT
) 1);
10584 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10585 zero and X is a comparison and C1 and C2 describe only bits set
10586 in STORE_FLAG_VALUE, we can compare with X. */
10587 if (const_op
== 0 && equality_comparison_p
10588 && mode_width
<= HOST_BITS_PER_WIDE_INT
10589 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10590 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10591 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10592 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10593 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10595 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10596 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10597 if ((~STORE_FLAG_VALUE
& mask
) == 0
10598 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10599 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10600 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10602 op0
= XEXP (XEXP (op0
, 0), 0);
10607 /* If we are doing an equality comparison of an AND of a bit equal
10608 to the sign bit, replace this with a LT or GE comparison of
10609 the underlying value. */
10610 if (equality_comparison_p
10612 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10613 && mode_width
<= HOST_BITS_PER_WIDE_INT
10614 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10615 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10617 op0
= XEXP (op0
, 0);
10618 code
= (code
== EQ
? GE
: LT
);
10622 /* If this AND operation is really a ZERO_EXTEND from a narrower
10623 mode, the constant fits within that mode, and this is either an
10624 equality or unsigned comparison, try to do this comparison in
10625 the narrower mode. */
10626 if ((equality_comparison_p
|| unsigned_comparison_p
)
10627 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10628 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10629 & GET_MODE_MASK (mode
))
10631 && const_op
>> i
== 0
10632 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10634 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10638 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10639 in both M1 and M2 and the SUBREG is either paradoxical or
10640 represents the low part, permute the SUBREG and the AND and
10642 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10644 #ifdef WORD_REGISTER_OPERATIONS
10646 > (GET_MODE_BITSIZE
10647 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10648 && mode_width
<= BITS_PER_WORD
)
10651 <= (GET_MODE_BITSIZE
10652 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10653 && subreg_lowpart_p (XEXP (op0
, 0))))
10654 #ifndef WORD_REGISTER_OPERATIONS
10655 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10656 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10657 As originally written the upper bits have a defined value
10658 due to the AND operation. However, if we commute the AND
10659 inside the SUBREG then they no longer have defined values
10660 and the meaning of the code has been changed. */
10661 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10662 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10664 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10665 && mode_width
<= HOST_BITS_PER_WIDE_INT
10666 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10667 <= HOST_BITS_PER_WIDE_INT
)
10668 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10669 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10670 & INTVAL (XEXP (op0
, 1)))
10671 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10672 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10673 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10677 = gen_lowpart_for_combine
10679 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10680 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10684 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10685 (eq (and (lshiftrt X) 1) 0). */
10686 if (const_op
== 0 && equality_comparison_p
10687 && XEXP (op0
, 1) == const1_rtx
10688 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10689 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10691 op0
= simplify_and_const_int
10693 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10694 XEXP (XEXP (op0
, 0), 1)),
10695 (HOST_WIDE_INT
) 1);
10696 code
= (code
== NE
? EQ
: NE
);
10702 /* If we have (compare (ashift FOO N) (const_int C)) and
10703 the high order N bits of FOO (N+1 if an inequality comparison)
10704 are known to be zero, we can do this by comparing FOO with C
10705 shifted right N bits so long as the low-order N bits of C are
10707 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10708 && INTVAL (XEXP (op0
, 1)) >= 0
10709 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10710 < HOST_BITS_PER_WIDE_INT
)
10712 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10713 && mode_width
<= HOST_BITS_PER_WIDE_INT
10714 && (nonzero_bits (XEXP (op0
, 0), mode
)
10715 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10716 + ! equality_comparison_p
))) == 0)
10718 /* We must perform a logical shift, not an arithmetic one,
10719 as we want the top N bits of C to be zero. */
10720 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10722 temp
>>= INTVAL (XEXP (op0
, 1));
10723 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10724 op0
= XEXP (op0
, 0);
10728 /* If we are doing a sign bit comparison, it means we are testing
10729 a particular bit. Convert it to the appropriate AND. */
10730 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10731 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10733 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10736 - INTVAL (XEXP (op0
, 1)))));
10737 code
= (code
== LT
? NE
: EQ
);
10741 /* If this an equality comparison with zero and we are shifting
10742 the low bit to the sign bit, we can convert this to an AND of the
10744 if (const_op
== 0 && equality_comparison_p
10745 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10746 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10748 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10749 (HOST_WIDE_INT
) 1);
10755 /* If this is an equality comparison with zero, we can do this
10756 as a logical shift, which might be much simpler. */
10757 if (equality_comparison_p
&& const_op
== 0
10758 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10760 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10762 INTVAL (XEXP (op0
, 1)));
10766 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10767 do the comparison in a narrower mode. */
10768 if (! unsigned_comparison_p
10769 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10770 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10771 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10772 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10773 MODE_INT
, 1)) != BLKmode
10774 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10775 || ((unsigned HOST_WIDE_INT
) -const_op
10776 <= GET_MODE_MASK (tmode
))))
10778 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10782 /* Likewise if OP0 is a PLUS of a sign extension with a
10783 constant, which is usually represented with the PLUS
10784 between the shifts. */
10785 if (! unsigned_comparison_p
10786 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10787 && GET_CODE (XEXP (op0
, 0)) == PLUS
10788 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10789 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10790 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10791 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10792 MODE_INT
, 1)) != BLKmode
10793 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10794 || ((unsigned HOST_WIDE_INT
) -const_op
10795 <= GET_MODE_MASK (tmode
))))
10797 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10798 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10799 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10802 op0
= gen_binary (PLUS
, tmode
,
10803 gen_lowpart_for_combine (tmode
, inner
),
10808 /* ... fall through ... */
10810 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10811 the low order N bits of FOO are known to be zero, we can do this
10812 by comparing FOO with C shifted left N bits so long as no
10813 overflow occurs. */
10814 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10815 && INTVAL (XEXP (op0
, 1)) >= 0
10816 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10817 && mode_width
<= HOST_BITS_PER_WIDE_INT
10818 && (nonzero_bits (XEXP (op0
, 0), mode
)
10819 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10821 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10824 const_op
<<= INTVAL (XEXP (op0
, 1));
10825 op1
= GEN_INT (const_op
);
10826 op0
= XEXP (op0
, 0);
10830 /* If we are using this shift to extract just the sign bit, we
10831 can replace this with an LT or GE comparison. */
10833 && (equality_comparison_p
|| sign_bit_comparison_p
)
10834 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10835 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10837 op0
= XEXP (op0
, 0);
10838 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10850 /* Now make any compound operations involved in this comparison. Then,
10851 check for an outmost SUBREG on OP0 that is not doing anything or is
10852 paradoxical. The latter case can only occur when it is known that the
10853 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10854 We can never remove a SUBREG for a non-equality comparison because the
10855 sign bit is in a different place in the underlying object. */
10857 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10858 op1
= make_compound_operation (op1
, SET
);
10860 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10861 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10862 && (code
== NE
|| code
== EQ
)
10863 && ((GET_MODE_SIZE (GET_MODE (op0
))
10864 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10866 op0
= SUBREG_REG (op0
);
10867 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10870 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10871 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10872 && (code
== NE
|| code
== EQ
)
10873 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10874 <= HOST_BITS_PER_WIDE_INT
)
10875 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10876 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
10877 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10879 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10880 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
10881 op0
= SUBREG_REG (op0
), op1
= tem
;
10883 /* We now do the opposite procedure: Some machines don't have compare
10884 insns in all modes. If OP0's mode is an integer mode smaller than a
10885 word and we can't do a compare in that mode, see if there is a larger
10886 mode for which we can do the compare. There are a number of cases in
10887 which we can use the wider mode. */
10889 mode
= GET_MODE (op0
);
10890 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10891 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10892 && ! have_insn_for (COMPARE
, mode
))
10893 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10895 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10896 tmode
= GET_MODE_WIDER_MODE (tmode
))
10897 if (have_insn_for (COMPARE
, tmode
))
10899 /* If the only nonzero bits in OP0 and OP1 are those in the
10900 narrower mode and this is an equality or unsigned comparison,
10901 we can use the wider mode. Similarly for sign-extended
10902 values, in which case it is true for all comparisons. */
10903 if (((code
== EQ
|| code
== NE
10904 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10905 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
10906 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
10907 || ((num_sign_bit_copies (op0
, tmode
)
10908 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10909 && (num_sign_bit_copies (op1
, tmode
)
10910 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10912 /* If OP0 is an AND and we don't have an AND in MODE either,
10913 make a new AND in the proper mode. */
10914 if (GET_CODE (op0
) == AND
10915 && !have_insn_for (AND
, mode
))
10916 op0
= gen_binary (AND
, tmode
,
10917 gen_lowpart_for_combine (tmode
,
10919 gen_lowpart_for_combine (tmode
,
10922 op0
= gen_lowpart_for_combine (tmode
, op0
);
10923 op1
= gen_lowpart_for_combine (tmode
, op1
);
10927 /* If this is a test for negative, we can make an explicit
10928 test of the sign bit. */
10930 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10931 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10933 op0
= gen_binary (AND
, tmode
,
10934 gen_lowpart_for_combine (tmode
, op0
),
10935 GEN_INT ((HOST_WIDE_INT
) 1
10936 << (GET_MODE_BITSIZE (mode
) - 1)));
10937 code
= (code
== LT
) ? NE
: EQ
;
10942 #ifdef CANONICALIZE_COMPARISON
10943 /* If this machine only supports a subset of valid comparisons, see if we
10944 can convert an unsupported one into a supported one. */
10945 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10954 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10955 searching backward. */
10956 static enum rtx_code
10957 combine_reversed_comparison_code (exp
)
10960 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10963 if (code1
!= UNKNOWN
10964 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10966 /* Otherwise try and find where the condition codes were last set and
10968 x
= get_last_value (XEXP (exp
, 0));
10969 if (!x
|| GET_CODE (x
) != COMPARE
)
10971 return reversed_comparison_code_parts (GET_CODE (exp
),
10972 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10974 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10975 Return NULL_RTX in case we fail to do the reversal. */
10977 reversed_comparison (exp
, mode
, op0
, op1
)
10979 enum machine_mode mode
;
10981 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10982 if (reversed_code
== UNKNOWN
)
10985 return gen_binary (reversed_code
, mode
, op0
, op1
);
10988 /* Utility function for following routine. Called when X is part of a value
10989 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10990 for each register mentioned. Similar to mention_regs in cse.c */
10993 update_table_tick (x
)
10996 register enum rtx_code code
= GET_CODE (x
);
10997 register const char *fmt
= GET_RTX_FORMAT (code
);
11002 unsigned int regno
= REGNO (x
);
11003 unsigned int endregno
11004 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11005 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11008 for (r
= regno
; r
< endregno
; r
++)
11009 reg_last_set_table_tick
[r
] = label_tick
;
11014 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11015 /* Note that we can't have an "E" in values stored; see
11016 get_last_value_validate. */
11018 update_table_tick (XEXP (x
, i
));
11021 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11022 are saying that the register is clobbered and we no longer know its
11023 value. If INSN is zero, don't update reg_last_set; this is only permitted
11024 with VALUE also zero and is used to invalidate the register. */
11027 record_value_for_reg (reg
, insn
, value
)
11032 unsigned int regno
= REGNO (reg
);
11033 unsigned int endregno
11034 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11035 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11038 /* If VALUE contains REG and we have a previous value for REG, substitute
11039 the previous value. */
11040 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11044 /* Set things up so get_last_value is allowed to see anything set up to
11046 subst_low_cuid
= INSN_CUID (insn
);
11047 tem
= get_last_value (reg
);
11049 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11050 it isn't going to be useful and will take a lot of time to process,
11051 so just use the CLOBBER. */
11055 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11056 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11057 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11058 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11059 tem
= XEXP (tem
, 0);
11061 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11065 /* For each register modified, show we don't know its value, that
11066 we don't know about its bitwise content, that its value has been
11067 updated, and that we don't know the location of the death of the
11069 for (i
= regno
; i
< endregno
; i
++)
11072 reg_last_set
[i
] = insn
;
11074 reg_last_set_value
[i
] = 0;
11075 reg_last_set_mode
[i
] = 0;
11076 reg_last_set_nonzero_bits
[i
] = 0;
11077 reg_last_set_sign_bit_copies
[i
] = 0;
11078 reg_last_death
[i
] = 0;
11081 /* Mark registers that are being referenced in this value. */
11083 update_table_tick (value
);
11085 /* Now update the status of each register being set.
11086 If someone is using this register in this block, set this register
11087 to invalid since we will get confused between the two lives in this
11088 basic block. This makes using this register always invalid. In cse, we
11089 scan the table to invalidate all entries using this register, but this
11090 is too much work for us. */
11092 for (i
= regno
; i
< endregno
; i
++)
11094 reg_last_set_label
[i
] = label_tick
;
11095 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11096 reg_last_set_invalid
[i
] = 1;
11098 reg_last_set_invalid
[i
] = 0;
11101 /* The value being assigned might refer to X (like in "x++;"). In that
11102 case, we must replace it with (clobber (const_int 0)) to prevent
11104 if (value
&& ! get_last_value_validate (&value
, insn
,
11105 reg_last_set_label
[regno
], 0))
11107 value
= copy_rtx (value
);
11108 if (! get_last_value_validate (&value
, insn
,
11109 reg_last_set_label
[regno
], 1))
11113 /* For the main register being modified, update the value, the mode, the
11114 nonzero bits, and the number of sign bit copies. */
11116 reg_last_set_value
[regno
] = value
;
11120 subst_low_cuid
= INSN_CUID (insn
);
11121 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11122 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11123 reg_last_set_sign_bit_copies
[regno
]
11124 = num_sign_bit_copies (value
, GET_MODE (reg
));
11128 /* Called via note_stores from record_dead_and_set_regs to handle one
11129 SET or CLOBBER in an insn. DATA is the instruction in which the
11130 set is occurring. */
11133 record_dead_and_set_regs_1 (dest
, setter
, data
)
11137 rtx record_dead_insn
= (rtx
) data
;
11139 if (GET_CODE (dest
) == SUBREG
)
11140 dest
= SUBREG_REG (dest
);
11142 if (GET_CODE (dest
) == REG
)
11144 /* If we are setting the whole register, we know its value. Otherwise
11145 show that we don't know the value. We can handle SUBREG in
11147 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11148 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11149 else if (GET_CODE (setter
) == SET
11150 && GET_CODE (SET_DEST (setter
)) == SUBREG
11151 && SUBREG_REG (SET_DEST (setter
)) == dest
11152 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11153 && subreg_lowpart_p (SET_DEST (setter
)))
11154 record_value_for_reg (dest
, record_dead_insn
,
11155 gen_lowpart_for_combine (GET_MODE (dest
),
11156 SET_SRC (setter
)));
11158 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11160 else if (GET_CODE (dest
) == MEM
11161 /* Ignore pushes, they clobber nothing. */
11162 && ! push_operand (dest
, GET_MODE (dest
)))
11163 mem_last_set
= INSN_CUID (record_dead_insn
);
11166 /* Update the records of when each REG was most recently set or killed
11167 for the things done by INSN. This is the last thing done in processing
11168 INSN in the combiner loop.
11170 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11171 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11172 and also the similar information mem_last_set (which insn most recently
11173 modified memory) and last_call_cuid (which insn was the most recent
11174 subroutine call). */
11177 record_dead_and_set_regs (insn
)
11183 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11185 if (REG_NOTE_KIND (link
) == REG_DEAD
11186 && GET_CODE (XEXP (link
, 0)) == REG
)
11188 unsigned int regno
= REGNO (XEXP (link
, 0));
11189 unsigned int endregno
11190 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11191 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11194 for (i
= regno
; i
< endregno
; i
++)
11195 reg_last_death
[i
] = insn
;
11197 else if (REG_NOTE_KIND (link
) == REG_INC
)
11198 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11201 if (GET_CODE (insn
) == CALL_INSN
)
11203 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11204 if (call_used_regs
[i
])
11206 reg_last_set_value
[i
] = 0;
11207 reg_last_set_mode
[i
] = 0;
11208 reg_last_set_nonzero_bits
[i
] = 0;
11209 reg_last_set_sign_bit_copies
[i
] = 0;
11210 reg_last_death
[i
] = 0;
11213 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11216 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11219 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11220 register present in the SUBREG, so for each such SUBREG go back and
11221 adjust nonzero and sign bit information of the registers that are
11222 known to have some zero/sign bits set.
11224 This is needed because when combine blows the SUBREGs away, the
11225 information on zero/sign bits is lost and further combines can be
11226 missed because of that. */
11229 record_promoted_value (insn
, subreg
)
11234 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11235 enum machine_mode mode
= GET_MODE (subreg
);
11237 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11240 for (links
= LOG_LINKS (insn
); links
;)
11242 insn
= XEXP (links
, 0);
11243 set
= single_set (insn
);
11245 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11246 || REGNO (SET_DEST (set
)) != regno
11247 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11249 links
= XEXP (links
, 1);
11253 if (reg_last_set
[regno
] == insn
)
11255 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11256 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11259 if (GET_CODE (SET_SRC (set
)) == REG
)
11261 regno
= REGNO (SET_SRC (set
));
11262 links
= LOG_LINKS (insn
);
11269 /* Scan X for promoted SUBREGs. For each one found,
11270 note what it implies to the registers used in it. */
11273 check_promoted_subreg (insn
, x
)
11277 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11278 && GET_CODE (SUBREG_REG (x
)) == REG
)
11279 record_promoted_value (insn
, x
);
11282 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11285 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11289 check_promoted_subreg (insn
, XEXP (x
, i
));
11293 if (XVEC (x
, i
) != 0)
11294 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11295 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11301 /* Utility routine for the following function. Verify that all the registers
11302 mentioned in *LOC are valid when *LOC was part of a value set when
11303 label_tick == TICK. Return 0 if some are not.
11305 If REPLACE is non-zero, replace the invalid reference with
11306 (clobber (const_int 0)) and return 1. This replacement is useful because
11307 we often can get useful information about the form of a value (e.g., if
11308 it was produced by a shift that always produces -1 or 0) even though
11309 we don't know exactly what registers it was produced from. */
11312 get_last_value_validate (loc
, insn
, tick
, replace
)
11319 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11320 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11323 if (GET_CODE (x
) == REG
)
11325 unsigned int regno
= REGNO (x
);
11326 unsigned int endregno
11327 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11328 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11331 for (j
= regno
; j
< endregno
; j
++)
11332 if (reg_last_set_invalid
[j
]
11333 /* If this is a pseudo-register that was only set once and not
11334 live at the beginning of the function, it is always valid. */
11335 || (! (regno
>= FIRST_PSEUDO_REGISTER
11336 && REG_N_SETS (regno
) == 1
11337 && (! REGNO_REG_SET_P
11338 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11339 && reg_last_set_label
[j
] > tick
))
11342 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11348 /* If this is a memory reference, make sure that there were
11349 no stores after it that might have clobbered the value. We don't
11350 have alias info, so we assume any store invalidates it. */
11351 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11352 && INSN_CUID (insn
) <= mem_last_set
)
11355 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11359 for (i
= 0; i
< len
; i
++)
11361 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11362 /* Don't bother with these. They shouldn't occur anyway. */
11366 /* If we haven't found a reason for it to be invalid, it is valid. */
11370 /* Get the last value assigned to X, if known. Some registers
11371 in the value may be replaced with (clobber (const_int 0)) if their value
11372 is known longer known reliably. */
11378 unsigned int regno
;
11381 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11382 then convert it to the desired mode. If this is a paradoxical SUBREG,
11383 we cannot predict what values the "extra" bits might have. */
11384 if (GET_CODE (x
) == SUBREG
11385 && subreg_lowpart_p (x
)
11386 && (GET_MODE_SIZE (GET_MODE (x
))
11387 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11388 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11389 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11391 if (GET_CODE (x
) != REG
)
11395 value
= reg_last_set_value
[regno
];
11397 /* If we don't have a value, or if it isn't for this basic block and
11398 it's either a hard register, set more than once, or it's a live
11399 at the beginning of the function, return 0.
11401 Because if it's not live at the beginnning of the function then the reg
11402 is always set before being used (is never used without being set).
11403 And, if it's set only once, and it's always set before use, then all
11404 uses must have the same last value, even if it's not from this basic
11408 || (reg_last_set_label
[regno
] != label_tick
11409 && (regno
< FIRST_PSEUDO_REGISTER
11410 || REG_N_SETS (regno
) != 1
11411 || (REGNO_REG_SET_P
11412 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11415 /* If the value was set in a later insn than the ones we are processing,
11416 we can't use it even if the register was only set once. */
11417 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11420 /* If the value has all its registers valid, return it. */
11421 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11422 reg_last_set_label
[regno
], 0))
11425 /* Otherwise, make a copy and replace any invalid register with
11426 (clobber (const_int 0)). If that fails for some reason, return 0. */
11428 value
= copy_rtx (value
);
11429 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11430 reg_last_set_label
[regno
], 1))
11436 /* Return nonzero if expression X refers to a REG or to memory
11437 that is set in an instruction more recent than FROM_CUID. */
11440 use_crosses_set_p (x
, from_cuid
)
11444 register const char *fmt
;
11446 register enum rtx_code code
= GET_CODE (x
);
11450 unsigned int regno
= REGNO (x
);
11451 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11452 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11454 #ifdef PUSH_ROUNDING
11455 /* Don't allow uses of the stack pointer to be moved,
11456 because we don't know whether the move crosses a push insn. */
11457 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11460 for (; regno
< endreg
; regno
++)
11461 if (reg_last_set
[regno
]
11462 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11467 if (code
== MEM
&& mem_last_set
> from_cuid
)
11470 fmt
= GET_RTX_FORMAT (code
);
11472 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11477 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11478 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11481 else if (fmt
[i
] == 'e'
11482 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11488 /* Define three variables used for communication between the following
11491 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11492 static int reg_dead_flag
;
11494 /* Function called via note_stores from reg_dead_at_p.
11496 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11497 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11500 reg_dead_at_p_1 (dest
, x
, data
)
11503 void *data ATTRIBUTE_UNUSED
;
11505 unsigned int regno
, endregno
;
11507 if (GET_CODE (dest
) != REG
)
11510 regno
= REGNO (dest
);
11511 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11512 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11514 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11515 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11518 /* Return non-zero if REG is known to be dead at INSN.
11520 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11521 referencing REG, it is dead. If we hit a SET referencing REG, it is
11522 live. Otherwise, see if it is live or dead at the start of the basic
11523 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11524 must be assumed to be always live. */
11527 reg_dead_at_p (reg
, insn
)
11534 /* Set variables for reg_dead_at_p_1. */
11535 reg_dead_regno
= REGNO (reg
);
11536 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11537 ? HARD_REGNO_NREGS (reg_dead_regno
,
11543 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11544 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11546 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11547 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11551 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11552 beginning of function. */
11553 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11554 insn
= prev_nonnote_insn (insn
))
11556 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11558 return reg_dead_flag
== 1 ? 1 : 0;
11560 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11564 /* Get the basic block number that we were in. */
11569 for (block
= 0; block
< n_basic_blocks
; block
++)
11570 if (insn
== BLOCK_HEAD (block
))
11573 if (block
== n_basic_blocks
)
11577 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11578 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11584 /* Note hard registers in X that are used. This code is similar to
11585 that in flow.c, but much simpler since we don't care about pseudos. */
11588 mark_used_regs_combine (x
)
11591 RTX_CODE code
= GET_CODE (x
);
11592 unsigned int regno
;
11604 case ADDR_DIFF_VEC
:
11607 /* CC0 must die in the insn after it is set, so we don't need to take
11608 special note of it here. */
11614 /* If we are clobbering a MEM, mark any hard registers inside the
11615 address as used. */
11616 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11617 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11622 /* A hard reg in a wide mode may really be multiple registers.
11623 If so, mark all of them just like the first. */
11624 if (regno
< FIRST_PSEUDO_REGISTER
)
11626 unsigned int endregno
, r
;
11628 /* None of this applies to the stack, frame or arg pointers */
11629 if (regno
== STACK_POINTER_REGNUM
11630 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11631 || regno
== HARD_FRAME_POINTER_REGNUM
11633 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11634 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11636 || regno
== FRAME_POINTER_REGNUM
)
11639 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11640 for (r
= regno
; r
< endregno
; r
++)
11641 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11647 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11649 register rtx testreg
= SET_DEST (x
);
11651 while (GET_CODE (testreg
) == SUBREG
11652 || GET_CODE (testreg
) == ZERO_EXTRACT
11653 || GET_CODE (testreg
) == SIGN_EXTRACT
11654 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11655 testreg
= XEXP (testreg
, 0);
11657 if (GET_CODE (testreg
) == MEM
)
11658 mark_used_regs_combine (XEXP (testreg
, 0));
11660 mark_used_regs_combine (SET_SRC (x
));
11668 /* Recursively scan the operands of this expression. */
11671 register const char *fmt
= GET_RTX_FORMAT (code
);
11673 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11676 mark_used_regs_combine (XEXP (x
, i
));
11677 else if (fmt
[i
] == 'E')
11681 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11682 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11688 /* Remove register number REGNO from the dead registers list of INSN.
11690 Return the note used to record the death, if there was one. */
11693 remove_death (regno
, insn
)
11694 unsigned int regno
;
11697 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11701 REG_N_DEATHS (regno
)--;
11702 remove_note (insn
, note
);
11708 /* For each register (hardware or pseudo) used within expression X, if its
11709 death is in an instruction with cuid between FROM_CUID (inclusive) and
11710 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11711 list headed by PNOTES.
11713 That said, don't move registers killed by maybe_kill_insn.
11715 This is done when X is being merged by combination into TO_INSN. These
11716 notes will then be distributed as needed. */
11719 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11721 rtx maybe_kill_insn
;
11726 register const char *fmt
;
11727 register int len
, i
;
11728 register enum rtx_code code
= GET_CODE (x
);
11732 unsigned int regno
= REGNO (x
);
11733 register rtx where_dead
= reg_last_death
[regno
];
11734 register rtx before_dead
, after_dead
;
11736 /* Don't move the register if it gets killed in between from and to */
11737 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11738 && ! reg_referenced_p (x
, maybe_kill_insn
))
11741 /* WHERE_DEAD could be a USE insn made by combine, so first we
11742 make sure that we have insns with valid INSN_CUID values. */
11743 before_dead
= where_dead
;
11744 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11745 before_dead
= PREV_INSN (before_dead
);
11747 after_dead
= where_dead
;
11748 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11749 after_dead
= NEXT_INSN (after_dead
);
11751 if (before_dead
&& after_dead
11752 && INSN_CUID (before_dead
) >= from_cuid
11753 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11754 || (where_dead
!= after_dead
11755 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11757 rtx note
= remove_death (regno
, where_dead
);
11759 /* It is possible for the call above to return 0. This can occur
11760 when reg_last_death points to I2 or I1 that we combined with.
11761 In that case make a new note.
11763 We must also check for the case where X is a hard register
11764 and NOTE is a death note for a range of hard registers
11765 including X. In that case, we must put REG_DEAD notes for
11766 the remaining registers in place of NOTE. */
11768 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11769 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11770 > GET_MODE_SIZE (GET_MODE (x
))))
11772 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11773 unsigned int deadend
11774 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11775 GET_MODE (XEXP (note
, 0))));
11776 unsigned int ourend
11777 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11780 for (i
= deadregno
; i
< deadend
; i
++)
11781 if (i
< regno
|| i
>= ourend
)
11782 REG_NOTES (where_dead
)
11783 = gen_rtx_EXPR_LIST (REG_DEAD
,
11784 gen_rtx_REG (reg_raw_mode
[i
], i
),
11785 REG_NOTES (where_dead
));
11788 /* If we didn't find any note, or if we found a REG_DEAD note that
11789 covers only part of the given reg, and we have a multi-reg hard
11790 register, then to be safe we must check for REG_DEAD notes
11791 for each register other than the first. They could have
11792 their own REG_DEAD notes lying around. */
11793 else if ((note
== 0
11795 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11796 < GET_MODE_SIZE (GET_MODE (x
)))))
11797 && regno
< FIRST_PSEUDO_REGISTER
11798 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11800 unsigned int ourend
11801 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11802 unsigned int i
, offset
;
11806 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11810 for (i
= regno
+ offset
; i
< ourend
; i
++)
11811 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11812 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11815 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11817 XEXP (note
, 1) = *pnotes
;
11821 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11823 REG_N_DEATHS (regno
)++;
11829 else if (GET_CODE (x
) == SET
)
11831 rtx dest
= SET_DEST (x
);
11833 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11835 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11836 that accesses one word of a multi-word item, some
11837 piece of everything register in the expression is used by
11838 this insn, so remove any old death. */
11839 /* ??? So why do we test for equality of the sizes? */
11841 if (GET_CODE (dest
) == ZERO_EXTRACT
11842 || GET_CODE (dest
) == STRICT_LOW_PART
11843 || (GET_CODE (dest
) == SUBREG
11844 && (((GET_MODE_SIZE (GET_MODE (dest
))
11845 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11846 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11847 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11849 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11853 /* If this is some other SUBREG, we know it replaces the entire
11854 value, so use that as the destination. */
11855 if (GET_CODE (dest
) == SUBREG
)
11856 dest
= SUBREG_REG (dest
);
11858 /* If this is a MEM, adjust deaths of anything used in the address.
11859 For a REG (the only other possibility), the entire value is
11860 being replaced so the old value is not used in this insn. */
11862 if (GET_CODE (dest
) == MEM
)
11863 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11868 else if (GET_CODE (x
) == CLOBBER
)
11871 len
= GET_RTX_LENGTH (code
);
11872 fmt
= GET_RTX_FORMAT (code
);
11874 for (i
= 0; i
< len
; i
++)
11879 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11880 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11883 else if (fmt
[i
] == 'e')
11884 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11888 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11889 pattern of an insn. X must be a REG. */
11892 reg_bitfield_target_p (x
, body
)
11898 if (GET_CODE (body
) == SET
)
11900 rtx dest
= SET_DEST (body
);
11902 unsigned int regno
, tregno
, endregno
, endtregno
;
11904 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11905 target
= XEXP (dest
, 0);
11906 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11907 target
= SUBREG_REG (XEXP (dest
, 0));
11911 if (GET_CODE (target
) == SUBREG
)
11912 target
= SUBREG_REG (target
);
11914 if (GET_CODE (target
) != REG
)
11917 tregno
= REGNO (target
), regno
= REGNO (x
);
11918 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11919 return target
== x
;
11921 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11922 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11924 return endregno
> tregno
&& regno
< endtregno
;
11927 else if (GET_CODE (body
) == PARALLEL
)
11928 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11929 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11935 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11936 as appropriate. I3 and I2 are the insns resulting from the combination
11937 insns including FROM (I2 may be zero).
11939 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11940 not need REG_DEAD notes because they are being substituted for. This
11941 saves searching in the most common cases.
11943 Each note in the list is either ignored or placed on some insns, depending
11944 on the type of note. */
11947 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11951 rtx elim_i2
, elim_i1
;
11953 rtx note
, next_note
;
11956 for (note
= notes
; note
; note
= next_note
)
11958 rtx place
= 0, place2
= 0;
11960 /* If this NOTE references a pseudo register, ensure it references
11961 the latest copy of that register. */
11962 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11963 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11964 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11966 next_note
= XEXP (note
, 1);
11967 switch (REG_NOTE_KIND (note
))
11971 case REG_EXEC_COUNT
:
11972 /* Doesn't matter much where we put this, as long as it's somewhere.
11973 It is preferable to keep these notes on branches, which is most
11974 likely to be i3. */
11978 case REG_NON_LOCAL_GOTO
:
11979 if (GET_CODE (i3
) == JUMP_INSN
)
11981 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
11987 case REG_EH_REGION
:
11988 /* These notes must remain with the call or trapping instruction. */
11989 if (GET_CODE (i3
) == CALL_INSN
)
11991 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11993 else if (flag_non_call_exceptions
)
11995 if (may_trap_p (i3
))
11997 else if (i2
&& may_trap_p (i2
))
11999 /* ??? Otherwise assume we've combined things such that we
12000 can now prove that the instructions can't trap. Drop the
12001 note in this case. */
12009 /* These notes must remain with the call. It should not be
12010 possible for both I2 and I3 to be a call. */
12011 if (GET_CODE (i3
) == CALL_INSN
)
12013 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12020 /* Any clobbers for i3 may still exist, and so we must process
12021 REG_UNUSED notes from that insn.
12023 Any clobbers from i2 or i1 can only exist if they were added by
12024 recog_for_combine. In that case, recog_for_combine created the
12025 necessary REG_UNUSED notes. Trying to keep any original
12026 REG_UNUSED notes from these insns can cause incorrect output
12027 if it is for the same register as the original i3 dest.
12028 In that case, we will notice that the register is set in i3,
12029 and then add a REG_UNUSED note for the destination of i3, which
12030 is wrong. However, it is possible to have REG_UNUSED notes from
12031 i2 or i1 for register which were both used and clobbered, so
12032 we keep notes from i2 or i1 if they will turn into REG_DEAD
12035 /* If this register is set or clobbered in I3, put the note there
12036 unless there is one already. */
12037 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12039 if (from_insn
!= i3
)
12042 if (! (GET_CODE (XEXP (note
, 0)) == REG
12043 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12044 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12047 /* Otherwise, if this register is used by I3, then this register
12048 now dies here, so we must put a REG_DEAD note here unless there
12050 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12051 && ! (GET_CODE (XEXP (note
, 0)) == REG
12052 ? find_regno_note (i3
, REG_DEAD
,
12053 REGNO (XEXP (note
, 0)))
12054 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12056 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12064 /* These notes say something about results of an insn. We can
12065 only support them if they used to be on I3 in which case they
12066 remain on I3. Otherwise they are ignored.
12068 If the note refers to an expression that is not a constant, we
12069 must also ignore the note since we cannot tell whether the
12070 equivalence is still true. It might be possible to do
12071 slightly better than this (we only have a problem if I2DEST
12072 or I1DEST is present in the expression), but it doesn't
12073 seem worth the trouble. */
12075 if (from_insn
== i3
12076 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12081 case REG_NO_CONFLICT
:
12082 /* These notes say something about how a register is used. They must
12083 be present on any use of the register in I2 or I3. */
12084 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12087 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12097 /* This can show up in several ways -- either directly in the
12098 pattern, or hidden off in the constant pool with (or without?)
12099 a REG_EQUAL note. */
12100 /* ??? Ignore the without-reg_equal-note problem for now. */
12101 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12102 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12103 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12104 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12108 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12109 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12110 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12111 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12122 /* These notes say something about the value of a register prior
12123 to the execution of an insn. It is too much trouble to see
12124 if the note is still correct in all situations. It is better
12125 to simply delete it. */
12129 /* If the insn previously containing this note still exists,
12130 put it back where it was. Otherwise move it to the previous
12131 insn. Adjust the corresponding REG_LIBCALL note. */
12132 if (GET_CODE (from_insn
) != NOTE
)
12136 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12137 place
= prev_real_insn (from_insn
);
12139 XEXP (tem
, 0) = place
;
12140 /* If we're deleting the last remaining instruction of a
12141 libcall sequence, don't add the notes. */
12142 else if (XEXP (note
, 0) == from_insn
)
12148 /* This is handled similarly to REG_RETVAL. */
12149 if (GET_CODE (from_insn
) != NOTE
)
12153 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12154 place
= next_real_insn (from_insn
);
12156 XEXP (tem
, 0) = place
;
12157 /* If we're deleting the last remaining instruction of a
12158 libcall sequence, don't add the notes. */
12159 else if (XEXP (note
, 0) == from_insn
)
12165 /* If the register is used as an input in I3, it dies there.
12166 Similarly for I2, if it is non-zero and adjacent to I3.
12168 If the register is not used as an input in either I3 or I2
12169 and it is not one of the registers we were supposed to eliminate,
12170 there are two possibilities. We might have a non-adjacent I2
12171 or we might have somehow eliminated an additional register
12172 from a computation. For example, we might have had A & B where
12173 we discover that B will always be zero. In this case we will
12174 eliminate the reference to A.
12176 In both cases, we must search to see if we can find a previous
12177 use of A and put the death note there. */
12180 && GET_CODE (from_insn
) == CALL_INSN
12181 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12183 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12185 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12186 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12189 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12190 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12195 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12197 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12199 if (! INSN_P (tem
))
12201 if (tem
== bb
->head
)
12206 /* If the register is being set at TEM, see if that is all
12207 TEM is doing. If so, delete TEM. Otherwise, make this
12208 into a REG_UNUSED note instead. */
12209 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12211 rtx set
= single_set (tem
);
12212 rtx inner_dest
= 0;
12214 rtx cc0_setter
= NULL_RTX
;
12218 for (inner_dest
= SET_DEST (set
);
12219 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12220 || GET_CODE (inner_dest
) == SUBREG
12221 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12222 inner_dest
= XEXP (inner_dest
, 0))
12225 /* Verify that it was the set, and not a clobber that
12226 modified the register.
12228 CC0 targets must be careful to maintain setter/user
12229 pairs. If we cannot delete the setter due to side
12230 effects, mark the user with an UNUSED note instead
12233 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12234 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12236 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12237 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12238 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12242 /* Move the notes and links of TEM elsewhere.
12243 This might delete other dead insns recursively.
12244 First set the pattern to something that won't use
12247 PATTERN (tem
) = pc_rtx
;
12249 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12250 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12251 distribute_links (LOG_LINKS (tem
));
12253 PUT_CODE (tem
, NOTE
);
12254 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12255 NOTE_SOURCE_FILE (tem
) = 0;
12258 /* Delete the setter too. */
12261 PATTERN (cc0_setter
) = pc_rtx
;
12263 distribute_notes (REG_NOTES (cc0_setter
),
12264 cc0_setter
, cc0_setter
,
12265 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12266 distribute_links (LOG_LINKS (cc0_setter
));
12268 PUT_CODE (cc0_setter
, NOTE
);
12269 NOTE_LINE_NUMBER (cc0_setter
)
12270 = NOTE_INSN_DELETED
;
12271 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12275 /* If the register is both set and used here, put the
12276 REG_DEAD note here, but place a REG_UNUSED note
12277 here too unless there already is one. */
12278 else if (reg_referenced_p (XEXP (note
, 0),
12283 if (! find_regno_note (tem
, REG_UNUSED
,
12284 REGNO (XEXP (note
, 0))))
12286 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12291 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12293 /* If there isn't already a REG_UNUSED note, put one
12295 if (! find_regno_note (tem
, REG_UNUSED
,
12296 REGNO (XEXP (note
, 0))))
12301 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12302 || (GET_CODE (tem
) == CALL_INSN
12303 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12307 /* If we are doing a 3->2 combination, and we have a
12308 register which formerly died in i3 and was not used
12309 by i2, which now no longer dies in i3 and is used in
12310 i2 but does not die in i2, and place is between i2
12311 and i3, then we may need to move a link from place to
12313 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12314 && INSN_CUID (place
) > INSN_CUID (i2
)
12316 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12317 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12319 rtx links
= LOG_LINKS (place
);
12320 LOG_LINKS (place
) = 0;
12321 distribute_links (links
);
12326 if (tem
== bb
->head
)
12330 /* We haven't found an insn for the death note and it
12331 is still a REG_DEAD note, but we have hit the beginning
12332 of the block. If the existing life info says the reg
12333 was dead, there's nothing left to do. Otherwise, we'll
12334 need to do a global life update after combine. */
12335 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12336 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12337 REGNO (XEXP (note
, 0))))
12339 SET_BIT (refresh_blocks
, this_basic_block
);
12344 /* If the register is set or already dead at PLACE, we needn't do
12345 anything with this note if it is still a REG_DEAD note.
12346 We can here if it is set at all, not if is it totally replace,
12347 which is what `dead_or_set_p' checks, so also check for it being
12350 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12352 unsigned int regno
= REGNO (XEXP (note
, 0));
12354 /* Similarly, if the instruction on which we want to place
12355 the note is a noop, we'll need do a global live update
12356 after we remove them in delete_noop_moves. */
12357 if (noop_move_p (place
))
12359 SET_BIT (refresh_blocks
, this_basic_block
);
12363 if (dead_or_set_p (place
, XEXP (note
, 0))
12364 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12366 /* Unless the register previously died in PLACE, clear
12367 reg_last_death. [I no longer understand why this is
12369 if (reg_last_death
[regno
] != place
)
12370 reg_last_death
[regno
] = 0;
12374 reg_last_death
[regno
] = place
;
12376 /* If this is a death note for a hard reg that is occupying
12377 multiple registers, ensure that we are still using all
12378 parts of the object. If we find a piece of the object
12379 that is unused, we must arrange for an appropriate REG_DEAD
12380 note to be added for it. However, we can't just emit a USE
12381 and tag the note to it, since the register might actually
12382 be dead; so we recourse, and the recursive call then finds
12383 the previous insn that used this register. */
12385 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12386 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12388 unsigned int endregno
12389 = regno
+ HARD_REGNO_NREGS (regno
,
12390 GET_MODE (XEXP (note
, 0)));
12394 for (i
= regno
; i
< endregno
; i
++)
12395 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12396 && ! find_regno_fusage (place
, USE
, i
))
12397 || dead_or_set_regno_p (place
, i
))
12402 /* Put only REG_DEAD notes for pieces that are
12403 not already dead or set. */
12405 for (i
= regno
; i
< endregno
;
12406 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12408 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12409 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12411 if (! dead_or_set_p (place
, piece
)
12412 && ! reg_bitfield_target_p (piece
,
12416 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12418 distribute_notes (new_note
, place
, place
,
12419 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12421 else if (! refers_to_regno_p (i
, i
+ 1,
12422 PATTERN (place
), 0)
12423 && ! find_regno_fusage (place
, USE
, i
))
12424 for (tem
= PREV_INSN (place
); ;
12425 tem
= PREV_INSN (tem
))
12427 if (! INSN_P (tem
))
12429 if (tem
== bb
->head
)
12431 SET_BIT (refresh_blocks
,
12438 if (dead_or_set_p (tem
, piece
)
12439 || reg_bitfield_target_p (piece
,
12443 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12458 /* Any other notes should not be present at this point in the
12465 XEXP (note
, 1) = REG_NOTES (place
);
12466 REG_NOTES (place
) = note
;
12468 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12469 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12470 && GET_CODE (XEXP (note
, 0)) == REG
)
12471 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12475 if ((REG_NOTE_KIND (note
) == REG_DEAD
12476 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12477 && GET_CODE (XEXP (note
, 0)) == REG
)
12478 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12480 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12481 REG_NOTE_KIND (note
),
12483 REG_NOTES (place2
));
12488 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12489 I3, I2, and I1 to new locations. This is also called in one case to
12490 add a link pointing at I3 when I3's destination is changed. */
12493 distribute_links (links
)
12496 rtx link
, next_link
;
12498 for (link
= links
; link
; link
= next_link
)
12504 next_link
= XEXP (link
, 1);
12506 /* If the insn that this link points to is a NOTE or isn't a single
12507 set, ignore it. In the latter case, it isn't clear what we
12508 can do other than ignore the link, since we can't tell which
12509 register it was for. Such links wouldn't be used by combine
12512 It is not possible for the destination of the target of the link to
12513 have been changed by combine. The only potential of this is if we
12514 replace I3, I2, and I1 by I3 and I2. But in that case the
12515 destination of I2 also remains unchanged. */
12517 if (GET_CODE (XEXP (link
, 0)) == NOTE
12518 || (set
= single_set (XEXP (link
, 0))) == 0)
12521 reg
= SET_DEST (set
);
12522 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12523 || GET_CODE (reg
) == SIGN_EXTRACT
12524 || GET_CODE (reg
) == STRICT_LOW_PART
)
12525 reg
= XEXP (reg
, 0);
12527 /* A LOG_LINK is defined as being placed on the first insn that uses
12528 a register and points to the insn that sets the register. Start
12529 searching at the next insn after the target of the link and stop
12530 when we reach a set of the register or the end of the basic block.
12532 Note that this correctly handles the link that used to point from
12533 I3 to I2. Also note that not much searching is typically done here
12534 since most links don't point very far away. */
12536 for (insn
= NEXT_INSN (XEXP (link
, 0));
12537 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12538 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12539 insn
= NEXT_INSN (insn
))
12540 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12542 if (reg_referenced_p (reg
, PATTERN (insn
)))
12546 else if (GET_CODE (insn
) == CALL_INSN
12547 && find_reg_fusage (insn
, USE
, reg
))
12553 /* If we found a place to put the link, place it there unless there
12554 is already a link to the same insn as LINK at that point. */
12560 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12561 if (XEXP (link2
, 0) == XEXP (link
, 0))
12566 XEXP (link
, 1) = LOG_LINKS (place
);
12567 LOG_LINKS (place
) = link
;
12569 /* Set added_links_insn to the earliest insn we added a
12571 if (added_links_insn
== 0
12572 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12573 added_links_insn
= place
;
12579 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12585 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12586 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12587 insn
= NEXT_INSN (insn
);
12589 if (INSN_UID (insn
) > max_uid_cuid
)
12592 return INSN_CUID (insn
);
12596 dump_combine_stats (file
)
12601 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12602 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12606 dump_combine_total_stats (file
)
12611 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12612 total_attempts
, total_merges
, total_extras
, total_successes
);