1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
41 #include "integrate.h"
44 #include "target-def.h"
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
48 rtx m32r_compare_op0
, m32r_compare_op1
;
50 /* Array of valid operand punctuation characters. */
51 char m32r_punct_chars
[256];
53 /* Selected code model. */
54 const char * m32r_model_string
= M32R_MODEL_DEFAULT
;
55 enum m32r_model m32r_model
;
57 /* Selected SDA support. */
58 const char * m32r_sdata_string
= M32R_SDATA_DEFAULT
;
59 enum m32r_sdata m32r_sdata
;
61 /* Machine-specific symbol_ref flags. */
62 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
63 #define SYMBOL_REF_MODEL(X) \
64 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
66 /* For string literals, etc. */
67 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
69 /* Cache-flush support. Cache-flush is used at trampoline.
70 Default cache-flush is "trap 12".
71 default cache-flush function is "_flush_cache" (CACHE_FLUSH_FUNC)
72 default cache-flush trap-interrupt number is "12". (CACHE_FLUSH_TRAP)
73 You can change how to generate code of cache-flush with following options.
74 -flush-func=FLUSH-FUNC-NAME
76 -fluch-trap=TRAP-NUMBER
78 const char *m32r_cache_flush_func
= CACHE_FLUSH_FUNC
;
79 const char *m32r_cache_flush_trap_string
= CACHE_FLUSH_TRAP
;
80 int m32r_cache_flush_trap
= 12;
82 /* Forward declaration. */
83 static void init_reg_tables (void);
84 static void block_move_call (rtx
, rtx
, rtx
);
85 static int m32r_is_insn (rtx
);
86 const struct attribute_spec m32r_attribute_table
[];
87 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
88 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT
);
89 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT
);
91 static void m32r_file_start (void);
93 static int m32r_adjust_priority (rtx
, int);
94 static int m32r_issue_rate (void);
96 static void m32r_encode_section_info (tree
, rtx
, int);
97 static bool m32r_in_small_data_p (tree
);
98 static bool m32r_return_in_memory (tree
, tree
);
99 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
101 static void init_idents (void);
102 static bool m32r_rtx_costs (rtx
, int, int, int *);
103 static bool m32r_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
106 /* Initialize the GCC target structure. */
107 #undef TARGET_ATTRIBUTE_TABLE
108 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
112 #undef TARGET_ASM_ALIGNED_SI_OP
113 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
115 #undef TARGET_ASM_FUNCTION_PROLOGUE
116 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
117 #undef TARGET_ASM_FUNCTION_EPILOGUE
118 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
120 #undef TARGET_ASM_FILE_START
121 #define TARGET_ASM_FILE_START m32r_file_start
123 #undef TARGET_SCHED_ADJUST_PRIORITY
124 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
125 #undef TARGET_SCHED_ISSUE_RATE
126 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
128 #undef TARGET_ENCODE_SECTION_INFO
129 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
130 #undef TARGET_IN_SMALL_DATA_P
131 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
133 #undef TARGET_RTX_COSTS
134 #define TARGET_RTX_COSTS m32r_rtx_costs
135 #undef TARGET_ADDRESS_COST
136 #define TARGET_ADDRESS_COST hook_int_rtx_0
138 #undef TARGET_PROMOTE_PROTOTYPES
139 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
140 #undef TARGET_RETURN_IN_MEMORY
141 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
142 #undef TARGET_SETUP_INCOMING_VARARGS
143 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
144 #undef TARGET_MUST_PASS_IN_STACK
145 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
146 #undef TARGET_PASS_BY_REFERENCE
147 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
149 struct gcc_target targetm
= TARGET_INITIALIZER
;
151 /* Called by OVERRIDE_OPTIONS to initialize various things. */
158 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
159 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
160 m32r_punct_chars
['#'] = 1;
161 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
163 /* Provide default value if not specified. */
165 g_switch_value
= SDATA_DEFAULT_SIZE
;
167 if (strcmp (m32r_model_string
, "small") == 0)
168 m32r_model
= M32R_MODEL_SMALL
;
169 else if (strcmp (m32r_model_string
, "medium") == 0)
170 m32r_model
= M32R_MODEL_MEDIUM
;
171 else if (strcmp (m32r_model_string
, "large") == 0)
172 m32r_model
= M32R_MODEL_LARGE
;
174 error ("bad value (%s) for -mmodel switch", m32r_model_string
);
176 if (strcmp (m32r_sdata_string
, "none") == 0)
177 m32r_sdata
= M32R_SDATA_NONE
;
178 else if (strcmp (m32r_sdata_string
, "sdata") == 0)
179 m32r_sdata
= M32R_SDATA_SDATA
;
180 else if (strcmp (m32r_sdata_string
, "use") == 0)
181 m32r_sdata
= M32R_SDATA_USE
;
183 error ("bad value (%s) for -msdata switch", m32r_sdata_string
);
185 if (m32r_cache_flush_trap_string
)
187 /* Change trap-number (12) for cache-flush to the others (0 - 15). */
188 m32r_cache_flush_trap
= atoi (m32r_cache_flush_trap_string
);
189 if (m32r_cache_flush_trap
< 0 || m32r_cache_flush_trap
> 15)
190 error ("bad value (%s) for -flush-trap=n (0=<n<=15)",
191 m32r_cache_flush_trap_string
);
195 /* Vectors to keep interesting information about registers where it can easily
196 be got. We use to use the actual mode value as the bit number, but there
197 is (or may be) more than 32 modes now. Instead we use two tables: one
198 indexed by hard register number, and one indexed by mode. */
200 /* The purpose of m32r_mode_class is to shrink the range of modes so that
201 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
202 mapped into one m32r_mode_class mode. */
207 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
208 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
211 /* Modes for condition codes. */
212 #define C_MODES (1 << (int) C_MODE)
214 /* Modes for single-word and smaller quantities. */
215 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
217 /* Modes for double-word and smaller quantities. */
218 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
220 /* Modes for quad-word and smaller quantities. */
221 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
223 /* Modes for accumulators. */
224 #define A_MODES (1 << (int) A_MODE)
226 /* Value is 1 if register/mode pair is acceptable on arc. */
228 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
230 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
231 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
232 S_MODES
, C_MODES
, A_MODES
, A_MODES
235 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
237 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
240 init_reg_tables (void)
244 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
246 switch (GET_MODE_CLASS (i
))
249 case MODE_PARTIAL_INT
:
250 case MODE_COMPLEX_INT
:
251 if (GET_MODE_SIZE (i
) <= 4)
252 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
253 else if (GET_MODE_SIZE (i
) == 8)
254 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
255 else if (GET_MODE_SIZE (i
) == 16)
256 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
257 else if (GET_MODE_SIZE (i
) == 32)
258 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
260 m32r_mode_class
[i
] = 0;
263 case MODE_COMPLEX_FLOAT
:
264 if (GET_MODE_SIZE (i
) <= 4)
265 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
266 else if (GET_MODE_SIZE (i
) == 8)
267 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
268 else if (GET_MODE_SIZE (i
) == 16)
269 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
270 else if (GET_MODE_SIZE (i
) == 32)
271 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
273 m32r_mode_class
[i
] = 0;
276 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
279 m32r_mode_class
[i
] = 0;
284 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
287 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
288 else if (i
== ARG_POINTER_REGNUM
)
289 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
291 m32r_regno_reg_class
[i
] = NO_REGS
;
295 /* M32R specific attribute support.
297 interrupt - for interrupt functions
299 model - select code model used to access object
301 small: addresses use 24 bits, use bl to make calls
302 medium: addresses use 32 bits, use bl to make calls
303 large: addresses use 32 bits, use seth/add3/jl to make calls
305 Grep for MODEL in m32r.h for more info. */
307 static tree small_ident1
;
308 static tree small_ident2
;
309 static tree medium_ident1
;
310 static tree medium_ident2
;
311 static tree large_ident1
;
312 static tree large_ident2
;
317 if (small_ident1
== 0)
319 small_ident1
= get_identifier ("small");
320 small_ident2
= get_identifier ("__small__");
321 medium_ident1
= get_identifier ("medium");
322 medium_ident2
= get_identifier ("__medium__");
323 large_ident1
= get_identifier ("large");
324 large_ident2
= get_identifier ("__large__");
328 const struct attribute_spec m32r_attribute_table
[] =
330 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
331 { "interrupt", 0, 0, true, false, false, NULL
},
332 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
},
333 { NULL
, 0, 0, false, false, false, NULL
}
337 /* Handle an "model" attribute; arguments as in
338 struct attribute_spec.handler. */
340 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
341 tree args
, int flags ATTRIBUTE_UNUSED
,
347 arg
= TREE_VALUE (args
);
349 if (arg
!= small_ident1
350 && arg
!= small_ident2
351 && arg
!= medium_ident1
352 && arg
!= medium_ident2
353 && arg
!= large_ident1
354 && arg
!= large_ident2
)
356 warning ("invalid argument of `%s' attribute",
357 IDENTIFIER_POINTER (name
));
358 *no_add_attrs
= true;
364 /* Encode section information of DECL, which is either a VAR_DECL,
365 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
367 For the M32R we want to record:
369 - whether the object lives in .sdata/.sbss.
370 - what code model should be used to access the object
374 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
378 enum m32r_model model
;
380 default_encode_section_info (decl
, rtl
, first
);
385 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
392 id
= TREE_VALUE (TREE_VALUE (model_attr
));
394 if (id
== small_ident1
|| id
== small_ident2
)
395 model
= M32R_MODEL_SMALL
;
396 else if (id
== medium_ident1
|| id
== medium_ident2
)
397 model
= M32R_MODEL_MEDIUM
;
398 else if (id
== large_ident1
|| id
== large_ident2
)
399 model
= M32R_MODEL_LARGE
;
401 abort (); /* shouldn't happen */
405 if (TARGET_MODEL_SMALL
)
406 model
= M32R_MODEL_SMALL
;
407 else if (TARGET_MODEL_MEDIUM
)
408 model
= M32R_MODEL_MEDIUM
;
409 else if (TARGET_MODEL_LARGE
)
410 model
= M32R_MODEL_LARGE
;
412 abort (); /* shouldn't happen */
414 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
417 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
420 /* Only mark the object as being small data area addressable if
421 it hasn't been explicitly marked with a code model.
423 The user can explicitly put an object in the small data area with the
424 section attribute. If the object is in sdata/sbss and marked with a
425 code model do both [put the object in .sdata and mark it as being
426 addressed with a specific code model - don't mark it as being addressed
427 with an SDA reloc though]. This is ok and might be useful at times. If
428 the object doesn't fit the linker will give an error. */
431 m32r_in_small_data_p (tree decl
)
435 if (TREE_CODE (decl
) != VAR_DECL
)
438 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
441 section
= DECL_SECTION_NAME (decl
);
444 char *name
= (char *) TREE_STRING_POINTER (section
);
445 if (strcmp (name
, ".sdata") == 0 || strcmp (name
, ".sbss") == 0)
450 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
452 int size
= int_size_in_bytes (TREE_TYPE (decl
));
454 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
462 /* Do anything needed before RTL is emitted for each function. */
465 m32r_init_expanders (void)
467 /* ??? At one point there was code here. The function is left in
468 to make it easy to experiment. */
471 /* Acceptable arguments to the call insn. */
474 call_address_operand (rtx op
, enum machine_mode mode
)
476 return symbolic_operand (op
, mode
);
478 /* Constants and values in registers are not OK, because
479 the m32r BL instruction can only support PC relative branching. */
483 call_operand (rtx op
, enum machine_mode mode
)
485 if (GET_CODE (op
) != MEM
)
488 return call_address_operand (op
, mode
);
491 /* Returns 1 if OP is a symbol reference. */
494 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
496 switch (GET_CODE (op
))
508 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
511 small_data_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
513 if (! TARGET_SDATA_USE
)
516 if (GET_CODE (op
) == SYMBOL_REF
)
517 return SYMBOL_REF_SMALL_P (op
);
519 if (GET_CODE (op
) == CONST
520 && GET_CODE (XEXP (op
, 0)) == PLUS
521 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
522 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
523 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
524 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
529 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
532 addr24_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
539 if (GET_CODE (op
) == LABEL_REF
)
540 return TARGET_ADDR24
;
542 if (GET_CODE (op
) == SYMBOL_REF
)
544 else if (GET_CODE (op
) == CONST
545 && GET_CODE (XEXP (op
, 0)) == PLUS
546 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
547 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
548 && UINT24_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
549 sym
= XEXP (XEXP (op
, 0), 0);
553 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
557 && (CONSTANT_POOL_ADDRESS_P (sym
)
558 || LIT_NAME_P (XSTR (sym
, 0))))
564 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
567 addr32_operand (rtx op
, enum machine_mode mode
)
571 if (GET_CODE (op
) == LABEL_REF
)
572 return TARGET_ADDR32
;
574 if (GET_CODE (op
) == SYMBOL_REF
)
576 else if (GET_CODE (op
) == CONST
577 && GET_CODE (XEXP (op
, 0)) == PLUS
578 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
579 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
581 sym
= XEXP (XEXP (op
, 0), 0);
585 return (! addr24_operand (sym
, mode
)
586 && ! small_data_operand (sym
, mode
));
589 /* Return 1 if OP is a function that can be called with the `bl' insn. */
592 call26_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
597 if (GET_CODE (op
) == SYMBOL_REF
)
598 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
600 return TARGET_CALL26
;
603 /* Returns 1 if OP is an acceptable operand for seth/add3. */
606 seth_add3_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
611 if (GET_CODE (op
) == SYMBOL_REF
612 || GET_CODE (op
) == LABEL_REF
)
615 if (GET_CODE (op
) == CONST
616 && GET_CODE (XEXP (op
, 0)) == PLUS
617 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
618 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
619 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
625 /* Return true if OP is a signed 8 bit immediate value. */
628 int8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
630 if (GET_CODE (op
) != CONST_INT
)
632 return INT8_P (INTVAL (op
));
635 /* Return true if OP is a signed 16 bit immediate value
636 useful in comparisons. */
639 cmp_int16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
641 if (GET_CODE (op
) != CONST_INT
)
643 return CMP_INT16_P (INTVAL (op
));
646 /* Return true if OP is an unsigned 16 bit immediate value. */
649 uint16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
651 if (GET_CODE (op
) != CONST_INT
)
653 return UINT16_P (INTVAL (op
));
656 /* Return true if OP is a register or signed 16 bit value. */
659 reg_or_int16_operand (rtx op
, enum machine_mode mode
)
661 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
662 return register_operand (op
, mode
);
663 if (GET_CODE (op
) != CONST_INT
)
665 return INT16_P (INTVAL (op
));
668 /* Return true if OP is a register or an unsigned 16 bit value. */
671 reg_or_uint16_operand (rtx op
, enum machine_mode mode
)
673 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
674 return register_operand (op
, mode
);
675 if (GET_CODE (op
) != CONST_INT
)
677 return UINT16_P (INTVAL (op
));
680 /* Return true if OP is a register or an integer value that can be
681 used is SEQ/SNE. We can use either XOR of the value or ADD of
682 the negative of the value for the constant. Don't allow 0,
683 because that is special cased. */
686 reg_or_eq_int16_operand (rtx op
, enum machine_mode mode
)
690 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
691 return register_operand (op
, mode
);
693 if (GET_CODE (op
) != CONST_INT
)
697 return (value
!= 0) && (UINT16_P (value
) || CMP_INT16_P (-value
));
700 /* Return true if OP is a register or signed 16 bit value for compares. */
703 reg_or_cmp_int16_operand (rtx op
, enum machine_mode mode
)
705 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
706 return register_operand (op
, mode
);
707 if (GET_CODE (op
) != CONST_INT
)
709 return CMP_INT16_P (INTVAL (op
));
712 /* Return true if OP is a register or the constant 0. */
715 reg_or_zero_operand (rtx op
, enum machine_mode mode
)
717 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
718 return register_operand (op
, mode
);
720 if (GET_CODE (op
) != CONST_INT
)
723 return INTVAL (op
) == 0;
726 /* Return true if OP is a const_int requiring two instructions to load. */
729 two_insn_const_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
731 if (GET_CODE (op
) != CONST_INT
)
733 if (INT16_P (INTVAL (op
))
734 || UINT24_P (INTVAL (op
))
735 || UPPER16_P (INTVAL (op
)))
740 /* Return true if OP is an acceptable argument for a single word
744 move_src_operand (rtx op
, enum machine_mode mode
)
746 switch (GET_CODE (op
))
751 return addr24_operand (op
, mode
);
753 /* ??? We allow more cse opportunities if we only allow constants
754 loadable with one insn, and split the rest into two. The instances
755 where this would help should be rare and the current way is
757 if (HOST_BITS_PER_WIDE_INT
> 32)
759 HOST_WIDE_INT rest
= INTVAL (op
) >> 31;
760 return (rest
== 0 || rest
== -1);
767 else if (mode
== SImode
)
769 /* Large unsigned constants are represented as const_double's. */
770 unsigned HOST_WIDE_INT low
, high
;
772 low
= CONST_DOUBLE_LOW (op
);
773 high
= CONST_DOUBLE_HIGH (op
);
774 return high
== 0 && low
<= (unsigned) 0xffffffff;
779 return register_operand (op
, mode
);
781 /* (subreg (mem ...) ...) can occur here if the inner part was once a
782 pseudo-reg and is now a stack slot. */
783 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
784 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
786 return register_operand (op
, mode
);
788 if (GET_CODE (XEXP (op
, 0)) == PRE_INC
789 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
790 return 0; /* loads can't do pre-{inc,dec} */
791 return address_operand (XEXP (op
, 0), mode
);
797 /* Return true if OP is an acceptable argument for a double word
801 move_double_src_operand (rtx op
, enum machine_mode mode
)
803 switch (GET_CODE (op
))
809 return register_operand (op
, mode
);
811 /* (subreg (mem ...) ...) can occur here if the inner part was once a
812 pseudo-reg and is now a stack slot. */
813 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
814 return move_double_src_operand (SUBREG_REG (op
), mode
);
816 return register_operand (op
, mode
);
818 /* Disallow auto inc/dec for now. */
819 if (GET_CODE (XEXP (op
, 0)) == PRE_DEC
820 || GET_CODE (XEXP (op
, 0)) == PRE_INC
)
822 return address_operand (XEXP (op
, 0), mode
);
828 /* Return true if OP is an acceptable argument for a move destination. */
831 move_dest_operand (rtx op
, enum machine_mode mode
)
833 switch (GET_CODE (op
))
836 return register_operand (op
, mode
);
838 /* (subreg (mem ...) ...) can occur here if the inner part was once a
839 pseudo-reg and is now a stack slot. */
840 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
841 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
843 return register_operand (op
, mode
);
845 if (GET_CODE (XEXP (op
, 0)) == POST_INC
)
846 return 0; /* stores can't do post inc */
847 return address_operand (XEXP (op
, 0), mode
);
853 /* Return 1 if OP is a DImode const we want to handle inline.
854 This must match the code in the movdi pattern.
855 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
858 easy_di_const (rtx op
)
860 rtx high_rtx
, low_rtx
;
861 HOST_WIDE_INT high
, low
;
863 split_double (op
, &high_rtx
, &low_rtx
);
864 high
= INTVAL (high_rtx
);
865 low
= INTVAL (low_rtx
);
866 /* Pick constants loadable with 2 16 bit `ldi' insns. */
867 if (high
>= -128 && high
<= 127
868 && low
>= -128 && low
<= 127)
873 /* Return 1 if OP is a DFmode const we want to handle inline.
874 This must match the code in the movdf pattern.
875 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
878 easy_df_const (rtx op
)
883 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
884 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
885 if (l
[0] == 0 && l
[1] == 0)
887 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
892 /* Return 1 if OP is an EQ or NE comparison operator. */
895 eqne_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
897 enum rtx_code code
= GET_CODE (op
);
899 return (code
== EQ
|| code
== NE
);
902 /* Return 1 if OP is a signed comparison operator. */
905 signed_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
907 enum rtx_code code
= GET_CODE (op
);
909 return (COMPARISON_P (op
)
910 && (code
== EQ
|| code
== NE
911 || code
== LT
|| code
== LE
|| code
== GT
|| code
== GE
));
914 /* Return 1 if OP is (mem (reg ...)).
915 This is used in insn length calcs. */
918 memreg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
920 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == REG
;
923 /* Return true if OP is an acceptable input argument for a zero/sign extend
927 extend_operand (rtx op
, enum machine_mode mode
)
931 switch (GET_CODE (op
))
935 return register_operand (op
, mode
);
939 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
940 return 0; /* loads can't do pre inc/pre dec */
942 return address_operand (addr
, mode
);
949 /* Return nonzero if the operand is an insn that is a small insn.
950 Allow const_int 0 as well, which is a placeholder for NOP slots. */
953 small_insn_p (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
955 if (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
961 return get_attr_length (op
) == 2;
964 /* Return nonzero if the operand is an insn that is a large insn. */
967 large_insn_p (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
972 return get_attr_length (op
) != 2;
975 /* Return nonzero if TYPE must be passed by indirect reference. */
978 m32r_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
979 enum machine_mode mode
, tree type
,
980 bool named ATTRIBUTE_UNUSED
)
985 size
= int_size_in_bytes (type
);
987 size
= GET_MODE_SIZE (mode
);
989 return (size
< 0 || size
> 8);
994 /* X and Y are two things to compare using CODE. Emit the compare insn and
995 return the rtx for compare [arg0 of the if_then_else].
996 If need_compare is true then the comparison insn must be generated, rather
997 than being subsumed into the following branch instruction. */
1000 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
1002 enum rtx_code compare_code
;
1003 enum rtx_code branch_code
;
1004 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
1009 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
1010 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
1011 case LT
: compare_code
= LT
; branch_code
= NE
; break;
1012 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
1013 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
1014 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
1015 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
1016 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
1017 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
1018 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
1026 switch (compare_code
)
1029 if (GET_CODE (y
) == CONST_INT
1030 && CMP_INT16_P (INTVAL (y
)) /* Reg equal to small const. */
1033 rtx tmp
= gen_reg_rtx (SImode
);
1035 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
1039 else if (CONSTANT_P (y
)) /* Reg equal to const. */
1041 rtx tmp
= force_reg (GET_MODE (x
), y
);
1045 if (register_operand (y
, SImode
) /* Reg equal to reg. */
1046 || y
== const0_rtx
) /* Reg equal to zero. */
1048 emit_insn (gen_cmp_eqsi_insn (x
, y
));
1050 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
1055 if (register_operand (y
, SImode
)
1056 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1058 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
1063 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1067 if (y
== const0_rtx
)
1070 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
1071 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1075 if (GET_CODE (y
) == CONST_INT
)
1076 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
1078 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
1079 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1083 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1090 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
1095 if (register_operand (y
, SImode
)
1096 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1098 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
1103 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1107 if (y
== const0_rtx
)
1110 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
1111 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1115 if (GET_CODE (y
) == CONST_INT
)
1116 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
1118 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
1119 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1123 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1130 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
1140 /* Reg/reg equal comparison. */
1141 if (compare_code
== EQ
1142 && register_operand (y
, SImode
))
1143 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
1145 /* Reg/zero signed comparison. */
1146 if ((compare_code
== EQ
|| compare_code
== LT
)
1148 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
1150 /* Reg/smallconst equal comparison. */
1151 if (compare_code
== EQ
1152 && GET_CODE (y
) == CONST_INT
1153 && CMP_INT16_P (INTVAL (y
)))
1155 rtx tmp
= gen_reg_rtx (SImode
);
1157 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
1158 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
1161 /* Reg/const equal comparison. */
1162 if (compare_code
== EQ
1165 rtx tmp
= force_reg (GET_MODE (x
), y
);
1167 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
1174 y
= force_reg (GET_MODE (x
), y
);
1178 (code
== LTU
|| code
== LEU
|| code
== GTU
|| code
== GEU
)
1179 ? uint16_operand (y
, GET_MODE (y
))
1180 : reg_or_cmp_int16_operand (y
, GET_MODE (y
));
1183 y
= force_reg (GET_MODE (x
), y
);
1187 switch (compare_code
)
1190 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1193 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1196 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1203 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
1206 /* Split a 2 word move (DI or DF) into component parts. */
1209 gen_split_move_double (rtx operands
[])
1211 enum machine_mode mode
= GET_MODE (operands
[0]);
1212 rtx dest
= operands
[0];
1213 rtx src
= operands
[1];
1216 /* We might have (SUBREG (MEM)) here, so just get rid of the
1217 subregs to make this code simpler. It is safe to call
1218 alter_subreg any time after reload. */
1219 if (GET_CODE (dest
) == SUBREG
)
1220 alter_subreg (&dest
);
1221 if (GET_CODE (src
) == SUBREG
)
1222 alter_subreg (&src
);
1225 if (GET_CODE (dest
) == REG
)
1227 int dregno
= REGNO (dest
);
1230 if (GET_CODE (src
) == REG
)
1232 int sregno
= REGNO (src
);
1234 int reverse
= (dregno
== sregno
+ 1);
1236 /* We normally copy the low-numbered register first. However, if
1237 the first register operand 0 is the same as the second register of
1238 operand 1, we must copy in the opposite order. */
1239 emit_insn (gen_rtx_SET (VOIDmode
,
1240 operand_subword (dest
, reverse
, TRUE
, mode
),
1241 operand_subword (src
, reverse
, TRUE
, mode
)));
1243 emit_insn (gen_rtx_SET (VOIDmode
,
1244 operand_subword (dest
, !reverse
, TRUE
, mode
),
1245 operand_subword (src
, !reverse
, TRUE
, mode
)));
1248 /* Reg = constant. */
1249 else if (GET_CODE (src
) == CONST_INT
|| GET_CODE (src
) == CONST_DOUBLE
)
1252 split_double (src
, &words
[0], &words
[1]);
1253 emit_insn (gen_rtx_SET (VOIDmode
,
1254 operand_subword (dest
, 0, TRUE
, mode
),
1257 emit_insn (gen_rtx_SET (VOIDmode
,
1258 operand_subword (dest
, 1, TRUE
, mode
),
1263 else if (GET_CODE (src
) == MEM
)
1265 /* If the high-address word is used in the address, we must load it
1266 last. Otherwise, load it first. */
1268 = (refers_to_regno_p (dregno
, dregno
+ 1, XEXP (src
, 0), 0) != 0);
1270 /* We used to optimize loads from single registers as
1274 if r3 were not used subsequently. However, the REG_NOTES aren't
1275 propagated correctly by the reload phase, and it can cause bad
1276 code to be generated. We could still try:
1278 ld r1,r3+; ld r2,r3; addi r3,-4
1280 which saves 2 bytes and doesn't force longword alignment. */
1281 emit_insn (gen_rtx_SET (VOIDmode
,
1282 operand_subword (dest
, reverse
, TRUE
, mode
),
1283 adjust_address (src
, SImode
,
1284 reverse
* UNITS_PER_WORD
)));
1286 emit_insn (gen_rtx_SET (VOIDmode
,
1287 operand_subword (dest
, !reverse
, TRUE
, mode
),
1288 adjust_address (src
, SImode
,
1289 !reverse
* UNITS_PER_WORD
)));
1296 /* We used to optimize loads from single registers as
1300 if r3 were not used subsequently. However, the REG_NOTES aren't
1301 propagated correctly by the reload phase, and it can cause bad
1302 code to be generated. We could still try:
1304 st r1,r3; st r2,+r3; addi r3,-4
1306 which saves 2 bytes and doesn't force longword alignment. */
1307 else if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
1309 emit_insn (gen_rtx_SET (VOIDmode
,
1310 adjust_address (dest
, SImode
, 0),
1311 operand_subword (src
, 0, TRUE
, mode
)));
1313 emit_insn (gen_rtx_SET (VOIDmode
,
1314 adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1315 operand_subword (src
, 1, TRUE
, mode
)));
1327 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1330 function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1331 tree type
, int named ATTRIBUTE_UNUSED
)
1335 (((mode
== BLKmode
&& type
)
1336 ? (unsigned int) int_size_in_bytes (type
)
1337 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1340 if (*cum
>= M32R_MAX_PARM_REGS
)
1342 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1343 ret
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1350 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1353 m32r_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
1355 return m32r_pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
1358 /* Do any needed setup for a variadic function. For the M32R, we must
1359 create a register parameter block, and then copy any anonymous arguments
1360 in registers to memory.
1362 CUM has not been updated for the last named argument which has type TYPE
1363 and mode MODE, and we rely on this fact. */
1366 m32r_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1367 tree type
, int *pretend_size
, int no_rtl
)
1374 /* All BLKmode values are passed by reference. */
1375 if (mode
== BLKmode
)
1378 first_anon_arg
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1379 + ROUND_ADVANCE_ARG (mode
, type
));
1381 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1383 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1384 int first_reg_offset
= first_anon_arg
;
1385 /* Size in words to "pretend" allocate. */
1386 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1389 regblock
= gen_rtx_MEM (BLKmode
,
1390 plus_constant (arg_pointer_rtx
,
1391 FIRST_PARM_OFFSET (0)));
1392 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1393 move_block_from_reg (first_reg_offset
, regblock
, size
);
1395 *pretend_size
= (size
* UNITS_PER_WORD
);
1400 /* Return true if INSN is real instruction bearing insn. */
1403 m32r_is_insn (rtx insn
)
1405 return (INSN_P (insn
)
1406 && GET_CODE (PATTERN (insn
)) != USE
1407 && GET_CODE (PATTERN (insn
)) != CLOBBER
1408 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
);
1411 /* Increase the priority of long instructions so that the
1412 short instructions are scheduled ahead of the long ones. */
1415 m32r_adjust_priority (rtx insn
, int priority
)
1417 if (m32r_is_insn (insn
)
1418 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1425 /* Indicate how many instructions can be issued at the same time.
1426 This is sort of a lie. The m32r can issue only 1 long insn at
1427 once, but it can issue 2 short insns. The default therefore is
1428 set at 2, but this can be overridden by the command line option
1432 m32r_issue_rate (void)
1434 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1437 /* Cost functions. */
1440 m32r_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int *total
)
1444 /* Small integers are as cheap as registers. 4 byte values can be
1445 fetched as immediate constants - let's give that the cost of an
1448 if (INT16_P (INTVAL (x
)))
1458 *total
= COSTS_N_INSNS (1);
1465 split_double (x
, &high
, &low
);
1466 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1467 + !INT16_P (INTVAL (low
)));
1472 *total
= COSTS_N_INSNS (3);
1479 *total
= COSTS_N_INSNS (10);
1487 /* Type of function DECL.
1489 The result is cached. To reset the cache at the end of a function,
1490 call with DECL = NULL_TREE. */
1492 enum m32r_function_type
1493 m32r_compute_function_type (tree decl
)
1496 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1497 /* Last function we were called for. */
1498 static tree last_fn
= NULL_TREE
;
1500 /* Resetting the cached value? */
1501 if (decl
== NULL_TREE
)
1503 fn_type
= M32R_FUNCTION_UNKNOWN
;
1504 last_fn
= NULL_TREE
;
1508 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1511 /* Compute function type. */
1512 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1513 ? M32R_FUNCTION_INTERRUPT
1514 : M32R_FUNCTION_NORMAL
);
1519 \f/* Function prologue/epilogue handlers. */
1521 /* M32R stack frames look like:
1523 Before call After call
1524 +-----------------------+ +-----------------------+
1526 high | local variables, | | local variables, |
1527 mem | reg save area, etc. | | reg save area, etc. |
1529 +-----------------------+ +-----------------------+
1531 | arguments on stack. | | arguments on stack. |
1533 SP+0->+-----------------------+ +-----------------------+
1534 | reg parm save area, |
1535 | only created for |
1536 | variable argument |
1538 +-----------------------+
1539 | previous frame ptr |
1540 +-----------------------+
1542 | register save area |
1544 +-----------------------+
1546 +-----------------------+
1550 +-----------------------+
1552 | alloca allocations |
1554 +-----------------------+
1556 low | arguments on stack |
1558 SP+0->+-----------------------+
1561 1) The "reg parm save area" does not exist for non variable argument fns.
1562 2) The "reg parm save area" can be eliminated completely if we saved regs
1563 containing anonymous args separately but that complicates things too
1564 much (so it's not done).
1565 3) The return address is saved after the register save area so as to have as
1566 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1568 /* Structure to be filled in by m32r_compute_frame_size with register
1569 save masks, and offsets for the current function. */
1570 struct m32r_frame_info
1572 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1573 unsigned int extra_size
; /* # bytes of extra stuff. */
1574 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1575 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1576 unsigned int reg_size
; /* # bytes needed to store regs. */
1577 unsigned int var_size
; /* # bytes that variables take up. */
1578 unsigned int gmask
; /* Mask of saved gp registers. */
1579 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1580 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1581 int initialized
; /* Nonzero if frame size already calculated. */
1584 /* Current frame information calculated by m32r_compute_frame_size. */
1585 static struct m32r_frame_info current_frame_info
;
1587 /* Zero structure to initialize current_frame_info. */
1588 static struct m32r_frame_info zero_frame_info
;
1590 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1591 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1593 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1594 The return address and frame pointer are treated separately.
1595 Don't consider them here. */
1596 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1597 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1598 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1600 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1601 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1603 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1604 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1606 /* Return the bytes needed to compute the frame pointer from the current
1609 SIZE is the size needed for local variables. */
1612 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1615 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1616 unsigned int reg_size
, frame_size
;
1618 enum m32r_function_type fn_type
;
1620 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
);
1622 var_size
= M32R_STACK_ALIGN (size
);
1623 args_size
= M32R_STACK_ALIGN (current_function_outgoing_args_size
);
1624 pretend_size
= current_function_pretend_args_size
;
1625 extra_size
= FIRST_PARM_OFFSET (0);
1626 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1630 /* See if this is an interrupt handler. Call used registers must be saved
1632 fn_type
= m32r_compute_function_type (current_function_decl
);
1633 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1635 /* Calculate space needed for registers. */
1636 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1638 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1639 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1641 reg_size
+= UNITS_PER_WORD
;
1642 gmask
|= 1 << regno
;
1646 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1647 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1649 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1651 total_size
+= reg_size
;
1653 /* ??? Not sure this is necessary, and I don't think the epilogue
1654 handler will do the right thing if this changes total_size. */
1655 total_size
= M32R_STACK_ALIGN (total_size
);
1657 frame_size
= total_size
- (pretend_size
+ reg_size
);
1659 /* Save computed information. */
1660 current_frame_info
.total_size
= total_size
;
1661 current_frame_info
.extra_size
= extra_size
;
1662 current_frame_info
.pretend_size
= pretend_size
;
1663 current_frame_info
.var_size
= var_size
;
1664 current_frame_info
.args_size
= args_size
;
1665 current_frame_info
.reg_size
= reg_size
;
1666 current_frame_info
.gmask
= gmask
;
1667 current_frame_info
.initialized
= reload_completed
;
1669 /* Ok, we're done. */
1673 /* The table we use to reference PIC data. */
1674 static rtx global_offset_table
;
1677 m32r_reload_lr (rtx sp
, int size
)
1679 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1682 emit_insn (gen_movsi (lr
, gen_rtx_MEM (Pmode
, sp
)));
1683 else if (size
<= 32768)
1684 emit_insn (gen_movsi (lr
, gen_rtx_MEM (Pmode
,
1685 gen_rtx_PLUS (Pmode
, sp
,
1689 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1691 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1692 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1693 emit_insn (gen_movsi (lr
, gen_rtx_MEM (Pmode
, tmp
)));
1696 emit_insn (gen_rtx_USE (VOIDmode
, lr
));
1700 m32r_load_pic_register (void)
1702 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1703 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1704 GEN_INT (TARGET_MODEL_SMALL
)));
1706 /* Need to emit this whether or not we obey regdecls,
1707 since setjmp/longjmp can cause life info to screw up. */
1708 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
1711 /* Expand the m32r prologue as a series of insns. */
1714 m32r_expand_prologue (void)
1719 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
);
1721 if (! current_frame_info
.initialized
)
1722 m32r_compute_frame_size (get_frame_size ());
1724 gmask
= current_frame_info
.gmask
;
1726 /* These cases shouldn't happen. Catch them now. */
1727 if (current_frame_info
.total_size
== 0 && gmask
)
1730 /* Allocate space for register arguments if this is a variadic function. */
1731 if (current_frame_info
.pretend_size
!= 0)
1733 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1734 the wrong result on a 64-bit host. */
1735 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1736 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1738 GEN_INT (-pretend_size
)));
1741 /* Save any registers we need to and set up fp. */
1742 if (current_frame_info
.save_fp
)
1743 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1745 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1747 /* Save any needed call-saved regs (and call-used if this is an
1748 interrupt handler). */
1749 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1751 if ((gmask
& (1 << regno
)) != 0)
1752 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1753 gen_rtx_REG (Pmode
, regno
)));
1756 if (current_frame_info
.save_lr
)
1757 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1758 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1760 /* Allocate the stack frame. */
1761 frame_size
= (current_frame_info
.total_size
1762 - (current_frame_info
.pretend_size
1763 + current_frame_info
.reg_size
));
1765 if (frame_size
== 0)
1766 ; /* Nothing to do. */
1767 else if (frame_size
<= 32768)
1768 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1769 GEN_INT (-frame_size
)));
1772 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1774 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1775 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1778 if (frame_pointer_needed
)
1779 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1781 if (current_function_profile
)
1782 /* Push lr for mcount (form_pc, x). */
1783 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1784 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1788 m32r_load_pic_register ();
1789 m32r_reload_lr (stack_pointer_rtx
,
1790 (current_function_profile
? 0 : frame_size
));
1793 if (current_function_profile
&& !pic_reg_used
)
1794 emit_insn (gen_blockage ());
1798 /* Set up the stack and frame pointer (if desired) for the function.
1799 Note, if this is changed, you need to mirror the changes in
1800 m32r_compute_frame_size which calculates the prolog size. */
1803 m32r_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
1805 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1807 /* If this is an interrupt handler, mark it as such. */
1808 if (M32R_INTERRUPT_P (fn_type
))
1809 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1811 if (! current_frame_info
.initialized
)
1812 m32r_compute_frame_size (size
);
1814 /* This is only for the human reader. */
1816 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1818 current_frame_info
.var_size
,
1819 current_frame_info
.reg_size
/ 4,
1820 current_frame_info
.args_size
,
1821 current_frame_info
.extra_size
);
1824 /* Do any necessary cleanup after a function to restore stack, frame,
1828 m32r_output_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1831 int noepilogue
= FALSE
;
1833 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1835 /* This is only for the human reader. */
1836 fprintf (file
, "\t%s EPILOGUE\n", ASM_COMMENT_START
);
1838 if (!current_frame_info
.initialized
)
1840 total_size
= current_frame_info
.total_size
;
1842 if (total_size
== 0)
1844 rtx insn
= get_last_insn ();
1846 /* If the last insn was a BARRIER, we don't have to write any code
1847 because a jump (aka return) was put there. */
1848 if (GET_CODE (insn
) == NOTE
)
1849 insn
= prev_nonnote_insn (insn
);
1850 if (insn
&& GET_CODE (insn
) == BARRIER
)
1856 unsigned int var_size
= current_frame_info
.var_size
;
1857 unsigned int args_size
= current_frame_info
.args_size
;
1858 unsigned int gmask
= current_frame_info
.gmask
;
1859 int can_trust_sp_p
= !current_function_calls_alloca
;
1860 const char * sp_str
= reg_names
[STACK_POINTER_REGNUM
];
1861 const char * fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
1863 /* The first thing to do is point the sp at the bottom of the register
1867 unsigned int reg_offset
= var_size
+ args_size
;
1868 if (reg_offset
== 0)
1869 ; /* Nothing to do. */
1870 else if (reg_offset
< 128)
1871 fprintf (file
, "\taddi %s,%s%d\n",
1872 sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1873 else if (reg_offset
< 32768)
1874 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
1875 sp_str
, sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1877 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1878 reg_names
[PROLOGUE_TMP_REGNUM
],
1879 IMMEDIATE_PREFIX
, reg_offset
,
1880 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
1882 else if (frame_pointer_needed
)
1884 unsigned int reg_offset
= var_size
+ args_size
;
1886 if (reg_offset
== 0)
1887 fprintf (file
, "\tmv %s,%s\n", sp_str
, fp_str
);
1888 else if (reg_offset
< 32768)
1889 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
1890 sp_str
, fp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1892 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1893 reg_names
[PROLOGUE_TMP_REGNUM
],
1894 IMMEDIATE_PREFIX
, reg_offset
,
1895 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
1900 if (current_frame_info
.save_lr
)
1901 fprintf (file
, "\tpop %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
1903 /* Restore any saved registers, in reverse order of course. */
1904 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1905 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1907 if ((gmask
& (1L << regno
)) != 0)
1908 fprintf (file
, "\tpop %s\n", reg_names
[regno
]);
1911 if (current_frame_info
.save_fp
)
1912 fprintf (file
, "\tpop %s\n", fp_str
);
1914 /* Remove varargs area if present. */
1915 if (current_frame_info
.pretend_size
!= 0)
1916 fprintf (file
, "\taddi %s,%s%d\n",
1917 sp_str
, IMMEDIATE_PREFIX
, current_frame_info
.pretend_size
);
1919 /* Emit the return instruction. */
1920 if (M32R_INTERRUPT_P (fn_type
))
1921 fprintf (file
, "\trte\n");
1923 fprintf (file
, "\tjmp %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
1926 /* Reset state info for each function. */
1927 current_frame_info
= zero_frame_info
;
1928 m32r_compute_function_type (NULL_TREE
);
1931 /* Return nonzero if this function is known to have a null or 1 instruction
1935 direct_return (void)
1937 if (!reload_completed
)
1940 if (! current_frame_info
.initialized
)
1941 m32r_compute_frame_size (get_frame_size ());
1943 return current_frame_info
.total_size
== 0;
1950 m32r_legitimate_pic_operand_p (rtx x
)
1952 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1955 if (GET_CODE (x
) == CONST
1956 && GET_CODE (XEXP (x
, 0)) == PLUS
1957 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1958 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1959 && (GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
1966 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1969 printf("m32r_legitimize_pic_address()\n");
1972 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1974 rtx pic_ref
, address
;
1980 if (reload_in_progress
|| reload_completed
)
1983 reg
= gen_reg_rtx (Pmode
);
1989 address
= gen_reg_rtx (Pmode
);
1993 emit_insn (gen_pic_load_addr (address
, orig
));
1995 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
1996 pic_ref
= gen_const_mem (Pmode
, address
);
1997 insn
= emit_move_insn (reg
, pic_ref
);
1998 current_function_uses_pic_offset_table
= 1;
2000 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2002 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2007 else if (GET_CODE (orig
) == CONST
)
2011 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2012 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
2017 if (reload_in_progress
|| reload_completed
)
2020 reg
= gen_reg_rtx (Pmode
);
2023 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2025 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
2027 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
2029 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
2034 if (GET_CODE (offset
) == CONST_INT
)
2036 if (INT16_P (INTVAL (offset
)))
2037 return plus_constant (base
, INTVAL (offset
));
2038 else if (! reload_in_progress
&& ! reload_completed
)
2039 offset
= force_reg (Pmode
, offset
);
2041 /* If we reach here, then something is seriously wrong. */
2045 return gen_rtx_PLUS (Pmode
, base
, offset
);
2051 /* Emit special PIC prologues and epilogues. */
2054 m32r_finalize_pic (void)
2056 current_function_uses_pic_offset_table
|= current_function_profile
;
2059 /* Nested function support. */
2061 /* Emit RTL insns to initialize the variable parts of a trampoline.
2062 FNADDR is an RTX for the address of the function's pure code.
2063 CXT is an RTX for the static chain value for the function. */
2066 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
2067 rtx fnaddr ATTRIBUTE_UNUSED
,
2068 rtx cxt ATTRIBUTE_UNUSED
)
2073 m32r_file_start (void)
2075 default_file_start ();
2077 if (flag_verbose_asm
)
2078 fprintf (asm_out_file
,
2079 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
2080 ASM_COMMENT_START
, g_switch_value
);
2082 if (TARGET_LITTLE_ENDIAN
)
2083 fprintf (asm_out_file
, "\t.little\n");
2086 /* Print operand X (an rtx) in assembler syntax to file FILE.
2087 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2088 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2091 m32r_print_operand (FILE * file
, rtx x
, int code
)
2097 /* The 's' and 'p' codes are used by output_block_move() to
2098 indicate post-increment 's'tores and 'p're-increment loads. */
2100 if (GET_CODE (x
) == REG
)
2101 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2103 output_operand_lossage ("invalid operand to %%s code");
2107 if (GET_CODE (x
) == REG
)
2108 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2110 output_operand_lossage ("invalid operand to %%p code");
2114 /* Write second word of DImode or DFmode reference,
2115 register or memory. */
2116 if (GET_CODE (x
) == REG
)
2117 fputs (reg_names
[REGNO (x
)+1], file
);
2118 else if (GET_CODE (x
) == MEM
)
2120 fprintf (file
, "@(");
2121 /* Handle possible auto-increment. Since it is pre-increment and
2122 we have already done it, we can just use an offset of four. */
2123 /* ??? This is taken from rs6000.c I think. I don't think it is
2124 currently necessary, but keep it around. */
2125 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2126 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2127 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
2129 output_address (plus_constant (XEXP (x
, 0), 4));
2133 output_operand_lossage ("invalid operand to %%R code");
2136 case 'H' : /* High word. */
2137 case 'L' : /* Low word. */
2138 if (GET_CODE (x
) == REG
)
2140 /* L = least significant word, H = most significant word. */
2141 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2142 fputs (reg_names
[REGNO (x
)], file
);
2144 fputs (reg_names
[REGNO (x
)+1], file
);
2146 else if (GET_CODE (x
) == CONST_INT
2147 || GET_CODE (x
) == CONST_DOUBLE
)
2151 split_double (x
, &first
, &second
);
2152 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2153 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2156 output_operand_lossage ("invalid operand to %%H/%%L code");
2163 if (GET_CODE (x
) != CONST_DOUBLE
2164 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2165 fatal_insn ("bad insn for 'A'", x
);
2167 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2168 fprintf (file
, "%s", str
);
2172 case 'B' : /* Bottom half. */
2173 case 'T' : /* Top half. */
2174 /* Output the argument to a `seth' insn (sets the Top half-word).
2175 For constants output arguments to a seth/or3 pair to set Top and
2176 Bottom halves. For symbols output arguments to a seth/add3 pair to
2177 set Top and Bottom halves. The difference exists because for
2178 constants seth/or3 is more readable but for symbols we need to use
2179 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2180 switch (GET_CODE (x
))
2187 split_double (x
, &first
, &second
);
2188 x
= WORDS_BIG_ENDIAN
? second
: first
;
2189 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2191 ? INTVAL (x
) & 0xffff
2192 : (INTVAL (x
) >> 16) & 0xffff));
2198 && small_data_operand (x
, VOIDmode
))
2200 fputs ("sda(", file
);
2201 output_addr_const (file
, x
);
2207 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2208 output_addr_const (file
, x
);
2212 output_operand_lossage ("invalid operand to %%T/%%B code");
2219 /* Output a load/store with update indicator if appropriate. */
2220 if (GET_CODE (x
) == MEM
)
2222 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2223 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2227 output_operand_lossage ("invalid operand to %%U code");
2231 /* Print a constant value negated. */
2232 if (GET_CODE (x
) == CONST_INT
)
2233 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2235 output_operand_lossage ("invalid operand to %%N code");
2239 /* Print a const_int in hex. Used in comments. */
2240 if (GET_CODE (x
) == CONST_INT
)
2241 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2245 fputs (IMMEDIATE_PREFIX
, file
);
2249 /* Do nothing special. */
2254 output_operand_lossage ("invalid operand output code");
2257 switch (GET_CODE (x
))
2260 fputs (reg_names
[REGNO (x
)], file
);
2265 if (GET_CODE (addr
) == PRE_INC
)
2267 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2268 fatal_insn ("pre-increment address is not a register", x
);
2270 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2272 else if (GET_CODE (addr
) == PRE_DEC
)
2274 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2275 fatal_insn ("pre-decrement address is not a register", x
);
2277 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2279 else if (GET_CODE (addr
) == POST_INC
)
2281 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2282 fatal_insn ("post-increment address is not a register", x
);
2284 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2289 output_address (XEXP (x
, 0));
2295 /* We handle SFmode constants here as output_addr_const doesn't. */
2296 if (GET_MODE (x
) == SFmode
)
2301 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2302 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2303 fprintf (file
, "0x%08lx", l
);
2307 /* Fall through. Let output_addr_const deal with it. */
2310 output_addr_const (file
, x
);
2315 /* Print a memory address as an operand to reference that memory location. */
2318 m32r_print_operand_address (FILE * file
, rtx addr
)
2324 switch (GET_CODE (addr
))
2327 fputs (reg_names
[REGNO (addr
)], file
);
2331 if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
2332 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2333 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2334 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2336 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2337 if (GET_CODE (base
) == REG
)
2339 /* Print the offset first (if present) to conform to the manual. */
2343 fprintf (file
, "%d,", offset
);
2344 fputs (reg_names
[REGNO (base
)], file
);
2346 /* The chip doesn't support this, but left in for generality. */
2347 else if (GET_CODE (index
) == REG
)
2348 fprintf (file
, "%s,%s",
2349 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2350 /* Not sure this can happen, but leave in for now. */
2351 else if (GET_CODE (index
) == SYMBOL_REF
)
2353 output_addr_const (file
, index
);
2355 fputs (reg_names
[REGNO (base
)], file
);
2358 fatal_insn ("bad address", addr
);
2360 else if (GET_CODE (base
) == LO_SUM
)
2363 || GET_CODE (XEXP (base
, 0)) != REG
)
2365 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2366 fputs ("sda(", file
);
2368 fputs ("low(", file
);
2369 output_addr_const (file
, plus_constant (XEXP (base
, 1), offset
));
2371 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2374 fatal_insn ("bad address", addr
);
2378 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2379 fatal_insn ("lo_sum not of register", addr
);
2380 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2381 fputs ("sda(", file
);
2383 fputs ("low(", file
);
2384 output_addr_const (file
, XEXP (addr
, 1));
2386 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2389 case PRE_INC
: /* Assume SImode. */
2390 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2393 case PRE_DEC
: /* Assume SImode. */
2394 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2397 case POST_INC
: /* Assume SImode. */
2398 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2402 output_addr_const (file
, addr
);
2407 /* Return true if the operands are the constants 0 and 1. */
2410 zero_and_one (rtx operand1
, rtx operand2
)
2413 GET_CODE (operand1
) == CONST_INT
2414 && GET_CODE (operand2
) == CONST_INT
2415 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2416 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2419 /* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2422 conditional_move_operand (rtx operand
, enum machine_mode mode
)
2424 /* Only defined for simple integers so far... */
2425 if (mode
!= SImode
&& mode
!= HImode
&& mode
!= QImode
)
2428 /* At the moment we can handle moving registers and loading constants. */
2429 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2431 switch (GET_CODE (operand
))
2437 return INT8_P (INTVAL (operand
));
2441 fprintf (stderr
, "Test for cond move op of type: %s\n",
2442 GET_RTX_NAME (GET_CODE (operand
)));
2448 /* Return true if the code is a test of the carry bit. */
2451 carry_compare_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2455 if (GET_MODE (op
) != CCmode
&& GET_MODE (op
) != VOIDmode
)
2458 if (GET_CODE (op
) != NE
&& GET_CODE (op
) != EQ
)
2462 if (GET_CODE (x
) != REG
|| REGNO (x
) != CARRY_REGNUM
)
2466 if (GET_CODE (x
) != CONST_INT
|| INTVAL (x
) != 0)
2472 /* Generate the correct assembler code to handle the conditional loading of a
2473 value into a register. It is known that the operands satisfy the
2474 conditional_move_operand() function above. The destination is operand[0].
2475 The condition is operand [1]. The 'true' value is operand [2] and the
2476 'false' value is operand [3]. */
2479 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2481 static char buffer
[100];
2482 const char * dest
= reg_names
[REGNO (operands
[0])];
2486 /* Destination must be a register. */
2487 if (GET_CODE (operands
[0]) != REG
)
2489 if (! conditional_move_operand (operands
[2], SImode
))
2491 if (! conditional_move_operand (operands
[3], SImode
))
2494 /* Check to see if the test is reversed. */
2495 if (GET_CODE (operands
[1]) == NE
)
2497 rtx tmp
= operands
[2];
2498 operands
[2] = operands
[3];
2502 sprintf (buffer
, "mvfc %s, cbr", dest
);
2504 /* If the true value was '0' then we need to invert the results of the move. */
2505 if (INTVAL (operands
[2]) == 0)
2506 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2512 /* Returns true if the registers contained in the two
2513 rtl expressions are different. */
2516 m32r_not_same_reg (rtx a
, rtx b
)
2521 while (GET_CODE (a
) == SUBREG
)
2524 if (GET_CODE (a
) == REG
)
2527 while (GET_CODE (b
) == SUBREG
)
2530 if (GET_CODE (b
) == REG
)
2533 return reg_a
!= reg_b
;
2538 m32r_function_symbol (const char *name
)
2540 int extra_flags
= 0;
2541 enum m32r_model model
;
2542 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2544 if (TARGET_MODEL_SMALL
)
2545 model
= M32R_MODEL_SMALL
;
2546 else if (TARGET_MODEL_MEDIUM
)
2547 model
= M32R_MODEL_MEDIUM
;
2548 else if (TARGET_MODEL_LARGE
)
2549 model
= M32R_MODEL_LARGE
;
2551 abort (); /* Shouldn't happen. */
2552 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2555 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2560 /* Use a library function to move some bytes. */
2563 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2565 /* We want to pass the size as Pmode, which will normally be SImode
2566 but will be DImode if we are using 64 bit longs and pointers. */
2567 if (GET_MODE (bytes_rtx
) != VOIDmode
2568 && GET_MODE (bytes_rtx
) != Pmode
)
2569 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2571 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2572 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2573 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2574 TYPE_UNSIGNED (sizetype
)),
2575 TYPE_MODE (sizetype
));
2578 /* The maximum number of bytes to copy using pairs of load/store instructions.
2579 If a block is larger than this then a loop will be generated to copy
2580 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
2581 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2582 string copy in it. */
2583 #define MAX_MOVE_BYTES 32
2585 /* Expand string/block move operations.
2587 operands[0] is the pointer to the destination.
2588 operands[1] is the pointer to the source.
2589 operands[2] is the number of bytes to move.
2590 operands[3] is the alignment. */
2593 m32r_expand_block_move (rtx operands
[])
2595 rtx orig_dst
= operands
[0];
2596 rtx orig_src
= operands
[1];
2597 rtx bytes_rtx
= operands
[2];
2598 rtx align_rtx
= operands
[3];
2599 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
2600 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2601 int align
= INTVAL (align_rtx
);
2606 if (constp
&& bytes
<= 0)
2609 /* Move the address into scratch registers. */
2610 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2611 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2613 if (align
> UNITS_PER_WORD
)
2614 align
= UNITS_PER_WORD
;
2616 /* If we prefer size over speed, always use a function call.
2617 If we do not know the size, use a function call.
2618 If the blocks are not word aligned, use a function call. */
2619 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2621 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2625 leftover
= bytes
% MAX_MOVE_BYTES
;
2628 /* If necessary, generate a loop to handle the bulk of the copy. */
2631 rtx label
= NULL_RTX
;
2632 rtx final_src
= NULL_RTX
;
2633 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2634 rtx rounded_total
= GEN_INT (bytes
);
2635 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2636 rtx new_src_reg
= gen_reg_rtx (SImode
);
2638 /* If we are going to have to perform this loop more than
2639 once, then generate a label and compute the address the
2640 source register will contain upon completion of the final
2642 if (bytes
> MAX_MOVE_BYTES
)
2644 final_src
= gen_reg_rtx (Pmode
);
2647 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2650 emit_insn (gen_movsi (final_src
, rounded_total
));
2651 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2654 label
= gen_label_rtx ();
2658 /* It is known that output_block_move() will update src_reg to point
2659 to the word after the end of the source block, and dst_reg to point
2660 to the last word of the destination block, provided that the block
2661 is MAX_MOVE_BYTES long. */
2662 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2663 new_dst_reg
, new_src_reg
));
2664 emit_move_insn (dst_reg
, new_dst_reg
);
2665 emit_move_insn (src_reg
, new_src_reg
);
2666 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2668 if (bytes
> MAX_MOVE_BYTES
)
2670 emit_insn (gen_cmpsi (src_reg
, final_src
));
2671 emit_jump_insn (gen_bne (label
));
2676 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2677 gen_reg_rtx (SImode
),
2678 gen_reg_rtx (SImode
)));
2682 /* Emit load/stores for a small constant word aligned block_move.
2684 operands[0] is the memory address of the destination.
2685 operands[1] is the memory address of the source.
2686 operands[2] is the number of bytes to move.
2687 operands[3] is a temp register.
2688 operands[4] is a temp register. */
2691 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2693 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2697 if (bytes
< 1 || bytes
> MAX_MOVE_BYTES
)
2700 /* We do not have a post-increment store available, so the first set of
2701 stores are done without any increment, then the remaining ones can use
2702 the pre-increment addressing mode.
2704 Note: expand_block_move() also relies upon this behavior when building
2705 loops to copy large blocks. */
2714 output_asm_insn ("ld\t%5, %p1", operands
);
2715 output_asm_insn ("ld\t%6, %p1", operands
);
2716 output_asm_insn ("st\t%5, @%0", operands
);
2717 output_asm_insn ("st\t%6, %s0", operands
);
2721 output_asm_insn ("ld\t%5, %p1", operands
);
2722 output_asm_insn ("ld\t%6, %p1", operands
);
2723 output_asm_insn ("st\t%5, %s0", operands
);
2724 output_asm_insn ("st\t%6, %s0", operands
);
2729 else if (bytes
>= 4)
2734 output_asm_insn ("ld\t%5, %p1", operands
);
2737 output_asm_insn ("ld\t%6, %p1", operands
);
2740 output_asm_insn ("st\t%5, @%0", operands
);
2742 output_asm_insn ("st\t%5, %s0", operands
);
2748 /* Get the entire next word, even though we do not want all of it.
2749 The saves us from doing several smaller loads, and we assume that
2750 we cannot cause a page fault when at least part of the word is in
2751 valid memory [since we don't get called if things aren't properly
2753 int dst_offset
= first_time
? 0 : 4;
2754 /* The amount of increment we have to make to the
2755 destination pointer. */
2756 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2757 /* The same for the source pointer. */
2758 int src_inc_amount
= bytes
;
2762 /* If got_extra is true then we have already loaded
2763 the next word as part of loading and storing the previous word. */
2765 output_asm_insn ("ld\t%6, @%1", operands
);
2771 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2772 my_operands
[0] = operands
[5];
2773 my_operands
[1] = GEN_INT (dst_offset
);
2774 my_operands
[2] = operands
[0];
2775 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2777 /* If there is a byte left to store then increment the
2778 destination address and shift the contents of the source
2779 register down by 8 bits. We could not do the address
2780 increment in the store half word instruction, because it does
2781 not have an auto increment mode. */
2782 if (bytes
> 0) /* assert (bytes == 1) */
2793 my_operands
[0] = operands
[6];
2794 my_operands
[1] = GEN_INT (last_shift
);
2795 output_asm_insn ("srai\t%0, #%1", my_operands
);
2796 my_operands
[0] = operands
[6];
2797 my_operands
[1] = GEN_INT (dst_offset
);
2798 my_operands
[2] = operands
[0];
2799 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2802 /* Update the destination pointer if needed. We have to do
2803 this so that the patterns matches what we output in this
2806 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2808 my_operands
[0] = operands
[0];
2809 my_operands
[1] = GEN_INT (dst_inc_amount
);
2810 output_asm_insn ("addi\t%0, #%1", my_operands
);
2813 /* Update the source pointer if needed. We have to do this
2814 so that the patterns matches what we output in this
2817 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2819 my_operands
[0] = operands
[1];
2820 my_operands
[1] = GEN_INT (src_inc_amount
);
2821 output_asm_insn ("addi\t%0, #%1", my_operands
);
2831 /* Return true if op is an integer constant, less than or equal to
2835 m32r_block_immediate_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2837 if (GET_CODE (op
) != CONST_INT
2838 || INTVAL (op
) > MAX_MOVE_BYTES
2839 || INTVAL (op
) <= 0)
2845 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2848 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2849 unsigned int new_reg
)
2851 /* Interrupt routines can't clobber any register that isn't already used. */
2852 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2853 && !regs_ever_live
[new_reg
])
2856 /* We currently emit epilogues as text, not rtl, so the liveness
2857 of the return address register isn't visible. */
2858 if (current_function_is_leaf
&& new_reg
== RETURN_ADDR_REGNUM
)
2865 m32r_return_addr (int count
)
2870 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);