1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static unsigned long thumb_compute_save_reg_mask (void);
75 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
76 static rtx
emit_multi_reg_push (int);
77 static rtx
emit_sfm (int, int);
79 static bool arm_assemble_integer (rtx
, unsigned int, int);
81 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
82 static arm_cc
get_arm_condition_code (rtx
);
83 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
84 static rtx
is_jump_table (rtx
);
85 static const char *output_multi_immediate (rtx
*, const char *, const char *,
87 static void print_multi_reg (FILE *, const char *, int, int);
88 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
89 static struct machine_function
*arm_init_machine_status (void);
90 static int number_of_first_bit_set (int);
91 static void replace_symbols_in_block (tree
, rtx
, rtx
);
92 static void thumb_exit (FILE *, int);
93 static void thumb_pushpop (FILE *, int, int, int *, int);
94 static rtx
is_jump_table (rtx
);
95 static HOST_WIDE_INT
get_jump_table_size (rtx
);
96 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
97 static Mnode
*add_minipool_forward_ref (Mfix
*);
98 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
99 static Mnode
*add_minipool_backward_ref (Mfix
*);
100 static void assign_minipool_offsets (Mfix
*);
101 static void arm_print_value (FILE *, rtx
);
102 static void dump_minipool (rtx
);
103 static int arm_barrier_cost (rtx
);
104 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
105 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
106 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
108 static void arm_reorg (void);
109 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
110 static int current_file_function_operand (rtx
);
111 static unsigned long arm_compute_save_reg0_reg12_mask (void);
112 static unsigned long arm_compute_save_reg_mask (void);
113 static unsigned long arm_isr_value (tree
);
114 static unsigned long arm_compute_func_type (void);
115 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
116 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
119 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
120 static int arm_comp_type_attributes (tree
, tree
);
121 static void arm_set_default_type_attributes (tree
);
122 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
123 static int count_insns_for_constant (HOST_WIDE_INT
, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree
, tree
);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
129 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
130 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
132 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
133 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
134 static int arm_address_cost (rtx
);
135 static bool arm_memory_load_p (rtx
);
136 static bool arm_cirrus_insn_p (rtx
);
137 static void cirrus_reorg (rtx
);
138 static void arm_init_builtins (void);
139 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
140 static void arm_init_iwmmxt_builtins (void);
141 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
142 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
143 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
144 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
145 static void emit_constant_insn (rtx cond
, rtx pattern
);
147 #ifdef OBJECT_FORMAT_ELF
148 static void arm_elf_asm_named_section (const char *, unsigned int);
151 static void arm_encode_section_info (tree
, rtx
, int);
154 static void aof_globalize_label (FILE *, const char *);
155 static void aof_dump_imports (FILE *);
156 static void aof_dump_pic_table (FILE *);
157 static void aof_file_start (void);
158 static void aof_file_end (void);
160 static rtx
arm_struct_value_rtx (tree
, int);
161 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
163 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
164 enum machine_mode
, tree
, bool);
165 static bool arm_promote_prototypes (tree
);
166 static bool arm_default_short_enums (void);
167 static bool arm_align_anon_bitfield (void);
169 static tree
arm_cxx_guard_type (void);
170 static bool arm_cxx_guard_mask_bit (void);
171 static tree
arm_get_cookie_size (tree
);
172 static bool arm_cookie_has_size (void);
173 static bool arm_cxx_cdtor_returns_this (void);
174 static void arm_init_libfuncs (void);
177 /* Initialize the GCC target structure. */
178 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
179 #undef TARGET_MERGE_DECL_ATTRIBUTES
180 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
183 #undef TARGET_ATTRIBUTE_TABLE
184 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
187 #undef TARGET_ASM_BYTE_OP
188 #define TARGET_ASM_BYTE_OP "\tDCB\t"
189 #undef TARGET_ASM_ALIGNED_HI_OP
190 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
191 #undef TARGET_ASM_ALIGNED_SI_OP
192 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
193 #undef TARGET_ASM_GLOBALIZE_LABEL
194 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
195 #undef TARGET_ASM_FILE_START
196 #define TARGET_ASM_FILE_START aof_file_start
197 #undef TARGET_ASM_FILE_END
198 #define TARGET_ASM_FILE_END aof_file_end
200 #undef TARGET_ASM_ALIGNED_SI_OP
201 #define TARGET_ASM_ALIGNED_SI_OP NULL
202 #undef TARGET_ASM_INTEGER
203 #define TARGET_ASM_INTEGER arm_assemble_integer
206 #undef TARGET_ASM_FUNCTION_PROLOGUE
207 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
209 #undef TARGET_ASM_FUNCTION_EPILOGUE
210 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
212 #undef TARGET_COMP_TYPE_ATTRIBUTES
213 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
215 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
216 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
218 #undef TARGET_SCHED_ADJUST_COST
219 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
221 #undef TARGET_ENCODE_SECTION_INFO
223 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
225 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
228 #undef TARGET_STRIP_NAME_ENCODING
229 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
231 #undef TARGET_ASM_INTERNAL_LABEL
232 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
234 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
235 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
237 #undef TARGET_ASM_OUTPUT_MI_THUNK
238 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
239 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
240 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
242 /* This will be overridden in arm_override_options. */
243 #undef TARGET_RTX_COSTS
244 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
245 #undef TARGET_ADDRESS_COST
246 #define TARGET_ADDRESS_COST arm_address_cost
248 #undef TARGET_MACHINE_DEPENDENT_REORG
249 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
251 #undef TARGET_INIT_BUILTINS
252 #define TARGET_INIT_BUILTINS arm_init_builtins
253 #undef TARGET_EXPAND_BUILTIN
254 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
256 #undef TARGET_INIT_LIBFUNCS
257 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
259 #undef TARGET_PROMOTE_FUNCTION_ARGS
260 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
261 #undef TARGET_PROMOTE_FUNCTION_RETURN
262 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
263 #undef TARGET_PROMOTE_PROTOTYPES
264 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
265 #undef TARGET_PASS_BY_REFERENCE
266 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
268 #undef TARGET_STRUCT_VALUE_RTX
269 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
271 #undef TARGET_SETUP_INCOMING_VARARGS
272 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
274 #undef TARGET_DEFAULT_SHORT_ENUMS
275 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
277 #undef TARGET_ALIGN_ANON_BITFIELD
278 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
280 #undef TARGET_CXX_GUARD_TYPE
281 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
283 #undef TARGET_CXX_GUARD_MASK_BIT
284 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
286 #undef TARGET_CXX_GET_COOKIE_SIZE
287 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
289 #undef TARGET_CXX_COOKIE_HAS_SIZE
290 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
292 #undef TARGET_CXX_CDTOR_RETURNS_THIS
293 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
295 struct gcc_target targetm
= TARGET_INITIALIZER
;
297 /* Obstack for minipool constant handling. */
298 static struct obstack minipool_obstack
;
299 static char * minipool_startobj
;
301 /* The maximum number of insns skipped which
302 will be conditionalised if possible. */
303 static int max_insns_skipped
= 5;
305 extern FILE * asm_out_file
;
307 /* True if we are currently building a constant table. */
308 int making_const_table
;
310 /* Define the information needed to generate branch insns. This is
311 stored from the compare operation. */
312 rtx arm_compare_op0
, arm_compare_op1
;
314 /* The processor for which instructions should be scheduled. */
315 enum processor_type arm_tune
= arm_none
;
317 /* Which floating point model to use. */
318 enum arm_fp_model arm_fp_model
;
320 /* Which floating point hardware is available. */
321 enum fputype arm_fpu_arch
;
323 /* Which floating point hardware to schedule for. */
324 enum fputype arm_fpu_tune
;
326 /* Whether to use floating point hardware. */
327 enum float_abi_type arm_float_abi
;
329 /* Which ABI to use. */
330 enum arm_abi_type arm_abi
;
332 /* Set by the -mfpu=... option. */
333 const char * target_fpu_name
= NULL
;
335 /* Set by the -mfpe=... option. */
336 const char * target_fpe_name
= NULL
;
338 /* Set by the -mfloat-abi=... option. */
339 const char * target_float_abi_name
= NULL
;
341 /* Set by the -mabi=... option. */
342 const char * target_abi_name
= NULL
;
344 /* Used to parse -mstructure_size_boundary command line option. */
345 const char * structure_size_string
= NULL
;
346 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
348 /* Bit values used to identify processor capabilities. */
349 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
350 #define FL_ARCH3M (1 << 1) /* Extended multiply */
351 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
352 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
353 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
354 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
355 #define FL_THUMB (1 << 6) /* Thumb aware */
356 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
357 #define FL_STRONG (1 << 8) /* StrongARM */
358 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
359 #define FL_XSCALE (1 << 10) /* XScale */
360 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
361 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
362 media instructions. */
363 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
365 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
367 #define FL_FOR_ARCH2 0
368 #define FL_FOR_ARCH3 FL_MODE32
369 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
370 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
371 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
372 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
373 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
374 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
375 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
376 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
377 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
378 #define FL_FOR_ARCH6J FL_FOR_ARCH6
380 /* The bits in this mask specify which
381 instructions we are allowed to generate. */
382 static unsigned long insn_flags
= 0;
384 /* The bits in this mask specify which instruction scheduling options should
386 static unsigned long tune_flags
= 0;
388 /* The following are used in the arm.md file as equivalents to bits
389 in the above two flag variables. */
391 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
394 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
397 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
400 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
403 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
406 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
409 /* Nonzero if this chip can benefit from load scheduling. */
410 int arm_ld_sched
= 0;
412 /* Nonzero if this chip is a StrongARM. */
413 int arm_is_strong
= 0;
415 /* Nonzero if this chip is a Cirrus variant. */
416 int arm_arch_cirrus
= 0;
418 /* Nonzero if this chip supports Intel Wireless MMX technology. */
419 int arm_arch_iwmmxt
= 0;
421 /* Nonzero if this chip is an XScale. */
422 int arm_arch_xscale
= 0;
424 /* Nonzero if tuning for XScale */
425 int arm_tune_xscale
= 0;
427 /* Nonzero if this chip is an ARM6 or an ARM7. */
428 int arm_is_6_or_7
= 0;
430 /* Nonzero if generating Thumb instructions. */
433 /* Nonzero if we should define __THUMB_INTERWORK__ in the
435 XXX This is a bit of a hack, it's intended to help work around
436 problems in GLD which doesn't understand that armv5t code is
437 interworking clean. */
438 int arm_cpp_interwork
= 0;
440 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
441 must report the mode of the memory reference from PRINT_OPERAND to
442 PRINT_OPERAND_ADDRESS. */
443 enum machine_mode output_memory_reference_mode
;
445 /* The register number to be used for the PIC offset register. */
446 const char * arm_pic_register_string
= NULL
;
447 int arm_pic_register
= INVALID_REGNUM
;
449 /* Set to 1 when a return insn is output, this means that the epilogue
451 int return_used_this_function
;
453 /* Set to 1 after arm_reorg has started. Reset to start at the start of
454 the next function. */
455 static int after_arm_reorg
= 0;
457 /* The maximum number of insns to be used when loading a constant. */
458 static int arm_constant_limit
= 3;
460 /* For an explanation of these variables, see final_prescan_insn below. */
462 enum arm_cond_code arm_current_cc
;
464 int arm_target_label
;
466 /* The condition codes of the ARM, and the inverse function. */
467 static const char * const arm_condition_codes
[] =
469 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
470 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
473 #define streq(string1, string2) (strcmp (string1, string2) == 0)
475 /* Initialization code. */
479 const char *const name
;
480 enum processor_type core
;
482 const unsigned long flags
;
483 bool (* rtx_costs
) (rtx
, int, int, int *);
486 /* Not all of these give usefully different compilation alternatives,
487 but there is no simple way of generalizing them. */
488 static const struct processors all_cores
[] =
491 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
492 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
493 #include "arm-cores.def"
495 {NULL
, arm_none
, NULL
, 0, NULL
}
498 static const struct processors all_architectures
[] =
500 /* ARM Architectures */
501 /* We don't specify rtx_costs here as it will be figured out
504 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
505 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
506 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
507 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
508 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
509 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
510 implementations that support it, so we will leave it out for now. */
511 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
512 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
513 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
514 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
515 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
516 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
517 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
518 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
519 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
520 {NULL
, arm_none
, NULL
, 0 , NULL
}
523 /* This is a magic structure. The 'string' field is magically filled in
524 with a pointer to the value specified by the user on the command line
525 assuming that the user has specified such a value. */
527 struct arm_cpu_select arm_select
[] =
529 /* string name processors */
530 { NULL
, "-mcpu=", all_cores
},
531 { NULL
, "-march=", all_architectures
},
532 { NULL
, "-mtune=", all_cores
}
536 /* The name of the proprocessor macro to define for this architecture. */
538 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
547 /* Available values for for -mfpu=. */
549 static const struct fpu_desc all_fpus
[] =
551 {"fpa", FPUTYPE_FPA
},
552 {"fpe2", FPUTYPE_FPA_EMU2
},
553 {"fpe3", FPUTYPE_FPA_EMU2
},
554 {"maverick", FPUTYPE_MAVERICK
},
559 /* Floating point models used by the different hardware.
560 See fputype in arm.h. */
562 static const enum fputype fp_model_for_fpu
[] =
564 /* No FP hardware. */
565 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
566 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
567 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
568 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
569 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
570 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
577 enum float_abi_type abi_type
;
581 /* Available values for -mfloat-abi=. */
583 static const struct float_abi all_float_abis
[] =
585 {"soft", ARM_FLOAT_ABI_SOFT
},
586 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
587 {"hard", ARM_FLOAT_ABI_HARD
}
594 enum arm_abi_type abi_type
;
598 /* Available values for -mabi=. */
600 static const struct abi_name arm_all_abis
[] =
602 {"apcs-gnu", ARM_ABI_APCS
},
603 {"atpcs", ARM_ABI_ATPCS
},
604 {"aapcs", ARM_ABI_AAPCS
},
605 {"iwmmxt", ARM_ABI_IWMMXT
}
608 /* Return the number of bits set in VALUE. */
610 bit_count (unsigned long value
)
612 unsigned long count
= 0;
617 value
&= value
- 1; /* Clear the least-significant set bit. */
623 /* Set up library functions uqniue to ARM. */
626 arm_init_libfuncs (void)
628 /* There are no special library functions unless we are using the
633 /* The functions below are described in Section 4 of the "Run-Time
634 ABI for the ARM architecture", Version 1.0. */
636 /* Double-precision floating-point arithmetic. Table 2. */
637 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
638 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
639 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
640 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
641 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
643 /* Double-precision comparisions. Table 3. */
644 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
645 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
646 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
647 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
648 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
649 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
650 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
652 /* Single-precision floating-point arithmetic. Table 4. */
653 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
654 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
655 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
656 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
657 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
659 /* Single-precision comparisions. Table 5. */
660 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
661 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
662 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
663 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
664 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
665 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
666 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
668 /* Floating-point to integer conversions. Table 6. */
669 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
670 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
671 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
672 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
673 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
674 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
675 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
676 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
678 /* Conversions between floating types. Table 7. */
679 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
680 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
682 /* Integer to floating-point converisons. Table 8. */
683 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
684 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
685 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
686 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
687 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
688 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
689 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
690 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
692 /* Long long. Table 9. */
693 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
694 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
695 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
696 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
697 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
698 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
699 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
700 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
702 /* Integer (32/32->32) division. \S 4.3.1. */
703 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
704 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
706 /* The divmod functions are designed so that they can be used for
707 plain division, even though they return both the quotient and the
708 remainder. The quotient is returned in the usual location (i.e.,
709 r0 for SImode, {r0, r1} for DImode), just as would be expected
710 for an ordinary division routine. Because the AAPCS calling
711 conventions specify that all of { r0, r1, r2, r3 } are
712 callee-saved registers, there is no need to tell the compiler
713 explicitly that those registers are clobbered by these
715 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
716 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
717 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idivmod");
718 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidivmod");
721 /* Fix up any incompatible options that the user has specified.
722 This has now turned into a maze. */
724 arm_override_options (void)
728 /* Set up the flags based on the cpu/architecture selected by the user. */
729 for (i
= ARRAY_SIZE (arm_select
); i
--;)
731 struct arm_cpu_select
* ptr
= arm_select
+ i
;
733 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
735 const struct processors
* sel
;
737 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
738 if (streq (ptr
->string
, sel
->name
))
740 /* Set the architecture define. */
742 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
744 /* Determine the processor core for which we should
745 tune code-generation. */
746 if (/* -mcpu= is a sensible default. */
748 /* If -march= is used, and -mcpu= has not been used,
749 assume that we should tune for a representative
750 CPU from that architecture. */
752 /* -mtune= overrides -mcpu= and -march=. */
754 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
758 /* If we have been given an architecture and a processor
759 make sure that they are compatible. We only generate
760 a warning though, and we prefer the CPU over the
762 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
763 warning ("switch -mcpu=%s conflicts with -march= switch",
766 insn_flags
= sel
->flags
;
772 if (sel
->name
== NULL
)
773 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
777 /* If the user did not specify a processor, choose one for them. */
780 const struct processors
* sel
;
782 enum processor_type cpu
;
784 cpu
= TARGET_CPU_DEFAULT
;
787 #ifdef SUBTARGET_CPU_DEFAULT
788 /* Use the subtarget default CPU if none was specified by
790 cpu
= SUBTARGET_CPU_DEFAULT
;
792 /* Default to ARM6. */
796 sel
= &all_cores
[cpu
];
798 insn_flags
= sel
->flags
;
800 /* Now check to see if the user has specified some command line
801 switch that require certain abilities from the cpu. */
804 if (TARGET_INTERWORK
|| TARGET_THUMB
)
806 sought
|= (FL_THUMB
| FL_MODE32
);
808 /* There are no ARM processors that support both APCS-26 and
809 interworking. Therefore we force FL_MODE26 to be removed
810 from insn_flags here (if it was set), so that the search
811 below will always be able to find a compatible processor. */
812 insn_flags
&= ~FL_MODE26
;
815 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
817 /* Try to locate a CPU type that supports all of the abilities
818 of the default CPU, plus the extra abilities requested by
820 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
821 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
824 if (sel
->name
== NULL
)
826 unsigned current_bit_count
= 0;
827 const struct processors
* best_fit
= NULL
;
829 /* Ideally we would like to issue an error message here
830 saying that it was not possible to find a CPU compatible
831 with the default CPU, but which also supports the command
832 line options specified by the programmer, and so they
833 ought to use the -mcpu=<name> command line option to
834 override the default CPU type.
836 If we cannot find a cpu that has both the
837 characteristics of the default cpu and the given
838 command line options we scan the array again looking
840 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
841 if ((sel
->flags
& sought
) == sought
)
845 count
= bit_count (sel
->flags
& insn_flags
);
847 if (count
>= current_bit_count
)
850 current_bit_count
= count
;
854 if (best_fit
== NULL
)
860 insn_flags
= sel
->flags
;
862 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
863 if (arm_tune
== arm_none
)
864 arm_tune
= (enum processor_type
) (sel
- all_cores
);
867 /* The processor for which we should tune should now have been
869 if (arm_tune
== arm_none
)
872 tune_flags
= all_cores
[(int)arm_tune
].flags
;
873 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
875 /* Make sure that the processor choice does not conflict with any of the
876 other command line choices. */
877 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
879 warning ("target CPU does not support interworking" );
880 target_flags
&= ~ARM_FLAG_INTERWORK
;
883 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
885 warning ("target CPU does not support THUMB instructions");
886 target_flags
&= ~ARM_FLAG_THUMB
;
889 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
891 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
892 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
895 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
896 from here where no function is being compiled currently. */
897 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
899 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
901 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
902 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
904 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
905 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
907 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
909 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
910 target_flags
|= ARM_FLAG_APCS_FRAME
;
913 if (TARGET_POKE_FUNCTION_NAME
)
914 target_flags
|= ARM_FLAG_APCS_FRAME
;
916 if (TARGET_APCS_REENT
&& flag_pic
)
917 error ("-fpic and -mapcs-reent are incompatible");
919 if (TARGET_APCS_REENT
)
920 warning ("APCS reentrant code not supported. Ignored");
922 /* If this target is normally configured to use APCS frames, warn if they
923 are turned off and debugging is turned on. */
925 && write_symbols
!= NO_DEBUG
926 && !TARGET_APCS_FRAME
927 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
928 warning ("-g with -mno-apcs-frame may not give sensible debugging");
930 /* If stack checking is disabled, we can use r10 as the PIC register,
931 which keeps r9 available. */
933 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
935 if (TARGET_APCS_FLOAT
)
936 warning ("passing floating point arguments in fp regs not yet supported");
938 /* Initialize boolean versions of the flags, for use in the arm.md file. */
939 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
940 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
941 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
942 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
943 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
944 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
945 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
946 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
948 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
949 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
950 thumb_code
= (TARGET_ARM
== 0);
951 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
952 && !(tune_flags
& FL_ARCH4
))) != 0;
953 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
954 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
956 /* V5 code we generate is completely interworking capable, so we turn off
957 TARGET_INTERWORK here to avoid many tests later on. */
959 /* XXX However, we must pass the right pre-processor defines to CPP
960 or GLD can get confused. This is a hack. */
961 if (TARGET_INTERWORK
)
962 arm_cpp_interwork
= 1;
965 target_flags
&= ~ARM_FLAG_INTERWORK
;
969 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
971 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
973 arm_abi
= arm_all_abis
[i
].abi_type
;
977 if (i
== ARRAY_SIZE (arm_all_abis
))
978 error ("invalid ABI option: -mabi=%s", target_abi_name
);
981 arm_abi
= ARM_DEFAULT_ABI
;
983 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
984 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
986 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
987 error ("iwmmxt abi requires an iwmmxt capable cpu");
989 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
990 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
992 if (streq (target_fpe_name
, "2"))
993 target_fpu_name
= "fpe2";
994 else if (streq (target_fpe_name
, "3"))
995 target_fpu_name
= "fpe3";
997 error ("invalid floating point emulation option: -mfpe=%s",
1000 if (target_fpu_name
!= NULL
)
1002 /* The user specified a FPU. */
1003 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1005 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1007 arm_fpu_arch
= all_fpus
[i
].fpu
;
1008 arm_fpu_tune
= arm_fpu_arch
;
1009 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1013 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1014 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1018 #ifdef FPUTYPE_DEFAULT
1019 /* Use the default if it is specified for this platform. */
1020 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1021 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1023 /* Pick one based on CPU type. */
1024 /* ??? Some targets assume FPA is the default.
1025 if ((insn_flags & FL_VFP) != 0)
1026 arm_fpu_arch = FPUTYPE_VFP;
1029 if (arm_arch_cirrus
)
1030 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1032 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1034 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1035 arm_fpu_tune
= FPUTYPE_FPA
;
1037 arm_fpu_tune
= arm_fpu_arch
;
1038 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1039 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1043 if (target_float_abi_name
!= NULL
)
1045 /* The user specified a FP ABI. */
1046 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1048 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1050 arm_float_abi
= all_float_abis
[i
].abi_type
;
1054 if (i
== ARRAY_SIZE (all_float_abis
))
1055 error ("invalid floating point abi: -mfloat-abi=%s",
1056 target_float_abi_name
);
1060 /* Use soft-float target flag. */
1061 if (target_flags
& ARM_FLAG_SOFT_FLOAT
)
1062 arm_float_abi
= ARM_FLOAT_ABI_SOFT
;
1064 arm_float_abi
= ARM_FLOAT_ABI_HARD
;
1067 if (arm_float_abi
== ARM_FLOAT_ABI_SOFTFP
)
1068 sorry ("-mfloat-abi=softfp");
1069 /* If soft-float is specified then don't use FPU. */
1070 if (TARGET_SOFT_FLOAT
)
1071 arm_fpu_arch
= FPUTYPE_NONE
;
1073 /* For arm2/3 there is no need to do any scheduling if there is only
1074 a floating point emulator, or we are doing software floating-point. */
1075 if ((TARGET_SOFT_FLOAT
1076 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1077 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1078 && (tune_flags
& FL_MODE32
) == 0)
1079 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1081 /* Override the default structure alignment for AAPCS ABI. */
1082 if (arm_abi
== ARM_ABI_AAPCS
)
1083 arm_structure_size_boundary
= 8;
1085 if (structure_size_string
!= NULL
)
1087 int size
= strtol (structure_size_string
, NULL
, 0);
1089 if (size
== 8 || size
== 32
1090 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1091 arm_structure_size_boundary
= size
;
1093 warning ("structure size boundary can only be set to %s",
1094 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1097 if (arm_pic_register_string
!= NULL
)
1099 int pic_register
= decode_reg_name (arm_pic_register_string
);
1102 warning ("-mpic-register= is useless without -fpic");
1104 /* Prevent the user from choosing an obviously stupid PIC register. */
1105 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1106 || pic_register
== HARD_FRAME_POINTER_REGNUM
1107 || pic_register
== STACK_POINTER_REGNUM
1108 || pic_register
>= PC_REGNUM
)
1109 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1111 arm_pic_register
= pic_register
;
1114 if (TARGET_THUMB
&& flag_schedule_insns
)
1116 /* Don't warn since it's on by default in -O2. */
1117 flag_schedule_insns
= 0;
1122 /* There's some dispute as to whether this should be 1 or 2. However,
1123 experiments seem to show that in pathological cases a setting of
1124 1 degrades less severely than a setting of 2. This could change if
1125 other parts of the compiler change their behavior. */
1126 arm_constant_limit
= 1;
1128 /* If optimizing for size, bump the number of instructions that we
1129 are prepared to conditionally execute (even on a StrongARM). */
1130 max_insns_skipped
= 6;
1134 /* For processors with load scheduling, it never costs more than
1135 2 cycles to load a constant, and the load scheduler may well
1136 reduce that to 1. */
1137 if (tune_flags
& FL_LDSCHED
)
1138 arm_constant_limit
= 1;
1140 /* On XScale the longer latency of a load makes it more difficult
1141 to achieve a good schedule, so it's faster to synthesize
1142 constants that can be done in two insns. */
1143 if (arm_tune_xscale
)
1144 arm_constant_limit
= 2;
1146 /* StrongARM has early execution of branches, so a sequence
1147 that is worth skipping is shorter. */
1149 max_insns_skipped
= 3;
1152 /* Register global variables with the garbage collector. */
1153 arm_add_gc_roots ();
1157 arm_add_gc_roots (void)
1159 gcc_obstack_init(&minipool_obstack
);
1160 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1163 /* A table of known ARM exception types.
1164 For use with the interrupt function attribute. */
1168 const char *const arg
;
1169 const unsigned long return_value
;
1173 static const isr_attribute_arg isr_attribute_args
[] =
1175 { "IRQ", ARM_FT_ISR
},
1176 { "irq", ARM_FT_ISR
},
1177 { "FIQ", ARM_FT_FIQ
},
1178 { "fiq", ARM_FT_FIQ
},
1179 { "ABORT", ARM_FT_ISR
},
1180 { "abort", ARM_FT_ISR
},
1181 { "ABORT", ARM_FT_ISR
},
1182 { "abort", ARM_FT_ISR
},
1183 { "UNDEF", ARM_FT_EXCEPTION
},
1184 { "undef", ARM_FT_EXCEPTION
},
1185 { "SWI", ARM_FT_EXCEPTION
},
1186 { "swi", ARM_FT_EXCEPTION
},
1187 { NULL
, ARM_FT_NORMAL
}
1190 /* Returns the (interrupt) function type of the current
1191 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1193 static unsigned long
1194 arm_isr_value (tree argument
)
1196 const isr_attribute_arg
* ptr
;
1199 /* No argument - default to IRQ. */
1200 if (argument
== NULL_TREE
)
1203 /* Get the value of the argument. */
1204 if (TREE_VALUE (argument
) == NULL_TREE
1205 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1206 return ARM_FT_UNKNOWN
;
1208 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1210 /* Check it against the list of known arguments. */
1211 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1212 if (streq (arg
, ptr
->arg
))
1213 return ptr
->return_value
;
1215 /* An unrecognized interrupt type. */
1216 return ARM_FT_UNKNOWN
;
1219 /* Computes the type of the current function. */
1221 static unsigned long
1222 arm_compute_func_type (void)
1224 unsigned long type
= ARM_FT_UNKNOWN
;
1228 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
1231 /* Decide if the current function is volatile. Such functions
1232 never return, and many memory cycles can be saved by not storing
1233 register values that will never be needed again. This optimization
1234 was added to speed up context switching in a kernel application. */
1236 && TREE_NOTHROW (current_function_decl
)
1237 && TREE_THIS_VOLATILE (current_function_decl
))
1238 type
|= ARM_FT_VOLATILE
;
1240 if (cfun
->static_chain_decl
!= NULL
)
1241 type
|= ARM_FT_NESTED
;
1243 attr
= DECL_ATTRIBUTES (current_function_decl
);
1245 a
= lookup_attribute ("naked", attr
);
1247 type
|= ARM_FT_NAKED
;
1249 a
= lookup_attribute ("isr", attr
);
1251 a
= lookup_attribute ("interrupt", attr
);
1254 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1256 type
|= arm_isr_value (TREE_VALUE (a
));
1261 /* Returns the type of the current function. */
1264 arm_current_func_type (void)
1266 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1267 cfun
->machine
->func_type
= arm_compute_func_type ();
1269 return cfun
->machine
->func_type
;
1272 /* Return 1 if it is possible to return using a single instruction.
1273 If SIBLING is non-null, this is a test for a return before a sibling
1274 call. SIBLING is the call insn, so we can examine its register usage. */
1277 use_return_insn (int iscond
, rtx sibling
)
1280 unsigned int func_type
;
1281 unsigned long saved_int_regs
;
1282 unsigned HOST_WIDE_INT stack_adjust
;
1283 arm_stack_offsets
*offsets
;
1285 /* Never use a return instruction before reload has run. */
1286 if (!reload_completed
)
1289 func_type
= arm_current_func_type ();
1291 /* Naked functions and volatile functions need special
1293 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1296 /* So do interrupt functions that use the frame pointer. */
1297 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1300 offsets
= arm_get_frame_offsets ();
1301 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1303 /* As do variadic functions. */
1304 if (current_function_pretend_args_size
1305 || cfun
->machine
->uses_anonymous_args
1306 /* Or if the function calls __builtin_eh_return () */
1307 || current_function_calls_eh_return
1308 /* Or if the function calls alloca */
1309 || current_function_calls_alloca
1310 /* Or if there is a stack adjustment. However, if the stack pointer
1311 is saved on the stack, we can use a pre-incrementing stack load. */
1312 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1315 saved_int_regs
= arm_compute_save_reg_mask ();
1317 /* Unfortunately, the insn
1319 ldmib sp, {..., sp, ...}
1321 triggers a bug on most SA-110 based devices, such that the stack
1322 pointer won't be correctly restored if the instruction takes a
1323 page fault. We work around this problem by popping r3 along with
1324 the other registers, since that is never slower than executing
1325 another instruction.
1327 We test for !arm_arch5 here, because code for any architecture
1328 less than this could potentially be run on one of the buggy
1330 if (stack_adjust
== 4 && !arm_arch5
)
1332 /* Validate that r3 is a call-clobbered register (always true in
1333 the default abi) ... */
1334 if (!call_used_regs
[3])
1337 /* ... that it isn't being used for a return value (always true
1338 until we implement return-in-regs), or for a tail-call
1342 if (GET_CODE (sibling
) != CALL_INSN
)
1345 if (find_regno_fusage (sibling
, USE
, 3))
1349 /* ... and that there are no call-saved registers in r0-r2
1350 (always true in the default ABI). */
1351 if (saved_int_regs
& 0x7)
1355 /* Can't be done if interworking with Thumb, and any registers have been
1357 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1360 /* On StrongARM, conditional returns are expensive if they aren't
1361 taken and multiple registers have been stacked. */
1362 if (iscond
&& arm_is_strong
)
1364 /* Conditional return when just the LR is stored is a simple
1365 conditional-load instruction, that's not expensive. */
1366 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1369 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1373 /* If there are saved registers but the LR isn't saved, then we need
1374 two instructions for the return. */
1375 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1378 /* Can't be done if any of the FPA regs are pushed,
1379 since this also requires an insn. */
1380 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1381 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1382 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1385 /* Likewise VFP regs. */
1386 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1387 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1388 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1391 if (TARGET_REALLY_IWMMXT
)
1392 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1393 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1399 /* Return TRUE if int I is a valid immediate ARM constant. */
1402 const_ok_for_arm (HOST_WIDE_INT i
)
1404 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1406 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1407 be all zero, or all one. */
1408 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1409 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1410 != ((~(unsigned HOST_WIDE_INT
) 0)
1411 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1414 /* Fast return for 0 and powers of 2 */
1415 if ((i
& (i
- 1)) == 0)
1420 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1423 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1424 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1426 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1431 /* Return true if I is a valid constant for the operation CODE. */
1433 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1435 if (const_ok_for_arm (i
))
1441 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1443 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1449 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1456 /* Emit a sequence of insns to handle a large constant.
1457 CODE is the code of the operation required, it can be any of SET, PLUS,
1458 IOR, AND, XOR, MINUS;
1459 MODE is the mode in which the operation is being performed;
1460 VAL is the integer to operate on;
1461 SOURCE is the other operand (a register, or a null-pointer for SET);
1462 SUBTARGETS means it is safe to create scratch registers if that will
1463 either produce a simpler sequence, or we will want to cse the values.
1464 Return value is the number of insns emitted. */
1467 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1468 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1472 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1473 cond
= COND_EXEC_TEST (PATTERN (insn
));
1477 if (subtargets
|| code
== SET
1478 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1479 && REGNO (target
) != REGNO (source
)))
1481 /* After arm_reorg has been called, we can't fix up expensive
1482 constants by pushing them into memory so we must synthesize
1483 them in-line, regardless of the cost. This is only likely to
1484 be more costly on chips that have load delay slots and we are
1485 compiling without running the scheduler (so no splitting
1486 occurred before the final instruction emission).
1488 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1490 if (!after_arm_reorg
1492 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1494 > arm_constant_limit
+ (code
!= SET
)))
1498 /* Currently SET is the only monadic value for CODE, all
1499 the rest are diadic. */
1500 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1505 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1507 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1508 /* For MINUS, the value is subtracted from, since we never
1509 have subtraction of a constant. */
1511 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1512 gen_rtx_MINUS (mode
, temp
, source
)));
1514 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1515 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1521 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1526 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1528 HOST_WIDE_INT temp1
;
1536 if (remainder
& (3 << (i
- 2)))
1541 temp1
= remainder
& ((0x0ff << end
)
1542 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1543 remainder
&= ~temp1
;
1548 } while (remainder
);
1552 /* Emit an instruction with the indicated PATTERN. If COND is
1553 non-NULL, conditionalize the execution of the instruction on COND
1557 emit_constant_insn (rtx cond
, rtx pattern
)
1560 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1561 emit_insn (pattern
);
1564 /* As above, but extra parameter GENERATE which, if clear, suppresses
1568 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1569 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1574 int can_negate_initial
= 0;
1577 int num_bits_set
= 0;
1578 int set_sign_bit_copies
= 0;
1579 int clear_sign_bit_copies
= 0;
1580 int clear_zero_bit_copies
= 0;
1581 int set_zero_bit_copies
= 0;
1583 unsigned HOST_WIDE_INT temp1
, temp2
;
1584 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1586 /* Find out which operations are safe for a given CODE. Also do a quick
1587 check for degenerate cases; these can occur when DImode operations
1599 can_negate_initial
= 1;
1603 if (remainder
== 0xffffffff)
1606 emit_constant_insn (cond
,
1607 gen_rtx_SET (VOIDmode
, target
,
1608 GEN_INT (ARM_SIGN_EXTEND (val
))));
1613 if (reload_completed
&& rtx_equal_p (target
, source
))
1616 emit_constant_insn (cond
,
1617 gen_rtx_SET (VOIDmode
, target
, source
));
1626 emit_constant_insn (cond
,
1627 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1630 if (remainder
== 0xffffffff)
1632 if (reload_completed
&& rtx_equal_p (target
, source
))
1635 emit_constant_insn (cond
,
1636 gen_rtx_SET (VOIDmode
, target
, source
));
1645 if (reload_completed
&& rtx_equal_p (target
, source
))
1648 emit_constant_insn (cond
,
1649 gen_rtx_SET (VOIDmode
, target
, source
));
1652 if (remainder
== 0xffffffff)
1655 emit_constant_insn (cond
,
1656 gen_rtx_SET (VOIDmode
, target
,
1657 gen_rtx_NOT (mode
, source
)));
1661 /* We don't know how to handle this yet below. */
1665 /* We treat MINUS as (val - source), since (source - val) is always
1666 passed as (source + (-val)). */
1670 emit_constant_insn (cond
,
1671 gen_rtx_SET (VOIDmode
, target
,
1672 gen_rtx_NEG (mode
, source
)));
1675 if (const_ok_for_arm (val
))
1678 emit_constant_insn (cond
,
1679 gen_rtx_SET (VOIDmode
, target
,
1680 gen_rtx_MINUS (mode
, GEN_INT (val
),
1692 /* If we can do it in one insn get out quickly. */
1693 if (const_ok_for_arm (val
)
1694 || (can_negate_initial
&& const_ok_for_arm (-val
))
1695 || (can_invert
&& const_ok_for_arm (~val
)))
1698 emit_constant_insn (cond
,
1699 gen_rtx_SET (VOIDmode
, target
,
1701 ? gen_rtx_fmt_ee (code
, mode
, source
,
1707 /* Calculate a few attributes that may be useful for specific
1709 for (i
= 31; i
>= 0; i
--)
1711 if ((remainder
& (1 << i
)) == 0)
1712 clear_sign_bit_copies
++;
1717 for (i
= 31; i
>= 0; i
--)
1719 if ((remainder
& (1 << i
)) != 0)
1720 set_sign_bit_copies
++;
1725 for (i
= 0; i
<= 31; i
++)
1727 if ((remainder
& (1 << i
)) == 0)
1728 clear_zero_bit_copies
++;
1733 for (i
= 0; i
<= 31; i
++)
1735 if ((remainder
& (1 << i
)) != 0)
1736 set_zero_bit_copies
++;
1744 /* See if we can do this by sign_extending a constant that is known
1745 to be negative. This is a good, way of doing it, since the shift
1746 may well merge into a subsequent insn. */
1747 if (set_sign_bit_copies
> 1)
1749 if (const_ok_for_arm
1750 (temp1
= ARM_SIGN_EXTEND (remainder
1751 << (set_sign_bit_copies
- 1))))
1755 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1756 emit_constant_insn (cond
,
1757 gen_rtx_SET (VOIDmode
, new_src
,
1759 emit_constant_insn (cond
,
1760 gen_ashrsi3 (target
, new_src
,
1761 GEN_INT (set_sign_bit_copies
- 1)));
1765 /* For an inverted constant, we will need to set the low bits,
1766 these will be shifted out of harm's way. */
1767 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1768 if (const_ok_for_arm (~temp1
))
1772 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1773 emit_constant_insn (cond
,
1774 gen_rtx_SET (VOIDmode
, new_src
,
1776 emit_constant_insn (cond
,
1777 gen_ashrsi3 (target
, new_src
,
1778 GEN_INT (set_sign_bit_copies
- 1)));
1784 /* See if we can generate this by setting the bottom (or the top)
1785 16 bits, and then shifting these into the other half of the
1786 word. We only look for the simplest cases, to do more would cost
1787 too much. Be careful, however, not to generate this when the
1788 alternative would take fewer insns. */
1789 if (val
& 0xffff0000)
1791 temp1
= remainder
& 0xffff0000;
1792 temp2
= remainder
& 0x0000ffff;
1794 /* Overlaps outside this range are best done using other methods. */
1795 for (i
= 9; i
< 24; i
++)
1797 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1798 && !const_ok_for_arm (temp2
))
1800 rtx new_src
= (subtargets
1801 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1803 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
1804 source
, subtargets
, generate
);
1812 gen_rtx_ASHIFT (mode
, source
,
1819 /* Don't duplicate cases already considered. */
1820 for (i
= 17; i
< 24; i
++)
1822 if (((temp1
| (temp1
>> i
)) == remainder
)
1823 && !const_ok_for_arm (temp1
))
1825 rtx new_src
= (subtargets
1826 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1828 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
1829 source
, subtargets
, generate
);
1834 gen_rtx_SET (VOIDmode
, target
,
1837 gen_rtx_LSHIFTRT (mode
, source
,
1848 /* If we have IOR or XOR, and the constant can be loaded in a
1849 single instruction, and we can find a temporary to put it in,
1850 then this can be done in two instructions instead of 3-4. */
1852 /* TARGET can't be NULL if SUBTARGETS is 0 */
1853 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1855 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1859 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1861 emit_constant_insn (cond
,
1862 gen_rtx_SET (VOIDmode
, sub
,
1864 emit_constant_insn (cond
,
1865 gen_rtx_SET (VOIDmode
, target
,
1866 gen_rtx_fmt_ee (code
, mode
,
1876 if (set_sign_bit_copies
> 8
1877 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1881 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1882 rtx shift
= GEN_INT (set_sign_bit_copies
);
1886 gen_rtx_SET (VOIDmode
, sub
,
1888 gen_rtx_ASHIFT (mode
,
1893 gen_rtx_SET (VOIDmode
, target
,
1895 gen_rtx_LSHIFTRT (mode
, sub
,
1901 if (set_zero_bit_copies
> 8
1902 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1906 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1907 rtx shift
= GEN_INT (set_zero_bit_copies
);
1911 gen_rtx_SET (VOIDmode
, sub
,
1913 gen_rtx_LSHIFTRT (mode
,
1918 gen_rtx_SET (VOIDmode
, target
,
1920 gen_rtx_ASHIFT (mode
, sub
,
1926 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1930 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1931 emit_constant_insn (cond
,
1932 gen_rtx_SET (VOIDmode
, sub
,
1933 gen_rtx_NOT (mode
, source
)));
1936 sub
= gen_reg_rtx (mode
);
1937 emit_constant_insn (cond
,
1938 gen_rtx_SET (VOIDmode
, sub
,
1939 gen_rtx_AND (mode
, source
,
1941 emit_constant_insn (cond
,
1942 gen_rtx_SET (VOIDmode
, target
,
1943 gen_rtx_NOT (mode
, sub
)));
1950 /* See if two shifts will do 2 or more insn's worth of work. */
1951 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1953 HOST_WIDE_INT shift_mask
= ((0xffffffff
1954 << (32 - clear_sign_bit_copies
))
1957 if ((remainder
| shift_mask
) != 0xffffffff)
1961 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1962 insns
= arm_gen_constant (AND
, mode
, cond
,
1963 remainder
| shift_mask
,
1964 new_src
, source
, subtargets
, 1);
1969 rtx targ
= subtargets
? NULL_RTX
: target
;
1970 insns
= arm_gen_constant (AND
, mode
, cond
,
1971 remainder
| shift_mask
,
1972 targ
, source
, subtargets
, 0);
1978 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1979 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1981 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1982 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1988 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1990 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1992 if ((remainder
| shift_mask
) != 0xffffffff)
1996 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1998 insns
= arm_gen_constant (AND
, mode
, cond
,
1999 remainder
| shift_mask
,
2000 new_src
, source
, subtargets
, 1);
2005 rtx targ
= subtargets
? NULL_RTX
: target
;
2007 insns
= arm_gen_constant (AND
, mode
, cond
,
2008 remainder
| shift_mask
,
2009 targ
, source
, subtargets
, 0);
2015 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2016 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2018 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2019 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2031 for (i
= 0; i
< 32; i
++)
2032 if (remainder
& (1 << i
))
2035 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2036 remainder
= (~remainder
) & 0xffffffff;
2037 else if (code
== PLUS
&& num_bits_set
> 16)
2038 remainder
= (-remainder
) & 0xffffffff;
2045 /* Now try and find a way of doing the job in either two or three
2047 We start by looking for the largest block of zeros that are aligned on
2048 a 2-bit boundary, we then fill up the temps, wrapping around to the
2049 top of the word when we drop off the bottom.
2050 In the worst case this code should produce no more than four insns. */
2053 int best_consecutive_zeros
= 0;
2055 for (i
= 0; i
< 32; i
+= 2)
2057 int consecutive_zeros
= 0;
2059 if (!(remainder
& (3 << i
)))
2061 while ((i
< 32) && !(remainder
& (3 << i
)))
2063 consecutive_zeros
+= 2;
2066 if (consecutive_zeros
> best_consecutive_zeros
)
2068 best_consecutive_zeros
= consecutive_zeros
;
2069 best_start
= i
- consecutive_zeros
;
2075 /* So long as it won't require any more insns to do so, it's
2076 desirable to emit a small constant (in bits 0...9) in the last
2077 insn. This way there is more chance that it can be combined with
2078 a later addressing insn to form a pre-indexed load or store
2079 operation. Consider:
2081 *((volatile int *)0xe0000100) = 1;
2082 *((volatile int *)0xe0000110) = 2;
2084 We want this to wind up as:
2088 str rB, [rA, #0x100]
2090 str rB, [rA, #0x110]
2092 rather than having to synthesize both large constants from scratch.
2094 Therefore, we calculate how many insns would be required to emit
2095 the constant starting from `best_start', and also starting from
2096 zero (ie with bit 31 first to be output). If `best_start' doesn't
2097 yield a shorter sequence, we may as well use zero. */
2099 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2100 && (count_insns_for_constant (remainder
, 0) <=
2101 count_insns_for_constant (remainder
, best_start
)))
2104 /* Now start emitting the insns. */
2112 if (remainder
& (3 << (i
- 2)))
2117 temp1
= remainder
& ((0x0ff << end
)
2118 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2119 remainder
&= ~temp1
;
2123 rtx new_src
, temp1_rtx
;
2125 if (code
== SET
|| code
== MINUS
)
2127 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2128 if (can_invert
&& code
!= MINUS
)
2133 if (remainder
&& subtargets
)
2134 new_src
= gen_reg_rtx (mode
);
2139 else if (can_negate
)
2143 temp1
= trunc_int_for_mode (temp1
, mode
);
2144 temp1_rtx
= GEN_INT (temp1
);
2148 else if (code
== MINUS
)
2149 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2151 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2153 emit_constant_insn (cond
,
2154 gen_rtx_SET (VOIDmode
, new_src
,
2164 else if (code
== MINUS
)
2178 /* Canonicalize a comparison so that we are more likely to recognize it.
2179 This can be done for a few constant compares, where we can make the
2180 immediate value easier to load. */
2183 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
2185 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2195 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
2196 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2198 *op1
= GEN_INT (i
+ 1);
2199 return code
== GT
? GE
: LT
;
2205 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
2206 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2208 *op1
= GEN_INT (i
- 1);
2209 return code
== GE
? GT
: LE
;
2215 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2216 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2218 *op1
= GEN_INT (i
+ 1);
2219 return code
== GTU
? GEU
: LTU
;
2226 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2228 *op1
= GEN_INT (i
- 1);
2229 return code
== GEU
? GTU
: LEU
;
2241 /* Define how to find the value returned by a function. */
2243 rtx
arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2245 enum machine_mode mode
;
2246 int unsignedp ATTRIBUTE_UNUSED
;
2247 rtx r ATTRIBUTE_UNUSED
;
2250 mode
= TYPE_MODE (type
);
2251 /* Promote integer types. */
2252 if (INTEGRAL_TYPE_P (type
))
2253 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2254 return LIBCALL_VALUE(mode
);
2258 /* Decide whether a type should be returned in memory (true)
2259 or in a register (false). This is called by the macro
2260 RETURN_IN_MEMORY. */
2262 arm_return_in_memory (tree type
)
2266 if (!AGGREGATE_TYPE_P (type
))
2267 /* All simple types are returned in registers. */
2270 size
= int_size_in_bytes (type
);
2272 if (arm_abi
!= ARM_ABI_APCS
)
2274 /* ATPCS and later return aggregate types in memory only if they are
2275 larger than a word (or are variable size). */
2276 return (size
< 0 || size
> UNITS_PER_WORD
);
2279 /* For the arm-wince targets we choose to be compatible with Microsoft's
2280 ARM and Thumb compilers, which always return aggregates in memory. */
2282 /* All structures/unions bigger than one word are returned in memory.
2283 Also catch the case where int_size_in_bytes returns -1. In this case
2284 the aggregate is either huge or of variable size, and in either case
2285 we will want to return it via memory and not in a register. */
2286 if (size
< 0 || size
> UNITS_PER_WORD
)
2289 if (TREE_CODE (type
) == RECORD_TYPE
)
2293 /* For a struct the APCS says that we only return in a register
2294 if the type is 'integer like' and every addressable element
2295 has an offset of zero. For practical purposes this means
2296 that the structure can have at most one non bit-field element
2297 and that this element must be the first one in the structure. */
2299 /* Find the first field, ignoring non FIELD_DECL things which will
2300 have been created by C++. */
2301 for (field
= TYPE_FIELDS (type
);
2302 field
&& TREE_CODE (field
) != FIELD_DECL
;
2303 field
= TREE_CHAIN (field
))
2307 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2309 /* Check that the first field is valid for returning in a register. */
2311 /* ... Floats are not allowed */
2312 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2315 /* ... Aggregates that are not themselves valid for returning in
2316 a register are not allowed. */
2317 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2320 /* Now check the remaining fields, if any. Only bitfields are allowed,
2321 since they are not addressable. */
2322 for (field
= TREE_CHAIN (field
);
2324 field
= TREE_CHAIN (field
))
2326 if (TREE_CODE (field
) != FIELD_DECL
)
2329 if (!DECL_BIT_FIELD_TYPE (field
))
2336 if (TREE_CODE (type
) == UNION_TYPE
)
2340 /* Unions can be returned in registers if every element is
2341 integral, or can be returned in an integer register. */
2342 for (field
= TYPE_FIELDS (type
);
2344 field
= TREE_CHAIN (field
))
2346 if (TREE_CODE (field
) != FIELD_DECL
)
2349 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2352 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2358 #endif /* not ARM_WINCE */
2360 /* Return all other types in memory. */
2364 /* Indicate whether or not words of a double are in big-endian order. */
2367 arm_float_words_big_endian (void)
2369 if (TARGET_MAVERICK
)
2372 /* For FPA, float words are always big-endian. For VFP, floats words
2373 follow the memory system mode. */
2381 return (TARGET_BIG_END
? 1 : 0);
2386 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2387 for a call to a function whose data type is FNTYPE.
2388 For a library call, FNTYPE is NULL. */
2390 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2391 rtx libname ATTRIBUTE_UNUSED
,
2392 tree fndecl ATTRIBUTE_UNUSED
)
2394 /* On the ARM, the offset starts at 0. */
2395 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2396 pcum
->iwmmxt_nregs
= 0;
2397 pcum
->can_split
= true;
2399 pcum
->call_cookie
= CALL_NORMAL
;
2401 if (TARGET_LONG_CALLS
)
2402 pcum
->call_cookie
= CALL_LONG
;
2404 /* Check for long call/short call attributes. The attributes
2405 override any command line option. */
2408 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2409 pcum
->call_cookie
= CALL_SHORT
;
2410 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2411 pcum
->call_cookie
= CALL_LONG
;
2414 /* Varargs vectors are treated the same as long long.
2415 named_count avoids having to change the way arm handles 'named' */
2416 pcum
->named_count
= 0;
2419 if (TARGET_REALLY_IWMMXT
&& fntype
)
2423 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2425 fn_arg
= TREE_CHAIN (fn_arg
))
2426 pcum
->named_count
+= 1;
2428 if (! pcum
->named_count
)
2429 pcum
->named_count
= INT_MAX
;
2434 /* Return true if mode/type need doubleword alignment. */
2436 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2438 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2439 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2443 /* Determine where to put an argument to a function.
2444 Value is zero to push the argument on the stack,
2445 or a hard register in which to store the argument.
2447 MODE is the argument's machine mode.
2448 TYPE is the data type of the argument (as a tree).
2449 This is null for libcalls where that information may
2451 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2452 the preceding args and about the function being called.
2453 NAMED is nonzero if this argument is a named parameter
2454 (otherwise it is an extra parameter matching an ellipsis). */
2457 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2458 tree type
, int named
)
2462 /* Varargs vectors are treated the same as long long.
2463 named_count avoids having to change the way arm handles 'named' */
2464 if (TARGET_IWMMXT_ABI
2465 && VECTOR_MODE_SUPPORTED_P (mode
)
2466 && pcum
->named_count
> pcum
->nargs
+ 1)
2468 if (pcum
->iwmmxt_nregs
<= 9)
2469 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2472 pcum
->can_split
= false;
2477 /* Put doubleword aligned quantities in even register pairs. */
2479 && ARM_DOUBLEWORD_ALIGN
2480 && arm_needs_doubleword_align (mode
, type
))
2483 if (mode
== VOIDmode
)
2484 /* Compute operand 2 of the call insn. */
2485 return GEN_INT (pcum
->call_cookie
);
2487 /* Only allow splitting an arg between regs and memory if all preceding
2488 args were allocated to regs. For args passed by reference we only count
2489 the reference pointer. */
2490 if (pcum
->can_split
)
2493 nregs
= ARM_NUM_REGS2 (mode
, type
);
2495 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2498 return gen_rtx_REG (mode
, pcum
->nregs
);
2501 /* Variable sized types are passed by reference. This is a GCC
2502 extension to the ARM ABI. */
2505 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2506 enum machine_mode mode ATTRIBUTE_UNUSED
,
2507 tree type
, bool named ATTRIBUTE_UNUSED
)
2509 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2512 /* Encode the current state of the #pragma [no_]long_calls. */
2515 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2516 LONG
, /* #pragma long_calls is in effect. */
2517 SHORT
/* #pragma no_long_calls is in effect. */
2520 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2523 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2525 arm_pragma_long_calls
= LONG
;
2529 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2531 arm_pragma_long_calls
= SHORT
;
2535 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2537 arm_pragma_long_calls
= OFF
;
2540 /* Table of machine attributes. */
2541 const struct attribute_spec arm_attribute_table
[] =
2543 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2544 /* Function calls made to this symbol must be done indirectly, because
2545 it may lie outside of the 26 bit addressing range of a normal function
2547 { "long_call", 0, 0, false, true, true, NULL
},
2548 /* Whereas these functions are always known to reside within the 26 bit
2549 addressing range. */
2550 { "short_call", 0, 0, false, true, true, NULL
},
2551 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2552 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2553 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2554 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2556 /* ARM/PE has three new attributes:
2558 dllexport - for exporting a function/variable that will live in a dll
2559 dllimport - for importing a function/variable from a dll
2561 Microsoft allows multiple declspecs in one __declspec, separating
2562 them with spaces. We do NOT support this. Instead, use __declspec
2565 { "dllimport", 0, 0, true, false, false, NULL
},
2566 { "dllexport", 0, 0, true, false, false, NULL
},
2567 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2568 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2569 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2570 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2572 { NULL
, 0, 0, false, false, false, NULL
}
2575 /* Handle an attribute requiring a FUNCTION_DECL;
2576 arguments as in struct attribute_spec.handler. */
2578 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2579 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2581 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2583 warning ("`%s' attribute only applies to functions",
2584 IDENTIFIER_POINTER (name
));
2585 *no_add_attrs
= true;
2591 /* Handle an "interrupt" or "isr" attribute;
2592 arguments as in struct attribute_spec.handler. */
2594 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2599 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2601 warning ("`%s' attribute only applies to functions",
2602 IDENTIFIER_POINTER (name
));
2603 *no_add_attrs
= true;
2605 /* FIXME: the argument if any is checked for type attributes;
2606 should it be checked for decl ones? */
2610 if (TREE_CODE (*node
) == FUNCTION_TYPE
2611 || TREE_CODE (*node
) == METHOD_TYPE
)
2613 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2615 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2616 *no_add_attrs
= true;
2619 else if (TREE_CODE (*node
) == POINTER_TYPE
2620 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2621 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2622 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2624 *node
= build_type_copy (*node
);
2625 TREE_TYPE (*node
) = build_type_attribute_variant
2627 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2628 *no_add_attrs
= true;
2632 /* Possibly pass this attribute on from the type to a decl. */
2633 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2634 | (int) ATTR_FLAG_FUNCTION_NEXT
2635 | (int) ATTR_FLAG_ARRAY_NEXT
))
2637 *no_add_attrs
= true;
2638 return tree_cons (name
, args
, NULL_TREE
);
2642 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2650 /* Return 0 if the attributes for two types are incompatible, 1 if they
2651 are compatible, and 2 if they are nearly compatible (which causes a
2652 warning to be generated). */
2654 arm_comp_type_attributes (tree type1
, tree type2
)
2658 /* Check for mismatch of non-default calling convention. */
2659 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2662 /* Check for mismatched call attributes. */
2663 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2664 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2665 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2666 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2668 /* Only bother to check if an attribute is defined. */
2669 if (l1
| l2
| s1
| s2
)
2671 /* If one type has an attribute, the other must have the same attribute. */
2672 if ((l1
!= l2
) || (s1
!= s2
))
2675 /* Disallow mixed attributes. */
2676 if ((l1
& s2
) || (l2
& s1
))
2680 /* Check for mismatched ISR attribute. */
2681 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2683 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2684 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2686 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2693 /* Encode long_call or short_call attribute by prefixing
2694 symbol name in DECL with a special character FLAG. */
2696 arm_encode_call_attribute (tree decl
, int flag
)
2698 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2699 int len
= strlen (str
);
2702 /* Do not allow weak functions to be treated as short call. */
2703 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2706 newstr
= alloca (len
+ 2);
2708 strcpy (newstr
+ 1, str
);
2710 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2711 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2714 /* Assigns default attributes to newly defined type. This is used to
2715 set short_call/long_call attributes for function types of
2716 functions defined inside corresponding #pragma scopes. */
2718 arm_set_default_type_attributes (tree type
)
2720 /* Add __attribute__ ((long_call)) to all functions, when
2721 inside #pragma long_calls or __attribute__ ((short_call)),
2722 when inside #pragma no_long_calls. */
2723 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2725 tree type_attr_list
, attr_name
;
2726 type_attr_list
= TYPE_ATTRIBUTES (type
);
2728 if (arm_pragma_long_calls
== LONG
)
2729 attr_name
= get_identifier ("long_call");
2730 else if (arm_pragma_long_calls
== SHORT
)
2731 attr_name
= get_identifier ("short_call");
2735 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2736 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2740 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2741 defined within the current compilation unit. If this cannot be
2742 determined, then 0 is returned. */
2744 current_file_function_operand (rtx sym_ref
)
2746 /* This is a bit of a fib. A function will have a short call flag
2747 applied to its name if it has the short call attribute, or it has
2748 already been defined within the current compilation unit. */
2749 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2752 /* The current function is always defined within the current compilation
2753 unit. If it s a weak definition however, then this may not be the real
2754 definition of the function, and so we have to say no. */
2755 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2756 && !DECL_WEAK (current_function_decl
))
2759 /* We cannot make the determination - default to returning 0. */
2763 /* Return nonzero if a 32 bit "long_call" should be generated for
2764 this call. We generate a long_call if the function:
2766 a. has an __attribute__((long call))
2767 or b. is within the scope of a #pragma long_calls
2768 or c. the -mlong-calls command line switch has been specified
2770 1. -ffunction-sections is in effect
2771 or 2. the current function has __attribute__ ((section))
2772 or 3. the target function has __attribute__ ((section))
2774 However we do not generate a long call if the function:
2776 d. has an __attribute__ ((short_call))
2777 or e. is inside the scope of a #pragma no_long_calls
2778 or f. is defined within the current compilation unit.
2780 This function will be called by C fragments contained in the machine
2781 description file. SYM_REF and CALL_COOKIE correspond to the matched
2782 rtl operands. CALL_SYMBOL is used to distinguish between
2783 two different callers of the function. It is set to 1 in the
2784 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2785 and "call_value" patterns. This is because of the difference in the
2786 SYM_REFs passed by these patterns. */
2788 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2792 if (GET_CODE (sym_ref
) != MEM
)
2795 sym_ref
= XEXP (sym_ref
, 0);
2798 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2801 if (call_cookie
& CALL_SHORT
)
2804 if (TARGET_LONG_CALLS
)
2806 if (flag_function_sections
2807 || DECL_SECTION_NAME (current_function_decl
))
2808 /* c.3 is handled by the defintion of the
2809 ARM_DECLARE_FUNCTION_SIZE macro. */
2813 if (current_file_function_operand (sym_ref
))
2816 return (call_cookie
& CALL_LONG
)
2817 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2818 || TARGET_LONG_CALLS
;
2821 /* Return nonzero if it is ok to make a tail-call to DECL. */
2823 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2825 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2827 if (cfun
->machine
->sibcall_blocked
)
2830 /* Never tailcall something for which we have no decl, or if we
2831 are in Thumb mode. */
2832 if (decl
== NULL
|| TARGET_THUMB
)
2835 /* Get the calling method. */
2836 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2837 call_type
= CALL_SHORT
;
2838 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2839 call_type
= CALL_LONG
;
2841 /* Cannot tail-call to long calls, since these are out of range of
2842 a branch instruction. However, if not compiling PIC, we know
2843 we can reach the symbol if it is in this compilation unit. */
2844 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2847 /* If we are interworking and the function is not declared static
2848 then we can't tail-call it unless we know that it exists in this
2849 compilation unit (since it might be a Thumb routine). */
2850 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2853 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2854 if (IS_INTERRUPT (arm_current_func_type ()))
2857 /* Everything else is ok. */
2862 /* Addressing mode support functions. */
2864 /* Return nonzero if X is a legitimate immediate operand when compiling
2867 legitimate_pic_operand_p (rtx x
)
2871 && (GET_CODE (x
) == SYMBOL_REF
2872 || (GET_CODE (x
) == CONST
2873 && GET_CODE (XEXP (x
, 0)) == PLUS
2874 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2881 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2883 if (GET_CODE (orig
) == SYMBOL_REF
2884 || GET_CODE (orig
) == LABEL_REF
)
2886 #ifndef AOF_ASSEMBLER
2887 rtx pic_ref
, address
;
2897 reg
= gen_reg_rtx (Pmode
);
2902 #ifdef AOF_ASSEMBLER
2903 /* The AOF assembler can generate relocations for these directly, and
2904 understands that the PIC register has to be added into the offset. */
2905 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2908 address
= gen_reg_rtx (Pmode
);
2913 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2915 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2917 if ((GET_CODE (orig
) == LABEL_REF
2918 || (GET_CODE (orig
) == SYMBOL_REF
&&
2919 SYMBOL_REF_LOCAL_P (orig
)))
2921 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2924 pic_ref
= gen_const_mem (Pmode
,
2925 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2929 insn
= emit_move_insn (reg
, pic_ref
);
2931 current_function_uses_pic_offset_table
= 1;
2932 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2934 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2938 else if (GET_CODE (orig
) == CONST
)
2942 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2943 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2951 reg
= gen_reg_rtx (Pmode
);
2954 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2956 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2957 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2958 base
== reg
? 0 : reg
);
2963 if (GET_CODE (offset
) == CONST_INT
)
2965 /* The base register doesn't really matter, we only want to
2966 test the index for the appropriate mode. */
2967 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
2969 if (!no_new_pseudos
)
2970 offset
= force_reg (Pmode
, offset
);
2975 if (GET_CODE (offset
) == CONST_INT
)
2976 return plus_constant (base
, INTVAL (offset
));
2979 if (GET_MODE_SIZE (mode
) > 4
2980 && (GET_MODE_CLASS (mode
) == MODE_INT
2981 || TARGET_SOFT_FLOAT
))
2983 emit_insn (gen_addsi3 (reg
, base
, offset
));
2987 return gen_rtx_PLUS (Pmode
, base
, offset
);
2994 /* Find a spare low register. */
2997 thumb_find_work_register (int live_regs_mask
)
3001 /* Use a spare arg register. */
3002 if (!regs_ever_live
[LAST_ARG_REGNUM
])
3003 return LAST_ARG_REGNUM
;
3005 /* Look for a pushed register. */
3006 for (reg
= 0; reg
< LAST_LO_REGNUM
; reg
++)
3007 if (live_regs_mask
& (1 << reg
))
3010 /* Something went wrong. */
3015 /* Generate code to load the PIC register. */
3018 arm_load_pic_register (void)
3020 #ifndef AOF_ASSEMBLER
3021 rtx l1
, pic_tmp
, pic_tmp2
, pic_rtx
;
3022 rtx global_offset_table
;
3024 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3030 l1
= gen_label_rtx ();
3032 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3033 /* On the ARM the PC register contains 'dot + 8' at the time of the
3034 addition, on the Thumb it is 'dot + 4'. */
3035 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
3037 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3038 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3040 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3042 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3046 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3047 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
3051 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3055 /* We will have pushed the pic register, so should always be
3056 able to find a work register. */
3057 reg
= thumb_find_work_register (thumb_compute_save_reg_mask ());
3058 pic_tmp
= gen_rtx_REG (SImode
, reg
);
3059 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3060 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3063 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3064 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
3067 /* Need to emit this whether or not we obey regdecls,
3068 since setjmp/longjmp can cause life info to screw up. */
3069 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3070 #endif /* AOF_ASSEMBLER */
3074 /* Return nonzero if X is valid as an ARM state addressing register. */
3076 arm_address_register_rtx_p (rtx x
, int strict_p
)
3080 if (GET_CODE (x
) != REG
)
3086 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3088 return (regno
<= LAST_ARM_REGNUM
3089 || regno
>= FIRST_PSEUDO_REGISTER
3090 || regno
== FRAME_POINTER_REGNUM
3091 || regno
== ARG_POINTER_REGNUM
);
3094 /* Return nonzero if X is a valid ARM state address operand. */
3096 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3100 enum rtx_code code
= GET_CODE (x
);
3102 if (arm_address_register_rtx_p (x
, strict_p
))
3105 use_ldrd
= (TARGET_LDRD
3107 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3109 if (code
== POST_INC
|| code
== PRE_DEC
3110 || ((code
== PRE_INC
|| code
== POST_DEC
)
3111 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3112 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3114 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3115 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3116 && GET_CODE (XEXP (x
, 1)) == PLUS
3117 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3119 rtx addend
= XEXP (XEXP (x
, 1), 1);
3121 /* Don't allow ldrd post increment by register becuase it's hard
3122 to fixup invalid register choices. */
3124 && GET_CODE (x
) == POST_MODIFY
3125 && GET_CODE (addend
) == REG
)
3128 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3129 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3132 /* After reload constants split into minipools will have addresses
3133 from a LABEL_REF. */
3134 else if (reload_completed
3135 && (code
== LABEL_REF
3137 && GET_CODE (XEXP (x
, 0)) == PLUS
3138 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3139 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3142 else if (mode
== TImode
)
3145 else if (code
== PLUS
)
3147 rtx xop0
= XEXP (x
, 0);
3148 rtx xop1
= XEXP (x
, 1);
3150 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3151 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3152 || (arm_address_register_rtx_p (xop1
, strict_p
)
3153 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3157 /* Reload currently can't handle MINUS, so disable this for now */
3158 else if (GET_CODE (x
) == MINUS
)
3160 rtx xop0
= XEXP (x
, 0);
3161 rtx xop1
= XEXP (x
, 1);
3163 return (arm_address_register_rtx_p (xop0
, strict_p
)
3164 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3168 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3169 && code
== SYMBOL_REF
3170 && CONSTANT_POOL_ADDRESS_P (x
)
3172 && symbol_mentioned_p (get_pool_constant (x
))))
3178 /* Return nonzero if INDEX is valid for an address index operand in
3181 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3184 HOST_WIDE_INT range
;
3185 enum rtx_code code
= GET_CODE (index
);
3187 /* Standard coprocessor addressing modes. */
3188 if (TARGET_HARD_FLOAT
3189 && (TARGET_FPA
|| TARGET_MAVERICK
)
3190 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3191 || (TARGET_MAVERICK
&& mode
== DImode
)))
3192 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3193 && INTVAL (index
) > -1024
3194 && (INTVAL (index
) & 3) == 0);
3196 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3197 return (code
== CONST_INT
3198 && INTVAL (index
) < 1024
3199 && INTVAL (index
) > -1024
3200 && (INTVAL (index
) & 3) == 0);
3202 if (arm_address_register_rtx_p (index
, strict_p
)
3203 && (GET_MODE_SIZE (mode
) <= 4))
3206 if (mode
== DImode
|| mode
== DFmode
)
3208 if (code
== CONST_INT
)
3210 HOST_WIDE_INT val
= INTVAL (index
);
3213 return val
> -256 && val
< 256;
3215 return val
> -4096 && val
< 4092;
3218 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3221 if (GET_MODE_SIZE (mode
) <= 4
3224 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3228 rtx xiop0
= XEXP (index
, 0);
3229 rtx xiop1
= XEXP (index
, 1);
3231 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3232 && power_of_two_operand (xiop1
, SImode
))
3233 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3234 && power_of_two_operand (xiop0
, SImode
)));
3236 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3237 || code
== ASHIFT
|| code
== ROTATERT
)
3239 rtx op
= XEXP (index
, 1);
3241 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3242 && GET_CODE (op
) == CONST_INT
3244 && INTVAL (op
) <= 31);
3248 /* For ARM v4 we may be doing a sign-extend operation during the
3252 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3258 range
= (mode
== HImode
) ? 4095 : 4096;
3260 return (code
== CONST_INT
3261 && INTVAL (index
) < range
3262 && INTVAL (index
) > -range
);
3265 /* Return nonzero if X is valid as a Thumb state base register. */
3267 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3271 if (GET_CODE (x
) != REG
)
3277 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3279 return (regno
<= LAST_LO_REGNUM
3280 || regno
> LAST_VIRTUAL_REGISTER
3281 || regno
== FRAME_POINTER_REGNUM
3282 || (GET_MODE_SIZE (mode
) >= 4
3283 && (regno
== STACK_POINTER_REGNUM
3284 || regno
>= FIRST_PSEUDO_REGISTER
3285 || x
== hard_frame_pointer_rtx
3286 || x
== arg_pointer_rtx
)));
3289 /* Return nonzero if x is a legitimate index register. This is the case
3290 for any base register that can access a QImode object. */
3292 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3294 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3297 /* Return nonzero if x is a legitimate Thumb-state address.
3299 The AP may be eliminated to either the SP or the FP, so we use the
3300 least common denominator, e.g. SImode, and offsets from 0 to 64.
3302 ??? Verify whether the above is the right approach.
3304 ??? Also, the FP may be eliminated to the SP, so perhaps that
3305 needs special handling also.
3307 ??? Look at how the mips16 port solves this problem. It probably uses
3308 better ways to solve some of these problems.
3310 Although it is not incorrect, we don't accept QImode and HImode
3311 addresses based on the frame pointer or arg pointer until the
3312 reload pass starts. This is so that eliminating such addresses
3313 into stack based ones won't produce impossible code. */
3315 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3317 /* ??? Not clear if this is right. Experiment. */
3318 if (GET_MODE_SIZE (mode
) < 4
3319 && !(reload_in_progress
|| reload_completed
)
3320 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3321 || reg_mentioned_p (arg_pointer_rtx
, x
)
3322 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3323 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3324 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3325 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3328 /* Accept any base register. SP only in SImode or larger. */
3329 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3332 /* This is PC relative data before arm_reorg runs. */
3333 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3334 && GET_CODE (x
) == SYMBOL_REF
3335 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3338 /* This is PC relative data after arm_reorg runs. */
3339 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3340 && (GET_CODE (x
) == LABEL_REF
3341 || (GET_CODE (x
) == CONST
3342 && GET_CODE (XEXP (x
, 0)) == PLUS
3343 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3344 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3347 /* Post-inc indexing only supported for SImode and larger. */
3348 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3349 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3352 else if (GET_CODE (x
) == PLUS
)
3354 /* REG+REG address can be any two index registers. */
3355 /* We disallow FRAME+REG addressing since we know that FRAME
3356 will be replaced with STACK, and SP relative addressing only
3357 permits SP+OFFSET. */
3358 if (GET_MODE_SIZE (mode
) <= 4
3359 && XEXP (x
, 0) != frame_pointer_rtx
3360 && XEXP (x
, 1) != frame_pointer_rtx
3361 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3362 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3365 /* REG+const has 5-7 bit offset for non-SP registers. */
3366 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3367 || XEXP (x
, 0) == arg_pointer_rtx
)
3368 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3369 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3372 /* REG+const has 10 bit offset for SP, but only SImode and
3373 larger is supported. */
3374 /* ??? Should probably check for DI/DFmode overflow here
3375 just like GO_IF_LEGITIMATE_OFFSET does. */
3376 else if (GET_CODE (XEXP (x
, 0)) == REG
3377 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3378 && GET_MODE_SIZE (mode
) >= 4
3379 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3380 && INTVAL (XEXP (x
, 1)) >= 0
3381 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3382 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3385 else if (GET_CODE (XEXP (x
, 0)) == REG
3386 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3387 && GET_MODE_SIZE (mode
) >= 4
3388 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3389 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3393 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3394 && GET_MODE_SIZE (mode
) == 4
3395 && GET_CODE (x
) == SYMBOL_REF
3396 && CONSTANT_POOL_ADDRESS_P (x
)
3398 && symbol_mentioned_p (get_pool_constant (x
))))
3404 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3405 instruction of mode MODE. */
3407 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3409 switch (GET_MODE_SIZE (mode
))
3412 return val
>= 0 && val
< 32;
3415 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3419 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3424 /* Try machine-dependent ways of modifying an illegitimate address
3425 to be legitimate. If we find one, return the new, valid address. */
3427 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3429 if (GET_CODE (x
) == PLUS
)
3431 rtx xop0
= XEXP (x
, 0);
3432 rtx xop1
= XEXP (x
, 1);
3434 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3435 xop0
= force_reg (SImode
, xop0
);
3437 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3438 xop1
= force_reg (SImode
, xop1
);
3440 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3441 && GET_CODE (xop1
) == CONST_INT
)
3443 HOST_WIDE_INT n
, low_n
;
3447 /* VFP addressing modes actually allow greater offsets, but for
3448 now we just stick with the lowest common denominator. */
3450 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3462 low_n
= ((mode
) == TImode
? 0
3463 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3467 base_reg
= gen_reg_rtx (SImode
);
3468 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3469 GEN_INT (n
)), NULL_RTX
);
3470 emit_move_insn (base_reg
, val
);
3471 x
= (low_n
== 0 ? base_reg
3472 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3474 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3475 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3478 /* XXX We don't allow MINUS any more -- see comment in
3479 arm_legitimate_address_p (). */
3480 else if (GET_CODE (x
) == MINUS
)
3482 rtx xop0
= XEXP (x
, 0);
3483 rtx xop1
= XEXP (x
, 1);
3485 if (CONSTANT_P (xop0
))
3486 xop0
= force_reg (SImode
, xop0
);
3488 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3489 xop1
= force_reg (SImode
, xop1
);
3491 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3492 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3497 /* We need to find and carefully transform any SYMBOL and LABEL
3498 references; so go back to the original address expression. */
3499 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3501 if (new_x
!= orig_x
)
3509 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3510 to be legitimate. If we find one, return the new, valid address. */
3512 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3514 if (GET_CODE (x
) == PLUS
3515 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3516 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
3517 || INTVAL (XEXP (x
, 1)) < 0))
3519 rtx xop0
= XEXP (x
, 0);
3520 rtx xop1
= XEXP (x
, 1);
3521 HOST_WIDE_INT offset
= INTVAL (xop1
);
3523 /* Try and fold the offset into a biasing of the base register and
3524 then offsetting that. Don't do this when optimizing for space
3525 since it can cause too many CSEs. */
3526 if (optimize_size
&& offset
>= 0
3527 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
3529 HOST_WIDE_INT delta
;
3532 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
3533 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
3534 delta
= 31 * GET_MODE_SIZE (mode
);
3536 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
3538 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
3540 x
= plus_constant (xop0
, delta
);
3542 else if (offset
< 0 && offset
> -256)
3543 /* Small negative offsets are best done with a subtract before the
3544 dereference, forcing these into a register normally takes two
3546 x
= force_operand (x
, NULL_RTX
);
3549 /* For the remaining cases, force the constant into a register. */
3550 xop1
= force_reg (SImode
, xop1
);
3551 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3554 else if (GET_CODE (x
) == PLUS
3555 && s_register_operand (XEXP (x
, 1), SImode
)
3556 && !s_register_operand (XEXP (x
, 0), SImode
))
3558 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
3560 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
3565 /* We need to find and carefully transform any SYMBOL and LABEL
3566 references; so go back to the original address expression. */
3567 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3569 if (new_x
!= orig_x
)
3578 #define REG_OR_SUBREG_REG(X) \
3579 (GET_CODE (X) == REG \
3580 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3582 #define REG_OR_SUBREG_RTX(X) \
3583 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3585 #ifndef COSTS_N_INSNS
3586 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3589 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3591 enum machine_mode mode
= GET_MODE (x
);
3604 return COSTS_N_INSNS (1);
3607 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3610 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3617 return COSTS_N_INSNS (2) + cycles
;
3619 return COSTS_N_INSNS (1) + 16;
3622 return (COSTS_N_INSNS (1)
3623 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3624 + GET_CODE (SET_DEST (x
)) == MEM
));
3629 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3631 if (thumb_shiftable_const (INTVAL (x
)))
3632 return COSTS_N_INSNS (2);
3633 return COSTS_N_INSNS (3);
3635 else if ((outer
== PLUS
|| outer
== COMPARE
)
3636 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3638 else if (outer
== AND
3639 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3640 return COSTS_N_INSNS (1);
3641 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3642 || outer
== LSHIFTRT
)
3644 return COSTS_N_INSNS (2);
3650 return COSTS_N_INSNS (3);
3668 /* XXX another guess. */
3669 /* Memory costs quite a lot for the first word, but subsequent words
3670 load at the equivalent of a single insn each. */
3671 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3672 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3677 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3682 /* XXX still guessing. */
3683 switch (GET_MODE (XEXP (x
, 0)))
3686 return (1 + (mode
== DImode
? 4 : 0)
3687 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3690 return (4 + (mode
== DImode
? 4 : 0)
3691 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3694 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3706 /* Worker routine for arm_rtx_costs. */
3708 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3710 enum machine_mode mode
= GET_MODE (x
);
3711 enum rtx_code subcode
;
3717 /* Memory costs quite a lot for the first word, but subsequent words
3718 load at the equivalent of a single insn each. */
3719 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3720 + (GET_CODE (x
) == SYMBOL_REF
3721 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3727 return optimize_size
? COSTS_N_INSNS (2) : 100;
3730 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3737 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3739 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3740 + ((GET_CODE (XEXP (x
, 0)) == REG
3741 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3742 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3744 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3745 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3746 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3748 + ((GET_CODE (XEXP (x
, 1)) == REG
3749 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3750 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3751 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3756 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3757 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3758 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3759 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3762 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3763 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3764 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3765 && arm_const_double_rtx (XEXP (x
, 1))))
3767 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3768 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3769 && arm_const_double_rtx (XEXP (x
, 0))))
3772 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3773 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3774 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3775 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3776 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3777 || subcode
== ROTATE
|| subcode
== ROTATERT
3779 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3780 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3781 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3782 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3783 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3784 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3785 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3790 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3791 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3792 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3793 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3794 && arm_const_double_rtx (XEXP (x
, 1))))
3798 case AND
: case XOR
: case IOR
:
3801 /* Normally the frame registers will be spilt into reg+const during
3802 reload, so it is a bad idea to combine them with other instructions,
3803 since then they might not be moved outside of loops. As a compromise
3804 we allow integration with ops that have a constant as their second
3806 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3807 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3808 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3809 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3810 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3814 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3815 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3816 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3817 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3820 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3821 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3822 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3823 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3824 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3827 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3828 return (1 + extra_cost
3829 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3830 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3831 || subcode
== ROTATE
|| subcode
== ROTATERT
3833 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3834 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3835 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3836 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3837 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3838 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3844 /* This should have been handled by the CPU specific routines. */
3848 if (arm_arch3m
&& mode
== SImode
3849 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3850 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3851 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3852 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3853 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3854 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3859 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3860 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3864 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3866 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3869 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3877 return 4 + (mode
== DImode
? 4 : 0);
3880 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3881 return (4 + (mode
== DImode
? 4 : 0)
3882 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3885 switch (GET_MODE (XEXP (x
, 0)))
3888 return (1 + (mode
== DImode
? 4 : 0)
3889 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3892 return (4 + (mode
== DImode
? 4 : 0)
3893 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3896 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3911 if (const_ok_for_arm (INTVAL (x
)))
3912 return outer
== SET
? 2 : -1;
3913 else if (outer
== AND
3914 && const_ok_for_arm (~INTVAL (x
)))
3916 else if ((outer
== COMPARE
3917 || outer
== PLUS
|| outer
== MINUS
)
3918 && const_ok_for_arm (-INTVAL (x
)))
3929 if (arm_const_double_rtx (x
))
3930 return outer
== SET
? 2 : -1;
3931 else if ((outer
== COMPARE
|| outer
== PLUS
)
3932 && neg_const_double_rtx_ok_for_fpa (x
))
3941 /* RTX costs for cores with a slow MUL implementation. */
3944 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3946 enum machine_mode mode
= GET_MODE (x
);
3950 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3957 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3964 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3966 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3967 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3968 int cost
, const_ok
= const_ok_for_arm (i
);
3969 int j
, booth_unit_size
;
3971 /* Tune as appropriate. */
3972 cost
= const_ok
? 4 : 8;
3973 booth_unit_size
= 2;
3974 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3976 i
>>= booth_unit_size
;
3984 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3985 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
3989 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3995 /* RTX cost for cores with a fast multiply unit (M variants). */
3998 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4000 enum machine_mode mode
= GET_MODE (x
);
4004 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4011 /* There is no point basing this on the tuning, since it is always the
4012 fast variant if it exists at all. */
4014 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4015 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4016 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4023 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4030 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4032 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4033 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4034 int cost
, const_ok
= const_ok_for_arm (i
);
4035 int j
, booth_unit_size
;
4037 /* Tune as appropriate. */
4038 cost
= const_ok
? 4 : 8;
4039 booth_unit_size
= 8;
4040 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4042 i
>>= booth_unit_size
;
4050 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4051 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4055 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4061 /* RTX cost for XScale CPUs. */
4064 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4066 enum machine_mode mode
= GET_MODE (x
);
4070 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4077 /* There is no point basing this on the tuning, since it is always the
4078 fast variant if it exists at all. */
4080 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4081 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4082 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4089 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4096 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4098 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4099 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4100 int cost
, const_ok
= const_ok_for_arm (i
);
4101 unsigned HOST_WIDE_INT masked_const
;
4103 /* The cost will be related to two insns.
4104 First a load of the constant (MOV or LDR), then a multiply. */
4107 cost
+= 1; /* LDR is probably more expensive because
4108 of longer result latency. */
4109 masked_const
= i
& 0xffff8000;
4110 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4112 masked_const
= i
& 0xf8000000;
4113 if (masked_const
== 0 || masked_const
== 0xf8000000)
4122 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4123 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4127 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4133 /* RTX costs for 9e (and later) cores. */
4136 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4138 enum machine_mode mode
= GET_MODE (x
);
4147 *total
= COSTS_N_INSNS (3);
4151 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4159 /* There is no point basing this on the tuning, since it is always the
4160 fast variant if it exists at all. */
4162 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4163 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4164 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4171 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4188 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
4189 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
4193 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4197 /* All address computations that can be done are free, but rtx cost returns
4198 the same for practically all of them. So we weight the different types
4199 of address here in the order (most pref first):
4200 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4202 arm_arm_address_cost (rtx x
)
4204 enum rtx_code c
= GET_CODE (x
);
4206 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
4208 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
4211 if (c
== PLUS
|| c
== MINUS
)
4213 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4216 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
4226 arm_thumb_address_cost (rtx x
)
4228 enum rtx_code c
= GET_CODE (x
);
4233 && GET_CODE (XEXP (x
, 0)) == REG
4234 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4241 arm_address_cost (rtx x
)
4243 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
4247 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
4251 /* Some true dependencies can have a higher cost depending
4252 on precisely how certain input operands are used. */
4254 && REG_NOTE_KIND (link
) == 0
4255 && recog_memoized (insn
) >= 0
4256 && recog_memoized (dep
) >= 0)
4258 int shift_opnum
= get_attr_shift (insn
);
4259 enum attr_type attr_type
= get_attr_type (dep
);
4261 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4262 operand for INSN. If we have a shifted input operand and the
4263 instruction we depend on is another ALU instruction, then we may
4264 have to account for an additional stall. */
4265 if (shift_opnum
!= 0
4266 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
4268 rtx shifted_operand
;
4271 /* Get the shifted operand. */
4272 extract_insn (insn
);
4273 shifted_operand
= recog_data
.operand
[shift_opnum
];
4275 /* Iterate over all the operands in DEP. If we write an operand
4276 that overlaps with SHIFTED_OPERAND, then we have increase the
4277 cost of this dependency. */
4279 preprocess_constraints ();
4280 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4282 /* We can ignore strict inputs. */
4283 if (recog_data
.operand_type
[opno
] == OP_IN
)
4286 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
4293 /* XXX This is not strictly true for the FPA. */
4294 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
4295 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4298 /* Call insns don't incur a stall, even if they follow a load. */
4299 if (REG_NOTE_KIND (link
) == 0
4300 && GET_CODE (insn
) == CALL_INSN
)
4303 if ((i_pat
= single_set (insn
)) != NULL
4304 && GET_CODE (SET_SRC (i_pat
)) == MEM
4305 && (d_pat
= single_set (dep
)) != NULL
4306 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
4308 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
4309 /* This is a load after a store, there is no conflict if the load reads
4310 from a cached area. Assume that loads from the stack, and from the
4311 constant pool are cached, and that others will miss. This is a
4314 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
4315 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
4316 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
4317 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
4324 static int fp_consts_inited
= 0;
4326 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4327 static const char * const strings_fp
[8] =
4330 "4", "5", "0.5", "10"
4333 static REAL_VALUE_TYPE values_fp
[8];
4336 init_fp_table (void)
4342 fp_consts_inited
= 1;
4344 fp_consts_inited
= 8;
4346 for (i
= 0; i
< fp_consts_inited
; i
++)
4348 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
4353 /* Return TRUE if rtx X is a valid immediate FP constant. */
4355 arm_const_double_rtx (rtx x
)
4360 if (!fp_consts_inited
)
4363 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4364 if (REAL_VALUE_MINUS_ZERO (r
))
4367 for (i
= 0; i
< fp_consts_inited
; i
++)
4368 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4374 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4376 neg_const_double_rtx_ok_for_fpa (rtx x
)
4381 if (!fp_consts_inited
)
4384 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4385 r
= REAL_VALUE_NEGATE (r
);
4386 if (REAL_VALUE_MINUS_ZERO (r
))
4389 for (i
= 0; i
< 8; i
++)
4390 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4396 /* Predicates for `match_operand' and `match_operator'. */
4398 /* s_register_operand is the same as register_operand, but it doesn't accept
4401 This function exists because at the time it was put in it led to better
4402 code. SUBREG(MEM) always needs a reload in the places where
4403 s_register_operand is used, and this seemed to lead to excessive
4406 s_register_operand (rtx op
, enum machine_mode mode
)
4408 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4411 if (GET_CODE (op
) == SUBREG
)
4412 op
= SUBREG_REG (op
);
4414 /* We don't consider registers whose class is NO_REGS
4415 to be a register operand. */
4416 /* XXX might have to check for lo regs only for thumb ??? */
4417 return (GET_CODE (op
) == REG
4418 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4419 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4422 /* A hard register operand (even before reload. */
4424 arm_hard_register_operand (rtx op
, enum machine_mode mode
)
4426 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4429 return (GET_CODE (op
) == REG
4430 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
4433 /* An arm register operand. */
4435 arm_general_register_operand (rtx op
, enum machine_mode mode
)
4437 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4440 if (GET_CODE (op
) == SUBREG
)
4441 op
= SUBREG_REG (op
);
4443 return (GET_CODE (op
) == REG
4444 && (REGNO (op
) <= LAST_ARM_REGNUM
4445 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
));
4448 /* Only accept reg, subreg(reg), const_int. */
4450 reg_or_int_operand (rtx op
, enum machine_mode mode
)
4452 if (GET_CODE (op
) == CONST_INT
)
4455 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4458 if (GET_CODE (op
) == SUBREG
)
4459 op
= SUBREG_REG (op
);
4461 /* We don't consider registers whose class is NO_REGS
4462 to be a register operand. */
4463 return (GET_CODE (op
) == REG
4464 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4465 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4468 /* Return 1 if OP is an item in memory, given that we are in reload. */
4470 arm_reload_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4472 int regno
= true_regnum (op
);
4474 return (!CONSTANT_P (op
)
4476 || (GET_CODE (op
) == REG
4477 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
4480 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4482 arm_rhs_operand (rtx op
, enum machine_mode mode
)
4484 return (s_register_operand (op
, mode
)
4485 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
4488 /* Return TRUE for valid operands for the
4489 rhs of an ARM instruction, or a load. */
4491 arm_rhsm_operand (rtx op
, enum machine_mode mode
)
4493 return (s_register_operand (op
, mode
)
4494 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
4495 || memory_operand (op
, mode
));
4498 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4499 constant that is valid when negated. */
4501 arm_add_operand (rtx op
, enum machine_mode mode
)
4504 return thumb_cmp_operand (op
, mode
);
4506 return (s_register_operand (op
, mode
)
4507 || (GET_CODE (op
) == CONST_INT
4508 && (const_ok_for_arm (INTVAL (op
))
4509 || const_ok_for_arm (-INTVAL (op
)))));
4512 /* Return TRUE for valid ARM constants (or when valid if negated). */
4514 arm_addimm_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4516 return (GET_CODE (op
) == CONST_INT
4517 && (const_ok_for_arm (INTVAL (op
))
4518 || const_ok_for_arm (-INTVAL (op
))));
4522 arm_not_operand (rtx op
, enum machine_mode mode
)
4524 return (s_register_operand (op
, mode
)
4525 || (GET_CODE (op
) == CONST_INT
4526 && (const_ok_for_arm (INTVAL (op
))
4527 || const_ok_for_arm (~INTVAL (op
)))));
4530 /* Return TRUE if the operand is a memory reference which contains an
4531 offsettable address. */
4533 offsettable_memory_operand (rtx op
, enum machine_mode mode
)
4535 if (mode
== VOIDmode
)
4536 mode
= GET_MODE (op
);
4538 return (mode
== GET_MODE (op
)
4539 && GET_CODE (op
) == MEM
4540 && offsettable_address_p (reload_completed
| reload_in_progress
,
4541 mode
, XEXP (op
, 0)));
4544 /* Return TRUE if the operand is a memory reference which is, or can be
4545 made word aligned by adjusting the offset. */
4547 alignable_memory_operand (rtx op
, enum machine_mode mode
)
4551 if (mode
== VOIDmode
)
4552 mode
= GET_MODE (op
);
4554 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
4559 return ((GET_CODE (reg
= op
) == REG
4560 || (GET_CODE (op
) == SUBREG
4561 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
4562 || (GET_CODE (op
) == PLUS
4563 && GET_CODE (XEXP (op
, 1)) == CONST_INT
4564 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
4565 || (GET_CODE (XEXP (op
, 0)) == SUBREG
4566 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
4567 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
4570 /* Similar to s_register_operand, but does not allow hard integer
4573 f_register_operand (rtx op
, enum machine_mode mode
)
4575 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4578 if (GET_CODE (op
) == SUBREG
)
4579 op
= SUBREG_REG (op
);
4581 /* We don't consider registers whose class is NO_REGS
4582 to be a register operand. */
4583 return (GET_CODE (op
) == REG
4584 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4585 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
4588 /* Return TRUE for valid operands for the rhs of an floating point insns.
4589 Allows regs or certain consts on FPA, just regs for everything else. */
4591 arm_float_rhs_operand (rtx op
, enum machine_mode mode
)
4593 if (s_register_operand (op
, mode
))
4596 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4599 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4600 return arm_const_double_rtx (op
);
4606 arm_float_add_operand (rtx op
, enum machine_mode mode
)
4608 if (s_register_operand (op
, mode
))
4611 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4614 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4615 return (arm_const_double_rtx (op
)
4616 || neg_const_double_rtx_ok_for_fpa (op
));
4622 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4623 Depends which fpu we are targeting. */
4626 arm_float_compare_operand (rtx op
, enum machine_mode mode
)
4629 return vfp_compare_operand (op
, mode
);
4631 return arm_float_rhs_operand (op
, mode
);
4635 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4637 cirrus_memory_offset (rtx op
)
4639 /* Reject eliminable registers. */
4640 if (! (reload_in_progress
|| reload_completed
)
4641 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4642 || reg_mentioned_p (arg_pointer_rtx
, op
)
4643 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4644 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4645 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4646 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4649 if (GET_CODE (op
) == MEM
)
4655 /* Match: (mem (reg)). */
4656 if (GET_CODE (ind
) == REG
)
4662 if (GET_CODE (ind
) == PLUS
4663 && GET_CODE (XEXP (ind
, 0)) == REG
4664 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4665 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4673 arm_extendqisi_mem_op (rtx op
, enum machine_mode mode
)
4675 if (!memory_operand (op
, mode
))
4678 return arm_legitimate_address_p (mode
, XEXP (op
, 0), SIGN_EXTEND
, 0);
4681 /* Return nonzero if OP is a Cirrus or general register. */
4683 cirrus_register_operand (rtx op
, enum machine_mode mode
)
4685 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4688 if (GET_CODE (op
) == SUBREG
)
4689 op
= SUBREG_REG (op
);
4691 return (GET_CODE (op
) == REG
4692 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
4693 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
4696 /* Return nonzero if OP is a cirrus FP register. */
4698 cirrus_fp_register (rtx op
, enum machine_mode mode
)
4700 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4703 if (GET_CODE (op
) == SUBREG
)
4704 op
= SUBREG_REG (op
);
4706 return (GET_CODE (op
) == REG
4707 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4708 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
4711 /* Return nonzero if OP is a 6bit constant (0..63). */
4713 cirrus_shift_const (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4715 return (GET_CODE (op
) == CONST_INT
4717 && INTVAL (op
) < 64);
4721 /* Return TRUE if OP is a valid VFP memory address pattern.
4722 WB if true if writeback address modes are allowed. */
4725 arm_coproc_mem_operand (rtx op
, bool wb
)
4729 /* Reject eliminable registers. */
4730 if (! (reload_in_progress
|| reload_completed
)
4731 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4732 || reg_mentioned_p (arg_pointer_rtx
, op
)
4733 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4734 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4735 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4736 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4739 /* Constants are converted into offsets from labels. */
4740 if (GET_CODE (op
) != MEM
)
4745 if (reload_completed
4746 && (GET_CODE (ind
) == LABEL_REF
4747 || (GET_CODE (ind
) == CONST
4748 && GET_CODE (XEXP (ind
, 0)) == PLUS
4749 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
4750 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
4753 /* Match: (mem (reg)). */
4754 if (GET_CODE (ind
) == REG
)
4755 return arm_address_register_rtx_p (ind
, 0);
4757 /* Autoincremment addressing modes. */
4759 && (GET_CODE (ind
) == PRE_INC
4760 || GET_CODE (ind
) == POST_INC
4761 || GET_CODE (ind
) == PRE_DEC
4762 || GET_CODE (ind
) == POST_DEC
))
4763 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
4766 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
4767 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
4768 && GET_CODE (XEXP (ind
, 1)) == PLUS
4769 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
4770 ind
= XEXP (ind
, 1);
4775 if (GET_CODE (ind
) == PLUS
4776 && GET_CODE (XEXP (ind
, 0)) == REG
4777 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4778 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
4779 && INTVAL (XEXP (ind
, 1)) > -1024
4780 && INTVAL (XEXP (ind
, 1)) < 1024
4781 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
4788 /* Return TRUE if OP is a REG or constant zero. */
4790 vfp_compare_operand (rtx op
, enum machine_mode mode
)
4792 if (s_register_operand (op
, mode
))
4795 return (GET_CODE (op
) == CONST_DOUBLE
4796 && arm_const_double_rtx (op
));
4800 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4801 VFP registers. Otherwise return NO_REGS. */
4804 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
4806 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
4809 return GENERAL_REGS
;
4813 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4814 Use by the Cirrus Maverick code which has to workaround
4815 a hardware bug triggered by such instructions. */
4817 arm_memory_load_p (rtx insn
)
4819 rtx body
, lhs
, rhs
;;
4821 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
4824 body
= PATTERN (insn
);
4826 if (GET_CODE (body
) != SET
)
4829 lhs
= XEXP (body
, 0);
4830 rhs
= XEXP (body
, 1);
4832 lhs
= REG_OR_SUBREG_RTX (lhs
);
4834 /* If the destination is not a general purpose
4835 register we do not have to worry. */
4836 if (GET_CODE (lhs
) != REG
4837 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
4840 /* As well as loads from memory we also have to react
4841 to loads of invalid constants which will be turned
4842 into loads from the minipool. */
4843 return (GET_CODE (rhs
) == MEM
4844 || GET_CODE (rhs
) == SYMBOL_REF
4845 || note_invalid_constants (insn
, -1, false));
4848 /* Return TRUE if INSN is a Cirrus instruction. */
4850 arm_cirrus_insn_p (rtx insn
)
4852 enum attr_cirrus attr
;
4854 /* get_attr aborts on USE and CLOBBER. */
4856 || GET_CODE (insn
) != INSN
4857 || GET_CODE (PATTERN (insn
)) == USE
4858 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4861 attr
= get_attr_cirrus (insn
);
4863 return attr
!= CIRRUS_NOT
;
4866 /* Cirrus reorg for invalid instruction combinations. */
4868 cirrus_reorg (rtx first
)
4870 enum attr_cirrus attr
;
4871 rtx body
= PATTERN (first
);
4875 /* Any branch must be followed by 2 non Cirrus instructions. */
4876 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4879 t
= next_nonnote_insn (first
);
4881 if (arm_cirrus_insn_p (t
))
4884 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4888 emit_insn_after (gen_nop (), first
);
4893 /* (float (blah)) is in parallel with a clobber. */
4894 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4895 body
= XVECEXP (body
, 0, 0);
4897 if (GET_CODE (body
) == SET
)
4899 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4901 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4902 be followed by a non Cirrus insn. */
4903 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4905 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4906 emit_insn_after (gen_nop (), first
);
4910 else if (arm_memory_load_p (first
))
4912 unsigned int arm_regno
;
4914 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4915 ldr/cfmv64hr combination where the Rd field is the same
4916 in both instructions must be split with a non Cirrus
4923 /* Get Arm register number for ldr insn. */
4924 if (GET_CODE (lhs
) == REG
)
4925 arm_regno
= REGNO (lhs
);
4926 else if (GET_CODE (rhs
) == REG
)
4927 arm_regno
= REGNO (rhs
);
4932 first
= next_nonnote_insn (first
);
4934 if (! arm_cirrus_insn_p (first
))
4937 body
= PATTERN (first
);
4939 /* (float (blah)) is in parallel with a clobber. */
4940 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4941 body
= XVECEXP (body
, 0, 0);
4943 if (GET_CODE (body
) == FLOAT
)
4944 body
= XEXP (body
, 0);
4946 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4947 && GET_CODE (XEXP (body
, 1)) == REG
4948 && arm_regno
== REGNO (XEXP (body
, 1)))
4949 emit_insn_after (gen_nop (), first
);
4955 /* get_attr aborts on USE and CLOBBER. */
4957 || GET_CODE (first
) != INSN
4958 || GET_CODE (PATTERN (first
)) == USE
4959 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4962 attr
= get_attr_cirrus (first
);
4964 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4965 must be followed by a non-coprocessor instruction. */
4966 if (attr
== CIRRUS_COMPARE
)
4970 t
= next_nonnote_insn (first
);
4972 if (arm_cirrus_insn_p (t
))
4975 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4979 emit_insn_after (gen_nop (), first
);
4985 /* Return nonzero if OP is a constant power of two. */
4987 power_of_two_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4989 if (GET_CODE (op
) == CONST_INT
)
4991 HOST_WIDE_INT value
= INTVAL (op
);
4993 return value
!= 0 && (value
& (value
- 1)) == 0;
4999 /* Return TRUE for a valid operand of a DImode operation.
5000 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
5001 Note that this disallows MEM(REG+REG), but allows
5002 MEM(PRE/POST_INC/DEC(REG)). */
5004 di_operand (rtx op
, enum machine_mode mode
)
5006 if (s_register_operand (op
, mode
))
5009 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
5012 if (GET_CODE (op
) == SUBREG
)
5013 op
= SUBREG_REG (op
);
5015 switch (GET_CODE (op
))
5022 return memory_address_p (DImode
, XEXP (op
, 0));
5029 /* Like di_operand, but don't accept constants. */
5031 nonimmediate_di_operand (rtx op
, enum machine_mode mode
)
5033 if (s_register_operand (op
, mode
))
5036 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
5039 if (GET_CODE (op
) == SUBREG
)
5040 op
= SUBREG_REG (op
);
5042 if (GET_CODE (op
) == MEM
)
5043 return memory_address_p (DImode
, XEXP (op
, 0));
5048 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
5049 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
5050 Note that this disallows MEM(REG+REG), but allows
5051 MEM(PRE/POST_INC/DEC(REG)). */
5053 soft_df_operand (rtx op
, enum machine_mode mode
)
5055 if (s_register_operand (op
, mode
))
5058 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
5061 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
5064 if (GET_CODE (op
) == SUBREG
)
5065 op
= SUBREG_REG (op
);
5067 switch (GET_CODE (op
))
5073 return memory_address_p (DFmode
, XEXP (op
, 0));
5080 /* Like soft_df_operand, but don't accept constants. */
5082 nonimmediate_soft_df_operand (rtx op
, enum machine_mode mode
)
5084 if (s_register_operand (op
, mode
))
5087 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
5090 if (GET_CODE (op
) == SUBREG
)
5091 op
= SUBREG_REG (op
);
5093 if (GET_CODE (op
) == MEM
)
5094 return memory_address_p (DFmode
, XEXP (op
, 0));
5098 /* Return TRUE for valid index operands. */
5100 index_operand (rtx op
, enum machine_mode mode
)
5102 return (s_register_operand (op
, mode
)
5103 || (immediate_operand (op
, mode
)
5104 && (GET_CODE (op
) != CONST_INT
5105 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
5108 /* Return TRUE for valid shifts by a constant. This also accepts any
5109 power of two on the (somewhat overly relaxed) assumption that the
5110 shift operator in this case was a mult. */
5112 const_shift_operand (rtx op
, enum machine_mode mode
)
5114 return (power_of_two_operand (op
, mode
)
5115 || (immediate_operand (op
, mode
)
5116 && (GET_CODE (op
) != CONST_INT
5117 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
5120 /* Return TRUE for arithmetic operators which can be combined with a multiply
5123 shiftable_operator (rtx x
, enum machine_mode mode
)
5127 if (GET_MODE (x
) != mode
)
5130 code
= GET_CODE (x
);
5132 return (code
== PLUS
|| code
== MINUS
5133 || code
== IOR
|| code
== XOR
|| code
== AND
);
5136 /* Return TRUE for binary logical operators. */
5138 logical_binary_operator (rtx x
, enum machine_mode mode
)
5142 if (GET_MODE (x
) != mode
)
5145 code
= GET_CODE (x
);
5147 return (code
== IOR
|| code
== XOR
|| code
== AND
);
5150 /* Return TRUE for shift operators. */
5152 shift_operator (rtx x
,enum machine_mode mode
)
5156 if (GET_MODE (x
) != mode
)
5159 code
= GET_CODE (x
);
5162 return power_of_two_operand (XEXP (x
, 1), mode
);
5164 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
5165 || code
== ROTATERT
);
5168 /* Return TRUE if x is EQ or NE. */
5170 equality_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5172 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
5175 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5177 arm_comparison_operator (rtx x
, enum machine_mode mode
)
5179 return (comparison_operator (x
, mode
)
5180 && GET_CODE (x
) != LTGT
5181 && GET_CODE (x
) != UNEQ
);
5184 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5186 minmax_operator (rtx x
, enum machine_mode mode
)
5188 enum rtx_code code
= GET_CODE (x
);
5190 if (GET_MODE (x
) != mode
)
5193 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
5196 /* Return TRUE if this is the condition code register, if we aren't given
5197 a mode, accept any class CCmode register. */
5199 cc_register (rtx x
, enum machine_mode mode
)
5201 if (mode
== VOIDmode
)
5203 mode
= GET_MODE (x
);
5205 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5209 if ( GET_MODE (x
) == mode
5210 && GET_CODE (x
) == REG
5211 && REGNO (x
) == CC_REGNUM
)
5217 /* Return TRUE if this is the condition code register, if we aren't given
5218 a mode, accept any class CCmode register which indicates a dominance
5221 dominant_cc_register (rtx x
, enum machine_mode mode
)
5223 if (mode
== VOIDmode
)
5225 mode
= GET_MODE (x
);
5227 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5231 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
5232 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
5233 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
5234 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
5235 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
5238 return cc_register (x
, mode
);
5241 /* Return TRUE if X references a SYMBOL_REF. */
5243 symbol_mentioned_p (rtx x
)
5248 if (GET_CODE (x
) == SYMBOL_REF
)
5251 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5253 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5259 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5260 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5263 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5270 /* Return TRUE if X references a LABEL_REF. */
5272 label_mentioned_p (rtx x
)
5277 if (GET_CODE (x
) == LABEL_REF
)
5280 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5281 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5287 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5288 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5291 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5301 enum rtx_code code
= GET_CODE (x
);
5305 else if (code
== SMIN
)
5307 else if (code
== UMIN
)
5309 else if (code
== UMAX
)
5315 /* Return 1 if memory locations are adjacent. */
5317 adjacent_mem_locations (rtx a
, rtx b
)
5319 if ((GET_CODE (XEXP (a
, 0)) == REG
5320 || (GET_CODE (XEXP (a
, 0)) == PLUS
5321 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5322 && (GET_CODE (XEXP (b
, 0)) == REG
5323 || (GET_CODE (XEXP (b
, 0)) == PLUS
5324 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5326 int val0
= 0, val1
= 0;
5329 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5331 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
5332 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5335 reg0
= REGNO (XEXP (a
, 0));
5337 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5339 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
5340 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5343 reg1
= REGNO (XEXP (b
, 0));
5345 /* Don't accept any offset that will require multiple
5346 instructions to handle, since this would cause the
5347 arith_adjacentmem pattern to output an overlong sequence. */
5348 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5351 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
5356 /* Return 1 if OP is a load multiple operation. It is known to be
5357 parallel and the first section will be tested. */
5359 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5361 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5364 HOST_WIDE_INT i
= 1, base
= 0;
5368 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5371 /* Check to see if this might be a write-back. */
5372 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5377 /* Now check it more carefully. */
5378 if (GET_CODE (SET_DEST (elt
)) != REG
5379 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5380 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5381 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5385 /* Perform a quick check so we don't blow up below. */
5387 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5388 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
5389 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
5392 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
5393 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
5395 for (; i
< count
; i
++)
5397 elt
= XVECEXP (op
, 0, i
);
5399 if (GET_CODE (elt
) != SET
5400 || GET_CODE (SET_DEST (elt
)) != REG
5401 || GET_MODE (SET_DEST (elt
)) != SImode
5402 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
5403 || GET_CODE (SET_SRC (elt
)) != MEM
5404 || GET_MODE (SET_SRC (elt
)) != SImode
5405 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
5406 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
5407 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
5408 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
5415 /* Return 1 if OP is a store multiple operation. It is known to be
5416 parallel and the first section will be tested. */
5418 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5420 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5423 HOST_WIDE_INT i
= 1, base
= 0;
5427 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5430 /* Check to see if this might be a write-back. */
5431 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5436 /* Now check it more carefully. */
5437 if (GET_CODE (SET_DEST (elt
)) != REG
5438 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5439 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5440 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5444 /* Perform a quick check so we don't blow up below. */
5446 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5447 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
5448 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
5451 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
5452 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
5454 for (; i
< count
; i
++)
5456 elt
= XVECEXP (op
, 0, i
);
5458 if (GET_CODE (elt
) != SET
5459 || GET_CODE (SET_SRC (elt
)) != REG
5460 || GET_MODE (SET_SRC (elt
)) != SImode
5461 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
5462 || GET_CODE (SET_DEST (elt
)) != MEM
5463 || GET_MODE (SET_DEST (elt
)) != SImode
5464 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
5465 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
5466 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
5467 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
5475 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5476 HOST_WIDE_INT
*load_offset
)
5478 int unsorted_regs
[4];
5479 HOST_WIDE_INT unsorted_offsets
[4];
5484 /* Can only handle 2, 3, or 4 insns at present,
5485 though could be easily extended if required. */
5486 if (nops
< 2 || nops
> 4)
5489 /* Loop over the operands and check that the memory references are
5490 suitable (ie immediate offsets from the same base register). At
5491 the same time, extract the target register, and the memory
5493 for (i
= 0; i
< nops
; i
++)
5498 /* Convert a subreg of a mem into the mem itself. */
5499 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5500 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5502 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5505 /* Don't reorder volatile memory references; it doesn't seem worth
5506 looking for the case where the order is ok anyway. */
5507 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5510 offset
= const0_rtx
;
5512 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5513 || (GET_CODE (reg
) == SUBREG
5514 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5515 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5516 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5518 || (GET_CODE (reg
) == SUBREG
5519 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5520 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5525 base_reg
= REGNO (reg
);
5526 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5527 ? REGNO (operands
[i
])
5528 : REGNO (SUBREG_REG (operands
[i
])));
5533 if (base_reg
!= (int) REGNO (reg
))
5534 /* Not addressed from the same base register. */
5537 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5538 ? REGNO (operands
[i
])
5539 : REGNO (SUBREG_REG (operands
[i
])));
5540 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5544 /* If it isn't an integer register, or if it overwrites the
5545 base register but isn't the last insn in the list, then
5546 we can't do this. */
5547 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5548 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5551 unsorted_offsets
[i
] = INTVAL (offset
);
5554 /* Not a suitable memory address. */
5558 /* All the useful information has now been extracted from the
5559 operands into unsorted_regs and unsorted_offsets; additionally,
5560 order[0] has been set to the lowest numbered register in the
5561 list. Sort the registers into order, and check that the memory
5562 offsets are ascending and adjacent. */
5564 for (i
= 1; i
< nops
; i
++)
5568 order
[i
] = order
[i
- 1];
5569 for (j
= 0; j
< nops
; j
++)
5570 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5571 && (order
[i
] == order
[i
- 1]
5572 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5575 /* Have we found a suitable register? if not, one must be used more
5577 if (order
[i
] == order
[i
- 1])
5580 /* Is the memory address adjacent and ascending? */
5581 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5589 for (i
= 0; i
< nops
; i
++)
5590 regs
[i
] = unsorted_regs
[order
[i
]];
5592 *load_offset
= unsorted_offsets
[order
[0]];
5595 if (unsorted_offsets
[order
[0]] == 0)
5596 return 1; /* ldmia */
5598 if (unsorted_offsets
[order
[0]] == 4)
5599 return 2; /* ldmib */
5601 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5602 return 3; /* ldmda */
5604 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5605 return 4; /* ldmdb */
5607 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5608 if the offset isn't small enough. The reason 2 ldrs are faster
5609 is because these ARMs are able to do more than one cache access
5610 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5611 whilst the ARM8 has a double bandwidth cache. This means that
5612 these cores can do both an instruction fetch and a data fetch in
5613 a single cycle, so the trick of calculating the address into a
5614 scratch register (one of the result regs) and then doing a load
5615 multiple actually becomes slower (and no smaller in code size).
5616 That is the transformation
5618 ldr rd1, [rbase + offset]
5619 ldr rd2, [rbase + offset + 4]
5623 add rd1, rbase, offset
5624 ldmia rd1, {rd1, rd2}
5626 produces worse code -- '3 cycles + any stalls on rd2' instead of
5627 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5628 access per cycle, the first sequence could never complete in less
5629 than 6 cycles, whereas the ldm sequence would only take 5 and
5630 would make better use of sequential accesses if not hitting the
5633 We cheat here and test 'arm_ld_sched' which we currently know to
5634 only be true for the ARM8, ARM9 and StrongARM. If this ever
5635 changes, then the test below needs to be reworked. */
5636 if (nops
== 2 && arm_ld_sched
)
5639 /* Can't do it without setting up the offset, only do this if it takes
5640 no more than one insn. */
5641 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5642 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5646 emit_ldm_seq (rtx
*operands
, int nops
)
5650 HOST_WIDE_INT offset
;
5654 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5657 strcpy (buf
, "ldm%?ia\t");
5661 strcpy (buf
, "ldm%?ib\t");
5665 strcpy (buf
, "ldm%?da\t");
5669 strcpy (buf
, "ldm%?db\t");
5674 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5675 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5678 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5679 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5681 output_asm_insn (buf
, operands
);
5683 strcpy (buf
, "ldm%?ia\t");
5690 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5691 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5693 for (i
= 1; i
< nops
; i
++)
5694 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5695 reg_names
[regs
[i
]]);
5697 strcat (buf
, "}\t%@ phole ldm");
5699 output_asm_insn (buf
, operands
);
5704 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5705 HOST_WIDE_INT
* load_offset
)
5707 int unsorted_regs
[4];
5708 HOST_WIDE_INT unsorted_offsets
[4];
5713 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5714 extended if required. */
5715 if (nops
< 2 || nops
> 4)
5718 /* Loop over the operands and check that the memory references are
5719 suitable (ie immediate offsets from the same base register). At
5720 the same time, extract the target register, and the memory
5722 for (i
= 0; i
< nops
; i
++)
5727 /* Convert a subreg of a mem into the mem itself. */
5728 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5729 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5731 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5734 /* Don't reorder volatile memory references; it doesn't seem worth
5735 looking for the case where the order is ok anyway. */
5736 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5739 offset
= const0_rtx
;
5741 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5742 || (GET_CODE (reg
) == SUBREG
5743 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5744 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5745 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5747 || (GET_CODE (reg
) == SUBREG
5748 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5749 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5754 base_reg
= REGNO (reg
);
5755 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5756 ? REGNO (operands
[i
])
5757 : REGNO (SUBREG_REG (operands
[i
])));
5762 if (base_reg
!= (int) REGNO (reg
))
5763 /* Not addressed from the same base register. */
5766 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5767 ? REGNO (operands
[i
])
5768 : REGNO (SUBREG_REG (operands
[i
])));
5769 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5773 /* If it isn't an integer register, then we can't do this. */
5774 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5777 unsorted_offsets
[i
] = INTVAL (offset
);
5780 /* Not a suitable memory address. */
5784 /* All the useful information has now been extracted from the
5785 operands into unsorted_regs and unsorted_offsets; additionally,
5786 order[0] has been set to the lowest numbered register in the
5787 list. Sort the registers into order, and check that the memory
5788 offsets are ascending and adjacent. */
5790 for (i
= 1; i
< nops
; i
++)
5794 order
[i
] = order
[i
- 1];
5795 for (j
= 0; j
< nops
; j
++)
5796 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5797 && (order
[i
] == order
[i
- 1]
5798 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5801 /* Have we found a suitable register? if not, one must be used more
5803 if (order
[i
] == order
[i
- 1])
5806 /* Is the memory address adjacent and ascending? */
5807 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5815 for (i
= 0; i
< nops
; i
++)
5816 regs
[i
] = unsorted_regs
[order
[i
]];
5818 *load_offset
= unsorted_offsets
[order
[0]];
5821 if (unsorted_offsets
[order
[0]] == 0)
5822 return 1; /* stmia */
5824 if (unsorted_offsets
[order
[0]] == 4)
5825 return 2; /* stmib */
5827 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5828 return 3; /* stmda */
5830 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5831 return 4; /* stmdb */
5837 emit_stm_seq (rtx
*operands
, int nops
)
5841 HOST_WIDE_INT offset
;
5845 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5848 strcpy (buf
, "stm%?ia\t");
5852 strcpy (buf
, "stm%?ib\t");
5856 strcpy (buf
, "stm%?da\t");
5860 strcpy (buf
, "stm%?db\t");
5867 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5868 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5870 for (i
= 1; i
< nops
; i
++)
5871 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5872 reg_names
[regs
[i
]]);
5874 strcat (buf
, "}\t%@ phole stm");
5876 output_asm_insn (buf
, operands
);
5881 multi_register_push (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5883 if (GET_CODE (op
) != PARALLEL
5884 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5885 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5886 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5892 /* Routines for use in generating RTL. */
5895 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5896 int write_back
, int unchanging_p
, int in_struct_p
,
5901 int sign
= up
? 1 : -1;
5904 /* XScale has load-store double instructions, but they have stricter
5905 alignment requirements than load-store multiple, so we cannot
5908 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5909 the pipeline until completion.
5917 An ldr instruction takes 1-3 cycles, but does not block the
5926 Best case ldr will always win. However, the more ldr instructions
5927 we issue, the less likely we are to be able to schedule them well.
5928 Using ldr instructions also increases code size.
5930 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5931 for counts of 3 or 4 regs. */
5932 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5938 for (i
= 0; i
< count
; i
++)
5940 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5941 MEM_READONLY_P (mem
) = unchanging_p
;
5942 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5943 MEM_SCALAR_P (mem
) = scalar_p
;
5944 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5948 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5956 result
= gen_rtx_PARALLEL (VOIDmode
,
5957 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5960 XVECEXP (result
, 0, 0)
5961 = gen_rtx_SET (GET_MODE (from
), from
,
5962 plus_constant (from
, count
* 4 * sign
));
5967 for (j
= 0; i
< count
; i
++, j
++)
5969 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5970 MEM_READONLY_P (mem
) = unchanging_p
;
5971 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5972 MEM_SCALAR_P (mem
) = scalar_p
;
5973 XVECEXP (result
, 0, i
)
5974 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5981 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5982 int write_back
, int unchanging_p
, int in_struct_p
,
5987 int sign
= up
? 1 : -1;
5990 /* See arm_gen_load_multiple for discussion of
5991 the pros/cons of ldm/stm usage for XScale. */
5992 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5998 for (i
= 0; i
< count
; i
++)
6000 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
6001 MEM_READONLY_P (mem
) = unchanging_p
;
6002 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
6003 MEM_SCALAR_P (mem
) = scalar_p
;
6004 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6008 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6016 result
= gen_rtx_PARALLEL (VOIDmode
,
6017 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6020 XVECEXP (result
, 0, 0)
6021 = gen_rtx_SET (GET_MODE (to
), to
,
6022 plus_constant (to
, count
* 4 * sign
));
6027 for (j
= 0; i
< count
; i
++, j
++)
6029 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
6030 MEM_READONLY_P (mem
) = unchanging_p
;
6031 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
6032 MEM_SCALAR_P (mem
) = scalar_p
;
6034 XVECEXP (result
, 0, i
)
6035 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6042 arm_gen_movmemqi (rtx
*operands
)
6044 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6047 rtx st_src
, st_dst
, fin_src
, fin_dst
;
6048 rtx part_bytes_reg
= NULL
;
6050 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
6051 int dst_scalar_p
, src_scalar_p
;
6053 if (GET_CODE (operands
[2]) != CONST_INT
6054 || GET_CODE (operands
[3]) != CONST_INT
6055 || INTVAL (operands
[2]) > 64
6056 || INTVAL (operands
[3]) & 3)
6059 st_dst
= XEXP (operands
[0], 0);
6060 st_src
= XEXP (operands
[1], 0);
6062 dst_unchanging_p
= MEM_READONLY_P (operands
[0]);
6063 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
6064 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
6065 src_unchanging_p
= MEM_READONLY_P (operands
[1]);
6066 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
6067 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
6069 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
6070 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
6072 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6073 out_words_to_go
= INTVAL (operands
[2]) / 4;
6074 last_bytes
= INTVAL (operands
[2]) & 3;
6076 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6077 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6079 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6081 if (in_words_to_go
> 4)
6082 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6087 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6088 FALSE
, src_unchanging_p
,
6089 src_in_struct_p
, src_scalar_p
));
6091 if (out_words_to_go
)
6093 if (out_words_to_go
> 4)
6094 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6098 else if (out_words_to_go
!= 1)
6099 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6108 mem
= gen_rtx_MEM (SImode
, dst
);
6109 MEM_READONLY_P (mem
) = dst_unchanging_p
;
6110 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6111 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6112 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6113 if (last_bytes
!= 0)
6114 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6118 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6119 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6122 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6123 if (out_words_to_go
)
6127 mem
= gen_rtx_MEM (SImode
, src
);
6128 MEM_READONLY_P (mem
) = src_unchanging_p
;
6129 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6130 MEM_SCALAR_P (mem
) = src_scalar_p
;
6131 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
6132 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
6134 mem
= gen_rtx_MEM (SImode
, dst
);
6135 MEM_READONLY_P (mem
) = dst_unchanging_p
;
6136 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6137 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6138 emit_move_insn (mem
, sreg
);
6139 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
6142 if (in_words_to_go
) /* Sanity check */
6148 if (in_words_to_go
< 0)
6151 mem
= gen_rtx_MEM (SImode
, src
);
6152 MEM_READONLY_P (mem
) = src_unchanging_p
;
6153 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6154 MEM_SCALAR_P (mem
) = src_scalar_p
;
6155 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6158 if (last_bytes
&& part_bytes_reg
== NULL
)
6161 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6163 rtx tmp
= gen_reg_rtx (SImode
);
6165 /* The bytes we want are in the top end of the word. */
6166 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6167 GEN_INT (8 * (4 - last_bytes
))));
6168 part_bytes_reg
= tmp
;
6172 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
6173 MEM_READONLY_P (mem
) = dst_unchanging_p
;
6174 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6175 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6176 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6180 tmp
= gen_reg_rtx (SImode
);
6181 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6182 part_bytes_reg
= tmp
;
6191 mem
= gen_rtx_MEM (HImode
, dst
);
6192 MEM_READONLY_P (mem
) = dst_unchanging_p
;
6193 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6194 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6195 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6199 rtx tmp
= gen_reg_rtx (SImode
);
6201 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6202 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6203 part_bytes_reg
= tmp
;
6209 mem
= gen_rtx_MEM (QImode
, dst
);
6210 MEM_READONLY_P (mem
) = dst_unchanging_p
;
6211 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6212 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6213 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6220 /* Generate a memory reference for a half word, such that it will be loaded
6221 into the top 16 bits of the word. We can assume that the address is
6222 known to be alignable and of the form reg, or plus (reg, const). */
6225 arm_gen_rotated_half_load (rtx memref
)
6227 HOST_WIDE_INT offset
= 0;
6228 rtx base
= XEXP (memref
, 0);
6230 if (GET_CODE (base
) == PLUS
)
6232 offset
= INTVAL (XEXP (base
, 1));
6233 base
= XEXP (base
, 0);
6236 /* If we aren't allowed to generate unaligned addresses, then fail. */
6237 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0))
6240 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
6242 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
6245 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
6248 /* Select a dominance comparison mode if possible for a test of the general
6249 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6250 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6251 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6252 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6253 In all cases OP will be either EQ or NE, but we don't need to know which
6254 here. If we are unable to support a dominance comparison we return
6255 CC mode. This will then fail to match for the RTL expressions that
6256 generate this call. */
6258 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6260 enum rtx_code cond1
, cond2
;
6263 /* Currently we will probably get the wrong result if the individual
6264 comparisons are not simple. This also ensures that it is safe to
6265 reverse a comparison if necessary. */
6266 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6268 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6272 /* The if_then_else variant of this tests the second condition if the
6273 first passes, but is true if the first fails. Reverse the first
6274 condition to get a true "inclusive-or" expression. */
6275 if (cond_or
== DOM_CC_NX_OR_Y
)
6276 cond1
= reverse_condition (cond1
);
6278 /* If the comparisons are not equal, and one doesn't dominate the other,
6279 then we can't do this. */
6281 && !comparison_dominates_p (cond1
, cond2
)
6282 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6287 enum rtx_code temp
= cond1
;
6295 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
6300 case LE
: return CC_DLEmode
;
6301 case LEU
: return CC_DLEUmode
;
6302 case GE
: return CC_DGEmode
;
6303 case GEU
: return CC_DGEUmode
;
6310 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
6319 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
6328 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
6337 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
6345 /* The remaining cases only occur when both comparisons are the
6370 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6372 /* All floating point compares return CCFP if it is an equality
6373 comparison, and CCFPE otherwise. */
6374 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6394 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6403 /* A compare with a shifted operand. Because of canonicalization, the
6404 comparison will have to be swapped when we emit the assembler. */
6405 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6406 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6407 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6408 || GET_CODE (x
) == ROTATERT
))
6411 /* This is a special case that is used by combine to allow a
6412 comparison of a shifted byte load to be split into a zero-extend
6413 followed by a comparison of the shifted integer (only valid for
6414 equalities and unsigned inequalities). */
6415 if (GET_MODE (x
) == SImode
6416 && GET_CODE (x
) == ASHIFT
6417 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6418 && GET_CODE (XEXP (x
, 0)) == SUBREG
6419 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6420 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6421 && (op
== EQ
|| op
== NE
6422 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6423 && GET_CODE (y
) == CONST_INT
)
6426 /* A construct for a conditional compare, if the false arm contains
6427 0, then both conditions must be true, otherwise either condition
6428 must be true. Not all conditions are possible, so CCmode is
6429 returned if it can't be done. */
6430 if (GET_CODE (x
) == IF_THEN_ELSE
6431 && (XEXP (x
, 2) == const0_rtx
6432 || XEXP (x
, 2) == const1_rtx
)
6433 && COMPARISON_P (XEXP (x
, 0))
6434 && COMPARISON_P (XEXP (x
, 1)))
6435 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6436 INTVAL (XEXP (x
, 2)));
6438 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6439 if (GET_CODE (x
) == AND
6440 && COMPARISON_P (XEXP (x
, 0))
6441 && COMPARISON_P (XEXP (x
, 1)))
6442 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6445 if (GET_CODE (x
) == IOR
6446 && COMPARISON_P (XEXP (x
, 0))
6447 && COMPARISON_P (XEXP (x
, 1)))
6448 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6451 /* An operation (on Thumb) where we want to test for a single bit.
6452 This is done by shifting that bit up into the top bit of a
6453 scratch register; we can then branch on the sign bit. */
6455 && GET_MODE (x
) == SImode
6456 && (op
== EQ
|| op
== NE
)
6457 && (GET_CODE (x
) == ZERO_EXTRACT
))
6460 /* An operation that sets the condition codes as a side-effect, the
6461 V flag is not set correctly, so we can only use comparisons where
6462 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6464 if (GET_MODE (x
) == SImode
6466 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6467 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6468 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6469 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6470 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6471 || GET_CODE (x
) == LSHIFTRT
6472 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6473 || GET_CODE (x
) == ROTATERT
6474 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6477 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6480 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6481 && GET_CODE (x
) == PLUS
6482 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6488 /* X and Y are two things to compare using CODE. Emit the compare insn and
6489 return the rtx for register 0 in the proper mode. FP means this is a
6490 floating point compare: I don't think that it is needed on the arm. */
6492 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6494 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6495 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6497 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6498 gen_rtx_COMPARE (mode
, x
, y
)));
6503 /* Generate a sequence of insns that will generate the correct return
6504 address mask depending on the physical architecture that the program
6507 arm_gen_return_addr_mask (void)
6509 rtx reg
= gen_reg_rtx (Pmode
);
6511 emit_insn (gen_return_addr_mask (reg
));
6516 arm_reload_in_hi (rtx
*operands
)
6518 rtx ref
= operands
[1];
6520 HOST_WIDE_INT offset
= 0;
6522 if (GET_CODE (ref
) == SUBREG
)
6524 offset
= SUBREG_BYTE (ref
);
6525 ref
= SUBREG_REG (ref
);
6528 if (GET_CODE (ref
) == REG
)
6530 /* We have a pseudo which has been spilt onto the stack; there
6531 are two cases here: the first where there is a simple
6532 stack-slot replacement and a second where the stack-slot is
6533 out of range, or is used as a subreg. */
6534 if (reg_equiv_mem
[REGNO (ref
)])
6536 ref
= reg_equiv_mem
[REGNO (ref
)];
6537 base
= find_replacement (&XEXP (ref
, 0));
6540 /* The slot is out of range, or was dressed up in a SUBREG. */
6541 base
= reg_equiv_address
[REGNO (ref
)];
6544 base
= find_replacement (&XEXP (ref
, 0));
6546 /* Handle the case where the address is too complex to be offset by 1. */
6547 if (GET_CODE (base
) == MINUS
6548 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6550 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6552 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6555 else if (GET_CODE (base
) == PLUS
)
6557 /* The addend must be CONST_INT, or we would have dealt with it above. */
6558 HOST_WIDE_INT hi
, lo
;
6560 offset
+= INTVAL (XEXP (base
, 1));
6561 base
= XEXP (base
, 0);
6563 /* Rework the address into a legal sequence of insns. */
6564 /* Valid range for lo is -4095 -> 4095 */
6567 : -((-offset
) & 0xfff));
6569 /* Corner case, if lo is the max offset then we would be out of range
6570 once we have added the additional 1 below, so bump the msb into the
6571 pre-loading insn(s). */
6575 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6576 ^ (HOST_WIDE_INT
) 0x80000000)
6577 - (HOST_WIDE_INT
) 0x80000000);
6579 if (hi
+ lo
!= offset
)
6584 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6586 /* Get the base address; addsi3 knows how to handle constants
6587 that require more than one insn. */
6588 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6594 /* Operands[2] may overlap operands[0] (though it won't overlap
6595 operands[1]), that's why we asked for a DImode reg -- so we can
6596 use the bit that does not overlap. */
6597 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6598 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6600 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6602 emit_insn (gen_zero_extendqisi2 (scratch
,
6603 gen_rtx_MEM (QImode
,
6604 plus_constant (base
,
6606 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6607 gen_rtx_MEM (QImode
,
6608 plus_constant (base
,
6610 if (!BYTES_BIG_ENDIAN
)
6611 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6612 gen_rtx_IOR (SImode
,
6615 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6619 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6620 gen_rtx_IOR (SImode
,
6621 gen_rtx_ASHIFT (SImode
, scratch
,
6623 gen_rtx_SUBREG (SImode
, operands
[0],
6627 /* Handle storing a half-word to memory during reload by synthesizing as two
6628 byte stores. Take care not to clobber the input values until after we
6629 have moved them somewhere safe. This code assumes that if the DImode
6630 scratch in operands[2] overlaps either the input value or output address
6631 in some way, then that value must die in this insn (we absolutely need
6632 two scratch registers for some corner cases). */
6634 arm_reload_out_hi (rtx
*operands
)
6636 rtx ref
= operands
[0];
6637 rtx outval
= operands
[1];
6639 HOST_WIDE_INT offset
= 0;
6641 if (GET_CODE (ref
) == SUBREG
)
6643 offset
= SUBREG_BYTE (ref
);
6644 ref
= SUBREG_REG (ref
);
6647 if (GET_CODE (ref
) == REG
)
6649 /* We have a pseudo which has been spilt onto the stack; there
6650 are two cases here: the first where there is a simple
6651 stack-slot replacement and a second where the stack-slot is
6652 out of range, or is used as a subreg. */
6653 if (reg_equiv_mem
[REGNO (ref
)])
6655 ref
= reg_equiv_mem
[REGNO (ref
)];
6656 base
= find_replacement (&XEXP (ref
, 0));
6659 /* The slot is out of range, or was dressed up in a SUBREG. */
6660 base
= reg_equiv_address
[REGNO (ref
)];
6663 base
= find_replacement (&XEXP (ref
, 0));
6665 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6667 /* Handle the case where the address is too complex to be offset by 1. */
6668 if (GET_CODE (base
) == MINUS
6669 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6671 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6673 /* Be careful not to destroy OUTVAL. */
6674 if (reg_overlap_mentioned_p (base_plus
, outval
))
6676 /* Updating base_plus might destroy outval, see if we can
6677 swap the scratch and base_plus. */
6678 if (!reg_overlap_mentioned_p (scratch
, outval
))
6681 scratch
= base_plus
;
6686 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6688 /* Be conservative and copy OUTVAL into the scratch now,
6689 this should only be necessary if outval is a subreg
6690 of something larger than a word. */
6691 /* XXX Might this clobber base? I can't see how it can,
6692 since scratch is known to overlap with OUTVAL, and
6693 must be wider than a word. */
6694 emit_insn (gen_movhi (scratch_hi
, outval
));
6695 outval
= scratch_hi
;
6699 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6702 else if (GET_CODE (base
) == PLUS
)
6704 /* The addend must be CONST_INT, or we would have dealt with it above. */
6705 HOST_WIDE_INT hi
, lo
;
6707 offset
+= INTVAL (XEXP (base
, 1));
6708 base
= XEXP (base
, 0);
6710 /* Rework the address into a legal sequence of insns. */
6711 /* Valid range for lo is -4095 -> 4095 */
6714 : -((-offset
) & 0xfff));
6716 /* Corner case, if lo is the max offset then we would be out of range
6717 once we have added the additional 1 below, so bump the msb into the
6718 pre-loading insn(s). */
6722 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6723 ^ (HOST_WIDE_INT
) 0x80000000)
6724 - (HOST_WIDE_INT
) 0x80000000);
6726 if (hi
+ lo
!= offset
)
6731 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6733 /* Be careful not to destroy OUTVAL. */
6734 if (reg_overlap_mentioned_p (base_plus
, outval
))
6736 /* Updating base_plus might destroy outval, see if we
6737 can swap the scratch and base_plus. */
6738 if (!reg_overlap_mentioned_p (scratch
, outval
))
6741 scratch
= base_plus
;
6746 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6748 /* Be conservative and copy outval into scratch now,
6749 this should only be necessary if outval is a
6750 subreg of something larger than a word. */
6751 /* XXX Might this clobber base? I can't see how it
6752 can, since scratch is known to overlap with
6754 emit_insn (gen_movhi (scratch_hi
, outval
));
6755 outval
= scratch_hi
;
6759 /* Get the base address; addsi3 knows how to handle constants
6760 that require more than one insn. */
6761 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6767 if (BYTES_BIG_ENDIAN
)
6769 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6770 plus_constant (base
, offset
+ 1)),
6771 gen_lowpart (QImode
, outval
)));
6772 emit_insn (gen_lshrsi3 (scratch
,
6773 gen_rtx_SUBREG (SImode
, outval
, 0),
6775 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6776 gen_lowpart (QImode
, scratch
)));
6780 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6781 gen_lowpart (QImode
, outval
)));
6782 emit_insn (gen_lshrsi3 (scratch
,
6783 gen_rtx_SUBREG (SImode
, outval
, 0),
6785 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6786 plus_constant (base
, offset
+ 1)),
6787 gen_lowpart (QImode
, scratch
)));
6791 /* Print a symbolic form of X to the debug file, F. */
6793 arm_print_value (FILE *f
, rtx x
)
6795 switch (GET_CODE (x
))
6798 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6802 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6810 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6812 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6813 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6821 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6825 fprintf (f
, "`%s'", XSTR (x
, 0));
6829 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6833 arm_print_value (f
, XEXP (x
, 0));
6837 arm_print_value (f
, XEXP (x
, 0));
6839 arm_print_value (f
, XEXP (x
, 1));
6847 fprintf (f
, "????");
6852 /* Routines for manipulation of the constant pool. */
6854 /* Arm instructions cannot load a large constant directly into a
6855 register; they have to come from a pc relative load. The constant
6856 must therefore be placed in the addressable range of the pc
6857 relative load. Depending on the precise pc relative load
6858 instruction the range is somewhere between 256 bytes and 4k. This
6859 means that we often have to dump a constant inside a function, and
6860 generate code to branch around it.
6862 It is important to minimize this, since the branches will slow
6863 things down and make the code larger.
6865 Normally we can hide the table after an existing unconditional
6866 branch so that there is no interruption of the flow, but in the
6867 worst case the code looks like this:
6885 We fix this by performing a scan after scheduling, which notices
6886 which instructions need to have their operands fetched from the
6887 constant table and builds the table.
6889 The algorithm starts by building a table of all the constants that
6890 need fixing up and all the natural barriers in the function (places
6891 where a constant table can be dropped without breaking the flow).
6892 For each fixup we note how far the pc-relative replacement will be
6893 able to reach and the offset of the instruction into the function.
6895 Having built the table we then group the fixes together to form
6896 tables that are as large as possible (subject to addressing
6897 constraints) and emit each table of constants after the last
6898 barrier that is within range of all the instructions in the group.
6899 If a group does not contain a barrier, then we forcibly create one
6900 by inserting a jump instruction into the flow. Once the table has
6901 been inserted, the insns are then modified to reference the
6902 relevant entry in the pool.
6904 Possible enhancements to the algorithm (not implemented) are:
6906 1) For some processors and object formats, there may be benefit in
6907 aligning the pools to the start of cache lines; this alignment
6908 would need to be taken into account when calculating addressability
6911 /* These typedefs are located at the start of this file, so that
6912 they can be used in the prototypes there. This comment is to
6913 remind readers of that fact so that the following structures
6914 can be understood more easily.
6916 typedef struct minipool_node Mnode;
6917 typedef struct minipool_fixup Mfix; */
6919 struct minipool_node
6921 /* Doubly linked chain of entries. */
6924 /* The maximum offset into the code that this entry can be placed. While
6925 pushing fixes for forward references, all entries are sorted in order
6926 of increasing max_address. */
6927 HOST_WIDE_INT max_address
;
6928 /* Similarly for an entry inserted for a backwards ref. */
6929 HOST_WIDE_INT min_address
;
6930 /* The number of fixes referencing this entry. This can become zero
6931 if we "unpush" an entry. In this case we ignore the entry when we
6932 come to emit the code. */
6934 /* The offset from the start of the minipool. */
6935 HOST_WIDE_INT offset
;
6936 /* The value in table. */
6938 /* The mode of value. */
6939 enum machine_mode mode
;
6940 /* The size of the value. With iWMMXt enabled
6941 sizes > 4 also imply an alignment of 8-bytes. */
6945 struct minipool_fixup
6949 HOST_WIDE_INT address
;
6951 enum machine_mode mode
;
6955 HOST_WIDE_INT forwards
;
6956 HOST_WIDE_INT backwards
;
6959 /* Fixes less than a word need padding out to a word boundary. */
6960 #define MINIPOOL_FIX_SIZE(mode) \
6961 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6963 static Mnode
* minipool_vector_head
;
6964 static Mnode
* minipool_vector_tail
;
6965 static rtx minipool_vector_label
;
6967 /* The linked list of all minipool fixes required for this function. */
6968 Mfix
* minipool_fix_head
;
6969 Mfix
* minipool_fix_tail
;
6970 /* The fix entry for the current minipool, once it has been placed. */
6971 Mfix
* minipool_barrier
;
6973 /* Determines if INSN is the start of a jump table. Returns the end
6974 of the TABLE or NULL_RTX. */
6976 is_jump_table (rtx insn
)
6980 if (GET_CODE (insn
) == JUMP_INSN
6981 && JUMP_LABEL (insn
) != NULL
6982 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6983 == next_real_insn (insn
))
6985 && GET_CODE (table
) == JUMP_INSN
6986 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6987 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6993 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6994 #define JUMP_TABLES_IN_TEXT_SECTION 0
6997 static HOST_WIDE_INT
6998 get_jump_table_size (rtx insn
)
7000 /* ADDR_VECs only take room if read-only data does into the text
7002 if (JUMP_TABLES_IN_TEXT_SECTION
7003 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
7008 rtx body
= PATTERN (insn
);
7009 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7011 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7017 /* Move a minipool fix MP from its current location to before MAX_MP.
7018 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7019 constraints may need updating. */
7021 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7022 HOST_WIDE_INT max_address
)
7024 /* This should never be true and the code below assumes these are
7031 if (max_address
< mp
->max_address
)
7032 mp
->max_address
= max_address
;
7036 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7037 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7039 mp
->max_address
= max_address
;
7041 /* Unlink MP from its current position. Since max_mp is non-null,
7042 mp->prev must be non-null. */
7043 mp
->prev
->next
= mp
->next
;
7044 if (mp
->next
!= NULL
)
7045 mp
->next
->prev
= mp
->prev
;
7047 minipool_vector_tail
= mp
->prev
;
7049 /* Re-insert it before MAX_MP. */
7051 mp
->prev
= max_mp
->prev
;
7054 if (mp
->prev
!= NULL
)
7055 mp
->prev
->next
= mp
;
7057 minipool_vector_head
= mp
;
7060 /* Save the new entry. */
7063 /* Scan over the preceding entries and adjust their addresses as
7065 while (mp
->prev
!= NULL
7066 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7068 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7075 /* Add a constant to the minipool for a forward reference. Returns the
7076 node added or NULL if the constant will not fit in this pool. */
7078 add_minipool_forward_ref (Mfix
*fix
)
7080 /* If set, max_mp is the first pool_entry that has a lower
7081 constraint than the one we are trying to add. */
7082 Mnode
* max_mp
= NULL
;
7083 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7086 /* If this fix's address is greater than the address of the first
7087 entry, then we can't put the fix in this pool. We subtract the
7088 size of the current fix to ensure that if the table is fully
7089 packed we still have enough room to insert this value by suffling
7090 the other fixes forwards. */
7091 if (minipool_vector_head
&&
7092 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7095 /* Scan the pool to see if a constant with the same value has
7096 already been added. While we are doing this, also note the
7097 location where we must insert the constant if it doesn't already
7099 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7101 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7102 && fix
->mode
== mp
->mode
7103 && (GET_CODE (fix
->value
) != CODE_LABEL
7104 || (CODE_LABEL_NUMBER (fix
->value
)
7105 == CODE_LABEL_NUMBER (mp
->value
)))
7106 && rtx_equal_p (fix
->value
, mp
->value
))
7108 /* More than one fix references this entry. */
7110 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7113 /* Note the insertion point if necessary. */
7115 && mp
->max_address
> max_address
)
7118 /* If we are inserting an 8-bytes aligned quantity and
7119 we have not already found an insertion point, then
7120 make sure that all such 8-byte aligned quantities are
7121 placed at the start of the pool. */
7122 if (ARM_DOUBLEWORD_ALIGN
7124 && fix
->fix_size
== 8
7125 && mp
->fix_size
!= 8)
7128 max_address
= mp
->max_address
;
7132 /* The value is not currently in the minipool, so we need to create
7133 a new entry for it. If MAX_MP is NULL, the entry will be put on
7134 the end of the list since the placement is less constrained than
7135 any existing entry. Otherwise, we insert the new fix before
7136 MAX_MP and, if necessary, adjust the constraints on the other
7138 mp
= xmalloc (sizeof (* mp
));
7139 mp
->fix_size
= fix
->fix_size
;
7140 mp
->mode
= fix
->mode
;
7141 mp
->value
= fix
->value
;
7143 /* Not yet required for a backwards ref. */
7144 mp
->min_address
= -65536;
7148 mp
->max_address
= max_address
;
7150 mp
->prev
= minipool_vector_tail
;
7152 if (mp
->prev
== NULL
)
7154 minipool_vector_head
= mp
;
7155 minipool_vector_label
= gen_label_rtx ();
7158 mp
->prev
->next
= mp
;
7160 minipool_vector_tail
= mp
;
7164 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7165 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7167 mp
->max_address
= max_address
;
7170 mp
->prev
= max_mp
->prev
;
7172 if (mp
->prev
!= NULL
)
7173 mp
->prev
->next
= mp
;
7175 minipool_vector_head
= mp
;
7178 /* Save the new entry. */
7181 /* Scan over the preceding entries and adjust their addresses as
7183 while (mp
->prev
!= NULL
7184 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7186 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7194 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7195 HOST_WIDE_INT min_address
)
7197 HOST_WIDE_INT offset
;
7199 /* This should never be true, and the code below assumes these are
7206 if (min_address
> mp
->min_address
)
7207 mp
->min_address
= min_address
;
7211 /* We will adjust this below if it is too loose. */
7212 mp
->min_address
= min_address
;
7214 /* Unlink MP from its current position. Since min_mp is non-null,
7215 mp->next must be non-null. */
7216 mp
->next
->prev
= mp
->prev
;
7217 if (mp
->prev
!= NULL
)
7218 mp
->prev
->next
= mp
->next
;
7220 minipool_vector_head
= mp
->next
;
7222 /* Reinsert it after MIN_MP. */
7224 mp
->next
= min_mp
->next
;
7226 if (mp
->next
!= NULL
)
7227 mp
->next
->prev
= mp
;
7229 minipool_vector_tail
= mp
;
7235 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7237 mp
->offset
= offset
;
7238 if (mp
->refcount
> 0)
7239 offset
+= mp
->fix_size
;
7241 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7242 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7248 /* Add a constant to the minipool for a backward reference. Returns the
7249 node added or NULL if the constant will not fit in this pool.
7251 Note that the code for insertion for a backwards reference can be
7252 somewhat confusing because the calculated offsets for each fix do
7253 not take into account the size of the pool (which is still under
7256 add_minipool_backward_ref (Mfix
*fix
)
7258 /* If set, min_mp is the last pool_entry that has a lower constraint
7259 than the one we are trying to add. */
7260 Mnode
*min_mp
= NULL
;
7261 /* This can be negative, since it is only a constraint. */
7262 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7265 /* If we can't reach the current pool from this insn, or if we can't
7266 insert this entry at the end of the pool without pushing other
7267 fixes out of range, then we don't try. This ensures that we
7268 can't fail later on. */
7269 if (min_address
>= minipool_barrier
->address
7270 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7271 >= minipool_barrier
->address
))
7274 /* Scan the pool to see if a constant with the same value has
7275 already been added. While we are doing this, also note the
7276 location where we must insert the constant if it doesn't already
7278 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7280 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7281 && fix
->mode
== mp
->mode
7282 && (GET_CODE (fix
->value
) != CODE_LABEL
7283 || (CODE_LABEL_NUMBER (fix
->value
)
7284 == CODE_LABEL_NUMBER (mp
->value
)))
7285 && rtx_equal_p (fix
->value
, mp
->value
)
7286 /* Check that there is enough slack to move this entry to the
7287 end of the table (this is conservative). */
7289 > (minipool_barrier
->address
7290 + minipool_vector_tail
->offset
7291 + minipool_vector_tail
->fix_size
)))
7294 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7298 mp
->min_address
+= fix
->fix_size
;
7301 /* Note the insertion point if necessary. */
7302 if (mp
->min_address
< min_address
)
7304 /* For now, we do not allow the insertion of 8-byte alignment
7305 requiring nodes anywhere but at the start of the pool. */
7306 if (ARM_DOUBLEWORD_ALIGN
7307 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7312 else if (mp
->max_address
7313 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7315 /* Inserting before this entry would push the fix beyond
7316 its maximum address (which can happen if we have
7317 re-located a forwards fix); force the new fix to come
7320 min_address
= mp
->min_address
+ fix
->fix_size
;
7322 /* If we are inserting an 8-bytes aligned quantity and
7323 we have not already found an insertion point, then
7324 make sure that all such 8-byte aligned quantities are
7325 placed at the start of the pool. */
7326 else if (ARM_DOUBLEWORD_ALIGN
7328 && fix
->fix_size
== 8
7329 && mp
->fix_size
< 8)
7332 min_address
= mp
->min_address
+ fix
->fix_size
;
7337 /* We need to create a new entry. */
7338 mp
= xmalloc (sizeof (* mp
));
7339 mp
->fix_size
= fix
->fix_size
;
7340 mp
->mode
= fix
->mode
;
7341 mp
->value
= fix
->value
;
7343 mp
->max_address
= minipool_barrier
->address
+ 65536;
7345 mp
->min_address
= min_address
;
7350 mp
->next
= minipool_vector_head
;
7352 if (mp
->next
== NULL
)
7354 minipool_vector_tail
= mp
;
7355 minipool_vector_label
= gen_label_rtx ();
7358 mp
->next
->prev
= mp
;
7360 minipool_vector_head
= mp
;
7364 mp
->next
= min_mp
->next
;
7368 if (mp
->next
!= NULL
)
7369 mp
->next
->prev
= mp
;
7371 minipool_vector_tail
= mp
;
7374 /* Save the new entry. */
7382 /* Scan over the following entries and adjust their offsets. */
7383 while (mp
->next
!= NULL
)
7385 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7386 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7389 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7391 mp
->next
->offset
= mp
->offset
;
7400 assign_minipool_offsets (Mfix
*barrier
)
7402 HOST_WIDE_INT offset
= 0;
7405 minipool_barrier
= barrier
;
7407 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7409 mp
->offset
= offset
;
7411 if (mp
->refcount
> 0)
7412 offset
+= mp
->fix_size
;
7416 /* Output the literal table */
7418 dump_minipool (rtx scan
)
7424 if (ARM_DOUBLEWORD_ALIGN
)
7425 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7426 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7434 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7435 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7437 scan
= emit_label_after (gen_label_rtx (), scan
);
7438 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7439 scan
= emit_label_after (minipool_vector_label
, scan
);
7441 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7443 if (mp
->refcount
> 0)
7448 ";; Offset %u, min %ld, max %ld ",
7449 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7450 (unsigned long) mp
->max_address
);
7451 arm_print_value (dump_file
, mp
->value
);
7452 fputc ('\n', dump_file
);
7455 switch (mp
->fix_size
)
7457 #ifdef HAVE_consttable_1
7459 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7463 #ifdef HAVE_consttable_2
7465 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7469 #ifdef HAVE_consttable_4
7471 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7475 #ifdef HAVE_consttable_8
7477 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7491 minipool_vector_head
= minipool_vector_tail
= NULL
;
7492 scan
= emit_insn_after (gen_consttable_end (), scan
);
7493 scan
= emit_barrier_after (scan
);
7496 /* Return the cost of forcibly inserting a barrier after INSN. */
7498 arm_barrier_cost (rtx insn
)
7500 /* Basing the location of the pool on the loop depth is preferable,
7501 but at the moment, the basic block information seems to be
7502 corrupt by this stage of the compilation. */
7504 rtx next
= next_nonnote_insn (insn
);
7506 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7509 switch (GET_CODE (insn
))
7512 /* It will always be better to place the table before the label, rather
7521 return base_cost
- 10;
7524 return base_cost
+ 10;
7528 /* Find the best place in the insn stream in the range
7529 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7530 Create the barrier by inserting a jump and add a new fix entry for
7533 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7535 HOST_WIDE_INT count
= 0;
7537 rtx from
= fix
->insn
;
7538 rtx selected
= from
;
7540 HOST_WIDE_INT selected_address
;
7542 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7543 rtx label
= gen_label_rtx ();
7545 selected_cost
= arm_barrier_cost (from
);
7546 selected_address
= fix
->address
;
7548 while (from
&& count
< max_count
)
7553 /* This code shouldn't have been called if there was a natural barrier
7555 if (GET_CODE (from
) == BARRIER
)
7558 /* Count the length of this insn. */
7559 count
+= get_attr_length (from
);
7561 /* If there is a jump table, add its length. */
7562 tmp
= is_jump_table (from
);
7565 count
+= get_jump_table_size (tmp
);
7567 /* Jump tables aren't in a basic block, so base the cost on
7568 the dispatch insn. If we select this location, we will
7569 still put the pool after the table. */
7570 new_cost
= arm_barrier_cost (from
);
7572 if (count
< max_count
&& new_cost
<= selected_cost
)
7575 selected_cost
= new_cost
;
7576 selected_address
= fix
->address
+ count
;
7579 /* Continue after the dispatch table. */
7580 from
= NEXT_INSN (tmp
);
7584 new_cost
= arm_barrier_cost (from
);
7586 if (count
< max_count
&& new_cost
<= selected_cost
)
7589 selected_cost
= new_cost
;
7590 selected_address
= fix
->address
+ count
;
7593 from
= NEXT_INSN (from
);
7596 /* Create a new JUMP_INSN that branches around a barrier. */
7597 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7598 JUMP_LABEL (from
) = label
;
7599 barrier
= emit_barrier_after (from
);
7600 emit_label_after (label
, barrier
);
7602 /* Create a minipool barrier entry for the new barrier. */
7603 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7604 new_fix
->insn
= barrier
;
7605 new_fix
->address
= selected_address
;
7606 new_fix
->next
= fix
->next
;
7607 fix
->next
= new_fix
;
7612 /* Record that there is a natural barrier in the insn stream at
7615 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7617 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7620 fix
->address
= address
;
7623 if (minipool_fix_head
!= NULL
)
7624 minipool_fix_tail
->next
= fix
;
7626 minipool_fix_head
= fix
;
7628 minipool_fix_tail
= fix
;
7631 /* Record INSN, which will need fixing up to load a value from the
7632 minipool. ADDRESS is the offset of the insn since the start of the
7633 function; LOC is a pointer to the part of the insn which requires
7634 fixing; VALUE is the constant that must be loaded, which is of type
7637 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7638 enum machine_mode mode
, rtx value
)
7640 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7642 #ifdef AOF_ASSEMBLER
7643 /* PIC symbol references need to be converted into offsets into the
7645 /* XXX This shouldn't be done here. */
7646 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7647 value
= aof_pic_entry (value
);
7648 #endif /* AOF_ASSEMBLER */
7651 fix
->address
= address
;
7654 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7656 fix
->forwards
= get_attr_pool_range (insn
);
7657 fix
->backwards
= get_attr_neg_pool_range (insn
);
7658 fix
->minipool
= NULL
;
7660 /* If an insn doesn't have a range defined for it, then it isn't
7661 expecting to be reworked by this code. Better to abort now than
7662 to generate duff assembly code. */
7663 if (fix
->forwards
== 0 && fix
->backwards
== 0)
7666 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7667 So there might be an empty word before the start of the pool.
7668 Hence we reduce the forward range by 4 to allow for this
7670 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7676 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7677 GET_MODE_NAME (mode
),
7678 INSN_UID (insn
), (unsigned long) address
,
7679 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7680 arm_print_value (dump_file
, fix
->value
);
7681 fprintf (dump_file
, "\n");
7684 /* Add it to the chain of fixes. */
7687 if (minipool_fix_head
!= NULL
)
7688 minipool_fix_tail
->next
= fix
;
7690 minipool_fix_head
= fix
;
7692 minipool_fix_tail
= fix
;
7695 /* Scan INSN and note any of its operands that need fixing.
7696 If DO_PUSHES is false we do not actually push any of the fixups
7697 needed. The function returns TRUE is any fixups were needed/pushed.
7698 This is used by arm_memory_load_p() which needs to know about loads
7699 of constants that will be converted into minipool loads. */
7701 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
7703 bool result
= false;
7706 extract_insn (insn
);
7708 if (!constrain_operands (1))
7709 fatal_insn_not_found (insn
);
7711 if (recog_data
.n_alternatives
== 0)
7714 /* Fill in recog_op_alt with information about the constraints of this insn. */
7715 preprocess_constraints ();
7717 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7719 /* Things we need to fix can only occur in inputs. */
7720 if (recog_data
.operand_type
[opno
] != OP_IN
)
7723 /* If this alternative is a memory reference, then any mention
7724 of constants in this alternative is really to fool reload
7725 into allowing us to accept one there. We need to fix them up
7726 now so that we output the right code. */
7727 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
7729 rtx op
= recog_data
.operand
[opno
];
7731 if (CONSTANT_P (op
))
7734 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
7735 recog_data
.operand_mode
[opno
], op
);
7738 else if (GET_CODE (op
) == MEM
7739 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
7740 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
7744 rtx cop
= avoid_constant_pool_reference (op
);
7746 /* Casting the address of something to a mode narrower
7747 than a word can cause avoid_constant_pool_reference()
7748 to return the pool reference itself. That's no good to
7749 us here. Lets just hope that we can use the
7750 constant pool value directly. */
7752 cop
= get_pool_constant (XEXP (op
, 0));
7754 push_minipool_fix (insn
, address
,
7755 recog_data
.operand_loc
[opno
],
7756 recog_data
.operand_mode
[opno
], cop
);
7767 /* Gcc puts the pool in the wrong place for ARM, since we can only
7768 load addresses a limited distance around the pc. We do some
7769 special munging to move the constant pool values to the correct
7770 point in the code. */
7775 HOST_WIDE_INT address
= 0;
7778 minipool_fix_head
= minipool_fix_tail
= NULL
;
7780 /* The first insn must always be a note, or the code below won't
7781 scan it properly. */
7782 insn
= get_insns ();
7783 if (GET_CODE (insn
) != NOTE
)
7786 /* Scan all the insns and record the operands that will need fixing. */
7787 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7789 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7790 && (arm_cirrus_insn_p (insn
)
7791 || GET_CODE (insn
) == JUMP_INSN
7792 || arm_memory_load_p (insn
)))
7793 cirrus_reorg (insn
);
7795 if (GET_CODE (insn
) == BARRIER
)
7796 push_minipool_barrier (insn
, address
);
7797 else if (INSN_P (insn
))
7801 note_invalid_constants (insn
, address
, true);
7802 address
+= get_attr_length (insn
);
7804 /* If the insn is a vector jump, add the size of the table
7805 and skip the table. */
7806 if ((table
= is_jump_table (insn
)) != NULL
)
7808 address
+= get_jump_table_size (table
);
7814 fix
= minipool_fix_head
;
7816 /* Now scan the fixups and perform the required changes. */
7821 Mfix
* last_added_fix
;
7822 Mfix
* last_barrier
= NULL
;
7825 /* Skip any further barriers before the next fix. */
7826 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7829 /* No more fixes. */
7833 last_added_fix
= NULL
;
7835 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7837 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7839 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7842 last_barrier
= ftmp
;
7844 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7847 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7850 /* If we found a barrier, drop back to that; any fixes that we
7851 could have reached but come after the barrier will now go in
7852 the next mini-pool. */
7853 if (last_barrier
!= NULL
)
7855 /* Reduce the refcount for those fixes that won't go into this
7857 for (fdel
= last_barrier
->next
;
7858 fdel
&& fdel
!= ftmp
;
7861 fdel
->minipool
->refcount
--;
7862 fdel
->minipool
= NULL
;
7865 ftmp
= last_barrier
;
7869 /* ftmp is first fix that we can't fit into this pool and
7870 there no natural barriers that we could use. Insert a
7871 new barrier in the code somewhere between the previous
7872 fix and this one, and arrange to jump around it. */
7873 HOST_WIDE_INT max_address
;
7875 /* The last item on the list of fixes must be a barrier, so
7876 we can never run off the end of the list of fixes without
7877 last_barrier being set. */
7881 max_address
= minipool_vector_head
->max_address
;
7882 /* Check that there isn't another fix that is in range that
7883 we couldn't fit into this pool because the pool was
7884 already too large: we need to put the pool before such an
7886 if (ftmp
->address
< max_address
)
7887 max_address
= ftmp
->address
;
7889 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7892 assign_minipool_offsets (last_barrier
);
7896 if (GET_CODE (ftmp
->insn
) != BARRIER
7897 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7904 /* Scan over the fixes we have identified for this pool, fixing them
7905 up and adding the constants to the pool itself. */
7906 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7907 this_fix
= this_fix
->next
)
7908 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7911 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7912 minipool_vector_label
),
7913 this_fix
->minipool
->offset
);
7914 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7917 dump_minipool (last_barrier
->insn
);
7921 /* From now on we must synthesize any constants that we can't handle
7922 directly. This can happen if the RTL gets split during final
7923 instruction generation. */
7924 after_arm_reorg
= 1;
7926 /* Free the minipool memory. */
7927 obstack_free (&minipool_obstack
, minipool_startobj
);
7930 /* Routines to output assembly language. */
7932 /* If the rtx is the correct value then return the string of the number.
7933 In this way we can ensure that valid double constants are generated even
7934 when cross compiling. */
7936 fp_immediate_constant (rtx x
)
7941 if (!fp_consts_inited
)
7944 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7945 for (i
= 0; i
< 8; i
++)
7946 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7947 return strings_fp
[i
];
7952 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7954 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7958 if (!fp_consts_inited
)
7961 for (i
= 0; i
< 8; i
++)
7962 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
7963 return strings_fp
[i
];
7968 /* Output the operands of a LDM/STM instruction to STREAM.
7969 MASK is the ARM register set mask of which only bits 0-15 are important.
7970 REG is the base register, either the frame pointer or the stack pointer,
7971 INSTR is the possibly suffixed load or store instruction. */
7973 print_multi_reg (FILE *stream
, const char *instr
, int reg
, int mask
)
7976 int not_first
= FALSE
;
7978 fputc ('\t', stream
);
7979 asm_fprintf (stream
, instr
, reg
);
7980 fputs (", {", stream
);
7982 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7983 if (mask
& (1 << i
))
7986 fprintf (stream
, ", ");
7988 asm_fprintf (stream
, "%r", i
);
7992 fprintf (stream
, "}\n");
7996 /* Output a FLDMX instruction to STREAM.
7997 BASE if the register containing the address.
7998 REG and COUNT specify the register range.
7999 Extra registers may be added to avoid hardware bugs. */
8002 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8006 /* Workaround ARM10 VFPr1 bug. */
8007 if (count
== 2 && !arm_arch6
)
8014 fputc ('\t', stream
);
8015 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8017 for (i
= reg
; i
< reg
+ count
; i
++)
8020 fputs (", ", stream
);
8021 asm_fprintf (stream
, "d%d", i
);
8023 fputs ("}\n", stream
);
8028 /* Output the assembly for a store multiple. */
8031 vfp_output_fstmx (rtx
* operands
)
8038 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8039 p
= strlen (pattern
);
8041 if (GET_CODE (operands
[1]) != REG
)
8044 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8045 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8047 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8049 strcpy (&pattern
[p
], "}");
8051 output_asm_insn (pattern
, operands
);
8056 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8057 number of bytes pushed. */
8060 vfp_emit_fstmx (int base_reg
, int count
)
8067 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8068 register pairs are stored by a store multiple insn. We avoid this
8069 by pushing an extra pair. */
8070 if (count
== 2 && !arm_arch6
)
8072 if (base_reg
== LAST_VFP_REGNUM
- 3)
8077 /* ??? The frame layout is implementation defined. We describe
8078 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8079 We really need some way of representing the whole block so that the
8080 unwinder can figure it out at runtime. */
8081 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8082 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8084 reg
= gen_rtx_REG (DFmode
, base_reg
);
8088 = gen_rtx_SET (VOIDmode
,
8089 gen_rtx_MEM (BLKmode
,
8090 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8091 gen_rtx_UNSPEC (BLKmode
,
8095 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8096 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8097 GEN_INT (-(count
* 8 + 4))));
8098 RTX_FRAME_RELATED_P (tmp
) = 1;
8099 XVECEXP (dwarf
, 0, 0) = tmp
;
8101 tmp
= gen_rtx_SET (VOIDmode
,
8102 gen_rtx_MEM (DFmode
, stack_pointer_rtx
),
8104 RTX_FRAME_RELATED_P (tmp
) = 1;
8105 XVECEXP (dwarf
, 0, 1) = tmp
;
8107 for (i
= 1; i
< count
; i
++)
8109 reg
= gen_rtx_REG (DFmode
, base_reg
);
8111 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8113 tmp
= gen_rtx_SET (VOIDmode
,
8114 gen_rtx_MEM (DFmode
,
8115 gen_rtx_PLUS (SImode
,
8119 RTX_FRAME_RELATED_P (tmp
) = 1;
8120 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8123 par
= emit_insn (par
);
8124 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8126 RTX_FRAME_RELATED_P (par
) = 1;
8128 return count
* 8 + 4;
8132 /* Output a 'call' insn. */
8134 output_call (rtx
*operands
)
8137 abort (); /* Patterns should call blx <reg> directly. */
8139 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8140 if (REGNO (operands
[0]) == LR_REGNUM
)
8142 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8143 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8146 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8148 if (TARGET_INTERWORK
|| arm_arch4t
)
8149 output_asm_insn ("bx%?\t%0", operands
);
8151 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8156 /* Output a 'call' insn that is a reference in memory. */
8158 output_call_mem (rtx
*operands
)
8160 if (TARGET_INTERWORK
&& !arm_arch5
)
8162 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8163 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8164 output_asm_insn ("bx%?\t%|ip", operands
);
8166 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8168 /* LR is used in the memory address. We load the address in the
8169 first instruction. It's safe to use IP as the target of the
8170 load since the call will kill it anyway. */
8171 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8173 output_asm_insn ("blx%?%|ip", operands
);
8176 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8178 output_asm_insn ("bx%?\t%|ip", operands
);
8180 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8185 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8186 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8193 /* Output a move from arm registers to an fpa registers.
8194 OPERANDS[0] is an fpa register.
8195 OPERANDS[1] is the first registers of an arm register pair. */
8197 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8199 int arm_reg0
= REGNO (operands
[1]);
8202 if (arm_reg0
== IP_REGNUM
)
8205 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8206 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8207 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8209 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8210 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8215 /* Output a move from an fpa register to arm registers.
8216 OPERANDS[0] is the first registers of an arm register pair.
8217 OPERANDS[1] is an fpa register. */
8219 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8221 int arm_reg0
= REGNO (operands
[0]);
8224 if (arm_reg0
== IP_REGNUM
)
8227 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8228 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8229 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8231 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8232 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8236 /* Output a move from arm registers to arm registers of a long double
8237 OPERANDS[0] is the destination.
8238 OPERANDS[1] is the source. */
8240 output_mov_long_double_arm_from_arm (rtx
*operands
)
8242 /* We have to be careful here because the two might overlap. */
8243 int dest_start
= REGNO (operands
[0]);
8244 int src_start
= REGNO (operands
[1]);
8248 if (dest_start
< src_start
)
8250 for (i
= 0; i
< 3; i
++)
8252 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8253 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8254 output_asm_insn ("mov%?\t%0, %1", ops
);
8259 for (i
= 2; i
>= 0; i
--)
8261 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8262 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8263 output_asm_insn ("mov%?\t%0, %1", ops
);
8271 /* Output a move from arm registers to an fpa registers.
8272 OPERANDS[0] is an fpa register.
8273 OPERANDS[1] is the first registers of an arm register pair. */
8275 output_mov_double_fpa_from_arm (rtx
*operands
)
8277 int arm_reg0
= REGNO (operands
[1]);
8280 if (arm_reg0
== IP_REGNUM
)
8283 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8284 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8285 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8286 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8290 /* Output a move from an fpa register to arm registers.
8291 OPERANDS[0] is the first registers of an arm register pair.
8292 OPERANDS[1] is an fpa register. */
8294 output_mov_double_arm_from_fpa (rtx
*operands
)
8296 int arm_reg0
= REGNO (operands
[0]);
8299 if (arm_reg0
== IP_REGNUM
)
8302 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8303 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8304 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8305 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8309 /* Output a move between double words.
8310 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8311 or MEM<-REG and all MEMs must be offsettable addresses. */
8313 output_move_double (rtx
*operands
)
8315 enum rtx_code code0
= GET_CODE (operands
[0]);
8316 enum rtx_code code1
= GET_CODE (operands
[1]);
8321 int reg0
= REGNO (operands
[0]);
8323 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8327 int reg1
= REGNO (operands
[1]);
8328 if (reg1
== IP_REGNUM
)
8331 /* Ensure the second source is not overwritten. */
8332 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
8333 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
8335 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
8337 else if (code1
== CONST_VECTOR
)
8339 HOST_WIDE_INT hint
= 0;
8341 switch (GET_MODE (operands
[1]))
8344 otherops
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 1)));
8345 operands
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 0)));
8349 if (BYTES_BIG_ENDIAN
)
8351 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8353 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8357 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8359 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8362 otherops
[1] = GEN_INT (hint
);
8365 if (BYTES_BIG_ENDIAN
)
8367 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8369 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8373 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8375 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8378 operands
[1] = GEN_INT (hint
);
8382 if (BYTES_BIG_ENDIAN
)
8384 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8386 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8388 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8390 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8394 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8396 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8398 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8400 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8403 otherops
[1] = GEN_INT (hint
);
8406 if (BYTES_BIG_ENDIAN
)
8408 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8410 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8412 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8414 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8418 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8420 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8422 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8424 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8427 operands
[1] = GEN_INT (hint
);
8433 output_mov_immediate (operands
);
8434 output_mov_immediate (otherops
);
8436 else if (code1
== CONST_DOUBLE
)
8438 if (GET_MODE (operands
[1]) == DFmode
)
8443 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
8444 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
8445 otherops
[1] = GEN_INT (l
[1]);
8446 operands
[1] = GEN_INT (l
[0]);
8448 else if (GET_MODE (operands
[1]) != VOIDmode
)
8450 else if (WORDS_BIG_ENDIAN
)
8452 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8453 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8457 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8458 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8461 output_mov_immediate (operands
);
8462 output_mov_immediate (otherops
);
8464 else if (code1
== CONST_INT
)
8466 #if HOST_BITS_PER_WIDE_INT > 32
8467 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8468 what the upper word is. */
8469 if (WORDS_BIG_ENDIAN
)
8471 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8472 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8476 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8477 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8480 /* Sign extend the intval into the high-order word. */
8481 if (WORDS_BIG_ENDIAN
)
8483 otherops
[1] = operands
[1];
8484 operands
[1] = (INTVAL (operands
[1]) < 0
8485 ? constm1_rtx
: const0_rtx
);
8488 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
8490 output_mov_immediate (otherops
);
8491 output_mov_immediate (operands
);
8493 else if (code1
== MEM
)
8495 switch (GET_CODE (XEXP (operands
[1], 0)))
8498 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8503 abort (); /* Should never happen now. */
8504 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8508 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8512 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8517 abort (); /* Should never happen now. */
8518 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8523 otherops
[0] = operands
[0];
8524 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8525 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8527 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8529 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8531 /* Registers overlap so split out the increment. */
8532 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8533 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8536 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8540 /* We only allow constant increments, so this is safe. */
8541 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8547 output_asm_insn ("adr%?\t%0, %1", operands
);
8548 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8552 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8553 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8555 otherops
[0] = operands
[0];
8556 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8557 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8559 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8561 if (GET_CODE (otherops
[2]) == CONST_INT
)
8563 switch ((int) INTVAL (otherops
[2]))
8566 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8569 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8572 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8577 && (GET_CODE (otherops
[2]) == REG
8578 || (GET_CODE (otherops
[2]) == CONST_INT
8579 && INTVAL (otherops
[2]) > -256
8580 && INTVAL (otherops
[2]) < 256)))
8582 if (reg_overlap_mentioned_p (otherops
[0],
8585 /* Swap base and index registers over to
8586 avoid a conflict. */
8587 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8588 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8591 /* If both registers conflict, it will usually
8592 have been fixed by a splitter. */
8593 if (reg_overlap_mentioned_p (otherops
[0],
8596 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8597 output_asm_insn ("ldr%?d\t%0, [%1]",
8603 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8608 if (GET_CODE (otherops
[2]) == CONST_INT
)
8610 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8611 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8613 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8616 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8619 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8621 return "ldm%?ia\t%0, %M0";
8625 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8626 /* Take care of overlapping base/data reg. */
8627 if (reg_mentioned_p (operands
[0], operands
[1]))
8629 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8630 output_asm_insn ("ldr%?\t%0, %1", operands
);
8634 output_asm_insn ("ldr%?\t%0, %1", operands
);
8635 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8641 abort (); /* Constraints should prevent this. */
8643 else if (code0
== MEM
&& code1
== REG
)
8645 if (REGNO (operands
[1]) == IP_REGNUM
)
8648 switch (GET_CODE (XEXP (operands
[0], 0)))
8651 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8656 abort (); /* Should never happen now. */
8657 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8661 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8665 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8670 abort (); /* Should never happen now. */
8671 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8676 otherops
[0] = operands
[1];
8677 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8678 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8680 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8681 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8683 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8687 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8688 if (GET_CODE (otherops
[2]) == CONST_INT
)
8690 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8693 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8697 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8701 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8706 && (GET_CODE (otherops
[2]) == REG
8707 || (GET_CODE (otherops
[2]) == CONST_INT
8708 && INTVAL (otherops
[2]) > -256
8709 && INTVAL (otherops
[2]) < 256)))
8711 otherops
[0] = operands
[1];
8712 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8713 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8719 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8720 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8721 output_asm_insn ("str%?\t%1, %0", operands
);
8722 output_asm_insn ("str%?\t%1, %0", otherops
);
8726 /* Constraints should prevent this. */
8733 /* Output an arbitrary MOV reg, #n.
8734 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8736 output_mov_immediate (rtx
*operands
)
8738 HOST_WIDE_INT n
= INTVAL (operands
[1]);
8740 /* Try to use one MOV. */
8741 if (const_ok_for_arm (n
))
8742 output_asm_insn ("mov%?\t%0, %1", operands
);
8744 /* Try to use one MVN. */
8745 else if (const_ok_for_arm (~n
))
8747 operands
[1] = GEN_INT (~n
);
8748 output_asm_insn ("mvn%?\t%0, %1", operands
);
8755 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8756 for (i
= 0; i
< 32; i
++)
8760 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
8761 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
8763 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
8769 /* Output an ADD r, s, #n where n may be too big for one instruction.
8770 If adding zero to one register, output nothing. */
8772 output_add_immediate (rtx
*operands
)
8774 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8776 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8779 output_multi_immediate (operands
,
8780 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8783 output_multi_immediate (operands
,
8784 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8791 /* Output a multiple immediate operation.
8792 OPERANDS is the vector of operands referred to in the output patterns.
8793 INSTR1 is the output pattern to use for the first constant.
8794 INSTR2 is the output pattern to use for subsequent constants.
8795 IMMED_OP is the index of the constant slot in OPERANDS.
8796 N is the constant value. */
8798 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8799 int immed_op
, HOST_WIDE_INT n
)
8801 #if HOST_BITS_PER_WIDE_INT > 32
8807 /* Quick and easy output. */
8808 operands
[immed_op
] = const0_rtx
;
8809 output_asm_insn (instr1
, operands
);
8814 const char * instr
= instr1
;
8816 /* Note that n is never zero here (which would give no output). */
8817 for (i
= 0; i
< 32; i
+= 2)
8821 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8822 output_asm_insn (instr
, operands
);
8832 /* Return the appropriate ARM instruction for the operation code.
8833 The returned result should not be overwritten. OP is the rtx of the
8834 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8837 arithmetic_instr (rtx op
, int shift_first_arg
)
8839 switch (GET_CODE (op
))
8845 return shift_first_arg
? "rsb" : "sub";
8861 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8862 for the operation code. The returned result should not be overwritten.
8863 OP is the rtx code of the shift.
8864 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8867 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8870 enum rtx_code code
= GET_CODE (op
);
8872 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
8874 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
8875 *amountp
= INTVAL (XEXP (op
, 1));
8898 /* We never have to worry about the amount being other than a
8899 power of 2, since this case can never be reloaded from a reg. */
8901 *amountp
= int_log2 (*amountp
);
8912 /* This is not 100% correct, but follows from the desire to merge
8913 multiplication by a power of 2 with the recognizer for a
8914 shift. >=32 is not a valid shift for "asl", so we must try and
8915 output a shift that produces the correct arithmetical result.
8916 Using lsr #32 is identical except for the fact that the carry bit
8917 is not set correctly if we set the flags; but we never use the
8918 carry bit from such an operation, so we can ignore that. */
8919 if (code
== ROTATERT
)
8920 /* Rotate is just modulo 32. */
8922 else if (*amountp
!= (*amountp
& 31))
8929 /* Shifts of 0 are no-ops. */
8937 /* Obtain the shift from the POWER of two. */
8939 static HOST_WIDE_INT
8940 int_log2 (HOST_WIDE_INT power
)
8942 HOST_WIDE_INT shift
= 0;
8944 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
8954 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8955 /bin/as is horribly restrictive. */
8956 #define MAX_ASCII_LEN 51
8959 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
8964 fputs ("\t.ascii\t\"", stream
);
8966 for (i
= 0; i
< len
; i
++)
8970 if (len_so_far
>= MAX_ASCII_LEN
)
8972 fputs ("\"\n\t.ascii\t\"", stream
);
8979 fputs ("\\t", stream
);
8984 fputs ("\\f", stream
);
8989 fputs ("\\b", stream
);
8994 fputs ("\\r", stream
);
8998 case TARGET_NEWLINE
:
8999 fputs ("\\n", stream
);
9001 if ((c
>= ' ' && c
<= '~')
9003 /* This is a good place for a line break. */
9004 len_so_far
= MAX_ASCII_LEN
;
9011 putc ('\\', stream
);
9016 if (c
>= ' ' && c
<= '~')
9023 fprintf (stream
, "\\%03o", c
);
9030 fputs ("\"\n", stream
);
9033 /* Compute the register save mask for registers 0 through 12
9034 inclusive. This code is used by arm_compute_save_reg_mask. */
9035 static unsigned long
9036 arm_compute_save_reg0_reg12_mask (void)
9038 unsigned long func_type
= arm_current_func_type ();
9039 unsigned int save_reg_mask
= 0;
9042 if (IS_INTERRUPT (func_type
))
9044 unsigned int max_reg
;
9045 /* Interrupt functions must not corrupt any registers,
9046 even call clobbered ones. If this is a leaf function
9047 we can just examine the registers used by the RTL, but
9048 otherwise we have to assume that whatever function is
9049 called might clobber anything, and so we have to save
9050 all the call-clobbered registers as well. */
9051 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9052 /* FIQ handlers have registers r8 - r12 banked, so
9053 we only need to check r0 - r7, Normal ISRs only
9054 bank r14 and r15, so we must check up to r12.
9055 r13 is the stack pointer which is always preserved,
9056 so we do not need to consider it here. */
9061 for (reg
= 0; reg
<= max_reg
; reg
++)
9062 if (regs_ever_live
[reg
]
9063 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9064 save_reg_mask
|= (1 << reg
);
9068 /* In the normal case we only need to save those registers
9069 which are call saved and which are used by this function. */
9070 for (reg
= 0; reg
<= 10; reg
++)
9071 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9072 save_reg_mask
|= (1 << reg
);
9074 /* Handle the frame pointer as a special case. */
9075 if (! TARGET_APCS_FRAME
9076 && ! frame_pointer_needed
9077 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9078 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9079 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9081 /* If we aren't loading the PIC register,
9082 don't stack it even though it may be live. */
9084 && ! TARGET_SINGLE_PIC_BASE
9085 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
9086 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9089 /* Save registers so the exception handler can modify them. */
9090 if (current_function_calls_eh_return
)
9096 reg
= EH_RETURN_DATA_REGNO (i
);
9097 if (reg
== INVALID_REGNUM
)
9099 save_reg_mask
|= 1 << reg
;
9103 return save_reg_mask
;
9106 /* Compute a bit mask of which registers need to be
9107 saved on the stack for the current function. */
9109 static unsigned long
9110 arm_compute_save_reg_mask (void)
9112 unsigned int save_reg_mask
= 0;
9113 unsigned long func_type
= arm_current_func_type ();
9115 if (IS_NAKED (func_type
))
9116 /* This should never really happen. */
9119 /* If we are creating a stack frame, then we must save the frame pointer,
9120 IP (which will hold the old stack pointer), LR and the PC. */
9121 if (frame_pointer_needed
)
9123 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9128 /* Volatile functions do not return, so there
9129 is no need to save any other registers. */
9130 if (IS_VOLATILE (func_type
))
9131 return save_reg_mask
;
9133 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9135 /* Decide if we need to save the link register.
9136 Interrupt routines have their own banked link register,
9137 so they never need to save it.
9138 Otherwise if we do not use the link register we do not need to save
9139 it. If we are pushing other registers onto the stack however, we
9140 can save an instruction in the epilogue by pushing the link register
9141 now and then popping it back into the PC. This incurs extra memory
9142 accesses though, so we only do it when optimizing for size, and only
9143 if we know that we will not need a fancy return sequence. */
9144 if (regs_ever_live
[LR_REGNUM
]
9147 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9148 && !current_function_calls_eh_return
))
9149 save_reg_mask
|= 1 << LR_REGNUM
;
9151 if (cfun
->machine
->lr_save_eliminated
)
9152 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9154 if (TARGET_REALLY_IWMMXT
9155 && ((bit_count (save_reg_mask
)
9156 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9160 /* The total number of registers that are going to be pushed
9161 onto the stack is odd. We need to ensure that the stack
9162 is 64-bit aligned before we start to save iWMMXt registers,
9163 and also before we start to create locals. (A local variable
9164 might be a double or long long which we will load/store using
9165 an iWMMXt instruction). Therefore we need to push another
9166 ARM register, so that the stack will be 64-bit aligned. We
9167 try to avoid using the arg registers (r0 -r3) as they might be
9168 used to pass values in a tail call. */
9169 for (reg
= 4; reg
<= 12; reg
++)
9170 if ((save_reg_mask
& (1 << reg
)) == 0)
9174 save_reg_mask
|= (1 << reg
);
9177 cfun
->machine
->sibcall_blocked
= 1;
9178 save_reg_mask
|= (1 << 3);
9182 return save_reg_mask
;
9186 /* Compute a bit mask of which registers need to be
9187 saved on the stack for the current function. */
9188 static unsigned long
9189 thumb_compute_save_reg_mask (void)
9195 for (reg
= 0; reg
< 12; reg
++)
9197 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9201 if (flag_pic
&& !TARGET_SINGLE_PIC_BASE
)
9202 mask
|= PIC_OFFSET_TABLE_REGNUM
;
9203 if (TARGET_SINGLE_PIC_BASE
)
9204 mask
&= ~(1 << arm_pic_register
);
9206 /* lr will also be pushed if any lo regs are pushed. */
9207 if (mask
& 0xff || thumb_force_lr_save ())
9208 mask
|= (1 << LR_REGNUM
);
9210 /* Make sure we have a low work register if we need one. */
9211 if (((mask
& 0xff) == 0 && regs_ever_live
[LAST_ARG_REGNUM
])
9212 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9213 mask
|= 1 << LAST_LO_REGNUM
;
9219 /* Return the number of bytes required to save VFP registers. */
9221 arm_get_vfp_saved_size (void)
9228 /* Space for saved VFP registers. */
9229 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9232 for (regno
= FIRST_VFP_REGNUM
;
9233 regno
< LAST_VFP_REGNUM
;
9236 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9237 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9241 /* Workaround ARM10 VFPr1 bug. */
9242 if (count
== 2 && !arm_arch6
)
9244 saved
+= count
* 8 + 4;
9253 if (count
== 2 && !arm_arch6
)
9255 saved
+= count
* 8 + 4;
9262 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9263 everything bar the final return instruction. */
9265 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9267 char conditional
[10];
9270 unsigned long live_regs_mask
;
9271 unsigned long func_type
;
9272 arm_stack_offsets
*offsets
;
9274 func_type
= arm_current_func_type ();
9276 if (IS_NAKED (func_type
))
9279 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9281 /* If this function was declared non-returning, and we have
9282 found a tail call, then we have to trust that the called
9283 function won't return. */
9288 /* Otherwise, trap an attempted return by aborting. */
9290 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9292 assemble_external_libcall (ops
[1]);
9293 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9299 if (current_function_calls_alloca
&& !really_return
)
9302 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9304 return_used_this_function
= 1;
9306 live_regs_mask
= arm_compute_save_reg_mask ();
9310 const char * return_reg
;
9312 /* If we do not have any special requirements for function exit
9313 (eg interworking, or ISR) then we can load the return address
9314 directly into the PC. Otherwise we must load it into LR. */
9316 && ! TARGET_INTERWORK
)
9317 return_reg
= reg_names
[PC_REGNUM
];
9319 return_reg
= reg_names
[LR_REGNUM
];
9321 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9323 /* There are three possible reasons for the IP register
9324 being saved. 1) a stack frame was created, in which case
9325 IP contains the old stack pointer, or 2) an ISR routine
9326 corrupted it, or 3) it was saved to align the stack on
9327 iWMMXt. In case 1, restore IP into SP, otherwise just
9329 if (frame_pointer_needed
)
9331 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9332 live_regs_mask
|= (1 << SP_REGNUM
);
9336 if (! IS_INTERRUPT (func_type
)
9337 && ! TARGET_REALLY_IWMMXT
)
9342 /* On some ARM architectures it is faster to use LDR rather than
9343 LDM to load a single register. On other architectures, the
9344 cost is the same. In 26 bit mode, or for exception handlers,
9345 we have to use LDM to load the PC so that the CPSR is also
9347 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9349 if (live_regs_mask
== (unsigned int)(1 << reg
))
9352 if (reg
<= LAST_ARM_REGNUM
9353 && (reg
!= LR_REGNUM
9355 || ! IS_INTERRUPT (func_type
)))
9357 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9358 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9365 /* Generate the load multiple instruction to restore the
9366 registers. Note we can get here, even if
9367 frame_pointer_needed is true, but only if sp already
9368 points to the base of the saved core registers. */
9369 if (live_regs_mask
& (1 << SP_REGNUM
))
9371 unsigned HOST_WIDE_INT stack_adjust
;
9373 offsets
= arm_get_frame_offsets ();
9374 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9375 if (stack_adjust
!= 0 && stack_adjust
!= 4)
9378 if (stack_adjust
&& arm_arch5
)
9379 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9382 /* If we can't use ldmib (SA110 bug), then try to pop r3
9385 live_regs_mask
|= 1 << 3;
9386 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9390 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9392 p
= instr
+ strlen (instr
);
9394 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9395 if (live_regs_mask
& (1 << reg
))
9397 int l
= strlen (reg_names
[reg
]);
9403 memcpy (p
, ", ", 2);
9407 memcpy (p
, "%|", 2);
9408 memcpy (p
+ 2, reg_names
[reg
], l
);
9412 if (live_regs_mask
& (1 << LR_REGNUM
))
9414 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9415 /* If returning from an interrupt, restore the CPSR. */
9416 if (IS_INTERRUPT (func_type
))
9423 output_asm_insn (instr
, & operand
);
9425 /* See if we need to generate an extra instruction to
9426 perform the actual function return. */
9428 && func_type
!= ARM_FT_INTERWORKED
9429 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9431 /* The return has already been handled
9432 by loading the LR into the PC. */
9439 switch ((int) ARM_FUNC_TYPE (func_type
))
9443 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9446 case ARM_FT_INTERWORKED
:
9447 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9450 case ARM_FT_EXCEPTION
:
9451 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9455 /* Use bx if it's available. */
9456 if (arm_arch5
|| arm_arch4t
)
9457 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9459 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9463 output_asm_insn (instr
, & operand
);
9469 /* Write the function name into the code section, directly preceding
9470 the function prologue.
9472 Code will be output similar to this:
9474 .ascii "arm_poke_function_name", 0
9477 .word 0xff000000 + (t1 - t0)
9478 arm_poke_function_name
9480 stmfd sp!, {fp, ip, lr, pc}
9483 When performing a stack backtrace, code can inspect the value
9484 of 'pc' stored at 'fp' + 0. If the trace function then looks
9485 at location pc - 12 and the top 8 bits are set, then we know
9486 that there is a function name embedded immediately preceding this
9487 location and has length ((pc[-3]) & 0xff000000).
9489 We assume that pc is declared as a pointer to an unsigned long.
9491 It is of no benefit to output the function name if we are assembling
9492 a leaf function. These function types will not contain a stack
9493 backtrace structure, therefore it is not possible to determine the
9496 arm_poke_function_name (FILE *stream
, const char *name
)
9498 unsigned long alignlength
;
9499 unsigned long length
;
9502 length
= strlen (name
) + 1;
9503 alignlength
= ROUND_UP_WORD (length
);
9505 ASM_OUTPUT_ASCII (stream
, name
, length
);
9506 ASM_OUTPUT_ALIGN (stream
, 2);
9507 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9508 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9511 /* Place some comments into the assembler stream
9512 describing the current function. */
9514 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9516 unsigned long func_type
;
9520 thumb_output_function_prologue (f
, frame_size
);
9525 if (arm_ccfsm_state
|| arm_target_insn
)
9528 func_type
= arm_current_func_type ();
9530 switch ((int) ARM_FUNC_TYPE (func_type
))
9535 case ARM_FT_INTERWORKED
:
9536 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9539 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9542 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9544 case ARM_FT_EXCEPTION
:
9545 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9549 if (IS_NAKED (func_type
))
9550 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9552 if (IS_VOLATILE (func_type
))
9553 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9555 if (IS_NESTED (func_type
))
9556 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9558 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9559 current_function_args_size
,
9560 current_function_pretend_args_size
, frame_size
);
9562 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9563 frame_pointer_needed
,
9564 cfun
->machine
->uses_anonymous_args
);
9566 if (cfun
->machine
->lr_save_eliminated
)
9567 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9569 if (current_function_calls_eh_return
)
9570 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9572 #ifdef AOF_ASSEMBLER
9574 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9577 return_used_this_function
= 0;
9581 arm_output_epilogue (rtx sibling
)
9584 unsigned long saved_regs_mask
;
9585 unsigned long func_type
;
9586 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9587 frame that is $fp + 4 for a non-variadic function. */
9588 int floats_offset
= 0;
9590 FILE * f
= asm_out_file
;
9591 unsigned int lrm_count
= 0;
9592 int really_return
= (sibling
== NULL
);
9594 arm_stack_offsets
*offsets
;
9596 /* If we have already generated the return instruction
9597 then it is futile to generate anything else. */
9598 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9601 func_type
= arm_current_func_type ();
9603 if (IS_NAKED (func_type
))
9604 /* Naked functions don't have epilogues. */
9607 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9611 /* A volatile function should never return. Call abort. */
9612 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9613 assemble_external_libcall (op
);
9614 output_asm_insn ("bl\t%a0", &op
);
9619 if (current_function_calls_eh_return
9621 /* If we are throwing an exception, then we really must
9622 be doing a return, so we can't tail-call. */
9625 offsets
= arm_get_frame_offsets ();
9626 saved_regs_mask
= arm_compute_save_reg_mask ();
9629 lrm_count
= bit_count (saved_regs_mask
);
9631 floats_offset
= offsets
->saved_args
;
9632 /* Compute how far away the floats will be. */
9633 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9634 if (saved_regs_mask
& (1 << reg
))
9637 if (frame_pointer_needed
)
9639 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9640 int vfp_offset
= offsets
->frame
;
9642 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9644 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9645 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9647 floats_offset
+= 12;
9648 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9649 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9654 start_reg
= LAST_FPA_REGNUM
;
9656 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9658 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9660 floats_offset
+= 12;
9662 /* We can't unstack more than four registers at once. */
9663 if (start_reg
- reg
== 3)
9665 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9666 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9667 start_reg
= reg
- 1;
9672 if (reg
!= start_reg
)
9673 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9674 reg
+ 1, start_reg
- reg
,
9675 FP_REGNUM
, floats_offset
- vfp_offset
);
9676 start_reg
= reg
- 1;
9680 /* Just in case the last register checked also needs unstacking. */
9681 if (reg
!= start_reg
)
9682 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9683 reg
+ 1, start_reg
- reg
,
9684 FP_REGNUM
, floats_offset
- vfp_offset
);
9687 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9691 /* The fldmx insn does not have base+offset addressing modes,
9692 so we use IP to hold the address. */
9693 saved_size
= arm_get_vfp_saved_size ();
9697 floats_offset
+= saved_size
;
9698 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9699 FP_REGNUM
, floats_offset
- vfp_offset
);
9701 start_reg
= FIRST_VFP_REGNUM
;
9702 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9704 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9705 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9707 if (start_reg
!= reg
)
9708 arm_output_fldmx (f
, IP_REGNUM
,
9709 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9710 (reg
- start_reg
) / 2);
9711 start_reg
= reg
+ 2;
9714 if (start_reg
!= reg
)
9715 arm_output_fldmx (f
, IP_REGNUM
,
9716 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9717 (reg
- start_reg
) / 2);
9722 /* The frame pointer is guaranteed to be non-double-word aligned.
9723 This is because it is set to (old_stack_pointer - 4) and the
9724 old_stack_pointer was double word aligned. Thus the offset to
9725 the iWMMXt registers to be loaded must also be non-double-word
9726 sized, so that the resultant address *is* double-word aligned.
9727 We can ignore floats_offset since that was already included in
9728 the live_regs_mask. */
9729 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9731 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9732 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9734 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9735 reg
, FP_REGNUM
, lrm_count
* 4);
9740 /* saved_regs_mask should contain the IP, which at the time of stack
9741 frame generation actually contains the old stack pointer. So a
9742 quick way to unwind the stack is just pop the IP register directly
9743 into the stack pointer. */
9744 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
9746 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9747 saved_regs_mask
|= (1 << SP_REGNUM
);
9749 /* There are two registers left in saved_regs_mask - LR and PC. We
9750 only need to restore the LR register (the return address), but to
9751 save time we can load it directly into the PC, unless we need a
9752 special function exit sequence, or we are not really returning. */
9754 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9755 && !current_function_calls_eh_return
)
9756 /* Delete the LR from the register mask, so that the LR on
9757 the stack is loaded into the PC in the register mask. */
9758 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9760 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9762 /* We must use SP as the base register, because SP is one of the
9763 registers being restored. If an interrupt or page fault
9764 happens in the ldm instruction, the SP might or might not
9765 have been restored. That would be bad, as then SP will no
9766 longer indicate the safe area of stack, and we can get stack
9767 corruption. Using SP as the base register means that it will
9768 be reset correctly to the original value, should an interrupt
9769 occur. If the stack pointer already points at the right
9770 place, then omit the subtraction. */
9771 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9772 || current_function_calls_alloca
)
9773 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9774 4 * bit_count (saved_regs_mask
));
9775 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9777 if (IS_INTERRUPT (func_type
))
9778 /* Interrupt handlers will have pushed the
9779 IP onto the stack, so restore it now. */
9780 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9784 /* Restore stack pointer if necessary. */
9785 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9787 operands
[0] = operands
[1] = stack_pointer_rtx
;
9788 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9789 output_add_immediate (operands
);
9792 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9794 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9795 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9796 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9801 start_reg
= FIRST_FPA_REGNUM
;
9803 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9805 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9807 if (reg
- start_reg
== 3)
9809 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9810 start_reg
, SP_REGNUM
);
9811 start_reg
= reg
+ 1;
9816 if (reg
!= start_reg
)
9817 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9818 start_reg
, reg
- start_reg
,
9821 start_reg
= reg
+ 1;
9825 /* Just in case the last register checked also needs unstacking. */
9826 if (reg
!= start_reg
)
9827 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9828 start_reg
, reg
- start_reg
, SP_REGNUM
);
9831 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9833 start_reg
= FIRST_VFP_REGNUM
;
9834 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9836 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9837 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9839 if (start_reg
!= reg
)
9840 arm_output_fldmx (f
, SP_REGNUM
,
9841 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9842 (reg
- start_reg
) / 2);
9843 start_reg
= reg
+ 2;
9846 if (start_reg
!= reg
)
9847 arm_output_fldmx (f
, SP_REGNUM
,
9848 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9849 (reg
- start_reg
) / 2);
9852 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9853 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9854 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9856 /* If we can, restore the LR into the PC. */
9857 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9859 && current_function_pretend_args_size
== 0
9860 && saved_regs_mask
& (1 << LR_REGNUM
)
9861 && !current_function_calls_eh_return
)
9863 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9864 saved_regs_mask
|= (1 << PC_REGNUM
);
9867 /* Load the registers off the stack. If we only have one register
9868 to load use the LDR instruction - it is faster. */
9869 if (saved_regs_mask
== (1 << LR_REGNUM
))
9871 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9873 else if (saved_regs_mask
)
9875 if (saved_regs_mask
& (1 << SP_REGNUM
))
9876 /* Note - write back to the stack register is not enabled
9877 (ie "ldmfd sp!..."). We know that the stack pointer is
9878 in the list of registers and if we add writeback the
9879 instruction becomes UNPREDICTABLE. */
9880 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9882 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9885 if (current_function_pretend_args_size
)
9887 /* Unwind the pre-pushed regs. */
9888 operands
[0] = operands
[1] = stack_pointer_rtx
;
9889 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9890 output_add_immediate (operands
);
9894 /* We may have already restored PC directly from the stack. */
9895 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
9898 /* Stack adjustment for exception handler. */
9899 if (current_function_calls_eh_return
)
9900 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
9901 ARM_EH_STACKADJ_REGNUM
);
9903 /* Generate the return instruction. */
9904 switch ((int) ARM_FUNC_TYPE (func_type
))
9908 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
9911 case ARM_FT_EXCEPTION
:
9912 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9915 case ARM_FT_INTERWORKED
:
9916 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9920 if (arm_arch5
|| arm_arch4t
)
9921 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9923 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9931 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9932 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
9934 arm_stack_offsets
*offsets
;
9938 /* ??? Probably not safe to set this here, since it assumes that a
9939 function will be emitted as assembly immediately after we generate
9940 RTL for it. This does not happen for inline functions. */
9941 return_used_this_function
= 0;
9945 /* We need to take into account any stack-frame rounding. */
9946 offsets
= arm_get_frame_offsets ();
9948 if (use_return_insn (FALSE
, NULL
)
9949 && return_used_this_function
9950 && offsets
->saved_regs
!= offsets
->outgoing_args
9951 && !frame_pointer_needed
)
9954 /* Reset the ARM-specific per-function variables. */
9955 after_arm_reorg
= 0;
9959 /* Generate and emit an insn that we will recognize as a push_multi.
9960 Unfortunately, since this insn does not reflect very well the actual
9961 semantics of the operation, we need to annotate the insn for the benefit
9962 of DWARF2 frame unwind information. */
9964 emit_multi_reg_push (int mask
)
9971 int dwarf_par_index
;
9974 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9975 if (mask
& (1 << i
))
9978 if (num_regs
== 0 || num_regs
> 16)
9981 /* We don't record the PC in the dwarf frame information. */
9982 num_dwarf_regs
= num_regs
;
9983 if (mask
& (1 << PC_REGNUM
))
9986 /* For the body of the insn we are going to generate an UNSPEC in
9987 parallel with several USEs. This allows the insn to be recognized
9988 by the push_multi pattern in the arm.md file. The insn looks
9989 something like this:
9992 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9993 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9994 (use (reg:SI 11 fp))
9995 (use (reg:SI 12 ip))
9996 (use (reg:SI 14 lr))
9997 (use (reg:SI 15 pc))
10000 For the frame note however, we try to be more explicit and actually
10001 show each register being stored into the stack frame, plus a (single)
10002 decrement of the stack pointer. We do it this way in order to be
10003 friendly to the stack unwinding code, which only wants to see a single
10004 stack decrement per instruction. The RTL we generate for the note looks
10005 something like this:
10008 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10009 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10010 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10011 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10012 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10015 This sequence is used both by the code to support stack unwinding for
10016 exceptions handlers and the code to generate dwarf2 frame debugging. */
10018 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10019 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10020 dwarf_par_index
= 1;
10022 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10024 if (mask
& (1 << i
))
10026 reg
= gen_rtx_REG (SImode
, i
);
10028 XVECEXP (par
, 0, 0)
10029 = gen_rtx_SET (VOIDmode
,
10030 gen_rtx_MEM (BLKmode
,
10031 gen_rtx_PRE_DEC (BLKmode
,
10032 stack_pointer_rtx
)),
10033 gen_rtx_UNSPEC (BLKmode
,
10034 gen_rtvec (1, reg
),
10035 UNSPEC_PUSH_MULT
));
10037 if (i
!= PC_REGNUM
)
10039 tmp
= gen_rtx_SET (VOIDmode
,
10040 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
10042 RTX_FRAME_RELATED_P (tmp
) = 1;
10043 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10051 for (j
= 1, i
++; j
< num_regs
; i
++)
10053 if (mask
& (1 << i
))
10055 reg
= gen_rtx_REG (SImode
, i
);
10057 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10059 if (i
!= PC_REGNUM
)
10061 tmp
= gen_rtx_SET (VOIDmode
,
10062 gen_rtx_MEM (SImode
,
10063 plus_constant (stack_pointer_rtx
,
10066 RTX_FRAME_RELATED_P (tmp
) = 1;
10067 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10074 par
= emit_insn (par
);
10076 tmp
= gen_rtx_SET (SImode
,
10078 gen_rtx_PLUS (SImode
,
10080 GEN_INT (-4 * num_regs
)));
10081 RTX_FRAME_RELATED_P (tmp
) = 1;
10082 XVECEXP (dwarf
, 0, 0) = tmp
;
10084 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10090 emit_sfm (int base_reg
, int count
)
10097 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10098 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10100 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10102 XVECEXP (par
, 0, 0)
10103 = gen_rtx_SET (VOIDmode
,
10104 gen_rtx_MEM (BLKmode
,
10105 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
10106 gen_rtx_UNSPEC (BLKmode
,
10107 gen_rtvec (1, reg
),
10108 UNSPEC_PUSH_MULT
));
10109 tmp
= gen_rtx_SET (VOIDmode
,
10110 gen_rtx_MEM (XFmode
, stack_pointer_rtx
), reg
);
10111 RTX_FRAME_RELATED_P (tmp
) = 1;
10112 XVECEXP (dwarf
, 0, 1) = tmp
;
10114 for (i
= 1; i
< count
; i
++)
10116 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10117 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10119 tmp
= gen_rtx_SET (VOIDmode
,
10120 gen_rtx_MEM (XFmode
,
10121 plus_constant (stack_pointer_rtx
,
10124 RTX_FRAME_RELATED_P (tmp
) = 1;
10125 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10128 tmp
= gen_rtx_SET (VOIDmode
,
10130 gen_rtx_PLUS (SImode
,
10132 GEN_INT (-12 * count
)));
10133 RTX_FRAME_RELATED_P (tmp
) = 1;
10134 XVECEXP (dwarf
, 0, 0) = tmp
;
10136 par
= emit_insn (par
);
10137 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10143 /* Return true if the current function needs to save/restore LR. */
10146 thumb_force_lr_save (void)
10148 return !cfun
->machine
->lr_save_eliminated
10149 && (!leaf_function_p ()
10150 || thumb_far_jump_used_p ()
10151 || regs_ever_live
[LR_REGNUM
]);
10155 /* Compute the distance from register FROM to register TO.
10156 These can be the arg pointer (26), the soft frame pointer (25),
10157 the stack pointer (13) or the hard frame pointer (11).
10158 In thumb mode r7 is used as the soft frame pointer, if needed.
10159 Typical stack layout looks like this:
10161 old stack pointer -> | |
10164 | | saved arguments for
10165 | | vararg functions
10168 hard FP & arg pointer -> | | \
10176 soft frame pointer -> | | /
10186 current stack pointer -> | | /
10189 For a given function some or all of these stack components
10190 may not be needed, giving rise to the possibility of
10191 eliminating some of the registers.
10193 The values returned by this function must reflect the behavior
10194 of arm_expand_prologue() and arm_compute_save_reg_mask().
10196 The sign of the number returned reflects the direction of stack
10197 growth, so the values are positive for all eliminations except
10198 from the soft frame pointer to the hard frame pointer.
10200 SFP may point just inside the local variables block to ensure correct
10204 /* Calculate stack offsets. These are used to calculate register elimination
10205 offsets and in prologue/epilogue code. */
10207 static arm_stack_offsets
*
10208 arm_get_frame_offsets (void)
10210 struct arm_stack_offsets
*offsets
;
10211 unsigned long func_type
;
10214 HOST_WIDE_INT frame_size
;
10216 offsets
= &cfun
->machine
->stack_offsets
;
10218 /* We need to know if we are a leaf function. Unfortunately, it
10219 is possible to be called after start_sequence has been called,
10220 which causes get_insns to return the insns for the sequence,
10221 not the function, which will cause leaf_function_p to return
10222 the incorrect result.
10224 to know about leaf functions once reload has completed, and the
10225 frame size cannot be changed after that time, so we can safely
10226 use the cached value. */
10228 if (reload_completed
)
10231 /* Initially this is the size of the local variables. It will translated
10232 into an offset once we have determined the size of preceding data. */
10233 frame_size
= ROUND_UP_WORD (get_frame_size ());
10235 leaf
= leaf_function_p ();
10237 /* Space for variadic functions. */
10238 offsets
->saved_args
= current_function_pretend_args_size
;
10240 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10244 unsigned int regno
;
10246 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10248 /* We know that SP will be doubleword aligned on entry, and we must
10249 preserve that condition at any subroutine call. We also require the
10250 soft frame pointer to be doubleword aligned. */
10252 if (TARGET_REALLY_IWMMXT
)
10254 /* Check for the call-saved iWMMXt registers. */
10255 for (regno
= FIRST_IWMMXT_REGNUM
;
10256 regno
<= LAST_IWMMXT_REGNUM
;
10258 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10262 func_type
= arm_current_func_type ();
10263 if (! IS_VOLATILE (func_type
))
10265 /* Space for saved FPA registers. */
10266 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10267 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10270 /* Space for saved VFP registers. */
10271 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10272 saved
+= arm_get_vfp_saved_size ();
10275 else /* TARGET_THUMB */
10277 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10278 if (TARGET_BACKTRACE
)
10282 /* Saved registers include the stack frame. */
10283 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10284 offsets
->soft_frame
= offsets
->saved_regs
;
10285 /* A leaf function does not need any stack alignment if it has nothing
10287 if (leaf
&& frame_size
== 0)
10289 offsets
->outgoing_args
= offsets
->soft_frame
;
10293 /* Ensure SFP has the correct alignment. */
10294 if (ARM_DOUBLEWORD_ALIGN
10295 && (offsets
->soft_frame
& 7))
10296 offsets
->soft_frame
+= 4;
10298 offsets
->outgoing_args
= offsets
->soft_frame
+ frame_size
10299 + current_function_outgoing_args_size
;
10301 if (ARM_DOUBLEWORD_ALIGN
)
10303 /* Ensure SP remains doubleword aligned. */
10304 if (offsets
->outgoing_args
& 7)
10305 offsets
->outgoing_args
+= 4;
10306 if (offsets
->outgoing_args
& 7)
10314 /* Calculate the relative offsets for the different stack pointers. Positive
10315 offsets are in the direction of stack growth. */
10318 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10320 arm_stack_offsets
*offsets
;
10322 offsets
= arm_get_frame_offsets ();
10324 /* OK, now we have enough information to compute the distances.
10325 There must be an entry in these switch tables for each pair
10326 of registers in ELIMINABLE_REGS, even if some of the entries
10327 seem to be redundant or useless. */
10330 case ARG_POINTER_REGNUM
:
10333 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10336 case FRAME_POINTER_REGNUM
:
10337 /* This is the reverse of the soft frame pointer
10338 to hard frame pointer elimination below. */
10339 return offsets
->soft_frame
- offsets
->saved_args
;
10341 case ARM_HARD_FRAME_POINTER_REGNUM
:
10342 /* If there is no stack frame then the hard
10343 frame pointer and the arg pointer coincide. */
10344 if (offsets
->frame
== offsets
->saved_regs
)
10346 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10347 return (frame_pointer_needed
10348 && cfun
->static_chain_decl
!= NULL
10349 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10351 case STACK_POINTER_REGNUM
:
10352 /* If nothing has been pushed on the stack at all
10353 then this will return -4. This *is* correct! */
10354 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10361 case FRAME_POINTER_REGNUM
:
10364 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10367 case ARM_HARD_FRAME_POINTER_REGNUM
:
10368 /* The hard frame pointer points to the top entry in the
10369 stack frame. The soft frame pointer to the bottom entry
10370 in the stack frame. If there is no stack frame at all,
10371 then they are identical. */
10373 return offsets
->frame
- offsets
->soft_frame
;
10375 case STACK_POINTER_REGNUM
:
10376 return offsets
->outgoing_args
- offsets
->soft_frame
;
10384 /* You cannot eliminate from the stack pointer.
10385 In theory you could eliminate from the hard frame
10386 pointer to the stack pointer, but this will never
10387 happen, since if a stack frame is not needed the
10388 hard frame pointer will never be used. */
10394 /* Generate the prologue instructions for entry into an ARM function. */
10396 arm_expand_prologue (void)
10402 unsigned long live_regs_mask
;
10403 unsigned long func_type
;
10405 int saved_pretend_args
= 0;
10406 int saved_regs
= 0;
10407 unsigned int args_to_push
;
10408 arm_stack_offsets
*offsets
;
10410 func_type
= arm_current_func_type ();
10412 /* Naked functions don't have prologues. */
10413 if (IS_NAKED (func_type
))
10416 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10417 args_to_push
= current_function_pretend_args_size
;
10419 /* Compute which register we will have to save onto the stack. */
10420 live_regs_mask
= arm_compute_save_reg_mask ();
10422 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10424 if (frame_pointer_needed
)
10426 if (IS_INTERRUPT (func_type
))
10428 /* Interrupt functions must not corrupt any registers.
10429 Creating a frame pointer however, corrupts the IP
10430 register, so we must push it first. */
10431 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10433 /* Do not set RTX_FRAME_RELATED_P on this insn.
10434 The dwarf stack unwinding code only wants to see one
10435 stack decrement per function, and this is not it. If
10436 this instruction is labeled as being part of the frame
10437 creation sequence then dwarf2out_frame_debug_expr will
10438 abort when it encounters the assignment of IP to FP
10439 later on, since the use of SP here establishes SP as
10440 the CFA register and not IP.
10442 Anyway this instruction is not really part of the stack
10443 frame creation although it is part of the prologue. */
10445 else if (IS_NESTED (func_type
))
10447 /* The Static chain register is the same as the IP register
10448 used as a scratch register during stack frame creation.
10449 To get around this need to find somewhere to store IP
10450 whilst the frame is being created. We try the following
10453 1. The last argument register.
10454 2. A slot on the stack above the frame. (This only
10455 works if the function is not a varargs function).
10456 3. Register r3, after pushing the argument registers
10459 Note - we only need to tell the dwarf2 backend about the SP
10460 adjustment in the second variant; the static chain register
10461 doesn't need to be unwound, as it doesn't contain a value
10462 inherited from the caller. */
10464 if (regs_ever_live
[3] == 0)
10466 insn
= gen_rtx_REG (SImode
, 3);
10467 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10468 insn
= emit_insn (insn
);
10470 else if (args_to_push
== 0)
10473 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10474 insn
= gen_rtx_MEM (SImode
, insn
);
10475 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10476 insn
= emit_insn (insn
);
10480 /* Just tell the dwarf backend that we adjusted SP. */
10481 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10482 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10483 GEN_INT (-fp_offset
)));
10484 RTX_FRAME_RELATED_P (insn
) = 1;
10485 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10486 dwarf
, REG_NOTES (insn
));
10490 /* Store the args on the stack. */
10491 if (cfun
->machine
->uses_anonymous_args
)
10492 insn
= emit_multi_reg_push
10493 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10496 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10497 GEN_INT (- args_to_push
)));
10499 RTX_FRAME_RELATED_P (insn
) = 1;
10501 saved_pretend_args
= 1;
10502 fp_offset
= args_to_push
;
10505 /* Now reuse r3 to preserve IP. */
10506 insn
= gen_rtx_REG (SImode
, 3);
10507 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10508 (void) emit_insn (insn
);
10514 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10515 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10518 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10520 insn
= emit_insn (insn
);
10521 RTX_FRAME_RELATED_P (insn
) = 1;
10526 /* Push the argument registers, or reserve space for them. */
10527 if (cfun
->machine
->uses_anonymous_args
)
10528 insn
= emit_multi_reg_push
10529 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10532 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10533 GEN_INT (- args_to_push
)));
10534 RTX_FRAME_RELATED_P (insn
) = 1;
10537 /* If this is an interrupt service routine, and the link register
10538 is going to be pushed, and we are not creating a stack frame,
10539 (which would involve an extra push of IP and a pop in the epilogue)
10540 subtracting four from LR now will mean that the function return
10541 can be done with a single instruction. */
10542 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10543 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10544 && ! frame_pointer_needed
)
10545 emit_insn (gen_rtx_SET (SImode
,
10546 gen_rtx_REG (SImode
, LR_REGNUM
),
10547 gen_rtx_PLUS (SImode
,
10548 gen_rtx_REG (SImode
, LR_REGNUM
),
10551 if (live_regs_mask
)
10553 insn
= emit_multi_reg_push (live_regs_mask
);
10554 saved_regs
+= bit_count (live_regs_mask
) * 4;
10555 RTX_FRAME_RELATED_P (insn
) = 1;
10559 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10560 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10562 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10563 insn
= gen_rtx_MEM (V2SImode
, insn
);
10564 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10565 gen_rtx_REG (V2SImode
, reg
)));
10566 RTX_FRAME_RELATED_P (insn
) = 1;
10570 if (! IS_VOLATILE (func_type
))
10574 /* Save any floating point call-saved registers used by this
10576 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10578 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10579 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10581 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10582 insn
= gen_rtx_MEM (XFmode
, insn
);
10583 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10584 gen_rtx_REG (XFmode
, reg
)));
10585 RTX_FRAME_RELATED_P (insn
) = 1;
10591 start_reg
= LAST_FPA_REGNUM
;
10593 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10595 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10597 if (start_reg
- reg
== 3)
10599 insn
= emit_sfm (reg
, 4);
10600 RTX_FRAME_RELATED_P (insn
) = 1;
10602 start_reg
= reg
- 1;
10607 if (start_reg
!= reg
)
10609 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10610 RTX_FRAME_RELATED_P (insn
) = 1;
10611 saved_regs
+= (start_reg
- reg
) * 12;
10613 start_reg
= reg
- 1;
10617 if (start_reg
!= reg
)
10619 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10620 saved_regs
+= (start_reg
- reg
) * 12;
10621 RTX_FRAME_RELATED_P (insn
) = 1;
10624 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10626 start_reg
= FIRST_VFP_REGNUM
;
10628 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10630 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10631 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10633 if (start_reg
!= reg
)
10634 saved_regs
+= vfp_emit_fstmx (start_reg
,
10635 (reg
- start_reg
) / 2);
10636 start_reg
= reg
+ 2;
10639 if (start_reg
!= reg
)
10640 saved_regs
+= vfp_emit_fstmx (start_reg
,
10641 (reg
- start_reg
) / 2);
10645 if (frame_pointer_needed
)
10647 /* Create the new frame pointer. */
10648 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10649 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10650 RTX_FRAME_RELATED_P (insn
) = 1;
10652 if (IS_NESTED (func_type
))
10654 /* Recover the static chain register. */
10655 if (regs_ever_live
[3] == 0
10656 || saved_pretend_args
)
10657 insn
= gen_rtx_REG (SImode
, 3);
10658 else /* if (current_function_pretend_args_size == 0) */
10660 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10662 insn
= gen_rtx_MEM (SImode
, insn
);
10665 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10666 /* Add a USE to stop propagate_one_insn() from barfing. */
10667 emit_insn (gen_prologue_use (ip_rtx
));
10671 offsets
= arm_get_frame_offsets ();
10672 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10674 /* This add can produce multiple insns for a large constant, so we
10675 need to get tricky. */
10676 rtx last
= get_last_insn ();
10678 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10679 - offsets
->outgoing_args
);
10681 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10685 last
= last
? NEXT_INSN (last
) : get_insns ();
10686 RTX_FRAME_RELATED_P (last
) = 1;
10688 while (last
!= insn
);
10690 /* If the frame pointer is needed, emit a special barrier that
10691 will prevent the scheduler from moving stores to the frame
10692 before the stack adjustment. */
10693 if (frame_pointer_needed
)
10694 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10695 hard_frame_pointer_rtx
));
10700 arm_load_pic_register ();
10702 /* If we are profiling, make sure no instructions are scheduled before
10703 the call to mcount. Similarly if the user has requested no
10704 scheduling in the prolog. */
10705 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10706 emit_insn (gen_blockage ());
10708 /* If the link register is being kept alive, with the return address in it,
10709 then make sure that it does not get reused by the ce2 pass. */
10710 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10712 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10713 cfun
->machine
->lr_save_eliminated
= 1;
10717 /* If CODE is 'd', then the X is a condition operand and the instruction
10718 should only be executed if the condition is true.
10719 if CODE is 'D', then the X is a condition operand and the instruction
10720 should only be executed if the condition is false: however, if the mode
10721 of the comparison is CCFPEmode, then always execute the instruction -- we
10722 do this because in these circumstances !GE does not necessarily imply LT;
10723 in these cases the instruction pattern will take care to make sure that
10724 an instruction containing %d will follow, thereby undoing the effects of
10725 doing this instruction unconditionally.
10726 If CODE is 'N' then X is a floating point operand that must be negated
10728 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10729 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10731 arm_print_operand (FILE *stream
, rtx x
, int code
)
10736 fputs (ASM_COMMENT_START
, stream
);
10740 fputs (user_label_prefix
, stream
);
10744 fputs (REGISTER_PREFIX
, stream
);
10748 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10750 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
10753 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10755 else if (current_insn_predicate
)
10757 enum arm_cond_code code
;
10762 code
= get_arm_condition_code (current_insn_predicate
);
10763 fputs (arm_condition_codes
[code
], stream
);
10770 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10771 r
= REAL_VALUE_NEGATE (r
);
10772 fprintf (stream
, "%s", fp_const_from_val (&r
));
10777 if (GET_CODE (x
) == CONST_INT
)
10780 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10781 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10785 putc ('~', stream
);
10786 output_addr_const (stream
, x
);
10791 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10794 /* Truncate Cirrus shift counts. */
10796 if (GET_CODE (x
) == CONST_INT
)
10798 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10801 arm_print_operand (stream
, x
, 0);
10805 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10811 const char * shift
= shift_op (x
, &val
);
10815 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10817 arm_print_operand (stream
, XEXP (x
, 1), 0);
10819 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10824 /* An explanation of the 'Q', 'R' and 'H' register operands:
10826 In a pair of registers containing a DI or DF value the 'Q'
10827 operand returns the register number of the register containing
10828 the least significant part of the value. The 'R' operand returns
10829 the register number of the register containing the most
10830 significant part of the value.
10832 The 'H' operand returns the higher of the two register numbers.
10833 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10834 same as the 'Q' operand, since the most significant part of the
10835 value is held in the lower number register. The reverse is true
10836 on systems where WORDS_BIG_ENDIAN is false.
10838 The purpose of these operands is to distinguish between cases
10839 where the endian-ness of the values is important (for example
10840 when they are added together), and cases where the endian-ness
10841 is irrelevant, but the order of register operations is important.
10842 For example when loading a value from memory into a register
10843 pair, the endian-ness does not matter. Provided that the value
10844 from the lower memory address is put into the lower numbered
10845 register, and the value from the higher address is put into the
10846 higher numbered register, the load will work regardless of whether
10847 the value being loaded is big-wordian or little-wordian. The
10848 order of the two register loads can matter however, if the address
10849 of the memory location is actually held in one of the registers
10850 being overwritten by the load. */
10852 if (REGNO (x
) > LAST_ARM_REGNUM
)
10854 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
10858 if (REGNO (x
) > LAST_ARM_REGNUM
)
10860 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
10864 if (REGNO (x
) > LAST_ARM_REGNUM
)
10866 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
10870 asm_fprintf (stream
, "%r",
10871 GET_CODE (XEXP (x
, 0)) == REG
10872 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
10876 asm_fprintf (stream
, "{%r-%r}",
10878 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
10882 /* CONST_TRUE_RTX means always -- that's the default. */
10883 if (x
== const_true_rtx
)
10886 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
10891 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10892 want to do that. */
10893 if (x
== const_true_rtx
)
10896 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
10897 (get_arm_condition_code (x
))],
10901 /* Cirrus registers can be accessed in a variety of ways:
10902 single floating point (f)
10903 double floating point (d)
10905 64bit integer (dx). */
10906 case 'W': /* Cirrus register in F mode. */
10907 case 'X': /* Cirrus register in D mode. */
10908 case 'Y': /* Cirrus register in FX mode. */
10909 case 'Z': /* Cirrus register in DX mode. */
10910 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10913 fprintf (stream
, "mv%s%s",
10915 : code
== 'X' ? "d"
10916 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
10920 /* Print cirrus register in the mode specified by the register's mode. */
10923 int mode
= GET_MODE (x
);
10925 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10928 fprintf (stream
, "mv%s%s",
10929 mode
== DFmode
? "d"
10930 : mode
== SImode
? "fx"
10931 : mode
== DImode
? "dx"
10932 : "f", reg_names
[REGNO (x
)] + 2);
10938 if (GET_CODE (x
) != REG
10939 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
10940 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
10941 /* Bad value for wCG register number. */
10944 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
10947 /* Print an iWMMXt control register name. */
10949 if (GET_CODE (x
) != CONST_INT
10951 || INTVAL (x
) >= 16)
10952 /* Bad value for wC register number. */
10956 static const char * wc_reg_names
[16] =
10958 "wCID", "wCon", "wCSSF", "wCASF",
10959 "wC4", "wC5", "wC6", "wC7",
10960 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10961 "wC12", "wC13", "wC14", "wC15"
10964 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
10968 /* Print a VFP double precision register name. */
10971 int mode
= GET_MODE (x
);
10974 if (mode
!= DImode
&& mode
!= DFmode
)
10977 if (GET_CODE (x
) != REG
10978 || !IS_VFP_REGNUM (REGNO (x
)))
10981 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
10985 fprintf (stream
, "d%d", num
>> 1);
10993 if (GET_CODE (x
) == REG
)
10994 asm_fprintf (stream
, "%r", REGNO (x
));
10995 else if (GET_CODE (x
) == MEM
)
10997 output_memory_reference_mode
= GET_MODE (x
);
10998 output_address (XEXP (x
, 0));
11000 else if (GET_CODE (x
) == CONST_DOUBLE
)
11001 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11002 else if (GET_CODE (x
) == NEG
)
11003 abort (); /* This should never happen now. */
11006 fputc ('#', stream
);
11007 output_addr_const (stream
, x
);
11012 #ifndef AOF_ASSEMBLER
11013 /* Target hook for assembling integer objects. The ARM version needs to
11014 handle word-sized values specially. */
11016 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11018 if (size
== UNITS_PER_WORD
&& aligned_p
)
11020 fputs ("\t.word\t", asm_out_file
);
11021 output_addr_const (asm_out_file
, x
);
11023 /* Mark symbols as position independent. We only do this in the
11024 .text segment, not in the .data segment. */
11025 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11026 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11028 if (GET_CODE (x
) == SYMBOL_REF
11029 && (CONSTANT_POOL_ADDRESS_P (x
)
11030 || SYMBOL_REF_LOCAL_P (x
)))
11031 fputs ("(GOTOFF)", asm_out_file
);
11032 else if (GET_CODE (x
) == LABEL_REF
)
11033 fputs ("(GOTOFF)", asm_out_file
);
11035 fputs ("(GOT)", asm_out_file
);
11037 fputc ('\n', asm_out_file
);
11041 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x
)))
11045 if (GET_CODE (x
) != CONST_VECTOR
)
11048 units
= CONST_VECTOR_NUNITS (x
);
11050 switch (GET_MODE (x
))
11052 case V2SImode
: size
= 4; break;
11053 case V4HImode
: size
= 2; break;
11054 case V8QImode
: size
= 1; break;
11059 for (i
= 0; i
< units
; i
++)
11063 elt
= CONST_VECTOR_ELT (x
, i
);
11065 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11071 return default_assemble_integer (x
, size
, aligned_p
);
11075 /* A finite state machine takes care of noticing whether or not instructions
11076 can be conditionally executed, and thus decrease execution time and code
11077 size by deleting branch instructions. The fsm is controlled by
11078 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11080 /* The state of the fsm controlling condition codes are:
11081 0: normal, do nothing special
11082 1: make ASM_OUTPUT_OPCODE not output this instruction
11083 2: make ASM_OUTPUT_OPCODE not output this instruction
11084 3: make instructions conditional
11085 4: make instructions conditional
11087 State transitions (state->state by whom under condition):
11088 0 -> 1 final_prescan_insn if the `target' is a label
11089 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11090 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11091 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11092 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11093 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11094 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11095 (the target insn is arm_target_insn).
11097 If the jump clobbers the conditions then we use states 2 and 4.
11099 A similar thing can be done with conditional return insns.
11101 XXX In case the `target' is an unconditional branch, this conditionalising
11102 of the instructions always reduces code size, but not always execution
11103 time. But then, I want to reduce the code size to somewhere near what
11104 /bin/cc produces. */
11106 /* Returns the index of the ARM condition code string in
11107 `arm_condition_codes'. COMPARISON should be an rtx like
11108 `(eq (...) (...))'. */
11109 static enum arm_cond_code
11110 get_arm_condition_code (rtx comparison
)
11112 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11114 enum rtx_code comp_code
= GET_CODE (comparison
);
11116 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11117 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11118 XEXP (comparison
, 1));
11122 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11123 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11124 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11125 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11126 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11127 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11128 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11129 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11130 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11131 case CC_DLTUmode
: code
= ARM_CC
;
11134 if (comp_code
!= EQ
&& comp_code
!= NE
)
11137 if (comp_code
== EQ
)
11138 return ARM_INVERSE_CONDITION_CODE (code
);
11144 case NE
: return ARM_NE
;
11145 case EQ
: return ARM_EQ
;
11146 case GE
: return ARM_PL
;
11147 case LT
: return ARM_MI
;
11154 case NE
: return ARM_NE
;
11155 case EQ
: return ARM_EQ
;
11162 case NE
: return ARM_MI
;
11163 case EQ
: return ARM_PL
;
11169 /* These encodings assume that AC=1 in the FPA system control
11170 byte. This allows us to handle all cases except UNEQ and
11174 case GE
: return ARM_GE
;
11175 case GT
: return ARM_GT
;
11176 case LE
: return ARM_LS
;
11177 case LT
: return ARM_MI
;
11178 case NE
: return ARM_NE
;
11179 case EQ
: return ARM_EQ
;
11180 case ORDERED
: return ARM_VC
;
11181 case UNORDERED
: return ARM_VS
;
11182 case UNLT
: return ARM_LT
;
11183 case UNLE
: return ARM_LE
;
11184 case UNGT
: return ARM_HI
;
11185 case UNGE
: return ARM_PL
;
11186 /* UNEQ and LTGT do not have a representation. */
11187 case UNEQ
: /* Fall through. */
11188 case LTGT
: /* Fall through. */
11195 case NE
: return ARM_NE
;
11196 case EQ
: return ARM_EQ
;
11197 case GE
: return ARM_LE
;
11198 case GT
: return ARM_LT
;
11199 case LE
: return ARM_GE
;
11200 case LT
: return ARM_GT
;
11201 case GEU
: return ARM_LS
;
11202 case GTU
: return ARM_CC
;
11203 case LEU
: return ARM_CS
;
11204 case LTU
: return ARM_HI
;
11211 case LTU
: return ARM_CS
;
11212 case GEU
: return ARM_CC
;
11219 case NE
: return ARM_NE
;
11220 case EQ
: return ARM_EQ
;
11221 case GE
: return ARM_GE
;
11222 case GT
: return ARM_GT
;
11223 case LE
: return ARM_LE
;
11224 case LT
: return ARM_LT
;
11225 case GEU
: return ARM_CS
;
11226 case GTU
: return ARM_HI
;
11227 case LEU
: return ARM_LS
;
11228 case LTU
: return ARM_CC
;
11239 arm_final_prescan_insn (rtx insn
)
11241 /* BODY will hold the body of INSN. */
11242 rtx body
= PATTERN (insn
);
11244 /* This will be 1 if trying to repeat the trick, and things need to be
11245 reversed if it appears to fail. */
11248 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11249 taken are clobbered, even if the rtl suggests otherwise. It also
11250 means that we have to grub around within the jump expression to find
11251 out what the conditions are when the jump isn't taken. */
11252 int jump_clobbers
= 0;
11254 /* If we start with a return insn, we only succeed if we find another one. */
11255 int seeking_return
= 0;
11257 /* START_INSN will hold the insn from where we start looking. This is the
11258 first insn after the following code_label if REVERSE is true. */
11259 rtx start_insn
= insn
;
11261 /* If in state 4, check if the target branch is reached, in order to
11262 change back to state 0. */
11263 if (arm_ccfsm_state
== 4)
11265 if (insn
== arm_target_insn
)
11267 arm_target_insn
= NULL
;
11268 arm_ccfsm_state
= 0;
11273 /* If in state 3, it is possible to repeat the trick, if this insn is an
11274 unconditional branch to a label, and immediately following this branch
11275 is the previous target label which is only used once, and the label this
11276 branch jumps to is not too far off. */
11277 if (arm_ccfsm_state
== 3)
11279 if (simplejump_p (insn
))
11281 start_insn
= next_nonnote_insn (start_insn
);
11282 if (GET_CODE (start_insn
) == BARRIER
)
11284 /* XXX Isn't this always a barrier? */
11285 start_insn
= next_nonnote_insn (start_insn
);
11287 if (GET_CODE (start_insn
) == CODE_LABEL
11288 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11289 && LABEL_NUSES (start_insn
) == 1)
11294 else if (GET_CODE (body
) == RETURN
)
11296 start_insn
= next_nonnote_insn (start_insn
);
11297 if (GET_CODE (start_insn
) == BARRIER
)
11298 start_insn
= next_nonnote_insn (start_insn
);
11299 if (GET_CODE (start_insn
) == CODE_LABEL
11300 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11301 && LABEL_NUSES (start_insn
) == 1)
11304 seeking_return
= 1;
11313 if (arm_ccfsm_state
!= 0 && !reverse
)
11315 if (GET_CODE (insn
) != JUMP_INSN
)
11318 /* This jump might be paralleled with a clobber of the condition codes
11319 the jump should always come first */
11320 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11321 body
= XVECEXP (body
, 0, 0);
11324 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11325 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11328 int fail
= FALSE
, succeed
= FALSE
;
11329 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11330 int then_not_else
= TRUE
;
11331 rtx this_insn
= start_insn
, label
= 0;
11333 /* If the jump cannot be done with one instruction, we cannot
11334 conditionally execute the instruction in the inverse case. */
11335 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11341 /* Register the insn jumped to. */
11344 if (!seeking_return
)
11345 label
= XEXP (SET_SRC (body
), 0);
11347 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11348 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11349 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11351 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11352 then_not_else
= FALSE
;
11354 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11355 seeking_return
= 1;
11356 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11358 seeking_return
= 1;
11359 then_not_else
= FALSE
;
11364 /* See how many insns this branch skips, and what kind of insns. If all
11365 insns are okay, and the label or unconditional branch to the same
11366 label is not too far away, succeed. */
11367 for (insns_skipped
= 0;
11368 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11372 this_insn
= next_nonnote_insn (this_insn
);
11376 switch (GET_CODE (this_insn
))
11379 /* Succeed if it is the target label, otherwise fail since
11380 control falls in from somewhere else. */
11381 if (this_insn
== label
)
11385 arm_ccfsm_state
= 2;
11386 this_insn
= next_nonnote_insn (this_insn
);
11389 arm_ccfsm_state
= 1;
11397 /* Succeed if the following insn is the target label.
11399 If return insns are used then the last insn in a function
11400 will be a barrier. */
11401 this_insn
= next_nonnote_insn (this_insn
);
11402 if (this_insn
&& this_insn
== label
)
11406 arm_ccfsm_state
= 2;
11407 this_insn
= next_nonnote_insn (this_insn
);
11410 arm_ccfsm_state
= 1;
11418 /* The AAPCS says that conditional calls should not be
11419 used since they make interworking inefficient (the
11420 linker can't transform BL<cond> into BLX). That's
11421 only a problem if the machine has BLX. */
11428 /* Succeed if the following insn is the target label, or
11429 if the following two insns are a barrier and the
11431 this_insn
= next_nonnote_insn (this_insn
);
11432 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11433 this_insn
= next_nonnote_insn (this_insn
);
11435 if (this_insn
&& this_insn
== label
11436 && insns_skipped
< max_insns_skipped
)
11440 arm_ccfsm_state
= 2;
11441 this_insn
= next_nonnote_insn (this_insn
);
11444 arm_ccfsm_state
= 1;
11452 /* If this is an unconditional branch to the same label, succeed.
11453 If it is to another label, do nothing. If it is conditional,
11455 /* XXX Probably, the tests for SET and the PC are
11458 scanbody
= PATTERN (this_insn
);
11459 if (GET_CODE (scanbody
) == SET
11460 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11462 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11463 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11465 arm_ccfsm_state
= 2;
11468 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11471 /* Fail if a conditional return is undesirable (eg on a
11472 StrongARM), but still allow this if optimizing for size. */
11473 else if (GET_CODE (scanbody
) == RETURN
11474 && !use_return_insn (TRUE
, NULL
)
11477 else if (GET_CODE (scanbody
) == RETURN
11480 arm_ccfsm_state
= 2;
11483 else if (GET_CODE (scanbody
) == PARALLEL
)
11485 switch (get_attr_conds (this_insn
))
11495 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
11500 /* Instructions using or affecting the condition codes make it
11502 scanbody
= PATTERN (this_insn
);
11503 if (!(GET_CODE (scanbody
) == SET
11504 || GET_CODE (scanbody
) == PARALLEL
)
11505 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11508 /* A conditional cirrus instruction must be followed by
11509 a non Cirrus instruction. However, since we
11510 conditionalize instructions in this function and by
11511 the time we get here we can't add instructions
11512 (nops), because shorten_branches() has already been
11513 called, we will disable conditionalizing Cirrus
11514 instructions to be safe. */
11515 if (GET_CODE (scanbody
) != USE
11516 && GET_CODE (scanbody
) != CLOBBER
11517 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11527 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11528 arm_target_label
= CODE_LABEL_NUMBER (label
);
11529 else if (seeking_return
|| arm_ccfsm_state
== 2)
11531 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11533 this_insn
= next_nonnote_insn (this_insn
);
11534 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
11535 || GET_CODE (this_insn
) == CODE_LABEL
))
11540 /* Oh, dear! we ran off the end.. give up. */
11541 recog (PATTERN (insn
), insn
, NULL
);
11542 arm_ccfsm_state
= 0;
11543 arm_target_insn
= NULL
;
11546 arm_target_insn
= this_insn
;
11555 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11557 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11558 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11559 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11560 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11564 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11567 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11571 if (reverse
|| then_not_else
)
11572 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11575 /* Restore recog_data (getting the attributes of other insns can
11576 destroy this array, but final.c assumes that it remains intact
11577 across this call; since the insn has been recognized already we
11578 call recog direct). */
11579 recog (PATTERN (insn
), insn
, NULL
);
11583 /* Returns true if REGNO is a valid register
11584 for holding a quantity of tyoe MODE. */
11586 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11588 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11589 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11592 /* For the Thumb we only allow values bigger than SImode in
11593 registers 0 - 6, so that there is always a second low
11594 register available to hold the upper part of the value.
11595 We probably we ought to ensure that the register is the
11596 start of an even numbered register pair. */
11597 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11599 if (IS_CIRRUS_REGNUM (regno
))
11600 /* We have outlawed SI values in Cirrus registers because they
11601 reside in the lower 32 bits, but SF values reside in the
11602 upper 32 bits. This causes gcc all sorts of grief. We can't
11603 even split the registers into pairs because Cirrus SI values
11604 get sign extended to 64bits-- aldyh. */
11605 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11607 if (IS_VFP_REGNUM (regno
))
11609 if (mode
== SFmode
|| mode
== SImode
)
11612 /* DFmode values are only valid in even register pairs. */
11613 if (mode
== DFmode
)
11614 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11618 if (IS_IWMMXT_GR_REGNUM (regno
))
11619 return mode
== SImode
;
11621 if (IS_IWMMXT_REGNUM (regno
))
11622 return VALID_IWMMXT_REG_MODE (mode
);
11624 /* We allow any value to be stored in the general registers.
11625 Restrict doubleword quantities to even register pairs so that we can
11627 if (regno
<= LAST_ARM_REGNUM
)
11628 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11630 if ( regno
== FRAME_POINTER_REGNUM
11631 || regno
== ARG_POINTER_REGNUM
)
11632 /* We only allow integers in the fake hard registers. */
11633 return GET_MODE_CLASS (mode
) == MODE_INT
;
11635 /* The only registers left are the FPA registers
11636 which we only allow to hold FP values. */
11637 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11638 && regno
>= FIRST_FPA_REGNUM
11639 && regno
<= LAST_FPA_REGNUM
;
11643 arm_regno_class (int regno
)
11647 if (regno
== STACK_POINTER_REGNUM
)
11649 if (regno
== CC_REGNUM
)
11656 if ( regno
<= LAST_ARM_REGNUM
11657 || regno
== FRAME_POINTER_REGNUM
11658 || regno
== ARG_POINTER_REGNUM
)
11659 return GENERAL_REGS
;
11661 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11664 if (IS_CIRRUS_REGNUM (regno
))
11665 return CIRRUS_REGS
;
11667 if (IS_VFP_REGNUM (regno
))
11670 if (IS_IWMMXT_REGNUM (regno
))
11671 return IWMMXT_REGS
;
11673 if (IS_IWMMXT_GR_REGNUM (regno
))
11674 return IWMMXT_GR_REGS
;
11679 /* Handle a special case when computing the offset
11680 of an argument from the frame pointer. */
11682 arm_debugger_arg_offset (int value
, rtx addr
)
11686 /* We are only interested if dbxout_parms() failed to compute the offset. */
11690 /* We can only cope with the case where the address is held in a register. */
11691 if (GET_CODE (addr
) != REG
)
11694 /* If we are using the frame pointer to point at the argument, then
11695 an offset of 0 is correct. */
11696 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11699 /* If we are using the stack pointer to point at the
11700 argument, then an offset of 0 is correct. */
11701 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11702 && REGNO (addr
) == SP_REGNUM
)
11705 /* Oh dear. The argument is pointed to by a register rather
11706 than being held in a register, or being stored at a known
11707 offset from the frame pointer. Since GDB only understands
11708 those two kinds of argument we must translate the address
11709 held in the register into an offset from the frame pointer.
11710 We do this by searching through the insns for the function
11711 looking to see where this register gets its value. If the
11712 register is initialized from the frame pointer plus an offset
11713 then we are in luck and we can continue, otherwise we give up.
11715 This code is exercised by producing debugging information
11716 for a function with arguments like this:
11718 double func (double a, double b, int c, double d) {return d;}
11720 Without this code the stab for parameter 'd' will be set to
11721 an offset of 0 from the frame pointer, rather than 8. */
11723 /* The if() statement says:
11725 If the insn is a normal instruction
11726 and if the insn is setting the value in a register
11727 and if the register being set is the register holding the address of the argument
11728 and if the address is computing by an addition
11729 that involves adding to a register
11730 which is the frame pointer
11735 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11737 if ( GET_CODE (insn
) == INSN
11738 && GET_CODE (PATTERN (insn
)) == SET
11739 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11740 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11741 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11742 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11743 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11746 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11755 warning ("unable to compute real location of stacked parameter");
11756 value
= 8; /* XXX magic hack */
11762 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11765 if ((MASK) & insn_flags) \
11766 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11767 BUILT_IN_MD, NULL, NULL_TREE); \
11771 struct builtin_description
11773 const unsigned int mask
;
11774 const enum insn_code icode
;
11775 const char * const name
;
11776 const enum arm_builtins code
;
11777 const enum rtx_code comparison
;
11778 const unsigned int flag
;
11781 static const struct builtin_description bdesc_2arg
[] =
11783 #define IWMMXT_BUILTIN(code, string, builtin) \
11784 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11785 ARM_BUILTIN_##builtin, 0, 0 },
11787 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
11788 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
11789 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
11790 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
11791 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
11792 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
11793 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
11794 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
11795 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
11796 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
11797 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
11798 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
11799 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
11800 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
11801 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
11802 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
11803 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
11804 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
11805 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
11806 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
11807 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
11808 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
11809 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
11810 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
11811 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
11812 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
11813 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
11814 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
11815 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
11816 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
11817 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
11818 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
11819 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
11820 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
11821 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
11822 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
11823 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
11824 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
11825 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
11826 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
11827 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
11828 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
11829 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
11830 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
11831 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
11832 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
11833 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
11834 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
11835 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
11836 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
11837 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
11838 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
11839 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
11840 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
11841 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
11842 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
11843 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
11844 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
11846 #define IWMMXT_BUILTIN2(code, builtin) \
11847 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11849 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
11850 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
11851 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
11852 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
11853 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
11854 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
11855 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
11856 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
11857 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
11858 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
11859 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
11860 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
11861 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
11862 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
11863 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
11864 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
11865 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
11866 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
11867 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
11868 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
11869 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
11870 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
11871 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
11872 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
11873 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
11874 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
11875 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
11876 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
11877 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
11878 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
11879 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
11880 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
11883 static const struct builtin_description bdesc_1arg
[] =
11885 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
11886 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
11887 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
11888 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
11889 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
11890 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
11891 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
11892 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
11893 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
11894 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
11895 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
11896 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
11897 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
11898 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
11899 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
11900 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
11901 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
11902 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
11905 /* Set up all the iWMMXt builtins. This is
11906 not called if TARGET_IWMMXT is zero. */
11909 arm_init_iwmmxt_builtins (void)
11911 const struct builtin_description
* d
;
11913 tree endlink
= void_list_node
;
11915 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
11916 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
11917 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
11920 = build_function_type (integer_type_node
,
11921 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
11922 tree v8qi_ftype_v8qi_v8qi_int
11923 = build_function_type (V8QI_type_node
,
11924 tree_cons (NULL_TREE
, V8QI_type_node
,
11925 tree_cons (NULL_TREE
, V8QI_type_node
,
11926 tree_cons (NULL_TREE
,
11929 tree v4hi_ftype_v4hi_int
11930 = build_function_type (V4HI_type_node
,
11931 tree_cons (NULL_TREE
, V4HI_type_node
,
11932 tree_cons (NULL_TREE
, integer_type_node
,
11934 tree v2si_ftype_v2si_int
11935 = build_function_type (V2SI_type_node
,
11936 tree_cons (NULL_TREE
, V2SI_type_node
,
11937 tree_cons (NULL_TREE
, integer_type_node
,
11939 tree v2si_ftype_di_di
11940 = build_function_type (V2SI_type_node
,
11941 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11942 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11944 tree di_ftype_di_int
11945 = build_function_type (long_long_integer_type_node
,
11946 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11947 tree_cons (NULL_TREE
, integer_type_node
,
11949 tree di_ftype_di_int_int
11950 = build_function_type (long_long_integer_type_node
,
11951 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11952 tree_cons (NULL_TREE
, integer_type_node
,
11953 tree_cons (NULL_TREE
,
11956 tree int_ftype_v8qi
11957 = build_function_type (integer_type_node
,
11958 tree_cons (NULL_TREE
, V8QI_type_node
,
11960 tree int_ftype_v4hi
11961 = build_function_type (integer_type_node
,
11962 tree_cons (NULL_TREE
, V4HI_type_node
,
11964 tree int_ftype_v2si
11965 = build_function_type (integer_type_node
,
11966 tree_cons (NULL_TREE
, V2SI_type_node
,
11968 tree int_ftype_v8qi_int
11969 = build_function_type (integer_type_node
,
11970 tree_cons (NULL_TREE
, V8QI_type_node
,
11971 tree_cons (NULL_TREE
, integer_type_node
,
11973 tree int_ftype_v4hi_int
11974 = build_function_type (integer_type_node
,
11975 tree_cons (NULL_TREE
, V4HI_type_node
,
11976 tree_cons (NULL_TREE
, integer_type_node
,
11978 tree int_ftype_v2si_int
11979 = build_function_type (integer_type_node
,
11980 tree_cons (NULL_TREE
, V2SI_type_node
,
11981 tree_cons (NULL_TREE
, integer_type_node
,
11983 tree v8qi_ftype_v8qi_int_int
11984 = build_function_type (V8QI_type_node
,
11985 tree_cons (NULL_TREE
, V8QI_type_node
,
11986 tree_cons (NULL_TREE
, integer_type_node
,
11987 tree_cons (NULL_TREE
,
11990 tree v4hi_ftype_v4hi_int_int
11991 = build_function_type (V4HI_type_node
,
11992 tree_cons (NULL_TREE
, V4HI_type_node
,
11993 tree_cons (NULL_TREE
, integer_type_node
,
11994 tree_cons (NULL_TREE
,
11997 tree v2si_ftype_v2si_int_int
11998 = build_function_type (V2SI_type_node
,
11999 tree_cons (NULL_TREE
, V2SI_type_node
,
12000 tree_cons (NULL_TREE
, integer_type_node
,
12001 tree_cons (NULL_TREE
,
12004 /* Miscellaneous. */
12005 tree v8qi_ftype_v4hi_v4hi
12006 = build_function_type (V8QI_type_node
,
12007 tree_cons (NULL_TREE
, V4HI_type_node
,
12008 tree_cons (NULL_TREE
, V4HI_type_node
,
12010 tree v4hi_ftype_v2si_v2si
12011 = build_function_type (V4HI_type_node
,
12012 tree_cons (NULL_TREE
, V2SI_type_node
,
12013 tree_cons (NULL_TREE
, V2SI_type_node
,
12015 tree v2si_ftype_v4hi_v4hi
12016 = build_function_type (V2SI_type_node
,
12017 tree_cons (NULL_TREE
, V4HI_type_node
,
12018 tree_cons (NULL_TREE
, V4HI_type_node
,
12020 tree v2si_ftype_v8qi_v8qi
12021 = build_function_type (V2SI_type_node
,
12022 tree_cons (NULL_TREE
, V8QI_type_node
,
12023 tree_cons (NULL_TREE
, V8QI_type_node
,
12025 tree v4hi_ftype_v4hi_di
12026 = build_function_type (V4HI_type_node
,
12027 tree_cons (NULL_TREE
, V4HI_type_node
,
12028 tree_cons (NULL_TREE
,
12029 long_long_integer_type_node
,
12031 tree v2si_ftype_v2si_di
12032 = build_function_type (V2SI_type_node
,
12033 tree_cons (NULL_TREE
, V2SI_type_node
,
12034 tree_cons (NULL_TREE
,
12035 long_long_integer_type_node
,
12037 tree void_ftype_int_int
12038 = build_function_type (void_type_node
,
12039 tree_cons (NULL_TREE
, integer_type_node
,
12040 tree_cons (NULL_TREE
, integer_type_node
,
12043 = build_function_type (long_long_unsigned_type_node
, endlink
);
12045 = build_function_type (long_long_integer_type_node
,
12046 tree_cons (NULL_TREE
, V8QI_type_node
,
12049 = build_function_type (long_long_integer_type_node
,
12050 tree_cons (NULL_TREE
, V4HI_type_node
,
12053 = build_function_type (long_long_integer_type_node
,
12054 tree_cons (NULL_TREE
, V2SI_type_node
,
12056 tree v2si_ftype_v4hi
12057 = build_function_type (V2SI_type_node
,
12058 tree_cons (NULL_TREE
, V4HI_type_node
,
12060 tree v4hi_ftype_v8qi
12061 = build_function_type (V4HI_type_node
,
12062 tree_cons (NULL_TREE
, V8QI_type_node
,
12065 tree di_ftype_di_v4hi_v4hi
12066 = build_function_type (long_long_unsigned_type_node
,
12067 tree_cons (NULL_TREE
,
12068 long_long_unsigned_type_node
,
12069 tree_cons (NULL_TREE
, V4HI_type_node
,
12070 tree_cons (NULL_TREE
,
12074 tree di_ftype_v4hi_v4hi
12075 = build_function_type (long_long_unsigned_type_node
,
12076 tree_cons (NULL_TREE
, V4HI_type_node
,
12077 tree_cons (NULL_TREE
, V4HI_type_node
,
12080 /* Normal vector binops. */
12081 tree v8qi_ftype_v8qi_v8qi
12082 = build_function_type (V8QI_type_node
,
12083 tree_cons (NULL_TREE
, V8QI_type_node
,
12084 tree_cons (NULL_TREE
, V8QI_type_node
,
12086 tree v4hi_ftype_v4hi_v4hi
12087 = build_function_type (V4HI_type_node
,
12088 tree_cons (NULL_TREE
, V4HI_type_node
,
12089 tree_cons (NULL_TREE
, V4HI_type_node
,
12091 tree v2si_ftype_v2si_v2si
12092 = build_function_type (V2SI_type_node
,
12093 tree_cons (NULL_TREE
, V2SI_type_node
,
12094 tree_cons (NULL_TREE
, V2SI_type_node
,
12096 tree di_ftype_di_di
12097 = build_function_type (long_long_unsigned_type_node
,
12098 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12099 tree_cons (NULL_TREE
,
12100 long_long_unsigned_type_node
,
12103 /* Add all builtins that are more or less simple operations on two
12105 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12107 /* Use one of the operands; the target can have a different mode for
12108 mask-generating compares. */
12109 enum machine_mode mode
;
12115 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12120 type
= v8qi_ftype_v8qi_v8qi
;
12123 type
= v4hi_ftype_v4hi_v4hi
;
12126 type
= v2si_ftype_v2si_v2si
;
12129 type
= di_ftype_di_di
;
12136 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12139 /* Add the remaining MMX insns with somewhat more complicated types. */
12140 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12141 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12142 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12144 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12145 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12146 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12147 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12148 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12149 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12151 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12152 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12153 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12154 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12155 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12156 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12158 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12159 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12160 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12161 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12162 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12163 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12165 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12166 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12167 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12168 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12169 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12170 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12172 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12174 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12175 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12176 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12177 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12179 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12180 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12181 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12182 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12183 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12184 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12185 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12186 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12187 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12189 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12190 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12191 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12193 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12194 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12195 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12197 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12198 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12199 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12200 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12201 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12202 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12204 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12205 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12206 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12207 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12208 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12209 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12210 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12211 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12212 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12213 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12214 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12215 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12217 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12218 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12219 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12220 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12222 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12223 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12224 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12225 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12226 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12227 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12228 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12232 arm_init_builtins (void)
12234 if (TARGET_REALLY_IWMMXT
)
12235 arm_init_iwmmxt_builtins ();
12238 /* Errors in the source file can cause expand_expr to return const0_rtx
12239 where we expect a vector. To avoid crashing, use one of the vector
12240 clear instructions. */
12243 safe_vector_operand (rtx x
, enum machine_mode mode
)
12245 if (x
!= const0_rtx
)
12247 x
= gen_reg_rtx (mode
);
12249 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12250 : gen_rtx_SUBREG (DImode
, x
, 0)));
12254 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12257 arm_expand_binop_builtin (enum insn_code icode
,
12258 tree arglist
, rtx target
)
12261 tree arg0
= TREE_VALUE (arglist
);
12262 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12263 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12264 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12265 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12266 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12267 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12269 if (VECTOR_MODE_P (mode0
))
12270 op0
= safe_vector_operand (op0
, mode0
);
12271 if (VECTOR_MODE_P (mode1
))
12272 op1
= safe_vector_operand (op1
, mode1
);
12275 || GET_MODE (target
) != tmode
12276 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12277 target
= gen_reg_rtx (tmode
);
12279 /* In case the insn wants input operands in modes different from
12280 the result, abort. */
12281 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
12284 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12285 op0
= copy_to_mode_reg (mode0
, op0
);
12286 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12287 op1
= copy_to_mode_reg (mode1
, op1
);
12289 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12296 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12299 arm_expand_unop_builtin (enum insn_code icode
,
12300 tree arglist
, rtx target
, int do_load
)
12303 tree arg0
= TREE_VALUE (arglist
);
12304 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12305 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12306 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12309 || GET_MODE (target
) != tmode
12310 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12311 target
= gen_reg_rtx (tmode
);
12313 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12316 if (VECTOR_MODE_P (mode0
))
12317 op0
= safe_vector_operand (op0
, mode0
);
12319 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12320 op0
= copy_to_mode_reg (mode0
, op0
);
12323 pat
= GEN_FCN (icode
) (target
, op0
);
12330 /* Expand an expression EXP that calls a built-in function,
12331 with result going to TARGET if that's convenient
12332 (and in mode MODE if that's convenient).
12333 SUBTARGET may be used as the target for computing one of EXP's operands.
12334 IGNORE is nonzero if the value is to be ignored. */
12337 arm_expand_builtin (tree exp
,
12339 rtx subtarget ATTRIBUTE_UNUSED
,
12340 enum machine_mode mode ATTRIBUTE_UNUSED
,
12341 int ignore ATTRIBUTE_UNUSED
)
12343 const struct builtin_description
* d
;
12344 enum insn_code icode
;
12345 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12346 tree arglist
= TREE_OPERAND (exp
, 1);
12354 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12356 enum machine_mode tmode
;
12357 enum machine_mode mode0
;
12358 enum machine_mode mode1
;
12359 enum machine_mode mode2
;
12363 case ARM_BUILTIN_TEXTRMSB
:
12364 case ARM_BUILTIN_TEXTRMUB
:
12365 case ARM_BUILTIN_TEXTRMSH
:
12366 case ARM_BUILTIN_TEXTRMUH
:
12367 case ARM_BUILTIN_TEXTRMSW
:
12368 case ARM_BUILTIN_TEXTRMUW
:
12369 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12370 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12371 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12372 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12373 : CODE_FOR_iwmmxt_textrmw
);
12375 arg0
= TREE_VALUE (arglist
);
12376 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12377 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12378 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12379 tmode
= insn_data
[icode
].operand
[0].mode
;
12380 mode0
= insn_data
[icode
].operand
[1].mode
;
12381 mode1
= insn_data
[icode
].operand
[2].mode
;
12383 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12384 op0
= copy_to_mode_reg (mode0
, op0
);
12385 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12387 /* @@@ better error message */
12388 error ("selector must be an immediate");
12389 return gen_reg_rtx (tmode
);
12392 || GET_MODE (target
) != tmode
12393 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12394 target
= gen_reg_rtx (tmode
);
12395 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12401 case ARM_BUILTIN_TINSRB
:
12402 case ARM_BUILTIN_TINSRH
:
12403 case ARM_BUILTIN_TINSRW
:
12404 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12405 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12406 : CODE_FOR_iwmmxt_tinsrw
);
12407 arg0
= TREE_VALUE (arglist
);
12408 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12409 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12410 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12411 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12412 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12413 tmode
= insn_data
[icode
].operand
[0].mode
;
12414 mode0
= insn_data
[icode
].operand
[1].mode
;
12415 mode1
= insn_data
[icode
].operand
[2].mode
;
12416 mode2
= insn_data
[icode
].operand
[3].mode
;
12418 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12419 op0
= copy_to_mode_reg (mode0
, op0
);
12420 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12421 op1
= copy_to_mode_reg (mode1
, op1
);
12422 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12424 /* @@@ better error message */
12425 error ("selector must be an immediate");
12429 || GET_MODE (target
) != tmode
12430 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12431 target
= gen_reg_rtx (tmode
);
12432 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12438 case ARM_BUILTIN_SETWCX
:
12439 arg0
= TREE_VALUE (arglist
);
12440 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12441 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12442 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12443 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12446 case ARM_BUILTIN_GETWCX
:
12447 arg0
= TREE_VALUE (arglist
);
12448 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12449 target
= gen_reg_rtx (SImode
);
12450 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12453 case ARM_BUILTIN_WSHUFH
:
12454 icode
= CODE_FOR_iwmmxt_wshufh
;
12455 arg0
= TREE_VALUE (arglist
);
12456 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12457 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12458 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12459 tmode
= insn_data
[icode
].operand
[0].mode
;
12460 mode1
= insn_data
[icode
].operand
[1].mode
;
12461 mode2
= insn_data
[icode
].operand
[2].mode
;
12463 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12464 op0
= copy_to_mode_reg (mode1
, op0
);
12465 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12467 /* @@@ better error message */
12468 error ("mask must be an immediate");
12472 || GET_MODE (target
) != tmode
12473 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12474 target
= gen_reg_rtx (tmode
);
12475 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12481 case ARM_BUILTIN_WSADB
:
12482 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12483 case ARM_BUILTIN_WSADH
:
12484 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12485 case ARM_BUILTIN_WSADBZ
:
12486 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12487 case ARM_BUILTIN_WSADHZ
:
12488 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12490 /* Several three-argument builtins. */
12491 case ARM_BUILTIN_WMACS
:
12492 case ARM_BUILTIN_WMACU
:
12493 case ARM_BUILTIN_WALIGN
:
12494 case ARM_BUILTIN_TMIA
:
12495 case ARM_BUILTIN_TMIAPH
:
12496 case ARM_BUILTIN_TMIATT
:
12497 case ARM_BUILTIN_TMIATB
:
12498 case ARM_BUILTIN_TMIABT
:
12499 case ARM_BUILTIN_TMIABB
:
12500 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12501 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12502 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12503 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12504 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12505 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12506 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12507 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12508 : CODE_FOR_iwmmxt_walign
);
12509 arg0
= TREE_VALUE (arglist
);
12510 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12511 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12512 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12513 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12514 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12515 tmode
= insn_data
[icode
].operand
[0].mode
;
12516 mode0
= insn_data
[icode
].operand
[1].mode
;
12517 mode1
= insn_data
[icode
].operand
[2].mode
;
12518 mode2
= insn_data
[icode
].operand
[3].mode
;
12520 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12521 op0
= copy_to_mode_reg (mode0
, op0
);
12522 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12523 op1
= copy_to_mode_reg (mode1
, op1
);
12524 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12525 op2
= copy_to_mode_reg (mode2
, op2
);
12527 || GET_MODE (target
) != tmode
12528 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12529 target
= gen_reg_rtx (tmode
);
12530 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12536 case ARM_BUILTIN_WZERO
:
12537 target
= gen_reg_rtx (DImode
);
12538 emit_insn (gen_iwmmxt_clrdi (target
));
12545 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12546 if (d
->code
== (const enum arm_builtins
) fcode
)
12547 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12549 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12550 if (d
->code
== (const enum arm_builtins
) fcode
)
12551 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12553 /* @@@ Should really do something sensible here. */
12557 /* Recursively search through all of the blocks in a function
12558 checking to see if any of the variables created in that
12559 function match the RTX called 'orig'. If they do then
12560 replace them with the RTX called 'new'. */
12562 replace_symbols_in_block (tree block
, rtx orig
, rtx
new)
12564 for (; block
; block
= BLOCK_CHAIN (block
))
12568 if (!TREE_USED (block
))
12571 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
12573 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
12574 || DECL_IGNORED_P (sym
)
12575 || TREE_CODE (sym
) != VAR_DECL
12576 || DECL_EXTERNAL (sym
)
12577 || !rtx_equal_p (DECL_RTL (sym
), orig
)
12581 SET_DECL_RTL (sym
, new);
12584 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
12588 /* Return the number (counting from 0) of
12589 the least significant set bit in MASK. */
12592 number_of_first_bit_set (int mask
)
12597 (mask
& (1 << bit
)) == 0;
12604 /* Generate code to return from a thumb function.
12605 If 'reg_containing_return_addr' is -1, then the return address is
12606 actually on the stack, at the stack pointer. */
12608 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12610 unsigned regs_available_for_popping
;
12611 unsigned regs_to_pop
;
12613 unsigned available
;
12617 int restore_a4
= FALSE
;
12619 /* Compute the registers we need to pop. */
12623 if (reg_containing_return_addr
== -1)
12625 regs_to_pop
|= 1 << LR_REGNUM
;
12629 if (TARGET_BACKTRACE
)
12631 /* Restore the (ARM) frame pointer and stack pointer. */
12632 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12636 /* If there is nothing to pop then just emit the BX instruction and
12638 if (pops_needed
== 0)
12640 if (current_function_calls_eh_return
)
12641 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12643 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12646 /* Otherwise if we are not supporting interworking and we have not created
12647 a backtrace structure and the function was not entered in ARM mode then
12648 just pop the return address straight into the PC. */
12649 else if (!TARGET_INTERWORK
12650 && !TARGET_BACKTRACE
12651 && !is_called_in_ARM_mode (current_function_decl
)
12652 && !current_function_calls_eh_return
)
12654 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12658 /* Find out how many of the (return) argument registers we can corrupt. */
12659 regs_available_for_popping
= 0;
12661 /* If returning via __builtin_eh_return, the bottom three registers
12662 all contain information needed for the return. */
12663 if (current_function_calls_eh_return
)
12667 /* If we can deduce the registers used from the function's
12668 return value. This is more reliable that examining
12669 regs_ever_live[] because that will be set if the register is
12670 ever used in the function, not just if the register is used
12671 to hold a return value. */
12673 if (current_function_return_rtx
!= 0)
12674 mode
= GET_MODE (current_function_return_rtx
);
12676 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12678 size
= GET_MODE_SIZE (mode
);
12682 /* In a void function we can use any argument register.
12683 In a function that returns a structure on the stack
12684 we can use the second and third argument registers. */
12685 if (mode
== VOIDmode
)
12686 regs_available_for_popping
=
12687 (1 << ARG_REGISTER (1))
12688 | (1 << ARG_REGISTER (2))
12689 | (1 << ARG_REGISTER (3));
12691 regs_available_for_popping
=
12692 (1 << ARG_REGISTER (2))
12693 | (1 << ARG_REGISTER (3));
12695 else if (size
<= 4)
12696 regs_available_for_popping
=
12697 (1 << ARG_REGISTER (2))
12698 | (1 << ARG_REGISTER (3));
12699 else if (size
<= 8)
12700 regs_available_for_popping
=
12701 (1 << ARG_REGISTER (3));
12704 /* Match registers to be popped with registers into which we pop them. */
12705 for (available
= regs_available_for_popping
,
12706 required
= regs_to_pop
;
12707 required
!= 0 && available
!= 0;
12708 available
&= ~(available
& - available
),
12709 required
&= ~(required
& - required
))
12712 /* If we have any popping registers left over, remove them. */
12714 regs_available_for_popping
&= ~available
;
12716 /* Otherwise if we need another popping register we can use
12717 the fourth argument register. */
12718 else if (pops_needed
)
12720 /* If we have not found any free argument registers and
12721 reg a4 contains the return address, we must move it. */
12722 if (regs_available_for_popping
== 0
12723 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
12725 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12726 reg_containing_return_addr
= LR_REGNUM
;
12728 else if (size
> 12)
12730 /* Register a4 is being used to hold part of the return value,
12731 but we have dire need of a free, low register. */
12734 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
12737 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
12739 /* The fourth argument register is available. */
12740 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
12746 /* Pop as many registers as we can. */
12747 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12748 regs_available_for_popping
);
12750 /* Process the registers we popped. */
12751 if (reg_containing_return_addr
== -1)
12753 /* The return address was popped into the lowest numbered register. */
12754 regs_to_pop
&= ~(1 << LR_REGNUM
);
12756 reg_containing_return_addr
=
12757 number_of_first_bit_set (regs_available_for_popping
);
12759 /* Remove this register for the mask of available registers, so that
12760 the return address will not be corrupted by further pops. */
12761 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
12764 /* If we popped other registers then handle them here. */
12765 if (regs_available_for_popping
)
12769 /* Work out which register currently contains the frame pointer. */
12770 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12772 /* Move it into the correct place. */
12773 asm_fprintf (f
, "\tmov\t%r, %r\n",
12774 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
12776 /* (Temporarily) remove it from the mask of popped registers. */
12777 regs_available_for_popping
&= ~(1 << frame_pointer
);
12778 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
12780 if (regs_available_for_popping
)
12784 /* We popped the stack pointer as well,
12785 find the register that contains it. */
12786 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12788 /* Move it into the stack register. */
12789 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
12791 /* At this point we have popped all necessary registers, so
12792 do not worry about restoring regs_available_for_popping
12793 to its correct value:
12795 assert (pops_needed == 0)
12796 assert (regs_available_for_popping == (1 << frame_pointer))
12797 assert (regs_to_pop == (1 << STACK_POINTER)) */
12801 /* Since we have just move the popped value into the frame
12802 pointer, the popping register is available for reuse, and
12803 we know that we still have the stack pointer left to pop. */
12804 regs_available_for_popping
|= (1 << frame_pointer
);
12808 /* If we still have registers left on the stack, but we no longer have
12809 any registers into which we can pop them, then we must move the return
12810 address into the link register and make available the register that
12812 if (regs_available_for_popping
== 0 && pops_needed
> 0)
12814 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
12816 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
12817 reg_containing_return_addr
);
12819 reg_containing_return_addr
= LR_REGNUM
;
12822 /* If we have registers left on the stack then pop some more.
12823 We know that at most we will want to pop FP and SP. */
12824 if (pops_needed
> 0)
12829 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12830 regs_available_for_popping
);
12832 /* We have popped either FP or SP.
12833 Move whichever one it is into the correct register. */
12834 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12835 move_to
= number_of_first_bit_set (regs_to_pop
);
12837 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
12839 regs_to_pop
&= ~(1 << move_to
);
12844 /* If we still have not popped everything then we must have only
12845 had one register available to us and we are now popping the SP. */
12846 if (pops_needed
> 0)
12850 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12851 regs_available_for_popping
);
12853 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12855 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
12857 assert (regs_to_pop == (1 << STACK_POINTER))
12858 assert (pops_needed == 1)
12862 /* If necessary restore the a4 register. */
12865 if (reg_containing_return_addr
!= LR_REGNUM
)
12867 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12868 reg_containing_return_addr
= LR_REGNUM
;
12871 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12874 if (current_function_calls_eh_return
)
12875 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12877 /* Return to caller. */
12878 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12881 /* Emit code to push or pop registers to or from the stack. F is the
12882 assembly file. MASK is the registers to push or pop. PUSH is
12883 nonzero if we should push, and zero if we should pop. For debugging
12884 output, if pushing, adjust CFA_OFFSET by the amount of space added
12885 to the stack. REAL_REGS should have the same number of bits set as
12886 MASK, and will be used instead (in the same order) to describe which
12887 registers were saved - this is used to mark the save slots when we
12888 push high registers after moving them to low registers. */
12890 thumb_pushpop (FILE *f
, int mask
, int push
, int *cfa_offset
, int real_regs
)
12893 int lo_mask
= mask
& 0xFF;
12894 int pushed_words
= 0;
12896 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12898 /* Special case. Do not generate a POP PC statement here, do it in
12900 thumb_exit (f
, -1);
12904 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12906 /* Look at the low registers first. */
12907 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12911 asm_fprintf (f
, "%r", regno
);
12913 if ((lo_mask
& ~1) != 0)
12920 if (push
&& (mask
& (1 << LR_REGNUM
)))
12922 /* Catch pushing the LR. */
12926 asm_fprintf (f
, "%r", LR_REGNUM
);
12930 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12932 /* Catch popping the PC. */
12933 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12934 || current_function_calls_eh_return
)
12936 /* The PC is never poped directly, instead
12937 it is popped into r3 and then BX is used. */
12938 fprintf (f
, "}\n");
12940 thumb_exit (f
, -1);
12949 asm_fprintf (f
, "%r", PC_REGNUM
);
12953 fprintf (f
, "}\n");
12955 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12957 char *l
= dwarf2out_cfi_label ();
12958 int pushed_mask
= real_regs
;
12960 *cfa_offset
+= pushed_words
* 4;
12961 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12964 pushed_mask
= real_regs
;
12965 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12967 if (pushed_mask
& 1)
12968 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12974 thumb_final_prescan_insn (rtx insn
)
12976 if (flag_print_asm_name
)
12977 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
12978 INSN_ADDRESSES (INSN_UID (insn
)));
12982 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
12984 unsigned HOST_WIDE_INT mask
= 0xff;
12987 if (val
== 0) /* XXX */
12990 for (i
= 0; i
< 25; i
++)
12991 if ((val
& (mask
<< i
)) == val
)
12997 /* Returns nonzero if the current function contains,
12998 or might contain a far jump. */
13000 thumb_far_jump_used_p (void)
13004 /* This test is only important for leaf functions. */
13005 /* assert (!leaf_function_p ()); */
13007 /* If we have already decided that far jumps may be used,
13008 do not bother checking again, and always return true even if
13009 it turns out that they are not being used. Once we have made
13010 the decision that far jumps are present (and that hence the link
13011 register will be pushed onto the stack) we cannot go back on it. */
13012 if (cfun
->machine
->far_jump_used
)
13015 /* If this function is not being called from the prologue/epilogue
13016 generation code then it must be being called from the
13017 INITIAL_ELIMINATION_OFFSET macro. */
13018 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13020 /* In this case we know that we are being asked about the elimination
13021 of the arg pointer register. If that register is not being used,
13022 then there are no arguments on the stack, and we do not have to
13023 worry that a far jump might force the prologue to push the link
13024 register, changing the stack offsets. In this case we can just
13025 return false, since the presence of far jumps in the function will
13026 not affect stack offsets.
13028 If the arg pointer is live (or if it was live, but has now been
13029 eliminated and so set to dead) then we do have to test to see if
13030 the function might contain a far jump. This test can lead to some
13031 false negatives, since before reload is completed, then length of
13032 branch instructions is not known, so gcc defaults to returning their
13033 longest length, which in turn sets the far jump attribute to true.
13035 A false negative will not result in bad code being generated, but it
13036 will result in a needless push and pop of the link register. We
13037 hope that this does not occur too often.
13039 If we need doubleword stack alignment this could affect the other
13040 elimination offsets so we can't risk getting it wrong. */
13041 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13042 cfun
->machine
->arg_pointer_live
= 1;
13043 else if (!cfun
->machine
->arg_pointer_live
)
13047 /* Check to see if the function contains a branch
13048 insn with the far jump attribute set. */
13049 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13051 if (GET_CODE (insn
) == JUMP_INSN
13052 /* Ignore tablejump patterns. */
13053 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13054 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13055 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13058 /* Record the fact that we have decided that
13059 the function does use far jumps. */
13060 cfun
->machine
->far_jump_used
= 1;
13068 /* Return nonzero if FUNC must be entered in ARM mode. */
13070 is_called_in_ARM_mode (tree func
)
13072 if (TREE_CODE (func
) != FUNCTION_DECL
)
13075 /* Ignore the problem about functions whoes address is taken. */
13076 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13080 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13086 /* The bits which aren't usefully expanded as rtl. */
13088 thumb_unexpanded_epilogue (void)
13091 int live_regs_mask
= 0;
13092 int high_regs_pushed
= 0;
13093 int had_to_push_lr
;
13097 if (return_used_this_function
)
13100 if (IS_NAKED (arm_current_func_type ()))
13103 live_regs_mask
= thumb_compute_save_reg_mask ();
13104 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13106 /* If we can deduce the registers used from the function's return value.
13107 This is more reliable that examining regs_ever_live[] because that
13108 will be set if the register is ever used in the function, not just if
13109 the register is used to hold a return value. */
13111 if (current_function_return_rtx
!= 0)
13112 mode
= GET_MODE (current_function_return_rtx
);
13114 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13116 size
= GET_MODE_SIZE (mode
);
13118 /* The prolog may have pushed some high registers to use as
13119 work registers. eg the testsuite file:
13120 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13121 compiles to produce:
13122 push {r4, r5, r6, r7, lr}
13126 as part of the prolog. We have to undo that pushing here. */
13128 if (high_regs_pushed
)
13130 int mask
= live_regs_mask
& 0xff;
13133 /* The available low registers depend on the size of the value we are
13141 /* Oh dear! We have no low registers into which we can pop
13144 ("no low registers available for popping high registers");
13146 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13147 if (live_regs_mask
& (1 << next_hi_reg
))
13150 while (high_regs_pushed
)
13152 /* Find lo register(s) into which the high register(s) can
13154 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13156 if (mask
& (1 << regno
))
13157 high_regs_pushed
--;
13158 if (high_regs_pushed
== 0)
13162 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13164 /* Pop the values into the low register(s). */
13165 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13167 /* Move the value(s) into the high registers. */
13168 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13170 if (mask
& (1 << regno
))
13172 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13175 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13176 if (live_regs_mask
& (1 << next_hi_reg
))
13181 live_regs_mask
&= ~0x0f00;
13184 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13185 live_regs_mask
&= 0xff;
13187 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13189 /* Pop the return address into the PC. */
13190 if (had_to_push_lr
)
13191 live_regs_mask
|= 1 << PC_REGNUM
;
13193 /* Either no argument registers were pushed or a backtrace
13194 structure was created which includes an adjusted stack
13195 pointer, so just pop everything. */
13196 if (live_regs_mask
)
13197 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13200 /* We have either just popped the return address into the
13201 PC or it is was kept in LR for the entire function. */
13202 if (!had_to_push_lr
)
13203 thumb_exit (asm_out_file
, LR_REGNUM
);
13207 /* Pop everything but the return address. */
13208 if (live_regs_mask
)
13209 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13212 if (had_to_push_lr
)
13216 /* We have no free low regs, so save one. */
13217 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13221 /* Get the return address into a temporary register. */
13222 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13223 1 << LAST_ARG_REGNUM
);
13227 /* Move the return address to lr. */
13228 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13230 /* Restore the low register. */
13231 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13236 regno
= LAST_ARG_REGNUM
;
13241 /* Remove the argument registers that were pushed onto the stack. */
13242 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13243 SP_REGNUM
, SP_REGNUM
,
13244 current_function_pretend_args_size
);
13246 thumb_exit (asm_out_file
, regno
);
13252 /* Functions to save and restore machine-specific function data. */
13253 static struct machine_function
*
13254 arm_init_machine_status (void)
13256 struct machine_function
*machine
;
13257 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13259 #if ARM_FT_UNKNOWN != 0
13260 machine
->func_type
= ARM_FT_UNKNOWN
;
13265 /* Return an RTX indicating where the return address to the
13266 calling function can be found. */
13268 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13273 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13276 /* Do anything needed before RTL is emitted for each function. */
13278 arm_init_expanders (void)
13280 /* Arrange to initialize and mark the machine per-function status. */
13281 init_machine_status
= arm_init_machine_status
;
13283 /* This is to stop the combine pass optimizing away the alignment
13284 adjustment of va_arg. */
13285 /* ??? It is claimed that this should not be necessary. */
13287 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13291 /* Like arm_compute_initial_elimination offset. Simpler because
13292 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13295 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13297 arm_stack_offsets
*offsets
;
13299 offsets
= arm_get_frame_offsets ();
13303 case ARG_POINTER_REGNUM
:
13306 case STACK_POINTER_REGNUM
:
13307 return offsets
->outgoing_args
- offsets
->saved_args
;
13309 case FRAME_POINTER_REGNUM
:
13310 return offsets
->soft_frame
- offsets
->saved_args
;
13312 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13313 case ARM_HARD_FRAME_POINTER_REGNUM
:
13314 return offsets
->saved_regs
- offsets
->saved_args
;
13321 case FRAME_POINTER_REGNUM
:
13324 case STACK_POINTER_REGNUM
:
13325 return offsets
->outgoing_args
- offsets
->soft_frame
;
13327 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13328 case ARM_HARD_FRAME_POINTER_REGNUM
:
13329 return offsets
->saved_regs
- offsets
->soft_frame
;
13342 /* Generate the rest of a function's prologue. */
13344 thumb_expand_prologue (void)
13348 HOST_WIDE_INT amount
;
13349 arm_stack_offsets
*offsets
;
13350 unsigned long func_type
;
13352 unsigned long live_regs_mask
;
13354 func_type
= arm_current_func_type ();
13356 /* Naked functions don't have prologues. */
13357 if (IS_NAKED (func_type
))
13360 if (IS_INTERRUPT (func_type
))
13362 error ("interrupt Service Routines cannot be coded in Thumb mode");
13366 /* Load the pic recister before setting the frame pointer, so we can use r7
13367 as a temporary work register. */
13369 arm_load_pic_register ();
13371 offsets
= arm_get_frame_offsets ();
13373 if (frame_pointer_needed
)
13375 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
13376 stack_pointer_rtx
));
13377 RTX_FRAME_RELATED_P (insn
) = 1;
13380 live_regs_mask
= thumb_compute_save_reg_mask ();
13381 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13386 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13387 GEN_INT (- amount
)));
13388 RTX_FRAME_RELATED_P (insn
) = 1;
13394 /* The stack decrement is too big for an immediate value in a single
13395 insn. In theory we could issue multiple subtracts, but after
13396 three of them it becomes more space efficient to place the full
13397 value in the constant pool and load into a register. (Also the
13398 ARM debugger really likes to see only one stack decrement per
13399 function). So instead we look for a scratch register into which
13400 we can load the decrement, and then we subtract this from the
13401 stack pointer. Unfortunately on the thumb the only available
13402 scratch registers are the argument registers, and we cannot use
13403 these as they may hold arguments to the function. Instead we
13404 attempt to locate a call preserved register which is used by this
13405 function. If we can find one, then we know that it will have
13406 been pushed at the start of the prologue and so we can corrupt
13408 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13409 if (live_regs_mask
& (1 << regno
)
13410 && !(frame_pointer_needed
13411 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13414 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13416 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13418 /* Choose an arbitrary, non-argument low register. */
13419 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13421 /* Save it by copying it into a high, scratch register. */
13422 emit_insn (gen_movsi (spare
, reg
));
13423 /* Add a USE to stop propagate_one_insn() from barfing. */
13424 emit_insn (gen_prologue_use (spare
));
13426 /* Decrement the stack. */
13427 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13428 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13429 stack_pointer_rtx
, reg
));
13430 RTX_FRAME_RELATED_P (insn
) = 1;
13431 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13432 plus_constant (stack_pointer_rtx
,
13434 RTX_FRAME_RELATED_P (dwarf
) = 1;
13436 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13439 /* Restore the low register's original value. */
13440 emit_insn (gen_movsi (reg
, spare
));
13442 /* Emit a USE of the restored scratch register, so that flow
13443 analysis will not consider the restore redundant. The
13444 register won't be used again in this function and isn't
13445 restored by the epilogue. */
13446 emit_insn (gen_prologue_use (reg
));
13450 reg
= gen_rtx_REG (SImode
, regno
);
13452 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13454 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13455 stack_pointer_rtx
, reg
));
13456 RTX_FRAME_RELATED_P (insn
) = 1;
13457 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13458 plus_constant (stack_pointer_rtx
,
13460 RTX_FRAME_RELATED_P (dwarf
) = 1;
13462 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13466 /* If the frame pointer is needed, emit a special barrier that
13467 will prevent the scheduler from moving stores to the frame
13468 before the stack adjustment. */
13469 if (frame_pointer_needed
)
13470 emit_insn (gen_stack_tie (stack_pointer_rtx
,
13471 hard_frame_pointer_rtx
));
13474 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13475 emit_insn (gen_blockage ());
13477 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13478 if (live_regs_mask
& 0xff)
13479 cfun
->machine
->lr_save_eliminated
= 0;
13481 /* If the link register is being kept alive, with the return address in it,
13482 then make sure that it does not get reused by the ce2 pass. */
13483 if (cfun
->machine
->lr_save_eliminated
)
13484 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13489 thumb_expand_epilogue (void)
13491 HOST_WIDE_INT amount
;
13492 arm_stack_offsets
*offsets
;
13495 /* Naked functions don't have prologues. */
13496 if (IS_NAKED (arm_current_func_type ()))
13499 offsets
= arm_get_frame_offsets ();
13500 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13502 if (frame_pointer_needed
)
13503 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13507 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13508 GEN_INT (amount
)));
13511 /* r3 is always free in the epilogue. */
13512 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13514 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13515 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13519 /* Emit a USE (stack_pointer_rtx), so that
13520 the stack adjustment will not be deleted. */
13521 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13523 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13524 emit_insn (gen_blockage ());
13526 /* Emit a clobber for each insn that will be restored in the epilogue,
13527 so that flow2 will get register lifetimes correct. */
13528 for (regno
= 0; regno
< 13; regno
++)
13529 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13530 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13532 if (! regs_ever_live
[LR_REGNUM
])
13533 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13537 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13539 int live_regs_mask
= 0;
13541 int high_regs_pushed
= 0;
13542 int cfa_offset
= 0;
13545 if (IS_NAKED (arm_current_func_type ()))
13548 if (is_called_in_ARM_mode (current_function_decl
))
13552 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
13554 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
13556 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13558 /* Generate code sequence to switch us into Thumb mode. */
13559 /* The .code 32 directive has already been emitted by
13560 ASM_DECLARE_FUNCTION_NAME. */
13561 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13562 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13564 /* Generate a label, so that the debugger will notice the
13565 change in instruction sets. This label is also used by
13566 the assembler to bypass the ARM code when this function
13567 is called from a Thumb encoded function elsewhere in the
13568 same file. Hence the definition of STUB_NAME here must
13569 agree with the definition in gas/config/tc-arm.c. */
13571 #define STUB_NAME ".real_start_of"
13573 fprintf (f
, "\t.code\t16\n");
13575 if (arm_dllexport_name_p (name
))
13576 name
= arm_strip_name_encoding (name
);
13578 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13579 fprintf (f
, "\t.thumb_func\n");
13580 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13583 if (current_function_pretend_args_size
)
13585 if (cfun
->machine
->uses_anonymous_args
)
13589 fprintf (f
, "\tpush\t{");
13591 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13593 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13594 regno
<= LAST_ARG_REGNUM
;
13596 asm_fprintf (f
, "%r%s", regno
,
13597 regno
== LAST_ARG_REGNUM
? "" : ", ");
13599 fprintf (f
, "}\n");
13602 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13603 SP_REGNUM
, SP_REGNUM
,
13604 current_function_pretend_args_size
);
13606 /* We don't need to record the stores for unwinding (would it
13607 help the debugger any if we did?), but record the change in
13608 the stack pointer. */
13609 if (dwarf2out_do_frame ())
13611 char *l
= dwarf2out_cfi_label ();
13612 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13613 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13617 live_regs_mask
= thumb_compute_save_reg_mask ();
13618 /* Just low regs and lr. */
13619 l_mask
= live_regs_mask
& 0x40ff;
13621 if (TARGET_BACKTRACE
)
13626 /* We have been asked to create a stack backtrace structure.
13627 The code looks like this:
13631 0 sub SP, #16 Reserve space for 4 registers.
13632 2 push {R7} Push low registers.
13633 4 add R7, SP, #20 Get the stack pointer before the push.
13634 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13635 8 mov R7, PC Get hold of the start of this code plus 12.
13636 10 str R7, [SP, #16] Store it.
13637 12 mov R7, FP Get hold of the current frame pointer.
13638 14 str R7, [SP, #4] Store it.
13639 16 mov R7, LR Get hold of the current return address.
13640 18 str R7, [SP, #12] Store it.
13641 20 add R7, SP, #16 Point at the start of the backtrace structure.
13642 22 mov FP, R7 Put this value into the frame pointer. */
13644 work_register
= thumb_find_work_register (live_regs_mask
);
13647 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13648 SP_REGNUM
, SP_REGNUM
);
13650 if (dwarf2out_do_frame ())
13652 char *l
= dwarf2out_cfi_label ();
13653 cfa_offset
= cfa_offset
+ 16;
13654 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13659 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13660 offset
= bit_count (l_mask
);
13665 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13666 offset
+ 16 + current_function_pretend_args_size
);
13668 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13671 /* Make sure that the instruction fetching the PC is in the right place
13672 to calculate "start of backtrace creation code + 12". */
13675 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13676 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13678 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13679 ARM_HARD_FRAME_POINTER_REGNUM
);
13680 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13685 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13686 ARM_HARD_FRAME_POINTER_REGNUM
);
13687 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13689 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13690 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13694 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13695 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13697 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13699 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13700 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13703 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13705 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13707 if (high_regs_pushed
)
13709 int pushable_regs
= 0;
13712 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13713 if (live_regs_mask
& (1 << next_hi_reg
))
13716 pushable_regs
= l_mask
& 0xff;
13718 if (pushable_regs
== 0)
13719 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13721 while (high_regs_pushed
> 0)
13723 int real_regs_mask
= 0;
13725 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13727 if (pushable_regs
& (1 << regno
))
13729 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13731 high_regs_pushed
--;
13732 real_regs_mask
|= (1 << next_hi_reg
);
13734 if (high_regs_pushed
)
13736 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13738 if (live_regs_mask
& (1 << next_hi_reg
))
13743 pushable_regs
&= ~((1 << regno
) - 1);
13749 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
13754 /* Handle the case of a double word load into a low register from
13755 a computed memory address. The computed address may involve a
13756 register which is overwritten by the load. */
13758 thumb_load_double_from_address (rtx
*operands
)
13766 if (GET_CODE (operands
[0]) != REG
)
13769 if (GET_CODE (operands
[1]) != MEM
)
13772 /* Get the memory address. */
13773 addr
= XEXP (operands
[1], 0);
13775 /* Work out how the memory address is computed. */
13776 switch (GET_CODE (addr
))
13779 operands
[2] = gen_rtx_MEM (SImode
,
13780 plus_constant (XEXP (operands
[1], 0), 4));
13782 if (REGNO (operands
[0]) == REGNO (addr
))
13784 output_asm_insn ("ldr\t%H0, %2", operands
);
13785 output_asm_insn ("ldr\t%0, %1", operands
);
13789 output_asm_insn ("ldr\t%0, %1", operands
);
13790 output_asm_insn ("ldr\t%H0, %2", operands
);
13795 /* Compute <address> + 4 for the high order load. */
13796 operands
[2] = gen_rtx_MEM (SImode
,
13797 plus_constant (XEXP (operands
[1], 0), 4));
13799 output_asm_insn ("ldr\t%0, %1", operands
);
13800 output_asm_insn ("ldr\t%H0, %2", operands
);
13804 arg1
= XEXP (addr
, 0);
13805 arg2
= XEXP (addr
, 1);
13807 if (CONSTANT_P (arg1
))
13808 base
= arg2
, offset
= arg1
;
13810 base
= arg1
, offset
= arg2
;
13812 if (GET_CODE (base
) != REG
)
13815 /* Catch the case of <address> = <reg> + <reg> */
13816 if (GET_CODE (offset
) == REG
)
13818 int reg_offset
= REGNO (offset
);
13819 int reg_base
= REGNO (base
);
13820 int reg_dest
= REGNO (operands
[0]);
13822 /* Add the base and offset registers together into the
13823 higher destination register. */
13824 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
13825 reg_dest
+ 1, reg_base
, reg_offset
);
13827 /* Load the lower destination register from the address in
13828 the higher destination register. */
13829 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
13830 reg_dest
, reg_dest
+ 1);
13832 /* Load the higher destination register from its own address
13834 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
13835 reg_dest
+ 1, reg_dest
+ 1);
13839 /* Compute <address> + 4 for the high order load. */
13840 operands
[2] = gen_rtx_MEM (SImode
,
13841 plus_constant (XEXP (operands
[1], 0), 4));
13843 /* If the computed address is held in the low order register
13844 then load the high order register first, otherwise always
13845 load the low order register first. */
13846 if (REGNO (operands
[0]) == REGNO (base
))
13848 output_asm_insn ("ldr\t%H0, %2", operands
);
13849 output_asm_insn ("ldr\t%0, %1", operands
);
13853 output_asm_insn ("ldr\t%0, %1", operands
);
13854 output_asm_insn ("ldr\t%H0, %2", operands
);
13860 /* With no registers to worry about we can just load the value
13862 operands
[2] = gen_rtx_MEM (SImode
,
13863 plus_constant (XEXP (operands
[1], 0), 4));
13865 output_asm_insn ("ldr\t%H0, %2", operands
);
13866 output_asm_insn ("ldr\t%0, %1", operands
);
13878 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
13885 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13888 operands
[4] = operands
[5];
13891 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
13892 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
13896 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13899 operands
[4] = operands
[5];
13902 if (REGNO (operands
[5]) > REGNO (operands
[6]))
13905 operands
[5] = operands
[6];
13908 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13911 operands
[4] = operands
[5];
13915 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
13916 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
13926 /* Routines for generating rtl. */
13928 thumb_expand_movmemqi (rtx
*operands
)
13930 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
13931 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
13932 HOST_WIDE_INT len
= INTVAL (operands
[2]);
13933 HOST_WIDE_INT offset
= 0;
13937 emit_insn (gen_movmem12b (out
, in
, out
, in
));
13943 emit_insn (gen_movmem8b (out
, in
, out
, in
));
13949 rtx reg
= gen_reg_rtx (SImode
);
13950 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
13951 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
13958 rtx reg
= gen_reg_rtx (HImode
);
13959 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
13960 plus_constant (in
, offset
))));
13961 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
13969 rtx reg
= gen_reg_rtx (QImode
);
13970 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
13971 plus_constant (in
, offset
))));
13972 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
13978 thumb_cmp_operand (rtx op
, enum machine_mode mode
)
13980 return ((GET_CODE (op
) == CONST_INT
13981 && INTVAL (op
) < 256
13982 && INTVAL (op
) >= 0)
13983 || s_register_operand (op
, mode
));
13987 thumb_cmpneg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
13989 return (GET_CODE (op
) == CONST_INT
13991 && INTVAL (op
) > -256);
13994 /* Return TRUE if a result can be stored in OP without clobbering the
13995 condition code register. Prior to reload we only accept a
13996 register. After reload we have to be able to handle memory as
13997 well, since a pseudo may not get a hard reg and reload cannot
13998 handle output-reloads on jump insns.
14000 We could possibly handle mem before reload as well, but that might
14001 complicate things with the need to handle increment
14005 thumb_cbrch_target_operand (rtx op
, enum machine_mode mode
)
14007 return (s_register_operand (op
, mode
)
14008 || ((reload_in_progress
|| reload_completed
)
14009 && memory_operand (op
, mode
)));
14012 /* Handle storing a half-word to memory during reload. */
14014 thumb_reload_out_hi (rtx
*operands
)
14016 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14019 /* Handle reading a half-word from memory during reload. */
14021 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14026 /* Return the length of a function name prefix
14027 that starts with the character 'c'. */
14029 arm_get_strip_length (int c
)
14033 ARM_NAME_ENCODING_LENGTHS
14038 /* Return a pointer to a function's name with any
14039 and all prefix encodings stripped from it. */
14041 arm_strip_name_encoding (const char *name
)
14045 while ((skip
= arm_get_strip_length (* name
)))
14051 /* If there is a '*' anywhere in the name's prefix, then
14052 emit the stripped name verbatim, otherwise prepend an
14053 underscore if leading underscores are being used. */
14055 arm_asm_output_labelref (FILE *stream
, const char *name
)
14060 while ((skip
= arm_get_strip_length (* name
)))
14062 verbatim
|= (*name
== '*');
14067 fputs (name
, stream
);
14069 asm_fprintf (stream
, "%U%s", name
);
14074 #ifdef AOF_ASSEMBLER
14075 /* Special functions only needed when producing AOF syntax assembler. */
14079 struct pic_chain
* next
;
14080 const char * symname
;
14083 static struct pic_chain
* aof_pic_chain
= NULL
;
14086 aof_pic_entry (rtx x
)
14088 struct pic_chain
** chainp
;
14091 if (aof_pic_label
== NULL_RTX
)
14093 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14096 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14097 offset
+= 4, chainp
= &(*chainp
)->next
)
14098 if ((*chainp
)->symname
== XSTR (x
, 0))
14099 return plus_constant (aof_pic_label
, offset
);
14101 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14102 (*chainp
)->next
= NULL
;
14103 (*chainp
)->symname
= XSTR (x
, 0);
14104 return plus_constant (aof_pic_label
, offset
);
14108 aof_dump_pic_table (FILE *f
)
14110 struct pic_chain
* chain
;
14112 if (aof_pic_chain
== NULL
)
14115 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14116 PIC_OFFSET_TABLE_REGNUM
,
14117 PIC_OFFSET_TABLE_REGNUM
);
14118 fputs ("|x$adcons|\n", f
);
14120 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14122 fputs ("\tDCD\t", f
);
14123 assemble_name (f
, chain
->symname
);
14128 int arm_text_section_count
= 1;
14131 aof_text_section (void )
14133 static char buf
[100];
14134 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14135 arm_text_section_count
++);
14137 strcat (buf
, ", PIC, REENTRANT");
14141 static int arm_data_section_count
= 1;
14144 aof_data_section (void)
14146 static char buf
[100];
14147 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14151 /* The AOF assembler is religiously strict about declarations of
14152 imported and exported symbols, so that it is impossible to declare
14153 a function as imported near the beginning of the file, and then to
14154 export it later on. It is, however, possible to delay the decision
14155 until all the functions in the file have been compiled. To get
14156 around this, we maintain a list of the imports and exports, and
14157 delete from it any that are subsequently defined. At the end of
14158 compilation we spit the remainder of the list out before the END
14163 struct import
* next
;
14167 static struct import
* imports_list
= NULL
;
14170 aof_add_import (const char *name
)
14172 struct import
* new;
14174 for (new = imports_list
; new; new = new->next
)
14175 if (new->name
== name
)
14178 new = (struct import
*) xmalloc (sizeof (struct import
));
14179 new->next
= imports_list
;
14180 imports_list
= new;
14185 aof_delete_import (const char *name
)
14187 struct import
** old
;
14189 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14191 if ((*old
)->name
== name
)
14193 *old
= (*old
)->next
;
14199 int arm_main_function
= 0;
14202 aof_dump_imports (FILE *f
)
14204 /* The AOF assembler needs this to cause the startup code to be extracted
14205 from the library. Brining in __main causes the whole thing to work
14207 if (arm_main_function
)
14210 fputs ("\tIMPORT __main\n", f
);
14211 fputs ("\tDCD __main\n", f
);
14214 /* Now dump the remaining imports. */
14215 while (imports_list
)
14217 fprintf (f
, "\tIMPORT\t");
14218 assemble_name (f
, imports_list
->name
);
14220 imports_list
= imports_list
->next
;
14225 aof_globalize_label (FILE *stream
, const char *name
)
14227 default_globalize_label (stream
, name
);
14228 if (! strcmp (name
, "main"))
14229 arm_main_function
= 1;
14233 aof_file_start (void)
14235 fputs ("__r0\tRN\t0\n", asm_out_file
);
14236 fputs ("__a1\tRN\t0\n", asm_out_file
);
14237 fputs ("__a2\tRN\t1\n", asm_out_file
);
14238 fputs ("__a3\tRN\t2\n", asm_out_file
);
14239 fputs ("__a4\tRN\t3\n", asm_out_file
);
14240 fputs ("__v1\tRN\t4\n", asm_out_file
);
14241 fputs ("__v2\tRN\t5\n", asm_out_file
);
14242 fputs ("__v3\tRN\t6\n", asm_out_file
);
14243 fputs ("__v4\tRN\t7\n", asm_out_file
);
14244 fputs ("__v5\tRN\t8\n", asm_out_file
);
14245 fputs ("__v6\tRN\t9\n", asm_out_file
);
14246 fputs ("__sl\tRN\t10\n", asm_out_file
);
14247 fputs ("__fp\tRN\t11\n", asm_out_file
);
14248 fputs ("__ip\tRN\t12\n", asm_out_file
);
14249 fputs ("__sp\tRN\t13\n", asm_out_file
);
14250 fputs ("__lr\tRN\t14\n", asm_out_file
);
14251 fputs ("__pc\tRN\t15\n", asm_out_file
);
14252 fputs ("__f0\tFN\t0\n", asm_out_file
);
14253 fputs ("__f1\tFN\t1\n", asm_out_file
);
14254 fputs ("__f2\tFN\t2\n", asm_out_file
);
14255 fputs ("__f3\tFN\t3\n", asm_out_file
);
14256 fputs ("__f4\tFN\t4\n", asm_out_file
);
14257 fputs ("__f5\tFN\t5\n", asm_out_file
);
14258 fputs ("__f6\tFN\t6\n", asm_out_file
);
14259 fputs ("__f7\tFN\t7\n", asm_out_file
);
14264 aof_file_end (void)
14267 aof_dump_pic_table (asm_out_file
);
14268 aof_dump_imports (asm_out_file
);
14269 fputs ("\tEND\n", asm_out_file
);
14271 #endif /* AOF_ASSEMBLER */
14273 #ifdef OBJECT_FORMAT_ELF
14274 /* Switch to an arbitrary section NAME with attributes as specified
14275 by FLAGS. ALIGN specifies any known alignment requirements for
14276 the section; 0 if the default should be used.
14278 Differs from the default elf version only in the prefix character
14279 used before the section type. */
14282 arm_elf_asm_named_section (const char *name
, unsigned int flags
)
14284 char flagchars
[10], *f
= flagchars
;
14286 if (! named_section_first_declaration (name
))
14288 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
14292 if (!(flags
& SECTION_DEBUG
))
14294 if (flags
& SECTION_WRITE
)
14296 if (flags
& SECTION_CODE
)
14298 if (flags
& SECTION_SMALL
)
14300 if (flags
& SECTION_MERGE
)
14302 if (flags
& SECTION_STRINGS
)
14304 if (flags
& SECTION_TLS
)
14308 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
14310 if (!(flags
& SECTION_NOTYPE
))
14314 if (flags
& SECTION_BSS
)
14319 fprintf (asm_out_file
, ",%%%s", type
);
14321 if (flags
& SECTION_ENTSIZE
)
14322 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
14325 putc ('\n', asm_out_file
);
14330 /* Symbols in the text segment can be accessed without indirecting via the
14331 constant pool; it may take an extra binary operation, but this is still
14332 faster than indirecting via memory. Don't do this when not optimizing,
14333 since we won't be calculating al of the offsets necessary to do this
14337 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14339 /* This doesn't work with AOF syntax, since the string table may be in
14340 a different AREA. */
14341 #ifndef AOF_ASSEMBLER
14342 if (optimize
> 0 && TREE_CONSTANT (decl
))
14343 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14346 /* If we are referencing a function that is weak then encode a long call
14347 flag in the function name, otherwise if the function is static or
14348 or known to be defined in this file then encode a short call flag. */
14349 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
14351 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14352 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14353 else if (! TREE_PUBLIC (decl
))
14354 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14357 #endif /* !ARM_PE */
14360 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14362 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14363 && !strcmp (prefix
, "L"))
14365 arm_ccfsm_state
= 0;
14366 arm_target_insn
= NULL
;
14368 default_internal_label (stream
, prefix
, labelno
);
14371 /* Output code to add DELTA to the first argument, and then jump
14372 to FUNCTION. Used for C++ multiple inheritance. */
14374 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14375 HOST_WIDE_INT delta
,
14376 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14379 static int thunk_label
= 0;
14381 int mi_delta
= delta
;
14382 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14384 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14387 mi_delta
= - mi_delta
;
14390 int labelno
= thunk_label
++;
14391 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14392 fputs ("\tldr\tr12, ", file
);
14393 assemble_name (file
, label
);
14394 fputc ('\n', file
);
14396 while (mi_delta
!= 0)
14398 if ((mi_delta
& (3 << shift
)) == 0)
14402 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14403 mi_op
, this_regno
, this_regno
,
14404 mi_delta
& (0xff << shift
));
14405 mi_delta
&= ~(0xff << shift
);
14411 fprintf (file
, "\tbx\tr12\n");
14412 ASM_OUTPUT_ALIGN (file
, 2);
14413 assemble_name (file
, label
);
14414 fputs (":\n", file
);
14415 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14419 fputs ("\tb\t", file
);
14420 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14421 if (NEED_PLT_RELOC
)
14422 fputs ("(PLT)", file
);
14423 fputc ('\n', file
);
14428 arm_emit_vector_const (FILE *file
, rtx x
)
14431 const char * pattern
;
14433 if (GET_CODE (x
) != CONST_VECTOR
)
14436 switch (GET_MODE (x
))
14438 case V2SImode
: pattern
= "%08x"; break;
14439 case V4HImode
: pattern
= "%04x"; break;
14440 case V8QImode
: pattern
= "%02x"; break;
14444 fprintf (file
, "0x");
14445 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14449 element
= CONST_VECTOR_ELT (x
, i
);
14450 fprintf (file
, pattern
, INTVAL (element
));
14457 arm_output_load_gr (rtx
*operands
)
14464 if (GET_CODE (operands
[1]) != MEM
14465 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14466 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14467 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14468 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14469 return "wldrw%?\t%0, %1";
14471 /* Fix up an out-of-range load of a GR register. */
14472 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14473 wcgr
= operands
[0];
14475 output_asm_insn ("ldr%?\t%0, %1", operands
);
14477 operands
[0] = wcgr
;
14479 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14480 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14486 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14487 int incoming ATTRIBUTE_UNUSED
)
14490 /* FIXME: The ARM backend has special code to handle structure
14491 returns, and will reserve its own hidden first argument. So
14492 if this macro is enabled a *second* hidden argument will be
14493 reserved, which will break binary compatibility with old
14494 toolchains and also thunk handling. One day this should be
14498 /* Register in which address to store a structure value
14499 is passed to a function. */
14500 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14504 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14506 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14507 named arg and all anonymous args onto the stack.
14508 XXX I know the prologue shouldn't be pushing registers, but it is faster
14512 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14513 enum machine_mode mode ATTRIBUTE_UNUSED
,
14514 tree type ATTRIBUTE_UNUSED
,
14516 int second_time ATTRIBUTE_UNUSED
)
14518 cfun
->machine
->uses_anonymous_args
= 1;
14519 if (cum
->nregs
< NUM_ARG_REGS
)
14520 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14523 /* Return nonzero if the CONSUMER instruction (a store) does not need
14524 PRODUCER's value to calculate the address. */
14527 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14529 rtx value
= PATTERN (producer
);
14530 rtx addr
= PATTERN (consumer
);
14532 if (GET_CODE (value
) == COND_EXEC
)
14533 value
= COND_EXEC_CODE (value
);
14534 if (GET_CODE (value
) == PARALLEL
)
14535 value
= XVECEXP (value
, 0, 0);
14536 value
= XEXP (value
, 0);
14537 if (GET_CODE (addr
) == COND_EXEC
)
14538 addr
= COND_EXEC_CODE (addr
);
14539 if (GET_CODE (addr
) == PARALLEL
)
14540 addr
= XVECEXP (addr
, 0, 0);
14541 addr
= XEXP (addr
, 0);
14543 return !reg_overlap_mentioned_p (value
, addr
);
14546 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14547 have an early register shift value or amount dependency on the
14548 result of PRODUCER. */
14551 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14553 rtx value
= PATTERN (producer
);
14554 rtx op
= PATTERN (consumer
);
14557 if (GET_CODE (value
) == COND_EXEC
)
14558 value
= COND_EXEC_CODE (value
);
14559 if (GET_CODE (value
) == PARALLEL
)
14560 value
= XVECEXP (value
, 0, 0);
14561 value
= XEXP (value
, 0);
14562 if (GET_CODE (op
) == COND_EXEC
)
14563 op
= COND_EXEC_CODE (op
);
14564 if (GET_CODE (op
) == PARALLEL
)
14565 op
= XVECEXP (op
, 0, 0);
14568 early_op
= XEXP (op
, 0);
14569 /* This is either an actual independent shift, or a shift applied to
14570 the first operand of another operation. We want the whole shift
14572 if (GET_CODE (early_op
) == REG
)
14575 return !reg_overlap_mentioned_p (value
, early_op
);
14578 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14579 have an early register shift value dependency on the result of
14583 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14585 rtx value
= PATTERN (producer
);
14586 rtx op
= PATTERN (consumer
);
14589 if (GET_CODE (value
) == COND_EXEC
)
14590 value
= COND_EXEC_CODE (value
);
14591 if (GET_CODE (value
) == PARALLEL
)
14592 value
= XVECEXP (value
, 0, 0);
14593 value
= XEXP (value
, 0);
14594 if (GET_CODE (op
) == COND_EXEC
)
14595 op
= COND_EXEC_CODE (op
);
14596 if (GET_CODE (op
) == PARALLEL
)
14597 op
= XVECEXP (op
, 0, 0);
14600 early_op
= XEXP (op
, 0);
14602 /* This is either an actual independent shift, or a shift applied to
14603 the first operand of another operation. We want the value being
14604 shifted, in either case. */
14605 if (GET_CODE (early_op
) != REG
)
14606 early_op
= XEXP (early_op
, 0);
14608 return !reg_overlap_mentioned_p (value
, early_op
);
14611 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14612 have an early register mult dependency on the result of
14616 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14618 rtx value
= PATTERN (producer
);
14619 rtx op
= PATTERN (consumer
);
14621 if (GET_CODE (value
) == COND_EXEC
)
14622 value
= COND_EXEC_CODE (value
);
14623 if (GET_CODE (value
) == PARALLEL
)
14624 value
= XVECEXP (value
, 0, 0);
14625 value
= XEXP (value
, 0);
14626 if (GET_CODE (op
) == COND_EXEC
)
14627 op
= COND_EXEC_CODE (op
);
14628 if (GET_CODE (op
) == PARALLEL
)
14629 op
= XVECEXP (op
, 0, 0);
14632 return (GET_CODE (op
) == PLUS
14633 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14637 /* We can't rely on the caller doing the proper promotion when
14638 using APCS or ATPCS. */
14641 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14643 return !TARGET_AAPCS_BASED
;
14647 /* AAPCS based ABIs use short enums by default. */
14650 arm_default_short_enums (void)
14652 return TARGET_AAPCS_BASED
;
14656 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14659 arm_align_anon_bitfield (void)
14661 return TARGET_AAPCS_BASED
;
14665 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14668 arm_cxx_guard_type (void)
14670 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14674 /* The EABI says test the least significan bit of a guard variable. */
14677 arm_cxx_guard_mask_bit (void)
14679 return TARGET_AAPCS_BASED
;
14683 /* The EABI specifies that all array cookies are 8 bytes long. */
14686 arm_get_cookie_size (tree type
)
14690 if (!TARGET_AAPCS_BASED
)
14691 return default_cxx_get_cookie_size (type
);
14693 size
= build_int_cst (sizetype
, 8, 0);
14698 /* The EABI says that array cookies should also contain the element size. */
14701 arm_cookie_has_size (void)
14703 return TARGET_AAPCS_BASED
;
14707 /* The EABI says constructors and destructors should return a pointer to
14708 the object constructed/destroyed. */
14711 arm_cxx_cdtor_returns_this (void)
14713 return TARGET_AAPCS_BASED
;
14718 arm_set_return_address (rtx source
, rtx scratch
)
14720 arm_stack_offsets
*offsets
;
14721 HOST_WIDE_INT delta
;
14723 unsigned long saved_regs
;
14725 saved_regs
= arm_compute_save_reg_mask ();
14727 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14728 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14731 if (frame_pointer_needed
)
14732 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
14735 /* LR will be the first saved register. */
14736 offsets
= arm_get_frame_offsets ();
14737 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
14742 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
14743 GEN_INT (delta
& ~4095)));
14748 addr
= stack_pointer_rtx
;
14750 addr
= plus_constant (addr
, delta
);
14752 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14758 thumb_set_return_address (rtx source
, rtx scratch
)
14760 arm_stack_offsets
*offsets
;
14761 HOST_WIDE_INT delta
;
14764 unsigned long mask
;
14766 emit_insn (gen_rtx_USE (VOIDmode
, source
));
14768 mask
= thumb_compute_save_reg_mask ();
14769 if (mask
& (1 << LR_REGNUM
))
14771 offsets
= arm_get_frame_offsets ();
14773 /* Find the saved regs. */
14774 if (frame_pointer_needed
)
14776 delta
= offsets
->soft_frame
- offsets
->saved_args
;
14777 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
14781 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
14784 /* Allow for the stack frame. */
14785 if (TARGET_BACKTRACE
)
14787 /* The link register is always the first saved register. */
14790 /* Construct the address. */
14791 addr
= gen_rtx_REG (SImode
, reg
);
14792 if ((reg
!= SP_REGNUM
&& delta
>= 128)
14795 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
14796 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
14800 addr
= plus_constant (addr
, delta
);
14802 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14805 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);