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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
89 #ifndef CHECK_STACK_LIMIT
90 #define CHECK_STACK_LIMIT (-1)
91 #endif
93 /* Return index of given mode in mult and division cost tables. */
94 #define MODE_INDEX(mode) \
95 ((mode) == QImode ? 0 \
96 : (mode) == HImode ? 1 \
97 : (mode) == SImode ? 2 \
98 : (mode) == DImode ? 3 \
99 : 4)
101 /* Processor costs (relative to an add) */
102 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
103 #define COSTS_N_BYTES(N) ((N) * 2)
105 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
114 const
137 in QImode, HImode and SImode.
138 Relative to reg-reg move (2). */
142 in SFmode, DFmode and XFmode */
144 in SFmode, DFmode and XFmode */
147 in SImode and DImode */
149 in SImode and DImode */
152 in SImode, DImode and TImode */
154 in SImode, DImode and TImode */
167 ix86_size_memcpy,
168 ix86_size_memset,
180 };
182 /* Processor costs (relative to an add) */
185 DUMMY_STRINGOP_ALGS};
188 DUMMY_STRINGOP_ALGS};
190 static const
213 in QImode, HImode and SImode.
214 Relative to reg-reg move (2). */
218 in SFmode, DFmode and XFmode */
220 in SFmode, DFmode and XFmode */
223 in SImode and DImode */
225 in SImode and DImode */
228 in SImode, DImode and TImode */
230 in SImode, DImode and TImode */
243 i386_memcpy,
244 i386_memset,
256 };
260 DUMMY_STRINGOP_ALGS};
263 DUMMY_STRINGOP_ALGS};
265 static const
288 in QImode, HImode and SImode.
289 Relative to reg-reg move (2). */
293 in SFmode, DFmode and XFmode */
295 in SFmode, DFmode and XFmode */
298 in SImode and DImode */
300 in SImode and DImode */
303 in SImode, DImode and TImode */
305 in SImode, DImode and TImode */
308 shared for code and data, so 4kB is
309 not really precise. */
320 i486_memcpy,
321 i486_memset,
333 };
337 DUMMY_STRINGOP_ALGS};
340 DUMMY_STRINGOP_ALGS};
342 static const
365 in QImode, HImode and SImode.
366 Relative to reg-reg move (2). */
370 in SFmode, DFmode and XFmode */
372 in SFmode, DFmode and XFmode */
375 in SImode and DImode */
377 in SImode and DImode */
380 in SImode, DImode and TImode */
382 in SImode, DImode and TImode */
395 pentium_memcpy,
396 pentium_memset,
408 };
410 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
411 (we ensure the alignment). For small blocks inline loop is still a
412 noticeable win, for bigger blocks either rep movsl or rep movsb is
413 way to go. Rep movsb has apparently more expensive startup time in CPU,
414 but after 4K the difference is down in the noise. */
419 DUMMY_STRINGOP_ALGS};
424 DUMMY_STRINGOP_ALGS};
425 static const
448 in QImode, HImode and SImode.
449 Relative to reg-reg move (2). */
453 in SFmode, DFmode and XFmode */
455 in SFmode, DFmode and XFmode */
458 in SImode and DImode */
460 in SImode and DImode */
463 in SImode, DImode and TImode */
465 in SImode, DImode and TImode */
478 pentiumpro_memcpy,
479 pentiumpro_memset,
491 };
495 DUMMY_STRINGOP_ALGS};
498 DUMMY_STRINGOP_ALGS};
499 static const
522 in QImode, HImode and SImode.
523 Relative to reg-reg move (2). */
527 in SFmode, DFmode and XFmode */
529 in SFmode, DFmode and XFmode */
533 in SImode and DImode */
535 in SImode and DImode */
538 in SImode, DImode and TImode */
540 in SImode, DImode and TImode */
553 geode_memcpy,
554 geode_memset,
566 };
570 DUMMY_STRINGOP_ALGS};
573 DUMMY_STRINGOP_ALGS};
574 static const
597 in QImode, HImode and SImode.
598 Relative to reg-reg move (2). */
602 in SFmode, DFmode and XFmode */
604 in SFmode, DFmode and XFmode */
607 in SImode and DImode */
609 in SImode and DImode */
612 in SImode, DImode and TImode */
614 in SImode, DImode and TImode */
618 have integrated l2 cache, but
619 optimizing for k6 is not important
620 enough to worry about that. */
630 k6_memcpy,
631 k6_memset,
643 };
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
650 DUMMY_STRINGOP_ALGS};
653 DUMMY_STRINGOP_ALGS};
654 static const
677 in QImode, HImode and SImode.
678 Relative to reg-reg move (2). */
682 in SFmode, DFmode and XFmode */
684 in SFmode, DFmode and XFmode */
687 in SImode and DImode */
689 in SImode and DImode */
692 in SImode, DImode and TImode */
694 in SImode, DImode and TImode */
707 athlon_memcpy,
708 athlon_memset,
720 };
722 /* K8 has optimized REP instruction for medium sized blocks, but for very
723 small blocks it is better to use loop. For large blocks, libcall can
724 do nontemporary accesses and beat inline considerably. */
735 static const
758 in QImode, HImode and SImode.
759 Relative to reg-reg move (2). */
763 in SFmode, DFmode and XFmode */
765 in SFmode, DFmode and XFmode */
768 in SImode and DImode */
770 in SImode and DImode */
773 in SImode, DImode and TImode */
775 in SImode, DImode and TImode */
780 /* New AMD processors never drop prefetches; if they cannot be performed
781 immediately, they are queued. We set number of simultaneous prefetches
782 to a large constant to reflect this (it probably is not a good idea not
783 to limit number of prefetches at all, as their execution also takes some
784 time). */
794 k8_memcpy,
795 k8_memset,
807 };
809 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
810 very small blocks it is better to use loop. For large blocks, libcall can
811 do nontemporary accesses and beat inline considerably. */
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
849 in SFmode, DFmode and XFmode */
851 in SFmode, DFmode and XFmode */
854 in SImode and DImode */
856 in SImode and DImode */
859 in SImode, DImode and TImode */
861 in SImode, DImode and TImode */
863 /* On K8:
864 MOVD reg64, xmmreg Double FSTORE 4
865 MOVD reg32, xmmreg Double FSTORE 4
866 On AMDFAM10:
867 MOVD reg64, xmmreg Double FADD 3
868 1/1 1/1
869 MOVD reg32, xmmreg Double FADD 3
870 1/1 1/1 */
874 /* New AMD processors never drop prefetches; if they cannot be performed
875 immediately, they are queued. We set number of simultaneous prefetches
876 to a large constant to reflect this (it probably is not a good idea not
877 to limit number of prefetches at all, as their execution also takes some
878 time). */
888 amdfam10_memcpy,
889 amdfam10_memset,
901 };
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
939 in QImode, HImode and SImode.
940 Relative to reg-reg move (2). */
944 in SFmode, DFmode and XFmode */
946 in SFmode, DFmode and XFmode */
949 in SImode and DImode */
951 in SImode and DImode */
954 in SImode, DImode and TImode */
956 in SImode, DImode and TImode */
958 /* On K8:
959 MOVD reg64, xmmreg Double FSTORE 4
960 MOVD reg32, xmmreg Double FSTORE 4
961 On AMDFAM10:
962 MOVD reg64, xmmreg Double FADD 3
963 1/1 1/1
964 MOVD reg32, xmmreg Double FADD 3
965 1/1 1/1 */
969 /* New AMD processors never drop prefetches; if they cannot be performed
970 immediately, they are queued. We set number of simultaneous prefetches
971 to a large constant to reflect this (it probably is not a good idea not
972 to limit number of prefetches at all, as their execution also takes some
973 time). */
983 bdver1_memcpy,
984 bdver1_memset,
996 };
998 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
999 very small blocks it is better to use loop. For large blocks, libcall
1000 can do nontemporary accesses and beat inline considerably. */
1035 in QImode, HImode and SImode.
1036 Relative to reg-reg move (2). */
1040 in SFmode, DFmode and XFmode */
1042 in SFmode, DFmode and XFmode */
1045 in SImode and DImode */
1047 in SImode and DImode */
1050 in SImode, DImode and TImode */
1052 in SImode, DImode and TImode */
1054 /* On K8:
1055 MOVD reg64, xmmreg Double FSTORE 4
1056 MOVD reg32, xmmreg Double FSTORE 4
1057 On AMDFAM10:
1058 MOVD reg64, xmmreg Double FADD 3
1059 1/1 1/1
1060 MOVD reg32, xmmreg Double FADD 3
1061 1/1 1/1 */
1065 /* New AMD processors never drop prefetches; if they cannot be performed
1066 immediately, they are queued. We set number of simultaneous prefetches
1067 to a large constant to reflect this (it probably is not a good idea not
1068 to limit number of prefetches at all, as their execution also takes some
1069 time). */
1079 bdver2_memcpy,
1080 bdver2_memset,
1092 };
1095 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1096 very small blocks it is better to use loop. For large blocks, libcall
1097 can do nontemporary accesses and beat inline considerably. */
1130 in QImode, HImode and SImode.
1131 Relative to reg-reg move (2). */
1135 in SFmode, DFmode and XFmode */
1137 in SFmode, DFmode and XFmode */
1140 in SImode and DImode */
1142 in SImode and DImode */
1145 in SImode, DImode and TImode */
1147 in SImode, DImode and TImode */
1152 /* New AMD processors never drop prefetches; if they cannot be performed
1153 immediately, they are queued. We set number of simultaneous prefetches
1154 to a large constant to reflect this (it probably is not a good idea not
1155 to limit number of prefetches at all, as their execution also takes some
1156 time). */
1166 bdver3_memcpy,
1167 bdver3_memset,
1179 };
1181 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1182 very small blocks it is better to use loop. For large blocks, libcall
1183 can do nontemporary accesses and beat inline considerably. */
1216 in QImode, HImode and SImode.
1217 Relative to reg-reg move (2). */
1221 in SFmode, DFmode and XFmode */
1223 in SFmode, DFmode and XFmode */
1226 in SImode and DImode */
1228 in SImode and DImode */
1231 in SImode, DImode and TImode */
1233 in SImode, DImode and TImode */
1238 /* New AMD processors never drop prefetches; if they cannot be performed
1239 immediately, they are queued. We set number of simultaneous prefetches
1240 to a large constant to reflect this (it probably is not a good idea not
1241 to limit number of prefetches at all, as their execution also takes some
1242 time). */
1252 bdver4_memcpy,
1253 bdver4_memset,
1265 };
1267 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1268 very small blocks it is better to use loop. For large blocks, libcall can
1269 do nontemporary accesses and beat inline considerably. */
1302 in QImode, HImode and SImode.
1303 Relative to reg-reg move (2). */
1307 in SFmode, DFmode and XFmode */
1309 in SFmode, DFmode and XFmode */
1312 in SImode and DImode */
1314 in SImode and DImode */
1317 in SImode, DImode and TImode */
1319 in SImode, DImode and TImode */
1321 /* On K8:
1322 MOVD reg64, xmmreg Double FSTORE 4
1323 MOVD reg32, xmmreg Double FSTORE 4
1324 On AMDFAM10:
1325 MOVD reg64, xmmreg Double FADD 3
1326 1/1 1/1
1327 MOVD reg32, xmmreg Double FADD 3
1328 1/1 1/1 */
1341 btver1_memcpy,
1342 btver1_memset,
1354 };
1388 in QImode, HImode and SImode.
1389 Relative to reg-reg move (2). */
1393 in SFmode, DFmode and XFmode */
1395 in SFmode, DFmode and XFmode */
1398 in SImode and DImode */
1400 in SImode and DImode */
1403 in SImode, DImode and TImode */
1405 in SImode, DImode and TImode */
1407 /* On K8:
1408 MOVD reg64, xmmreg Double FSTORE 4
1409 MOVD reg32, xmmreg Double FSTORE 4
1410 On AMDFAM10:
1411 MOVD reg64, xmmreg Double FADD 3
1412 1/1 1/1
1413 MOVD reg32, xmmreg Double FADD 3
1414 1/1 1/1 */
1426 btver2_memcpy,
1427 btver2_memset,
1439 };
1443 DUMMY_STRINGOP_ALGS};
1447 DUMMY_STRINGOP_ALGS};
1449 static const
1472 in QImode, HImode and SImode.
1473 Relative to reg-reg move (2). */
1477 in SFmode, DFmode and XFmode */
1479 in SFmode, DFmode and XFmode */
1482 in SImode and DImode */
1484 in SImode and DImode */
1487 in SImode, DImode and TImode */
1489 in SImode, DImode and TImode */
1502 pentium4_memcpy,
1503 pentium4_memset,
1515 };
1528 static const
1551 in QImode, HImode and SImode.
1552 Relative to reg-reg move (2). */
1556 in SFmode, DFmode and XFmode */
1558 in SFmode, DFmode and XFmode */
1561 in SImode and DImode */
1563 in SImode and DImode */
1566 in SImode, DImode and TImode */
1568 in SImode, DImode and TImode */
1581 nocona_memcpy,
1582 nocona_memset,
1594 };
1605 static const
1628 in QImode, HImode and SImode.
1629 Relative to reg-reg move (2). */
1633 in SFmode, DFmode and XFmode */
1635 in SFmode, DFmode and XFmode */
1638 in SImode and DImode */
1640 in SImode and DImode */
1643 in SImode, DImode and TImode */
1645 in SImode, DImode and TImode */
1658 atom_memcpy,
1659 atom_memset,
1671 };
1682 static const
1705 in QImode, HImode and SImode.
1706 Relative to reg-reg move (2). */
1710 in SFmode, DFmode and XFmode */
1712 in SFmode, DFmode and XFmode */
1715 in SImode and DImode */
1717 in SImode and DImode */
1720 in SImode, DImode and TImode */
1722 in SImode, DImode and TImode */
1735 slm_memcpy,
1736 slm_memset,
1748 };
1759 static const
1782 in QImode, HImode and SImode.
1783 Relative to reg-reg move (2). */
1787 in SFmode, DFmode and XFmode */
1789 in SFmode, DFmode and XFmode */
1792 in SImode and DImode */
1794 in SImode and DImode */
1797 in SImode, DImode and TImode */
1799 in SImode, DImode and TImode */
1812 intel_memcpy,
1813 intel_memset,
1825 };
1827 /* Generic should produce code tuned for Core-i7 (and newer chips)
1828 and btver1 (and newer chips). */
1840 static const
1843 /* On all chips taken into consideration lea is 2 cycles and more. With
1844 this cost however our current implementation of synth_mult results in
1845 use of unnecessary temporary registers causing regression on several
1846 SPECfp benchmarks. */
1867 in QImode, HImode and SImode.
1868 Relative to reg-reg move (2). */
1872 in SFmode, DFmode and XFmode */
1874 in SFmode, DFmode and XFmode */
1877 in SImode and DImode */
1879 in SImode and DImode */
1882 in SImode, DImode and TImode */
1884 in SImode, DImode and TImode */
1890 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1891 value is increased to perhaps more appropriate value of 5. */
1899 generic_memcpy,
1900 generic_memset,
1912 };
1914 /* core_cost should produce code tuned for Core familly of CPUs. */
1927 static const
1930 /* On all chips taken into consideration lea is 2 cycles and more. With
1931 this cost however our current implementation of synth_mult results in
1932 use of unnecessary temporary registers causing regression on several
1933 SPECfp benchmarks. */
1954 in QImode, HImode and SImode.
1955 Relative to reg-reg move (2). */
1959 in SFmode, DFmode and XFmode */
1961 in SFmode, DFmode and XFmode */
1964 in SImode and DImode */
1966 in SImode and DImode */
1969 in SImode, DImode and TImode */
1971 in SImode, DImode and TImode */
1977 /* FIXME perhaps more appropriate value is 5. */
1985 core_memcpy,
1986 core_memset,
1998 };
2001 /* Set by -mtune. */
2004 /* Set by -mtune or -Os. */
2007 /* Processor feature/optimization bitmasks. */
2008 #define m_386 (1<<PROCESSOR_I386)
2009 #define m_486 (1<<PROCESSOR_I486)
2010 #define m_PENT (1<<PROCESSOR_PENTIUM)
2011 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2012 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2013 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2014 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2015 #define m_CORE2 (1<<PROCESSOR_CORE2)
2016 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2017 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2018 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2019 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2020 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2021 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2022 #define m_INTEL (1<<PROCESSOR_INTEL)
2024 #define m_GEODE (1<<PROCESSOR_GEODE)
2025 #define m_K6 (1<<PROCESSOR_K6)
2026 #define m_K6_GEODE (m_K6 | m_GEODE)
2027 #define m_K8 (1<<PROCESSOR_K8)
2028 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2029 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2030 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2031 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2032 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2033 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2034 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2035 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2036 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2037 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2038 #define m_BTVER (m_BTVER1 | m_BTVER2)
2039 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2041 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2044 #undef DEF_TUNE
2045 #define DEF_TUNE(tune, name, selector) name,
2047 #undef DEF_TUNE
2048 };
2050 /* Feature tests against the various tunings. */
2053 /* Feature tests against the various tunings used to create ix86_tune_features
2054 based on the processor mask. */
2056 #undef DEF_TUNE
2057 #define DEF_TUNE(tune, name, selector) selector,
2059 #undef DEF_TUNE
2060 };
2062 /* Feature tests against the various architecture variations. */
2065 /* Feature tests against the various architecture variations, used to create
2066 ix86_arch_features based on the processor mask. */
2068 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2071 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2074 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2077 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2080 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2082 };
2084 /* In case the average insn count for single function invocation is
2085 lower than this constant, emit fast (but longer) prologue and
2086 epilogue code. */
2087 #define FAST_PROLOGUE_INSN_COUNT 20
2089 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2094 /* Array of the smallest class containing reg number REGNO, indexed by
2095 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2098 {
2099 /* ax, dx, cx, bx */
2101 /* si, di, bp, sp */
2103 /* FP registers */
2106 /* arg pointer */
2107 NON_Q_REGS,
2108 /* flags, fpsr, fpcr, frame */
2110 /* SSE registers */
2113 /* MMX registers */
2116 /* REX registers */
2119 /* SSE REX registers */
2122 /* AVX-512 SSE registers */
2127 /* Mask registers. */
2130 };
2132 /* The "default" register map used in 32bit mode. */
2135 {
2146 };
2148 /* The "default" register map used in 64bit mode. */
2151 {
2162 };
2164 /* Define the register numbers to be used in Dwarf debugging information.
2165 The SVR4 reference port C compiler uses the following register numbers
2166 in its Dwarf output code:
2167 0 for %eax (gcc regno = 0)
2168 1 for %ecx (gcc regno = 2)
2169 2 for %edx (gcc regno = 1)
2170 3 for %ebx (gcc regno = 3)
2171 4 for %esp (gcc regno = 7)
2172 5 for %ebp (gcc regno = 6)
2173 6 for %esi (gcc regno = 4)
2174 7 for %edi (gcc regno = 5)
2175 The following three DWARF register numbers are never generated by
2176 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2177 believes these numbers have these meanings.
2178 8 for %eip (no gcc equivalent)
2179 9 for %eflags (gcc regno = 17)
2180 10 for %trapno (no gcc equivalent)
2181 It is not at all clear how we should number the FP stack registers
2182 for the x86 architecture. If the version of SDB on x86/svr4 were
2183 a bit less brain dead with respect to floating-point then we would
2184 have a precedent to follow with respect to DWARF register numbers
2185 for x86 FP registers, but the SDB on x86/svr4 is so completely
2186 broken with respect to FP registers that it is hardly worth thinking
2187 of it as something to strive for compatibility with.
2188 The version of x86/svr4 SDB I have at the moment does (partially)
2189 seem to believe that DWARF register number 11 is associated with
2190 the x86 register %st(0), but that's about all. Higher DWARF
2191 register numbers don't seem to be associated with anything in
2192 particular, and even for DWARF regno 11, SDB only seems to under-
2193 stand that it should say that a variable lives in %st(0) (when
2194 asked via an `=' command) if we said it was in DWARF regno 11,
2195 but SDB still prints garbage when asked for the value of the
2196 variable in question (via a `/' command).
2197 (Also note that the labels SDB prints for various FP stack regs
2198 when doing an `x' command are all wrong.)
2199 Note that these problems generally don't affect the native SVR4
2200 C compiler because it doesn't allow the use of -O with -g and
2201 because when it is *not* optimizing, it allocates a memory
2202 location for each floating-point variable, and the memory
2203 location is what gets described in the DWARF AT_location
2204 attribute for the variable in question.
2205 Regardless of the severe mental illness of the x86/svr4 SDB, we
2206 do something sensible here and we use the following DWARF
2207 register numbers. Note that these are all stack-top-relative
2208 numbers.
2209 11 for %st(0) (gcc regno = 8)
2210 12 for %st(1) (gcc regno = 9)
2211 13 for %st(2) (gcc regno = 10)
2212 14 for %st(3) (gcc regno = 11)
2213 15 for %st(4) (gcc regno = 12)
2214 16 for %st(5) (gcc regno = 13)
2215 17 for %st(6) (gcc regno = 14)
2216 18 for %st(7) (gcc regno = 15)
2217 */
2219 {
2230 };
2232 /* Define parameter passing and return registers. */
2235 {
2237 };
2240 {
2242 };
2245 {
2247 };
2249 /* Additional registers that are clobbered by SYSV calls. */
2252 {
2257 };
2259 /* Define the structure for the machine field in struct function. */
2264 rtx rtl;
2266 };
2268 /* Structure describing stack frame layout.
2269 Stack grows downward:
2271 [arguments]
2272 <- ARG_POINTER
2273 saved pc
2275 saved static chain if ix86_static_chain_on_stack
2277 saved frame pointer if frame_pointer_needed
2278 <- HARD_FRAME_POINTER
2279 [saved regs]
2280 <- regs_save_offset
2281 [padding0]
2283 [saved SSE regs]
2284 <- sse_regs_save_offset
2285 [padding1] |
2286 | <- FRAME_POINTER
2287 [va_arg registers] |
2288 |
2289 [frame] |
2290 |
2291 [padding2] | = to_allocate
2292 <- STACK_POINTER
2293 */
2294 struct ix86_frame
2295 {
2302 /* The offsets relative to ARG_POINTER. */
2303 HOST_WIDE_INT frame_pointer_offset;
2304 HOST_WIDE_INT hard_frame_pointer_offset;
2305 HOST_WIDE_INT stack_pointer_offset;
2306 HOST_WIDE_INT hfp_save_offset;
2307 HOST_WIDE_INT reg_save_offset;
2308 HOST_WIDE_INT sse_reg_save_offset;
2310 /* When save_regs_using_mov is set, emit prologue using
2311 move instead of push instructions. */
2313 };
2315 /* Which cpu are we scheduling for. */
2318 /* Which cpu are we optimizing for. */
2321 /* Which instruction set architecture to use. */
2324 /* True if processor has SSE prefetch instruction. */
2327 /* -mstackrealign option */
2344 /* Preferred alignment for stack boundary in bits. */
2347 /* Alignment for incoming stack boundary in bits specified at
2348 command line. */
2351 /* Default alignment for incoming stack boundary in bits. */
2354 /* Alignment for incoming stack boundary in bits. */
2357 /* Calling abi specific va_list type nodes. */
2361 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2365 /* Fence to use after loop using movnt. */
2366 tree x86_mfence;
2368 /* Register class used for passing given 64bit part of the argument.
2369 These represent classes as documented by the PS ABI, with the exception
2370 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2371 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2373 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2374 whenever possible (upper half does contain padding). */
2375 enum x86_64_reg_class
2376 {
2377 X86_64_NO_CLASS,
2378 X86_64_INTEGER_CLASS,
2379 X86_64_INTEGERSI_CLASS,
2380 X86_64_SSE_CLASS,
2381 X86_64_SSESF_CLASS,
2382 X86_64_SSEDF_CLASS,
2383 X86_64_SSEUP_CLASS,
2384 X86_64_X87_CLASS,
2385 X86_64_X87UP_CLASS,
2386 X86_64_COMPLEX_X87_CLASS,
2387 X86_64_MEMORY_CLASS
2388 };
2390 #define MAX_CLASSES 8
2392 /* Table of constants used by fldpi, fldln2, etc.... */
2396 \f
2401 const_tree);
2413 enum ix86_function_specific_strings
2414 {
2415 IX86_FUNCTION_SPECIFIC_ARCH,
2416 IX86_FUNCTION_SPECIFIC_TUNE,
2417 IX86_FUNCTION_SPECIFIC_MAX
2418 };
2439 \f
2440 #ifndef SUBTARGET32_DEFAULT_CPU
2442 #endif
2444 /* Whether -mtune= or -march= were specified */
2448 /* Vectorization library interface and handlers. */
2454 /* Processor target table, indexed by processor number */
2455 struct ptt
2456 {
2464 };
2466 /* This table must be in sync with enum processor_type in i386.h. */
2468 {
2494 };
2495 \f
2496 static bool
2498 {
2500 }
2502 static unsigned int
2504 {
2507 /* vzeroupper instructions are inserted immediately after reload to
2508 account for possible spills from 256bit registers. The pass
2509 reuses mode switching infrastructure by re-running mode insertion
2510 pass, so disable entities that have already been processed. */
2516 /* Call optimize_mode_switching. */
2519 }
2524 {
2536 };
2539 {
2543 {}
2545 /* opt_pass methods: */
2553 rtl_opt_pass *
2555 {
2557 }
2559 /* Return true if a red-zone is in use. */
2563 {
2565 }
2566 \f
2567 /* Return a string that documents the current -m options. The caller is
2568 responsible for freeing the string. */
2574 {
2575 struct ix86_target_opts
2576 {
2579 };
2581 /* This table is ordered so that options like -msse4.2 that imply
2582 preceding options while match those first. */
2584 {
2626 };
2628 /* Flag options. */
2630 {
2659 };
2676 /* Add -march= option. */
2678 {
2681 }
2683 /* Add -mtune= option. */
2685 {
2688 }
2690 /* Add -m32/-m64/-mx32. */
2692 {
2695 else
2697 isa &= ~ (OPTION_MASK_ISA_64BIT
2698 | OPTION_MASK_ABI_64
2700 }
2701 else
2705 /* Pick out the options in isa options. */
2707 {
2709 {
2712 }
2713 }
2716 {
2719 isa);
2720 }
2722 /* Add flag options. */
2724 {
2726 {
2729 }
2730 }
2733 {
2736 }
2738 /* Add -fpmath= option. */
2740 {
2743 {
2758 }
2759 }
2761 /* Any options? */
2767 /* Size the string. */
2771 {
2776 }
2778 /* Build the string. */
2783 {
2790 {
2792 line_len++;
2795 {
2799 }
2800 }
2804 {
2808 }
2809 }
2815 }
2817 /* Return true, if profiling code should be emitted before
2818 prologue. Otherwise it returns false.
2819 Note: For x86 with "hotfix" it is sorried. */
2820 static bool
2822 {
2824 }
2826 /* Function that is callable from the debugger to print the current
2827 options. */
2828 void ATTRIBUTE_UNUSED
2830 {
2836 {
2839 }
2840 else
2844 }
2847 #define DEF_ENUM
2848 #define DEF_ALG(alg, name) #name,
2850 #undef DEF_ENUM
2851 #undef DEF_ALG
2852 };
2854 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2855 The string is of the following form (or comma separated list of it):
2857 strategy_alg:max_size:[align|noalign]
2859 where the full size range for the strategy is either [0, max_size] or
2860 [min_size, max_size], in which min_size is the max_size + 1 of the
2861 preceding range. The last size range must have max_size == -1.
2863 Examples:
2865 1.
2866 -mmemcpy-strategy=libcall:-1:noalign
2868 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2871 2.
2872 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2874 This is to tell the compiler to use the following strategy for memset
2875 1) when the expected size is between [1, 16], use rep_8byte strategy;
2876 2) when the size is between [17, 2048], use vector_loop;
2877 3) when the size is > 2048, use libcall. */
2879 struct stringop_size_range
2880 {
2882 stringop_alg alg;
2884 };
2886 static void
2888 {
2896 else
2901 do
2902 {
2912 {
2916 }
2919 {
2923 }
2930 {
2932 alg_name,
2935 }
2943 else
2944 {
2948 }
2949 n++;
2951 }
2955 {
2960 }
2963 {
2967 }
2969 /* Now override the default algs array. */
2971 {
2977 }
2978 }
2980 \f
2981 /* parse -mtune-ctrl= option. When DUMP is true,
2982 print the features that are explicitly set. */
2984 static void
2986 {
2994 do
2995 {
3002 {
3003 curr_feature_string++;
3005 }
3007 {
3009 {
3015 }
3016 }
3021 }
3024 }
3026 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3027 processor type. */
3029 static void
3031 {
3036 {
3039 else
3041 }
3044 {
3049 }
3052 }
3055 /* Override various settings based on options. If MAIN_ARGS_P, the
3056 options are from the command line, otherwise they are from
3057 attributes. */
3059 static void
3063 {
3071 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3072 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3073 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3074 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3075 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3076 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3077 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3078 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3079 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3080 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3081 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3082 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3083 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3084 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3085 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3086 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3087 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3088 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3089 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3090 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3091 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3092 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3093 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3094 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3095 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3096 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3097 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3098 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3099 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3100 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3101 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3102 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3103 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3104 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3105 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3106 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3107 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3108 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3109 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3110 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3111 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3112 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3113 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3114 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3115 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3116 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3118 #define PTA_CORE2 \
3119 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3120 | PTA_CX16 | PTA_FXSR)
3121 #define PTA_NEHALEM \
3122 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3123 #define PTA_WESTMERE \
3124 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3125 #define PTA_SANDYBRIDGE \
3126 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3127 #define PTA_IVYBRIDGE \
3128 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3129 #define PTA_HASWELL \
3130 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3131 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE)
3132 #define PTA_BROADWELL \
3133 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3134 #define PTA_BONNELL \
3135 (PTA_CORE2 | PTA_MOVBE)
3136 #define PTA_SILVERMONT \
3137 (PTA_WESTMERE | PTA_MOVBE)
3139 /* if this reaches 64, need to widen struct pta flags below */
3141 static struct pta
3142 {
3147 }
3149 {
3183 PTA_SANDYBRIDGE},
3185 PTA_SANDYBRIDGE},
3187 PTA_IVYBRIDGE},
3189 PTA_IVYBRIDGE},
3279 PTA_64BIT
3281 };
3283 /* -mrecip options. */
3284 static struct
3285 {
3288 }
3290 {
3297 };
3301 /* Set up prefix/suffix so the error messages refer to either the command
3302 line argument, or the attribute(target). */
3304 {
3308 }
3309 else
3310 {
3314 }
3316 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3317 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3320 #ifdef TARGET_BI_ARCH
3321 else
3322 {
3323 #if TARGET_BI_ARCH == 1
3324 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3325 is on and OPTION_MASK_ABI_X32 is off. We turn off
3326 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3327 -mx32. */
3330 #else
3331 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3332 on and OPTION_MASK_ABI_64 is off. We turn off
3333 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3334 -m64. */
3337 #endif
3338 }
3339 #endif
3342 {
3343 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3344 OPTION_MASK_ABI_64 for TARGET_X32. */
3347 }
3350 | OPTION_MASK_ABI_X32
3353 {
3354 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3355 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3358 }
3360 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3361 SUBTARGET_OVERRIDE_OPTIONS;
3362 #endif
3364 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3365 SUBSUBTARGET_OVERRIDE_OPTIONS;
3366 #endif
3368 /* -fPIC is the default for x86_64. */
3372 /* Need to check -mtune=generic first. */
3374 {
3375 /* As special support for cross compilers we read -mtune=native
3376 as -mtune=generic. With native compilers we won't see the
3377 -mtune=native, as it was changed by the driver. */
3379 {
3381 }
3386 }
3387 else
3388 {
3392 {
3393 opts->x_ix86_tune_string
3396 }
3398 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3399 or defaulted. We need to use a sensible tune option. */
3401 {
3403 }
3404 }
3408 {
3409 /* rep; movq isn't available in 32-bit code. */
3412 }
3415 opts->x_ix86_arch_string
3418 else
3422 {
3430 }
3431 else
3438 /* For targets using ms ABI enable ms-extensions, if not
3439 explicit turned off. For non-ms ABI we turn off this
3440 option. */
3445 {
3447 {
3491 {
3494 }
3502 }
3503 }
3504 else
3505 {
3506 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3507 use of rip-relative addressing. This eliminates fixups that
3508 would otherwise be needed if this object is to be placed in a
3509 DLL, and is essentially just as efficient as direct addressing. */
3515 else
3517 }
3519 {
3522 }
3530 {
3533 /* Default cpu tuning to the architecture. */
3678 }
3696 {
3700 {
3702 {
3704 {
3712 }
3713 else
3716 }
3717 }
3718 /* Intel CPUs have always interpreted SSE prefetch instructions as
3719 NOPs; so, we can enable SSE prefetch instructions even when
3720 -mtune (rather than -march) points us to a processor that has them.
3721 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3722 higher processors. */
3727 }
3735 #ifndef USE_IX86_FRAME_POINTER
3736 #define USE_IX86_FRAME_POINTER 0
3737 #endif
3739 #ifndef USE_X86_64_FRAME_POINTER
3740 #define USE_X86_64_FRAME_POINTER 0
3741 #endif
3743 /* Set the default values for switches whose default depends on TARGET_64BIT
3744 in case they weren't overwritten by command line options. */
3746 {
3754 opts->x_flag_unwind_tables
3758 }
3759 else
3760 {
3762 opts->x_flag_omit_frame_pointer
3768 }
3773 else
3776 /* Arrange to set up i386_stack_locals for all functions. */
3779 /* Validate -mregparm= value. */
3781 {
3785 {
3789 }
3790 }
3794 /* Default align_* from the processor table. */
3796 {
3799 }
3801 {
3804 }
3806 {
3808 }
3810 /* Provide default for -mbranch-cost= value. */
3815 {
3816 opts->x_target_flags
3819 /* Enable by default the SSE and MMX builtins. Do allow the user to
3820 explicitly disable any of these. In particular, disabling SSE and
3821 MMX for kernel code is extremely useful. */
3823 opts->x_ix86_isa_flags
3830 }
3831 else
3832 {
3833 opts->x_target_flags
3837 opts->x_ix86_isa_flags
3840 /* i386 ABI does not specify red zone. It still makes sense to use it
3841 when programmer takes care to stack from being destroyed. */
3844 }
3846 /* Keep nonleaf frame pointers. */
3852 /* If we're doing fast math, we don't care about comparison order
3853 wrt NaNs. This lets us use a shorter comparison sequence. */
3857 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3858 since the insns won't need emulation. */
3862 /* Likewise, if the target doesn't have a 387, or we've specified
3863 software floating point, don't use 387 inline intrinsics. */
3867 /* Turn on MMX builtins for -msse. */
3869 opts->x_ix86_isa_flags
3872 /* Enable SSE prefetch. */
3877 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3880 opts->x_ix86_isa_flags
3883 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3886 opts->x_ix86_isa_flags
3889 /* Enable lzcnt instruction for -mabm. */
3891 opts->x_ix86_isa_flags
3894 /* Validate -mpreferred-stack-boundary= value or default it to
3895 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3898 {
3905 {
3909 else
3912 }
3913 else
3914 ix86_preferred_stack_boundary
3916 }
3918 /* Set the default value for -mstackrealign. */
3924 /* Validate -mincoming-stack-boundary= value or default it to
3925 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3928 {
3935 else
3936 {
3937 ix86_user_incoming_stack_boundary
3939 ix86_incoming_stack_boundary
3941 }
3942 }
3944 /* Accept -msseregparm only if at least SSE support is enabled. */
3950 {
3952 {
3954 {
3957 }
3960 {
3963 }
3964 }
3965 }
3966 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3967 fpmath=387. The second is however default at many targets since the
3968 extra 80bit precision of temporaries is considered to be part of ABI.
3969 Overwrite the default at least for -ffast-math.
3970 TODO: -mfpmath=both seems to produce same performing code with bit
3971 smaller binaries. It is however not clear if register allocation is
3972 ready for this setting.
3973 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3974 codegen. We may switch to 387 with -ffast-math for size optimized
3975 functions. */
3979 else
3982 /* If the i387 is disabled, then do not return values in it. */
3986 /* Use external vectorized library in vectorizing intrinsics. */
3989 {
4000 }
4007 /* If stack probes are required, the space used for large function
4008 arguments on the stack must also be probed, so enable
4009 -maccumulate-outgoing-args so this happens in the prologue. */
4012 {
4017 }
4019 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4020 {
4026 }
4028 /* When scheduling description is not available, disable scheduler pass
4029 so it won't slow down the compilation and make x87 code slower. */
4050 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4052 && HAVE_prefetch
4057 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4058 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4063 {
4066 {
4068 ix86_gen_tls_local_dynamic_base_64
4070 }
4071 else
4072 {
4074 ix86_gen_tls_local_dynamic_base_64
4076 }
4077 }
4078 else
4082 {
4092 }
4093 else
4094 {
4104 }
4106 #ifdef USE_IX86_CLD
4107 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4110 #endif
4113 {
4118 }
4120 {
4124 }
4126 {
4127 #if defined(PROFILE_BEFORE_PROLOGUE)
4129 #else
4131 #endif
4132 }
4134 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4135 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4136 AVX unaligned load/store. */
4138 {
4148 /* Enable 128-bit AVX instruction generation
4149 for the auto-vectorizer. */
4153 }
4156 {
4163 {
4166 {
4168 q++;
4169 }
4170 else
4175 else
4176 {
4179 {
4182 }
4185 {
4189 }
4190 }
4195 else
4197 }
4198 }
4205 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4206 for 64-bit Bionic. */
4211 ? MASK_LONG_DOUBLE_128
4214 /* Only one of them can be active. */
4218 /* Save the initial options in case the user does function specific
4219 options. */
4221 target_option_default_node = target_option_current_node
4224 /* Handle stack protector */
4226 opts->x_ix86_stack_protector_guard
4229 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4231 {
4235 }
4238 {
4242 }
4243 }
4245 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4247 static void
4249 {
4251 static struct register_pass_info insert_vzeroupper_info
4254 };
4259 /* This needs to be done at start up. It's convenient to do it here. */
4261 }
4263 /* Update register usage after having seen the compiler flags. */
4265 static void
4267 {
4271 /* The PIC register, if it exists, is fixed. */
4276 /* For 32-bit targets, squash the REX registers. */
4278 {
4285 }
4287 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4295 {
4296 /* Set/reset conditionally defined registers from
4297 CALL_USED_REGISTERS initializer. */
4301 /* Calculate registers of CLOBBERED_REGS register set
4302 as call used registers from GENERAL_REGS register set. */
4306 }
4308 /* If MMX is disabled, squash the registers. */
4314 /* If SSE is disabled, squash the registers. */
4320 /* If the FPU is disabled, squash the registers. */
4326 /* If AVX512F is disabled, squash the registers. */
4328 {
4334 }
4335 }
4337 \f
4338 /* Save the current options */
4340 static void
4343 {
4378 /* The fields are char but the variables are not; make sure the
4379 values fit in the fields. */
4384 }
4386 /* Restore the current options */
4388 static void
4391 {
4397 /* We don't change -fPIC. */
4434 /* Recreate the arch feature tests if the arch changed */
4436 {
4441 }
4443 /* Recreate the tune optimization tests */
4446 }
4448 /* Print the current options */
4450 static void
4453 {
4471 {
4474 }
4475 }
4477 \f
4478 /* Inner function to process the attribute((target(...))), take an argument and
4479 set the current options from the argument. If we have a list, recursively go
4480 over the list. */
4482 static bool
4487 {
4491 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4492 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4493 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4494 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4495 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4497 enum ix86_opt_type
4498 {
4499 ix86_opt_unknown,
4500 ix86_opt_yes,
4501 ix86_opt_no,
4502 ix86_opt_str,
4503 ix86_opt_enum,
4504 ix86_opt_isa
4505 };
4507 static const struct
4508 {
4515 /* isa options */
4558 /* enum options */
4561 /* string options */
4565 /* flag options */
4567 OPT_mcld,
4568 MASK_CLD),
4571 OPT_mfancy_math_387,
4572 MASK_NO_FANCY_MATH_387),
4575 OPT_mieee_fp,
4576 MASK_IEEE_FP),
4579 OPT_minline_all_stringops,
4580 MASK_INLINE_ALL_STRINGOPS),
4583 OPT_minline_stringops_dynamically,
4584 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4587 OPT_mno_align_stringops,
4588 MASK_NO_ALIGN_STRINGOPS),
4591 OPT_mrecip,
4592 MASK_RECIP),
4594 };
4596 /* If this is a list, recurse to get the options. */
4598 {
4605 enum_opts_set))
4609 }
4612 {
4615 }
4617 /* Handle multiple arguments separated by commas. */
4621 {
4635 {
4639 }
4640 else
4641 {
4644 }
4646 /* Recognize no-xxx. */
4648 {
4652 }
4653 else
4656 /* Find the option. */
4660 {
4668 {
4673 }
4674 }
4676 /* Process the option. */
4678 {
4681 }
4684 {
4690 }
4693 {
4699 else
4701 }
4704 {
4706 {
4709 }
4710 else
4712 }
4715 {
4723 global_dc);
4724 else
4725 {
4728 }
4729 }
4731 else
4733 }
4736 }
4738 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4740 tree
4744 {
4759 /* Process each of the options on the chain. */
4764 /* If the changed options are different from the default, rerun
4765 ix86_option_override_internal, and then save the options away.
4766 The string options are are attribute options, and will be undone
4767 when we copy the save structure. */
4773 {
4774 /* If we are using the default tune= or arch=, undo the string assigned,
4775 and use the default. */
4786 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4791 {
4794 }
4796 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4799 /* Add any builtin functions with the new isa if any. */
4802 /* Save the current options unless we are validating options for
4803 #pragma. */
4810 /* Free up memory allocated to hold the strings */
4813 }
4816 }
4818 /* Hook to validate attribute((target("string"))). */
4820 static bool
4823 tree args,
4825 {
4830 /* attribute((target("default"))) does nothing, beyond
4831 affecting multi-versioning. */
4840 /* Get the optimization options of the current function. */
4846 /* Init func_options. */
4854 /* Initialize func_options to the default before its target options can
4855 be set. */
4868 {
4873 }
4876 }
4878 \f
4879 /* Hook to determine if one function can safely inline another. */
4881 static bool
4883 {
4888 /* If callee has no option attributes, then it is ok to inline. */
4892 /* If caller has no option attributes, but callee does then it is not ok to
4893 inline. */
4897 else
4898 {
4902 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4903 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4904 function. */
4909 /* See if we have the same non-isa options. */
4913 /* See if arch, tune, etc. are the same. */
4926 else
4928 }
4931 }
4933 \f
4934 /* Remember the last target of ix86_set_current_function. */
4937 /* Invalidate ix86_previous_fndecl cache. */
4938 void
4940 {
4942 }
4944 /* Establish appropriate back-end context for processing the function
4945 FNDECL. The argument might be NULL to indicate processing at top
4946 level, outside of any function scope. */
4947 static void
4949 {
4950 /* Only change the context if the function changes. This hook is called
4951 several times in the course of compiling a function, and we don't want to
4952 slow things down too much or call target_reinit when it isn't safe. */
4954 {
4955 tree old_tree = (ix86_previous_fndecl
4959 tree new_tree = (fndecl
4965 ;
4968 {
4973 else
4976 }
4979 {
4987 else
4990 }
4991 }
4992 }
4994 \f
4995 /* Return true if this goes in large data/bss. */
4997 static bool
4999 {
5003 /* Functions are never large data. */
5008 {
5014 }
5015 else
5016 {
5019 /* If this is an incomplete type with size 0, then we can't put it
5020 in data because it might be too big when completed. */
5023 }
5026 }
5028 /* Switch to the appropriate section for output of DECL.
5029 DECL is either a `VAR_DECL' node or a constant of some sort.
5030 RELOC indicates whether forming the initial value of DECL requires
5031 link-time relocations. */
5036 {
5039 {
5043 {
5077 /* We don't split these for medium model. Place them into
5078 default sections and hope for best. */
5080 }
5082 {
5083 /* We might get called with string constants, but get_named_section
5084 doesn't like them as they are not DECLs. Also, we need to set
5085 flags in that case. */
5089 }
5090 }
5092 }
5094 /* Select a set of attributes for section NAME based on the properties
5095 of DECL and whether or not RELOC indicates that DECL's initializer
5096 might contain runtime relocations. */
5098 static unsigned int ATTRIBUTE_UNUSED
5100 {
5114 }
5116 /* Build up a unique section name, expressed as a
5117 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5118 RELOC indicates whether the initial value of EXP requires
5119 link-time relocations. */
5121 static void ATTRIBUTE_UNUSED
5123 {
5126 {
5128 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5132 {
5156 /* We don't split these for medium model. Place them into
5157 default sections and hope for best. */
5159 }
5161 {
5168 /* If we're using one_only, then there needs to be a .gnu.linkonce
5169 prefix to the section name. */
5176 }
5177 }
5179 }
5181 #ifdef COMMON_ASM_OP
5182 /* This says how to output assembler code to declare an
5183 uninitialized external linkage data object.
5185 For medium model x86-64 we need to use .largecomm opcode for
5186 large objects. */
5187 void
5191 {
5195 else
5200 }
5201 #endif
5203 /* Utility function for targets to use in implementing
5204 ASM_OUTPUT_ALIGNED_BSS. */
5206 void
5210 {
5214 else
5217 #ifdef ASM_DECLARE_OBJECT_NAME
5220 #else
5221 /* Standard thing is just output label for the object. */
5225 }
5226 \f
5227 /* Decide whether we must probe the stack before any space allocation
5228 on this target. It's essentially TARGET_STACK_PROBE except when
5229 -fstack-check causes the stack to be already probed differently. */
5231 bool
5233 {
5234 /* Do not probe the stack twice if static stack checking is enabled. */
5239 }
5240 \f
5241 /* Decide whether we can make a sibling call to a function. DECL is the
5242 declaration of the function being targeted by the call and EXP is the
5243 CALL_EXPR representing the call. */
5245 static bool
5247 {
5251 /* If we are generating position-independent code, we cannot sibcall
5252 optimize any indirect call, or a direct call to a global function,
5253 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5255 && !TARGET_64BIT
5256 && flag_pic
5260 /* If we need to align the outgoing stack, then sibcalling would
5261 unalign the stack, which may break the called function. */
5267 {
5270 }
5271 else
5272 {
5273 /* We're looking at the CALL_EXPR, we need the type of the function. */
5278 }
5280 /* Check that the return value locations are the same. Like
5281 if we are returning floats on the 80387 register stack, we cannot
5282 make a sibcall from a function that doesn't return a float to a
5283 function that does or, conversely, from a function that does return
5284 a float to a function that doesn't; the necessary stack adjustment
5285 would not be executed. This is also the place we notice
5286 differences in the return value ABI. Note that it is ok for one
5287 of the functions to have void return type as long as the return
5288 value of the other is passed in a register. */
5293 {
5296 }
5298 ;
5303 {
5304 /* The SYSV ABI has more call-clobbered registers;
5305 disallow sibcalls from MS to SYSV. */
5309 }
5310 else
5311 {
5312 /* If this call is indirect, we'll need to be able to use a
5313 call-clobbered register for the address of the target function.
5314 Make sure that all such registers are not used for passing
5315 parameters. Note that DLLIMPORT functions are indirect. */
5318 {
5320 {
5321 /* ??? Need to count the actual number of registers to be used,
5322 not the possible number of registers. Fix later. */
5324 }
5325 }
5326 }
5328 /* Otherwise okay. That also includes certain types of indirect calls. */
5330 }
5332 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5333 and "sseregparm" calling convention attributes;
5334 arguments as in struct attribute_spec.handler. */
5336 static tree
5338 tree args,
5341 {
5346 {
5348 name);
5351 }
5353 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5355 {
5356 tree cst;
5359 {
5361 }
5364 {
5366 }
5370 {
5373 name);
5375 }
5377 {
5381 }
5384 }
5387 {
5388 /* Do not warn when emulating the MS ABI. */
5393 name);
5396 }
5398 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5400 {
5402 {
5404 }
5406 {
5408 }
5410 {
5412 }
5414 {
5416 }
5417 }
5419 /* Can combine stdcall with fastcall (redundant), regparm and
5420 sseregparm. */
5422 {
5424 {
5426 }
5428 {
5430 }
5432 {
5434 }
5435 }
5437 /* Can combine cdecl with regparm and sseregparm. */
5439 {
5441 {
5443 }
5445 {
5447 }
5449 {
5451 }
5452 }
5454 {
5457 name);
5459 {
5461 }
5463 {
5465 }
5467 {
5469 }
5470 }
5472 /* Can combine sseregparm with all attributes. */
5475 }
5477 /* The transactional memory builtins are implicitly regparm or fastcall
5478 depending on the ABI. Override the generic do-nothing attribute that
5479 these builtins were declared with, and replace it with one of the two
5480 attributes that we expect elsewhere. */
5482 static tree
5484 tree args ATTRIBUTE_UNUSED,
5486 {
5487 tree alt;
5489 /* In no case do we want to add the placeholder attribute. */
5492 /* The 64-bit ABI is unchanged for transactional memory. */
5496 /* ??? Is there a better way to validate 32-bit windows? We have
5497 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5500 else
5501 {
5504 }
5508 }
5510 /* This function determines from TYPE the calling-convention. */
5512 unsigned int
5514 {
5517 tree attrs;
5524 {
5534 /* Regparam isn't allowed for thiscall and fastcall. */
5536 {
5541 }
5545 }
5552 || is_stdarg
5558 }
5560 /* Return 0 if the attributes for two types are incompatible, 1 if they
5561 are compatible, and 2 if they are nearly compatible (which causes a
5562 warning to be generated). */
5564 static int
5566 {
5582 }
5583 \f
5584 /* Return the regparm value for a function with the indicated TYPE and DECL.
5585 DECL may be NULL when calling function indirectly
5586 or considering a libcall. */
5588 static int
5590 {
5591 tree attr;
5602 {
5605 {
5608 }
5609 }
5615 /* Use register calling convention for local functions when possible. */
5618 /* Caller and callee must agree on the calling convention, so
5619 checking here just optimize means that with
5620 __attribute__((optimize (...))) caller could use regparm convention
5621 and callee not, or vice versa. Instead look at whether the callee
5622 is optimized or not. */
5625 {
5626 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5629 {
5632 /* Make sure no regparm register is taken by a
5633 fixed register variable. */
5638 /* We don't want to use regparm(3) for nested functions as
5639 these use a static chain pointer in the third argument. */
5643 /* In 32-bit mode save a register for the split stack. */
5647 /* Each fixed register usage increases register pressure,
5648 so less registers should be used for argument passing.
5649 This functionality can be overriden by an explicit
5650 regparm value. */
5653 globals++;
5655 local_regparm
5660 }
5661 }
5664 }
5666 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5667 DFmode (2) arguments in SSE registers for a function with the
5668 indicated TYPE and DECL. DECL may be NULL when calling function
5669 indirectly or considering a libcall. Otherwise return 0. */
5671 static int
5673 {
5676 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5677 by the sseregparm attribute. */
5680 {
5682 {
5684 {
5688 else
5691 }
5693 }
5696 }
5698 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5699 (and DFmode for SSE2) arguments in SSE registers. */
5702 {
5703 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5707 }
5710 }
5712 /* Return true if EAX is live at the start of the function. Used by
5713 ix86_expand_prologue to determine if we need special help before
5714 calling allocate_stack_worker. */
5716 static bool
5718 {
5719 /* Cheat. Don't bother working forward from ix86_function_regparm
5720 to the function type to whether an actual argument is located in
5721 eax. Instead just look at cfg info, which is still close enough
5722 to correct at this point. This gives false positives for broken
5723 functions that might use uninitialized data that happens to be
5724 allocated in eax, but who cares? */
5726 }
5728 static bool
5730 {
5731 tree attr;
5734 {
5740 /* For 32-bit MS-ABI the default is to keep aggregate
5741 return pointer. */
5744 }
5746 }
5748 /* Value is the number of bytes of arguments automatically
5749 popped when returning from a subroutine call.
5750 FUNDECL is the declaration node of the function (as a tree),
5751 FUNTYPE is the data type of the function (as a tree),
5752 or for a library call it is an identifier node for the subroutine name.
5753 SIZE is the number of bytes of arguments passed on the stack.
5755 On the 80386, the RTD insn may be used to pop them if the number
5756 of args is fixed, but if the number is variable then the caller
5757 must pop them all. RTD can't be used for library calls now
5758 because the library is compiled with the Unix compiler.
5759 Use of RTD is a selectable option, since it is incompatible with
5760 standard Unix calling sequences. If the option is not selected,
5761 the caller must always pop the args.
5763 The attribute stdcall is equivalent to RTD on a per module basis. */
5765 static int
5767 {
5770 /* None of the 64-bit ABIs pop arguments. */
5781 /* Lose any fake structure return argument if it is passed on the stack. */
5784 {
5788 }
5791 }
5793 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5795 static bool
5797 {
5798 /* Check operand constraints in case hard registers were propagated
5799 into insn pattern. This check prevents combine pass from
5800 generating insn patterns with invalid hard register operands.
5801 These invalid insns can eventually confuse reload to error out
5802 with a spill failure. See also PRs 46829 and 46843. */
5804 {
5811 {
5819 /* For pre-AVX disallow unaligned loads/stores where the
5820 instructions don't support it. */
5824 {
5828 }
5830 /* A unary operator may be accepted by the predicate, but it
5831 is irrelevant for matching constraints. */
5836 {
5844 }
5851 /* Operand has no constraints, anything is OK. */
5855 {
5858 && operands_match_p
5862 {
5865 }
5866 }
5870 }
5871 }
5874 }
5875 \f
5876 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5878 static unsigned HOST_WIDE_INT
5880 {
5884 }
5885 \f
5886 /* Argument support functions. */
5888 /* Return true when register may be used to pass function parameters. */
5889 bool
5891 {
5896 {
5900 else
5906 }
5912 /* TODO: The function should depend on current function ABI but
5913 builtins.c would need updating then. Therefore we use the
5914 default ABI. */
5916 /* RAX is used as hidden argument to va_arg functions. */
5922 else
5929 }
5931 /* Return if we do not know how to pass TYPE solely in registers. */
5933 static bool
5935 {
5939 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5940 The layout_type routine is crafty and tries to trick us into passing
5941 currently unsupported vector types on the stack by using TImode. */
5944 }
5946 /* It returns the size, in bytes, of the area reserved for arguments passed
5947 in registers for the function represented by fndecl dependent to the used
5948 abi format. */
5949 int
5951 {
5955 else
5960 }
5962 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5963 call abi used. */
5964 enum calling_abi
5966 {
5968 {
5971 {
5974 }
5978 }
5980 }
5982 /* We add this as a workaround in order to use libc_has_function
5983 hook in i386.md. */
5984 bool
5986 {
5988 }
5990 static bool
5992 {
5994 {
5998 else
6000 }
6002 }
6004 static enum calling_abi
6006 {
6010 }
6012 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6013 call abi used. */
6014 enum calling_abi
6016 {
6020 }
6022 /* Write the extra assembler code needed to declare a function properly. */
6024 void
6026 tree decl)
6027 {
6031 {
6037 }
6039 #ifdef SUBTARGET_ASM_UNWIND_INIT
6041 #endif
6045 /* Output magic byte marker, if hot-patch attribute is set. */
6047 {
6049 {
6050 /* leaq [%rsp + 0], %rsp */
6053 }
6054 else
6055 {
6056 /* movl.s %edi, %edi
6057 push %ebp
6058 movl.s %esp, %ebp */
6061 }
6062 }
6063 }
6065 /* regclass.c */
6068 /* Implementation of call abi switching target hook. Specific to FNDECL
6069 the specific call register sets are set. See also
6070 ix86_conditional_register_usage for more details. */
6071 void
6073 {
6076 else
6078 }
6080 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6081 expensive re-initialization of init_regs each time we switch function context
6082 since this is needed only during RTL expansion. */
6083 static void
6085 {
6089 }
6091 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6092 for a call to a function whose data type is FNTYPE.
6093 For a library call, FNTYPE is 0. */
6095 void
6099 tree fndecl,
6101 {
6107 {
6110 }
6111 else
6112 {
6115 }
6119 /* Set up the number of registers to use for passing arguments. */
6122 {
6124 ? X86_64_REGPARM_MAX
6126 }
6128 {
6131 {
6133 ? X86_64_SSE_REGPARM_MAX
6135 }
6136 }
6144 /* Because type might mismatch in between caller and callee, we need to
6145 use actual type of function for local calls.
6146 FIXME: cgraph_analyze can be told to actually record if function uses
6147 va_start so for local functions maybe_vaarg can be made aggressive
6148 helping K&R code.
6149 FIXME: once typesytem is fixed, we won't need this code anymore. */
6157 {
6158 /* If there are variable arguments, then we won't pass anything
6159 in registers in 32-bit mode. */
6161 {
6170 }
6172 /* Use ecx and edx registers if function has fastcall attribute,
6173 else look for regparm information. */
6175 {
6178 {
6181 }
6183 {
6186 }
6187 else
6189 }
6191 /* Set up the number of SSE registers used for passing SFmode
6192 and DFmode arguments. Warn for mismatching ABI. */
6194 }
6195 }
6197 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6198 But in the case of vector types, it is some vector mode.
6200 When we have only some of our vector isa extensions enabled, then there
6201 are some modes for which vector_mode_supported_p is false. For these
6202 modes, the generic vector support in gcc will choose some non-vector mode
6203 in order to implement the type. By computing the natural mode, we'll
6204 select the proper ABI location for the operand and not depend on whatever
6205 the middle-end decides to do with these vector types.
6207 The midde-end can't deal with the vector types > 16 bytes. In this
6208 case, we return the original mode and warn ABI change if CUM isn't
6209 NULL.
6211 If INT_RETURN is true, warn ABI change if the vector mode isn't
6212 available for function return value. */
6214 static enum machine_mode
6217 {
6221 {
6224 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6226 {
6231 else
6234 /* Get the mode which has this inner mode and number of units. */
6238 {
6240 {
6245 {
6249 }
6251 {
6255 }
6258 }
6260 {
6265 {
6269 }
6271 {
6275 }
6278 }
6281 {
6286 {
6290 }
6292 {
6296 }
6297 }
6299 {
6304 {
6308 }
6310 {
6314 }
6315 }
6317 }
6320 }
6321 }
6324 }
6326 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6327 this may not agree with the mode that the type system has chosen for the
6328 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6329 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6331 static rtx
6334 {
6335 rtx tmp;
6339 else
6340 {
6344 }
6347 }
6349 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6350 of this code is to classify each 8bytes of incoming argument by the register
6351 class and assign registers accordingly. */
6353 /* Return the union class of CLASS1 and CLASS2.
6354 See the x86-64 PS ABI for details. */
6356 static enum x86_64_reg_class
6358 {
6359 /* Rule #1: If both classes are equal, this is the resulting class. */
6363 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6364 the other class. */
6370 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6374 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6382 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6383 MEMORY is used. */
6392 /* Rule #6: Otherwise class SSE is used. */
6394 }
6396 /* Classify the argument of type TYPE and mode MODE.
6397 CLASSES will be filled by the register class used to pass each word
6398 of the operand. The number of words is returned. In case the parameter
6399 should be passed in memory, 0 is returned. As a special case for zero
6400 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6402 BIT_OFFSET is used internally for handling records and specifies offset
6403 of the offset in bits modulo 512 to avoid overflow cases.
6405 See the x86-64 PS ABI for details.
6406 */
6408 static int
6411 {
6412 HOST_WIDE_INT bytes =
6414 int words
6417 /* Variable sized entities are always passed/returned in memory. */
6425 /* Special case check for pointer to shared, on 64-bit target. */
6429 {
6432 }
6435 {
6437 tree field;
6440 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6447 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6448 signalize memory class, so handle it as special case. */
6450 {
6453 }
6455 /* Classify each field of record and merge classes. */
6457 {
6459 /* And now merge the fields of structure. */
6461 {
6463 {
6469 /* Bitfields are always classified as integer. Handle them
6470 early, since later code would consider them to be
6471 misaligned integers. */
6473 {
6482 }
6483 else
6484 {
6489 /* Flexible array member is ignored. */
6496 {
6500 {
6503 "the ABI of passing struct with"
6504 " a flexible array member has"
6506 }
6508 }
6510 subclasses,
6520 }
6521 }
6522 }
6526 /* Arrays are handled as small records. */
6527 {
6534 /* The partial classes are now full classes. */
6545 }
6548 /* Unions are similar to RECORD_TYPE but offset is always 0.
6549 */
6551 {
6553 {
6561 bit_offset);
6566 }
6567 }
6572 }
6575 {
6576 /* When size > 16 bytes, if the first one isn't
6577 X86_64_SSE_CLASS or any other ones aren't
6578 X86_64_SSEUP_CLASS, everything should be passed in
6579 memory. */
6586 }
6588 /* Final merger cleanup. */
6590 {
6591 /* If one class is MEMORY, everything should be passed in
6592 memory. */
6596 /* The X86_64_SSEUP_CLASS should be always preceded by
6597 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6601 {
6602 /* The first one should never be X86_64_SSEUP_CLASS. */
6605 }
6607 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6608 everything should be passed in memory. */
6611 {
6614 /* The first one should never be X86_64_X87UP_CLASS. */
6617 {
6620 "the ABI of passing union with long double"
6622 }
6624 }
6625 }
6627 }
6629 /* Compute alignment needed. We align all types to natural boundaries with
6630 exception of XFmode that is aligned to 64bits. */
6632 {
6641 /* Misaligned fields are always returned in memory. */
6644 }
6646 /* for V1xx modes, just use the base mode */
6651 /* Classification of atomic types. */
6653 {
6669 {
6672 /* Analyze last 128 bits only. */
6676 {
6679 }
6681 {
6684 }
6686 {
6690 }
6692 {
6695 }
6696 else
6698 }
6705 /* OImode shouldn't be used directly. */
6712 else
6730 else
6731 {
6735 {
6738 "the ABI of passing structure with complex float"
6740 }
6743 }
6752 /* This modes is larger than 16 bytes. */
6810 else
6814 }
6815 }
6817 /* Examine the argument and return set number of register required in each
6818 class. Return 0 iff parameter should be passed in memory. */
6819 static int
6822 {
6832 {
6854 }
6856 }
6858 /* Construct container for the argument used by GCC interface. See
6859 FUNCTION_ARG for the detailed description. */
6861 static rtx
6865 {
6866 /* The following variables hold the static issued_error state. */
6880 rtx ret;
6891 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6892 some less clueful developer tries to use floating-point anyway. */
6894 {
6896 {
6898 {
6901 }
6902 }
6904 {
6907 }
6909 }
6911 /* Likewise, error if the ABI requires us to return values in the
6912 x87 registers and the user specified -mno-80387. */
6918 {
6920 {
6923 }
6925 }
6927 /* First construct simple cases. Avoid SCmode, since we want to use
6928 single register to pass this type. */
6931 {
6946 /* Zero sized array, struct or class. */
6950 }
6989 /* Otherwise figure out the entries of the PARALLEL. */
6991 {
6995 {
7000 /* Merge TImodes on aligned occasions here too. */
7002 tmpmode
7006 else
7008 /* We've requested 24 bytes we
7009 don't have mode for. Use DImode. */
7016 intreg++;
7024 sse_regno++;
7032 sse_regno++;
7037 {
7043 {
7045 i++;
7046 }
7047 else
7072 }
7078 sse_regno++;
7082 }
7083 }
7085 /* Empty aligned struct, union or class. */
7093 }
7095 /* Update the data in CUM to advance over an argument of mode MODE
7096 and data type TYPE. (TYPE is null for libcalls where that information
7097 may not be available.) */
7099 static void
7102 HOST_WIDE_INT words)
7103 {
7105 {
7112 /* FALLTHRU */
7123 {
7126 }
7130 /* OImode shouldn't be used directly. */
7139 /* FALLTHRU */
7161 {
7166 {
7169 }
7170 }
7180 {
7185 {
7188 }
7189 }
7191 }
7192 }
7194 static void
7197 {
7200 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7207 {
7212 }
7213 else
7214 {
7218 }
7219 }
7221 static void
7223 HOST_WIDE_INT words)
7224 {
7225 /* Otherwise, this should be passed indirect. */
7230 {
7233 }
7234 }
7236 /* Update the data in CUM to advance over an argument of mode MODE and
7237 data type TYPE. (TYPE is null for libcalls where that information
7238 may not be available.) */
7240 static void
7243 {
7249 else
7260 else
7262 }
7264 /* Define where to put the arguments to a function.
7265 Value is zero to push the argument on the stack,
7266 or a hard register in which to store the argument.
7268 MODE is the argument's machine mode.
7269 TYPE is the data type of the argument (as a tree).
7270 This is null for libcalls where that information may
7271 not be available.
7272 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7273 the preceding args and about the function being called.
7274 NAMED is nonzero if this argument is a named parameter
7275 (otherwise it is an extra parameter matching an ellipsis). */
7277 static rtx
7281 {
7282 /* Avoid the AL settings for the Unix64 ABI. */
7287 {
7294 /* FALLTHRU */
7300 {
7303 /* Fastcall allocates the first two DWORD (SImode) or
7304 smaller arguments to ECX and EDX if it isn't an
7305 aggregate type . */
7307 {
7313 /* ECX not EAX is the first allocated register. */
7316 }
7318 }
7327 /* FALLTHRU */
7329 /* In 32bit, we pass TImode in xmm registers. */
7337 {
7341 }
7346 /* OImode and XImode shouldn't be used directly. */
7362 {
7366 }
7376 {
7380 }
7382 }
7385 }
7387 static rtx
7390 {
7391 /* Handle a hidden AL argument containing number of registers
7392 for varargs x86-64 functions. */
7396 ? X86_64_SSE_REGPARM_MAX
7401 {
7417 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7421 }
7427 }
7429 static rtx
7432 HOST_WIDE_INT bytes)
7433 {
7436 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7437 We use value of -2 to specify that current function call is MSABI. */
7441 /* If we've run out of registers, it goes on the stack. */
7447 /* Only floating point modes are passed in anything but integer regs. */
7449 {
7452 else
7453 {
7456 /* Unnamed floating parameters are passed in both the
7457 SSE and integer registers. */
7463 }
7464 }
7465 /* Handle aggregated types passed in register. */
7467 {
7472 }
7475 }
7477 /* Return where to put the arguments to a function.
7478 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7480 MODE is the argument's machine mode. TYPE is the data type of the
7481 argument. It is null for libcalls where that information may not be
7482 available. CUM gives information about the preceding args and about
7483 the function being called. NAMED is nonzero if this argument is a
7484 named parameter (otherwise it is an extra parameter matching an
7485 ellipsis). */
7487 static rtx
7490 {
7494 rtx arg;
7498 else
7502 /* To simplify the code below, represent vector types with a vector mode
7503 even if MMX/SSE are not active. */
7511 else
7515 }
7517 /* A C expression that indicates when an argument must be passed by
7518 reference. If nonzero for an argument, a copy of that argument is
7519 made in memory and a pointer to the argument is passed instead of
7520 the argument itself. The pointer is passed in whatever way is
7521 appropriate for passing a pointer to that type. */
7523 static bool
7526 {
7529 /* See Windows x64 Software Convention. */
7531 {
7534 {
7535 /* Arrays are passed by reference. */
7540 {
7541 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7542 are passed by reference. */
7544 }
7545 }
7547 /* __m128 is passed by reference. */
7553 }
7554 }
7559 }
7561 /* Return true when TYPE should be 128bit aligned for 32bit argument
7562 passing ABI. XXX: This function is obsolete and is only used for
7563 checking psABI compatibility with previous versions of GCC. */
7565 static bool
7567 {
7579 {
7580 /* Walk the aggregates recursively. */
7582 {
7586 {
7587 tree field;
7589 /* Walk all the structure fields. */
7591 {
7595 }
7597 }
7600 /* Just for use if some languages passes arrays by value. */
7607 }
7608 }
7610 }
7612 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7613 XXX: This function is obsolete and is only used for checking psABI
7614 compatibility with previous versions of GCC. */
7616 static unsigned int
7619 {
7620 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7621 natural boundaries. */
7623 {
7624 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7625 make an exception for SSE modes since these require 128bit
7626 alignment.
7628 The handling here differs from field_alignment. ICC aligns MMX
7629 arguments to 4 byte boundaries, while structure fields are aligned
7630 to 8 byte boundaries. */
7632 {
7635 }
7636 else
7637 {
7640 }
7641 }
7645 }
7647 /* Return true when TYPE should be 128bit aligned for 32bit argument
7648 passing ABI. */
7650 static bool
7652 {
7662 {
7663 /* Walk the aggregates recursively. */
7665 {
7669 {
7670 tree field;
7672 /* Walk all the structure fields. */
7674 field;
7676 {
7680 }
7682 }
7685 /* Just for use if some languages passes arrays by value. */
7692 }
7693 }
7694 else
7698 }
7700 /* Gives the alignment boundary, in bits, of an argument with the
7701 specified mode and type. */
7703 static unsigned int
7705 {
7708 {
7709 /* Since the main variant type is used for call, we convert it to
7710 the main variant type. */
7713 }
7714 else
7718 else
7719 {
7724 {
7725 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7727 {
7730 }
7736 }
7739 && !warned
7741 saved_align))
7742 {
7745 "The ABI for passing parameters with %d-byte"
7748 }
7749 }
7752 }
7754 /* Return true if N is a possible register number of function value. */
7756 static bool
7758 {
7760 {
7768 /* Complex values are returned in %st(0)/%st(1) pair. */
7771 /* TODO: The function should depend on current function ABI but
7772 builtins.c would need updating then. Therefore we use the
7773 default ABI. */
7778 /* Complex values are returned in %xmm0/%xmm1 pair. */
7787 }
7790 }
7792 /* Define how to find the value returned by a function.
7793 VALTYPE is the data type of the value (as a tree).
7794 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7795 otherwise, FUNC is 0. */
7797 static rtx
7800 {
7803 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7804 we normally prevent this case when mmx is not available. However
7805 some ABIs may require the result to be returned like DImode. */
7809 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7810 we prevent this case when sse is not available. However some ABIs
7811 may require the result to be returned like integer TImode. */
7816 /* 32-byte vector modes in %ymm0. */
7820 /* 64-byte vector modes in %zmm0. */
7824 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7827 else
7828 /* Most things go in %eax. */
7831 /* Override FP return register with %xmm0 for local functions when
7832 SSE math is enabled or for functions with sseregparm attribute. */
7834 {
7839 }
7841 /* OImode shouldn't be used directly. */
7845 }
7847 static rtx
7849 const_tree valtype)
7850 {
7851 rtx ret;
7853 /* Handle libcalls, which don't provide a type node. */
7855 {
7859 {
7878 }
7881 }
7884 {
7885 /* Pointers are always returned in word_mode. */
7887 }
7893 /* For zero sized structures, construct_container returns NULL, but we
7894 need to keep rest of compiler happy by returning meaningful value. */
7899 }
7901 static rtx
7903 const_tree valtype)
7904 {
7908 {
7910 {
7929 }
7930 }
7932 }
7934 static rtx
7937 {
7949 else
7951 }
7953 static rtx
7956 {
7962 }
7964 /* Pointer function arguments and return values are promoted to
7965 word_mode. */
7967 static enum machine_mode
7971 {
7973 {
7975 {
7978 }
7981 }
7983 for_return);
7984 }
7986 /* Return true if a structure, union or array with MODE containing FIELD
7987 should be accessed using BLKmode. */
7989 static bool
7991 {
7992 /* Union with XFmode must be in BLKmode. */
7996 }
7998 rtx
8000 {
8002 }
8004 /* Return true iff type is returned in memory. */
8006 static bool ATTRIBUTE_UNUSED
8008 {
8009 HOST_WIDE_INT size;
8020 {
8021 /* User-created vectors small enough to fit in EAX. */
8025 /* MMX/3dNow values are returned in MM0,
8026 except when it doesn't exits or the ABI prescribes otherwise. */
8030 /* SSE values are returned in XMM0, except when it doesn't exist. */
8034 /* AVX values are returned in YMM0, except when it doesn't exist. */
8038 /* AVX512F values are returned in ZMM0, except when it doesn't exist. */
8041 }
8049 /* OImode shouldn't be used directly. */
8053 }
8055 static bool ATTRIBUTE_UNUSED
8057 {
8060 }
8062 static bool ATTRIBUTE_UNUSED
8064 {
8067 /* __m128 is returned in xmm0. */
8074 /* Otherwise, the size must be exactly in [1248]. */
8076 }
8078 static bool
8080 {
8081 #ifdef SUBTARGET_RETURN_IN_MEMORY
8083 #else
8087 {
8090 else
8092 }
8093 else
8095 #endif
8096 }
8098 \f
8099 /* Create the va_list data type. */
8101 /* Returns the calling convention specific va_list date type.
8102 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8104 static tree
8106 {
8109 /* For i386 we use plain pointer to argument area. */
8119 unsigned_type_node);
8122 unsigned_type_node);
8125 ptr_type_node);
8128 ptr_type_node);
8147 /* The correct type is an array type of one element. */
8149 }
8151 /* Setup the builtin va_list data type and for 64-bit the additional
8152 calling convention specific va_list data types. */
8154 static tree
8156 {
8159 /* Initialize abi specific va_list builtin types. */
8161 {
8162 tree t;
8164 {
8169 }
8170 else
8171 {
8176 }
8178 {
8183 }
8184 else
8185 {
8190 }
8191 }
8194 }
8196 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8198 static void
8200 {
8202 alias_set_type set;
8205 /* GPR size of varargs save area. */
8208 else
8211 /* FPR size of varargs save area. We don't need it if we don't pass
8212 anything in SSE registers. */
8215 else
8229 {
8237 }
8240 {
8244 /* Now emit code to save SSE registers. The AX parameter contains number
8245 of SSE parameter registers used to call this function, though all we
8246 actually check here is the zero/non-zero status. */
8251 label));
8253 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8254 we used movdqa (i.e. TImode) instead? Perhaps even better would
8255 be if we could determine the real mode of the data, via a hook
8256 into pass_stdarg. Ignore all that for now. */
8266 {
8275 }
8278 }
8279 }
8281 static void
8283 {
8287 /* Reset to zero, as there might be a sysv vaarg used
8288 before. */
8293 {
8304 }
8305 }
8307 static void
8311 {
8313 CUMULATIVE_ARGS next_cum;
8314 tree fntype;
8316 /* This argument doesn't appear to be used anymore. Which is good,
8317 because the old code here didn't suppress rtl generation. */
8325 /* For varargs, we do not want to skip the dummy va_dcl argument.
8326 For stdargs, we do want to skip the last named argument. */
8334 else
8336 }
8338 /* Checks if TYPE is of kind va_list char *. */
8340 static bool
8342 {
8343 tree canonic;
8345 /* For 32-bit it is always true. */
8351 }
8353 /* Implement va_start. */
8355 static void
8357 {
8361 tree type;
8362 rtx ovf_rtx;
8366 {
8369 /* When we are splitting the stack, we can't refer to the stack
8370 arguments using internal_arg_pointer, because they may be on
8371 the old stack. The split stack prologue will arrange to
8372 leave a pointer to the old stack arguments in a scratch
8373 register, which we here copy to a pseudo-register. The split
8374 stack prologue can't set the pseudo-register directly because
8375 it (the prologue) runs before any registers have been saved. */
8379 {
8393 }
8394 }
8396 /* Only 64bit target needs something special. */
8398 {
8401 else
8402 {
8411 }
8413 }
8422 /* The following should be folded into the MEM_REF offset. */
8432 /* Count number of gp and fp argument registers used. */
8438 {
8444 }
8447 {
8453 }
8455 /* Find the overflow area. */
8459 else
8469 {
8470 /* Find the register save area.
8471 Prologue of the function save it right above stack frame. */
8479 }
8480 }
8482 /* Implement va_arg. */
8484 static tree
8487 {
8494 rtx container;
8496 tree ptrtype;
8500 /* Only 64bit target needs something special. */
8524 {
8537 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8539 {
8542 }
8550 }
8552 /* Pull the value out of the saved registers. */
8557 {
8571 /* In case we are passing structure, verify that it is consecutive block
8572 on the register save area. If not we need to do moves. */
8574 {
8575 /* Verify that all registers are strictly consecutive */
8577 {
8581 {
8586 }
8587 }
8588 else
8589 {
8593 {
8598 }
8599 }
8600 }
8602 {
8605 }
8606 else
8607 {
8610 }
8612 /* First ensure that we fit completely in registers. */
8614 {
8621 }
8623 {
8631 }
8633 /* Compute index to start of area used for integer regs. */
8635 {
8636 /* int_addr = gpr + sav; */
8639 }
8641 {
8642 /* sse_addr = fpr + sav; */
8645 }
8647 {
8651 /* addr = &temp; */
8656 {
8660 tree piece_type;
8661 tree addr_type;
8662 tree daddr_type;
8671 {
8676 }
8680 else
8687 {
8690 }
8691 else
8692 {
8695 }
8702 {
8707 }
8708 else
8709 {
8710 tree copy
8715 }
8717 }
8718 }
8721 {
8725 }
8728 {
8732 }
8737 }
8739 /* ... otherwise out of the overflow area. */
8741 /* When we align parameter on stack for caller, if the parameter
8742 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8743 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8744 here with caller. */
8749 /* Care for on-stack alignment if needed. */
8752 else
8753 {
8758 }
8775 }
8776 \f
8777 /* Return true if OPNUM's MEM should be matched
8778 in movabs* patterns. */
8780 bool
8782 {
8794 }
8795 \f
8796 /* Initialize the table of extra 80387 mathematical constants. */
8798 static void
8800 {
8802 {
8808 };
8812 {
8814 /* Ensure each constant is rounded to XFmode precision. */
8817 }
8820 }
8822 /* Return non-zero if the constant is something that
8823 can be loaded with a special instruction. */
8825 int
8827 {
8830 REAL_VALUE_TYPE r;
8842 /* For XFmode constants, try to find a special 80387 instruction when
8843 optimizing for size or on those CPUs that benefit from them. */
8846 {
8855 }
8857 /* Load of the constant -0.0 or -1.0 will be split as
8858 fldz;fchs or fld1;fchs sequence. */
8865 }
8867 /* Return the opcode of the special instruction to be used to load
8868 the constant X. */
8872 {
8874 {
8894 }
8895 }
8897 /* Return the CONST_DOUBLE representing the 80387 constant that is
8898 loaded by the specified special instruction. The argument IDX
8899 matches the return value from standard_80387_constant_p. */
8901 rtx
8903 {
8910 {
8921 }
8924 XFmode);
8925 }
8927 /* Return 1 if X is all 0s and 2 if x is all 1s
8928 in supported SSE/AVX vector mode. */
8930 int
8932 {
8939 {
8960 }
8963 }
8965 /* Return the opcode of the special instruction to be used to load
8966 the constant X. */
8970 {
8972 {
8975 {
8997 }
9006 else
9011 }
9013 }
9015 /* Returns true if OP contains a symbol reference */
9017 bool
9019 {
9028 {
9030 {
9036 }
9040 }
9043 }
9045 /* Return true if it is appropriate to emit `ret' instructions in the
9046 body of a function. Do this only if the epilogue is simple, needing a
9047 couple of insns. Prior to reloading, we can't tell how many registers
9048 must be saved, so return false then. Return false if there is no frame
9049 marker to de-allocate. */
9051 bool
9053 {
9059 /* Don't allow more than 32k pop, since that's all we can do
9060 with one instruction. */
9067 }
9068 \f
9069 /* Value should be nonzero if functions must have frame pointers.
9070 Zero means the frame pointer need not be set up (and parms may
9071 be accessed via the stack pointer) in functions that seem suitable. */
9073 static bool
9075 {
9076 /* If we accessed previous frames, then the generated code expects
9077 to be able to access the saved ebp value in our frame. */
9081 /* Several x86 os'es need a frame pointer for other reasons,
9082 usually pertaining to setjmp. */
9086 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9090 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9091 allocation is 4GB. */
9095 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9096 turns off the frame pointer by default. Turn it back on now if
9097 we've not got a leaf function. */
9107 }
9109 /* Record that the current function accesses previous call frames. */
9111 void
9113 {
9115 }
9116 \f
9117 #ifndef USE_HIDDEN_LINKONCE
9118 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9119 # define USE_HIDDEN_LINKONCE 1
9120 # else
9121 # define USE_HIDDEN_LINKONCE 0
9122 # endif
9123 #endif
9127 /* Fills in the label name that should be used for a pc thunk for
9128 the given register. */
9130 static void
9132 {
9137 else
9139 }
9142 /* This function generates code for -fpic that loads %ebx with
9143 the return address of the caller and then returns. */
9145 static void
9147 {
9152 {
9154 tree decl;
9170 #if TARGET_MACHO
9172 {
9181 }
9182 else
9183 #endif
9185 {
9196 }
9197 else
9198 {
9201 }
9207 /* Make sure unwind info is emitted for the thunk if needed. */
9210 /* Pad stack IP move with 4 instructions (two NOPs count
9211 as one instruction). */
9213 {
9218 }
9229 }
9233 }
9235 /* Emit code for the SET_GOT patterns. */
9239 {
9245 {
9246 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9251 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9252 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9253 an unadorned address. */
9258 }
9263 {
9265 /* We don't need a pic base, we're not producing pic. */
9272 }
9273 else
9274 {
9283 #if TARGET_MACHO
9284 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9285 This is what will be referenced by the Mach-O PIC subsystem. */
9289 /* When we are restoring the pic base at the site of a nonlocal label,
9290 and we decided to emit the pic base above, we will still output a
9291 local label used for calculating the correction offset (even though
9292 the offset will be 0 in that case). */
9296 #endif
9297 }
9303 }
9305 /* Generate an "push" pattern for input ARG. */
9307 static rtx
9309 {
9322 stack_pointer_rtx)),
9323 arg);
9324 }
9326 /* Generate an "pop" pattern for input ARG. */
9328 static rtx
9330 {
9335 arg,
9338 stack_pointer_rtx)));
9339 }
9341 /* Return >= 0 if there is an unused call-clobbered register available
9342 for the entire function. */
9344 static unsigned int
9346 {
9350 {
9352 /* Can't use the same register for both PIC and DRAP. */
9355 else
9360 }
9363 }
9365 /* Return TRUE if we need to save REGNO. */
9367 static bool
9369 {
9380 {
9383 {
9389 }
9390 }
9401 }
9403 /* Return number of saved general prupose registers. */
9405 static int
9407 {
9413 nregs ++;
9415 }
9417 /* Return number of saved SSE registrers. */
9419 static int
9421 {
9429 nregs ++;
9431 }
9433 /* Given FROM and TO register numbers, say whether this elimination is
9434 allowed. If stack alignment is needed, we can only replace argument
9435 pointer with hard frame pointer, or replace frame pointer with stack
9436 pointer. Otherwise, frame pointer elimination is automatically
9437 handled and all other eliminations are valid. */
9439 static bool
9441 {
9447 else
9449 }
9451 /* Return the offset between two registers, one to be eliminated, and the other
9452 its replacement, at the start of a routine. */
9454 HOST_WIDE_INT
9456 {
9465 else
9466 {
9474 }
9475 }
9477 /* In a dynamically-aligned function, we can't know the offset from
9478 stack pointer to frame pointer, so we must ensure that setjmp
9479 eliminates fp against the hard fp (%ebp) rather than trying to
9480 index from %esp up to the top of the frame across a gap that is
9481 of unknown (at compile-time) size. */
9482 static rtx
9484 {
9486 }
9488 /* When using -fsplit-stack, the allocation routines set a field in
9489 the TCB to the bottom of the stack plus this much space, measured
9490 in bytes. */
9492 #define SPLIT_STACK_AVAILABLE 256
9494 /* Fill structure ix86_frame about frame of currently computed function. */
9496 static void
9498 {
9500 HOST_WIDE_INT offset;
9503 HOST_WIDE_INT to_allocate;
9511 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9512 function prologues and leaf. */
9516 {
9521 }
9527 /* For SEH we have to limit the amount of code movement into the prologue.
9528 At present we do this via a BLOCKAGE, at which point there's very little
9529 scheduling that can be done, which means that there's very little point
9530 in doing anything except PUSHs. */
9534 /* During reload iteration the amount of registers saved can change.
9535 Recompute the value as needed. Do not recompute when amount of registers
9536 didn't change as reload does multiple calls to the function and does not
9537 expect the decision to change within single iteration. */
9540 {
9546 /* The fast prologue uses move instead of push to save registers. This
9547 is significantly longer, but also executes faster as modern hardware
9548 can execute the moves in parallel, but can't do that for push/pop.
9550 Be careful about choosing what prologue to emit: When function takes
9551 many instructions to execute we may use slow version as well as in
9552 case function is known to be outside hot spot (this is known with
9553 feedback only). Weight the size of function by number of registers
9554 to save as it is cheap to use one or two push instructions but very
9555 slow to use many of them. */
9559 || (flag_branch_probabilities
9562 else
9565 }
9567 frame->save_regs_using_mov
9569 /* If static stack checking is enabled and done with probes,
9570 the registers need to be saved before allocating the frame. */
9573 /* Skip return address. */
9576 /* Skip pushed static chain. */
9580 /* Skip saved base pointer. */
9585 /* The traditional frame pointer location is at the top of the frame. */
9588 /* Register save area */
9592 /* On SEH target, registers are pushed just before the frame pointer
9593 location. */
9597 /* Align and set SSE register save area. */
9599 {
9600 /* The only ABI that has saved SSE registers (Win64) also has a
9601 16-byte aligned default stack, and thus we don't need to be
9602 within the re-aligned local stack frame to save them. */
9606 }
9609 /* The re-aligned stack starts here. Values before this point are not
9610 directly comparable with values below this point. In order to make
9611 sure that no value happens to be the same before and after, force
9612 the alignment computation below to add a non-zero value. */
9616 /* Va-arg area */
9620 /* Align start of frame for local function. */
9629 /* Frame pointer points here. */
9634 /* Add outgoing arguments area. Can be skipped if we eliminated
9635 all the function calls as dead code.
9636 Skipping is however impossible when function calls alloca. Alloca
9637 expander assumes that last crtl->outgoing_args_size
9638 of stack frame are unused. */
9642 {
9645 }
9646 else
9649 /* Align stack boundary. Only needed if we're calling another function
9650 or using alloca. */
9655 /* We've reached end of stack frame. */
9658 /* Size prologue needs to allocate. */
9669 {
9675 }
9676 else
9680 /* The SEH frame pointer location is near the bottom of the frame.
9681 This is enforced by the fact that the difference between the
9682 stack pointer and the frame pointer is limited to 240 bytes in
9683 the unwind data structure. */
9685 {
9686 HOST_WIDE_INT diff;
9688 /* If we can leave the frame pointer where it is, do so. Also, returns
9689 the establisher frame for __builtin_frame_address (0). */
9694 {
9695 /* Ideally we'd determine what portion of the local stack frame
9696 (within the constraint of the lowest 240) is most heavily used.
9697 But without that complication, simply bias the frame pointer
9698 by 128 bytes so as to maximize the amount of the local stack
9699 frame that is addressable with 8-bit offsets. */
9701 }
9702 }
9703 }
9705 /* This is semi-inlined memory_address_length, but simplified
9706 since we know that we're always dealing with reg+offset, and
9707 to avoid having to create and discard all that rtl. */
9711 {
9715 {
9716 /* EBP and R13 cannot be encoded without an offset. */
9718 }
9722 /* ESP and R12 must be encoded with a SIB byte. */
9724 len++;
9727 }
9729 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9730 The valid base registers are taken from CFUN->MACHINE->FS. */
9732 static rtx
9734 {
9740 {
9741 /* Choose the base register most likely to allow the most scheduling
9742 opportunities. Generally FP is valid throughout the function,
9743 while DRAP must be reloaded within the epilogue. But choose either
9744 over the SP due to increased encoding size. */
9747 {
9750 }
9752 {
9755 }
9757 {
9760 }
9761 }
9762 else
9763 {
9764 HOST_WIDE_INT toffset;
9767 /* Choose the base register with the smallest address encoding.
9768 With a tie, choose FP > DRAP > SP. */
9770 {
9774 }
9776 {
9780 {
9784 }
9785 }
9787 {
9791 {
9795 }
9796 }
9797 }
9801 }
9803 /* Emit code to save registers in the prologue. */
9805 static void
9807 {
9809 rtx insn;
9813 {
9816 }
9817 }
9819 /* Emit a single register save at CFA - CFA_OFFSET. */
9821 static void
9823 HOST_WIDE_INT cfa_offset)
9824 {
9832 /* For SSE saves, we need to indicate the 128-bit alignment. */
9843 /* When saving registers into a re-aligned local stack frame, avoid
9844 any tricky guessing by dwarf2out. */
9846 {
9850 {
9851 /* A bit of a hack. We force the DRAP register to be saved in
9852 the re-aligned stack frame, which provides us with a copy
9853 of the CFA that will last past the prologue. Install it. */
9859 }
9860 else
9861 {
9862 /* The frame pointer is a stable reference within the
9863 aligned frame. Use it. */
9870 }
9871 }
9873 /* The memory may not be relative to the current CFA register,
9874 which means that we may need to generate a new pattern for
9875 use by the unwind info. */
9877 {
9882 }
9883 }
9885 /* Emit code to save registers using MOV insns.
9886 First register is stored at CFA - CFA_OFFSET. */
9887 static void
9889 {
9894 {
9897 }
9898 }
9900 /* Emit code to save SSE registers using MOV insns.
9901 First register is stored at CFA - CFA_OFFSET. */
9902 static void
9904 {
9909 {
9912 }
9913 }
9917 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9918 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9919 Don't add the note if the previously saved value will be left untouched
9920 within stack red-zone till return, as unwinders can find the same value
9921 in the register and on the stack. */
9923 static void
9925 {
9931 {
9934 }
9935 else
9936 queued_cfa_restores
9938 }
9940 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9942 static void
9944 {
9945 rtx last;
9949 ;
9954 }
9956 /* Expand prologue or epilogue stack adjustment.
9957 The pattern exist to put a dependency on all ebp-based memory accesses.
9958 STYLE should be negative if instructions should be marked as frame related,
9959 zero if %r11 register is live and cannot be freely used and positive
9960 otherwise. */
9962 static void
9965 {
9967 rtx insn;
9974 else
9975 {
9976 rtx tmp;
9977 /* r11 is used by indirect sibcall return as well, set before the
9978 epilogue and used after the epilogue. */
9981 else
9982 {
9986 }
9992 }
9999 {
10000 rtx r;
10010 }
10012 {
10015 {
10019 }
10020 }
10023 {
10028 {
10031 }
10033 {
10036 }
10037 else
10038 {
10039 /* Else there are two possibilities: SP itself, which we set
10040 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10041 taken care of this by hand along the eh_return path. */
10044 }
10048 }
10049 }
10051 /* Find an available register to be used as dynamic realign argument
10052 pointer regsiter. Such a register will be written in prologue and
10053 used in begin of body, so it must not be
10054 1. parameter passing register.
10055 2. GOT pointer.
10056 We reuse static-chain register if it is available. Otherwise, we
10057 use DI for i386 and R13 for x86-64. We chose R13 since it has
10058 shorter encoding.
10060 Return: the regno of chosen register. */
10062 static unsigned int
10064 {
10068 {
10069 /* Use R13 for nested function or function need static chain.
10070 Since function with tail call may use any caller-saved
10071 registers in epilogue, DRAP must not use caller-saved
10072 register in such case. */
10077 }
10078 else
10079 {
10080 /* Use DI for nested function or function need static chain.
10081 Since function with tail call may use any caller-saved
10082 registers in epilogue, DRAP must not use caller-saved
10083 register in such case. */
10087 /* Reuse static chain register if it isn't used for parameter
10088 passing. */
10090 {
10094 }
10096 }
10097 }
10099 /* Return minimum incoming stack alignment. */
10101 static unsigned int
10103 {
10106 /* Prefer the one specified at command line. */
10109 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10110 if -mstackrealign is used, it isn't used for sibcall check and
10111 estimated stack alignment is 128bit. */
10113 && !TARGET_64BIT
10114 && ix86_force_align_arg_pointer
10117 else
10120 /* Incoming stack alignment can be changed on individual functions
10121 via force_align_arg_pointer attribute. We use the smallest
10122 incoming stack boundary. */
10128 /* The incoming stack frame has to be aligned at least at
10129 parm_stack_boundary. */
10133 /* Stack at entrance of main is aligned by runtime. We use the
10134 smallest incoming stack boundary. */
10142 }
10144 /* Update incoming stack boundary and estimated stack alignment. */
10146 static void
10148 {
10149 ix86_incoming_stack_boundary
10152 /* x86_64 vararg needs 16byte stack alignment for register save
10153 area. */
10158 }
10160 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10161 needed or an rtx for DRAP otherwise. */
10163 static rtx
10165 {
10170 {
10171 /* Assign DRAP to vDRAP and returns vDRAP */
10173 rtx drap_vreg;
10174 rtx arg_ptr;
10187 {
10190 }
10192 }
10193 else
10195 }
10197 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10199 static rtx
10201 {
10203 }
10206 rtx reg;
10208 };
10210 /* Return a short-lived scratch register for use on function entry.
10211 In 32-bit mode, it is valid only after the registers are saved
10212 in the prologue. This register must be released by means of
10213 release_scratch_register_on_entry once it is dead. */
10215 static void
10217 {
10223 {
10224 /* We always use R11 in 64-bit mode. */
10226 }
10227 else
10228 {
10230 bool fastcall_p
10232 bool thiscall_p
10236 int drap_regno
10239 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10240 for the static chain register. */
10244 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10245 for the static chain register. */
10250 /* ecx is the static chain register. */
10252 && !static_chain_p
10257 /* esi is the static chain register. */
10263 else
10264 {
10267 }
10268 }
10272 {
10275 }
10276 }
10278 /* Release a scratch register obtained from the preceding function. */
10280 static void
10282 {
10284 {
10288 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10294 }
10295 }
10297 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10299 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10301 static void
10303 {
10304 /* We skip the probe for the first interval + a small dope of 4 words and
10305 probe that many bytes past the specified size to maintain a protection
10306 area at the botton of the stack. */
10310 /* See if we have a constant small number of probes to generate. If so,
10311 that's the easy case. The run-time loop is made up of 11 insns in the
10312 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10313 for n # of intervals. */
10315 {
10319 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10320 values of N from 1 until it exceeds SIZE. If only one probe is
10321 needed, this will not generate any code. Then adjust and probe
10322 to PROBE_INTERVAL + SIZE. */
10324 {
10326 {
10329 }
10330 else
10337 }
10341 else
10349 /* Adjust back to account for the additional first interval. */
10353 }
10355 /* Otherwise, do the same as above, but in a loop. Note that we must be
10356 extra careful with variables wrapping around because we might be at
10357 the very top (or the very bottom) of the address space and we have
10358 to be able to handle this case properly; in particular, we use an
10359 equality test for the loop condition. */
10360 else
10361 {
10362 HOST_WIDE_INT rounded_size;
10368 /* Step 1: round SIZE to the previous multiple of the interval. */
10373 /* Step 2: compute initial and final value of the loop counter. */
10375 /* SP = SP_0 + PROBE_INTERVAL. */
10380 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10384 stack_pointer_rtx)));
10387 /* Step 3: the loop
10389 while (SP != LAST_ADDR)
10390 {
10391 SP = SP + PROBE_INTERVAL
10392 probe at SP
10393 }
10395 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10396 values of N from 1 until it is equal to ROUNDED_SIZE. */
10401 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10402 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10405 {
10410 }
10412 /* Adjust back to account for the additional first interval. */
10418 }
10422 /* Even if the stack pointer isn't the CFA register, we need to correctly
10423 describe the adjustments made to it, in particular differentiate the
10424 frame-related ones from the frame-unrelated ones. */
10426 {
10439 }
10441 /* Make sure nothing is scheduled before we are done. */
10443 }
10445 /* Adjust the stack pointer up to REG while probing it. */
10449 {
10459 /* Jump to END_LAB if SP == LAST_ADDR. */
10467 /* SP = SP + PROBE_INTERVAL. */
10471 /* Probe at SP. */
10482 }
10484 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10485 inclusive. These are offsets from the current stack pointer. */
10487 static void
10489 {
10490 /* See if we have a constant small number of probes to generate. If so,
10491 that's the easy case. The run-time loop is made up of 7 insns in the
10492 generic case while the compile-time loop is made up of n insns for n #
10493 of intervals. */
10495 {
10496 HOST_WIDE_INT i;
10498 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10499 it exceeds SIZE. If only one probe is needed, this will not
10500 generate any code. Then probe at FIRST + SIZE. */
10507 }
10509 /* Otherwise, do the same as above, but in a loop. Note that we must be
10510 extra careful with variables wrapping around because we might be at
10511 the very top (or the very bottom) of the address space and we have
10512 to be able to handle this case properly; in particular, we use an
10513 equality test for the loop condition. */
10514 else
10515 {
10522 /* Step 1: round SIZE to the previous multiple of the interval. */
10527 /* Step 2: compute initial and final value of the loop counter. */
10529 /* TEST_OFFSET = FIRST. */
10532 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10536 /* Step 3: the loop
10538 while (TEST_ADDR != LAST_ADDR)
10539 {
10540 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10541 probe at TEST_ADDR
10542 }
10544 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10545 until it is equal to ROUNDED_SIZE. */
10550 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10551 that SIZE is equal to ROUNDED_SIZE. */
10556 stack_pointer_rtx,
10561 }
10563 /* Make sure nothing is scheduled before we are done. */
10565 }
10567 /* Probe a range of stack addresses from REG to END, inclusive. These are
10568 offsets from the current stack pointer. */
10572 {
10582 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10590 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10594 /* Probe at TEST_ADDR. */
10607 }
10609 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10610 to be generated in correct form. */
10611 static void
10613 {
10614 /* Check if stack realign is really needed after reload, and
10615 stores result in cfun */
10616 unsigned int incoming_stack_boundary
10625 {
10626 /* After stack_realign_needed is finalized, we can't no longer
10627 change it. */
10630 }
10632 /* If the only reason for frame_pointer_needed is that we conservatively
10633 assumed stack realignment might be needed, but in the end nothing that
10634 needed the stack alignment had been spilled, clear frame_pointer_needed
10635 and say we don't need stack realignment. */
10637 && frame_pointer_needed
10639 && flag_omit_frame_pointer
10641 && !ix86_current_function_calls_tls_descriptor
10650 {
10652 basic_block bb;
10659 HARD_FRAME_POINTER_REGNUM);
10661 {
10662 rtx insn;
10666 set_up_by_prologue))
10667 {
10671 }
10672 }
10674 /* If drap has been set, but it actually isn't live at the start
10675 of the function, there is no reason to set it up. */
10677 {
10680 {
10683 }
10684 }
10685 else
10700 }
10704 }
10706 /* Expand the prologue into a bunch of separate insns. */
10708 void
10710 {
10715 HOST_WIDE_INT allocate;
10721 /* DRAP should not coexist with stack_realign_fp */
10726 /* Initialize CFA state for before the prologue. */
10730 /* Track SP offset to the CFA. We continue tracking this after we've
10731 swapped the CFA register away from SP. In the case of re-alignment
10732 this is fudged; we're interested to offsets within the local frame. */
10739 {
10740 /* We should have already generated an error for any use of
10741 ms_hook on a nested function. */
10744 /* Check if profiling is active and we shall use profiling before
10745 prologue variant. If so sorry. */
10750 /* In ix86_asm_output_function_label we emitted:
10751 8b ff movl.s %edi,%edi
10752 55 push %ebp
10753 8b ec movl.s %esp,%ebp
10755 This matches the hookable function prologue in Win32 API
10756 functions in Microsoft Windows XP Service Pack 2 and newer.
10757 Wine uses this to enable Windows apps to hook the Win32 API
10758 functions provided by Wine.
10760 What that means is that we've already set up the frame pointer. */
10764 {
10767 /* We've decided to use the frame pointer already set up.
10768 Describe this to the unwinder by pretending that both
10769 push and mov insns happen right here.
10771 Putting the unwind info here at the end of the ms_hook
10772 is done so that we can make absolutely certain we get
10773 the required byte sequence at the start of the function,
10774 rather than relying on an assembler that can produce
10775 the exact encoding required.
10777 However it does mean (in the unpatched case) that we have
10778 a 1 insn window where the asynchronous unwind info is
10779 incorrect. However, if we placed the unwind info at
10780 its correct location we would have incorrect unwind info
10781 in the patched case. Which is probably all moot since
10782 I don't expect Wine generates dwarf2 unwind info for the
10783 system libraries that use this feature. */
10789 stack_pointer_rtx);
10797 /* Note that gen_push incremented m->fs.cfa_offset, even
10798 though we didn't emit the push insn here. */
10802 }
10803 else
10804 {
10805 /* The frame pointer is not needed so pop %ebp again.
10806 This leaves us with a pristine state. */
10808 }
10809 }
10811 /* The first insn of a function that accepts its static chain on the
10812 stack is to push the register that would be filled in by a direct
10813 call. This insn will be skipped by the trampoline. */
10815 {
10819 /* We don't want to interpret this push insn as a register save,
10820 only as a stack adjustment. The real copy of the register as
10821 a save will be done later, if needed. */
10826 }
10828 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10829 of DRAP is needed and stack realignment is really needed after reload */
10831 {
10834 /* Only need to push parameter pointer reg if it is caller saved. */
10836 {
10837 /* Push arg pointer reg */
10840 }
10842 /* Grab the argument pointer. */
10849 /* Align the stack. */
10851 stack_pointer_rtx,
10855 /* Replicate the return address on the stack so that return
10856 address can be reached via (argp - 1) slot. This is needed
10857 to implement macro RETURN_ADDR_RTX and intrinsic function
10858 expand_builtin_return_addr etc. */
10864 /* For the purposes of frame and register save area addressing,
10865 we've started over with a new frame. */
10868 }
10874 {
10875 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10876 slower on all targets. Also sdb doesn't like it. */
10880 /* Push registers now, before setting the frame pointer
10881 on SEH target. */
10883 && TARGET_SEH
10885 {
10889 }
10892 {
10900 }
10901 }
10904 {
10905 /* If saving registers via PUSH, do so now. */
10907 {
10911 }
10913 /* When using red zone we may start register saving before allocating
10914 the stack frame saving one cycle of the prologue. However, avoid
10915 doing this if we have to probe the stack; at least on x86_64 the
10916 stack probe can turn into a call that clobbers a red zone location. */
10918 && (! TARGET_STACK_PROBE
10920 {
10923 }
10924 }
10927 {
10931 /* The computation of the size of the re-aligned stack frame means
10932 that we must allocate the size of the register save area before
10933 performing the actual alignment. Otherwise we cannot guarantee
10934 that there's enough storage above the realignment point. */
10941 /* Align the stack. */
10943 stack_pointer_rtx,
10946 /* For the purposes of register save area addressing, the stack
10947 pointer is no longer valid. As for the value of sp_offset,
10948 see ix86_compute_frame_layout, which we need to match in order
10949 to pass verification of stack_pointer_offset at the end. */
10952 }
10957 {
10958 /* We start to count from ARG_POINTER. */
10961 /* If it was realigned, take into account the fake frame. */
10963 {
10970 /* This over-estimates by 1 minimal-stack-alignment-unit but
10971 mitigates that by counting in the new return address slot. */
10972 current_function_dynamic_stack_size
10974 }
10977 }
10979 /* On SEH target with very large frame size, allocate an area to save
10980 SSE registers (as the very large allocation won't be described). */
10984 {
10985 HOST_WIDE_INT sse_size =
10990 /* No need to do stack checking as the area will be immediately
10991 written. */
10998 }
11000 /* The stack has already been decremented by the instruction calling us
11001 so probe if the size is non-negative to preserve the protection area. */
11003 {
11004 /* We expect the registers to be saved when probes are used. */
11008 {
11011 {
11014 }
11015 }
11016 else
11017 {
11024 {
11026 {
11029 }
11030 else
11032 }
11033 else
11034 {
11036 {
11040 }
11041 else
11043 }
11044 }
11045 }
11048 ;
11051 {
11055 }
11056 else
11057 {
11069 {
11072 /* Note that SEH directives need to continue tracking the stack
11073 pointer even after the frame pointer has been set up. */
11075 {
11079 }
11080 }
11083 {
11088 {
11092 }
11093 }
11098 /* Use the fact that AX still contains ALLOCATE. */
11100 ? gen_pro_epilogue_adjust_stack_di_sub
11107 {
11115 }
11118 /* Use stack_pointer_rtx for relative addressing so that code
11119 works for realigned stack, too. */
11121 {
11128 }
11130 {
11135 }
11136 }
11139 /* If we havn't already set up the frame pointer, do so now. */
11141 {
11153 }
11161 /* We don't use pic-register for pe-coff target. */
11163 && !TARGET_PECOFF
11166 {
11173 }
11176 {
11178 {
11180 {
11190 label));
11194 }
11195 else
11197 }
11198 else
11199 {
11203 }
11204 }
11206 /* In the pic_reg_used case, make sure that the got load isn't deleted
11207 when mcount needs it. Blockage to avoid call movement across mcount
11208 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11209 note. */
11214 {
11215 /* vDRAP is setup but after reload it turns out stack realign
11216 isn't necessary, here we will emit prologue to setup DRAP
11217 without stack realign adjustment */
11220 }
11222 /* Prevent instructions from being scheduled into register save push
11223 sequence when access to the redzone area is done through frame pointer.
11224 The offset between the frame pointer and the stack pointer is calculated
11225 relative to the value of the stack pointer at the end of the function
11226 prologue, and moving instructions that access redzone area via frame
11227 pointer inside push sequence violates this assumption. */
11231 /* Emit cld instruction if stringops are used in the function. */
11235 /* SEH requires that the prologue end within 256 bytes of the start of
11236 the function. Prevent instruction schedules that would extend that.
11237 Further, prevent alloca modifications to the stack pointer from being
11238 combined with prologue modifications. */
11241 }
11243 /* Emit code to restore REG using a POP insn. */
11245 static void
11247 {
11256 {
11257 /* Previously we'd represented the CFA as an expression
11258 like *(%ebp - 8). We've just popped that value from
11259 the stack, which means we need to reset the CFA to
11260 the drap register. This will remain until we restore
11261 the stack pointer. */
11265 /* This means that the DRAP register is valid for addressing too. */
11268 }
11271 {
11278 }
11280 /* When the frame pointer is the CFA, and we pop it, we are
11281 swapping back to the stack pointer as the CFA. This happens
11282 for stack frames that don't allocate other data, so we assume
11283 the stack pointer is now pointing at the return address, i.e.
11284 the function entry state, which makes the offset be 1 word. */
11286 {
11289 {
11297 }
11298 }
11299 }
11301 /* Emit code to restore saved registers using POP insns. */
11303 static void
11305 {
11311 }
11313 /* Emit code and notes for the LEAVE instruction. */
11315 static void
11317 {
11329 {
11337 }
11340 }
11342 /* Emit code to restore saved registers using MOV insns.
11343 First register is restored from CFA - CFA_OFFSET. */
11344 static void
11347 {
11353 {
11362 {
11363 /* Previously we'd represented the CFA as an expression
11364 like *(%ebp - 8). We've just popped that value from
11365 the stack, which means we need to reset the CFA to
11366 the drap register. This will remain until we restore
11367 the stack pointer. */
11371 /* This means that the DRAP register is valid for addressing. */
11373 }
11374 else
11378 }
11379 }
11381 /* Emit code to restore saved registers using MOV insns.
11382 First register is restored from CFA - CFA_OFFSET. */
11383 static void
11386 {
11391 {
11393 rtx mem;
11403 }
11404 }
11406 /* Restore function stack, frame, and registers. */
11408 void
11410 {
11426 /* The FP must be valid if the frame pointer is present. */
11431 /* We must have *some* valid pointer to the stack frame. */
11434 /* The DRAP is never valid at this point. */
11437 /* See the comment about red zone and frame
11438 pointer usage in ix86_expand_prologue. */
11445 /* Determine the CFA offset of the end of the red-zone. */
11448 {
11449 /* The red-zone begins below the return address. */
11452 /* When the register save area is in the aligned portion of
11453 the stack, determine the maximum runtime displacement that
11454 matches up with the aligned frame. */
11458 }
11460 /* Special care must be taken for the normal return case of a function
11461 using eh_return: the eax and edx registers are marked as saved, but
11462 not restored along this path. Adjust the save location to match. */
11466 /* EH_RETURN requires the use of moves to function properly. */
11469 /* SEH requires the use of pops to identify the epilogue. */
11472 /* If we're only restoring one register and sp is not valid then
11473 using a move instruction to restore the register since it's
11474 less work than reloading sp and popping the register. */
11487 && TARGET_USE_LEAVE
11491 else
11495 {
11496 /* Ensure that the entire register save area is addressable via
11497 the stack pointer, if we will restore via sp. */
11502 {
11506 style,
11508 }
11509 }
11511 /* If there are any SSE registers to restore, then we have to do it
11512 via moves, since there's obviously no pop for SSE regs. */
11518 {
11519 rtx t;
11524 /* eh_return epilogues need %ecx added to the stack pointer. */
11526 {
11529 /* Stack align doesn't work with eh_return. */
11531 /* Neither does regparm nested functions. */
11535 {
11543 /* Note that we use SA as a temporary CFA, as the return
11544 address is at the proper place relative to it. We
11545 pretend this happens at the FP restore insn because
11546 prior to this insn the FP would be stored at the wrong
11547 offset relative to SA, and after this insn we have no
11548 other reasonable register to use for the CFA. We don't
11549 bother resetting the CFA to the SP for the duration of
11550 the return insn. */
11563 }
11564 else
11565 {
11573 {
11577 UNITS_PER_WORD));
11579 }
11580 }
11583 }
11584 }
11585 else
11586 {
11587 /* SEH requires that the function end with (1) a stack adjustment
11588 if necessary, (2) a sequence of pops, and (3) a return or
11589 jump instruction. Prevent insns from the function body from
11590 being scheduled into this sequence. */
11592 {
11593 /* Prevent a catch region from being adjacent to the standard
11594 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11595 several other flags that would be interesting to test are
11596 not yet set up. */
11599 else
11601 }
11603 /* First step is to deallocate the stack frame so that we can
11604 pop the registers. Also do it on SEH target for very large
11605 frame as the emitted instructions aren't allowed by the ABI in
11606 epilogues. */
11608 || (TARGET_SEH
11611 {
11616 }
11618 {
11622 style,
11624 }
11627 }
11629 /* If we used a stack pointer and haven't already got rid of it,
11630 then do so now. */
11632 {
11633 /* If the stack pointer is valid and pointing at the frame
11634 pointer store address, then we only need a pop. */
11637 /* Leave results in shorter dependency chains on CPUs that are
11638 able to grok it fast. */
11643 else
11644 {
11646 hard_frame_pointer_rtx,
11649 }
11650 }
11653 {
11655 rtx insn;
11681 }
11683 /* At this point the stack pointer must be valid, and we must have
11684 restored all of the registers. We may not have deallocated the
11685 entire stack frame. We've delayed this until now because it may
11686 be possible to merge the local stack deallocation with the
11687 deallocation forced by ix86_static_chain_on_stack. */
11692 {
11696 }
11697 else
11700 /* Sibcall epilogues don't want a return instruction. */
11702 {
11705 }
11708 {
11711 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11712 address, do explicit add, and jump indirectly to the caller. */
11715 {
11717 rtx insn;
11719 /* There is no "pascal" calling convention in any 64bit ABI. */
11735 }
11736 else
11738 }
11739 else
11742 /* Restore the state back to the state from the prologue,
11743 so that it's correct for the next epilogue. */
11745 }
11747 /* Reset from the function's potential modifications. */
11749 static void
11751 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11752 {
11755 #if TARGET_MACHO
11756 /* Mach-O doesn't support labels at the end of objects, so if
11757 it looks like we might want one, insert a NOP. */
11758 {
11764 {
11765 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11766 notes only, instead set their CODE_LABEL_NUMBER to -1,
11767 otherwise there would be code generation differences
11768 in between -g and -g0. */
11772 }
11782 }
11783 #endif
11785 }
11787 /* Return a scratch register to use in the split stack prologue. The
11788 split stack prologue is used for -fsplit-stack. It is the first
11789 instructions in the function, even before the regular prologue.
11790 The scratch register can be any caller-saved register which is not
11791 used for parameters or for the static chain. */
11793 static unsigned int
11795 {
11798 else
11799 {
11812 {
11814 {
11818 }
11820 }
11822 {
11826 }
11828 {
11831 else
11832 {
11834 {
11838 }
11840 }
11841 }
11842 else
11843 {
11844 /* FIXME: We could make this work by pushing a register
11845 around the addition and comparison. */
11848 }
11849 }
11850 }
11852 /* A SYMBOL_REF for the function which allocates new stackspace for
11853 -fsplit-stack. */
11857 /* A SYMBOL_REF for the more stack function when using the large
11858 model. */
11862 /* Handle -fsplit-stack. These are the first instructions in the
11863 function, even before the regular prologue. */
11865 void
11867 {
11869 HOST_WIDE_INT allocate;
11874 rtx fn;
11882 /* This is the label we will branch to if we have enough stack
11883 space. We expect the basic block reordering pass to reverse this
11884 branch if optimizing, so that we branch in the unlikely case. */
11887 /* We need to compare the stack pointer minus the frame size with
11888 the stack boundary in the TCB. The stack boundary always gives
11889 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11890 can compare directly. Otherwise we need to do an addition. */
11893 UNSPEC_STACK_CHECK);
11898 else
11899 {
11901 rtx offset;
11903 /* We need a scratch register to hold the stack pointer minus
11904 the required frame size. Since this is the very start of the
11905 function, the scratch register can be any caller-saved
11906 register which is not used for parameters. */
11913 {
11914 /* We don't use ix86_gen_add3 in this case because it will
11915 want to split to lea, but when not optimizing the insn
11916 will not be split after this point. */
11919 offset)));
11920 }
11921 else
11922 {
11925 stack_pointer_rtx));
11926 }
11928 }
11934 /* Mark the jump as very likely to be taken. */
11942 /* Get more stack space. We pass in the desired stack space and the
11943 size of the arguments to copy to the new stack. In 32-bit mode
11944 we push the parameters; __morestack will return on a new stack
11945 anyhow. In 64-bit mode we pass the parameters in r10 and
11946 r11. */
11951 {
11957 /* If this function uses a static chain, it will be in %r10.
11958 Preserve it across the call to __morestack. */
11960 {
11961 rtx rax;
11966 }
11970 {
11971 HOST_WIDE_INT argval;
11974 /* When using the large model we need to load the address
11975 into a register, and we've run out of registers. So we
11976 switch to a different calling convention, and we call a
11977 different function: __morestack_large. We pass the
11978 argument size in the upper 32 bits of r10 and pass the
11979 frame size in the lower 32 bits. */
11984 split_stack_fn_large =
11988 {
11998 UNSPEC_GOT);
12004 }
12005 else
12012 }
12013 else
12014 {
12018 }
12021 }
12022 else
12023 {
12026 }
12032 /* In order to make call/return prediction work right, we now need
12033 to execute a return instruction. See
12034 libgcc/config/i386/morestack.S for the details on how this works.
12036 For flow purposes gcc must not see this as a return
12037 instruction--we need control flow to continue at the subsequent
12038 label. Therefore, we use an unspec. */
12042 /* If we are in 64-bit mode and this function uses a static chain,
12043 we saved %r10 in %rax before calling _morestack. */
12048 /* If this function calls va_start, we need to store a pointer to
12049 the arguments on the old stack, because they may not have been
12050 all copied to the new stack. At this point the old stack can be
12051 found at the frame pointer value used by __morestack, because
12052 __morestack has set that up before calling back to us. Here we
12053 store that pointer in a scratch register, and in
12054 ix86_expand_prologue we store the scratch register in a stack
12055 slot. */
12057 {
12059 rtx frame_reg;
12066 /* 64-bit:
12067 fp -> old fp value
12068 return address within this function
12069 return address of caller of this function
12070 stack arguments
12071 So we add three words to get to the stack arguments.
12073 32-bit:
12074 fp -> old fp value
12075 return address within this function
12076 first argument to __morestack
12077 second argument to __morestack
12078 return address of caller of this function
12079 stack arguments
12080 So we add five words to get to the stack arguments.
12081 */
12092 }
12097 /* If this function calls va_start, we now have to set the scratch
12098 register for the case where we do not call __morestack. In this
12099 case we need to set it based on the stack pointer. */
12101 {
12108 }
12109 }
12111 /* We may have to tell the dataflow pass that the split stack prologue
12112 is initializing a scratch register. */
12114 static void
12116 {
12118 {
12121 }
12122 }
12123 \f
12124 /* Extract the parts of an RTL expression that is a valid memory address
12125 for an instruction. Return 0 if the structure of the address is
12126 grossly off. Return -1 if the address contains ASHIFT, so it is not
12127 strictly valid, but still used for computing length of lea instruction. */
12129 int
12131 {
12136 rtx tmp;
12140 /* Allow zero-extended SImode addresses,
12141 they will be emitted with addr32 prefix. */
12143 {
12146 {
12150 }
12153 {
12160 }
12161 }
12163 /* Allow SImode subregs of DImode addresses,
12164 they will be emitted with addr32 prefix. */
12166 {
12169 {
12173 }
12174 }
12179 {
12182 else
12184 }
12186 {
12191 do
12192 {
12197 }
12204 {
12207 {
12232 /* FALLTHRU */
12236 && TARGET_TLS_DIRECT_SEG_REFS
12239 else
12246 /* FALLTHRU */
12253 else
12268 }
12269 }
12270 }
12272 {
12275 }
12277 {
12278 /* We're called for lea too, which implements ashift on occasion. */
12288 }
12289 else
12293 {
12295 ;
12298 ;
12299 else
12301 }
12303 /* Extract the integral value of scale. */
12305 {
12309 }
12314 /* Avoid useless 0 displacement. */
12318 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12323 {
12324 rtx tmp;
12327 }
12329 /* Special case: %ebp cannot be encoded as a base without a displacement.
12330 Similarly %r13. */
12332 && base_reg
12341 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12342 Avoid this by transforming to [%esi+0].
12343 Reload calls address legitimization without cfun defined, so we need
12344 to test cfun for being non-NULL. */
12350 /* Special case: encode reg+reg instead of reg*2. */
12354 /* Special case: scaling cannot be encoded without base or displacement. */
12365 }
12366 \f
12367 /* Return cost of the memory address x.
12368 For i386, it is better to use a complex address than let gcc copy
12369 the address into a reg and make a new pseudo. But not if the address
12370 requires to two regs - that would mean more pseudos with longer
12371 lifetimes. */
12372 static int
12374 addr_space_t as ATTRIBUTE_UNUSED,
12376 {
12388 /* Attempt to minimize number of registers in the address. */
12394 cost++;
12401 cost++;
12403 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12404 since it's predecode logic can't detect the length of instructions
12405 and it degenerates to vector decoded. Increase cost of such
12406 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12407 to split such addresses or even refuse such addresses at all.
12409 Following addressing modes are affected:
12410 [base+scale*index]
12411 [scale*index+disp]
12412 [base+index]
12414 The first and last case may be avoidable by explicitly coding the zero in
12415 memory address, but I don't have AMD-K6 machine handy to check this
12416 theory. */
12425 }
12426 \f
12427 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12428 this is used for to form addresses to local data when -fPIC is in
12429 use. */
12431 static bool
12433 {
12436 }
12438 /* Determine if a given RTX is a valid constant. We already know this
12439 satisfies CONSTANT_P. */
12441 static bool
12443 {
12445 {
12450 {
12454 }
12459 /* Only some unspecs are valid as "constants". */
12462 {
12478 }
12480 /* We must have drilled down to a symbol. */
12485 /* FALLTHRU */
12488 /* TLS symbols are never valid. */
12492 /* DLLIMPORT symbols are never valid. */
12497 #if TARGET_MACHO
12498 /* mdynamic-no-pic */
12501 #endif
12517 }
12519 /* Otherwise we handle everything else in the move patterns. */
12521 }
12523 /* Determine if it's legal to put X into the constant pool. This
12524 is not possible for the address of thread-local symbols, which
12525 is checked above. */
12527 static bool
12529 {
12530 /* We can always put integral constants and vectors in memory. */
12532 {
12540 }
12542 }
12544 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12545 otherwise zero. */
12547 static bool
12549 {
12555 }
12558 /* Nonzero if the constant value X is a legitimate general operand
12559 when generating PIC code. It is given that flag_pic is on and
12560 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12562 bool
12564 {
12565 rtx inner;
12568 {
12575 /* Only some unspecs are valid as "constants". */
12578 {
12591 }
12592 /* FALLTHRU */
12600 }
12601 }
12603 /* Determine if a given CONST RTX is a valid memory displacement
12604 in PIC mode. */
12606 bool
12608 {
12611 /* In 64bit mode we can allow direct addresses of symbols and labels
12612 when they are not dynamic symbols. */
12614 {
12618 {
12642 /* FALLTHRU */
12645 /* TLS references should always be enclosed in UNSPEC.
12646 The dllimported symbol needs always to be resolved. */
12652 {
12660 /* Function-symbols need to be resolved only for
12661 large-model.
12662 For the small-model we don't need to resolve anything
12663 here. */
12668 /* Non-external symbols don't need to be resolved for
12669 large, and medium-model. */
12674 }
12683 }
12684 }
12690 {
12691 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12692 of GOT tables. We should not need these anyway. */
12704 }
12708 {
12713 }
12722 {
12726 /* We need to check for both symbols and labels because VxWorks loads
12727 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12728 details. */
12732 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12733 While ABI specify also 32bit relocation but we don't produce it in
12734 small PIC model at all. */
12756 }
12759 }
12761 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12762 replace the input X, or the original X if no replacement is called for.
12763 The output parameter *WIN is 1 if the calling macro should goto WIN,
12764 0 if it should not. */
12766 bool
12771 {
12772 /* Reload can generate:
12774 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12775 (reg:DI 97))
12776 (reg:DI 2 cx))
12778 This RTX is rejected from ix86_legitimate_address_p due to
12779 non-strictness of base register 97. Following this rejection,
12780 reload pushes all three components into separate registers,
12781 creating invalid memory address RTX.
12783 Following code reloads only the invalid part of the
12784 memory address RTX. */
12790 {
12796 {
12801 }
12805 {
12810 }
12814 }
12817 }
12819 /* Determine if op is suitable RTX for an address register.
12820 Return naked register if a register or a register subreg is
12821 found, otherwise return NULL_RTX. */
12823 static rtx
12825 {
12828 /* Only SImode or DImode registers can form the address. */
12835 {
12843 /* Don't allow SUBREGs that span more than a word. It can
12844 lead to spill failures when the register is one word out
12845 of a two word structure. */
12849 /* Allow only SUBREGs of non-eliminable hard registers. */
12852 }
12854 /* Op is not a register. */
12856 }
12858 /* Recognizes RTL expressions that are valid memory addresses for an
12859 instruction. The MODE argument is the machine mode for the MEM
12860 expression that wants to use this address.
12862 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12863 convert common non-canonical forms to canonical form so that they will
12864 be recognized. */
12866 static bool
12869 {
12872 HOST_WIDE_INT scale;
12876 /* Decomposition failed. */
12885 /* Validate base register. */
12887 {
12895 /* Base is not valid. */
12897 }
12899 /* Validate index register. */
12901 {
12909 /* Index is not valid. */
12911 }
12913 /* Index and base should have the same mode. */
12918 /* Address override works only on the (%reg) part of %fs:(%reg). */
12924 /* Validate scale factor. */
12926 {
12928 /* Scale without index. */
12932 /* Scale is not a valid multiplier. */
12934 }
12936 /* Validate displacement. */
12938 {
12943 {
12944 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12945 used. While ABI specify also 32bit relocations, we don't produce
12946 them at all and use IP relative instead. */
12953 /* 64bit address unspec. */
12973 /* Invalid address unspec. */
12975 }
12978 && (flag_pic
12979 || (TARGET_MACHO
12980 #if TARGET_MACHO
12981 && MACHOPIC_INDIRECT
12983 #endif
12984 )))
12985 {
12987 is_legitimate_pic:
12989 {
12990 /* foo@dtpoff(%rX) is ok. */
12997 /* Non-constant pic memory reference. */
12999 }
13002 /* Displacement is an invalid pic construct. */
13004 #if TARGET_MACHO
13007 /* displacment must be referenced via non_lazy_pointer */
13009 #endif
13011 /* This code used to verify that a symbolic pic displacement
13012 includes the pic_offset_table_rtx register.
13014 While this is good idea, unfortunately these constructs may
13015 be created by "adds using lea" optimization for incorrect
13016 code like:
13018 int a;
13019 int foo(int i)
13020 {
13021 return *(&a+i);
13022 }
13024 This code is nonsensical, but results in addressing
13025 GOT table with pic_offset_table_rtx base. We can't
13026 just refuse it easily, since it gets matched by
13027 "addsi3" pattern, that later gets split to lea in the
13028 case output register differs from input. While this
13029 can be handled by separate addsi pattern for this case
13030 that never results in lea, this seems to be easier and
13031 correct fix for crash to disable this test. */
13032 }
13039 /* Displacement is not constant. */
13043 /* Displacement is out of range. */
13045 /* In x32 mode, constant addresses are sign extended to 64bit, so
13046 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13051 }
13053 /* Everything looks valid. */
13055 }
13057 /* Determine if a given RTX is a valid constant address. */
13059 bool
13061 {
13063 }
13064 \f
13065 /* Return a unique alias set for the GOT. */
13067 static alias_set_type
13069 {
13074 }
13076 /* Return a legitimate reference for ORIG (an address) using the
13077 register REG. If REG is 0, a new pseudo is generated.
13079 There are two types of references that must be handled:
13081 1. Global data references must load the address from the GOT, via
13082 the PIC reg. An insn is emitted to do this load, and the reg is
13083 returned.
13085 2. Static data references, constant pool addresses, and code labels
13086 compute the address as an offset from the GOT, whose base is in
13087 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13088 differentiate them from global data objects. The returned
13089 address is the PIC reg + an unspec constant.
13091 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13092 reg also appears in the address. */
13094 static rtx
13096 {
13100 #if TARGET_MACHO
13102 {
13105 /* Use the generic Mach-O PIC machinery. */
13107 }
13108 #endif
13111 {
13115 }
13121 {
13122 rtx tmpreg;
13123 /* This symbol may be referenced via a displacement from the PIC
13124 base address (@GOTOFF). */
13131 {
13133 UNSPEC_GOTOFF);
13135 }
13136 else
13141 else
13146 {
13150 }
13151 else
13153 }
13155 {
13156 /* This symbol may be referenced via a displacement from the PIC
13157 base address (@GOTOFF). */
13164 {
13166 UNSPEC_GOTOFF);
13168 }
13169 else
13175 {
13178 }
13179 }
13181 /* We can't use @GOTOFF for text labels on VxWorks;
13182 see gotoff_operand. */
13184 {
13189 /* For x64 PE-COFF there is no GOT table. So we use address
13190 directly. */
13192 {
13200 }
13202 {
13210 /* Use directly gen_movsi, otherwise the address is loaded
13211 into register for CSE. We don't want to CSE this addresses,
13212 instead we CSE addresses from the GOT table, so skip this. */
13215 }
13216 else
13217 {
13218 /* This symbol must be referenced via a load from the
13219 Global Offset Table (@GOT). */
13235 }
13236 }
13237 else
13238 {
13241 {
13243 {
13246 }
13247 else
13249 }
13251 {
13254 /* We must match stuff we generate before. Assume the only
13255 unspecs that can get here are ours. Not that we could do
13256 anything with them anyway.... */
13262 }
13264 {
13267 /* Check first to see if this is a constant offset from a @GOTOFF
13268 symbol reference. */
13271 {
13273 {
13277 UNSPEC_GOTOFF);
13283 {
13286 }
13287 }
13288 else
13289 {
13292 {
13296 }
13297 }
13298 }
13299 else
13300 {
13303 new_rtx
13307 {
13310 {
13313 new_rtx
13315 }
13316 else
13318 }
13319 else
13320 {
13323 {
13326 }
13328 }
13329 }
13330 }
13331 }
13333 }
13334 \f
13335 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13337 static rtx
13339 {
13343 {
13348 }
13354 }
13356 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13360 static rtx
13362 {
13364 {
13370 }
13373 {
13375 UNSPEC_PLTOFF);
13378 }
13381 }
13383 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13387 rtx
13389 {
13391 {
13392 ix86_tls_module_base_symbol
13397 }
13400 }
13402 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13403 false if we expect this to be used for a memory address and true if
13404 we expect to load the address into a register. */
13406 static rtx
13408 {
13414 /* Fall back to global dynamic model if tool chain cannot support local
13415 dynamic. */
13422 {
13427 {
13430 else
13431 {
13434 }
13435 }
13438 {
13441 else
13451 }
13452 else
13453 {
13457 {
13459 rtx insns;
13462 emit_call_insn
13472 }
13473 else
13475 }
13482 {
13485 else
13486 {
13489 }
13490 }
13493 {
13498 else
13504 }
13505 else
13506 {
13510 {
13515 emit_call_insn
13520 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13521 share the LD_BASE result with other LD model accesses. */
13523 UNSPEC_TLS_LD_BASE);
13527 }
13528 else
13530 }
13538 {
13545 }
13550 {
13552 {
13553 /* The Sun linker took the AMD64 TLS spec literally
13554 and can only handle %rax as destination of the
13555 initial executable code sequence. */
13560 }
13562 /* Generate DImode references to avoid %fs:(%reg32)
13563 problems and linker IE->LE relaxation bug. */
13567 }
13569 {
13574 }
13576 {
13580 }
13581 else
13582 {
13585 }
13595 {
13600 }
13601 else
13602 {
13606 }
13616 {
13620 }
13621 else
13622 {
13626 }
13631 }
13634 }
13636 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13637 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13638 unique refptr-DECL symbol corresponding to symbol DECL. */
13641 htab_t dllimport_map;
13643 static tree
13645 {
13652 tree to;
13653 rtx rtl;
13680 else
13693 {
13695 #ifdef SUB_TARGET_RECORD_STUB
13697 #endif
13698 }
13707 }
13709 /* Expand SYMBOL into its corresponding far-addresse symbol.
13710 WANT_REG is true if we require the result be a register. */
13712 static rtx
13714 {
13715 tree imp_decl;
13716 rtx x;
13725 }
13727 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13728 true if we require the result be a register. */
13730 static rtx
13732 {
13733 tree imp_decl;
13734 rtx x;
13743 }
13745 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13746 is true if we require the result be a register. */
13748 static rtx
13750 {
13755 {
13762 {
13765 }
13766 }
13782 {
13785 }
13787 }
13789 /* Try machine-dependent ways of modifying an illegitimate address
13790 to be legitimate. If we find one, return the new, valid address.
13791 This macro is used in only one place: `memory_address' in explow.c.
13793 OLDX is the address as it was before break_out_memory_refs was called.
13794 In some cases it is useful to look at this to decide what needs to be done.
13796 It is always safe for this macro to do nothing. It exists to recognize
13797 opportunities to optimize the output.
13799 For the 80386, we handle X+REG by loading X into a register R and
13800 using R+REG. R will go in a general reg and indexing will be used.
13801 However, if REG is a broken-out memory address or multiplication,
13802 nothing needs to be done because REG can certainly go in a general reg.
13804 When -fpic is used, special handling is needed for symbolic references.
13805 See comments by legitimize_pic_address in i386.c for details. */
13807 static rtx
13810 {
13821 {
13825 }
13828 {
13832 }
13837 #if TARGET_MACHO
13840 #endif
13842 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13846 {
13851 }
13854 {
13855 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13860 {
13866 }
13871 {
13877 }
13879 /* Put multiply first if it isn't already. */
13881 {
13886 }
13888 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13889 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13890 created by virtual register instantiation, register elimination, and
13891 similar optimizations. */
13893 {
13899 }
13901 /* Canonicalize
13902 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13903 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13908 {
13909 rtx constant;
13913 {
13916 }
13918 {
13921 }
13922 else
13926 {
13933 }
13934 }
13940 {
13943 }
13946 {
13949 }
13957 {
13960 }
13966 {
13970 {
13973 }
13977 }
13980 {
13984 {
13987 }
13991 }
13992 }
13995 }
13996 \f
13997 /* Print an integer constant expression in assembler syntax. Addition
13998 and subtraction are the only arithmetic that may appear in these
13999 expressions. FILE is the stdio stream to write to, X is the rtx, and
14000 CODE is the operand print code from the output string. */
14002 static void
14004 {
14008 {
14017 else
14018 {
14021 /* Mark the decl as referenced so that cgraph will
14022 output the function. */
14026 #if TARGET_MACHO
14030 #endif
14032 }
14040 /* FALLTHRU */
14051 /* This used to output parentheses around the expression,
14052 but that does not work on the 386 (either ATT or BSD assembler). */
14058 {
14059 /* We can use %d if the number is <32 bits and positive. */
14064 else
14066 }
14067 else
14068 /* We can't handle floating point constants;
14069 TARGET_PRINT_OPERAND must handle them. */
14074 /* Some assemblers need integer constants to appear first. */
14076 {
14080 }
14081 else
14082 {
14087 }
14102 {
14106 }
14111 {
14130 /* FIXME: This might be @TPOFF in Sun ld too. */
14139 else
14149 else
14155 #if TARGET_MACHO
14160 #endif
14164 }
14169 }
14170 }
14172 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14173 We need to emit DTP-relative relocations. */
14175 static void ATTRIBUTE_UNUSED
14177 {
14182 {
14190 }
14191 }
14193 /* Return true if X is a representation of the PIC register. This copes
14194 with calls from ix86_find_base_term, where the register might have
14195 been replaced by a cselib value. */
14197 static bool
14199 {
14203 else
14205 }
14207 /* Helper function for ix86_delegitimize_address.
14208 Attempt to delegitimize TLS local-exec accesses. */
14210 static rtx
14212 {
14237 {
14242 }
14248 }
14250 /* In the name of slightly smaller debug output, and to cater to
14251 general assembler lossage, recognize PIC+GOTOFF and turn it back
14252 into a direct symbol reference.
14254 On Darwin, this is necessary to avoid a crash, because Darwin
14255 has a different PIC label for each routine but the DWARF debugging
14256 information is not associated with any particular routine, so it's
14257 necessary to remove references to the PIC label from RTL stored by
14258 the DWARF output code. */
14260 static rtx
14262 {
14264 /* addend is NULL or some rtx if x is something+GOTOFF where
14265 something doesn't include the PIC register. */
14267 /* reg_addend is NULL or a multiple of some register. */
14269 /* const_addend is NULL or a const_int. */
14271 /* This is the result, or NULL. */
14280 {
14287 {
14293 }
14300 {
14303 {
14308 }
14310 }
14315 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14316 and -mcmodel=medium -fpic. */
14317 }
14324 /* %ebx + GOT/GOTOFF */
14325 ;
14327 {
14328 /* %ebx + %reg * scale + GOT/GOTOFF */
14334 else
14335 {
14338 }
14339 }
14340 else
14346 {
14349 }
14370 {
14371 /* If the rest of original X doesn't involve the PIC register, add
14372 addend and subtract pic_offset_table_rtx. This can happen e.g.
14373 for code like:
14374 leal (%ebx, %ecx, 4), %ecx
14375 ...
14376 movl foo@GOTOFF(%ecx), %edx
14377 in which case we return (%ecx - %ebx) + foo. */
14380 pic_offset_table_rtx),
14381 result);
14382 else
14384 }
14386 {
14390 }
14392 }
14394 /* If X is a machine specific address (i.e. a symbol or label being
14395 referenced as a displacement from the GOT implemented using an
14396 UNSPEC), then return the base term. Otherwise return X. */
14398 rtx
14400 {
14401 rtx term;
14404 {
14418 }
14421 }
14422 \f
14423 static void
14426 {
14430 {
14433 }
14438 {
14441 {
14460 }
14464 {
14483 }
14490 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14491 Those same assemblers have the same but opposite lossage on cmov. */
14494 else
14499 {
14512 }
14519 else
14524 {
14537 }
14544 else
14554 else
14565 }
14567 }
14569 /* Print the name of register X to FILE based on its machine mode and number.
14570 If CODE is 'w', pretend the mode is HImode.
14571 If CODE is 'b', pretend the mode is QImode.
14572 If CODE is 'k', pretend the mode is SImode.
14573 If CODE is 'q', pretend the mode is DImode.
14574 If CODE is 'x', pretend the mode is V4SFmode.
14575 If CODE is 't', pretend the mode is V8SFmode.
14576 If CODE is 'g', pretend the mode is V16SFmode.
14577 If CODE is 'h', pretend the reg is the 'high' byte register.
14578 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14579 If CODE is 'd', duplicate the operand for AVX instruction.
14580 */
14582 void
14584 {
14593 {
14597 }
14624 else
14627 /* Irritatingly, AMD extended registers use different naming convention
14628 from the normal registers: "r%d[bwd]" */
14630 {
14635 {
14649 /* no suffix */
14654 }
14656 }
14660 {
14663 {
14666 }
14667 /* FALLTHRU */
14673 /* FALLTHRU */
14676 normal:
14691 {
14696 }
14699 {
14704 }
14708 }
14712 {
14715 else
14717 }
14718 }
14720 /* Locate some local-dynamic symbol still in use by this function
14721 so that we can print its name in some tls_local_dynamic_base
14722 pattern. */
14724 static int
14726 {
14731 {
14734 }
14737 }
14741 {
14742 rtx insn;
14753 }
14755 /* Meaning of CODE:
14756 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14757 C -- print opcode suffix for set/cmov insn.
14758 c -- like C, but print reversed condition
14759 F,f -- likewise, but for floating-point.
14760 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14761 otherwise nothing
14762 R -- print embeded rounding and sae.
14763 r -- print only sae.
14764 z -- print the opcode suffix for the size of the current operand.
14765 Z -- likewise, with special suffixes for x87 instructions.
14766 * -- print a star (in certain assembler syntax)
14767 A -- print an absolute memory reference.
14768 E -- print address with DImode register names if TARGET_64BIT.
14769 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14770 s -- print a shift double count, followed by the assemblers argument
14771 delimiter.
14772 b -- print the QImode name of the register for the indicated operand.
14773 %b0 would print %al if operands[0] is reg 0.
14774 w -- likewise, print the HImode name of the register.
14775 k -- likewise, print the SImode name of the register.
14776 q -- likewise, print the DImode name of the register.
14777 x -- likewise, print the V4SFmode name of the register.
14778 t -- likewise, print the V8SFmode name of the register.
14779 g -- likewise, print the V16SFmode name of the register.
14780 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14781 y -- print "st(0)" instead of "st" as a register.
14782 d -- print duplicated register operand for AVX instruction.
14783 D -- print condition for SSE cmp instruction.
14784 P -- if PIC, print an @PLT suffix.
14785 p -- print raw symbol name.
14786 X -- don't print any sort of PIC '@' suffix for a symbol.
14787 & -- print some in-use local-dynamic symbol name.
14788 H -- print a memory address offset by 8; used for sse high-parts
14789 Y -- print condition for XOP pcom* instruction.
14790 + -- print a branch hint as 'cs' or 'ds' prefix
14791 ; -- print a semicolon (after prefixes due to bug in older gas).
14792 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14793 @ -- print a segment register of thread base pointer load
14794 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14795 */
14797 void
14799 {
14801 {
14803 {
14806 {
14812 /* Intel syntax. For absolute addresses, registers should not
14813 be surrounded by braces. */
14815 {
14820 }
14825 }
14831 /* Wrap address in an UNSPEC to declare special handling. */
14869 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14874 {
14888 output_operand_lossage
14891 }
14894 #endif
14899 {
14900 /* Opcodes don't get size suffixes if using Intel opcodes. */
14905 {
14923 output_operand_lossage
14926 }
14927 }
14930 warning
14932 /* FALLTHRU */
14935 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14940 {
14942 {
14944 #ifdef HAVE_AS_IX86_FILDS
14946 #endif
14954 #ifdef HAVE_AS_IX86_FILDQ
14956 #else
14958 #endif
14963 }
14964 }
14966 {
14967 /* 387 opcodes don't get size suffixes
14968 if the operands are registers. */
14973 {
14989 }
14990 }
14991 else
14992 {
14993 output_operand_lossage
14996 }
14998 output_operand_lossage
15019 {
15022 }
15027 {
15078 }
15082 /* Little bit of braindamage here. The SSE compare instructions
15083 does use completely different names for the comparisons that the
15084 fp conditional moves. */
15086 {
15089 {
15092 }
15098 {
15101 }
15107 {
15110 }
15119 {
15122 }
15128 {
15131 }
15137 {
15140 }
15151 }
15156 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15159 #endif
15164 {
15168 }
15172 file);
15177 {
15181 }
15182 /* It doesn't actually matter what mode we use here, as we're
15183 only going to use this for printing. */
15185 /* Output 'qword ptr' for intel assembler dialect. */
15194 #ifdef HAVE_AS_IX86_HLE
15196 #else
15198 #endif
15200 #ifdef HAVE_AS_IX86_HLE
15202 #else
15204 #endif
15205 /* We do not want to print value of the operand. */
15234 {
15249 }
15262 {
15267 else
15270 }
15273 {
15274 rtx x;
15283 {
15288 {
15290 bool cputaken
15293 /* Emit hints only in the case default branch prediction
15294 heuristics would fail. */
15296 {
15297 /* We use 3e (DS) prefix for taken branches and
15298 2e (CS) prefix for not taken branches. */
15301 else
15303 }
15304 }
15305 }
15307 }
15310 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15312 #endif
15319 /* The kernel uses a different segment register for performance
15320 reasons; a system call would not have to trash the userspace
15321 segment register, which would be expensive. */
15324 else
15339 }
15340 }
15346 {
15347 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15350 {
15353 {
15362 else
15369 }
15371 /* Check for explicit size override (codes 'b', 'w', 'k',
15372 'q' and 'x') */
15386 }
15389 /* Avoid (%rip) for call operands. */
15395 else
15397 }
15400 {
15401 REAL_VALUE_TYPE r;
15409 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15413 else
15415 }
15418 {
15419 REAL_VALUE_TYPE r;
15428 }
15430 /* These float cases don't actually occur as immediate operands. */
15432 {
15437 }
15439 else
15440 {
15441 /* We have patterns that allow zero sets of memory, for instance.
15442 In 64-bit mode, we should probably support all 8-byte vectors,
15443 since we can in fact encode that into an immediate. */
15445 {
15448 }
15451 {
15453 {
15456 }
15459 {
15462 else
15464 }
15465 }
15470 else
15472 }
15473 }
15475 static bool
15477 {
15480 }
15481 \f
15482 /* Print a memory operand whose address is ADDR. */
15484 static void
15486 {
15495 {
15502 }
15504 {
15508 }
15509 else
15520 {
15531 }
15533 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15535 {
15547 }
15549 {
15550 /* Displacement only requires special attention. */
15553 {
15557 }
15560 else
15562 }
15563 else
15564 {
15565 /* Print SImode register names to force addr32 prefix. */
15567 {
15568 #ifdef ENABLE_CHECKING
15571 {
15582 }
15583 #endif
15586 }
15588 && TARGET_X32
15589 && disp
15592 {
15593 /* X32 runs in 64-bit mode, where displacement, DISP, in
15594 address DISP(%r64), is encoded as 32-bit immediate sign-
15595 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15596 address is %r64 + 0xffffffffbffffd00. When %r64 <
15597 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15598 which is invalid for x32. The correct address is %r64
15599 - 0x40000300 == 0xf7ffdd64. To properly encode
15600 -0x40000300(%r64) for x32, we zero-extend negative
15601 displacement by forcing addr32 prefix which truncates
15602 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15603 zero-extend all negative displacements, including -1(%rsp).
15604 However, for small negative displacements, sign-extension
15605 won't cause overflow. We only zero-extend negative
15606 displacements if they < -16*1024*1024, which is also used
15607 to check legitimate address displacements for PIC. */
15609 }
15612 {
15614 {
15619 else
15621 }
15627 {
15632 }
15634 }
15635 else
15636 {
15640 {
15641 /* Pull out the offset of a symbol; print any symbol itself. */
15645 {
15649 }
15657 else
15659 }
15663 {
15666 {
15670 }
15671 }
15674 else
15678 {
15683 }
15685 }
15686 }
15687 }
15689 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15691 static bool
15693 {
15694 rtx op;
15701 {
15704 /* FIXME: This might be @TPOFF in Sun ld. */
15715 else
15727 else
15734 #if TARGET_MACHO
15740 #endif
15743 {
15748 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15750 #else
15752 #endif
15755 }
15760 }
15763 }
15764 \f
15765 /* Split one or more double-mode RTL references into pairs of half-mode
15766 references. The RTL can be REG, offsettable MEM, integer constant, or
15767 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15768 split and "num" is its length. lo_half and hi_half are output arrays
15769 that parallel "operands". */
15771 void
15774 {
15779 {
15788 }
15793 {
15796 /* simplify_subreg refuse to split volatile memory addresses,
15797 but we still have to handle it. */
15799 {
15802 }
15803 else
15804 {
15811 }
15812 }
15813 }
15814 \f
15815 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15816 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15817 is the expression of the binary operation. The output may either be
15818 emitted here, or returned to the caller, like all output_* functions.
15820 There is no guarantee that the operands are the same mode, as they
15821 might be within FLOAT or FLOAT_EXTEND expressions. */
15823 #ifndef SYSV386_COMPAT
15824 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15825 wants to fix the assemblers because that causes incompatibility
15826 with gcc. No-one wants to fix gcc because that causes
15827 incompatibility with assemblers... You can use the option of
15828 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15829 #define SYSV386_COMPAT 1
15830 #endif
15834 {
15840 #ifdef ENABLE_CHECKING
15841 /* Even if we do not want to check the inputs, this documents input
15842 constraints. Which helps in understanding the following code. */
15852 else
15854 #endif
15857 {
15862 else
15871 else
15880 else
15889 else
15896 }
15899 {
15901 {
15905 else
15907 }
15908 else
15909 {
15913 else
15915 }
15917 }
15921 {
15925 {
15929 }
15931 /* know operands[0] == operands[1]. */
15934 {
15937 }
15940 {
15942 /* How is it that we are storing to a dead operand[2]?
15943 Well, presumably operands[1] is dead too. We can't
15944 store the result to st(0) as st(0) gets popped on this
15945 instruction. Instead store to operands[2] (which I
15946 think has to be st(1)). st(1) will be popped later.
15947 gcc <= 2.8.1 didn't have this check and generated
15948 assembly code that the Unixware assembler rejected. */
15950 else
15953 }
15957 else
15964 {
15967 }
15970 {
15973 }
15976 {
15977 #if SYSV386_COMPAT
15978 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15979 derived assemblers, confusingly reverse the direction of
15980 the operation for fsub{r} and fdiv{r} when the
15981 destination register is not st(0). The Intel assembler
15982 doesn't have this brain damage. Read !SYSV386_COMPAT to
15983 figure out what the hardware really does. */
15986 else
15988 #else
15990 /* As above for fmul/fadd, we can't store to st(0). */
15992 else
15994 #endif
15996 }
15999 {
16000 #if SYSV386_COMPAT
16003 else
16005 #else
16008 else
16010 #endif
16012 }
16015 {
16018 else
16021 }
16023 {
16024 #if SYSV386_COMPAT
16026 #else
16028 #endif
16029 }
16030 else
16031 {
16032 #if SYSV386_COMPAT
16034 #else
16036 #endif
16037 }
16042 }
16046 }
16048 /* Check if a 256bit AVX register is referenced inside of EXP. */
16050 static int
16052 {
16063 }
16065 /* Return needed mode for entity in optimize_mode_switching pass. */
16067 static int
16069 {
16071 {
16072 rtx link;
16074 /* Needed mode is set to AVX_U128_CLEAN if there are
16075 no 256bit modes used in function arguments. */
16077 link;
16079 {
16081 {
16086 }
16087 }
16090 }
16092 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16093 changes state only when a 256bit register is written to, but we need
16094 to prevent the compiler from moving optimal insertion point above
16095 eventual read from 256bit register. */
16100 }
16102 /* Return mode that i387 must be switched into
16103 prior to the execution of insn. */
16105 static int
16107 {
16110 /* The mode UNINITIALIZED is used to store control word after a
16111 function call or ASM pattern. The mode ANY specify that function
16112 has no requirements on the control word and make no changes in the
16113 bits we are interested in. */
16127 {
16150 }
16153 }
16155 /* Return mode that entity must be switched into
16156 prior to the execution of insn. */
16158 int
16160 {
16162 {
16172 }
16174 }
16176 /* Check if a 256bit AVX register is referenced in stores. */
16178 static void
16180 {
16182 {
16185 }
16186 }
16188 /* Calculate mode of upper 128bit AVX registers after the insn. */
16190 static int
16192 {
16199 /* We know that state is clean after CALL insn if there are no
16200 256bit registers used in the function return register. */
16202 {
16207 }
16209 /* Otherwise, return current mode. Remember that if insn
16210 references AVX 256bit registers, the mode was already changed
16211 to DIRTY from MODE_NEEDED. */
16213 }
16215 /* Return the mode that an insn results in. */
16217 int
16219 {
16221 {
16231 }
16232 }
16234 static int
16236 {
16237 tree arg;
16239 /* Entry mode is set to AVX_U128_DIRTY if there are
16240 256bit modes used in function arguments. */
16243 {
16248 }
16251 }
16253 /* Return a mode that ENTITY is assumed to be
16254 switched to at function entry. */
16256 int
16258 {
16260 {
16270 }
16271 }
16273 static int
16275 {
16278 /* Exit mode is set to AVX_U128_DIRTY if there are
16279 256bit modes used in the function return register. */
16284 }
16286 /* Return a mode that ENTITY is assumed to be
16287 switched to at function exit. */
16289 int
16291 {
16293 {
16303 }
16304 }
16306 /* Output code to initialize control word copies used by trunc?f?i and
16307 rounding patterns. CURRENT_MODE is set to current control word,
16308 while NEW_MODE is set to new control word. */
16310 static void
16312 {
16314 rtx new_mode;
16325 {
16327 {
16329 /* round toward zero (truncate) */
16335 /* round down toward -oo */
16342 /* round up toward +oo */
16349 /* mask precision exception for nearbyint() */
16356 }
16357 }
16358 else
16359 {
16361 {
16363 /* round toward zero (truncate) */
16369 /* round down toward -oo */
16375 /* round up toward +oo */
16381 /* mask precision exception for nearbyint() */
16388 }
16389 }
16395 }
16397 /* Emit vzeroupper. */
16399 void
16401 {
16404 /* Cancel automatic vzeroupper insertion if there are
16405 live call-saved SSE registers at the insertion point. */
16417 }
16419 /* Generate one or more insns to set ENTITY to MODE. */
16421 void
16423 {
16425 {
16440 }
16441 }
16443 /* Output code for INSN to convert a float to a signed int. OPERANDS
16444 are the insn operands. The output may be [HSD]Imode and the input
16445 operand may be [SDX]Fmode. */
16449 {
16454 /* Jump through a hoop or two for DImode, since the hardware has no
16455 non-popping instruction. We used to do this a different way, but
16456 that was somewhat fragile and broke with post-reload splitters. */
16466 else
16467 {
16472 else
16476 }
16479 }
16481 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16482 have the values zero or one, indicates the ffreep insn's operand
16483 from the OPERANDS array. */
16487 {
16489 #ifdef HAVE_AS_IX86_FFREEP
16491 #else
16492 {
16502 }
16503 #endif
16506 }
16509 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16510 should be used. UNORDERED_P is true when fucom should be used. */
16514 {
16520 {
16523 }
16524 else
16525 {
16528 }
16531 {
16535 else
16537 else
16540 else
16542 }
16549 {
16551 {
16554 }
16555 else
16557 }
16560 && stack_top_dies
16563 {
16564 /* If both the top of the 387 stack dies, and the other operand
16565 is also a stack register that dies, then this must be a
16566 `fcompp' float compare */
16569 {
16570 /* There is no double popping fcomi variant. Fortunately,
16571 eflags is immune from the fstp's cc clobbering. */
16574 else
16577 }
16578 else
16579 {
16582 else
16584 }
16585 }
16586 else
16587 {
16588 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16591 {
16599 NULL,
16600 NULL,
16607 NULL,
16608 NULL,
16609 NULL,
16610 NULL
16611 };
16626 }
16627 }
16629 void
16631 {
16634 #ifdef ASM_QUAD
16637 #else
16639 #endif
16642 }
16644 void
16646 {
16649 #ifdef ASM_QUAD
16652 #else
16654 #endif
16655 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16661 #if TARGET_MACHO
16663 {
16667 }
16668 #endif
16669 else
16672 }
16673 \f
16674 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16675 for the target. */
16677 void
16679 {
16680 rtx tmp;
16682 /* We play register width games, which are only valid after reload. */
16685 /* Avoid HImode and its attendant prefix byte. */
16690 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16692 {
16695 }
16698 }
16700 /* X is an unchanging MEM. If it is a constant pool reference, return
16701 the constant pool rtx, else NULL. */
16703 rtx
16705 {
16712 }
16714 void
16716 {
16724 {
16725 rtx tmp;
16729 {
16735 }
16738 }
16742 {
16745 rtx tmp;
16750 else
16754 {
16761 }
16762 }
16766 {
16768 {
16769 #if TARGET_MACHO
16770 /* dynamic-no-pic */
16772 {
16773 rtx temp = ((reload_in_progress
16781 }
16783 {
16787 }
16790 else
16791 {
16799 }
16800 /* dynamic-no-pic */
16801 #endif
16802 }
16803 else
16804 {
16808 {
16814 }
16815 }
16816 }
16817 else
16818 {
16829 /* Force large constants in 64bit compilation into register
16830 to get them CSEed. */
16842 {
16843 /* If we are loading a floating point constant to a register,
16844 force the value to memory now, since we'll get better code
16845 out the back end. */
16849 {
16854 }
16855 }
16856 }
16859 }
16861 void
16863 {
16870 /* Force constants other than zero into memory. We do not know how
16871 the instructions used to build constants modify the upper 64 bits
16872 of the register, once we have that information we may be able
16873 to handle some of them more efficiently. */
16882 /* We need to check memory alignment for SSE mode since attribute
16883 can make operands unaligned. */
16888 {
16891 /* ix86_expand_vector_move_misalign() does not like constants ... */
16897 /* ... nor both arguments in memory. */
16905 }
16907 /* Make operand1 a register if it isn't already. */
16911 {
16914 }
16917 }
16919 /* Split 32-byte AVX unaligned load and store if needed. */
16921 static void
16923 {
16924 rtx m;
16931 {
16952 }
16955 {
16957 {
16964 }
16965 /* Normal *mov<mode>_internal pattern will handle
16966 unaligned loads just fine if misaligned_operand
16967 is true, and without the UNSPEC it can be combined
16968 with arithmetic instructions. */
16971 else
16973 }
16975 {
16977 {
16982 }
16983 else
16985 }
16986 else
16988 }
16990 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16991 straight to ix86_expand_vector_move. */
16992 /* Code generation for scalar reg-reg moves of single and double precision data:
16993 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16994 movaps reg, reg
16995 else
16996 movss reg, reg
16997 if (x86_sse_partial_reg_dependency == true)
16998 movapd reg, reg
16999 else
17000 movsd reg, reg
17002 Code generation for scalar loads of double precision data:
17003 if (x86_sse_split_regs == true)
17004 movlpd mem, reg (gas syntax)
17005 else
17006 movsd mem, reg
17008 Code generation for unaligned packed loads of single precision data
17009 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17010 if (x86_sse_unaligned_move_optimal)
17011 movups mem, reg
17013 if (x86_sse_partial_reg_dependency == true)
17014 {
17015 xorps reg, reg
17016 movlps mem, reg
17017 movhps mem+8, reg
17018 }
17019 else
17020 {
17021 movlps mem, reg
17022 movhps mem+8, reg
17023 }
17025 Code generation for unaligned packed loads of double precision data
17026 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17027 if (x86_sse_unaligned_move_optimal)
17028 movupd mem, reg
17030 if (x86_sse_split_regs == true)
17031 {
17032 movlpd mem, reg
17033 movhpd mem+8, reg
17034 }
17035 else
17036 {
17037 movsd mem, reg
17038 movhpd mem+8, reg
17039 }
17040 */
17042 void
17044 {
17053 {
17055 {
17059 {
17061 {
17064 }
17065 else
17067 }
17069 /* FALLTHRU */
17073 {
17088 }
17094 else
17102 }
17105 }
17109 {
17111 {
17115 {
17117 {
17120 }
17121 else
17123 }
17125 /* FALLTHRU */
17135 }
17138 }
17141 {
17142 /* Normal *mov<mode>_internal pattern will handle
17143 unaligned loads just fine if misaligned_operand
17144 is true, and without the UNSPEC it can be combined
17145 with arithmetic instructions. */
17151 /* ??? If we have typed data, then it would appear that using
17152 movdqu is the only way to get unaligned data loaded with
17153 integer type. */
17155 {
17157 {
17160 }
17162 /* We will eventually emit movups based on insn attributes. */
17166 }
17168 {
17169 rtx zero;
17172 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17173 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17175 {
17176 /* We will eventually emit movups based on insn attributes. */
17179 }
17181 /* When SSE registers are split into halves, we can avoid
17182 writing to the top half twice. */
17184 {
17187 }
17188 else
17189 {
17190 /* ??? Not sure about the best option for the Intel chips.
17191 The following would seem to satisfy; the register is
17192 entirely cleared, breaking the dependency chain. We
17193 then store to the upper half, with a dependency depth
17194 of one. A rumor has it that Intel recommends two movsd
17195 followed by an unpacklpd, but this is unconfirmed. And
17196 given that the dependency depth of the unpacklpd would
17197 still be one, I'm not sure why this would be better. */
17199 }
17205 }
17206 else
17207 {
17208 rtx t;
17211 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17212 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17214 {
17216 {
17219 }
17226 }
17230 else
17235 else
17244 }
17245 }
17247 {
17249 {
17252 /* We will eventually emit movups based on insn attributes. */
17254 }
17256 {
17258 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17259 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17261 /* We will eventually emit movups based on insn attributes. */
17263 else
17264 {
17269 }
17270 }
17271 else
17272 {
17277 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17278 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17280 {
17283 }
17284 else
17285 {
17290 }
17291 }
17292 }
17293 else
17295 }
17297 /* Helper function of ix86_fixup_binary_operands to canonicalize
17298 operand order. Returns true if the operands should be swapped. */
17300 static bool
17302 rtx operands[])
17303 {
17308 /* If the operation is not commutative, we can't do anything. */
17312 /* Highest priority is that src1 should match dst. */
17318 /* Next highest priority is that immediate constants come second. */
17324 /* Lowest priority is that memory references should come second. */
17331 }
17334 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17335 destination to use for the operation. If different from the true
17336 destination in operands[0], a copy operation will be required. */
17338 rtx
17340 rtx operands[])
17341 {
17346 /* Canonicalize operand order. */
17348 {
17349 rtx temp;
17351 /* It is invalid to swap operands of different modes. */
17357 }
17359 /* Both source operands cannot be in memory. */
17361 {
17362 /* Optimization: Only read from memory once. */
17364 {
17367 }
17370 else
17372 }
17374 /* If the destination is memory, and we do not have matching source
17375 operands, do things in registers. */
17379 /* Source 1 cannot be a constant. */
17383 /* Source 1 cannot be a non-matching memory. */
17387 /* Improve address combine. */
17396 }
17398 /* Similarly, but assume that the destination has already been
17399 set up properly. */
17401 void
17404 {
17407 }
17409 /* Attempt to expand a binary operator. Make the expansion closer to the
17410 actual machine, then just general_operand, which will allow 3 separate
17411 memory references (one output, two input) in a single insn. */
17413 void
17415 rtx operands[])
17416 {
17423 /* Emit the instruction. */
17427 {
17428 /* Reload doesn't know about the flags register, and doesn't know that
17429 it doesn't want to clobber it. We can only do this with PLUS. */
17432 }
17436 {
17437 /* This is going to be an LEA; avoid splitting it later. */
17439 }
17440 else
17441 {
17444 }
17446 /* Fix up the destination if needed. */
17449 }
17451 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17452 the given OPERANDS. */
17454 void
17456 rtx operands[])
17457 {
17460 {
17463 }
17465 {
17468 }
17469 /* Optimize (__m128i) d | (__m128i) e and similar code
17470 when d and e are float vectors into float vector logical
17471 insn. In C/C++ without using intrinsics there is no other way
17472 to express vector logical operation on float vectors than
17473 to cast them temporarily to integer vectors. */
17475 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17484 {
17485 rtx dst;
17487 {
17494 {
17497 }
17498 else
17499 {
17504 }
17515 }
17516 }
17525 }
17527 /* Return TRUE or FALSE depending on whether the binary operator meets the
17528 appropriate constraints. */
17530 bool
17533 {
17538 /* Both source operands cannot be in memory. */
17542 /* Canonicalize operand order for commutative operators. */
17544 {
17548 }
17550 /* If the destination is memory, we must have a matching source operand. */
17554 /* Source 1 cannot be a constant. */
17558 /* Source 1 cannot be a non-matching memory. */
17560 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17568 }
17570 /* Attempt to expand a unary operator. Make the expansion closer to the
17571 actual machine, then just general_operand, which will allow 2 separate
17572 memory references (one output, one input) in a single insn. */
17574 void
17576 rtx operands[])
17577 {
17584 /* If the destination is memory, and we do not have matching source
17585 operands, do things in registers. */
17588 {
17591 else
17593 }
17595 /* When source operand is memory, destination must match. */
17599 /* Emit the instruction. */
17603 {
17604 /* Reload doesn't know about the flags register, and doesn't know that
17605 it doesn't want to clobber it. */
17608 }
17609 else
17610 {
17613 }
17615 /* Fix up the destination if needed. */
17618 }
17620 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17621 divisor are within the range [0-255]. */
17623 void
17626 {
17635 {
17648 }
17655 /* Use 8bit unsigned divimod if dividend and divisor are within
17656 the range [0-255]. */
17665 pc_rtx);
17670 /* Generate original signed/unsigned divimod. */
17675 /* Branch to the end. */
17679 /* Generate 8bit unsigned divide. */
17681 /* Don't use operands[0] for result of 8bit divide since not all
17682 registers support QImode ZERO_EXTRACT. */
17689 {
17692 }
17693 else
17694 {
17697 }
17699 /* Extract remainder from AH. */
17703 else
17704 {
17705 /* Need a new scratch register since the old one has result
17706 of 8bit divide. */
17710 }
17713 /* Zero extend quotient from AL. */
17719 }
17721 /* Whether it is OK to emit CFI directives when emitting asm code. */
17723 bool
17725 {
17727 }
17729 #define LEA_MAX_STALL (3)
17730 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17732 /* Increase given DISTANCE in half-cycles according to
17733 dependencies between PREV and NEXT instructions.
17734 Add 1 half-cycle if there is no dependency and
17735 go to next cycle if there is some dependecy. */
17737 static unsigned int
17739 {
17756 }
17758 /* Function checks if instruction INSN defines register number
17759 REGNO1 or REGNO2. */
17761 static bool
17763 rtx insn)
17764 {
17772 {
17774 }
17777 }
17779 /* Function checks if instruction INSN uses register number
17780 REGNO as a part of address expression. */
17782 static bool
17784 {
17792 }
17794 /* Search backward for non-agu definition of register number REGNO1
17795 or register number REGNO2 in basic block starting from instruction
17796 START up to head of basic block or instruction INSN.
17798 Function puts true value into *FOUND var if definition was found
17799 and false otherwise.
17801 Distance in half-cycles between START and found instruction or head
17802 of BB is added to DISTANCE and returned. */
17804 static int
17808 {
17818 {
17820 {
17823 {
17826 {
17829 }
17830 }
17833 }
17838 }
17841 }
17843 /* Search backward for non-agu definition of register number REGNO1
17844 or register number REGNO2 in INSN's basic block until
17845 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17846 2. Reach neighbour BBs boundary, or
17847 3. Reach agu definition.
17848 Returns the distance between the non-agu definition point and INSN.
17849 If no definition point, returns -1. */
17851 static int
17853 rtx insn)
17854 {
17865 {
17866 edge e;
17867 edge_iterator ei;
17872 {
17875 }
17881 else
17882 {
17887 {
17888 int bb_dist
17894 {
17901 }
17902 }
17905 }
17906 }
17908 /* get_attr_type may modify recog data. We want to make sure
17909 that recog data is valid for instruction INSN, on which
17910 distance_non_agu_define is called. INSN is unchanged here. */
17917 }
17919 /* Return the distance in half-cycles between INSN and the next
17920 insn that uses register number REGNO in memory address added
17921 to DISTANCE. Return -1 if REGNO0 is set.
17923 Put true value into *FOUND if register usage was found and
17924 false otherwise.
17925 Put true value into *REDEFINED if register redefinition was
17926 found and false otherwise. */
17928 static int
17932 {
17941 {
17944 /* If insn and start belong to the same bb, set prev to insn,
17945 so the call to increase_distance will increase the distance
17946 between insns by 1. */
17948 }
17953 {
17955 {
17958 {
17959 /* Return DISTANCE if OP0 is used in memory
17960 address in NEXT. */
17963 }
17966 {
17967 /* Return -1 if OP0 is set in NEXT. */
17970 }
17973 }
17979 }
17982 }
17984 /* Return the distance between INSN and the next insn that uses
17985 register number REGNO0 in memory address. Return -1 if no such
17986 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17988 static int
17990 {
18002 {
18003 edge e;
18004 edge_iterator ei;
18009 {
18012 }
18018 else
18019 {
18025 {
18026 int bb_dist
18031 {
18038 }
18039 }
18042 }
18043 }
18049 }
18051 /* Define this macro to tune LEA priority vs ADD, it take effect when
18052 there is a dilemma of choicing LEA or ADD
18053 Negative value: ADD is more preferred than LEA
18054 Zero: Netrual
18055 Positive value: LEA is more preferred than ADD*/
18056 #define IX86_LEA_PRIORITY 0
18058 /* Return true if usage of lea INSN has performance advantage
18059 over a sequence of instructions. Instructions sequence has
18060 SPLIT_COST cycles higher latency than lea latency. */
18062 static bool
18065 {
18068 /* For Silvermont if using a 2-source or 3-source LEA for
18069 non-destructive destination purposes, or due to wanting
18070 ability to use SCALE, the use of LEA is justified. */
18072 {
18080 }
18086 {
18087 /* If there is no non AGU operand definition, no AGU
18088 operand usage and split cost is 0 then both lea
18089 and non lea variants have same priority. Currently
18090 we prefer lea for 64 bit code and non lea on 32 bit
18091 code. */
18094 else
18096 }
18098 /* With longer definitions distance lea is more preferable.
18099 Here we change it to take into account splitting cost and
18100 lea priority. */
18103 /* If there is no use in memory addess then we just check
18104 that split cost exceeds AGU stall. */
18108 /* If this insn has both backward non-agu dependence and forward
18109 agu dependence, the one with short distance takes effect. */
18111 }
18113 /* Return true if it is legal to clobber flags by INSN and
18114 false otherwise. */
18116 static bool
18118 {
18121 bitmap live;
18124 {
18126 {
18133 }
18139 }
18143 }
18145 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18146 move and add to avoid AGU stalls. */
18148 bool
18150 {
18153 /* Check if we need to optimize. */
18157 /* Check it is correct to split here. */
18165 /* We need to split only adds with non destructive
18166 destination operand. */
18169 else
18171 }
18173 /* Return true if we should emit lea instruction instead of mov
18174 instruction. */
18176 bool
18178 {
18181 /* Check if we need to optimize. */
18185 /* Use lea for reg to reg moves only. */
18193 }
18195 /* Return true if we need to split lea into a sequence of
18196 instructions to avoid AGU stalls. */
18198 bool
18200 {
18206 /* Check we need to optimize. */
18210 /* The "at least two components" test below might not catch simple
18211 move or zero extension insns if parts.base is non-NULL and parts.disp
18212 is const0_rtx as the only components in the address, e.g. if the
18213 register is %rbp or %r13. As this test is much cheaper and moves or
18214 zero extensions are the common case, do this check first. */
18220 /* Check if it is OK to split here. */
18227 /* There should be at least two components in the address. */
18232 /* We should not split into add if non legitimate pic
18233 operand is used as displacement. */
18248 /* Compute how many cycles we will add to execution time
18249 if split lea into a sequence of instructions. */
18251 {
18252 /* Have to use mov instruction if non desctructive
18253 destination form is used. */
18257 /* Have to add index to base if both exist. */
18261 /* Have to use shift and adds if scale is 2 or greater. */
18263 {
18268 else
18270 }
18272 /* Have to use add instruction with immediate if
18273 disp is non zero. */
18277 /* Subtract the price of lea. */
18279 }
18283 }
18285 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18286 matches destination. RTX includes clobber of FLAGS_REG. */
18288 static void
18291 {
18298 }
18300 /* Return true if regno1 def is nearest to the insn. */
18302 static bool
18304 {
18311 {
18313 {
18316 }
18322 }
18324 /* None of the regs is defined in the bb. */
18326 }
18328 /* Split lea instructions into a sequence of instructions
18329 which are executed on ALU to avoid AGU stalls.
18330 It is assumed that it is allowed to clobber flags register
18331 at lea position. */
18333 void
18335 {
18351 {
18354 }
18357 {
18360 }
18366 {
18367 /* Case r1 = r1 + ... */
18369 {
18370 /* If we have a case r1 = r1 + C * r2 then we
18371 should use multiplication which is very
18372 expensive. Assume cost model is wrong if we
18373 have such case here. */
18378 }
18379 else
18380 {
18381 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18385 /* Use shift for scaling. */
18394 }
18395 }
18397 {
18400 }
18401 else
18402 {
18404 {
18407 }
18409 {
18412 }
18413 else
18414 {
18419 else
18420 {
18421 rtx tmp1;
18423 /* Find better operand for SET instruction, depending
18424 on which definition is farther from the insn. */
18427 else
18437 }
18440 }
18444 }
18445 }
18447 /* Return true if it is ok to optimize an ADD operation to LEA
18448 operation to avoid flag register consumation. For most processors,
18449 ADD is faster than LEA. For the processors like BONNELL, if the
18450 destination register of LEA holds an actual address which will be
18451 used soon, LEA is better and otherwise ADD is better. */
18453 bool
18455 {
18460 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18468 }
18470 /* Return true if destination reg of SET_BODY is shift count of
18471 USE_BODY. */
18473 static bool
18475 {
18476 rtx set_dest;
18477 rtx shift_rtx;
18480 /* Retrieve destination of SET_BODY. */
18482 {
18491 use_body))
18496 }
18498 /* Retrieve shift count of USE_BODY. */
18500 {
18512 }
18520 {
18523 /* Return true if shift count is dest of SET_BODY. */
18525 {
18526 /* Add check since it can be invoked before register
18527 allocation in pre-reload schedule. */
18533 }
18534 }
18537 }
18539 /* Return true if destination reg of SET_INSN is shift count of
18540 USE_INSN. */
18542 bool
18544 {
18547 }
18549 /* Return TRUE or FALSE depending on whether the unary operator meets the
18550 appropriate constraints. */
18552 bool
18556 {
18557 /* If one of operands is memory, source and destination must match. */
18563 }
18565 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18566 are ok, keeping in mind the possible movddup alternative. */
18568 bool
18570 {
18576 }
18578 /* Post-reload splitter for converting an SF or DFmode value in an
18579 SSE register into an unsigned SImode. */
18581 void
18583 {
18594 /* Load up the value into the low element. We must ensure that the other
18595 elements are valid floats -- zero is the easiest such value. */
18597 {
18600 else
18602 }
18603 else
18604 {
18609 else
18611 }
18631 else
18636 }
18638 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18639 Expects the 64-bit DImode to be supplied in a pair of integral
18640 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18641 -mfpmath=sse, !optimize_size only. */
18643 void
18645 {
18649 rtx x;
18655 {
18658 }
18659 else
18660 {
18664 }
18672 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18675 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18676 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18677 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18678 (0x1.0p84 + double(fp_value_hi_xmm)).
18679 Note these exponents differ by 32. */
18683 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18684 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18693 /* Add the upper and lower DFmode values together. */
18696 else
18697 {
18701 }
18704 }
18706 /* Not used, but eases macroization of patterns. */
18707 void
18709 rtx input ATTRIBUTE_UNUSED)
18710 {
18712 }
18714 /* Convert an unsigned SImode value into a DFmode. Only currently used
18715 for SSE, but applicable anywhere. */
18717 void
18719 {
18720 REAL_VALUE_TYPE TWO31r;
18735 }
18737 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18738 32-bit mode; otherwise we have a direct convert instruction. */
18740 void
18742 {
18743 REAL_VALUE_TYPE TWO32r;
18761 }
18763 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18764 For x86_32, -mfpmath=sse, !optimize_size only. */
18765 void
18767 {
18768 REAL_VALUE_TYPE ONE16r;
18787 }
18789 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18790 a vector of unsigned ints VAL to vector of floats TARGET. */
18792 void
18794 {
18796 REAL_VALUE_TYPE TWO16r;
18803 else
18808 OPTAB_DIRECT);
18819 OPTAB_DIRECT);
18821 OPTAB_DIRECT);
18824 }
18826 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18827 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18828 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18829 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18831 rtx
18833 {
18834 REAL_VALUE_TYPE TWO31r;
18849 {
18855 }
18864 OPTAB_DIRECT);
18865 else
18866 {
18872 OPTAB_DIRECT);
18873 }
18876 }
18878 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18879 then replicate the value for all elements of the vector
18880 register. */
18882 rtx
18884 {
18886 rtvec v;
18890 {
18923 }
18924 }
18926 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18927 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18928 for an SSE register. If VECT is true, then replicate the mask for
18929 all elements of the vector register. If INVERT is true, then create
18930 a mask excluding the sign bit. */
18932 rtx
18934 {
18938 rtx v;
18939 rtx mask;
18941 /* Find the sign bit, sign extended to 2*HWI. */
18943 {
18967 else
18975 {
18978 }
18979 else
18980 {
18981 rtvec vec;
18987 {
18990 }
18991 else
19001 }
19006 }
19011 /* Force this value into the low part of a fp vector constant. */
19020 }
19022 /* Generate code for floating point ABS or NEG. */
19024 void
19026 rtx operands[])
19027 {
19038 {
19044 }
19046 /* NEG and ABS performed with SSE use bitwise mask operations.
19047 Create the appropriate mask now. */
19050 else
19060 {
19062 rtvec par;
19067 else
19068 {
19071 }
19073 }
19074 else
19076 }
19078 /* Expand a copysign operation. Special case operand 0 being a constant. */
19080 void
19082 {
19096 else
19100 {
19107 {
19110 else
19111 {
19115 }
19116 }
19126 else
19130 }
19131 else
19132 {
19142 else
19146 }
19147 }
19149 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19150 be a constant, and so has already been expanded into a vector constant. */
19152 void
19154 {
19170 {
19173 }
19174 }
19176 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19177 so we have to do two masks. */
19179 void
19181 {
19196 {
19197 /* Shouldn't happen often (it's useless, obviously), but when it does
19198 we'd generate incorrect code if we continue below. */
19201 }
19204 {
19215 }
19216 else
19217 {
19219 {
19221 }
19223 {
19227 }
19231 {
19234 }
19236 {
19241 }
19243 }
19247 }
19249 /* Return TRUE or FALSE depending on whether the first SET in INSN
19250 has source and destination with matching CC modes, and that the
19251 CC mode is at least as constrained as REQ_MODE. */
19253 bool
19255 {
19256 rtx set;
19267 {
19277 /* FALLTHRU */
19281 /* FALLTHRU */
19285 /* FALLTHRU */
19299 }
19302 }
19304 /* Generate insn patterns to do an integer compare of OPERANDS. */
19306 static rtx
19308 {
19315 /* This is very simple, but making the interface the same as in the
19316 FP case makes the rest of the code easier. */
19320 /* Return the test that should be put into the flags user, i.e.
19321 the bcc, scc, or cmov instruction. */
19323 }
19325 /* Figure out whether to use ordered or unordered fp comparisons.
19326 Return the appropriate mode to use. */
19328 enum machine_mode
19330 {
19331 /* ??? In order to make all comparisons reversible, we do all comparisons
19332 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19333 all forms trapping and nontrapping comparisons, we can make inequality
19334 comparisons trapping again, since it results in better code when using
19335 FCOM based compares. */
19337 }
19339 enum machine_mode
19341 {
19345 {
19348 }
19351 {
19352 /* Only zero flag is needed. */
19356 /* Codes needing carry flag. */
19359 /* Detect overflow checks. They need just the carry flag. */
19363 else
19368 /* Codes possibly doable only with sign flag when
19369 comparing against zero. */
19374 else
19375 /* For other cases Carry flag is not required. */
19377 /* Codes doable only with sign flag when comparing
19378 against zero, but we miss jump instruction for it
19379 so we need to use relational tests against overflow
19380 that thus needs to be zero. */
19385 else
19387 /* strcmp pattern do (use flags) and combine may ask us for proper
19388 mode. */
19393 }
19394 }
19396 /* Return the fixed registers used for condition codes. */
19398 static bool
19400 {
19404 }
19406 /* If two condition code modes are compatible, return a condition code
19407 mode which is compatible with both. Otherwise, return
19408 VOIDmode. */
19410 static enum machine_mode
19412 {
19429 {
19443 {
19457 }
19461 /* These are only compatible with themselves, which we already
19462 checked above. */
19464 }
19465 }
19468 /* Return a comparison we can do and that it is equivalent to
19469 swap_condition (code) apart possibly from orderedness.
19470 But, never change orderedness if TARGET_IEEE_FP, returning
19471 UNKNOWN in that case if necessary. */
19473 static enum rtx_code
19475 {
19477 {
19488 }
19489 }
19491 /* Return cost of comparison CODE using the best strategy for performance.
19492 All following functions do use number of instructions as a cost metrics.
19493 In future this should be tweaked to compute bytes for optimize_size and
19494 take into account performance of various instructions on various CPUs. */
19496 static int
19498 {
19501 /* The cost of code using bit-twiddling on %ah. */
19503 {
19526 }
19529 {
19536 }
19537 }
19539 /* Return strategy to use for floating-point. We assume that fcomi is always
19540 preferrable where available, since that is also true when looking at size
19541 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19543 enum ix86_fpcmp_strategy
19545 {
19546 /* Do fcomi/sahf based test when profitable. */
19555 }
19557 /* Swap, force into registers, or otherwise massage the two operands
19558 to a fp comparison. The operands are updated in place; the new
19559 comparison code is returned. */
19561 static enum rtx_code
19563 {
19569 /* All of the unordered compare instructions only work on registers.
19570 The same is true of the fcomi compare instructions. The XFmode
19571 compare instructions require registers except when comparing
19572 against zero or when converting operand 1 from fixed point to
19573 floating point. */
19582 {
19585 }
19586 else
19587 {
19588 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19589 things around if they appear profitable, otherwise force op0
19590 into a register. */
19596 {
19599 {
19600 rtx tmp;
19603 }
19604 }
19610 {
19615 {
19618 }
19619 else
19621 }
19622 }
19624 /* Try to rearrange the comparison to make it cheaper. */
19628 {
19629 rtx tmp;
19634 }
19639 }
19641 /* Convert comparison codes we use to represent FP comparison to integer
19642 code that will result in proper branch. Return UNKNOWN if no such code
19643 is available. */
19645 enum rtx_code
19647 {
19649 {
19672 }
19673 }
19675 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19677 static rtx
19679 {
19686 /* Do fcomi/sahf based test when profitable. */
19688 {
19693 tmp);
19701 tmp);
19710 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19717 /* In the unordered case, we have to check C2 for NaN's, which
19718 doesn't happen to work out to anything nice combination-wise.
19719 So do some bit twiddling on the value we've got in AH to come
19720 up with an appropriate set of condition codes. */
19724 {
19728 {
19731 }
19732 else
19733 {
19739 }
19744 {
19749 }
19750 else
19751 {
19754 }
19759 {
19762 }
19763 else
19764 {
19768 }
19773 {
19779 }
19780 else
19781 {
19784 }
19789 {
19794 }
19795 else
19796 {
19799 }
19804 {
19809 }
19810 else
19811 {
19814 }
19828 }
19833 }
19835 /* Return the test that should be put into the flags user, i.e.
19836 the bcc, scc, or cmov instruction. */
19839 const0_rtx);
19840 }
19842 static rtx
19844 {
19845 rtx ret;
19851 {
19854 }
19855 else
19859 }
19861 void
19863 {
19865 rtx tmp;
19868 {
19875 simple:
19879 pc_rtx);
19887 /* Expand DImode branch into multiple compare+branch. */
19888 {
19894 {
19897 }
19904 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19905 avoid two branches. This costs one extra insn, so disable when
19906 optimizing for size. */
19911 {
19929 }
19931 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19932 op1 is a constant and the low word is zero, then we can just
19933 examine the high word. Similarly for low word -1 and
19934 less-or-equal-than or greater-than. */
19938 {
19941 {
19944 }
19948 {
19951 }
19955 }
19957 /* Otherwise, we need two or three jumps. */
19966 {
19980 }
19982 /*
19983 * a < b =>
19984 * if (hi(a) < hi(b)) goto true;
19985 * if (hi(a) > hi(b)) goto false;
19986 * if (lo(a) < lo(b)) goto true;
19987 * false:
19988 */
20000 }
20005 }
20006 }
20008 /* Split branch based on floating point condition. */
20009 void
20012 {
20013 rtx condition;
20014 rtx i;
20017 {
20022 }
20025 tmp);
20027 /* Remove pushed operand from stack. */
20037 }
20039 void
20041 {
20042 rtx ret;
20049 }
20051 /* Expand comparison setting or clearing carry flag. Return true when
20052 successful and set pop for the operation. */
20053 static bool
20055 {
20059 /* Do not handle double-mode compares that go through special path. */
20064 {
20069 /* Shortcut: following common codes never translate
20070 into carry flag compares. */
20075 /* These comparisons require zero flag; swap operands so they won't. */
20078 {
20083 }
20085 /* Try to expand the comparison and verify that we end up with
20086 carry flag based comparison. This fails to be true only when
20087 we decide to expand comparison using arithmetic that is not
20088 too common scenario. */
20097 else
20106 }
20112 {
20117 /* Convert a==0 into (unsigned)a<1. */
20126 /* Convert a>b into b<a or a>=b-1. */
20130 {
20132 /* Bail out on overflow. We still can swap operands but that
20133 would force loading of the constant into register. */
20138 }
20139 else
20140 {
20145 }
20148 /* Convert a>=0 into (unsigned)a<0x80000000. */
20166 }
20167 /* Swapping operands may cause constant to appear as first operand. */
20169 {
20173 }
20177 }
20179 bool
20181 {
20205 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20206 HImode insns, we'd be swallowed in word prefix ops. */
20212 {
20216 HOST_WIDE_INT diff;
20219 /* Sign bit compares are better done using shifts than we do by using
20220 sbb. */
20223 {
20224 /* Detect overlap between destination and compare sources. */
20228 {
20229 rtx flags;
20238 {
20240 compare_code
20242 }
20244 /* To simplify rest of code, restrict to the GEU case. */
20246 {
20252 }
20253 else
20254 {
20257 reverse_condition_maybe_unordered
20259 else
20262 }
20271 else
20274 }
20275 else
20276 {
20279 else
20280 {
20285 }
20287 }
20290 {
20291 /*
20292 * cmpl op0,op1
20293 * sbbl dest,dest
20294 * [addl dest, ct]
20295 *
20296 * Size 5 - 8.
20297 */
20302 }
20304 {
20305 /*
20306 * cmpl op0,op1
20307 * sbbl dest,dest
20308 * orl $ct, dest
20309 *
20310 * Size 8.
20311 */
20315 }
20317 {
20318 /*
20319 * cmpl op0,op1
20320 * sbbl dest,dest
20321 * notl dest
20322 * [addl dest, cf]
20323 *
20324 * Size 8 - 11.
20325 */
20331 }
20332 else
20333 {
20334 /*
20335 * cmpl op0,op1
20336 * sbbl dest,dest
20337 * [notl dest]
20338 * andl cf - ct, dest
20339 * [addl dest, ct]
20340 *
20341 * Size 8 - 11.
20342 */
20345 {
20349 }
20359 }
20365 }
20368 {
20371 HOST_WIDE_INT tmp;
20376 {
20379 /* We may be reversing unordered compare to normal compare, that
20380 is not valid in general (we may convert non-trapping condition
20381 to trapping one), however on i386 we currently emit all
20382 comparisons unordered. */
20385 }
20386 else
20387 {
20390 }
20391 }
20396 {
20401 {
20406 }
20407 }
20409 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20413 {
20414 /* If lea code below could be used, only optimize
20415 if it results in a 2 insn sequence. */
20421 {
20422 /*
20423 * notl op1 (if necessary)
20424 * sarl $31, op1
20425 * orl cf, op1
20426 */
20428 {
20432 }
20443 }
20444 }
20452 {
20453 /*
20454 * xorl dest,dest
20455 * cmpl op1,op2
20456 * setcc dest
20457 * lea cf(dest*(ct-cf)),dest
20458 *
20459 * Size 14.
20460 *
20461 * This also catches the degenerate setcc-only case.
20462 */
20464 rtx tmp;
20470 /* On x86_64 the lea instruction operates on Pmode, so we need
20471 to get arithmetics done in proper mode to match. */
20474 else
20475 {
20476 rtx out1;
20479 nops++;
20481 {
20483 nops++;
20484 }
20485 }
20487 {
20489 nops++;
20490 }
20492 {
20495 else
20497 }
20502 }
20504 /*
20505 * General case: Jumpful:
20506 * xorl dest,dest cmpl op1, op2
20507 * cmpl op1, op2 movl ct, dest
20508 * setcc dest jcc 1f
20509 * decl dest movl cf, dest
20510 * andl (cf-ct),dest 1:
20511 * addl ct,dest
20512 *
20513 * Size 20. Size 14.
20514 *
20515 * This is reasonably steep, but branch mispredict costs are
20516 * high on modern cpus, so consider failing only if optimizing
20517 * for space.
20518 */
20523 {
20525 {
20532 {
20535 /* We may be reversing unordered compare to normal compare,
20536 that is not valid in general (we may convert non-trapping
20537 condition to trapping one), however on i386 we currently
20538 emit all comparisons unordered. */
20540 }
20541 else
20542 {
20546 }
20547 }
20550 {
20551 /* notl op1 (if needed)
20552 sarl $31, op1
20553 andl (cf-ct), op1
20554 addl ct, op1
20556 For x < 0 (resp. x <= -1) there will be no notl,
20557 so if possible swap the constants to get rid of the
20558 complement.
20559 True/false will be -1/0 while code below (store flag
20560 followed by decrement) is 0/-1, so the constants need
20561 to be exchanged once more. */
20564 {
20567 }
20568 else
20569 {
20573 }
20576 }
20577 else
20578 {
20582 constm1_rtx,
20584 }
20596 }
20597 }
20600 {
20601 /* Try a few things more with specific constants and a variable. */
20603 optab op;
20609 /* If one of the two operands is an interesting constant, load a
20610 constant with the above and mask it in with a logical operation. */
20613 {
20619 else
20621 }
20623 {
20629 else
20631 }
20632 else
20639 /* Recurse to get the constant loaded. */
20643 /* Mask in the interesting variable. */
20645 OPTAB_WIDEN);
20650 }
20652 /*
20653 * For comparison with above,
20654 *
20655 * movl cf,dest
20656 * movl ct,tmp
20657 * cmpl op1,op2
20658 * cmovcc tmp,dest
20659 *
20660 * Size 15.
20661 */
20683 }
20685 /* Swap, force into registers, or otherwise massage the two operands
20686 to an sse comparison with a mask result. Thus we differ a bit from
20687 ix86_prepare_fp_compare_args which expects to produce a flags result.
20689 The DEST operand exists to help determine whether to commute commutative
20690 operators. The POP0/POP1 operands are updated in place. The new
20691 comparison code is returned, or UNKNOWN if not implementable. */
20693 static enum rtx_code
20696 {
20697 rtx tmp;
20700 {
20703 /* AVX supports all the needed comparisons. */
20706 /* We have no LTGT as an operator. We could implement it with
20707 NE & ORDERED, but this requires an extra temporary. It's
20708 not clear that it's worth it. */
20715 /* These are supported directly. */
20722 /* AVX has 3 operand comparisons, no need to swap anything. */
20725 /* For commutative operators, try to canonicalize the destination
20726 operand to be first in the comparison - this helps reload to
20727 avoid extra moves. */
20730 /* FALLTHRU */
20736 /* These are not supported directly before AVX, and furthermore
20737 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20738 comparison operands to transform into something that is
20739 supported. */
20748 }
20751 }
20753 /* Detect conditional moves that exactly match min/max operational
20754 semantics. Note that this is IEEE safe, as long as we don't
20755 interchange the operands.
20757 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20758 and TRUE if the operation is successful and instructions are emitted. */
20760 static bool
20763 {
20766 rtx tmp;
20769 ;
20771 {
20775 }
20776 else
20783 else
20788 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20789 but MODE may be a vector mode and thus not appropriate. */
20791 {
20793 rtvec v;
20798 }
20799 else
20800 {
20803 }
20807 }
20809 /* Expand an sse vector comparison. Return the register with the result. */
20811 static rtx
20814 {
20818 /* In general case result of comparison can differ from operands' type. */
20821 /* In AVX512F the result of comparison is an integer mask. */
20823 rtx x;
20826 {
20831 }
20832 else
20845 /* Compare patterns for int modes are unspec in AVX512F only. */
20847 {
20851 {
20860 }
20863 {
20866 }
20867 }
20871 {
20874 }
20875 else
20879 }
20881 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20882 operations. This is used for both scalar and vector conditional moves. */
20884 static void
20886 {
20890 /* In AVX512F the result of comparison is an integer mask. */
20898 {
20900 }
20903 {
20907 }
20910 {
20915 }
20918 {
20922 }
20925 {
20933 op_true,
20934 op_false)));
20935 }
20936 else
20937 {
20947 {
20961 {
20968 }
20983 {
20990 }
21008 }
21011 {
21015 }
21016 else
21017 {
21023 else
21035 }
21036 }
21037 }
21039 /* Expand a floating-point conditional move. Return true if successful. */
21041 bool
21043 {
21051 {
21054 /* Since we've no cmove for sse registers, don't force bad register
21055 allocation just to gain access to it. Deny movcc when the
21056 comparison mode doesn't match the move mode. */
21075 }
21082 /* The floating point conditional move instructions don't directly
21083 support conditions resulting from a signed integer comparison. */
21087 {
21092 }
21099 }
21101 /* Expand a floating-point vector conditional move; a vcond operation
21102 rather than a movcc operation. */
21104 bool
21106 {
21108 rtx cmp;
21113 {
21114 rtx temp;
21116 {
21133 }
21135 OPTAB_DIRECT);
21138 }
21148 }
21150 /* Expand a signed/unsigned integral vector conditional move. */
21152 bool
21154 {
21164 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21165 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21174 {
21178 {
21184 }
21187 {
21193 }
21194 }
21203 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21207 ;
21208 else
21209 {
21210 /* Canonicalize the comparison to EQ, GT, GTU. */
21212 {
21229 /* FALLTHRU */
21239 }
21241 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21243 {
21245 {
21247 /* SSE4.1 supports EQ. */
21254 /* SSE4.2 supports GT/GTU. */
21261 }
21262 }
21264 /* Unsigned parallel compare is not supported by the hardware.
21265 Play some tricks to turn this into a signed comparison
21266 against 0. */
21268 {
21272 {
21279 {
21284 {
21293 }
21294 /* Subtract (-(INT MAX) - 1) from both operands to make
21295 them signed. */
21306 }
21313 /* Perform a parallel unsigned saturating subtraction. */
21326 }
21327 }
21328 }
21330 /* Allow the comparison to be done in one mode, but the movcc to
21331 happen in another mode. */
21333 {
21336 }
21337 else
21338 {
21344 }
21349 }
21351 static bool
21353 {
21356 {
21360 op1));
21365 op1));
21377 }
21378 }
21380 /* Expand a variable vector permutation. */
21382 void
21384 {
21395 /* Number of elements in the vector. */
21404 {
21406 {
21407 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21408 an constant shuffle operand. With a tiny bit of effort we can
21409 use VPERMD instead. A re-interpretation stall for V4DFmode is
21410 unfortunate but there's no avoiding it.
21411 Similarly for V16HImode we don't have instructions for variable
21412 shuffling, while for V32QImode we can use after preparing suitable
21413 masks vpshufb; vpshufb; vpermq; vpor. */
21416 {
21420 }
21421 else
21422 {
21426 }
21429 /* Replicate the low bits of the V4DImode mask into V8SImode:
21430 mask = { A B C D }
21431 t1 = { A A B B C C D D }. */
21439 else
21442 /* Multiply the shuffle indicies by two. */
21444 OPTAB_DIRECT);
21446 /* Add one to the odd shuffle indicies:
21447 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21449 {
21452 }
21456 OPTAB_DIRECT);
21458 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21463 }
21466 {
21468 /* The VPERMD and VPERMPS instructions already properly ignore
21469 the high bits of the shuffle elements. No need for us to
21470 perform an AND ourselves. */
21472 {
21477 }
21478 else
21479 {
21485 }
21492 else
21493 {
21499 }
21503 /* By combining the two 128-bit input vectors into one 256-bit
21504 input vector, we can use VPERMD and VPERMPS for the full
21505 two-operand shuffle. */
21537 /* From mask create two adjusted masks, which contain the same
21538 bits as mask in the low 7 bits of each vector element.
21539 The first mask will have the most significant bit clear
21540 if it requests element from the same 128-bit lane
21541 and MSB set if it requests element from the other 128-bit lane.
21542 The second mask will have the opposite values of the MSB,
21543 and additionally will have its 128-bit lanes swapped.
21544 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21545 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21546 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21547 stands for other 12 bytes. */
21548 /* The bit whether element is from the same lane or the other
21549 lane is bit 4, so shift it up by 3 to the MSB position. */
21553 /* Clear MSB bits from the mask just in case it had them set. */
21555 /* After this t1 will have MSB set for elements from other lane. */
21557 /* Clear bits other than MSB. */
21559 /* Or in the lower bits from mask into t3. */
21561 /* And invert MSB bits in t1, so MSB is set for elements from the same
21562 lane. */
21564 /* Swap 128-bit lanes in t3. */
21569 /* And or in the lower bits from mask into t1. */
21572 {
21573 /* Each of these shuffles will put 0s in places where
21574 element from the other 128-bit lane is needed, otherwise
21575 will shuffle in the requested value. */
21579 /* For t3 the 128-bit lanes are swapped again. */
21584 /* And oring both together leads to the result. */
21591 }
21594 /* Similarly to the above one_operand_shuffle code,
21595 just for repeated twice for each operand. merge_two:
21596 code will merge the two results together. */
21620 }
21621 }
21624 {
21625 /* The XOP VPPERM insn supports three inputs. By ignoring the
21626 one_operand_shuffle special case, we avoid creating another
21627 set of constant vectors in memory. */
21630 /* mask = mask & {2*w-1, ...} */
21632 }
21633 else
21634 {
21635 /* mask = mask & {w-1, ...} */
21637 }
21645 /* For non-QImode operations, convert the word permutation control
21646 into a byte permutation control. */
21648 {
21653 /* Convert mask to vector of chars. */
21656 /* Replicate each of the input bytes into byte positions:
21657 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21658 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21659 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21666 else
21669 /* Convert it into the byte positions by doing
21670 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21676 }
21678 /* The actual shuffle operations all operate on V16QImode. */
21683 {
21690 }
21692 {
21699 }
21700 else
21701 {
21705 /* Shuffle the two input vectors independently. */
21711 merge_two:
21712 /* Then merge them together. The key is whether any given control
21713 element contained a bit set that indicates the second word. */
21717 {
21718 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21719 more shuffle to convert the V2DI input mask into a V4SI
21720 input mask. At which point the masking that expand_int_vcond
21721 will work as desired. */
21729 }
21751 }
21752 }
21754 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21755 true if we should do zero extension, else sign extension. HIGH_P is
21756 true if we want the N/2 high elements, else the low elements. */
21758 void
21760 {
21762 rtx tmp;
21765 {
21771 {
21775 else
21778 extract
21784 else
21787 extract
21793 else
21796 extract
21802 else
21805 extract
21811 else
21814 extract
21820 else
21826 else
21832 else
21837 }
21840 {
21843 }
21845 {
21846 /* Shift higher 8 bytes to lower 8 bytes. */
21851 }
21852 else
21856 }
21857 else
21858 {
21862 {
21866 else
21872 else
21878 else
21883 }
21887 else
21894 }
21895 }
21897 /* Expand conditional increment or decrement using adb/sbb instructions.
21898 The default case using setcc followed by the conditional move can be
21899 done by generic code. */
21900 bool
21902 {
21904 rtx flags;
21906 rtx compare_op;
21924 {
21927 }
21930 {
21934 reverse_condition_maybe_unordered
21936 else
21938 }
21942 /* Construct either adc or sbb insn. */
21944 {
21946 {
21961 }
21962 }
21963 else
21964 {
21966 {
21981 }
21982 }
21986 }
21989 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21990 but works for floating pointer parameters and nonoffsetable memories.
21991 For pushes, it returns just stack offsets; the values will be saved
21992 in the right order. Maximally three parts are generated. */
21994 static int
21996 {
22001 else
22007 /* Optimize constant pool reference to immediates. This is used by fp
22008 moves, that force all constants to memory to allow combining. */
22010 {
22014 }
22017 {
22018 /* The only non-offsetable memories we handle are pushes. */
22027 }
22030 {
22032 /* Caution: if we looked through a constant pool memory above,
22033 the operand may actually have a different mode now. That's
22034 ok, since we want to pun this all the way back to an integer. */
22038 }
22041 {
22044 else
22045 {
22049 {
22053 }
22055 {
22060 }
22062 {
22063 REAL_VALUE_TYPE r;
22068 {
22075 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22076 long double may not be 80-bit. */
22085 }
22088 }
22089 else
22091 }
22092 }
22093 else
22094 {
22098 {
22101 {
22105 }
22107 {
22111 }
22113 {
22114 REAL_VALUE_TYPE r;
22120 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22123 = gen_int_mode
22126 DImode);
22127 else
22134 = gen_int_mode
22137 DImode);
22138 else
22140 }
22141 else
22143 }
22144 }
22147 }
22149 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22150 Return false when normal moves are needed; true when all required
22151 insns have been emitted. Operands 2-4 contain the input values
22152 int the correct order; operands 5-7 contain the output values. */
22154 void
22156 {
22164 /* The DFmode expanders may ask us to move double.
22165 For 64bit target this is single move. By hiding the fact
22166 here we simplify i386.md splitters. */
22168 {
22169 /* Optimize constant pool reference to immediates. This is used by
22170 fp moves, that force all constants to memory to allow combining. */
22177 {
22180 }
22181 else
22186 }
22188 /* The only non-offsettable memory we handle is push. */
22191 else
22198 /* When emitting push, take care for source operands on the stack. */
22201 {
22204 /* Compensate for the stack decrement by 4. */
22209 /* src_base refers to the stack pointer and is
22210 automatically decreased by emitted push. */
22214 }
22216 /* We need to do copy in the right order in case an address register
22217 of the source overlaps the destination. */
22219 {
22220 rtx tmp;
22223 {
22227 collisions++;
22228 }
22230 /* Collision in the middle part can be handled by reordering. */
22232 {
22235 }
22239 {
22241 {
22244 }
22245 else
22246 {
22249 }
22250 }
22252 /* If there are more collisions, we can't handle it by reordering.
22253 Do an lea to the last part and use only one colliding move. */
22255 {
22256 rtx base;
22262 /* Handle the case when the last part isn't valid for lea.
22263 Happens in 64-bit mode storing the 12-byte XFmode. */
22270 {
22273 }
22274 }
22275 }
22278 {
22280 {
22282 {
22287 }
22289 {
22292 }
22293 }
22294 else
22295 {
22296 /* In 64bit mode we don't have 32bit push available. In case this is
22297 register, it is OK - we will just use larger counterpart. We also
22298 retype memory - these comes from attempt to avoid REX prefix on
22299 moving of second half of TFmode value. */
22301 {
22303 {
22314 }
22318 }
22319 }
22323 }
22325 /* Choose correct order to not overwrite the source before it is copied. */
22335 {
22337 {
22340 }
22341 }
22342 else
22343 {
22345 {
22348 }
22349 }
22351 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22353 {
22362 }
22368 }
22370 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22371 left shift by a constant, either using a single shift or
22372 a sequence of add instructions. */
22374 static void
22376 {
22382 {
22386 }
22387 else
22388 {
22391 }
22392 }
22394 void
22396 {
22405 {
22410 {
22416 }
22417 else
22418 {
22426 }
22428 }
22435 {
22436 /* Assuming we've chosen a QImode capable registers, then 1 << N
22437 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22439 {
22455 }
22457 /* Otherwise, we can get the same results by manually performing
22458 a bit extract operation on bit 5/6, and then performing the two
22459 shifts. The two methods of getting 0/1 into low/high are exactly
22460 the same size. Avoiding the shift in the bit extract case helps
22461 pentium4 a bit; no one else seems to care much either way. */
22462 else
22463 {
22468 HOST_WIDE_INT bits;
22469 rtx x;
22472 {
22478 }
22479 else
22480 {
22486 }
22490 else
22498 }
22503 }
22506 {
22507 /* For -1 << N, we can avoid the shld instruction, because we
22508 know that we're shifting 0...31/63 ones into a -1. */
22512 else
22514 }
22515 else
22516 {
22524 }
22529 {
22535 }
22536 else
22537 {
22542 }
22543 }
22545 void
22547 {
22557 {
22562 {
22568 }
22570 {
22579 }
22580 else
22581 {
22589 }
22590 }
22591 else
22592 {
22604 {
22612 scratch));
22613 }
22614 else
22615 {
22620 }
22621 }
22622 }
22624 void
22626 {
22636 {
22641 {
22648 }
22649 else
22650 {
22658 }
22659 }
22660 else
22661 {
22673 {
22679 scratch));
22680 }
22681 else
22682 {
22687 }
22688 }
22689 }
22691 /* Predict just emitted jump instruction to be taken with probability PROB. */
22692 static void
22694 {
22698 }
22700 /* Helper function for the string operations below. Dest VARIABLE whether
22701 it is aligned to VALUE bytes. If true, jump to the label. */
22702 static rtx
22704 {
22709 else
22715 else
22718 }
22720 /* Adjust COUNTER by the VALUE. */
22721 static void
22723 {
22728 }
22730 /* Zero extend possibly SImode EXP to Pmode register. */
22731 rtx
22733 {
22735 }
22737 /* Divide COUNTREG by SCALE. */
22738 static rtx
22740 {
22741 rtx sc;
22753 }
22755 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22756 DImode for constant loop counts. */
22758 static enum machine_mode
22760 {
22768 }
22770 /* Copy the address to a Pmode register. This is used for x32 to
22771 truncate DImode TLS address to a SImode register. */
22773 static rtx
22775 {
22778 else
22779 {
22782 }
22783 }
22785 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22786 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22787 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22788 memory by VALUE (supposed to be in MODE).
22790 The size is rounded down to whole number of chunk size moved at once.
22791 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22794 static void
22799 {
22805 rtx size;
22814 /* Those two should combine. */
22816 {
22820 }
22827 /* This assert could be relaxed - in this case we'll need to compute
22828 smallest power of two, containing in PIECE_SIZE_N and pass it to
22829 offset_address. */
22835 {
22839 /* When unrolling for chips that reorder memory reads and writes,
22840 we can save registers by using single temporary.
22841 Also using 4 temporaries is overkill in 32bit mode. */
22843 {
22845 {
22847 {
22848 destmem =
22850 srcmem =
22852 }
22854 }
22855 }
22856 else
22857 {
22861 {
22864 {
22865 srcmem =
22867 }
22869 }
22871 {
22873 {
22874 destmem =
22876 }
22878 }
22879 }
22880 }
22881 else
22883 {
22885 destmem =
22888 }
22898 {
22904 else
22906 }
22907 else
22915 {
22920 }
22922 }
22924 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22925 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22926 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22927 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22928 ORIG_VALUE is the original value passed to memset to fill the memory with.
22929 Other arguments have same meaning as for previous function. */
22931 static void
22934 rtx count,
22936 {
22937 rtx destexp;
22938 rtx srcexp;
22939 rtx countreg;
22940 HOST_WIDE_INT rounded_count;
22942 /* If possible, it is shorter to use rep movs.
22943 TODO: Maybe it is better to move this logic to decide_alg. */
22954 {
22958 }
22959 else
22962 {
22967 }
22972 {
22975 }
22976 else
22977 {
22981 {
22985 }
22986 else
22989 {
22994 }
22995 else
22996 {
22999 }
23002 }
23003 }
23005 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23006 DESTMEM.
23007 SRC is passed by pointer to be updated on return.
23008 Return value is updated DST. */
23009 static rtx
23011 HOST_WIDE_INT size_to_move)
23012 {
23018 /* Find the widest mode in which we could perform moves.
23019 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23020 it until move of such size is supported. */
23025 {
23029 }
23031 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23032 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23034 {
23039 {
23043 }
23044 }
23050 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23054 {
23055 /* We move from memory to memory, so we'll need to do it via
23056 a temporary register. */
23067 piece_size);
23069 piece_size);
23070 }
23072 /* Update DST and SRC rtx. */
23075 }
23077 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23078 static void
23081 {
23084 {
23089 /* For now MAX_SIZE should be a power of 2. This assert could be
23090 relaxed, but it'll require a bit more complicated epilogue
23091 expanding. */
23094 {
23097 }
23099 }
23101 {
23107 }
23109 /* When there are stringops, we can cheaply increase dest and src pointers.
23110 Otherwise we save code size by maintaining offset (zero is readily
23111 available from preceding rep operation) and using x86 addressing modes.
23112 */
23114 {
23116 {
23123 }
23125 {
23132 }
23134 {
23141 }
23142 }
23143 else
23144 {
23146 rtx tmp;
23149 {
23160 }
23162 {
23175 }
23177 {
23186 }
23187 }
23188 }
23190 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23191 with value PROMOTED_VAL.
23192 SRC is passed by pointer to be updated on return.
23193 Return value is updated DST. */
23194 static rtx
23196 HOST_WIDE_INT size_to_move)
23197 {
23203 /* Find the widest mode in which we could perform moves.
23204 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23205 it until move of such size is supported. */
23210 {
23213 }
23220 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23224 {
23226 {
23229 piece_size);
23231 }
23239 piece_size);
23240 }
23242 /* Update DST rtx. */
23244 }
23245 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23246 static void
23249 {
23250 count =
23256 }
23258 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23259 static void
23262 {
23263 rtx dest;
23266 {
23271 /* For now MAX_SIZE should be a power of 2. This assert could be
23272 relaxed, but it'll require a bit more complicated epilogue
23273 expanding. */
23276 {
23278 {
23281 else
23283 }
23284 }
23286 }
23288 {
23291 }
23293 {
23296 {
23301 }
23302 else
23303 {
23312 }
23315 }
23317 {
23320 {
23323 }
23324 else
23325 {
23330 }
23333 }
23335 {
23341 }
23343 {
23349 }
23351 {
23357 }
23358 }
23360 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23361 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23362 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23363 ignored.
23364 Return value is updated DESTMEM. */
23365 static rtx
23370 {
23373 {
23375 {
23378 {
23381 else
23383 }
23384 else
23390 }
23391 }
23393 }
23395 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23396 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23397 and jump to DONE_LABEL. */
23398 static void
23404 {
23407 rtx modesize;
23410 /* If we do not have vector value to copy, we must reduce size. */
23412 {
23414 {
23419 }
23420 else
23422 }
23423 else
23424 {
23425 /* Choose appropriate vector mode. */
23431 }
23436 {
23439 else
23440 {
23443 }
23445 }
23451 {
23455 }
23457 {
23460 else
23461 {
23464 }
23466 }
23472 }
23474 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23475 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23476 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23477 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23478 DONE_LABEL is a label after the whole copying sequence. The label is created
23479 on demand if *DONE_LABEL is NULL.
23480 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23481 bounds after the initial copies.
23483 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23484 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23485 we will dispatch to a library call for large blocks.
23487 In pseudocode we do:
23489 if (COUNT < SIZE)
23490 {
23491 Assume that SIZE is 4. Bigger sizes are handled analogously
23492 if (COUNT & 4)
23493 {
23494 copy 4 bytes from SRCPTR to DESTPTR
23495 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23496 goto done_label
23497 }
23498 if (!COUNT)
23499 goto done_label;
23500 copy 1 byte from SRCPTR to DESTPTR
23501 if (COUNT & 2)
23502 {
23503 copy 2 bytes from SRCPTR to DESTPTR
23504 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23505 }
23506 }
23507 else
23508 {
23509 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23510 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23512 OLD_DESPTR = DESTPTR;
23513 Align DESTPTR up to DESIRED_ALIGN
23514 SRCPTR += DESTPTR - OLD_DESTPTR
23515 COUNT -= DEST_PTR - OLD_DESTPTR
23516 if (DYNAMIC_CHECK)
23517 Round COUNT down to multiple of SIZE
23518 << optional caller supplied zero size guard is here >>
23519 << optional caller suppplied dynamic check is here >>
23520 << caller supplied main copy loop is here >>
23521 }
23522 done_label:
23523 */
23524 static void
23537 {
23540 rtx modesize;
23542 rtx mode_value;
23544 /* Chose proper value to copy. */
23547 else
23551 /* See if block is big or small, handle small blocks. */
23553 {
23564 /* Handle sizes > 3. */
23571 /* Nothing to copy? Jump to DONE_LABEL if so */
23575 /* Do a byte copy. */
23579 else
23580 {
23583 }
23585 /* Handle sizes 2 and 3. */
23592 else
23593 {
23598 }
23604 }
23605 else
23609 /* Start memcpy for COUNT >= SIZE. */
23611 {
23614 }
23616 /* Copy first desired_align bytes. */
23622 {
23625 else
23626 {
23629 }
23632 }
23635 /* Copy last SIZE bytes. */
23642 else
23643 {
23649 }
23651 {
23655 else
23656 {
23659 }
23660 }
23662 /* Align destination. */
23664 {
23668 /* Align destptr up, place it to new register. */
23675 /* See how many bytes we skipped. */
23679 /* Adjust srcptr and count. */
23685 /* We copied at most size + prolog_size. */
23688 else
23691 /* Our loops always round down the bock size, but for dispatch to library
23692 we need precise value. */
23696 }
23697 else
23698 {
23700 /* Decrease count, so we won't end up copying last word twice. */
23704 else
23708 }
23709 }
23712 /* This function is like the previous one, except here we know how many bytes
23713 need to be copied. That allows us to update alignment not only of DST, which
23714 is returned, but also of SRC, which is passed as a pointer for that
23715 reason. */
23716 static rtx
23721 {
23729 {
23733 }
23738 {
23740 {
23742 {
23745 else
23747 }
23748 else
23751 }
23752 }
23759 {
23765 {
23768 {
23772 }
23777 }
23781 }
23784 }
23786 /* Return true if ALG can be used in current context.
23787 Assume we expand memset if MEMSET is true. */
23788 static bool
23790 {
23795 /* Algorithms using the rep prefix want at least edi and ecx;
23796 additionally, memset wants eax and memcpy wants esi. Don't
23797 consider such algorithms if the user has appropriated those
23798 registers for their own purposes. */
23805 }
23807 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23808 static enum stringop_alg
23812 {
23823 /* Even if the string operation call is cold, we still might spend a lot
23824 of time processing large blocks. */
23830 else
23836 else
23839 /* See maximal size for user defined algorithm. */
23841 {
23848 }
23850 /* If expected size is not known but max size is small enough
23851 so inline version is a win, set expected size into
23852 the range. */
23857 /* If user specified the algorithm, honnor it if possible. */
23861 /* rep; movq or rep; movl is the smallest variant. */
23863 {
23868 else
23871 }
23872 /* Very tiny blocks are best handled via the loop, REP is expensive to
23873 setup. */
23877 {
23881 {
23882 /* We get here if the algorithms that were not libcall-based
23883 were rep-prefix based and we are unable to use rep prefixes
23884 based on global register usage. Break out of the loop and
23885 use the heuristic below. */
23889 {
23893 {
23896 }
23897 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23898 last non-libcall inline algorithm. */
23900 {
23901 /* When the current size is best to be copied by a libcall,
23902 but we are still forced to inline, run the heuristic below
23903 that will pick code for medium sized blocks. */
23905 {
23908 }
23910 }
23912 {
23915 }
23916 }
23917 }
23918 }
23919 /* When asked to inline the call anyway, try to pick meaningful choice.
23920 We look for maximal size of block that is faster to copy by hand and
23921 take blocks of at most of that size guessing that average size will
23922 be roughly half of the block.
23924 If this turns out to be bad, we might simply specify the preferred
23925 choice in ix86_costs. */
23929 {
23932 /* If there aren't any usable algorithms, then recursing on
23933 smaller sizes isn't going to find anything. Just return the
23934 simple byte-at-a-time copy loop. */
23936 {
23937 /* Pick something reasonable. */
23941 }
23951 }
23954 }
23956 /* Decide on alignment. We know that the operand is already aligned to ALIGN
23957 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
23958 static int
23963 {
23974 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
23975 copying whole cacheline at once. */
23988 }
23991 /* Helper function for memcpy. For QImode value 0xXY produce
23992 0xXYXYXYXY of wide specified by MODE. This is essentially
23993 a * 0x10101010, but we can do slightly better than
23994 synth_mult by unwinding the sequence by hand on CPUs with
23995 slow multiply. */
23996 static rtx
23998 {
24000 rtx tmp;
24007 {
24015 }
24024 nops--;
24029 {
24033 OPTAB_DIRECT);
24034 }
24035 else
24036 {
24042 else
24044 else
24045 {
24048 reg =
24050 }
24060 }
24061 }
24063 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24064 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24065 alignment from ALIGN to DESIRED_ALIGN. */
24066 static rtx
24069 {
24070 rtx promoted_val;
24079 else
24083 }
24085 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24086 operations when profitable. The code depends upon architecture, block size
24087 and alignment, but always has one of the following overall structures:
24089 Aligned move sequence:
24091 1) Prologue guard: Conditional that jumps up to epilogues for small
24092 blocks that can be handled by epilogue alone. This is faster
24093 but also needed for correctness, since prologue assume the block
24094 is larger than the desired alignment.
24096 Optional dynamic check for size and libcall for large
24097 blocks is emitted here too, with -minline-stringops-dynamically.
24099 2) Prologue: copy first few bytes in order to get destination
24100 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24101 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24102 copied. We emit either a jump tree on power of two sized
24103 blocks, or a byte loop.
24105 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24106 with specified algorithm.
24108 4) Epilogue: code copying tail of the block that is too small to be
24109 handled by main body (or up to size guarded by prologue guard).
24111 Misaligned move sequence
24113 1) missaligned move prologue/epilogue containing:
24114 a) Prologue handling small memory blocks and jumping to done_label
24115 (skipped if blocks are known to be large enough)
24116 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24117 needed by single possibly misaligned move
24118 (skipped if alignment is not needed)
24119 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24121 2) Zero size guard dispatching to done_label, if needed
24123 3) dispatch to library call, if needed,
24125 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24126 with specified algorithm. */
24127 bool
24133 {
24134 rtx destreg;
24137 rtx tmp;
24153 /* TODO: Once value ranges are available, fill in proper data. */
24161 /* i386 can do misaligned access on reasonably increased cost. */
24165 /* ALIGN is the minimum of destination and source alignment, but we care here
24166 just about destination alignment. */
24174 else
24175 {
24184 }
24186 /* Make sure we don't need to care about overflow later on. */
24190 /* Step 0: Decide on preferred algorithm, desired alignment and
24191 size of chunks to be copied by main loop. */
24193 issetmem,
24200 /* For now vector-version of memset is generated only for memory zeroing, as
24201 creating of promoted vector value is very cheap in this case. */
24214 {
24233 /* Find the widest supported mode. */
24239 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24240 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24242 {
24247 }
24259 }
24267 /* Step 1: Prologue guard. */
24269 /* Alignment code needs count to be in register. */
24271 {
24274 {
24275 align_bytes
24279 else
24281 }
24284 }
24287 /* Misaligned move sequences handle both prologue and epilogue at once.
24288 Default code generation results in a smaller code for large alignments
24289 and also avoids redundant job when sizes are known precisely. */
24290 misaligned_prologue_used
24291 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24297 /* Do the cheap promotion to allow better CSE across the
24298 main loop and epilogue (ie one load of the big constant in the
24299 front of all code.
24300 For now the misaligned move sequences do not have fast path
24301 without broadcasting. */
24303 {
24305 {
24311 }
24312 else
24313 {
24316 }
24317 }
24318 /* Misaligned move sequences handles both prologues and epilogues at once.
24319 Default code generation results in smaller code for large alignments and
24320 also avoids redundant job when sizes are known precisely. */
24322 {
24323 /* Misaligned move prologue handled small blocks by itself. */
24324 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24329 desired_align < align
24338 {
24339 /* It is possible that we copied enough so the main loop will not
24340 execute. */
24350 else
24352 }
24353 }
24354 /* Ensure that alignment prologue won't copy past end of block. */
24356 {
24358 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24359 Make sure it is power of 2. */
24362 /* To improve performance of small blocks, we jump around the VAL
24363 promoting mode. This mean that if the promoted VAL is not constant,
24364 we might not use it in the epilogue and have to use byte
24365 loop variant. */
24370 {
24371 /* If main algorithm works on QImode, no epilogue is needed.
24372 For small sizes just don't align anything. */
24375 else
24377 }
24380 {
24387 else
24389 }
24390 }
24392 /* Emit code to decide on runtime whether library call or inline should be
24393 used. */
24395 {
24397 {
24399 {
24403 }
24404 }
24405 else
24406 {
24415 else
24419 }
24420 }
24422 /* Step 2: Alignment prologue. */
24423 /* Do the expensive promotion once we branched off the small blocks. */
24429 {
24431 {
24432 /* Except for the first move in prologue, we no longer know
24433 constant offset in aliasing info. It don't seems to worth
24434 the pain to maintain it for the first move, so throw away
24435 the info early. */
24442 issetmem);
24443 /* At most desired_align - align bytes are copied. */
24446 else
24448 }
24449 else
24450 {
24451 /* If we know how many bytes need to be stored before dst is
24452 sufficiently aligned, maintain aliasing info accurately. */
24454 srcreg,
24455 promoted_val,
24456 vec_promoted_val,
24457 desired_align,
24458 align_bytes,
24459 issetmem);
24466 }
24468 && !min_size
24473 {
24474 /* It is possible that we copied enough so the main loop will not
24475 execute. */
24485 else
24487 }
24488 }
24490 {
24497 }
24501 /* Step 3: Main loop. */
24504 {
24527 }
24528 /* Adjust properly the offset of src and dest memory for aliasing. */
24530 {
24536 }
24537 else
24538 {
24542 }
24544 /* Step 4: Epilogue to copy the remaining bytes. */
24545 epilogue:
24547 {
24548 /* When the main loop is done, COUNT_EXP might hold original count,
24549 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24550 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24551 bytes. Compensate if needed. */
24554 {
24555 tmp =
24558 OPTAB_DIRECT);
24561 }
24564 }
24567 {
24570 epilogue_size_needed);
24571 else
24572 {
24576 epilogue_size_needed);
24577 else
24579 epilogue_size_needed);
24580 }
24581 }
24585 }
24588 /* Expand the appropriate insns for doing strlen if not just doing
24589 repnz; scasb
24591 out = result, initialized with the start address
24592 align_rtx = alignment of the address.
24593 scratch = scratch register, initialized with the startaddress when
24594 not aligned, otherwise undefined
24596 This is just the body. It needs the initializations mentioned above and
24597 some address computing at the end. These things are done in i386.md. */
24599 static void
24601 {
24603 rtx tmp;
24608 rtx mem;
24611 rtx cmp;
24617 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24619 /* Is there a known alignment and is it less than 4? */
24621 {
24624 /* Is there a known alignment and is it not 2? */
24626 {
24630 /* Leave just the 3 lower bits. */
24640 }
24641 else
24642 {
24643 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24644 check if is aligned to 4 - byte. */
24651 }
24655 /* Now compare the bytes. */
24657 /* Compare the first n unaligned byte on a byte per byte basis. */
24661 /* Increment the address. */
24664 /* Not needed with an alignment of 2 */
24666 {
24670 end_0_label);
24675 }
24678 end_0_label);
24681 }
24683 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24684 align this loop. It gives only huge programs, but does not help to
24685 speed up. */
24692 /* This formula yields a nonzero result iff one of the bytes is zero.
24693 This saves three branches inside loop and many cycles. */
24701 align_4_label);
24704 {
24710 /* If zero is not in the first two bytes, move two bytes forward. */
24716 reg,
24717 tmpreg)));
24718 /* Emit lea manually to avoid clobbering of flags. */
24726 reg2,
24727 out)));
24728 }
24729 else
24730 {
24732 /* Is zero in the first two bytes? */
24739 pc_rtx);
24743 /* Not in the first two. Move two bytes forward. */
24749 }
24751 /* Avoid branch in fixing the byte. */
24759 }
24761 /* Expand strlen. */
24763 bool
24765 {
24768 /* The generic case of strlen expander is long. Avoid it's
24769 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24772 && !TARGET_INLINE_ALL_STRINGOPS
24782 {
24783 /* Well it seems that some optimizer does not combine a call like
24784 foo(strlen(bar), strlen(bar));
24785 when the move and the subtraction is done here. It does calculate
24786 the length just once when these instructions are done inside of
24787 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24788 often used and I use one fewer register for the lifetime of
24789 output_strlen_unroll() this is better. */
24795 /* strlensi_unroll_1 returns the address of the zero at the end of
24796 the string, like memchr(), so compute the length by subtracting
24797 the start address. */
24799 }
24800 else
24801 {
24802 rtx unspec;
24804 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24817 /* If .md starts supporting :P, this can be done in .md. */
24823 }
24825 }
24827 /* For given symbol (function) construct code to compute address of it's PLT
24828 entry in large x86-64 PIC model. */
24829 static rtx
24831 {
24844 }
24846 rtx
24848 rtx callarg2,
24850 {
24851 unsigned int const cregs_size
24862 {
24863 #if TARGET_MACHO
24866 #endif
24867 }
24868 else
24869 {
24870 /* Static functions and indirect calls don't need the pic register. */
24872 && (!TARGET_64BIT
24878 }
24881 {
24885 }
24888 && !TARGET_PECOFF
24896 {
24899 }
24907 {
24911 }
24915 {
24919 UNSPEC_MS_TO_SYSV_CALL);
24922 {
24928 }
24929 }
24938 }
24940 /* Output the assembly for a call instruction. */
24944 {
24950 {
24953 /* SEH epilogue detection requires the indirect branch case
24954 to include REX.W. */
24957 else
24962 }
24964 /* SEH unwinding can require an extra nop to be emitted in several
24965 circumstances. Determine if we have one of those. */
24967 {
24968 rtx i;
24971 {
24972 /* If we get to another real insn, we don't need the nop. */
24976 /* If we get to the epilogue note, prevent a catch region from
24977 being adjacent to the standard epilogue sequence. If non-
24978 call-exceptions, we'll have done this during epilogue emission. */
24980 && !flag_non_call_exceptions
24982 {
24985 }
24986 }
24988 /* If we didn't find a real insn following the call, prevent the
24989 unwinder from looking into the next function. */
24992 }
24996 else
25005 }
25006 \f
25007 /* Clear stack slot assignments remembered from previous functions.
25008 This is called from INIT_EXPANDERS once before RTL is emitted for each
25009 function. */
25013 {
25021 }
25023 /* Return a MEM corresponding to a stack slot with mode MODE.
25024 Allocate a new slot if necessary.
25026 The RTL for a function can have several slots available: N is
25027 which slot to use. */
25029 rtx
25031 {
25048 }
25050 static void
25052 {
25058 }
25059 \f
25060 /* Check whether x86 address PARTS is a pc-relative address. */
25062 static bool
25064 {
25072 {
25074 {
25091 }
25092 }
25094 }
25096 /* Calculate the length of the memory address in the instruction encoding.
25097 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25098 or other prefixes. We never generate addr32 prefix for LEA insn. */
25100 int
25102 {
25119 /* If this is not LEA instruction, add the length of addr32 prefix. */
25124 len++;
25138 /* Rule of thumb:
25139 - esp as the base always wants an index,
25140 - ebp as the base always wants a displacement,
25141 - r12 as the base always wants an index,
25142 - r13 as the base always wants a displacement. */
25144 /* Register Indirect. */
25146 {
25147 /* esp (for its index) and ebp (for its displacement) need
25148 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25149 code. */
25156 len++;
25157 }
25159 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25160 is not disp32, but disp32(%rip), so for disp32
25161 SIB byte is needed, unless print_operand_address
25162 optimizes it into disp32(%rip) or (%rip) is implied
25163 by UNSPEC. */
25165 {
25168 len++;
25169 }
25170 else
25171 {
25172 /* Find the length of the displacement constant. */
25174 {
25177 else
25179 }
25180 /* ebp always wants a displacement. Similarly r13. */
25182 len++;
25184 /* An index requires the two-byte modrm form.... */
25186 /* ...like esp (or r12), which always wants an index. */
25190 len++;
25191 }
25194 }
25196 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25197 is set, expect that insn have 8bit immediate alternative. */
25198 int
25200 {
25206 {
25211 {
25214 {
25226 }
25228 {
25231 }
25232 }
25234 {
25244 /* Immediates for DImode instructions are encoded
25245 as 32bit sign extended values. */
25251 }
25252 }
25254 }
25256 /* Compute default value for "length_address" attribute. */
25257 int
25259 {
25263 {
25274 }
25279 {
25282 {
25287 constraints++;
25290 ;
25291 /* Skip ignored operands. */
25294 }
25296 }
25298 }
25300 /* Compute default value for "length_vex" attribute. It includes
25301 2 or 3 byte VEX prefix and 1 opcode byte. */
25303 int
25305 {
25308 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25309 byte VEX prefix. */
25313 /* We can always use 2 byte VEX prefix in 32bit. */
25321 {
25322 /* REX.W bit uses 3 byte VEX prefix. */
25326 }
25327 else
25328 {
25329 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25333 }
25336 }
25337 \f
25338 /* Return the maximum number of instructions a cpu can issue. */
25340 static int
25342 {
25344 {
25375 }
25376 }
25378 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25379 by DEP_INSN and nothing set by DEP_INSN. */
25381 static bool
25383 {
25386 /* Simplify the test for uninteresting insns. */
25394 {
25397 }
25402 {
25405 }
25406 else
25412 /* This test is true if the dependent insn reads the flags but
25413 not any other potentially set register. */
25421 }
25423 /* Return true iff USE_INSN has a memory address with operands set by
25424 SET_INSN. */
25426 bool
25428 {
25433 {
25436 }
25438 }
25440 /* Helper function for exact_store_load_dependency.
25441 Return true if addr is found in insn. */
25442 static bool
25444 {
25451 {
25457 CASE_CONST_ANY:
25466 }
25470 {
25472 {
25482 }
25483 }
25485 }
25487 /* Return true if there exists exact dependency for store & load, i.e.
25488 the same memory address is used in them. */
25489 static bool
25491 {
25505 }
25507 static int
25509 {
25515 /* Anti and output dependencies have zero cost on all CPUs. */
25521 /* If we can't recognize the insns, we can't really do anything. */
25529 {
25531 /* Address Generation Interlock adds a cycle of latency. */
25533 {
25544 }
25548 /* ??? Compares pair with jump/setcc. */
25552 /* Floating point stores require value to be ready one cycle earlier. */
25560 /* INT->FP conversion is expensive. */
25564 /* There is one cycle extra latency between an FP op and a store. */
25574 /* Show ability of reorder buffer to hide latency of load by executing
25575 in parallel with previous instruction in case
25576 previous instruction is not needed to compute the address. */
25579 {
25580 /* Claim moves to take one cycle, as core can issue one load
25581 at time and the next load can start cycle later. */
25586 cost--;
25587 }
25591 /* The esp dependency is resolved before
25592 the instruction is really finished. */
25597 /* INT->FP conversion is expensive. */
25603 /* Show ability of reorder buffer to hide latency of load by executing
25604 in parallel with previous instruction in case
25605 previous instruction is not needed to compute the address. */
25608 {
25609 /* Claim moves to take one cycle, as core can issue one load
25610 at time and the next load can start cycle later. */
25616 else
25618 }
25629 /* Stack engine allows to execute push&pop instructions in parall. */
25633 /* FALLTHRU */
25639 /* Show ability of reorder buffer to hide latency of load by executing
25640 in parallel with previous instruction in case
25641 previous instruction is not needed to compute the address. */
25644 {
25648 /* Because of the difference between the length of integer and
25649 floating unit pipeline preparation stages, the memory operands
25650 for floating point are cheaper.
25652 ??? For Athlon it the difference is most probably 2. */
25655 else
25660 else
25662 }
25669 /* Stack engine allows to execute push&pop instructions in parall. */
25676 /* Show ability of reorder buffer to hide latency of load by executing
25677 in parallel with previous instruction in case
25678 previous instruction is not needed to compute the address. */
25681 {
25684 else
25686 }
25694 /* Increase cost of integer loads. */
25697 {
25700 {
25703 else
25704 {
25705 /* Increase cost of ld/st for short int types only
25706 because of store forwarding issue. */
25710 {
25711 /* Increase cost of store/load insn if exact
25712 dependence exists and it is load insn. */
25717 }
25718 }
25719 }
25720 }
25724 }
25727 }
25729 /* How many alternative schedules to try. This should be as wide as the
25730 scheduling freedom in the DFA, but no wider. Making this value too
25731 large results extra work for the scheduler. */
25733 static int
25735 {
25737 {
25749 /* We use lookahead value 4 for BD both before and after reload
25750 schedules. Plan is to have value 8 included for O3. */
25760 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25761 as many instructions can be executed on a cycle, i.e.,
25762 issue_rate. I wonder why tuning for many CPUs does not do this. */
25765 /* Don't use lookahead for pre-reload schedule to save compile time. */
25770 }
25771 }
25773 /* Return true if target platform supports macro-fusion. */
25775 static bool
25777 {
25779 }
25781 /* Check whether current microarchitecture support macro fusion
25782 for insn pair "CONDGEN + CONDJMP". Refer to
25783 "Intel Architectures Optimization Reference Manual". */
25785 static bool
25787 {
25806 else
25807 {
25812 {
25816 else
25818 }
25819 }
25826 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25827 supported. */
25834 /* No fusion for RIP-relative address. */
25841 ix86_address parts;
25847 }
25852 /* Check whether conditional jump use Sign or Overflow Flags. */
25860 /* Return true for TYPE_TEST and TYPE_ICMP. */
25865 /* The following is the case that macro-fusion for alu + jmp. */
25869 /* No fusion for alu op with memory destination operand. */
25874 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25875 supported. */
25884 }
25886 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25887 execution. It is applied if
25888 (1) IMUL instruction is on the top of list;
25889 (2) There exists the only producer of independent IMUL instruction in
25890 ready list.
25891 Return index of IMUL producer if it was found and -1 otherwise. */
25892 static int
25894 {
25896 sd_iterator_def sd_it;
25897 dep_t dep;
25904 /* Check that IMUL instruction is on the top of ready list. */
25913 /* Search for producer of independent IMUL instruction. */
25915 {
25919 /* Skip IMUL instruction. */
25929 {
25930 rtx con;
25941 {
25942 sd_iterator_def sd_it1;
25943 dep_t dep1;
25944 /* Check if there is no other dependee for IMUL. */
25947 {
25948 rtx pro;
25954 }
25957 }
25958 }
25961 }
25963 }
25965 /* Try to find the best candidate on the top of ready list if two insns
25966 have the same priority - candidate is best if its dependees were
25967 scheduled earlier. Applied for Silvermont only.
25968 Return true if top 2 insns must be interchanged. */
25969 static bool
25971 {
25974 rtx set;
25975 sd_iterator_def sd_it;
25976 dep_t dep;
25979 #define INSN_TICK(INSN) (HID (INSN)->tick)
26000 {
26003 /* Determine winner more precise. */
26005 {
26006 rtx pro;
26012 }
26014 {
26015 rtx pro;
26021 }
26024 {
26025 /* Determine winner - load must win. */
26031 }
26033 }
26035 #undef INSN_TICK
26036 }
26038 /* Perform possible reodering of ready list for Atom/Silvermont only.
26039 Return issue rate. */
26040 static int
26043 {
26047 rtx insn;
26050 /* Set up issue rate. */
26053 /* Do reodering for BONNELL/SILVERMONT only. */
26057 /* Nothing to do if ready list contains only 1 instruction. */
26061 /* Do reodering for post-reload scheduler only. */
26066 {
26071 /* Put IMUL producer (ready[index]) at the top of ready list. */
26077 }
26079 {
26083 /* Swap 2 top elements of ready list. */
26087 }
26089 }
26091 static bool
26094 /* Returns true if lhs of insn is HW function argument register and set up
26095 is_spilled to true if it is likely spilled HW register. */
26096 static bool
26098 {
26099 rtx dst;
26103 /* Call instructions are not movable, ignore it. */
26114 {
26115 /* Is it likely spilled HW register? */
26120 }
26122 }
26124 /* Add output dependencies for chain of function adjacent arguments if only
26125 there is a move to likely spilled HW register. Return first argument
26126 if at least one dependence was added or NULL otherwise. */
26127 static rtx
26129 {
26130 rtx insn;
26137 /* Find nearest to call argument passing instruction. */
26139 {
26148 }
26152 {
26159 {
26162 }
26164 {
26165 /* Add output depdendence between two function arguments if chain
26166 of output arguments contains likely spilled HW registers. */
26170 }
26171 else
26173 }
26177 }
26179 /* Add output or anti dependency from insn to first_arg to restrict its code
26180 motion. */
26181 static void
26183 {
26184 rtx set;
26185 rtx tmp;
26192 {
26193 /* Add output dependency to the first function argument. */
26196 }
26197 /* Add anti dependency. */
26199 }
26201 /* Avoid cross block motion of function argument through adding dependency
26202 from the first non-jump instruction in bb. */
26203 static void
26205 {
26209 {
26211 {
26214 {
26217 }
26218 }
26222 }
26223 }
26225 /* Hook for pre-reload schedule - avoid motion of function arguments
26226 passed in likely spilled HW registers. */
26227 static void
26229 {
26230 rtx insn;
26238 {
26241 {
26242 /* Add dependee for first argument to predecessors if only
26243 region contains more than one block. */
26247 /* Skip trivial regions and region head blocks that can have
26248 predecessors outside of region. */
26250 {
26251 edge e;
26252 edge_iterator ei;
26253 /* Assume that region is SCC, i.e. all immediate predecessors
26254 of non-head block are in the same region. */
26256 {
26257 /* Avoid creating of loop-carried dependencies through
26258 using topological odering in region. */
26261 }
26262 }
26266 }
26267 }
26270 }
26272 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26273 HW registers to maximum, to schedule them at soon as possible. These are
26274 moves from function argument registers at the top of the function entry
26275 and moves from function return value registers after call. */
26276 static int
26278 {
26279 rtx set;
26289 {
26296 }
26299 }
26301 /* Model decoder of Core 2/i7.
26302 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26303 track the instruction fetch block boundaries and make sure that long
26304 (9+ bytes) instructions are assigned to D0. */
26306 /* Maximum length of an insn that can be handled by
26307 a secondary decoder unit. '8' for Core 2/i7. */
26310 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26311 '16' for Core 2/i7. */
26314 /* Maximum number of instructions decoder can handle per cycle.
26315 '6' for Core 2/i7. */
26319 ix86_first_cycle_multipass_data_t;
26321 const_ix86_first_cycle_multipass_data_t;
26323 /* A variable to store target state across calls to max_issue within
26324 one cycle. */
26328 /* Initialize DATA. */
26329 static void
26331 {
26332 ix86_first_cycle_multipass_data_t data
26339 }
26341 /* Advancing the cycle; reset ifetch block counts. */
26342 static void
26344 {
26351 }
26355 /* Filter out insns from ready_try that the core will not be able to issue
26356 on current cycle due to decoder. */
26357 static void
26358 core2i7_first_cycle_multipass_filter_ready_try
26361 {
26363 {
26364 rtx insn;
26374 (!first_cycle_insn_p
26376 /* ... or it would not fit into the ifetch block ... */
26378 /* ... or the decoder is full already ... */
26380 /* ... mask the insn out. */
26381 {
26386 }
26387 }
26388 }
26390 /* Prepare for a new round of multipass lookahead scheduling. */
26391 static void
26394 {
26395 ix86_first_cycle_multipass_data_t data
26397 const_ix86_first_cycle_multipass_data_t prev_data
26400 /* Restore the state from the end of the previous round. */
26404 /* Filter instructions that cannot be issued on current cycle due to
26405 decoder restrictions. */
26407 first_cycle_insn_p);
26408 }
26410 /* INSN is being issued in current solution. Account for its impact on
26411 the decoder model. */
26412 static void
26415 {
26416 ix86_first_cycle_multipass_data_t data
26418 const_ix86_first_cycle_multipass_data_t prev_data
26428 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26430 {
26433 }
26435 {
26439 }
26442 /* Filter out insns from ready_try that the core will not be able to issue
26443 on current cycle due to decoder. */
26446 }
26448 /* Revert the effect on ready_try. */
26449 static void
26453 {
26454 const_ix86_first_cycle_multipass_data_t data
26457 sbitmap_iterator sbi;
26461 {
26463 }
26464 }
26466 /* Save the result of multipass lookahead scheduling for the next round. */
26467 static void
26469 {
26470 const_ix86_first_cycle_multipass_data_t data
26472 ix86_first_cycle_multipass_data_t next_data
26476 {
26479 }
26480 }
26482 /* Deallocate target data. */
26483 static void
26485 {
26486 ix86_first_cycle_multipass_data_t data
26490 {
26494 }
26495 }
26497 /* Prepare for scheduling pass. */
26498 static void
26502 {
26503 /* Install scheduling hooks for current CPU. Some of these hooks are used
26504 in time-critical parts of the scheduler, so we only set them up when
26505 they are actually used. */
26507 {
26512 /* Do not perform multipass scheduling for pre-reload schedule
26513 to save compile time. */
26515 {
26531 /* Set decoder parameters. */
26536 }
26537 /* ... Fall through ... */
26547 }
26548 }
26550 \f
26551 /* Compute the alignment given to a constant that is being placed in memory.
26552 EXP is the constant and ALIGN is the alignment that the object would
26553 ordinarily have.
26554 The value of this function is used instead of that alignment to align
26555 the object. */
26557 int
26559 {
26562 {
26567 }
26573 }
26575 /* Compute the alignment for a static variable.
26576 TYPE is the data type, and ALIGN is the alignment that
26577 the object would ordinarily have. The value of this function is used
26578 instead of that alignment to align the object. */
26580 int
26582 {
26583 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26584 for symbols from other compilation units or symbols that don't need
26585 to bind locally. In order to preserve some ABI compatibility with
26586 those compilers, ensure we don't decrease alignment from what we
26587 used to assume. */
26589 int max_align_compat
26592 /* A data structure, equal or greater than the size of a cache line
26593 (64 bytes in the Pentium 4 and other recent Intel processors, including
26594 processors based on Intel Core microarchitecture) should be aligned
26595 so that its base address is a multiple of a cache line size. */
26597 int max_align
26607 {
26616 }
26618 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26619 to 16byte boundary. */
26621 {
26628 }
26634 {
26639 }
26641 {
26648 }
26653 {
26658 }
26661 {
26666 }
26669 }
26671 /* Compute the alignment for a local variable or a stack slot. EXP is
26672 the data type or decl itself, MODE is the widest mode available and
26673 ALIGN is the alignment that the object would ordinarily have. The
26674 value of this macro is used instead of that alignment to align the
26675 object. */
26677 unsigned int
26680 {
26684 {
26687 }
26688 else
26689 {
26692 }
26694 /* Don't do dynamic stack realignment for long long objects with
26695 -mpreferred-stack-boundary=2. */
26704 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26705 register in MODE. We will return the largest alignment of XF
26706 and DF. */
26708 {
26712 }
26714 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26715 to 16byte boundary. Exact wording is:
26717 An array uses the same alignment as its elements, except that a local or
26718 global array variable of length at least 16 bytes or
26719 a C99 variable-length array variable always has alignment of at least 16 bytes.
26721 This was added to allow use of aligned SSE instructions at arrays. This
26722 rule is meant for static storage (where compiler can not do the analysis
26723 by itself). We follow it for automatic variables only when convenient.
26724 We fully control everything in the function compiled and functions from
26725 other unit can not rely on the alignment.
26727 Exclude va_list type. It is the common case of local array where
26728 we can not benefit from the alignment.
26730 TODO: Probably one should optimize for size only when var is not escaping. */
26733 {
26743 }
26745 {
26750 }
26752 {
26758 }
26763 {
26768 }
26771 {
26777 }
26779 }
26781 /* Compute the minimum required alignment for dynamic stack realignment
26782 purposes for a local variable, parameter or a stack slot. EXP is
26783 the data type or decl itself, MODE is its mode and ALIGN is the
26784 alignment that the object would ordinarily have. */
26786 unsigned int
26789 {
26793 {
26796 }
26797 else
26798 {
26801 }
26806 /* Don't do dynamic stack realignment for long long objects with
26807 -mpreferred-stack-boundary=2. */
26814 }
26815 \f
26816 /* Find a location for the static chain incoming to a nested function.
26817 This is a register, unless all free registers are used by arguments. */
26819 static rtx
26821 {
26828 {
26829 /* We always use R10 in 64-bit mode. */
26831 }
26832 else
26833 {
26834 tree fntype;
26837 /* By default in 32-bit mode we use ECX to pass the static chain. */
26843 {
26844 /* Fastcall functions use ecx/edx for arguments, which leaves
26845 us with EAX for the static chain.
26846 Thiscall functions use ecx for arguments, which also
26847 leaves us with EAX for the static chain. */
26849 }
26851 {
26852 /* Thiscall functions use ecx for arguments, which leaves
26853 us with EAX and EDX for the static chain.
26854 We are using for abi-compatibility EAX. */
26856 }
26858 {
26859 /* For regparm 3, we have no free call-clobbered registers in
26860 which to store the static chain. In order to implement this,
26861 we have the trampoline push the static chain to the stack.
26862 However, we can't push a value below the return address when
26863 we call the nested function directly, so we have to use an
26864 alternate entry point. For this we use ESI, and have the
26865 alternate entry point push ESI, so that things appear the
26866 same once we're executing the nested function. */
26868 {
26874 }
26876 }
26877 }
26880 }
26882 /* Emit RTL insns to initialize the variable parts of a trampoline.
26883 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26884 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26885 to be passed to the target function. */
26887 static void
26889 {
26897 {
26900 /* Load the function address to r11. Try to load address using
26901 the shorter movl instead of movabs. We may want to support
26902 movq for kernel mode, but kernel does not use trampolines at
26903 the moment. FNADDR is a 32bit address and may not be in
26904 DImode when ptr_mode == SImode. Always use movl in this
26905 case. */
26908 {
26917 }
26918 else
26919 {
26926 }
26928 /* Load static chain using movabs to r10. Use the shorter movl
26929 instead of movabs when ptr_mode == SImode. */
26931 {
26934 }
26935 else
26936 {
26939 }
26948 /* Jump to r11; the last (unused) byte is a nop, only there to
26949 pad the write out to a single 32-bit store. */
26953 }
26954 else
26955 {
26958 /* Depending on the static chain location, either load a register
26959 with a constant, or push the constant to the stack. All of the
26960 instructions are the same size. */
26963 {
26965 {
26972 }
26973 }
26974 else
26989 /* Compute offset from the end of the jmp to the target function.
26990 In the case in which the trampoline stores the static chain on
26991 the stack, we need to skip the first insn which pushes the
26992 (call-saved) register static chain; this push is 1 byte. */
26999 }
27003 #ifdef HAVE_ENABLE_EXECUTE_STACK
27004 #ifdef CHECK_EXECUTE_STACK_ENABLED
27006 #endif
27009 #endif
27010 }
27011 \f
27012 /* The following file contains several enumerations and data structures
27013 built from the definitions in i386-builtin-types.def. */
27017 /* Table for the ix86 builtin non-function types. */
27020 /* Retrieve an element from the above table, building some of
27021 the types lazily. */
27023 static tree
27025 {
27037 {
27045 }
27046 else
27047 {
27053 else
27061 }
27065 }
27067 /* Table for the ix86 builtin function types. */
27070 /* Retrieve an element from the above table, building some of
27071 the types lazily. */
27073 static tree
27075 {
27076 tree type;
27085 {
27093 {
27096 }
27099 }
27100 else
27101 {
27107 }
27111 }
27114 /* Codes for all the SSE/MMX builtins. */
27115 enum ix86_builtins
27116 {
27117 IX86_BUILTIN_ADDPS,
27118 IX86_BUILTIN_ADDSS,
27119 IX86_BUILTIN_DIVPS,
27120 IX86_BUILTIN_DIVSS,
27121 IX86_BUILTIN_MULPS,
27122 IX86_BUILTIN_MULSS,
27123 IX86_BUILTIN_SUBPS,
27124 IX86_BUILTIN_SUBSS,
27126 IX86_BUILTIN_CMPEQPS,
27127 IX86_BUILTIN_CMPLTPS,
27128 IX86_BUILTIN_CMPLEPS,
27129 IX86_BUILTIN_CMPGTPS,
27130 IX86_BUILTIN_CMPGEPS,
27131 IX86_BUILTIN_CMPNEQPS,
27132 IX86_BUILTIN_CMPNLTPS,
27133 IX86_BUILTIN_CMPNLEPS,
27134 IX86_BUILTIN_CMPNGTPS,
27135 IX86_BUILTIN_CMPNGEPS,
27136 IX86_BUILTIN_CMPORDPS,
27137 IX86_BUILTIN_CMPUNORDPS,
27138 IX86_BUILTIN_CMPEQSS,
27139 IX86_BUILTIN_CMPLTSS,
27140 IX86_BUILTIN_CMPLESS,
27141 IX86_BUILTIN_CMPNEQSS,
27142 IX86_BUILTIN_CMPNLTSS,
27143 IX86_BUILTIN_CMPNLESS,
27144 IX86_BUILTIN_CMPORDSS,
27145 IX86_BUILTIN_CMPUNORDSS,
27147 IX86_BUILTIN_COMIEQSS,
27148 IX86_BUILTIN_COMILTSS,
27149 IX86_BUILTIN_COMILESS,
27150 IX86_BUILTIN_COMIGTSS,
27151 IX86_BUILTIN_COMIGESS,
27152 IX86_BUILTIN_COMINEQSS,
27153 IX86_BUILTIN_UCOMIEQSS,
27154 IX86_BUILTIN_UCOMILTSS,
27155 IX86_BUILTIN_UCOMILESS,
27156 IX86_BUILTIN_UCOMIGTSS,
27157 IX86_BUILTIN_UCOMIGESS,
27158 IX86_BUILTIN_UCOMINEQSS,
27160 IX86_BUILTIN_CVTPI2PS,
27161 IX86_BUILTIN_CVTPS2PI,
27162 IX86_BUILTIN_CVTSI2SS,
27163 IX86_BUILTIN_CVTSI642SS,
27164 IX86_BUILTIN_CVTSS2SI,
27165 IX86_BUILTIN_CVTSS2SI64,
27166 IX86_BUILTIN_CVTTPS2PI,
27167 IX86_BUILTIN_CVTTSS2SI,
27168 IX86_BUILTIN_CVTTSS2SI64,
27170 IX86_BUILTIN_MAXPS,
27171 IX86_BUILTIN_MAXSS,
27172 IX86_BUILTIN_MINPS,
27173 IX86_BUILTIN_MINSS,
27175 IX86_BUILTIN_LOADUPS,
27176 IX86_BUILTIN_STOREUPS,
27177 IX86_BUILTIN_MOVSS,
27179 IX86_BUILTIN_MOVHLPS,
27180 IX86_BUILTIN_MOVLHPS,
27181 IX86_BUILTIN_LOADHPS,
27182 IX86_BUILTIN_LOADLPS,
27183 IX86_BUILTIN_STOREHPS,
27184 IX86_BUILTIN_STORELPS,
27186 IX86_BUILTIN_MASKMOVQ,
27187 IX86_BUILTIN_MOVMSKPS,
27188 IX86_BUILTIN_PMOVMSKB,
27190 IX86_BUILTIN_MOVNTPS,
27191 IX86_BUILTIN_MOVNTQ,
27193 IX86_BUILTIN_LOADDQU,
27194 IX86_BUILTIN_STOREDQU,
27196 IX86_BUILTIN_PACKSSWB,
27197 IX86_BUILTIN_PACKSSDW,
27198 IX86_BUILTIN_PACKUSWB,
27200 IX86_BUILTIN_PADDB,
27201 IX86_BUILTIN_PADDW,
27202 IX86_BUILTIN_PADDD,
27203 IX86_BUILTIN_PADDQ,
27204 IX86_BUILTIN_PADDSB,
27205 IX86_BUILTIN_PADDSW,
27206 IX86_BUILTIN_PADDUSB,
27207 IX86_BUILTIN_PADDUSW,
27208 IX86_BUILTIN_PSUBB,
27209 IX86_BUILTIN_PSUBW,
27210 IX86_BUILTIN_PSUBD,
27211 IX86_BUILTIN_PSUBQ,
27212 IX86_BUILTIN_PSUBSB,
27213 IX86_BUILTIN_PSUBSW,
27214 IX86_BUILTIN_PSUBUSB,
27215 IX86_BUILTIN_PSUBUSW,
27217 IX86_BUILTIN_PAND,
27218 IX86_BUILTIN_PANDN,
27219 IX86_BUILTIN_POR,
27220 IX86_BUILTIN_PXOR,
27222 IX86_BUILTIN_PAVGB,
27223 IX86_BUILTIN_PAVGW,
27225 IX86_BUILTIN_PCMPEQB,
27226 IX86_BUILTIN_PCMPEQW,
27227 IX86_BUILTIN_PCMPEQD,
27228 IX86_BUILTIN_PCMPGTB,
27229 IX86_BUILTIN_PCMPGTW,
27230 IX86_BUILTIN_PCMPGTD,
27232 IX86_BUILTIN_PMADDWD,
27234 IX86_BUILTIN_PMAXSW,
27235 IX86_BUILTIN_PMAXUB,
27236 IX86_BUILTIN_PMINSW,
27237 IX86_BUILTIN_PMINUB,
27239 IX86_BUILTIN_PMULHUW,
27240 IX86_BUILTIN_PMULHW,
27241 IX86_BUILTIN_PMULLW,
27243 IX86_BUILTIN_PSADBW,
27244 IX86_BUILTIN_PSHUFW,
27246 IX86_BUILTIN_PSLLW,
27247 IX86_BUILTIN_PSLLD,
27248 IX86_BUILTIN_PSLLQ,
27249 IX86_BUILTIN_PSRAW,
27250 IX86_BUILTIN_PSRAD,
27251 IX86_BUILTIN_PSRLW,
27252 IX86_BUILTIN_PSRLD,
27253 IX86_BUILTIN_PSRLQ,
27254 IX86_BUILTIN_PSLLWI,
27255 IX86_BUILTIN_PSLLDI,
27256 IX86_BUILTIN_PSLLQI,
27257 IX86_BUILTIN_PSRAWI,
27258 IX86_BUILTIN_PSRADI,
27259 IX86_BUILTIN_PSRLWI,
27260 IX86_BUILTIN_PSRLDI,
27261 IX86_BUILTIN_PSRLQI,
27263 IX86_BUILTIN_PUNPCKHBW,
27264 IX86_BUILTIN_PUNPCKHWD,
27265 IX86_BUILTIN_PUNPCKHDQ,
27266 IX86_BUILTIN_PUNPCKLBW,
27267 IX86_BUILTIN_PUNPCKLWD,
27268 IX86_BUILTIN_PUNPCKLDQ,
27270 IX86_BUILTIN_SHUFPS,
27272 IX86_BUILTIN_RCPPS,
27273 IX86_BUILTIN_RCPSS,
27274 IX86_BUILTIN_RSQRTPS,
27275 IX86_BUILTIN_RSQRTPS_NR,
27276 IX86_BUILTIN_RSQRTSS,
27277 IX86_BUILTIN_RSQRTF,
27278 IX86_BUILTIN_SQRTPS,
27279 IX86_BUILTIN_SQRTPS_NR,
27280 IX86_BUILTIN_SQRTSS,
27282 IX86_BUILTIN_UNPCKHPS,
27283 IX86_BUILTIN_UNPCKLPS,
27285 IX86_BUILTIN_ANDPS,
27286 IX86_BUILTIN_ANDNPS,
27287 IX86_BUILTIN_ORPS,
27288 IX86_BUILTIN_XORPS,
27290 IX86_BUILTIN_EMMS,
27291 IX86_BUILTIN_LDMXCSR,
27292 IX86_BUILTIN_STMXCSR,
27293 IX86_BUILTIN_SFENCE,
27295 IX86_BUILTIN_FXSAVE,
27296 IX86_BUILTIN_FXRSTOR,
27297 IX86_BUILTIN_FXSAVE64,
27298 IX86_BUILTIN_FXRSTOR64,
27300 IX86_BUILTIN_XSAVE,
27301 IX86_BUILTIN_XRSTOR,
27302 IX86_BUILTIN_XSAVE64,
27303 IX86_BUILTIN_XRSTOR64,
27305 IX86_BUILTIN_XSAVEOPT,
27306 IX86_BUILTIN_XSAVEOPT64,
27308 /* 3DNow! Original */
27309 IX86_BUILTIN_FEMMS,
27310 IX86_BUILTIN_PAVGUSB,
27311 IX86_BUILTIN_PF2ID,
27312 IX86_BUILTIN_PFACC,
27313 IX86_BUILTIN_PFADD,
27314 IX86_BUILTIN_PFCMPEQ,
27315 IX86_BUILTIN_PFCMPGE,
27316 IX86_BUILTIN_PFCMPGT,
27317 IX86_BUILTIN_PFMAX,
27318 IX86_BUILTIN_PFMIN,
27319 IX86_BUILTIN_PFMUL,
27320 IX86_BUILTIN_PFRCP,
27321 IX86_BUILTIN_PFRCPIT1,
27322 IX86_BUILTIN_PFRCPIT2,
27323 IX86_BUILTIN_PFRSQIT1,
27324 IX86_BUILTIN_PFRSQRT,
27325 IX86_BUILTIN_PFSUB,
27326 IX86_BUILTIN_PFSUBR,
27327 IX86_BUILTIN_PI2FD,
27328 IX86_BUILTIN_PMULHRW,
27330 /* 3DNow! Athlon Extensions */
27331 IX86_BUILTIN_PF2IW,
27332 IX86_BUILTIN_PFNACC,
27333 IX86_BUILTIN_PFPNACC,
27334 IX86_BUILTIN_PI2FW,
27335 IX86_BUILTIN_PSWAPDSI,
27336 IX86_BUILTIN_PSWAPDSF,
27338 /* SSE2 */
27339 IX86_BUILTIN_ADDPD,
27340 IX86_BUILTIN_ADDSD,
27341 IX86_BUILTIN_DIVPD,
27342 IX86_BUILTIN_DIVSD,
27343 IX86_BUILTIN_MULPD,
27344 IX86_BUILTIN_MULSD,
27345 IX86_BUILTIN_SUBPD,
27346 IX86_BUILTIN_SUBSD,
27348 IX86_BUILTIN_CMPEQPD,
27349 IX86_BUILTIN_CMPLTPD,
27350 IX86_BUILTIN_CMPLEPD,
27351 IX86_BUILTIN_CMPGTPD,
27352 IX86_BUILTIN_CMPGEPD,
27353 IX86_BUILTIN_CMPNEQPD,
27354 IX86_BUILTIN_CMPNLTPD,
27355 IX86_BUILTIN_CMPNLEPD,
27356 IX86_BUILTIN_CMPNGTPD,
27357 IX86_BUILTIN_CMPNGEPD,
27358 IX86_BUILTIN_CMPORDPD,
27359 IX86_BUILTIN_CMPUNORDPD,
27360 IX86_BUILTIN_CMPEQSD,
27361 IX86_BUILTIN_CMPLTSD,
27362 IX86_BUILTIN_CMPLESD,
27363 IX86_BUILTIN_CMPNEQSD,
27364 IX86_BUILTIN_CMPNLTSD,
27365 IX86_BUILTIN_CMPNLESD,
27366 IX86_BUILTIN_CMPORDSD,
27367 IX86_BUILTIN_CMPUNORDSD,
27369 IX86_BUILTIN_COMIEQSD,
27370 IX86_BUILTIN_COMILTSD,
27371 IX86_BUILTIN_COMILESD,
27372 IX86_BUILTIN_COMIGTSD,
27373 IX86_BUILTIN_COMIGESD,
27374 IX86_BUILTIN_COMINEQSD,
27375 IX86_BUILTIN_UCOMIEQSD,
27376 IX86_BUILTIN_UCOMILTSD,
27377 IX86_BUILTIN_UCOMILESD,
27378 IX86_BUILTIN_UCOMIGTSD,
27379 IX86_BUILTIN_UCOMIGESD,
27380 IX86_BUILTIN_UCOMINEQSD,
27382 IX86_BUILTIN_MAXPD,
27383 IX86_BUILTIN_MAXSD,
27384 IX86_BUILTIN_MINPD,
27385 IX86_BUILTIN_MINSD,
27387 IX86_BUILTIN_ANDPD,
27388 IX86_BUILTIN_ANDNPD,
27389 IX86_BUILTIN_ORPD,
27390 IX86_BUILTIN_XORPD,
27392 IX86_BUILTIN_SQRTPD,
27393 IX86_BUILTIN_SQRTSD,
27395 IX86_BUILTIN_UNPCKHPD,
27396 IX86_BUILTIN_UNPCKLPD,
27398 IX86_BUILTIN_SHUFPD,
27400 IX86_BUILTIN_LOADUPD,
27401 IX86_BUILTIN_STOREUPD,
27402 IX86_BUILTIN_MOVSD,
27404 IX86_BUILTIN_LOADHPD,
27405 IX86_BUILTIN_LOADLPD,
27407 IX86_BUILTIN_CVTDQ2PD,
27408 IX86_BUILTIN_CVTDQ2PS,
27410 IX86_BUILTIN_CVTPD2DQ,
27411 IX86_BUILTIN_CVTPD2PI,
27412 IX86_BUILTIN_CVTPD2PS,
27413 IX86_BUILTIN_CVTTPD2DQ,
27414 IX86_BUILTIN_CVTTPD2PI,
27416 IX86_BUILTIN_CVTPI2PD,
27417 IX86_BUILTIN_CVTSI2SD,
27418 IX86_BUILTIN_CVTSI642SD,
27420 IX86_BUILTIN_CVTSD2SI,
27421 IX86_BUILTIN_CVTSD2SI64,
27422 IX86_BUILTIN_CVTSD2SS,
27423 IX86_BUILTIN_CVTSS2SD,
27424 IX86_BUILTIN_CVTTSD2SI,
27425 IX86_BUILTIN_CVTTSD2SI64,
27427 IX86_BUILTIN_CVTPS2DQ,
27428 IX86_BUILTIN_CVTPS2PD,
27429 IX86_BUILTIN_CVTTPS2DQ,
27431 IX86_BUILTIN_MOVNTI,
27432 IX86_BUILTIN_MOVNTI64,
27433 IX86_BUILTIN_MOVNTPD,
27434 IX86_BUILTIN_MOVNTDQ,
27436 IX86_BUILTIN_MOVQ128,
27438 /* SSE2 MMX */
27439 IX86_BUILTIN_MASKMOVDQU,
27440 IX86_BUILTIN_MOVMSKPD,
27441 IX86_BUILTIN_PMOVMSKB128,
27443 IX86_BUILTIN_PACKSSWB128,
27444 IX86_BUILTIN_PACKSSDW128,
27445 IX86_BUILTIN_PACKUSWB128,
27447 IX86_BUILTIN_PADDB128,
27448 IX86_BUILTIN_PADDW128,
27449 IX86_BUILTIN_PADDD128,
27450 IX86_BUILTIN_PADDQ128,
27451 IX86_BUILTIN_PADDSB128,
27452 IX86_BUILTIN_PADDSW128,
27453 IX86_BUILTIN_PADDUSB128,
27454 IX86_BUILTIN_PADDUSW128,
27455 IX86_BUILTIN_PSUBB128,
27456 IX86_BUILTIN_PSUBW128,
27457 IX86_BUILTIN_PSUBD128,
27458 IX86_BUILTIN_PSUBQ128,
27459 IX86_BUILTIN_PSUBSB128,
27460 IX86_BUILTIN_PSUBSW128,
27461 IX86_BUILTIN_PSUBUSB128,
27462 IX86_BUILTIN_PSUBUSW128,
27464 IX86_BUILTIN_PAND128,
27465 IX86_BUILTIN_PANDN128,
27466 IX86_BUILTIN_POR128,
27467 IX86_BUILTIN_PXOR128,
27469 IX86_BUILTIN_PAVGB128,
27470 IX86_BUILTIN_PAVGW128,
27472 IX86_BUILTIN_PCMPEQB128,
27473 IX86_BUILTIN_PCMPEQW128,
27474 IX86_BUILTIN_PCMPEQD128,
27475 IX86_BUILTIN_PCMPGTB128,
27476 IX86_BUILTIN_PCMPGTW128,
27477 IX86_BUILTIN_PCMPGTD128,
27479 IX86_BUILTIN_PMADDWD128,
27481 IX86_BUILTIN_PMAXSW128,
27482 IX86_BUILTIN_PMAXUB128,
27483 IX86_BUILTIN_PMINSW128,
27484 IX86_BUILTIN_PMINUB128,
27486 IX86_BUILTIN_PMULUDQ,
27487 IX86_BUILTIN_PMULUDQ128,
27488 IX86_BUILTIN_PMULHUW128,
27489 IX86_BUILTIN_PMULHW128,
27490 IX86_BUILTIN_PMULLW128,
27492 IX86_BUILTIN_PSADBW128,
27493 IX86_BUILTIN_PSHUFHW,
27494 IX86_BUILTIN_PSHUFLW,
27495 IX86_BUILTIN_PSHUFD,
27497 IX86_BUILTIN_PSLLDQI128,
27498 IX86_BUILTIN_PSLLWI128,
27499 IX86_BUILTIN_PSLLDI128,
27500 IX86_BUILTIN_PSLLQI128,
27501 IX86_BUILTIN_PSRAWI128,
27502 IX86_BUILTIN_PSRADI128,
27503 IX86_BUILTIN_PSRLDQI128,
27504 IX86_BUILTIN_PSRLWI128,
27505 IX86_BUILTIN_PSRLDI128,
27506 IX86_BUILTIN_PSRLQI128,
27508 IX86_BUILTIN_PSLLDQ128,
27509 IX86_BUILTIN_PSLLW128,
27510 IX86_BUILTIN_PSLLD128,
27511 IX86_BUILTIN_PSLLQ128,
27512 IX86_BUILTIN_PSRAW128,
27513 IX86_BUILTIN_PSRAD128,
27514 IX86_BUILTIN_PSRLW128,
27515 IX86_BUILTIN_PSRLD128,
27516 IX86_BUILTIN_PSRLQ128,
27518 IX86_BUILTIN_PUNPCKHBW128,
27519 IX86_BUILTIN_PUNPCKHWD128,
27520 IX86_BUILTIN_PUNPCKHDQ128,
27521 IX86_BUILTIN_PUNPCKHQDQ128,
27522 IX86_BUILTIN_PUNPCKLBW128,
27523 IX86_BUILTIN_PUNPCKLWD128,
27524 IX86_BUILTIN_PUNPCKLDQ128,
27525 IX86_BUILTIN_PUNPCKLQDQ128,
27527 IX86_BUILTIN_CLFLUSH,
27528 IX86_BUILTIN_MFENCE,
27529 IX86_BUILTIN_LFENCE,
27530 IX86_BUILTIN_PAUSE,
27532 IX86_BUILTIN_FNSTENV,
27533 IX86_BUILTIN_FLDENV,
27534 IX86_BUILTIN_FNSTSW,
27535 IX86_BUILTIN_FNCLEX,
27537 IX86_BUILTIN_BSRSI,
27538 IX86_BUILTIN_BSRDI,
27539 IX86_BUILTIN_RDPMC,
27540 IX86_BUILTIN_RDTSC,
27541 IX86_BUILTIN_RDTSCP,
27542 IX86_BUILTIN_ROLQI,
27543 IX86_BUILTIN_ROLHI,
27544 IX86_BUILTIN_RORQI,
27545 IX86_BUILTIN_RORHI,
27547 /* SSE3. */
27548 IX86_BUILTIN_ADDSUBPS,
27549 IX86_BUILTIN_HADDPS,
27550 IX86_BUILTIN_HSUBPS,
27551 IX86_BUILTIN_MOVSHDUP,
27552 IX86_BUILTIN_MOVSLDUP,
27553 IX86_BUILTIN_ADDSUBPD,
27554 IX86_BUILTIN_HADDPD,
27555 IX86_BUILTIN_HSUBPD,
27556 IX86_BUILTIN_LDDQU,
27558 IX86_BUILTIN_MONITOR,
27559 IX86_BUILTIN_MWAIT,
27561 /* SSSE3. */
27562 IX86_BUILTIN_PHADDW,
27563 IX86_BUILTIN_PHADDD,
27564 IX86_BUILTIN_PHADDSW,
27565 IX86_BUILTIN_PHSUBW,
27566 IX86_BUILTIN_PHSUBD,
27567 IX86_BUILTIN_PHSUBSW,
27568 IX86_BUILTIN_PMADDUBSW,
27569 IX86_BUILTIN_PMULHRSW,
27570 IX86_BUILTIN_PSHUFB,
27571 IX86_BUILTIN_PSIGNB,
27572 IX86_BUILTIN_PSIGNW,
27573 IX86_BUILTIN_PSIGND,
27574 IX86_BUILTIN_PALIGNR,
27575 IX86_BUILTIN_PABSB,
27576 IX86_BUILTIN_PABSW,
27577 IX86_BUILTIN_PABSD,
27579 IX86_BUILTIN_PHADDW128,
27580 IX86_BUILTIN_PHADDD128,
27581 IX86_BUILTIN_PHADDSW128,
27582 IX86_BUILTIN_PHSUBW128,
27583 IX86_BUILTIN_PHSUBD128,
27584 IX86_BUILTIN_PHSUBSW128,
27585 IX86_BUILTIN_PMADDUBSW128,
27586 IX86_BUILTIN_PMULHRSW128,
27587 IX86_BUILTIN_PSHUFB128,
27588 IX86_BUILTIN_PSIGNB128,
27589 IX86_BUILTIN_PSIGNW128,
27590 IX86_BUILTIN_PSIGND128,
27591 IX86_BUILTIN_PALIGNR128,
27592 IX86_BUILTIN_PABSB128,
27593 IX86_BUILTIN_PABSW128,
27594 IX86_BUILTIN_PABSD128,
27596 /* AMDFAM10 - SSE4A New Instructions. */
27597 IX86_BUILTIN_MOVNTSD,
27598 IX86_BUILTIN_MOVNTSS,
27599 IX86_BUILTIN_EXTRQI,
27600 IX86_BUILTIN_EXTRQ,
27601 IX86_BUILTIN_INSERTQI,
27602 IX86_BUILTIN_INSERTQ,
27604 /* SSE4.1. */
27605 IX86_BUILTIN_BLENDPD,
27606 IX86_BUILTIN_BLENDPS,
27607 IX86_BUILTIN_BLENDVPD,
27608 IX86_BUILTIN_BLENDVPS,
27609 IX86_BUILTIN_PBLENDVB128,
27610 IX86_BUILTIN_PBLENDW128,
27612 IX86_BUILTIN_DPPD,
27613 IX86_BUILTIN_DPPS,
27615 IX86_BUILTIN_INSERTPS128,
27617 IX86_BUILTIN_MOVNTDQA,
27618 IX86_BUILTIN_MPSADBW128,
27619 IX86_BUILTIN_PACKUSDW128,
27620 IX86_BUILTIN_PCMPEQQ,
27621 IX86_BUILTIN_PHMINPOSUW128,
27623 IX86_BUILTIN_PMAXSB128,
27624 IX86_BUILTIN_PMAXSD128,
27625 IX86_BUILTIN_PMAXUD128,
27626 IX86_BUILTIN_PMAXUW128,
27628 IX86_BUILTIN_PMINSB128,
27629 IX86_BUILTIN_PMINSD128,
27630 IX86_BUILTIN_PMINUD128,
27631 IX86_BUILTIN_PMINUW128,
27633 IX86_BUILTIN_PMOVSXBW128,
27634 IX86_BUILTIN_PMOVSXBD128,
27635 IX86_BUILTIN_PMOVSXBQ128,
27636 IX86_BUILTIN_PMOVSXWD128,
27637 IX86_BUILTIN_PMOVSXWQ128,
27638 IX86_BUILTIN_PMOVSXDQ128,
27640 IX86_BUILTIN_PMOVZXBW128,
27641 IX86_BUILTIN_PMOVZXBD128,
27642 IX86_BUILTIN_PMOVZXBQ128,
27643 IX86_BUILTIN_PMOVZXWD128,
27644 IX86_BUILTIN_PMOVZXWQ128,
27645 IX86_BUILTIN_PMOVZXDQ128,
27647 IX86_BUILTIN_PMULDQ128,
27648 IX86_BUILTIN_PMULLD128,
27650 IX86_BUILTIN_ROUNDSD,
27651 IX86_BUILTIN_ROUNDSS,
27653 IX86_BUILTIN_ROUNDPD,
27654 IX86_BUILTIN_ROUNDPS,
27656 IX86_BUILTIN_FLOORPD,
27657 IX86_BUILTIN_CEILPD,
27658 IX86_BUILTIN_TRUNCPD,
27659 IX86_BUILTIN_RINTPD,
27660 IX86_BUILTIN_ROUNDPD_AZ,
27662 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27663 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27664 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27666 IX86_BUILTIN_FLOORPS,
27667 IX86_BUILTIN_CEILPS,
27668 IX86_BUILTIN_TRUNCPS,
27669 IX86_BUILTIN_RINTPS,
27670 IX86_BUILTIN_ROUNDPS_AZ,
27672 IX86_BUILTIN_FLOORPS_SFIX,
27673 IX86_BUILTIN_CEILPS_SFIX,
27674 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27676 IX86_BUILTIN_PTESTZ,
27677 IX86_BUILTIN_PTESTC,
27678 IX86_BUILTIN_PTESTNZC,
27680 IX86_BUILTIN_VEC_INIT_V2SI,
27681 IX86_BUILTIN_VEC_INIT_V4HI,
27682 IX86_BUILTIN_VEC_INIT_V8QI,
27683 IX86_BUILTIN_VEC_EXT_V2DF,
27684 IX86_BUILTIN_VEC_EXT_V2DI,
27685 IX86_BUILTIN_VEC_EXT_V4SF,
27686 IX86_BUILTIN_VEC_EXT_V4SI,
27687 IX86_BUILTIN_VEC_EXT_V8HI,
27688 IX86_BUILTIN_VEC_EXT_V2SI,
27689 IX86_BUILTIN_VEC_EXT_V4HI,
27690 IX86_BUILTIN_VEC_EXT_V16QI,
27691 IX86_BUILTIN_VEC_SET_V2DI,
27692 IX86_BUILTIN_VEC_SET_V4SF,
27693 IX86_BUILTIN_VEC_SET_V4SI,
27694 IX86_BUILTIN_VEC_SET_V8HI,
27695 IX86_BUILTIN_VEC_SET_V4HI,
27696 IX86_BUILTIN_VEC_SET_V16QI,
27698 IX86_BUILTIN_VEC_PACK_SFIX,
27699 IX86_BUILTIN_VEC_PACK_SFIX256,
27701 /* SSE4.2. */
27702 IX86_BUILTIN_CRC32QI,
27703 IX86_BUILTIN_CRC32HI,
27704 IX86_BUILTIN_CRC32SI,
27705 IX86_BUILTIN_CRC32DI,
27707 IX86_BUILTIN_PCMPESTRI128,
27708 IX86_BUILTIN_PCMPESTRM128,
27709 IX86_BUILTIN_PCMPESTRA128,
27710 IX86_BUILTIN_PCMPESTRC128,
27711 IX86_BUILTIN_PCMPESTRO128,
27712 IX86_BUILTIN_PCMPESTRS128,
27713 IX86_BUILTIN_PCMPESTRZ128,
27714 IX86_BUILTIN_PCMPISTRI128,
27715 IX86_BUILTIN_PCMPISTRM128,
27716 IX86_BUILTIN_PCMPISTRA128,
27717 IX86_BUILTIN_PCMPISTRC128,
27718 IX86_BUILTIN_PCMPISTRO128,
27719 IX86_BUILTIN_PCMPISTRS128,
27720 IX86_BUILTIN_PCMPISTRZ128,
27722 IX86_BUILTIN_PCMPGTQ,
27724 /* AES instructions */
27725 IX86_BUILTIN_AESENC128,
27726 IX86_BUILTIN_AESENCLAST128,
27727 IX86_BUILTIN_AESDEC128,
27728 IX86_BUILTIN_AESDECLAST128,
27729 IX86_BUILTIN_AESIMC128,
27730 IX86_BUILTIN_AESKEYGENASSIST128,
27732 /* PCLMUL instruction */
27733 IX86_BUILTIN_PCLMULQDQ128,
27735 /* AVX */
27736 IX86_BUILTIN_ADDPD256,
27737 IX86_BUILTIN_ADDPS256,
27738 IX86_BUILTIN_ADDSUBPD256,
27739 IX86_BUILTIN_ADDSUBPS256,
27740 IX86_BUILTIN_ANDPD256,
27741 IX86_BUILTIN_ANDPS256,
27742 IX86_BUILTIN_ANDNPD256,
27743 IX86_BUILTIN_ANDNPS256,
27744 IX86_BUILTIN_BLENDPD256,
27745 IX86_BUILTIN_BLENDPS256,
27746 IX86_BUILTIN_BLENDVPD256,
27747 IX86_BUILTIN_BLENDVPS256,
27748 IX86_BUILTIN_DIVPD256,
27749 IX86_BUILTIN_DIVPS256,
27750 IX86_BUILTIN_DPPS256,
27751 IX86_BUILTIN_HADDPD256,
27752 IX86_BUILTIN_HADDPS256,
27753 IX86_BUILTIN_HSUBPD256,
27754 IX86_BUILTIN_HSUBPS256,
27755 IX86_BUILTIN_MAXPD256,
27756 IX86_BUILTIN_MAXPS256,
27757 IX86_BUILTIN_MINPD256,
27758 IX86_BUILTIN_MINPS256,
27759 IX86_BUILTIN_MULPD256,
27760 IX86_BUILTIN_MULPS256,
27761 IX86_BUILTIN_ORPD256,
27762 IX86_BUILTIN_ORPS256,
27763 IX86_BUILTIN_SHUFPD256,
27764 IX86_BUILTIN_SHUFPS256,
27765 IX86_BUILTIN_SUBPD256,
27766 IX86_BUILTIN_SUBPS256,
27767 IX86_BUILTIN_XORPD256,
27768 IX86_BUILTIN_XORPS256,
27769 IX86_BUILTIN_CMPSD,
27770 IX86_BUILTIN_CMPSS,
27771 IX86_BUILTIN_CMPPD,
27772 IX86_BUILTIN_CMPPS,
27773 IX86_BUILTIN_CMPPD256,
27774 IX86_BUILTIN_CMPPS256,
27775 IX86_BUILTIN_CVTDQ2PD256,
27776 IX86_BUILTIN_CVTDQ2PS256,
27777 IX86_BUILTIN_CVTPD2PS256,
27778 IX86_BUILTIN_CVTPS2DQ256,
27779 IX86_BUILTIN_CVTPS2PD256,
27780 IX86_BUILTIN_CVTTPD2DQ256,
27781 IX86_BUILTIN_CVTPD2DQ256,
27782 IX86_BUILTIN_CVTTPS2DQ256,
27783 IX86_BUILTIN_EXTRACTF128PD256,
27784 IX86_BUILTIN_EXTRACTF128PS256,
27785 IX86_BUILTIN_EXTRACTF128SI256,
27786 IX86_BUILTIN_VZEROALL,
27787 IX86_BUILTIN_VZEROUPPER,
27788 IX86_BUILTIN_VPERMILVARPD,
27789 IX86_BUILTIN_VPERMILVARPS,
27790 IX86_BUILTIN_VPERMILVARPD256,
27791 IX86_BUILTIN_VPERMILVARPS256,
27792 IX86_BUILTIN_VPERMILPD,
27793 IX86_BUILTIN_VPERMILPS,
27794 IX86_BUILTIN_VPERMILPD256,
27795 IX86_BUILTIN_VPERMILPS256,
27796 IX86_BUILTIN_VPERMIL2PD,
27797 IX86_BUILTIN_VPERMIL2PS,
27798 IX86_BUILTIN_VPERMIL2PD256,
27799 IX86_BUILTIN_VPERMIL2PS256,
27800 IX86_BUILTIN_VPERM2F128PD256,
27801 IX86_BUILTIN_VPERM2F128PS256,
27802 IX86_BUILTIN_VPERM2F128SI256,
27803 IX86_BUILTIN_VBROADCASTSS,
27804 IX86_BUILTIN_VBROADCASTSD256,
27805 IX86_BUILTIN_VBROADCASTSS256,
27806 IX86_BUILTIN_VBROADCASTPD256,
27807 IX86_BUILTIN_VBROADCASTPS256,
27808 IX86_BUILTIN_VINSERTF128PD256,
27809 IX86_BUILTIN_VINSERTF128PS256,
27810 IX86_BUILTIN_VINSERTF128SI256,
27811 IX86_BUILTIN_LOADUPD256,
27812 IX86_BUILTIN_LOADUPS256,
27813 IX86_BUILTIN_STOREUPD256,
27814 IX86_BUILTIN_STOREUPS256,
27815 IX86_BUILTIN_LDDQU256,
27816 IX86_BUILTIN_MOVNTDQ256,
27817 IX86_BUILTIN_MOVNTPD256,
27818 IX86_BUILTIN_MOVNTPS256,
27819 IX86_BUILTIN_LOADDQU256,
27820 IX86_BUILTIN_STOREDQU256,
27821 IX86_BUILTIN_MASKLOADPD,
27822 IX86_BUILTIN_MASKLOADPS,
27823 IX86_BUILTIN_MASKSTOREPD,
27824 IX86_BUILTIN_MASKSTOREPS,
27825 IX86_BUILTIN_MASKLOADPD256,
27826 IX86_BUILTIN_MASKLOADPS256,
27827 IX86_BUILTIN_MASKSTOREPD256,
27828 IX86_BUILTIN_MASKSTOREPS256,
27829 IX86_BUILTIN_MOVSHDUP256,
27830 IX86_BUILTIN_MOVSLDUP256,
27831 IX86_BUILTIN_MOVDDUP256,
27833 IX86_BUILTIN_SQRTPD256,
27834 IX86_BUILTIN_SQRTPS256,
27835 IX86_BUILTIN_SQRTPS_NR256,
27836 IX86_BUILTIN_RSQRTPS256,
27837 IX86_BUILTIN_RSQRTPS_NR256,
27839 IX86_BUILTIN_RCPPS256,
27841 IX86_BUILTIN_ROUNDPD256,
27842 IX86_BUILTIN_ROUNDPS256,
27844 IX86_BUILTIN_FLOORPD256,
27845 IX86_BUILTIN_CEILPD256,
27846 IX86_BUILTIN_TRUNCPD256,
27847 IX86_BUILTIN_RINTPD256,
27848 IX86_BUILTIN_ROUNDPD_AZ256,
27850 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27851 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27852 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27854 IX86_BUILTIN_FLOORPS256,
27855 IX86_BUILTIN_CEILPS256,
27856 IX86_BUILTIN_TRUNCPS256,
27857 IX86_BUILTIN_RINTPS256,
27858 IX86_BUILTIN_ROUNDPS_AZ256,
27860 IX86_BUILTIN_FLOORPS_SFIX256,
27861 IX86_BUILTIN_CEILPS_SFIX256,
27862 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27864 IX86_BUILTIN_UNPCKHPD256,
27865 IX86_BUILTIN_UNPCKLPD256,
27866 IX86_BUILTIN_UNPCKHPS256,
27867 IX86_BUILTIN_UNPCKLPS256,
27869 IX86_BUILTIN_SI256_SI,
27870 IX86_BUILTIN_PS256_PS,
27871 IX86_BUILTIN_PD256_PD,
27872 IX86_BUILTIN_SI_SI256,
27873 IX86_BUILTIN_PS_PS256,
27874 IX86_BUILTIN_PD_PD256,
27876 IX86_BUILTIN_VTESTZPD,
27877 IX86_BUILTIN_VTESTCPD,
27878 IX86_BUILTIN_VTESTNZCPD,
27879 IX86_BUILTIN_VTESTZPS,
27880 IX86_BUILTIN_VTESTCPS,
27881 IX86_BUILTIN_VTESTNZCPS,
27882 IX86_BUILTIN_VTESTZPD256,
27883 IX86_BUILTIN_VTESTCPD256,
27884 IX86_BUILTIN_VTESTNZCPD256,
27885 IX86_BUILTIN_VTESTZPS256,
27886 IX86_BUILTIN_VTESTCPS256,
27887 IX86_BUILTIN_VTESTNZCPS256,
27888 IX86_BUILTIN_PTESTZ256,
27889 IX86_BUILTIN_PTESTC256,
27890 IX86_BUILTIN_PTESTNZC256,
27892 IX86_BUILTIN_MOVMSKPD256,
27893 IX86_BUILTIN_MOVMSKPS256,
27895 /* AVX2 */
27896 IX86_BUILTIN_MPSADBW256,
27897 IX86_BUILTIN_PABSB256,
27898 IX86_BUILTIN_PABSW256,
27899 IX86_BUILTIN_PABSD256,
27900 IX86_BUILTIN_PACKSSDW256,
27901 IX86_BUILTIN_PACKSSWB256,
27902 IX86_BUILTIN_PACKUSDW256,
27903 IX86_BUILTIN_PACKUSWB256,
27904 IX86_BUILTIN_PADDB256,
27905 IX86_BUILTIN_PADDW256,
27906 IX86_BUILTIN_PADDD256,
27907 IX86_BUILTIN_PADDQ256,
27908 IX86_BUILTIN_PADDSB256,
27909 IX86_BUILTIN_PADDSW256,
27910 IX86_BUILTIN_PADDUSB256,
27911 IX86_BUILTIN_PADDUSW256,
27912 IX86_BUILTIN_PALIGNR256,
27913 IX86_BUILTIN_AND256I,
27914 IX86_BUILTIN_ANDNOT256I,
27915 IX86_BUILTIN_PAVGB256,
27916 IX86_BUILTIN_PAVGW256,
27917 IX86_BUILTIN_PBLENDVB256,
27918 IX86_BUILTIN_PBLENDVW256,
27919 IX86_BUILTIN_PCMPEQB256,
27920 IX86_BUILTIN_PCMPEQW256,
27921 IX86_BUILTIN_PCMPEQD256,
27922 IX86_BUILTIN_PCMPEQQ256,
27923 IX86_BUILTIN_PCMPGTB256,
27924 IX86_BUILTIN_PCMPGTW256,
27925 IX86_BUILTIN_PCMPGTD256,
27926 IX86_BUILTIN_PCMPGTQ256,
27927 IX86_BUILTIN_PHADDW256,
27928 IX86_BUILTIN_PHADDD256,
27929 IX86_BUILTIN_PHADDSW256,
27930 IX86_BUILTIN_PHSUBW256,
27931 IX86_BUILTIN_PHSUBD256,
27932 IX86_BUILTIN_PHSUBSW256,
27933 IX86_BUILTIN_PMADDUBSW256,
27934 IX86_BUILTIN_PMADDWD256,
27935 IX86_BUILTIN_PMAXSB256,
27936 IX86_BUILTIN_PMAXSW256,
27937 IX86_BUILTIN_PMAXSD256,
27938 IX86_BUILTIN_PMAXUB256,
27939 IX86_BUILTIN_PMAXUW256,
27940 IX86_BUILTIN_PMAXUD256,
27941 IX86_BUILTIN_PMINSB256,
27942 IX86_BUILTIN_PMINSW256,
27943 IX86_BUILTIN_PMINSD256,
27944 IX86_BUILTIN_PMINUB256,
27945 IX86_BUILTIN_PMINUW256,
27946 IX86_BUILTIN_PMINUD256,
27947 IX86_BUILTIN_PMOVMSKB256,
27948 IX86_BUILTIN_PMOVSXBW256,
27949 IX86_BUILTIN_PMOVSXBD256,
27950 IX86_BUILTIN_PMOVSXBQ256,
27951 IX86_BUILTIN_PMOVSXWD256,
27952 IX86_BUILTIN_PMOVSXWQ256,
27953 IX86_BUILTIN_PMOVSXDQ256,
27954 IX86_BUILTIN_PMOVZXBW256,
27955 IX86_BUILTIN_PMOVZXBD256,
27956 IX86_BUILTIN_PMOVZXBQ256,
27957 IX86_BUILTIN_PMOVZXWD256,
27958 IX86_BUILTIN_PMOVZXWQ256,
27959 IX86_BUILTIN_PMOVZXDQ256,
27960 IX86_BUILTIN_PMULDQ256,
27961 IX86_BUILTIN_PMULHRSW256,
27962 IX86_BUILTIN_PMULHUW256,
27963 IX86_BUILTIN_PMULHW256,
27964 IX86_BUILTIN_PMULLW256,
27965 IX86_BUILTIN_PMULLD256,
27966 IX86_BUILTIN_PMULUDQ256,
27967 IX86_BUILTIN_POR256,
27968 IX86_BUILTIN_PSADBW256,
27969 IX86_BUILTIN_PSHUFB256,
27970 IX86_BUILTIN_PSHUFD256,
27971 IX86_BUILTIN_PSHUFHW256,
27972 IX86_BUILTIN_PSHUFLW256,
27973 IX86_BUILTIN_PSIGNB256,
27974 IX86_BUILTIN_PSIGNW256,
27975 IX86_BUILTIN_PSIGND256,
27976 IX86_BUILTIN_PSLLDQI256,
27977 IX86_BUILTIN_PSLLWI256,
27978 IX86_BUILTIN_PSLLW256,
27979 IX86_BUILTIN_PSLLDI256,
27980 IX86_BUILTIN_PSLLD256,
27981 IX86_BUILTIN_PSLLQI256,
27982 IX86_BUILTIN_PSLLQ256,
27983 IX86_BUILTIN_PSRAWI256,
27984 IX86_BUILTIN_PSRAW256,
27985 IX86_BUILTIN_PSRADI256,
27986 IX86_BUILTIN_PSRAD256,
27987 IX86_BUILTIN_PSRLDQI256,
27988 IX86_BUILTIN_PSRLWI256,
27989 IX86_BUILTIN_PSRLW256,
27990 IX86_BUILTIN_PSRLDI256,
27991 IX86_BUILTIN_PSRLD256,
27992 IX86_BUILTIN_PSRLQI256,
27993 IX86_BUILTIN_PSRLQ256,
27994 IX86_BUILTIN_PSUBB256,
27995 IX86_BUILTIN_PSUBW256,
27996 IX86_BUILTIN_PSUBD256,
27997 IX86_BUILTIN_PSUBQ256,
27998 IX86_BUILTIN_PSUBSB256,
27999 IX86_BUILTIN_PSUBSW256,
28000 IX86_BUILTIN_PSUBUSB256,
28001 IX86_BUILTIN_PSUBUSW256,
28002 IX86_BUILTIN_PUNPCKHBW256,
28003 IX86_BUILTIN_PUNPCKHWD256,
28004 IX86_BUILTIN_PUNPCKHDQ256,
28005 IX86_BUILTIN_PUNPCKHQDQ256,
28006 IX86_BUILTIN_PUNPCKLBW256,
28007 IX86_BUILTIN_PUNPCKLWD256,
28008 IX86_BUILTIN_PUNPCKLDQ256,
28009 IX86_BUILTIN_PUNPCKLQDQ256,
28010 IX86_BUILTIN_PXOR256,
28011 IX86_BUILTIN_MOVNTDQA256,
28012 IX86_BUILTIN_VBROADCASTSS_PS,
28013 IX86_BUILTIN_VBROADCASTSS_PS256,
28014 IX86_BUILTIN_VBROADCASTSD_PD256,
28015 IX86_BUILTIN_VBROADCASTSI256,
28016 IX86_BUILTIN_PBLENDD256,
28017 IX86_BUILTIN_PBLENDD128,
28018 IX86_BUILTIN_PBROADCASTB256,
28019 IX86_BUILTIN_PBROADCASTW256,
28020 IX86_BUILTIN_PBROADCASTD256,
28021 IX86_BUILTIN_PBROADCASTQ256,
28022 IX86_BUILTIN_PBROADCASTB128,
28023 IX86_BUILTIN_PBROADCASTW128,
28024 IX86_BUILTIN_PBROADCASTD128,
28025 IX86_BUILTIN_PBROADCASTQ128,
28026 IX86_BUILTIN_VPERMVARSI256,
28027 IX86_BUILTIN_VPERMDF256,
28028 IX86_BUILTIN_VPERMVARSF256,
28029 IX86_BUILTIN_VPERMDI256,
28030 IX86_BUILTIN_VPERMTI256,
28031 IX86_BUILTIN_VEXTRACT128I256,
28032 IX86_BUILTIN_VINSERT128I256,
28033 IX86_BUILTIN_MASKLOADD,
28034 IX86_BUILTIN_MASKLOADQ,
28035 IX86_BUILTIN_MASKLOADD256,
28036 IX86_BUILTIN_MASKLOADQ256,
28037 IX86_BUILTIN_MASKSTORED,
28038 IX86_BUILTIN_MASKSTOREQ,
28039 IX86_BUILTIN_MASKSTORED256,
28040 IX86_BUILTIN_MASKSTOREQ256,
28041 IX86_BUILTIN_PSLLVV4DI,
28042 IX86_BUILTIN_PSLLVV2DI,
28043 IX86_BUILTIN_PSLLVV8SI,
28044 IX86_BUILTIN_PSLLVV4SI,
28045 IX86_BUILTIN_PSRAVV8SI,
28046 IX86_BUILTIN_PSRAVV4SI,
28047 IX86_BUILTIN_PSRLVV4DI,
28048 IX86_BUILTIN_PSRLVV2DI,
28049 IX86_BUILTIN_PSRLVV8SI,
28050 IX86_BUILTIN_PSRLVV4SI,
28052 IX86_BUILTIN_GATHERSIV2DF,
28053 IX86_BUILTIN_GATHERSIV4DF,
28054 IX86_BUILTIN_GATHERDIV2DF,
28055 IX86_BUILTIN_GATHERDIV4DF,
28056 IX86_BUILTIN_GATHERSIV4SF,
28057 IX86_BUILTIN_GATHERSIV8SF,
28058 IX86_BUILTIN_GATHERDIV4SF,
28059 IX86_BUILTIN_GATHERDIV8SF,
28060 IX86_BUILTIN_GATHERSIV2DI,
28061 IX86_BUILTIN_GATHERSIV4DI,
28062 IX86_BUILTIN_GATHERDIV2DI,
28063 IX86_BUILTIN_GATHERDIV4DI,
28064 IX86_BUILTIN_GATHERSIV4SI,
28065 IX86_BUILTIN_GATHERSIV8SI,
28066 IX86_BUILTIN_GATHERDIV4SI,
28067 IX86_BUILTIN_GATHERDIV8SI,
28069 /* AVX512F */
28070 IX86_BUILTIN_ADDPD512,
28071 IX86_BUILTIN_ADDPS512,
28072 IX86_BUILTIN_ADDSD_ROUND,
28073 IX86_BUILTIN_ADDSS_ROUND,
28074 IX86_BUILTIN_ALIGND512,
28075 IX86_BUILTIN_ALIGNQ512,
28076 IX86_BUILTIN_BLENDMD512,
28077 IX86_BUILTIN_BLENDMPD512,
28078 IX86_BUILTIN_BLENDMPS512,
28079 IX86_BUILTIN_BLENDMQ512,
28080 IX86_BUILTIN_BROADCASTF32X4_512,
28081 IX86_BUILTIN_BROADCASTF64X4_512,
28082 IX86_BUILTIN_BROADCASTI32X4_512,
28083 IX86_BUILTIN_BROADCASTI64X4_512,
28084 IX86_BUILTIN_BROADCASTSD512,
28085 IX86_BUILTIN_BROADCASTSS512,
28086 IX86_BUILTIN_CMPD512,
28087 IX86_BUILTIN_CMPPD512,
28088 IX86_BUILTIN_CMPPS512,
28089 IX86_BUILTIN_CMPQ512,
28090 IX86_BUILTIN_CMPSD_MASK,
28091 IX86_BUILTIN_CMPSS_MASK,
28092 IX86_BUILTIN_COMIDF,
28093 IX86_BUILTIN_COMISF,
28094 IX86_BUILTIN_COMPRESSPD512,
28095 IX86_BUILTIN_COMPRESSPDSTORE512,
28096 IX86_BUILTIN_COMPRESSPS512,
28097 IX86_BUILTIN_COMPRESSPSSTORE512,
28098 IX86_BUILTIN_CVTDQ2PD512,
28099 IX86_BUILTIN_CVTDQ2PS512,
28100 IX86_BUILTIN_CVTPD2DQ512,
28101 IX86_BUILTIN_CVTPD2PS512,
28102 IX86_BUILTIN_CVTPD2UDQ512,
28103 IX86_BUILTIN_CVTPH2PS512,
28104 IX86_BUILTIN_CVTPS2DQ512,
28105 IX86_BUILTIN_CVTPS2PD512,
28106 IX86_BUILTIN_CVTPS2PH512,
28107 IX86_BUILTIN_CVTPS2UDQ512,
28108 IX86_BUILTIN_CVTSD2SS_ROUND,
28109 IX86_BUILTIN_CVTSI2SD64,
28110 IX86_BUILTIN_CVTSI2SS32,
28111 IX86_BUILTIN_CVTSI2SS64,
28112 IX86_BUILTIN_CVTSS2SD_ROUND,
28113 IX86_BUILTIN_CVTTPD2DQ512,
28114 IX86_BUILTIN_CVTTPD2UDQ512,
28115 IX86_BUILTIN_CVTTPS2DQ512,
28116 IX86_BUILTIN_CVTTPS2UDQ512,
28117 IX86_BUILTIN_CVTUDQ2PD512,
28118 IX86_BUILTIN_CVTUDQ2PS512,
28119 IX86_BUILTIN_CVTUSI2SD32,
28120 IX86_BUILTIN_CVTUSI2SD64,
28121 IX86_BUILTIN_CVTUSI2SS32,
28122 IX86_BUILTIN_CVTUSI2SS64,
28123 IX86_BUILTIN_DIVPD512,
28124 IX86_BUILTIN_DIVPS512,
28125 IX86_BUILTIN_DIVSD_ROUND,
28126 IX86_BUILTIN_DIVSS_ROUND,
28127 IX86_BUILTIN_EXPANDPD512,
28128 IX86_BUILTIN_EXPANDPD512Z,
28129 IX86_BUILTIN_EXPANDPDLOAD512,
28130 IX86_BUILTIN_EXPANDPDLOAD512Z,
28131 IX86_BUILTIN_EXPANDPS512,
28132 IX86_BUILTIN_EXPANDPS512Z,
28133 IX86_BUILTIN_EXPANDPSLOAD512,
28134 IX86_BUILTIN_EXPANDPSLOAD512Z,
28135 IX86_BUILTIN_EXTRACTF32X4,
28136 IX86_BUILTIN_EXTRACTF64X4,
28137 IX86_BUILTIN_EXTRACTI32X4,
28138 IX86_BUILTIN_EXTRACTI64X4,
28139 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28140 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28141 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28142 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28143 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28144 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28145 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28146 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28147 IX86_BUILTIN_GETEXPPD512,
28148 IX86_BUILTIN_GETEXPPS512,
28149 IX86_BUILTIN_GETEXPSD128,
28150 IX86_BUILTIN_GETEXPSS128,
28151 IX86_BUILTIN_GETMANTPD512,
28152 IX86_BUILTIN_GETMANTPS512,
28153 IX86_BUILTIN_GETMANTSD128,
28154 IX86_BUILTIN_GETMANTSS128,
28155 IX86_BUILTIN_INSERTF32X4,
28156 IX86_BUILTIN_INSERTF64X4,
28157 IX86_BUILTIN_INSERTI32X4,
28158 IX86_BUILTIN_INSERTI64X4,
28159 IX86_BUILTIN_LOADAPD512,
28160 IX86_BUILTIN_LOADAPS512,
28161 IX86_BUILTIN_LOADDQUDI512,
28162 IX86_BUILTIN_LOADDQUSI512,
28163 IX86_BUILTIN_LOADUPD512,
28164 IX86_BUILTIN_LOADUPS512,
28165 IX86_BUILTIN_MAXPD512,
28166 IX86_BUILTIN_MAXPS512,
28167 IX86_BUILTIN_MAXSD_ROUND,
28168 IX86_BUILTIN_MAXSS_ROUND,
28169 IX86_BUILTIN_MINPD512,
28170 IX86_BUILTIN_MINPS512,
28171 IX86_BUILTIN_MINSD_ROUND,
28172 IX86_BUILTIN_MINSS_ROUND,
28173 IX86_BUILTIN_MOVAPD512,
28174 IX86_BUILTIN_MOVAPS512,
28175 IX86_BUILTIN_MOVDDUP512,
28176 IX86_BUILTIN_MOVDQA32LOAD512,
28177 IX86_BUILTIN_MOVDQA32STORE512,
28178 IX86_BUILTIN_MOVDQA32_512,
28179 IX86_BUILTIN_MOVDQA64LOAD512,
28180 IX86_BUILTIN_MOVDQA64STORE512,
28181 IX86_BUILTIN_MOVDQA64_512,
28182 IX86_BUILTIN_MOVNTDQ512,
28183 IX86_BUILTIN_MOVNTDQA512,
28184 IX86_BUILTIN_MOVNTPD512,
28185 IX86_BUILTIN_MOVNTPS512,
28186 IX86_BUILTIN_MOVSHDUP512,
28187 IX86_BUILTIN_MOVSLDUP512,
28188 IX86_BUILTIN_MULPD512,
28189 IX86_BUILTIN_MULPS512,
28190 IX86_BUILTIN_MULSD_ROUND,
28191 IX86_BUILTIN_MULSS_ROUND,
28192 IX86_BUILTIN_PABSD512,
28193 IX86_BUILTIN_PABSQ512,
28194 IX86_BUILTIN_PADDD512,
28195 IX86_BUILTIN_PADDQ512,
28196 IX86_BUILTIN_PANDD512,
28197 IX86_BUILTIN_PANDND512,
28198 IX86_BUILTIN_PANDNQ512,
28199 IX86_BUILTIN_PANDQ512,
28200 IX86_BUILTIN_PBROADCASTD512,
28201 IX86_BUILTIN_PBROADCASTD512_GPR,
28202 IX86_BUILTIN_PBROADCASTMB512,
28203 IX86_BUILTIN_PBROADCASTMW512,
28204 IX86_BUILTIN_PBROADCASTQ512,
28205 IX86_BUILTIN_PBROADCASTQ512_GPR,
28206 IX86_BUILTIN_PBROADCASTQ512_MEM,
28207 IX86_BUILTIN_PCMPEQD512_MASK,
28208 IX86_BUILTIN_PCMPEQQ512_MASK,
28209 IX86_BUILTIN_PCMPGTD512_MASK,
28210 IX86_BUILTIN_PCMPGTQ512_MASK,
28211 IX86_BUILTIN_PCOMPRESSD512,
28212 IX86_BUILTIN_PCOMPRESSDSTORE512,
28213 IX86_BUILTIN_PCOMPRESSQ512,
28214 IX86_BUILTIN_PCOMPRESSQSTORE512,
28215 IX86_BUILTIN_PEXPANDD512,
28216 IX86_BUILTIN_PEXPANDD512Z,
28217 IX86_BUILTIN_PEXPANDDLOAD512,
28218 IX86_BUILTIN_PEXPANDDLOAD512Z,
28219 IX86_BUILTIN_PEXPANDQ512,
28220 IX86_BUILTIN_PEXPANDQ512Z,
28221 IX86_BUILTIN_PEXPANDQLOAD512,
28222 IX86_BUILTIN_PEXPANDQLOAD512Z,
28223 IX86_BUILTIN_PMAXSD512,
28224 IX86_BUILTIN_PMAXSQ512,
28225 IX86_BUILTIN_PMAXUD512,
28226 IX86_BUILTIN_PMAXUQ512,
28227 IX86_BUILTIN_PMINSD512,
28228 IX86_BUILTIN_PMINSQ512,
28229 IX86_BUILTIN_PMINUD512,
28230 IX86_BUILTIN_PMINUQ512,
28231 IX86_BUILTIN_PMOVDB512,
28232 IX86_BUILTIN_PMOVDB512_MEM,
28233 IX86_BUILTIN_PMOVDW512,
28234 IX86_BUILTIN_PMOVDW512_MEM,
28235 IX86_BUILTIN_PMOVQB512,
28236 IX86_BUILTIN_PMOVQB512_MEM,
28237 IX86_BUILTIN_PMOVQD512,
28238 IX86_BUILTIN_PMOVQD512_MEM,
28239 IX86_BUILTIN_PMOVQW512,
28240 IX86_BUILTIN_PMOVQW512_MEM,
28241 IX86_BUILTIN_PMOVSDB512,
28242 IX86_BUILTIN_PMOVSDB512_MEM,
28243 IX86_BUILTIN_PMOVSDW512,
28244 IX86_BUILTIN_PMOVSDW512_MEM,
28245 IX86_BUILTIN_PMOVSQB512,
28246 IX86_BUILTIN_PMOVSQB512_MEM,
28247 IX86_BUILTIN_PMOVSQD512,
28248 IX86_BUILTIN_PMOVSQD512_MEM,
28249 IX86_BUILTIN_PMOVSQW512,
28250 IX86_BUILTIN_PMOVSQW512_MEM,
28251 IX86_BUILTIN_PMOVSXBD512,
28252 IX86_BUILTIN_PMOVSXBQ512,
28253 IX86_BUILTIN_PMOVSXDQ512,
28254 IX86_BUILTIN_PMOVSXWD512,
28255 IX86_BUILTIN_PMOVSXWQ512,
28256 IX86_BUILTIN_PMOVUSDB512,
28257 IX86_BUILTIN_PMOVUSDB512_MEM,
28258 IX86_BUILTIN_PMOVUSDW512,
28259 IX86_BUILTIN_PMOVUSDW512_MEM,
28260 IX86_BUILTIN_PMOVUSQB512,
28261 IX86_BUILTIN_PMOVUSQB512_MEM,
28262 IX86_BUILTIN_PMOVUSQD512,
28263 IX86_BUILTIN_PMOVUSQD512_MEM,
28264 IX86_BUILTIN_PMOVUSQW512,
28265 IX86_BUILTIN_PMOVUSQW512_MEM,
28266 IX86_BUILTIN_PMOVZXBD512,
28267 IX86_BUILTIN_PMOVZXBQ512,
28268 IX86_BUILTIN_PMOVZXDQ512,
28269 IX86_BUILTIN_PMOVZXWD512,
28270 IX86_BUILTIN_PMOVZXWQ512,
28271 IX86_BUILTIN_PMULDQ512,
28272 IX86_BUILTIN_PMULLD512,
28273 IX86_BUILTIN_PMULUDQ512,
28274 IX86_BUILTIN_PORD512,
28275 IX86_BUILTIN_PORQ512,
28276 IX86_BUILTIN_PROLD512,
28277 IX86_BUILTIN_PROLQ512,
28278 IX86_BUILTIN_PROLVD512,
28279 IX86_BUILTIN_PROLVQ512,
28280 IX86_BUILTIN_PRORD512,
28281 IX86_BUILTIN_PRORQ512,
28282 IX86_BUILTIN_PRORVD512,
28283 IX86_BUILTIN_PRORVQ512,
28284 IX86_BUILTIN_PSHUFD512,
28285 IX86_BUILTIN_PSLLD512,
28286 IX86_BUILTIN_PSLLDI512,
28287 IX86_BUILTIN_PSLLQ512,
28288 IX86_BUILTIN_PSLLQI512,
28289 IX86_BUILTIN_PSLLVV16SI,
28290 IX86_BUILTIN_PSLLVV8DI,
28291 IX86_BUILTIN_PSRAD512,
28292 IX86_BUILTIN_PSRADI512,
28293 IX86_BUILTIN_PSRAQ512,
28294 IX86_BUILTIN_PSRAQI512,
28295 IX86_BUILTIN_PSRAVV16SI,
28296 IX86_BUILTIN_PSRAVV8DI,
28297 IX86_BUILTIN_PSRLD512,
28298 IX86_BUILTIN_PSRLDI512,
28299 IX86_BUILTIN_PSRLQ512,
28300 IX86_BUILTIN_PSRLQI512,
28301 IX86_BUILTIN_PSRLVV16SI,
28302 IX86_BUILTIN_PSRLVV8DI,
28303 IX86_BUILTIN_PSUBD512,
28304 IX86_BUILTIN_PSUBQ512,
28305 IX86_BUILTIN_PTESTMD512,
28306 IX86_BUILTIN_PTESTMQ512,
28307 IX86_BUILTIN_PTESTNMD512,
28308 IX86_BUILTIN_PTESTNMQ512,
28309 IX86_BUILTIN_PUNPCKHDQ512,
28310 IX86_BUILTIN_PUNPCKHQDQ512,
28311 IX86_BUILTIN_PUNPCKLDQ512,
28312 IX86_BUILTIN_PUNPCKLQDQ512,
28313 IX86_BUILTIN_PXORD512,
28314 IX86_BUILTIN_PXORQ512,
28315 IX86_BUILTIN_RCP14PD512,
28316 IX86_BUILTIN_RCP14PS512,
28317 IX86_BUILTIN_RCP14SD,
28318 IX86_BUILTIN_RCP14SS,
28319 IX86_BUILTIN_RNDSCALEPD,
28320 IX86_BUILTIN_RNDSCALEPS,
28321 IX86_BUILTIN_RNDSCALESD,
28322 IX86_BUILTIN_RNDSCALESS,
28323 IX86_BUILTIN_RSQRT14PD512,
28324 IX86_BUILTIN_RSQRT14PS512,
28325 IX86_BUILTIN_RSQRT14SD,
28326 IX86_BUILTIN_RSQRT14SS,
28327 IX86_BUILTIN_SCALEFPD512,
28328 IX86_BUILTIN_SCALEFPS512,
28329 IX86_BUILTIN_SCALEFSD,
28330 IX86_BUILTIN_SCALEFSS,
28331 IX86_BUILTIN_SHUFPD512,
28332 IX86_BUILTIN_SHUFPS512,
28333 IX86_BUILTIN_SHUF_F32x4,
28334 IX86_BUILTIN_SHUF_F64x2,
28335 IX86_BUILTIN_SHUF_I32x4,
28336 IX86_BUILTIN_SHUF_I64x2,
28337 IX86_BUILTIN_SQRTPD512,
28338 IX86_BUILTIN_SQRTPD512_MASK,
28339 IX86_BUILTIN_SQRTPS512_MASK,
28340 IX86_BUILTIN_SQRTPS_NR512,
28341 IX86_BUILTIN_SQRTSD_ROUND,
28342 IX86_BUILTIN_SQRTSS_ROUND,
28343 IX86_BUILTIN_STOREAPD512,
28344 IX86_BUILTIN_STOREAPS512,
28345 IX86_BUILTIN_STOREDQUDI512,
28346 IX86_BUILTIN_STOREDQUSI512,
28347 IX86_BUILTIN_STOREUPD512,
28348 IX86_BUILTIN_STOREUPS512,
28349 IX86_BUILTIN_SUBPD512,
28350 IX86_BUILTIN_SUBPS512,
28351 IX86_BUILTIN_SUBSD_ROUND,
28352 IX86_BUILTIN_SUBSS_ROUND,
28353 IX86_BUILTIN_UCMPD512,
28354 IX86_BUILTIN_UCMPQ512,
28355 IX86_BUILTIN_UNPCKHPD512,
28356 IX86_BUILTIN_UNPCKHPS512,
28357 IX86_BUILTIN_UNPCKLPD512,
28358 IX86_BUILTIN_UNPCKLPS512,
28359 IX86_BUILTIN_VCVTSD2SI32,
28360 IX86_BUILTIN_VCVTSD2SI64,
28361 IX86_BUILTIN_VCVTSD2USI32,
28362 IX86_BUILTIN_VCVTSD2USI64,
28363 IX86_BUILTIN_VCVTSS2SI32,
28364 IX86_BUILTIN_VCVTSS2SI64,
28365 IX86_BUILTIN_VCVTSS2USI32,
28366 IX86_BUILTIN_VCVTSS2USI64,
28367 IX86_BUILTIN_VCVTTSD2SI32,
28368 IX86_BUILTIN_VCVTTSD2SI64,
28369 IX86_BUILTIN_VCVTTSD2USI32,
28370 IX86_BUILTIN_VCVTTSD2USI64,
28371 IX86_BUILTIN_VCVTTSS2SI32,
28372 IX86_BUILTIN_VCVTTSS2SI64,
28373 IX86_BUILTIN_VCVTTSS2USI32,
28374 IX86_BUILTIN_VCVTTSS2USI64,
28375 IX86_BUILTIN_VFMADDPD512_MASK,
28376 IX86_BUILTIN_VFMADDPD512_MASK3,
28377 IX86_BUILTIN_VFMADDPD512_MASKZ,
28378 IX86_BUILTIN_VFMADDPS512_MASK,
28379 IX86_BUILTIN_VFMADDPS512_MASK3,
28380 IX86_BUILTIN_VFMADDPS512_MASKZ,
28381 IX86_BUILTIN_VFMADDSD3_ROUND,
28382 IX86_BUILTIN_VFMADDSS3_ROUND,
28383 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28384 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28385 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28386 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28387 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28388 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28389 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28390 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28391 IX86_BUILTIN_VFMSUBPD512_MASK3,
28392 IX86_BUILTIN_VFMSUBPS512_MASK3,
28393 IX86_BUILTIN_VFMSUBSD3_MASK3,
28394 IX86_BUILTIN_VFMSUBSS3_MASK3,
28395 IX86_BUILTIN_VFNMADDPD512_MASK,
28396 IX86_BUILTIN_VFNMADDPS512_MASK,
28397 IX86_BUILTIN_VFNMSUBPD512_MASK,
28398 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28399 IX86_BUILTIN_VFNMSUBPS512_MASK,
28400 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28401 IX86_BUILTIN_VPCLZCNTD512,
28402 IX86_BUILTIN_VPCLZCNTQ512,
28403 IX86_BUILTIN_VPCONFLICTD512,
28404 IX86_BUILTIN_VPCONFLICTQ512,
28405 IX86_BUILTIN_VPERMDF512,
28406 IX86_BUILTIN_VPERMDI512,
28407 IX86_BUILTIN_VPERMI2VARD512,
28408 IX86_BUILTIN_VPERMI2VARPD512,
28409 IX86_BUILTIN_VPERMI2VARPS512,
28410 IX86_BUILTIN_VPERMI2VARQ512,
28411 IX86_BUILTIN_VPERMILPD512,
28412 IX86_BUILTIN_VPERMILPS512,
28413 IX86_BUILTIN_VPERMILVARPD512,
28414 IX86_BUILTIN_VPERMILVARPS512,
28415 IX86_BUILTIN_VPERMT2VARD512,
28416 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28417 IX86_BUILTIN_VPERMT2VARPD512,
28418 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28419 IX86_BUILTIN_VPERMT2VARPS512,
28420 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28421 IX86_BUILTIN_VPERMT2VARQ512,
28422 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28423 IX86_BUILTIN_VPERMVARDF512,
28424 IX86_BUILTIN_VPERMVARDI512,
28425 IX86_BUILTIN_VPERMVARSF512,
28426 IX86_BUILTIN_VPERMVARSI512,
28427 IX86_BUILTIN_VTERNLOGD512_MASK,
28428 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28429 IX86_BUILTIN_VTERNLOGQ512_MASK,
28430 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28432 /* Mask arithmetic operations */
28433 IX86_BUILTIN_KAND16,
28434 IX86_BUILTIN_KANDN16,
28435 IX86_BUILTIN_KNOT16,
28436 IX86_BUILTIN_KOR16,
28437 IX86_BUILTIN_KORTESTC16,
28438 IX86_BUILTIN_KORTESTZ16,
28439 IX86_BUILTIN_KUNPCKBW,
28440 IX86_BUILTIN_KXNOR16,
28441 IX86_BUILTIN_KXOR16,
28442 IX86_BUILTIN_KMOV16,
28444 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28445 where all operands are 32-byte or 64-byte wide respectively. */
28446 IX86_BUILTIN_GATHERALTSIV4DF,
28447 IX86_BUILTIN_GATHERALTDIV8SF,
28448 IX86_BUILTIN_GATHERALTSIV4DI,
28449 IX86_BUILTIN_GATHERALTDIV8SI,
28450 IX86_BUILTIN_GATHER3ALTDIV16SF,
28451 IX86_BUILTIN_GATHER3ALTDIV16SI,
28452 IX86_BUILTIN_GATHER3ALTSIV8DF,
28453 IX86_BUILTIN_GATHER3ALTSIV8DI,
28454 IX86_BUILTIN_GATHER3DIV16SF,
28455 IX86_BUILTIN_GATHER3DIV16SI,
28456 IX86_BUILTIN_GATHER3DIV8DF,
28457 IX86_BUILTIN_GATHER3DIV8DI,
28458 IX86_BUILTIN_GATHER3SIV16SF,
28459 IX86_BUILTIN_GATHER3SIV16SI,
28460 IX86_BUILTIN_GATHER3SIV8DF,
28461 IX86_BUILTIN_GATHER3SIV8DI,
28462 IX86_BUILTIN_SCATTERDIV16SF,
28463 IX86_BUILTIN_SCATTERDIV16SI,
28464 IX86_BUILTIN_SCATTERDIV8DF,
28465 IX86_BUILTIN_SCATTERDIV8DI,
28466 IX86_BUILTIN_SCATTERSIV16SF,
28467 IX86_BUILTIN_SCATTERSIV16SI,
28468 IX86_BUILTIN_SCATTERSIV8DF,
28469 IX86_BUILTIN_SCATTERSIV8DI,
28471 /* AVX512PF */
28472 IX86_BUILTIN_GATHERPFQPD,
28473 IX86_BUILTIN_GATHERPFDPS,
28474 IX86_BUILTIN_GATHERPFDPD,
28475 IX86_BUILTIN_GATHERPFQPS,
28476 IX86_BUILTIN_SCATTERPFDPD,
28477 IX86_BUILTIN_SCATTERPFDPS,
28478 IX86_BUILTIN_SCATTERPFQPD,
28479 IX86_BUILTIN_SCATTERPFQPS,
28481 /* AVX-512ER */
28482 IX86_BUILTIN_EXP2PD_MASK,
28483 IX86_BUILTIN_EXP2PS_MASK,
28484 IX86_BUILTIN_EXP2PS,
28485 IX86_BUILTIN_RCP28PD,
28486 IX86_BUILTIN_RCP28PS,
28487 IX86_BUILTIN_RCP28SD,
28488 IX86_BUILTIN_RCP28SS,
28489 IX86_BUILTIN_RSQRT28PD,
28490 IX86_BUILTIN_RSQRT28PS,
28491 IX86_BUILTIN_RSQRT28SD,
28492 IX86_BUILTIN_RSQRT28SS,
28494 /* SHA builtins. */
28495 IX86_BUILTIN_SHA1MSG1,
28496 IX86_BUILTIN_SHA1MSG2,
28497 IX86_BUILTIN_SHA1NEXTE,
28498 IX86_BUILTIN_SHA1RNDS4,
28499 IX86_BUILTIN_SHA256MSG1,
28500 IX86_BUILTIN_SHA256MSG2,
28501 IX86_BUILTIN_SHA256RNDS2,
28503 /* TFmode support builtins. */
28504 IX86_BUILTIN_INFQ,
28505 IX86_BUILTIN_HUGE_VALQ,
28506 IX86_BUILTIN_FABSQ,
28507 IX86_BUILTIN_COPYSIGNQ,
28509 /* Vectorizer support builtins. */
28510 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28511 IX86_BUILTIN_CPYSGNPS,
28512 IX86_BUILTIN_CPYSGNPD,
28513 IX86_BUILTIN_CPYSGNPS256,
28514 IX86_BUILTIN_CPYSGNPS512,
28515 IX86_BUILTIN_CPYSGNPD256,
28516 IX86_BUILTIN_CPYSGNPD512,
28517 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28518 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28521 /* FMA4 instructions. */
28522 IX86_BUILTIN_VFMADDSS,
28523 IX86_BUILTIN_VFMADDSD,
28524 IX86_BUILTIN_VFMADDPS,
28525 IX86_BUILTIN_VFMADDPD,
28526 IX86_BUILTIN_VFMADDPS256,
28527 IX86_BUILTIN_VFMADDPD256,
28528 IX86_BUILTIN_VFMADDSUBPS,
28529 IX86_BUILTIN_VFMADDSUBPD,
28530 IX86_BUILTIN_VFMADDSUBPS256,
28531 IX86_BUILTIN_VFMADDSUBPD256,
28533 /* FMA3 instructions. */
28534 IX86_BUILTIN_VFMADDSS3,
28535 IX86_BUILTIN_VFMADDSD3,
28537 /* XOP instructions. */
28538 IX86_BUILTIN_VPCMOV,
28539 IX86_BUILTIN_VPCMOV_V2DI,
28540 IX86_BUILTIN_VPCMOV_V4SI,
28541 IX86_BUILTIN_VPCMOV_V8HI,
28542 IX86_BUILTIN_VPCMOV_V16QI,
28543 IX86_BUILTIN_VPCMOV_V4SF,
28544 IX86_BUILTIN_VPCMOV_V2DF,
28545 IX86_BUILTIN_VPCMOV256,
28546 IX86_BUILTIN_VPCMOV_V4DI256,
28547 IX86_BUILTIN_VPCMOV_V8SI256,
28548 IX86_BUILTIN_VPCMOV_V16HI256,
28549 IX86_BUILTIN_VPCMOV_V32QI256,
28550 IX86_BUILTIN_VPCMOV_V8SF256,
28551 IX86_BUILTIN_VPCMOV_V4DF256,
28553 IX86_BUILTIN_VPPERM,
28555 IX86_BUILTIN_VPMACSSWW,
28556 IX86_BUILTIN_VPMACSWW,
28557 IX86_BUILTIN_VPMACSSWD,
28558 IX86_BUILTIN_VPMACSWD,
28559 IX86_BUILTIN_VPMACSSDD,
28560 IX86_BUILTIN_VPMACSDD,
28561 IX86_BUILTIN_VPMACSSDQL,
28562 IX86_BUILTIN_VPMACSSDQH,
28563 IX86_BUILTIN_VPMACSDQL,
28564 IX86_BUILTIN_VPMACSDQH,
28565 IX86_BUILTIN_VPMADCSSWD,
28566 IX86_BUILTIN_VPMADCSWD,
28568 IX86_BUILTIN_VPHADDBW,
28569 IX86_BUILTIN_VPHADDBD,
28570 IX86_BUILTIN_VPHADDBQ,
28571 IX86_BUILTIN_VPHADDWD,
28572 IX86_BUILTIN_VPHADDWQ,
28573 IX86_BUILTIN_VPHADDDQ,
28574 IX86_BUILTIN_VPHADDUBW,
28575 IX86_BUILTIN_VPHADDUBD,
28576 IX86_BUILTIN_VPHADDUBQ,
28577 IX86_BUILTIN_VPHADDUWD,
28578 IX86_BUILTIN_VPHADDUWQ,
28579 IX86_BUILTIN_VPHADDUDQ,
28580 IX86_BUILTIN_VPHSUBBW,
28581 IX86_BUILTIN_VPHSUBWD,
28582 IX86_BUILTIN_VPHSUBDQ,
28584 IX86_BUILTIN_VPROTB,
28585 IX86_BUILTIN_VPROTW,
28586 IX86_BUILTIN_VPROTD,
28587 IX86_BUILTIN_VPROTQ,
28588 IX86_BUILTIN_VPROTB_IMM,
28589 IX86_BUILTIN_VPROTW_IMM,
28590 IX86_BUILTIN_VPROTD_IMM,
28591 IX86_BUILTIN_VPROTQ_IMM,
28593 IX86_BUILTIN_VPSHLB,
28594 IX86_BUILTIN_VPSHLW,
28595 IX86_BUILTIN_VPSHLD,
28596 IX86_BUILTIN_VPSHLQ,
28597 IX86_BUILTIN_VPSHAB,
28598 IX86_BUILTIN_VPSHAW,
28599 IX86_BUILTIN_VPSHAD,
28600 IX86_BUILTIN_VPSHAQ,
28602 IX86_BUILTIN_VFRCZSS,
28603 IX86_BUILTIN_VFRCZSD,
28604 IX86_BUILTIN_VFRCZPS,
28605 IX86_BUILTIN_VFRCZPD,
28606 IX86_BUILTIN_VFRCZPS256,
28607 IX86_BUILTIN_VFRCZPD256,
28609 IX86_BUILTIN_VPCOMEQUB,
28610 IX86_BUILTIN_VPCOMNEUB,
28611 IX86_BUILTIN_VPCOMLTUB,
28612 IX86_BUILTIN_VPCOMLEUB,
28613 IX86_BUILTIN_VPCOMGTUB,
28614 IX86_BUILTIN_VPCOMGEUB,
28615 IX86_BUILTIN_VPCOMFALSEUB,
28616 IX86_BUILTIN_VPCOMTRUEUB,
28618 IX86_BUILTIN_VPCOMEQUW,
28619 IX86_BUILTIN_VPCOMNEUW,
28620 IX86_BUILTIN_VPCOMLTUW,
28621 IX86_BUILTIN_VPCOMLEUW,
28622 IX86_BUILTIN_VPCOMGTUW,
28623 IX86_BUILTIN_VPCOMGEUW,
28624 IX86_BUILTIN_VPCOMFALSEUW,
28625 IX86_BUILTIN_VPCOMTRUEUW,
28627 IX86_BUILTIN_VPCOMEQUD,
28628 IX86_BUILTIN_VPCOMNEUD,
28629 IX86_BUILTIN_VPCOMLTUD,
28630 IX86_BUILTIN_VPCOMLEUD,
28631 IX86_BUILTIN_VPCOMGTUD,
28632 IX86_BUILTIN_VPCOMGEUD,
28633 IX86_BUILTIN_VPCOMFALSEUD,
28634 IX86_BUILTIN_VPCOMTRUEUD,
28636 IX86_BUILTIN_VPCOMEQUQ,
28637 IX86_BUILTIN_VPCOMNEUQ,
28638 IX86_BUILTIN_VPCOMLTUQ,
28639 IX86_BUILTIN_VPCOMLEUQ,
28640 IX86_BUILTIN_VPCOMGTUQ,
28641 IX86_BUILTIN_VPCOMGEUQ,
28642 IX86_BUILTIN_VPCOMFALSEUQ,
28643 IX86_BUILTIN_VPCOMTRUEUQ,
28645 IX86_BUILTIN_VPCOMEQB,
28646 IX86_BUILTIN_VPCOMNEB,
28647 IX86_BUILTIN_VPCOMLTB,
28648 IX86_BUILTIN_VPCOMLEB,
28649 IX86_BUILTIN_VPCOMGTB,
28650 IX86_BUILTIN_VPCOMGEB,
28651 IX86_BUILTIN_VPCOMFALSEB,
28652 IX86_BUILTIN_VPCOMTRUEB,
28654 IX86_BUILTIN_VPCOMEQW,
28655 IX86_BUILTIN_VPCOMNEW,
28656 IX86_BUILTIN_VPCOMLTW,
28657 IX86_BUILTIN_VPCOMLEW,
28658 IX86_BUILTIN_VPCOMGTW,
28659 IX86_BUILTIN_VPCOMGEW,
28660 IX86_BUILTIN_VPCOMFALSEW,
28661 IX86_BUILTIN_VPCOMTRUEW,
28663 IX86_BUILTIN_VPCOMEQD,
28664 IX86_BUILTIN_VPCOMNED,
28665 IX86_BUILTIN_VPCOMLTD,
28666 IX86_BUILTIN_VPCOMLED,
28667 IX86_BUILTIN_VPCOMGTD,
28668 IX86_BUILTIN_VPCOMGED,
28669 IX86_BUILTIN_VPCOMFALSED,
28670 IX86_BUILTIN_VPCOMTRUED,
28672 IX86_BUILTIN_VPCOMEQQ,
28673 IX86_BUILTIN_VPCOMNEQ,
28674 IX86_BUILTIN_VPCOMLTQ,
28675 IX86_BUILTIN_VPCOMLEQ,
28676 IX86_BUILTIN_VPCOMGTQ,
28677 IX86_BUILTIN_VPCOMGEQ,
28678 IX86_BUILTIN_VPCOMFALSEQ,
28679 IX86_BUILTIN_VPCOMTRUEQ,
28681 /* LWP instructions. */
28682 IX86_BUILTIN_LLWPCB,
28683 IX86_BUILTIN_SLWPCB,
28684 IX86_BUILTIN_LWPVAL32,
28685 IX86_BUILTIN_LWPVAL64,
28686 IX86_BUILTIN_LWPINS32,
28687 IX86_BUILTIN_LWPINS64,
28689 IX86_BUILTIN_CLZS,
28691 /* RTM */
28692 IX86_BUILTIN_XBEGIN,
28693 IX86_BUILTIN_XEND,
28694 IX86_BUILTIN_XABORT,
28695 IX86_BUILTIN_XTEST,
28697 /* BMI instructions. */
28698 IX86_BUILTIN_BEXTR32,
28699 IX86_BUILTIN_BEXTR64,
28700 IX86_BUILTIN_CTZS,
28702 /* TBM instructions. */
28703 IX86_BUILTIN_BEXTRI32,
28704 IX86_BUILTIN_BEXTRI64,
28706 /* BMI2 instructions. */
28707 IX86_BUILTIN_BZHI32,
28708 IX86_BUILTIN_BZHI64,
28709 IX86_BUILTIN_PDEP32,
28710 IX86_BUILTIN_PDEP64,
28711 IX86_BUILTIN_PEXT32,
28712 IX86_BUILTIN_PEXT64,
28714 /* ADX instructions. */
28715 IX86_BUILTIN_ADDCARRYX32,
28716 IX86_BUILTIN_ADDCARRYX64,
28718 /* FSGSBASE instructions. */
28719 IX86_BUILTIN_RDFSBASE32,
28720 IX86_BUILTIN_RDFSBASE64,
28721 IX86_BUILTIN_RDGSBASE32,
28722 IX86_BUILTIN_RDGSBASE64,
28723 IX86_BUILTIN_WRFSBASE32,
28724 IX86_BUILTIN_WRFSBASE64,
28725 IX86_BUILTIN_WRGSBASE32,
28726 IX86_BUILTIN_WRGSBASE64,
28728 /* RDRND instructions. */
28729 IX86_BUILTIN_RDRAND16_STEP,
28730 IX86_BUILTIN_RDRAND32_STEP,
28731 IX86_BUILTIN_RDRAND64_STEP,
28733 /* RDSEED instructions. */
28734 IX86_BUILTIN_RDSEED16_STEP,
28735 IX86_BUILTIN_RDSEED32_STEP,
28736 IX86_BUILTIN_RDSEED64_STEP,
28738 /* F16C instructions. */
28739 IX86_BUILTIN_CVTPH2PS,
28740 IX86_BUILTIN_CVTPH2PS256,
28741 IX86_BUILTIN_CVTPS2PH,
28742 IX86_BUILTIN_CVTPS2PH256,
28744 /* CFString built-in for darwin */
28745 IX86_BUILTIN_CFSTRING,
28747 /* Builtins to get CPU type and supported features. */
28748 IX86_BUILTIN_CPU_INIT,
28749 IX86_BUILTIN_CPU_IS,
28750 IX86_BUILTIN_CPU_SUPPORTS,
28752 /* Read/write FLAGS register built-ins. */
28753 IX86_BUILTIN_READ_FLAGS,
28754 IX86_BUILTIN_WRITE_FLAGS,
28756 IX86_BUILTIN_MAX
28757 };
28759 /* Table for the ix86 builtin decls. */
28762 /* Table of all of the builtin functions that are possible with different ISA's
28763 but are waiting to be built until a function is declared to use that
28764 ISA. */
28771 };
28776 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28777 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28778 function decl in the ix86_builtins array. Returns the function decl or
28779 NULL_TREE, if the builtin was not added.
28781 If the front end has a special hook for builtin functions, delay adding
28782 builtin functions that aren't in the current ISA until the ISA is changed
28783 with function specific optimization. Doing so, can save about 300K for the
28784 default compiler. When the builtin is expanded, check at that time whether
28785 it is valid.
28787 If the front end doesn't have a special hook, record all builtins, even if
28788 it isn't an instruction set in the current ISA in case the user uses
28789 function specific options for a different ISA, so that we don't get scope
28790 errors if a builtin is added in the middle of a function scope. */
28796 {
28800 {
28809 {
28815 }
28816 else
28817 {
28823 }
28824 }
28827 }
28829 /* Like def_builtin, but also marks the function decl "const". */
28834 {
28838 else
28842 }
28844 /* Add any new builtin functions for a given ISA that may not have been
28845 declared. This saves a bit of space compared to adding all of the
28846 declarations to the tree, even if we didn't use them. */
28848 static void
28850 {
28854 {
28857 {
28860 /* Don't define the builtin again. */
28866 NULL_TREE);
28871 }
28872 }
28873 }
28875 /* Bits for builtin_description.flag. */
28877 /* Set when we don't support the comparison natively, and should
28878 swap_comparison in order to support it. */
28879 #define BUILTIN_DESC_SWAP_OPERANDS 1
28881 struct builtin_description
28882 {
28889 };
28892 {
28893 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28894 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28895 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28896 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28897 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28898 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28899 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28900 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28901 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28902 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28903 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28904 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28906 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
28911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
28912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
28913 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
28914 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
28915 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
28916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
28917 };
28920 {
28921 /* SSE4.2 */
28922 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
28923 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
28924 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
28925 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
28926 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
28927 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
28928 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
28929 };
28932 {
28933 /* SSE4.2 */
28934 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
28935 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
28936 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
28937 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
28938 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
28939 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
28940 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
28941 };
28943 /* Special builtins with variable number of arguments. */
28945 {
28946 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
28947 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
28948 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
28950 /* 80387 (for use internally for atomic compound assignment). */
28951 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
28952 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
28953 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
28954 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
28956 /* MMX */
28957 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28959 /* 3DNow! */
28960 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28962 /* FXSR, XSAVE and XSAVEOPT */
28963 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
28964 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
28965 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28966 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28967 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28969 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28970 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28971 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28972 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28973 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28975 /* SSE */
28976 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28977 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28978 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
28980 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28982 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28985 /* SSE or 3DNow!A */
28986 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28987 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
28989 /* SSE2 */
28990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28993 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
28994 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28995 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
28996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
28997 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
28998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
28999 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29002 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29004 /* SSE3 */
29005 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29007 /* SSE4.1 */
29008 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
29010 /* SSE4A */
29011 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29012 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29014 /* AVX */
29015 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
29016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
29018 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29019 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29020 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29021 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29022 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29024 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29025 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29026 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29027 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29028 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29029 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29030 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29032 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29033 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29034 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29037 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29038 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29042 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29043 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29045 /* AVX2 */
29046 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29047 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29048 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29049 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29050 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29051 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29052 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29053 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29054 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29056 /* AVX512F */
29057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29105 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29106 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29107 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29108 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29109 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29110 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29112 /* FSGSBASE */
29113 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29114 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29115 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29116 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29117 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29118 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29119 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29120 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29122 /* RTM */
29123 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29124 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29125 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29126 };
29128 /* Builtins with variable number of arguments. */
29130 {
29131 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29132 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29133 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29134 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29135 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29136 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29137 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29139 /* MMX */
29140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29157 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29159 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29161 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29162 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29166 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29168 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29173 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29174 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29175 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29176 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29178 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29179 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29180 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29182 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29184 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29185 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29186 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29187 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29188 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29189 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29191 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29192 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29193 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29194 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29195 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29196 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29198 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29199 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29200 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29201 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29203 /* 3DNow! */
29204 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29205 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29206 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29207 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29209 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29210 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29211 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29212 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29213 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29214 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29215 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29216 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29217 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29218 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29219 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29220 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29221 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29222 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29223 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29225 /* 3DNow!A */
29226 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29227 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29228 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29229 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29230 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29231 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29233 /* SSE */
29234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29236 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29238 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29242 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29245 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29249 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29250 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29251 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29259 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29260 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29261 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29262 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29263 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29264 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29265 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29266 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29267 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29268 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29269 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29270 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29271 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29272 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29275 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29276 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29277 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29279 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29280 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29282 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29284 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29285 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29286 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29287 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29289 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29291 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29292 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29293 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29294 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29295 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29297 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29298 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29299 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29301 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29303 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29307 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29308 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29310 /* SSE MMX or 3Dnow!A */
29311 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29312 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29313 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29315 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29316 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29317 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29318 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29320 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29321 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29323 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29325 /* SSE2 */
29326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29332 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29344 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29345 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29349 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29351 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29352 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29353 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29354 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29361 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29362 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29366 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29370 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29371 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29372 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29373 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29374 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29375 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29376 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29377 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29378 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29382 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29386 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29388 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29389 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29391 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29394 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29395 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29397 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29399 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29400 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29401 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29402 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29403 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29404 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29405 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29406 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29417 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29418 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29420 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29422 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29423 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29428 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29435 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29436 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29437 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29438 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29440 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29441 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29443 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29444 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29445 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29457 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29462 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29467 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29468 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29469 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29470 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29471 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29472 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29475 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29476 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29477 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29478 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29479 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29480 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29482 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29483 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29484 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29485 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29489 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29491 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29493 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29495 /* SSE2 MMX */
29496 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29497 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29499 /* SSE3 */
29500 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29501 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29503 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29504 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29505 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29506 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29507 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29508 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29510 /* SSSE3 */
29511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29513 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29514 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29515 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29516 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29518 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29519 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29520 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29521 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29522 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29523 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29524 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29525 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29526 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29527 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29528 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29529 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29530 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29531 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29532 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29533 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29534 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29535 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29536 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29537 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29538 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29539 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29540 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29541 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29543 /* SSSE3. */
29544 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29545 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29547 /* SSE4.1 */
29548 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29550 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29553 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29556 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29557 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29559 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29560 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29561 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29562 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29563 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29564 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29565 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29566 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29567 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29568 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29569 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29570 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29571 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29573 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29574 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29575 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29576 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29577 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29578 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29579 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29580 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29581 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29582 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29583 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29584 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29586 /* SSE4.1 */
29587 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29588 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29589 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29590 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29592 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29593 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29594 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29595 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29597 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29598 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29600 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29601 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29603 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29604 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29605 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29606 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29608 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29609 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29611 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29612 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29614 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29615 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29616 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29618 /* SSE4.2 */
29619 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29620 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29621 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29622 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29623 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29625 /* SSE4A */
29626 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29627 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29628 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29629 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29631 /* AES */
29632 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29633 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29635 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29636 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29637 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29638 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29640 /* PCLMUL */
29641 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29643 /* AVX */
29644 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29645 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29646 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29648 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29649 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29652 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29658 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29659 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29660 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29661 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29662 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29663 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29664 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29665 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29666 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29667 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29668 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29669 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29673 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29692 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29693 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29695 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29696 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29697 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29698 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29699 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29706 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29707 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29709 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29712 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29715 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29717 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29719 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29731 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29732 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29746 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29756 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29757 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29758 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29760 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29763 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29765 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29768 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29779 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29780 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29782 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29784 /* AVX2 */
29785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29786 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29787 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29788 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29793 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29794 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29795 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29796 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29802 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29803 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29804 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29805 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29806 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29807 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29808 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29809 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29810 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29811 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29822 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29824 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29825 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29826 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29827 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29828 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29829 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29830 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29831 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29832 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29833 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29834 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29835 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29836 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29837 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29839 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29842 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29843 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29844 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29845 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29846 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29847 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29848 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29849 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29850 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29851 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29852 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29853 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29854 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29855 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29856 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29857 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29858 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29859 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29860 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29861 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29862 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29866 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29867 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29868 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29869 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29870 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29871 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29872 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29873 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29874 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29875 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29877 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29878 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29879 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
29905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
29907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
29908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29909 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29910 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29911 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29912 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29913 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29914 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29915 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29916 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29917 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
29918 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
29919 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
29920 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
29921 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29922 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29926 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29932 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29934 /* BMI */
29935 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29936 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29937 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29939 /* TBM */
29940 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29941 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29943 /* F16C */
29944 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
29945 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
29946 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
29947 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
29949 /* BMI2 */
29950 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29951 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29952 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29953 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29954 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29955 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29957 /* AVX512F */
29958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
29959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
29960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
29966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
29967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
29968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
29969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
29971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
29972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
29976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
29978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
29983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
29984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
29985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
29986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
29987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
29988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
29989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
29990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
30007 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
30008 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
30009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
30010 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30011 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30119 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30120 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30121 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30122 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30154 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30159 /* Mask arithmetic operations */
30160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30171 /* SHA */
30172 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30173 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30179 };
30181 /* Builtins with rounding support. */
30183 {
30184 /* AVX512F */
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30204 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30206 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30213 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30215 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30265 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30267 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30269 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30271 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30273 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30275 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30277 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30279 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30305 /* AVX512ER */
30306 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30307 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30308 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30309 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30310 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30311 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30312 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30313 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30314 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30315 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30316 };
30318 /* FMA4 and XOP. */
30319 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30320 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30321 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30322 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30323 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30324 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30325 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30326 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30327 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30328 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30329 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30330 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30331 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30332 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30333 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30334 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30335 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30336 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30337 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30338 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30339 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30340 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30341 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30342 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30343 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30344 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30345 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30346 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30347 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30348 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30349 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30350 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30351 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30352 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30353 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30354 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30355 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30356 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30357 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30358 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30359 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30360 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30361 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30362 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30363 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30364 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30365 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30366 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30367 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30368 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30369 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30370 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30373 {
30414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30572 };
30573 \f
30574 /* TM vector builtins. */
30576 /* Reuse the existing x86-specific `struct builtin_description' cause
30577 we're lazy. Add casts to make them fit. */
30579 {
30580 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30581 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30582 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30583 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30584 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30585 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30586 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30588 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30589 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30590 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30591 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30592 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30593 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30594 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30596 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30597 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30598 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30599 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30600 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30601 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30602 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30604 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30605 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30606 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30607 };
30609 /* TM callbacks. */
30611 /* Return the builtin decl needed to load a vector of TYPE. */
30613 static tree
30615 {
30617 {
30619 {
30626 }
30627 }
30629 }
30631 /* Return the builtin decl needed to store a vector of TYPE. */
30633 static tree
30635 {
30637 {
30639 {
30646 }
30647 }
30649 }
30650 \f
30651 /* Initialize the transactional memory vector load/store builtins. */
30653 static void
30655 {
30659 tree decl;
30666 /* If there are no builtins defined, we must be compiling in a
30667 language without trans-mem support. */
30671 /* Use whatever attributes a normal TM load has. */
30675 /* Use whatever attributes a normal TM store has. */
30679 /* Use whatever attributes a normal TM log has. */
30687 {
30691 {
30699 {
30702 }
30704 {
30707 }
30708 else
30709 {
30712 }
30714 /* The builtin without the prefix for
30715 calling it directly. */
30717 attrs);
30718 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30719 set the TYPE_ATTRIBUTES. */
30723 }
30724 }
30725 }
30727 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30728 in the current target ISA to allow the user to compile particular modules
30729 with different target specific options that differ from the command line
30730 options. */
30731 static void
30733 {
30738 /* Add all special builtins with variable number of operands. */
30742 {
30748 }
30750 /* Add all builtins with variable number of operands. */
30754 {
30760 }
30762 /* Add all builtins with rounding. */
30766 {
30772 }
30774 /* pcmpestr[im] insns. */
30778 {
30781 else
30784 }
30786 /* pcmpistr[im] insns. */
30790 {
30793 else
30796 }
30798 /* comi/ucomi insns. */
30800 {
30803 else
30806 }
30808 /* SSE */
30814 /* SSE or 3DNow!A */
30817 IX86_BUILTIN_MASKMOVQ);
30819 /* SSE2 */
30828 /* SSE3. */
30834 /* AES */
30848 /* PCLMUL */
30852 /* RDRND */
30859 IX86_BUILTIN_RDRAND64_STEP);
30861 /* AVX2 */
30863 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30864 IX86_BUILTIN_GATHERSIV2DF);
30867 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30868 IX86_BUILTIN_GATHERSIV4DF);
30871 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30872 IX86_BUILTIN_GATHERDIV2DF);
30875 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30876 IX86_BUILTIN_GATHERDIV4DF);
30879 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30880 IX86_BUILTIN_GATHERSIV4SF);
30883 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30884 IX86_BUILTIN_GATHERSIV8SF);
30887 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30888 IX86_BUILTIN_GATHERDIV4SF);
30891 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30892 IX86_BUILTIN_GATHERDIV8SF);
30895 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30896 IX86_BUILTIN_GATHERSIV2DI);
30899 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
30900 IX86_BUILTIN_GATHERSIV4DI);
30903 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
30904 IX86_BUILTIN_GATHERDIV2DI);
30907 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
30908 IX86_BUILTIN_GATHERDIV4DI);
30911 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
30912 IX86_BUILTIN_GATHERSIV4SI);
30915 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
30916 IX86_BUILTIN_GATHERSIV8SI);
30919 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
30920 IX86_BUILTIN_GATHERDIV4SI);
30923 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
30924 IX86_BUILTIN_GATHERDIV8SI);
30927 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
30928 IX86_BUILTIN_GATHERALTSIV4DF);
30931 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
30932 IX86_BUILTIN_GATHERALTDIV8SF);
30935 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
30936 IX86_BUILTIN_GATHERALTSIV4DI);
30939 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
30940 IX86_BUILTIN_GATHERALTDIV8SI);
30942 /* AVX512F */
30944 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
30945 IX86_BUILTIN_GATHER3SIV16SF);
30948 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
30949 IX86_BUILTIN_GATHER3SIV8DF);
30952 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
30953 IX86_BUILTIN_GATHER3DIV16SF);
30956 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
30957 IX86_BUILTIN_GATHER3DIV8DF);
30960 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
30961 IX86_BUILTIN_GATHER3SIV16SI);
30964 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
30965 IX86_BUILTIN_GATHER3SIV8DI);
30968 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
30969 IX86_BUILTIN_GATHER3DIV16SI);
30972 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
30973 IX86_BUILTIN_GATHER3DIV8DI);
30976 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
30977 IX86_BUILTIN_GATHER3ALTSIV8DF);
30980 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
30981 IX86_BUILTIN_GATHER3ALTDIV16SF);
30984 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
30985 IX86_BUILTIN_GATHER3ALTSIV8DI);
30988 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
30989 IX86_BUILTIN_GATHER3ALTDIV16SI);
30992 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
30993 IX86_BUILTIN_SCATTERSIV16SF);
30996 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
30997 IX86_BUILTIN_SCATTERSIV8DF);
31000 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
31001 IX86_BUILTIN_SCATTERDIV16SF);
31004 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
31005 IX86_BUILTIN_SCATTERDIV8DF);
31008 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
31009 IX86_BUILTIN_SCATTERSIV16SI);
31012 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
31013 IX86_BUILTIN_SCATTERSIV8DI);
31016 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
31017 IX86_BUILTIN_SCATTERDIV16SI);
31020 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
31021 IX86_BUILTIN_SCATTERDIV8DI);
31023 /* AVX512PF */
31025 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31026 IX86_BUILTIN_GATHERPFDPD);
31028 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31029 IX86_BUILTIN_GATHERPFDPS);
31031 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31032 IX86_BUILTIN_GATHERPFQPD);
31034 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31035 IX86_BUILTIN_GATHERPFQPS);
31037 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31038 IX86_BUILTIN_SCATTERPFDPD);
31040 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31041 IX86_BUILTIN_SCATTERPFDPS);
31043 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31044 IX86_BUILTIN_SCATTERPFQPD);
31046 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31047 IX86_BUILTIN_SCATTERPFQPS);
31049 /* SHA */
31065 /* RTM. */
31069 /* MMX access to the vec_init patterns. */
31074 V4HI_FTYPE_HI_HI_HI_HI,
31075 IX86_BUILTIN_VEC_INIT_V4HI);
31078 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31079 IX86_BUILTIN_VEC_INIT_V8QI);
31081 /* Access to the vec_extract patterns. */
31103 /* Access to the vec_set patterns. */
31124 /* RDSEED */
31133 /* ADCX */
31138 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31139 IX86_BUILTIN_ADDCARRYX64);
31141 /* Read/write FLAGS. */
31152 /* Add FMA4 multi-arg argument instructions */
31154 {
31160 }
31161 }
31163 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31164 to return a pointer to VERSION_DECL if the outcome of the expression
31165 formed by PREDICATE_CHAIN is true. This function will be called during
31166 version dispatch to decide which function version to execute. It returns
31167 the basic block at the end, to which more conditions can be added. */
31169 static basic_block
31172 {
31173 gimple return_stmt;
31175 gimple convert_stmt;
31176 gimple call_cond_stmt;
31177 gimple if_else_stmt;
31183 gimple_seq gseq;
31200 {
31208 }
31211 {
31226 else
31227 {
31228 gimple assign_stmt;
31229 /* Use MIN_EXPR to check if any integer is zero?.
31230 and_expr_var = min_expr <cond_var, and_expr_var> */
31238 }
31239 }
31242 integer_zero_node,
31272 }
31274 /* This parses the attribute arguments to target in DECL and determines
31275 the right builtin to use to match the platform specification.
31276 It returns the priority value for this version decl. If PREDICATE_LIST
31277 is not NULL, it stores the list of cpu features that need to be checked
31278 before dispatching this function. */
31280 static unsigned int
31282 {
31283 tree attrs;
31285 tree target_node;
31292 /* Priority of i386 features, greater value is higher priority. This is
31293 used to decide the order in which function dispatch must happen. For
31294 instance, a version specialized for SSE4.2 should be checked for dispatch
31295 before a version for SSE3, as SSE4.2 implies SSE3. */
31296 enum feature_priority
31297 {
31299 P_MMX,
31300 P_SSE,
31301 P_SSE2,
31302 P_SSE3,
31303 P_SSSE3,
31304 P_PROC_SSSE3,
31305 P_SSE4_A,
31306 P_PROC_SSE4_A,
31307 P_SSE4_1,
31308 P_SSE4_2,
31309 P_PROC_SSE4_2,
31310 P_POPCNT,
31311 P_AVX,
31312 P_PROC_AVX,
31313 P_FMA4,
31314 P_XOP,
31315 P_PROC_XOP,
31316 P_FMA,
31317 P_PROC_FMA,
31318 P_AVX2,
31319 P_PROC_AVX2
31320 };
31324 /* These are the target attribute strings for which a dispatcher is
31325 available, from fold_builtin_cpu. */
31327 static struct _feature_list
31328 {
31331 }
31333 {
31348 };
31351 static unsigned int NUM_FEATURES
31367 /* Return priority zero for default function. */
31371 /* Handle arch= if specified. For priority, set it to be 1 more than
31372 the best instruction set the processor can handle. For instance, if
31373 there is a version for atom and a version for ssse3 (the highest ISA
31374 priority for atom), the atom version must be checked for dispatch
31375 before the ssse3 version. */
31377 {
31387 {
31389 {
31397 else
31398 /* We translate "arch=corei7" and "arch=nehalem" to
31399 "corei7" so that it will be mapped to M_INTEL_COREI7
31400 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31407 else
31414 else
31454 }
31455 }
31460 {
31464 }
31467 {
31469 /* For a C string literal the length includes the trailing NULL. */
31472 predicate_chain);
31473 }
31474 }
31476 /* Process feature name. */
31483 {
31484 /* Do not process "arch=" */
31486 {
31489 }
31491 {
31493 {
31495 {
31500 predicate_chain);
31501 }
31502 /* Find the maximum priority feature. */
31507 }
31508 }
31510 {
31514 }
31516 }
31520 {
31523 attrs_str);
31525 }
31527 {
31530 }
31533 }
31535 /* This compares the priority of target features in function DECL1
31536 and DECL2. It returns positive value if DECL1 is higher priority,
31537 negative value if DECL2 is higher priority and 0 if they are the
31538 same. */
31540 static int
31542 {
31547 }
31549 /* V1 and V2 point to function versions with different priorities
31550 based on the target ISA. This function compares their priorities. */
31552 static int
31554 {
31556 {
31557 tree version_decl;
31558 tree predicate_chain;
31565 }
31567 /* This function generates the dispatch function for
31568 multi-versioned functions. DISPATCH_DECL is the function which will
31569 contain the dispatch logic. FNDECLS are the function choices for
31570 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31571 in DISPATCH_DECL in which the dispatch code is generated. */
31573 static int
31577 {
31578 tree default_decl;
31579 gimple ifunc_cpu_init_stmt;
31580 gimple_seq gseq;
31582 tree ele;
31588 struct _function_version_info
31589 {
31590 tree version_decl;
31591 tree predicate_chain;
31599 /*fndecls_p is actually a vector. */
31602 /* At least one more version other than the default. */
31609 /* The first version in the vector is the default decl. */
31615 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31616 constructors, so explicity call __builtin_cpu_init here. */
31627 {
31631 /* Get attribute string, parse it and find the right predicate decl.
31632 The predicate function could be a lengthy combination of many
31633 features, like arch-type and various isa-variants. */
31644 actual_versions++;
31645 }
31647 /* Sort the versions according to descending order of dispatch priority. The
31648 priority is based on the ISA. This is not a perfect solution. There
31649 could still be ambiguity. If more than one function version is suitable
31650 to execute, which one should be dispatched? In future, allow the user
31651 to specify a dispatch priority next to the version. */
31661 /* dispatch default version at the end. */
31667 }
31669 /* Comparator function to be used in qsort routine to sort attribute
31670 specification strings to "target". */
31672 static int
31674 {
31678 }
31680 /* ARGLIST is the argument to target attribute. This function tokenizes
31681 the comma separated arguments, sorts them and returns a string which
31682 is a unique identifier for the comma separated arguments. It also
31683 replaces non-identifier characters "=,-" with "_". */
31687 {
31688 tree arg;
31697 {
31702 argnum++;
31705 argnum++;
31706 }
31711 {
31717 }
31719 /* Replace "=,-" with "_". */
31732 {
31734 i++;
31736 }
31743 {
31748 }
31753 }
31755 /* This function changes the assembler name for functions that are
31756 versions. If DECL is a function version and has a "target"
31757 attribute, it appends the attribute string to its assembler name. */
31759 static tree
31761 {
31762 tree version_attr;
31770 "Function versions cannot be marked as gnu_inline,"
31779 /* target attribute string cannot be NULL. */
31783 version_string
31794 /* Allow assembler name to be modified if already set. */
31802 }
31804 /* This function returns true if FN1 and FN2 are versions of the same function,
31805 that is, the target strings of the function decls are different. This assumes
31806 that FN1 and FN2 have the same signature. */
31808 static bool
31810 {
31822 /* At least one function decl should have the target attribute specified. */
31826 /* Diagnose missing target attribute if one of the decls is already
31827 multi-versioned. */
31829 {
31831 {
31833 {
31838 }
31841 fn2);
31844 /* Prevent diagnosing of the same error multiple times. */
31849 }
31851 }
31856 /* The sorted target strings must be different for fn1 and fn2
31857 to be versions. */
31860 else
31867 }
31869 static tree
31871 {
31872 /* For function version, add the target suffix to the assembler name. */
31876 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31878 #endif
31881 }
31883 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31884 is true, append the full path name of the source file. */
31888 {
31896 /* Get a unique name that can be used globally without any chances
31897 of collision at link time. */
31907 /* Use '.' to concatenate names as it is demangler friendly. */
31910 suffix);
31911 else
31915 }
31917 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
31919 /* Make a dispatcher declaration for the multi-versioned function DECL.
31920 Calls to DECL function will be replaced with calls to the dispatcher
31921 by the front-end. Return the decl created. */
31923 static tree
31925 {
31926 tree func_decl;
31946 /* Mark this func as external, the resolver will flip it again if
31947 it gets generated. */
31949 /* This will be of type IFUNCs have to be externally visible. */
31953 }
31955 #endif
31957 /* Returns true if decl is multi-versioned and DECL is the default function,
31958 that is it is not tagged with target specific optimization. */
31960 static bool
31962 {
31971 }
31973 /* Make a dispatcher declaration for the multi-versioned function DECL.
31974 Calls to DECL function will be replaced with calls to the dispatcher
31975 by the front-end. Returns the decl of the dispatcher function. */
31977 static tree
31979 {
32001 /* Find the default version and make it the first node. */
32003 /* Go to the beginning of the chain. */
32008 {
32013 }
32015 /* If there is no default node, just return NULL. */
32019 /* Make default info the first node. */
32021 {
32028 }
32032 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32034 {
32039 /* Right now, the dispatching is done via ifunc. */
32045 dispatcher_version_info
32050 /* Set the dispatcher for all the versions. */
32053 {
32056 }
32057 }
32058 else
32059 #endif
32060 {
32062 "multiversioning needs ifunc which is not supported "
32064 }
32067 }
32069 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32070 it to CHAIN. */
32072 static tree
32074 {
32075 tree attr_name;
32076 tree attr_arg_name;
32077 tree attr_args;
32078 tree attr;
32085 }
32087 /* Make the resolver function decl to dispatch the versions of
32088 a multi-versioned function, DEFAULT_DECL. Create an
32089 empty basic block in the resolver and store the pointer in
32090 EMPTY_BB. Return the decl of the resolver function. */
32092 static tree
32096 {
32101 /* IFUNC's have to be globally visible. So, if the default_decl is
32102 not, then the name of the IFUNC should be made unique. */
32106 /* Append the filename to the resolver function if the versions are
32107 not externally visible. This is because the resolver function has
32108 to be externally visible for the loader to find it. So, appending
32109 the filename will prevent conflicts with a resolver function from
32110 another module which is based on the same version name. */
32113 /* The resolver function should return a (void *). */
32124 /* IFUNC resolvers have to be externally visible. */
32128 /* Resolver is not external, body is generated. */
32138 {
32139 /* In this case, each translation unit with a call to this
32140 versioned function will put out a resolver. Ensure it
32141 is comdat to keep just one copy. */
32144 }
32145 /* Build result decl and add to function_decl. */
32161 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32165 /* Create the alias for dispatch to resolver here. */
32166 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32170 }
32172 /* Generate the dispatching code body to dispatch multi-versioned function
32173 DECL. The target hook is called to process the "target" attributes and
32174 provide the code to dispatch the right function at run-time. NODE points
32175 to the dispatcher decl whose body will be created. */
32177 static tree
32179 {
32180 tree resolver_decl;
32181 basic_block empty_bb;
32182 tree default_ver_decl;
32198 /* The first version in the chain corresponds to the default version. */
32201 /* node is going to be an alias, so remove the finalized bit. */
32215 {
32217 /* Check for virtual functions here again, as by this time it should
32218 have been determined if this function needs a vtable index or
32219 not. This happens for methods in derived classes that override
32220 virtual methods in base classes but are not explicitly marked as
32221 virtual. */
32226 }
32232 }
32233 /* This builds the processor_model struct type defined in
32234 libgcc/config/i386/cpuinfo.c */
32236 static tree
32238 {
32245 /* The first 3 fields are unsigned int. */
32247 {
32253 }
32255 /* The last field is an array of unsigned integers of size one. */
32266 }
32268 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32270 static tree
32272 {
32273 tree new_decl;
32276 VAR_DECL,
32278 type);
32291 }
32293 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32294 into an integer defined in libgcc/config/i386/cpuinfo.c */
32296 static tree
32298 {
32304 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32305 enum processor_features
32306 {
32308 F_MMX,
32309 F_POPCNT,
32310 F_SSE,
32311 F_SSE2,
32312 F_SSE3,
32313 F_SSSE3,
32314 F_SSE4_1,
32315 F_SSE4_2,
32316 F_AVX,
32317 F_AVX2,
32318 F_SSE4_A,
32319 F_FMA4,
32320 F_XOP,
32321 F_FMA,
32322 F_MAX
32323 };
32325 /* These are the values for vendor types and cpu types and subtypes
32326 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32327 the corresponding start value. */
32328 enum processor_model
32329 {
32331 M_AMD,
32332 M_CPU_TYPE_START,
32333 M_INTEL_BONNELL,
32334 M_INTEL_CORE2,
32335 M_INTEL_COREI7,
32336 M_AMDFAM10H,
32337 M_AMDFAM15H,
32338 M_INTEL_SILVERMONT,
32339 M_AMD_BTVER1,
32340 M_AMD_BTVER2,
32341 M_CPU_SUBTYPE_START,
32342 M_INTEL_COREI7_NEHALEM,
32343 M_INTEL_COREI7_WESTMERE,
32344 M_INTEL_COREI7_SANDYBRIDGE,
32345 M_AMDFAM10H_BARCELONA,
32346 M_AMDFAM10H_SHANGHAI,
32347 M_AMDFAM10H_ISTANBUL,
32348 M_AMDFAM15H_BDVER1,
32349 M_AMDFAM15H_BDVER2,
32350 M_AMDFAM15H_BDVER3,
32351 M_AMDFAM15H_BDVER4,
32352 M_INTEL_COREI7_IVYBRIDGE,
32353 M_INTEL_COREI7_HASWELL
32354 };
32356 static struct _arch_names_table
32357 {
32360 }
32362 {
32387 };
32389 static struct _isa_names_table
32390 {
32393 }
32395 {
32411 };
32425 {
32426 /* *args must be a expr that can contain other EXPRS leading to a
32427 STRING_CST. */
32429 {
32432 }
32434 }
32439 {
32440 tree ref;
32441 tree field;
32442 tree final;
32445 unsigned int NUM_ARCH_NAMES
32454 {
32458 }
32463 /* CPU types are stored in the next field. */
32466 {
32469 }
32471 /* CPU subtypes are stored in the next field. */
32473 {
32476 }
32478 /* Get the appropriate field in __cpu_model. */
32482 /* Check the value. */
32486 }
32488 {
32489 tree ref;
32490 tree array_elt;
32491 tree field;
32492 tree final;
32495 unsigned int NUM_ISA_NAMES
32504 {
32508 }
32511 /* Get the last field, which is __cpu_features. */
32515 /* Get the appropriate field: __cpu_model.__cpu_features */
32519 /* Access the 0th element of __cpu_features array. */
32524 /* Return __cpu_model.__cpu_features[0] & field_val */
32528 }
32530 }
32532 static tree
32535 {
32537 {
32542 {
32545 }
32546 }
32548 #ifdef SUBTARGET_FOLD_BUILTIN
32550 #endif
32553 }
32555 /* Make builtins to detect cpu type and features supported. NAME is
32556 the builtin name, CODE is the builtin code, and FTYPE is the function
32557 type of the builtin. */
32559 static void
32562 {
32563 tree decl;
32564 tree type;
32572 }
32574 /* Make builtins to get CPU type and features supported. The created
32575 builtins are :
32577 __builtin_cpu_init (), to detect cpu type and features,
32578 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32579 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32580 */
32582 static void
32584 {
32591 }
32593 /* Internal method for ix86_init_builtins. */
32595 static void
32597 {
32609 sysv_va_ref =
32612 fnvoid_va_end_ms =
32614 fnvoid_va_start_ms =
32616 fnvoid_va_end_sysv =
32618 fnvoid_va_start_sysv =
32620 NULL_TREE);
32621 fnvoid_va_copy_ms =
32623 NULL_TREE);
32624 fnvoid_va_copy_sysv =
32640 }
32642 static void
32644 {
32647 /* The __float80 type. */
32650 {
32651 /* The __float80 type. */
32656 }
32659 /* The __float128 type. */
32665 /* This macro is built by i386-builtin-types.awk. */
32666 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32667 }
32669 static void
32671 {
32672 tree t;
32676 /* Builtins to get CPU type and features. */
32679 /* TFmode support builtins. */
32685 /* We will expand them to normal call if SSE isn't available since
32686 they are used by libgcc. */
32705 #ifdef SUBTARGET_INIT_BUILTINS
32706 SUBTARGET_INIT_BUILTINS;
32707 #endif
32708 }
32710 /* Return the ix86 builtin for CODE. */
32712 static tree
32714 {
32719 }
32721 /* Errors in the source file can cause expand_expr to return const0_rtx
32722 where we expect a vector. To avoid crashing, use one of the vector
32723 clear instructions. */
32724 static rtx
32726 {
32730 }
32732 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32734 static rtx
32736 {
32737 rtx pat;
32757 {
32761 }
32775 }
32777 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32779 static rtx
32783 {
32784 rtx pat;
32792 rtx op;
32799 {
32879 }
32889 {
32896 {
32898 {
32901 {
32919 xop_rotl:
32921 {
32924 gcc_checking_assert
32926 }
32927 else
32928 {
32929 gcc_checking_assert
32940 }
32944 }
32945 }
32946 }
32947 else
32948 {
32949 non_constant:
32953 /* If we aren't optimizing, only allow one memory operand to be
32954 generated. */
32956 num_memory++;
32964 }
32968 }
32971 {
32982 else
32983 {
32989 }
33002 }
33009 }
33011 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
33012 insns with vec_merge. */
33014 static rtx
33016 rtx target)
33017 {
33018 rtx pat;
33045 }
33047 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33049 static rtx
33052 {
33053 rtx pat;
33058 rtx op2;
33069 /* Swap operands if we have a comparison that isn't available in
33070 hardware. */
33072 {
33077 }
33097 }
33099 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33101 static rtx
33103 rtx target)
33104 {
33105 rtx pat;
33119 /* Swap operands if we have a comparison that isn't available in
33120 hardware. */
33122 {
33126 }
33147 const0_rtx)));
33150 }
33152 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33154 static rtx
33156 rtx target)
33157 {
33158 rtx pat;
33183 }
33185 static rtx
33188 {
33189 rtx pat;
33194 rtx op2;
33221 }
33223 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33225 static rtx
33227 rtx target)
33228 {
33229 rtx pat;
33262 const0_rtx)));
33265 }
33267 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33269 static rtx
33272 {
33273 rtx pat;
33311 {
33314 }
33317 {
33326 }
33328 {
33337 }
33338 else
33339 {
33346 }
33354 {
33359 emit_insn
33363 FLAGS_REG),
33364 const0_rtx)));
33366 }
33367 else
33369 }
33372 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33374 static rtx
33377 {
33378 rtx pat;
33406 {
33409 }
33412 {
33421 }
33423 {
33432 }
33433 else
33434 {
33441 }
33449 {
33454 emit_insn
33458 FLAGS_REG),
33459 const0_rtx)));
33461 }
33462 else
33464 }
33466 /* Subroutine of ix86_expand_builtin to take care of insns with
33467 variable number of operands. */
33469 static rtx
33472 {
33478 struct
33479 {
33480 rtx op;
33492 {
33940 }
33945 {
33948 }
33951 {
33958 }
33959 else
33960 {
33963 }
33966 {
33973 {
33974 /* SIMD shift insns take either an 8-bit immediate or
33975 register as count. But builtin functions take int as
33976 count. If count doesn't match, we put it in register. */
33978 {
33982 }
33983 }
33986 {
33989 {
34065 {
34069 {
34072 }
34078 }
34080 }
34081 }
34082 else
34083 {
34087 /* If we aren't optimizing, only allow one memory operand to
34088 be generated. */
34090 num_memory++;
34093 {
34096 }
34097 else
34098 {
34101 }
34102 }
34106 }
34109 {
34134 }
34141 }
34143 /* Transform pattern of following layout:
34144 (parallel [
34145 set (A B)
34146 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34147 ])
34148 into:
34149 (set (A B))
34151 Or:
34152 (parallel [ A B
34153 ...
34154 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34155 ...
34156 ])
34157 into:
34158 (parallel [ A B ... ]) */
34160 static rtx
34162 {
34169 {
34178 }
34179 else
34180 {
34186 {
34191 }
34193 /* No more than 1 occurence was removed. */
34197 }
34198 }
34200 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34201 with rounding. */
34202 static rtx
34205 {
34222 /* See avxintrin.h for values. */
34224 {
34228 };
34230 {
34235 };
34238 {
34241 }
34243 {
34246 }
34249 {
34252 }
34275 ? CODE_FOR_sse_ucomi_round
34282 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34284 {
34290 }
34291 else
34292 {
34295 }
34301 set_dst,
34302 const0_rtx)));
34305 }
34307 static rtx
34310 {
34311 rtx pat;
34313 struct
34314 {
34315 rtx op;
34325 {
34402 }
34412 {
34419 {
34421 {
34423 {
34439 }
34440 }
34441 }
34443 {
34445 {
34448 }
34450 /* If there is no rounding use normal version of the pattern. */
34453 }
34454 else
34455 {
34460 {
34463 }
34464 else
34465 {
34468 }
34469 }
34473 }
34476 {
34501 }
34511 }
34513 /* Subroutine of ix86_expand_builtin to take care of special insns
34514 with variable number of operands. */
34516 static rtx
34519 {
34520 tree arg;
34524 struct
34525 {
34526 rtx op;
34536 {
34575 {
34583 }
34602 /* Reserve memory operand for target. */
34605 {
34606 /* These builtins and instructions require the memory
34607 to be properly aligned. */
34626 }
34651 {
34652 /* These builtins and instructions require the memory
34653 to be properly aligned. */
34662 }
34663 /* FALLTHRU */
34681 /* Reserve memory operand for target. */
34694 {
34695 /* These builtins and instructions require the memory
34696 to be properly aligned. */
34705 }
34718 }
34723 {
34728 {
34731 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34732 on it. Try to improve it using get_pointer_alignment,
34733 and if the special builtin is one that requires strict
34734 mode alignment, also from it's GET_MODE_ALIGNMENT.
34735 Failure to do so could lead to ix86_legitimate_combined_insn
34736 rejecting all changes to such insns. */
34742 }
34743 else
34746 }
34747 else
34748 {
34755 }
34758 {
34767 {
34769 {
34775 else
34778 }
34779 }
34780 else
34781 {
34783 {
34784 /* This must be the memory operand. */
34787 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34788 on it. Try to improve it using get_pointer_alignment,
34789 and if the special builtin is one that requires strict
34790 mode alignment, also from it's GET_MODE_ALIGNMENT.
34791 Failure to do so could lead to ix86_legitimate_combined_insn
34792 rejecting all changes to such insns. */
34798 }
34799 else
34800 {
34801 /* This must be register. */
34807 else
34808 {
34811 }
34812 }
34813 }
34817 }
34820 {
34835 }
34841 }
34843 /* Return the integer constant in ARG. Constrain it to be in the range
34844 of the subparts of VEC_TYPE; issue an error if not. */
34846 static int
34848 {
34853 {
34856 }
34859 }
34861 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34862 ix86_expand_vector_init. We DO have language-level syntax for this, in
34863 the form of (type){ init-list }. Except that since we can't place emms
34864 instructions from inside the compiler, we can't allow the use of MMX
34865 registers unless the user explicitly asks for it. So we do *not* define
34866 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34867 we have builtins invoked by mmintrin.h that gives us license to emit
34868 these sorts of instructions. */
34870 static rtx
34872 {
34882 {
34885 }
34892 }
34894 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34895 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
34896 had a language-level syntax for referencing vector elements. */
34898 static rtx
34900 {
34904 rtx op0;
34924 }
34926 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34927 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
34928 a language-level syntax for referencing vector elements. */
34930 static rtx
34932 {
34956 /* OP0 is the source of these builtin functions and shouldn't be
34957 modified. Create a copy, use it and return it as target. */
34963 }
34965 /* Expand an expression EXP that calls a built-in function,
34966 with result going to TARGET if that's convenient
34967 (and in mode MODE if that's convenient).
34968 SUBTARGET may be used as the target for computing one of EXP's operands.
34969 IGNORE is nonzero if the value is to be ignored. */
34971 static rtx
34974 {
34984 /* For CPU builtins that can be folded, fold first and expand the fold. */
34986 {
34988 {
34989 /* Make it call __cpu_indicator_init in libgcc. */
34995 }
34998 {
35003 }
35004 }
35006 /* Determine whether the builtin function is available under the current ISA.
35007 Originally the builtin was not created if it wasn't applicable to the
35008 current ISA based on the command line switches. With function specific
35009 options, we need to check in the context of the function making the call
35010 whether it is supported. */
35013 {
35019 else
35020 {
35024 }
35026 }
35029 {
35033 ? CODE_FOR_mmx_maskmovq
35035 /* Note the arg order is different from the operand order. */
35136 {
35137 REAL_VALUE_TYPE inf;
35138 rtx tmp;
35150 }
35160 {
35166 insn = (TARGET_64BIT
35170 }
35172 {
35173 insn = (TARGET_64BIT
35177 }
35178 else
35179 {
35182 insn = (TARGET_64BIT
35190 {
35193 }
35195 }
35198 {
35199 /* mode is VOIDmode if __builtin_rd* has been called
35200 without lhs. */
35204 }
35207 {
35212 }
35226 {
35251 }
35257 {
35260 }
35280 {
35283 }
35289 {
35293 {
35314 }
35319 }
35320 else
35321 {
35323 {
35335 }
35337 }
35367 ? CODE_FOR_tbm_bextri_si
35370 {
35373 }
35374 else
35375 {
35384 }
35400 rdrand_step:
35407 {
35410 }
35416 /* Emit SImode conditional move. */
35418 {
35421 }
35424 else
35431 const0_rtx);
35450 rdseed_step:
35457 {
35460 }
35466 const0_rtx);
35484 addcarryx:
35492 /* Generate CF from input operand. */
35497 /* Gen ADCX instruction to compute X+Y+CF. */
35512 /* Store the result. */
35515 {
35518 }
35521 /* Return current CF value. */
35563 kortest:
35577 /* Emit kortest. */
35579 /* And use setcc to return result from flags. */
35730 gather_gen:
35731 rtx half;
35744 /* Note the arg order is different from the operand order. */
35755 else
35759 {
35781 else
35788 {
35793 }
35800 else
35807 {
35812 }
35816 }
35818 /* Force memory operand only with base register here. But we
35819 don't want to do it on memory operand for other builtin
35820 functions. */
35830 {
35833 }
35834 else
35835 {
35838 }
35840 {
35843 }
35845 /* Optimize. If mask is known to have all high bits set,
35846 replace op0 with pc_rtx to signal that the instruction
35847 overwrites the whole destination and doesn't use its
35848 previous contents. */
35850 {
35852 {
35855 }
35857 {
35860 {
35864 negative++;
35867 negative++;
35868 }
35871 }
35874 {
35875 /* Recognize also when mask is like:
35876 __v2df src = _mm_setzero_pd ();
35877 __v2df mask = _mm_cmpeq_pd (src, src);
35878 or
35879 __v8sf src = _mm256_setzero_ps ();
35880 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
35881 as that is a cheaper way to load all ones into
35882 a register than having to load a constant from
35883 memory. */
35886 {
35891 {
35898 /* FALLTHRU */
35908 }
35909 }
35910 }
35911 }
35919 {
35943 }
35946 scatter_gen:
35962 /* Force memory operand only with base register here. But we
35963 don't want to do it on memory operand for other builtin
35964 functions. */
35971 {
35974 }
35975 else
35976 {
35979 }
35988 {
35991 }
36000 vec_prefetch_gen:
36018 {
36021 }
36023 {
36026 }
36031 /* Force memory operand only with base register here. But we
36032 don't want to do it on memory operand for other builtin
36033 functions. */
36040 {
36043 }
36046 {
36049 }
36065 {
36068 }
36074 }
36087 {
36091 /* Emit a normal call if SSE isn't available. */
36095 }
36124 }
36126 /* This returns the target-specific builtin with code CODE if
36127 current_function_decl has visibility on this builtin, which is checked
36128 using isa flags. Returns NULL_TREE otherwise. */
36131 {
36135 /* Determine the isa flags of current_function_decl. */
36147 else
36149 }
36151 /* Returns a function decl for a vectorized version of the builtin function
36152 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36153 if it is not available. */
36155 static tree
36157 tree type_in)
36158 {
36174 {
36177 {
36184 }
36189 {
36192 }
36197 {
36204 }
36210 /* The round insn does not trap on denormals. */
36215 {
36222 }
36228 /* The round insn does not trap on denormals. */
36233 {
36238 }
36244 /* The round insn does not trap on denormals. */
36249 {
36256 }
36262 /* The round insn does not trap on denormals. */
36267 {
36272 }
36279 {
36284 }
36291 {
36296 }
36302 /* The round insn does not trap on denormals. */
36307 {
36314 }
36320 /* The round insn does not trap on denormals. */
36325 {
36330 }
36335 {
36342 }
36347 {
36354 }
36358 /* The round insn does not trap on denormals. */
36363 {
36368 }
36372 /* The round insn does not trap on denormals. */
36377 {
36382 }
36386 /* The round insn does not trap on denormals. */
36391 {
36396 }
36400 /* The round insn does not trap on denormals. */
36405 {
36410 }
36414 /* The round insn does not trap on denormals. */
36419 {
36424 }
36428 /* The round insn does not trap on denormals. */
36433 {
36438 }
36442 /* The round insn does not trap on denormals. */
36447 {
36452 }
36456 /* The round insn does not trap on denormals. */
36461 {
36466 }
36470 /* The round insn does not trap on denormals. */
36475 {
36480 }
36484 /* The round insn does not trap on denormals. */
36489 {
36494 }
36499 {
36504 }
36509 {
36514 }
36519 }
36521 /* Dispatch to a handler for a vectorization library. */
36524 type_in);
36527 }
36529 /* Handler for an SVML-style interface to
36530 a library with vectorized intrinsics. */
36532 static tree
36534 {
36542 /* The SVML is suitable for unsafe math only. */
36555 {
36602 }
36611 {
36614 }
36615 else
36618 /* Convert to uppercase. */
36623 args;
36625 arity++;
36629 else
36632 /* Build a function declaration for the vectorized function. */
36641 }
36643 /* Handler for an ACML-style interface to
36644 a library with vectorized intrinsics. */
36646 static tree
36648 {
36656 /* The ACML is 64bits only and suitable for unsafe math only as
36657 it does not correctly support parts of IEEE with the required
36658 precision such as denormals. */
36672 {
36702 }
36709 args;
36711 arity++;
36715 else
36718 /* Build a function declaration for the vectorized function. */
36727 }
36729 /* Returns a decl of a function that implements gather load with
36730 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36731 Return NULL_TREE if it is not available. */
36733 static tree
36736 {
36752 /* v*gather* insn sign extends index to pointer mode. */
36764 {
36792 else
36798 else
36804 else
36810 else
36815 }
36818 }
36820 /* Returns a code for a target-specific builtin that implements
36821 reciprocal of the function, or NULL_TREE if not available. */
36823 static tree
36826 {
36833 /* Machine dependent builtins. */
36835 {
36836 /* Vectorized version of sqrt to rsqrt conversion. */
36845 }
36846 else
36847 /* Normal builtins. */
36849 {
36850 /* Sqrt to rsqrt conversion. */
36856 }
36857 }
36858 \f
36859 /* Helper for avx_vpermilps256_operand et al. This is also used by
36860 the expansion functions to turn the parallel back into a mask.
36861 The return value is 0 for no match and the imm8+1 for a match. */
36863 int
36865 {
36873 /* Validate that all of the elements are constants, and not totally
36874 out of range. Copy the data into an integral array to make the
36875 subsequent checks easier. */
36877 {
36887 }
36890 {
36892 /* In the 512-bit DFmode case, we can only move elements within
36893 a 128-bit lane. First fill the second part of the mask,
36894 then fallthru. */
36896 {
36900 }
36902 {
36906 }
36907 /* FALLTHRU */
36910 /* In the 256-bit DFmode case, we can only move elements within
36911 a 128-bit lane. */
36913 {
36917 }
36919 {
36923 }
36927 /* In 512 bit SFmode case, permutation in the upper 256 bits
36928 must mirror the permutation in the lower 256-bits. */
36932 /* FALLTHRU */
36935 /* In 256 bit SFmode case, we have full freedom of
36936 movement within the low 128-bit lane, but the high 128-bit
36937 lane must mirror the exact same pattern. */
36942 /* FALLTHRU */
36946 /* In the 128-bit case, we've full freedom in the placement of
36947 the elements from the source operand. */
36954 }
36956 /* Make sure success has a non-zero value by adding one. */
36958 }
36960 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
36961 the expansion functions to turn the parallel back into a mask.
36962 The return value is 0 for no match and the imm8+1 for a match. */
36964 int
36966 {
36974 /* Validate that all of the elements are constants, and not totally
36975 out of range. Copy the data into an integral array to make the
36976 subsequent checks easier. */
36978 {
36988 }
36990 /* Validate that the halves of the permute are halves. */
36998 /* Reconstruct the mask. */
37000 {
37006 }
37008 /* Make sure success has a non-zero value by adding one. */
37010 }
37011 \f
37012 /* Store OPERAND to the memory after reload is completed. This means
37013 that we can't easily use assign_stack_local. */
37014 rtx
37016 {
37017 rtx result;
37021 {
37024 stack_pointer_rtx,
37027 }
37029 {
37031 {
37035 /* FALLTHRU */
37041 stack_pointer_rtx)),
37042 operand));
37046 }
37048 }
37049 else
37050 {
37052 {
37054 {
37061 stack_pointer_rtx)),
37067 stack_pointer_rtx)),
37069 }
37072 /* Store HImodes as SImodes. */
37074 /* FALLTHRU */
37080 stack_pointer_rtx)),
37081 operand));
37085 }
37087 }
37089 }
37091 /* Free operand from the memory. */
37092 void
37094 {
37096 {
37101 else
37103 /* Use LEA to deallocate stack space. In peephole2 it will be converted
37104 to pop or add instruction if registers are available. */
37108 }
37109 }
37111 /* Return a register priority for hard reg REGNO. */
37112 static int
37114 {
37115 /* ebp and r13 as the base always wants a displacement, r12 as the
37116 base always wants an index. So discourage their usage in an
37117 address. */
37122 /* New x86-64 int registers result in bigger code size. Discourage
37123 them. */
37126 /* New x86-64 SSE registers result in bigger code size. Discourage
37127 them. */
37130 /* Usage of AX register results in smaller code. Prefer it. */
37134 }
37136 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37138 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37139 QImode must go into class Q_REGS.
37140 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37141 movdf to do mem-to-mem moves through integer regs. */
37143 static reg_class_t
37145 {
37148 /* We're only allowed to return a subclass of CLASS. Many of the
37149 following checks fail for NO_REGS, so eliminate that early. */
37153 /* All classes can load zeros. */
37157 /* Force constants into memory if we are loading a (nonzero) constant into
37158 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37159 instructions to load from a constant. */
37166 /* Prefer SSE regs only, if we can use them for math. */
37170 /* Floating-point constants need more complex checks. */
37172 {
37173 /* General regs can load everything. */
37177 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37178 zero above. We only want to wind up preferring 80387 registers if
37179 we plan on doing computation with them. */
37182 {
37183 /* Limit class to non-sse. */
37192 }
37195 }
37197 /* Generally when we see PLUS here, it's the function invariant
37198 (plus soft-fp const_int). Which can only be computed into general
37199 regs. */
37203 /* QImode constants are easy to load, but non-constant QImode data
37204 must go into Q_REGS. */
37206 {
37212 }
37215 }
37217 /* Discourage putting floating-point values in SSE registers unless
37218 SSE math is being used, and likewise for the 387 registers. */
37219 static reg_class_t
37221 {
37224 /* Restrict the output reload class to the register bank that we are doing
37225 math on. If we would like not to return a subset of CLASS, reject this
37226 alternative: if reload cannot do this, it will still use its choice. */
37232 {
37237 else
37239 }
37242 }
37244 static reg_class_t
37247 {
37248 /* Double-word spills from general registers to non-offsettable memory
37249 references (zero-extended addresses) require special handling. */
37255 {
37257 ? CODE_FOR_reload_noff_load
37259 /* Add the cost of moving address to a temporary. */
37263 }
37265 /* QImode spills from non-QI registers require
37266 intermediate register on 32bit targets. */
37272 {
37277 else
37283 /* Return Q_REGS if the operand is in memory. */
37286 }
37288 /* This condition handles corner case where an expression involving
37289 pointers gets vectorized. We're trying to use the address of a
37290 stack slot as a vector initializer.
37292 (set (reg:V2DI 74 [ vect_cst_.2 ])
37293 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37295 Eventually frame gets turned into sp+offset like this:
37297 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37298 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37299 (const_int 392 [0x188]))))
37301 That later gets turned into:
37303 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37304 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37305 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37307 We'll have the following reload recorded:
37309 Reload 0: reload_in (DI) =
37310 (plus:DI (reg/f:DI 7 sp)
37311 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37312 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37313 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37314 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37315 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37316 reload_reg_rtx: (reg:V2DI 22 xmm1)
37318 Which isn't going to work since SSE instructions can't handle scalar
37319 additions. Returning GENERAL_REGS forces the addition into integer
37320 register and reload can handle subsequent reloads without problems. */
37328 }
37330 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37332 static bool
37334 {
37336 {
37351 }
37354 }
37356 /* If we are copying between general and FP registers, we need a memory
37357 location. The same is true for SSE and MMX registers.
37359 To optimize register_move_cost performance, allow inline variant.
37361 The macro can't work reliably when one of the CLASSES is class containing
37362 registers from multiple units (SSE, MMX, integer). We avoid this by never
37363 combining those units in single alternative in the machine description.
37364 Ensure that this constraint holds to avoid unexpected surprises.
37366 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37367 enforce these sanity checks. */
37372 {
37381 {
37384 }
37389 /* ??? This is a lie. We do have moves between mmx/general, and for
37390 mmx/sse2. But by saying we need secondary memory we discourage the
37391 register allocator from using the mmx registers unless needed. */
37396 {
37397 /* SSE1 doesn't have any direct moves from other classes. */
37401 /* If the target says that inter-unit moves are more expensive
37402 than moving through memory, then don't generate them. */
37407 /* Between SSE and general, we have moves no larger than word size. */
37410 }
37413 }
37415 bool
37418 {
37420 }
37422 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37424 On the 80386, this is the size of MODE in words,
37425 except in the FP regs, where a single reg is always enough. */
37427 static unsigned char
37429 {
37431 {
37436 else
37438 }
37439 else
37440 {
37443 else
37445 }
37446 }
37448 /* Return true if the registers in CLASS cannot represent the change from
37449 modes FROM to TO. */
37451 bool
37454 {
37458 /* x87 registers can't do subreg at all, as all values are reformatted
37459 to extended precision. */
37464 {
37465 /* Vector registers do not support QI or HImode loads. If we don't
37466 disallow a change to these modes, reload will assume it's ok to
37467 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37468 the vec_dupv4hi pattern. */
37472 /* Vector registers do not support subreg with nonzero offsets, which
37473 are otherwise valid for integer registers. Since we can't see
37474 whether we have a nonzero offset from here, prohibit all
37475 nonparadoxical subregs changing size. */
37478 }
37481 }
37483 /* Return the cost of moving data of mode M between a
37484 register and memory. A value of 2 is the default; this cost is
37485 relative to those in `REGISTER_MOVE_COST'.
37487 This function is used extensively by register_move_cost that is used to
37488 build tables at startup. Make it inline in this case.
37489 When IN is 2, return maximum of in and out move cost.
37491 If moving between registers and memory is more expensive than
37492 between two registers, you should define this macro to express the
37493 relative cost.
37495 Model also increased moving costs of QImode registers in non
37496 Q_REGS classes.
37497 */
37501 {
37504 {
37507 {
37519 }
37523 }
37525 {
37528 {
37540 }
37544 }
37546 {
37549 {
37558 }
37562 }
37564 {
37567 {
37573 else
37578 }
37579 else
37580 {
37585 else
37587 }
37594 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37601 else
37605 }
37606 }
37608 static int
37611 {
37613 }
37616 /* Return the cost of moving data from a register in class CLASS1 to
37617 one in class CLASS2.
37619 It is not required that the cost always equal 2 when FROM is the same as TO;
37620 on some machines it is expensive to move between registers if they are not
37621 general registers. */
37623 static int
37625 reg_class_t class2_i)
37626 {
37630 /* In case we require secondary memory, compute cost of the store followed
37631 by load. In order to avoid bad register allocation choices, we need
37632 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37635 {
37641 /* In case of copying from general_purpose_register we may emit multiple
37642 stores followed by single load causing memory size mismatch stall.
37643 Count this as arbitrarily high cost of 20. */
37648 /* In the case of FP/MMX moves, the registers actually overlap, and we
37649 have to switch modes in order to treat them differently. */
37655 }
37657 /* Moves between SSE/MMX and integer unit are expensive. */
37661 /* ??? By keeping returned value relatively high, we limit the number
37662 of moves between integer and MMX/SSE registers for all targets.
37663 Additionally, high value prevents problem with x86_modes_tieable_p(),
37664 where integer modes in MMX/SSE registers are not tieable
37665 because of missing QImode and HImode moves to, from or between
37666 MMX/SSE registers. */
37676 }
37678 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37679 MODE. */
37681 bool
37683 {
37684 /* Flags and only flags can only hold CCmode values. */
37696 {
37697 /* We implement the move patterns for all vector modes into and
37698 out of SSE registers, even when no operation instructions
37699 are available. */
37701 /* For AVX-512 we allow, regardless of regno:
37702 - XI mode
37703 - any of 512-bit wide vector mode
37704 - any scalar mode. */
37711 /* xmm16-xmm31 are only available for AVX-512. */
37715 /* OImode and AVX modes are available only when AVX is enabled. */
37722 }
37724 {
37725 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37726 so if the register is available at all, then we can move data of
37727 the given mode into or out of it. */
37730 }
37733 {
37734 /* Take care for QImode values - they can be in non-QI regs,
37735 but then they do cause partial register stalls. */
37740 /* LRA checks if the hard register is OK for the given mode.
37741 QImode values can live in non-QI regs, so we allow all
37742 registers here. */
37746 }
37747 /* We handle both integer and floats in the general purpose registers. */
37754 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37755 on to use that value in smaller contexts, this can easily force a
37756 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37757 supporting DImode, allow it. */
37762 }
37764 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37765 tieable integer mode. */
37767 static bool
37769 {
37771 {
37784 }
37785 }
37787 /* Return true if MODE1 is accessible in a register that can hold MODE2
37788 without copying. That is, all register classes that can hold MODE2
37789 can also hold MODE1. */
37791 bool
37793 {
37801 /* MODE2 being XFmode implies fp stack or general regs, which means we
37802 can tie any smaller floating point modes to it. Note that we do not
37803 tie this with TFmode. */
37807 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37808 that we can tie it with SFmode. */
37812 /* If MODE2 is only appropriate for an SSE register, then tie with
37813 any other mode acceptable to SSE registers. */
37823 /* If MODE2 is appropriate for an MMX register, then tie
37824 with any other mode acceptable to MMX registers. */
37831 }
37833 /* Return the cost of moving between two registers of mode MODE. */
37835 static int
37837 {
37841 {
37873 }
37875 /* Return the cost of moving between two registers of mode MODE,
37876 assuming that the move will be in pieces of at most UNITS bytes. */
37878 }
37880 /* Compute a (partial) cost for rtx X. Return true if the complete
37881 cost has been computed, and false if subexpressions should be
37882 scanned. In either case, *TOTAL contains the cost result. */
37884 static bool
37887 {
37888 rtx mask;
37895 {
37899 {
37902 }
37914 && (!TARGET_64BIT
37919 else
37925 {
37928 }
37930 {
37940 }
37942 {
37945 {
37954 }
37955 }
37956 /* Fall back to (MEM (SYMBOL_REF)), since that's where
37957 it'll probably end up. Add a penalty for size. */
37964 /* The zero extensions is often completely free on x86_64, so make
37965 it as cheap as possible. */
37971 else
37983 {
37986 {
37989 }
37992 {
37995 }
37996 }
37997 /* FALLTHRU */
38004 {
38005 /* ??? Should be SSE vector operation cost. */
38006 /* At least for published AMD latencies, this really is the same
38007 as the latency for a simple fpu operation like fabs. */
38008 /* V*QImode is emulated with 1-11 insns. */
38010 {
38013 {
38014 /* For XOP we use vpshab, which requires a broadcast of the
38015 value to the variable shift insn. For constants this
38016 means a V16Q const in mem; even when we can perform the
38017 shift with one insn set the cost to prefer paddb. */
38019 {
38024 }
38026 }
38030 }
38031 else
38033 }
38035 {
38037 {
38040 else
38042 }
38043 else
38044 {
38047 else
38049 }
38050 }
38051 else
38052 {
38057 {
38058 /* Return the cost after shift-and truncation. */
38061 }
38062 else
38064 }
38068 {
38069 rtx sub;
38074 /* ??? SSE scalar/vector cost should be used here. */
38075 /* ??? Bald assumption that fma has the same cost as fmul. */
38079 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38090 }
38094 {
38095 /* ??? SSE scalar cost should be used here. */
38098 }
38100 {
38103 }
38105 {
38106 /* ??? SSE vector cost should be used here. */
38109 }
38111 {
38112 /* V*QImode is emulated with 7-13 insns. */
38114 {
38121 }
38122 /* V*DImode is emulated with 5-8 insns. */
38124 {
38127 else
38129 }
38130 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38131 insns, including two PMULUDQ. */
38134 else
38137 }
38138 else
38139 {
38144 {
38147 nbits++;
38148 }
38149 else
38150 /* This is arbitrary. */
38153 /* Compute costs correctly for widening multiplication. */
38157 {
38164 {
38168 else
38170 }
38174 }
38182 }
38189 /* ??? SSE cost should be used here. */
38194 /* ??? SSE vector cost should be used here. */
38196 else
38203 {
38208 {
38211 {
38219 }
38220 }
38223 {
38226 {
38232 }
38233 }
38235 {
38243 }
38244 }
38245 /* FALLTHRU */
38249 {
38250 /* ??? SSE cost should be used here. */
38253 }
38255 {
38258 }
38260 {
38261 /* ??? SSE vector cost should be used here. */
38264 }
38265 /* FALLTHRU */
38272 {
38279 }
38280 /* FALLTHRU */
38284 {
38285 /* ??? SSE cost should be used here. */
38288 }
38290 {
38293 }
38295 {
38296 /* ??? SSE vector cost should be used here. */
38299 }
38300 /* FALLTHRU */
38304 {
38305 /* ??? Should be SSE vector operation cost. */
38306 /* At least for published AMD latencies, this really is the same
38307 as the latency for a simple fpu operation like fabs. */
38309 }
38312 else
38321 {
38322 /* This kind of construct is implemented using test[bwl].
38323 Treat it as if we had an AND. */
38328 }
38338 /* ??? SSE cost should be used here. */
38343 /* ??? SSE vector cost should be used here. */
38349 /* ??? SSE cost should be used here. */
38354 /* ??? SSE vector cost should be used here. */
38366 /* ??? Assume all of these vector manipulation patterns are
38367 recognizable. In which case they all pretty much have the
38368 same cost. */
38373 /* This is masked instruction, assume the same cost,
38374 as nonmasked variant. */
38377 else
38383 }
38384 }
38386 #if TARGET_MACHO
38390 /* Given a symbol name and its associated stub, write out the
38391 definition of the stub. */
38393 void
38395 {
38400 /* For 64-bit we shouldn't get here. */
38403 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38420 else
38427 {
38429 }
38431 {
38432 /* PIC stub. */
38433 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38439 }
38440 else
38443 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38444 it needs no stub-binding-helper. */
38451 {
38454 }
38455 else
38460 /* N.B. Keep the correspondence of these
38461 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38462 old-pic/new-pic/non-pic stubs; altering this will break
38463 compatibility with existing dylibs. */
38465 {
38466 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38468 }
38469 else
38470 /* 16-byte -mdynamic-no-pic stub. */
38476 }
38479 /* Order the registers for register allocator. */
38481 void
38483 {
38487 /* First allocate the local general purpose registers. */
38492 /* Global general purpose registers. */
38497 /* x87 registers come first in case we are doing FP math
38498 using them. */
38503 /* SSE registers. */
38509 /* Extended REX SSE registers. */
38513 /* Mask register. */
38517 /* x87 registers. */
38525 /* Initialize the rest of array as we do not allocate some registers
38526 at all. */
38529 }
38531 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38532 in struct attribute_spec handler. */
38533 static tree
38535 tree args,
38538 {
38543 {
38545 name);
38548 }
38550 {
38552 name);
38555 }
38557 {
38558 tree cst;
38562 {
38565 name);
38567 }
38570 {
38573 name);
38575 }
38578 }
38581 }
38583 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38584 struct attribute_spec.handler. */
38585 static tree
38587 tree args ATTRIBUTE_UNUSED,
38589 {
38594 {
38596 name);
38599 }
38601 /* Can combine regparm with all attributes but fastcall. */
38603 {
38605 {
38607 }
38610 }
38612 {
38614 {
38616 }
38619 }
38622 }
38624 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38625 struct attribute_spec.handler. */
38626 static tree
38628 tree args ATTRIBUTE_UNUSED,
38630 {
38633 {
38636 }
38637 else
38641 {
38643 name);
38645 }
38651 {
38653 name);
38655 }
38658 }
38660 static tree
38662 tree args ATTRIBUTE_UNUSED,
38664 {
38666 {
38668 name);
38670 }
38672 }
38674 static bool
38676 {
38680 }
38682 /* Returns an expression indicating where the this parameter is
38683 located on entry to the FUNCTION. */
38685 static rtx
38687 {
38693 {
38698 else
38701 }
38706 {
38713 {
38718 }
38719 else
38720 {
38723 {
38729 }
38730 }
38732 }
38736 }
38738 /* Determine whether x86_output_mi_thunk can succeed. */
38740 static bool
38742 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
38744 {
38745 /* 64-bit can handle anything. */
38749 /* For 32-bit, everything's fine if we have one free register. */
38753 /* Need a free register for vcall_offset. */
38757 /* Need a free register for GOT references. */
38761 /* Otherwise ok. */
38763 }
38765 /* Output the assembler code for a thunk function. THUNK_DECL is the
38766 declaration for the thunk function itself, FUNCTION is the decl for
38767 the target function. DELTA is an immediate constant offset to be
38768 added to THIS. If VCALL_OFFSET is nonzero, the word at
38769 *(*this + vcall_offset) should be added to THIS. */
38771 static void
38775 {
38782 else
38783 {
38789 else
38791 }
38795 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38796 pull it in now and let DELTA benefit. */
38800 {
38801 /* Put the this parameter into %eax. */
38804 }
38805 else
38808 /* Adjust the this parameter by a fixed constant. */
38810 {
38815 {
38817 {
38821 }
38822 }
38825 }
38827 /* Adjust the this parameter by a value stored in the vtable. */
38829 {
38839 /* Adjust the this parameter. */
38843 {
38847 }
38854 vcall_mem));
38855 else
38857 }
38859 /* If necessary, drop THIS back to its stack slot. */
38865 {
38868 ;
38869 else
38870 {
38874 }
38875 }
38876 else
38877 {
38879 ;
38880 #if TARGET_MACHO
38882 {
38885 }
38887 else
38888 {
38895 }
38896 }
38898 /* Our sibling call patterns do not allow memories, because we have no
38899 predicate that can distinguish between frame and non-frame memory.
38900 For our purposes here, we can get away with (ab)using a jump pattern,
38901 because we're going to do no optimization. */
38904 else
38905 {
38911 {
38917 }
38923 }
38926 /* Emit just enough of rest_of_compilation to get the insns emitted.
38927 Note that use_thunk calls assemble_start_function et al. */
38933 }
38935 static void
38937 {
38941 #if TARGET_MACHO
38943 #endif
38950 }
38952 int
38954 {
38966 }
38968 /* Output assembler code to FILE to increment profiler label # LABELNO
38969 for profiling a function entry. */
38970 void
38972 {
38977 {
38978 #ifndef NO_PROFILE_COUNTERS
38980 #endif
38984 else
38986 }
38988 {
38989 #ifndef NO_PROFILE_COUNTERS
38992 #endif
38994 }
38995 else
38996 {
38997 #ifndef NO_PROFILE_COUNTERS
39000 #endif
39002 }
39003 }
39005 /* We don't have exact information about the insn sizes, but we may assume
39006 quite safely that we are informed about all 1 byte insns and memory
39007 address sizes. This is enough to eliminate unnecessary padding in
39008 99% of cases. */
39010 static int
39012 {
39018 /* Discard alignments we've emit and jump instructions. */
39023 /* Important case - calls are always 5 bytes.
39024 It is common to have many calls in the row. */
39033 /* For normal instructions we rely on get_attr_length being exact,
39034 with a few exceptions. */
39036 {
39040 {
39050 /* Otherwise trust get_attr_length. */
39052 }
39057 }
39060 else
39062 }
39064 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39066 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39067 window. */
39069 static void
39071 {
39076 /* Look for all minimal intervals of instructions containing 4 jumps.
39077 The intervals are bounded by START and INSN. NBYTES is the total
39078 size of instructions in the interval including INSN and not including
39079 START. When the NBYTES is smaller than 16 bytes, it is possible
39080 that the end of START and INSN ends up in the same 16byte page.
39082 The smallest offset in the page INSN can start is the case where START
39083 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39084 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39086 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39087 have to, control transfer to label(s) can be performed through other
39088 means, and also we estimate minimum length of all asm stmts as 0. */
39090 {
39094 {
39100 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39101 already in the current 16 byte page, because otherwise
39102 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39103 bytes to reach 16 byte boundary. */
39111 {
39113 {
39118 else
39121 }
39122 }
39124 }
39133 njumps++;
39134 else
39138 {
39143 else
39146 }
39153 {
39160 }
39161 }
39162 }
39163 #endif
39165 /* AMD Athlon works faster
39166 when RET is not destination of conditional jump or directly preceded
39167 by other jump instruction. We avoid the penalty by inserting NOP just
39168 before the RET instructions in such cases. */
39169 static void
39171 {
39172 edge e;
39173 edge_iterator ei;
39176 {
39179 rtx prev;
39189 {
39190 edge e;
39191 edge_iterator ei;
39196 {
39199 }
39200 }
39202 {
39208 /* Empty functions get branch mispredict even when
39209 the jump destination is not visible to us. */
39212 }
39214 {
39217 }
39218 }
39219 }
39221 /* Count the minimum number of instructions in BB. Return 4 if the
39222 number of instructions >= 4. */
39224 static int
39226 {
39227 rtx insn;
39230 /* Count number of instructions in this block. Return 4 if the number
39231 of instructions >= 4. */
39233 {
39234 /* Only happen in exit blocks. */
39242 {
39243 insn_count++;
39246 }
39247 }
39250 }
39253 /* Count the minimum number of instructions in code path in BB.
39254 Return 4 if the number of instructions >= 4. */
39256 static int
39258 {
39259 edge e;
39260 edge_iterator ei;
39263 /* Only bother counting instructions along paths with no
39264 more than 2 basic blocks between entry and exit. Given
39265 that BB has an edge to exit, determine if a predecessor
39266 of BB has an edge from entry. If so, compute the number
39267 of instructions in the predecessor block. If there
39268 happen to be multiple such blocks, compute the minimum. */
39271 {
39272 edge prev_e;
39273 edge_iterator prev_ei;
39276 {
39279 }
39281 {
39283 {
39288 }
39289 }
39290 }
39296 }
39298 /* Pad short function to 4 instructions. */
39300 static void
39302 {
39303 edge e;
39304 edge_iterator ei;
39307 {
39310 {
39313 /* Pad short function. */
39315 {
39318 /* Find epilogue. */
39327 /* Two NOPs count as one instruction. */
39330 }
39331 }
39332 }
39333 }
39335 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39336 the epilogue, the Windows system unwinder will apply epilogue logic and
39337 produce incorrect offsets. This can be avoided by adding a nop between
39338 the last insn that can throw and the first insn of the epilogue. */
39340 static void
39342 {
39343 edge e;
39344 edge_iterator ei;
39347 {
39350 /* Find the beginning of the epilogue. */
39357 /* We only care about preceding insns that can throw. */
39362 /* Do not separate calls from their debug information. */
39368 else
39372 }
39373 }
39375 /* Implement machine specific optimizations. We implement padding of returns
39376 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39377 static void
39379 {
39380 /* We are freeing block_for_insn in the toplev to keep compatibility
39381 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39388 {
39393 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39396 #endif
39397 }
39398 }
39400 /* Return nonzero when QImode register that must be represented via REX prefix
39401 is used. */
39402 bool
39404 {
39412 }
39414 /* Return nonzero when P points to register encoded via REX prefix.
39415 Called via for_each_rtx. */
39416 static int
39418 {
39424 }
39426 /* Return true when INSN mentions register that must be encoded using REX
39427 prefix. */
39428 bool
39430 {
39433 }
39435 /* If profitable, negate (without causing overflow) integer constant
39436 of mode MODE at location LOC. Return true in this case. */
39437 bool
39439 {
39440 HOST_WIDE_INT val;
39446 {
39448 /* DImode x86_64 constants must fit in 32 bits. */
39461 }
39463 /* Avoid overflows. */
39469 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39470 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39473 {
39476 }
39479 }
39481 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39482 optabs would emit if we didn't have TFmode patterns. */
39484 void
39486 {
39520 }
39521 \f
39522 /* AVX512F does support 64-byte integer vector operations,
39523 thus the longest vector we are faced with is V64QImode. */
39524 #define MAX_VECT_LEN 64
39526 struct expand_vec_perm_d
39527 {
39534 };
39540 /* Get a vector mode of the same size as the original but with elements
39541 twice as wide. This is only guaranteed to apply to integral vectors. */
39545 {
39546 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39551 }
39553 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39554 fill target with val via vec_duplicate. */
39556 static bool
39558 {
39562 /* First attempt to recognize VAL as-is. */
39566 {
39567 rtx seq;
39568 /* If that fails, force VAL into a register. */
39579 }
39581 }
39583 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39584 with all elements equal to VAR. Return true if successful. */
39586 static bool
39589 {
39593 {
39598 /* FALLTHRU */
39618 {
39619 rtx x;
39626 }
39636 {
39640 permute:
39648 /* Extend to SImode using a paradoxical SUBREG. */
39652 /* Insert the SImode value as low element of a V4SImode vector. */
39661 }
39669 widen:
39670 /* Replicate the value once into the next wider mode and recurse. */
39671 {
39673 rtx x;
39690 }
39694 {
39703 }
39708 }
39709 }
39711 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39712 whose ONE_VAR element is VAR, and other elements are zero. Return true
39713 if successful. */
39715 static bool
39718 {
39720 rtx new_target;
39725 {
39727 /* For SSE4.1, we normally use vector set. But if the second
39728 element is zero and inter-unit moves are OK, we use movq
39729 instead. */
39731 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39753 /* Use ix86_expand_vector_set in 64bit mode only. */
39758 }
39761 {
39766 }
39769 {
39774 /* FALLTHRU */
39789 else
39796 {
39797 /* We need to shuffle the value to the correct position, so
39798 create a new pseudo to store the intermediate result. */
39800 /* With SSE2, we can use the integer shuffle insns. */
39802 {
39804 const1_rtx,
39811 }
39813 /* Otherwise convert the intermediate result to V4SFmode and
39814 use the SSE1 shuffle instructions. */
39816 {
39819 }
39820 else
39824 const1_rtx,
39833 }
39848 widen:
39852 /* Zero extend the variable element to SImode and recurse. */
39865 }
39866 }
39868 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39869 consisting of the values in VALS. It is known that all elements
39870 except ONE_VAR are constants. Return true if successful. */
39872 static bool
39875 {
39885 {
39890 /* For the two element vectors, it's just as easy to use
39891 the general case. */
39895 /* Use ix86_expand_vector_set in 64bit mode only. */
39917 widen:
39918 /* There's no way to set one QImode entry easily. Combine
39919 the variable value with its adjacent constant value, and
39920 promote to an HImode set. */
39923 {
39928 }
39929 else
39930 {
39933 }
39947 }
39952 }
39954 /* A subroutine of ix86_expand_vector_init_general. Use vector
39955 concatenate to handle the most general case: all values variable,
39956 and none identical. */
39958 static void
39961 {
39964 rtvec v;
39968 {
39971 {
40016 }
40029 {
40044 }
40049 {
40068 }
40073 {
40086 }
40089 half:
40090 /* FIXME: We process inputs backward to help RA. PR 36222. */
40094 {
40099 }
40103 {
40107 {
40111 }
40114 {
40118 }
40121 }
40123 {
40126 {
40130 }
40133 }
40134 else
40140 }
40141 }
40143 /* A subroutine of ix86_expand_vector_init_general. Use vector
40144 interleave to handle the most general case: all values variable,
40145 and none identical. */
40147 static void
40150 {
40159 {
40180 }
40183 {
40184 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40188 /* Insert the SImode value as low element of V4SImode vector. */
40192 op0),
40194 const1_rtx);
40197 /* Cast the V4SImode vector back to a vector in orignal mode. */
40201 /* Load even elements into the second position. */
40205 const1_rtx));
40207 /* Cast vector to FIRST_IMODE vector. */
40210 }
40212 /* Interleave low FIRST_IMODE vectors. */
40214 {
40218 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40221 }
40223 /* Interleave low SECOND_IMODE vectors. */
40225 {
40228 {
40233 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40234 vector. */
40237 }
40240 /* FALLTHRU */
40247 /* Cast the SECOND_IMODE vector back to a vector on original
40248 mode. */
40255 }
40256 }
40258 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40259 all values variable, and none identical. */
40261 static void
40264 {
40270 {
40275 /* FALLTHRU */
40303 half:
40320 /* FALLTHRU */
40326 /* Don't use ix86_expand_vector_init_interleave if we can't
40327 move from GPR to SSE register directly. */
40343 }
40345 {
40357 {
40361 {
40367 else
40368 {
40373 }
40374 }
40377 }
40382 {
40388 }
40390 {
40396 }
40397 else
40399 }
40400 }
40402 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40403 instructions unless MMX_OK is true. */
40405 void
40407 {
40414 rtx x;
40417 {
40427 }
40429 /* Constants are best loaded from the constant pool. */
40431 {
40434 }
40436 /* If all values are identical, broadcast the value. */
40442 /* Values where only one field is non-constant are best loaded from
40443 the pool and overwritten via move later. */
40445 {
40449 one_var))
40454 }
40457 }
40459 void
40461 {
40466 rtx tmp;
40468 = {
40475 };
40477 = {
40484 };
40488 {
40492 {
40497 else
40501 }
40513 else
40519 {
40522 /* For the two element vectors, we implement a VEC_CONCAT with
40523 the extraction of the other element. */
40530 else
40535 }
40544 {
40550 /* tmp = target = A B C D */
40552 /* target = A A B B */
40554 /* target = X A B B */
40556 /* target = A X C D */
40563 /* tmp = target = A B C D */
40565 /* tmp = X B C D */
40567 /* target = A B X D */
40574 /* tmp = target = A B C D */
40576 /* tmp = X B C D */
40578 /* target = A B X D */
40586 }
40594 /* Element 0 handled by vec_merge below. */
40596 {
40599 }
40602 {
40603 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40604 store into element 0, then shuffle them back. */
40621 }
40622 else
40623 {
40624 /* For SSE1, we have to reuse the V4SF code. */
40628 }
40681 half:
40682 /* Compute offset. */
40688 /* Extract the half. */
40692 /* Put val in tmp at elt. */
40695 /* Put it back. */
40701 }
40704 {
40708 }
40709 else
40710 {
40719 }
40720 }
40722 void
40724 {
40728 rtx tmp;
40731 {
40736 /* FALLTHRU */
40749 {
40769 }
40781 {
40783 {
40803 }
40807 }
40808 else
40809 {
40810 /* For SSE1, we have to reuse the V4SF code. */
40814 }
40830 {
40834 else
40838 }
40843 {
40847 else
40851 }
40856 {
40860 else
40864 }
40869 {
40873 else
40877 }
40882 {
40886 else
40890 }
40895 {
40899 else
40903 }
40910 else
40919 else
40928 else
40937 else
40943 /* ??? Could extract the appropriate HImode element and shift. */
40946 }
40949 {
40953 /* Let the rtl optimizers know about the zero extension performed. */
40955 {
40958 }
40961 }
40962 else
40963 {
40970 }
40971 }
40973 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
40974 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
40975 The upper bits of DEST are undefined, though they shouldn't cause
40976 exceptions (some bits from src or all zeros are ok). */
40978 static void
40980 {
40983 {
40987 else
41005 else
41012 else
41020 {
41025 const1_rtx);
41026 }
41027 else
41028 {
41032 }
41052 else
41074 }
41078 }
41080 /* Expand a vector reduction. FN is the binary pattern to reduce;
41081 DEST is the destination; IN is the input vector. */
41083 void
41085 {
41090 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41094 {
41097 }
41102 {
41107 else
41111 }
41112 }
41113 \f
41114 /* Target hook for scalar_mode_supported_p. */
41115 static bool
41117 {
41122 else
41124 }
41126 /* Implements target hook vector_mode_supported_p. */
41127 static bool
41129 {
41143 }
41145 /* Target hook for c_mode_for_suffix. */
41146 static enum machine_mode
41148 {
41155 }
41157 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41159 We do this in the new i386 backend to maintain source compatibility
41160 with the old cc0-based compiler. */
41162 static tree
41164 tree inputs ATTRIBUTE_UNUSED,
41165 tree clobbers)
41166 {
41168 clobbers);
41170 clobbers);
41172 }
41174 /* Implements target vector targetm.asm.encode_section_info. */
41176 static void ATTRIBUTE_UNUSED
41178 {
41185 }
41187 /* Worker function for REVERSE_CONDITION. */
41189 enum rtx_code
41191 {
41195 }
41197 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41198 to OPERANDS[0]. */
41202 {
41204 {
41207 {
41211 }
41215 }
41217 {
41221 else
41222 {
41223 /* There is no non-popping store to memory for XFmode.
41224 So if we need one, follow the store with a load. */
41227 else
41229 }
41230 }
41231 else
41233 }
41235 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41236 FP status register is set. */
41238 void
41240 {
41242 rtx temp;
41247 {
41252 }
41253 else
41254 {
41259 }
41263 pc_rtx);
41268 }
41270 /* Output code to perform a log1p XFmode calculation. */
41273 {
41279 rtx test;
41285 XFmode));
41299 }
41301 /* Emit code for round calculation. */
41303 {
41310 rtx insn;
41315 {
41327 }
41330 {
41351 }
41359 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41361 /* scratch = fxam(op1) */
41364 UNSPEC_FXAM)));
41365 /* e1 = fabs(op1) */
41368 /* e2 = e1 + 0.5 */
41373 /* res = floor(e2) */
41375 {
41380 }
41381 else
41385 {
41388 {
41395 UNSPEC_TRUNC_NOOP)));
41396 }
41412 }
41414 /* flags = signbit(a) */
41417 /* if (flags) then res = -res */
41421 pc_rtx);
41432 }
41434 /* Output code to perform a Newton-Rhapson approximation of a single precision
41435 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41438 {
41446 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41450 /* x0 = rcp(b) estimate */
41454 UNSPEC_RCP14)));
41455 else
41458 UNSPEC_RCP)));
41460 /* e0 = x0 * b */
41464 /* e0 = x0 * e0 */
41468 /* e1 = x0 + x0 */
41472 /* x1 = e1 - e0 */
41476 /* res = a * x1 */
41479 }
41481 /* Output code to perform a Newton-Rhapson approximation of a
41482 single precision floating point [reciprocal] square root. */
41486 {
41488 REAL_VALUE_TYPE r;
41505 {
41508 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41511 }
41513 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41514 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41518 /* x0 = rsqrt(a) estimate */
41521 unspec)));
41523 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41525 {
41533 /* Handle masked compare. */
41535 {
41537 /* Imm value 0x4 corresponds to not-equal comparison. */
41540 }
41541 else
41542 {
41548 }
41549 }
41551 /* e0 = x0 * a */
41554 /* e1 = e0 * x0 */
41558 /* e2 = e1 - 3. */
41565 /* e3 = -.5 * x0 */
41568 else
41569 /* e3 = -.5 * e0 */
41572 /* ret = e2 * e3 */
41575 }
41577 #ifdef TARGET_SOLARIS
41578 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41580 static void
41582 tree decl)
41583 {
41584 /* With Binutils 2.15, the "@unwind" marker must be specified on
41585 every occurrence of the ".eh_frame" section, not just the first
41586 one. */
41589 {
41593 }
41595 #ifndef USE_GAS
41597 {
41600 }
41601 #endif
41604 }
41607 /* Return the mangling of TYPE if it is an extended fundamental type. */
41611 {
41619 {
41621 /* __float128 is "g". */
41624 /* "long double" or __float80 is "e". */
41628 }
41629 }
41631 /* For 32-bit code we can save PIC register setup by using
41632 __stack_chk_fail_local hidden function instead of calling
41633 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41634 register, so it is better to call __stack_chk_fail directly. */
41636 static tree ATTRIBUTE_UNUSED
41638 {
41639 return TARGET_64BIT
41642 }
41644 /* Select a format to encode pointers in exception handling data. CODE
41645 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41646 true if the symbol may be affected by dynamic relocations.
41648 ??? All x86 object file formats are capable of representing this.
41649 After all, the relocation needed is the same as for the call insn.
41650 Whether or not a particular assembler allows us to enter such, I
41651 guess we'll have to see. */
41652 int
41654 {
41656 {
41663 }
41668 }
41669 \f
41670 /* Expand copysign from SIGN to the positive value ABS_VALUE
41671 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41672 the sign-bit. */
41673 static void
41675 {
41679 {
41686 else
41691 {
41692 /* We need to generate a scalar mode mask in this case. */
41697 }
41698 }
41699 else
41705 }
41707 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41708 mask for masking out the sign-bit is stored in *SMASK, if that is
41709 non-null. */
41710 static rtx
41712 {
41721 else
41725 {
41726 /* We need to generate a scalar mode mask in this case. */
41731 }
41739 }
41741 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41742 swapping the operands if SWAP_OPERANDS is true. The expanded
41743 code is a forward jump to a newly created label in case the
41744 comparison is true. The generated label rtx is returned. */
41745 static rtx
41748 {
41753 {
41757 }
41770 }
41772 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41773 using comparison code CODE. Operands are swapped for the comparison if
41774 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41775 static rtx
41778 {
41784 {
41788 }
41795 }
41797 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41798 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41799 static rtx
41801 {
41802 REAL_VALUE_TYPE TWO52r;
41803 rtx TWO52;
41810 }
41812 /* Expand SSE sequence for computing lround from OP1 storing
41813 into OP0. */
41814 void
41816 {
41817 /* C code for the stuff we're doing below:
41818 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41819 return (long)tmp;
41820 */
41824 rtx adj;
41826 /* load nextafter (0.5, 0.0) */
41831 /* adj = copysign (0.5, op1) */
41835 /* adj = op1 + adj */
41838 /* op0 = (imode)adj */
41840 }
41842 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41843 into OPERAND0. */
41844 void
41846 {
41847 /* C code for the stuff we're doing below (for do_floor):
41848 xi = (long)op1;
41849 xi -= (double)xi > op1 ? 1 : 0;
41850 return xi;
41851 */
41856 /* reg = (long)op1 */
41860 /* freg = (double)reg */
41864 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41875 }
41877 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41878 result in OPERAND0. */
41879 void
41881 {
41882 /* C code for the stuff we're doing below:
41883 xa = fabs (operand1);
41884 if (!isless (xa, 2**52))
41885 return operand1;
41886 xa = xa + 2**52 - 2**52;
41887 return copysign (xa, operand1);
41888 */
41895 /* xa = abs (operand1) */
41898 /* if (!isless (xa, TWO52)) goto label; */
41911 }
41913 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41914 into OPERAND0. */
41915 void
41917 {
41918 /* C code for the stuff we expand below.
41919 double xa = fabs (x), x2;
41920 if (!isless (xa, TWO52))
41921 return x;
41922 xa = xa + TWO52 - TWO52;
41923 x2 = copysign (xa, x);
41924 Compensate. Floor:
41925 if (x2 > x)
41926 x2 -= 1;
41927 Compensate. Ceil:
41928 if (x2 < x)
41929 x2 -= -1;
41930 return x2;
41931 */
41937 /* Temporary for holding the result, initialized to the input
41938 operand to ease control flow. */
41942 /* xa = abs (operand1) */
41945 /* if (!isless (xa, TWO52)) goto label; */
41948 /* xa = xa + TWO52 - TWO52; */
41952 /* xa = copysign (xa, operand1) */
41955 /* generate 1.0 or -1.0 */
41960 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41964 /* We always need to subtract here to preserve signed zero. */
41973 }
41975 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41976 into OPERAND0. */
41977 void
41979 {
41980 /* C code for the stuff we expand below.
41981 double xa = fabs (x), x2;
41982 if (!isless (xa, TWO52))
41983 return x;
41984 x2 = (double)(long)x;
41985 Compensate. Floor:
41986 if (x2 > x)
41987 x2 -= 1;
41988 Compensate. Ceil:
41989 if (x2 < x)
41990 x2 += 1;
41991 if (HONOR_SIGNED_ZEROS (mode))
41992 return copysign (x2, x);
41993 return x2;
41994 */
42000 /* Temporary for holding the result, initialized to the input
42001 operand to ease control flow. */
42005 /* xa = abs (operand1) */
42008 /* if (!isless (xa, TWO52)) goto label; */
42011 /* xa = (double)(long)x */
42016 /* generate 1.0 */
42019 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42034 }
42036 /* Expand SSE sequence for computing round from OPERAND1 storing
42037 into OPERAND0. Sequence that works without relying on DImode truncation
42038 via cvttsd2siq that is only available on 64bit targets. */
42039 void
42041 {
42042 /* C code for the stuff we expand below.
42043 double xa = fabs (x), xa2, x2;
42044 if (!isless (xa, TWO52))
42045 return x;
42046 Using the absolute value and copying back sign makes
42047 -0.0 -> -0.0 correct.
42048 xa2 = xa + TWO52 - TWO52;
42049 Compensate.
42050 dxa = xa2 - xa;
42051 if (dxa <= -0.5)
42052 xa2 += 1;
42053 else if (dxa > 0.5)
42054 xa2 -= 1;
42055 x2 = copysign (xa2, x);
42056 return x2;
42057 */
42063 /* Temporary for holding the result, initialized to the input
42064 operand to ease control flow. */
42068 /* xa = abs (operand1) */
42071 /* if (!isless (xa, TWO52)) goto label; */
42074 /* xa2 = xa + TWO52 - TWO52; */
42078 /* dxa = xa2 - xa; */
42081 /* generate 0.5, 1.0 and -0.5 */
42087 /* Compensate. */
42089 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42094 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42100 /* res = copysign (xa2, operand1) */
42107 }
42109 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42110 into OPERAND0. */
42111 void
42113 {
42114 /* C code for SSE variant we expand below.
42115 double xa = fabs (x), x2;
42116 if (!isless (xa, TWO52))
42117 return x;
42118 x2 = (double)(long)x;
42119 if (HONOR_SIGNED_ZEROS (mode))
42120 return copysign (x2, x);
42121 return x2;
42122 */
42128 /* Temporary for holding the result, initialized to the input
42129 operand to ease control flow. */
42133 /* xa = abs (operand1) */
42136 /* if (!isless (xa, TWO52)) goto label; */
42139 /* x = (double)(long)x */
42151 }
42153 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42154 into OPERAND0. */
42155 void
42157 {
42161 /* C code for SSE variant we expand below.
42162 double xa = fabs (x), x2;
42163 if (!isless (xa, TWO52))
42164 return x;
42165 xa2 = xa + TWO52 - TWO52;
42166 Compensate:
42167 if (xa2 > xa)
42168 xa2 -= 1.0;
42169 x2 = copysign (xa2, x);
42170 return x2;
42171 */
42175 /* Temporary for holding the result, initialized to the input
42176 operand to ease control flow. */
42180 /* xa = abs (operand1) */
42183 /* if (!isless (xa, TWO52)) goto label; */
42186 /* res = xa + TWO52 - TWO52; */
42191 /* generate 1.0 */
42194 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42202 /* res = copysign (res, operand1) */
42209 }
42211 /* Expand SSE sequence for computing round from OPERAND1 storing
42212 into OPERAND0. */
42213 void
42215 {
42216 /* C code for the stuff we're doing below:
42217 double xa = fabs (x);
42218 if (!isless (xa, TWO52))
42219 return x;
42220 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42221 return copysign (xa, x);
42222 */
42228 /* Temporary for holding the result, initialized to the input
42229 operand to ease control flow. */
42237 /* load nextafter (0.5, 0.0) */
42242 /* xa = xa + 0.5 */
42246 /* xa = (double)(int64_t)xa */
42251 /* res = copysign (xa, operand1) */
42258 }
42260 /* Expand SSE sequence for computing round
42261 from OP1 storing into OP0 using sse4 round insn. */
42262 void
42264 {
42273 {
42284 }
42286 /* round (a) = trunc (a + copysign (0.5, a)) */
42288 /* load nextafter (0.5, 0.0) */
42294 /* e1 = copysign (0.5, op1) */
42298 /* e2 = op1 + e1 */
42301 /* res = trunc (e2) */
42306 }
42307 \f
42309 /* Table of valid machine attributes. */
42311 {
42312 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42313 affects_type_identity } */
42314 /* Stdcall attribute says callee is responsible for popping arguments
42315 if they are not variable. */
42318 /* Fastcall attribute says callee is responsible for popping arguments
42319 if they are not variable. */
42322 /* Thiscall attribute says callee is responsible for popping arguments
42323 if they are not variable. */
42326 /* Cdecl attribute says the callee is a normal C declaration */
42329 /* Regparm attribute specifies how many integer arguments are to be
42330 passed in registers. */
42333 /* Sseregparm attribute says we are using x86_64 calling conventions
42334 for FP arguments. */
42337 /* The transactional memory builtins are implicitly regparm or fastcall
42338 depending on the ABI. Override the generic do-nothing attribute that
42339 these builtins were declared with. */
42342 /* force_align_arg_pointer says this function realigns the stack at entry. */
42345 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42350 #endif
42355 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42356 SUBTARGET_ATTRIBUTE_TABLE,
42357 #endif
42358 /* ms_abi and sysv_abi calling convention function attributes. */
42365 /* End element. */
42367 };
42369 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42370 static int
42372 tree vectype,
42374 {
42378 {
42423 }
42424 }
42426 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42427 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42428 insn every time. */
42432 /* Initialize vselect_insn. */
42434 static void
42436 {
42438 rtx x;
42449 }
42451 /* Construct (set target (vec_select op0 (parallel perm))) and
42452 return true if that's a valid instruction in the active ISA. */
42454 static bool
42457 {
42483 }
42485 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42487 static bool
42491 {
42493 rtx x;
42508 }
42510 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42511 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42513 static bool
42515 {
42524 ;
42526 ;
42528 ;
42529 else
42532 /* This is a blend, not a permute. Elements must stay in their
42533 respective lanes. */
42535 {
42539 }
42544 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42545 decision should be extracted elsewhere, so that we only try that
42546 sequence once all budget==3 options have been tried. */
42553 {
42577 /* See if bytes move in pairs so we can use pblendw with
42578 an immediate argument, rather than pblendvb with a vector
42579 argument. */
42582 {
42583 use_pblendvb:
42587 finish_pblendvb:
42593 else
42598 }
42603 /* FALLTHRU */
42605 do_subreg:
42612 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42616 /* See if bytes move in quadruplets. If yes, vpblendd
42617 with immediate can be used. */
42622 {
42623 /* See if bytes move the same in both lanes. If yes,
42624 vpblendw with immediate can be used. */
42629 /* Use vpblendw. */
42634 }
42636 /* Use vpblendd. */
42643 /* See if words move in pairs. If yes, vpblendd can be used. */
42648 {
42649 /* See if words move the same in both lanes. If not,
42650 vpblendvb must be used. */
42653 {
42654 /* Use vpblendvb. */
42664 }
42666 /* Use vpblendw. */
42670 }
42672 /* Use vpblendd. */
42679 /* Use vpblendd. */
42687 }
42689 /* This matches five different patterns with the different modes. */
42697 }
42699 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42700 in terms of the variable form of vpermilps.
42702 Note that we will have already failed the immediate input vpermilps,
42703 which requires that the high and low part shuffle be identical; the
42704 variable form doesn't require that. */
42706 static bool
42708 {
42715 /* We can only permute within the 128-bit lane. */
42717 {
42721 }
42727 {
42730 /* Within each 128-bit lane, the elements of op0 are numbered
42731 from 0 and the elements of op1 are numbered from 4. */
42738 }
42745 }
42747 /* Return true if permutation D can be performed as VMODE permutation
42748 instead. */
42750 static bool
42752 {
42767 else
42773 }
42775 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42776 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42778 static bool
42780 {
42789 {
42791 {
42794 {
42798 /* Use vperm2i128 insn. The pattern uses
42799 V4DImode instead of V2TImode. */
42812 }
42814 }
42815 }
42816 else
42817 {
42819 {
42822 }
42824 {
42828 /* V4DImode should be already handled through
42829 expand_vselect by vpermq instruction. */
42836 {
42837 /* First see if vpermq can be used for
42838 V8SImode/V16HImode/V32QImode. */
42840 {
42848 {
42852 }
42854 }
42856 /* Next see if vpermd can be used. */
42859 }
42860 /* Or if vpermps can be used. */
42865 {
42866 /* vpshufb only works intra lanes, it is not
42867 possible to shuffle bytes in between the lanes. */
42871 }
42872 }
42873 else
42875 }
42883 else
42884 {
42890 else
42894 {
42898 }
42899 }
42910 {
42917 else
42919 }
42920 else
42921 {
42924 }
42929 }
42931 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
42932 in a single instruction. */
42934 static bool
42936 {
42940 /* Check plain VEC_SELECT first, because AVX has instructions that could
42941 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
42942 input where SEL+CONCAT may not. */
42944 {
42950 {
42956 }
42959 {
42963 }
42965 {
42966 /* Use vpbroadcast{b,w,d}. */
42969 {
42988 /* For other modes prefer other shuffles this function creates. */
42990 }
42992 {
42996 }
42997 }
43002 /* There are plenty of patterns in sse.md that are written for
43003 SEL+CONCAT and are not replicated for a single op. Perhaps
43004 that should be changed, to avoid the nastiness here. */
43006 /* Recognize interleave style patterns, which means incrementing
43007 every other permutation operand. */
43009 {
43012 }
43017 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
43019 {
43021 {
43026 }
43031 }
43032 }
43034 /* Finally, try the fully general two operand permute. */
43039 /* Recognize interleave style patterns with reversed operands. */
43041 {
43043 {
43047 else
43050 }
43055 }
43057 /* Try the SSE4.1 blend variable merge instructions. */
43061 /* Try one of the AVX vpermil variable permutations. */
43065 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43066 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43070 /* Try the AVX512F vpermi2 instructions. */
43084 }
43086 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43087 in terms of a pair of pshuflw + pshufhw instructions. */
43089 static bool
43091 {
43099 /* The two permutations only operate in 64-bit lanes. */
43110 /* Emit the pshuflw. */
43117 /* Emit the pshufhw. */
43125 }
43127 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43128 the permutation using the SSSE3 palignr instruction. This succeeds
43129 when all of the elements in PERM fit within one vector and we merely
43130 need to shift them down so that a single vector permutation has a
43131 chance to succeed. */
43133 static bool
43135 {
43142 /* Even with AVX, palignr only operates on 128-bit vectors. */
43148 {
43154 }
43158 /* Given that we have SSSE3, we know we'll be able to implement the
43159 single operand permutation after the palignr with pshufb. */
43174 {
43179 }
43181 /* Test for the degenerate case where the alignment by itself
43182 produces the desired permutation. */
43184 {
43187 }
43193 }
43197 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43198 a two vector permutation into a single vector permutation by using
43199 an interleave operation to merge the vectors. */
43201 static bool
43203 {
43208 rtx seq;
43212 {
43215 }
43217 {
43220 /* For 32-byte modes allow even d->one_operand_p.
43221 The lack of cross-lane shuffling in some instructions
43222 might prevent a single insn shuffle. */
43225 /* If expand_vec_perm_interleave3 can expand this into
43226 a 3 insn sequence, give up and let it be expanded as
43227 3 insn sequence. While that is one insn longer,
43228 it doesn't need a memory operand and in the common
43229 case that both interleave low and high permutations
43230 with the same operands are adjacent needs 4 insns
43231 for both after CSE. */
43234 }
43235 else
43238 /* Examine from whence the elements come. */
43247 {
43250 /* Split the two input vectors into 4 halves. */
43256 /* If the elements from the low halves use interleave low, and similarly
43257 for interleave high. If the elements are from mis-matched halves, we
43258 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43260 {
43261 /* punpckl* */
43263 {
43268 }
43271 }
43273 {
43274 /* punpckh* */
43276 {
43281 }
43284 }
43286 {
43287 /* shufps */
43289 {
43294 }
43296 {
43297 /* shufpd */
43302 }
43303 }
43305 {
43306 /* shufps */
43308 {
43313 }
43315 {
43316 /* shufpd */
43321 }
43322 }
43323 else
43325 }
43326 else
43327 {
43332 /* Split the two input vectors into 8 quarters. */
43338 {
43341 }
43344 {
43348 }
43350 {
43353 }
43356 {
43358 {
43359 /* Attempt to increase the likelihood that dfinal
43360 shuffle will be intra-lane. */
43364 }
43366 /* vperm2f128 or vperm2i128. */
43368 {
43373 }
43378 {
43382 {
43385 }
43386 }
43387 }
43392 {
43393 /* vpunpckl* */
43395 {
43404 }
43405 }
43408 {
43409 /* vpunpckh* */
43411 {
43420 }
43421 }
43422 else
43424 }
43426 /* Use the remapping array set up above to move the elements from their
43427 swizzled locations into their final destinations. */
43430 {
43433 /* If same_halves is true, both halves of the remapped vector are the
43434 same. Avoid cross-lane accesses if possible. */
43436 {
43439 }
43440 else
43442 }
43444 {
43447 }
43451 /* Test if the final remap can be done with a single insn. For V4SFmode or
43452 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43465 {
43468 }
43475 }
43477 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43478 a single vector cross-lane permutation into vpermq followed
43479 by any of the single insn permutations. */
43481 static bool
43483 {
43497 {
43500 }
43503 {
43508 }
43521 {
43528 }
43535 {
43540 ;
43543 else
43545 }
43554 }
43556 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43557 a vector permutation using two instructions, vperm2f128 resp.
43558 vperm2i128 followed by any single in-lane permutation. */
43560 static bool
43562 {
43576 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43577 immediate. For perm < 16 the second permutation uses
43578 d->op0 as first operand, for perm >= 16 it uses d->op1
43579 as first operand. The second operand is the result of
43580 vperm2[fi]128. */
43582 {
43583 /* Ignore permutations which do not move anything cross-lane. */
43585 {
43586 /* The second shuffle for e.g. V4DFmode has
43587 0123 and ABCD operands.
43588 Ignore AB23, as 23 is already in the second lane
43589 of the first operand. */
43591 /* And 01CD, as 01 is in the first lane of the first
43592 operand. */
43594 /* And 4567, as then the vperm2[fi]128 doesn't change
43595 anything on the original 4567 second operand. */
43597 }
43598 else
43599 {
43600 /* The second shuffle for e.g. V4DFmode has
43601 4567 and ABCD operands.
43602 Ignore AB67, as 67 is already in the second lane
43603 of the first operand. */
43605 /* And 45CD, as 45 is in the first lane of the first
43606 operand. */
43608 /* And 0123, as then the vperm2[fi]128 doesn't change
43609 anything on the original 0123 first operand. */
43611 }
43614 {
43620 else
43622 }
43625 {
43629 }
43630 else
43634 {
43638 /* Found a usable second shuffle. dfirst will be
43639 vperm2f128 on d->op0 and d->op1. */
43650 /* And dsecond is some single insn shuffle, taking
43651 d->op0 and result of vperm2f128 (if perm < 16) or
43652 d->op1 and result of vperm2f128 (otherwise). */
43661 }
43663 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43666 }
43669 }
43671 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43672 a two vector permutation using 2 intra-lane interleave insns
43673 and cross-lane shuffle for 32-byte vectors. */
43675 static bool
43677 {
43684 ;
43686 ;
43687 else
43702 {
43706 else
43712 else
43718 else
43724 else
43730 else
43736 else
43741 }
43745 }
43747 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43748 a single vector permutation using a single intra-lane vector
43749 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43750 the non-swapped and swapped vectors together. */
43752 static bool
43754 {
43757 rtx seq;
43762 || TARGET_AVX2
43771 {
43778 }
43813 }
43815 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43816 permutation using two vperm2f128, followed by a vshufpd insn blending
43817 the two vectors together. */
43819 static bool
43821 {
43864 }
43866 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
43867 permutation with two pshufb insns and an ior. We should have already
43868 failed all two instruction sequences. */
43870 static bool
43872 {
43886 /* Generate two permutation masks. If the required element is within
43887 the given vector it is shuffled into the proper lane. If the required
43888 element is in the other vector, force a zero into the lane by setting
43889 bit 7 in the permutation mask. */
43892 {
43899 {
43902 }
43903 }
43927 }
43929 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
43930 with two vpshufb insns, vpermq and vpor. We should have already failed
43931 all two or three instruction sequences. */
43933 static bool
43935 {
43950 /* Generate two permutation masks. If the required element is within
43951 the same lane, it is shuffled in. If the required element from the
43952 other lane, force a zero by setting bit 7 in the permutation mask.
43953 In the other mask the mask has non-negative elements if element
43954 is requested from the other lane, but also moved to the other lane,
43955 so that the result of vpshufb can have the two V2TImode halves
43956 swapped. */
43959 {
43964 {
43967 }
43968 }
43977 /* Swap the 128-byte lanes of h into hp. */
43981 const1_rtx));
43998 }
44000 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
44001 and extract-odd permutations of two V32QImode and V16QImode operand
44002 with two vpshufb insns, vpor and vpermq. We should have already
44003 failed all two or three instruction sequences. */
44005 static bool
44007 {
44026 /* Generate two permutation masks. In the first permutation mask
44027 the first quarter will contain indexes for the first half
44028 of the op0, the second quarter will contain bit 7 set, third quarter
44029 will contain indexes for the second half of the op0 and the
44030 last quarter bit 7 set. In the second permutation mask
44031 the first quarter will contain bit 7 set, the second quarter
44032 indexes for the first half of the op1, the third quarter bit 7 set
44033 and last quarter indexes for the second half of the op1.
44034 I.e. the first mask e.g. for V32QImode extract even will be:
44035 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44036 (all values masked with 0xf except for -128) and second mask
44037 for extract even will be
44038 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44041 {
44047 {
44050 }
44051 }
44070 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44078 }
44080 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44081 and extract-odd permutations. */
44083 static bool
44085 {
44089 {
44096 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44100 /* Now an unpck[lh]pd will produce the result required. */
44103 else
44109 {
44118 /* Shuffle within the 128-bit lanes to produce:
44119 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44123 /* Shuffle the lanes around to produce:
44124 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44128 /* Shuffle within the 128-bit lanes to produce:
44129 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44132 /* Shuffle within the 128-bit lanes to produce:
44133 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44136 /* Shuffle the lanes around to produce:
44137 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44140 }
44147 /* These are always directly implementable by expand_vec_perm_1. */
44153 else
44154 {
44157 /* We need 2*log2(N)-1 operations to achieve odd/even
44158 with interleave. */
44167 else
44170 }
44176 else
44177 {
44191 else
44194 }
44203 {
44208 else
44213 {
44218 }
44220 }
44228 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44232 /* Now an vpunpck[lh]qdq will produce the result required. */
44235 else
44242 {
44247 else
44252 {
44257 }
44259 }
44270 /* Shuffle the lanes around into
44271 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44279 /* Swap the 2nd and 3rd position in each lane into
44280 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44286 /* Now an vpunpck[lh]qdq will produce
44287 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44291 else
44300 }
44303 }
44305 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44306 extract-even and extract-odd permutations. */
44308 static bool
44310 {
44322 }
44324 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44325 permutations. We assume that expand_vec_perm_1 has already failed. */
44327 static bool
44329 {
44337 {
44340 /* These are special-cased in sse.md so that we can optionally
44341 use the vbroadcast instruction. They expand to two insns
44342 if the input happens to be in a register. */
44349 /* These are always implementable using standard shuffle patterns. */
44354 /* These can be implemented via interleave. We save one insn by
44355 stopping once we have promoted to V4SImode and then use pshufd. */
44358 do
44359 {
44360 rtx dest;
44366 {
44370 }
44377 }
44392 /* For AVX2 broadcasts of the first element vpbroadcast* or
44393 vpermq should be used by expand_vec_perm_1. */
44399 }
44400 }
44402 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44403 broadcast permutations. */
44405 static bool
44407 {
44419 }
44421 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44422 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44423 all the shorter instruction sequences. */
44425 static bool
44427 {
44443 /* Generate 4 permutation masks. If the required element is within
44444 the same lane, it is shuffled in. If the required element from the
44445 other lane, force a zero by setting bit 7 in the permutation mask.
44446 In the other mask the mask has non-negative elements if element
44447 is requested from the other lane, but also moved to the other lane,
44448 so that the result of vpshufb can have the two V2TImode halves
44449 swapped. */
44452 {
44457 }
44463 {
44471 }
44474 {
44476 {
44479 }
44486 }
44488 /* Swap the 128-byte lanes of h[X]. */
44490 {
44496 const1_rtx));
44498 }
44501 {
44503 {
44506 }
44512 }
44515 {
44517 {
44521 }
44524 }
44534 }
44536 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44537 With all of the interface bits taken care of, perform the expansion
44538 in D and return true on success. */
44540 static bool
44542 {
44543 /* Try a single instruction expansion. */
44547 /* Try sequences of two instructions. */
44567 /* Try sequences of three instructions. */
44581 /* Try sequences of four instructions. */
44589 /* ??? Look for narrow permutations whose element orderings would
44590 allow the promotion to a wider mode. */
44592 /* ??? Look for sequences of interleave or a wider permute that place
44593 the data into the correct lanes for a half-vector shuffle like
44594 pshuf[lh]w or vpermilps. */
44596 /* ??? Look for sequences of interleave that produce the desired results.
44597 The combinatorics of punpck[lh] get pretty ugly... */
44602 /* Even longer sequences. */
44607 }
44609 /* If a permutation only uses one operand, make it clear. Returns true
44610 if the permutation references both operands. */
44612 static bool
44614 {
44622 {
44628 {
44631 }
44632 /* The elements of PERM do not suggest that only the first operand
44633 is used, but both operands are identical. Allow easier matching
44634 of the permutation by folding the permutation into the single
44635 input vector. */
44636 /* FALLTHRU */
44647 }
44650 }
44652 bool
44654 {
44659 rtx sel;
44676 {
44681 }
44688 /* If the selector says both arguments are needed, but the operands are the
44689 same, the above tried to expand with one_operand_p and flattened selector.
44690 If that didn't work, retry without one_operand_p; we succeeded with that
44691 during testing. */
44693 {
44697 }
44700 }
44702 /* Implement targetm.vectorize.vec_perm_const_ok. */
44704 static bool
44707 {
44716 /* Given sufficient ISA support we can just return true here
44717 for selected vector modes. */
44720 /* All implementable with a single vpermi2 insn. */
44723 {
44724 /* All implementable with a single vpperm insn. */
44727 /* All implementable with 2 pshufb + 1 ior. */
44730 /* All implementable with shufpd or unpck[lh]pd. */
44733 }
44735 /* Extract the values from the vector CST into the permutation
44736 array in D. */
44739 {
44743 }
44745 /* For all elements from second vector, fold the elements to first. */
44750 /* Check whether the mask can be applied to the vector type. */
44753 /* Implementable with shufps or pshufd. */
44757 /* Otherwise we have to go through the motions and see if we can
44758 figure out how to generate the requested permutation. */
44769 }
44771 void
44773 {
44788 /* We'll either be able to implement the permutation directly... */
44792 /* ... or we use the special-case patterns. */
44794 }
44796 static void
44798 {
44813 {
44816 }
44818 /* Note that for AVX this isn't one instruction. */
44821 }
44824 /* Expand a vector operation CODE for a V*QImode in terms of the
44825 same operation on V*HImode. */
44827 void
44829 {
44841 {
44854 }
44858 {
44860 /* Unpack data such that we've got a source byte in each low byte of
44861 each word. We don't care what goes into the high byte of each word.
44862 Rather than trying to get zero in there, most convenient is to let
44863 it be a copy of the low byte. */
44868 /* FALLTHRU */
44880 /* FALLTHRU */
44890 }
44892 /* Perform the operation. */
44899 /* Merge the data back into the right place. */
44909 {
44910 /* For SSE2, we used an full interleave, so the desired
44911 results are in the even elements. */
44914 }
44915 else
44916 {
44917 /* For AVX, the interleave used above was not cross-lane. So the
44918 extraction is evens but with the second and third quarter swapped.
44919 Happily, that is even one insn shorter than even extraction. */
44922 }
44929 }
44931 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
44932 if op is CONST_VECTOR with all odd elements equal to their
44933 preceding element. */
44935 static bool
44937 {
44947 }
44949 void
44952 {
44955 rtx x;
44963 /* We only play even/odd games with vectors of SImode. */
44966 /* If we're looking for the odd results, shift those members down to
44967 the even slots. For some cpus this is faster than a PSHUFD. */
44969 {
44970 /* For XOP use vpmacsdqh, but only for smult, as it is only
44971 signed. */
44973 {
44977 }
44988 }
44991 {
44994 else
44996 }
44998 {
45001 else
45003 }
45008 else
45009 {
45012 /* The easiest way to implement this without PMULDQ is to go through
45013 the motions as if we are performing a full 64-bit multiply. With
45014 the exception that we need to do less shuffling of the elements. */
45016 /* Compute the sign-extension, aka highparts, of the two operands. */
45022 /* Multiply LO(A) * HI(B), and vice-versa. */
45028 /* Multiply LO(A) * LO(B). */
45032 /* Combine and shift the highparts into place. */
45037 /* Combine high and low parts. */
45040 }
45042 }
45044 void
45047 {
45053 {
45058 {
45059 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45060 shuffle the elements once so that all elements are in the right
45061 place for immediate use: { A C B D }. */
45066 }
45067 else
45068 {
45069 /* Put the elements into place for the multiply. */
45073 }
45078 /* Shuffle the elements between the lanes. After this we
45079 have { A B E F | C D G H } for each operand. */
45089 /* Shuffle the elements within the lanes. After this we
45090 have { A A B B | C C D D } or { E E F F | G G H H }. */
45128 }
45129 }
45131 void
45133 {
45143 /* Move the results in element 2 down to element 1; we don't care
45144 what goes in elements 2 and 3. Then we can merge the parts
45145 back together with an interleave.
45147 Note that two other sequences were tried:
45148 (1) Use interleaves at the start instead of psrldq, which allows
45149 us to use a single shufps to merge things back at the end.
45150 (2) Use shufps here to combine the two vectors, then pshufd to
45151 put the elements in the correct order.
45152 In both cases the cost of the reformatting stall was too high
45153 and the overall sequence slower. */
45164 }
45166 void
45168 {
45173 {
45174 /* op1: A,B,C,D, op2: E,F,G,H */
45183 /* t1: B,A,D,C */
45190 /* t2: (B*E),(A*F),(D*G),(C*H) */
45193 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45196 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45199 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
45201 }
45202 else
45203 {
45208 {
45211 }
45213 {
45216 }
45218 {
45221 }
45222 else
45226 /* Multiply low parts. */
45230 /* Shift input vectors right 32 bits so we can multiply high parts. */
45235 /* Multiply high parts by low parts. */
45241 /* Combine and shift the highparts back. */
45245 /* Combine high and low parts. */
45247 }
45251 }
45253 /* Calculate integer abs() using only SSE2 instructions. */
45255 void
45257 {
45262 {
45263 /* For 32-bit signed integer X, the best way to calculate the absolute
45264 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45276 /* For 16-bit signed integer X, the best way to calculate the absolute
45277 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45285 /* For 8-bit signed integer X, the best way to calculate the absolute
45286 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45287 as SSE2 provides the PMINUB insn. */
45297 }
45301 }
45303 /* Expand an insert into a vector register through pinsr insn.
45304 Return true if successful. */
45306 bool
45308 {
45316 {
45319 }
45325 {
45330 {
45337 {
45369 }
45383 }
45387 }
45388 }
45389 \f
45390 /* This function returns the calling abi specific va_list type node.
45391 It returns the FNDECL specific va_list type. */
45393 static tree
45395 {
45402 else
45404 }
45406 /* Returns the canonical va_list type specified by TYPE. If there
45407 is no valid TYPE provided, it return NULL_TREE. */
45409 static tree
45411 {
45414 /* Resolve references and pointers to va_list type. */
45423 {
45428 {
45429 /* If va_list is an array type, the argument may have decayed
45430 to a pointer type, e.g. by being passed to another function.
45431 In that case, unwrap both types so that we can compare the
45432 underlying records. */
45435 {
45438 }
45439 }
45446 {
45447 /* If va_list is an array type, the argument may have decayed
45448 to a pointer type, e.g. by being passed to another function.
45449 In that case, unwrap both types so that we can compare the
45450 underlying records. */
45453 {
45456 }
45457 }
45464 {
45465 /* If va_list is an array type, the argument may have decayed
45466 to a pointer type, e.g. by being passed to another function.
45467 In that case, unwrap both types so that we can compare the
45468 underlying records. */
45471 {
45474 }
45475 }
45479 }
45481 }
45483 /* Iterate through the target-specific builtin types for va_list.
45484 IDX denotes the iterator, *PTREE is set to the result type of
45485 the va_list builtin, and *PNAME to its internal type.
45486 Returns zero if there is no element for this index, otherwise
45487 IDX should be increased upon the next call.
45488 Note, do not iterate a base builtin's name like __builtin_va_list.
45489 Used from c_common_nodes_and_builtins. */
45491 static int
45493 {
45495 {
45497 {
45510 }
45511 }
45514 }
45516 #undef TARGET_SCHED_DISPATCH
45517 #define TARGET_SCHED_DISPATCH has_dispatch
45518 #undef TARGET_SCHED_DISPATCH_DO
45519 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45520 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45521 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45522 #undef TARGET_SCHED_REORDER
45523 #define TARGET_SCHED_REORDER ix86_sched_reorder
45524 #undef TARGET_SCHED_ADJUST_PRIORITY
45525 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45526 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45527 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45528 ix86_dependencies_evaluation_hook
45530 /* The size of the dispatch window is the total number of bytes of
45531 object code allowed in a window. */
45532 #define DISPATCH_WINDOW_SIZE 16
45534 /* Number of dispatch windows considered for scheduling. */
45535 #define MAX_DISPATCH_WINDOWS 3
45537 /* Maximum number of instructions in a window. */
45538 #define MAX_INSN 4
45540 /* Maximum number of immediate operands in a window. */
45541 #define MAX_IMM 4
45543 /* Maximum number of immediate bits allowed in a window. */
45544 #define MAX_IMM_SIZE 128
45546 /* Maximum number of 32 bit immediates allowed in a window. */
45547 #define MAX_IMM_32 4
45549 /* Maximum number of 64 bit immediates allowed in a window. */
45550 #define MAX_IMM_64 2
45552 /* Maximum total of loads or prefetches allowed in a window. */
45553 #define MAX_LOAD 2
45555 /* Maximum total of stores allowed in a window. */
45556 #define MAX_STORE 1
45558 #undef BIG
45559 #define BIG 100
45562 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45565 disp_load,
45566 disp_store,
45567 disp_load_store,
45568 disp_prefetch,
45569 disp_imm,
45570 disp_imm_32,
45571 disp_imm_64,
45572 disp_branch,
45573 disp_cmp,
45574 disp_jcc,
45575 disp_last
45576 };
45578 /* Number of allowable groups in a dispatch window. It is an array
45579 indexed by dispatch_group enum. 100 is used as a big number,
45580 because the number of these kind of operations does not have any
45581 effect in dispatch window, but we need them for other reasons in
45582 the table. */
45585 };
45591 };
45593 /* Instruction path. */
45599 last_path
45600 };
45602 /* sched_insn_info defines a window to the instructions scheduled in
45603 the basic block. It contains a pointer to the insn_info table and
45604 the instruction scheduled.
45606 Windows are allocated for each basic block and are linked
45607 together. */
45609 rtx insn;
45616 /* Linked list of dispatch windows. This is a two way list of
45617 dispatch windows of a basic block. It contains information about
45618 the number of uops in the window and the total number of
45619 instructions and of bytes in the object code for this dispatch
45620 window. */
45638 /* Immediate valuse used in an insn. */
45640 {
45649 /* Get dispatch group of insn. */
45651 static enum dispatch_group
45653 {
45669 }
45671 /* Return true if insn is a compare instruction. */
45673 static bool
45675 {
45683 }
45685 /* Return true if a dispatch violation encountered. */
45687 static bool
45689 {
45693 }
45695 /* Return true if insn is a branch instruction. */
45697 static bool
45699 {
45701 }
45703 /* Return true if insn is a prefetch instruction. */
45705 static bool
45707 {
45709 }
45711 /* This function initializes a dispatch window and the list container holding a
45712 pointer to the window. */
45714 static void
45716 {
45722 else
45740 {
45746 }
45748 }
45750 /* This function allocates and initializes a dispatch window and the
45751 list container holding a pointer to the window. */
45755 {
45760 }
45762 /* This routine initializes the dispatch scheduling information. It
45763 initiates building dispatch scheduler tables and constructs the
45764 first dispatch window. */
45766 static void
45768 {
45769 /* Allocate a dispatch list and a window. */
45774 }
45776 /* This function returns true if a branch is detected. End of a basic block
45777 does not have to be a branch, but here we assume only branches end a
45778 window. */
45780 static bool
45782 {
45784 }
45786 /* This function is called when the end of a window processing is reached. */
45788 static void
45790 {
45793 {
45798 }
45800 }
45802 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45803 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45804 for 48 bytes of instructions. Note that these windows are not dispatch
45805 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45809 {
45811 {
45816 }
45822 }
45824 /* Increment the number of immediate operands of an instruction. */
45826 static int
45828 {
45833 {
45840 else
45851 {
45854 }
45859 }
45862 }
45864 /* Compute number of immediate operands of an instruction. */
45866 static void
45868 {
45871 }
45873 /* Return total size of immediate operands of an instruction along with number
45874 of corresponding immediate-operands. It initializes its parameters to zero
45875 befor calling FIND_CONSTANT.
45876 INSN is the input instruction. IMM is the total of immediates.
45877 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
45878 bit immediates. */
45880 static int
45882 {
45890 }
45892 /* This function indicates if an operand of an instruction is an
45893 immediate. */
45895 static bool
45897 {
45906 }
45908 /* Return single or double path for instructions. */
45910 static enum insn_path
45912 {
45922 }
45924 /* Return insn dispatch group. */
45926 static enum dispatch_group
45928 {
45946 }
45948 /* Count number of GROUP restricted instructions in a dispatch
45949 window WINDOW_LIST. */
45951 static int
45953 {
45964 {
45983 }
45996 }
45998 /* This function returns true if insn satisfies dispatch rules on the
45999 last window scheduled. */
46001 static bool
46003 {
46011 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
46012 instructions should be given the lowest priority in the
46013 scheduling process in Haifa scheduler to make sure they will be
46014 scheduled in the same dispatch window as the reference to them. */
46018 /* Check nonrestricted. */
46022 /* Get last dispatch window. */
46027 {
46032 /* Window 1 is full. Go for next window. */
46034 }
46041 /* See if it fits in the first window. */
46043 {
46044 /* The first widow should have only single and double path
46045 uops. */
46051 }
46053 }
46055 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46056 dispatch window WINDOW_LIST. */
46058 static void
46060 {
46078 /* Initialize window with new instruction. */
46099 {
46102 }
46103 }
46105 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46106 If the total bytes of instructions or the number of instructions in
46107 the window exceed allowable, it allocates a new window. */
46109 static void
46111 {
46134 /* Get the last dispatch window. */
46142 else
46145 /* If current window is full, get a new window.
46146 Window number zero is full, if MAX_INSN uops are scheduled in it.
46147 Window number one is full, if window zero's bytes plus window
46148 one's bytes is 32, or if the bytes of the new instruction added
46149 to the total makes it greater than 48, or it has already MAX_INSN
46150 instructions in it. */
46159 {
46162 }
46165 {
46169 {
46172 }
46173 }
46175 {
46180 {
46183 }
46186 }
46187 else
46191 {
46192 /* End of basic block is reached do end-basic-block process. */
46195 }
46196 }
46198 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46200 DEBUG_FUNCTION static void
46202 {
46208 else
46222 {
46225 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46231 }
46232 }
46234 /* Print to stdout a dispatch window. */
46236 DEBUG_FUNCTION void
46238 {
46240 }
46242 /* Print INSN dispatch information to FILE. */
46244 DEBUG_FUNCTION static void
46246 {
46269 }
46271 /* Print to STDERR the status of the ready list with respect to
46272 dispatch windows. */
46274 DEBUG_FUNCTION void
46276 {
46284 }
46286 /* This routine is the driver of the dispatch scheduler. */
46288 static void
46290 {
46295 }
46297 /* Return TRUE if Dispatch Scheduling is supported. */
46299 static bool
46301 {
46305 {
46321 }
46324 }
46326 /* Implementation of reassociation_width target hook used by
46327 reassoc phase to identify parallelism level in reassociated
46328 tree. Statements tree_code is passed in OPC. Arguments type
46329 is passed in MODE.
46331 Currently parallel reassociation is enabled for Atom
46332 processors only and we set reassociation width to be 2
46333 because Atom may issue up to 2 instructions per cycle.
46335 Return value should be fixed if parallel reassociation is
46336 enabled for other processors. */
46338 static int
46341 {
46350 }
46352 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46353 place emms and femms instructions. */
46355 static enum machine_mode
46357 {
46362 {
46379 else
46391 /* FALLTHRU */
46395 }
46396 }
46398 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46399 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46400 256bit and 128bit vectors. */
46402 static unsigned int
46404 {
46407 }
46409 \f
46411 /* Return class of registers which could be used for pseudo of MODE
46412 and of class RCLASS for spilling instead of memory. Return NO_REGS
46413 if it is not possible or non-profitable. */
46414 static reg_class_t
46416 {
46422 }
46424 /* Implement targetm.vectorize.init_cost. */
46428 {
46432 }
46434 /* Implement targetm.vectorize.add_stmt_cost. */
46436 static unsigned
46440 {
46447 /* Statements in an inner loop relative to the loop being
46448 vectorized are weighted more heavily. The value here is
46449 arbitrary and could potentially be improved with analysis. */
46457 }
46459 /* Implement targetm.vectorize.finish_cost. */
46461 static void
46464 {
46469 }
46471 /* Implement targetm.vectorize.destroy_cost_data. */
46473 static void
46475 {
46477 }
46479 /* Validate target specific memory model bits in VAL. */
46481 static unsigned HOST_WIDE_INT
46483 {
46490 {
46494 }
46497 {
46501 }
46503 {
46507 }
46509 }
46511 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46512 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46513 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46514 or number of vecsize_mangle variants that should be emitted. */
46516 static int
46520 {
46527 {
46531 }
46536 {
46543 /* case SCmode: */
46544 /* case DCmode: */
46550 }
46552 tree t;
46556 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46558 {
46565 /* case SCmode: */
46566 /* case DCmode: */
46572 }
46575 {
46576 /* Parse here processor clause. If not present, default to 'b'. */
46578 }
46580 {
46581 /* If the function isn't exported, we can pick up just one ISA
46582 for the clones. */
46587 else
46590 }
46591 else
46592 {
46595 }
46597 {
46610 }
46612 {
46615 else
46620 }
46622 }
46624 /* Add target attribute to SIMD clone NODE if needed. */
46626 static void
46628 {
46632 {
46647 }
46657 }
46659 /* If SIMD clone NODE can't be used in a vectorized loop
46660 in current function, return -1, otherwise return a badness of using it
46661 (0 if it is most desirable from vecsize_mangle point of view, 1
46662 slightly less desirable, etc.). */
46664 static int
46666 {
46668 {
46686 }
46687 }
46689 /* This function gives out the number of memory references.
46690 This value determines the unrolling factor for
46691 bdver3 and bdver4 architectures. */
46693 static int
46695 {
46697 {
46706 else
46708 }
46710 }
46712 /* This function adjusts the unroll factor based on
46713 the hardware capabilities. For ex, bdver3 has
46714 a loop buffer which makes unrolling of smaller
46715 loops less important. This function decides the
46716 unroll factor using number of memory references
46717 (value 32 is used) as a heuristic. */
46719 static unsigned
46721 {
46723 rtx insn;
46730 /* Count the number of memory references within the loop body. */
46733 {
46737 }
46744 }
46747 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46749 static bool
46751 {
46752 /* For x87 floating point with standard excess precision handling,
46753 there is no adddf3 pattern (since x87 floating point only has
46754 XFmode operations) so the default hook implementation gets this
46755 wrong. */
46757 }
46759 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46761 static void
46763 {
46768 {
46783 hold_fnclex);
46797 }
46799 {
46808 mxcsr_orig_var,
46818 ldmxcsr_hold_call);
46821 else
46826 ldmxcsr_clear_call);
46827 else
46831 stxmcsr_update_call);
46833 {
46839 exceptions_assign);
46840 }
46841 else
46846 ldmxcsr_update_call);
46847 }
46848 tree atomic_feraiseexcept
46853 atomic_feraiseexcept_call);
46854 }
46856 /* Initialize the GCC target structure. */
46857 #undef TARGET_RETURN_IN_MEMORY
46858 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
46860 #undef TARGET_LEGITIMIZE_ADDRESS
46861 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
46863 #undef TARGET_ATTRIBUTE_TABLE
46864 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
46865 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
46866 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
46867 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46868 # undef TARGET_MERGE_DECL_ATTRIBUTES
46869 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
46870 #endif
46872 #undef TARGET_COMP_TYPE_ATTRIBUTES
46873 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
46875 #undef TARGET_INIT_BUILTINS
46876 #define TARGET_INIT_BUILTINS ix86_init_builtins
46877 #undef TARGET_BUILTIN_DECL
46878 #define TARGET_BUILTIN_DECL ix86_builtin_decl
46879 #undef TARGET_EXPAND_BUILTIN
46880 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
46882 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
46883 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
46884 ix86_builtin_vectorized_function
46886 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
46887 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
46889 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
46890 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
46892 #undef TARGET_VECTORIZE_BUILTIN_GATHER
46893 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
46895 #undef TARGET_BUILTIN_RECIPROCAL
46896 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
46898 #undef TARGET_ASM_FUNCTION_EPILOGUE
46899 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
46901 #undef TARGET_ENCODE_SECTION_INFO
46902 #ifndef SUBTARGET_ENCODE_SECTION_INFO
46903 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
46904 #else
46905 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
46906 #endif
46908 #undef TARGET_ASM_OPEN_PAREN
46910 #undef TARGET_ASM_CLOSE_PAREN
46913 #undef TARGET_ASM_BYTE_OP
46914 #define TARGET_ASM_BYTE_OP ASM_BYTE
46916 #undef TARGET_ASM_ALIGNED_HI_OP
46917 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
46918 #undef TARGET_ASM_ALIGNED_SI_OP
46919 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
46920 #ifdef ASM_QUAD
46921 #undef TARGET_ASM_ALIGNED_DI_OP
46922 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
46923 #endif
46925 #undef TARGET_PROFILE_BEFORE_PROLOGUE
46926 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
46928 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
46929 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
46931 #undef TARGET_ASM_UNALIGNED_HI_OP
46932 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
46933 #undef TARGET_ASM_UNALIGNED_SI_OP
46934 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
46935 #undef TARGET_ASM_UNALIGNED_DI_OP
46936 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
46938 #undef TARGET_PRINT_OPERAND
46939 #define TARGET_PRINT_OPERAND ix86_print_operand
46940 #undef TARGET_PRINT_OPERAND_ADDRESS
46941 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
46942 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
46943 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
46944 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
46945 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
46947 #undef TARGET_SCHED_INIT_GLOBAL
46948 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
46949 #undef TARGET_SCHED_ADJUST_COST
46950 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
46951 #undef TARGET_SCHED_ISSUE_RATE
46952 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
46953 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
46954 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
46955 ia32_multipass_dfa_lookahead
46956 #undef TARGET_SCHED_MACRO_FUSION_P
46957 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
46958 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
46959 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
46961 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
46962 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
46964 #undef TARGET_MEMMODEL_CHECK
46965 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
46967 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
46968 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
46970 #ifdef HAVE_AS_TLS
46971 #undef TARGET_HAVE_TLS
46972 #define TARGET_HAVE_TLS true
46973 #endif
46974 #undef TARGET_CANNOT_FORCE_CONST_MEM
46975 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
46976 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
46977 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
46979 #undef TARGET_DELEGITIMIZE_ADDRESS
46980 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
46982 #undef TARGET_MS_BITFIELD_LAYOUT_P
46983 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
46985 #if TARGET_MACHO
46986 #undef TARGET_BINDS_LOCAL_P
46987 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
46988 #endif
46989 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46990 #undef TARGET_BINDS_LOCAL_P
46991 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
46992 #endif
46994 #undef TARGET_ASM_OUTPUT_MI_THUNK
46995 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
46996 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
46997 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
46999 #undef TARGET_ASM_FILE_START
47000 #define TARGET_ASM_FILE_START x86_file_start
47002 #undef TARGET_OPTION_OVERRIDE
47003 #define TARGET_OPTION_OVERRIDE ix86_option_override
47005 #undef TARGET_REGISTER_MOVE_COST
47006 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
47007 #undef TARGET_MEMORY_MOVE_COST
47008 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
47009 #undef TARGET_RTX_COSTS
47010 #define TARGET_RTX_COSTS ix86_rtx_costs
47011 #undef TARGET_ADDRESS_COST
47012 #define TARGET_ADDRESS_COST ix86_address_cost
47014 #undef TARGET_FIXED_CONDITION_CODE_REGS
47015 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
47016 #undef TARGET_CC_MODES_COMPATIBLE
47017 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
47019 #undef TARGET_MACHINE_DEPENDENT_REORG
47020 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47022 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47023 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47025 #undef TARGET_BUILD_BUILTIN_VA_LIST
47026 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47028 #undef TARGET_FOLD_BUILTIN
47029 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47031 #undef TARGET_COMPARE_VERSION_PRIORITY
47032 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47034 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47035 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47036 ix86_generate_version_dispatcher_body
47038 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47039 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47040 ix86_get_function_versions_dispatcher
47042 #undef TARGET_ENUM_VA_LIST_P
47043 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47045 #undef TARGET_FN_ABI_VA_LIST
47046 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47048 #undef TARGET_CANONICAL_VA_LIST_TYPE
47049 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47051 #undef TARGET_EXPAND_BUILTIN_VA_START
47052 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47054 #undef TARGET_MD_ASM_CLOBBERS
47055 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47057 #undef TARGET_PROMOTE_PROTOTYPES
47058 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47059 #undef TARGET_SETUP_INCOMING_VARARGS
47060 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47061 #undef TARGET_MUST_PASS_IN_STACK
47062 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47063 #undef TARGET_FUNCTION_ARG_ADVANCE
47064 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47065 #undef TARGET_FUNCTION_ARG
47066 #define TARGET_FUNCTION_ARG ix86_function_arg
47067 #undef TARGET_FUNCTION_ARG_BOUNDARY
47068 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47069 #undef TARGET_PASS_BY_REFERENCE
47070 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47071 #undef TARGET_INTERNAL_ARG_POINTER
47072 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47073 #undef TARGET_UPDATE_STACK_BOUNDARY
47074 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47075 #undef TARGET_GET_DRAP_RTX
47076 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47077 #undef TARGET_STRICT_ARGUMENT_NAMING
47078 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47079 #undef TARGET_STATIC_CHAIN
47080 #define TARGET_STATIC_CHAIN ix86_static_chain
47081 #undef TARGET_TRAMPOLINE_INIT
47082 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47083 #undef TARGET_RETURN_POPS_ARGS
47084 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47086 #undef TARGET_LEGITIMATE_COMBINED_INSN
47087 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47089 #undef TARGET_ASAN_SHADOW_OFFSET
47090 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47092 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47093 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47095 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47096 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47098 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47099 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47101 #undef TARGET_C_MODE_FOR_SUFFIX
47102 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47104 #ifdef HAVE_AS_TLS
47105 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47106 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47107 #endif
47109 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47110 #undef TARGET_INSERT_ATTRIBUTES
47111 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47112 #endif
47114 #undef TARGET_MANGLE_TYPE
47115 #define TARGET_MANGLE_TYPE ix86_mangle_type
47117 #if !TARGET_MACHO
47118 #undef TARGET_STACK_PROTECT_FAIL
47119 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47120 #endif
47122 #undef TARGET_FUNCTION_VALUE
47123 #define TARGET_FUNCTION_VALUE ix86_function_value
47125 #undef TARGET_FUNCTION_VALUE_REGNO_P
47126 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47128 #undef TARGET_PROMOTE_FUNCTION_MODE
47129 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47131 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47132 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47134 #undef TARGET_INSTANTIATE_DECLS
47135 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47137 #undef TARGET_SECONDARY_RELOAD
47138 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47140 #undef TARGET_CLASS_MAX_NREGS
47141 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47143 #undef TARGET_PREFERRED_RELOAD_CLASS
47144 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47145 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47146 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47147 #undef TARGET_CLASS_LIKELY_SPILLED_P
47148 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47150 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47151 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47152 ix86_builtin_vectorization_cost
47153 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47154 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47155 ix86_vectorize_vec_perm_const_ok
47156 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47157 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47158 ix86_preferred_simd_mode
47159 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47160 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47161 ix86_autovectorize_vector_sizes
47162 #undef TARGET_VECTORIZE_INIT_COST
47163 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47164 #undef TARGET_VECTORIZE_ADD_STMT_COST
47165 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47166 #undef TARGET_VECTORIZE_FINISH_COST
47167 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47168 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47169 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47171 #undef TARGET_SET_CURRENT_FUNCTION
47172 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47174 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47175 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47177 #undef TARGET_OPTION_SAVE
47178 #define TARGET_OPTION_SAVE ix86_function_specific_save
47180 #undef TARGET_OPTION_RESTORE
47181 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47183 #undef TARGET_OPTION_PRINT
47184 #define TARGET_OPTION_PRINT ix86_function_specific_print
47186 #undef TARGET_OPTION_FUNCTION_VERSIONS
47187 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47189 #undef TARGET_CAN_INLINE_P
47190 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47192 #undef TARGET_EXPAND_TO_RTL_HOOK
47193 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47195 #undef TARGET_LEGITIMATE_ADDRESS_P
47196 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47198 #undef TARGET_LRA_P
47199 #define TARGET_LRA_P hook_bool_void_true
47201 #undef TARGET_REGISTER_PRIORITY
47202 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47204 #undef TARGET_REGISTER_USAGE_LEVELING_P
47205 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47207 #undef TARGET_LEGITIMATE_CONSTANT_P
47208 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47210 #undef TARGET_FRAME_POINTER_REQUIRED
47211 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47213 #undef TARGET_CAN_ELIMINATE
47214 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47216 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47217 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47219 #undef TARGET_ASM_CODE_END
47220 #define TARGET_ASM_CODE_END ix86_code_end
47222 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47223 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47225 #if TARGET_MACHO
47226 #undef TARGET_INIT_LIBFUNCS
47227 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47228 #endif
47230 #undef TARGET_LOOP_UNROLL_ADJUST
47231 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47233 #undef TARGET_SPILL_CLASS
47234 #define TARGET_SPILL_CLASS ix86_spill_class
47236 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47237 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47238 ix86_simd_clone_compute_vecsize_and_simdlen
47240 #undef TARGET_SIMD_CLONE_ADJUST
47241 #define TARGET_SIMD_CLONE_ADJUST \
47242 ix86_simd_clone_adjust
47244 #undef TARGET_SIMD_CLONE_USABLE
47245 #define TARGET_SIMD_CLONE_USABLE \
47246 ix86_simd_clone_usable
47248 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47249 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47250 ix86_float_exceptions_rounding_supported_p
47253 \f