gcc/config/aarch64/aarch64-protos.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_PROTOS_H
  23 #define GCC_AARCH64_PROTOS_H
  24
  25 #include "input.h"
  26
  27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through
  28    high and lo relocs that calculate the base address using a PC
  29    relative reloc.
  30    So to get the address of foo, we generate
  31    adrp x0, foo
  32    add  x0, x0, :lo12:foo
  33
  34    To load or store something to foo, we could use the corresponding
  35    load store variants that generate an
  36    ldr x0, [x0,:lo12:foo]
  37    or
  38    str x1, [x0, :lo12:foo]
  39
  40    This corresponds to the small code model of the compiler.
  41
  42    SYMBOL_SMALL_GOT_4G: Similar to the one above but this
  43    gives us the GOT entry of the symbol being referred to :
  44    Thus calculating the GOT entry for foo is done using the
  45    following sequence of instructions.  The ADRP instruction
  46    gets us to the page containing the GOT entry of the symbol
  47    and the got_lo12 gets us the actual offset in it, together
  48    the base and offset, we can address 4G size GOT table.
  49
  50    adrp  x0, :got:foo
  51    ldr   x0, [x0, :gotoff_lo12:foo]
  52
  53    This corresponds to the small PIC model of the compiler.
  54
  55    SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol
  56    restricted within 28K GOT table size.
  57
  58    ldr reg, [gp, #:gotpage_lo15:sym]
  59
  60    This corresponds to -fpic model for small memory model of the compiler.
  61
  62    SYMBOL_SMALL_TLSGD
  63    SYMBOL_SMALL_TLSDESC
  64    SYMBOL_SMALL_TLSIE
  65    SYMBOL_TINY_TLSIE
  66    SYMBOL_TLSLE12
  67    SYMBOL_TLSLE24
  68    SYMBOL_TLSLE32
  69    SYMBOL_TLSLE48
  70    Each of these represents a thread-local symbol, and corresponds to the
  71    thread local storage relocation operator for the symbol being referred to.
  72
  73    SYMBOL_TINY_ABSOLUTE
  74
  75    Generate symbol accesses as a PC relative address using a single
  76    instruction.  To compute the address of symbol foo, we generate:
  77
  78    ADR x0, foo
  79
  80    SYMBOL_TINY_GOT
  81
  82    Generate symbol accesses via the GOT using a single PC relative
  83    instruction.  To compute the address of symbol foo, we generate:
  84
  85    ldr t0, :got:foo
  86
  87    The value of foo can subsequently read using:
  88
  89    ldrb    t0, [t0]
  90
  91    SYMBOL_FORCE_TO_MEM : Global variables are addressed using
  92    constant pool.  All variable addresses are spilled into constant
  93    pools.  The constant pools themselves are addressed using PC
  94    relative accesses.  This only works for the large code model.
  95  */
  96 enum aarch64_symbol_type
  97 {
  98   SYMBOL_SMALL_ABSOLUTE,
  99   SYMBOL_SMALL_GOT_28K,
 100   SYMBOL_SMALL_GOT_4G,
 101   SYMBOL_SMALL_TLSGD,
 102   SYMBOL_SMALL_TLSDESC,
 103   SYMBOL_SMALL_TLSIE,
 104   SYMBOL_TINY_ABSOLUTE,
 105   SYMBOL_TINY_GOT,
 106   SYMBOL_TINY_TLSIE,
 107   SYMBOL_TLSLE12,
 108   SYMBOL_TLSLE24,
 109   SYMBOL_TLSLE32,
 110   SYMBOL_TLSLE48,
 111   SYMBOL_FORCE_TO_MEM
 112 };
 113
 114 /* Classifies the type of an address query.
 115
 116    ADDR_QUERY_M
 117       Query what is valid for an "m" constraint and a memory_operand
 118       (the rules are the same for both).
 119
 120    ADDR_QUERY_LDP_STP
 121       Query what is valid for a load/store pair.  */
 122 enum aarch64_addr_query_type {
 123   ADDR_QUERY_M,
 124   ADDR_QUERY_LDP_STP
 125 };
 126
 127 /* A set of tuning parameters contains references to size and time
 128    cost models and vectors for address cost calculations, register
 129    move costs and memory move costs.  */
 130
 131 /* Scaled addressing modes can vary cost depending on the mode of the
 132    value to be loaded/stored.  QImode values cannot use scaled
 133    addressing modes.  */
 134
 135 struct scale_addr_mode_cost
 136 {
 137   const int hi;
 138   const int si;
 139   const int di;
 140   const int ti;
 141 };
 142
 143 /* Additional cost for addresses.  */
 144 struct cpu_addrcost_table
 145 {
 146   const struct scale_addr_mode_cost addr_scale_costs;
 147   const int pre_modify;
 148   const int post_modify;
 149   const int register_offset;
 150   const int register_sextend;
 151   const int register_zextend;
 152   const int imm_offset;
 153 };
 154
 155 /* Additional costs for register copies.  Cost is for one register.  */
 156 struct cpu_regmove_cost
 157 {
 158   const int GP2GP;
 159   const int GP2FP;
 160   const int FP2GP;
 161   const int FP2FP;
 162 };
 163
 164 /* Cost for vector insn classes.  */
 165 struct cpu_vector_cost
 166 {
 167   const int scalar_int_stmt_cost;        /* Cost of any int scalar operation,
 168                                             excluding load and store.  */
 169   const int scalar_fp_stmt_cost;         /* Cost of any fp scalar operation,
 170                                             excluding load and store.  */
 171   const int scalar_load_cost;            /* Cost of scalar load.  */
 172   const int scalar_store_cost;           /* Cost of scalar store.  */
 173   const int vec_int_stmt_cost;           /* Cost of any int vector operation,
 174                                             excluding load, store, permute,
 175                                             vector-to-scalar and
 176                                             scalar-to-vector operation.  */
 177   const int vec_fp_stmt_cost;            /* Cost of any fp vector operation,
 178                                             excluding load, store, permute,
 179                                             vector-to-scalar and
 180                                             scalar-to-vector operation.  */
 181   const int vec_permute_cost;            /* Cost of permute operation.  */
 182   const int vec_to_scalar_cost;          /* Cost of vec-to-scalar operation.  */
 183   const int scalar_to_vec_cost;          /* Cost of scalar-to-vector
 184                                             operation.  */
 185   const int vec_align_load_cost;         /* Cost of aligned vector load.  */
 186   const int vec_unalign_load_cost;       /* Cost of unaligned vector load.  */
 187   const int vec_unalign_store_cost;      /* Cost of unaligned vector store.  */
 188   const int vec_store_cost;              /* Cost of vector store.  */
 189   const int cond_taken_branch_cost;      /* Cost of taken branch.  */
 190   const int cond_not_taken_branch_cost;  /* Cost of not taken branch.  */
 191 };
 192
 193 /* Branch costs.  */
 194 struct cpu_branch_cost
 195 {
 196   const int predictable;    /* Predictable branch or optimizing for size.  */
 197   const int unpredictable;  /* Unpredictable branch or optimizing for speed.  */
 198 };
 199
 200 /* Control approximate alternatives to certain FP operators.  */
 201 #define AARCH64_APPROX_MODE(MODE) \
 202   ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \
 203    ? (1 << ((MODE) - MIN_MODE_FLOAT)) \
 204    : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \
 205      ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \
 206               + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \
 207      : (0))
 208 #define AARCH64_APPROX_NONE (0)
 209 #define AARCH64_APPROX_ALL (-1)
 210
 211 /* Allowed modes for approximations.  */
 212 struct cpu_approx_modes
 213 {
 214   const unsigned int division;          /* Division.  */
 215   const unsigned int sqrt;              /* Square root.  */
 216   const unsigned int recip_sqrt;        /* Reciprocal square root.  */
 217 };
 218
 219 /* Cache prefetch settings for prefetch-loop-arrays.  */
 220 struct cpu_prefetch_tune
 221 {
 222   const int num_slots;
 223   const int l1_cache_size;
 224   const int l1_cache_line_size;
 225   const int l2_cache_size;
 226   const int default_opt_level;
 227 };
 228
 229 struct tune_params
 230 {
 231   const struct cpu_cost_table *insn_extra_cost;
 232   const struct cpu_addrcost_table *addr_cost;
 233   const struct cpu_regmove_cost *regmove_cost;
 234   const struct cpu_vector_cost *vec_costs;
 235   const struct cpu_branch_cost *branch_costs;
 236   const struct cpu_approx_modes *approx_modes;
 237   int memmov_cost;
 238   int issue_rate;
 239   unsigned int fusible_ops;
 240   int function_align;
 241   int jump_align;
 242   int loop_align;
 243   int int_reassoc_width;
 244   int fp_reassoc_width;
 245   int vec_reassoc_width;
 246   int min_div_recip_mul_sf;
 247   int min_div_recip_mul_df;
 248   /* Value for aarch64_case_values_threshold; or 0 for the default.  */
 249   unsigned int max_case_values;
 250 /* An enum specifying how to take into account CPU autoprefetch capabilities
 251    during instruction scheduling:
 252    - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account.
 253    - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of
 254    offsets but allow the pipeline hazard recognizer to alter that order to
 255    maximize multi-issue opportunities.
 256    - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of
 257    offsets and prefer this even if it restricts multi-issue opportunities.  */
 258
 259   enum aarch64_autoprefetch_model
 260   {
 261     AUTOPREFETCHER_OFF,
 262     AUTOPREFETCHER_WEAK,
 263     AUTOPREFETCHER_STRONG
 264   } autoprefetcher_model;
 265
 266   unsigned int extra_tuning_flags;
 267
 268   /* Place prefetch struct pointer at the end to enable type checking
 269      errors when tune_params misses elements (e.g., from erroneous merges).  */
 270   const struct cpu_prefetch_tune *prefetch;
 271 };
 272
 273 #define AARCH64_FUSION_PAIR(x, name) \
 274   AARCH64_FUSE_##name##_index,
 275 /* Supported fusion operations.  */
 276 enum aarch64_fusion_pairs_index
 277 {
 278 #include "aarch64-fusion-pairs.def"
 279   AARCH64_FUSE_index_END
 280 };
 281
 282 #define AARCH64_FUSION_PAIR(x, name) \
 283   AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index),
 284 /* Supported fusion operations.  */
 285 enum aarch64_fusion_pairs
 286 {
 287   AARCH64_FUSE_NOTHING = 0,
 288 #include "aarch64-fusion-pairs.def"
 289   AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1
 290 };
 291
 292 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
 293   AARCH64_EXTRA_TUNE_##name##_index,
 294 /* Supported tuning flags indexes.  */
 295 enum aarch64_extra_tuning_flags_index
 296 {
 297 #include "aarch64-tuning-flags.def"
 298   AARCH64_EXTRA_TUNE_index_END
 299 };
 300
 301
 302 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
 303   AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index),
 304 /* Supported tuning flags.  */
 305 enum aarch64_extra_tuning_flags
 306 {
 307   AARCH64_EXTRA_TUNE_NONE = 0,
 308 #include "aarch64-tuning-flags.def"
 309   AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1
 310 };
 311
 312 /* Enum describing the various ways that the
 313    aarch64_parse_{arch,tune,cpu,extension} functions can fail.
 314    This way their callers can choose what kind of error to give.  */
 315
 316 enum aarch64_parse_opt_result
 317 {
 318   AARCH64_PARSE_OK,                     /* Parsing was successful.  */
 319   AARCH64_PARSE_MISSING_ARG,            /* Missing argument.  */
 320   AARCH64_PARSE_INVALID_FEATURE,        /* Invalid feature modifier.  */
 321   AARCH64_PARSE_INVALID_ARG             /* Invalid arch, tune, cpu arg.  */
 322 };
 323
 324 /* Enum to distinguish which type of check is to be done in
 325    aarch64_simd_valid_immediate.  This is used as a bitmask where
 326    AARCH64_CHECK_MOV has both bits set.  Thus AARCH64_CHECK_MOV will
 327    perform all checks.  Adding new types would require changes accordingly.  */
 328 enum simd_immediate_check {
 329   AARCH64_CHECK_ORR  = 1 << 0,
 330   AARCH64_CHECK_BIC  = 1 << 1,
 331   AARCH64_CHECK_MOV  = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
 332 };
 333
 334 extern struct tune_params aarch64_tune_params;
 335
 336 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
 337 int aarch64_get_condition_code (rtx);
 338 bool aarch64_address_valid_for_prefetch_p (rtx, bool);
 339 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
 340 unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in);
 341 unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in);
 342 bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode mode);
 343 int aarch64_branch_cost (bool, bool);
 344 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
 345 bool aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode);
 346 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
 347 bool aarch64_constant_address_p (rtx);
 348 bool aarch64_emit_approx_div (rtx, rtx, rtx);
 349 bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
 350 void aarch64_expand_call (rtx, rtx, bool);
 351 bool aarch64_expand_movmem (rtx *);
 352 bool aarch64_float_const_zero_rtx_p (rtx);
 353 bool aarch64_float_const_rtx_p (rtx);
 354 bool aarch64_function_arg_regno_p (unsigned);
 355 bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs);
 356 bool aarch64_gen_movmemqi (rtx *);
 357 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *);
 358 bool aarch64_is_extend_from_extract (scalar_int_mode, rtx, rtx);
 359 bool aarch64_is_long_call_p (rtx);
 360 bool aarch64_is_noplt_call_p (rtx);
 361 bool aarch64_label_mentioned_p (rtx);
 362 void aarch64_declare_function_name (FILE *, const char*, tree);
 363 bool aarch64_legitimate_pic_operand_p (rtx);
 364 bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx);
 365 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
 366 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
 367 bool aarch64_mov_operand_p (rtx, machine_mode);
 368 rtx aarch64_reverse_mask (machine_mode, unsigned int);
 369 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT);
 370 char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
 371 char *aarch64_output_simd_mov_immediate (rtx, unsigned,
 372                         enum simd_immediate_check w = AARCH64_CHECK_MOV);
 373 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
 374 bool aarch64_regno_ok_for_base_p (int, bool);
 375 bool aarch64_regno_ok_for_index_p (int, bool);
 376 bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail);
 377 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
 378                                             bool high);
 379 bool aarch64_simd_imm_zero_p (rtx, machine_mode);
 380 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode);
 381 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
 382 bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
 383                         enum simd_immediate_check w = AARCH64_CHECK_MOV);
 384 bool aarch64_split_dimode_const_store (rtx, rtx);
 385 bool aarch64_symbolic_address_p (rtx);
 386 bool aarch64_uimm12_shift (HOST_WIDE_INT);
 387 bool aarch64_use_return_insn_p (void);
 388 const char *aarch64_mangle_builtin_type (const_tree);
 389 const char *aarch64_output_casesi (rtx *);
 390
 391 enum aarch64_symbol_type aarch64_classify_symbol (rtx, rtx);
 392 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
 393 enum reg_class aarch64_regno_regclass (unsigned);
 394 int aarch64_asm_preferred_eh_data_format (int, int);
 395 int aarch64_fpconst_pow_of_2 (rtx);
 396 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
 397                                                        machine_mode);
 398 int aarch64_uxt_size (int, HOST_WIDE_INT);
 399 int aarch64_vec_fpconst_pow_of_2 (rtx);
 400 rtx aarch64_eh_return_handler_rtx (void);
 401 rtx aarch64_mask_from_zextract_ops (rtx, rtx);
 402 const char *aarch64_output_move_struct (rtx *operands);
 403 rtx aarch64_return_addr (int, rtx);
 404 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
 405 bool aarch64_simd_mem_operand_p (rtx);
 406 rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool);
 407 rtx aarch64_tls_get_addr (void);
 408 tree aarch64_fold_builtin (tree, int, tree *, bool);
 409 unsigned aarch64_dbx_register_number (unsigned);
 410 unsigned aarch64_trampoline_size (void);
 411 void aarch64_asm_output_labelref (FILE *, const char *);
 412 void aarch64_cpu_cpp_builtins (cpp_reader *);
 413 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
 414 const char * aarch64_output_probe_stack_range (rtx, rtx);
 415 void aarch64_err_no_fpadvsimd (machine_mode, const char *);
 416 void aarch64_expand_epilogue (bool);
 417 void aarch64_expand_mov_immediate (rtx, rtx);
 418 void aarch64_expand_prologue (void);
 419 void aarch64_expand_vector_init (rtx, rtx);
 420 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
 421                                    const_tree, unsigned);
 422 void aarch64_init_expanders (void);
 423 void aarch64_init_simd_builtins (void);
 424 void aarch64_emit_call_insn (rtx);
 425 void aarch64_register_pragmas (void);
 426 void aarch64_relayout_simd_types (void);
 427 void aarch64_reset_previous_fndecl (void);
 428 bool aarch64_return_address_signing_enabled (void);
 429 void aarch64_save_restore_target_globals (tree);
 430
 431 /* Initialize builtins for SIMD intrinsics.  */
 432 void init_aarch64_simd_builtins (void);
 433
 434 void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int);
 435
 436 /* Expand builtins for SIMD intrinsics.  */
 437 rtx aarch64_simd_expand_builtin (int, tree, rtx);
 438
 439 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
 440 rtx aarch64_endian_lane_rtx (machine_mode, unsigned int);
 441
 442 void aarch64_split_128bit_move (rtx, rtx);
 443
 444 bool aarch64_split_128bit_move_p (rtx, rtx);
 445
 446 void aarch64_split_simd_combine (rtx, rtx, rtx);
 447
 448 void aarch64_split_simd_move (rtx, rtx);
 449
 450 /* Check for a legitimate floating point constant for FMOV.  */
 451 bool aarch64_float_const_representable_p (rtx);
 452
 453 #if defined (RTX_CODE)
 454
 455 bool aarch64_legitimate_address_p (machine_mode, rtx, bool,
 456                                    aarch64_addr_query_type = ADDR_QUERY_M);
 457 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx);
 458 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx);
 459 rtx aarch64_load_tp (rtx);
 460
 461 void aarch64_expand_compare_and_swap (rtx op[]);
 462 void aarch64_split_compare_and_swap (rtx op[]);
 463 void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
 464
 465 bool aarch64_atomic_ldop_supported_p (enum rtx_code);
 466 void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
 467 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 468
 469 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE);
 470 #endif /* RTX_CODE */
 471
 472 void aarch64_init_builtins (void);
 473
 474 bool aarch64_process_target_attr (tree);
 475 void aarch64_override_options_internal (struct gcc_options *);
 476
 477 rtx aarch64_expand_builtin (tree exp,
 478                             rtx target,
 479                             rtx subtarget ATTRIBUTE_UNUSED,
 480                             machine_mode mode ATTRIBUTE_UNUSED,
 481                             int ignore ATTRIBUTE_UNUSED);
 482 tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED);
 483 tree aarch64_builtin_rsqrt (unsigned int);
 484 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree);
 485
 486 extern void aarch64_split_combinev16qi (rtx operands[3]);
 487 extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int);
 488 extern bool aarch64_madd_needs_nop (rtx_insn *);
 489 extern void aarch64_final_prescan_insn (rtx_insn *);
 490 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
 491 int aarch64_ccmp_mode_to_code (machine_mode mode);
 492
 493 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
 494 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);
 495 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);
 496
 497 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
 498                                               tree, HOST_WIDE_INT);
 499
 500 /* Defined in common/config/aarch64-common.c.  */
 501 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *,
 502                              const struct cl_decoded_option *, location_t);
 503 const char *aarch64_rewrite_selected_cpu (const char *name);
 504 enum aarch64_parse_opt_result aarch64_parse_extension (const char *,
 505                                                        unsigned long *);
 506 std::string aarch64_get_extension_string_for_isa_flags (unsigned long,
 507                                                         unsigned long);
 508
 509 rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt);
 510
 511 #endif /* GCC_AARCH64_PROTOS_H */