1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "hard-reg-set.h"
36 #include "basic-block.h"
40 #ifndef STACK_PUSH_CODE
41 #ifdef STACK_GROWS_DOWNWARD
42 #define STACK_PUSH_CODE PRE_DEC
44 #define STACK_PUSH_CODE PRE_INC
48 #ifndef STACK_POP_CODE
49 #ifdef STACK_GROWS_DOWNWARD
50 #define STACK_POP_CODE POST_INC
52 #define STACK_POP_CODE POST_DEC
56 static void validate_replace_rtx_1
PARAMS ((rtx
*, rtx
, rtx
, rtx
));
57 static rtx
*find_single_use_1
PARAMS ((rtx
, rtx
*));
58 static rtx
*find_constant_term_loc
PARAMS ((rtx
*));
59 static void validate_replace_src_1
PARAMS ((rtx
*, void *));
61 /* Nonzero means allow operands to be volatile.
62 This should be 0 if you are generating rtl, such as if you are calling
63 the functions in optabs.c and expmed.c (most of the time).
64 This should be 1 if all valid insns need to be recognized,
65 such as in regclass.c and final.c and reload.c.
67 init_recog and init_recog_no_volatile are responsible for setting this. */
71 struct recog_data recog_data
;
73 /* Contains a vector of operand_alternative structures for every operand.
74 Set up by preprocess_constraints. */
75 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
77 /* On return from `constrain_operands', indicate which alternative
80 int which_alternative
;
82 /* Nonzero after end of reload pass.
83 Set to 1 or 0 by toplev.c.
84 Controls the significance of (SUBREG (MEM)). */
88 /* Initialize data used by the function `recog'.
89 This must be called once in the compilation of a function
90 before any insn recognition may be done in the function. */
93 init_recog_no_volatile ()
104 /* Try recognizing the instruction INSN,
105 and return the code number that results.
106 Remember the code so that repeated calls do not
107 need to spend the time for actual rerecognition.
109 This function is the normal interface to instruction recognition.
110 The automatically-generated function `recog' is normally called
111 through this one. (The only exception is in combine.c.) */
114 recog_memoized_1 (insn
)
117 if (INSN_CODE (insn
) < 0)
118 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, 0);
119 return INSN_CODE (insn
);
122 /* Check that X is an insn-body for an `asm' with operands
123 and that the operands mentioned in it are legitimate. */
126 check_asm_operands (x
)
131 const char **constraints
;
134 /* Post-reload, be more strict with things. */
135 if (reload_completed
)
137 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
138 extract_insn (make_insn_raw (x
));
139 constrain_operands (1);
140 return which_alternative
>= 0;
143 noperands
= asm_noperands (x
);
149 operands
= (rtx
*) alloca (noperands
* sizeof (rtx
));
150 constraints
= (const char **) alloca (noperands
* sizeof (char *));
152 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
);
154 for (i
= 0; i
< noperands
; i
++)
156 const char *c
= constraints
[i
];
159 if (ISDIGIT ((unsigned char)c
[0]) && c
[1] == '\0')
160 c
= constraints
[c
[0] - '0'];
162 if (! asm_operand_ok (operands
[i
], c
))
169 /* Static data for the next two routines. */
171 typedef struct change_t
179 static change_t
*changes
;
180 static int changes_allocated
;
182 static int num_changes
= 0;
184 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
185 at which NEW will be placed. If OBJECT is zero, no validation is done,
186 the change is simply made.
188 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
189 will be called with the address and mode as parameters. If OBJECT is
190 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
193 IN_GROUP is non-zero if this is part of a group of changes that must be
194 performed as a group. In that case, the changes will be stored. The
195 function `apply_change_group' will validate and apply the changes.
197 If IN_GROUP is zero, this is a single change. Try to recognize the insn
198 or validate the memory reference with the change applied. If the result
199 is not valid for the machine, suppress the change and return zero.
200 Otherwise, perform the change and return 1. */
203 validate_change (object
, loc
, new, in_group
)
211 if (old
== new || rtx_equal_p (old
, new))
214 if (in_group
== 0 && num_changes
!= 0)
219 /* Save the information describing this change. */
220 if (num_changes
>= changes_allocated
)
222 if (changes_allocated
== 0)
223 /* This value allows for repeated substitutions inside complex
224 indexed addresses, or changes in up to 5 insns. */
225 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
227 changes_allocated
*= 2;
230 (change_t
*) xrealloc (changes
,
231 sizeof (change_t
) * changes_allocated
);
234 changes
[num_changes
].object
= object
;
235 changes
[num_changes
].loc
= loc
;
236 changes
[num_changes
].old
= old
;
238 if (object
&& GET_CODE (object
) != MEM
)
240 /* Set INSN_CODE to force rerecognition of insn. Save old code in
242 changes
[num_changes
].old_code
= INSN_CODE (object
);
243 INSN_CODE (object
) = -1;
248 /* If we are making a group of changes, return 1. Otherwise, validate the
249 change group we made. */
254 return apply_change_group ();
257 /* This subroutine of apply_change_group verifies whether the changes to INSN
258 were valid; i.e. whether INSN can still be recognized. */
261 insn_invalid_p (insn
)
264 rtx pat
= PATTERN (insn
);
265 int num_clobbers
= 0;
266 /* If we are before reload and the pattern is a SET, see if we can add
268 int icode
= recog (pat
, insn
,
269 (GET_CODE (pat
) == SET
270 && ! reload_completed
&& ! reload_in_progress
)
271 ? &num_clobbers
: 0);
272 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
275 /* If this is an asm and the operand aren't legal, then fail. Likewise if
276 this is not an asm and the insn wasn't recognized. */
277 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
278 || (!is_asm
&& icode
< 0))
281 /* If we have to add CLOBBERs, fail if we have to add ones that reference
282 hard registers since our callers can't know if they are live or not.
283 Otherwise, add them. */
284 if (num_clobbers
> 0)
288 if (added_clobbers_hard_reg_p (icode
))
291 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
292 XVECEXP (newpat
, 0, 0) = pat
;
293 add_clobbers (newpat
, icode
);
294 PATTERN (insn
) = pat
= newpat
;
297 /* After reload, verify that all constraints are satisfied. */
298 if (reload_completed
)
302 if (! constrain_operands (1))
306 INSN_CODE (insn
) = icode
;
310 /* Apply a group of changes previously issued with `validate_change'.
311 Return 1 if all changes are valid, zero otherwise. */
314 apply_change_group ()
317 rtx last_validated
= NULL_RTX
;
319 /* The changes have been applied and all INSN_CODEs have been reset to force
322 The changes are valid if we aren't given an object, or if we are
323 given a MEM and it still is a valid address, or if this is in insn
324 and it is recognized. In the latter case, if reload has completed,
325 we also require that the operands meet the constraints for
328 for (i
= 0; i
< num_changes
; i
++)
330 rtx object
= changes
[i
].object
;
332 /* if there is no object to test or if it is the same as the one we
333 already tested, ignore it. */
334 if (object
== 0 || object
== last_validated
)
337 if (GET_CODE (object
) == MEM
)
339 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
342 else if (insn_invalid_p (object
))
344 rtx pat
= PATTERN (object
);
346 /* Perhaps we couldn't recognize the insn because there were
347 extra CLOBBERs at the end. If so, try to re-recognize
348 without the last CLOBBER (later iterations will cause each of
349 them to be eliminated, in turn). But don't do this if we
350 have an ASM_OPERAND. */
351 if (GET_CODE (pat
) == PARALLEL
352 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
353 && asm_noperands (PATTERN (object
)) < 0)
357 if (XVECLEN (pat
, 0) == 2)
358 newpat
= XVECEXP (pat
, 0, 0);
364 = gen_rtx_PARALLEL (VOIDmode
,
365 rtvec_alloc (XVECLEN (pat
, 0) - 1));
366 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
367 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
370 /* Add a new change to this group to replace the pattern
371 with this new pattern. Then consider this change
372 as having succeeded. The change we added will
373 cause the entire call to fail if things remain invalid.
375 Note that this can lose if a later change than the one
376 we are processing specified &XVECEXP (PATTERN (object), 0, X)
377 but this shouldn't occur. */
379 validate_change (object
, &PATTERN (object
), newpat
, 1);
382 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
383 /* If this insn is a CLOBBER or USE, it is always valid, but is
389 last_validated
= object
;
392 if (i
== num_changes
)
404 /* Return the number of changes so far in the current group. */
407 num_validated_changes ()
412 /* Retract the changes numbered NUM and up. */
420 /* Back out all the changes. Do this in the opposite order in which
422 for (i
= num_changes
- 1; i
>= num
; i
--)
424 *changes
[i
].loc
= changes
[i
].old
;
425 if (changes
[i
].object
&& GET_CODE (changes
[i
].object
) != MEM
)
426 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
431 /* Replace every occurrence of FROM in X with TO. Mark each change with
432 validate_change passing OBJECT. */
435 validate_replace_rtx_1 (loc
, from
, to
, object
)
437 rtx from
, to
, object
;
440 register const char *fmt
;
441 register rtx x
= *loc
;
443 enum machine_mode op0_mode
= VOIDmode
;
444 int prev_changes
= num_changes
;
451 fmt
= GET_RTX_FORMAT (code
);
453 op0_mode
= GET_MODE (XEXP (x
, 0));
455 /* X matches FROM if it is the same rtx or they are both referring to the
456 same register in the same mode. Avoid calling rtx_equal_p unless the
457 operands look similar. */
460 || (GET_CODE (x
) == REG
&& GET_CODE (from
) == REG
461 && GET_MODE (x
) == GET_MODE (from
)
462 && REGNO (x
) == REGNO (from
))
463 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
464 && rtx_equal_p (x
, from
)))
466 validate_change (object
, loc
, to
, 1);
470 /* Call ourseves recursivly to perform the replacements. */
472 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
475 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
476 else if (fmt
[i
] == 'E')
477 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
478 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
481 /* In case we didn't substituted, there is nothing to do. */
482 if (num_changes
== prev_changes
)
485 /* Allow substituted expression to have different mode. This is used by
486 regmove to change mode of pseudo register. */
487 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
488 op0_mode
= GET_MODE (XEXP (x
, 0));
490 /* Do changes needed to keep rtx consistent. Don't do any other
491 simplifications, as it is not our job. */
493 if ((GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
494 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
496 validate_change (object
, loc
,
497 gen_rtx_fmt_ee (GET_RTX_CLASS (code
) == 'c' ? code
498 : swap_condition (code
),
499 GET_MODE (x
), XEXP (x
, 1),
508 /* If we have a PLUS whose second operand is now a CONST_INT, use
509 plus_constant to try to simplify it.
510 ??? We may want later to remove this, once simplification is
511 separated from this function. */
512 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& XEXP (x
, 1) == to
)
513 validate_change (object
, loc
,
514 plus_constant (XEXP (x
, 0), INTVAL (to
)), 1);
517 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
518 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
519 validate_change (object
, loc
,
521 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
522 simplify_gen_unary (NEG
,
523 op0_mode
, XEXP (x
, 1),
528 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
530 new = simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
532 /* If any of the above failed, substitute in something that
533 we know won't be recognized. */
535 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
536 validate_change (object
, loc
, new, 1);
540 /* All subregs possible to simplify should be simplified. */
541 new = simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
544 /* Subregs of VOIDmode operands are incorect. */
545 if (!new && GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
546 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
548 validate_change (object
, loc
, new, 1);
552 /* If we are replacing a register with memory, try to change the memory
553 to be the mode required for memory in extract operations (this isn't
554 likely to be an insertion operation; if it was, nothing bad will
555 happen, we might just fail in some cases). */
557 if (GET_CODE (XEXP (x
, 0)) == MEM
558 && GET_CODE (XEXP (x
, 1)) == CONST_INT
559 && GET_CODE (XEXP (x
, 2)) == CONST_INT
560 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
561 && !MEM_VOLATILE_P (XEXP (x
, 0)))
563 enum machine_mode wanted_mode
= VOIDmode
;
564 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
565 int pos
= INTVAL (XEXP (x
, 2));
568 if (code
== ZERO_EXTRACT
)
570 wanted_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
571 if (wanted_mode
== VOIDmode
)
572 wanted_mode
= word_mode
;
576 if (code
== SIGN_EXTRACT
)
578 wanted_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
579 if (wanted_mode
== VOIDmode
)
580 wanted_mode
= word_mode
;
584 /* If we have a narrower mode, we can do something. */
585 if (wanted_mode
!= VOIDmode
586 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
588 int offset
= pos
/ BITS_PER_UNIT
;
591 /* If the bytes and bits are counted differently, we
592 must adjust the offset. */
593 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
595 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
598 pos
%= GET_MODE_BITSIZE (wanted_mode
);
600 newmem
= gen_rtx_MEM (wanted_mode
,
601 plus_constant (XEXP (XEXP (x
, 0), 0),
603 MEM_COPY_ATTRIBUTES (newmem
, XEXP (x
, 0));
605 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
606 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
617 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
618 with TO. After all changes have been made, validate by seeing
619 if INSN is still valid. */
622 validate_replace_rtx_subexp (from
, to
, insn
, loc
)
623 rtx from
, to
, insn
, *loc
;
625 validate_replace_rtx_1 (loc
, from
, to
, insn
);
626 return apply_change_group ();
629 /* Try replacing every occurrence of FROM in INSN with TO. After all
630 changes have been made, validate by seeing if INSN is still valid. */
633 validate_replace_rtx (from
, to
, insn
)
636 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
637 return apply_change_group ();
640 /* Try replacing every occurrence of FROM in INSN with TO. */
643 validate_replace_rtx_group (from
, to
, insn
)
646 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
649 /* Function called by note_uses to replace used subexpressions. */
650 struct validate_replace_src_data
652 rtx from
; /* Old RTX */
653 rtx to
; /* New RTX */
654 rtx insn
; /* Insn in which substitution is occurring. */
658 validate_replace_src_1 (x
, data
)
662 struct validate_replace_src_data
*d
663 = (struct validate_replace_src_data
*) data
;
665 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
);
668 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
669 SET_DESTs. After all changes have been made, validate by seeing if
670 INSN is still valid. */
673 validate_replace_src (from
, to
, insn
)
676 struct validate_replace_src_data d
;
681 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
682 return apply_change_group ();
686 /* Return 1 if the insn using CC0 set by INSN does not contain
687 any ordered tests applied to the condition codes.
688 EQ and NE tests do not count. */
691 next_insn_tests_no_inequality (insn
)
694 register rtx next
= next_cc0_user (insn
);
696 /* If there is no next insn, we have to take the conservative choice. */
700 return ((GET_CODE (next
) == JUMP_INSN
701 || GET_CODE (next
) == INSN
702 || GET_CODE (next
) == CALL_INSN
)
703 && ! inequality_comparisons_p (PATTERN (next
)));
706 #if 0 /* This is useless since the insn that sets the cc's
707 must be followed immediately by the use of them. */
708 /* Return 1 if the CC value set up by INSN is not used. */
711 next_insns_test_no_inequality (insn
)
714 register rtx next
= NEXT_INSN (insn
);
716 for (; next
!= 0; next
= NEXT_INSN (next
))
718 if (GET_CODE (next
) == CODE_LABEL
719 || GET_CODE (next
) == BARRIER
)
721 if (GET_CODE (next
) == NOTE
)
723 if (inequality_comparisons_p (PATTERN (next
)))
725 if (sets_cc0_p (PATTERN (next
)) == 1)
727 if (! reg_mentioned_p (cc0_rtx
, PATTERN (next
)))
735 /* This is used by find_single_use to locate an rtx that contains exactly one
736 use of DEST, which is typically either a REG or CC0. It returns a
737 pointer to the innermost rtx expression containing DEST. Appearances of
738 DEST that are being used to totally replace it are not counted. */
741 find_single_use_1 (dest
, loc
)
746 enum rtx_code code
= GET_CODE (x
);
763 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
764 of a REG that occupies all of the REG, the insn uses DEST if
765 it is mentioned in the destination or the source. Otherwise, we
766 need just check the source. */
767 if (GET_CODE (SET_DEST (x
)) != CC0
768 && GET_CODE (SET_DEST (x
)) != PC
769 && GET_CODE (SET_DEST (x
)) != REG
770 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
771 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
772 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
773 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
774 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
775 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
778 return find_single_use_1 (dest
, &SET_SRC (x
));
782 return find_single_use_1 (dest
, &XEXP (x
, 0));
788 /* If it wasn't one of the common cases above, check each expression and
789 vector of this code. Look for a unique usage of DEST. */
791 fmt
= GET_RTX_FORMAT (code
);
792 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
796 if (dest
== XEXP (x
, i
)
797 || (GET_CODE (dest
) == REG
&& GET_CODE (XEXP (x
, i
)) == REG
798 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
801 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
804 result
= this_result
;
805 else if (this_result
)
806 /* Duplicate usage. */
809 else if (fmt
[i
] == 'E')
813 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
815 if (XVECEXP (x
, i
, j
) == dest
816 || (GET_CODE (dest
) == REG
817 && GET_CODE (XVECEXP (x
, i
, j
)) == REG
818 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
821 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
824 result
= this_result
;
825 else if (this_result
)
834 /* See if DEST, produced in INSN, is used only a single time in the
835 sequel. If so, return a pointer to the innermost rtx expression in which
838 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
840 This routine will return usually zero either before flow is called (because
841 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
842 note can't be trusted).
844 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
845 care about REG_DEAD notes or LOG_LINKS.
847 Otherwise, we find the single use by finding an insn that has a
848 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
849 only referenced once in that insn, we know that it must be the first
850 and last insn referencing DEST. */
853 find_single_use (dest
, insn
, ploc
)
865 next
= NEXT_INSN (insn
);
867 || (GET_CODE (next
) != INSN
&& GET_CODE (next
) != JUMP_INSN
))
870 result
= find_single_use_1 (dest
, &PATTERN (next
));
877 if (reload_completed
|| reload_in_progress
|| GET_CODE (dest
) != REG
)
880 for (next
= next_nonnote_insn (insn
);
881 next
!= 0 && GET_CODE (next
) != CODE_LABEL
;
882 next
= next_nonnote_insn (next
))
883 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
885 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
886 if (XEXP (link
, 0) == insn
)
891 result
= find_single_use_1 (dest
, &PATTERN (next
));
901 /* Return 1 if OP is a valid general operand for machine mode MODE.
902 This is either a register reference, a memory reference,
903 or a constant. In the case of a memory reference, the address
904 is checked for general validity for the target machine.
906 Register and memory references must have mode MODE in order to be valid,
907 but some constants have no machine mode and are valid for any mode.
909 If MODE is VOIDmode, OP is checked for validity for whatever mode
912 The main use of this function is as a predicate in match_operand
913 expressions in the machine description.
915 For an explanation of this function's behavior for registers of
916 class NO_REGS, see the comment for `register_operand'. */
919 general_operand (op
, mode
)
921 enum machine_mode mode
;
923 register enum rtx_code code
= GET_CODE (op
);
925 if (mode
== VOIDmode
)
926 mode
= GET_MODE (op
);
928 /* Don't accept CONST_INT or anything similar
929 if the caller wants something floating. */
930 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
931 && GET_MODE_CLASS (mode
) != MODE_INT
932 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
935 if (GET_CODE (op
) == CONST_INT
936 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
940 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
942 #ifdef LEGITIMATE_PIC_OPERAND_P
943 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
945 && LEGITIMATE_CONSTANT_P (op
));
947 /* Except for certain constants with VOIDmode, already checked for,
948 OP's mode must match MODE if MODE specifies a mode. */
950 if (GET_MODE (op
) != mode
)
955 #ifdef INSN_SCHEDULING
956 /* On machines that have insn scheduling, we want all memory
957 reference to be explicit, so outlaw paradoxical SUBREGs. */
958 if (GET_CODE (SUBREG_REG (op
)) == MEM
959 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
962 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
963 may result in incorrect reference. We should simplify all valid
964 subregs of MEM anyway. But allow this after reload because we
965 might be called from cleanup_subreg_operands.
967 ??? This is a kludge. */
968 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
969 && GET_CODE (SUBREG_REG (op
)) == MEM
)
972 op
= SUBREG_REG (op
);
973 code
= GET_CODE (op
);
977 /* A register whose class is NO_REGS is not a general operand. */
978 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
979 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
983 register rtx y
= XEXP (op
, 0);
985 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
988 if (GET_CODE (y
) == ADDRESSOF
)
991 /* Use the mem's mode, since it will be reloaded thus. */
992 mode
= GET_MODE (op
);
993 GO_IF_LEGITIMATE_ADDRESS (mode
, y
, win
);
996 /* Pretend this is an operand for now; we'll run force_operand
997 on its replacement in fixup_var_refs_1. */
998 if (code
== ADDRESSOF
)
1007 /* Return 1 if OP is a valid memory address for a memory reference
1010 The main use of this function is as a predicate in match_operand
1011 expressions in the machine description. */
1014 address_operand (op
, mode
)
1016 enum machine_mode mode
;
1018 return memory_address_p (mode
, op
);
1021 /* Return 1 if OP is a register reference of mode MODE.
1022 If MODE is VOIDmode, accept a register in any mode.
1024 The main use of this function is as a predicate in match_operand
1025 expressions in the machine description.
1027 As a special exception, registers whose class is NO_REGS are
1028 not accepted by `register_operand'. The reason for this change
1029 is to allow the representation of special architecture artifacts
1030 (such as a condition code register) without extending the rtl
1031 definitions. Since registers of class NO_REGS cannot be used
1032 as registers in any case where register classes are examined,
1033 it is most consistent to keep this function from accepting them. */
1036 register_operand (op
, mode
)
1038 enum machine_mode mode
;
1040 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1043 if (GET_CODE (op
) == SUBREG
)
1045 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1046 because it is guaranteed to be reloaded into one.
1047 Just make sure the MEM is valid in itself.
1048 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1049 but currently it does result from (SUBREG (REG)...) where the
1050 reg went on the stack.) */
1051 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1052 return general_operand (op
, mode
);
1054 #ifdef CLASS_CANNOT_CHANGE_MODE
1055 if (GET_CODE (SUBREG_REG (op
)) == REG
1056 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
1057 && (TEST_HARD_REG_BIT
1058 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
1059 REGNO (SUBREG_REG (op
))))
1060 && CLASS_CANNOT_CHANGE_MODE_P (mode
, GET_MODE (SUBREG_REG (op
)))
1061 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_INT
1062 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_FLOAT
)
1066 op
= SUBREG_REG (op
);
1069 /* If we have an ADDRESSOF, consider it valid since it will be
1070 converted into something that will not be a MEM. */
1071 if (GET_CODE (op
) == ADDRESSOF
)
1074 /* We don't consider registers whose class is NO_REGS
1075 to be a register operand. */
1076 return (GET_CODE (op
) == REG
1077 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1078 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1081 /* Return 1 for a register in Pmode; ignore the tested mode. */
1084 pmode_register_operand (op
, mode
)
1086 enum machine_mode mode ATTRIBUTE_UNUSED
;
1088 return register_operand (op
, Pmode
);
1091 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1092 or a hard register. */
1095 scratch_operand (op
, mode
)
1097 enum machine_mode mode
;
1099 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1102 return (GET_CODE (op
) == SCRATCH
1103 || (GET_CODE (op
) == REG
1104 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1107 /* Return 1 if OP is a valid immediate operand for mode MODE.
1109 The main use of this function is as a predicate in match_operand
1110 expressions in the machine description. */
1113 immediate_operand (op
, mode
)
1115 enum machine_mode mode
;
1117 /* Don't accept CONST_INT or anything similar
1118 if the caller wants something floating. */
1119 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1120 && GET_MODE_CLASS (mode
) != MODE_INT
1121 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1124 if (GET_CODE (op
) == CONST_INT
1125 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1128 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1129 result in 0/1. It seems a safe assumption that this is
1130 in range for everyone. */
1131 if (GET_CODE (op
) == CONSTANT_P_RTX
)
1134 return (CONSTANT_P (op
)
1135 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1136 || GET_MODE (op
) == VOIDmode
)
1137 #ifdef LEGITIMATE_PIC_OPERAND_P
1138 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1140 && LEGITIMATE_CONSTANT_P (op
));
1143 /* Returns 1 if OP is an operand that is a CONST_INT. */
1146 const_int_operand (op
, mode
)
1148 enum machine_mode mode
;
1150 if (GET_CODE (op
) != CONST_INT
)
1153 if (mode
!= VOIDmode
1154 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1160 /* Returns 1 if OP is an operand that is a constant integer or constant
1161 floating-point number. */
1164 const_double_operand (op
, mode
)
1166 enum machine_mode mode
;
1168 /* Don't accept CONST_INT or anything similar
1169 if the caller wants something floating. */
1170 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1171 && GET_MODE_CLASS (mode
) != MODE_INT
1172 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1175 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
1176 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1177 || GET_MODE (op
) == VOIDmode
));
1180 /* Return 1 if OP is a general operand that is not an immediate operand. */
1183 nonimmediate_operand (op
, mode
)
1185 enum machine_mode mode
;
1187 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1190 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1193 nonmemory_operand (op
, mode
)
1195 enum machine_mode mode
;
1197 if (CONSTANT_P (op
))
1199 /* Don't accept CONST_INT or anything similar
1200 if the caller wants something floating. */
1201 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1202 && GET_MODE_CLASS (mode
) != MODE_INT
1203 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1206 if (GET_CODE (op
) == CONST_INT
1207 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1210 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1211 || mode
== VOIDmode
)
1212 #ifdef LEGITIMATE_PIC_OPERAND_P
1213 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1215 && LEGITIMATE_CONSTANT_P (op
));
1218 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1221 if (GET_CODE (op
) == SUBREG
)
1223 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1224 because it is guaranteed to be reloaded into one.
1225 Just make sure the MEM is valid in itself.
1226 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1227 but currently it does result from (SUBREG (REG)...) where the
1228 reg went on the stack.) */
1229 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1230 return general_operand (op
, mode
);
1231 op
= SUBREG_REG (op
);
1234 /* We don't consider registers whose class is NO_REGS
1235 to be a register operand. */
1236 return (GET_CODE (op
) == REG
1237 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1238 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1241 /* Return 1 if OP is a valid operand that stands for pushing a
1242 value of mode MODE onto the stack.
1244 The main use of this function is as a predicate in match_operand
1245 expressions in the machine description. */
1248 push_operand (op
, mode
)
1250 enum machine_mode mode
;
1252 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1254 #ifdef PUSH_ROUNDING
1255 rounded_size
= PUSH_ROUNDING (rounded_size
);
1258 if (GET_CODE (op
) != MEM
)
1261 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1266 if (rounded_size
== GET_MODE_SIZE (mode
))
1268 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1273 if (GET_CODE (op
) != PRE_MODIFY
1274 || GET_CODE (XEXP (op
, 1)) != PLUS
1275 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1276 || GET_CODE (XEXP (XEXP (op
, 1), 1)) != CONST_INT
1277 #ifdef STACK_GROWS_DOWNWARD
1278 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1280 || INTVAL (XEXP (XEXP (op
, 1), 1)) != rounded_size
1286 return XEXP (op
, 0) == stack_pointer_rtx
;
1289 /* Return 1 if OP is a valid operand that stands for popping a
1290 value of mode MODE off the stack.
1292 The main use of this function is as a predicate in match_operand
1293 expressions in the machine description. */
1296 pop_operand (op
, mode
)
1298 enum machine_mode mode
;
1300 if (GET_CODE (op
) != MEM
)
1303 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1308 if (GET_CODE (op
) != STACK_POP_CODE
)
1311 return XEXP (op
, 0) == stack_pointer_rtx
;
1314 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1317 memory_address_p (mode
, addr
)
1318 enum machine_mode mode ATTRIBUTE_UNUSED
;
1321 if (GET_CODE (addr
) == ADDRESSOF
)
1324 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1331 /* Return 1 if OP is a valid memory reference with mode MODE,
1332 including a valid address.
1334 The main use of this function is as a predicate in match_operand
1335 expressions in the machine description. */
1338 memory_operand (op
, mode
)
1340 enum machine_mode mode
;
1344 if (! reload_completed
)
1345 /* Note that no SUBREG is a memory operand before end of reload pass,
1346 because (SUBREG (MEM...)) forces reloading into a register. */
1347 return GET_CODE (op
) == MEM
&& general_operand (op
, mode
);
1349 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1353 if (GET_CODE (inner
) == SUBREG
)
1354 inner
= SUBREG_REG (inner
);
1356 return (GET_CODE (inner
) == MEM
&& general_operand (op
, mode
));
1359 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1360 that is, a memory reference whose address is a general_operand. */
1363 indirect_operand (op
, mode
)
1365 enum machine_mode mode
;
1367 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1368 if (! reload_completed
1369 && GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1371 register int offset
= SUBREG_BYTE (op
);
1372 rtx inner
= SUBREG_REG (op
);
1374 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1377 /* The only way that we can have a general_operand as the resulting
1378 address is if OFFSET is zero and the address already is an operand
1379 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1382 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1383 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1384 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1385 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1386 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1389 return (GET_CODE (op
) == MEM
1390 && memory_operand (op
, mode
)
1391 && general_operand (XEXP (op
, 0), Pmode
));
1394 /* Return 1 if this is a comparison operator. This allows the use of
1395 MATCH_OPERATOR to recognize all the branch insns. */
1398 comparison_operator (op
, mode
)
1400 enum machine_mode mode
;
1402 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1403 && GET_RTX_CLASS (GET_CODE (op
)) == '<');
1406 /* If BODY is an insn body that uses ASM_OPERANDS,
1407 return the number of operands (both input and output) in the insn.
1408 Otherwise return -1. */
1411 asm_noperands (body
)
1414 switch (GET_CODE (body
))
1417 /* No output operands: return number of input operands. */
1418 return ASM_OPERANDS_INPUT_LENGTH (body
);
1420 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1421 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1422 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1426 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
1427 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1429 /* Multiple output operands, or 1 output plus some clobbers:
1430 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1434 /* Count backwards through CLOBBERs to determine number of SETs. */
1435 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1437 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1439 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1443 /* N_SETS is now number of output operands. */
1446 /* Verify that all the SETs we have
1447 came from a single original asm_operands insn
1448 (so that invalid combinations are blocked). */
1449 for (i
= 0; i
< n_sets
; i
++)
1451 rtx elt
= XVECEXP (body
, 0, i
);
1452 if (GET_CODE (elt
) != SET
)
1454 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1456 /* If these ASM_OPERANDS rtx's came from different original insns
1457 then they aren't allowed together. */
1458 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1459 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1462 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1465 else if (GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1467 /* 0 outputs, but some clobbers:
1468 body is [(asm_operands ...) (clobber (reg ...))...]. */
1471 /* Make sure all the other parallel things really are clobbers. */
1472 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1473 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1476 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1485 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1486 copy its operands (both input and output) into the vector OPERANDS,
1487 the locations of the operands within the insn into the vector OPERAND_LOCS,
1488 and the constraints for the operands into CONSTRAINTS.
1489 Write the modes of the operands into MODES.
1490 Return the assembler-template.
1492 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1493 we don't store that info. */
1496 decode_asm_operands (body
, operands
, operand_locs
, constraints
, modes
)
1500 const char **constraints
;
1501 enum machine_mode
*modes
;
1505 const char *template = 0;
1507 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1509 rtx asmop
= SET_SRC (body
);
1510 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1512 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1514 for (i
= 1; i
< noperands
; i
++)
1517 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1519 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1521 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1523 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1526 /* The output is in the SET.
1527 Its constraint is in the ASM_OPERANDS itself. */
1529 operands
[0] = SET_DEST (body
);
1531 operand_locs
[0] = &SET_DEST (body
);
1533 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1535 modes
[0] = GET_MODE (SET_DEST (body
));
1536 template = ASM_OPERANDS_TEMPLATE (asmop
);
1538 else if (GET_CODE (body
) == ASM_OPERANDS
)
1541 /* No output operands: BODY is (asm_operands ....). */
1543 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1545 /* The input operands are found in the 1st element vector. */
1546 /* Constraints for inputs are in the 2nd element vector. */
1547 for (i
= 0; i
< noperands
; i
++)
1550 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1552 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1554 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1556 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1558 template = ASM_OPERANDS_TEMPLATE (asmop
);
1560 else if (GET_CODE (body
) == PARALLEL
1561 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1563 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1564 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1565 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1566 int nout
= 0; /* Does not include CLOBBERs. */
1568 /* At least one output, plus some CLOBBERs. */
1570 /* The outputs are in the SETs.
1571 Their constraints are in the ASM_OPERANDS itself. */
1572 for (i
= 0; i
< nparallel
; i
++)
1574 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1575 break; /* Past last SET */
1578 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1580 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1582 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1584 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1588 for (i
= 0; i
< nin
; i
++)
1591 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1593 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1595 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1597 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1600 template = ASM_OPERANDS_TEMPLATE (asmop
);
1602 else if (GET_CODE (body
) == PARALLEL
1603 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1605 /* No outputs, but some CLOBBERs. */
1607 rtx asmop
= XVECEXP (body
, 0, 0);
1608 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1610 for (i
= 0; i
< nin
; i
++)
1613 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1615 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1617 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1619 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1622 template = ASM_OPERANDS_TEMPLATE (asmop
);
1628 /* Check if an asm_operand matches it's constraints.
1629 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1632 asm_operand_ok (op
, constraint
)
1634 const char *constraint
;
1638 /* Use constrain_operands after reload. */
1639 if (reload_completed
)
1644 char c
= *constraint
++;
1658 case '0': case '1': case '2': case '3': case '4':
1659 case '5': case '6': case '7': case '8': case '9':
1660 /* For best results, our caller should have given us the
1661 proper matching constraint, but we can't actually fail
1662 the check if they didn't. Indicate that results are
1668 if (address_operand (op
, VOIDmode
))
1673 case 'V': /* non-offsettable */
1674 if (memory_operand (op
, VOIDmode
))
1678 case 'o': /* offsettable */
1679 if (offsettable_nonstrict_memref_p (op
))
1684 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1685 excepting those that expand_call created. Further, on some
1686 machines which do not have generalized auto inc/dec, an inc/dec
1687 is not a memory_operand.
1689 Match any memory and hope things are resolved after reload. */
1691 if (GET_CODE (op
) == MEM
1693 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1694 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1699 if (GET_CODE (op
) == MEM
1701 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1702 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1707 #ifndef REAL_ARITHMETIC
1708 /* Match any floating double constant, but only if
1709 we can examine the bits of it reliably. */
1710 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1711 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1712 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1718 if (GET_CODE (op
) == CONST_DOUBLE
)
1723 if (GET_CODE (op
) == CONST_DOUBLE
1724 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'G'))
1728 if (GET_CODE (op
) == CONST_DOUBLE
1729 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'H'))
1734 if (GET_CODE (op
) == CONST_INT
1735 || (GET_CODE (op
) == CONST_DOUBLE
1736 && GET_MODE (op
) == VOIDmode
))
1742 #ifdef LEGITIMATE_PIC_OPERAND_P
1743 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1750 if (GET_CODE (op
) == CONST_INT
1751 || (GET_CODE (op
) == CONST_DOUBLE
1752 && GET_MODE (op
) == VOIDmode
))
1757 if (GET_CODE (op
) == CONST_INT
1758 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I'))
1762 if (GET_CODE (op
) == CONST_INT
1763 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'J'))
1767 if (GET_CODE (op
) == CONST_INT
1768 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K'))
1772 if (GET_CODE (op
) == CONST_INT
1773 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'))
1777 if (GET_CODE (op
) == CONST_INT
1778 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'M'))
1782 if (GET_CODE (op
) == CONST_INT
1783 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'N'))
1787 if (GET_CODE (op
) == CONST_INT
1788 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'))
1792 if (GET_CODE (op
) == CONST_INT
1793 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P'))
1801 if (general_operand (op
, VOIDmode
))
1806 /* For all other letters, we first check for a register class,
1807 otherwise it is an EXTRA_CONSTRAINT. */
1808 if (REG_CLASS_FROM_LETTER (c
) != NO_REGS
)
1811 if (GET_MODE (op
) == BLKmode
)
1813 if (register_operand (op
, VOIDmode
))
1816 #ifdef EXTRA_CONSTRAINT
1817 if (EXTRA_CONSTRAINT (op
, c
))
1827 /* Given an rtx *P, if it is a sum containing an integer constant term,
1828 return the location (type rtx *) of the pointer to that constant term.
1829 Otherwise, return a null pointer. */
1832 find_constant_term_loc (p
)
1836 register enum rtx_code code
= GET_CODE (*p
);
1838 /* If *P IS such a constant term, P is its location. */
1840 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1844 /* Otherwise, if not a sum, it has no constant term. */
1846 if (GET_CODE (*p
) != PLUS
)
1849 /* If one of the summands is constant, return its location. */
1851 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1852 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1855 /* Otherwise, check each summand for containing a constant term. */
1857 if (XEXP (*p
, 0) != 0)
1859 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1864 if (XEXP (*p
, 1) != 0)
1866 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1874 /* Return 1 if OP is a memory reference
1875 whose address contains no side effects
1876 and remains valid after the addition
1877 of a positive integer less than the
1878 size of the object being referenced.
1880 We assume that the original address is valid and do not check it.
1882 This uses strict_memory_address_p as a subroutine, so
1883 don't use it before reload. */
1886 offsettable_memref_p (op
)
1889 return ((GET_CODE (op
) == MEM
)
1890 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1893 /* Similar, but don't require a strictly valid mem ref:
1894 consider pseudo-regs valid as index or base regs. */
1897 offsettable_nonstrict_memref_p (op
)
1900 return ((GET_CODE (op
) == MEM
)
1901 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1904 /* Return 1 if Y is a memory address which contains no side effects
1905 and would remain valid after the addition of a positive integer
1906 less than the size of that mode.
1908 We assume that the original address is valid and do not check it.
1909 We do check that it is valid for narrower modes.
1911 If STRICTP is nonzero, we require a strictly valid address,
1912 for the sake of use in reload.c. */
1915 offsettable_address_p (strictp
, mode
, y
)
1917 enum machine_mode mode
;
1920 register enum rtx_code ycode
= GET_CODE (y
);
1924 int (*addressp
) PARAMS ((enum machine_mode
, rtx
)) =
1925 (strictp
? strict_memory_address_p
: memory_address_p
);
1926 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1928 if (CONSTANT_ADDRESS_P (y
))
1931 /* Adjusting an offsettable address involves changing to a narrower mode.
1932 Make sure that's OK. */
1934 if (mode_dependent_address_p (y
))
1937 /* ??? How much offset does an offsettable BLKmode reference need?
1938 Clearly that depends on the situation in which it's being used.
1939 However, the current situation in which we test 0xffffffff is
1940 less than ideal. Caveat user. */
1942 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1944 /* If the expression contains a constant term,
1945 see if it remains valid when max possible offset is added. */
1947 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1952 *y2
= plus_constant (*y2
, mode_sz
- 1);
1953 /* Use QImode because an odd displacement may be automatically invalid
1954 for any wider mode. But it should be valid for a single byte. */
1955 good
= (*addressp
) (QImode
, y
);
1957 /* In any case, restore old contents of memory. */
1962 if (GET_RTX_CLASS (ycode
) == 'a')
1965 /* The offset added here is chosen as the maximum offset that
1966 any instruction could need to add when operating on something
1967 of the specified mode. We assume that if Y and Y+c are
1968 valid addresses then so is Y+d for all 0<d<c. */
1970 z
= plus_constant_for_output (y
, mode_sz
- 1);
1972 /* Use QImode because an odd displacement may be automatically invalid
1973 for any wider mode. But it should be valid for a single byte. */
1974 return (*addressp
) (QImode
, z
);
1977 /* Return 1 if ADDR is an address-expression whose effect depends
1978 on the mode of the memory reference it is used in.
1980 Autoincrement addressing is a typical example of mode-dependence
1981 because the amount of the increment depends on the mode. */
1984 mode_dependent_address_p (addr
)
1985 rtx addr ATTRIBUTE_UNUSED
; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1987 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
1989 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1990 win
: ATTRIBUTE_UNUSED_LABEL
1994 /* Return 1 if OP is a general operand
1995 other than a memory ref with a mode dependent address. */
1998 mode_independent_operand (op
, mode
)
1999 enum machine_mode mode
;
2004 if (! general_operand (op
, mode
))
2007 if (GET_CODE (op
) != MEM
)
2010 addr
= XEXP (op
, 0);
2011 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, lose
);
2013 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2014 lose
: ATTRIBUTE_UNUSED_LABEL
2018 /* Given an operand OP that is a valid memory reference which
2019 satisfies offsettable_memref_p, return a new memory reference whose
2020 address has been adjusted by OFFSET. OFFSET should be positive and
2021 less than the size of the object referenced. */
2024 adj_offsettable_operand (op
, offset
)
2028 register enum rtx_code code
= GET_CODE (op
);
2032 register rtx y
= XEXP (op
, 0);
2035 if (CONSTANT_ADDRESS_P (y
))
2037 new = gen_rtx_MEM (GET_MODE (op
),
2038 plus_constant_for_output (y
, offset
));
2039 MEM_COPY_ATTRIBUTES (new, op
);
2043 if (GET_CODE (y
) == PLUS
)
2046 register rtx
*const_loc
;
2050 const_loc
= find_constant_term_loc (&z
);
2053 *const_loc
= plus_constant_for_output (*const_loc
, offset
);
2058 new = gen_rtx_MEM (GET_MODE (op
), plus_constant_for_output (y
, offset
));
2059 MEM_COPY_ATTRIBUTES (new, op
);
2065 /* Like extract_insn, but save insn extracted and don't extract again, when
2066 called again for the same insn expecting that recog_data still contain the
2067 valid information. This is used primary by gen_attr infrastructure that
2068 often does extract insn again and again. */
2070 extract_insn_cached (insn
)
2073 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2075 extract_insn (insn
);
2076 recog_data
.insn
= insn
;
2078 /* Do cached extract_insn, constrain_operand and complain about failures.
2079 Used by insn_attrtab. */
2081 extract_constrain_insn_cached (insn
)
2084 extract_insn_cached (insn
);
2085 if (which_alternative
== -1
2086 && !constrain_operands (reload_completed
))
2087 fatal_insn_not_found (insn
);
2089 /* Do cached constrain_operand and complain about failures. */
2091 constrain_operands_cached (strict
)
2094 if (which_alternative
== -1)
2095 return constrain_operands (strict
);
2100 /* Analyze INSN and fill in recog_data. */
2109 rtx body
= PATTERN (insn
);
2111 recog_data
.insn
= NULL
;
2112 recog_data
.n_operands
= 0;
2113 recog_data
.n_alternatives
= 0;
2114 recog_data
.n_dups
= 0;
2115 which_alternative
= -1;
2117 switch (GET_CODE (body
))
2127 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2132 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2133 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2134 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2140 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2143 /* This insn is an `asm' with operands. */
2145 /* expand_asm_operands makes sure there aren't too many operands. */
2146 if (noperands
> MAX_RECOG_OPERANDS
)
2149 /* Now get the operand values and constraints out of the insn. */
2150 decode_asm_operands (body
, recog_data
.operand
,
2151 recog_data
.operand_loc
,
2152 recog_data
.constraints
,
2153 recog_data
.operand_mode
);
2156 const char *p
= recog_data
.constraints
[0];
2157 recog_data
.n_alternatives
= 1;
2159 recog_data
.n_alternatives
+= (*p
++ == ',');
2163 fatal_insn_not_found (insn
);
2167 /* Ordinary insn: recognize it, get the operands via insn_extract
2168 and get the constraints. */
2170 icode
= recog_memoized (insn
);
2172 fatal_insn_not_found (insn
);
2174 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2175 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2176 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2178 insn_extract (insn
);
2180 for (i
= 0; i
< noperands
; i
++)
2182 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2183 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2184 /* VOIDmode match_operands gets mode from their real operand. */
2185 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2186 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2189 for (i
= 0; i
< noperands
; i
++)
2190 recog_data
.operand_type
[i
]
2191 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2192 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2195 if (recog_data
.n_alternatives
> MAX_RECOG_ALTERNATIVES
)
2199 /* After calling extract_insn, you can use this function to extract some
2200 information from the constraint strings into a more usable form.
2201 The collected data is stored in recog_op_alt. */
2203 preprocess_constraints ()
2207 memset (recog_op_alt
, 0, sizeof recog_op_alt
);
2208 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2211 struct operand_alternative
*op_alt
;
2212 const char *p
= recog_data
.constraints
[i
];
2214 op_alt
= recog_op_alt
[i
];
2216 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2218 op_alt
[j
].class = NO_REGS
;
2219 op_alt
[j
].constraint
= p
;
2220 op_alt
[j
].matches
= -1;
2221 op_alt
[j
].matched
= -1;
2223 if (*p
== '\0' || *p
== ',')
2225 op_alt
[j
].anything_ok
= 1;
2235 while (c
!= ',' && c
!= '\0');
2236 if (c
== ',' || c
== '\0')
2241 case '=': case '+': case '*': case '%':
2242 case 'E': case 'F': case 'G': case 'H':
2243 case 's': case 'i': case 'n':
2244 case 'I': case 'J': case 'K': case 'L':
2245 case 'M': case 'N': case 'O': case 'P':
2246 /* These don't say anything we care about. */
2250 op_alt
[j
].reject
+= 6;
2253 op_alt
[j
].reject
+= 600;
2256 op_alt
[j
].earlyclobber
= 1;
2259 case '0': case '1': case '2': case '3': case '4':
2260 case '5': case '6': case '7': case '8': case '9':
2261 op_alt
[j
].matches
= c
- '0';
2262 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2266 op_alt
[j
].memory_ok
= 1;
2269 op_alt
[j
].decmem_ok
= 1;
2272 op_alt
[j
].incmem_ok
= 1;
2275 op_alt
[j
].nonoffmem_ok
= 1;
2278 op_alt
[j
].offmem_ok
= 1;
2281 op_alt
[j
].anything_ok
= 1;
2285 op_alt
[j
].is_address
= 1;
2286 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) BASE_REG_CLASS
];
2290 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) GENERAL_REGS
];
2294 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
2302 /* Check the operands of an insn against the insn's operand constraints
2303 and return 1 if they are valid.
2304 The information about the insn's operands, constraints, operand modes
2305 etc. is obtained from the global variables set up by extract_insn.
2307 WHICH_ALTERNATIVE is set to a number which indicates which
2308 alternative of constraints was matched: 0 for the first alternative,
2309 1 for the next, etc.
2311 In addition, when two operands are match
2312 and it happens that the output operand is (reg) while the
2313 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2314 make the output operand look like the input.
2315 This is because the output operand is the one the template will print.
2317 This is used in final, just before printing the assembler code and by
2318 the routines that determine an insn's attribute.
2320 If STRICT is a positive non-zero value, it means that we have been
2321 called after reload has been completed. In that case, we must
2322 do all checks strictly. If it is zero, it means that we have been called
2323 before reload has completed. In that case, we first try to see if we can
2324 find an alternative that matches strictly. If not, we try again, this
2325 time assuming that reload will fix up the insn. This provides a "best
2326 guess" for the alternative and is used to compute attributes of insns prior
2327 to reload. A negative value of STRICT is used for this internal call. */
2335 constrain_operands (strict
)
2338 const char *constraints
[MAX_RECOG_OPERANDS
];
2339 int matching_operands
[MAX_RECOG_OPERANDS
];
2340 int earlyclobber
[MAX_RECOG_OPERANDS
];
2343 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2344 int funny_match_index
;
2346 which_alternative
= 0;
2347 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2350 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2352 constraints
[c
] = recog_data
.constraints
[c
];
2353 matching_operands
[c
] = -1;
2360 funny_match_index
= 0;
2362 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2364 register rtx op
= recog_data
.operand
[opno
];
2365 enum machine_mode mode
= GET_MODE (op
);
2366 register const char *p
= constraints
[opno
];
2371 earlyclobber
[opno
] = 0;
2373 /* A unary operator may be accepted by the predicate, but it
2374 is irrelevant for matching constraints. */
2375 if (GET_RTX_CLASS (GET_CODE (op
)) == '1')
2378 if (GET_CODE (op
) == SUBREG
)
2380 if (GET_CODE (SUBREG_REG (op
)) == REG
2381 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2382 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2383 GET_MODE (SUBREG_REG (op
)),
2386 op
= SUBREG_REG (op
);
2389 /* An empty constraint or empty alternative
2390 allows anything which matched the pattern. */
2391 if (*p
== 0 || *p
== ',')
2394 while (*p
&& (c
= *p
++) != ',')
2397 case '?': case '!': case '*': case '%':
2402 /* Ignore rest of this alternative as far as
2403 constraint checking is concerned. */
2404 while (*p
&& *p
!= ',')
2409 earlyclobber
[opno
] = 1;
2412 case '0': case '1': case '2': case '3': case '4':
2413 case '5': case '6': case '7': case '8': case '9':
2415 /* This operand must be the same as a previous one.
2416 This kind of constraint is used for instructions such
2417 as add when they take only two operands.
2419 Note that the lower-numbered operand is passed first.
2421 If we are not testing strictly, assume that this constraint
2422 will be satisfied. */
2427 rtx op1
= recog_data
.operand
[c
- '0'];
2428 rtx op2
= recog_data
.operand
[opno
];
2430 /* A unary operator may be accepted by the predicate,
2431 but it is irrelevant for matching constraints. */
2432 if (GET_RTX_CLASS (GET_CODE (op1
)) == '1')
2433 op1
= XEXP (op1
, 0);
2434 if (GET_RTX_CLASS (GET_CODE (op2
)) == '1')
2435 op2
= XEXP (op2
, 0);
2437 val
= operands_match_p (op1
, op2
);
2440 matching_operands
[opno
] = c
- '0';
2441 matching_operands
[c
- '0'] = opno
;
2445 /* If output is *x and input is *--x,
2446 arrange later to change the output to *--x as well,
2447 since the output op is the one that will be printed. */
2448 if (val
== 2 && strict
> 0)
2450 funny_match
[funny_match_index
].this = opno
;
2451 funny_match
[funny_match_index
++].other
= c
- '0';
2456 /* p is used for address_operands. When we are called by
2457 gen_reload, no one will have checked that the address is
2458 strictly valid, i.e., that all pseudos requiring hard regs
2459 have gotten them. */
2461 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2466 /* No need to check general_operand again;
2467 it was done in insn-recog.c. */
2469 /* Anything goes unless it is a REG and really has a hard reg
2470 but the hard reg is not in the class GENERAL_REGS. */
2472 || GENERAL_REGS
== ALL_REGS
2473 || GET_CODE (op
) != REG
2474 || (reload_in_progress
2475 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2476 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2481 /* This is used for a MATCH_SCRATCH in the cases when
2482 we don't actually need anything. So anything goes
2488 if (GET_CODE (op
) == MEM
2489 /* Before reload, accept what reload can turn into mem. */
2490 || (strict
< 0 && CONSTANT_P (op
))
2491 /* During reload, accept a pseudo */
2492 || (reload_in_progress
&& GET_CODE (op
) == REG
2493 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2498 if (GET_CODE (op
) == MEM
2499 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2500 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2505 if (GET_CODE (op
) == MEM
2506 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2507 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2512 #ifndef REAL_ARITHMETIC
2513 /* Match any CONST_DOUBLE, but only if
2514 we can examine the bits of it reliably. */
2515 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
2516 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
2517 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
2520 if (GET_CODE (op
) == CONST_DOUBLE
)
2525 if (GET_CODE (op
) == CONST_DOUBLE
)
2531 if (GET_CODE (op
) == CONST_DOUBLE
2532 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
2537 if (GET_CODE (op
) == CONST_INT
2538 || (GET_CODE (op
) == CONST_DOUBLE
2539 && GET_MODE (op
) == VOIDmode
))
2542 if (CONSTANT_P (op
))
2547 if (GET_CODE (op
) == CONST_INT
2548 || (GET_CODE (op
) == CONST_DOUBLE
2549 && GET_MODE (op
) == VOIDmode
))
2561 if (GET_CODE (op
) == CONST_INT
2562 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
2567 if (GET_CODE (op
) == MEM
2568 && ((strict
> 0 && ! offsettable_memref_p (op
))
2570 && !(CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2571 || (reload_in_progress
2572 && !(GET_CODE (op
) == REG
2573 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2578 if ((strict
> 0 && offsettable_memref_p (op
))
2579 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2580 /* Before reload, accept what reload can handle. */
2582 && (CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2583 /* During reload, accept a pseudo */
2584 || (reload_in_progress
&& GET_CODE (op
) == REG
2585 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2591 enum reg_class
class;
2593 class = (c
== 'r' ? GENERAL_REGS
: REG_CLASS_FROM_LETTER (c
));
2594 if (class != NO_REGS
)
2598 && GET_CODE (op
) == REG
2599 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2600 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2601 || (GET_CODE (op
) == REG
2602 && reg_fits_class_p (op
, class, offset
, mode
)))
2605 #ifdef EXTRA_CONSTRAINT
2606 else if (EXTRA_CONSTRAINT (op
, c
))
2613 constraints
[opno
] = p
;
2614 /* If this operand did not win somehow,
2615 this alternative loses. */
2619 /* This alternative won; the operands are ok.
2620 Change whichever operands this alternative says to change. */
2625 /* See if any earlyclobber operand conflicts with some other
2629 for (eopno
= 0; eopno
< recog_data
.n_operands
; eopno
++)
2630 /* Ignore earlyclobber operands now in memory,
2631 because we would often report failure when we have
2632 two memory operands, one of which was formerly a REG. */
2633 if (earlyclobber
[eopno
]
2634 && GET_CODE (recog_data
.operand
[eopno
]) == REG
)
2635 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2636 if ((GET_CODE (recog_data
.operand
[opno
]) == MEM
2637 || recog_data
.operand_type
[opno
] != OP_OUT
)
2639 /* Ignore things like match_operator operands. */
2640 && *recog_data
.constraints
[opno
] != 0
2641 && ! (matching_operands
[opno
] == eopno
2642 && operands_match_p (recog_data
.operand
[opno
],
2643 recog_data
.operand
[eopno
]))
2644 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2645 recog_data
.operand
[eopno
]))
2650 while (--funny_match_index
>= 0)
2652 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2653 = recog_data
.operand
[funny_match
[funny_match_index
].this];
2660 which_alternative
++;
2662 while (which_alternative
< recog_data
.n_alternatives
);
2664 which_alternative
= -1;
2665 /* If we are about to reject this, but we are not to test strictly,
2666 try a very loose test. Only return failure if it fails also. */
2668 return constrain_operands (-1);
2673 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2674 is a hard reg in class CLASS when its regno is offset by OFFSET
2675 and changed to mode MODE.
2676 If REG occupies multiple hard regs, all of them must be in CLASS. */
2679 reg_fits_class_p (operand
, class, offset
, mode
)
2681 register enum reg_class
class;
2683 enum machine_mode mode
;
2685 register int regno
= REGNO (operand
);
2686 if (regno
< FIRST_PSEUDO_REGISTER
2687 && TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2692 for (sr
= HARD_REGNO_NREGS (regno
, mode
) - 1;
2694 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2703 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2706 split_all_insns (upd_life
)
2713 blocks
= sbitmap_alloc (n_basic_blocks
);
2714 sbitmap_zero (blocks
);
2717 for (i
= n_basic_blocks
- 1; i
>= 0; --i
)
2719 basic_block bb
= BASIC_BLOCK (i
);
2722 for (insn
= bb
->head
; insn
; insn
= next
)
2726 /* Can't use `next_real_insn' because that might go across
2727 CODE_LABELS and short-out basic blocks. */
2728 next
= NEXT_INSN (insn
);
2729 if (! INSN_P (insn
))
2732 /* Don't split no-op move insns. These should silently
2733 disappear later in final. Splitting such insns would
2734 break the code that handles REG_NO_CONFLICT blocks. */
2736 else if ((set
= single_set (insn
)) != NULL
2737 && set_noop_p (set
))
2739 /* Nops get in the way while scheduling, so delete them
2740 now if register allocation has already been done. It
2741 is too risky to try to do this before register
2742 allocation, and there are unlikely to be very many
2743 nops then anyways. */
2744 if (reload_completed
)
2746 PUT_CODE (insn
, NOTE
);
2747 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2748 NOTE_SOURCE_FILE (insn
) = 0;
2753 /* Split insns here to get max fine-grain parallelism. */
2754 rtx first
= PREV_INSN (insn
);
2755 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2759 SET_BIT (blocks
, i
);
2762 /* try_split returns the NOTE that INSN became. */
2763 PUT_CODE (insn
, NOTE
);
2764 NOTE_SOURCE_FILE (insn
) = 0;
2765 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2767 /* ??? Coddle to md files that generate subregs in post-
2768 reload splitters instead of computing the proper
2770 if (reload_completed
&& first
!= last
)
2772 first
= NEXT_INSN (first
);
2776 cleanup_subreg_operands (first
);
2779 first
= NEXT_INSN (first
);
2783 if (insn
== bb
->end
)
2791 if (insn
== bb
->end
)
2795 /* ??? When we're called from just after reload, the CFG is in bad
2796 shape, and we may have fallen off the end. This could be fixed
2797 by having reload not try to delete unreachable code. Otherwise
2798 assert we found the end insn. */
2799 if (insn
== NULL
&& upd_life
)
2803 if (changed
&& upd_life
)
2805 compute_bb_for_insn (get_max_uid ());
2806 count_or_remove_death_notes (blocks
, 1);
2807 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
2810 sbitmap_free (blocks
);
2813 #ifdef HAVE_peephole2
2814 struct peep2_insn_data
2820 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2821 static int peep2_current
;
2823 /* A non-insn marker indicating the last insn of the block.
2824 The live_before regset for this element is correct, indicating
2825 global_live_at_end for the block. */
2826 #define PEEP2_EOB pc_rtx
2828 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2829 does not exist. Used by the recognizer to find the next insn to match
2830 in a multi-insn pattern. */
2836 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2840 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2841 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2843 if (peep2_insn_data
[n
].insn
== PEEP2_EOB
)
2845 return peep2_insn_data
[n
].insn
;
2848 /* Return true if REGNO is dead before the Nth non-note insn
2852 peep2_regno_dead_p (ofs
, regno
)
2856 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2859 ofs
+= peep2_current
;
2860 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2861 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2863 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2866 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
2869 /* Similarly for a REG. */
2872 peep2_reg_dead_p (ofs
, reg
)
2878 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2881 ofs
+= peep2_current
;
2882 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2883 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2885 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2888 regno
= REGNO (reg
);
2889 n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2891 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
2896 /* Try to find a hard register of mode MODE, matching the register class in
2897 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2898 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2899 in which case the only condition is that the register must be available
2900 before CURRENT_INSN.
2901 Registers that already have bits set in REG_SET will not be considered.
2903 If an appropriate register is available, it will be returned and the
2904 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2908 peep2_find_free_register (from
, to
, class_str
, mode
, reg_set
)
2910 const char *class_str
;
2911 enum machine_mode mode
;
2912 HARD_REG_SET
*reg_set
;
2914 static int search_ofs
;
2915 enum reg_class
class;
2919 if (from
>= MAX_INSNS_PER_PEEP2
+ 1 || to
>= MAX_INSNS_PER_PEEP2
+ 1)
2922 from
+= peep2_current
;
2923 if (from
>= MAX_INSNS_PER_PEEP2
+ 1)
2924 from
-= MAX_INSNS_PER_PEEP2
+ 1;
2925 to
+= peep2_current
;
2926 if (to
>= MAX_INSNS_PER_PEEP2
+ 1)
2927 to
-= MAX_INSNS_PER_PEEP2
+ 1;
2929 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2931 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
2935 HARD_REG_SET this_live
;
2937 if (++from
>= MAX_INSNS_PER_PEEP2
+ 1)
2939 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2941 REG_SET_TO_HARD_REG_SET (this_live
, peep2_insn_data
[from
].live_before
);
2942 IOR_HARD_REG_SET (live
, this_live
);
2945 class = (class_str
[0] == 'r' ? GENERAL_REGS
2946 : REG_CLASS_FROM_LETTER (class_str
[0]));
2948 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2950 int raw_regno
, regno
, success
, j
;
2952 /* Distribute the free registers as much as possible. */
2953 raw_regno
= search_ofs
+ i
;
2954 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
2955 raw_regno
-= FIRST_PSEUDO_REGISTER
;
2956 #ifdef REG_ALLOC_ORDER
2957 regno
= reg_alloc_order
[raw_regno
];
2962 /* Don't allocate fixed registers. */
2963 if (fixed_regs
[regno
])
2965 /* Make sure the register is of the right class. */
2966 if (! TEST_HARD_REG_BIT (reg_class_contents
[class], regno
))
2968 /* And can support the mode we need. */
2969 if (! HARD_REGNO_MODE_OK (regno
, mode
))
2971 /* And that we don't create an extra save/restore. */
2972 if (! call_used_regs
[regno
] && ! regs_ever_live
[regno
])
2974 /* And we don't clobber traceback for noreturn functions. */
2975 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
2976 && (! reload_completed
|| frame_pointer_needed
))
2980 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
2982 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
2983 || TEST_HARD_REG_BIT (live
, regno
+ j
))
2991 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
2992 SET_HARD_REG_BIT (*reg_set
, regno
+ j
);
2994 /* Start the next search with the next register. */
2995 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
2997 search_ofs
= raw_regno
;
2999 return gen_rtx_REG (mode
, regno
);
3007 /* Perform the peephole2 optimization pass. */
3010 peephole2_optimize (dump_file
)
3011 FILE *dump_file ATTRIBUTE_UNUSED
;
3013 regset_head rs_heads
[MAX_INSNS_PER_PEEP2
+ 2];
3017 #ifdef HAVE_conditional_execution
3022 /* Initialize the regsets we're going to use. */
3023 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3024 peep2_insn_data
[i
].live_before
= INITIALIZE_REG_SET (rs_heads
[i
]);
3025 live
= INITIALIZE_REG_SET (rs_heads
[i
]);
3027 #ifdef HAVE_conditional_execution
3028 blocks
= sbitmap_alloc (n_basic_blocks
);
3029 sbitmap_zero (blocks
);
3032 count_or_remove_death_notes (NULL
, 1);
3035 for (b
= n_basic_blocks
- 1; b
>= 0; --b
)
3037 basic_block bb
= BASIC_BLOCK (b
);
3038 struct propagate_block_info
*pbi
;
3040 /* Indicate that all slots except the last holds invalid data. */
3041 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3042 peep2_insn_data
[i
].insn
= NULL_RTX
;
3044 /* Indicate that the last slot contains live_after data. */
3045 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3046 peep2_current
= MAX_INSNS_PER_PEEP2
;
3048 /* Start up propagation. */
3049 COPY_REG_SET (live
, bb
->global_live_at_end
);
3050 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3052 #ifdef HAVE_conditional_execution
3053 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, 0);
3055 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, PROP_DEATH_NOTES
);
3058 for (insn
= bb
->end
; ; insn
= prev
)
3060 prev
= PREV_INSN (insn
);
3066 /* Record this insn. */
3067 if (--peep2_current
< 0)
3068 peep2_current
= MAX_INSNS_PER_PEEP2
;
3069 peep2_insn_data
[peep2_current
].insn
= insn
;
3070 propagate_one_insn (pbi
, insn
);
3071 COPY_REG_SET (peep2_insn_data
[peep2_current
].live_before
, live
);
3073 /* Match the peephole. */
3074 try = peephole2_insns (PATTERN (insn
), insn
, &match_len
);
3077 i
= match_len
+ peep2_current
;
3078 if (i
>= MAX_INSNS_PER_PEEP2
+ 1)
3079 i
-= MAX_INSNS_PER_PEEP2
+ 1;
3081 /* Replace the old sequence with the new. */
3082 flow_delete_insn_chain (insn
, peep2_insn_data
[i
].insn
);
3083 try = emit_insn_after (try, prev
);
3085 /* Adjust the basic block boundaries. */
3086 if (peep2_insn_data
[i
].insn
== bb
->end
)
3088 if (insn
== bb
->head
)
3089 bb
->head
= NEXT_INSN (prev
);
3091 #ifdef HAVE_conditional_execution
3092 /* With conditional execution, we cannot back up the
3093 live information so easily, since the conditional
3094 death data structures are not so self-contained.
3095 So record that we've made a modification to this
3096 block and update life information at the end. */
3097 SET_BIT (blocks
, b
);
3100 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3101 peep2_insn_data
[i
].insn
= NULL_RTX
;
3102 peep2_insn_data
[peep2_current
].insn
= PEEP2_EOB
;
3104 /* Back up lifetime information past the end of the
3105 newly created sequence. */
3106 if (++i
>= MAX_INSNS_PER_PEEP2
+ 1)
3108 COPY_REG_SET (live
, peep2_insn_data
[i
].live_before
);
3110 /* Update life information for the new sequence. */
3116 i
= MAX_INSNS_PER_PEEP2
;
3117 peep2_insn_data
[i
].insn
= try;
3118 propagate_one_insn (pbi
, try);
3119 COPY_REG_SET (peep2_insn_data
[i
].live_before
, live
);
3121 try = PREV_INSN (try);
3123 while (try != prev
);
3125 /* ??? Should verify that LIVE now matches what we
3126 had before the new sequence. */
3133 if (insn
== bb
->head
)
3137 free_propagate_block_info (pbi
);
3140 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3141 FREE_REG_SET (peep2_insn_data
[i
].live_before
);
3142 FREE_REG_SET (live
);
3144 #ifdef HAVE_conditional_execution
3145 count_or_remove_death_notes (blocks
, 1);
3146 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
3147 sbitmap_free (blocks
);
3150 #endif /* HAVE_peephole2 */