| blob | 2f905d2b31a1acc7c3133a47efc3967d5abe5263 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
72 #ifndef CHECK_STACK_LIMIT
73 #define CHECK_STACK_LIMIT (-1)
74 #endif
76 /* Return index of given mode in mult and division cost tables. */
77 #define MODE_INDEX(mode) \
78 ((mode) == QImode ? 0 \
79 : (mode) == HImode ? 1 \
80 : (mode) == SImode ? 2 \
81 : (mode) == DImode ? 3 \
82 : 4)
84 /* Processor costs (relative to an add) */
85 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
86 #define COSTS_N_BYTES(N) ((N) * 2)
88 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
97 const
120 in QImode, HImode and SImode.
121 Relative to reg-reg move (2). */
125 in SFmode, DFmode and XFmode */
127 in SFmode, DFmode and XFmode */
130 in SImode and DImode */
132 in SImode and DImode */
135 in SImode, DImode and TImode */
137 in SImode, DImode and TImode */
150 ix86_size_memcpy,
151 ix86_size_memset,
163 };
165 /* Processor costs (relative to an add) */
168 DUMMY_STRINGOP_ALGS};
171 DUMMY_STRINGOP_ALGS};
173 static const
196 in QImode, HImode and SImode.
197 Relative to reg-reg move (2). */
201 in SFmode, DFmode and XFmode */
203 in SFmode, DFmode and XFmode */
206 in SImode and DImode */
208 in SImode and DImode */
211 in SImode, DImode and TImode */
213 in SImode, DImode and TImode */
226 i386_memcpy,
227 i386_memset,
239 };
243 DUMMY_STRINGOP_ALGS};
246 DUMMY_STRINGOP_ALGS};
248 static const
271 in QImode, HImode and SImode.
272 Relative to reg-reg move (2). */
276 in SFmode, DFmode and XFmode */
278 in SFmode, DFmode and XFmode */
281 in SImode and DImode */
283 in SImode and DImode */
286 in SImode, DImode and TImode */
288 in SImode, DImode and TImode */
291 shared for code and data, so 4kB is
292 not really precise. */
303 i486_memcpy,
304 i486_memset,
316 };
320 DUMMY_STRINGOP_ALGS};
323 DUMMY_STRINGOP_ALGS};
325 static const
348 in QImode, HImode and SImode.
349 Relative to reg-reg move (2). */
353 in SFmode, DFmode and XFmode */
355 in SFmode, DFmode and XFmode */
358 in SImode and DImode */
360 in SImode and DImode */
363 in SImode, DImode and TImode */
365 in SImode, DImode and TImode */
378 pentium_memcpy,
379 pentium_memset,
391 };
393 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
394 (we ensure the alignment). For small blocks inline loop is still a
395 noticeable win, for bigger blocks either rep movsl or rep movsb is
396 way to go. Rep movsb has apparently more expensive startup time in CPU,
397 but after 4K the difference is down in the noise. */
402 DUMMY_STRINGOP_ALGS};
407 DUMMY_STRINGOP_ALGS};
408 static const
431 in QImode, HImode and SImode.
432 Relative to reg-reg move (2). */
436 in SFmode, DFmode and XFmode */
438 in SFmode, DFmode and XFmode */
441 in SImode and DImode */
443 in SImode and DImode */
446 in SImode, DImode and TImode */
448 in SImode, DImode and TImode */
461 pentiumpro_memcpy,
462 pentiumpro_memset,
474 };
478 DUMMY_STRINGOP_ALGS};
481 DUMMY_STRINGOP_ALGS};
482 static const
505 in QImode, HImode and SImode.
506 Relative to reg-reg move (2). */
510 in SFmode, DFmode and XFmode */
512 in SFmode, DFmode and XFmode */
516 in SImode and DImode */
518 in SImode and DImode */
521 in SImode, DImode and TImode */
523 in SImode, DImode and TImode */
536 geode_memcpy,
537 geode_memset,
549 };
553 DUMMY_STRINGOP_ALGS};
556 DUMMY_STRINGOP_ALGS};
557 static const
580 in QImode, HImode and SImode.
581 Relative to reg-reg move (2). */
585 in SFmode, DFmode and XFmode */
587 in SFmode, DFmode and XFmode */
590 in SImode and DImode */
592 in SImode and DImode */
595 in SImode, DImode and TImode */
597 in SImode, DImode and TImode */
601 have integrated l2 cache, but
602 optimizing for k6 is not important
603 enough to worry about that. */
613 k6_memcpy,
614 k6_memset,
626 };
628 /* For some reason, Athlon deals better with REP prefix (relative to loops)
629 compared to K8. Alignment becomes important after 8 bytes for memcpy and
630 128 bytes for memset. */
633 DUMMY_STRINGOP_ALGS};
636 DUMMY_STRINGOP_ALGS};
637 static const
660 in QImode, HImode and SImode.
661 Relative to reg-reg move (2). */
665 in SFmode, DFmode and XFmode */
667 in SFmode, DFmode and XFmode */
670 in SImode and DImode */
672 in SImode and DImode */
675 in SImode, DImode and TImode */
677 in SImode, DImode and TImode */
690 athlon_memcpy,
691 athlon_memset,
703 };
705 /* K8 has optimized REP instruction for medium sized blocks, but for very
706 small blocks it is better to use loop. For large blocks, libcall can
707 do nontemporary accesses and beat inline considerably. */
718 static const
741 in QImode, HImode and SImode.
742 Relative to reg-reg move (2). */
746 in SFmode, DFmode and XFmode */
748 in SFmode, DFmode and XFmode */
751 in SImode and DImode */
753 in SImode and DImode */
756 in SImode, DImode and TImode */
758 in SImode, DImode and TImode */
763 /* New AMD processors never drop prefetches; if they cannot be performed
764 immediately, they are queued. We set number of simultaneous prefetches
765 to a large constant to reflect this (it probably is not a good idea not
766 to limit number of prefetches at all, as their execution also takes some
767 time). */
777 k8_memcpy,
778 k8_memset,
790 };
792 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
793 very small blocks it is better to use loop. For large blocks, libcall can
794 do nontemporary accesses and beat inline considerably. */
827 in QImode, HImode and SImode.
828 Relative to reg-reg move (2). */
832 in SFmode, DFmode and XFmode */
834 in SFmode, DFmode and XFmode */
837 in SImode and DImode */
839 in SImode and DImode */
842 in SImode, DImode and TImode */
844 in SImode, DImode and TImode */
846 /* On K8:
847 MOVD reg64, xmmreg Double FSTORE 4
848 MOVD reg32, xmmreg Double FSTORE 4
849 On AMDFAM10:
850 MOVD reg64, xmmreg Double FADD 3
851 1/1 1/1
852 MOVD reg32, xmmreg Double FADD 3
853 1/1 1/1 */
857 /* New AMD processors never drop prefetches; if they cannot be performed
858 immediately, they are queued. We set number of simultaneous prefetches
859 to a large constant to reflect this (it probably is not a good idea not
860 to limit number of prefetches at all, as their execution also takes some
861 time). */
871 amdfam10_memcpy,
872 amdfam10_memset,
884 };
886 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
887 very small blocks it is better to use loop. For large blocks, libcall
888 can do nontemporary accesses and beat inline considerably. */
922 in QImode, HImode and SImode.
923 Relative to reg-reg move (2). */
927 in SFmode, DFmode and XFmode */
929 in SFmode, DFmode and XFmode */
932 in SImode and DImode */
934 in SImode and DImode */
937 in SImode, DImode and TImode */
939 in SImode, DImode and TImode */
941 /* On K8:
942 MOVD reg64, xmmreg Double FSTORE 4
943 MOVD reg32, xmmreg Double FSTORE 4
944 On AMDFAM10:
945 MOVD reg64, xmmreg Double FADD 3
946 1/1 1/1
947 MOVD reg32, xmmreg Double FADD 3
948 1/1 1/1 */
952 /* New AMD processors never drop prefetches; if they cannot be performed
953 immediately, they are queued. We set number of simultaneous prefetches
954 to a large constant to reflect this (it probably is not a good idea not
955 to limit number of prefetches at all, as their execution also takes some
956 time). */
966 bdver1_memcpy,
967 bdver1_memset,
979 };
981 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
982 very small blocks it is better to use loop. For large blocks, libcall
983 can do nontemporary accesses and beat inline considerably. */
1018 in QImode, HImode and SImode.
1019 Relative to reg-reg move (2). */
1023 in SFmode, DFmode and XFmode */
1025 in SFmode, DFmode and XFmode */
1028 in SImode and DImode */
1030 in SImode and DImode */
1033 in SImode, DImode and TImode */
1035 in SImode, DImode and TImode */
1037 /* On K8:
1038 MOVD reg64, xmmreg Double FSTORE 4
1039 MOVD reg32, xmmreg Double FSTORE 4
1040 On AMDFAM10:
1041 MOVD reg64, xmmreg Double FADD 3
1042 1/1 1/1
1043 MOVD reg32, xmmreg Double FADD 3
1044 1/1 1/1 */
1048 /* New AMD processors never drop prefetches; if they cannot be performed
1049 immediately, they are queued. We set number of simultaneous prefetches
1050 to a large constant to reflect this (it probably is not a good idea not
1051 to limit number of prefetches at all, as their execution also takes some
1052 time). */
1062 bdver2_memcpy,
1063 bdver2_memset,
1075 };
1078 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1079 very small blocks it is better to use loop. For large blocks, libcall
1080 can do nontemporary accesses and beat inline considerably. */
1113 in QImode, HImode and SImode.
1114 Relative to reg-reg move (2). */
1118 in SFmode, DFmode and XFmode */
1120 in SFmode, DFmode and XFmode */
1123 in SImode and DImode */
1125 in SImode and DImode */
1128 in SImode, DImode and TImode */
1130 in SImode, DImode and TImode */
1135 /* New AMD processors never drop prefetches; if they cannot be performed
1136 immediately, they are queued. We set number of simultaneous prefetches
1137 to a large constant to reflect this (it probably is not a good idea not
1138 to limit number of prefetches at all, as their execution also takes some
1139 time). */
1149 bdver3_memcpy,
1150 bdver3_memset,
1162 };
1164 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1165 very small blocks it is better to use loop. For large blocks, libcall can
1166 do nontemporary accesses and beat inline considerably. */
1199 in QImode, HImode and SImode.
1200 Relative to reg-reg move (2). */
1204 in SFmode, DFmode and XFmode */
1206 in SFmode, DFmode and XFmode */
1209 in SImode and DImode */
1211 in SImode and DImode */
1214 in SImode, DImode and TImode */
1216 in SImode, DImode and TImode */
1218 /* On K8:
1219 MOVD reg64, xmmreg Double FSTORE 4
1220 MOVD reg32, xmmreg Double FSTORE 4
1221 On AMDFAM10:
1222 MOVD reg64, xmmreg Double FADD 3
1223 1/1 1/1
1224 MOVD reg32, xmmreg Double FADD 3
1225 1/1 1/1 */
1238 btver1_memcpy,
1239 btver1_memset,
1251 };
1285 in QImode, HImode and SImode.
1286 Relative to reg-reg move (2). */
1290 in SFmode, DFmode and XFmode */
1292 in SFmode, DFmode and XFmode */
1295 in SImode and DImode */
1297 in SImode and DImode */
1300 in SImode, DImode and TImode */
1302 in SImode, DImode and TImode */
1304 /* On K8:
1305 MOVD reg64, xmmreg Double FSTORE 4
1306 MOVD reg32, xmmreg Double FSTORE 4
1307 On AMDFAM10:
1308 MOVD reg64, xmmreg Double FADD 3
1309 1/1 1/1
1310 MOVD reg32, xmmreg Double FADD 3
1311 1/1 1/1 */
1323 btver2_memcpy,
1324 btver2_memset,
1336 };
1340 DUMMY_STRINGOP_ALGS};
1344 DUMMY_STRINGOP_ALGS};
1346 static const
1369 in QImode, HImode and SImode.
1370 Relative to reg-reg move (2). */
1374 in SFmode, DFmode and XFmode */
1376 in SFmode, DFmode and XFmode */
1379 in SImode and DImode */
1381 in SImode and DImode */
1384 in SImode, DImode and TImode */
1386 in SImode, DImode and TImode */
1399 pentium4_memcpy,
1400 pentium4_memset,
1412 };
1425 static const
1448 in QImode, HImode and SImode.
1449 Relative to reg-reg move (2). */
1453 in SFmode, DFmode and XFmode */
1455 in SFmode, DFmode and XFmode */
1458 in SImode and DImode */
1460 in SImode and DImode */
1463 in SImode, DImode and TImode */
1465 in SImode, DImode and TImode */
1478 nocona_memcpy,
1479 nocona_memset,
1491 };
1502 static const
1525 in QImode, HImode and SImode.
1526 Relative to reg-reg move (2). */
1530 in SFmode, DFmode and XFmode */
1532 in SFmode, DFmode and XFmode */
1535 in SImode and DImode */
1537 in SImode and DImode */
1540 in SImode, DImode and TImode */
1542 in SImode, DImode and TImode */
1555 atom_memcpy,
1556 atom_memset,
1568 };
1579 static const
1602 in QImode, HImode and SImode.
1603 Relative to reg-reg move (2). */
1607 in SFmode, DFmode and XFmode */
1609 in SFmode, DFmode and XFmode */
1612 in SImode and DImode */
1614 in SImode and DImode */
1617 in SImode, DImode and TImode */
1619 in SImode, DImode and TImode */
1632 slm_memcpy,
1633 slm_memset,
1645 };
1647 /* Generic64 should produce code tuned for Nocona and K8. */
1650 DUMMY_STRINGOP_ALGS,
1654 DUMMY_STRINGOP_ALGS,
1657 static const
1660 /* On all chips taken into consideration lea is 2 cycles and more. With
1661 this cost however our current implementation of synth_mult results in
1662 use of unnecessary temporary registers causing regression on several
1663 SPECfp benchmarks. */
1684 in QImode, HImode and SImode.
1685 Relative to reg-reg move (2). */
1689 in SFmode, DFmode and XFmode */
1691 in SFmode, DFmode and XFmode */
1694 in SImode and DImode */
1696 in SImode and DImode */
1699 in SImode, DImode and TImode */
1701 in SImode, DImode and TImode */
1707 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1708 value is increased to perhaps more appropriate value of 5. */
1716 generic64_memcpy,
1717 generic64_memset,
1729 };
1731 /* core_cost should produce code tuned for Core familly of CPUs. */
1744 static const
1747 /* On all chips taken into consideration lea is 2 cycles and more. With
1748 this cost however our current implementation of synth_mult results in
1749 use of unnecessary temporary registers causing regression on several
1750 SPECfp benchmarks. */
1771 in QImode, HImode and SImode.
1772 Relative to reg-reg move (2). */
1776 in SFmode, DFmode and XFmode */
1778 in SFmode, DFmode and XFmode */
1781 in SImode and DImode */
1783 in SImode and DImode */
1786 in SImode, DImode and TImode */
1788 in SImode, DImode and TImode */
1794 /* FIXME perhaps more appropriate value is 5. */
1802 core_memcpy,
1803 core_memset,
1815 };
1817 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1818 Athlon and K8. */
1822 DUMMY_STRINGOP_ALGS};
1826 DUMMY_STRINGOP_ALGS};
1827 static const
1850 in QImode, HImode and SImode.
1851 Relative to reg-reg move (2). */
1855 in SFmode, DFmode and XFmode */
1857 in SFmode, DFmode and XFmode */
1860 in SImode and DImode */
1862 in SImode and DImode */
1865 in SImode, DImode and TImode */
1867 in SImode, DImode and TImode */
1880 generic32_memcpy,
1881 generic32_memset,
1893 };
1895 /* Set by -mtune. */
1898 /* Set by -mtune or -Os. */
1901 /* Processor feature/optimization bitmasks. */
1902 #define m_386 (1<<PROCESSOR_I386)
1903 #define m_486 (1<<PROCESSOR_I486)
1904 #define m_PENT (1<<PROCESSOR_PENTIUM)
1905 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1906 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1907 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1908 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1909 #define m_CORE2 (1<<PROCESSOR_CORE2)
1910 #define m_COREI7 (1<<PROCESSOR_COREI7)
1911 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1912 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1913 #define m_ATOM (1<<PROCESSOR_ATOM)
1914 #define m_SLM (1<<PROCESSOR_SLM)
1916 #define m_GEODE (1<<PROCESSOR_GEODE)
1917 #define m_K6 (1<<PROCESSOR_K6)
1918 #define m_K6_GEODE (m_K6 | m_GEODE)
1919 #define m_K8 (1<<PROCESSOR_K8)
1920 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1921 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1922 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1923 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1924 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1925 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1926 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1927 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1928 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1929 #define m_BTVER (m_BTVER1 | m_BTVER2)
1930 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1932 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1933 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1935 /* Generic instruction choice should be common subset of supported CPUs
1936 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1937 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1940 #undef DEF_TUNE
1941 #define DEF_TUNE(tune, name, selector) name,
1943 #undef DEF_TUNE
1944 };
1946 /* Feature tests against the various tunings. */
1949 /* Feature tests against the various tunings used to create ix86_tune_features
1950 based on the processor mask. */
1952 #undef DEF_TUNE
1953 #define DEF_TUNE(tune, name, selector) selector,
1955 #undef DEF_TUNE
1956 };
1958 /* Feature tests against the various architecture variations. */
1961 /* Feature tests against the various architecture variations, used to create
1962 ix86_arch_features based on the processor mask. */
1964 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
1967 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1970 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1973 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1976 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1978 };
1980 static const unsigned int x86_accumulate_outgoing_args
1983 static const unsigned int x86_arch_always_fancy_math_387
1986 static const unsigned int x86_avx256_split_unaligned_load
1989 static const unsigned int x86_avx256_split_unaligned_store
1992 /* In case the average insn count for single function invocation is
1993 lower than this constant, emit fast (but longer) prologue and
1994 epilogue code. */
1995 #define FAST_PROLOGUE_INSN_COUNT 20
1997 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2002 /* Array of the smallest class containing reg number REGNO, indexed by
2003 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2006 {
2007 /* ax, dx, cx, bx */
2009 /* si, di, bp, sp */
2011 /* FP registers */
2014 /* arg pointer */
2015 NON_Q_REGS,
2016 /* flags, fpsr, fpcr, frame */
2018 /* SSE registers */
2021 /* MMX registers */
2024 /* REX registers */
2027 /* SSE REX registers */
2030 };
2032 /* The "default" register map used in 32bit mode. */
2035 {
2043 };
2045 /* The "default" register map used in 64bit mode. */
2048 {
2056 };
2058 /* Define the register numbers to be used in Dwarf debugging information.
2059 The SVR4 reference port C compiler uses the following register numbers
2060 in its Dwarf output code:
2061 0 for %eax (gcc regno = 0)
2062 1 for %ecx (gcc regno = 2)
2063 2 for %edx (gcc regno = 1)
2064 3 for %ebx (gcc regno = 3)
2065 4 for %esp (gcc regno = 7)
2066 5 for %ebp (gcc regno = 6)
2067 6 for %esi (gcc regno = 4)
2068 7 for %edi (gcc regno = 5)
2069 The following three DWARF register numbers are never generated by
2070 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2071 believes these numbers have these meanings.
2072 8 for %eip (no gcc equivalent)
2073 9 for %eflags (gcc regno = 17)
2074 10 for %trapno (no gcc equivalent)
2075 It is not at all clear how we should number the FP stack registers
2076 for the x86 architecture. If the version of SDB on x86/svr4 were
2077 a bit less brain dead with respect to floating-point then we would
2078 have a precedent to follow with respect to DWARF register numbers
2079 for x86 FP registers, but the SDB on x86/svr4 is so completely
2080 broken with respect to FP registers that it is hardly worth thinking
2081 of it as something to strive for compatibility with.
2082 The version of x86/svr4 SDB I have at the moment does (partially)
2083 seem to believe that DWARF register number 11 is associated with
2084 the x86 register %st(0), but that's about all. Higher DWARF
2085 register numbers don't seem to be associated with anything in
2086 particular, and even for DWARF regno 11, SDB only seems to under-
2087 stand that it should say that a variable lives in %st(0) (when
2088 asked via an `=' command) if we said it was in DWARF regno 11,
2089 but SDB still prints garbage when asked for the value of the
2090 variable in question (via a `/' command).
2091 (Also note that the labels SDB prints for various FP stack regs
2092 when doing an `x' command are all wrong.)
2093 Note that these problems generally don't affect the native SVR4
2094 C compiler because it doesn't allow the use of -O with -g and
2095 because when it is *not* optimizing, it allocates a memory
2096 location for each floating-point variable, and the memory
2097 location is what gets described in the DWARF AT_location
2098 attribute for the variable in question.
2099 Regardless of the severe mental illness of the x86/svr4 SDB, we
2100 do something sensible here and we use the following DWARF
2101 register numbers. Note that these are all stack-top-relative
2102 numbers.
2103 11 for %st(0) (gcc regno = 8)
2104 12 for %st(1) (gcc regno = 9)
2105 13 for %st(2) (gcc regno = 10)
2106 14 for %st(3) (gcc regno = 11)
2107 15 for %st(4) (gcc regno = 12)
2108 16 for %st(5) (gcc regno = 13)
2109 17 for %st(6) (gcc regno = 14)
2110 18 for %st(7) (gcc regno = 15)
2111 */
2113 {
2121 };
2123 /* Define parameter passing and return registers. */
2126 {
2128 };
2131 {
2133 };
2136 {
2138 };
2140 /* Additional registers that are clobbered by SYSV calls. */
2143 {
2148 };
2150 /* Define the structure for the machine field in struct function. */
2155 rtx rtl;
2157 };
2159 /* Structure describing stack frame layout.
2160 Stack grows downward:
2162 [arguments]
2163 <- ARG_POINTER
2164 saved pc
2166 saved static chain if ix86_static_chain_on_stack
2168 saved frame pointer if frame_pointer_needed
2169 <- HARD_FRAME_POINTER
2170 [saved regs]
2171 <- regs_save_offset
2172 [padding0]
2174 [saved SSE regs]
2175 <- sse_regs_save_offset
2176 [padding1] |
2177 | <- FRAME_POINTER
2178 [va_arg registers] |
2179 |
2180 [frame] |
2181 |
2182 [padding2] | = to_allocate
2183 <- STACK_POINTER
2184 */
2185 struct ix86_frame
2186 {
2193 /* The offsets relative to ARG_POINTER. */
2194 HOST_WIDE_INT frame_pointer_offset;
2195 HOST_WIDE_INT hard_frame_pointer_offset;
2196 HOST_WIDE_INT stack_pointer_offset;
2197 HOST_WIDE_INT hfp_save_offset;
2198 HOST_WIDE_INT reg_save_offset;
2199 HOST_WIDE_INT sse_reg_save_offset;
2201 /* When save_regs_using_mov is set, emit prologue using
2202 move instead of push instructions. */
2204 };
2206 /* Which cpu are we scheduling for. */
2209 /* Which cpu are we optimizing for. */
2212 /* Which instruction set architecture to use. */
2215 /* True if processor has SSE prefetch instruction. */
2218 /* -mstackrealign option */
2235 /* Preferred alignment for stack boundary in bits. */
2238 /* Alignment for incoming stack boundary in bits specified at
2239 command line. */
2242 /* Default alignment for incoming stack boundary in bits. */
2245 /* Alignment for incoming stack boundary in bits. */
2248 /* Calling abi specific va_list type nodes. */
2252 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2256 /* Fence to use after loop using movnt. */
2257 tree x86_mfence;
2259 /* Register class used for passing given 64bit part of the argument.
2260 These represent classes as documented by the PS ABI, with the exception
2261 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2262 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2264 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2265 whenever possible (upper half does contain padding). */
2266 enum x86_64_reg_class
2267 {
2268 X86_64_NO_CLASS,
2269 X86_64_INTEGER_CLASS,
2270 X86_64_INTEGERSI_CLASS,
2271 X86_64_SSE_CLASS,
2272 X86_64_SSESF_CLASS,
2273 X86_64_SSEDF_CLASS,
2274 X86_64_SSEUP_CLASS,
2275 X86_64_X87_CLASS,
2276 X86_64_X87UP_CLASS,
2277 X86_64_COMPLEX_X87_CLASS,
2278 X86_64_MEMORY_CLASS
2279 };
2281 #define MAX_CLASSES 4
2283 /* Table of constants used by fldpi, fldln2, etc.... */
2287 \f
2292 const_tree);
2304 enum ix86_function_specific_strings
2305 {
2306 IX86_FUNCTION_SPECIFIC_ARCH,
2307 IX86_FUNCTION_SPECIFIC_TUNE,
2308 IX86_FUNCTION_SPECIFIC_MAX
2309 };
2327 \f
2328 #ifndef SUBTARGET32_DEFAULT_CPU
2330 #endif
2332 /* Whether -mtune= or -march= were specified */
2336 /* Vectorization library interface and handlers. */
2342 /* Processor target table, indexed by processor number */
2343 struct ptt
2344 {
2351 };
2354 {
2365 /* Core 2 */
2367 /* Core i7 */
2369 /* Core avx2 */
2381 };
2384 {
2414 "btver2"
2415 };
2416 \f
2417 static bool
2419 {
2421 }
2423 static unsigned int
2425 {
2428 /* vzeroupper instructions are inserted immediately after reload to
2429 account for possible spills from 256bit registers. The pass
2430 reuses mode switching infrastructure by re-running mode insertion
2431 pass, so disable entities that have already been processed. */
2437 /* Call optimize_mode_switching. */
2440 }
2445 {
2457 };
2460 {
2464 {}
2466 /* opt_pass methods: */
2474 rtl_opt_pass *
2476 {
2478 }
2480 /* Return true if a red-zone is in use. */
2484 {
2486 }
2487 \f
2488 /* Return a string that documents the current -m options. The caller is
2489 responsible for freeing the string. */
2495 {
2496 struct ix86_target_opts
2497 {
2500 };
2502 /* This table is ordered so that options like -msse4.2 that imply
2503 preceding options while match those first. */
2505 {
2541 };
2543 /* Flag options. */
2545 {
2573 };
2590 /* Add -march= option. */
2592 {
2595 }
2597 /* Add -mtune= option. */
2599 {
2602 }
2604 /* Add -m32/-m64/-mx32. */
2606 {
2609 else
2611 isa &= ~ (OPTION_MASK_ISA_64BIT
2612 | OPTION_MASK_ABI_64
2614 }
2615 else
2619 /* Pick out the options in isa options. */
2621 {
2623 {
2626 }
2627 }
2630 {
2633 isa);
2634 }
2636 /* Add flag options. */
2638 {
2640 {
2643 }
2644 }
2647 {
2650 }
2652 /* Add -fpmath= option. */
2654 {
2657 {
2672 }
2673 }
2675 /* Any options? */
2681 /* Size the string. */
2685 {
2690 }
2692 /* Build the string. */
2697 {
2704 {
2706 line_len++;
2709 {
2713 }
2714 }
2718 {
2722 }
2723 }
2729 }
2731 /* Return true, if profiling code should be emitted before
2732 prologue. Otherwise it returns false.
2733 Note: For x86 with "hotfix" it is sorried. */
2734 static bool
2736 {
2738 }
2740 /* Function that is callable from the debugger to print the current
2741 options. */
2742 void
2744 {
2750 {
2753 }
2754 else
2758 }
2761 #define DEF_ENUM
2762 #define DEF_ALG(alg, name) #name,
2764 #undef DEF_ENUM
2765 #undef DEF_ALG
2766 };
2768 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2769 The string is of the following form (or comma separated list of it):
2771 strategy_alg:max_size:[align|noalign]
2773 where the full size range for the strategy is either [0, max_size] or
2774 [min_size, max_size], in which min_size is the max_size + 1 of the
2775 preceding range. The last size range must have max_size == -1.
2777 Examples:
2779 1.
2780 -mmemcpy-strategy=libcall:-1:noalign
2782 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2785 2.
2786 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2788 This is to tell the compiler to use the following strategy for memset
2789 1) when the expected size is between [1, 16], use rep_8byte strategy;
2790 2) when the size is between [17, 2048], use vector_loop;
2791 3) when the size is > 2048, use libcall. */
2793 struct stringop_size_range
2794 {
2796 stringop_alg alg;
2798 };
2800 static void
2802 {
2810 else
2815 do
2816 {
2818 stringop_alg alg;
2827 {
2831 }
2834 {
2838 }
2841 {
2843 {
2846 }
2847 }
2850 {
2852 alg_name,
2855 }
2863 else
2864 {
2868 }
2869 n++;
2871 }
2875 {
2880 }
2883 {
2887 }
2889 /* Now override the default algs array. */
2891 {
2897 }
2898 }
2900 \f
2901 /* parse -mtune-ctrl= option. When DUMP is true,
2902 print the features that are explicitly set. */
2904 static void
2906 {
2914 do
2915 {
2922 {
2923 curr_feature_string++;
2925 }
2927 {
2929 {
2935 }
2936 }
2941 }
2944 }
2946 /* Helper function to set ix86_tune_features. IX86_TUNE is the
2947 processor type. */
2949 static void
2951 {
2956 {
2959 else
2961 }
2964 {
2969 }
2972 }
2975 /* Override various settings based on options. If MAIN_ARGS_P, the
2976 options are from the command line, otherwise they are from
2977 attributes. */
2979 static void
2981 {
2989 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2990 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2991 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2992 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2993 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2994 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2995 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2996 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2997 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2998 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2999 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3000 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3001 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3002 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3003 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3004 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3005 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3006 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3007 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3008 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3009 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3010 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3011 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3012 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3013 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3014 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3015 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3016 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3017 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3018 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3019 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3020 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3021 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3022 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3023 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3024 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3025 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3026 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3027 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3028 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3030 /* if this reaches 64, need to widen struct pta flags below */
3032 static struct pta
3033 {
3038 }
3040 {
3175 PTA_64BIT
3177 };
3179 /* -mrecip options. */
3180 static struct
3181 {
3184 }
3186 {
3193 };
3197 /* Set up prefix/suffix so the error messages refer to either the command
3198 line argument, or the attribute(target). */
3200 {
3204 }
3205 else
3206 {
3210 }
3212 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3213 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3216 #ifdef TARGET_BI_ARCH
3217 else
3218 {
3219 #if TARGET_BI_ARCH == 1
3220 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3221 is on and OPTION_MASK_ABI_X32 is off. We turn off
3222 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3223 -mx32. */
3226 #else
3227 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3228 on and OPTION_MASK_ABI_64 is off. We turn off
3229 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3230 -m64. */
3233 #endif
3234 }
3235 #endif
3238 {
3239 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3240 OPTION_MASK_ABI_64 for TARGET_X32. */
3243 }
3245 {
3246 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3247 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3250 }
3252 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3253 SUBTARGET_OVERRIDE_OPTIONS;
3254 #endif
3256 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3257 SUBSUBTARGET_OVERRIDE_OPTIONS;
3258 #endif
3260 /* -fPIC is the default for x86_64. */
3264 /* Need to check -mtune=generic first. */
3266 {
3269 /* As special support for cross compilers we read -mtune=native
3270 as -mtune=generic. With native compilers we won't see the
3271 -mtune=native, as it was changed by the driver. */
3273 {
3276 else
3278 }
3279 /* If this call is for setting the option attribute, allow the
3280 generic32/generic64 that was previously set. */
3284 ;
3292 }
3293 else
3294 {
3298 {
3301 }
3303 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3304 need to use a sensible tune option. */
3308 {
3311 else
3313 }
3314 }
3317 {
3318 /* rep; movq isn't available in 32-bit code. */
3321 }
3325 else
3329 {
3335 }
3336 else
3343 {
3345 {
3389 {
3392 }
3400 }
3401 }
3402 else
3403 {
3404 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3405 use of rip-relative addressing. This eliminates fixups that
3406 would otherwise be needed if this object is to be placed in a
3407 DLL, and is essentially just as efficient as direct addressing. */
3412 else
3414 }
3416 {
3419 }
3426 {
3429 /* Default cpu tuning to the architecture. */
3554 }
3569 {
3573 {
3575 {
3577 {
3585 }
3586 else
3589 }
3590 }
3591 else
3592 {
3593 /* Adjust tuning when compiling for 32-bit ABI. */
3595 {
3603 }
3604 }
3605 /* Intel CPUs have always interpreted SSE prefetch instructions as
3606 NOPs; so, we can enable SSE prefetch instructions even when
3607 -mtune (rather than -march) points us to a processor that has them.
3608 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3609 higher processors. */
3614 }
3622 #ifndef USE_IX86_FRAME_POINTER
3623 #define USE_IX86_FRAME_POINTER 0
3624 #endif
3626 #ifndef USE_X86_64_FRAME_POINTER
3627 #define USE_X86_64_FRAME_POINTER 0
3628 #endif
3630 /* Set the default values for switches whose default depends on TARGET_64BIT
3631 in case they weren't overwritten by command line options. */
3633 {
3640 }
3641 else
3642 {
3649 }
3654 else
3657 /* Arrange to set up i386_stack_locals for all functions. */
3660 /* Validate -mregparm= value. */
3662 {
3666 {
3670 }
3671 }
3675 /* Default align_* from the processor table. */
3677 {
3680 }
3682 {
3685 }
3687 {
3689 }
3691 /* Provide default for -mbranch-cost= value. */
3696 {
3699 /* Enable by default the SSE and MMX builtins. Do allow the user to
3700 explicitly disable any of these. In particular, disabling SSE and
3701 MMX for kernel code is extremely useful. */
3703 ix86_isa_flags
3709 }
3710 else
3711 {
3715 ix86_isa_flags
3718 /* i386 ABI does not specify red zone. It still makes sense to use it
3719 when programmer takes care to stack from being destroyed. */
3722 }
3724 /* Keep nonleaf frame pointers. */
3730 /* If we're doing fast math, we don't care about comparison order
3731 wrt NaNs. This lets us use a shorter comparison sequence. */
3735 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3736 since the insns won't need emulation. */
3740 /* Likewise, if the target doesn't have a 387, or we've specified
3741 software floating point, don't use 387 inline intrinsics. */
3745 /* Turn on MMX builtins for -msse. */
3749 /* Enable SSE prefetch. */
3753 /* Enable prefetch{,w} instructions for -m3dnow. */
3757 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3761 /* Enable lzcnt instruction for -mabm. */
3765 /* Validate -mpreferred-stack-boundary= value or default it to
3766 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3769 {
3775 {
3779 else
3782 }
3783 else
3784 ix86_preferred_stack_boundary
3786 }
3788 /* Set the default value for -mstackrealign. */
3794 /* Validate -mincoming-stack-boundary= value or default it to
3795 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3798 {
3803 else
3804 {
3805 ix86_user_incoming_stack_boundary
3807 ix86_incoming_stack_boundary
3809 }
3810 }
3812 /* Accept -msseregparm only if at least SSE support is enabled. */
3818 {
3820 {
3822 {
3825 }
3827 {
3830 }
3831 }
3832 }
3833 else
3836 /* If the i387 is disabled, then do not return values in it. */
3840 /* Use external vectorized library in vectorizing intrinsics. */
3843 {
3854 }
3863 /* ??? Unwind info is not correct around the CFG unless either a frame
3864 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3865 unwind info generation to be aware of the CFG and propagating states
3866 around edges. */
3869 && flag_omit_frame_pointer
3871 {
3877 }
3879 /* If stack probes are required, the space used for large function
3880 arguments on the stack must also be probed, so enable
3881 -maccumulate-outgoing-args so this happens in the prologue. */
3884 {
3889 }
3891 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3892 {
3898 }
3900 /* When scheduling description is not available, disable scheduler pass
3901 so it won't slow down the compilation and make x87 code slower. */
3922 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3924 && HAVE_prefetch
3929 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3930 can be optimized to ap = __builtin_next_arg (0). */
3935 {
3938 {
3940 ix86_gen_tls_local_dynamic_base_64
3942 }
3943 else
3944 {
3946 ix86_gen_tls_local_dynamic_base_64
3948 }
3949 }
3950 else
3954 {
3964 }
3965 else
3966 {
3976 }
3978 #ifdef USE_IX86_CLD
3979 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3982 #endif
3985 {
3990 }
3992 {
3996 }
3998 {
3999 #if defined(PROFILE_BEFORE_PROLOGUE)
4001 #else
4003 #endif
4004 }
4006 /* When not optimize for size, enable vzeroupper optimization for
4007 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4008 AVX unaligned load/store. */
4010 {
4020 /* Enable 128-bit AVX instruction generation
4021 for the auto-vectorizer. */
4025 }
4028 {
4035 {
4038 {
4040 q++;
4041 }
4042 else
4047 else
4048 {
4051 {
4054 }
4057 {
4061 }
4062 }
4067 else
4069 }
4070 }
4077 /* Default long double to 64-bit for Bionic. */
4082 /* Save the initial options in case the user does function specific
4083 options. */
4085 target_option_default_node = target_option_current_node
4088 /* Handle stack protector */
4092 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4094 {
4098 }
4101 {
4105 }
4106 }
4108 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4110 static void
4112 {
4114 static struct register_pass_info insert_vzeroupper_info
4117 };
4122 /* This needs to be done at start up. It's convenient to do it here. */
4124 }
4126 /* Update register usage after having seen the compiler flags. */
4128 static void
4130 {
4134 /* The PIC register, if it exists, is fixed. */
4139 /* For 32-bit targets, squash the REX registers. */
4141 {
4146 }
4148 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4156 {
4157 /* Set/reset conditionally defined registers from
4158 CALL_USED_REGISTERS initializer. */
4162 /* Calculate registers of CLOBBERED_REGS register set
4163 as call used registers from GENERAL_REGS register set. */
4167 }
4169 /* If MMX is disabled, squash the registers. */
4175 /* If SSE is disabled, squash the registers. */
4181 /* If the FPU is disabled, squash the registers. */
4186 }
4188 \f
4189 /* Save the current options */
4191 static void
4193 {
4204 /* The fields are char but the variables are not; make sure the
4205 values fit in the fields. */
4210 }
4212 /* Restore the current options */
4214 static void
4216 {
4232 /* Recreate the arch feature tests if the arch changed */
4234 {
4239 }
4241 /* Recreate the tune optimization tests */
4244 }
4246 /* Print the current options */
4248 static void
4251 {
4273 {
4276 }
4277 }
4279 \f
4280 /* Inner function to process the attribute((target(...))), take an argument and
4281 set the current options from the argument. If we have a list, recursively go
4282 over the list. */
4284 static bool
4287 {
4291 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4292 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4293 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4294 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4295 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4297 enum ix86_opt_type
4298 {
4299 ix86_opt_unknown,
4300 ix86_opt_yes,
4301 ix86_opt_no,
4302 ix86_opt_str,
4303 ix86_opt_enum,
4304 ix86_opt_isa
4305 };
4307 static const struct
4308 {
4315 /* isa options */
4352 /* enum options */
4355 /* string options */
4359 /* flag options */
4361 OPT_mcld,
4362 MASK_CLD),
4365 OPT_mfancy_math_387,
4366 MASK_NO_FANCY_MATH_387),
4369 OPT_mieee_fp,
4370 MASK_IEEE_FP),
4373 OPT_minline_all_stringops,
4374 MASK_INLINE_ALL_STRINGOPS),
4377 OPT_minline_stringops_dynamically,
4378 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4381 OPT_mno_align_stringops,
4382 MASK_NO_ALIGN_STRINGOPS),
4385 OPT_mrecip,
4386 MASK_RECIP),
4388 };
4390 /* If this is a list, recurse to get the options. */
4392 {
4402 }
4405 {
4408 }
4410 /* Handle multiple arguments separated by commas. */
4414 {
4428 {
4432 }
4433 else
4434 {
4437 }
4439 /* Recognize no-xxx. */
4441 {
4445 }
4446 else
4449 /* Find the option. */
4453 {
4461 {
4466 }
4467 }
4469 /* Process the option. */
4471 {
4474 }
4477 {
4483 }
4486 {
4492 else
4494 }
4497 {
4499 {
4502 }
4503 else
4505 }
4508 {
4516 global_dc);
4517 else
4518 {
4521 }
4522 }
4524 else
4526 }
4529 }
4531 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4533 tree
4535 {
4550 /* Process each of the options on the chain. */
4555 /* If the changed options are different from the default, rerun
4556 ix86_option_override_internal, and then save the options away.
4557 The string options are are attribute options, and will be undone
4558 when we copy the save structure. */
4564 {
4565 /* If we are using the default tune= or arch=, undo the string assigned,
4566 and use the default. */
4577 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4581 {
4584 }
4586 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4589 /* Add any builtin functions with the new isa if any. */
4592 /* Save the current options unless we are validating options for
4593 #pragma. */
4600 /* Free up memory allocated to hold the strings */
4603 }
4606 }
4608 /* Hook to validate attribute((target("string"))). */
4610 static bool
4613 tree args,
4615 {
4619 /* attribute((target("default"))) does nothing, beyond
4620 affecting multi-versioning. */
4631 /* If the function changed the optimization levels as well as setting target
4632 options, start with the optimizations specified. */
4637 /* The target attributes may also change some optimization flags, so update
4638 the optimization options if necessary. */
4647 {
4652 }
4661 }
4663 \f
4664 /* Hook to determine if one function can safely inline another. */
4666 static bool
4668 {
4673 /* If callee has no option attributes, then it is ok to inline. */
4677 /* If caller has no option attributes, but callee does then it is not ok to
4678 inline. */
4682 else
4683 {
4687 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4688 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4689 function. */
4694 /* See if we have the same non-isa options. */
4698 /* See if arch, tune, etc. are the same. */
4711 else
4713 }
4716 }
4718 \f
4719 /* Remember the last target of ix86_set_current_function. */
4722 /* Invalidate ix86_previous_fndecl cache. */
4723 void
4725 {
4727 }
4729 /* Establish appropriate back-end context for processing the function
4730 FNDECL. The argument might be NULL to indicate processing at top
4731 level, outside of any function scope. */
4732 static void
4734 {
4735 /* Only change the context if the function changes. This hook is called
4736 several times in the course of compiling a function, and we don't want to
4737 slow things down too much or call target_reinit when it isn't safe. */
4739 {
4740 tree old_tree = (ix86_previous_fndecl
4744 tree new_tree = (fndecl
4750 ;
4753 {
4757 }
4760 {
4766 }
4767 }
4768 }
4770 \f
4771 /* Return true if this goes in large data/bss. */
4773 static bool
4775 {
4779 /* Functions are never large data. */
4784 {
4790 }
4791 else
4792 {
4795 /* If this is an incomplete type with size 0, then we can't put it
4796 in data because it might be too big when completed. */
4799 }
4802 }
4804 /* Switch to the appropriate section for output of DECL.
4805 DECL is either a `VAR_DECL' node or a constant of some sort.
4806 RELOC indicates whether forming the initial value of DECL requires
4807 link-time relocations. */
4810 ATTRIBUTE_UNUSED;
4815 {
4818 {
4822 {
4856 /* We don't split these for medium model. Place them into
4857 default sections and hope for best. */
4859 }
4861 {
4862 /* We might get called with string constants, but get_named_section
4863 doesn't like them as they are not DECLs. Also, we need to set
4864 flags in that case. */
4868 }
4869 }
4871 }
4873 /* Build up a unique section name, expressed as a
4874 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4875 RELOC indicates whether the initial value of EXP requires
4876 link-time relocations. */
4878 static void ATTRIBUTE_UNUSED
4880 {
4883 {
4885 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4889 {
4913 /* We don't split these for medium model. Place them into
4914 default sections and hope for best. */
4916 }
4918 {
4925 /* If we're using one_only, then there needs to be a .gnu.linkonce
4926 prefix to the section name. */
4933 }
4934 }
4936 }
4938 #ifdef COMMON_ASM_OP
4939 /* This says how to output assembler code to declare an
4940 uninitialized external linkage data object.
4942 For medium model x86-64 we need to use .largecomm opcode for
4943 large objects. */
4944 void
4948 {
4952 else
4957 }
4958 #endif
4960 /* Utility function for targets to use in implementing
4961 ASM_OUTPUT_ALIGNED_BSS. */
4963 void
4967 {
4971 else
4974 #ifdef ASM_DECLARE_OBJECT_NAME
4977 #else
4978 /* Standard thing is just output label for the object. */
4982 }
4983 \f
4984 /* Decide whether we must probe the stack before any space allocation
4985 on this target. It's essentially TARGET_STACK_PROBE except when
4986 -fstack-check causes the stack to be already probed differently. */
4988 bool
4990 {
4991 /* Do not probe the stack twice if static stack checking is enabled. */
4996 }
4997 \f
4998 /* Decide whether we can make a sibling call to a function. DECL is the
4999 declaration of the function being targeted by the call and EXP is the
5000 CALL_EXPR representing the call. */
5002 static bool
5004 {
5008 /* If we are generating position-independent code, we cannot sibcall
5009 optimize any indirect call, or a direct call to a global function,
5010 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5012 && !TARGET_64BIT
5013 && flag_pic
5017 /* If we need to align the outgoing stack, then sibcalling would
5018 unalign the stack, which may break the called function. */
5024 {
5027 }
5028 else
5029 {
5030 /* We're looking at the CALL_EXPR, we need the type of the function. */
5035 }
5037 /* Check that the return value locations are the same. Like
5038 if we are returning floats on the 80387 register stack, we cannot
5039 make a sibcall from a function that doesn't return a float to a
5040 function that does or, conversely, from a function that does return
5041 a float to a function that doesn't; the necessary stack adjustment
5042 would not be executed. This is also the place we notice
5043 differences in the return value ABI. Note that it is ok for one
5044 of the functions to have void return type as long as the return
5045 value of the other is passed in a register. */
5050 {
5053 }
5055 ;
5060 {
5061 /* The SYSV ABI has more call-clobbered registers;
5062 disallow sibcalls from MS to SYSV. */
5066 }
5067 else
5068 {
5069 /* If this call is indirect, we'll need to be able to use a
5070 call-clobbered register for the address of the target function.
5071 Make sure that all such registers are not used for passing
5072 parameters. Note that DLLIMPORT functions are indirect. */
5075 {
5077 {
5078 /* ??? Need to count the actual number of registers to be used,
5079 not the possible number of registers. Fix later. */
5081 }
5082 }
5083 }
5085 /* Otherwise okay. That also includes certain types of indirect calls. */
5087 }
5089 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5090 and "sseregparm" calling convention attributes;
5091 arguments as in struct attribute_spec.handler. */
5093 static tree
5095 tree args,
5098 {
5103 {
5105 name);
5108 }
5110 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5112 {
5113 tree cst;
5116 {
5118 }
5121 {
5123 }
5127 {
5130 name);
5132 }
5134 {
5138 }
5141 }
5144 {
5145 /* Do not warn when emulating the MS ABI. */
5150 name);
5153 }
5155 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5157 {
5159 {
5161 }
5163 {
5165 }
5167 {
5169 }
5171 {
5173 }
5174 }
5176 /* Can combine stdcall with fastcall (redundant), regparm and
5177 sseregparm. */
5179 {
5181 {
5183 }
5185 {
5187 }
5189 {
5191 }
5192 }
5194 /* Can combine cdecl with regparm and sseregparm. */
5196 {
5198 {
5200 }
5202 {
5204 }
5206 {
5208 }
5209 }
5211 {
5214 name);
5216 {
5218 }
5220 {
5222 }
5224 {
5226 }
5227 }
5229 /* Can combine sseregparm with all attributes. */
5232 }
5234 /* The transactional memory builtins are implicitly regparm or fastcall
5235 depending on the ABI. Override the generic do-nothing attribute that
5236 these builtins were declared with, and replace it with one of the two
5237 attributes that we expect elsewhere. */
5239 static tree
5241 tree args ATTRIBUTE_UNUSED,
5244 {
5245 tree alt;
5247 /* In no case do we want to add the placeholder attribute. */
5250 /* The 64-bit ABI is unchanged for transactional memory. */
5254 /* ??? Is there a better way to validate 32-bit windows? We have
5255 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5258 else
5259 {
5262 }
5266 }
5268 /* This function determines from TYPE the calling-convention. */
5270 unsigned int
5272 {
5275 tree attrs;
5282 {
5292 /* Regparam isn't allowed for thiscall and fastcall. */
5294 {
5299 }
5303 }
5310 || is_stdarg
5316 }
5318 /* Return 0 if the attributes for two types are incompatible, 1 if they
5319 are compatible, and 2 if they are nearly compatible (which causes a
5320 warning to be generated). */
5322 static int
5324 {
5340 }
5341 \f
5342 /* Return the regparm value for a function with the indicated TYPE and DECL.
5343 DECL may be NULL when calling function indirectly
5344 or considering a libcall. */
5346 static int
5348 {
5349 tree attr;
5360 {
5363 {
5366 }
5367 }
5373 /* Use register calling convention for local functions when possible. */
5376 && optimize
5378 {
5379 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5382 {
5385 /* Make sure no regparm register is taken by a
5386 fixed register variable. */
5391 /* We don't want to use regparm(3) for nested functions as
5392 these use a static chain pointer in the third argument. */
5396 /* In 32-bit mode save a register for the split stack. */
5400 /* Each fixed register usage increases register pressure,
5401 so less registers should be used for argument passing.
5402 This functionality can be overriden by an explicit
5403 regparm value. */
5406 globals++;
5408 local_regparm
5413 }
5414 }
5417 }
5419 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5420 DFmode (2) arguments in SSE registers for a function with the
5421 indicated TYPE and DECL. DECL may be NULL when calling function
5422 indirectly or considering a libcall. Otherwise return 0. */
5424 static int
5426 {
5429 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5430 by the sseregparm attribute. */
5433 {
5435 {
5437 {
5441 else
5444 }
5446 }
5449 }
5451 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5452 (and DFmode for SSE2) arguments in SSE registers. */
5455 {
5456 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5460 }
5463 }
5465 /* Return true if EAX is live at the start of the function. Used by
5466 ix86_expand_prologue to determine if we need special help before
5467 calling allocate_stack_worker. */
5469 static bool
5471 {
5472 /* Cheat. Don't bother working forward from ix86_function_regparm
5473 to the function type to whether an actual argument is located in
5474 eax. Instead just look at cfg info, which is still close enough
5475 to correct at this point. This gives false positives for broken
5476 functions that might use uninitialized data that happens to be
5477 allocated in eax, but who cares? */
5479 }
5481 static bool
5483 {
5484 tree attr;
5487 {
5493 /* For 32-bit MS-ABI the default is to keep aggregate
5494 return pointer. */
5497 }
5499 }
5501 /* Value is the number of bytes of arguments automatically
5502 popped when returning from a subroutine call.
5503 FUNDECL is the declaration node of the function (as a tree),
5504 FUNTYPE is the data type of the function (as a tree),
5505 or for a library call it is an identifier node for the subroutine name.
5506 SIZE is the number of bytes of arguments passed on the stack.
5508 On the 80386, the RTD insn may be used to pop them if the number
5509 of args is fixed, but if the number is variable then the caller
5510 must pop them all. RTD can't be used for library calls now
5511 because the library is compiled with the Unix compiler.
5512 Use of RTD is a selectable option, since it is incompatible with
5513 standard Unix calling sequences. If the option is not selected,
5514 the caller must always pop the args.
5516 The attribute stdcall is equivalent to RTD on a per module basis. */
5518 static int
5520 {
5523 /* None of the 64-bit ABIs pop arguments. */
5534 /* Lose any fake structure return argument if it is passed on the stack. */
5537 {
5541 }
5544 }
5546 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5548 static bool
5550 {
5551 /* Check operand constraints in case hard registers were propagated
5552 into insn pattern. This check prevents combine pass from
5553 generating insn patterns with invalid hard register operands.
5554 These invalid insns can eventually confuse reload to error out
5555 with a spill failure. See also PRs 46829 and 46843. */
5557 {
5564 {
5572 /* A unary operator may be accepted by the predicate, but it
5573 is irrelevant for matching constraints. */
5578 {
5586 }
5593 /* Operand has no constraints, anything is OK. */
5597 {
5600 && operands_match_p
5604 {
5607 }
5608 }
5612 }
5613 }
5616 }
5617 \f
5618 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5620 static unsigned HOST_WIDE_INT
5622 {
5626 }
5627 \f
5628 /* Argument support functions. */
5630 /* Return true when register may be used to pass function parameters. */
5631 bool
5633 {
5638 {
5642 else
5648 }
5651 {
5654 }
5655 else
5656 {
5660 }
5662 /* TODO: The function should depend on current function ABI but
5663 builtins.c would need updating then. Therefore we use the
5664 default ABI. */
5666 /* RAX is used as hidden argument to va_arg functions. */
5672 else
5679 }
5681 /* Return if we do not know how to pass TYPE solely in registers. */
5683 static bool
5685 {
5689 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5690 The layout_type routine is crafty and tries to trick us into passing
5691 currently unsupported vector types on the stack by using TImode. */
5694 }
5696 /* It returns the size, in bytes, of the area reserved for arguments passed
5697 in registers for the function represented by fndecl dependent to the used
5698 abi format. */
5699 int
5701 {
5705 else
5710 }
5712 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5713 call abi used. */
5714 enum calling_abi
5716 {
5718 {
5721 {
5724 }
5728 }
5730 }
5732 static bool
5734 {
5736 {
5740 else
5742 }
5744 }
5746 static enum calling_abi
5748 {
5752 }
5754 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5755 call abi used. */
5756 enum calling_abi
5758 {
5762 }
5764 /* Write the extra assembler code needed to declare a function properly. */
5766 void
5768 tree decl)
5769 {
5773 {
5779 }
5781 #ifdef SUBTARGET_ASM_UNWIND_INIT
5783 #endif
5787 /* Output magic byte marker, if hot-patch attribute is set. */
5789 {
5791 {
5792 /* leaq [%rsp + 0], %rsp */
5795 }
5796 else
5797 {
5798 /* movl.s %edi, %edi
5799 push %ebp
5800 movl.s %esp, %ebp */
5803 }
5804 }
5805 }
5807 /* regclass.c */
5810 /* Implementation of call abi switching target hook. Specific to FNDECL
5811 the specific call register sets are set. See also
5812 ix86_conditional_register_usage for more details. */
5813 void
5815 {
5818 else
5820 }
5822 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5823 expensive re-initialization of init_regs each time we switch function context
5824 since this is needed only during RTL expansion. */
5825 static void
5827 {
5831 }
5833 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5834 for a call to a function whose data type is FNTYPE.
5835 For a library call, FNTYPE is 0. */
5837 void
5841 tree fndecl,
5843 {
5849 {
5852 }
5853 else
5854 {
5857 }
5861 /* Set up the number of registers to use for passing arguments. */
5868 {
5870 ? X86_64_REGPARM_MAX
5872 }
5874 {
5877 {
5879 ? X86_64_SSE_REGPARM_MAX
5881 }
5882 }
5889 /* Because type might mismatch in between caller and callee, we need to
5890 use actual type of function for local calls.
5891 FIXME: cgraph_analyze can be told to actually record if function uses
5892 va_start so for local functions maybe_vaarg can be made aggressive
5893 helping K&R code.
5894 FIXME: once typesytem is fixed, we won't need this code anymore. */
5902 {
5903 /* If there are variable arguments, then we won't pass anything
5904 in registers in 32-bit mode. */
5906 {
5914 }
5916 /* Use ecx and edx registers if function has fastcall attribute,
5917 else look for regparm information. */
5919 {
5922 {
5925 }
5927 {
5930 }
5931 else
5933 }
5935 /* Set up the number of SSE registers used for passing SFmode
5936 and DFmode arguments. Warn for mismatching ABI. */
5938 }
5939 }
5941 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5942 But in the case of vector types, it is some vector mode.
5944 When we have only some of our vector isa extensions enabled, then there
5945 are some modes for which vector_mode_supported_p is false. For these
5946 modes, the generic vector support in gcc will choose some non-vector mode
5947 in order to implement the type. By computing the natural mode, we'll
5948 select the proper ABI location for the operand and not depend on whatever
5949 the middle-end decides to do with these vector types.
5951 The midde-end can't deal with the vector types > 16 bytes. In this
5952 case, we return the original mode and warn ABI change if CUM isn't
5953 NULL. */
5955 static enum machine_mode
5957 {
5961 {
5964 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5966 {
5971 else
5974 /* Get the mode which has this inner mode and number of units. */
5978 {
5980 {
5984 && !warnedavx
5986 {
5990 }
5992 }
5994 {
5998 && !warnedsse
6000 {
6004 }
6006 }
6007 else
6009 }
6012 }
6013 }
6016 }
6018 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6019 this may not agree with the mode that the type system has chosen for the
6020 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6021 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6023 static rtx
6026 {
6027 rtx tmp;
6031 else
6032 {
6036 }
6039 }
6041 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6042 of this code is to classify each 8bytes of incoming argument by the register
6043 class and assign registers accordingly. */
6045 /* Return the union class of CLASS1 and CLASS2.
6046 See the x86-64 PS ABI for details. */
6048 static enum x86_64_reg_class
6050 {
6051 /* Rule #1: If both classes are equal, this is the resulting class. */
6055 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6056 the other class. */
6062 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6066 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6074 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6075 MEMORY is used. */
6084 /* Rule #6: Otherwise class SSE is used. */
6086 }
6088 /* Classify the argument of type TYPE and mode MODE.
6089 CLASSES will be filled by the register class used to pass each word
6090 of the operand. The number of words is returned. In case the parameter
6091 should be passed in memory, 0 is returned. As a special case for zero
6092 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6094 BIT_OFFSET is used internally for handling records and specifies offset
6095 of the offset in bits modulo 256 to avoid overflow cases.
6097 See the x86-64 PS ABI for details.
6098 */
6100 static int
6103 {
6104 HOST_WIDE_INT bytes =
6106 int words
6109 /* Variable sized entities are always passed/returned in memory. */
6118 {
6120 tree field;
6123 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
6130 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6131 signalize memory class, so handle it as special case. */
6133 {
6136 }
6138 /* Classify each field of record and merge classes. */
6140 {
6142 /* And now merge the fields of structure. */
6144 {
6146 {
6152 /* Bitfields are always classified as integer. Handle them
6153 early, since later code would consider them to be
6154 misaligned integers. */
6156 {
6165 }
6166 else
6167 {
6172 /* Flexible array member is ignored. */
6179 {
6183 {
6186 "the ABI of passing struct with"
6187 " a flexible array member has"
6189 }
6191 }
6193 subclasses,
6203 }
6204 }
6205 }
6209 /* Arrays are handled as small records. */
6210 {
6217 /* The partial classes are now full classes. */
6228 }
6231 /* Unions are similar to RECORD_TYPE but offset is always 0.
6232 */
6234 {
6236 {
6244 bit_offset);
6249 }
6250 }
6255 }
6258 {
6259 /* When size > 16 bytes, if the first one isn't
6260 X86_64_SSE_CLASS or any other ones aren't
6261 X86_64_SSEUP_CLASS, everything should be passed in
6262 memory. */
6269 }
6271 /* Final merger cleanup. */
6273 {
6274 /* If one class is MEMORY, everything should be passed in
6275 memory. */
6279 /* The X86_64_SSEUP_CLASS should be always preceded by
6280 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6284 {
6285 /* The first one should never be X86_64_SSEUP_CLASS. */
6288 }
6290 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6291 everything should be passed in memory. */
6294 {
6297 /* The first one should never be X86_64_X87UP_CLASS. */
6300 {
6303 "the ABI of passing union with long double"
6305 }
6307 }
6308 }
6310 }
6312 /* Compute alignment needed. We align all types to natural boundaries with
6313 exception of XFmode that is aligned to 64bits. */
6315 {
6324 /* Misaligned fields are always returned in memory. */
6327 }
6329 /* for V1xx modes, just use the base mode */
6334 /* Classification of atomic types. */
6336 {
6352 {
6356 {
6359 }
6361 {
6364 }
6366 {
6370 }
6372 {
6375 }
6376 else
6378 }
6385 /* OImode shouldn't be used directly. */
6392 else
6410 else
6411 {
6415 {
6418 "the ABI of passing structure with complex float"
6420 }
6423 }
6432 /* This modes is larger than 16 bytes. */
6475 else
6479 }
6480 }
6482 /* Examine the argument and return set number of register required in each
6483 class. Return 0 iff parameter should be passed in memory. */
6484 static int
6487 {
6497 {
6519 }
6521 }
6523 /* Construct container for the argument used by GCC interface. See
6524 FUNCTION_ARG for the detailed description. */
6526 static rtx
6530 {
6531 /* The following variables hold the static issued_error state. */
6545 rtx ret;
6556 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6557 some less clueful developer tries to use floating-point anyway. */
6559 {
6561 {
6563 {
6566 }
6567 }
6569 {
6572 }
6574 }
6576 /* Likewise, error if the ABI requires us to return values in the
6577 x87 registers and the user specified -mno-80387. */
6583 {
6585 {
6588 }
6590 }
6592 /* First construct simple cases. Avoid SCmode, since we want to use
6593 single register to pass this type. */
6596 {
6611 /* Zero sized array, struct or class. */
6615 }
6642 /* Otherwise figure out the entries of the PARALLEL. */
6644 {
6648 {
6653 /* Merge TImodes on aligned occasions here too. */
6655 tmpmode
6659 else
6661 /* We've requested 24 bytes we
6662 don't have mode for. Use DImode. */
6669 intreg++;
6677 sse_regno++;
6685 sse_regno++;
6690 {
6696 {
6698 i++;
6699 }
6700 else
6713 }
6719 sse_regno++;
6723 }
6724 }
6726 /* Empty aligned struct, union or class. */
6734 }
6736 /* Update the data in CUM to advance over an argument of mode MODE
6737 and data type TYPE. (TYPE is null for libcalls where that information
6738 may not be available.) */
6740 static void
6743 HOST_WIDE_INT words)
6744 {
6746 {
6753 /* FALLTHRU */
6764 {
6767 }
6771 /* OImode shouldn't be used directly. */
6780 /* FALLTHRU */
6796 {
6801 {
6804 }
6805 }
6815 {
6820 {
6823 }
6824 }
6826 }
6827 }
6829 static void
6832 {
6835 /* Unnamed 256bit vector mode parameters are passed on stack. */
6841 {
6846 }
6847 else
6848 {
6852 }
6853 }
6855 static void
6857 HOST_WIDE_INT words)
6858 {
6859 /* Otherwise, this should be passed indirect. */
6864 {
6867 }
6868 }
6870 /* Update the data in CUM to advance over an argument of mode MODE and
6871 data type TYPE. (TYPE is null for libcalls where that information
6872 may not be available.) */
6874 static void
6877 {
6883 else
6894 else
6896 }
6898 /* Define where to put the arguments to a function.
6899 Value is zero to push the argument on the stack,
6900 or a hard register in which to store the argument.
6902 MODE is the argument's machine mode.
6903 TYPE is the data type of the argument (as a tree).
6904 This is null for libcalls where that information may
6905 not be available.
6906 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6907 the preceding args and about the function being called.
6908 NAMED is nonzero if this argument is a named parameter
6909 (otherwise it is an extra parameter matching an ellipsis). */
6911 static rtx
6915 {
6918 /* Avoid the AL settings for the Unix64 ABI. */
6923 {
6930 /* FALLTHRU */
6936 {
6939 /* Fastcall allocates the first two DWORD (SImode) or
6940 smaller arguments to ECX and EDX if it isn't an
6941 aggregate type . */
6943 {
6949 /* ECX not EAX is the first allocated register. */
6952 }
6954 }
6963 /* FALLTHRU */
6965 /* In 32bit, we pass TImode in xmm registers. */
6973 {
6975 {
6979 }
6983 }
6987 /* OImode shouldn't be used directly. */
6997 {
7001 }
7011 {
7013 {
7017 }
7021 }
7023 }
7026 }
7028 static rtx
7031 {
7032 /* Handle a hidden AL argument containing number of registers
7033 for varargs x86-64 functions. */
7037 ? X86_64_SSE_REGPARM_MAX
7042 {
7052 /* Unnamed 256bit vector mode parameters are passed on stack. */
7056 }
7062 }
7064 static rtx
7067 HOST_WIDE_INT bytes)
7068 {
7071 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7072 We use value of -2 to specify that current function call is MSABI. */
7076 /* If we've run out of registers, it goes on the stack. */
7082 /* Only floating point modes are passed in anything but integer regs. */
7084 {
7087 else
7088 {
7091 /* Unnamed floating parameters are passed in both the
7092 SSE and integer registers. */
7098 }
7099 }
7100 /* Handle aggregated types passed in register. */
7102 {
7107 }
7110 }
7112 /* Return where to put the arguments to a function.
7113 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7115 MODE is the argument's machine mode. TYPE is the data type of the
7116 argument. It is null for libcalls where that information may not be
7117 available. CUM gives information about the preceding args and about
7118 the function being called. NAMED is nonzero if this argument is a
7119 named parameter (otherwise it is an extra parameter matching an
7120 ellipsis). */
7122 static rtx
7125 {
7129 rtx arg;
7133 else
7137 /* To simplify the code below, represent vector types with a vector mode
7138 even if MMX/SSE are not active. */
7146 else
7150 }
7152 /* A C expression that indicates when an argument must be passed by
7153 reference. If nonzero for an argument, a copy of that argument is
7154 made in memory and a pointer to the argument is passed instead of
7155 the argument itself. The pointer is passed in whatever way is
7156 appropriate for passing a pointer to that type. */
7158 static bool
7162 {
7165 /* See Windows x64 Software Convention. */
7167 {
7170 {
7171 /* Arrays are passed by reference. */
7176 {
7177 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7178 are passed by reference. */
7180 }
7181 }
7183 /* __m128 is passed by reference. */
7189 }
7190 }
7195 }
7197 /* Return true when TYPE should be 128bit aligned for 32bit argument
7198 passing ABI. XXX: This function is obsolete and is only used for
7199 checking psABI compatibility with previous versions of GCC. */
7201 static bool
7203 {
7215 {
7216 /* Walk the aggregates recursively. */
7218 {
7222 {
7223 tree field;
7225 /* Walk all the structure fields. */
7227 {
7231 }
7233 }
7236 /* Just for use if some languages passes arrays by value. */
7243 }
7244 }
7246 }
7248 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7249 XXX: This function is obsolete and is only used for checking psABI
7250 compatibility with previous versions of GCC. */
7252 static unsigned int
7255 {
7256 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7257 natural boundaries. */
7259 {
7260 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7261 make an exception for SSE modes since these require 128bit
7262 alignment.
7264 The handling here differs from field_alignment. ICC aligns MMX
7265 arguments to 4 byte boundaries, while structure fields are aligned
7266 to 8 byte boundaries. */
7268 {
7271 }
7272 else
7273 {
7276 }
7277 }
7281 }
7283 /* Return true when TYPE should be 128bit aligned for 32bit argument
7284 passing ABI. */
7286 static bool
7288 {
7298 {
7299 /* Walk the aggregates recursively. */
7301 {
7305 {
7306 tree field;
7308 /* Walk all the structure fields. */
7310 field;
7312 {
7316 }
7318 }
7321 /* Just for use if some languages passes arrays by value. */
7328 }
7329 }
7330 else
7334 }
7336 /* Gives the alignment boundary, in bits, of an argument with the
7337 specified mode and type. */
7339 static unsigned int
7341 {
7344 {
7345 /* Since the main variant type is used for call, we convert it to
7346 the main variant type. */
7349 }
7350 else
7354 else
7355 {
7360 {
7361 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7363 {
7366 }
7372 }
7375 && !warned
7377 saved_align))
7378 {
7381 "The ABI for passing parameters with %d-byte"
7384 }
7385 }
7388 }
7390 /* Return true if N is a possible register number of function value. */
7392 static bool
7394 {
7396 {
7401 /* TODO: The function should depend on current function ABI but
7402 builtins.c would need updating then. Therefore we use the
7403 default ABI. */
7415 }
7418 }
7420 /* Define how to find the value returned by a function.
7421 VALTYPE is the data type of the value (as a tree).
7422 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7423 otherwise, FUNC is 0. */
7425 static rtx
7428 {
7431 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7432 we normally prevent this case when mmx is not available. However
7433 some ABIs may require the result to be returned like DImode. */
7437 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7438 we prevent this case when sse is not available. However some ABIs
7439 may require the result to be returned like integer TImode. */
7444 /* 32-byte vector modes in %ymm0. */
7448 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7451 else
7452 /* Most things go in %eax. */
7455 /* Override FP return register with %xmm0 for local functions when
7456 SSE math is enabled or for functions with sseregparm attribute. */
7458 {
7463 }
7465 /* OImode shouldn't be used directly. */
7469 }
7471 static rtx
7473 const_tree valtype)
7474 {
7475 rtx ret;
7477 /* Handle libcalls, which don't provide a type node. */
7479 {
7483 {
7502 }
7505 }
7507 {
7508 /* Pointers are always returned in word_mode. */
7510 }
7516 /* For zero sized structures, construct_container returns NULL, but we
7517 need to keep rest of compiler happy by returning meaningful value. */
7522 }
7524 static rtx
7526 const_tree valtype)
7527 {
7531 {
7533 {
7552 }
7553 }
7555 }
7557 static rtx
7560 {
7572 else
7574 }
7576 static rtx
7579 {
7585 }
7587 /* Pointer function arguments and return values are promoted to
7588 word_mode. */
7590 static enum machine_mode
7594 {
7596 {
7599 }
7601 for_return);
7602 }
7604 /* Return true if a structure, union or array with MODE containing FIELD
7605 should be accessed using BLKmode. */
7607 static bool
7609 {
7610 /* Union with XFmode must be in BLKmode. */
7614 }
7616 rtx
7618 {
7620 }
7622 /* Return true iff type is returned in memory. */
7624 static bool ATTRIBUTE_UNUSED
7626 {
7627 HOST_WIDE_INT size;
7638 {
7639 /* User-created vectors small enough to fit in EAX. */
7643 /* MMX/3dNow values are returned in MM0,
7644 except when it doesn't exits or the ABI prescribes otherwise. */
7648 /* SSE values are returned in XMM0, except when it doesn't exist. */
7652 /* AVX values are returned in YMM0, except when it doesn't exist. */
7655 }
7663 /* OImode shouldn't be used directly. */
7667 }
7669 static bool ATTRIBUTE_UNUSED
7671 {
7674 }
7676 static bool ATTRIBUTE_UNUSED
7678 {
7681 /* __m128 is returned in xmm0. */
7688 /* Otherwise, the size must be exactly in [1248]. */
7690 }
7692 static bool
7694 {
7695 #ifdef SUBTARGET_RETURN_IN_MEMORY
7697 #else
7701 {
7704 else
7706 }
7707 else
7709 #endif
7710 }
7712 /* When returning SSE vector types, we have a choice of either
7713 (1) being abi incompatible with a -march switch, or
7714 (2) generating an error.
7715 Given no good solution, I think the safest thing is one warning.
7716 The user won't be able to use -Werror, but....
7718 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7719 called in response to actually generating a caller or callee that
7720 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7721 via aggregate_value_p for general type probing from tree-ssa. */
7723 static rtx
7725 {
7729 {
7730 /* Look at the return type of the function, not the function type. */
7734 {
7737 {
7741 }
7742 }
7745 {
7747 {
7751 }
7752 }
7753 }
7756 }
7758 \f
7759 /* Create the va_list data type. */
7761 /* Returns the calling convention specific va_list date type.
7762 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7764 static tree
7766 {
7769 /* For i386 we use plain pointer to argument area. */
7779 unsigned_type_node);
7782 unsigned_type_node);
7785 ptr_type_node);
7788 ptr_type_node);
7807 /* The correct type is an array type of one element. */
7809 }
7811 /* Setup the builtin va_list data type and for 64-bit the additional
7812 calling convention specific va_list data types. */
7814 static tree
7816 {
7819 /* Initialize abi specific va_list builtin types. */
7821 {
7822 tree t;
7824 {
7829 }
7830 else
7831 {
7836 }
7838 {
7843 }
7844 else
7845 {
7850 }
7851 }
7854 }
7856 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7858 static void
7860 {
7862 alias_set_type set;
7865 /* GPR size of varargs save area. */
7868 else
7871 /* FPR size of varargs save area. We don't need it if we don't pass
7872 anything in SSE registers. */
7875 else
7889 {
7897 }
7900 {
7904 /* Now emit code to save SSE registers. The AX parameter contains number
7905 of SSE parameter registers used to call this function, though all we
7906 actually check here is the zero/non-zero status. */
7911 label));
7913 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7914 we used movdqa (i.e. TImode) instead? Perhaps even better would
7915 be if we could determine the real mode of the data, via a hook
7916 into pass_stdarg. Ignore all that for now. */
7926 {
7935 }
7938 }
7939 }
7941 static void
7943 {
7947 /* Reset to zero, as there might be a sysv vaarg used
7948 before. */
7953 {
7964 }
7965 }
7967 static void
7971 {
7973 CUMULATIVE_ARGS next_cum;
7974 tree fntype;
7976 /* This argument doesn't appear to be used anymore. Which is good,
7977 because the old code here didn't suppress rtl generation. */
7985 /* For varargs, we do not want to skip the dummy va_dcl argument.
7986 For stdargs, we do want to skip the last named argument. */
7994 else
7996 }
7998 /* Checks if TYPE is of kind va_list char *. */
8000 static bool
8002 {
8003 tree canonic;
8005 /* For 32-bit it is always true. */
8011 }
8013 /* Implement va_start. */
8015 static void
8017 {
8021 tree type;
8022 rtx ovf_rtx;
8026 {
8029 /* When we are splitting the stack, we can't refer to the stack
8030 arguments using internal_arg_pointer, because they may be on
8031 the old stack. The split stack prologue will arrange to
8032 leave a pointer to the old stack arguments in a scratch
8033 register, which we here copy to a pseudo-register. The split
8034 stack prologue can't set the pseudo-register directly because
8035 it (the prologue) runs before any registers have been saved. */
8039 {
8053 }
8054 }
8056 /* Only 64bit target needs something special. */
8058 {
8061 else
8062 {
8071 }
8073 }
8082 /* The following should be folded into the MEM_REF offset. */
8092 /* Count number of gp and fp argument registers used. */
8098 {
8104 }
8107 {
8113 }
8115 /* Find the overflow area. */
8119 else
8129 {
8130 /* Find the register save area.
8131 Prologue of the function save it right above stack frame. */
8139 }
8140 }
8142 /* Implement va_arg. */
8144 static tree
8147 {
8154 rtx container;
8156 tree ptrtype;
8160 /* Only 64bit target needs something special. */
8184 {
8191 /* Unnamed 256bit vector mode parameters are passed on stack. */
8193 {
8196 }
8204 }
8206 /* Pull the value out of the saved registers. */
8211 {
8225 /* In case we are passing structure, verify that it is consecutive block
8226 on the register save area. If not we need to do moves. */
8228 {
8229 /* Verify that all registers are strictly consecutive */
8231 {
8235 {
8240 }
8241 }
8242 else
8243 {
8247 {
8252 }
8253 }
8254 }
8256 {
8259 }
8260 else
8261 {
8264 }
8266 /* First ensure that we fit completely in registers. */
8268 {
8275 }
8277 {
8285 }
8287 /* Compute index to start of area used for integer regs. */
8289 {
8290 /* int_addr = gpr + sav; */
8293 }
8295 {
8296 /* sse_addr = fpr + sav; */
8299 }
8301 {
8305 /* addr = &temp; */
8310 {
8314 tree piece_type;
8315 tree addr_type;
8316 tree daddr_type;
8325 {
8330 }
8334 else
8341 {
8344 }
8345 else
8346 {
8349 }
8356 {
8361 }
8362 else
8363 {
8364 tree copy
8369 }
8371 }
8372 }
8375 {
8379 }
8382 {
8386 }
8391 }
8393 /* ... otherwise out of the overflow area. */
8395 /* When we align parameter on stack for caller, if the parameter
8396 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8397 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8398 here with caller. */
8403 /* Care for on-stack alignment if needed. */
8406 else
8407 {
8412 }
8429 }
8430 \f
8431 /* Return true if OPNUM's MEM should be matched
8432 in movabs* patterns. */
8434 bool
8436 {
8448 }
8449 \f
8450 /* Initialize the table of extra 80387 mathematical constants. */
8452 static void
8454 {
8456 {
8462 };
8466 {
8468 /* Ensure each constant is rounded to XFmode precision. */
8471 }
8474 }
8476 /* Return non-zero if the constant is something that
8477 can be loaded with a special instruction. */
8479 int
8481 {
8484 REAL_VALUE_TYPE r;
8496 /* For XFmode constants, try to find a special 80387 instruction when
8497 optimizing for size or on those CPUs that benefit from them. */
8500 {
8509 }
8511 /* Load of the constant -0.0 or -1.0 will be split as
8512 fldz;fchs or fld1;fchs sequence. */
8519 }
8521 /* Return the opcode of the special instruction to be used to load
8522 the constant X. */
8526 {
8528 {
8548 }
8549 }
8551 /* Return the CONST_DOUBLE representing the 80387 constant that is
8552 loaded by the specified special instruction. The argument IDX
8553 matches the return value from standard_80387_constant_p. */
8555 rtx
8557 {
8564 {
8575 }
8578 XFmode);
8579 }
8581 /* Return 1 if X is all 0s and 2 if x is all 1s
8582 in supported SSE/AVX vector mode. */
8584 int
8586 {
8593 {
8608 }
8611 }
8613 /* Return the opcode of the special instruction to be used to load
8614 the constant X. */
8618 {
8620 {
8623 {
8640 }
8645 else
8650 }
8652 }
8654 /* Returns true if OP contains a symbol reference */
8656 bool
8658 {
8667 {
8669 {
8675 }
8679 }
8682 }
8684 /* Return true if it is appropriate to emit `ret' instructions in the
8685 body of a function. Do this only if the epilogue is simple, needing a
8686 couple of insns. Prior to reloading, we can't tell how many registers
8687 must be saved, so return false then. Return false if there is no frame
8688 marker to de-allocate. */
8690 bool
8692 {
8698 /* Don't allow more than 32k pop, since that's all we can do
8699 with one instruction. */
8706 }
8707 \f
8708 /* Value should be nonzero if functions must have frame pointers.
8709 Zero means the frame pointer need not be set up (and parms may
8710 be accessed via the stack pointer) in functions that seem suitable. */
8712 static bool
8714 {
8715 /* If we accessed previous frames, then the generated code expects
8716 to be able to access the saved ebp value in our frame. */
8720 /* Several x86 os'es need a frame pointer for other reasons,
8721 usually pertaining to setjmp. */
8725 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8729 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8730 allocation is 4GB. */
8734 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8735 turns off the frame pointer by default. Turn it back on now if
8736 we've not got a leaf function. */
8746 }
8748 /* Record that the current function accesses previous call frames. */
8750 void
8752 {
8754 }
8755 \f
8756 #ifndef USE_HIDDEN_LINKONCE
8757 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8758 # define USE_HIDDEN_LINKONCE 1
8759 # else
8760 # define USE_HIDDEN_LINKONCE 0
8761 # endif
8762 #endif
8766 /* Fills in the label name that should be used for a pc thunk for
8767 the given register. */
8769 static void
8771 {
8776 else
8778 }
8781 /* This function generates code for -fpic that loads %ebx with
8782 the return address of the caller and then returns. */
8784 static void
8786 {
8791 {
8793 tree decl;
8809 #if TARGET_MACHO
8811 {
8820 }
8821 else
8822 #endif
8824 {
8835 }
8836 else
8837 {
8840 }
8846 /* Make sure unwind info is emitted for the thunk if needed. */
8849 /* Pad stack IP move with 4 instructions (two NOPs count
8850 as one instruction). */
8852 {
8857 }
8868 }
8872 }
8874 /* Emit code for the SET_GOT patterns. */
8878 {
8884 {
8885 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8890 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8891 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8892 an unadorned address. */
8897 }
8902 {
8904 /* We don't need a pic base, we're not producing pic. */
8911 }
8912 else
8913 {
8922 #if TARGET_MACHO
8923 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
8924 This is what will be referenced by the Mach-O PIC subsystem. */
8928 /* When we are restoring the pic base at the site of a nonlocal label,
8929 and we decided to emit the pic base above, we will still output a
8930 local label used for calculating the correction offset (even though
8931 the offset will be 0 in that case). */
8935 #endif
8936 }
8942 }
8944 /* Generate an "push" pattern for input ARG. */
8946 static rtx
8948 {
8961 stack_pointer_rtx)),
8962 arg);
8963 }
8965 /* Generate an "pop" pattern for input ARG. */
8967 static rtx
8969 {
8974 arg,
8977 stack_pointer_rtx)));
8978 }
8980 /* Return >= 0 if there is an unused call-clobbered register available
8981 for the entire function. */
8983 static unsigned int
8985 {
8989 {
8991 /* Can't use the same register for both PIC and DRAP. */
8994 else
8999 }
9002 }
9004 /* Return TRUE if we need to save REGNO. */
9006 static bool
9008 {
9019 {
9022 {
9028 }
9029 }
9038 }
9040 /* Return number of saved general prupose registers. */
9042 static int
9044 {
9050 nregs ++;
9052 }
9054 /* Return number of saved SSE registrers. */
9056 static int
9058 {
9066 nregs ++;
9068 }
9070 /* Given FROM and TO register numbers, say whether this elimination is
9071 allowed. If stack alignment is needed, we can only replace argument
9072 pointer with hard frame pointer, or replace frame pointer with stack
9073 pointer. Otherwise, frame pointer elimination is automatically
9074 handled and all other eliminations are valid. */
9076 static bool
9078 {
9084 else
9086 }
9088 /* Return the offset between two registers, one to be eliminated, and the other
9089 its replacement, at the start of a routine. */
9091 HOST_WIDE_INT
9093 {
9102 else
9103 {
9111 }
9112 }
9114 /* In a dynamically-aligned function, we can't know the offset from
9115 stack pointer to frame pointer, so we must ensure that setjmp
9116 eliminates fp against the hard fp (%ebp) rather than trying to
9117 index from %esp up to the top of the frame across a gap that is
9118 of unknown (at compile-time) size. */
9119 static rtx
9121 {
9123 }
9125 /* When using -fsplit-stack, the allocation routines set a field in
9126 the TCB to the bottom of the stack plus this much space, measured
9127 in bytes. */
9129 #define SPLIT_STACK_AVAILABLE 256
9131 /* Fill structure ix86_frame about frame of currently computed function. */
9133 static void
9135 {
9137 HOST_WIDE_INT offset;
9140 HOST_WIDE_INT to_allocate;
9148 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9149 function prologues and leaf. */
9153 {
9158 }
9164 /* For SEH we have to limit the amount of code movement into the prologue.
9165 At present we do this via a BLOCKAGE, at which point there's very little
9166 scheduling that can be done, which means that there's very little point
9167 in doing anything except PUSHs. */
9171 /* During reload iteration the amount of registers saved can change.
9172 Recompute the value as needed. Do not recompute when amount of registers
9173 didn't change as reload does multiple calls to the function and does not
9174 expect the decision to change within single iteration. */
9177 {
9183 /* The fast prologue uses move instead of push to save registers. This
9184 is significantly longer, but also executes faster as modern hardware
9185 can execute the moves in parallel, but can't do that for push/pop.
9187 Be careful about choosing what prologue to emit: When function takes
9188 many instructions to execute we may use slow version as well as in
9189 case function is known to be outside hot spot (this is known with
9190 feedback only). Weight the size of function by number of registers
9191 to save as it is cheap to use one or two push instructions but very
9192 slow to use many of them. */
9196 || (flag_branch_probabilities
9199 else
9202 }
9204 frame->save_regs_using_mov
9206 /* If static stack checking is enabled and done with probes,
9207 the registers need to be saved before allocating the frame. */
9210 /* Skip return address. */
9213 /* Skip pushed static chain. */
9217 /* Skip saved base pointer. */
9222 /* The traditional frame pointer location is at the top of the frame. */
9225 /* Register save area */
9229 /* On SEH target, registers are pushed just before the frame pointer
9230 location. */
9234 /* Align and set SSE register save area. */
9236 {
9237 /* The only ABI that has saved SSE registers (Win64) also has a
9238 16-byte aligned default stack, and thus we don't need to be
9239 within the re-aligned local stack frame to save them. */
9243 }
9246 /* The re-aligned stack starts here. Values before this point are not
9247 directly comparable with values below this point. In order to make
9248 sure that no value happens to be the same before and after, force
9249 the alignment computation below to add a non-zero value. */
9253 /* Va-arg area */
9257 /* Align start of frame for local function. */
9266 /* Frame pointer points here. */
9271 /* Add outgoing arguments area. Can be skipped if we eliminated
9272 all the function calls as dead code.
9273 Skipping is however impossible when function calls alloca. Alloca
9274 expander assumes that last crtl->outgoing_args_size
9275 of stack frame are unused. */
9279 {
9282 }
9283 else
9286 /* Align stack boundary. Only needed if we're calling another function
9287 or using alloca. */
9292 /* We've reached end of stack frame. */
9295 /* Size prologue needs to allocate. */
9306 {
9312 }
9313 else
9317 /* The SEH frame pointer location is near the bottom of the frame.
9318 This is enforced by the fact that the difference between the
9319 stack pointer and the frame pointer is limited to 240 bytes in
9320 the unwind data structure. */
9322 {
9323 HOST_WIDE_INT diff;
9325 /* If we can leave the frame pointer where it is, do so. Also, returns
9326 the establisher frame for __builtin_frame_address (0). */
9331 {
9332 /* Ideally we'd determine what portion of the local stack frame
9333 (within the constraint of the lowest 240) is most heavily used.
9334 But without that complication, simply bias the frame pointer
9335 by 128 bytes so as to maximize the amount of the local stack
9336 frame that is addressable with 8-bit offsets. */
9338 }
9339 }
9340 }
9342 /* This is semi-inlined memory_address_length, but simplified
9343 since we know that we're always dealing with reg+offset, and
9344 to avoid having to create and discard all that rtl. */
9348 {
9352 {
9353 /* EBP and R13 cannot be encoded without an offset. */
9355 }
9359 /* ESP and R12 must be encoded with a SIB byte. */
9361 len++;
9364 }
9366 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9367 The valid base registers are taken from CFUN->MACHINE->FS. */
9369 static rtx
9371 {
9377 {
9378 /* Choose the base register most likely to allow the most scheduling
9379 opportunities. Generally FP is valid throughout the function,
9380 while DRAP must be reloaded within the epilogue. But choose either
9381 over the SP due to increased encoding size. */
9384 {
9387 }
9389 {
9392 }
9394 {
9397 }
9398 }
9399 else
9400 {
9401 HOST_WIDE_INT toffset;
9404 /* Choose the base register with the smallest address encoding.
9405 With a tie, choose FP > DRAP > SP. */
9407 {
9411 }
9413 {
9417 {
9421 }
9422 }
9424 {
9428 {
9432 }
9433 }
9434 }
9438 }
9440 /* Emit code to save registers in the prologue. */
9442 static void
9444 {
9446 rtx insn;
9450 {
9453 }
9454 }
9456 /* Emit a single register save at CFA - CFA_OFFSET. */
9458 static void
9460 HOST_WIDE_INT cfa_offset)
9461 {
9469 /* For SSE saves, we need to indicate the 128-bit alignment. */
9480 /* When saving registers into a re-aligned local stack frame, avoid
9481 any tricky guessing by dwarf2out. */
9483 {
9487 {
9488 /* A bit of a hack. We force the DRAP register to be saved in
9489 the re-aligned stack frame, which provides us with a copy
9490 of the CFA that will last past the prologue. Install it. */
9496 }
9497 else
9498 {
9499 /* The frame pointer is a stable reference within the
9500 aligned frame. Use it. */
9507 }
9508 }
9510 /* The memory may not be relative to the current CFA register,
9511 which means that we may need to generate a new pattern for
9512 use by the unwind info. */
9514 {
9519 }
9520 }
9522 /* Emit code to save registers using MOV insns.
9523 First register is stored at CFA - CFA_OFFSET. */
9524 static void
9526 {
9531 {
9534 }
9535 }
9537 /* Emit code to save SSE registers using MOV insns.
9538 First register is stored at CFA - CFA_OFFSET. */
9539 static void
9541 {
9546 {
9549 }
9550 }
9554 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9555 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9556 Don't add the note if the previously saved value will be left untouched
9557 within stack red-zone till return, as unwinders can find the same value
9558 in the register and on the stack. */
9560 static void
9562 {
9568 {
9571 }
9572 else
9573 queued_cfa_restores
9575 }
9577 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9579 static void
9581 {
9582 rtx last;
9586 ;
9591 }
9593 /* Expand prologue or epilogue stack adjustment.
9594 The pattern exist to put a dependency on all ebp-based memory accesses.
9595 STYLE should be negative if instructions should be marked as frame related,
9596 zero if %r11 register is live and cannot be freely used and positive
9597 otherwise. */
9599 static void
9602 {
9604 rtx insn;
9611 else
9612 {
9613 rtx tmp;
9614 /* r11 is used by indirect sibcall return as well, set before the
9615 epilogue and used after the epilogue. */
9618 else
9619 {
9623 }
9629 }
9636 {
9637 rtx r;
9647 }
9649 {
9652 {
9656 }
9657 }
9660 {
9665 {
9668 }
9670 {
9673 }
9674 else
9675 {
9676 /* Else there are two possibilities: SP itself, which we set
9677 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9678 taken care of this by hand along the eh_return path. */
9681 }
9685 }
9686 }
9688 /* Find an available register to be used as dynamic realign argument
9689 pointer regsiter. Such a register will be written in prologue and
9690 used in begin of body, so it must not be
9691 1. parameter passing register.
9692 2. GOT pointer.
9693 We reuse static-chain register if it is available. Otherwise, we
9694 use DI for i386 and R13 for x86-64. We chose R13 since it has
9695 shorter encoding.
9697 Return: the regno of chosen register. */
9699 static unsigned int
9701 {
9705 {
9706 /* Use R13 for nested function or function need static chain.
9707 Since function with tail call may use any caller-saved
9708 registers in epilogue, DRAP must not use caller-saved
9709 register in such case. */
9714 }
9715 else
9716 {
9717 /* Use DI for nested function or function need static chain.
9718 Since function with tail call may use any caller-saved
9719 registers in epilogue, DRAP must not use caller-saved
9720 register in such case. */
9724 /* Reuse static chain register if it isn't used for parameter
9725 passing. */
9727 {
9731 }
9733 }
9734 }
9736 /* Return minimum incoming stack alignment. */
9738 static unsigned int
9740 {
9743 /* Prefer the one specified at command line. */
9746 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9747 if -mstackrealign is used, it isn't used for sibcall check and
9748 estimated stack alignment is 128bit. */
9750 && !TARGET_64BIT
9751 && ix86_force_align_arg_pointer
9754 else
9757 /* Incoming stack alignment can be changed on individual functions
9758 via force_align_arg_pointer attribute. We use the smallest
9759 incoming stack boundary. */
9765 /* The incoming stack frame has to be aligned at least at
9766 parm_stack_boundary. */
9770 /* Stack at entrance of main is aligned by runtime. We use the
9771 smallest incoming stack boundary. */
9779 }
9781 /* Update incoming stack boundary and estimated stack alignment. */
9783 static void
9785 {
9786 ix86_incoming_stack_boundary
9789 /* x86_64 vararg needs 16byte stack alignment for register save
9790 area. */
9795 }
9797 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9798 needed or an rtx for DRAP otherwise. */
9800 static rtx
9802 {
9807 {
9808 /* Assign DRAP to vDRAP and returns vDRAP */
9810 rtx drap_vreg;
9811 rtx arg_ptr;
9824 {
9827 }
9829 }
9830 else
9832 }
9834 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9836 static rtx
9838 {
9840 }
9843 rtx reg;
9845 };
9847 /* Return a short-lived scratch register for use on function entry.
9848 In 32-bit mode, it is valid only after the registers are saved
9849 in the prologue. This register must be released by means of
9850 release_scratch_register_on_entry once it is dead. */
9852 static void
9854 {
9860 {
9861 /* We always use R11 in 64-bit mode. */
9863 }
9864 else
9865 {
9867 bool fastcall_p
9869 bool thiscall_p
9873 int drap_regno
9876 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9877 for the static chain register. */
9881 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9882 for the static chain register. */
9887 /* ecx is the static chain register. */
9889 && !static_chain_p
9894 /* esi is the static chain register. */
9900 else
9901 {
9904 }
9905 }
9909 {
9912 }
9913 }
9915 /* Release a scratch register obtained from the preceding function. */
9917 static void
9919 {
9921 {
9925 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9931 }
9932 }
9934 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9936 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9938 static void
9940 {
9941 /* We skip the probe for the first interval + a small dope of 4 words and
9942 probe that many bytes past the specified size to maintain a protection
9943 area at the botton of the stack. */
9947 /* See if we have a constant small number of probes to generate. If so,
9948 that's the easy case. The run-time loop is made up of 11 insns in the
9949 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9950 for n # of intervals. */
9952 {
9956 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9957 values of N from 1 until it exceeds SIZE. If only one probe is
9958 needed, this will not generate any code. Then adjust and probe
9959 to PROBE_INTERVAL + SIZE. */
9961 {
9963 {
9966 }
9967 else
9974 }
9978 else
9986 /* Adjust back to account for the additional first interval. */
9990 }
9992 /* Otherwise, do the same as above, but in a loop. Note that we must be
9993 extra careful with variables wrapping around because we might be at
9994 the very top (or the very bottom) of the address space and we have
9995 to be able to handle this case properly; in particular, we use an
9996 equality test for the loop condition. */
9997 else
9998 {
9999 HOST_WIDE_INT rounded_size;
10005 /* Step 1: round SIZE to the previous multiple of the interval. */
10010 /* Step 2: compute initial and final value of the loop counter. */
10012 /* SP = SP_0 + PROBE_INTERVAL. */
10017 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10021 stack_pointer_rtx)));
10024 /* Step 3: the loop
10026 while (SP != LAST_ADDR)
10027 {
10028 SP = SP + PROBE_INTERVAL
10029 probe at SP
10030 }
10032 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10033 values of N from 1 until it is equal to ROUNDED_SIZE. */
10038 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10039 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10042 {
10047 }
10049 /* Adjust back to account for the additional first interval. */
10055 }
10059 /* Even if the stack pointer isn't the CFA register, we need to correctly
10060 describe the adjustments made to it, in particular differentiate the
10061 frame-related ones from the frame-unrelated ones. */
10063 {
10076 }
10078 /* Make sure nothing is scheduled before we are done. */
10080 }
10082 /* Adjust the stack pointer up to REG while probing it. */
10086 {
10096 /* Jump to END_LAB if SP == LAST_ADDR. */
10104 /* SP = SP + PROBE_INTERVAL. */
10108 /* Probe at SP. */
10119 }
10121 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10122 inclusive. These are offsets from the current stack pointer. */
10124 static void
10126 {
10127 /* See if we have a constant small number of probes to generate. If so,
10128 that's the easy case. The run-time loop is made up of 7 insns in the
10129 generic case while the compile-time loop is made up of n insns for n #
10130 of intervals. */
10132 {
10133 HOST_WIDE_INT i;
10135 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10136 it exceeds SIZE. If only one probe is needed, this will not
10137 generate any code. Then probe at FIRST + SIZE. */
10144 }
10146 /* Otherwise, do the same as above, but in a loop. Note that we must be
10147 extra careful with variables wrapping around because we might be at
10148 the very top (or the very bottom) of the address space and we have
10149 to be able to handle this case properly; in particular, we use an
10150 equality test for the loop condition. */
10151 else
10152 {
10159 /* Step 1: round SIZE to the previous multiple of the interval. */
10164 /* Step 2: compute initial and final value of the loop counter. */
10166 /* TEST_OFFSET = FIRST. */
10169 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10173 /* Step 3: the loop
10175 while (TEST_ADDR != LAST_ADDR)
10176 {
10177 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10178 probe at TEST_ADDR
10179 }
10181 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10182 until it is equal to ROUNDED_SIZE. */
10187 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10188 that SIZE is equal to ROUNDED_SIZE. */
10193 stack_pointer_rtx,
10198 }
10200 /* Make sure nothing is scheduled before we are done. */
10202 }
10204 /* Probe a range of stack addresses from REG to END, inclusive. These are
10205 offsets from the current stack pointer. */
10209 {
10219 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10227 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10231 /* Probe at TEST_ADDR. */
10244 }
10246 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10247 to be generated in correct form. */
10248 static void
10250 {
10251 /* Check if stack realign is really needed after reload, and
10252 stores result in cfun */
10253 unsigned int incoming_stack_boundary
10262 {
10263 /* After stack_realign_needed is finalized, we can't no longer
10264 change it. */
10267 }
10269 /* If the only reason for frame_pointer_needed is that we conservatively
10270 assumed stack realignment might be needed, but in the end nothing that
10271 needed the stack alignment had been spilled, clear frame_pointer_needed
10272 and say we don't need stack realignment. */
10275 && frame_pointer_needed
10277 && flag_omit_frame_pointer
10279 && !ix86_current_function_calls_tls_descriptor
10288 {
10290 basic_block bb;
10297 HARD_FRAME_POINTER_REGNUM);
10299 {
10300 rtx insn;
10304 set_up_by_prologue))
10305 {
10309 }
10310 }
10324 }
10328 }
10330 /* Expand the prologue into a bunch of separate insns. */
10332 void
10334 {
10339 HOST_WIDE_INT allocate;
10345 /* DRAP should not coexist with stack_realign_fp */
10350 /* Initialize CFA state for before the prologue. */
10354 /* Track SP offset to the CFA. We continue tracking this after we've
10355 swapped the CFA register away from SP. In the case of re-alignment
10356 this is fudged; we're interested to offsets within the local frame. */
10363 {
10364 /* We should have already generated an error for any use of
10365 ms_hook on a nested function. */
10368 /* Check if profiling is active and we shall use profiling before
10369 prologue variant. If so sorry. */
10374 /* In ix86_asm_output_function_label we emitted:
10375 8b ff movl.s %edi,%edi
10376 55 push %ebp
10377 8b ec movl.s %esp,%ebp
10379 This matches the hookable function prologue in Win32 API
10380 functions in Microsoft Windows XP Service Pack 2 and newer.
10381 Wine uses this to enable Windows apps to hook the Win32 API
10382 functions provided by Wine.
10384 What that means is that we've already set up the frame pointer. */
10388 {
10391 /* We've decided to use the frame pointer already set up.
10392 Describe this to the unwinder by pretending that both
10393 push and mov insns happen right here.
10395 Putting the unwind info here at the end of the ms_hook
10396 is done so that we can make absolutely certain we get
10397 the required byte sequence at the start of the function,
10398 rather than relying on an assembler that can produce
10399 the exact encoding required.
10401 However it does mean (in the unpatched case) that we have
10402 a 1 insn window where the asynchronous unwind info is
10403 incorrect. However, if we placed the unwind info at
10404 its correct location we would have incorrect unwind info
10405 in the patched case. Which is probably all moot since
10406 I don't expect Wine generates dwarf2 unwind info for the
10407 system libraries that use this feature. */
10413 stack_pointer_rtx);
10421 /* Note that gen_push incremented m->fs.cfa_offset, even
10422 though we didn't emit the push insn here. */
10426 }
10427 else
10428 {
10429 /* The frame pointer is not needed so pop %ebp again.
10430 This leaves us with a pristine state. */
10432 }
10433 }
10435 /* The first insn of a function that accepts its static chain on the
10436 stack is to push the register that would be filled in by a direct
10437 call. This insn will be skipped by the trampoline. */
10439 {
10443 /* We don't want to interpret this push insn as a register save,
10444 only as a stack adjustment. The real copy of the register as
10445 a save will be done later, if needed. */
10450 }
10452 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10453 of DRAP is needed and stack realignment is really needed after reload */
10455 {
10458 /* Only need to push parameter pointer reg if it is caller saved. */
10460 {
10461 /* Push arg pointer reg */
10464 }
10466 /* Grab the argument pointer. */
10473 /* Align the stack. */
10475 stack_pointer_rtx,
10479 /* Replicate the return address on the stack so that return
10480 address can be reached via (argp - 1) slot. This is needed
10481 to implement macro RETURN_ADDR_RTX and intrinsic function
10482 expand_builtin_return_addr etc. */
10488 /* For the purposes of frame and register save area addressing,
10489 we've started over with a new frame. */
10492 }
10498 {
10499 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10500 slower on all targets. Also sdb doesn't like it. */
10504 /* Push registers now, before setting the frame pointer
10505 on SEH target. */
10507 && TARGET_SEH
10509 {
10513 }
10516 {
10524 }
10525 }
10528 {
10529 /* If saving registers via PUSH, do so now. */
10531 {
10535 }
10537 /* When using red zone we may start register saving before allocating
10538 the stack frame saving one cycle of the prologue. However, avoid
10539 doing this if we have to probe the stack; at least on x86_64 the
10540 stack probe can turn into a call that clobbers a red zone location. */
10542 && (! TARGET_STACK_PROBE
10544 {
10547 }
10548 }
10551 {
10555 /* The computation of the size of the re-aligned stack frame means
10556 that we must allocate the size of the register save area before
10557 performing the actual alignment. Otherwise we cannot guarantee
10558 that there's enough storage above the realignment point. */
10565 /* Align the stack. */
10567 stack_pointer_rtx,
10570 /* For the purposes of register save area addressing, the stack
10571 pointer is no longer valid. As for the value of sp_offset,
10572 see ix86_compute_frame_layout, which we need to match in order
10573 to pass verification of stack_pointer_offset at the end. */
10576 }
10581 {
10582 /* We start to count from ARG_POINTER. */
10585 /* If it was realigned, take into account the fake frame. */
10587 {
10594 /* This over-estimates by 1 minimal-stack-alignment-unit but
10595 mitigates that by counting in the new return address slot. */
10596 current_function_dynamic_stack_size
10598 }
10601 }
10603 /* On SEH target with very large frame size, allocate an area to save
10604 SSE registers (as the very large allocation won't be described). */
10608 {
10609 HOST_WIDE_INT sse_size =
10614 /* No need to do stack checking as the area will be immediately
10615 written. */
10622 }
10624 /* The stack has already been decremented by the instruction calling us
10625 so probe if the size is non-negative to preserve the protection area. */
10627 {
10628 /* We expect the registers to be saved when probes are used. */
10632 {
10635 }
10636 else
10637 {
10645 else
10647 }
10648 }
10651 ;
10654 {
10658 }
10659 else
10660 {
10673 /* Note that SEH directives need to continue tracking the stack
10674 pointer even after the frame pointer has been set up. */
10676 {
10680 {
10684 }
10685 }
10688 {
10693 {
10697 }
10698 }
10703 /* Use the fact that AX still contains ALLOCATE. */
10705 ? gen_pro_epilogue_adjust_stack_di_sub
10712 {
10720 }
10724 {
10731 }
10733 {
10738 }
10739 }
10742 /* If we havn't already set up the frame pointer, do so now. */
10744 {
10756 }
10764 /* We don't use pic-register for pe-coff target. */
10766 && !TARGET_PECOFF
10769 {
10776 }
10779 {
10781 {
10783 {
10793 label));
10797 }
10798 else
10800 }
10801 else
10802 {
10806 }
10807 }
10809 /* In the pic_reg_used case, make sure that the got load isn't deleted
10810 when mcount needs it. Blockage to avoid call movement across mcount
10811 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10812 note. */
10817 {
10818 /* vDRAP is setup but after reload it turns out stack realign
10819 isn't necessary, here we will emit prologue to setup DRAP
10820 without stack realign adjustment */
10823 }
10825 /* Prevent instructions from being scheduled into register save push
10826 sequence when access to the redzone area is done through frame pointer.
10827 The offset between the frame pointer and the stack pointer is calculated
10828 relative to the value of the stack pointer at the end of the function
10829 prologue, and moving instructions that access redzone area via frame
10830 pointer inside push sequence violates this assumption. */
10834 /* Emit cld instruction if stringops are used in the function. */
10838 /* SEH requires that the prologue end within 256 bytes of the start of
10839 the function. Prevent instruction schedules that would extend that.
10840 Further, prevent alloca modifications to the stack pointer from being
10841 combined with prologue modifications. */
10844 }
10846 /* Emit code to restore REG using a POP insn. */
10848 static void
10850 {
10859 {
10860 /* Previously we'd represented the CFA as an expression
10861 like *(%ebp - 8). We've just popped that value from
10862 the stack, which means we need to reset the CFA to
10863 the drap register. This will remain until we restore
10864 the stack pointer. */
10868 /* This means that the DRAP register is valid for addressing too. */
10871 }
10874 {
10881 }
10883 /* When the frame pointer is the CFA, and we pop it, we are
10884 swapping back to the stack pointer as the CFA. This happens
10885 for stack frames that don't allocate other data, so we assume
10886 the stack pointer is now pointing at the return address, i.e.
10887 the function entry state, which makes the offset be 1 word. */
10889 {
10892 {
10900 }
10901 }
10902 }
10904 /* Emit code to restore saved registers using POP insns. */
10906 static void
10908 {
10914 }
10916 /* Emit code and notes for the LEAVE instruction. */
10918 static void
10920 {
10932 {
10940 }
10943 }
10945 /* Emit code to restore saved registers using MOV insns.
10946 First register is restored from CFA - CFA_OFFSET. */
10947 static void
10950 {
10956 {
10965 {
10966 /* Previously we'd represented the CFA as an expression
10967 like *(%ebp - 8). We've just popped that value from
10968 the stack, which means we need to reset the CFA to
10969 the drap register. This will remain until we restore
10970 the stack pointer. */
10974 /* This means that the DRAP register is valid for addressing. */
10976 }
10977 else
10981 }
10982 }
10984 /* Emit code to restore saved registers using MOV insns.
10985 First register is restored from CFA - CFA_OFFSET. */
10986 static void
10989 {
10994 {
10996 rtx mem;
11006 }
11007 }
11009 /* Restore function stack, frame, and registers. */
11011 void
11013 {
11029 /* The FP must be valid if the frame pointer is present. */
11034 /* We must have *some* valid pointer to the stack frame. */
11037 /* The DRAP is never valid at this point. */
11040 /* See the comment about red zone and frame
11041 pointer usage in ix86_expand_prologue. */
11048 /* Determine the CFA offset of the end of the red-zone. */
11051 {
11052 /* The red-zone begins below the return address. */
11055 /* When the register save area is in the aligned portion of
11056 the stack, determine the maximum runtime displacement that
11057 matches up with the aligned frame. */
11061 }
11063 /* Special care must be taken for the normal return case of a function
11064 using eh_return: the eax and edx registers are marked as saved, but
11065 not restored along this path. Adjust the save location to match. */
11069 /* EH_RETURN requires the use of moves to function properly. */
11072 /* SEH requires the use of pops to identify the epilogue. */
11075 /* If we're only restoring one register and sp is not valid then
11076 using a move instruction to restore the register since it's
11077 less work than reloading sp and popping the register. */
11090 && TARGET_USE_LEAVE
11094 else
11098 {
11099 /* Ensure that the entire register save area is addressable via
11100 the stack pointer, if we will restore via sp. */
11105 {
11109 style,
11111 }
11112 }
11114 /* If there are any SSE registers to restore, then we have to do it
11115 via moves, since there's obviously no pop for SSE regs. */
11121 {
11122 rtx t;
11127 /* eh_return epilogues need %ecx added to the stack pointer. */
11129 {
11132 /* Stack align doesn't work with eh_return. */
11134 /* Neither does regparm nested functions. */
11138 {
11146 /* Note that we use SA as a temporary CFA, as the return
11147 address is at the proper place relative to it. We
11148 pretend this happens at the FP restore insn because
11149 prior to this insn the FP would be stored at the wrong
11150 offset relative to SA, and after this insn we have no
11151 other reasonable register to use for the CFA. We don't
11152 bother resetting the CFA to the SP for the duration of
11153 the return insn. */
11166 }
11167 else
11168 {
11176 {
11180 UNITS_PER_WORD));
11182 }
11183 }
11186 }
11187 }
11188 else
11189 {
11190 /* SEH requires that the function end with (1) a stack adjustment
11191 if necessary, (2) a sequence of pops, and (3) a return or
11192 jump instruction. Prevent insns from the function body from
11193 being scheduled into this sequence. */
11195 {
11196 /* Prevent a catch region from being adjacent to the standard
11197 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11198 several other flags that would be interesting to test are
11199 not yet set up. */
11202 else
11204 }
11206 /* First step is to deallocate the stack frame so that we can
11207 pop the registers. Also do it on SEH target for very large
11208 frame as the emitted instructions aren't allowed by the ABI in
11209 epilogues. */
11211 || (TARGET_SEH
11214 {
11219 }
11221 {
11225 style,
11227 }
11230 }
11232 /* If we used a stack pointer and haven't already got rid of it,
11233 then do so now. */
11235 {
11236 /* If the stack pointer is valid and pointing at the frame
11237 pointer store address, then we only need a pop. */
11240 /* Leave results in shorter dependency chains on CPUs that are
11241 able to grok it fast. */
11246 else
11247 {
11249 hard_frame_pointer_rtx,
11252 }
11253 }
11256 {
11258 rtx insn;
11284 }
11286 /* At this point the stack pointer must be valid, and we must have
11287 restored all of the registers. We may not have deallocated the
11288 entire stack frame. We've delayed this until now because it may
11289 be possible to merge the local stack deallocation with the
11290 deallocation forced by ix86_static_chain_on_stack. */
11295 {
11299 }
11300 else
11303 /* Sibcall epilogues don't want a return instruction. */
11305 {
11308 }
11311 {
11314 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11315 address, do explicit add, and jump indirectly to the caller. */
11318 {
11320 rtx insn;
11322 /* There is no "pascal" calling convention in any 64bit ABI. */
11338 }
11339 else
11341 }
11342 else
11345 /* Restore the state back to the state from the prologue,
11346 so that it's correct for the next epilogue. */
11348 }
11350 /* Reset from the function's potential modifications. */
11352 static void
11354 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11355 {
11358 #if TARGET_MACHO
11359 /* Mach-O doesn't support labels at the end of objects, so if
11360 it looks like we might want one, insert a NOP. */
11361 {
11367 {
11368 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11369 notes only, instead set their CODE_LABEL_NUMBER to -1,
11370 otherwise there would be code generation differences
11371 in between -g and -g0. */
11375 }
11385 }
11386 #endif
11388 }
11390 /* Return a scratch register to use in the split stack prologue. The
11391 split stack prologue is used for -fsplit-stack. It is the first
11392 instructions in the function, even before the regular prologue.
11393 The scratch register can be any caller-saved register which is not
11394 used for parameters or for the static chain. */
11396 static unsigned int
11398 {
11401 else
11402 {
11415 {
11417 {
11421 }
11423 }
11425 {
11429 }
11431 {
11434 else
11435 {
11437 {
11441 }
11443 }
11444 }
11445 else
11446 {
11447 /* FIXME: We could make this work by pushing a register
11448 around the addition and comparison. */
11451 }
11452 }
11453 }
11455 /* A SYMBOL_REF for the function which allocates new stackspace for
11456 -fsplit-stack. */
11460 /* A SYMBOL_REF for the more stack function when using the large
11461 model. */
11465 /* Handle -fsplit-stack. These are the first instructions in the
11466 function, even before the regular prologue. */
11468 void
11470 {
11472 HOST_WIDE_INT allocate;
11477 rtx fn;
11485 /* This is the label we will branch to if we have enough stack
11486 space. We expect the basic block reordering pass to reverse this
11487 branch if optimizing, so that we branch in the unlikely case. */
11490 /* We need to compare the stack pointer minus the frame size with
11491 the stack boundary in the TCB. The stack boundary always gives
11492 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11493 can compare directly. Otherwise we need to do an addition. */
11496 UNSPEC_STACK_CHECK);
11501 else
11502 {
11504 rtx offset;
11506 /* We need a scratch register to hold the stack pointer minus
11507 the required frame size. Since this is the very start of the
11508 function, the scratch register can be any caller-saved
11509 register which is not used for parameters. */
11516 {
11517 /* We don't use ix86_gen_add3 in this case because it will
11518 want to split to lea, but when not optimizing the insn
11519 will not be split after this point. */
11522 offset)));
11523 }
11524 else
11525 {
11528 stack_pointer_rtx));
11529 }
11531 }
11537 /* Mark the jump as very likely to be taken. */
11545 /* Get more stack space. We pass in the desired stack space and the
11546 size of the arguments to copy to the new stack. In 32-bit mode
11547 we push the parameters; __morestack will return on a new stack
11548 anyhow. In 64-bit mode we pass the parameters in r10 and
11549 r11. */
11554 {
11560 /* If this function uses a static chain, it will be in %r10.
11561 Preserve it across the call to __morestack. */
11563 {
11564 rtx rax;
11569 }
11573 {
11574 HOST_WIDE_INT argval;
11577 /* When using the large model we need to load the address
11578 into a register, and we've run out of registers. So we
11579 switch to a different calling convention, and we call a
11580 different function: __morestack_large. We pass the
11581 argument size in the upper 32 bits of r10 and pass the
11582 frame size in the lower 32 bits. */
11587 split_stack_fn_large =
11591 {
11601 UNSPEC_GOT);
11607 }
11608 else
11615 }
11616 else
11617 {
11621 }
11624 }
11625 else
11626 {
11629 }
11635 /* In order to make call/return prediction work right, we now need
11636 to execute a return instruction. See
11637 libgcc/config/i386/morestack.S for the details on how this works.
11639 For flow purposes gcc must not see this as a return
11640 instruction--we need control flow to continue at the subsequent
11641 label. Therefore, we use an unspec. */
11645 /* If we are in 64-bit mode and this function uses a static chain,
11646 we saved %r10 in %rax before calling _morestack. */
11651 /* If this function calls va_start, we need to store a pointer to
11652 the arguments on the old stack, because they may not have been
11653 all copied to the new stack. At this point the old stack can be
11654 found at the frame pointer value used by __morestack, because
11655 __morestack has set that up before calling back to us. Here we
11656 store that pointer in a scratch register, and in
11657 ix86_expand_prologue we store the scratch register in a stack
11658 slot. */
11660 {
11662 rtx frame_reg;
11669 /* 64-bit:
11670 fp -> old fp value
11671 return address within this function
11672 return address of caller of this function
11673 stack arguments
11674 So we add three words to get to the stack arguments.
11676 32-bit:
11677 fp -> old fp value
11678 return address within this function
11679 first argument to __morestack
11680 second argument to __morestack
11681 return address of caller of this function
11682 stack arguments
11683 So we add five words to get to the stack arguments.
11684 */
11695 }
11700 /* If this function calls va_start, we now have to set the scratch
11701 register for the case where we do not call __morestack. In this
11702 case we need to set it based on the stack pointer. */
11704 {
11711 }
11712 }
11714 /* We may have to tell the dataflow pass that the split stack prologue
11715 is initializing a scratch register. */
11717 static void
11719 {
11721 {
11724 }
11725 }
11726 \f
11727 /* Determine if op is suitable SUBREG RTX for address. */
11729 static bool
11731 {
11742 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11743 failures when the register is one word out of a two word structure. */
11747 /* Allow only SUBREGs of non-eliminable hard registers. */
11749 }
11751 /* Extract the parts of an RTL expression that is a valid memory address
11752 for an instruction. Return 0 if the structure of the address is
11753 grossly off. Return -1 if the address contains ASHIFT, so it is not
11754 strictly valid, but still used for computing length of lea instruction. */
11756 int
11758 {
11763 rtx tmp;
11767 /* Allow zero-extended SImode addresses,
11768 they will be emitted with addr32 prefix. */
11770 {
11773 {
11777 }
11780 {
11787 }
11788 }
11790 /* Allow SImode subregs of DImode addresses,
11791 they will be emitted with addr32 prefix. */
11793 {
11796 {
11800 }
11801 }
11806 {
11809 else
11811 }
11813 {
11818 do
11819 {
11824 }
11831 {
11834 {
11859 /* FALLTHRU */
11863 && TARGET_TLS_DIRECT_SEG_REFS
11866 else
11873 /* FALLTHRU */
11880 else
11895 }
11896 }
11897 }
11899 {
11902 }
11904 {
11905 /* We're called for lea too, which implements ashift on occasion. */
11915 }
11917 {
11921 /* Constant addresses are sign extended to 64bit, we have to
11922 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11928 }
11929 else
11933 {
11935 ;
11938 ;
11939 else
11941 }
11943 /* Address override works only on the (%reg) part of %fs:(%reg). */
11949 /* Extract the integral value of scale. */
11951 {
11955 }
11960 /* Avoid useless 0 displacement. */
11964 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11969 {
11970 rtx tmp;
11973 }
11975 /* Special case: %ebp cannot be encoded as a base without a displacement.
11976 Similarly %r13. */
11978 && base_reg
11987 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11988 Avoid this by transforming to [%esi+0].
11989 Reload calls address legitimization without cfun defined, so we need
11990 to test cfun for being non-NULL. */
11996 /* Special case: encode reg+reg instead of reg*2. */
12000 /* Special case: scaling cannot be encoded without base or displacement. */
12011 }
12012 \f
12013 /* Return cost of the memory address x.
12014 For i386, it is better to use a complex address than let gcc copy
12015 the address into a reg and make a new pseudo. But not if the address
12016 requires to two regs - that would mean more pseudos with longer
12017 lifetimes. */
12018 static int
12020 addr_space_t as ATTRIBUTE_UNUSED,
12022 {
12034 /* Attempt to minimize number of registers in the address. */
12040 cost++;
12047 cost++;
12049 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12050 since it's predecode logic can't detect the length of instructions
12051 and it degenerates to vector decoded. Increase cost of such
12052 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12053 to split such addresses or even refuse such addresses at all.
12055 Following addressing modes are affected:
12056 [base+scale*index]
12057 [scale*index+disp]
12058 [base+index]
12060 The first and last case may be avoidable by explicitly coding the zero in
12061 memory address, but I don't have AMD-K6 machine handy to check this
12062 theory. */
12071 }
12072 \f
12073 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12074 this is used for to form addresses to local data when -fPIC is in
12075 use. */
12077 static bool
12079 {
12082 }
12084 /* Determine if a given RTX is a valid constant. We already know this
12085 satisfies CONSTANT_P. */
12087 static bool
12089 {
12091 {
12096 {
12100 }
12105 /* Only some unspecs are valid as "constants". */
12108 {
12124 }
12126 /* We must have drilled down to a symbol. */
12131 /* FALLTHRU */
12134 /* TLS symbols are never valid. */
12138 /* DLLIMPORT symbols are never valid. */
12143 #if TARGET_MACHO
12144 /* mdynamic-no-pic */
12147 #endif
12163 }
12165 /* Otherwise we handle everything else in the move patterns. */
12167 }
12169 /* Determine if it's legal to put X into the constant pool. This
12170 is not possible for the address of thread-local symbols, which
12171 is checked above. */
12173 static bool
12175 {
12176 /* We can always put integral constants and vectors in memory. */
12178 {
12186 }
12188 }
12190 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12191 otherwise zero. */
12193 static bool
12195 {
12201 }
12204 /* Nonzero if the constant value X is a legitimate general operand
12205 when generating PIC code. It is given that flag_pic is on and
12206 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12208 bool
12210 {
12211 rtx inner;
12214 {
12221 /* Only some unspecs are valid as "constants". */
12224 {
12237 }
12238 /* FALLTHRU */
12246 }
12247 }
12249 /* Determine if a given CONST RTX is a valid memory displacement
12250 in PIC mode. */
12252 bool
12254 {
12257 /* In 64bit mode we can allow direct addresses of symbols and labels
12258 when they are not dynamic symbols. */
12260 {
12264 {
12288 /* FALLTHRU */
12291 /* TLS references should always be enclosed in UNSPEC.
12292 The dllimported symbol needs always to be resolved. */
12298 {
12306 /* Function-symbols need to be resolved only for
12307 large-model.
12308 For the small-model we don't need to resolve anything
12309 here. */
12314 /* Non-external symbols don't need to be resolved for
12315 large, and medium-model. */
12320 }
12329 }
12330 }
12336 {
12337 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12338 of GOT tables. We should not need these anyway. */
12350 }
12354 {
12359 }
12368 {
12372 /* We need to check for both symbols and labels because VxWorks loads
12373 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12374 details. */
12378 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12379 While ABI specify also 32bit relocation but we don't produce it in
12380 small PIC model at all. */
12402 }
12405 }
12407 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12408 replace the input X, or the original X if no replacement is called for.
12409 The output parameter *WIN is 1 if the calling macro should goto WIN,
12410 0 if it should not. */
12412 bool
12417 {
12418 /* Reload can generate:
12420 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12421 (reg:DI 97))
12422 (reg:DI 2 cx))
12424 This RTX is rejected from ix86_legitimate_address_p due to
12425 non-strictness of base register 97. Following this rejection,
12426 reload pushes all three components into separate registers,
12427 creating invalid memory address RTX.
12429 Following code reloads only the invalid part of the
12430 memory address RTX. */
12436 {
12442 {
12447 }
12451 {
12456 }
12460 }
12463 }
12465 /* Recognizes RTL expressions that are valid memory addresses for an
12466 instruction. The MODE argument is the machine mode for the MEM
12467 expression that wants to use this address.
12469 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12470 convert common non-canonical forms to canonical form so that they will
12471 be recognized. */
12473 static bool
12476 {
12479 HOST_WIDE_INT scale;
12482 /* Decomposition failed. */
12490 /* Validate base register. */
12492 {
12493 rtx reg;
12499 else
12500 /* Base is not a register. */
12508 /* Base is not valid. */
12510 }
12512 /* Validate index register. */
12514 {
12515 rtx reg;
12521 else
12522 /* Index is not a register. */
12530 /* Index is not valid. */
12532 }
12534 /* Index and base should have the same mode. */
12539 /* Validate scale factor. */
12541 {
12543 /* Scale without index. */
12547 /* Scale is not a valid multiplier. */
12549 }
12551 /* Validate displacement. */
12553 {
12558 {
12559 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12560 used. While ABI specify also 32bit relocations, we don't produce
12561 them at all and use IP relative instead. */
12568 /* 64bit address unspec. */
12588 /* Invalid address unspec. */
12590 }
12593 && (flag_pic
12594 || (TARGET_MACHO
12595 #if TARGET_MACHO
12596 && MACHOPIC_INDIRECT
12598 #endif
12599 )))
12600 {
12602 is_legitimate_pic:
12604 {
12605 /* foo@dtpoff(%rX) is ok. */
12612 /* Non-constant pic memory reference. */
12614 }
12617 /* Displacement is an invalid pic construct. */
12619 #if TARGET_MACHO
12622 /* displacment must be referenced via non_lazy_pointer */
12624 #endif
12626 /* This code used to verify that a symbolic pic displacement
12627 includes the pic_offset_table_rtx register.
12629 While this is good idea, unfortunately these constructs may
12630 be created by "adds using lea" optimization for incorrect
12631 code like:
12633 int a;
12634 int foo(int i)
12635 {
12636 return *(&a+i);
12637 }
12639 This code is nonsensical, but results in addressing
12640 GOT table with pic_offset_table_rtx base. We can't
12641 just refuse it easily, since it gets matched by
12642 "addsi3" pattern, that later gets split to lea in the
12643 case output register differs from input. While this
12644 can be handled by separate addsi pattern for this case
12645 that never results in lea, this seems to be easier and
12646 correct fix for crash to disable this test. */
12647 }
12654 /* Displacement is not constant. */
12658 /* Displacement is out of range. */
12660 }
12662 /* Everything looks valid. */
12664 }
12666 /* Determine if a given RTX is a valid constant address. */
12668 bool
12670 {
12672 }
12673 \f
12674 /* Return a unique alias set for the GOT. */
12676 static alias_set_type
12678 {
12683 }
12685 /* Return a legitimate reference for ORIG (an address) using the
12686 register REG. If REG is 0, a new pseudo is generated.
12688 There are two types of references that must be handled:
12690 1. Global data references must load the address from the GOT, via
12691 the PIC reg. An insn is emitted to do this load, and the reg is
12692 returned.
12694 2. Static data references, constant pool addresses, and code labels
12695 compute the address as an offset from the GOT, whose base is in
12696 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12697 differentiate them from global data objects. The returned
12698 address is the PIC reg + an unspec constant.
12700 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12701 reg also appears in the address. */
12703 static rtx
12705 {
12709 #if TARGET_MACHO
12711 {
12714 /* Use the generic Mach-O PIC machinery. */
12716 }
12717 #endif
12720 {
12724 }
12730 {
12731 rtx tmpreg;
12732 /* This symbol may be referenced via a displacement from the PIC
12733 base address (@GOTOFF). */
12740 {
12742 UNSPEC_GOTOFF);
12744 }
12745 else
12750 else
12755 {
12759 }
12760 else
12762 }
12764 {
12765 /* This symbol may be referenced via a displacement from the PIC
12766 base address (@GOTOFF). */
12773 {
12775 UNSPEC_GOTOFF);
12777 }
12778 else
12784 {
12787 }
12788 }
12790 /* We can't use @GOTOFF for text labels on VxWorks;
12791 see gotoff_operand. */
12793 {
12798 /* For x64 PE-COFF there is no GOT table. So we use address
12799 directly. */
12801 {
12809 }
12811 {
12819 /* Use directly gen_movsi, otherwise the address is loaded
12820 into register for CSE. We don't want to CSE this addresses,
12821 instead we CSE addresses from the GOT table, so skip this. */
12824 }
12825 else
12826 {
12827 /* This symbol must be referenced via a load from the
12828 Global Offset Table (@GOT). */
12844 }
12845 }
12846 else
12847 {
12850 {
12852 {
12855 }
12856 else
12858 }
12860 {
12863 /* We must match stuff we generate before. Assume the only
12864 unspecs that can get here are ours. Not that we could do
12865 anything with them anyway.... */
12871 }
12873 {
12876 /* Check first to see if this is a constant offset from a @GOTOFF
12877 symbol reference. */
12880 {
12882 {
12886 UNSPEC_GOTOFF);
12892 {
12895 }
12896 }
12897 else
12898 {
12901 {
12905 }
12906 }
12907 }
12908 else
12909 {
12912 new_rtx
12916 {
12919 {
12922 new_rtx
12924 }
12925 else
12927 }
12928 else
12929 {
12932 {
12935 }
12937 }
12938 }
12939 }
12940 }
12942 }
12943 \f
12944 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12946 static rtx
12948 {
12952 {
12957 }
12963 }
12965 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12969 static rtx
12971 {
12973 {
12979 }
12982 }
12984 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12988 rtx
12990 {
12992 {
12993 ix86_tls_module_base_symbol
12998 }
13001 }
13003 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13004 false if we expect this to be used for a memory address and true if
13005 we expect to load the address into a register. */
13007 static rtx
13009 {
13016 {
13021 {
13024 else
13025 {
13028 }
13029 }
13032 {
13035 else
13045 }
13046 else
13047 {
13051 {
13053 rtx insns;
13056 emit_call_insn
13066 }
13067 else
13069 }
13076 {
13079 else
13080 {
13083 }
13084 }
13087 {
13092 else
13098 }
13099 else
13100 {
13104 {
13109 emit_call_insn
13114 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13115 share the LD_BASE result with other LD model accesses. */
13117 UNSPEC_TLS_LD_BASE);
13121 }
13122 else
13124 }
13132 {
13139 }
13144 {
13146 {
13147 /* The Sun linker took the AMD64 TLS spec literally
13148 and can only handle %rax as destination of the
13149 initial executable code sequence. */
13154 }
13156 /* Generate DImode references to avoid %fs:(%reg32)
13157 problems and linker IE->LE relaxation bug. */
13161 }
13163 {
13168 }
13170 {
13174 }
13175 else
13176 {
13179 }
13189 {
13194 }
13195 else
13196 {
13200 }
13210 {
13214 }
13215 else
13216 {
13220 }
13225 }
13228 }
13230 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13231 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13232 unique refptr-DECL symbol corresponding to symbol DECL. */
13235 htab_t dllimport_map;
13237 static tree
13239 {
13246 tree to;
13247 rtx rtl;
13274 else
13287 {
13289 #ifdef SUB_TARGET_RECORD_STUB
13291 #endif
13292 }
13301 }
13303 /* Expand SYMBOL into its corresponding far-addresse symbol.
13304 WANT_REG is true if we require the result be a register. */
13306 static rtx
13308 {
13309 tree imp_decl;
13310 rtx x;
13319 }
13321 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13322 true if we require the result be a register. */
13324 static rtx
13326 {
13327 tree imp_decl;
13328 rtx x;
13337 }
13339 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13340 is true if we require the result be a register. */
13342 static rtx
13344 {
13349 {
13356 {
13359 }
13360 }
13376 {
13379 }
13381 }
13383 /* Try machine-dependent ways of modifying an illegitimate address
13384 to be legitimate. If we find one, return the new, valid address.
13385 This macro is used in only one place: `memory_address' in explow.c.
13387 OLDX is the address as it was before break_out_memory_refs was called.
13388 In some cases it is useful to look at this to decide what needs to be done.
13390 It is always safe for this macro to do nothing. It exists to recognize
13391 opportunities to optimize the output.
13393 For the 80386, we handle X+REG by loading X into a register R and
13394 using R+REG. R will go in a general reg and indexing will be used.
13395 However, if REG is a broken-out memory address or multiplication,
13396 nothing needs to be done because REG can certainly go in a general reg.
13398 When -fpic is used, special handling is needed for symbolic references.
13399 See comments by legitimize_pic_address in i386.c for details. */
13401 static rtx
13404 {
13415 {
13419 }
13422 {
13426 }
13431 #if TARGET_MACHO
13434 #endif
13436 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13440 {
13445 }
13448 {
13449 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13454 {
13460 }
13465 {
13471 }
13473 /* Put multiply first if it isn't already. */
13475 {
13480 }
13482 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13483 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13484 created by virtual register instantiation, register elimination, and
13485 similar optimizations. */
13487 {
13493 }
13495 /* Canonicalize
13496 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13497 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13502 {
13503 rtx constant;
13507 {
13510 }
13512 {
13515 }
13516 else
13520 {
13527 }
13528 }
13534 {
13537 }
13540 {
13543 }
13551 {
13554 }
13560 {
13564 {
13567 }
13571 }
13574 {
13578 {
13581 }
13585 }
13586 }
13589 }
13590 \f
13591 /* Print an integer constant expression in assembler syntax. Addition
13592 and subtraction are the only arithmetic that may appear in these
13593 expressions. FILE is the stdio stream to write to, X is the rtx, and
13594 CODE is the operand print code from the output string. */
13596 static void
13598 {
13602 {
13611 else
13612 {
13615 /* Mark the decl as referenced so that cgraph will
13616 output the function. */
13620 #if TARGET_MACHO
13624 #endif
13626 }
13634 /* FALLTHRU */
13645 /* This used to output parentheses around the expression,
13646 but that does not work on the 386 (either ATT or BSD assembler). */
13652 {
13653 /* We can use %d if the number is <32 bits and positive. */
13658 else
13660 }
13661 else
13662 /* We can't handle floating point constants;
13663 TARGET_PRINT_OPERAND must handle them. */
13668 /* Some assemblers need integer constants to appear first. */
13670 {
13674 }
13675 else
13676 {
13681 }
13696 {
13700 }
13705 {
13724 /* FIXME: This might be @TPOFF in Sun ld too. */
13733 else
13743 else
13749 #if TARGET_MACHO
13754 #endif
13758 }
13763 }
13764 }
13766 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13767 We need to emit DTP-relative relocations. */
13769 static void ATTRIBUTE_UNUSED
13771 {
13776 {
13784 }
13785 }
13787 /* Return true if X is a representation of the PIC register. This copes
13788 with calls from ix86_find_base_term, where the register might have
13789 been replaced by a cselib value. */
13791 static bool
13793 {
13797 else
13799 }
13801 /* Helper function for ix86_delegitimize_address.
13802 Attempt to delegitimize TLS local-exec accesses. */
13804 static rtx
13806 {
13831 {
13836 }
13842 }
13844 /* In the name of slightly smaller debug output, and to cater to
13845 general assembler lossage, recognize PIC+GOTOFF and turn it back
13846 into a direct symbol reference.
13848 On Darwin, this is necessary to avoid a crash, because Darwin
13849 has a different PIC label for each routine but the DWARF debugging
13850 information is not associated with any particular routine, so it's
13851 necessary to remove references to the PIC label from RTL stored by
13852 the DWARF output code. */
13854 static rtx
13856 {
13858 /* addend is NULL or some rtx if x is something+GOTOFF where
13859 something doesn't include the PIC register. */
13861 /* reg_addend is NULL or a multiple of some register. */
13863 /* const_addend is NULL or a const_int. */
13865 /* This is the result, or NULL. */
13874 {
13881 {
13887 }
13894 {
13897 {
13902 }
13904 }
13909 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
13910 and -mcmodel=medium -fpic. */
13911 }
13918 /* %ebx + GOT/GOTOFF */
13919 ;
13921 {
13922 /* %ebx + %reg * scale + GOT/GOTOFF */
13928 else
13929 {
13932 }
13933 }
13934 else
13940 {
13943 }
13964 {
13965 /* If the rest of original X doesn't involve the PIC register, add
13966 addend and subtract pic_offset_table_rtx. This can happen e.g.
13967 for code like:
13968 leal (%ebx, %ecx, 4), %ecx
13969 ...
13970 movl foo@GOTOFF(%ecx), %edx
13971 in which case we return (%ecx - %ebx) + foo. */
13974 pic_offset_table_rtx),
13975 result);
13976 else
13978 }
13980 {
13984 }
13986 }
13988 /* If X is a machine specific address (i.e. a symbol or label being
13989 referenced as a displacement from the GOT implemented using an
13990 UNSPEC), then return the base term. Otherwise return X. */
13992 rtx
13994 {
13995 rtx term;
13998 {
14012 }
14015 }
14016 \f
14017 static void
14020 {
14024 {
14027 }
14032 {
14035 {
14054 }
14058 {
14077 }
14084 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14085 Those same assemblers have the same but opposite lossage on cmov. */
14090 else
14095 {
14108 }
14116 {
14129 }
14132 /* ??? As above. */
14141 /* ??? As above. */
14146 else
14157 }
14159 }
14161 /* Print the name of register X to FILE based on its machine mode and number.
14162 If CODE is 'w', pretend the mode is HImode.
14163 If CODE is 'b', pretend the mode is QImode.
14164 If CODE is 'k', pretend the mode is SImode.
14165 If CODE is 'q', pretend the mode is DImode.
14166 If CODE is 'x', pretend the mode is V4SFmode.
14167 If CODE is 't', pretend the mode is V8SFmode.
14168 If CODE is 'h', pretend the reg is the 'high' byte register.
14169 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14170 If CODE is 'd', duplicate the operand for AVX instruction.
14171 */
14173 void
14175 {
14184 {
14188 }
14213 else
14216 /* Irritatingly, AMD extended registers use different naming convention
14217 from the normal registers: "r%d[bwd]" */
14219 {
14224 {
14238 /* no suffix */
14243 }
14245 }
14249 {
14252 {
14255 }
14256 /* FALLTHRU */
14262 /* FALLTHRU */
14265 normal:
14280 {
14285 }
14289 }
14293 {
14296 else
14298 }
14299 }
14301 /* Locate some local-dynamic symbol still in use by this function
14302 so that we can print its name in some tls_local_dynamic_base
14303 pattern. */
14305 static int
14307 {
14312 {
14315 }
14318 }
14322 {
14323 rtx insn;
14334 }
14336 /* Meaning of CODE:
14337 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14338 C -- print opcode suffix for set/cmov insn.
14339 c -- like C, but print reversed condition
14340 F,f -- likewise, but for floating-point.
14341 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14342 otherwise nothing
14343 R -- print the prefix for register names.
14344 z -- print the opcode suffix for the size of the current operand.
14345 Z -- likewise, with special suffixes for x87 instructions.
14346 * -- print a star (in certain assembler syntax)
14347 A -- print an absolute memory reference.
14348 E -- print address with DImode register names if TARGET_64BIT.
14349 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14350 s -- print a shift double count, followed by the assemblers argument
14351 delimiter.
14352 b -- print the QImode name of the register for the indicated operand.
14353 %b0 would print %al if operands[0] is reg 0.
14354 w -- likewise, print the HImode name of the register.
14355 k -- likewise, print the SImode name of the register.
14356 q -- likewise, print the DImode name of the register.
14357 x -- likewise, print the V4SFmode name of the register.
14358 t -- likewise, print the V8SFmode name of the register.
14359 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14360 y -- print "st(0)" instead of "st" as a register.
14361 d -- print duplicated register operand for AVX instruction.
14362 D -- print condition for SSE cmp instruction.
14363 P -- if PIC, print an @PLT suffix.
14364 p -- print raw symbol name.
14365 X -- don't print any sort of PIC '@' suffix for a symbol.
14366 & -- print some in-use local-dynamic symbol name.
14367 H -- print a memory address offset by 8; used for sse high-parts
14368 Y -- print condition for XOP pcom* instruction.
14369 + -- print a branch hint as 'cs' or 'ds' prefix
14370 ; -- print a semicolon (after prefixes due to bug in older gas).
14371 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14372 @ -- print a segment register of thread base pointer load
14373 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14374 */
14376 void
14378 {
14380 {
14382 {
14385 {
14391 /* Intel syntax. For absolute addresses, registers should not
14392 be surrounded by braces. */
14394 {
14399 }
14404 }
14410 /* Wrap address in an UNSPEC to declare special handling. */
14448 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14453 {
14467 output_operand_lossage
14470 }
14473 #endif
14478 {
14479 /* Opcodes don't get size suffixes if using Intel opcodes. */
14484 {
14502 output_operand_lossage
14505 }
14506 }
14509 warning
14511 /* FALLTHRU */
14514 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14519 {
14521 {
14523 #ifdef HAVE_AS_IX86_FILDS
14525 #endif
14533 #ifdef HAVE_AS_IX86_FILDQ
14535 #else
14537 #endif
14542 }
14543 }
14545 {
14546 /* 387 opcodes don't get size suffixes
14547 if the operands are registers. */
14552 {
14568 }
14569 }
14570 else
14571 {
14572 output_operand_lossage
14575 }
14577 output_operand_lossage
14597 {
14600 }
14605 {
14656 }
14660 /* Little bit of braindamage here. The SSE compare instructions
14661 does use completely different names for the comparisons that the
14662 fp conditional moves. */
14664 {
14667 {
14670 }
14676 {
14679 }
14685 {
14688 }
14697 {
14700 }
14706 {
14709 }
14715 {
14718 }
14729 }
14734 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14737 #endif
14742 {
14746 }
14750 file);
14755 {
14759 }
14760 /* It doesn't actually matter what mode we use here, as we're
14761 only going to use this for printing. */
14763 /* Output 'qword ptr' for intel assembler dialect. */
14772 #ifdef HAVE_AS_IX86_HLE
14774 #else
14776 #endif
14778 #ifdef HAVE_AS_IX86_HLE
14780 #else
14782 #endif
14783 /* We do not want to print value of the operand. */
14792 {
14797 else
14800 }
14803 {
14804 rtx x;
14813 {
14818 {
14820 bool cputaken
14823 /* Emit hints only in the case default branch prediction
14824 heuristics would fail. */
14826 {
14827 /* We use 3e (DS) prefix for taken branches and
14828 2e (CS) prefix for not taken branches. */
14831 else
14833 }
14834 }
14835 }
14837 }
14840 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14842 #endif
14849 /* The kernel uses a different segment register for performance
14850 reasons; a system call would not have to trash the userspace
14851 segment register, which would be expensive. */
14854 else
14869 }
14870 }
14876 {
14877 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14880 {
14883 {
14892 else
14898 }
14900 /* Check for explicit size override (codes 'b', 'w', 'k',
14901 'q' and 'x') */
14915 }
14918 /* Avoid (%rip) for call operands. */
14924 else
14926 }
14929 {
14930 REAL_VALUE_TYPE r;
14938 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14942 else
14944 }
14947 {
14948 REAL_VALUE_TYPE r;
14957 }
14959 /* These float cases don't actually occur as immediate operands. */
14961 {
14966 }
14968 else
14969 {
14970 /* We have patterns that allow zero sets of memory, for instance.
14971 In 64-bit mode, we should probably support all 8-byte vectors,
14972 since we can in fact encode that into an immediate. */
14974 {
14977 }
14980 {
14982 {
14985 }
14988 {
14991 else
14993 }
14994 }
14999 else
15001 }
15002 }
15004 static bool
15006 {
15009 }
15010 \f
15011 /* Print a memory operand whose address is ADDR. */
15013 static void
15015 {
15024 {
15031 }
15033 {
15037 }
15038 else
15049 {
15060 }
15062 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15064 {
15076 }
15078 {
15079 /* Displacement only requires special attention. */
15082 {
15086 }
15089 else
15091 }
15092 else
15093 {
15094 /* Print SImode register names to force addr32 prefix. */
15096 {
15097 #ifdef ENABLE_CHECKING
15100 {
15111 }
15112 #endif
15115 }
15117 && TARGET_X32
15118 && disp
15121 {
15122 /* X32 runs in 64-bit mode, where displacement, DISP, in
15123 address DISP(%r64), is encoded as 32-bit immediate sign-
15124 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15125 address is %r64 + 0xffffffffbffffd00. When %r64 <
15126 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15127 which is invalid for x32. The correct address is %r64
15128 - 0x40000300 == 0xf7ffdd64. To properly encode
15129 -0x40000300(%r64) for x32, we zero-extend negative
15130 displacement by forcing addr32 prefix which truncates
15131 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15132 zero-extend all negative displacements, including -1(%rsp).
15133 However, for small negative displacements, sign-extension
15134 won't cause overflow. We only zero-extend negative
15135 displacements if they < -16*1024*1024, which is also used
15136 to check legitimate address displacements for PIC. */
15138 }
15141 {
15143 {
15148 else
15150 }
15156 {
15161 }
15163 }
15164 else
15165 {
15169 {
15170 /* Pull out the offset of a symbol; print any symbol itself. */
15174 {
15178 }
15186 else
15188 }
15192 {
15195 {
15199 }
15200 }
15203 else
15207 {
15212 }
15214 }
15215 }
15216 }
15218 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15220 static bool
15222 {
15223 rtx op;
15230 {
15233 /* FIXME: This might be @TPOFF in Sun ld. */
15244 else
15256 else
15263 #if TARGET_MACHO
15269 #endif
15272 {
15277 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15279 #else
15281 #endif
15284 }
15289 }
15292 }
15293 \f
15294 /* Split one or more double-mode RTL references into pairs of half-mode
15295 references. The RTL can be REG, offsettable MEM, integer constant, or
15296 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15297 split and "num" is its length. lo_half and hi_half are output arrays
15298 that parallel "operands". */
15300 void
15303 {
15308 {
15317 }
15322 {
15325 /* simplify_subreg refuse to split volatile memory addresses,
15326 but we still have to handle it. */
15328 {
15331 }
15332 else
15333 {
15340 }
15341 }
15342 }
15343 \f
15344 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15345 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15346 is the expression of the binary operation. The output may either be
15347 emitted here, or returned to the caller, like all output_* functions.
15349 There is no guarantee that the operands are the same mode, as they
15350 might be within FLOAT or FLOAT_EXTEND expressions. */
15352 #ifndef SYSV386_COMPAT
15353 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15354 wants to fix the assemblers because that causes incompatibility
15355 with gcc. No-one wants to fix gcc because that causes
15356 incompatibility with assemblers... You can use the option of
15357 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15358 #define SYSV386_COMPAT 1
15359 #endif
15363 {
15369 #ifdef ENABLE_CHECKING
15370 /* Even if we do not want to check the inputs, this documents input
15371 constraints. Which helps in understanding the following code. */
15381 else
15383 #endif
15386 {
15391 else
15400 else
15409 else
15418 else
15425 }
15428 {
15430 {
15434 else
15436 }
15437 else
15438 {
15442 else
15444 }
15446 }
15450 {
15454 {
15458 }
15460 /* know operands[0] == operands[1]. */
15463 {
15466 }
15469 {
15471 /* How is it that we are storing to a dead operand[2]?
15472 Well, presumably operands[1] is dead too. We can't
15473 store the result to st(0) as st(0) gets popped on this
15474 instruction. Instead store to operands[2] (which I
15475 think has to be st(1)). st(1) will be popped later.
15476 gcc <= 2.8.1 didn't have this check and generated
15477 assembly code that the Unixware assembler rejected. */
15479 else
15482 }
15486 else
15493 {
15496 }
15499 {
15502 }
15505 {
15506 #if SYSV386_COMPAT
15507 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15508 derived assemblers, confusingly reverse the direction of
15509 the operation for fsub{r} and fdiv{r} when the
15510 destination register is not st(0). The Intel assembler
15511 doesn't have this brain damage. Read !SYSV386_COMPAT to
15512 figure out what the hardware really does. */
15515 else
15517 #else
15519 /* As above for fmul/fadd, we can't store to st(0). */
15521 else
15523 #endif
15525 }
15528 {
15529 #if SYSV386_COMPAT
15532 else
15534 #else
15537 else
15539 #endif
15541 }
15544 {
15547 else
15550 }
15552 {
15553 #if SYSV386_COMPAT
15555 #else
15557 #endif
15558 }
15559 else
15560 {
15561 #if SYSV386_COMPAT
15563 #else
15565 #endif
15566 }
15571 }
15575 }
15577 /* Check if a 256bit AVX register is referenced inside of EXP. */
15579 static int
15581 {
15592 }
15594 /* Return needed mode for entity in optimize_mode_switching pass. */
15596 static int
15598 {
15600 {
15601 rtx link;
15603 /* Needed mode is set to AVX_U128_CLEAN if there are
15604 no 256bit modes used in function arguments. */
15606 link;
15608 {
15610 {
15615 }
15616 }
15619 }
15621 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15622 changes state only when a 256bit register is written to, but we need
15623 to prevent the compiler from moving optimal insertion point above
15624 eventual read from 256bit register. */
15629 }
15631 /* Return mode that i387 must be switched into
15632 prior to the execution of insn. */
15634 static int
15636 {
15639 /* The mode UNINITIALIZED is used to store control word after a
15640 function call or ASM pattern. The mode ANY specify that function
15641 has no requirements on the control word and make no changes in the
15642 bits we are interested in. */
15656 {
15679 }
15682 }
15684 /* Return mode that entity must be switched into
15685 prior to the execution of insn. */
15687 int
15689 {
15691 {
15701 }
15703 }
15705 /* Check if a 256bit AVX register is referenced in stores. */
15707 static void
15709 {
15711 {
15714 }
15715 }
15717 /* Calculate mode of upper 128bit AVX registers after the insn. */
15719 static int
15721 {
15728 /* We know that state is clean after CALL insn if there are no
15729 256bit registers used in the function return register. */
15731 {
15736 }
15738 /* Otherwise, return current mode. Remember that if insn
15739 references AVX 256bit registers, the mode was already changed
15740 to DIRTY from MODE_NEEDED. */
15742 }
15744 /* Return the mode that an insn results in. */
15746 int
15748 {
15750 {
15760 }
15761 }
15763 static int
15765 {
15766 tree arg;
15768 /* Entry mode is set to AVX_U128_DIRTY if there are
15769 256bit modes used in function arguments. */
15772 {
15777 }
15780 }
15782 /* Return a mode that ENTITY is assumed to be
15783 switched to at function entry. */
15785 int
15787 {
15789 {
15799 }
15800 }
15802 static int
15804 {
15807 /* Exit mode is set to AVX_U128_DIRTY if there are
15808 256bit modes used in the function return register. */
15813 }
15815 /* Return a mode that ENTITY is assumed to be
15816 switched to at function exit. */
15818 int
15820 {
15822 {
15832 }
15833 }
15835 /* Output code to initialize control word copies used by trunc?f?i and
15836 rounding patterns. CURRENT_MODE is set to current control word,
15837 while NEW_MODE is set to new control word. */
15839 static void
15841 {
15843 rtx new_mode;
15854 {
15856 {
15858 /* round toward zero (truncate) */
15864 /* round down toward -oo */
15871 /* round up toward +oo */
15878 /* mask precision exception for nearbyint() */
15885 }
15886 }
15887 else
15888 {
15890 {
15892 /* round toward zero (truncate) */
15898 /* round down toward -oo */
15904 /* round up toward +oo */
15910 /* mask precision exception for nearbyint() */
15917 }
15918 }
15924 }
15926 /* Emit vzeroupper. */
15928 void
15930 {
15933 /* Cancel automatic vzeroupper insertion if there are
15934 live call-saved SSE registers at the insertion point. */
15946 }
15948 /* Generate one or more insns to set ENTITY to MODE. */
15950 void
15952 {
15954 {
15969 }
15970 }
15972 /* Output code for INSN to convert a float to a signed int. OPERANDS
15973 are the insn operands. The output may be [HSD]Imode and the input
15974 operand may be [SDX]Fmode. */
15978 {
15983 /* Jump through a hoop or two for DImode, since the hardware has no
15984 non-popping instruction. We used to do this a different way, but
15985 that was somewhat fragile and broke with post-reload splitters. */
15995 else
15996 {
16001 else
16005 }
16008 }
16010 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16011 have the values zero or one, indicates the ffreep insn's operand
16012 from the OPERANDS array. */
16016 {
16018 #ifdef HAVE_AS_IX86_FFREEP
16020 #else
16021 {
16031 }
16032 #endif
16035 }
16038 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16039 should be used. UNORDERED_P is true when fucom should be used. */
16043 {
16049 {
16052 }
16053 else
16054 {
16057 }
16060 {
16064 else
16066 else
16069 else
16071 }
16078 {
16080 {
16083 }
16084 else
16086 }
16089 && stack_top_dies
16092 {
16093 /* If both the top of the 387 stack dies, and the other operand
16094 is also a stack register that dies, then this must be a
16095 `fcompp' float compare */
16098 {
16099 /* There is no double popping fcomi variant. Fortunately,
16100 eflags is immune from the fstp's cc clobbering. */
16103 else
16106 }
16107 else
16108 {
16111 else
16113 }
16114 }
16115 else
16116 {
16117 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16120 {
16128 NULL,
16129 NULL,
16136 NULL,
16137 NULL,
16138 NULL,
16139 NULL
16140 };
16155 }
16156 }
16158 void
16160 {
16163 #ifdef ASM_QUAD
16166 #else
16168 #endif
16171 }
16173 void
16175 {
16178 #ifdef ASM_QUAD
16181 #else
16183 #endif
16184 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16190 #if TARGET_MACHO
16192 {
16196 }
16197 #endif
16198 else
16201 }
16202 \f
16203 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16204 for the target. */
16206 void
16208 {
16209 rtx tmp;
16211 /* We play register width games, which are only valid after reload. */
16214 /* Avoid HImode and its attendant prefix byte. */
16219 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16221 {
16224 }
16227 }
16229 /* X is an unchanging MEM. If it is a constant pool reference, return
16230 the constant pool rtx, else NULL. */
16232 rtx
16234 {
16241 }
16243 void
16245 {
16253 {
16254 rtx tmp;
16258 {
16264 }
16267 }
16271 {
16274 rtx tmp;
16279 else
16283 {
16290 }
16291 }
16295 {
16297 {
16298 #if TARGET_MACHO
16299 /* dynamic-no-pic */
16301 {
16302 rtx temp = ((reload_in_progress
16310 }
16312 {
16316 }
16319 else
16320 {
16328 }
16329 /* dynamic-no-pic */
16330 #endif
16331 }
16332 else
16333 {
16337 {
16343 }
16344 }
16345 }
16346 else
16347 {
16358 /* Force large constants in 64bit compilation into register
16359 to get them CSEed. */
16371 {
16372 /* If we are loading a floating point constant to a register,
16373 force the value to memory now, since we'll get better code
16374 out the back end. */
16378 {
16383 }
16384 }
16385 }
16388 }
16390 void
16392 {
16396 /* Force constants other than zero into memory. We do not know how
16397 the instructions used to build constants modify the upper 64 bits
16398 of the register, once we have that information we may be able
16399 to handle some of them more efficiently. */
16408 /* We need to check memory alignment for SSE mode since attribute
16409 can make operands unaligned. */
16414 {
16417 /* ix86_expand_vector_move_misalign() does not like constants ... */
16423 /* ... nor both arguments in memory. */
16431 }
16433 /* Make operand1 a register if it isn't already. */
16437 {
16440 }
16443 }
16445 /* Split 32-byte AVX unaligned load and store if needed. */
16447 static void
16449 {
16450 rtx m;
16457 {
16478 }
16481 {
16483 {
16490 }
16491 else
16493 }
16495 {
16497 {
16502 }
16503 else
16505 }
16506 else
16508 }
16510 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16511 straight to ix86_expand_vector_move. */
16512 /* Code generation for scalar reg-reg moves of single and double precision data:
16513 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16514 movaps reg, reg
16515 else
16516 movss reg, reg
16517 if (x86_sse_partial_reg_dependency == true)
16518 movapd reg, reg
16519 else
16520 movsd reg, reg
16522 Code generation for scalar loads of double precision data:
16523 if (x86_sse_split_regs == true)
16524 movlpd mem, reg (gas syntax)
16525 else
16526 movsd mem, reg
16528 Code generation for unaligned packed loads of single precision data
16529 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16530 if (x86_sse_unaligned_move_optimal)
16531 movups mem, reg
16533 if (x86_sse_partial_reg_dependency == true)
16534 {
16535 xorps reg, reg
16536 movlps mem, reg
16537 movhps mem+8, reg
16538 }
16539 else
16540 {
16541 movlps mem, reg
16542 movhps mem+8, reg
16543 }
16545 Code generation for unaligned packed loads of double precision data
16546 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16547 if (x86_sse_unaligned_move_optimal)
16548 movupd mem, reg
16550 if (x86_sse_split_regs == true)
16551 {
16552 movlpd mem, reg
16553 movhpd mem+8, reg
16554 }
16555 else
16556 {
16557 movsd mem, reg
16558 movhpd mem+8, reg
16559 }
16560 */
16562 void
16564 {
16572 {
16574 {
16579 /* FALLTHRU */
16587 }
16590 }
16593 {
16594 /* ??? If we have typed data, then it would appear that using
16595 movdqu is the only way to get unaligned data loaded with
16596 integer type. */
16598 {
16601 /* We will eventually emit movups based on insn attributes. */
16603 }
16605 {
16606 rtx zero;
16609 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16610 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16612 {
16613 /* We will eventually emit movups based on insn attributes. */
16616 }
16618 /* When SSE registers are split into halves, we can avoid
16619 writing to the top half twice. */
16621 {
16624 }
16625 else
16626 {
16627 /* ??? Not sure about the best option for the Intel chips.
16628 The following would seem to satisfy; the register is
16629 entirely cleared, breaking the dependency chain. We
16630 then store to the upper half, with a dependency depth
16631 of one. A rumor has it that Intel recommends two movsd
16632 followed by an unpacklpd, but this is unconfirmed. And
16633 given that the dependency depth of the unpacklpd would
16634 still be one, I'm not sure why this would be better. */
16636 }
16642 }
16643 else
16644 {
16646 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16647 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16649 {
16654 }
16658 else
16668 }
16669 }
16671 {
16673 {
16676 /* We will eventually emit movups based on insn attributes. */
16678 }
16680 {
16682 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16683 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16685 /* We will eventually emit movups based on insn attributes. */
16687 else
16688 {
16693 }
16694 }
16695 else
16696 {
16701 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16702 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16704 {
16707 }
16708 else
16709 {
16714 }
16715 }
16716 }
16717 else
16719 }
16721 /* Expand a push in MODE. This is some mode for which we do not support
16722 proper push instructions, at least from the registers that we expect
16723 the value to live in. */
16725 void
16727 {
16728 rtx tmp;
16738 /* When we push an operand onto stack, it has to be aligned at least
16739 at the function argument boundary. However since we don't have
16740 the argument type, we can't determine the actual argument
16741 boundary. */
16743 }
16745 /* Helper function of ix86_fixup_binary_operands to canonicalize
16746 operand order. Returns true if the operands should be swapped. */
16748 static bool
16750 rtx operands[])
16751 {
16756 /* If the operation is not commutative, we can't do anything. */
16760 /* Highest priority is that src1 should match dst. */
16766 /* Next highest priority is that immediate constants come second. */
16772 /* Lowest priority is that memory references should come second. */
16779 }
16782 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16783 destination to use for the operation. If different from the true
16784 destination in operands[0], a copy operation will be required. */
16786 rtx
16788 rtx operands[])
16789 {
16794 /* Canonicalize operand order. */
16796 {
16797 rtx temp;
16799 /* It is invalid to swap operands of different modes. */
16805 }
16807 /* Both source operands cannot be in memory. */
16809 {
16810 /* Optimization: Only read from memory once. */
16812 {
16815 }
16816 else
16818 }
16820 /* If the destination is memory, and we do not have matching source
16821 operands, do things in registers. */
16825 /* Source 1 cannot be a constant. */
16829 /* Source 1 cannot be a non-matching memory. */
16833 /* Improve address combine. */
16842 }
16844 /* Similarly, but assume that the destination has already been
16845 set up properly. */
16847 void
16850 {
16853 }
16855 /* Attempt to expand a binary operator. Make the expansion closer to the
16856 actual machine, then just general_operand, which will allow 3 separate
16857 memory references (one output, two input) in a single insn. */
16859 void
16861 rtx operands[])
16862 {
16869 /* Emit the instruction. */
16873 {
16874 /* Reload doesn't know about the flags register, and doesn't know that
16875 it doesn't want to clobber it. We can only do this with PLUS. */
16878 }
16882 {
16883 /* This is going to be an LEA; avoid splitting it later. */
16885 }
16886 else
16887 {
16890 }
16892 /* Fix up the destination if needed. */
16895 }
16897 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16898 the given OPERANDS. */
16900 void
16902 rtx operands[])
16903 {
16906 {
16909 }
16911 {
16914 }
16915 /* Optimize (__m128i) d | (__m128i) e and similar code
16916 when d and e are float vectors into float vector logical
16917 insn. In C/C++ without using intrinsics there is no other way
16918 to express vector logical operation on float vectors than
16919 to cast them temporarily to integer vectors. */
16921 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16930 {
16931 rtx dst;
16933 {
16940 {
16943 }
16944 else
16945 {
16950 }
16961 }
16962 }
16971 }
16973 /* Return TRUE or FALSE depending on whether the binary operator meets the
16974 appropriate constraints. */
16976 bool
16979 {
16984 /* Both source operands cannot be in memory. */
16988 /* Canonicalize operand order for commutative operators. */
16990 {
16994 }
16996 /* If the destination is memory, we must have a matching source operand. */
17000 /* Source 1 cannot be a constant. */
17004 /* Source 1 cannot be a non-matching memory. */
17006 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17014 }
17016 /* Attempt to expand a unary operator. Make the expansion closer to the
17017 actual machine, then just general_operand, which will allow 2 separate
17018 memory references (one output, one input) in a single insn. */
17020 void
17022 rtx operands[])
17023 {
17030 /* If the destination is memory, and we do not have matching source
17031 operands, do things in registers. */
17034 {
17037 else
17039 }
17041 /* When source operand is memory, destination must match. */
17045 /* Emit the instruction. */
17049 {
17050 /* Reload doesn't know about the flags register, and doesn't know that
17051 it doesn't want to clobber it. */
17054 }
17055 else
17056 {
17059 }
17061 /* Fix up the destination if needed. */
17064 }
17066 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17067 divisor are within the range [0-255]. */
17069 void
17072 {
17081 {
17094 }
17101 /* Use 8bit unsigned divimod if dividend and divisor are within
17102 the range [0-255]. */
17111 pc_rtx);
17116 /* Generate original signed/unsigned divimod. */
17121 /* Branch to the end. */
17125 /* Generate 8bit unsigned divide. */
17127 /* Don't use operands[0] for result of 8bit divide since not all
17128 registers support QImode ZERO_EXTRACT. */
17135 {
17138 }
17139 else
17140 {
17143 }
17145 /* Extract remainder from AH. */
17149 else
17150 {
17151 /* Need a new scratch register since the old one has result
17152 of 8bit divide. */
17156 }
17159 /* Zero extend quotient from AL. */
17165 }
17167 #define LEA_MAX_STALL (3)
17168 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17170 /* Increase given DISTANCE in half-cycles according to
17171 dependencies between PREV and NEXT instructions.
17172 Add 1 half-cycle if there is no dependency and
17173 go to next cycle if there is some dependecy. */
17175 static unsigned int
17177 {
17194 }
17196 /* Function checks if instruction INSN defines register number
17197 REGNO1 or REGNO2. */
17199 static bool
17201 rtx insn)
17202 {
17210 {
17212 }
17215 }
17217 /* Function checks if instruction INSN uses register number
17218 REGNO as a part of address expression. */
17220 static bool
17222 {
17230 }
17232 /* Search backward for non-agu definition of register number REGNO1
17233 or register number REGNO2 in basic block starting from instruction
17234 START up to head of basic block or instruction INSN.
17236 Function puts true value into *FOUND var if definition was found
17237 and false otherwise.
17239 Distance in half-cycles between START and found instruction or head
17240 of BB is added to DISTANCE and returned. */
17242 static int
17246 {
17256 {
17258 {
17261 {
17264 {
17267 }
17268 }
17271 }
17276 }
17279 }
17281 /* Search backward for non-agu definition of register number REGNO1
17282 or register number REGNO2 in INSN's basic block until
17283 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17284 2. Reach neighbour BBs boundary, or
17285 3. Reach agu definition.
17286 Returns the distance between the non-agu definition point and INSN.
17287 If no definition point, returns -1. */
17289 static int
17291 rtx insn)
17292 {
17303 {
17304 edge e;
17305 edge_iterator ei;
17310 {
17313 }
17319 else
17320 {
17325 {
17326 int bb_dist
17332 {
17339 }
17340 }
17343 }
17344 }
17346 /* get_attr_type may modify recog data. We want to make sure
17347 that recog data is valid for instruction INSN, on which
17348 distance_non_agu_define is called. INSN is unchanged here. */
17355 }
17357 /* Return the distance in half-cycles between INSN and the next
17358 insn that uses register number REGNO in memory address added
17359 to DISTANCE. Return -1 if REGNO0 is set.
17361 Put true value into *FOUND if register usage was found and
17362 false otherwise.
17363 Put true value into *REDEFINED if register redefinition was
17364 found and false otherwise. */
17366 static int
17370 {
17381 {
17383 {
17386 {
17387 /* Return DISTANCE if OP0 is used in memory
17388 address in NEXT. */
17391 }
17394 {
17395 /* Return -1 if OP0 is set in NEXT. */
17398 }
17401 }
17407 }
17410 }
17412 /* Return the distance between INSN and the next insn that uses
17413 register number REGNO0 in memory address. Return -1 if no such
17414 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17416 static int
17418 {
17430 {
17431 edge e;
17432 edge_iterator ei;
17437 {
17440 }
17446 else
17447 {
17453 {
17454 int bb_dist
17459 {
17466 }
17467 }
17470 }
17471 }
17477 }
17479 /* Define this macro to tune LEA priority vs ADD, it take effect when
17480 there is a dilemma of choicing LEA or ADD
17481 Negative value: ADD is more preferred than LEA
17482 Zero: Netrual
17483 Positive value: LEA is more preferred than ADD*/
17484 #define IX86_LEA_PRIORITY 0
17486 /* Return true if usage of lea INSN has performance advantage
17487 over a sequence of instructions. Instructions sequence has
17488 SPLIT_COST cycles higher latency than lea latency. */
17490 static bool
17493 {
17496 /* For Silvermont if using a 2-source or 3-source LEA for
17497 non-destructive destination purposes, or due to wanting
17498 ability to use SCALE, the use of LEA is justified. */
17500 {
17508 }
17514 {
17515 /* If there is no non AGU operand definition, no AGU
17516 operand usage and split cost is 0 then both lea
17517 and non lea variants have same priority. Currently
17518 we prefer lea for 64 bit code and non lea on 32 bit
17519 code. */
17522 else
17524 }
17526 /* With longer definitions distance lea is more preferable.
17527 Here we change it to take into account splitting cost and
17528 lea priority. */
17531 /* If there is no use in memory addess then we just check
17532 that split cost exceeds AGU stall. */
17536 /* If this insn has both backward non-agu dependence and forward
17537 agu dependence, the one with short distance takes effect. */
17539 }
17541 /* Return true if it is legal to clobber flags by INSN and
17542 false otherwise. */
17544 static bool
17546 {
17549 bitmap live;
17552 {
17554 {
17561 }
17567 }
17571 }
17573 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17574 move and add to avoid AGU stalls. */
17576 bool
17578 {
17581 /* Check if we need to optimize. */
17585 /* Check it is correct to split here. */
17593 /* We need to split only adds with non destructive
17594 destination operand. */
17597 else
17599 }
17601 /* Return true if we should emit lea instruction instead of mov
17602 instruction. */
17604 bool
17606 {
17609 /* Check if we need to optimize. */
17613 /* Use lea for reg to reg moves only. */
17621 }
17623 /* Return true if we need to split lea into a sequence of
17624 instructions to avoid AGU stalls. */
17626 bool
17628 {
17634 /* Check we need to optimize. */
17638 /* Check it is correct to split here. */
17645 /* There should be at least two components in the address. */
17650 /* We should not split into add if non legitimate pic
17651 operand is used as displacement. */
17666 /* Compute how many cycles we will add to execution time
17667 if split lea into a sequence of instructions. */
17669 {
17670 /* Have to use mov instruction if non desctructive
17671 destination form is used. */
17675 /* Have to add index to base if both exist. */
17679 /* Have to use shift and adds if scale is 2 or greater. */
17681 {
17686 else
17688 }
17690 /* Have to use add instruction with immediate if
17691 disp is non zero. */
17695 /* Subtract the price of lea. */
17697 }
17701 }
17703 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17704 matches destination. RTX includes clobber of FLAGS_REG. */
17706 static void
17709 {
17716 }
17718 /* Return true if regno1 def is nearest to the insn. */
17720 static bool
17722 {
17729 {
17731 {
17734 }
17740 }
17742 /* None of the regs is defined in the bb. */
17744 }
17746 /* Split lea instructions into a sequence of instructions
17747 which are executed on ALU to avoid AGU stalls.
17748 It is assumed that it is allowed to clobber flags register
17749 at lea position. */
17751 void
17753 {
17769 {
17772 }
17775 {
17778 }
17784 {
17785 /* Case r1 = r1 + ... */
17787 {
17788 /* If we have a case r1 = r1 + C * r1 then we
17789 should use multiplication which is very
17790 expensive. Assume cost model is wrong if we
17791 have such case here. */
17796 }
17797 else
17798 {
17799 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17803 /* Use shift for scaling. */
17812 }
17813 }
17815 {
17818 }
17819 else
17820 {
17822 {
17825 }
17827 {
17830 }
17831 else
17832 {
17837 else
17838 {
17839 rtx tmp1;
17841 /* Find better operand for SET instruction, depending
17842 on which definition is farther from the insn. */
17845 else
17855 }
17858 }
17862 }
17863 }
17865 /* Return true if it is ok to optimize an ADD operation to LEA
17866 operation to avoid flag register consumation. For most processors,
17867 ADD is faster than LEA. For the processors like ATOM, if the
17868 destination register of LEA holds an actual address which will be
17869 used soon, LEA is better and otherwise ADD is better. */
17871 bool
17873 {
17878 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17886 }
17888 /* Return true if destination reg of SET_BODY is shift count of
17889 USE_BODY. */
17891 static bool
17893 {
17894 rtx set_dest;
17895 rtx shift_rtx;
17898 /* Retrieve destination of SET_BODY. */
17900 {
17909 use_body))
17914 }
17916 /* Retrieve shift count of USE_BODY. */
17918 {
17930 }
17938 {
17941 /* Return true if shift count is dest of SET_BODY. */
17943 {
17944 /* Add check since it can be invoked before register
17945 allocation in pre-reload schedule. */
17951 }
17952 }
17955 }
17957 /* Return true if destination reg of SET_INSN is shift count of
17958 USE_INSN. */
17960 bool
17962 {
17965 }
17967 /* Return TRUE or FALSE depending on whether the unary operator meets the
17968 appropriate constraints. */
17970 bool
17974 {
17975 /* If one of operands is memory, source and destination must match. */
17981 }
17983 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17984 are ok, keeping in mind the possible movddup alternative. */
17986 bool
17988 {
17994 }
17996 /* Post-reload splitter for converting an SF or DFmode value in an
17997 SSE register into an unsigned SImode. */
17999 void
18001 {
18012 /* Load up the value into the low element. We must ensure that the other
18013 elements are valid floats -- zero is the easiest such value. */
18015 {
18018 else
18020 }
18021 else
18022 {
18027 else
18029 }
18049 else
18054 }
18056 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18057 Expects the 64-bit DImode to be supplied in a pair of integral
18058 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18059 -mfpmath=sse, !optimize_size only. */
18061 void
18063 {
18067 rtx x;
18073 {
18076 }
18077 else
18078 {
18082 }
18090 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18093 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18094 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18095 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18096 (0x1.0p84 + double(fp_value_hi_xmm)).
18097 Note these exponents differ by 32. */
18101 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18102 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18111 /* Add the upper and lower DFmode values together. */
18114 else
18115 {
18119 }
18122 }
18124 /* Not used, but eases macroization of patterns. */
18125 void
18127 rtx input ATTRIBUTE_UNUSED)
18128 {
18130 }
18132 /* Convert an unsigned SImode value into a DFmode. Only currently used
18133 for SSE, but applicable anywhere. */
18135 void
18137 {
18138 REAL_VALUE_TYPE TWO31r;
18153 }
18155 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18156 32-bit mode; otherwise we have a direct convert instruction. */
18158 void
18160 {
18161 REAL_VALUE_TYPE TWO32r;
18179 }
18181 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18182 For x86_32, -mfpmath=sse, !optimize_size only. */
18183 void
18185 {
18186 REAL_VALUE_TYPE ONE16r;
18205 }
18207 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18208 a vector of unsigned ints VAL to vector of floats TARGET. */
18210 void
18212 {
18214 REAL_VALUE_TYPE TWO16r;
18221 else
18226 OPTAB_DIRECT);
18237 OPTAB_DIRECT);
18239 OPTAB_DIRECT);
18242 }
18244 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18245 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18246 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18247 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18249 rtx
18251 {
18252 REAL_VALUE_TYPE TWO31r;
18267 {
18273 }
18282 OPTAB_DIRECT);
18283 else
18284 {
18290 OPTAB_DIRECT);
18291 }
18294 }
18296 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18297 then replicate the value for all elements of the vector
18298 register. */
18300 rtx
18302 {
18304 rtvec v;
18308 {
18335 }
18336 }
18338 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18339 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18340 for an SSE register. If VECT is true, then replicate the mask for
18341 all elements of the vector register. If INVERT is true, then create
18342 a mask excluding the sign bit. */
18344 rtx
18346 {
18350 rtx v;
18351 rtx mask;
18353 /* Find the sign bit, sign extended to 2*HWI. */
18355 {
18375 else
18383 {
18386 }
18387 else
18388 {
18389 rtvec vec;
18395 {
18398 }
18399 else
18409 }
18414 }
18419 /* Force this value into the low part of a fp vector constant. */
18428 }
18430 /* Generate code for floating point ABS or NEG. */
18432 void
18434 rtx operands[])
18435 {
18446 {
18452 }
18454 /* NEG and ABS performed with SSE use bitwise mask operations.
18455 Create the appropriate mask now. */
18458 else
18468 {
18470 rtvec par;
18475 else
18476 {
18479 }
18481 }
18482 else
18484 }
18486 /* Expand a copysign operation. Special case operand 0 being a constant. */
18488 void
18490 {
18504 else
18508 {
18515 {
18518 else
18519 {
18523 }
18524 }
18534 else
18538 }
18539 else
18540 {
18550 else
18554 }
18555 }
18557 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18558 be a constant, and so has already been expanded into a vector constant. */
18560 void
18562 {
18578 {
18581 }
18582 }
18584 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18585 so we have to do two masks. */
18587 void
18589 {
18604 {
18605 /* Shouldn't happen often (it's useless, obviously), but when it does
18606 we'd generate incorrect code if we continue below. */
18609 }
18612 {
18623 }
18624 else
18625 {
18627 {
18629 }
18631 {
18635 }
18639 {
18642 }
18644 {
18649 }
18651 }
18655 }
18657 /* Return TRUE or FALSE depending on whether the first SET in INSN
18658 has source and destination with matching CC modes, and that the
18659 CC mode is at least as constrained as REQ_MODE. */
18661 bool
18663 {
18664 rtx set;
18675 {
18685 /* FALLTHRU */
18689 /* FALLTHRU */
18693 /* FALLTHRU */
18707 }
18710 }
18712 /* Generate insn patterns to do an integer compare of OPERANDS. */
18714 static rtx
18716 {
18723 /* This is very simple, but making the interface the same as in the
18724 FP case makes the rest of the code easier. */
18728 /* Return the test that should be put into the flags user, i.e.
18729 the bcc, scc, or cmov instruction. */
18731 }
18733 /* Figure out whether to use ordered or unordered fp comparisons.
18734 Return the appropriate mode to use. */
18736 enum machine_mode
18738 {
18739 /* ??? In order to make all comparisons reversible, we do all comparisons
18740 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18741 all forms trapping and nontrapping comparisons, we can make inequality
18742 comparisons trapping again, since it results in better code when using
18743 FCOM based compares. */
18745 }
18747 enum machine_mode
18749 {
18753 {
18756 }
18759 {
18760 /* Only zero flag is needed. */
18764 /* Codes needing carry flag. */
18767 /* Detect overflow checks. They need just the carry flag. */
18771 else
18775 /* Detect overflow checks. They need just the carry flag. */
18779 else
18781 /* Codes possibly doable only with sign flag when
18782 comparing against zero. */
18787 else
18788 /* For other cases Carry flag is not required. */
18790 /* Codes doable only with sign flag when comparing
18791 against zero, but we miss jump instruction for it
18792 so we need to use relational tests against overflow
18793 that thus needs to be zero. */
18798 else
18800 /* strcmp pattern do (use flags) and combine may ask us for proper
18801 mode. */
18806 }
18807 }
18809 /* Return the fixed registers used for condition codes. */
18811 static bool
18813 {
18817 }
18819 /* If two condition code modes are compatible, return a condition code
18820 mode which is compatible with both. Otherwise, return
18821 VOIDmode. */
18823 static enum machine_mode
18825 {
18842 {
18856 {
18870 }
18874 /* These are only compatible with themselves, which we already
18875 checked above. */
18877 }
18878 }
18881 /* Return a comparison we can do and that it is equivalent to
18882 swap_condition (code) apart possibly from orderedness.
18883 But, never change orderedness if TARGET_IEEE_FP, returning
18884 UNKNOWN in that case if necessary. */
18886 static enum rtx_code
18888 {
18890 {
18901 }
18902 }
18904 /* Return cost of comparison CODE using the best strategy for performance.
18905 All following functions do use number of instructions as a cost metrics.
18906 In future this should be tweaked to compute bytes for optimize_size and
18907 take into account performance of various instructions on various CPUs. */
18909 static int
18911 {
18914 /* The cost of code using bit-twiddling on %ah. */
18916 {
18939 }
18942 {
18949 }
18950 }
18952 /* Return strategy to use for floating-point. We assume that fcomi is always
18953 preferrable where available, since that is also true when looking at size
18954 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18956 enum ix86_fpcmp_strategy
18958 {
18959 /* Do fcomi/sahf based test when profitable. */
18968 }
18970 /* Swap, force into registers, or otherwise massage the two operands
18971 to a fp comparison. The operands are updated in place; the new
18972 comparison code is returned. */
18974 static enum rtx_code
18976 {
18982 /* All of the unordered compare instructions only work on registers.
18983 The same is true of the fcomi compare instructions. The XFmode
18984 compare instructions require registers except when comparing
18985 against zero or when converting operand 1 from fixed point to
18986 floating point. */
18995 {
18998 }
18999 else
19000 {
19001 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19002 things around if they appear profitable, otherwise force op0
19003 into a register. */
19009 {
19012 {
19013 rtx tmp;
19016 }
19017 }
19023 {
19028 {
19031 }
19032 else
19034 }
19035 }
19037 /* Try to rearrange the comparison to make it cheaper. */
19041 {
19042 rtx tmp;
19047 }
19052 }
19054 /* Convert comparison codes we use to represent FP comparison to integer
19055 code that will result in proper branch. Return UNKNOWN if no such code
19056 is available. */
19058 enum rtx_code
19060 {
19062 {
19085 }
19086 }
19088 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19090 static rtx
19092 {
19099 /* Do fcomi/sahf based test when profitable. */
19101 {
19106 tmp);
19114 tmp);
19123 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19130 /* In the unordered case, we have to check C2 for NaN's, which
19131 doesn't happen to work out to anything nice combination-wise.
19132 So do some bit twiddling on the value we've got in AH to come
19133 up with an appropriate set of condition codes. */
19137 {
19141 {
19144 }
19145 else
19146 {
19152 }
19157 {
19162 }
19163 else
19164 {
19167 }
19172 {
19175 }
19176 else
19177 {
19181 }
19186 {
19192 }
19193 else
19194 {
19197 }
19202 {
19207 }
19208 else
19209 {
19212 }
19217 {
19222 }
19223 else
19224 {
19227 }
19241 }
19246 }
19248 /* Return the test that should be put into the flags user, i.e.
19249 the bcc, scc, or cmov instruction. */
19252 const0_rtx);
19253 }
19255 static rtx
19257 {
19258 rtx ret;
19264 {
19267 }
19268 else
19272 }
19274 void
19276 {
19278 rtx tmp;
19281 {
19288 simple:
19292 pc_rtx);
19300 /* Expand DImode branch into multiple compare+branch. */
19301 {
19307 {
19310 }
19317 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19318 avoid two branches. This costs one extra insn, so disable when
19319 optimizing for size. */
19324 {
19342 }
19344 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19345 op1 is a constant and the low word is zero, then we can just
19346 examine the high word. Similarly for low word -1 and
19347 less-or-equal-than or greater-than. */
19351 {
19354 {
19357 }
19361 {
19364 }
19368 }
19370 /* Otherwise, we need two or three jumps. */
19379 {
19393 }
19395 /*
19396 * a < b =>
19397 * if (hi(a) < hi(b)) goto true;
19398 * if (hi(a) > hi(b)) goto false;
19399 * if (lo(a) < lo(b)) goto true;
19400 * false:
19401 */
19413 }
19418 }
19419 }
19421 /* Split branch based on floating point condition. */
19422 void
19425 {
19426 rtx condition;
19427 rtx i;
19430 {
19435 }
19438 tmp);
19440 /* Remove pushed operand from stack. */
19450 }
19452 void
19454 {
19455 rtx ret;
19462 }
19464 /* Expand comparison setting or clearing carry flag. Return true when
19465 successful and set pop for the operation. */
19466 static bool
19468 {
19472 /* Do not handle double-mode compares that go through special path. */
19477 {
19482 /* Shortcut: following common codes never translate
19483 into carry flag compares. */
19488 /* These comparisons require zero flag; swap operands so they won't. */
19491 {
19496 }
19498 /* Try to expand the comparison and verify that we end up with
19499 carry flag based comparison. This fails to be true only when
19500 we decide to expand comparison using arithmetic that is not
19501 too common scenario. */
19510 else
19519 }
19525 {
19530 /* Convert a==0 into (unsigned)a<1. */
19539 /* Convert a>b into b<a or a>=b-1. */
19543 {
19545 /* Bail out on overflow. We still can swap operands but that
19546 would force loading of the constant into register. */
19551 }
19552 else
19553 {
19558 }
19561 /* Convert a>=0 into (unsigned)a<0x80000000. */
19579 }
19580 /* Swapping operands may cause constant to appear as first operand. */
19582 {
19586 }
19590 }
19592 bool
19594 {
19618 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19619 HImode insns, we'd be swallowed in word prefix ops. */
19625 {
19629 HOST_WIDE_INT diff;
19632 /* Sign bit compares are better done using shifts than we do by using
19633 sbb. */
19636 {
19637 /* Detect overlap between destination and compare sources. */
19641 {
19642 rtx flags;
19651 {
19653 compare_code
19655 }
19657 /* To simplify rest of code, restrict to the GEU case. */
19659 {
19665 }
19666 else
19667 {
19670 reverse_condition_maybe_unordered
19672 else
19675 }
19684 else
19687 }
19688 else
19689 {
19692 else
19693 {
19698 }
19700 }
19703 {
19704 /*
19705 * cmpl op0,op1
19706 * sbbl dest,dest
19707 * [addl dest, ct]
19708 *
19709 * Size 5 - 8.
19710 */
19715 }
19717 {
19718 /*
19719 * cmpl op0,op1
19720 * sbbl dest,dest
19721 * orl $ct, dest
19722 *
19723 * Size 8.
19724 */
19728 }
19730 {
19731 /*
19732 * cmpl op0,op1
19733 * sbbl dest,dest
19734 * notl dest
19735 * [addl dest, cf]
19736 *
19737 * Size 8 - 11.
19738 */
19744 }
19745 else
19746 {
19747 /*
19748 * cmpl op0,op1
19749 * sbbl dest,dest
19750 * [notl dest]
19751 * andl cf - ct, dest
19752 * [addl dest, ct]
19753 *
19754 * Size 8 - 11.
19755 */
19758 {
19762 }
19772 }
19778 }
19781 {
19784 HOST_WIDE_INT tmp;
19789 {
19792 /* We may be reversing unordered compare to normal compare, that
19793 is not valid in general (we may convert non-trapping condition
19794 to trapping one), however on i386 we currently emit all
19795 comparisons unordered. */
19798 }
19799 else
19800 {
19803 }
19804 }
19809 {
19814 {
19819 }
19820 }
19822 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19826 {
19827 /* If lea code below could be used, only optimize
19828 if it results in a 2 insn sequence. */
19834 {
19835 /*
19836 * notl op1 (if necessary)
19837 * sarl $31, op1
19838 * orl cf, op1
19839 */
19841 {
19845 }
19856 }
19857 }
19865 {
19866 /*
19867 * xorl dest,dest
19868 * cmpl op1,op2
19869 * setcc dest
19870 * lea cf(dest*(ct-cf)),dest
19871 *
19872 * Size 14.
19873 *
19874 * This also catches the degenerate setcc-only case.
19875 */
19877 rtx tmp;
19883 /* On x86_64 the lea instruction operates on Pmode, so we need
19884 to get arithmetics done in proper mode to match. */
19887 else
19888 {
19889 rtx out1;
19892 nops++;
19894 {
19896 nops++;
19897 }
19898 }
19900 {
19902 nops++;
19903 }
19905 {
19908 else
19910 }
19915 }
19917 /*
19918 * General case: Jumpful:
19919 * xorl dest,dest cmpl op1, op2
19920 * cmpl op1, op2 movl ct, dest
19921 * setcc dest jcc 1f
19922 * decl dest movl cf, dest
19923 * andl (cf-ct),dest 1:
19924 * addl ct,dest
19925 *
19926 * Size 20. Size 14.
19927 *
19928 * This is reasonably steep, but branch mispredict costs are
19929 * high on modern cpus, so consider failing only if optimizing
19930 * for space.
19931 */
19936 {
19938 {
19945 {
19948 /* We may be reversing unordered compare to normal compare,
19949 that is not valid in general (we may convert non-trapping
19950 condition to trapping one), however on i386 we currently
19951 emit all comparisons unordered. */
19953 }
19954 else
19955 {
19959 }
19960 }
19963 {
19964 /* notl op1 (if needed)
19965 sarl $31, op1
19966 andl (cf-ct), op1
19967 addl ct, op1
19969 For x < 0 (resp. x <= -1) there will be no notl,
19970 so if possible swap the constants to get rid of the
19971 complement.
19972 True/false will be -1/0 while code below (store flag
19973 followed by decrement) is 0/-1, so the constants need
19974 to be exchanged once more. */
19977 {
19980 }
19981 else
19982 {
19986 }
19989 }
19990 else
19991 {
19995 constm1_rtx,
19997 }
20009 }
20010 }
20013 {
20014 /* Try a few things more with specific constants and a variable. */
20016 optab op;
20022 /* If one of the two operands is an interesting constant, load a
20023 constant with the above and mask it in with a logical operation. */
20026 {
20032 else
20034 }
20036 {
20042 else
20044 }
20045 else
20052 /* Recurse to get the constant loaded. */
20056 /* Mask in the interesting variable. */
20058 OPTAB_WIDEN);
20063 }
20065 /*
20066 * For comparison with above,
20067 *
20068 * movl cf,dest
20069 * movl ct,tmp
20070 * cmpl op1,op2
20071 * cmovcc tmp,dest
20072 *
20073 * Size 15.
20074 */
20096 }
20098 /* Swap, force into registers, or otherwise massage the two operands
20099 to an sse comparison with a mask result. Thus we differ a bit from
20100 ix86_prepare_fp_compare_args which expects to produce a flags result.
20102 The DEST operand exists to help determine whether to commute commutative
20103 operators. The POP0/POP1 operands are updated in place. The new
20104 comparison code is returned, or UNKNOWN if not implementable. */
20106 static enum rtx_code
20109 {
20110 rtx tmp;
20113 {
20116 /* AVX supports all the needed comparisons. */
20119 /* We have no LTGT as an operator. We could implement it with
20120 NE & ORDERED, but this requires an extra temporary. It's
20121 not clear that it's worth it. */
20128 /* These are supported directly. */
20135 /* AVX has 3 operand comparisons, no need to swap anything. */
20138 /* For commutative operators, try to canonicalize the destination
20139 operand to be first in the comparison - this helps reload to
20140 avoid extra moves. */
20143 /* FALLTHRU */
20149 /* These are not supported directly before AVX, and furthermore
20150 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20151 comparison operands to transform into something that is
20152 supported. */
20161 }
20164 }
20166 /* Detect conditional moves that exactly match min/max operational
20167 semantics. Note that this is IEEE safe, as long as we don't
20168 interchange the operands.
20170 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20171 and TRUE if the operation is successful and instructions are emitted. */
20173 static bool
20176 {
20179 rtx tmp;
20182 ;
20184 {
20188 }
20189 else
20196 else
20201 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20202 but MODE may be a vector mode and thus not appropriate. */
20204 {
20206 rtvec v;
20211 }
20212 else
20213 {
20216 }
20220 }
20222 /* Expand an sse vector comparison. Return the register with the result. */
20224 static rtx
20227 {
20230 rtx x;
20243 {
20246 }
20247 else
20251 }
20253 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20254 operations. This is used for both scalar and vector conditional moves. */
20256 static void
20258 {
20264 {
20266 }
20268 {
20272 }
20274 {
20279 }
20281 {
20285 }
20287 {
20295 op_true,
20296 op_false)));
20297 }
20298 else
20299 {
20308 {
20322 {
20328 }
20343 {
20349 }
20353 }
20357 else
20358 {
20364 else
20376 }
20377 }
20378 }
20380 /* Expand a floating-point conditional move. Return true if successful. */
20382 bool
20384 {
20392 {
20395 /* Since we've no cmove for sse registers, don't force bad register
20396 allocation just to gain access to it. Deny movcc when the
20397 comparison mode doesn't match the move mode. */
20416 }
20423 /* The floating point conditional move instructions don't directly
20424 support conditions resulting from a signed integer comparison. */
20428 {
20433 }
20440 }
20442 /* Expand a floating-point vector conditional move; a vcond operation
20443 rather than a movcc operation. */
20445 bool
20447 {
20449 rtx cmp;
20454 {
20455 rtx temp;
20457 {
20474 }
20476 OPTAB_DIRECT);
20479 }
20489 }
20491 /* Expand a signed/unsigned integral vector conditional move. */
20493 bool
20495 {
20505 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20506 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20515 {
20519 {
20525 }
20528 {
20534 }
20535 }
20544 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20548 ;
20549 else
20550 {
20551 /* Canonicalize the comparison to EQ, GT, GTU. */
20553 {
20570 /* FALLTHRU */
20580 }
20582 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20584 {
20586 {
20588 /* SSE4.1 supports EQ. */
20595 /* SSE4.2 supports GT/GTU. */
20602 }
20603 }
20605 /* Unsigned parallel compare is not supported by the hardware.
20606 Play some tricks to turn this into a signed comparison
20607 against 0. */
20609 {
20613 {
20618 {
20623 {
20630 }
20631 /* Subtract (-(INT MAX) - 1) from both operands to make
20632 them signed. */
20643 }
20650 /* Perform a parallel unsigned saturating subtraction. */
20663 }
20664 }
20665 }
20667 /* Allow the comparison to be done in one mode, but the movcc to
20668 happen in another mode. */
20670 {
20673 }
20674 else
20675 {
20681 }
20686 }
20688 /* Expand a variable vector permutation. */
20690 void
20692 {
20703 /* Number of elements in the vector. */
20709 {
20711 {
20712 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20713 an constant shuffle operand. With a tiny bit of effort we can
20714 use VPERMD instead. A re-interpretation stall for V4DFmode is
20715 unfortunate but there's no avoiding it.
20716 Similarly for V16HImode we don't have instructions for variable
20717 shuffling, while for V32QImode we can use after preparing suitable
20718 masks vpshufb; vpshufb; vpermq; vpor. */
20721 {
20725 }
20726 else
20727 {
20731 }
20734 /* Replicate the low bits of the V4DImode mask into V8SImode:
20735 mask = { A B C D }
20736 t1 = { A A B B C C D D }. */
20744 else
20747 /* Multiply the shuffle indicies by two. */
20749 OPTAB_DIRECT);
20751 /* Add one to the odd shuffle indicies:
20752 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20754 {
20757 }
20761 OPTAB_DIRECT);
20763 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20768 }
20771 {
20773 /* The VPERMD and VPERMPS instructions already properly ignore
20774 the high bits of the shuffle elements. No need for us to
20775 perform an AND ourselves. */
20778 else
20779 {
20785 }
20792 else
20793 {
20799 }
20803 /* By combining the two 128-bit input vectors into one 256-bit
20804 input vector, we can use VPERMD and VPERMPS for the full
20805 two-operand shuffle. */
20837 /* From mask create two adjusted masks, which contain the same
20838 bits as mask in the low 7 bits of each vector element.
20839 The first mask will have the most significant bit clear
20840 if it requests element from the same 128-bit lane
20841 and MSB set if it requests element from the other 128-bit lane.
20842 The second mask will have the opposite values of the MSB,
20843 and additionally will have its 128-bit lanes swapped.
20844 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20845 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20846 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20847 stands for other 12 bytes. */
20848 /* The bit whether element is from the same lane or the other
20849 lane is bit 4, so shift it up by 3 to the MSB position. */
20853 /* Clear MSB bits from the mask just in case it had them set. */
20855 /* After this t1 will have MSB set for elements from other lane. */
20857 /* Clear bits other than MSB. */
20859 /* Or in the lower bits from mask into t3. */
20861 /* And invert MSB bits in t1, so MSB is set for elements from the same
20862 lane. */
20864 /* Swap 128-bit lanes in t3. */
20869 /* And or in the lower bits from mask into t1. */
20872 {
20873 /* Each of these shuffles will put 0s in places where
20874 element from the other 128-bit lane is needed, otherwise
20875 will shuffle in the requested value. */
20878 /* For t3 the 128-bit lanes are swapped again. */
20883 /* And oring both together leads to the result. */
20886 }
20889 /* Similarly to the above one_operand_shuffle code,
20890 just for repeated twice for each operand. merge_two:
20891 code will merge the two results together. */
20913 }
20914 }
20917 {
20918 /* The XOP VPPERM insn supports three inputs. By ignoring the
20919 one_operand_shuffle special case, we avoid creating another
20920 set of constant vectors in memory. */
20923 /* mask = mask & {2*w-1, ...} */
20925 }
20926 else
20927 {
20928 /* mask = mask & {w-1, ...} */
20930 }
20938 /* For non-QImode operations, convert the word permutation control
20939 into a byte permutation control. */
20941 {
20946 /* Convert mask to vector of chars. */
20949 /* Replicate each of the input bytes into byte positions:
20950 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20951 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20952 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20959 else
20962 /* Convert it into the byte positions by doing
20963 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20969 }
20971 /* The actual shuffle operations all operate on V16QImode. */
20977 {
20979 }
20981 {
20983 }
20984 else
20985 {
20989 /* Shuffle the two input vectors independently. */
20995 merge_two:
20996 /* Then merge them together. The key is whether any given control
20997 element contained a bit set that indicates the second word. */
21001 {
21002 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21003 more shuffle to convert the V2DI input mask into a V4SI
21004 input mask. At which point the masking that expand_int_vcond
21005 will work as desired. */
21013 }
21030 }
21031 }
21033 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21034 true if we should do zero extension, else sign extension. HIGH_P is
21035 true if we want the N/2 high elements, else the low elements. */
21037 void
21039 {
21041 rtx tmp;
21044 {
21050 {
21054 else
21057 extract
21063 else
21066 extract
21072 else
21075 extract
21081 else
21087 else
21093 else
21098 }
21101 {
21104 }
21106 {
21107 /* Shift higher 8 bytes to lower 8 bytes. */
21112 }
21113 else
21117 }
21118 else
21119 {
21123 {
21127 else
21133 else
21139 else
21144 }
21148 else
21153 }
21154 }
21156 /* Expand conditional increment or decrement using adb/sbb instructions.
21157 The default case using setcc followed by the conditional move can be
21158 done by generic code. */
21159 bool
21161 {
21163 rtx flags;
21165 rtx compare_op;
21183 {
21186 }
21189 {
21193 reverse_condition_maybe_unordered
21195 else
21197 }
21201 /* Construct either adc or sbb insn. */
21203 {
21205 {
21220 }
21221 }
21222 else
21223 {
21225 {
21240 }
21241 }
21245 }
21248 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21249 but works for floating pointer parameters and nonoffsetable memories.
21250 For pushes, it returns just stack offsets; the values will be saved
21251 in the right order. Maximally three parts are generated. */
21253 static int
21255 {
21260 else
21266 /* Optimize constant pool reference to immediates. This is used by fp
21267 moves, that force all constants to memory to allow combining. */
21269 {
21273 }
21276 {
21277 /* The only non-offsetable memories we handle are pushes. */
21286 }
21289 {
21291 /* Caution: if we looked through a constant pool memory above,
21292 the operand may actually have a different mode now. That's
21293 ok, since we want to pun this all the way back to an integer. */
21297 }
21300 {
21303 else
21304 {
21308 {
21312 }
21314 {
21319 }
21321 {
21322 REAL_VALUE_TYPE r;
21327 {
21334 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21335 long double may not be 80-bit. */
21344 }
21347 }
21348 else
21350 }
21351 }
21352 else
21353 {
21357 {
21360 {
21364 }
21366 {
21370 }
21372 {
21373 REAL_VALUE_TYPE r;
21379 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21382 = gen_int_mode
21385 DImode);
21386 else
21393 = gen_int_mode
21396 DImode);
21397 else
21399 }
21400 else
21402 }
21403 }
21406 }
21408 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21409 Return false when normal moves are needed; true when all required
21410 insns have been emitted. Operands 2-4 contain the input values
21411 int the correct order; operands 5-7 contain the output values. */
21413 void
21415 {
21423 /* The DFmode expanders may ask us to move double.
21424 For 64bit target this is single move. By hiding the fact
21425 here we simplify i386.md splitters. */
21427 {
21428 /* Optimize constant pool reference to immediates. This is used by
21429 fp moves, that force all constants to memory to allow combining. */
21436 {
21439 }
21440 else
21445 }
21447 /* The only non-offsettable memory we handle is push. */
21450 else
21457 /* When emitting push, take care for source operands on the stack. */
21460 {
21463 /* Compensate for the stack decrement by 4. */
21468 /* src_base refers to the stack pointer and is
21469 automatically decreased by emitted push. */
21473 }
21475 /* We need to do copy in the right order in case an address register
21476 of the source overlaps the destination. */
21478 {
21479 rtx tmp;
21482 {
21486 collisions++;
21487 }
21489 /* Collision in the middle part can be handled by reordering. */
21491 {
21494 }
21498 {
21500 {
21503 }
21504 else
21505 {
21508 }
21509 }
21511 /* If there are more collisions, we can't handle it by reordering.
21512 Do an lea to the last part and use only one colliding move. */
21514 {
21515 rtx base;
21521 /* Handle the case when the last part isn't valid for lea.
21522 Happens in 64-bit mode storing the 12-byte XFmode. */
21529 {
21532 }
21533 }
21534 }
21537 {
21539 {
21541 {
21546 }
21548 {
21551 }
21552 }
21553 else
21554 {
21555 /* In 64bit mode we don't have 32bit push available. In case this is
21556 register, it is OK - we will just use larger counterpart. We also
21557 retype memory - these comes from attempt to avoid REX prefix on
21558 moving of second half of TFmode value. */
21560 {
21562 {
21573 }
21577 }
21578 }
21582 }
21584 /* Choose correct order to not overwrite the source before it is copied. */
21594 {
21596 {
21599 }
21600 }
21601 else
21602 {
21604 {
21607 }
21608 }
21610 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21612 {
21621 }
21627 }
21629 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21630 left shift by a constant, either using a single shift or
21631 a sequence of add instructions. */
21633 static void
21635 {
21641 {
21645 }
21646 else
21647 {
21650 }
21651 }
21653 void
21655 {
21664 {
21669 {
21675 }
21676 else
21677 {
21685 }
21687 }
21694 {
21695 /* Assuming we've chosen a QImode capable registers, then 1 << N
21696 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21698 {
21714 }
21716 /* Otherwise, we can get the same results by manually performing
21717 a bit extract operation on bit 5/6, and then performing the two
21718 shifts. The two methods of getting 0/1 into low/high are exactly
21719 the same size. Avoiding the shift in the bit extract case helps
21720 pentium4 a bit; no one else seems to care much either way. */
21721 else
21722 {
21727 HOST_WIDE_INT bits;
21728 rtx x;
21731 {
21737 }
21738 else
21739 {
21745 }
21749 else
21757 }
21762 }
21765 {
21766 /* For -1 << N, we can avoid the shld instruction, because we
21767 know that we're shifting 0...31/63 ones into a -1. */
21771 else
21773 }
21774 else
21775 {
21783 }
21788 {
21794 }
21795 else
21796 {
21801 }
21802 }
21804 void
21806 {
21816 {
21821 {
21827 }
21829 {
21838 }
21839 else
21840 {
21848 }
21849 }
21850 else
21851 {
21863 {
21871 scratch));
21872 }
21873 else
21874 {
21879 }
21880 }
21881 }
21883 void
21885 {
21895 {
21900 {
21907 }
21908 else
21909 {
21917 }
21918 }
21919 else
21920 {
21932 {
21938 scratch));
21939 }
21940 else
21941 {
21946 }
21947 }
21948 }
21950 /* Predict just emitted jump instruction to be taken with probability PROB. */
21951 static void
21953 {
21957 }
21959 /* Helper function for the string operations below. Dest VARIABLE whether
21960 it is aligned to VALUE bytes. If true, jump to the label. */
21961 static rtx
21963 {
21968 else
21974 else
21977 }
21979 /* Adjust COUNTER by the VALUE. */
21980 static void
21982 {
21987 }
21989 /* Zero extend possibly SImode EXP to Pmode register. */
21990 rtx
21992 {
21994 }
21996 /* Divide COUNTREG by SCALE. */
21997 static rtx
21999 {
22000 rtx sc;
22012 }
22014 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22015 DImode for constant loop counts. */
22017 static enum machine_mode
22019 {
22027 }
22029 /* When SRCPTR is non-NULL, output simple loop to move memory
22030 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
22031 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
22032 equivalent loop to set memory by VALUE (supposed to be in MODE).
22034 The size is rounded down to whole number of chunk size moved at once.
22035 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22038 static void
22043 {
22049 rtx size;
22058 /* Those two should combine. */
22060 {
22064 }
22071 /* This assert could be relaxed - in this case we'll need to compute
22072 smallest power of two, containing in PIECE_SIZE_N and pass it to
22073 offset_address. */
22079 {
22083 /* When unrolling for chips that reorder memory reads and writes,
22084 we can save registers by using single temporary.
22085 Also using 4 temporaries is overkill in 32bit mode. */
22087 {
22089 {
22091 {
22092 destmem =
22094 srcmem =
22096 }
22098 }
22099 }
22100 else
22101 {
22105 {
22108 {
22109 srcmem =
22111 }
22113 }
22115 {
22117 {
22118 destmem =
22120 }
22122 }
22123 }
22124 }
22125 else
22127 {
22129 destmem =
22132 }
22142 {
22148 else
22150 }
22151 else
22159 {
22164 }
22166 }
22168 /* Output "rep; mov" instruction.
22169 Arguments have same meaning as for previous function */
22170 static void
22173 rtx count,
22175 {
22176 rtx destexp;
22177 rtx srcexp;
22178 rtx countreg;
22179 HOST_WIDE_INT rounded_count;
22181 /* If the size is known, it is shorter to use rep movs. */
22192 {
22199 }
22200 else
22201 {
22204 }
22206 {
22213 }
22214 else
22215 {
22220 }
22223 }
22225 /* Output "rep; stos" instruction.
22226 Arguments have same meaning as for previous function */
22227 static void
22230 rtx orig_value)
22231 {
22232 rtx destexp;
22233 rtx countreg;
22234 HOST_WIDE_INT rounded_count;
22241 {
22245 }
22246 else
22249 {
22254 }
22258 }
22260 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
22261 DESTMEM.
22262 SRC is passed by pointer to be updated on return.
22263 Return value is updated DST. */
22264 static rtx
22266 HOST_WIDE_INT size_to_move)
22267 {
22273 /* Find the widest mode in which we could perform moves.
22274 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
22275 it until move of such size is supported. */
22280 {
22284 }
22286 /* Find the corresponding vector mode with the same size as MOVE_MODE.
22287 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
22289 {
22294 {
22298 }
22299 }
22305 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
22309 {
22310 /* We move from memory to memory, so we'll need to do it via
22311 a temporary register. */
22322 piece_size);
22324 piece_size);
22325 }
22327 /* Update DST and SRC rtx. */
22330 }
22332 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
22333 static void
22336 {
22339 {
22344 /* For now MAX_SIZE should be a power of 2. This assert could be
22345 relaxed, but it'll require a bit more complicated epilogue
22346 expanding. */
22349 {
22352 }
22354 }
22356 {
22362 }
22364 /* When there are stringops, we can cheaply increase dest and src pointers.
22365 Otherwise we save code size by maintaining offset (zero is readily
22366 available from preceding rep operation) and using x86 addressing modes.
22367 */
22369 {
22371 {
22378 }
22380 {
22387 }
22389 {
22396 }
22397 }
22398 else
22399 {
22401 rtx tmp;
22404 {
22415 }
22417 {
22430 }
22432 {
22441 }
22442 }
22443 }
22445 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22446 static void
22449 {
22450 count =
22456 }
22458 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22459 static void
22461 {
22462 rtx dest;
22465 {
22470 {
22472 {
22477 }
22478 else
22481 }
22483 {
22485 {
22488 }
22489 else
22490 {
22495 }
22497 }
22499 {
22503 }
22505 {
22509 }
22511 {
22515 }
22517 }
22519 {
22522 }
22524 {
22527 {
22531 }
22532 else
22533 {
22539 }
22542 }
22544 {
22547 {
22550 }
22551 else
22552 {
22556 }
22559 }
22561 {
22567 }
22569 {
22575 }
22577 {
22583 }
22584 }
22586 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22587 DESIRED_ALIGNMENT.
22588 Return value is updated DESTMEM. */
22589 static rtx
22593 {
22596 {
22598 {
22605 }
22606 }
22608 }
22610 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22611 ALIGN_BYTES is how many bytes need to be copied.
22612 The function updates DST and SRC, namely, it sets proper alignment.
22613 DST is returned via return value, SRC is updated via pointer SRCP. */
22614 static rtx
22617 {
22630 {
22632 {
22635 }
22636 }
22641 {
22644 {
22648 }
22653 }
22660 }
22662 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22663 DESIRED_ALIGNMENT. */
22664 static void
22667 {
22669 {
22676 }
22678 {
22685 }
22687 {
22694 }
22696 }
22698 /* Set enough from DST to align DST known to by aligned by ALIGN to
22699 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22700 static rtx
22703 {
22707 {
22712 }
22714 {
22721 }
22723 {
22730 }
22737 }
22739 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22740 static enum stringop_alg
22743 {
22746 /* Algorithms using the rep prefix want at least edi and ecx;
22747 additionally, memset wants eax and memcpy wants esi. Don't
22748 consider such algorithms if the user has appropriated those
22749 registers for their own purposes. */
22751 || (memset
22755 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22756 || (alg != rep_prefix_1_byte \
22757 && alg != rep_prefix_4_byte \
22758 && alg != rep_prefix_8_byte))
22761 /* Even if the string operation call is cold, we still might spend a lot
22762 of time processing large blocks. */
22767 else
22775 else
22779 /* rep; movq or rep; movl is the smallest variant. */
22781 {
22784 else
22786 }
22787 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22788 */
22792 {
22796 {
22797 /* We get here if the algorithms that were not libcall-based
22798 were rep-prefix based and we are unable to use rep prefixes
22799 based on global register usage. Break out of the loop and
22800 use the heuristic below. */
22804 {
22809 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22810 last non-libcall inline algorithm. */
22812 {
22813 /* When the current size is best to be copied by a libcall,
22814 but we are still forced to inline, run the heuristic below
22815 that will pick code for medium sized blocks. */
22819 }
22821 {
22824 }
22825 }
22826 }
22828 }
22829 /* When asked to inline the call anyway, try to pick meaningful choice.
22830 We look for maximal size of block that is faster to copy by hand and
22831 take blocks of at most of that size guessing that average size will
22832 be roughly half of the block.
22834 If this turns out to be bad, we might simply specify the preferred
22835 choice in ix86_costs. */
22838 {
22845 {
22852 }
22853 /* If there aren't any usable algorithms, then recursing on
22854 smaller sizes isn't going to find anything. Just return the
22855 simple byte-at-a-time copy loop. */
22857 {
22858 /* Pick something reasonable. */
22862 }
22871 }
22873 #undef ALG_USABLE_P
22874 }
22876 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22877 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22878 static int
22883 {
22894 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22895 copying whole cacheline at once. */
22908 }
22910 /* Expand string move (memcpy) operation. Use i386 string operations
22911 when profitable. expand_setmem contains similar code. The code
22912 depends upon architecture, block size and alignment, but always has
22913 the same overall structure:
22915 1) Prologue guard: Conditional that jumps up to epilogues for small
22916 blocks that can be handled by epilogue alone. This is faster
22917 but also needed for correctness, since prologue assume the block
22918 is larger than the desired alignment.
22920 Optional dynamic check for size and libcall for large
22921 blocks is emitted here too, with -minline-stringops-dynamically.
22923 2) Prologue: copy first few bytes in order to get destination
22924 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22925 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22926 copied. We emit either a jump tree on power of two sized
22927 blocks, or a byte loop.
22929 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22930 with specified algorithm.
22932 4) Epilogue: code copying tail of the block that is too small to be
22933 handled by main body (or up to size guarded by prologue guard). */
22935 bool
22938 {
22939 rtx destreg;
22940 rtx srcreg;
22942 rtx tmp;
22958 /* i386 can do misaligned access on reasonably increased cost. */
22962 /* ALIGN is the minimum of destination and source alignment, but we care here
22963 just about destination alignment. */
22972 /* Make sure we don't need to care about overflow later on. */
22976 /* Step 0: Decide on preferred algorithm, desired alignment and
22977 size of chunks to be copied by main loop. */
22991 {
23010 /* Find the widest supported mode. */
23016 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23017 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23019 {
23024 }
23036 }
23044 /* Step 1: Prologue guard. */
23046 /* Alignment code needs count to be in register. */
23048 {
23051 {
23052 align_bytes
23056 else
23058 }
23061 }
23064 /* Ensure that alignment prologue won't copy past end of block. */
23066 {
23068 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
23069 Make sure it is power of 2. */
23073 {
23075 {
23076 /* If main algorithm works on QImode, no epilogue is needed.
23077 For small sizes just don't align anything. */
23080 else
23082 }
23083 }
23084 else
23085 {
23092 else
23094 }
23095 }
23097 /* Emit code to decide on runtime whether library call or inline should be
23098 used. */
23100 {
23102 {
23104 {
23108 }
23109 }
23110 else
23111 {
23120 }
23121 }
23123 /* Step 2: Alignment prologue. */
23126 {
23128 {
23129 /* Except for the first move in epilogue, we no longer know
23130 constant offset in aliasing info. It don't seems to worth
23131 the pain to maintain it for the first move, so throw away
23132 the info early. */
23136 desired_align);
23137 }
23138 else
23139 {
23140 /* If we know how many bytes need to be stored before dst is
23141 sufficiently aligned, maintain aliasing info accurately. */
23147 }
23153 {
23154 /* It is possible that we copied enough so the main loop will not
23155 execute. */
23165 else
23167 }
23168 }
23170 {
23175 }
23179 /* Step 3: Main loop. */
23182 {
23193 expected_size);
23199 move_mode);
23201 }
23202 /* Adjust properly the offset of src and dest memory for aliasing. */
23204 {
23209 }
23210 else
23211 {
23214 }
23216 /* Step 4: Epilogue to copy the remaining bytes. */
23217 epilogue:
23219 {
23220 /* When the main loop is done, COUNT_EXP might hold original count,
23221 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23222 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23223 bytes. Compensate if needed. */
23226 {
23227 tmp =
23230 OPTAB_DIRECT);
23233 }
23236 }
23240 size_needed);
23244 }
23246 /* Helper function for memcpy. For QImode value 0xXY produce
23247 0xXYXYXYXY of wide specified by MODE. This is essentially
23248 a * 0x10101010, but we can do slightly better than
23249 synth_mult by unwinding the sequence by hand on CPUs with
23250 slow multiply. */
23251 static rtx
23253 {
23255 rtx tmp;
23262 {
23270 }
23279 nops--;
23284 {
23288 OPTAB_DIRECT);
23289 }
23290 else
23291 {
23297 else
23299 else
23300 {
23303 reg =
23305 }
23315 }
23316 }
23318 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23319 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23320 alignment from ALIGN to DESIRED_ALIGN. */
23321 static rtx
23323 {
23324 rtx promoted_val;
23333 else
23337 }
23339 /* Expand string clear operation (bzero). Use i386 string operations when
23340 profitable. See expand_movmem comment for explanation of individual
23341 steps performed. */
23342 bool
23345 {
23346 rtx destreg;
23348 rtx tmp;
23366 /* i386 can do misaligned access on reasonably increased cost. */
23375 /* Make sure we don't need to care about overflow later on. */
23379 /* Step 0: Decide on preferred algorithm, desired alignment and
23380 size of chunks to be copied by main loop. */
23394 {
23420 }
23428 /* Step 1: Prologue guard. */
23430 /* Alignment code needs count to be in register. */
23432 {
23435 {
23436 align_bytes
23440 else
23442 }
23444 {
23449 }
23450 }
23451 /* Do the cheap promotion to allow better CSE across the
23452 main loop and epilogue (ie one load of the big constant in the
23453 front of all code. */
23457 /* Ensure that alignment prologue won't copy past end of block. */
23459 {
23461 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23462 Make sure it is power of 2. */
23465 /* To improve performance of small blocks, we jump around the VAL
23466 promoting mode. This mean that if the promoted VAL is not constant,
23467 we might not use it in the epilogue and have to use byte
23468 loop variant. */
23472 {
23474 {
23475 /* If main algorithm works on QImode, no epilogue is needed.
23476 For small sizes just don't align anything. */
23479 else
23481 }
23482 }
23483 else
23484 {
23491 else
23493 }
23494 }
23496 {
23505 }
23507 /* Step 2: Alignment prologue. */
23509 /* Do the expensive promotion once we branched off the small blocks. */
23516 {
23518 {
23519 /* Except for the first move in epilogue, we no longer know
23520 constant offset in aliasing info. It don't seems to worth
23521 the pain to maintain it for the first move, so throw away
23522 the info early. */
23525 desired_align);
23526 }
23527 else
23528 {
23529 /* If we know how many bytes need to be stored before dst is
23530 sufficiently aligned, maintain aliasing info accurately. */
23536 }
23542 {
23543 /* It is possible that we copied enough so the main loop will not
23544 execute. */
23554 else
23556 }
23557 }
23559 {
23565 }
23569 /* Step 3: Main loop. */
23572 {
23583 expected_size);
23597 }
23598 /* Adjust properly the offset of src and dest memory for aliasing. */
23602 else
23605 /* Step 4: Epilogue to copy the remaining bytes. */
23608 {
23609 /* When the main loop is done, COUNT_EXP might hold original count,
23610 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23611 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23612 bytes. Compensate if needed. */
23615 {
23616 tmp =
23619 OPTAB_DIRECT);
23622 }
23625 }
23626 epilogue:
23628 {
23631 epilogue_size_needed);
23632 else
23634 epilogue_size_needed);
23635 }
23639 }
23641 /* Expand the appropriate insns for doing strlen if not just doing
23642 repnz; scasb
23644 out = result, initialized with the start address
23645 align_rtx = alignment of the address.
23646 scratch = scratch register, initialized with the startaddress when
23647 not aligned, otherwise undefined
23649 This is just the body. It needs the initializations mentioned above and
23650 some address computing at the end. These things are done in i386.md. */
23652 static void
23654 {
23656 rtx tmp;
23661 rtx mem;
23664 rtx cmp;
23670 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23672 /* Is there a known alignment and is it less than 4? */
23674 {
23677 /* Is there a known alignment and is it not 2? */
23679 {
23683 /* Leave just the 3 lower bits. */
23693 }
23694 else
23695 {
23696 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23697 check if is aligned to 4 - byte. */
23704 }
23708 /* Now compare the bytes. */
23710 /* Compare the first n unaligned byte on a byte per byte basis. */
23714 /* Increment the address. */
23717 /* Not needed with an alignment of 2 */
23719 {
23723 end_0_label);
23728 }
23731 end_0_label);
23734 }
23736 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23737 align this loop. It gives only huge programs, but does not help to
23738 speed up. */
23745 /* This formula yields a nonzero result iff one of the bytes is zero.
23746 This saves three branches inside loop and many cycles. */
23754 align_4_label);
23757 {
23763 /* If zero is not in the first two bytes, move two bytes forward. */
23769 reg,
23770 tmpreg)));
23771 /* Emit lea manually to avoid clobbering of flags. */
23779 reg2,
23780 out)));
23781 }
23782 else
23783 {
23785 /* Is zero in the first two bytes? */
23792 pc_rtx);
23796 /* Not in the first two. Move two bytes forward. */
23802 }
23804 /* Avoid branch in fixing the byte. */
23812 }
23814 /* Expand strlen. */
23816 bool
23818 {
23821 /* The generic case of strlen expander is long. Avoid it's
23822 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23825 && !TARGET_INLINE_ALL_STRINGOPS
23835 {
23836 /* Well it seems that some optimizer does not combine a call like
23837 foo(strlen(bar), strlen(bar));
23838 when the move and the subtraction is done here. It does calculate
23839 the length just once when these instructions are done inside of
23840 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23841 often used and I use one fewer register for the lifetime of
23842 output_strlen_unroll() this is better. */
23848 /* strlensi_unroll_1 returns the address of the zero at the end of
23849 the string, like memchr(), so compute the length by subtracting
23850 the start address. */
23852 }
23853 else
23854 {
23855 rtx unspec;
23857 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23870 /* If .md starts supporting :P, this can be done in .md. */
23876 }
23878 }
23880 /* For given symbol (function) construct code to compute address of it's PLT
23881 entry in large x86-64 PIC model. */
23882 static rtx
23884 {
23897 }
23899 rtx
23901 rtx callarg2,
23903 {
23904 unsigned int const cregs_size
23915 {
23916 #if TARGET_MACHO
23919 #endif
23920 }
23921 else
23922 {
23923 /* Static functions and indirect calls don't need the pic register. */
23925 && (!TARGET_64BIT
23931 }
23934 {
23938 }
23941 && !TARGET_PECOFF
23949 {
23952 }
23960 {
23964 }
23968 {
23972 UNSPEC_MS_TO_SYSV_CALL);
23975 {
23981 }
23982 }
23991 }
23993 /* Output the assembly for a call instruction. */
23997 {
24003 {
24006 /* SEH epilogue detection requires the indirect branch case
24007 to include REX.W. */
24010 else
24015 }
24017 /* SEH unwinding can require an extra nop to be emitted in several
24018 circumstances. Determine if we have one of those. */
24020 {
24021 rtx i;
24024 {
24025 /* If we get to another real insn, we don't need the nop. */
24029 /* If we get to the epilogue note, prevent a catch region from
24030 being adjacent to the standard epilogue sequence. If non-
24031 call-exceptions, we'll have done this during epilogue emission. */
24033 && !flag_non_call_exceptions
24035 {
24038 }
24039 }
24041 /* If we didn't find a real insn following the call, prevent the
24042 unwinder from looking into the next function. */
24045 }
24049 else
24058 }
24059 \f
24060 /* Clear stack slot assignments remembered from previous functions.
24061 This is called from INIT_EXPANDERS once before RTL is emitted for each
24062 function. */
24066 {
24074 }
24076 /* Return a MEM corresponding to a stack slot with mode MODE.
24077 Allocate a new slot if necessary.
24079 The RTL for a function can have several slots available: N is
24080 which slot to use. */
24082 rtx
24084 {
24101 }
24103 static void
24105 {
24111 }
24112 \f
24113 /* Calculate the length of the memory address in the instruction encoding.
24114 Includes addr32 prefix, does not include the one-byte modrm, opcode,
24115 or other prefixes. We never generate addr32 prefix for LEA insn. */
24117 int
24119 {
24136 /* If this is not LEA instruction, add the length of addr32 prefix. */
24141 len++;
24155 /* Rule of thumb:
24156 - esp as the base always wants an index,
24157 - ebp as the base always wants a displacement,
24158 - r12 as the base always wants an index,
24159 - r13 as the base always wants a displacement. */
24161 /* Register Indirect. */
24163 {
24164 /* esp (for its index) and ebp (for its displacement) need
24165 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
24166 code. */
24173 len++;
24174 }
24176 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
24177 is not disp32, but disp32(%rip), so for disp32
24178 SIB byte is needed, unless print_operand_address
24179 optimizes it into disp32(%rip) or (%rip) is implied
24180 by UNSPEC. */
24182 {
24185 {
24201 len++;
24202 }
24203 }
24204 else
24205 {
24206 /* Find the length of the displacement constant. */
24208 {
24211 else
24213 }
24214 /* ebp always wants a displacement. Similarly r13. */
24216 len++;
24218 /* An index requires the two-byte modrm form.... */
24220 /* ...like esp (or r12), which always wants an index. */
24224 len++;
24225 }
24228 }
24230 /* Compute default value for "length_immediate" attribute. When SHORTFORM
24231 is set, expect that insn have 8bit immediate alternative. */
24232 int
24234 {
24240 {
24245 {
24248 {
24260 }
24262 {
24265 }
24266 }
24268 {
24278 /* Immediates for DImode instructions are encoded
24279 as 32bit sign extended values. */
24285 }
24286 }
24288 }
24290 /* Compute default value for "length_address" attribute. */
24291 int
24293 {
24297 {
24308 }
24313 {
24316 {
24321 constraints++;
24324 ;
24325 /* Skip ignored operands. */
24328 }
24330 }
24332 }
24334 /* Compute default value for "length_vex" attribute. It includes
24335 2 or 3 byte VEX prefix and 1 opcode byte. */
24337 int
24339 {
24342 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24343 byte VEX prefix. */
24347 /* We can always use 2 byte VEX prefix in 32bit. */
24355 {
24356 /* REX.W bit uses 3 byte VEX prefix. */
24360 }
24361 else
24362 {
24363 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24367 }
24370 }
24371 \f
24372 /* Return the maximum number of instructions a cpu can issue. */
24374 static int
24376 {
24378 {
24405 }
24406 }
24408 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24409 by DEP_INSN and nothing set by DEP_INSN. */
24411 static bool
24413 {
24416 /* Simplify the test for uninteresting insns. */
24424 {
24427 }
24432 {
24435 }
24436 else
24442 /* This test is true if the dependent insn reads the flags but
24443 not any other potentially set register. */
24451 }
24453 /* Return true iff USE_INSN has a memory address with operands set by
24454 SET_INSN. */
24456 bool
24458 {
24463 {
24466 }
24468 }
24470 /* Helper function for exact_store_load_dependency.
24471 Return true if addr is found in insn. */
24472 static bool
24474 {
24481 {
24487 CASE_CONST_ANY:
24496 }
24500 {
24502 {
24512 }
24513 }
24515 }
24517 /* Return true if there exists exact dependency for store & load, i.e.
24518 the same memory address is used in them. */
24519 static bool
24521 {
24535 }
24537 static int
24539 {
24545 /* Anti and output dependencies have zero cost on all CPUs. */
24551 /* If we can't recognize the insns, we can't really do anything. */
24559 {
24561 /* Address Generation Interlock adds a cycle of latency. */
24563 {
24574 }
24578 /* ??? Compares pair with jump/setcc. */
24582 /* Floating point stores require value to be ready one cycle earlier. */
24592 /* INT->FP conversion is expensive. */
24596 /* There is one cycle extra latency between an FP op and a store. */
24604 /* Show ability of reorder buffer to hide latency of load by executing
24605 in parallel with previous instruction in case
24606 previous instruction is not needed to compute the address. */
24609 {
24610 /* Claim moves to take one cycle, as core can issue one load
24611 at time and the next load can start cycle later. */
24616 cost--;
24617 }
24623 /* The esp dependency is resolved before the instruction is really
24624 finished. */
24629 /* INT->FP conversion is expensive. */
24633 /* Show ability of reorder buffer to hide latency of load by executing
24634 in parallel with previous instruction in case
24635 previous instruction is not needed to compute the address. */
24638 {
24639 /* Claim moves to take one cycle, as core can issue one load
24640 at time and the next load can start cycle later. */
24646 else
24648 }
24664 /* Show ability of reorder buffer to hide latency of load by executing
24665 in parallel with previous instruction in case
24666 previous instruction is not needed to compute the address. */
24669 {
24673 /* Because of the difference between the length of integer and
24674 floating unit pipeline preparation stages, the memory operands
24675 for floating point are cheaper.
24677 ??? For Athlon it the difference is most probably 2. */
24680 else
24685 else
24687 }
24694 /* Increase cost of integer loads. */
24697 {
24700 {
24703 else
24704 {
24705 /* Increase cost of ld/st for short int types only
24706 because of store forwarding issue. */
24710 {
24711 /* Increase cost of store/load insn if exact
24712 dependence exists and it is load insn. */
24717 }
24718 }
24719 }
24720 }
24724 }
24727 }
24729 /* How many alternative schedules to try. This should be as wide as the
24730 scheduling freedom in the DFA, but no wider. Making this value too
24731 large results extra work for the scheduler. */
24733 static int
24735 {
24737 {
24750 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24751 as many instructions can be executed on a cycle, i.e.,
24752 issue_rate. I wonder why tuning for many CPUs does not do this. */
24755 /* Don't use lookahead for pre-reload schedule to save compile time. */
24760 }
24761 }
24763 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24764 execution. It is applied if
24765 (1) IMUL instruction is on the top of list;
24766 (2) There exists the only producer of independent IMUL instruction in
24767 ready list.
24768 Return index of IMUL producer if it was found and -1 otherwise. */
24769 static int
24771 {
24773 sd_iterator_def sd_it;
24774 dep_t dep;
24781 /* Check that IMUL instruction is on the top of ready list. */
24790 /* Search for producer of independent IMUL instruction. */
24792 {
24796 /* Skip IMUL instruction. */
24806 {
24807 rtx con;
24818 {
24819 sd_iterator_def sd_it1;
24820 dep_t dep1;
24821 /* Check if there is no other dependee for IMUL. */
24824 {
24825 rtx pro;
24831 }
24834 }
24835 }
24838 }
24840 }
24842 /* Try to find the best candidate on the top of ready list if two insns
24843 have the same priority - candidate is best if its dependees were
24844 scheduled earlier. Applied for Silvermont only.
24845 Return true if top 2 insns must be interchanged. */
24846 static bool
24848 {
24851 rtx set;
24852 sd_iterator_def sd_it;
24853 dep_t dep;
24856 #define INSN_TICK(INSN) (HID (INSN)->tick)
24877 {
24880 /* Determine winner more precise. */
24882 {
24883 rtx pro;
24889 }
24891 {
24892 rtx pro;
24898 }
24901 {
24902 /* Determine winner - load must win. */
24908 }
24910 }
24912 #undef INSN_TICK
24913 }
24915 /* Perform possible reodering of ready list for Atom/Silvermont only.
24916 Return issue rate. */
24917 static int
24920 {
24924 rtx insn;
24927 /* Set up issue rate. */
24930 /* Do reodering for Atom/SLM only. */
24934 /* Nothing to do if ready list contains only 1 instruction. */
24938 /* Do reodering for post-reload scheduler only. */
24943 {
24948 /* Put IMUL producer (ready[index]) at the top of ready list. */
24954 }
24956 {
24960 /* Swap 2 top elements of ready list. */
24964 }
24966 }
24968 static bool
24971 /* Returns true if lhs of insn is HW function argument register and set up
24972 is_spilled to true if it is likely spilled HW register. */
24973 static bool
24975 {
24976 rtx dst;
24980 /* Call instructions are not movable, ignore it. */
24991 {
24992 /* Is it likely spilled HW register? */
24997 }
24999 }
25001 /* Add output dependencies for chain of function adjacent arguments if only
25002 there is a move to likely spilled HW register. Return first argument
25003 if at least one dependence was added or NULL otherwise. */
25004 static rtx
25006 {
25007 rtx insn;
25014 /* Find nearest to call argument passing instruction. */
25016 {
25025 }
25029 {
25036 {
25039 }
25041 {
25042 /* Add output depdendence between two function arguments if chain
25043 of output arguments contains likely spilled HW registers. */
25047 }
25048 else
25050 }
25054 }
25056 /* Add output or anti dependency from insn to first_arg to restrict its code
25057 motion. */
25058 static void
25060 {
25061 rtx set;
25062 rtx tmp;
25069 {
25070 /* Add output dependency to the first function argument. */
25073 }
25074 /* Add anti dependency. */
25076 }
25078 /* Avoid cross block motion of function argument through adding dependency
25079 from the first non-jump instruction in bb. */
25080 static void
25082 {
25086 {
25088 {
25091 {
25094 }
25095 }
25099 }
25100 }
25102 /* Hook for pre-reload schedule - avoid motion of function arguments
25103 passed in likely spilled HW registers. */
25104 static void
25106 {
25107 rtx insn;
25115 {
25118 {
25119 /* Add dependee for first argument to predecessors if only
25120 region contains more than one block. */
25124 /* Skip trivial regions and region head blocks that can have
25125 predecessors outside of region. */
25127 {
25128 edge e;
25129 edge_iterator ei;
25130 /* Assume that region is SCC, i.e. all immediate predecessors
25131 of non-head block are in the same region. */
25133 {
25134 /* Avoid creating of loop-carried dependencies through
25135 using topological odering in region. */
25138 }
25139 }
25143 }
25144 }
25147 }
25149 /* Hook for pre-reload schedule - set priority of moves from likely spilled
25150 HW registers to maximum, to schedule them at soon as possible. These are
25151 moves from function argument registers at the top of the function entry
25152 and moves from function return value registers after call. */
25153 static int
25155 {
25156 rtx set;
25166 {
25173 }
25176 }
25178 /* Model decoder of Core 2/i7.
25179 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
25180 track the instruction fetch block boundaries and make sure that long
25181 (9+ bytes) instructions are assigned to D0. */
25183 /* Maximum length of an insn that can be handled by
25184 a secondary decoder unit. '8' for Core 2/i7. */
25187 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
25188 '16' for Core 2/i7. */
25191 /* Maximum number of instructions decoder can handle per cycle.
25192 '6' for Core 2/i7. */
25196 ix86_first_cycle_multipass_data_t;
25198 const_ix86_first_cycle_multipass_data_t;
25200 /* A variable to store target state across calls to max_issue within
25201 one cycle. */
25205 /* Initialize DATA. */
25206 static void
25208 {
25209 ix86_first_cycle_multipass_data_t data
25216 }
25218 /* Advancing the cycle; reset ifetch block counts. */
25219 static void
25221 {
25228 }
25232 /* Filter out insns from ready_try that the core will not be able to issue
25233 on current cycle due to decoder. */
25234 static void
25235 core2i7_first_cycle_multipass_filter_ready_try
25238 {
25240 {
25241 rtx insn;
25251 (!first_cycle_insn_p
25253 /* ... or it would not fit into the ifetch block ... */
25255 /* ... or the decoder is full already ... */
25257 /* ... mask the insn out. */
25258 {
25263 }
25264 }
25265 }
25267 /* Prepare for a new round of multipass lookahead scheduling. */
25268 static void
25271 {
25272 ix86_first_cycle_multipass_data_t data
25274 const_ix86_first_cycle_multipass_data_t prev_data
25277 /* Restore the state from the end of the previous round. */
25281 /* Filter instructions that cannot be issued on current cycle due to
25282 decoder restrictions. */
25284 first_cycle_insn_p);
25285 }
25287 /* INSN is being issued in current solution. Account for its impact on
25288 the decoder model. */
25289 static void
25292 {
25293 ix86_first_cycle_multipass_data_t data
25295 const_ix86_first_cycle_multipass_data_t prev_data
25305 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
25307 {
25310 }
25312 {
25316 }
25319 /* Filter out insns from ready_try that the core will not be able to issue
25320 on current cycle due to decoder. */
25323 }
25325 /* Revert the effect on ready_try. */
25326 static void
25330 {
25331 const_ix86_first_cycle_multipass_data_t data
25334 sbitmap_iterator sbi;
25338 {
25340 }
25341 }
25343 /* Save the result of multipass lookahead scheduling for the next round. */
25344 static void
25346 {
25347 const_ix86_first_cycle_multipass_data_t data
25349 ix86_first_cycle_multipass_data_t next_data
25353 {
25356 }
25357 }
25359 /* Deallocate target data. */
25360 static void
25362 {
25363 ix86_first_cycle_multipass_data_t data
25367 {
25371 }
25372 }
25374 /* Prepare for scheduling pass. */
25375 static void
25379 {
25380 /* Install scheduling hooks for current CPU. Some of these hooks are used
25381 in time-critical parts of the scheduler, so we only set them up when
25382 they are actually used. */
25384 {
25388 /* Do not perform multipass scheduling for pre-reload schedule
25389 to save compile time. */
25391 {
25407 /* Set decoder parameters. */
25412 }
25413 /* ... Fall through ... */
25423 }
25424 }
25426 \f
25427 /* Compute the alignment given to a constant that is being placed in memory.
25428 EXP is the constant and ALIGN is the alignment that the object would
25429 ordinarily have.
25430 The value of this function is used instead of that alignment to align
25431 the object. */
25433 int
25435 {
25438 {
25443 }
25449 }
25451 /* Compute the alignment for a static variable.
25452 TYPE is the data type, and ALIGN is the alignment that
25453 the object would ordinarily have. The value of this function is used
25454 instead of that alignment to align the object. */
25456 int
25458 {
25470 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25471 to 16byte boundary. */
25473 {
25480 }
25486 {
25491 }
25493 {
25500 }
25505 {
25510 }
25513 {
25518 }
25521 }
25523 /* Compute the alignment for a local variable or a stack slot. EXP is
25524 the data type or decl itself, MODE is the widest mode available and
25525 ALIGN is the alignment that the object would ordinarily have. The
25526 value of this macro is used instead of that alignment to align the
25527 object. */
25529 unsigned int
25532 {
25536 {
25539 }
25540 else
25541 {
25544 }
25546 /* Don't do dynamic stack realignment for long long objects with
25547 -mpreferred-stack-boundary=2. */
25556 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25557 register in MODE. We will return the largest alignment of XF
25558 and DF. */
25560 {
25564 }
25566 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25567 to 16byte boundary. Exact wording is:
25569 An array uses the same alignment as its elements, except that a local or
25570 global array variable of length at least 16 bytes or
25571 a C99 variable-length array variable always has alignment of at least 16 bytes.
25573 This was added to allow use of aligned SSE instructions at arrays. This
25574 rule is meant for static storage (where compiler can not do the analysis
25575 by itself). We follow it for automatic variables only when convenient.
25576 We fully control everything in the function compiled and functions from
25577 other unit can not rely on the alignment.
25579 Exclude va_list type. It is the common case of local array where
25580 we can not benefit from the alignment.
25582 TODO: Probably one should optimize for size only when var is not escaping. */
25585 {
25595 }
25597 {
25602 }
25604 {
25610 }
25615 {
25620 }
25623 {
25629 }
25631 }
25633 /* Compute the minimum required alignment for dynamic stack realignment
25634 purposes for a local variable, parameter or a stack slot. EXP is
25635 the data type or decl itself, MODE is its mode and ALIGN is the
25636 alignment that the object would ordinarily have. */
25638 unsigned int
25641 {
25645 {
25648 }
25649 else
25650 {
25653 }
25658 /* Don't do dynamic stack realignment for long long objects with
25659 -mpreferred-stack-boundary=2. */
25666 }
25667 \f
25668 /* Find a location for the static chain incoming to a nested function.
25669 This is a register, unless all free registers are used by arguments. */
25671 static rtx
25673 {
25680 {
25681 /* We always use R10 in 64-bit mode. */
25683 }
25684 else
25685 {
25686 tree fntype;
25689 /* By default in 32-bit mode we use ECX to pass the static chain. */
25695 {
25696 /* Fastcall functions use ecx/edx for arguments, which leaves
25697 us with EAX for the static chain.
25698 Thiscall functions use ecx for arguments, which also
25699 leaves us with EAX for the static chain. */
25701 }
25703 {
25704 /* Thiscall functions use ecx for arguments, which leaves
25705 us with EAX and EDX for the static chain.
25706 We are using for abi-compatibility EAX. */
25708 }
25710 {
25711 /* For regparm 3, we have no free call-clobbered registers in
25712 which to store the static chain. In order to implement this,
25713 we have the trampoline push the static chain to the stack.
25714 However, we can't push a value below the return address when
25715 we call the nested function directly, so we have to use an
25716 alternate entry point. For this we use ESI, and have the
25717 alternate entry point push ESI, so that things appear the
25718 same once we're executing the nested function. */
25720 {
25726 }
25728 }
25729 }
25732 }
25734 /* Emit RTL insns to initialize the variable parts of a trampoline.
25735 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25736 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25737 to be passed to the target function. */
25739 static void
25741 {
25749 {
25752 /* Load the function address to r11. Try to load address using
25753 the shorter movl instead of movabs. We may want to support
25754 movq for kernel mode, but kernel does not use trampolines at
25755 the moment. FNADDR is a 32bit address and may not be in
25756 DImode when ptr_mode == SImode. Always use movl in this
25757 case. */
25760 {
25769 }
25770 else
25771 {
25778 }
25780 /* Load static chain using movabs to r10. Use the shorter movl
25781 instead of movabs when ptr_mode == SImode. */
25783 {
25786 }
25787 else
25788 {
25791 }
25800 /* Jump to r11; the last (unused) byte is a nop, only there to
25801 pad the write out to a single 32-bit store. */
25805 }
25806 else
25807 {
25810 /* Depending on the static chain location, either load a register
25811 with a constant, or push the constant to the stack. All of the
25812 instructions are the same size. */
25815 {
25817 {
25824 }
25825 }
25826 else
25841 /* Compute offset from the end of the jmp to the target function.
25842 In the case in which the trampoline stores the static chain on
25843 the stack, we need to skip the first insn which pushes the
25844 (call-saved) register static chain; this push is 1 byte. */
25851 }
25855 #ifdef HAVE_ENABLE_EXECUTE_STACK
25856 #ifdef CHECK_EXECUTE_STACK_ENABLED
25858 #endif
25861 #endif
25862 }
25863 \f
25864 /* The following file contains several enumerations and data structures
25865 built from the definitions in i386-builtin-types.def. */
25869 /* Table for the ix86 builtin non-function types. */
25872 /* Retrieve an element from the above table, building some of
25873 the types lazily. */
25875 static tree
25877 {
25889 {
25897 }
25898 else
25899 {
25905 else
25913 }
25917 }
25919 /* Table for the ix86 builtin function types. */
25922 /* Retrieve an element from the above table, building some of
25923 the types lazily. */
25925 static tree
25927 {
25928 tree type;
25937 {
25945 {
25948 }
25951 }
25952 else
25953 {
25959 }
25963 }
25966 /* Codes for all the SSE/MMX builtins. */
25967 enum ix86_builtins
25968 {
25969 IX86_BUILTIN_ADDPS,
25970 IX86_BUILTIN_ADDSS,
25971 IX86_BUILTIN_DIVPS,
25972 IX86_BUILTIN_DIVSS,
25973 IX86_BUILTIN_MULPS,
25974 IX86_BUILTIN_MULSS,
25975 IX86_BUILTIN_SUBPS,
25976 IX86_BUILTIN_SUBSS,
25978 IX86_BUILTIN_CMPEQPS,
25979 IX86_BUILTIN_CMPLTPS,
25980 IX86_BUILTIN_CMPLEPS,
25981 IX86_BUILTIN_CMPGTPS,
25982 IX86_BUILTIN_CMPGEPS,
25983 IX86_BUILTIN_CMPNEQPS,
25984 IX86_BUILTIN_CMPNLTPS,
25985 IX86_BUILTIN_CMPNLEPS,
25986 IX86_BUILTIN_CMPNGTPS,
25987 IX86_BUILTIN_CMPNGEPS,
25988 IX86_BUILTIN_CMPORDPS,
25989 IX86_BUILTIN_CMPUNORDPS,
25990 IX86_BUILTIN_CMPEQSS,
25991 IX86_BUILTIN_CMPLTSS,
25992 IX86_BUILTIN_CMPLESS,
25993 IX86_BUILTIN_CMPNEQSS,
25994 IX86_BUILTIN_CMPNLTSS,
25995 IX86_BUILTIN_CMPNLESS,
25996 IX86_BUILTIN_CMPORDSS,
25997 IX86_BUILTIN_CMPUNORDSS,
25999 IX86_BUILTIN_COMIEQSS,
26000 IX86_BUILTIN_COMILTSS,
26001 IX86_BUILTIN_COMILESS,
26002 IX86_BUILTIN_COMIGTSS,
26003 IX86_BUILTIN_COMIGESS,
26004 IX86_BUILTIN_COMINEQSS,
26005 IX86_BUILTIN_UCOMIEQSS,
26006 IX86_BUILTIN_UCOMILTSS,
26007 IX86_BUILTIN_UCOMILESS,
26008 IX86_BUILTIN_UCOMIGTSS,
26009 IX86_BUILTIN_UCOMIGESS,
26010 IX86_BUILTIN_UCOMINEQSS,
26012 IX86_BUILTIN_CVTPI2PS,
26013 IX86_BUILTIN_CVTPS2PI,
26014 IX86_BUILTIN_CVTSI2SS,
26015 IX86_BUILTIN_CVTSI642SS,
26016 IX86_BUILTIN_CVTSS2SI,
26017 IX86_BUILTIN_CVTSS2SI64,
26018 IX86_BUILTIN_CVTTPS2PI,
26019 IX86_BUILTIN_CVTTSS2SI,
26020 IX86_BUILTIN_CVTTSS2SI64,
26022 IX86_BUILTIN_MAXPS,
26023 IX86_BUILTIN_MAXSS,
26024 IX86_BUILTIN_MINPS,
26025 IX86_BUILTIN_MINSS,
26027 IX86_BUILTIN_LOADUPS,
26028 IX86_BUILTIN_STOREUPS,
26029 IX86_BUILTIN_MOVSS,
26031 IX86_BUILTIN_MOVHLPS,
26032 IX86_BUILTIN_MOVLHPS,
26033 IX86_BUILTIN_LOADHPS,
26034 IX86_BUILTIN_LOADLPS,
26035 IX86_BUILTIN_STOREHPS,
26036 IX86_BUILTIN_STORELPS,
26038 IX86_BUILTIN_MASKMOVQ,
26039 IX86_BUILTIN_MOVMSKPS,
26040 IX86_BUILTIN_PMOVMSKB,
26042 IX86_BUILTIN_MOVNTPS,
26043 IX86_BUILTIN_MOVNTQ,
26045 IX86_BUILTIN_LOADDQU,
26046 IX86_BUILTIN_STOREDQU,
26048 IX86_BUILTIN_PACKSSWB,
26049 IX86_BUILTIN_PACKSSDW,
26050 IX86_BUILTIN_PACKUSWB,
26052 IX86_BUILTIN_PADDB,
26053 IX86_BUILTIN_PADDW,
26054 IX86_BUILTIN_PADDD,
26055 IX86_BUILTIN_PADDQ,
26056 IX86_BUILTIN_PADDSB,
26057 IX86_BUILTIN_PADDSW,
26058 IX86_BUILTIN_PADDUSB,
26059 IX86_BUILTIN_PADDUSW,
26060 IX86_BUILTIN_PSUBB,
26061 IX86_BUILTIN_PSUBW,
26062 IX86_BUILTIN_PSUBD,
26063 IX86_BUILTIN_PSUBQ,
26064 IX86_BUILTIN_PSUBSB,
26065 IX86_BUILTIN_PSUBSW,
26066 IX86_BUILTIN_PSUBUSB,
26067 IX86_BUILTIN_PSUBUSW,
26069 IX86_BUILTIN_PAND,
26070 IX86_BUILTIN_PANDN,
26071 IX86_BUILTIN_POR,
26072 IX86_BUILTIN_PXOR,
26074 IX86_BUILTIN_PAVGB,
26075 IX86_BUILTIN_PAVGW,
26077 IX86_BUILTIN_PCMPEQB,
26078 IX86_BUILTIN_PCMPEQW,
26079 IX86_BUILTIN_PCMPEQD,
26080 IX86_BUILTIN_PCMPGTB,
26081 IX86_BUILTIN_PCMPGTW,
26082 IX86_BUILTIN_PCMPGTD,
26084 IX86_BUILTIN_PMADDWD,
26086 IX86_BUILTIN_PMAXSW,
26087 IX86_BUILTIN_PMAXUB,
26088 IX86_BUILTIN_PMINSW,
26089 IX86_BUILTIN_PMINUB,
26091 IX86_BUILTIN_PMULHUW,
26092 IX86_BUILTIN_PMULHW,
26093 IX86_BUILTIN_PMULLW,
26095 IX86_BUILTIN_PSADBW,
26096 IX86_BUILTIN_PSHUFW,
26098 IX86_BUILTIN_PSLLW,
26099 IX86_BUILTIN_PSLLD,
26100 IX86_BUILTIN_PSLLQ,
26101 IX86_BUILTIN_PSRAW,
26102 IX86_BUILTIN_PSRAD,
26103 IX86_BUILTIN_PSRLW,
26104 IX86_BUILTIN_PSRLD,
26105 IX86_BUILTIN_PSRLQ,
26106 IX86_BUILTIN_PSLLWI,
26107 IX86_BUILTIN_PSLLDI,
26108 IX86_BUILTIN_PSLLQI,
26109 IX86_BUILTIN_PSRAWI,
26110 IX86_BUILTIN_PSRADI,
26111 IX86_BUILTIN_PSRLWI,
26112 IX86_BUILTIN_PSRLDI,
26113 IX86_BUILTIN_PSRLQI,
26115 IX86_BUILTIN_PUNPCKHBW,
26116 IX86_BUILTIN_PUNPCKHWD,
26117 IX86_BUILTIN_PUNPCKHDQ,
26118 IX86_BUILTIN_PUNPCKLBW,
26119 IX86_BUILTIN_PUNPCKLWD,
26120 IX86_BUILTIN_PUNPCKLDQ,
26122 IX86_BUILTIN_SHUFPS,
26124 IX86_BUILTIN_RCPPS,
26125 IX86_BUILTIN_RCPSS,
26126 IX86_BUILTIN_RSQRTPS,
26127 IX86_BUILTIN_RSQRTPS_NR,
26128 IX86_BUILTIN_RSQRTSS,
26129 IX86_BUILTIN_RSQRTF,
26130 IX86_BUILTIN_SQRTPS,
26131 IX86_BUILTIN_SQRTPS_NR,
26132 IX86_BUILTIN_SQRTSS,
26134 IX86_BUILTIN_UNPCKHPS,
26135 IX86_BUILTIN_UNPCKLPS,
26137 IX86_BUILTIN_ANDPS,
26138 IX86_BUILTIN_ANDNPS,
26139 IX86_BUILTIN_ORPS,
26140 IX86_BUILTIN_XORPS,
26142 IX86_BUILTIN_EMMS,
26143 IX86_BUILTIN_LDMXCSR,
26144 IX86_BUILTIN_STMXCSR,
26145 IX86_BUILTIN_SFENCE,
26147 IX86_BUILTIN_FXSAVE,
26148 IX86_BUILTIN_FXRSTOR,
26149 IX86_BUILTIN_FXSAVE64,
26150 IX86_BUILTIN_FXRSTOR64,
26152 IX86_BUILTIN_XSAVE,
26153 IX86_BUILTIN_XRSTOR,
26154 IX86_BUILTIN_XSAVE64,
26155 IX86_BUILTIN_XRSTOR64,
26157 IX86_BUILTIN_XSAVEOPT,
26158 IX86_BUILTIN_XSAVEOPT64,
26160 /* 3DNow! Original */
26161 IX86_BUILTIN_FEMMS,
26162 IX86_BUILTIN_PAVGUSB,
26163 IX86_BUILTIN_PF2ID,
26164 IX86_BUILTIN_PFACC,
26165 IX86_BUILTIN_PFADD,
26166 IX86_BUILTIN_PFCMPEQ,
26167 IX86_BUILTIN_PFCMPGE,
26168 IX86_BUILTIN_PFCMPGT,
26169 IX86_BUILTIN_PFMAX,
26170 IX86_BUILTIN_PFMIN,
26171 IX86_BUILTIN_PFMUL,
26172 IX86_BUILTIN_PFRCP,
26173 IX86_BUILTIN_PFRCPIT1,
26174 IX86_BUILTIN_PFRCPIT2,
26175 IX86_BUILTIN_PFRSQIT1,
26176 IX86_BUILTIN_PFRSQRT,
26177 IX86_BUILTIN_PFSUB,
26178 IX86_BUILTIN_PFSUBR,
26179 IX86_BUILTIN_PI2FD,
26180 IX86_BUILTIN_PMULHRW,
26182 /* 3DNow! Athlon Extensions */
26183 IX86_BUILTIN_PF2IW,
26184 IX86_BUILTIN_PFNACC,
26185 IX86_BUILTIN_PFPNACC,
26186 IX86_BUILTIN_PI2FW,
26187 IX86_BUILTIN_PSWAPDSI,
26188 IX86_BUILTIN_PSWAPDSF,
26190 /* SSE2 */
26191 IX86_BUILTIN_ADDPD,
26192 IX86_BUILTIN_ADDSD,
26193 IX86_BUILTIN_DIVPD,
26194 IX86_BUILTIN_DIVSD,
26195 IX86_BUILTIN_MULPD,
26196 IX86_BUILTIN_MULSD,
26197 IX86_BUILTIN_SUBPD,
26198 IX86_BUILTIN_SUBSD,
26200 IX86_BUILTIN_CMPEQPD,
26201 IX86_BUILTIN_CMPLTPD,
26202 IX86_BUILTIN_CMPLEPD,
26203 IX86_BUILTIN_CMPGTPD,
26204 IX86_BUILTIN_CMPGEPD,
26205 IX86_BUILTIN_CMPNEQPD,
26206 IX86_BUILTIN_CMPNLTPD,
26207 IX86_BUILTIN_CMPNLEPD,
26208 IX86_BUILTIN_CMPNGTPD,
26209 IX86_BUILTIN_CMPNGEPD,
26210 IX86_BUILTIN_CMPORDPD,
26211 IX86_BUILTIN_CMPUNORDPD,
26212 IX86_BUILTIN_CMPEQSD,
26213 IX86_BUILTIN_CMPLTSD,
26214 IX86_BUILTIN_CMPLESD,
26215 IX86_BUILTIN_CMPNEQSD,
26216 IX86_BUILTIN_CMPNLTSD,
26217 IX86_BUILTIN_CMPNLESD,
26218 IX86_BUILTIN_CMPORDSD,
26219 IX86_BUILTIN_CMPUNORDSD,
26221 IX86_BUILTIN_COMIEQSD,
26222 IX86_BUILTIN_COMILTSD,
26223 IX86_BUILTIN_COMILESD,
26224 IX86_BUILTIN_COMIGTSD,
26225 IX86_BUILTIN_COMIGESD,
26226 IX86_BUILTIN_COMINEQSD,
26227 IX86_BUILTIN_UCOMIEQSD,
26228 IX86_BUILTIN_UCOMILTSD,
26229 IX86_BUILTIN_UCOMILESD,
26230 IX86_BUILTIN_UCOMIGTSD,
26231 IX86_BUILTIN_UCOMIGESD,
26232 IX86_BUILTIN_UCOMINEQSD,
26234 IX86_BUILTIN_MAXPD,
26235 IX86_BUILTIN_MAXSD,
26236 IX86_BUILTIN_MINPD,
26237 IX86_BUILTIN_MINSD,
26239 IX86_BUILTIN_ANDPD,
26240 IX86_BUILTIN_ANDNPD,
26241 IX86_BUILTIN_ORPD,
26242 IX86_BUILTIN_XORPD,
26244 IX86_BUILTIN_SQRTPD,
26245 IX86_BUILTIN_SQRTSD,
26247 IX86_BUILTIN_UNPCKHPD,
26248 IX86_BUILTIN_UNPCKLPD,
26250 IX86_BUILTIN_SHUFPD,
26252 IX86_BUILTIN_LOADUPD,
26253 IX86_BUILTIN_STOREUPD,
26254 IX86_BUILTIN_MOVSD,
26256 IX86_BUILTIN_LOADHPD,
26257 IX86_BUILTIN_LOADLPD,
26259 IX86_BUILTIN_CVTDQ2PD,
26260 IX86_BUILTIN_CVTDQ2PS,
26262 IX86_BUILTIN_CVTPD2DQ,
26263 IX86_BUILTIN_CVTPD2PI,
26264 IX86_BUILTIN_CVTPD2PS,
26265 IX86_BUILTIN_CVTTPD2DQ,
26266 IX86_BUILTIN_CVTTPD2PI,
26268 IX86_BUILTIN_CVTPI2PD,
26269 IX86_BUILTIN_CVTSI2SD,
26270 IX86_BUILTIN_CVTSI642SD,
26272 IX86_BUILTIN_CVTSD2SI,
26273 IX86_BUILTIN_CVTSD2SI64,
26274 IX86_BUILTIN_CVTSD2SS,
26275 IX86_BUILTIN_CVTSS2SD,
26276 IX86_BUILTIN_CVTTSD2SI,
26277 IX86_BUILTIN_CVTTSD2SI64,
26279 IX86_BUILTIN_CVTPS2DQ,
26280 IX86_BUILTIN_CVTPS2PD,
26281 IX86_BUILTIN_CVTTPS2DQ,
26283 IX86_BUILTIN_MOVNTI,
26284 IX86_BUILTIN_MOVNTI64,
26285 IX86_BUILTIN_MOVNTPD,
26286 IX86_BUILTIN_MOVNTDQ,
26288 IX86_BUILTIN_MOVQ128,
26290 /* SSE2 MMX */
26291 IX86_BUILTIN_MASKMOVDQU,
26292 IX86_BUILTIN_MOVMSKPD,
26293 IX86_BUILTIN_PMOVMSKB128,
26295 IX86_BUILTIN_PACKSSWB128,
26296 IX86_BUILTIN_PACKSSDW128,
26297 IX86_BUILTIN_PACKUSWB128,
26299 IX86_BUILTIN_PADDB128,
26300 IX86_BUILTIN_PADDW128,
26301 IX86_BUILTIN_PADDD128,
26302 IX86_BUILTIN_PADDQ128,
26303 IX86_BUILTIN_PADDSB128,
26304 IX86_BUILTIN_PADDSW128,
26305 IX86_BUILTIN_PADDUSB128,
26306 IX86_BUILTIN_PADDUSW128,
26307 IX86_BUILTIN_PSUBB128,
26308 IX86_BUILTIN_PSUBW128,
26309 IX86_BUILTIN_PSUBD128,
26310 IX86_BUILTIN_PSUBQ128,
26311 IX86_BUILTIN_PSUBSB128,
26312 IX86_BUILTIN_PSUBSW128,
26313 IX86_BUILTIN_PSUBUSB128,
26314 IX86_BUILTIN_PSUBUSW128,
26316 IX86_BUILTIN_PAND128,
26317 IX86_BUILTIN_PANDN128,
26318 IX86_BUILTIN_POR128,
26319 IX86_BUILTIN_PXOR128,
26321 IX86_BUILTIN_PAVGB128,
26322 IX86_BUILTIN_PAVGW128,
26324 IX86_BUILTIN_PCMPEQB128,
26325 IX86_BUILTIN_PCMPEQW128,
26326 IX86_BUILTIN_PCMPEQD128,
26327 IX86_BUILTIN_PCMPGTB128,
26328 IX86_BUILTIN_PCMPGTW128,
26329 IX86_BUILTIN_PCMPGTD128,
26331 IX86_BUILTIN_PMADDWD128,
26333 IX86_BUILTIN_PMAXSW128,
26334 IX86_BUILTIN_PMAXUB128,
26335 IX86_BUILTIN_PMINSW128,
26336 IX86_BUILTIN_PMINUB128,
26338 IX86_BUILTIN_PMULUDQ,
26339 IX86_BUILTIN_PMULUDQ128,
26340 IX86_BUILTIN_PMULHUW128,
26341 IX86_BUILTIN_PMULHW128,
26342 IX86_BUILTIN_PMULLW128,
26344 IX86_BUILTIN_PSADBW128,
26345 IX86_BUILTIN_PSHUFHW,
26346 IX86_BUILTIN_PSHUFLW,
26347 IX86_BUILTIN_PSHUFD,
26349 IX86_BUILTIN_PSLLDQI128,
26350 IX86_BUILTIN_PSLLWI128,
26351 IX86_BUILTIN_PSLLDI128,
26352 IX86_BUILTIN_PSLLQI128,
26353 IX86_BUILTIN_PSRAWI128,
26354 IX86_BUILTIN_PSRADI128,
26355 IX86_BUILTIN_PSRLDQI128,
26356 IX86_BUILTIN_PSRLWI128,
26357 IX86_BUILTIN_PSRLDI128,
26358 IX86_BUILTIN_PSRLQI128,
26360 IX86_BUILTIN_PSLLDQ128,
26361 IX86_BUILTIN_PSLLW128,
26362 IX86_BUILTIN_PSLLD128,
26363 IX86_BUILTIN_PSLLQ128,
26364 IX86_BUILTIN_PSRAW128,
26365 IX86_BUILTIN_PSRAD128,
26366 IX86_BUILTIN_PSRLW128,
26367 IX86_BUILTIN_PSRLD128,
26368 IX86_BUILTIN_PSRLQ128,
26370 IX86_BUILTIN_PUNPCKHBW128,
26371 IX86_BUILTIN_PUNPCKHWD128,
26372 IX86_BUILTIN_PUNPCKHDQ128,
26373 IX86_BUILTIN_PUNPCKHQDQ128,
26374 IX86_BUILTIN_PUNPCKLBW128,
26375 IX86_BUILTIN_PUNPCKLWD128,
26376 IX86_BUILTIN_PUNPCKLDQ128,
26377 IX86_BUILTIN_PUNPCKLQDQ128,
26379 IX86_BUILTIN_CLFLUSH,
26380 IX86_BUILTIN_MFENCE,
26381 IX86_BUILTIN_LFENCE,
26382 IX86_BUILTIN_PAUSE,
26384 IX86_BUILTIN_BSRSI,
26385 IX86_BUILTIN_BSRDI,
26386 IX86_BUILTIN_RDPMC,
26387 IX86_BUILTIN_RDTSC,
26388 IX86_BUILTIN_RDTSCP,
26389 IX86_BUILTIN_ROLQI,
26390 IX86_BUILTIN_ROLHI,
26391 IX86_BUILTIN_RORQI,
26392 IX86_BUILTIN_RORHI,
26394 /* SSE3. */
26395 IX86_BUILTIN_ADDSUBPS,
26396 IX86_BUILTIN_HADDPS,
26397 IX86_BUILTIN_HSUBPS,
26398 IX86_BUILTIN_MOVSHDUP,
26399 IX86_BUILTIN_MOVSLDUP,
26400 IX86_BUILTIN_ADDSUBPD,
26401 IX86_BUILTIN_HADDPD,
26402 IX86_BUILTIN_HSUBPD,
26403 IX86_BUILTIN_LDDQU,
26405 IX86_BUILTIN_MONITOR,
26406 IX86_BUILTIN_MWAIT,
26408 /* SSSE3. */
26409 IX86_BUILTIN_PHADDW,
26410 IX86_BUILTIN_PHADDD,
26411 IX86_BUILTIN_PHADDSW,
26412 IX86_BUILTIN_PHSUBW,
26413 IX86_BUILTIN_PHSUBD,
26414 IX86_BUILTIN_PHSUBSW,
26415 IX86_BUILTIN_PMADDUBSW,
26416 IX86_BUILTIN_PMULHRSW,
26417 IX86_BUILTIN_PSHUFB,
26418 IX86_BUILTIN_PSIGNB,
26419 IX86_BUILTIN_PSIGNW,
26420 IX86_BUILTIN_PSIGND,
26421 IX86_BUILTIN_PALIGNR,
26422 IX86_BUILTIN_PABSB,
26423 IX86_BUILTIN_PABSW,
26424 IX86_BUILTIN_PABSD,
26426 IX86_BUILTIN_PHADDW128,
26427 IX86_BUILTIN_PHADDD128,
26428 IX86_BUILTIN_PHADDSW128,
26429 IX86_BUILTIN_PHSUBW128,
26430 IX86_BUILTIN_PHSUBD128,
26431 IX86_BUILTIN_PHSUBSW128,
26432 IX86_BUILTIN_PMADDUBSW128,
26433 IX86_BUILTIN_PMULHRSW128,
26434 IX86_BUILTIN_PSHUFB128,
26435 IX86_BUILTIN_PSIGNB128,
26436 IX86_BUILTIN_PSIGNW128,
26437 IX86_BUILTIN_PSIGND128,
26438 IX86_BUILTIN_PALIGNR128,
26439 IX86_BUILTIN_PABSB128,
26440 IX86_BUILTIN_PABSW128,
26441 IX86_BUILTIN_PABSD128,
26443 /* AMDFAM10 - SSE4A New Instructions. */
26444 IX86_BUILTIN_MOVNTSD,
26445 IX86_BUILTIN_MOVNTSS,
26446 IX86_BUILTIN_EXTRQI,
26447 IX86_BUILTIN_EXTRQ,
26448 IX86_BUILTIN_INSERTQI,
26449 IX86_BUILTIN_INSERTQ,
26451 /* SSE4.1. */
26452 IX86_BUILTIN_BLENDPD,
26453 IX86_BUILTIN_BLENDPS,
26454 IX86_BUILTIN_BLENDVPD,
26455 IX86_BUILTIN_BLENDVPS,
26456 IX86_BUILTIN_PBLENDVB128,
26457 IX86_BUILTIN_PBLENDW128,
26459 IX86_BUILTIN_DPPD,
26460 IX86_BUILTIN_DPPS,
26462 IX86_BUILTIN_INSERTPS128,
26464 IX86_BUILTIN_MOVNTDQA,
26465 IX86_BUILTIN_MPSADBW128,
26466 IX86_BUILTIN_PACKUSDW128,
26467 IX86_BUILTIN_PCMPEQQ,
26468 IX86_BUILTIN_PHMINPOSUW128,
26470 IX86_BUILTIN_PMAXSB128,
26471 IX86_BUILTIN_PMAXSD128,
26472 IX86_BUILTIN_PMAXUD128,
26473 IX86_BUILTIN_PMAXUW128,
26475 IX86_BUILTIN_PMINSB128,
26476 IX86_BUILTIN_PMINSD128,
26477 IX86_BUILTIN_PMINUD128,
26478 IX86_BUILTIN_PMINUW128,
26480 IX86_BUILTIN_PMOVSXBW128,
26481 IX86_BUILTIN_PMOVSXBD128,
26482 IX86_BUILTIN_PMOVSXBQ128,
26483 IX86_BUILTIN_PMOVSXWD128,
26484 IX86_BUILTIN_PMOVSXWQ128,
26485 IX86_BUILTIN_PMOVSXDQ128,
26487 IX86_BUILTIN_PMOVZXBW128,
26488 IX86_BUILTIN_PMOVZXBD128,
26489 IX86_BUILTIN_PMOVZXBQ128,
26490 IX86_BUILTIN_PMOVZXWD128,
26491 IX86_BUILTIN_PMOVZXWQ128,
26492 IX86_BUILTIN_PMOVZXDQ128,
26494 IX86_BUILTIN_PMULDQ128,
26495 IX86_BUILTIN_PMULLD128,
26497 IX86_BUILTIN_ROUNDSD,
26498 IX86_BUILTIN_ROUNDSS,
26500 IX86_BUILTIN_ROUNDPD,
26501 IX86_BUILTIN_ROUNDPS,
26503 IX86_BUILTIN_FLOORPD,
26504 IX86_BUILTIN_CEILPD,
26505 IX86_BUILTIN_TRUNCPD,
26506 IX86_BUILTIN_RINTPD,
26507 IX86_BUILTIN_ROUNDPD_AZ,
26509 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26510 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26511 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26513 IX86_BUILTIN_FLOORPS,
26514 IX86_BUILTIN_CEILPS,
26515 IX86_BUILTIN_TRUNCPS,
26516 IX86_BUILTIN_RINTPS,
26517 IX86_BUILTIN_ROUNDPS_AZ,
26519 IX86_BUILTIN_FLOORPS_SFIX,
26520 IX86_BUILTIN_CEILPS_SFIX,
26521 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26523 IX86_BUILTIN_PTESTZ,
26524 IX86_BUILTIN_PTESTC,
26525 IX86_BUILTIN_PTESTNZC,
26527 IX86_BUILTIN_VEC_INIT_V2SI,
26528 IX86_BUILTIN_VEC_INIT_V4HI,
26529 IX86_BUILTIN_VEC_INIT_V8QI,
26530 IX86_BUILTIN_VEC_EXT_V2DF,
26531 IX86_BUILTIN_VEC_EXT_V2DI,
26532 IX86_BUILTIN_VEC_EXT_V4SF,
26533 IX86_BUILTIN_VEC_EXT_V4SI,
26534 IX86_BUILTIN_VEC_EXT_V8HI,
26535 IX86_BUILTIN_VEC_EXT_V2SI,
26536 IX86_BUILTIN_VEC_EXT_V4HI,
26537 IX86_BUILTIN_VEC_EXT_V16QI,
26538 IX86_BUILTIN_VEC_SET_V2DI,
26539 IX86_BUILTIN_VEC_SET_V4SF,
26540 IX86_BUILTIN_VEC_SET_V4SI,
26541 IX86_BUILTIN_VEC_SET_V8HI,
26542 IX86_BUILTIN_VEC_SET_V4HI,
26543 IX86_BUILTIN_VEC_SET_V16QI,
26545 IX86_BUILTIN_VEC_PACK_SFIX,
26546 IX86_BUILTIN_VEC_PACK_SFIX256,
26548 /* SSE4.2. */
26549 IX86_BUILTIN_CRC32QI,
26550 IX86_BUILTIN_CRC32HI,
26551 IX86_BUILTIN_CRC32SI,
26552 IX86_BUILTIN_CRC32DI,
26554 IX86_BUILTIN_PCMPESTRI128,
26555 IX86_BUILTIN_PCMPESTRM128,
26556 IX86_BUILTIN_PCMPESTRA128,
26557 IX86_BUILTIN_PCMPESTRC128,
26558 IX86_BUILTIN_PCMPESTRO128,
26559 IX86_BUILTIN_PCMPESTRS128,
26560 IX86_BUILTIN_PCMPESTRZ128,
26561 IX86_BUILTIN_PCMPISTRI128,
26562 IX86_BUILTIN_PCMPISTRM128,
26563 IX86_BUILTIN_PCMPISTRA128,
26564 IX86_BUILTIN_PCMPISTRC128,
26565 IX86_BUILTIN_PCMPISTRO128,
26566 IX86_BUILTIN_PCMPISTRS128,
26567 IX86_BUILTIN_PCMPISTRZ128,
26569 IX86_BUILTIN_PCMPGTQ,
26571 /* AES instructions */
26572 IX86_BUILTIN_AESENC128,
26573 IX86_BUILTIN_AESENCLAST128,
26574 IX86_BUILTIN_AESDEC128,
26575 IX86_BUILTIN_AESDECLAST128,
26576 IX86_BUILTIN_AESIMC128,
26577 IX86_BUILTIN_AESKEYGENASSIST128,
26579 /* PCLMUL instruction */
26580 IX86_BUILTIN_PCLMULQDQ128,
26582 /* AVX */
26583 IX86_BUILTIN_ADDPD256,
26584 IX86_BUILTIN_ADDPS256,
26585 IX86_BUILTIN_ADDSUBPD256,
26586 IX86_BUILTIN_ADDSUBPS256,
26587 IX86_BUILTIN_ANDPD256,
26588 IX86_BUILTIN_ANDPS256,
26589 IX86_BUILTIN_ANDNPD256,
26590 IX86_BUILTIN_ANDNPS256,
26591 IX86_BUILTIN_BLENDPD256,
26592 IX86_BUILTIN_BLENDPS256,
26593 IX86_BUILTIN_BLENDVPD256,
26594 IX86_BUILTIN_BLENDVPS256,
26595 IX86_BUILTIN_DIVPD256,
26596 IX86_BUILTIN_DIVPS256,
26597 IX86_BUILTIN_DPPS256,
26598 IX86_BUILTIN_HADDPD256,
26599 IX86_BUILTIN_HADDPS256,
26600 IX86_BUILTIN_HSUBPD256,
26601 IX86_BUILTIN_HSUBPS256,
26602 IX86_BUILTIN_MAXPD256,
26603 IX86_BUILTIN_MAXPS256,
26604 IX86_BUILTIN_MINPD256,
26605 IX86_BUILTIN_MINPS256,
26606 IX86_BUILTIN_MULPD256,
26607 IX86_BUILTIN_MULPS256,
26608 IX86_BUILTIN_ORPD256,
26609 IX86_BUILTIN_ORPS256,
26610 IX86_BUILTIN_SHUFPD256,
26611 IX86_BUILTIN_SHUFPS256,
26612 IX86_BUILTIN_SUBPD256,
26613 IX86_BUILTIN_SUBPS256,
26614 IX86_BUILTIN_XORPD256,
26615 IX86_BUILTIN_XORPS256,
26616 IX86_BUILTIN_CMPSD,
26617 IX86_BUILTIN_CMPSS,
26618 IX86_BUILTIN_CMPPD,
26619 IX86_BUILTIN_CMPPS,
26620 IX86_BUILTIN_CMPPD256,
26621 IX86_BUILTIN_CMPPS256,
26622 IX86_BUILTIN_CVTDQ2PD256,
26623 IX86_BUILTIN_CVTDQ2PS256,
26624 IX86_BUILTIN_CVTPD2PS256,
26625 IX86_BUILTIN_CVTPS2DQ256,
26626 IX86_BUILTIN_CVTPS2PD256,
26627 IX86_BUILTIN_CVTTPD2DQ256,
26628 IX86_BUILTIN_CVTPD2DQ256,
26629 IX86_BUILTIN_CVTTPS2DQ256,
26630 IX86_BUILTIN_EXTRACTF128PD256,
26631 IX86_BUILTIN_EXTRACTF128PS256,
26632 IX86_BUILTIN_EXTRACTF128SI256,
26633 IX86_BUILTIN_VZEROALL,
26634 IX86_BUILTIN_VZEROUPPER,
26635 IX86_BUILTIN_VPERMILVARPD,
26636 IX86_BUILTIN_VPERMILVARPS,
26637 IX86_BUILTIN_VPERMILVARPD256,
26638 IX86_BUILTIN_VPERMILVARPS256,
26639 IX86_BUILTIN_VPERMILPD,
26640 IX86_BUILTIN_VPERMILPS,
26641 IX86_BUILTIN_VPERMILPD256,
26642 IX86_BUILTIN_VPERMILPS256,
26643 IX86_BUILTIN_VPERMIL2PD,
26644 IX86_BUILTIN_VPERMIL2PS,
26645 IX86_BUILTIN_VPERMIL2PD256,
26646 IX86_BUILTIN_VPERMIL2PS256,
26647 IX86_BUILTIN_VPERM2F128PD256,
26648 IX86_BUILTIN_VPERM2F128PS256,
26649 IX86_BUILTIN_VPERM2F128SI256,
26650 IX86_BUILTIN_VBROADCASTSS,
26651 IX86_BUILTIN_VBROADCASTSD256,
26652 IX86_BUILTIN_VBROADCASTSS256,
26653 IX86_BUILTIN_VBROADCASTPD256,
26654 IX86_BUILTIN_VBROADCASTPS256,
26655 IX86_BUILTIN_VINSERTF128PD256,
26656 IX86_BUILTIN_VINSERTF128PS256,
26657 IX86_BUILTIN_VINSERTF128SI256,
26658 IX86_BUILTIN_LOADUPD256,
26659 IX86_BUILTIN_LOADUPS256,
26660 IX86_BUILTIN_STOREUPD256,
26661 IX86_BUILTIN_STOREUPS256,
26662 IX86_BUILTIN_LDDQU256,
26663 IX86_BUILTIN_MOVNTDQ256,
26664 IX86_BUILTIN_MOVNTPD256,
26665 IX86_BUILTIN_MOVNTPS256,
26666 IX86_BUILTIN_LOADDQU256,
26667 IX86_BUILTIN_STOREDQU256,
26668 IX86_BUILTIN_MASKLOADPD,
26669 IX86_BUILTIN_MASKLOADPS,
26670 IX86_BUILTIN_MASKSTOREPD,
26671 IX86_BUILTIN_MASKSTOREPS,
26672 IX86_BUILTIN_MASKLOADPD256,
26673 IX86_BUILTIN_MASKLOADPS256,
26674 IX86_BUILTIN_MASKSTOREPD256,
26675 IX86_BUILTIN_MASKSTOREPS256,
26676 IX86_BUILTIN_MOVSHDUP256,
26677 IX86_BUILTIN_MOVSLDUP256,
26678 IX86_BUILTIN_MOVDDUP256,
26680 IX86_BUILTIN_SQRTPD256,
26681 IX86_BUILTIN_SQRTPS256,
26682 IX86_BUILTIN_SQRTPS_NR256,
26683 IX86_BUILTIN_RSQRTPS256,
26684 IX86_BUILTIN_RSQRTPS_NR256,
26686 IX86_BUILTIN_RCPPS256,
26688 IX86_BUILTIN_ROUNDPD256,
26689 IX86_BUILTIN_ROUNDPS256,
26691 IX86_BUILTIN_FLOORPD256,
26692 IX86_BUILTIN_CEILPD256,
26693 IX86_BUILTIN_TRUNCPD256,
26694 IX86_BUILTIN_RINTPD256,
26695 IX86_BUILTIN_ROUNDPD_AZ256,
26697 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26698 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26699 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26701 IX86_BUILTIN_FLOORPS256,
26702 IX86_BUILTIN_CEILPS256,
26703 IX86_BUILTIN_TRUNCPS256,
26704 IX86_BUILTIN_RINTPS256,
26705 IX86_BUILTIN_ROUNDPS_AZ256,
26707 IX86_BUILTIN_FLOORPS_SFIX256,
26708 IX86_BUILTIN_CEILPS_SFIX256,
26709 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26711 IX86_BUILTIN_UNPCKHPD256,
26712 IX86_BUILTIN_UNPCKLPD256,
26713 IX86_BUILTIN_UNPCKHPS256,
26714 IX86_BUILTIN_UNPCKLPS256,
26716 IX86_BUILTIN_SI256_SI,
26717 IX86_BUILTIN_PS256_PS,
26718 IX86_BUILTIN_PD256_PD,
26719 IX86_BUILTIN_SI_SI256,
26720 IX86_BUILTIN_PS_PS256,
26721 IX86_BUILTIN_PD_PD256,
26723 IX86_BUILTIN_VTESTZPD,
26724 IX86_BUILTIN_VTESTCPD,
26725 IX86_BUILTIN_VTESTNZCPD,
26726 IX86_BUILTIN_VTESTZPS,
26727 IX86_BUILTIN_VTESTCPS,
26728 IX86_BUILTIN_VTESTNZCPS,
26729 IX86_BUILTIN_VTESTZPD256,
26730 IX86_BUILTIN_VTESTCPD256,
26731 IX86_BUILTIN_VTESTNZCPD256,
26732 IX86_BUILTIN_VTESTZPS256,
26733 IX86_BUILTIN_VTESTCPS256,
26734 IX86_BUILTIN_VTESTNZCPS256,
26735 IX86_BUILTIN_PTESTZ256,
26736 IX86_BUILTIN_PTESTC256,
26737 IX86_BUILTIN_PTESTNZC256,
26739 IX86_BUILTIN_MOVMSKPD256,
26740 IX86_BUILTIN_MOVMSKPS256,
26742 /* AVX2 */
26743 IX86_BUILTIN_MPSADBW256,
26744 IX86_BUILTIN_PABSB256,
26745 IX86_BUILTIN_PABSW256,
26746 IX86_BUILTIN_PABSD256,
26747 IX86_BUILTIN_PACKSSDW256,
26748 IX86_BUILTIN_PACKSSWB256,
26749 IX86_BUILTIN_PACKUSDW256,
26750 IX86_BUILTIN_PACKUSWB256,
26751 IX86_BUILTIN_PADDB256,
26752 IX86_BUILTIN_PADDW256,
26753 IX86_BUILTIN_PADDD256,
26754 IX86_BUILTIN_PADDQ256,
26755 IX86_BUILTIN_PADDSB256,
26756 IX86_BUILTIN_PADDSW256,
26757 IX86_BUILTIN_PADDUSB256,
26758 IX86_BUILTIN_PADDUSW256,
26759 IX86_BUILTIN_PALIGNR256,
26760 IX86_BUILTIN_AND256I,
26761 IX86_BUILTIN_ANDNOT256I,
26762 IX86_BUILTIN_PAVGB256,
26763 IX86_BUILTIN_PAVGW256,
26764 IX86_BUILTIN_PBLENDVB256,
26765 IX86_BUILTIN_PBLENDVW256,
26766 IX86_BUILTIN_PCMPEQB256,
26767 IX86_BUILTIN_PCMPEQW256,
26768 IX86_BUILTIN_PCMPEQD256,
26769 IX86_BUILTIN_PCMPEQQ256,
26770 IX86_BUILTIN_PCMPGTB256,
26771 IX86_BUILTIN_PCMPGTW256,
26772 IX86_BUILTIN_PCMPGTD256,
26773 IX86_BUILTIN_PCMPGTQ256,
26774 IX86_BUILTIN_PHADDW256,
26775 IX86_BUILTIN_PHADDD256,
26776 IX86_BUILTIN_PHADDSW256,
26777 IX86_BUILTIN_PHSUBW256,
26778 IX86_BUILTIN_PHSUBD256,
26779 IX86_BUILTIN_PHSUBSW256,
26780 IX86_BUILTIN_PMADDUBSW256,
26781 IX86_BUILTIN_PMADDWD256,
26782 IX86_BUILTIN_PMAXSB256,
26783 IX86_BUILTIN_PMAXSW256,
26784 IX86_BUILTIN_PMAXSD256,
26785 IX86_BUILTIN_PMAXUB256,
26786 IX86_BUILTIN_PMAXUW256,
26787 IX86_BUILTIN_PMAXUD256,
26788 IX86_BUILTIN_PMINSB256,
26789 IX86_BUILTIN_PMINSW256,
26790 IX86_BUILTIN_PMINSD256,
26791 IX86_BUILTIN_PMINUB256,
26792 IX86_BUILTIN_PMINUW256,
26793 IX86_BUILTIN_PMINUD256,
26794 IX86_BUILTIN_PMOVMSKB256,
26795 IX86_BUILTIN_PMOVSXBW256,
26796 IX86_BUILTIN_PMOVSXBD256,
26797 IX86_BUILTIN_PMOVSXBQ256,
26798 IX86_BUILTIN_PMOVSXWD256,
26799 IX86_BUILTIN_PMOVSXWQ256,
26800 IX86_BUILTIN_PMOVSXDQ256,
26801 IX86_BUILTIN_PMOVZXBW256,
26802 IX86_BUILTIN_PMOVZXBD256,
26803 IX86_BUILTIN_PMOVZXBQ256,
26804 IX86_BUILTIN_PMOVZXWD256,
26805 IX86_BUILTIN_PMOVZXWQ256,
26806 IX86_BUILTIN_PMOVZXDQ256,
26807 IX86_BUILTIN_PMULDQ256,
26808 IX86_BUILTIN_PMULHRSW256,
26809 IX86_BUILTIN_PMULHUW256,
26810 IX86_BUILTIN_PMULHW256,
26811 IX86_BUILTIN_PMULLW256,
26812 IX86_BUILTIN_PMULLD256,
26813 IX86_BUILTIN_PMULUDQ256,
26814 IX86_BUILTIN_POR256,
26815 IX86_BUILTIN_PSADBW256,
26816 IX86_BUILTIN_PSHUFB256,
26817 IX86_BUILTIN_PSHUFD256,
26818 IX86_BUILTIN_PSHUFHW256,
26819 IX86_BUILTIN_PSHUFLW256,
26820 IX86_BUILTIN_PSIGNB256,
26821 IX86_BUILTIN_PSIGNW256,
26822 IX86_BUILTIN_PSIGND256,
26823 IX86_BUILTIN_PSLLDQI256,
26824 IX86_BUILTIN_PSLLWI256,
26825 IX86_BUILTIN_PSLLW256,
26826 IX86_BUILTIN_PSLLDI256,
26827 IX86_BUILTIN_PSLLD256,
26828 IX86_BUILTIN_PSLLQI256,
26829 IX86_BUILTIN_PSLLQ256,
26830 IX86_BUILTIN_PSRAWI256,
26831 IX86_BUILTIN_PSRAW256,
26832 IX86_BUILTIN_PSRADI256,
26833 IX86_BUILTIN_PSRAD256,
26834 IX86_BUILTIN_PSRLDQI256,
26835 IX86_BUILTIN_PSRLWI256,
26836 IX86_BUILTIN_PSRLW256,
26837 IX86_BUILTIN_PSRLDI256,
26838 IX86_BUILTIN_PSRLD256,
26839 IX86_BUILTIN_PSRLQI256,
26840 IX86_BUILTIN_PSRLQ256,
26841 IX86_BUILTIN_PSUBB256,
26842 IX86_BUILTIN_PSUBW256,
26843 IX86_BUILTIN_PSUBD256,
26844 IX86_BUILTIN_PSUBQ256,
26845 IX86_BUILTIN_PSUBSB256,
26846 IX86_BUILTIN_PSUBSW256,
26847 IX86_BUILTIN_PSUBUSB256,
26848 IX86_BUILTIN_PSUBUSW256,
26849 IX86_BUILTIN_PUNPCKHBW256,
26850 IX86_BUILTIN_PUNPCKHWD256,
26851 IX86_BUILTIN_PUNPCKHDQ256,
26852 IX86_BUILTIN_PUNPCKHQDQ256,
26853 IX86_BUILTIN_PUNPCKLBW256,
26854 IX86_BUILTIN_PUNPCKLWD256,
26855 IX86_BUILTIN_PUNPCKLDQ256,
26856 IX86_BUILTIN_PUNPCKLQDQ256,
26857 IX86_BUILTIN_PXOR256,
26858 IX86_BUILTIN_MOVNTDQA256,
26859 IX86_BUILTIN_VBROADCASTSS_PS,
26860 IX86_BUILTIN_VBROADCASTSS_PS256,
26861 IX86_BUILTIN_VBROADCASTSD_PD256,
26862 IX86_BUILTIN_VBROADCASTSI256,
26863 IX86_BUILTIN_PBLENDD256,
26864 IX86_BUILTIN_PBLENDD128,
26865 IX86_BUILTIN_PBROADCASTB256,
26866 IX86_BUILTIN_PBROADCASTW256,
26867 IX86_BUILTIN_PBROADCASTD256,
26868 IX86_BUILTIN_PBROADCASTQ256,
26869 IX86_BUILTIN_PBROADCASTB128,
26870 IX86_BUILTIN_PBROADCASTW128,
26871 IX86_BUILTIN_PBROADCASTD128,
26872 IX86_BUILTIN_PBROADCASTQ128,
26873 IX86_BUILTIN_VPERMVARSI256,
26874 IX86_BUILTIN_VPERMDF256,
26875 IX86_BUILTIN_VPERMVARSF256,
26876 IX86_BUILTIN_VPERMDI256,
26877 IX86_BUILTIN_VPERMTI256,
26878 IX86_BUILTIN_VEXTRACT128I256,
26879 IX86_BUILTIN_VINSERT128I256,
26880 IX86_BUILTIN_MASKLOADD,
26881 IX86_BUILTIN_MASKLOADQ,
26882 IX86_BUILTIN_MASKLOADD256,
26883 IX86_BUILTIN_MASKLOADQ256,
26884 IX86_BUILTIN_MASKSTORED,
26885 IX86_BUILTIN_MASKSTOREQ,
26886 IX86_BUILTIN_MASKSTORED256,
26887 IX86_BUILTIN_MASKSTOREQ256,
26888 IX86_BUILTIN_PSLLVV4DI,
26889 IX86_BUILTIN_PSLLVV2DI,
26890 IX86_BUILTIN_PSLLVV8SI,
26891 IX86_BUILTIN_PSLLVV4SI,
26892 IX86_BUILTIN_PSRAVV8SI,
26893 IX86_BUILTIN_PSRAVV4SI,
26894 IX86_BUILTIN_PSRLVV4DI,
26895 IX86_BUILTIN_PSRLVV2DI,
26896 IX86_BUILTIN_PSRLVV8SI,
26897 IX86_BUILTIN_PSRLVV4SI,
26899 IX86_BUILTIN_GATHERSIV2DF,
26900 IX86_BUILTIN_GATHERSIV4DF,
26901 IX86_BUILTIN_GATHERDIV2DF,
26902 IX86_BUILTIN_GATHERDIV4DF,
26903 IX86_BUILTIN_GATHERSIV4SF,
26904 IX86_BUILTIN_GATHERSIV8SF,
26905 IX86_BUILTIN_GATHERDIV4SF,
26906 IX86_BUILTIN_GATHERDIV8SF,
26907 IX86_BUILTIN_GATHERSIV2DI,
26908 IX86_BUILTIN_GATHERSIV4DI,
26909 IX86_BUILTIN_GATHERDIV2DI,
26910 IX86_BUILTIN_GATHERDIV4DI,
26911 IX86_BUILTIN_GATHERSIV4SI,
26912 IX86_BUILTIN_GATHERSIV8SI,
26913 IX86_BUILTIN_GATHERDIV4SI,
26914 IX86_BUILTIN_GATHERDIV8SI,
26916 /* Alternate 4 element gather for the vectorizer where
26917 all operands are 32-byte wide. */
26918 IX86_BUILTIN_GATHERALTSIV4DF,
26919 IX86_BUILTIN_GATHERALTDIV8SF,
26920 IX86_BUILTIN_GATHERALTSIV4DI,
26921 IX86_BUILTIN_GATHERALTDIV8SI,
26923 /* TFmode support builtins. */
26924 IX86_BUILTIN_INFQ,
26925 IX86_BUILTIN_HUGE_VALQ,
26926 IX86_BUILTIN_FABSQ,
26927 IX86_BUILTIN_COPYSIGNQ,
26929 /* Vectorizer support builtins. */
26930 IX86_BUILTIN_CPYSGNPS,
26931 IX86_BUILTIN_CPYSGNPD,
26932 IX86_BUILTIN_CPYSGNPS256,
26933 IX86_BUILTIN_CPYSGNPD256,
26935 /* FMA4 instructions. */
26936 IX86_BUILTIN_VFMADDSS,
26937 IX86_BUILTIN_VFMADDSD,
26938 IX86_BUILTIN_VFMADDPS,
26939 IX86_BUILTIN_VFMADDPD,
26940 IX86_BUILTIN_VFMADDPS256,
26941 IX86_BUILTIN_VFMADDPD256,
26942 IX86_BUILTIN_VFMADDSUBPS,
26943 IX86_BUILTIN_VFMADDSUBPD,
26944 IX86_BUILTIN_VFMADDSUBPS256,
26945 IX86_BUILTIN_VFMADDSUBPD256,
26947 /* FMA3 instructions. */
26948 IX86_BUILTIN_VFMADDSS3,
26949 IX86_BUILTIN_VFMADDSD3,
26951 /* XOP instructions. */
26952 IX86_BUILTIN_VPCMOV,
26953 IX86_BUILTIN_VPCMOV_V2DI,
26954 IX86_BUILTIN_VPCMOV_V4SI,
26955 IX86_BUILTIN_VPCMOV_V8HI,
26956 IX86_BUILTIN_VPCMOV_V16QI,
26957 IX86_BUILTIN_VPCMOV_V4SF,
26958 IX86_BUILTIN_VPCMOV_V2DF,
26959 IX86_BUILTIN_VPCMOV256,
26960 IX86_BUILTIN_VPCMOV_V4DI256,
26961 IX86_BUILTIN_VPCMOV_V8SI256,
26962 IX86_BUILTIN_VPCMOV_V16HI256,
26963 IX86_BUILTIN_VPCMOV_V32QI256,
26964 IX86_BUILTIN_VPCMOV_V8SF256,
26965 IX86_BUILTIN_VPCMOV_V4DF256,
26967 IX86_BUILTIN_VPPERM,
26969 IX86_BUILTIN_VPMACSSWW,
26970 IX86_BUILTIN_VPMACSWW,
26971 IX86_BUILTIN_VPMACSSWD,
26972 IX86_BUILTIN_VPMACSWD,
26973 IX86_BUILTIN_VPMACSSDD,
26974 IX86_BUILTIN_VPMACSDD,
26975 IX86_BUILTIN_VPMACSSDQL,
26976 IX86_BUILTIN_VPMACSSDQH,
26977 IX86_BUILTIN_VPMACSDQL,
26978 IX86_BUILTIN_VPMACSDQH,
26979 IX86_BUILTIN_VPMADCSSWD,
26980 IX86_BUILTIN_VPMADCSWD,
26982 IX86_BUILTIN_VPHADDBW,
26983 IX86_BUILTIN_VPHADDBD,
26984 IX86_BUILTIN_VPHADDBQ,
26985 IX86_BUILTIN_VPHADDWD,
26986 IX86_BUILTIN_VPHADDWQ,
26987 IX86_BUILTIN_VPHADDDQ,
26988 IX86_BUILTIN_VPHADDUBW,
26989 IX86_BUILTIN_VPHADDUBD,
26990 IX86_BUILTIN_VPHADDUBQ,
26991 IX86_BUILTIN_VPHADDUWD,
26992 IX86_BUILTIN_VPHADDUWQ,
26993 IX86_BUILTIN_VPHADDUDQ,
26994 IX86_BUILTIN_VPHSUBBW,
26995 IX86_BUILTIN_VPHSUBWD,
26996 IX86_BUILTIN_VPHSUBDQ,
26998 IX86_BUILTIN_VPROTB,
26999 IX86_BUILTIN_VPROTW,
27000 IX86_BUILTIN_VPROTD,
27001 IX86_BUILTIN_VPROTQ,
27002 IX86_BUILTIN_VPROTB_IMM,
27003 IX86_BUILTIN_VPROTW_IMM,
27004 IX86_BUILTIN_VPROTD_IMM,
27005 IX86_BUILTIN_VPROTQ_IMM,
27007 IX86_BUILTIN_VPSHLB,
27008 IX86_BUILTIN_VPSHLW,
27009 IX86_BUILTIN_VPSHLD,
27010 IX86_BUILTIN_VPSHLQ,
27011 IX86_BUILTIN_VPSHAB,
27012 IX86_BUILTIN_VPSHAW,
27013 IX86_BUILTIN_VPSHAD,
27014 IX86_BUILTIN_VPSHAQ,
27016 IX86_BUILTIN_VFRCZSS,
27017 IX86_BUILTIN_VFRCZSD,
27018 IX86_BUILTIN_VFRCZPS,
27019 IX86_BUILTIN_VFRCZPD,
27020 IX86_BUILTIN_VFRCZPS256,
27021 IX86_BUILTIN_VFRCZPD256,
27023 IX86_BUILTIN_VPCOMEQUB,
27024 IX86_BUILTIN_VPCOMNEUB,
27025 IX86_BUILTIN_VPCOMLTUB,
27026 IX86_BUILTIN_VPCOMLEUB,
27027 IX86_BUILTIN_VPCOMGTUB,
27028 IX86_BUILTIN_VPCOMGEUB,
27029 IX86_BUILTIN_VPCOMFALSEUB,
27030 IX86_BUILTIN_VPCOMTRUEUB,
27032 IX86_BUILTIN_VPCOMEQUW,
27033 IX86_BUILTIN_VPCOMNEUW,
27034 IX86_BUILTIN_VPCOMLTUW,
27035 IX86_BUILTIN_VPCOMLEUW,
27036 IX86_BUILTIN_VPCOMGTUW,
27037 IX86_BUILTIN_VPCOMGEUW,
27038 IX86_BUILTIN_VPCOMFALSEUW,
27039 IX86_BUILTIN_VPCOMTRUEUW,
27041 IX86_BUILTIN_VPCOMEQUD,
27042 IX86_BUILTIN_VPCOMNEUD,
27043 IX86_BUILTIN_VPCOMLTUD,
27044 IX86_BUILTIN_VPCOMLEUD,
27045 IX86_BUILTIN_VPCOMGTUD,
27046 IX86_BUILTIN_VPCOMGEUD,
27047 IX86_BUILTIN_VPCOMFALSEUD,
27048 IX86_BUILTIN_VPCOMTRUEUD,
27050 IX86_BUILTIN_VPCOMEQUQ,
27051 IX86_BUILTIN_VPCOMNEUQ,
27052 IX86_BUILTIN_VPCOMLTUQ,
27053 IX86_BUILTIN_VPCOMLEUQ,
27054 IX86_BUILTIN_VPCOMGTUQ,
27055 IX86_BUILTIN_VPCOMGEUQ,
27056 IX86_BUILTIN_VPCOMFALSEUQ,
27057 IX86_BUILTIN_VPCOMTRUEUQ,
27059 IX86_BUILTIN_VPCOMEQB,
27060 IX86_BUILTIN_VPCOMNEB,
27061 IX86_BUILTIN_VPCOMLTB,
27062 IX86_BUILTIN_VPCOMLEB,
27063 IX86_BUILTIN_VPCOMGTB,
27064 IX86_BUILTIN_VPCOMGEB,
27065 IX86_BUILTIN_VPCOMFALSEB,
27066 IX86_BUILTIN_VPCOMTRUEB,
27068 IX86_BUILTIN_VPCOMEQW,
27069 IX86_BUILTIN_VPCOMNEW,
27070 IX86_BUILTIN_VPCOMLTW,
27071 IX86_BUILTIN_VPCOMLEW,
27072 IX86_BUILTIN_VPCOMGTW,
27073 IX86_BUILTIN_VPCOMGEW,
27074 IX86_BUILTIN_VPCOMFALSEW,
27075 IX86_BUILTIN_VPCOMTRUEW,
27077 IX86_BUILTIN_VPCOMEQD,
27078 IX86_BUILTIN_VPCOMNED,
27079 IX86_BUILTIN_VPCOMLTD,
27080 IX86_BUILTIN_VPCOMLED,
27081 IX86_BUILTIN_VPCOMGTD,
27082 IX86_BUILTIN_VPCOMGED,
27083 IX86_BUILTIN_VPCOMFALSED,
27084 IX86_BUILTIN_VPCOMTRUED,
27086 IX86_BUILTIN_VPCOMEQQ,
27087 IX86_BUILTIN_VPCOMNEQ,
27088 IX86_BUILTIN_VPCOMLTQ,
27089 IX86_BUILTIN_VPCOMLEQ,
27090 IX86_BUILTIN_VPCOMGTQ,
27091 IX86_BUILTIN_VPCOMGEQ,
27092 IX86_BUILTIN_VPCOMFALSEQ,
27093 IX86_BUILTIN_VPCOMTRUEQ,
27095 /* LWP instructions. */
27096 IX86_BUILTIN_LLWPCB,
27097 IX86_BUILTIN_SLWPCB,
27098 IX86_BUILTIN_LWPVAL32,
27099 IX86_BUILTIN_LWPVAL64,
27100 IX86_BUILTIN_LWPINS32,
27101 IX86_BUILTIN_LWPINS64,
27103 IX86_BUILTIN_CLZS,
27105 /* RTM */
27106 IX86_BUILTIN_XBEGIN,
27107 IX86_BUILTIN_XEND,
27108 IX86_BUILTIN_XABORT,
27109 IX86_BUILTIN_XTEST,
27111 /* BMI instructions. */
27112 IX86_BUILTIN_BEXTR32,
27113 IX86_BUILTIN_BEXTR64,
27114 IX86_BUILTIN_CTZS,
27116 /* TBM instructions. */
27117 IX86_BUILTIN_BEXTRI32,
27118 IX86_BUILTIN_BEXTRI64,
27120 /* BMI2 instructions. */
27121 IX86_BUILTIN_BZHI32,
27122 IX86_BUILTIN_BZHI64,
27123 IX86_BUILTIN_PDEP32,
27124 IX86_BUILTIN_PDEP64,
27125 IX86_BUILTIN_PEXT32,
27126 IX86_BUILTIN_PEXT64,
27128 /* ADX instructions. */
27129 IX86_BUILTIN_ADDCARRYX32,
27130 IX86_BUILTIN_ADDCARRYX64,
27132 /* FSGSBASE instructions. */
27133 IX86_BUILTIN_RDFSBASE32,
27134 IX86_BUILTIN_RDFSBASE64,
27135 IX86_BUILTIN_RDGSBASE32,
27136 IX86_BUILTIN_RDGSBASE64,
27137 IX86_BUILTIN_WRFSBASE32,
27138 IX86_BUILTIN_WRFSBASE64,
27139 IX86_BUILTIN_WRGSBASE32,
27140 IX86_BUILTIN_WRGSBASE64,
27142 /* RDRND instructions. */
27143 IX86_BUILTIN_RDRAND16_STEP,
27144 IX86_BUILTIN_RDRAND32_STEP,
27145 IX86_BUILTIN_RDRAND64_STEP,
27147 /* RDSEED instructions. */
27148 IX86_BUILTIN_RDSEED16_STEP,
27149 IX86_BUILTIN_RDSEED32_STEP,
27150 IX86_BUILTIN_RDSEED64_STEP,
27152 /* F16C instructions. */
27153 IX86_BUILTIN_CVTPH2PS,
27154 IX86_BUILTIN_CVTPH2PS256,
27155 IX86_BUILTIN_CVTPS2PH,
27156 IX86_BUILTIN_CVTPS2PH256,
27158 /* CFString built-in for darwin */
27159 IX86_BUILTIN_CFSTRING,
27161 /* Builtins to get CPU type and supported features. */
27162 IX86_BUILTIN_CPU_INIT,
27163 IX86_BUILTIN_CPU_IS,
27164 IX86_BUILTIN_CPU_SUPPORTS,
27166 IX86_BUILTIN_MAX
27167 };
27169 /* Table for the ix86 builtin decls. */
27172 /* Table of all of the builtin functions that are possible with different ISA's
27173 but are waiting to be built until a function is declared to use that
27174 ISA. */
27181 };
27186 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
27187 of which isa_flags to use in the ix86_builtins_isa array. Stores the
27188 function decl in the ix86_builtins array. Returns the function decl or
27189 NULL_TREE, if the builtin was not added.
27191 If the front end has a special hook for builtin functions, delay adding
27192 builtin functions that aren't in the current ISA until the ISA is changed
27193 with function specific optimization. Doing so, can save about 300K for the
27194 default compiler. When the builtin is expanded, check at that time whether
27195 it is valid.
27197 If the front end doesn't have a special hook, record all builtins, even if
27198 it isn't an instruction set in the current ISA in case the user uses
27199 function specific options for a different ISA, so that we don't get scope
27200 errors if a builtin is added in the middle of a function scope. */
27206 {
27210 {
27219 {
27225 }
27226 else
27227 {
27233 }
27234 }
27237 }
27239 /* Like def_builtin, but also marks the function decl "const". */
27244 {
27248 else
27252 }
27254 /* Add any new builtin functions for a given ISA that may not have been
27255 declared. This saves a bit of space compared to adding all of the
27256 declarations to the tree, even if we didn't use them. */
27258 static void
27260 {
27264 {
27267 {
27270 /* Don't define the builtin again. */
27276 NULL_TREE);
27281 }
27282 }
27283 }
27285 /* Bits for builtin_description.flag. */
27287 /* Set when we don't support the comparison natively, and should
27288 swap_comparison in order to support it. */
27289 #define BUILTIN_DESC_SWAP_OPERANDS 1
27291 struct builtin_description
27292 {
27299 };
27302 {
27303 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
27304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
27305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
27306 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
27307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
27308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
27309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
27310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
27311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
27312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
27313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
27314 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
27317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
27322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
27327 };
27330 {
27331 /* SSE4.2 */
27332 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
27333 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
27334 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
27335 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
27336 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
27337 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
27338 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
27339 };
27342 {
27343 /* SSE4.2 */
27344 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
27345 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
27346 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
27347 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
27348 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
27349 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
27350 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
27351 };
27353 /* Special builtins with variable number of arguments. */
27355 {
27356 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
27357 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
27358 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
27360 /* MMX */
27361 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
27363 /* 3DNow! */
27364 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
27366 /* FXSR, XSAVE and XSAVEOPT */
27367 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
27368 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
27369 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27370 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27371 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27373 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
27374 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
27375 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27376 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27377 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27379 /* SSE */
27380 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27381 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27382 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27386 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27389 /* SSE or 3DNow!A */
27390 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27391 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
27393 /* SSE2 */
27394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
27398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
27400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
27401 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
27402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
27403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27408 /* SSE3 */
27409 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27411 /* SSE4.1 */
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
27414 /* SSE4A */
27415 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27416 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27418 /* AVX */
27419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
27420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
27422 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27423 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27424 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
27426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
27428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27430 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27433 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
27434 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
27437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
27441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
27442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
27443 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
27444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
27445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
27446 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
27447 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
27449 /* AVX2 */
27450 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
27451 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
27452 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
27453 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
27454 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
27455 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
27456 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
27457 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
27458 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
27460 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
27461 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
27462 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
27463 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
27464 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
27465 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
27467 /* FSGSBASE */
27468 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27469 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27470 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27471 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27472 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27473 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27474 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27475 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27477 /* RTM */
27478 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27479 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
27480 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
27481 };
27483 /* Builtins with variable number of arguments. */
27485 {
27486 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
27487 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
27488 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
27489 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27490 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27491 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27492 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27494 /* MMX */
27495 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27496 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27497 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27498 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27499 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27500 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27502 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27503 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27504 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27505 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27506 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27507 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27508 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27509 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27511 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27512 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27514 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27515 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27516 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27517 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27519 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27520 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27521 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27522 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27523 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27524 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27526 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27527 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27528 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27529 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27530 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27531 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27533 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27534 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27535 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27537 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27539 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27540 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27541 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27542 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27543 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27544 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27546 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27547 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27548 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27549 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27550 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27551 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27553 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27554 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27555 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27556 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27558 /* 3DNow! */
27559 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27560 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27561 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27562 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27564 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27565 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27566 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27567 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27568 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27569 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27570 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27571 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27572 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27573 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27574 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27575 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27576 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27577 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27578 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27580 /* 3DNow!A */
27581 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27582 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27583 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27584 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27585 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27586 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27588 /* SSE */
27589 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27590 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27591 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27592 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27593 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27594 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27595 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27596 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27597 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27598 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27599 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27600 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27602 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27604 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27605 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27606 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27607 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27608 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27609 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27610 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27611 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27613 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27614 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27615 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27616 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27617 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27618 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27619 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27620 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27621 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27622 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27623 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27624 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27625 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27626 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27627 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27628 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27629 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27630 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27631 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27632 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27634 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27635 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27636 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27637 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27639 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27640 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27641 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27642 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27644 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27646 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27647 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27648 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27649 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27650 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27652 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27653 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27654 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27656 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27658 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27659 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27660 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27662 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27663 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27665 /* SSE MMX or 3Dnow!A */
27666 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27667 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27668 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27670 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27671 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27672 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27673 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27675 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27676 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27678 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27680 /* SSE2 */
27681 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27683 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27684 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27685 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27686 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27687 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27689 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27690 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27691 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27692 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27693 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27695 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27698 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27699 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27700 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27702 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27703 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27704 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27706 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27707 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27708 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27709 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27710 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27711 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27712 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27713 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27715 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27716 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27717 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27718 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27719 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27720 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27721 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27722 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27723 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27724 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27725 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27726 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27727 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27728 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27729 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27731 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27732 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27733 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27734 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27736 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27737 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27738 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27739 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27741 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27742 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27743 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27744 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27746 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27748 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27749 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27750 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27752 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27754 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27755 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27756 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27757 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27758 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27759 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27760 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27761 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27768 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27769 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27770 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27772 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27773 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27775 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27776 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27777 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27778 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27781 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27783 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27786 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27787 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27788 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27790 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27791 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27792 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27793 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27795 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27796 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27797 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27798 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27799 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27800 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27801 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27802 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27804 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27805 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27808 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27812 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27817 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27819 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27822 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27823 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27824 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27825 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27826 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27827 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27829 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27830 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27831 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27832 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27833 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27834 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27835 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27837 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27838 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27839 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27840 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27848 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27850 /* SSE2 MMX */
27851 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27852 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27854 /* SSE3 */
27855 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27856 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27858 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27859 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27860 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27861 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27862 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27863 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27865 /* SSSE3 */
27866 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27867 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27868 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27869 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27870 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27871 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27873 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27874 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27875 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27876 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27877 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27878 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27879 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27880 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27881 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27882 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27883 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27884 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27885 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27886 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27887 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27888 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27889 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27890 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27891 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27892 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27893 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27894 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27895 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27896 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27898 /* SSSE3. */
27899 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27900 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27902 /* SSE4.1 */
27903 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27904 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27905 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27906 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27907 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27908 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27909 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27910 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27911 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27912 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27914 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27915 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27916 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27917 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27918 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27919 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27920 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27921 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27922 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27923 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27924 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27925 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27926 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27928 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27929 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27930 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27931 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27932 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27933 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27934 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27935 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27936 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27937 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27938 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27939 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27941 /* SSE4.1 */
27942 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27943 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27944 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27945 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27947 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27948 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27949 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27950 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27952 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27953 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27955 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27956 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27958 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27959 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27960 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27961 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27963 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27964 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27966 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27967 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27969 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27970 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27971 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27973 /* SSE4.2 */
27974 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27975 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27976 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27977 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27978 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27980 /* SSE4A */
27981 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27982 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27983 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27984 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27986 /* AES */
27987 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27988 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27990 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27991 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27992 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27993 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27995 /* PCLMUL */
27996 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27998 /* AVX */
27999 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28000 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28002 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28003 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28004 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28007 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28009 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28013 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28014 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28015 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28016 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28017 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28018 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28019 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28020 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28021 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28022 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28023 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28024 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28026 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
28027 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
28028 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
28029 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
28031 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28032 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28033 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
28034 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
28035 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28037 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28038 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28042 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28043 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28044 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
28045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
28046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
28047 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
28048 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
28049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
28050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
28052 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
28053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
28054 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
28058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
28059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
28060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
28062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
28063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
28064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
28066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28070 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28072 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28074 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28078 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28079 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
28081 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
28082 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
28083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
28084 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
28086 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28087 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
28089 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
28090 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
28092 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
28093 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
28094 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
28095 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
28097 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
28098 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
28100 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28101 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28103 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28104 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28105 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28106 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28108 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
28109 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
28110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
28111 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
28112 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
28113 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
28115 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28116 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28117 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28118 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28119 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28120 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28121 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28122 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28123 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28124 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28125 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28126 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28127 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
28132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
28134 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28135 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28137 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
28139 /* AVX2 */
28140 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
28141 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
28142 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
28143 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
28144 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
28145 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
28146 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
28147 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
28148 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28149 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28150 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28151 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28152 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28153 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28154 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28155 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28156 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
28157 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28158 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28159 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28160 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28161 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
28162 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
28163 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28164 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28165 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28166 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28167 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28168 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28169 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28170 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28171 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28172 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28173 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28174 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28175 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28176 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28177 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
28178 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
28179 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28180 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28181 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28182 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28183 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28184 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28185 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28186 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28187 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28188 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28189 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28190 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28191 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
28192 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
28193 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
28194 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
28195 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
28196 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
28197 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
28198 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
28199 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
28200 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
28201 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
28202 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
28203 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
28204 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
28205 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28206 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28207 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28208 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28209 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28210 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
28211 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28212 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
28213 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28214 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
28215 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
28216 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
28217 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28218 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28219 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28220 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
28221 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28222 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28223 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28224 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28225 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
28226 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
28227 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28228 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28229 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28230 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28231 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
28232 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28233 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28234 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28235 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28236 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
28237 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
28238 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28239 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28240 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28241 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28242 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28243 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28244 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28245 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28246 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28247 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28248 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28249 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28250 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28251 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28252 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28253 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28254 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28255 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
28256 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
28257 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
28258 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
28259 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
28260 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
28261 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
28262 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
28263 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
28264 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
28265 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
28266 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
28267 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
28268 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
28269 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28270 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
28271 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28272 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
28273 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
28274 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
28275 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
28276 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28277 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28278 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28279 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28280 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28281 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28282 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28283 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28284 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28285 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28287 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
28289 /* BMI */
28290 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28291 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28292 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
28294 /* TBM */
28295 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28296 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28298 /* F16C */
28299 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
28300 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
28301 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
28302 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
28304 /* BMI2 */
28305 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28306 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28307 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28308 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28309 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28310 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28311 };
28313 /* FMA4 and XOP. */
28314 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
28315 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
28316 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
28317 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
28318 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
28319 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
28320 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
28321 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
28322 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
28323 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
28324 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
28325 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
28326 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
28327 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
28328 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
28329 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
28330 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
28331 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
28332 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
28333 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
28334 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
28335 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
28336 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
28337 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
28338 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
28339 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
28340 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
28341 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
28342 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
28343 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
28344 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
28345 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
28346 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
28347 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
28348 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
28349 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
28350 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
28351 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
28352 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
28353 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
28354 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
28355 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
28356 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
28357 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
28358 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
28359 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
28360 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
28361 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
28362 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
28363 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
28364 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
28365 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
28368 {
28409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
28410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
28411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
28412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
28413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
28414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
28415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
28417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
28420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
28421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
28422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
28423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
28425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
28427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
28442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
28443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
28444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
28445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
28446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
28447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
28448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
28450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
28451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
28452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
28454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
28455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
28457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
28458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
28459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
28460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
28461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
28462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
28464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
28481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
28484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
28485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
28486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
28488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
28489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
28492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
28493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
28494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
28496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
28497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
28500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
28501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
28502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
28504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28567 };
28568 \f
28569 /* TM vector builtins. */
28571 /* Reuse the existing x86-specific `struct builtin_description' cause
28572 we're lazy. Add casts to make them fit. */
28574 {
28575 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28576 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28577 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28578 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28579 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28580 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28581 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28583 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28584 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28585 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28586 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28587 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28588 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28589 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28591 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28592 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28593 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28594 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28595 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28596 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28597 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28599 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28600 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28601 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28602 };
28604 /* TM callbacks. */
28606 /* Return the builtin decl needed to load a vector of TYPE. */
28608 static tree
28610 {
28612 {
28614 {
28621 }
28622 }
28624 }
28626 /* Return the builtin decl needed to store a vector of TYPE. */
28628 static tree
28630 {
28632 {
28634 {
28641 }
28642 }
28644 }
28645 \f
28646 /* Initialize the transactional memory vector load/store builtins. */
28648 static void
28650 {
28654 tree decl;
28661 /* If there are no builtins defined, we must be compiling in a
28662 language without trans-mem support. */
28666 /* Use whatever attributes a normal TM load has. */
28670 /* Use whatever attributes a normal TM store has. */
28674 /* Use whatever attributes a normal TM log has. */
28682 {
28686 {
28694 {
28697 }
28699 {
28702 }
28703 else
28704 {
28707 }
28709 /* The builtin without the prefix for
28710 calling it directly. */
28712 attrs);
28713 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28714 set the TYPE_ATTRIBUTES. */
28718 }
28719 }
28720 }
28722 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28723 in the current target ISA to allow the user to compile particular modules
28724 with different target specific options that differ from the command line
28725 options. */
28726 static void
28728 {
28733 /* Add all special builtins with variable number of operands. */
28737 {
28743 }
28745 /* Add all builtins with variable number of operands. */
28749 {
28755 }
28757 /* pcmpestr[im] insns. */
28761 {
28764 else
28767 }
28769 /* pcmpistr[im] insns. */
28773 {
28776 else
28779 }
28781 /* comi/ucomi insns. */
28783 {
28786 else
28789 }
28791 /* SSE */
28797 /* SSE or 3DNow!A */
28800 IX86_BUILTIN_MASKMOVQ);
28802 /* SSE2 */
28811 /* SSE3. */
28817 /* AES */
28831 /* PCLMUL */
28835 /* RDRND */
28842 IX86_BUILTIN_RDRAND64_STEP);
28844 /* AVX2 */
28846 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28847 IX86_BUILTIN_GATHERSIV2DF);
28850 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28851 IX86_BUILTIN_GATHERSIV4DF);
28854 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28855 IX86_BUILTIN_GATHERDIV2DF);
28858 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28859 IX86_BUILTIN_GATHERDIV4DF);
28862 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28863 IX86_BUILTIN_GATHERSIV4SF);
28866 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28867 IX86_BUILTIN_GATHERSIV8SF);
28870 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28871 IX86_BUILTIN_GATHERDIV4SF);
28874 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28875 IX86_BUILTIN_GATHERDIV8SF);
28878 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28879 IX86_BUILTIN_GATHERSIV2DI);
28882 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28883 IX86_BUILTIN_GATHERSIV4DI);
28886 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28887 IX86_BUILTIN_GATHERDIV2DI);
28890 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28891 IX86_BUILTIN_GATHERDIV4DI);
28894 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28895 IX86_BUILTIN_GATHERSIV4SI);
28898 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28899 IX86_BUILTIN_GATHERSIV8SI);
28902 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28903 IX86_BUILTIN_GATHERDIV4SI);
28906 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28907 IX86_BUILTIN_GATHERDIV8SI);
28910 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28911 IX86_BUILTIN_GATHERALTSIV4DF);
28914 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28915 IX86_BUILTIN_GATHERALTDIV8SF);
28918 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28919 IX86_BUILTIN_GATHERALTSIV4DI);
28922 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28923 IX86_BUILTIN_GATHERALTDIV8SI);
28925 /* RTM. */
28929 /* MMX access to the vec_init patterns. */
28934 V4HI_FTYPE_HI_HI_HI_HI,
28935 IX86_BUILTIN_VEC_INIT_V4HI);
28938 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28939 IX86_BUILTIN_VEC_INIT_V8QI);
28941 /* Access to the vec_extract patterns. */
28963 /* Access to the vec_set patterns. */
28984 /* RDSEED */
28993 /* ADCX */
28998 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28999 IX86_BUILTIN_ADDCARRYX64);
29001 /* Add FMA4 multi-arg argument instructions */
29003 {
29009 }
29010 }
29012 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
29013 to return a pointer to VERSION_DECL if the outcome of the expression
29014 formed by PREDICATE_CHAIN is true. This function will be called during
29015 version dispatch to decide which function version to execute. It returns
29016 the basic block at the end, to which more conditions can be added. */
29018 static basic_block
29021 {
29022 gimple return_stmt;
29024 gimple convert_stmt;
29025 gimple call_cond_stmt;
29026 gimple if_else_stmt;
29032 gimple_seq gseq;
29049 {
29057 }
29060 {
29075 else
29076 {
29077 gimple assign_stmt;
29078 /* Use MIN_EXPR to check if any integer is zero?.
29079 and_expr_var = min_expr <cond_var, and_expr_var> */
29087 }
29088 }
29091 integer_zero_node,
29121 }
29123 /* This parses the attribute arguments to target in DECL and determines
29124 the right builtin to use to match the platform specification.
29125 It returns the priority value for this version decl. If PREDICATE_LIST
29126 is not NULL, it stores the list of cpu features that need to be checked
29127 before dispatching this function. */
29129 static unsigned int
29131 {
29132 tree attrs;
29134 tree target_node;
29141 /* Priority of i386 features, greater value is higher priority. This is
29142 used to decide the order in which function dispatch must happen. For
29143 instance, a version specialized for SSE4.2 should be checked for dispatch
29144 before a version for SSE3, as SSE4.2 implies SSE3. */
29145 enum feature_priority
29146 {
29148 P_MMX,
29149 P_SSE,
29150 P_SSE2,
29151 P_SSE3,
29152 P_SSSE3,
29153 P_PROC_SSSE3,
29154 P_SSE4_a,
29155 P_PROC_SSE4_a,
29156 P_SSE4_1,
29157 P_SSE4_2,
29158 P_PROC_SSE4_2,
29159 P_POPCNT,
29160 P_AVX,
29161 P_AVX2,
29162 P_FMA,
29163 P_PROC_FMA
29164 };
29168 /* These are the target attribute strings for which a dispatcher is
29169 available, from fold_builtin_cpu. */
29171 static struct _feature_list
29172 {
29175 }
29177 {
29188 };
29191 static unsigned int NUM_FEATURES
29207 /* Return priority zero for default function. */
29211 /* Handle arch= if specified. For priority, set it to be 1 more than
29212 the best instruction set the processor can handle. For instance, if
29213 there is a version for atom and a version for ssse3 (the highest ISA
29214 priority for atom), the atom version must be checked for dispatch
29215 before the ssse3 version. */
29217 {
29226 {
29228 {
29253 }
29254 }
29259 {
29263 }
29266 {
29268 /* For a C string literal the length includes the trailing NULL. */
29271 predicate_chain);
29272 }
29273 }
29275 /* Process feature name. */
29282 {
29283 /* Do not process "arch=" */
29285 {
29288 }
29290 {
29292 {
29294 {
29299 predicate_chain);
29300 }
29301 /* Find the maximum priority feature. */
29306 }
29307 }
29309 {
29313 }
29315 }
29319 {
29322 attrs_str);
29324 }
29326 {
29329 }
29332 }
29334 /* This compares the priority of target features in function DECL1
29335 and DECL2. It returns positive value if DECL1 is higher priority,
29336 negative value if DECL2 is higher priority and 0 if they are the
29337 same. */
29339 static int
29341 {
29346 }
29348 /* V1 and V2 point to function versions with different priorities
29349 based on the target ISA. This function compares their priorities. */
29351 static int
29353 {
29355 {
29356 tree version_decl;
29357 tree predicate_chain;
29364 }
29366 /* This function generates the dispatch function for
29367 multi-versioned functions. DISPATCH_DECL is the function which will
29368 contain the dispatch logic. FNDECLS are the function choices for
29369 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
29370 in DISPATCH_DECL in which the dispatch code is generated. */
29372 static int
29376 {
29377 tree default_decl;
29378 gimple ifunc_cpu_init_stmt;
29379 gimple_seq gseq;
29381 tree ele;
29387 struct _function_version_info
29388 {
29389 tree version_decl;
29390 tree predicate_chain;
29398 /*fndecls_p is actually a vector. */
29401 /* At least one more version other than the default. */
29408 /* The first version in the vector is the default decl. */
29414 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
29415 constructors, so explicity call __builtin_cpu_init here. */
29426 {
29430 /* Get attribute string, parse it and find the right predicate decl.
29431 The predicate function could be a lengthy combination of many
29432 features, like arch-type and various isa-variants. */
29443 actual_versions++;
29444 }
29446 /* Sort the versions according to descending order of dispatch priority. The
29447 priority is based on the ISA. This is not a perfect solution. There
29448 could still be ambiguity. If more than one function version is suitable
29449 to execute, which one should be dispatched? In future, allow the user
29450 to specify a dispatch priority next to the version. */
29460 /* dispatch default version at the end. */
29466 }
29468 /* Comparator function to be used in qsort routine to sort attribute
29469 specification strings to "target". */
29471 static int
29473 {
29477 }
29479 /* ARGLIST is the argument to target attribute. This function tokenizes
29480 the comma separated arguments, sorts them and returns a string which
29481 is a unique identifier for the comma separated arguments. It also
29482 replaces non-identifier characters "=,-" with "_". */
29486 {
29487 tree arg;
29496 {
29501 argnum++;
29504 argnum++;
29505 }
29510 {
29516 }
29518 /* Replace "=,-" with "_". */
29531 {
29533 i++;
29535 }
29542 {
29547 }
29552 }
29554 /* This function changes the assembler name for functions that are
29555 versions. If DECL is a function version and has a "target"
29556 attribute, it appends the attribute string to its assembler name. */
29558 static tree
29560 {
29561 tree version_attr;
29569 "Function versions cannot be marked as gnu_inline,"
29578 /* target attribute string cannot be NULL. */
29582 version_string
29593 /* Allow assembler name to be modified if already set. */
29601 }
29603 /* This function returns true if FN1 and FN2 are versions of the same function,
29604 that is, the target strings of the function decls are different. This assumes
29605 that FN1 and FN2 have the same signature. */
29607 static bool
29609 {
29621 /* At least one function decl should have the target attribute specified. */
29625 /* Diagnose missing target attribute if one of the decls is already
29626 multi-versioned. */
29628 {
29630 {
29632 {
29637 }
29640 fn2);
29643 /* Prevent diagnosing of the same error multiple times. */
29648 }
29650 }
29655 /* The sorted target strings must be different for fn1 and fn2
29656 to be versions. */
29659 else
29666 }
29668 static tree
29670 {
29671 /* For function version, add the target suffix to the assembler name. */
29675 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29677 #endif
29680 }
29682 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29683 is true, append the full path name of the source file. */
29687 {
29695 /* Get a unique name that can be used globally without any chances
29696 of collision at link time. */
29706 /* Use '.' to concatenate names as it is demangler friendly. */
29709 suffix);
29710 else
29714 }
29716 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29718 /* Make a dispatcher declaration for the multi-versioned function DECL.
29719 Calls to DECL function will be replaced with calls to the dispatcher
29720 by the front-end. Return the decl created. */
29722 static tree
29724 {
29725 tree func_decl;
29745 /* Mark this func as external, the resolver will flip it again if
29746 it gets generated. */
29748 /* This will be of type IFUNCs have to be externally visible. */
29752 }
29754 #endif
29756 /* Returns true if decl is multi-versioned and DECL is the default function,
29757 that is it is not tagged with target specific optimization. */
29759 static bool
29761 {
29770 }
29772 /* Make a dispatcher declaration for the multi-versioned function DECL.
29773 Calls to DECL function will be replaced with calls to the dispatcher
29774 by the front-end. Returns the decl of the dispatcher function. */
29776 static tree
29778 {
29800 /* Find the default version and make it the first node. */
29802 /* Go to the beginning of the chain. */
29807 {
29812 }
29814 /* If there is no default node, just return NULL. */
29818 /* Make default info the first node. */
29820 {
29827 }
29831 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29833 {
29838 /* Right now, the dispatching is done via ifunc. */
29844 dispatcher_version_info
29849 /* Set the dispatcher for all the versions. */
29852 {
29855 }
29856 }
29857 else
29858 #endif
29859 {
29861 "multiversioning needs ifunc which is not supported "
29863 }
29866 }
29868 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29869 it to CHAIN. */
29871 static tree
29873 {
29874 tree attr_name;
29875 tree attr_arg_name;
29876 tree attr_args;
29877 tree attr;
29884 }
29886 /* Make the resolver function decl to dispatch the versions of
29887 a multi-versioned function, DEFAULT_DECL. Create an
29888 empty basic block in the resolver and store the pointer in
29889 EMPTY_BB. Return the decl of the resolver function. */
29891 static tree
29895 {
29900 /* IFUNC's have to be globally visible. So, if the default_decl is
29901 not, then the name of the IFUNC should be made unique. */
29905 /* Append the filename to the resolver function if the versions are
29906 not externally visible. This is because the resolver function has
29907 to be externally visible for the loader to find it. So, appending
29908 the filename will prevent conflicts with a resolver function from
29909 another module which is based on the same version name. */
29912 /* The resolver function should return a (void *). */
29923 /* IFUNC resolvers have to be externally visible. */
29927 /* Resolver is not external, body is generated. */
29937 {
29938 /* In this case, each translation unit with a call to this
29939 versioned function will put out a resolver. Ensure it
29940 is comdat to keep just one copy. */
29943 }
29944 /* Build result decl and add to function_decl. */
29960 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29964 /* Create the alias for dispatch to resolver here. */
29965 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29969 }
29971 /* Generate the dispatching code body to dispatch multi-versioned function
29972 DECL. The target hook is called to process the "target" attributes and
29973 provide the code to dispatch the right function at run-time. NODE points
29974 to the dispatcher decl whose body will be created. */
29976 static tree
29978 {
29979 tree resolver_decl;
29980 basic_block empty_bb;
29982 tree default_ver_decl;
29998 /* The first version in the chain corresponds to the default version. */
30001 /* node is going to be an alias, so remove the finalized bit. */
30015 {
30017 /* Check for virtual functions here again, as by this time it should
30018 have been determined if this function needs a vtable index or
30019 not. This happens for methods in derived classes that override
30020 virtual methods in base classes but are not explicitly marked as
30021 virtual. */
30026 }
30033 }
30034 /* This builds the processor_model struct type defined in
30035 libgcc/config/i386/cpuinfo.c */
30037 static tree
30039 {
30046 /* The first 3 fields are unsigned int. */
30048 {
30054 }
30056 /* The last field is an array of unsigned integers of size one. */
30067 }
30069 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
30071 static tree
30073 {
30074 tree new_decl;
30077 VAR_DECL,
30079 type);
30092 }
30094 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
30095 into an integer defined in libgcc/config/i386/cpuinfo.c */
30097 static tree
30099 {
30105 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
30106 enum processor_features
30107 {
30109 F_MMX,
30110 F_POPCNT,
30111 F_SSE,
30112 F_SSE2,
30113 F_SSE3,
30114 F_SSSE3,
30115 F_SSE4_1,
30116 F_SSE4_2,
30117 F_AVX,
30118 F_AVX2,
30119 F_MAX
30120 };
30122 /* These are the values for vendor types and cpu types and subtypes
30123 in cpuinfo.c. Cpu types and subtypes should be subtracted by
30124 the corresponding start value. */
30125 enum processor_model
30126 {
30128 M_AMD,
30129 M_CPU_TYPE_START,
30130 M_INTEL_ATOM,
30131 M_INTEL_CORE2,
30132 M_INTEL_COREI7,
30133 M_AMDFAM10H,
30134 M_AMDFAM15H,
30135 M_INTEL_SLM,
30136 M_CPU_SUBTYPE_START,
30137 M_INTEL_COREI7_NEHALEM,
30138 M_INTEL_COREI7_WESTMERE,
30139 M_INTEL_COREI7_SANDYBRIDGE,
30140 M_AMDFAM10H_BARCELONA,
30141 M_AMDFAM10H_SHANGHAI,
30142 M_AMDFAM10H_ISTANBUL,
30143 M_AMDFAM15H_BDVER1,
30144 M_AMDFAM15H_BDVER2,
30145 M_AMDFAM15H_BDVER3
30146 };
30148 static struct _arch_names_table
30149 {
30152 }
30154 {
30172 };
30174 static struct _isa_names_table
30175 {
30178 }
30180 {
30192 };
30206 {
30207 /* *args must be a expr that can contain other EXPRS leading to a
30208 STRING_CST. */
30210 {
30213 }
30215 }
30220 {
30221 tree ref;
30222 tree field;
30223 tree final;
30226 unsigned int NUM_ARCH_NAMES
30235 {
30239 }
30244 /* CPU types are stored in the next field. */
30247 {
30250 }
30252 /* CPU subtypes are stored in the next field. */
30254 {
30257 }
30259 /* Get the appropriate field in __cpu_model. */
30263 /* Check the value. */
30267 }
30269 {
30270 tree ref;
30271 tree array_elt;
30272 tree field;
30273 tree final;
30276 unsigned int NUM_ISA_NAMES
30285 {
30289 }
30292 /* Get the last field, which is __cpu_features. */
30296 /* Get the appropriate field: __cpu_model.__cpu_features */
30300 /* Access the 0th element of __cpu_features array. */
30305 /* Return __cpu_model.__cpu_features[0] & field_val */
30309 }
30311 }
30313 static tree
30316 {
30318 {
30323 {
30326 }
30327 }
30329 #ifdef SUBTARGET_FOLD_BUILTIN
30331 #endif
30334 }
30336 /* Make builtins to detect cpu type and features supported. NAME is
30337 the builtin name, CODE is the builtin code, and FTYPE is the function
30338 type of the builtin. */
30340 static void
30343 {
30344 tree decl;
30345 tree type;
30353 }
30355 /* Make builtins to get CPU type and features supported. The created
30356 builtins are :
30358 __builtin_cpu_init (), to detect cpu type and features,
30359 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
30360 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
30361 */
30363 static void
30365 {
30372 }
30374 /* Internal method for ix86_init_builtins. */
30376 static void
30378 {
30390 sysv_va_ref =
30393 fnvoid_va_end_ms =
30395 fnvoid_va_start_ms =
30397 fnvoid_va_end_sysv =
30399 fnvoid_va_start_sysv =
30401 NULL_TREE);
30402 fnvoid_va_copy_ms =
30404 NULL_TREE);
30405 fnvoid_va_copy_sysv =
30421 }
30423 static void
30425 {
30428 /* The __float80 type. */
30431 {
30432 /* The __float80 type. */
30437 }
30440 /* The __float128 type. */
30446 /* This macro is built by i386-builtin-types.awk. */
30447 DEFINE_BUILTIN_PRIMITIVE_TYPES;
30448 }
30450 static void
30452 {
30453 tree t;
30457 /* Builtins to get CPU type and features. */
30460 /* TFmode support builtins. */
30466 /* We will expand them to normal call if SSE isn't available since
30467 they are used by libgcc. */
30486 #ifdef SUBTARGET_INIT_BUILTINS
30487 SUBTARGET_INIT_BUILTINS;
30488 #endif
30489 }
30491 /* Return the ix86 builtin for CODE. */
30493 static tree
30495 {
30500 }
30502 /* Errors in the source file can cause expand_expr to return const0_rtx
30503 where we expect a vector. To avoid crashing, use one of the vector
30504 clear instructions. */
30505 static rtx
30507 {
30511 }
30513 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30515 static rtx
30517 {
30518 rtx pat;
30538 {
30542 }
30556 }
30558 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30560 static rtx
30564 {
30565 rtx pat;
30573 rtx op;
30580 {
30660 }
30670 {
30677 {
30679 {
30682 {
30700 xop_rotl:
30702 {
30705 gcc_checking_assert
30707 }
30708 else
30709 {
30710 gcc_checking_assert
30721 }
30725 }
30726 }
30727 }
30728 else
30729 {
30730 non_constant:
30734 /* If we aren't optimizing, only allow one memory operand to be
30735 generated. */
30737 num_memory++;
30745 }
30749 }
30752 {
30763 else
30764 {
30770 }
30783 }
30790 }
30792 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30793 insns with vec_merge. */
30795 static rtx
30797 rtx target)
30798 {
30799 rtx pat;
30826 }
30828 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30830 static rtx
30833 {
30834 rtx pat;
30839 rtx op2;
30850 /* Swap operands if we have a comparison that isn't available in
30851 hardware. */
30853 {
30858 }
30878 }
30880 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30882 static rtx
30884 rtx target)
30885 {
30886 rtx pat;
30900 /* Swap operands if we have a comparison that isn't available in
30901 hardware. */
30903 {
30907 }
30928 const0_rtx)));
30931 }
30933 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30935 static rtx
30937 rtx target)
30938 {
30939 rtx pat;
30964 }
30966 static rtx
30969 {
30970 rtx pat;
30975 rtx op2;
31002 }
31004 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
31006 static rtx
31008 rtx target)
31009 {
31010 rtx pat;
31043 const0_rtx)));
31046 }
31048 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
31050 static rtx
31053 {
31054 rtx pat;
31092 {
31095 }
31098 {
31107 }
31109 {
31118 }
31119 else
31120 {
31127 }
31135 {
31140 emit_insn
31144 FLAGS_REG),
31145 const0_rtx)));
31147 }
31148 else
31150 }
31153 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
31155 static rtx
31158 {
31159 rtx pat;
31187 {
31190 }
31193 {
31202 }
31204 {
31213 }
31214 else
31215 {
31222 }
31230 {
31235 emit_insn
31239 FLAGS_REG),
31240 const0_rtx)));
31242 }
31243 else
31245 }
31247 /* Subroutine of ix86_expand_builtin to take care of insns with
31248 variable number of operands. */
31250 static rtx
31253 {
31258 struct
31259 {
31260 rtx op;
31272 {
31551 }
31556 {
31559 }
31562 {
31569 }
31570 else
31571 {
31574 }
31577 {
31584 {
31585 /* SIMD shift insns take either an 8-bit immediate or
31586 register as count. But builtin functions take int as
31587 count. If count doesn't match, we put it in register. */
31589 {
31593 }
31594 }
31596 {
31599 {
31653 {
31656 {
31659 }
31665 }
31667 }
31668 }
31669 else
31670 {
31674 /* If we aren't optimizing, only allow one memory operand to
31675 be generated. */
31677 num_memory++;
31680 {
31683 }
31684 else
31685 {
31688 }
31689 }
31693 }
31696 {
31713 }
31720 }
31722 /* Subroutine of ix86_expand_builtin to take care of special insns
31723 with variable number of operands. */
31725 static rtx
31728 {
31729 tree arg;
31732 struct
31733 {
31734 rtx op;
31744 {
31792 /* Reserve memory operand for target. */
31823 /* Reserve memory operand for target. */
31837 }
31842 {
31847 {
31850 }
31851 else
31854 }
31855 else
31856 {
31863 }
31866 {
31875 {
31877 {
31883 else
31886 }
31887 }
31888 else
31889 {
31891 {
31892 /* This must be the memory operand. */
31897 }
31898 else
31899 {
31900 /* This must be register. */
31907 }
31908 }
31912 }
31915 {
31930 }
31936 }
31938 /* Return the integer constant in ARG. Constrain it to be in the range
31939 of the subparts of VEC_TYPE; issue an error if not. */
31941 static int
31943 {
31948 {
31951 }
31954 }
31956 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31957 ix86_expand_vector_init. We DO have language-level syntax for this, in
31958 the form of (type){ init-list }. Except that since we can't place emms
31959 instructions from inside the compiler, we can't allow the use of MMX
31960 registers unless the user explicitly asks for it. So we do *not* define
31961 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31962 we have builtins invoked by mmintrin.h that gives us license to emit
31963 these sorts of instructions. */
31965 static rtx
31967 {
31977 {
31980 }
31987 }
31989 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31990 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31991 had a language-level syntax for referencing vector elements. */
31993 static rtx
31995 {
31999 rtx op0;
32019 }
32021 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
32022 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
32023 a language-level syntax for referencing vector elements. */
32025 static rtx
32027 {
32051 /* OP0 is the source of these builtin functions and shouldn't be
32052 modified. Create a copy, use it and return it as target. */
32058 }
32060 /* Expand an expression EXP that calls a built-in function,
32061 with result going to TARGET if that's convenient
32062 (and in mode MODE if that's convenient).
32063 SUBTARGET may be used as the target for computing one of EXP's operands.
32064 IGNORE is nonzero if the value is to be ignored. */
32066 static rtx
32070 {
32080 /* For CPU builtins that can be folded, fold first and expand the fold. */
32082 {
32084 {
32085 /* Make it call __cpu_indicator_init in libgcc. */
32091 }
32094 {
32099 }
32100 }
32102 /* Determine whether the builtin function is available under the current ISA.
32103 Originally the builtin was not created if it wasn't applicable to the
32104 current ISA based on the command line switches. With function specific
32105 options, we need to check in the context of the function making the call
32106 whether it is supported. */
32109 {
32115 else
32116 {
32120 }
32122 }
32125 {
32129 ? CODE_FOR_mmx_maskmovq
32131 /* Note the arg order is different from the operand order. */
32232 {
32233 REAL_VALUE_TYPE inf;
32234 rtx tmp;
32246 }
32256 {
32262 insn = (TARGET_64BIT
32266 }
32268 {
32269 insn = (TARGET_64BIT
32273 }
32274 else
32275 {
32278 insn = (TARGET_64BIT
32286 {
32289 }
32291 }
32294 {
32295 /* mode is VOIDmode if __builtin_rd* has been called
32296 without lhs. */
32300 }
32303 {
32308 }
32318 {
32333 }
32339 {
32342 }
32362 {
32365 }
32371 {
32375 {
32396 }
32401 }
32402 else
32403 {
32405 {
32417 }
32419 }
32449 ? CODE_FOR_tbm_bextri_si
32452 {
32455 }
32456 else
32457 {
32466 }
32482 rdrand_step:
32489 {
32492 }
32498 /* Emit SImode conditional move. */
32500 {
32503 }
32506 else
32513 const0_rtx);
32532 rdseed_step:
32539 {
32542 }
32548 const0_rtx);
32566 addcarryx:
32574 /* Generate CF from input operand. */
32579 /* Gen ADCX instruction to compute X+Y+CF. */
32594 /* Store the result. */
32597 {
32600 }
32603 /* Return current CF value. */
32672 gather_gen:
32683 /* Note the arg order is different from the operand order. */
32692 else
32697 {
32703 }
32706 {
32711 else
32721 }
32723 /* Force memory operand only with base register here. But we
32724 don't want to do it on memory operand for other builtin
32725 functions. */
32737 {
32740 }
32742 /* Optimize. If mask is known to have all high bits set,
32743 replace op0 with pc_rtx to signal that the instruction
32744 overwrites the whole destination and doesn't use its
32745 previous contents. */
32747 {
32749 {
32752 {
32756 negative++;
32759 negative++;
32760 }
32763 }
32765 {
32766 /* Recognize also when mask is like:
32767 __v2df src = _mm_setzero_pd ();
32768 __v2df mask = _mm_cmpeq_pd (src, src);
32769 or
32770 __v8sf src = _mm256_setzero_ps ();
32771 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32772 as that is a cheaper way to load all ones into
32773 a register than having to load a constant from
32774 memory. */
32777 {
32782 {
32789 /* FALLTHRU */
32799 }
32800 }
32801 }
32802 }
32811 {
32818 else
32820 }
32821 else
32832 {
32835 }
32841 }
32854 {
32858 /* Emit a normal call if SSE isn't available. */
32862 }
32887 }
32889 /* Returns a function decl for a vectorized version of the builtin function
32890 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32891 if it is not available. */
32893 static tree
32895 tree type_in)
32896 {
32912 {
32915 {
32920 }
32925 {
32930 }
32936 /* The round insn does not trap on denormals. */
32941 {
32946 }
32952 /* The round insn does not trap on denormals. */
32957 {
32962 }
32968 /* The round insn does not trap on denormals. */
32973 {
32978 }
32984 /* The round insn does not trap on denormals. */
32989 {
32994 }
33001 {
33006 }
33013 {
33018 }
33024 /* The round insn does not trap on denormals. */
33029 {
33034 }
33040 /* The round insn does not trap on denormals. */
33045 {
33050 }
33055 {
33060 }
33065 {
33070 }
33074 /* The round insn does not trap on denormals. */
33079 {
33084 }
33088 /* The round insn does not trap on denormals. */
33093 {
33098 }
33102 /* The round insn does not trap on denormals. */
33107 {
33112 }
33116 /* The round insn does not trap on denormals. */
33121 {
33126 }
33130 /* The round insn does not trap on denormals. */
33135 {
33140 }
33144 /* The round insn does not trap on denormals. */
33149 {
33154 }
33158 /* The round insn does not trap on denormals. */
33163 {
33168 }
33172 /* The round insn does not trap on denormals. */
33177 {
33182 }
33186 /* The round insn does not trap on denormals. */
33191 {
33196 }
33200 /* The round insn does not trap on denormals. */
33205 {
33210 }
33215 {
33220 }
33225 {
33230 }
33235 }
33237 /* Dispatch to a handler for a vectorization library. */
33240 type_in);
33243 }
33245 /* Handler for an SVML-style interface to
33246 a library with vectorized intrinsics. */
33248 static tree
33250 {
33258 /* The SVML is suitable for unsafe math only. */
33271 {
33318 }
33327 {
33330 }
33331 else
33334 /* Convert to uppercase. */
33339 args;
33341 arity++;
33345 else
33348 /* Build a function declaration for the vectorized function. */
33357 }
33359 /* Handler for an ACML-style interface to
33360 a library with vectorized intrinsics. */
33362 static tree
33364 {
33372 /* The ACML is 64bits only and suitable for unsafe math only as
33373 it does not correctly support parts of IEEE with the required
33374 precision such as denormals. */
33388 {
33418 }
33425 args;
33427 arity++;
33431 else
33434 /* Build a function declaration for the vectorized function. */
33443 }
33445 /* Returns a decl of a function that implements gather load with
33446 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
33447 Return NULL_TREE if it is not available. */
33449 static tree
33452 {
33468 /* v*gather* insn sign extends index to pointer mode. */
33480 {
33507 }
33510 }
33512 /* Returns a code for a target-specific builtin that implements
33513 reciprocal of the function, or NULL_TREE if not available. */
33515 static tree
33518 {
33525 /* Machine dependent builtins. */
33527 {
33528 /* Vectorized version of sqrt to rsqrt conversion. */
33537 }
33538 else
33539 /* Normal builtins. */
33541 {
33542 /* Sqrt to rsqrt conversion. */
33548 }
33549 }
33550 \f
33551 /* Helper for avx_vpermilps256_operand et al. This is also used by
33552 the expansion functions to turn the parallel back into a mask.
33553 The return value is 0 for no match and the imm8+1 for a match. */
33555 int
33557 {
33565 /* Validate that all of the elements are constants, and not totally
33566 out of range. Copy the data into an integral array to make the
33567 subsequent checks easier. */
33569 {
33579 }
33582 {
33584 /* In the 256-bit DFmode case, we can only move elements within
33585 a 128-bit lane. */
33587 {
33591 }
33593 {
33597 }
33601 /* In the 256-bit SFmode case, we have full freedom of movement
33602 within the low 128-bit lane, but the high 128-bit lane must
33603 mirror the exact same pattern. */
33608 /* FALLTHRU */
33612 /* In the 128-bit case, we've full freedom in the placement of
33613 the elements from the source operand. */
33620 }
33622 /* Make sure success has a non-zero value by adding one. */
33624 }
33626 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33627 the expansion functions to turn the parallel back into a mask.
33628 The return value is 0 for no match and the imm8+1 for a match. */
33630 int
33632 {
33640 /* Validate that all of the elements are constants, and not totally
33641 out of range. Copy the data into an integral array to make the
33642 subsequent checks easier. */
33644 {
33654 }
33656 /* Validate that the halves of the permute are halves. */
33664 /* Reconstruct the mask. */
33666 {
33672 }
33674 /* Make sure success has a non-zero value by adding one. */
33676 }
33677 \f
33678 /* Store OPERAND to the memory after reload is completed. This means
33679 that we can't easily use assign_stack_local. */
33680 rtx
33682 {
33683 rtx result;
33687 {
33690 stack_pointer_rtx,
33693 }
33695 {
33697 {
33701 /* FALLTHRU */
33707 stack_pointer_rtx)),
33708 operand));
33712 }
33714 }
33715 else
33716 {
33718 {
33720 {
33727 stack_pointer_rtx)),
33733 stack_pointer_rtx)),
33735 }
33738 /* Store HImodes as SImodes. */
33740 /* FALLTHRU */
33746 stack_pointer_rtx)),
33747 operand));
33751 }
33753 }
33755 }
33757 /* Free operand from the memory. */
33758 void
33760 {
33762 {
33767 else
33769 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33770 to pop or add instruction if registers are available. */
33774 }
33775 }
33777 /* Return a register priority for hard reg REGNO. */
33778 static int
33780 {
33781 /* ebp and r13 as the base always wants a displacement, r12 as the
33782 base always wants an index. So discourage their usage in an
33783 address. */
33788 /* New x86-64 int registers result in bigger code size. Discourage
33789 them. */
33792 /* New x86-64 SSE registers result in bigger code size. Discourage
33793 them. */
33796 /* Usage of AX register results in smaller code. Prefer it. */
33800 }
33802 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33804 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33805 QImode must go into class Q_REGS.
33806 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33807 movdf to do mem-to-mem moves through integer regs. */
33809 static reg_class_t
33811 {
33814 /* We're only allowed to return a subclass of CLASS. Many of the
33815 following checks fail for NO_REGS, so eliminate that early. */
33819 /* All classes can load zeros. */
33823 /* Force constants into memory if we are loading a (nonzero) constant into
33824 an MMX or SSE register. This is because there are no MMX/SSE instructions
33825 to load from a constant. */
33830 /* Prefer SSE regs only, if we can use them for math. */
33834 /* Floating-point constants need more complex checks. */
33836 {
33837 /* General regs can load everything. */
33841 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33842 zero above. We only want to wind up preferring 80387 registers if
33843 we plan on doing computation with them. */
33846 {
33847 /* Limit class to non-sse. */
33856 }
33859 }
33861 /* Generally when we see PLUS here, it's the function invariant
33862 (plus soft-fp const_int). Which can only be computed into general
33863 regs. */
33867 /* QImode constants are easy to load, but non-constant QImode data
33868 must go into Q_REGS. */
33870 {
33876 }
33879 }
33881 /* Discourage putting floating-point values in SSE registers unless
33882 SSE math is being used, and likewise for the 387 registers. */
33883 static reg_class_t
33885 {
33888 /* Restrict the output reload class to the register bank that we are doing
33889 math on. If we would like not to return a subset of CLASS, reject this
33890 alternative: if reload cannot do this, it will still use its choice. */
33896 {
33901 else
33903 }
33906 }
33908 static reg_class_t
33911 {
33912 /* Double-word spills from general registers to non-offsettable memory
33913 references (zero-extended addresses) require special handling. */
33919 {
33921 ? CODE_FOR_reload_noff_load
33923 /* Add the cost of moving address to a temporary. */
33927 }
33929 /* QImode spills from non-QI registers require
33930 intermediate register on 32bit targets. */
33935 {
33940 else
33946 /* Return Q_REGS if the operand is in memory. */
33949 }
33951 /* This condition handles corner case where an expression involving
33952 pointers gets vectorized. We're trying to use the address of a
33953 stack slot as a vector initializer.
33955 (set (reg:V2DI 74 [ vect_cst_.2 ])
33956 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33958 Eventually frame gets turned into sp+offset like this:
33960 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33961 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33962 (const_int 392 [0x188]))))
33964 That later gets turned into:
33966 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33967 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33968 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33970 We'll have the following reload recorded:
33972 Reload 0: reload_in (DI) =
33973 (plus:DI (reg/f:DI 7 sp)
33974 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33975 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33976 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33977 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33978 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33979 reload_reg_rtx: (reg:V2DI 22 xmm1)
33981 Which isn't going to work since SSE instructions can't handle scalar
33982 additions. Returning GENERAL_REGS forces the addition into integer
33983 register and reload can handle subsequent reloads without problems. */
33991 }
33993 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33995 static bool
33997 {
33999 {
34014 }
34017 }
34019 /* If we are copying between general and FP registers, we need a memory
34020 location. The same is true for SSE and MMX registers.
34022 To optimize register_move_cost performance, allow inline variant.
34024 The macro can't work reliably when one of the CLASSES is class containing
34025 registers from multiple units (SSE, MMX, integer). We avoid this by never
34026 combining those units in single alternative in the machine description.
34027 Ensure that this constraint holds to avoid unexpected surprises.
34029 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
34030 enforce these sanity checks. */
34035 {
34044 {
34047 }
34052 /* ??? This is a lie. We do have moves between mmx/general, and for
34053 mmx/sse2. But by saying we need secondary memory we discourage the
34054 register allocator from using the mmx registers unless needed. */
34059 {
34060 /* SSE1 doesn't have any direct moves from other classes. */
34064 /* If the target says that inter-unit moves are more expensive
34065 than moving through memory, then don't generate them. */
34070 /* Between SSE and general, we have moves no larger than word size. */
34073 }
34076 }
34078 bool
34081 {
34083 }
34085 /* Implement the TARGET_CLASS_MAX_NREGS hook.
34087 On the 80386, this is the size of MODE in words,
34088 except in the FP regs, where a single reg is always enough. */
34090 static unsigned char
34092 {
34094 {
34099 else
34101 }
34102 else
34103 {
34106 else
34108 }
34109 }
34111 /* Return true if the registers in CLASS cannot represent the change from
34112 modes FROM to TO. */
34114 bool
34117 {
34121 /* x87 registers can't do subreg at all, as all values are reformatted
34122 to extended precision. */
34127 {
34128 /* Vector registers do not support QI or HImode loads. If we don't
34129 disallow a change to these modes, reload will assume it's ok to
34130 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
34131 the vec_dupv4hi pattern. */
34135 /* Vector registers do not support subreg with nonzero offsets, which
34136 are otherwise valid for integer registers. Since we can't see
34137 whether we have a nonzero offset from here, prohibit all
34138 nonparadoxical subregs changing size. */
34141 }
34144 }
34146 /* Return the cost of moving data of mode M between a
34147 register and memory. A value of 2 is the default; this cost is
34148 relative to those in `REGISTER_MOVE_COST'.
34150 This function is used extensively by register_move_cost that is used to
34151 build tables at startup. Make it inline in this case.
34152 When IN is 2, return maximum of in and out move cost.
34154 If moving between registers and memory is more expensive than
34155 between two registers, you should define this macro to express the
34156 relative cost.
34158 Model also increased moving costs of QImode registers in non
34159 Q_REGS classes.
34160 */
34164 {
34167 {
34170 {
34182 }
34186 }
34188 {
34191 {
34203 }
34207 }
34209 {
34212 {
34221 }
34225 }
34227 {
34230 {
34236 else
34241 }
34242 else
34243 {
34248 else
34250 }
34257 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
34264 else
34268 }
34269 }
34271 static int
34274 {
34276 }
34279 /* Return the cost of moving data from a register in class CLASS1 to
34280 one in class CLASS2.
34282 It is not required that the cost always equal 2 when FROM is the same as TO;
34283 on some machines it is expensive to move between registers if they are not
34284 general registers. */
34286 static int
34288 reg_class_t class2_i)
34289 {
34293 /* In case we require secondary memory, compute cost of the store followed
34294 by load. In order to avoid bad register allocation choices, we need
34295 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
34298 {
34304 /* In case of copying from general_purpose_register we may emit multiple
34305 stores followed by single load causing memory size mismatch stall.
34306 Count this as arbitrarily high cost of 20. */
34311 /* In the case of FP/MMX moves, the registers actually overlap, and we
34312 have to switch modes in order to treat them differently. */
34318 }
34320 /* Moves between SSE/MMX and integer unit are expensive. */
34324 /* ??? By keeping returned value relatively high, we limit the number
34325 of moves between integer and MMX/SSE registers for all targets.
34326 Additionally, high value prevents problem with x86_modes_tieable_p(),
34327 where integer modes in MMX/SSE registers are not tieable
34328 because of missing QImode and HImode moves to, from or between
34329 MMX/SSE registers. */
34339 }
34341 /* Return TRUE if hard register REGNO can hold a value of machine-mode
34342 MODE. */
34344 bool
34346 {
34347 /* Flags and only flags can only hold CCmode values. */
34357 {
34358 /* We implement the move patterns for all vector modes into and
34359 out of SSE registers, even when no operation instructions
34360 are available. OImode move is available only when AVX is
34361 enabled. */
34368 }
34370 {
34371 /* We implement the move patterns for 3DNOW modes even in MMX mode,
34372 so if the register is available at all, then we can move data of
34373 the given mode into or out of it. */
34376 }
34379 {
34380 /* Take care for QImode values - they can be in non-QI regs,
34381 but then they do cause partial register stalls. */
34386 /* LRA checks if the hard register is OK for the given mode.
34387 QImode values can live in non-QI regs, so we allow all
34388 registers here. */
34392 }
34393 /* We handle both integer and floats in the general purpose registers. */
34400 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
34401 on to use that value in smaller contexts, this can easily force a
34402 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
34403 supporting DImode, allow it. */
34408 }
34410 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
34411 tieable integer mode. */
34413 static bool
34415 {
34417 {
34430 }
34431 }
34433 /* Return true if MODE1 is accessible in a register that can hold MODE2
34434 without copying. That is, all register classes that can hold MODE2
34435 can also hold MODE1. */
34437 bool
34439 {
34447 /* MODE2 being XFmode implies fp stack or general regs, which means we
34448 can tie any smaller floating point modes to it. Note that we do not
34449 tie this with TFmode. */
34453 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
34454 that we can tie it with SFmode. */
34458 /* If MODE2 is only appropriate for an SSE register, then tie with
34459 any other mode acceptable to SSE registers. */
34469 /* If MODE2 is appropriate for an MMX register, then tie
34470 with any other mode acceptable to MMX registers. */
34477 }
34479 /* Return the cost of moving between two registers of mode MODE. */
34481 static int
34483 {
34487 {
34518 }
34520 /* Return the cost of moving between two registers of mode MODE,
34521 assuming that the move will be in pieces of at most UNITS bytes. */
34523 }
34525 /* Compute a (partial) cost for rtx X. Return true if the complete
34526 cost has been computed, and false if subexpressions should be
34527 scanned. In either case, *TOTAL contains the cost result. */
34529 static bool
34532 {
34539 {
34543 {
34546 }
34558 && (!TARGET_64BIT
34563 else
34569 {
34572 }
34574 {
34584 }
34586 {
34589 {
34598 }
34599 }
34600 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34601 it'll probably end up. Add a penalty for size. */
34608 /* The zero extensions is often completely free on x86_64, so make
34609 it as cheap as possible. */
34615 else
34627 {
34630 {
34633 }
34636 {
34639 }
34640 }
34641 /* FALLTHRU */
34648 {
34649 /* ??? Should be SSE vector operation cost. */
34650 /* At least for published AMD latencies, this really is the same
34651 as the latency for a simple fpu operation like fabs. */
34652 /* V*QImode is emulated with 1-11 insns. */
34654 {
34657 {
34658 /* For XOP we use vpshab, which requires a broadcast of the
34659 value to the variable shift insn. For constants this
34660 means a V16Q const in mem; even when we can perform the
34661 shift with one insn set the cost to prefer paddb. */
34663 {
34668 }
34670 }
34674 }
34675 else
34677 }
34679 {
34681 {
34684 else
34686 }
34687 else
34688 {
34691 else
34693 }
34694 }
34695 else
34696 {
34701 {
34702 /* Return the cost after shift-and truncation. */
34705 }
34706 else
34708 }
34712 {
34713 rtx sub;
34718 /* ??? SSE scalar/vector cost should be used here. */
34719 /* ??? Bald assumption that fma has the same cost as fmul. */
34723 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34734 }
34738 {
34739 /* ??? SSE scalar cost should be used here. */
34742 }
34744 {
34747 }
34749 {
34750 /* ??? SSE vector cost should be used here. */
34753 }
34755 {
34756 /* V*QImode is emulated with 7-13 insns. */
34758 {
34765 }
34766 /* V*DImode is emulated with 5-8 insns. */
34768 {
34771 else
34773 }
34774 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34775 insns, including two PMULUDQ. */
34778 else
34781 }
34782 else
34783 {
34788 {
34791 nbits++;
34792 }
34793 else
34794 /* This is arbitrary. */
34797 /* Compute costs correctly for widening multiplication. */
34801 {
34808 {
34812 else
34814 }
34818 }
34826 }
34833 /* ??? SSE cost should be used here. */
34838 /* ??? SSE vector cost should be used here. */
34840 else
34847 {
34852 {
34855 {
34863 }
34864 }
34867 {
34870 {
34876 }
34877 }
34879 {
34887 }
34888 }
34889 /* FALLTHRU */
34893 {
34894 /* ??? SSE cost should be used here. */
34897 }
34899 {
34902 }
34904 {
34905 /* ??? SSE vector cost should be used here. */
34908 }
34909 /* FALLTHRU */
34916 {
34923 }
34924 /* FALLTHRU */
34928 {
34929 /* ??? SSE cost should be used here. */
34932 }
34934 {
34937 }
34939 {
34940 /* ??? SSE vector cost should be used here. */
34943 }
34944 /* FALLTHRU */
34948 {
34949 /* ??? Should be SSE vector operation cost. */
34950 /* At least for published AMD latencies, this really is the same
34951 as the latency for a simple fpu operation like fabs. */
34953 }
34956 else
34965 {
34966 /* This kind of construct is implemented using test[bwl].
34967 Treat it as if we had an AND. */
34972 }
34982 /* ??? SSE cost should be used here. */
34987 /* ??? SSE vector cost should be used here. */
34993 /* ??? SSE cost should be used here. */
34998 /* ??? SSE vector cost should be used here. */
35011 /* ??? Assume all of these vector manipulation patterns are
35012 recognizable. In which case they all pretty much have the
35013 same cost. */
35019 }
35020 }
35022 #if TARGET_MACHO
35026 /* Given a symbol name and its associated stub, write out the
35027 definition of the stub. */
35029 void
35031 {
35036 /* For 64-bit we shouldn't get here. */
35039 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
35056 else
35063 {
35065 }
35067 {
35068 /* PIC stub. */
35069 /* 25-byte PIC stub using "CALL get_pc_thunk". */
35075 }
35076 else
35079 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
35080 it needs no stub-binding-helper. */
35087 {
35090 }
35091 else
35096 /* N.B. Keep the correspondence of these
35097 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
35098 old-pic/new-pic/non-pic stubs; altering this will break
35099 compatibility with existing dylibs. */
35101 {
35102 /* 25-byte PIC stub using "CALL get_pc_thunk". */
35104 }
35105 else
35106 /* 16-byte -mdynamic-no-pic stub. */
35112 }
35115 /* Order the registers for register allocator. */
35117 void
35119 {
35123 /* First allocate the local general purpose registers. */
35128 /* Global general purpose registers. */
35133 /* x87 registers come first in case we are doing FP math
35134 using them. */
35139 /* SSE registers. */
35145 /* x87 registers. */
35153 /* Initialize the rest of array as we do not allocate some registers
35154 at all. */
35157 }
35159 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
35160 in struct attribute_spec handler. */
35161 static tree
35163 tree args,
35166 {
35171 {
35173 name);
35176 }
35178 {
35180 name);
35183 }
35185 {
35186 tree cst;
35190 {
35193 name);
35195 }
35198 {
35201 name);
35203 }
35206 }
35209 }
35211 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
35212 struct attribute_spec.handler. */
35213 static tree
35215 tree args ATTRIBUTE_UNUSED,
35217 {
35222 {
35224 name);
35227 }
35229 /* Can combine regparm with all attributes but fastcall. */
35231 {
35233 {
35235 }
35238 }
35240 {
35242 {
35244 }
35247 }
35250 }
35252 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
35253 struct attribute_spec.handler. */
35254 static tree
35256 tree args ATTRIBUTE_UNUSED,
35258 {
35261 {
35264 }
35265 else
35269 {
35271 name);
35273 }
35279 {
35281 name);
35283 }
35286 }
35288 static tree
35290 tree args ATTRIBUTE_UNUSED,
35292 {
35294 {
35296 name);
35298 }
35300 }
35302 static bool
35304 {
35308 }
35310 /* Returns an expression indicating where the this parameter is
35311 located on entry to the FUNCTION. */
35313 static rtx
35315 {
35321 {
35326 else
35329 }
35334 {
35341 {
35346 }
35347 else
35348 {
35351 {
35357 }
35358 }
35360 }
35364 }
35366 /* Determine whether x86_output_mi_thunk can succeed. */
35368 static bool
35370 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
35372 {
35373 /* 64-bit can handle anything. */
35377 /* For 32-bit, everything's fine if we have one free register. */
35381 /* Need a free register for vcall_offset. */
35385 /* Need a free register for GOT references. */
35389 /* Otherwise ok. */
35391 }
35393 /* Output the assembler code for a thunk function. THUNK_DECL is the
35394 declaration for the thunk function itself, FUNCTION is the decl for
35395 the target function. DELTA is an immediate constant offset to be
35396 added to THIS. If VCALL_OFFSET is nonzero, the word at
35397 *(*this + vcall_offset) should be added to THIS. */
35399 static void
35403 {
35410 else
35411 {
35417 else
35419 }
35423 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
35424 pull it in now and let DELTA benefit. */
35428 {
35429 /* Put the this parameter into %eax. */
35432 }
35433 else
35436 /* Adjust the this parameter by a fixed constant. */
35438 {
35443 {
35445 {
35449 }
35450 }
35453 }
35455 /* Adjust the this parameter by a value stored in the vtable. */
35457 {
35467 /* Adjust the this parameter. */
35471 {
35475 }
35482 vcall_mem));
35483 else
35485 }
35487 /* If necessary, drop THIS back to its stack slot. */
35493 {
35496 ;
35497 else
35498 {
35502 }
35503 }
35504 else
35505 {
35507 ;
35508 #if TARGET_MACHO
35510 {
35513 }
35515 else
35516 {
35523 }
35524 }
35526 /* Our sibling call patterns do not allow memories, because we have no
35527 predicate that can distinguish between frame and non-frame memory.
35528 For our purposes here, we can get away with (ab)using a jump pattern,
35529 because we're going to do no optimization. */
35532 else
35533 {
35539 {
35545 }
35551 }
35554 /* Emit just enough of rest_of_compilation to get the insns emitted.
35555 Note that use_thunk calls assemble_start_function et al. */
35561 }
35563 static void
35565 {
35567 #if TARGET_MACHO
35569 #endif
35576 }
35578 int
35580 {
35592 }
35594 /* Output assembler code to FILE to increment profiler label # LABELNO
35595 for profiling a function entry. */
35596 void
35598 {
35603 {
35604 #ifndef NO_PROFILE_COUNTERS
35606 #endif
35610 else
35612 }
35614 {
35615 #ifndef NO_PROFILE_COUNTERS
35618 #endif
35620 }
35621 else
35622 {
35623 #ifndef NO_PROFILE_COUNTERS
35626 #endif
35628 }
35629 }
35631 /* We don't have exact information about the insn sizes, but we may assume
35632 quite safely that we are informed about all 1 byte insns and memory
35633 address sizes. This is enough to eliminate unnecessary padding in
35634 99% of cases. */
35636 static int
35638 {
35644 /* Discard alignments we've emit and jump instructions. */
35649 /* Important case - calls are always 5 bytes.
35650 It is common to have many calls in the row. */
35659 /* For normal instructions we rely on get_attr_length being exact,
35660 with a few exceptions. */
35662 {
35666 {
35676 /* Otherwise trust get_attr_length. */
35678 }
35683 }
35686 else
35688 }
35690 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35692 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35693 window. */
35695 static void
35697 {
35702 /* Look for all minimal intervals of instructions containing 4 jumps.
35703 The intervals are bounded by START and INSN. NBYTES is the total
35704 size of instructions in the interval including INSN and not including
35705 START. When the NBYTES is smaller than 16 bytes, it is possible
35706 that the end of START and INSN ends up in the same 16byte page.
35708 The smallest offset in the page INSN can start is the case where START
35709 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35710 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35711 */
35713 {
35717 {
35723 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35724 already in the current 16 byte page, because otherwise
35725 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35726 bytes to reach 16 byte boundary. */
35734 {
35736 {
35740 else
35743 }
35744 }
35746 }
35754 njumps++;
35755 else
35759 {
35763 else
35766 }
35773 {
35780 }
35781 }
35782 }
35783 #endif
35785 /* AMD Athlon works faster
35786 when RET is not destination of conditional jump or directly preceded
35787 by other jump instruction. We avoid the penalty by inserting NOP just
35788 before the RET instructions in such cases. */
35789 static void
35791 {
35792 edge e;
35793 edge_iterator ei;
35796 {
35799 rtx prev;
35809 {
35810 edge e;
35811 edge_iterator ei;
35816 {
35819 }
35820 }
35822 {
35828 /* Empty functions get branch mispredict even when
35829 the jump destination is not visible to us. */
35832 }
35834 {
35837 }
35838 }
35839 }
35841 /* Count the minimum number of instructions in BB. Return 4 if the
35842 number of instructions >= 4. */
35844 static int
35846 {
35847 rtx insn;
35850 /* Count number of instructions in this block. Return 4 if the number
35851 of instructions >= 4. */
35853 {
35854 /* Only happen in exit blocks. */
35862 {
35863 insn_count++;
35866 }
35867 }
35870 }
35873 /* Count the minimum number of instructions in code path in BB.
35874 Return 4 if the number of instructions >= 4. */
35876 static int
35878 {
35879 edge e;
35880 edge_iterator ei;
35883 /* Only bother counting instructions along paths with no
35884 more than 2 basic blocks between entry and exit. Given
35885 that BB has an edge to exit, determine if a predecessor
35886 of BB has an edge from entry. If so, compute the number
35887 of instructions in the predecessor block. If there
35888 happen to be multiple such blocks, compute the minimum. */
35891 {
35892 edge prev_e;
35893 edge_iterator prev_ei;
35896 {
35899 }
35901 {
35903 {
35908 }
35909 }
35910 }
35916 }
35918 /* Pad short function to 4 instructions. */
35920 static void
35922 {
35923 edge e;
35924 edge_iterator ei;
35927 {
35930 {
35933 /* Pad short function. */
35935 {
35938 /* Find epilogue. */
35947 /* Two NOPs count as one instruction. */
35950 }
35951 }
35952 }
35953 }
35955 /* Fix up a Windows system unwinder issue. If an EH region falls through into
35956 the epilogue, the Windows system unwinder will apply epilogue logic and
35957 produce incorrect offsets. This can be avoided by adding a nop between
35958 the last insn that can throw and the first insn of the epilogue. */
35960 static void
35962 {
35963 edge e;
35964 edge_iterator ei;
35967 {
35970 /* Find the beginning of the epilogue. */
35977 /* We only care about preceding insns that can throw. */
35982 /* Do not separate calls from their debug information. */
35988 else
35992 }
35993 }
35995 /* Implement machine specific optimizations. We implement padding of returns
35996 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35997 static void
35999 {
36000 /* We are freeing block_for_insn in the toplev to keep compatibility
36001 with old MDEP_REORGS that are not CFG based. Recompute it now. */
36008 {
36013 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
36016 #endif
36017 }
36018 }
36020 /* Return nonzero when QImode register that must be represented via REX prefix
36021 is used. */
36022 bool
36024 {
36032 }
36034 /* Return nonzero when P points to register encoded via REX prefix.
36035 Called via for_each_rtx. */
36036 static int
36038 {
36044 }
36046 /* Return true when INSN mentions register that must be encoded using REX
36047 prefix. */
36048 bool
36050 {
36053 }
36055 /* If profitable, negate (without causing overflow) integer constant
36056 of mode MODE at location LOC. Return true in this case. */
36057 bool
36059 {
36060 HOST_WIDE_INT val;
36066 {
36068 /* DImode x86_64 constants must fit in 32 bits. */
36081 }
36083 /* Avoid overflows. */
36089 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
36090 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
36093 {
36096 }
36099 }
36101 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
36102 optabs would emit if we didn't have TFmode patterns. */
36104 void
36106 {
36140 }
36141 \f
36142 /* AVX2 does support 32-byte integer vector operations,
36143 thus the longest vector we are faced with is V32QImode. */
36144 #define MAX_VECT_LEN 32
36146 struct expand_vec_perm_d
36147 {
36154 };
36160 /* Get a vector mode of the same size as the original but with elements
36161 twice as wide. This is only guaranteed to apply to integral vectors. */
36165 {
36166 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
36171 }
36173 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36174 with all elements equal to VAR. Return true if successful. */
36176 static bool
36179 {
36183 {
36188 /* FALLTHRU */
36198 {
36201 /* First attempt to recognize VAL as-is. */
36205 {
36206 rtx seq;
36207 /* If that fails, force VAL into a register. */
36218 }
36219 }
36226 {
36227 rtx x;
36234 }
36244 {
36248 permute:
36256 /* Extend to SImode using a paradoxical SUBREG. */
36260 /* Insert the SImode value as low element of a V4SImode vector. */
36268 }
36276 widen:
36277 /* Replicate the value once into the next wider mode and recurse. */
36278 {
36280 rtx x;
36296 }
36300 {
36309 }
36314 }
36315 }
36317 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36318 whose ONE_VAR element is VAR, and other elements are zero. Return true
36319 if successful. */
36321 static bool
36324 {
36326 rtx new_target;
36331 {
36333 /* For SSE4.1, we normally use vector set. But if the second
36334 element is zero and inter-unit moves are OK, we use movq
36335 instead. */
36337 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
36359 /* Use ix86_expand_vector_set in 64bit mode only. */
36364 }
36367 {
36372 }
36375 {
36380 /* FALLTHRU */
36395 else
36402 {
36403 /* We need to shuffle the value to the correct position, so
36404 create a new pseudo to store the intermediate result. */
36406 /* With SSE2, we can use the integer shuffle insns. */
36408 {
36410 const1_rtx,
36417 }
36419 /* Otherwise convert the intermediate result to V4SFmode and
36420 use the SSE1 shuffle instructions. */
36422 {
36425 }
36426 else
36430 const1_rtx,
36439 }
36454 widen:
36458 /* Zero extend the variable element to SImode and recurse. */
36471 }
36472 }
36474 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36475 consisting of the values in VALS. It is known that all elements
36476 except ONE_VAR are constants. Return true if successful. */
36478 static bool
36481 {
36491 {
36496 /* For the two element vectors, it's just as easy to use
36497 the general case. */
36501 /* Use ix86_expand_vector_set in 64bit mode only. */
36523 widen:
36524 /* There's no way to set one QImode entry easily. Combine
36525 the variable value with its adjacent constant value, and
36526 promote to an HImode set. */
36529 {
36534 }
36535 else
36536 {
36539 }
36553 }
36558 }
36560 /* A subroutine of ix86_expand_vector_init_general. Use vector
36561 concatenate to handle the most general case: all values variable,
36562 and none identical. */
36564 static void
36567 {
36570 rtvec v;
36574 {
36577 {
36610 }
36623 {
36638 }
36643 {
36654 }
36657 half:
36658 /* FIXME: We process inputs backward to help RA. PR 36222. */
36662 {
36667 }
36671 {
36674 {
36678 }
36681 }
36682 else
36688 }
36689 }
36691 /* A subroutine of ix86_expand_vector_init_general. Use vector
36692 interleave to handle the most general case: all values variable,
36693 and none identical. */
36695 static void
36698 {
36707 {
36728 }
36731 {
36732 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36736 /* Insert the SImode value as low element of V4SImode vector. */
36740 op0),
36742 const1_rtx);
36745 /* Cast the V4SImode vector back to a vector in orignal mode. */
36749 /* Load even elements into the second position. */
36753 const1_rtx));
36755 /* Cast vector to FIRST_IMODE vector. */
36758 }
36760 /* Interleave low FIRST_IMODE vectors. */
36762 {
36766 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36769 }
36771 /* Interleave low SECOND_IMODE vectors. */
36773 {
36776 {
36781 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36782 vector. */
36785 }
36788 /* FALLTHRU */
36795 /* Cast the SECOND_IMODE vector back to a vector on original
36796 mode. */
36803 }
36804 }
36806 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36807 all values variable, and none identical. */
36809 static void
36812 {
36818 {
36823 /* FALLTHRU */
36847 half:
36864 /* FALLTHRU */
36870 /* Don't use ix86_expand_vector_init_interleave if we can't
36871 move from GPR to SSE register directly. */
36887 }
36889 {
36901 {
36905 {
36911 else
36912 {
36917 }
36918 }
36921 }
36926 {
36932 }
36934 {
36940 }
36941 else
36943 }
36944 }
36946 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36947 instructions unless MMX_OK is true. */
36949 void
36951 {
36958 rtx x;
36961 {
36971 }
36973 /* Constants are best loaded from the constant pool. */
36975 {
36978 }
36980 /* If all values are identical, broadcast the value. */
36986 /* Values where only one field is non-constant are best loaded from
36987 the pool and overwritten via move later. */
36989 {
36993 one_var))
36998 }
37001 }
37003 void
37005 {
37010 rtx tmp;
37012 = {
37019 };
37021 = {
37028 };
37032 {
37036 {
37041 else
37045 }
37057 else
37063 {
37066 /* For the two element vectors, we implement a VEC_CONCAT with
37067 the extraction of the other element. */
37074 else
37079 }
37088 {
37094 /* tmp = target = A B C D */
37096 /* target = A A B B */
37098 /* target = X A B B */
37100 /* target = A X C D */
37107 /* tmp = target = A B C D */
37109 /* tmp = X B C D */
37111 /* target = A B X D */
37118 /* tmp = target = A B C D */
37120 /* tmp = X B C D */
37122 /* target = A B X D */
37130 }
37138 /* Element 0 handled by vec_merge below. */
37140 {
37143 }
37146 {
37147 /* With SSE2, use integer shuffles to swap element 0 and ELT,
37148 store into element 0, then shuffle them back. */
37165 }
37166 else
37167 {
37168 /* For SSE1, we have to reuse the V4SF code. */
37171 }
37224 half:
37225 /* Compute offset. */
37231 /* Extract the half. */
37235 /* Put val in tmp at elt. */
37238 /* Put it back. */
37244 }
37247 {
37251 }
37252 else
37253 {
37262 }
37263 }
37265 void
37267 {
37271 rtx tmp;
37274 {
37279 /* FALLTHRU */
37292 {
37312 }
37324 {
37326 {
37346 }
37350 }
37351 else
37352 {
37353 /* For SSE1, we have to reuse the V4SF code. */
37357 }
37373 {
37377 else
37381 }
37386 {
37390 else
37394 }
37399 {
37403 else
37407 }
37412 {
37416 else
37420 }
37425 {
37429 else
37433 }
37438 {
37442 else
37446 }
37450 /* ??? Could extract the appropriate HImode element and shift. */
37453 }
37456 {
37460 /* Let the rtl optimizers know about the zero extension performed. */
37462 {
37465 }
37468 }
37469 else
37470 {
37477 }
37478 }
37480 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
37481 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
37482 The upper bits of DEST are undefined, though they shouldn't cause
37483 exceptions (some bits from src or all zeros are ok). */
37485 static void
37487 {
37488 rtx tem;
37490 {
37494 else
37512 else
37519 else
37530 const1_rtx);
37531 else
37538 }
37540 }
37542 /* Expand a vector reduction. FN is the binary pattern to reduce;
37543 DEST is the destination; IN is the input vector. */
37545 void
37547 {
37552 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
37556 {
37559 }
37564 {
37569 else
37573 }
37574 }
37575 \f
37576 /* Target hook for scalar_mode_supported_p. */
37577 static bool
37579 {
37584 else
37586 }
37588 /* Implements target hook vector_mode_supported_p. */
37589 static bool
37591 {
37603 }
37605 /* Target hook for c_mode_for_suffix. */
37606 static enum machine_mode
37608 {
37615 }
37617 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37619 We do this in the new i386 backend to maintain source compatibility
37620 with the old cc0-based compiler. */
37622 static tree
37624 tree inputs ATTRIBUTE_UNUSED,
37625 tree clobbers)
37626 {
37628 clobbers);
37630 clobbers);
37632 }
37634 /* Implements target vector targetm.asm.encode_section_info. */
37636 static void ATTRIBUTE_UNUSED
37638 {
37645 }
37647 /* Worker function for REVERSE_CONDITION. */
37649 enum rtx_code
37651 {
37655 }
37657 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37658 to OPERANDS[0]. */
37662 {
37664 {
37667 {
37671 }
37675 }
37677 {
37681 else
37682 {
37683 /* There is no non-popping store to memory for XFmode.
37684 So if we need one, follow the store with a load. */
37687 else
37689 }
37690 }
37691 else
37693 }
37695 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37696 FP status register is set. */
37698 void
37700 {
37702 rtx temp;
37707 {
37712 }
37713 else
37714 {
37719 }
37723 pc_rtx);
37728 }
37730 /* Output code to perform a log1p XFmode calculation. */
37733 {
37739 rtx test;
37745 XFmode));
37759 }
37761 /* Emit code for round calculation. */
37763 {
37770 rtx insn;
37775 {
37787 }
37790 {
37811 }
37819 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37821 /* scratch = fxam(op1) */
37824 UNSPEC_FXAM)));
37825 /* e1 = fabs(op1) */
37828 /* e2 = e1 + 0.5 */
37833 /* res = floor(e2) */
37835 {
37840 }
37841 else
37845 {
37848 {
37855 UNSPEC_TRUNC_NOOP)));
37856 }
37872 }
37874 /* flags = signbit(a) */
37877 /* if (flags) then res = -res */
37881 pc_rtx);
37892 }
37894 /* Output code to perform a Newton-Rhapson approximation of a single precision
37895 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37898 {
37906 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37910 /* x0 = rcp(b) estimate */
37913 UNSPEC_RCP)));
37914 /* e0 = x0 * b */
37918 /* e0 = x0 * e0 */
37922 /* e1 = x0 + x0 */
37926 /* x1 = e1 - e0 */
37930 /* res = a * x1 */
37933 }
37935 /* Output code to perform a Newton-Rhapson approximation of a
37936 single precision floating point [reciprocal] square root. */
37940 {
37942 REAL_VALUE_TYPE r;
37957 {
37960 }
37962 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37963 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37967 /* x0 = rsqrt(a) estimate */
37970 UNSPEC_RSQRT)));
37972 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37974 {
37986 }
37988 /* e0 = x0 * a */
37991 /* e1 = e0 * x0 */
37995 /* e2 = e1 - 3. */
38002 /* e3 = -.5 * x0 */
38005 else
38006 /* e3 = -.5 * e0 */
38009 /* ret = e2 * e3 */
38012 }
38014 #ifdef TARGET_SOLARIS
38015 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
38017 static void
38019 tree decl)
38020 {
38021 /* With Binutils 2.15, the "@unwind" marker must be specified on
38022 every occurrence of the ".eh_frame" section, not just the first
38023 one. */
38026 {
38030 }
38032 #ifndef USE_GAS
38034 {
38037 }
38038 #endif
38041 }
38044 /* Return the mangling of TYPE if it is an extended fundamental type. */
38048 {
38056 {
38058 /* __float128 is "g". */
38061 /* "long double" or __float80 is "e". */
38065 }
38066 }
38068 /* For 32-bit code we can save PIC register setup by using
38069 __stack_chk_fail_local hidden function instead of calling
38070 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
38071 register, so it is better to call __stack_chk_fail directly. */
38073 static tree ATTRIBUTE_UNUSED
38075 {
38076 return TARGET_64BIT
38079 }
38081 /* Select a format to encode pointers in exception handling data. CODE
38082 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
38083 true if the symbol may be affected by dynamic relocations.
38085 ??? All x86 object file formats are capable of representing this.
38086 After all, the relocation needed is the same as for the call insn.
38087 Whether or not a particular assembler allows us to enter such, I
38088 guess we'll have to see. */
38089 int
38091 {
38093 {
38100 }
38105 }
38106 \f
38107 /* Expand copysign from SIGN to the positive value ABS_VALUE
38108 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
38109 the sign-bit. */
38110 static void
38112 {
38116 {
38123 else
38128 {
38129 /* We need to generate a scalar mode mask in this case. */
38134 }
38135 }
38136 else
38142 }
38144 /* Expand fabs (OP0) and return a new rtx that holds the result. The
38145 mask for masking out the sign-bit is stored in *SMASK, if that is
38146 non-null. */
38147 static rtx
38149 {
38158 else
38162 {
38163 /* We need to generate a scalar mode mask in this case. */
38168 }
38176 }
38178 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
38179 swapping the operands if SWAP_OPERANDS is true. The expanded
38180 code is a forward jump to a newly created label in case the
38181 comparison is true. The generated label rtx is returned. */
38182 static rtx
38185 {
38189 {
38193 }
38206 }
38208 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
38209 using comparison code CODE. Operands are swapped for the comparison if
38210 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
38211 static rtx
38214 {
38220 {
38224 }
38231 }
38233 /* Generate and return a rtx of mode MODE for 2**n where n is the number
38234 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
38235 static rtx
38237 {
38238 REAL_VALUE_TYPE TWO52r;
38239 rtx TWO52;
38246 }
38248 /* Expand SSE sequence for computing lround from OP1 storing
38249 into OP0. */
38250 void
38252 {
38253 /* C code for the stuff we're doing below:
38254 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
38255 return (long)tmp;
38256 */
38260 rtx adj;
38262 /* load nextafter (0.5, 0.0) */
38267 /* adj = copysign (0.5, op1) */
38271 /* adj = op1 + adj */
38274 /* op0 = (imode)adj */
38276 }
38278 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
38279 into OPERAND0. */
38280 void
38282 {
38283 /* C code for the stuff we're doing below (for do_floor):
38284 xi = (long)op1;
38285 xi -= (double)xi > op1 ? 1 : 0;
38286 return xi;
38287 */
38292 /* reg = (long)op1 */
38296 /* freg = (double)reg */
38300 /* ireg = (freg > op1) ? ireg - 1 : ireg */
38311 }
38313 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
38314 result in OPERAND0. */
38315 void
38317 {
38318 /* C code for the stuff we're doing below:
38319 xa = fabs (operand1);
38320 if (!isless (xa, 2**52))
38321 return operand1;
38322 xa = xa + 2**52 - 2**52;
38323 return copysign (xa, operand1);
38324 */
38331 /* xa = abs (operand1) */
38334 /* if (!isless (xa, TWO52)) goto label; */
38347 }
38349 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
38350 into OPERAND0. */
38351 void
38353 {
38354 /* C code for the stuff we expand below.
38355 double xa = fabs (x), x2;
38356 if (!isless (xa, TWO52))
38357 return x;
38358 xa = xa + TWO52 - TWO52;
38359 x2 = copysign (xa, x);
38360 Compensate. Floor:
38361 if (x2 > x)
38362 x2 -= 1;
38363 Compensate. Ceil:
38364 if (x2 < x)
38365 x2 -= -1;
38366 return x2;
38367 */
38373 /* Temporary for holding the result, initialized to the input
38374 operand to ease control flow. */
38378 /* xa = abs (operand1) */
38381 /* if (!isless (xa, TWO52)) goto label; */
38384 /* xa = xa + TWO52 - TWO52; */
38388 /* xa = copysign (xa, operand1) */
38391 /* generate 1.0 or -1.0 */
38396 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38400 /* We always need to subtract here to preserve signed zero. */
38409 }
38411 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
38412 into OPERAND0. */
38413 void
38415 {
38416 /* C code for the stuff we expand below.
38417 double xa = fabs (x), x2;
38418 if (!isless (xa, TWO52))
38419 return x;
38420 x2 = (double)(long)x;
38421 Compensate. Floor:
38422 if (x2 > x)
38423 x2 -= 1;
38424 Compensate. Ceil:
38425 if (x2 < x)
38426 x2 += 1;
38427 if (HONOR_SIGNED_ZEROS (mode))
38428 return copysign (x2, x);
38429 return x2;
38430 */
38436 /* Temporary for holding the result, initialized to the input
38437 operand to ease control flow. */
38441 /* xa = abs (operand1) */
38444 /* if (!isless (xa, TWO52)) goto label; */
38447 /* xa = (double)(long)x */
38452 /* generate 1.0 */
38455 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38470 }
38472 /* Expand SSE sequence for computing round from OPERAND1 storing
38473 into OPERAND0. Sequence that works without relying on DImode truncation
38474 via cvttsd2siq that is only available on 64bit targets. */
38475 void
38477 {
38478 /* C code for the stuff we expand below.
38479 double xa = fabs (x), xa2, x2;
38480 if (!isless (xa, TWO52))
38481 return x;
38482 Using the absolute value and copying back sign makes
38483 -0.0 -> -0.0 correct.
38484 xa2 = xa + TWO52 - TWO52;
38485 Compensate.
38486 dxa = xa2 - xa;
38487 if (dxa <= -0.5)
38488 xa2 += 1;
38489 else if (dxa > 0.5)
38490 xa2 -= 1;
38491 x2 = copysign (xa2, x);
38492 return x2;
38493 */
38499 /* Temporary for holding the result, initialized to the input
38500 operand to ease control flow. */
38504 /* xa = abs (operand1) */
38507 /* if (!isless (xa, TWO52)) goto label; */
38510 /* xa2 = xa + TWO52 - TWO52; */
38514 /* dxa = xa2 - xa; */
38517 /* generate 0.5, 1.0 and -0.5 */
38523 /* Compensate. */
38525 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
38530 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
38536 /* res = copysign (xa2, operand1) */
38543 }
38545 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38546 into OPERAND0. */
38547 void
38549 {
38550 /* C code for SSE variant we expand below.
38551 double xa = fabs (x), x2;
38552 if (!isless (xa, TWO52))
38553 return x;
38554 x2 = (double)(long)x;
38555 if (HONOR_SIGNED_ZEROS (mode))
38556 return copysign (x2, x);
38557 return x2;
38558 */
38564 /* Temporary for holding the result, initialized to the input
38565 operand to ease control flow. */
38569 /* xa = abs (operand1) */
38572 /* if (!isless (xa, TWO52)) goto label; */
38575 /* x = (double)(long)x */
38587 }
38589 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38590 into OPERAND0. */
38591 void
38593 {
38597 /* C code for SSE variant we expand below.
38598 double xa = fabs (x), x2;
38599 if (!isless (xa, TWO52))
38600 return x;
38601 xa2 = xa + TWO52 - TWO52;
38602 Compensate:
38603 if (xa2 > xa)
38604 xa2 -= 1.0;
38605 x2 = copysign (xa2, x);
38606 return x2;
38607 */
38611 /* Temporary for holding the result, initialized to the input
38612 operand to ease control flow. */
38616 /* xa = abs (operand1) */
38619 /* if (!isless (xa, TWO52)) goto label; */
38622 /* res = xa + TWO52 - TWO52; */
38627 /* generate 1.0 */
38630 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38638 /* res = copysign (res, operand1) */
38645 }
38647 /* Expand SSE sequence for computing round from OPERAND1 storing
38648 into OPERAND0. */
38649 void
38651 {
38652 /* C code for the stuff we're doing below:
38653 double xa = fabs (x);
38654 if (!isless (xa, TWO52))
38655 return x;
38656 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38657 return copysign (xa, x);
38658 */
38664 /* Temporary for holding the result, initialized to the input
38665 operand to ease control flow. */
38673 /* load nextafter (0.5, 0.0) */
38678 /* xa = xa + 0.5 */
38682 /* xa = (double)(int64_t)xa */
38687 /* res = copysign (xa, operand1) */
38694 }
38696 /* Expand SSE sequence for computing round
38697 from OP1 storing into OP0 using sse4 round insn. */
38698 void
38700 {
38709 {
38720 }
38722 /* round (a) = trunc (a + copysign (0.5, a)) */
38724 /* load nextafter (0.5, 0.0) */
38730 /* e1 = copysign (0.5, op1) */
38734 /* e2 = op1 + e1 */
38737 /* res = trunc (e2) */
38742 }
38743 \f
38745 /* Table of valid machine attributes. */
38747 {
38748 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38749 affects_type_identity } */
38750 /* Stdcall attribute says callee is responsible for popping arguments
38751 if they are not variable. */
38754 /* Fastcall attribute says callee is responsible for popping arguments
38755 if they are not variable. */
38758 /* Thiscall attribute says callee is responsible for popping arguments
38759 if they are not variable. */
38762 /* Cdecl attribute says the callee is a normal C declaration */
38765 /* Regparm attribute specifies how many integer arguments are to be
38766 passed in registers. */
38769 /* Sseregparm attribute says we are using x86_64 calling conventions
38770 for FP arguments. */
38773 /* The transactional memory builtins are implicitly regparm or fastcall
38774 depending on the ABI. Override the generic do-nothing attribute that
38775 these builtins were declared with. */
38778 /* force_align_arg_pointer says this function realigns the stack at entry. */
38781 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38786 #endif
38791 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38792 SUBTARGET_ATTRIBUTE_TABLE,
38793 #endif
38794 /* ms_abi and sysv_abi calling convention function attributes. */
38801 /* End element. */
38803 };
38805 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38806 static int
38808 tree vectype,
38810 {
38814 {
38859 }
38860 }
38862 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38863 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38864 insn every time. */
38868 /* Initialize vselect_insn. */
38870 static void
38872 {
38874 rtx x;
38885 }
38887 /* Construct (set target (vec_select op0 (parallel perm))) and
38888 return true if that's a valid instruction in the active ISA. */
38890 static bool
38893 {
38919 }
38921 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38923 static bool
38927 {
38929 rtx x;
38944 }
38946 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38947 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38949 static bool
38951 {
38960 ;
38962 ;
38964 ;
38965 else
38968 /* This is a blend, not a permute. Elements must stay in their
38969 respective lanes. */
38971 {
38975 }
38980 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38981 decision should be extracted elsewhere, so that we only try that
38982 sequence once all budget==3 options have been tried. */
38989 {
39013 /* See if bytes move in pairs so we can use pblendw with
39014 an immediate argument, rather than pblendvb with a vector
39015 argument. */
39018 {
39019 use_pblendvb:
39023 finish_pblendvb:
39029 else
39032 }
39037 /* FALLTHRU */
39039 do_subreg:
39046 /* See if bytes move in pairs. If not, vpblendvb must be used. */
39050 /* See if bytes move in quadruplets. If yes, vpblendd
39051 with immediate can be used. */
39056 {
39057 /* See if bytes move the same in both lanes. If yes,
39058 vpblendw with immediate can be used. */
39063 /* Use vpblendw. */
39068 }
39070 /* Use vpblendd. */
39077 /* See if words move in pairs. If yes, vpblendd can be used. */
39082 {
39083 /* See if words move the same in both lanes. If not,
39084 vpblendvb must be used. */
39087 {
39088 /* Use vpblendvb. */
39098 }
39100 /* Use vpblendw. */
39104 }
39106 /* Use vpblendd. */
39113 /* Use vpblendd. */
39121 }
39123 /* This matches five different patterns with the different modes. */
39129 }
39131 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39132 in terms of the variable form of vpermilps.
39134 Note that we will have already failed the immediate input vpermilps,
39135 which requires that the high and low part shuffle be identical; the
39136 variable form doesn't require that. */
39138 static bool
39140 {
39147 /* We can only permute within the 128-bit lane. */
39149 {
39153 }
39159 {
39162 /* Within each 128-bit lane, the elements of op0 are numbered
39163 from 0 and the elements of op1 are numbered from 4. */
39170 }
39177 }
39179 /* Return true if permutation D can be performed as VMODE permutation
39180 instead. */
39182 static bool
39184 {
39199 else
39205 }
39207 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39208 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
39210 static bool
39212 {
39221 {
39223 {
39226 {
39230 /* Use vperm2i128 insn. The pattern uses
39231 V4DImode instead of V2TImode. */
39240 }
39242 }
39243 }
39244 else
39245 {
39247 {
39250 }
39252 {
39256 /* V4DImode should be already handled through
39257 expand_vselect by vpermq instruction. */
39264 {
39265 /* First see if vpermq can be used for
39266 V8SImode/V16HImode/V32QImode. */
39268 {
39276 }
39278 /* Next see if vpermd can be used. */
39281 }
39282 /* Or if vpermps can be used. */
39287 {
39288 /* vpshufb only works intra lanes, it is not
39289 possible to shuffle bytes in between the lanes. */
39293 }
39294 }
39295 else
39297 }
39305 else
39306 {
39312 else
39316 {
39320 }
39321 }
39330 {
39337 else
39339 }
39340 else
39341 {
39344 }
39347 }
39349 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
39350 in a single instruction. */
39352 static bool
39354 {
39358 /* Check plain VEC_SELECT first, because AVX has instructions that could
39359 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
39360 input where SEL+CONCAT may not. */
39362 {
39368 {
39374 }
39377 {
39381 }
39383 {
39384 /* Use vpbroadcast{b,w,d}. */
39387 {
39406 /* For other modes prefer other shuffles this function creates. */
39408 }
39410 {
39414 }
39415 }
39420 /* There are plenty of patterns in sse.md that are written for
39421 SEL+CONCAT and are not replicated for a single op. Perhaps
39422 that should be changed, to avoid the nastiness here. */
39424 /* Recognize interleave style patterns, which means incrementing
39425 every other permutation operand. */
39427 {
39430 }
39435 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
39437 {
39439 {
39444 }
39449 }
39450 }
39452 /* Finally, try the fully general two operand permute. */
39457 /* Recognize interleave style patterns with reversed operands. */
39459 {
39461 {
39465 else
39468 }
39473 }
39475 /* Try the SSE4.1 blend variable merge instructions. */
39479 /* Try one of the AVX vpermil variable permutations. */
39483 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
39484 vpshufb, vpermd, vpermps or vpermq variable permutation. */
39489 }
39491 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39492 in terms of a pair of pshuflw + pshufhw instructions. */
39494 static bool
39496 {
39504 /* The two permutations only operate in 64-bit lanes. */
39515 /* Emit the pshuflw. */
39522 /* Emit the pshufhw. */
39530 }
39532 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39533 the permutation using the SSSE3 palignr instruction. This succeeds
39534 when all of the elements in PERM fit within one vector and we merely
39535 need to shift them down so that a single vector permutation has a
39536 chance to succeed. */
39538 static bool
39540 {
39544 rtx shift;
39546 /* Even with AVX, palignr only operates on 128-bit vectors. */
39552 {
39558 }
39562 /* Given that we have SSSE3, we know we'll be able to implement the
39563 single operand permutation after the palignr with pshufb. */
39577 {
39582 }
39584 /* Test for the degenerate case where the alignment by itself
39585 produces the desired permutation. */
39593 }
39597 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39598 a two vector permutation into a single vector permutation by using
39599 an interleave operation to merge the vectors. */
39601 static bool
39603 {
39608 rtx seq;
39612 {
39615 }
39617 {
39620 /* For 32-byte modes allow even d->one_operand_p.
39621 The lack of cross-lane shuffling in some instructions
39622 might prevent a single insn shuffle. */
39625 /* If expand_vec_perm_interleave3 can expand this into
39626 a 3 insn sequence, give up and let it be expanded as
39627 3 insn sequence. While that is one insn longer,
39628 it doesn't need a memory operand and in the common
39629 case that both interleave low and high permutations
39630 with the same operands are adjacent needs 4 insns
39631 for both after CSE. */
39634 }
39635 else
39638 /* Examine from whence the elements come. */
39647 {
39650 /* Split the two input vectors into 4 halves. */
39656 /* If the elements from the low halves use interleave low, and similarly
39657 for interleave high. If the elements are from mis-matched halves, we
39658 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39660 {
39661 /* punpckl* */
39663 {
39668 }
39671 }
39673 {
39674 /* punpckh* */
39676 {
39681 }
39684 }
39686 {
39687 /* shufps */
39689 {
39694 }
39696 {
39697 /* shufpd */
39702 }
39703 }
39705 {
39706 /* shufps */
39708 {
39713 }
39715 {
39716 /* shufpd */
39721 }
39722 }
39723 else
39725 }
39726 else
39727 {
39732 /* Split the two input vectors into 8 quarters. */
39738 {
39741 }
39744 {
39748 }
39750 {
39753 }
39756 {
39758 {
39759 /* Attempt to increase the likelihood that dfinal
39760 shuffle will be intra-lane. */
39764 }
39766 /* vperm2f128 or vperm2i128. */
39768 {
39773 }
39778 {
39782 {
39785 }
39786 }
39787 }
39792 {
39793 /* vpunpckl* */
39795 {
39804 }
39805 }
39808 {
39809 /* vpunpckh* */
39811 {
39820 }
39821 }
39822 else
39824 }
39826 /* Use the remapping array set up above to move the elements from their
39827 swizzled locations into their final destinations. */
39830 {
39833 /* If same_halves is true, both halves of the remapped vector are the
39834 same. Avoid cross-lane accesses if possible. */
39836 {
39839 }
39840 else
39842 }
39848 /* Test if the final remap can be done with a single insn. For V4SFmode or
39849 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39862 {
39866 }
39873 }
39875 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39876 a single vector cross-lane permutation into vpermq followed
39877 by any of the single insn permutations. */
39879 static bool
39881 {
39895 {
39898 }
39901 {
39906 }
39919 {
39926 }
39933 {
39938 ;
39941 else
39943 }
39952 }
39954 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39955 a vector permutation using two instructions, vperm2f128 resp.
39956 vperm2i128 followed by any single in-lane permutation. */
39958 static bool
39960 {
39974 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39975 immediate. For perm < 16 the second permutation uses
39976 d->op0 as first operand, for perm >= 16 it uses d->op1
39977 as first operand. The second operand is the result of
39978 vperm2[fi]128. */
39980 {
39981 /* Ignore permutations which do not move anything cross-lane. */
39983 {
39984 /* The second shuffle for e.g. V4DFmode has
39985 0123 and ABCD operands.
39986 Ignore AB23, as 23 is already in the second lane
39987 of the first operand. */
39989 /* And 01CD, as 01 is in the first lane of the first
39990 operand. */
39992 /* And 4567, as then the vperm2[fi]128 doesn't change
39993 anything on the original 4567 second operand. */
39995 }
39996 else
39997 {
39998 /* The second shuffle for e.g. V4DFmode has
39999 4567 and ABCD operands.
40000 Ignore AB67, as 67 is already in the second lane
40001 of the first operand. */
40003 /* And 45CD, as 45 is in the first lane of the first
40004 operand. */
40006 /* And 0123, as then the vperm2[fi]128 doesn't change
40007 anything on the original 0123 first operand. */
40009 }
40012 {
40018 else
40020 }
40023 {
40027 }
40028 else
40032 {
40036 /* Found a usable second shuffle. dfirst will be
40037 vperm2f128 on d->op0 and d->op1. */
40048 /* And dsecond is some single insn shuffle, taking
40049 d->op0 and result of vperm2f128 (if perm < 16) or
40050 d->op1 and result of vperm2f128 (otherwise). */
40059 }
40061 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
40064 }
40067 }
40069 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
40070 a two vector permutation using 2 intra-lane interleave insns
40071 and cross-lane shuffle for 32-byte vectors. */
40073 static bool
40075 {
40082 ;
40084 ;
40085 else
40100 {
40104 else
40110 else
40116 else
40122 else
40128 else
40134 else
40139 }
40143 }
40145 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
40146 a single vector permutation using a single intra-lane vector
40147 permutation, vperm2f128 swapping the lanes and vblend* insn blending
40148 the non-swapped and swapped vectors together. */
40150 static bool
40152 {
40155 rtx seq;
40160 || TARGET_AVX2
40169 {
40176 }
40211 }
40213 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
40214 permutation using two vperm2f128, followed by a vshufpd insn blending
40215 the two vectors together. */
40217 static bool
40219 {
40262 }
40264 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
40265 permutation with two pshufb insns and an ior. We should have already
40266 failed all two instruction sequences. */
40268 static bool
40270 {
40281 /* Generate two permutation masks. If the required element is within
40282 the given vector it is shuffled into the proper lane. If the required
40283 element is in the other vector, force a zero into the lane by setting
40284 bit 7 in the permutation mask. */
40287 {
40294 {
40297 }
40298 }
40318 }
40320 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
40321 with two vpshufb insns, vpermq and vpor. We should have already failed
40322 all two or three instruction sequences. */
40324 static bool
40326 {
40341 /* Generate two permutation masks. If the required element is within
40342 the same lane, it is shuffled in. If the required element from the
40343 other lane, force a zero by setting bit 7 in the permutation mask.
40344 In the other mask the mask has non-negative elements if element
40345 is requested from the other lane, but also moved to the other lane,
40346 so that the result of vpshufb can have the two V2TImode halves
40347 swapped. */
40350 {
40355 {
40358 }
40359 }
40368 /* Swap the 128-byte lanes of h into hp. */
40372 const1_rtx));
40385 }
40387 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
40388 and extract-odd permutations of two V32QImode and V16QImode operand
40389 with two vpshufb insns, vpor and vpermq. We should have already
40390 failed all two or three instruction sequences. */
40392 static bool
40394 {
40413 /* Generate two permutation masks. In the first permutation mask
40414 the first quarter will contain indexes for the first half
40415 of the op0, the second quarter will contain bit 7 set, third quarter
40416 will contain indexes for the second half of the op0 and the
40417 last quarter bit 7 set. In the second permutation mask
40418 the first quarter will contain bit 7 set, the second quarter
40419 indexes for the first half of the op1, the third quarter bit 7 set
40420 and last quarter indexes for the second half of the op1.
40421 I.e. the first mask e.g. for V32QImode extract even will be:
40422 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
40423 (all values masked with 0xf except for -128) and second mask
40424 for extract even will be
40425 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
40428 {
40434 {
40437 }
40438 }
40457 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
40464 }
40466 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
40467 and extract-odd permutations. */
40469 static bool
40471 {
40475 {
40480 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40484 /* Now an unpck[lh]pd will produce the result required. */
40487 else
40493 {
40500 /* Shuffle within the 128-bit lanes to produce:
40501 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
40505 /* Shuffle the lanes around to produce:
40506 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
40510 /* Shuffle within the 128-bit lanes to produce:
40511 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
40514 /* Shuffle within the 128-bit lanes to produce:
40515 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
40518 /* Shuffle the lanes around to produce:
40519 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
40522 }
40529 /* These are always directly implementable by expand_vec_perm_1. */
40535 else
40536 {
40537 /* We need 2*log2(N)-1 operations to achieve odd/even
40538 with interleave. */
40547 else
40550 }
40556 else
40557 {
40569 else
40572 }
40581 {
40588 }
40593 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40597 /* Now an vpunpck[lh]qdq will produce the result required. */
40600 else
40607 {
40614 }
40619 /* Shuffle the lanes around into
40620 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40630 /* Swap the 2nd and 3rd position in each lane into
40631 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40637 /* Now an vpunpck[lh]qdq will produce
40638 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40643 else
40652 }
40655 }
40657 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40658 extract-even and extract-odd permutations. */
40660 static bool
40662 {
40674 }
40676 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40677 permutations. We assume that expand_vec_perm_1 has already failed. */
40679 static bool
40681 {
40689 {
40692 /* These are special-cased in sse.md so that we can optionally
40693 use the vbroadcast instruction. They expand to two insns
40694 if the input happens to be in a register. */
40701 /* These are always implementable using standard shuffle patterns. */
40706 /* These can be implemented via interleave. We save one insn by
40707 stopping once we have promoted to V4SImode and then use pshufd. */
40708 do
40709 {
40710 rtx dest;
40716 {
40720 }
40727 }
40740 /* For AVX2 broadcasts of the first element vpbroadcast* or
40741 vpermq should be used by expand_vec_perm_1. */
40747 }
40748 }
40750 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40751 broadcast permutations. */
40753 static bool
40755 {
40767 }
40769 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40770 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40771 all the shorter instruction sequences. */
40773 static bool
40775 {
40791 /* Generate 4 permutation masks. If the required element is within
40792 the same lane, it is shuffled in. If the required element from the
40793 other lane, force a zero by setting bit 7 in the permutation mask.
40794 In the other mask the mask has non-negative elements if element
40795 is requested from the other lane, but also moved to the other lane,
40796 so that the result of vpshufb can have the two V2TImode halves
40797 swapped. */
40800 {
40805 }
40811 {
40819 }
40822 {
40824 {
40827 }
40834 }
40836 /* Swap the 128-byte lanes of h[X]. */
40838 {
40844 const1_rtx));
40846 }
40849 {
40851 {
40854 }
40860 }
40863 {
40865 {
40869 }
40872 }
40878 }
40880 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40881 With all of the interface bits taken care of, perform the expansion
40882 in D and return true on success. */
40884 static bool
40886 {
40887 /* Try a single instruction expansion. */
40891 /* Try sequences of two instructions. */
40911 /* Try sequences of three instructions. */
40925 /* Try sequences of four instructions. */
40933 /* ??? Look for narrow permutations whose element orderings would
40934 allow the promotion to a wider mode. */
40936 /* ??? Look for sequences of interleave or a wider permute that place
40937 the data into the correct lanes for a half-vector shuffle like
40938 pshuf[lh]w or vpermilps. */
40940 /* ??? Look for sequences of interleave that produce the desired results.
40941 The combinatorics of punpck[lh] get pretty ugly... */
40946 /* Even longer sequences. */
40951 }
40953 /* If a permutation only uses one operand, make it clear. Returns true
40954 if the permutation references both operands. */
40956 static bool
40958 {
40966 {
40972 {
40975 }
40976 /* The elements of PERM do not suggest that only the first operand
40977 is used, but both operands are identical. Allow easier matching
40978 of the permutation by folding the permutation into the single
40979 input vector. */
40980 /* FALLTHRU */
40991 }
40994 }
40996 bool
40998 {
41003 rtx sel;
41020 {
41025 }
41032 /* If the selector says both arguments are needed, but the operands are the
41033 same, the above tried to expand with one_operand_p and flattened selector.
41034 If that didn't work, retry without one_operand_p; we succeeded with that
41035 during testing. */
41037 {
41041 }
41044 }
41046 /* Implement targetm.vectorize.vec_perm_const_ok. */
41048 static bool
41051 {
41060 /* Given sufficient ISA support we can just return true here
41061 for selected vector modes. */
41063 {
41064 /* All implementable with a single vpperm insn. */
41067 /* All implementable with 2 pshufb + 1 ior. */
41070 /* All implementable with shufpd or unpck[lh]pd. */
41073 }
41075 /* Extract the values from the vector CST into the permutation
41076 array in D. */
41079 {
41083 }
41085 /* For all elements from second vector, fold the elements to first. */
41090 /* Check whether the mask can be applied to the vector type. */
41093 /* Implementable with shufps or pshufd. */
41097 /* Otherwise we have to go through the motions and see if we can
41098 figure out how to generate the requested permutation. */
41109 }
41111 void
41113 {
41128 /* We'll either be able to implement the permutation directly... */
41132 /* ... or we use the special-case patterns. */
41134 }
41136 static void
41138 {
41153 {
41156 }
41158 /* Note that for AVX this isn't one instruction. */
41161 }
41164 /* Expand a vector operation CODE for a V*QImode in terms of the
41165 same operation on V*HImode. */
41167 void
41169 {
41181 {
41194 }
41198 {
41200 /* Unpack data such that we've got a source byte in each low byte of
41201 each word. We don't care what goes into the high byte of each word.
41202 Rather than trying to get zero in there, most convenient is to let
41203 it be a copy of the low byte. */
41208 /* FALLTHRU */
41220 /* FALLTHRU */
41230 }
41232 /* Perform the operation. */
41239 /* Merge the data back into the right place. */
41249 {
41250 /* For SSE2, we used an full interleave, so the desired
41251 results are in the even elements. */
41254 }
41255 else
41256 {
41257 /* For AVX, the interleave used above was not cross-lane. So the
41258 extraction is evens but with the second and third quarter swapped.
41259 Happily, that is even one insn shorter than even extraction. */
41262 }
41269 }
41271 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
41272 if op is CONST_VECTOR with all odd elements equal to their
41273 preceding element. */
41275 static bool
41277 {
41287 }
41289 void
41292 {
41295 rtx x;
41303 /* We only play even/odd games with vectors of SImode. */
41306 /* If we're looking for the odd results, shift those members down to
41307 the even slots. For some cpus this is faster than a PSHUFD. */
41309 {
41310 /* For XOP use vpmacsdqh, but only for smult, as it is only
41311 signed. */
41313 {
41317 }
41328 }
41331 {
41334 else
41336 }
41341 else
41342 {
41345 /* The easiest way to implement this without PMULDQ is to go through
41346 the motions as if we are performing a full 64-bit multiply. With
41347 the exception that we need to do less shuffling of the elements. */
41349 /* Compute the sign-extension, aka highparts, of the two operands. */
41355 /* Multiply LO(A) * HI(B), and vice-versa. */
41361 /* Multiply LO(A) * LO(B). */
41365 /* Combine and shift the highparts into place. */
41370 /* Combine high and low parts. */
41373 }
41375 }
41377 void
41380 {
41386 {
41391 {
41392 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
41393 shuffle the elements once so that all elements are in the right
41394 place for immediate use: { A C B D }. */
41399 }
41400 else
41401 {
41402 /* Put the elements into place for the multiply. */
41406 }
41411 /* Shuffle the elements between the lanes. After this we
41412 have { A B E F | C D G H } for each operand. */
41422 /* Shuffle the elements within the lanes. After this we
41423 have { A A B B | C C D D } or { E E F F | G G H H }. */
41459 }
41460 }
41462 void
41464 {
41474 /* Move the results in element 2 down to element 1; we don't care
41475 what goes in elements 2 and 3. Then we can merge the parts
41476 back together with an interleave.
41478 Note that two other sequences were tried:
41479 (1) Use interleaves at the start instead of psrldq, which allows
41480 us to use a single shufps to merge things back at the end.
41481 (2) Use shufps here to combine the two vectors, then pshufd to
41482 put the elements in the correct order.
41483 In both cases the cost of the reformatting stall was too high
41484 and the overall sequence slower. */
41493 }
41495 void
41497 {
41502 {
41503 /* op1: A,B,C,D, op2: E,F,G,H */
41512 /* t1: B,A,D,C */
41519 /* t2: (B*E),(A*F),(D*G),(C*H) */
41522 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
41525 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
41528 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
41530 }
41531 else
41532 {
41537 {
41540 }
41542 {
41545 }
41546 else
41550 /* Multiply low parts. */
41554 /* Shift input vectors right 32 bits so we can multiply high parts. */
41559 /* Multiply high parts by low parts. */
41565 /* Combine and shift the highparts back. */
41569 /* Combine high and low parts. */
41571 }
41575 }
41577 /* Expand an insert into a vector register through pinsr insn.
41578 Return true if successful. */
41580 bool
41582 {
41590 {
41593 }
41599 {
41604 {
41611 {
41643 }
41652 }
41656 }
41657 }
41658 \f
41659 /* This function returns the calling abi specific va_list type node.
41660 It returns the FNDECL specific va_list type. */
41662 static tree
41664 {
41671 else
41673 }
41675 /* Returns the canonical va_list type specified by TYPE. If there
41676 is no valid TYPE provided, it return NULL_TREE. */
41678 static tree
41680 {
41683 /* Resolve references and pointers to va_list type. */
41692 {
41697 {
41698 /* If va_list is an array type, the argument may have decayed
41699 to a pointer type, e.g. by being passed to another function.
41700 In that case, unwrap both types so that we can compare the
41701 underlying records. */
41704 {
41707 }
41708 }
41715 {
41716 /* If va_list is an array type, the argument may have decayed
41717 to a pointer type, e.g. by being passed to another function.
41718 In that case, unwrap both types so that we can compare the
41719 underlying records. */
41722 {
41725 }
41726 }
41733 {
41734 /* If va_list is an array type, the argument may have decayed
41735 to a pointer type, e.g. by being passed to another function.
41736 In that case, unwrap both types so that we can compare the
41737 underlying records. */
41740 {
41743 }
41744 }
41748 }
41750 }
41752 /* Iterate through the target-specific builtin types for va_list.
41753 IDX denotes the iterator, *PTREE is set to the result type of
41754 the va_list builtin, and *PNAME to its internal type.
41755 Returns zero if there is no element for this index, otherwise
41756 IDX should be increased upon the next call.
41757 Note, do not iterate a base builtin's name like __builtin_va_list.
41758 Used from c_common_nodes_and_builtins. */
41760 static int
41762 {
41764 {
41766 {
41779 }
41780 }
41783 }
41785 #undef TARGET_SCHED_DISPATCH
41786 #define TARGET_SCHED_DISPATCH has_dispatch
41787 #undef TARGET_SCHED_DISPATCH_DO
41788 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41789 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41790 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41791 #undef TARGET_SCHED_REORDER
41792 #define TARGET_SCHED_REORDER ix86_sched_reorder
41793 #undef TARGET_SCHED_ADJUST_PRIORITY
41794 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41795 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41796 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
41797 ix86_dependencies_evaluation_hook
41799 /* The size of the dispatch window is the total number of bytes of
41800 object code allowed in a window. */
41801 #define DISPATCH_WINDOW_SIZE 16
41803 /* Number of dispatch windows considered for scheduling. */
41804 #define MAX_DISPATCH_WINDOWS 3
41806 /* Maximum number of instructions in a window. */
41807 #define MAX_INSN 4
41809 /* Maximum number of immediate operands in a window. */
41810 #define MAX_IMM 4
41812 /* Maximum number of immediate bits allowed in a window. */
41813 #define MAX_IMM_SIZE 128
41815 /* Maximum number of 32 bit immediates allowed in a window. */
41816 #define MAX_IMM_32 4
41818 /* Maximum number of 64 bit immediates allowed in a window. */
41819 #define MAX_IMM_64 2
41821 /* Maximum total of loads or prefetches allowed in a window. */
41822 #define MAX_LOAD 2
41824 /* Maximum total of stores allowed in a window. */
41825 #define MAX_STORE 1
41827 #undef BIG
41828 #define BIG 100
41831 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41834 disp_load,
41835 disp_store,
41836 disp_load_store,
41837 disp_prefetch,
41838 disp_imm,
41839 disp_imm_32,
41840 disp_imm_64,
41841 disp_branch,
41842 disp_cmp,
41843 disp_jcc,
41844 disp_last
41845 };
41847 /* Number of allowable groups in a dispatch window. It is an array
41848 indexed by dispatch_group enum. 100 is used as a big number,
41849 because the number of these kind of operations does not have any
41850 effect in dispatch window, but we need them for other reasons in
41851 the table. */
41854 };
41860 };
41862 /* Instruction path. */
41868 last_path
41869 };
41871 /* sched_insn_info defines a window to the instructions scheduled in
41872 the basic block. It contains a pointer to the insn_info table and
41873 the instruction scheduled.
41875 Windows are allocated for each basic block and are linked
41876 together. */
41878 rtx insn;
41885 /* Linked list of dispatch windows. This is a two way list of
41886 dispatch windows of a basic block. It contains information about
41887 the number of uops in the window and the total number of
41888 instructions and of bytes in the object code for this dispatch
41889 window. */
41907 /* Immediate valuse used in an insn. */
41909 {
41918 /* Get dispatch group of insn. */
41920 static enum dispatch_group
41922 {
41938 }
41940 /* Return true if insn is a compare instruction. */
41942 static bool
41944 {
41952 }
41954 /* Return true if a dispatch violation encountered. */
41956 static bool
41958 {
41962 }
41964 /* Return true if insn is a branch instruction. */
41966 static bool
41968 {
41970 }
41972 /* Return true if insn is a prefetch instruction. */
41974 static bool
41976 {
41978 }
41980 /* This function initializes a dispatch window and the list container holding a
41981 pointer to the window. */
41983 static void
41985 {
41991 else
42009 {
42015 }
42017 }
42019 /* This function allocates and initializes a dispatch window and the
42020 list container holding a pointer to the window. */
42024 {
42029 }
42031 /* This routine initializes the dispatch scheduling information. It
42032 initiates building dispatch scheduler tables and constructs the
42033 first dispatch window. */
42035 static void
42037 {
42038 /* Allocate a dispatch list and a window. */
42043 }
42045 /* This function returns true if a branch is detected. End of a basic block
42046 does not have to be a branch, but here we assume only branches end a
42047 window. */
42049 static bool
42051 {
42053 }
42055 /* This function is called when the end of a window processing is reached. */
42057 static void
42059 {
42062 {
42067 }
42069 }
42071 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
42072 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
42073 for 48 bytes of instructions. Note that these windows are not dispatch
42074 windows that their sizes are DISPATCH_WINDOW_SIZE. */
42078 {
42080 {
42085 }
42091 }
42093 /* Increment the number of immediate operands of an instruction. */
42095 static int
42097 {
42102 {
42109 else
42120 {
42123 }
42128 }
42131 }
42133 /* Compute number of immediate operands of an instruction. */
42135 static void
42137 {
42140 }
42142 /* Return total size of immediate operands of an instruction along with number
42143 of corresponding immediate-operands. It initializes its parameters to zero
42144 befor calling FIND_CONSTANT.
42145 INSN is the input instruction. IMM is the total of immediates.
42146 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
42147 bit immediates. */
42149 static int
42151 {
42159 }
42161 /* This function indicates if an operand of an instruction is an
42162 immediate. */
42164 static bool
42166 {
42175 }
42177 /* Return single or double path for instructions. */
42179 static enum insn_path
42181 {
42191 }
42193 /* Return insn dispatch group. */
42195 static enum dispatch_group
42197 {
42215 }
42217 /* Count number of GROUP restricted instructions in a dispatch
42218 window WINDOW_LIST. */
42220 static int
42222 {
42233 {
42252 }
42265 }
42267 /* This function returns true if insn satisfies dispatch rules on the
42268 last window scheduled. */
42270 static bool
42272 {
42280 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
42281 instructions should be given the lowest priority in the
42282 scheduling process in Haifa scheduler to make sure they will be
42283 scheduled in the same dispatch window as the reference to them. */
42287 /* Check nonrestricted. */
42291 /* Get last dispatch window. */
42296 {
42301 /* Window 1 is full. Go for next window. */
42303 }
42310 /* See if it fits in the first window. */
42312 {
42313 /* The first widow should have only single and double path
42314 uops. */
42320 }
42322 }
42324 /* Add an instruction INSN with NUM_UOPS micro-operations to the
42325 dispatch window WINDOW_LIST. */
42327 static void
42329 {
42347 /* Initialize window with new instruction. */
42368 {
42371 }
42372 }
42374 /* Adds a scheduled instruction, INSN, to the current dispatch window.
42375 If the total bytes of instructions or the number of instructions in
42376 the window exceed allowable, it allocates a new window. */
42378 static void
42380 {
42403 /* Get the last dispatch window. */
42411 else
42414 /* If current window is full, get a new window.
42415 Window number zero is full, if MAX_INSN uops are scheduled in it.
42416 Window number one is full, if window zero's bytes plus window
42417 one's bytes is 32, or if the bytes of the new instruction added
42418 to the total makes it greater than 48, or it has already MAX_INSN
42419 instructions in it. */
42428 {
42431 }
42434 {
42438 {
42441 }
42442 }
42444 {
42449 {
42452 }
42455 }
42456 else
42460 {
42461 /* End of basic block is reached do end-basic-block process. */
42464 }
42465 }
42467 /* Print the dispatch window, WINDOW_NUM, to FILE. */
42469 DEBUG_FUNCTION static void
42471 {
42477 else
42491 {
42494 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
42500 }
42501 }
42503 /* Print to stdout a dispatch window. */
42505 DEBUG_FUNCTION void
42507 {
42509 }
42511 /* Print INSN dispatch information to FILE. */
42513 DEBUG_FUNCTION static void
42515 {
42538 }
42540 /* Print to STDERR the status of the ready list with respect to
42541 dispatch windows. */
42543 DEBUG_FUNCTION void
42545 {
42553 }
42555 /* This routine is the driver of the dispatch scheduler. */
42557 static void
42559 {
42564 }
42566 /* Return TRUE if Dispatch Scheduling is supported. */
42568 static bool
42570 {
42574 {
42590 }
42593 }
42595 /* Implementation of reassociation_width target hook used by
42596 reassoc phase to identify parallelism level in reassociated
42597 tree. Statements tree_code is passed in OPC. Arguments type
42598 is passed in MODE.
42600 Currently parallel reassociation is enabled for Atom
42601 processors only and we set reassociation width to be 2
42602 because Atom may issue up to 2 instructions per cycle.
42604 Return value should be fixed if parallel reassociation is
42605 enabled for other processors. */
42607 static int
42610 {
42619 }
42621 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42622 place emms and femms instructions. */
42624 static enum machine_mode
42626 {
42631 {
42644 else
42654 /* FALLTHRU */
42658 }
42659 }
42661 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42662 vectors. */
42664 static unsigned int
42666 {
42668 }
42670 \f
42672 /* Return class of registers which could be used for pseudo of MODE
42673 and of class RCLASS for spilling instead of memory. Return NO_REGS
42674 if it is not possible or non-profitable. */
42675 static reg_class_t
42677 {
42683 }
42685 /* Implement targetm.vectorize.init_cost. */
42689 {
42693 }
42695 /* Implement targetm.vectorize.add_stmt_cost. */
42697 static unsigned
42701 {
42706 {
42710 /* Statements in an inner loop relative to the loop being
42711 vectorized are weighted more heavily. The value here is
42712 arbitrary and could potentially be improved with analysis. */
42718 }
42721 }
42723 /* Implement targetm.vectorize.finish_cost. */
42725 static void
42728 {
42733 }
42735 /* Implement targetm.vectorize.destroy_cost_data. */
42737 static void
42739 {
42741 }
42743 /* Validate target specific memory model bits in VAL. */
42745 static unsigned HOST_WIDE_INT
42747 {
42754 {
42758 }
42761 {
42765 }
42767 {
42771 }
42773 }
42775 /* Initialize the GCC target structure. */
42776 #undef TARGET_RETURN_IN_MEMORY
42777 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42779 #undef TARGET_LEGITIMIZE_ADDRESS
42780 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42782 #undef TARGET_ATTRIBUTE_TABLE
42783 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42784 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
42785 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
42786 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42787 # undef TARGET_MERGE_DECL_ATTRIBUTES
42788 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42789 #endif
42791 #undef TARGET_COMP_TYPE_ATTRIBUTES
42792 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42794 #undef TARGET_INIT_BUILTINS
42795 #define TARGET_INIT_BUILTINS ix86_init_builtins
42796 #undef TARGET_BUILTIN_DECL
42797 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42798 #undef TARGET_EXPAND_BUILTIN
42799 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42801 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42802 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42803 ix86_builtin_vectorized_function
42805 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42806 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42808 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42809 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42811 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42812 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42814 #undef TARGET_BUILTIN_RECIPROCAL
42815 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42817 #undef TARGET_ASM_FUNCTION_EPILOGUE
42818 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42820 #undef TARGET_ENCODE_SECTION_INFO
42821 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42822 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42823 #else
42824 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42825 #endif
42827 #undef TARGET_ASM_OPEN_PAREN
42829 #undef TARGET_ASM_CLOSE_PAREN
42832 #undef TARGET_ASM_BYTE_OP
42833 #define TARGET_ASM_BYTE_OP ASM_BYTE
42835 #undef TARGET_ASM_ALIGNED_HI_OP
42836 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42837 #undef TARGET_ASM_ALIGNED_SI_OP
42838 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42839 #ifdef ASM_QUAD
42840 #undef TARGET_ASM_ALIGNED_DI_OP
42841 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42842 #endif
42844 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42845 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42847 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42848 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42850 #undef TARGET_ASM_UNALIGNED_HI_OP
42851 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42852 #undef TARGET_ASM_UNALIGNED_SI_OP
42853 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42854 #undef TARGET_ASM_UNALIGNED_DI_OP
42855 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42857 #undef TARGET_PRINT_OPERAND
42858 #define TARGET_PRINT_OPERAND ix86_print_operand
42859 #undef TARGET_PRINT_OPERAND_ADDRESS
42860 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42861 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42862 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42863 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42864 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42866 #undef TARGET_SCHED_INIT_GLOBAL
42867 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42868 #undef TARGET_SCHED_ADJUST_COST
42869 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42870 #undef TARGET_SCHED_ISSUE_RATE
42871 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42872 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42873 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42874 ia32_multipass_dfa_lookahead
42876 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42877 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42879 #undef TARGET_MEMMODEL_CHECK
42880 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42882 #ifdef HAVE_AS_TLS
42883 #undef TARGET_HAVE_TLS
42884 #define TARGET_HAVE_TLS true
42885 #endif
42886 #undef TARGET_CANNOT_FORCE_CONST_MEM
42887 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42888 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42889 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42891 #undef TARGET_DELEGITIMIZE_ADDRESS
42892 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42894 #undef TARGET_MS_BITFIELD_LAYOUT_P
42895 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42897 #if TARGET_MACHO
42898 #undef TARGET_BINDS_LOCAL_P
42899 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42900 #endif
42901 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42902 #undef TARGET_BINDS_LOCAL_P
42903 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42904 #endif
42906 #undef TARGET_ASM_OUTPUT_MI_THUNK
42907 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42908 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42909 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42911 #undef TARGET_ASM_FILE_START
42912 #define TARGET_ASM_FILE_START x86_file_start
42914 #undef TARGET_OPTION_OVERRIDE
42915 #define TARGET_OPTION_OVERRIDE ix86_option_override
42917 #undef TARGET_REGISTER_MOVE_COST
42918 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42919 #undef TARGET_MEMORY_MOVE_COST
42920 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42921 #undef TARGET_RTX_COSTS
42922 #define TARGET_RTX_COSTS ix86_rtx_costs
42923 #undef TARGET_ADDRESS_COST
42924 #define TARGET_ADDRESS_COST ix86_address_cost
42926 #undef TARGET_FIXED_CONDITION_CODE_REGS
42927 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42928 #undef TARGET_CC_MODES_COMPATIBLE
42929 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42931 #undef TARGET_MACHINE_DEPENDENT_REORG
42932 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42934 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42935 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42937 #undef TARGET_BUILD_BUILTIN_VA_LIST
42938 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42940 #undef TARGET_FOLD_BUILTIN
42941 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42943 #undef TARGET_COMPARE_VERSION_PRIORITY
42944 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42946 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42947 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42948 ix86_generate_version_dispatcher_body
42950 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42951 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42952 ix86_get_function_versions_dispatcher
42954 #undef TARGET_ENUM_VA_LIST_P
42955 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42957 #undef TARGET_FN_ABI_VA_LIST
42958 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42960 #undef TARGET_CANONICAL_VA_LIST_TYPE
42961 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42963 #undef TARGET_EXPAND_BUILTIN_VA_START
42964 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42966 #undef TARGET_MD_ASM_CLOBBERS
42967 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42969 #undef TARGET_PROMOTE_PROTOTYPES
42970 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42971 #undef TARGET_STRUCT_VALUE_RTX
42972 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42973 #undef TARGET_SETUP_INCOMING_VARARGS
42974 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42975 #undef TARGET_MUST_PASS_IN_STACK
42976 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42977 #undef TARGET_FUNCTION_ARG_ADVANCE
42978 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42979 #undef TARGET_FUNCTION_ARG
42980 #define TARGET_FUNCTION_ARG ix86_function_arg
42981 #undef TARGET_FUNCTION_ARG_BOUNDARY
42982 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42983 #undef TARGET_PASS_BY_REFERENCE
42984 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42985 #undef TARGET_INTERNAL_ARG_POINTER
42986 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42987 #undef TARGET_UPDATE_STACK_BOUNDARY
42988 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42989 #undef TARGET_GET_DRAP_RTX
42990 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42991 #undef TARGET_STRICT_ARGUMENT_NAMING
42992 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42993 #undef TARGET_STATIC_CHAIN
42994 #define TARGET_STATIC_CHAIN ix86_static_chain
42995 #undef TARGET_TRAMPOLINE_INIT
42996 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42997 #undef TARGET_RETURN_POPS_ARGS
42998 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
43000 #undef TARGET_LEGITIMATE_COMBINED_INSN
43001 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
43003 #undef TARGET_ASAN_SHADOW_OFFSET
43004 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
43006 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
43007 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
43009 #undef TARGET_SCALAR_MODE_SUPPORTED_P
43010 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
43012 #undef TARGET_VECTOR_MODE_SUPPORTED_P
43013 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
43015 #undef TARGET_C_MODE_FOR_SUFFIX
43016 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
43018 #ifdef HAVE_AS_TLS
43019 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
43020 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
43021 #endif
43023 #ifdef SUBTARGET_INSERT_ATTRIBUTES
43024 #undef TARGET_INSERT_ATTRIBUTES
43025 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
43026 #endif
43028 #undef TARGET_MANGLE_TYPE
43029 #define TARGET_MANGLE_TYPE ix86_mangle_type
43031 #if !TARGET_MACHO
43032 #undef TARGET_STACK_PROTECT_FAIL
43033 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
43034 #endif
43036 #undef TARGET_FUNCTION_VALUE
43037 #define TARGET_FUNCTION_VALUE ix86_function_value
43039 #undef TARGET_FUNCTION_VALUE_REGNO_P
43040 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
43042 #undef TARGET_PROMOTE_FUNCTION_MODE
43043 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
43045 #undef TARGET_MEMBER_TYPE_FORCES_BLK
43046 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
43048 #undef TARGET_INSTANTIATE_DECLS
43049 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
43051 #undef TARGET_SECONDARY_RELOAD
43052 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
43054 #undef TARGET_CLASS_MAX_NREGS
43055 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
43057 #undef TARGET_PREFERRED_RELOAD_CLASS
43058 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
43059 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
43060 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
43061 #undef TARGET_CLASS_LIKELY_SPILLED_P
43062 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
43064 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
43065 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
43066 ix86_builtin_vectorization_cost
43067 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
43068 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
43069 ix86_vectorize_vec_perm_const_ok
43070 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
43071 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
43072 ix86_preferred_simd_mode
43073 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
43074 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
43075 ix86_autovectorize_vector_sizes
43076 #undef TARGET_VECTORIZE_INIT_COST
43077 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
43078 #undef TARGET_VECTORIZE_ADD_STMT_COST
43079 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
43080 #undef TARGET_VECTORIZE_FINISH_COST
43081 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
43082 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
43083 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
43085 #undef TARGET_SET_CURRENT_FUNCTION
43086 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
43088 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
43089 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
43091 #undef TARGET_OPTION_SAVE
43092 #define TARGET_OPTION_SAVE ix86_function_specific_save
43094 #undef TARGET_OPTION_RESTORE
43095 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
43097 #undef TARGET_OPTION_PRINT
43098 #define TARGET_OPTION_PRINT ix86_function_specific_print
43100 #undef TARGET_OPTION_FUNCTION_VERSIONS
43101 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
43103 #undef TARGET_CAN_INLINE_P
43104 #define TARGET_CAN_INLINE_P ix86_can_inline_p
43106 #undef TARGET_EXPAND_TO_RTL_HOOK
43107 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
43109 #undef TARGET_LEGITIMATE_ADDRESS_P
43110 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
43112 #undef TARGET_LRA_P
43113 #define TARGET_LRA_P hook_bool_void_true
43115 #undef TARGET_REGISTER_PRIORITY
43116 #define TARGET_REGISTER_PRIORITY ix86_register_priority
43118 #undef TARGET_REGISTER_USAGE_LEVELING_P
43119 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
43121 #undef TARGET_LEGITIMATE_CONSTANT_P
43122 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
43124 #undef TARGET_FRAME_POINTER_REQUIRED
43125 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
43127 #undef TARGET_CAN_ELIMINATE
43128 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
43130 #undef TARGET_EXTRA_LIVE_ON_ENTRY
43131 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
43133 #undef TARGET_ASM_CODE_END
43134 #define TARGET_ASM_CODE_END ix86_code_end
43136 #undef TARGET_CONDITIONAL_REGISTER_USAGE
43137 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
43139 #if TARGET_MACHO
43140 #undef TARGET_INIT_LIBFUNCS
43141 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
43142 #endif
43144 #undef TARGET_SPILL_CLASS
43145 #define TARGET_SPILL_CLASS ix86_spill_class
43148 \f