1 ;; Frv Machine Description
2 ;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005 Free Software Foundation,
4 ;; Contributed by Red Hat, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; ::::::::::::::::::::
30 ;; ::::::::::::::::::::
32 ;; GOT constants must go 12/HI/LO for the splitter to work
38 (UNSPEC_PIC_PROLOGUE 3)
40 (UNSPEC_STACK_ADJUST 5)
41 (UNSPEC_EH_RETURN_EPILOGUE 6)
44 (UNSPEC_OPTIONAL_MEMBAR 9)
46 (UNSPEC_GETTLSOFF 200)
47 (UNSPEC_TLS_LOAD_GOTTLSOFF12 201)
48 (UNSPEC_TLS_INDIRECT_CALL 202)
49 (UNSPEC_TLS_TLSDESC_LDD 203)
50 (UNSPEC_TLS_TLSDESC_LDD_AUX 204)
51 (UNSPEC_TLS_TLSOFF_LD 205)
53 (UNSPEC_TLSOFF_HILO 207)
59 (R_FRV_FUNCDESC_GOT12 15)
60 (R_FRV_FUNCDESC_GOTHI 16)
61 (R_FRV_FUNCDESC_GOTLO 17)
62 (R_FRV_FUNCDESC_VALUE 18)
63 (R_FRV_FUNCDESC_GOTOFF12 19)
64 (R_FRV_FUNCDESC_GOTOFFHI 20)
65 (R_FRV_FUNCDESC_GOTOFFLO 21)
72 (R_FRV_GOTTLSOFF_HI 28)
73 (R_FRV_GOTTLSOFF_LO 29)
79 (R_FRV_GOTTLSDESCHI 35)
80 (R_FRV_GOTTLSDESCLO 36)
85 ;; LR_REG conflicts with definition in frv.h
90 (define_mode_macro IMODE [QI HI SI DI])
91 (define_mode_attr IMODEsuffix [(QI "b") (HI "h") (SI "") (DI "d")])
92 (define_mode_attr BREADsuffix [(QI "ub") (HI "uh") (SI "") (DI "d")])
94 ;; ::::::::::::::::::::
98 ;; ::::::::::::::::::::
100 ;; Standard Constraints
102 ;; `m' A memory operand is allowed, with any kind of address that the
103 ;; machine supports in general.
105 ;; `o' A memory operand is allowed, but only if the address is
106 ;; "offsettable". This means that adding a small integer (actually, the
107 ;; width in bytes of the operand, as determined by its machine mode) may be
108 ;; added to the address and the result is also a valid memory address.
110 ;; `V' A memory operand that is not offsettable. In other words,
111 ;; anything that would fit the `m' constraint but not the `o' constraint.
113 ;; `<' A memory operand with autodecrement addressing (either
114 ;; predecrement or postdecrement) is allowed.
116 ;; `>' A memory operand with autoincrement addressing (either
117 ;; preincrement or postincrement) is allowed.
119 ;; `r' A register operand is allowed provided that it is in a general
122 ;; `d', `a', `f', ...
123 ;; Other letters can be defined in machine-dependent fashion to stand for
124 ;; particular classes of registers. `d', `a' and `f' are defined on the
125 ;; 68000/68020 to stand for data, address and floating point registers.
127 ;; `i' An immediate integer operand (one with constant value) is allowed.
128 ;; This includes symbolic constants whose values will be known only at
131 ;; `n' An immediate integer operand with a known numeric value is allowed.
132 ;; Many systems cannot support assembly-time constants for operands less
133 ;; than a word wide. Constraints for these operands should use `n' rather
136 ;; 'I' First machine-dependent integer constant (6-bit signed ints).
137 ;; 'J' Second machine-dependent integer constant (10-bit signed ints).
138 ;; 'K' Third machine-dependent integer constant (-2048).
139 ;; 'L' Fourth machine-dependent integer constant (16-bit signed ints).
140 ;; 'M' Fifth machine-dependent integer constant (16-bit unsigned ints).
141 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
142 ;; 'O' Seventh machine-dependent integer constant (zero).
143 ;; 'P' Eighth machine-dependent integer constant (1..2047).
145 ;; Other letters in the range `I' through `P' may be defined in a
146 ;; machine-dependent fashion to permit immediate integer operands with
147 ;; explicit integer values in specified ranges. For example, on the 68000,
148 ;; `I' is defined to stand for the range of values 1 to 8. This is the
149 ;; range permitted as a shift count in the shift instructions.
151 ;; `E' An immediate floating operand (expression code `const_double') is
152 ;; allowed, but only if the target floating point format is the same as
153 ;; that of the host machine (on which the compiler is running).
155 ;; `F' An immediate floating operand (expression code `const_double') is
158 ;; 'G' First machine-dependent const_double.
159 ;; 'H' Second machine-dependent const_double.
161 ;; `s' An immediate integer operand whose value is not an explicit
162 ;; integer is allowed.
164 ;; This might appear strange; if an insn allows a constant operand with a
165 ;; value not known at compile time, it certainly must allow any known
166 ;; value. So why use `s' instead of `i'? Sometimes it allows better code
169 ;; For example, on the 68000 in a fullword instruction it is possible to
170 ;; use an immediate operand; but if the immediate value is between -128 and
171 ;; 127, better code results from loading the value into a register and
172 ;; using the register. This is because the load into the register can be
173 ;; done with a `moveq' instruction. We arrange for this to happen by
174 ;; defining the letter `K' to mean "any integer outside the range -128 to
175 ;; 127", and then specifying `Ks' in the operand constraints.
177 ;; `g' Any register, memory or immediate integer operand is allowed,
178 ;; except for registers that are not general registers.
180 ;; `X' Any operand whatsoever is allowed, even if it does not satisfy
181 ;; `general_operand'. This is normally used in the constraint of a
182 ;; `match_scratch' when certain alternatives will not actually require a
185 ;; `0' Match operand 0.
186 ;; `1' Match operand 1.
187 ;; `2' Match operand 2.
188 ;; `3' Match operand 3.
189 ;; `4' Match operand 4.
190 ;; `5' Match operand 5.
191 ;; `6' Match operand 6.
192 ;; `7' Match operand 7.
193 ;; `8' Match operand 8.
194 ;; `9' Match operand 9.
196 ;; An operand that matches the specified operand number is allowed. If a
197 ;; digit is used together with letters within the same alternative, the
198 ;; digit should come last.
200 ;; This is called a "matching constraint" and what it really means is that
201 ;; the assembler has only a single operand that fills two roles considered
202 ;; separate in the RTL insn. For example, an add insn has two input
203 ;; operands and one output operand in the RTL, but on most CISC machines an
204 ;; add instruction really has only two operands, one of them an
205 ;; input-output operand:
209 ;; Matching constraints are used in these circumstances. More precisely,
210 ;; the two operands that match must include one input-only operand and one
211 ;; output-only operand. Moreover, the digit must be a smaller number than
212 ;; the number of the operand that uses it in the constraint.
214 ;; For operands to match in a particular case usually means that they are
215 ;; identical-looking RTL expressions. But in a few special cases specific
216 ;; kinds of dissimilarity are allowed. For example, `*x' as an input
217 ;; operand will match `*x++' as an output operand. For proper results in
218 ;; such cases, the output template should always use the output-operand's
219 ;; number when printing the operand.
221 ;; `p' An operand that is a valid memory address is allowed. This is for
222 ;; "load address" and "push address" instructions.
224 ;; `p' in the constraint must be accompanied by `address_operand' as the
225 ;; predicate in the `match_operand'. This predicate interprets the mode
226 ;; specified in the `match_operand' as the mode of the memory reference for
227 ;; which the address would be valid.
229 ;; `Q` First non constant, non register machine-dependent insns
230 ;; `R` Second non constant, non register machine-dependent insns
231 ;; `S` Third non constant, non register machine-dependent insns
232 ;; `T` Fourth non constant, non register machine-dependent insns
233 ;; `U` Fifth non constant, non register machine-dependent insns
235 ;; Letters in the range `Q' through `U' may be defined in a
236 ;; machine-dependent fashion to stand for arbitrary operand types. The
237 ;; machine description macro `EXTRA_CONSTRAINT' is passed the operand as
238 ;; its first argument and the constraint letter as its second operand.
240 ;; A typical use for this would be to distinguish certain types of memory
241 ;; references that affect other insn operands.
243 ;; Do not define these constraint letters to accept register references
244 ;; (`reg'); the reload pass does not expect this and would not handle it
247 ;; Multiple Alternative Constraints
248 ;; `?' Disparage slightly the alternative that the `?' appears in, as a
249 ;; choice when no alternative applies exactly. The compiler regards this
250 ;; alternative as one unit more costly for each `?' that appears in it.
252 ;; `!' Disparage severely the alternative that the `!' appears in. This
253 ;; alternative can still be used if it fits without reloading, but if
254 ;; reloading is needed, some other alternative will be used.
256 ;; Constraint modifiers
257 ;; `=' Means that this operand is write-only for this instruction: the
258 ;; previous value is discarded and replaced by output data.
260 ;; `+' Means that this operand is both read and written by the
263 ;; When the compiler fixes up the operands to satisfy the constraints, it
264 ;; needs to know which operands are inputs to the instruction and which are
265 ;; outputs from it. `=' identifies an output; `+' identifies an operand
266 ;; that is both input and output; all other operands are assumed to be
269 ;; `&' Means (in a particular alternative) that this operand is written
270 ;; before the instruction is finished using the input operands. Therefore,
271 ;; this operand may not lie in a register that is used as an input operand
272 ;; or as part of any memory address.
274 ;; `&' applies only to the alternative in which it is written. In
275 ;; constraints with multiple alternatives, sometimes one alternative
276 ;; requires `&' while others do not.
278 ;; `&' does not obviate the need to write `='.
280 ;; `%' Declares the instruction to be commutative for this operand and the
281 ;; following operand. This means that the compiler may interchange the two
282 ;; operands if that is the cheapest way to make all operands fit the
283 ;; constraints. This is often used in patterns for addition instructions
284 ;; that really have only two operands: the result must go in one of the
287 ;; `#' Says that all following characters, up to the next comma, are to be
288 ;; ignored as a constraint. They are significant only for choosing
289 ;; register preferences.
291 ;; `*' Says that the following character should be ignored when choosing
292 ;; register preferences. `*' has no effect on the meaning of the
293 ;; constraint as a constraint, and no effect on reloading.
296 ;; ::::::::::::::::::::
300 ;; ::::::::::::::::::::
302 ;; The `define_attr' expression is used to define each attribute required by
303 ;; the target machine. It looks like:
305 ;; (define_attr NAME LIST-OF-VALUES DEFAULT)
307 ;; NAME is a string specifying the name of the attribute being defined.
309 ;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
310 ;; values that can be assigned to the attribute, or a null string to indicate
311 ;; that the attribute takes numeric values.
313 ;; DEFAULT is an attribute expression that gives the value of this attribute
314 ;; for insns that match patterns whose definition does not include an explicit
315 ;; value for this attribute.
317 ;; For each defined attribute, a number of definitions are written to the
318 ;; `insn-attr.h' file. For cases where an explicit set of values is specified
319 ;; for an attribute, the following are defined:
321 ;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
323 ;; * An enumeral class is defined for `attr_NAME' with elements of the
324 ;; form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
325 ;; converted to upper case.
327 ;; * A function `get_attr_NAME' is defined that is passed an insn and
328 ;; returns the attribute value for that insn.
330 ;; For example, if the following is present in the `md' file:
332 ;; (define_attr "type" "branch,fp,load,store,arith" ...)
334 ;; the following lines will be written to the file `insn-attr.h'.
336 ;; #define HAVE_ATTR_type
337 ;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
338 ;; extern enum attr_type get_attr_type ();
340 ;; If the attribute takes numeric values, no `enum' type will be defined and
341 ;; the function to obtain the attribute's value will return `int'.
343 (define_attr "length" "" (const_int 4))
345 ;; Processor type -- this attribute must exactly match the processor_type
346 ;; enumeration in frv-protos.h.
348 (define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat"
349 (const (symbol_ref "frv_cpu_type")))
351 ;; Attribute is "yes" for branches and jumps that span too great a distance
352 ;; to be implemented in the most natural way. Such instructions will use
353 ;; a call instruction in some way.
355 (define_attr "far_jump" "yes,no" (const_string "no"))
358 ;; "unknown" must come last.
360 "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown"
361 (const_string "unknown"))
363 (define_attr "acc_group" "none,even,odd"
364 (symbol_ref "frv_acc_group (insn)"))
366 ;; Scheduling and Packing Overview
367 ;; -------------------------------
369 ;; FR-V instructions are divided into five groups: integer, floating-point,
370 ;; media, branch and control. Each group is associated with a separate set
371 ;; of processing units, the number and behavior of which depend on the target
372 ;; target processor. Integer units have names like I0 and I1, floating-point
373 ;; units have names like F0 and F1, and so on.
375 ;; Each member of the FR-V family has its own restrictions on which
376 ;; instructions can issue to which units. For example, some processors
377 ;; allow loads to issue to I0 or I1 while others only allow them to issue
378 ;; to I0. As well as these processor-specific restrictions, there is a
379 ;; general rule that an instruction can only issue to unit X + 1 if an
380 ;; instruction in the same packet issued to unit X.
382 ;; Sometimes the only way to honor these restrictions is by adding nops
383 ;; to a packet. For example, on the fr550, media instructions that access
384 ;; ACC4-7 can only issue to M1 or M3. It is therefore only possible to
385 ;; execute these instructions by packing them with something that issues
386 ;; to M0. When no useful M0 instruction exists, an "mnop" can be used
389 ;; Having decided which instructions should issue to which units, the packet
390 ;; should be ordered according to the following template:
392 ;; I0 F0/M0 I1 F1/M1 .... B0 B1 ...
394 ;; Note that VLIW packets execute strictly in parallel. Every instruction
395 ;; in the packet will stall until all input operands are ready. These
396 ;; operands are then read simultaneously before any registers are modified.
397 ;; This means that it's OK to have write-after-read hazards between
398 ;; instructions in the same packet, even if the write is listed earlier
401 ;; Three gcc passes are involved in generating VLIW packets:
403 ;; (1) The scheduler. This pass uses the standard scheduling code and
404 ;; behaves in much the same way as it would for a superscalar RISC
407 ;; (2) frv_reorg. This pass inserts nops into packets in order to meet
408 ;; the processor's issue requirements. It also has code to optimize
409 ;; the type of padding used to align labels.
411 ;; (3) frv_pack_insns. The final packing phase, which puts the
412 ;; instructions into assembly language order according to the
413 ;; "I0 F0/M0 ..." template above.
415 ;; In the ideal case, these three passes will agree on which instructions
416 ;; should be packed together, but this won't always happen. In particular:
418 ;; (a) (2) might not pack predicated instructions in the same way as (1).
419 ;; The scheduler tries to schedule predicated instructions for the
420 ;; worst case, assuming the predicate is true. However, if we have
421 ;; something like a predicated load, it isn't always possible to
422 ;; fill the load delay with useful instructions. (2) should then
423 ;; pack the user of the loaded value as aggressively as possible,
424 ;; in order to optimize the case when the predicate is false.
425 ;; See frv_pack_insn_p for more details.
427 ;; (b) The final shorten_branches pass runs between (2) and (3).
428 ;; Since (2) inserts nops, it is possible that some branches
429 ;; that were thought to be in range during (2) turned out to
430 ;; out-of-range in (3).
432 ;; All three passes use DFAs to model issue restrictions. The main
433 ;; question that the DFAs are supposed to answer is simply: can these
434 ;; instructions be packed together? The DFAs are not responsible for
435 ;; assigning instructions to execution units; that's the job of
436 ;; frv_sort_insn_group, see below for details.
438 ;; To get the best results, the DFAs should try to allow packets to
439 ;; be built in every possible order. This gives the scheduler more
440 ;; flexibility, removing the need for things like multipass lookahead.
441 ;; It also means we can take more advantage of inter-packet dependencies.
443 ;; For example, suppose we're compiling for the fr400 and we have:
446 ;; ldi @(gr6,gr0),gr4
448 ;; We can pack these instructions together by assigning the load to I0 and
449 ;; the addition to I1. However, because of the anti dependence between the
450 ;; two instructions, the scheduler must schedule the addition first.
451 ;; We should generally get better schedules if the DFA allows both
452 ;; (ldi, addi) and (addi, ldi), leaving the final packing pass to
453 ;; reorder the packet where appropriate.
455 ;; Almost all integer instructions can issue to any unit in the range I0
456 ;; to Ix, where the value of "x" depends on the type of instruction and
457 ;; on the target processor. The rules for other instruction groups are
460 ;; When the restrictions are as regular as this, we can get the desired
461 ;; behavior by claiming the DFA unit associated with the highest unused
462 ;; execution unit. For example, if an instruction can issue to I0 or I1,
463 ;; the DFA first tries to take the DFA unit associated with I1, and will
464 ;; only take I0's unit if I1 isn't free. (Note that, as mentioned above,
465 ;; the DFA does not assign instructions to units. An instruction that
466 ;; claims DFA unit I1 will not necessarily issue to I1 in the final packet.)
468 ;; There are some cases, such as the fr550 media restriction mentioned
469 ;; above, where the rule is not as simple as "any unit between 0 and X".
470 ;; Even so, allocating higher units first brings us close to the ideal.
472 ;; Having divided instructions into packets, passes (2) and (3) must
473 ;; assign instructions to specific execution units. They do this using
474 ;; the following algorithm:
476 ;; 1. Partition the instructions into groups (integer, float/media, etc.)
478 ;; 2. For each group of instructions:
480 ;; (a) Issue each instruction in the reset DFA state and use the
481 ;; DFA cpu_unit_query interface to find out which unit it picks
484 ;; (b) Sort the instructions into ascending order of picked units.
485 ;; Instructions that pick I1 first come after those that pick
486 ;; I0 first, and so on. Let S be the sorted sequence and S[i]
487 ;; be the ith element of it (counting from zero).
489 ;; (c) If this is the control or branch group, goto (i)
491 ;; (d) Find the largest L such that S[0]...S[L-1] can be issued
492 ;; consecutively from the reset state and such that the DFA
493 ;; claims unit X when S[X] is added. Let D be the DFA state
494 ;; after instructions S[0]...S[L-1] have been issued.
496 ;; (e) If L is the length of S, goto (i)
498 ;; (f) Let U be the number of units belonging to this group and #S be
499 ;; the length of S. Create a new sequence S' by concatenating
500 ;; S[L]...S[#S-1] and (U - #S) nops.
502 ;; (g) For each permutation S'' of S', try issuing S'' from last to
503 ;; first, starting with state D. See if the DFA claims unit
504 ;; X + L when each S''[X] is added. If so, set S to the
505 ;; concatenation of S[0]...S[L-1] and S'', then goto (i).
507 ;; (h) If (g) found no permutation, abort.
509 ;; (i) S is now the sorted sequence for this group, meaning that S[X]
510 ;; issues to unit X. Trim any unwanted nops from the end of S.
512 ;; The sequence calculated by (b) is trivially correct for control
513 ;; instructions since they can't be packed. It is also correct for branch
514 ;; instructions due to their simple issue requirements. For integer and
515 ;; floating-point/media instructions, the sequence calculated by (b) is
516 ;; often the correct answer; the rest of the algorithm is optimized for
517 ;; the case in which it is correct.
519 ;; If there were no irregularities in the issue restrictions then step
520 ;; (d) would not be needed. It is mainly there to cope with the fr550
521 ;; integer restrictions, where a store can issue to I1, but only if a store
522 ;; also issues to I0. (Note that if a packet has two stores, they will be
523 ;; at the beginning of the sequence calculated by (b).) It also copes
524 ;; with fr400 M-2 instructions, which must issue to M0, and which cannot
525 ;; be issued together with an mnop in M1.
527 ;; Step (g) is the main one for integer and float/media instructions.
528 ;; The first permutation it tries is S' itself (because, as noted above,
529 ;; the sequence calculated by (b) is often correct). If S' doesn't work,
530 ;; the implementation tries varying the beginning of the sequence first.
531 ;; Thus the nops towards the end of the sequence will only move to lower
532 ;; positions if absolutely necessary.
534 ;; The algorithm is theoretically exponential in the number of instructions
535 ;; in a group, although it's only O(n log(n)) if the sequence calculated by
536 ;; (b) is acceptable. In practice, the algorithm completes quickly even
537 ;; in the rare cases where (g) needs to try other permutations.
538 (define_automaton "integer, float_media, branch, control, idiv, div")
540 ;; The main issue units. Note that not all units are available on
542 (define_query_cpu_unit "i0,i1,i2,i3" "integer")
543 (define_query_cpu_unit "f0,f1,f2,f3" "float_media")
544 (define_query_cpu_unit "b0,b1" "branch")
545 (define_query_cpu_unit "c" "control")
548 (define_cpu_unit "idiv1,idiv2" "idiv")
549 (define_cpu_unit "div1,div2,root" "div")
551 ;; Control instructions cannot be packed with others.
552 (define_reservation "control" "i0+i1+i2+i3+f0+f1+f2+f3+b0+b1")
554 ;; Generic reservation for control insns
555 (define_insn_reservation "control" 1
556 (eq_attr "type" "trap,spr,unknown,multi")
559 ;; Reservation for relaxable calls to gettlsoff.
560 (define_insn_reservation "load_or_call" 3
561 (eq_attr "type" "load_or_call")
564 ;; ::::::::::::::::::::
566 ;; :: Generic/FR500 scheduler description
568 ;; ::::::::::::::::::::
571 ;; Synthetic units used to describe issue restrictions.
572 (define_automaton "fr500_integer")
573 (define_cpu_unit "fr500_load0,fr500_load1,fr500_store0" "fr500_integer")
574 (exclusion_set "fr500_load0,fr500_load1" "fr500_store0")
576 (define_bypass 0 "fr500_i1_sethi" "fr500_i1_setlo")
577 (define_insn_reservation "fr500_i1_sethi" 1
578 (and (eq_attr "cpu" "generic,fr500,tomcat")
579 (eq_attr "type" "sethi"))
582 (define_insn_reservation "fr500_i1_setlo" 1
583 (and (eq_attr "cpu" "generic,fr500,tomcat")
584 (eq_attr "type" "setlo"))
587 (define_insn_reservation "fr500_i1_int" 1
588 (and (eq_attr "cpu" "generic,fr500,tomcat")
589 (eq_attr "type" "int"))
592 (define_insn_reservation "fr500_i1_mul" 3
593 (and (eq_attr "cpu" "generic,fr500,tomcat")
594 (eq_attr "type" "mul"))
597 (define_insn_reservation "fr500_i1_div" 19
598 (and (eq_attr "cpu" "generic,fr500,tomcat")
599 (eq_attr "type" "div"))
600 "(i1|i0),(idiv1*18|idiv2*18)")
602 (define_insn_reservation "fr500_i2" 4
603 (and (eq_attr "cpu" "generic,fr500,tomcat")
604 (eq_attr "type" "gload,fload"))
605 "(i1|i0) + (fr500_load0|fr500_load1)")
607 (define_insn_reservation "fr500_i3" 0
608 (and (eq_attr "cpu" "generic,fr500,tomcat")
609 (eq_attr "type" "gstore,fstore"))
612 (define_insn_reservation "fr500_i4" 3
613 (and (eq_attr "cpu" "generic,fr500,tomcat")
614 (eq_attr "type" "movgf,movfg"))
617 (define_insn_reservation "fr500_i5" 0
618 (and (eq_attr "cpu" "generic,fr500,tomcat")
619 (eq_attr "type" "jumpl"))
623 ;; Branch-instructions
625 (define_insn_reservation "fr500_branch" 0
626 (and (eq_attr "cpu" "generic,fr500,tomcat")
627 (eq_attr "type" "jump,branch,ccr"))
630 (define_insn_reservation "fr500_call" 0
631 (and (eq_attr "cpu" "generic,fr500,tomcat")
632 (eq_attr "type" "call"))
635 ;; Floating point insns. The default latencies are for non-media
636 ;; instructions; media instructions incur an extra cycle.
638 (define_bypass 4 "fr500_farith" "fr500_m1,fr500_m2,fr500_m3,
639 fr500_m4,fr500_m5,fr500_m6")
640 (define_insn_reservation "fr500_farith" 3
641 (and (eq_attr "cpu" "generic,fr500,tomcat")
642 (eq_attr "type" "fnop,fsconv,fsadd,fsmul,fsmadd,fdconv,fdadd,fdmul,fdmadd"))
645 (define_insn_reservation "fr500_fcmp" 4
646 (and (eq_attr "cpu" "generic,fr500,tomcat")
647 (eq_attr "type" "fscmp,fdcmp"))
650 (define_bypass 11 "fr500_fdiv" "fr500_m1,fr500_m2,fr500_m3,
651 fr500_m4,fr500_m5,fr500_m6")
652 (define_insn_reservation "fr500_fdiv" 10
653 (and (eq_attr "cpu" "generic,fr500,tomcat")
654 (eq_attr "type" "fsdiv,fddiv"))
655 "(f1|f0),(div1*9 | div2*9)")
657 (define_bypass 16 "fr500_froot" "fr500_m1,fr500_m2,fr500_m3,
658 fr500_m4,fr500_m5,fr500_m6")
659 (define_insn_reservation "fr500_froot" 15
660 (and (eq_attr "cpu" "generic,fr500,tomcat")
661 (eq_attr "type" "sqrt_single,sqrt_double"))
664 ;; Media insns. Conflict table is as follows:
674 ;; where X indicates an invalid combination.
676 ;; Target registers are as follows:
685 ;; The default FPR latencies are for integer instructions.
686 ;; Floating-point instructions need one cycle more and media
687 ;; instructions need one cycle less.
688 (define_automaton "fr500_media")
689 (define_cpu_unit "fr500_m2_0,fr500_m2_1" "fr500_media")
690 (define_cpu_unit "fr500_m3_0,fr500_m3_1" "fr500_media")
691 (define_cpu_unit "fr500_m4_0,fr500_m4_1" "fr500_media")
692 (define_cpu_unit "fr500_m5" "fr500_media")
693 (define_cpu_unit "fr500_m6" "fr500_media")
695 (exclusion_set "fr500_m5,fr500_m6" "fr500_m2_0,fr500_m2_1,
696 fr500_m3_0,fr500_m3_1")
697 (exclusion_set "fr500_m6" "fr500_m4_0,fr500_m4_1,fr500_m5")
699 (define_bypass 2 "fr500_m1" "fr500_m1,fr500_m2,fr500_m3,
700 fr500_m4,fr500_m5,fr500_m6")
701 (define_bypass 4 "fr500_m1" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
702 (define_insn_reservation "fr500_m1" 3
703 (and (eq_attr "cpu" "generic,fr500,tomcat")
704 (eq_attr "type" "mnop,mlogic,maveh,msath,maddh,mqaddh"))
707 (define_bypass 2 "fr500_m2" "fr500_m1,fr500_m2,fr500_m3,
708 fr500_m4,fr500_m5,fr500_m6")
709 (define_bypass 4 "fr500_m2" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
710 (define_insn_reservation "fr500_m2" 3
711 (and (eq_attr "cpu" "generic,fr500,tomcat")
712 (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
713 "(f1|f0) + (fr500_m2_0|fr500_m2_1)")
715 (define_bypass 1 "fr500_m3" "fr500_m4")
716 (define_insn_reservation "fr500_m3" 2
717 (and (eq_attr "cpu" "generic,fr500,tomcat")
718 (eq_attr "type" "mclracc,mwtacc"))
719 "(f1|f0) + (fr500_m3_0|fr500_m3_1)")
721 (define_bypass 1 "fr500_m4" "fr500_m4")
722 (define_insn_reservation "fr500_m4" 2
723 (and (eq_attr "cpu" "generic,fr500,tomcat")
724 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
725 "(f1|f0) + (fr500_m4_0|fr500_m4_1)")
727 (define_bypass 2 "fr500_m5" "fr500_m1,fr500_m2,fr500_m3,
728 fr500_m4,fr500_m5,fr500_m6")
729 (define_bypass 4 "fr500_m5" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
730 (define_insn_reservation "fr500_m5" 3
731 (and (eq_attr "cpu" "generic,fr500,tomcat")
732 (eq_attr "type" "mdpackh"))
733 "(f1|f0) + fr500_m5")
735 (define_bypass 1 "fr500_m6" "fr500_m4")
736 (define_insn_reservation "fr500_m6" 2
737 (and (eq_attr "cpu" "generic,fr500,tomcat")
738 (eq_attr "type" "mclracca"))
739 "(f1|f0) + fr500_m6")
741 ;; ::::::::::::::::::::
743 ;; :: FR400 scheduler description
745 ;; ::::::::::::::::::::
747 ;; Category 2 media instructions use both media units, but can be packed
748 ;; with non-media instructions. Use fr400_m1unit to claim the M1 unit
749 ;; without claiming a slot.
751 ;; Name Class Units Latency
752 ;; ==== ===== ===== =======
754 ;; sethi I1 I0/I1 0 -- does not interfere with setlo
759 ;; fload I2 I0 4 -- only 3 if read by a media insn
760 ;; gstore I3 I0 0 -- provides no result
761 ;; fstore I3 I0 0 -- provides no result
764 ;; jumpl I5 I0 0 -- provides no result
766 ;; (*) The results of these instructions can be read one cycle earlier
767 ;; than indicated. The penalty given is for instructions with write-after-
768 ;; write dependencies.
770 ;; The FR400 can only do loads and stores in I0, so we there's no danger
771 ;; of memory unit collision in the same packet. There's only one divide
774 (define_automaton "fr400_integer")
775 (define_cpu_unit "fr400_mul" "fr400_integer")
777 (define_insn_reservation "fr400_i1_int" 1
778 (and (eq_attr "cpu" "fr400,fr405,fr450")
779 (eq_attr "type" "int"))
782 (define_bypass 0 "fr400_i1_sethi" "fr400_i1_setlo")
783 (define_insn_reservation "fr400_i1_sethi" 1
784 (and (eq_attr "cpu" "fr400,fr405,fr450")
785 (eq_attr "type" "sethi"))
788 (define_insn_reservation "fr400_i1_setlo" 1
789 (and (eq_attr "cpu" "fr400,fr405,fr450")
790 (eq_attr "type" "setlo"))
793 ;; 3 is the worst case (write-after-write hazard).
794 (define_insn_reservation "fr400_i1_mul" 3
795 (and (eq_attr "cpu" "fr400,fr405")
796 (eq_attr "type" "mul"))
799 (define_insn_reservation "fr450_i1_mul" 2
800 (and (eq_attr "cpu" "fr450")
801 (eq_attr "type" "mul"))
804 (define_bypass 1 "fr400_i1_macc" "fr400_i1_macc")
805 (define_insn_reservation "fr400_i1_macc" 2
806 (and (eq_attr "cpu" "fr405,fr450")
807 (eq_attr "type" "macc"))
808 "(i0|i1) + fr400_mul")
810 (define_insn_reservation "fr400_i1_scan" 1
811 (and (eq_attr "cpu" "fr400,fr405,fr450")
812 (eq_attr "type" "scan"))
815 (define_insn_reservation "fr400_i1_cut" 2
816 (and (eq_attr "cpu" "fr405,fr450")
817 (eq_attr "type" "cut"))
820 ;; 20 is for a write-after-write hazard.
821 (define_insn_reservation "fr400_i1_div" 20
822 (and (eq_attr "cpu" "fr400,fr405")
823 (eq_attr "type" "div"))
826 (define_insn_reservation "fr450_i1_div" 19
827 (and (eq_attr "cpu" "fr450")
828 (eq_attr "type" "div"))
831 ;; 4 is for a write-after-write hazard.
832 (define_insn_reservation "fr400_i2" 4
833 (and (eq_attr "cpu" "fr400,fr405")
834 (eq_attr "type" "gload,fload"))
837 (define_insn_reservation "fr450_i2_gload" 3
838 (and (eq_attr "cpu" "fr450")
839 (eq_attr "type" "gload"))
842 ;; 4 is for a write-after-write hazard.
843 (define_insn_reservation "fr450_i2_fload" 4
844 (and (eq_attr "cpu" "fr450")
845 (eq_attr "type" "fload"))
848 (define_insn_reservation "fr400_i3" 0
849 (and (eq_attr "cpu" "fr400,fr405,fr450")
850 (eq_attr "type" "gstore,fstore"))
853 ;; 3 is for a write-after-write hazard.
854 (define_insn_reservation "fr400_i4" 3
855 (and (eq_attr "cpu" "fr400,fr405")
856 (eq_attr "type" "movfg,movgf"))
859 (define_insn_reservation "fr450_i4_movfg" 2
860 (and (eq_attr "cpu" "fr450")
861 (eq_attr "type" "movfg"))
864 ;; 3 is for a write-after-write hazard.
865 (define_insn_reservation "fr450_i4_movgf" 3
866 (and (eq_attr "cpu" "fr450")
867 (eq_attr "type" "movgf"))
870 (define_insn_reservation "fr400_i5" 0
871 (and (eq_attr "cpu" "fr400,fr405,fr450")
872 (eq_attr "type" "jumpl"))
875 ;; The bypass between FPR loads and media instructions, described above.
879 "fr400_m1_1,fr400_m1_2,\
880 fr400_m2_1,fr400_m2_2,\
881 fr400_m3_1,fr400_m3_2,\
882 fr400_m4_1,fr400_m4_2,\
885 ;; The branch instructions all use the B unit and produce no result.
887 (define_insn_reservation "fr400_b" 0
888 (and (eq_attr "cpu" "fr400,fr405,fr450")
889 (eq_attr "type" "jump,branch,ccr,call"))
892 ;; FP->FP moves are marked as "fsconv" instructions in the define_insns
893 ;; below, but are implemented on the FR400 using "mlogic" instructions.
894 ;; It's easier to class "fsconv" as a "m1:1" instruction than provide
895 ;; separate define_insns for the FR400.
897 ;; M1 instructions store their results in FPRs. Any instruction can read
898 ;; the result in the following cycle, so no penalty occurs.
900 (define_automaton "fr400_media")
901 (define_cpu_unit "fr400_m1a,fr400_m1b,fr400_m2a" "fr400_media")
902 (exclusion_set "fr400_m1a,fr400_m1b" "fr400_m2a")
904 (define_reservation "fr400_m1" "(f1|f0) + (fr400_m1a|fr400_m1b)")
905 (define_reservation "fr400_m2" "f0 + fr400_m2a")
907 (define_insn_reservation "fr400_m1_1" 1
908 (and (eq_attr "cpu" "fr400,fr405")
909 (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset"))
912 (define_insn_reservation "fr400_m1_2" 1
913 (and (eq_attr "cpu" "fr400,fr405")
914 (eq_attr "type" "mqaddh,mqsath,mqlimh,mqshift"))
917 ;; M2 instructions store their results in accumulators, which are read
918 ;; by M2 or M4 media commands. M2 instructions can read the results in
919 ;; the following cycle, but M4 instructions must wait a cycle more.
922 "fr400_m2_1,fr400_m2_2"
923 "fr400_m2_1,fr400_m2_2")
925 (define_insn_reservation "fr400_m2_1" 2
926 (and (eq_attr "cpu" "fr400,fr405")
927 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))
930 (define_insn_reservation "fr400_m2_2" 2
931 (and (eq_attr "cpu" "fr400,fr405")
932 (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))
935 ;; For our purposes, there seems to be little real difference between
936 ;; M1 and M3 instructions. Keep them separate anyway in case the distinction
939 (define_insn_reservation "fr400_m3_1" 1
940 (and (eq_attr "cpu" "fr400,fr405")
941 (eq_attr "type" "mpackh,mrot,mshift,mexpdhw"))
944 (define_insn_reservation "fr400_m3_2" 1
945 (and (eq_attr "cpu" "fr400,fr405")
946 (eq_attr "type" "munpackh,mdpackh,mbhconv,mexpdhd,mwcut,mdrot,mcpl"))
949 ;; M4 instructions write to accumulators or FPRs. MOVFG and STF
950 ;; instructions can read an FPR result in the following cycle, but
951 ;; M-unit instructions must wait a cycle more for either kind of result.
953 (define_bypass 1 "fr400_m4_1,fr400_m4_2" "fr400_i3,fr400_i4")
955 (define_insn_reservation "fr400_m4_1" 2
956 (and (eq_attr "cpu" "fr400,fr405")
957 (eq_attr "type" "mrdacc,mcut,mclracc"))
960 (define_insn_reservation "fr400_m4_2" 2
961 (and (eq_attr "cpu" "fr400,fr405")
962 (eq_attr "type" "mclracca,mdcut"))
965 ;; M5 instructions always incur a 1-cycle penalty.
967 (define_insn_reservation "fr400_m5" 2
968 (and (eq_attr "cpu" "fr400,fr405")
969 (eq_attr "type" "mwtacc"))
972 ;; ::::::::::::::::::::
974 ;; :: FR450 media scheduler description
976 ;; ::::::::::::::::::::
978 ;; The FR451 media restrictions are similar to the FR400's, but not as
979 ;; strict and not as regular. There are 6 categories with the following
983 ;; M-1 M-2 M-3 M-4 M-5 M-6
991 ;; where "x" indicates a conflict.
993 ;; There is no difference between M-1 and M-3 as far as issue
994 ;; restrictions are concerned, so they are combined as "m13".
996 ;; Units for odd-numbered categories. There can be two of these
998 (define_cpu_unit "fr450_m13a,fr450_m13b" "float_media")
999 (define_cpu_unit "fr450_m5a,fr450_m5b" "float_media")
1001 ;; Units for even-numbered categories. There can only be one per packet.
1002 (define_cpu_unit "fr450_m2a,fr450_m4a,fr450_m6a" "float_media")
1004 ;; Enforce the restriction matrix above.
1005 (exclusion_set "fr450_m2a,fr450_m4a,fr450_m6a" "fr450_m13a,fr450_m13b")
1006 (exclusion_set "fr450_m2a,fr450_m6a" "fr450_m5a,fr450_m5b")
1007 (exclusion_set "fr450_m4a,fr450_m6a" "fr450_m2a")
1009 (define_reservation "fr450_m13" "(f1|f0) + (fr450_m13a|fr450_m13b)")
1010 (define_reservation "fr450_m2" "f0 + fr450_m2a")
1011 (define_reservation "fr450_m4" "f0 + fr450_m4a")
1012 (define_reservation "fr450_m5" "(f1|f0) + (fr450_m5a|fr450_m5b)")
1013 (define_reservation "fr450_m6" "(f0|f1) + fr450_m6a")
1015 ;; MD-1, MD-3 and MD-8 instructions, which are the same as far
1016 ;; as scheduling is concerned. The inputs and outputs are FPRs.
1017 ;; Instructions that have 32-bit inputs and outputs belong to M-1 while
1018 ;; the rest belong to M-2.
1020 ;; ??? Arithmetic shifts (MD-6) have an extra cycle latency, but we don't
1021 ;; make the distinction between them and logical shifts.
1022 (define_insn_reservation "fr450_md138_1" 1
1023 (and (eq_attr "cpu" "fr450")
1024 (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset,
1025 mrot,mshift,mexpdhw,mpackh"))
1028 (define_insn_reservation "fr450_md138_2" 1
1029 (and (eq_attr "cpu" "fr450")
1030 (eq_attr "type" "mqaddh,mqsath,mqlimh,
1031 mdrot,mwcut,mqshift,mexpdhd,
1032 munpackh,mdpackh,mbhconv,mcpl"))
1035 ;; MD-2 instructions. These take FPR or ACC inputs and produce an ACC output.
1036 ;; Instructions that write to double ACCs belong to M-3 while those that write
1037 ;; to quad ACCs belong to M-4.
1038 (define_insn_reservation "fr450_md2_3" 2
1039 (and (eq_attr "cpu" "fr450")
1040 (eq_attr "type" "mmulh,mmach,mcpx,mmulxh,mmrdh,maddacc"))
1043 (define_insn_reservation "fr450_md2_4" 2
1044 (and (eq_attr "cpu" "fr450")
1045 (eq_attr "type" "mqmulh,mqmach,mqcpx,mqmulxh,mdaddacc"))
1048 ;; Another MD-2 instruction can use the result on the following cycle.
1049 (define_bypass 1 "fr450_md2_3,fr450_md2_4" "fr450_md2_3,fr450_md2_4")
1051 ;; MD-4 instructions that write to ACCs.
1052 (define_insn_reservation "fr450_md4_3" 2
1053 (and (eq_attr "cpu" "fr450")
1054 (eq_attr "type" "mclracc"))
1057 (define_insn_reservation "fr450_md4_4" 3
1058 (and (eq_attr "cpu" "fr450")
1059 (eq_attr "type" "mclracca"))
1062 ;; MD-4 instructions that write to FPRs.
1063 (define_insn_reservation "fr450_md4_1" 2
1064 (and (eq_attr "cpu" "fr450")
1065 (eq_attr "type" "mcut"))
1068 (define_insn_reservation "fr450_md4_5" 2
1069 (and (eq_attr "cpu" "fr450")
1070 (eq_attr "type" "mrdacc"))
1073 (define_insn_reservation "fr450_md4_6" 2
1074 (and (eq_attr "cpu" "fr450")
1075 (eq_attr "type" "mdcut"))
1078 ;; Integer instructions can read the FPR result of an MD-4 instruction on
1079 ;; the following cycle.
1080 (define_bypass 1 "fr450_md4_1,fr450_md4_5,fr450_md4_6"
1081 "fr400_i3,fr450_i4_movfg")
1083 ;; MD-5 instructions, which belong to M-3. They take FPR inputs and
1085 (define_insn_reservation "fr450_md5_3" 2
1086 (and (eq_attr "cpu" "fr450")
1087 (eq_attr "type" "mwtacc"))
1090 ;; ::::::::::::::::::::
1092 ;; :: FR550 scheduler description
1094 ;; ::::::::::::::::::::
1096 ;; Prevent loads and stores from being issued in the same packet.
1097 ;; These units must go into the generic "integer" reservation because
1098 ;; of the constraints on fr550_store0 and fr550_store1.
1099 (define_cpu_unit "fr550_load0,fr550_load1" "integer")
1100 (define_cpu_unit "fr550_store0,fr550_store1" "integer")
1101 (exclusion_set "fr550_load0,fr550_load1" "fr550_store0,fr550_store1")
1103 ;; A store can only issue to I1 if one has also been issued to I0.
1104 (presence_set "fr550_store1" "fr550_store0")
1106 (define_bypass 0 "fr550_sethi" "fr550_setlo")
1107 (define_insn_reservation "fr550_sethi" 1
1108 (and (eq_attr "cpu" "fr550")
1109 (eq_attr "type" "sethi"))
1112 (define_insn_reservation "fr550_setlo" 1
1113 (and (eq_attr "cpu" "fr550")
1114 (eq_attr "type" "setlo"))
1117 (define_insn_reservation "fr550_int" 1
1118 (and (eq_attr "cpu" "fr550")
1119 (eq_attr "type" "int"))
1122 (define_insn_reservation "fr550_mul" 2
1123 (and (eq_attr "cpu" "fr550")
1124 (eq_attr "type" "mul"))
1127 (define_insn_reservation "fr550_div" 19
1128 (and (eq_attr "cpu" "fr550")
1129 (eq_attr "type" "div"))
1130 "(i1|i0),(idiv1*18 | idiv2*18)")
1132 (define_insn_reservation "fr550_load" 3
1133 (and (eq_attr "cpu" "fr550")
1134 (eq_attr "type" "gload,fload"))
1135 "(i1|i0)+(fr550_load0|fr550_load1)")
1137 ;; We can only issue a store to I1 if one was also issued to I0.
1138 ;; This means that, as far as frv_reorder_packet is concerned,
1139 ;; the instruction has the same priority as an I0-only instruction.
1140 (define_insn_reservation "fr550_store" 1
1141 (and (eq_attr "cpu" "fr550")
1142 (eq_attr "type" "gstore,fstore"))
1143 "(i0+fr550_store0)|(i1+fr550_store1)")
1145 (define_insn_reservation "fr550_transfer" 2
1146 (and (eq_attr "cpu" "fr550")
1147 (eq_attr "type" "movgf,movfg"))
1150 (define_insn_reservation "fr550_jumpl" 0
1151 (and (eq_attr "cpu" "fr550")
1152 (eq_attr "type" "jumpl"))
1155 (define_cpu_unit "fr550_ccr0,fr550_ccr1" "float_media")
1157 (define_insn_reservation "fr550_branch" 0
1158 (and (eq_attr "cpu" "fr550")
1159 (eq_attr "type" "jump,branch"))
1162 (define_insn_reservation "fr550_ccr" 0
1163 (and (eq_attr "cpu" "fr550")
1164 (eq_attr "type" "ccr"))
1165 "(b1|b0) + (fr550_ccr1|fr550_ccr0)")
1167 (define_insn_reservation "fr550_call" 0
1168 (and (eq_attr "cpu" "fr550")
1169 (eq_attr "type" "call"))
1172 (define_automaton "fr550_float_media")
1173 (define_cpu_unit "fr550_add0,fr550_add1" "fr550_float_media")
1175 ;; There are three possible combinations of floating-point/media instructions:
1177 ;; - one media and one float
1178 ;; - up to four float, no media
1179 ;; - up to four media, no float
1180 (define_cpu_unit "fr550_f0,fr550_f1,fr550_f2,fr550_f3" "fr550_float_media")
1181 (define_cpu_unit "fr550_m0,fr550_m1,fr550_m2,fr550_m3" "fr550_float_media")
1182 (exclusion_set "fr550_f1,fr550_f2,fr550_f3" "fr550_m1,fr550_m2,fr550_m3")
1184 (define_reservation "fr550_float" "fr550_f0|fr550_f1|fr550_f2|fr550_f3")
1185 (define_reservation "fr550_media" "fr550_m0|fr550_m1|fr550_m2|fr550_m3")
1187 (define_insn_reservation "fr550_f1" 0
1188 (and (eq_attr "cpu" "fr550")
1189 (eq_attr "type" "fnop"))
1190 "(f3|f2|f1|f0) + fr550_float")
1192 (define_insn_reservation "fr550_f2" 3
1193 (and (eq_attr "cpu" "fr550")
1194 (eq_attr "type" "fsconv,fsadd,fscmp"))
1195 "(f3|f2|f1|f0) + (fr550_add0|fr550_add1) + fr550_float")
1197 (define_insn_reservation "fr550_f3_mul" 3
1198 (and (eq_attr "cpu" "fr550")
1199 (eq_attr "type" "fsmul"))
1200 "(f1|f0) + fr550_float")
1202 (define_insn_reservation "fr550_f3_div" 10
1203 (and (eq_attr "cpu" "fr550")
1204 (eq_attr "type" "fsdiv"))
1205 "(f1|f0) + fr550_float")
1207 (define_insn_reservation "fr550_f3_sqrt" 15
1208 (and (eq_attr "cpu" "fr550")
1209 (eq_attr "type" "sqrt_single"))
1210 "(f1|f0) + fr550_float")
1212 ;; Synthetic units for enforcing media issue restrictions. Certain types
1213 ;; of insn in M2 conflict with certain types in M0:
1216 ;; MNOP MALU MSFT MMAC MSET
1219 ;; M0 MSFT - - x - x
1223 ;; where "x" indicates a conflict. The same restrictions apply to
1226 ;; In addition -- and this is the awkward bit! -- instructions that
1227 ;; access ACC0-3 can only issue to M0 or M2. Those that access ACC4-7
1228 ;; can only issue to M1 or M3. We refer to such instructions as "even"
1229 ;; and "odd" respectively.
1230 (define_cpu_unit "fr550_malu0,fr550_malu1" "float_media")
1231 (define_cpu_unit "fr550_malu2,fr550_malu3" "float_media")
1232 (define_cpu_unit "fr550_msft0,fr550_msft1" "float_media")
1233 (define_cpu_unit "fr550_mmac0,fr550_mmac1" "float_media")
1234 (define_cpu_unit "fr550_mmac2,fr550_mmac3" "float_media")
1235 (define_cpu_unit "fr550_mset0,fr550_mset1" "float_media")
1236 (define_cpu_unit "fr550_mset2,fr550_mset3" "float_media")
1238 (exclusion_set "fr550_malu0" "fr550_malu2")
1239 (exclusion_set "fr550_malu1" "fr550_malu3")
1241 (exclusion_set "fr550_msft0" "fr550_mset2")
1242 (exclusion_set "fr550_msft1" "fr550_mset3")
1244 (exclusion_set "fr550_mmac0" "fr550_mmac2")
1245 (exclusion_set "fr550_mmac1" "fr550_mmac3")
1247 ;; If an MSFT or MMAC instruction issues to a unit other than M0, we may
1248 ;; need to insert some nops. In the worst case, the packet will end up
1249 ;; having 4 integer instructions and 4 media instructions, leaving no
1250 ;; room for any branch instructions that the DFA might have accepted.
1252 ;; This doesn't matter for JUMP_INSNs and CALL_INSNs because they are
1253 ;; always the last instructions to be passed to the DFA, and could be
1254 ;; pushed out to a separate packet once the nops have been added.
1255 ;; However, it does cause problems for ccr instructions since they
1256 ;; can occur anywhere in the unordered packet.
1257 (exclusion_set "fr550_msft1,fr550_mmac1,fr550_mmac2,fr550_mmac3"
1258 "fr550_ccr0,fr550_ccr1")
1260 (define_reservation "fr550_malu"
1261 "(f3 + fr550_malu3) | (f2 + fr550_malu2)
1262 | (f1 + fr550_malu1) | (f0 + fr550_malu0)")
1264 (define_reservation "fr550_msft_even"
1267 (define_reservation "fr550_msft_odd"
1270 (define_reservation "fr550_msft_either"
1271 "(f1 + fr550_msft1) | (f0 + fr550_msft0)")
1273 (define_reservation "fr550_mmac_even"
1274 "(f2 + fr550_mmac2) | (f0 + fr550_mmac0)")
1276 (define_reservation "fr550_mmac_odd"
1277 "(f3 + fr550_mmac3) | (f1 + fr550_mmac1)")
1279 (define_reservation "fr550_mset"
1280 "(f3 + fr550_mset3) | (f2 + fr550_mset2)
1281 | (f1 + fr550_mset1) | (f0 + fr550_mset0)")
1283 (define_insn_reservation "fr550_mnop" 0
1284 (and (eq_attr "cpu" "fr550")
1285 (eq_attr "type" "mnop"))
1286 "fr550_media + (f3|f2|f1|f0)")
1288 (define_insn_reservation "fr550_malu" 2
1289 (and (eq_attr "cpu" "fr550")
1290 (eq_attr "type" "mlogic,maveh,msath,mabsh,maddh,mqaddh,mqsath"))
1291 "fr550_media + fr550_malu")
1293 ;; These insns only operate on FPRs and so don't need to be classified
1295 (define_insn_reservation "fr550_msft_1_either" 2
1296 (and (eq_attr "cpu" "fr550")
1297 (eq_attr "type" "mrot,mwcut,mshift,mexpdhw,mexpdhd,mpackh,
1298 munpackh,mdpackh,mbhconv,mdrot,mcpl"))
1299 "fr550_media + fr550_msft_either")
1301 ;; These insns read from ACC0-3.
1302 (define_insn_reservation "fr550_msft_1_even" 2
1303 (and (eq_attr "cpu" "fr550")
1304 (and (eq_attr "type" "mcut,mrdacc,mdcut")
1305 (eq_attr "acc_group" "even")))
1306 "fr550_media + fr550_msft_even")
1308 ;; These insns read from ACC4-7.
1309 (define_insn_reservation "fr550_msft_1_odd" 2
1310 (and (eq_attr "cpu" "fr550")
1311 (and (eq_attr "type" "mcut,mrdacc,mdcut")
1312 (eq_attr "acc_group" "odd")))
1313 "fr550_media + fr550_msft_odd")
1315 ;; MCLRACC with A=1 can issue to either M0 or M1.
1316 (define_insn_reservation "fr550_msft_2_either" 2
1317 (and (eq_attr "cpu" "fr550")
1318 (eq_attr "type" "mclracca"))
1319 "fr550_media + fr550_msft_either")
1321 ;; These insns write to ACC0-3.
1322 (define_insn_reservation "fr550_msft_2_even" 2
1323 (and (eq_attr "cpu" "fr550")
1324 (and (eq_attr "type" "mclracc,mwtacc")
1325 (eq_attr "acc_group" "even")))
1326 "fr550_media + fr550_msft_even")
1328 ;; These insns write to ACC4-7.
1329 (define_insn_reservation "fr550_msft_2_odd" 2
1330 (and (eq_attr "cpu" "fr550")
1331 (and (eq_attr "type" "mclracc,mwtacc")
1332 (eq_attr "acc_group" "odd")))
1333 "fr550_media + fr550_msft_odd")
1335 ;; These insns read from and write to ACC0-3.
1336 (define_insn_reservation "fr550_mmac_even" 2
1337 (and (eq_attr "cpu" "fr550")
1338 (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1339 maddacc,mdaddacc,mcpx,mqcpx")
1340 (eq_attr "acc_group" "even")))
1341 "fr550_media + fr550_mmac_even")
1343 ;; These insns read from and write to ACC4-7.
1344 (define_insn_reservation "fr550_mmac_odd" 2
1345 (and (eq_attr "cpu" "fr550")
1346 (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1347 maddacc,mdaddacc,mcpx,mqcpx")
1348 (eq_attr "acc_group" "odd")))
1349 "fr550_media + fr550_mmac_odd")
1351 (define_insn_reservation "fr550_mset" 1
1352 (and (eq_attr "cpu" "fr550")
1353 (eq_attr "type" "mset"))
1354 "fr550_media + fr550_mset")
1356 ;; ::::::::::::::::::::
1358 ;; :: Simple/FR300 scheduler description
1360 ;; ::::::::::::::::::::
1362 ;; Fr300 or simple processor. To describe it as 1 insn issue
1363 ;; processor, we use control unit.
1365 (define_insn_reservation "fr300_lat1" 1
1366 (and (eq_attr "cpu" "fr300,simple")
1367 (eq_attr "type" "!gload,fload,movfg,movgf"))
1370 (define_insn_reservation "fr300_lat2" 2
1371 (and (eq_attr "cpu" "fr300,simple")
1372 (eq_attr "type" "gload,fload,movfg,movgf"))
1376 ;; ::::::::::::::::::::
1380 ;; ::::::::::::::::::::
1382 ;; The insn attribute mechanism can be used to specify the requirements for
1383 ;; delay slots, if any, on a target machine. An instruction is said to require
1384 ;; a "delay slot" if some instructions that are physically after the
1385 ;; instruction are executed as if they were located before it. Classic
1386 ;; examples are branch and call instructions, which often execute the following
1387 ;; instruction before the branch or call is performed.
1389 ;; On some machines, conditional branch instructions can optionally "annul"
1390 ;; instructions in the delay slot. This means that the instruction will not be
1391 ;; executed for certain branch outcomes. Both instructions that annul if the
1392 ;; branch is true and instructions that annul if the branch is false are
1395 ;; Delay slot scheduling differs from instruction scheduling in that
1396 ;; determining whether an instruction needs a delay slot is dependent only
1397 ;; on the type of instruction being generated, not on data flow between the
1398 ;; instructions. See the next section for a discussion of data-dependent
1399 ;; instruction scheduling.
1401 ;; The requirement of an insn needing one or more delay slots is indicated via
1402 ;; the `define_delay' expression. It has the following form:
1404 ;; (define_delay TEST
1405 ;; [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
1406 ;; DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
1409 ;; TEST is an attribute test that indicates whether this `define_delay' applies
1410 ;; to a particular insn. If so, the number of required delay slots is
1411 ;; determined by the length of the vector specified as the second argument. An
1412 ;; insn placed in delay slot N must satisfy attribute test DELAY-N.
1413 ;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
1414 ;; if the branch is true. Similarly, ANNUL-FALSE-N specifies which insns in
1415 ;; the delay slot may be annulled if the branch is false. If annulling is not
1416 ;; supported for that delay slot, `(nil)' should be coded.
1418 ;; For example, in the common case where branch and call insns require a single
1419 ;; delay slot, which may contain any insn other than a branch or call, the
1420 ;; following would be placed in the `md' file:
1422 ;; (define_delay (eq_attr "type" "branch,call")
1423 ;; [(eq_attr "type" "!branch,call") (nil) (nil)])
1425 ;; Multiple `define_delay' expressions may be specified. In this case, each
1426 ;; such expression specifies different delay slot requirements and there must
1427 ;; be no insn for which tests in two `define_delay' expressions are both true.
1429 ;; For example, if we have a machine that requires one delay slot for branches
1430 ;; but two for calls, no delay slot can contain a branch or call insn, and any
1431 ;; valid insn in the delay slot for the branch can be annulled if the branch is
1432 ;; true, we might represent this as follows:
1434 ;; (define_delay (eq_attr "type" "branch")
1435 ;; [(eq_attr "type" "!branch,call")
1436 ;; (eq_attr "type" "!branch,call")
1439 ;; (define_delay (eq_attr "type" "call")
1440 ;; [(eq_attr "type" "!branch,call") (nil) (nil)
1441 ;; (eq_attr "type" "!branch,call") (nil) (nil)])
1443 ;; Note - it is the backend's responsibility to fill any unfilled delay slots
1444 ;; at assembler generation time. This is usually done by adding a special print
1445 ;; operand to the delayed instruction, and then in the PRINT_OPERAND function
1446 ;; calling dbr_sequence_length() to determine how many delay slots were filled.
1449 ;; --------------<machine>.md-----------------
1450 ;; (define_insn "call"
1451 ;; [(call (match_operand 0 "memory_operand" "m")
1452 ;; (match_operand 1 "" ""))]
1454 ;; "call_delayed %0,%1,%2%#"
1455 ;; [(set_attr "length" "4")
1456 ;; (set_attr "type" "call")])
1458 ;; -------------<machine>.h-------------------
1459 ;; #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '#')
1461 ;; ------------<machine>.c------------------
1463 ;; machine_print_operand (file, x, code)
1471 ;; if (dbr_sequence_length () == 0)
1472 ;; fputs ("\n\tnop", file);
1475 ;; ::::::::::::::::::::
1477 ;; :: Notes on Patterns
1479 ;; ::::::::::::::::::::
1481 ;; If you need to construct a sequence of assembler instructions in order
1482 ;; to implement a pattern be sure to escape any backslashes and double quotes
1483 ;; that you use, e.g.:
1485 ;; (define_insn "an example"
1489 ;; { static char buffer [100];
1490 ;; sprintf (buffer, \"insn \\t %d\", REGNO (operands[1]));
1495 ;; Also if there is more than one instruction, they can be separated by \\;
1496 ;; which is a space saving synonym for \\n\\t:
1498 ;; (define_insn "another example"
1502 ;; { static char buffer [100];
1503 ;; sprintf (buffer, \"insn1 \\t %d\\;insn2 \\t %%1\",
1504 ;; REGNO (operands[1]));
1510 (include "predicates.md")
1512 ;; ::::::::::::::::::::
1516 ;; ::::::::::::::::::::
1518 ;; Wrap moves in define_expand to prevent memory->memory moves from being
1519 ;; generated at the RTL level, which generates better code for most machines
1520 ;; which can't do mem->mem moves.
1522 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
1523 ;; than M, the effect of this instruction is to store the specified value in
1524 ;; the part of the register that corresponds to mode M. The effect on the rest
1525 ;; of the register is undefined.
1527 ;; This class of patterns is special in several ways. First of all, each of
1528 ;; these names *must* be defined, because there is no other way to copy a datum
1529 ;; from one place to another.
1531 ;; Second, these patterns are not used solely in the RTL generation pass. Even
1532 ;; the reload pass can generate move insns to copy values from stack slots into
1533 ;; temporary registers. When it does so, one of the operands is a hard
1534 ;; register and the other is an operand that can need to be reloaded into a
1537 ;; Therefore, when given such a pair of operands, the pattern must
1538 ;; generate RTL which needs no reloading and needs no temporary
1539 ;; registers--no registers other than the operands. For example, if
1540 ;; you support the pattern with a `define_expand', then in such a
1541 ;; case the `define_expand' mustn't call `force_reg' or any other such
1542 ;; function which might generate new pseudo registers.
1544 ;; This requirement exists even for subword modes on a RISC machine
1545 ;; where fetching those modes from memory normally requires several
1546 ;; insns and some temporary registers. Look in `spur.md' to see how
1547 ;; the requirement can be satisfied.
1549 ;; During reload a memory reference with an invalid address may be passed as an
1550 ;; operand. Such an address will be replaced with a valid address later in the
1551 ;; reload pass. In this case, nothing may be done with the address except to
1552 ;; use it as it stands. If it is copied, it will not be replaced with a valid
1553 ;; address. No attempt should be made to make such an address into a valid
1554 ;; address and no routine (such as `change_address') that will do so may be
1555 ;; called. Note that `general_operand' will fail when applied to such an
1558 ;; The global variable `reload_in_progress' (which must be explicitly declared
1559 ;; if required) can be used to determine whether such special handling is
1562 ;; The variety of operands that have reloads depends on the rest of
1563 ;; the machine description, but typically on a RISC machine these can
1564 ;; only be pseudo registers that did not get hard registers, while on
1565 ;; other machines explicit memory references will get optional
1568 ;; If a scratch register is required to move an object to or from memory, it
1569 ;; can be allocated using `gen_reg_rtx' prior to reload. But this is
1570 ;; impossible during and after reload. If there are cases needing scratch
1571 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
1572 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
1573 ;; patterns `reload_inM' or `reload_outM' to handle them.
1575 ;; The constraints on a `moveM' must permit moving any hard register to any
1576 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
1577 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
1580 ;; It is obligatory to support floating point `moveM' instructions
1581 ;; into and out of any registers that can hold fixed point values,
1582 ;; because unions and structures (which have modes `SImode' or
1583 ;; `DImode') can be in those registers and they may have floating
1586 ;; There may also be a need to support fixed point `moveM' instructions in and
1587 ;; out of floating point registers. Unfortunately, I have forgotten why this
1588 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
1589 ;; rejects fixed point values in floating point registers, then the constraints
1590 ;; of the fixed point `moveM' instructions must be designed to avoid ever
1591 ;; trying to reload into a floating point register.
1593 (define_expand "movqi"
1594 [(set (match_operand:QI 0 "general_operand" "")
1595 (match_operand:QI 1 "general_operand" ""))]
1597 "{ frv_emit_move (QImode, operands[0], operands[1]); DONE; }")
1599 (define_insn "*movqi_load"
1600 [(set (match_operand:QI 0 "register_operand" "=d,f")
1601 (match_operand:QI 1 "frv_load_operand" "m,m"))]
1603 "* return output_move_single (operands, insn);"
1604 [(set_attr "length" "4")
1605 (set_attr "type" "gload,fload")])
1607 (define_insn "*movqi_internal"
1608 [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f,d,f")
1609 (match_operand:QI 1 "move_source_operand" "L,d,d,O, d, f, f, f,GO,!m,!m"))]
1610 "register_operand(operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
1611 "* return output_move_single (operands, insn);"
1612 [(set_attr "length" "4")
1613 (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1615 (define_expand "movhi"
1616 [(set (match_operand:HI 0 "general_operand" "")
1617 (match_operand:HI 1 "general_operand" ""))]
1619 "{ frv_emit_move (HImode, operands[0], operands[1]); DONE; }")
1621 (define_insn "*movhi_load"
1622 [(set (match_operand:HI 0 "register_operand" "=d,f")
1623 (match_operand:HI 1 "frv_load_operand" "m,m"))]
1625 "* return output_move_single (operands, insn);"
1626 [(set_attr "length" "4")
1627 (set_attr "type" "gload,fload")])
1629 (define_insn "*movhi_internal"
1630 [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f,d,f")
1631 (match_operand:HI 1 "move_source_operand" "L,n,d,d,O, d, f, f, f,GO,!m,!m"))]
1632 "register_operand(operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
1633 "* return output_move_single (operands, insn);"
1634 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4")
1635 (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1637 ;; Split 2 word load of constants into sethi/setlo instructions
1639 [(set (match_operand:HI 0 "integer_register_operand" "")
1640 (match_operand:HI 1 "int_2word_operand" ""))]
1643 (high:HI (match_dup 1)))
1645 (lo_sum:HI (match_dup 0)
1649 (define_insn "movhi_high"
1650 [(set (match_operand:HI 0 "integer_register_operand" "=d")
1651 (high:HI (match_operand:HI 1 "int_2word_operand" "i")))]
1654 [(set_attr "type" "sethi")
1655 (set_attr "length" "4")])
1657 (define_insn "movhi_lo_sum"
1658 [(set (match_operand:HI 0 "integer_register_operand" "+d")
1659 (lo_sum:HI (match_dup 0)
1660 (match_operand:HI 1 "int_2word_operand" "i")))]
1663 [(set_attr "type" "setlo")
1664 (set_attr "length" "4")])
1666 (define_expand "movsi"
1667 [(set (match_operand:SI 0 "move_destination_operand" "")
1668 (match_operand:SI 1 "move_source_operand" ""))]
1670 "{ frv_emit_move (SImode, operands[0], operands[1]); DONE; }")
1672 ;; Note - it is best to only have one movsi pattern and to handle
1673 ;; all the various contingencies by the use of alternatives. This
1674 ;; allows reload the greatest amount of flexibility (since reload will
1675 ;; only choose amongst alternatives for a selected insn, it will not
1676 ;; replace the insn with another one).
1678 ;; Unfortunately, we do have to separate out load-type moves from the rest,
1679 ;; and only allow memory source operands in the former. If we do memory and
1680 ;; constant loads in a single pattern, reload will be tempted to force
1681 ;; constants into memory when the destination is a floating-point register.
1682 ;; That may make a function use a PIC pointer when it didn't before, and we
1683 ;; cannot change PIC usage (and hence stack layout) so late in the game.
1684 ;; The resulting sequences for loading constants into FPRs are preferable
1685 ;; even when we're not generating PIC code.
1687 ;; However, if we don't accept input from memory at all in the generic
1688 ;; movsi pattern, reloads for asm instructions that reference pseudos
1689 ;; that end up assigned to memory will fail to match, because we
1690 ;; recognize them right after they're emitted, and we don't
1691 ;; re-recognize them again after the substitution for memory. So keep
1692 ;; a memory constraint available, just make sure reload won't be
1693 ;; tempted to use it.
1697 (define_insn "*movsi_load"
1698 [(set (match_operand:SI 0 "register_operand" "=d,f")
1699 (match_operand:SI 1 "frv_load_operand" "m,m"))]
1701 "* return output_move_single (operands, insn);"
1702 [(set_attr "length" "4")
1703 (set_attr "type" "gload,fload")])
1705 (define_insn "*movsi_got"
1706 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1707 (match_operand:SI 1 "got12_operand" ""))]
1710 [(set_attr "type" "int")
1711 (set_attr "length" "4")])
1713 (define_insn "*movsi_high_got"
1714 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1715 (high:SI (match_operand:SI 1 "const_unspec_operand" "")))]
1718 [(set_attr "type" "sethi")
1719 (set_attr "length" "4")])
1721 (define_insn "*movsi_lo_sum_got"
1722 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1723 (lo_sum:SI (match_operand:SI 1 "integer_register_operand" "0")
1724 (match_operand:SI 2 "const_unspec_operand" "")))]
1727 [(set_attr "type" "setlo")
1728 (set_attr "length" "4")])
1730 (define_insn "*movsi_internal"
1731 [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z,d,f")
1732 (match_operand:SI 1 "move_source_operand" "L,n,d,d,O,d,z,f,d,f,f,GO,GO,!m,!m"))]
1733 "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
1734 "* return output_move_single (operands, insn);"
1735 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4,4,4")
1736 (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr,gload,fload")])
1738 ;; Split 2 word load of constants into sethi/setlo instructions
1739 (define_insn_and_split "*movsi_2word"
1740 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1741 (match_operand:SI 1 "int_2word_operand" "i"))]
1746 (high:SI (match_dup 1)))
1748 (lo_sum:SI (match_dup 0)
1751 [(set_attr "length" "8")
1752 (set_attr "type" "multi")])
1754 (define_insn "movsi_high"
1755 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1756 (high:SI (match_operand:SI 1 "int_2word_operand" "i")))]
1759 [(set_attr "type" "sethi")
1760 (set_attr "length" "4")])
1762 (define_insn "movsi_lo_sum"
1763 [(set (match_operand:SI 0 "integer_register_operand" "+d")
1764 (lo_sum:SI (match_dup 0)
1765 (match_operand:SI 1 "int_2word_operand" "i")))]
1768 [(set_attr "type" "setlo")
1769 (set_attr "length" "4")])
1771 (define_expand "movdi"
1772 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1773 (match_operand:DI 1 "general_operand" ""))]
1775 "{ frv_emit_move (DImode, operands[0], operands[1]); DONE; }")
1777 (define_insn "*movdi_double"
1778 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1779 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1781 && (register_operand (operands[0], DImode)
1782 || reg_or_0_operand (operands[1], DImode))"
1783 "* return output_move_double (operands, insn);"
1784 [(set_attr "length" "8,4,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,16,16,8,8")
1785 (set_attr "type" "multi,fdconv,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1787 (define_insn "*movdi_nodouble"
1788 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1789 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1791 && (register_operand (operands[0], DImode)
1792 || reg_or_0_operand (operands[1], DImode))"
1793 "* return output_move_double (operands, insn);"
1794 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1795 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1798 [(set (match_operand:DI 0 "register_operand" "")
1799 (match_operand:DI 1 "dbl_memory_two_insn_operand" ""))]
1802 "frv_split_double_load (operands[0], operands[1]);")
1805 [(set (match_operand:DI 0 "odd_reg_operand" "")
1806 (match_operand:DI 1 "memory_operand" ""))]
1809 "frv_split_double_load (operands[0], operands[1]);")
1812 [(set (match_operand:DI 0 "dbl_memory_two_insn_operand" "")
1813 (match_operand:DI 1 "reg_or_0_operand" ""))]
1816 "frv_split_double_store (operands[0], operands[1]);")
1819 [(set (match_operand:DI 0 "memory_operand" "")
1820 (match_operand:DI 1 "odd_reg_operand" ""))]
1823 "frv_split_double_store (operands[0], operands[1]);")
1826 [(set (match_operand:DI 0 "register_operand" "")
1827 (match_operand:DI 1 "register_operand" ""))]
1829 && (odd_reg_operand (operands[0], DImode)
1830 || odd_reg_operand (operands[1], DImode)
1831 || (integer_register_operand (operands[0], DImode)
1832 && integer_register_operand (operands[1], DImode))
1834 && fpr_operand (operands[0], DImode)
1835 && fpr_operand (operands[1], DImode)))"
1836 [(set (match_dup 2) (match_dup 4))
1837 (set (match_dup 3) (match_dup 5))]
1840 rtx op0 = operands[0];
1841 rtx op0_low = gen_lowpart (SImode, op0);
1842 rtx op0_high = gen_highpart (SImode, op0);
1843 rtx op1 = operands[1];
1844 rtx op1_low = gen_lowpart (SImode, op1);
1845 rtx op1_high = gen_highpart (SImode, op1);
1847 /* We normally copy the low-numbered register first. However, if the first
1848 register operand 0 is the same as the second register of operand 1, we
1849 must copy in the opposite order. */
1851 if (REGNO (op0_high) == REGNO (op1_low))
1853 operands[2] = op0_low;
1854 operands[3] = op0_high;
1855 operands[4] = op1_low;
1856 operands[5] = op1_high;
1860 operands[2] = op0_high;
1861 operands[3] = op0_low;
1862 operands[4] = op1_high;
1863 operands[5] = op1_low;
1868 [(set (match_operand:DI 0 "register_operand" "")
1869 (match_operand:DI 1 "const_int_operand" ""))]
1871 [(set (match_dup 2) (match_dup 4))
1872 (set (match_dup 3) (match_dup 5))]
1875 rtx op0 = operands[0];
1876 rtx op1 = operands[1];
1878 operands[2] = gen_highpart (SImode, op0);
1879 operands[3] = gen_lowpart (SImode, op0);
1880 if (HOST_BITS_PER_WIDE_INT <= 32)
1882 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1887 operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
1888 >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31)
1889 - ((unsigned HOST_WIDE_INT)1 << 31));
1890 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
1895 [(set (match_operand:DI 0 "register_operand" "")
1896 (match_operand:DI 1 "const_double_operand" ""))]
1898 [(set (match_dup 2) (match_dup 4))
1899 (set (match_dup 3) (match_dup 5))]
1902 rtx op0 = operands[0];
1903 rtx op1 = operands[1];
1905 operands[2] = gen_highpart (SImode, op0);
1906 operands[3] = gen_lowpart (SImode, op0);
1907 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (op1));
1908 operands[5] = GEN_INT (CONST_DOUBLE_LOW (op1));
1911 ;; Floating Point Moves
1913 ;; Note - Patterns for SF mode moves are compulsory, but
1914 ;; patterns for DF are optional, as GCC can synthesize them.
1916 (define_expand "movsf"
1917 [(set (match_operand:SF 0 "general_operand" "")
1918 (match_operand:SF 1 "general_operand" ""))]
1920 "{ frv_emit_move (SFmode, operands[0], operands[1]); DONE; }")
1923 [(set (match_operand:SF 0 "integer_register_operand" "")
1924 (match_operand:SF 1 "int_2word_operand" ""))]
1927 (high:SF (match_dup 1)))
1929 (lo_sum:SF (match_dup 0)
1933 (define_insn "*movsf_load_has_fprs"
1934 [(set (match_operand:SF 0 "register_operand" "=f,d")
1935 (match_operand:SF 1 "frv_load_operand" "m,m"))]
1937 "* return output_move_single (operands, insn);"
1938 [(set_attr "length" "4")
1939 (set_attr "type" "fload,gload")])
1941 (define_insn "*movsf_internal_has_fprs"
1942 [(set (match_operand:SF 0 "move_destination_operand" "=f,f,m,m,?f,?d,?d,m,?d")
1943 (match_operand:SF 1 "move_source_operand" "f,OG,f,OG,d,f,d,d,F"))]
1945 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1946 "* return output_move_single (operands, insn);"
1947 [(set_attr "length" "4,4,4,4,4,4,4,4,8")
1948 (set_attr "type" "fsconv,movgf,fstore,gstore,movgf,movfg,int,gstore,multi")])
1950 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1951 ;; will all be emulated
1952 (define_insn "*movsf_internal_no_fprs"
1953 [(set (match_operand:SF 0 "move_destination_operand" "=d,d,m,d,d")
1954 (match_operand:SF 1 "move_source_operand" " d,OG,dOG,m,F"))]
1956 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1957 "* return output_move_single (operands, insn);"
1958 [(set_attr "length" "4,4,4,4,8")
1959 (set_attr "type" "int,int,gstore,gload,multi")])
1961 (define_insn "movsf_high"
1962 [(set (match_operand:SF 0 "integer_register_operand" "=d")
1963 (high:SF (match_operand:SF 1 "int_2word_operand" "i")))]
1966 [(set_attr "type" "sethi")
1967 (set_attr "length" "4")])
1969 (define_insn "movsf_lo_sum"
1970 [(set (match_operand:SF 0 "integer_register_operand" "+d")
1971 (lo_sum:SF (match_dup 0)
1972 (match_operand:SF 1 "int_2word_operand" "i")))]
1975 [(set_attr "type" "setlo")
1976 (set_attr "length" "4")])
1978 (define_expand "movdf"
1979 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1980 (match_operand:DF 1 "general_operand" ""))]
1982 "{ frv_emit_move (DFmode, operands[0], operands[1]); DONE; }")
1984 (define_insn "*movdf_double"
1985 [(set (match_operand:DF 0 "move_destination_operand" "=h,?e,??f,??d,R,?R,??m,??m,h,?e,??f,??d,?h,??f,?e,??d,R,m,h,??f,e,??d,e,??d")
1986 (match_operand:DF 1 "move_source_operand" " h,e,f,d,h,e,f,d,R,R,m,m,e,d,h,f,GO,GO,GO,GO,GO,GO,F,F"))]
1988 && (register_operand (operands[0], DFmode)
1989 || reg_or_0_operand (operands[1], DFmode))"
1990 "* return output_move_double (operands, insn);"
1991 [(set_attr "length" "4,8,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,8,8,16,16")
1992 (set_attr "type" "fdconv,multi,multi,multi,fstore,gstore,fstore,gstore,fload,gload,fload,gload,movgf,movgf,movfg,movfg,gstore,gstore,movgf,movgf,multi,multi,multi,multi")])
1994 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1995 ;; will all be emulated
1996 (define_insn "*movdf_nodouble"
1997 [(set (match_operand:DF 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1998 (match_operand:DF 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
2000 && (register_operand (operands[0], DFmode)
2001 || reg_or_0_operand (operands[1], DFmode))"
2002 "* return output_move_double (operands, insn);"
2003 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
2004 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
2007 [(set (match_operand:DF 0 "register_operand" "")
2008 (match_operand:DF 1 "dbl_memory_two_insn_operand" ""))]
2011 "frv_split_double_load (operands[0], operands[1]);")
2014 [(set (match_operand:DF 0 "odd_reg_operand" "")
2015 (match_operand:DF 1 "memory_operand" ""))]
2018 "frv_split_double_load (operands[0], operands[1]);")
2021 [(set (match_operand:DF 0 "dbl_memory_two_insn_operand" "")
2022 (match_operand:DF 1 "reg_or_0_operand" ""))]
2025 "frv_split_double_store (operands[0], operands[1]);")
2028 [(set (match_operand:DF 0 "memory_operand" "")
2029 (match_operand:DF 1 "odd_reg_operand" ""))]
2032 "frv_split_double_store (operands[0], operands[1]);")
2035 [(set (match_operand:DF 0 "register_operand" "")
2036 (match_operand:DF 1 "register_operand" ""))]
2038 && (odd_reg_operand (operands[0], DFmode)
2039 || odd_reg_operand (operands[1], DFmode)
2040 || (integer_register_operand (operands[0], DFmode)
2041 && integer_register_operand (operands[1], DFmode))
2043 && fpr_operand (operands[0], DFmode)
2044 && fpr_operand (operands[1], DFmode)))"
2045 [(set (match_dup 2) (match_dup 4))
2046 (set (match_dup 3) (match_dup 5))]
2049 rtx op0 = operands[0];
2050 rtx op0_low = gen_lowpart (SImode, op0);
2051 rtx op0_high = gen_highpart (SImode, op0);
2052 rtx op1 = operands[1];
2053 rtx op1_low = gen_lowpart (SImode, op1);
2054 rtx op1_high = gen_highpart (SImode, op1);
2056 /* We normally copy the low-numbered register first. However, if the first
2057 register operand 0 is the same as the second register of operand 1, we
2058 must copy in the opposite order. */
2060 if (REGNO (op0_high) == REGNO (op1_low))
2062 operands[2] = op0_low;
2063 operands[3] = op0_high;
2064 operands[4] = op1_low;
2065 operands[5] = op1_high;
2069 operands[2] = op0_high;
2070 operands[3] = op0_low;
2071 operands[4] = op1_high;
2072 operands[5] = op1_low;
2077 [(set (match_operand:DF 0 "register_operand" "")
2078 (match_operand:DF 1 "const_int_operand" ""))]
2080 [(set (match_dup 2) (match_dup 4))
2081 (set (match_dup 3) (match_dup 5))]
2084 rtx op0 = operands[0];
2085 rtx op1 = operands[1];
2087 operands[2] = gen_highpart (SImode, op0);
2088 operands[3] = gen_lowpart (SImode, op0);
2089 if (HOST_BITS_PER_WIDE_INT <= 32)
2091 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
2096 operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
2097 >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31)
2098 - ((unsigned HOST_WIDE_INT)1 << 31));
2099 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
2104 [(set (match_operand:DF 0 "register_operand" "")
2105 (match_operand:DF 1 "const_double_operand" ""))]
2107 [(set (match_dup 2) (match_dup 4))
2108 (set (match_dup 3) (match_dup 5))]
2111 rtx op0 = operands[0];
2112 rtx op1 = operands[1];
2116 REAL_VALUE_FROM_CONST_DOUBLE (rv, op1);
2117 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2119 operands[2] = gen_highpart (SImode, op0);
2120 operands[3] = gen_lowpart (SImode, op0);
2121 operands[4] = GEN_INT (l[0]);
2122 operands[5] = GEN_INT (l[1]);
2125 ;; String/block move insn.
2126 ;; Argument 0 is the destination
2127 ;; Argument 1 is the source
2128 ;; Argument 2 is the length
2129 ;; Argument 3 is the alignment
2131 (define_expand "movmemsi"
2132 [(parallel [(set (match_operand:BLK 0 "" "")
2133 (match_operand:BLK 1 "" ""))
2134 (use (match_operand:SI 2 "" ""))
2135 (use (match_operand:SI 3 "" ""))])]
2139 if (frv_expand_block_move (operands))
2145 ;; String/block set insn.
2146 ;; Argument 0 is the destination
2147 ;; Argument 1 is the length
2148 ;; Argument 2 is the byte value -- ignore any value but zero
2149 ;; Argument 3 is the alignment
2151 (define_expand "setmemsi"
2152 [(parallel [(set (match_operand:BLK 0 "" "")
2153 (match_operand 2 "" ""))
2154 (use (match_operand:SI 1 "" ""))
2155 (use (match_operand:SI 3 "" ""))])]
2159 /* If value to set is not zero, use the library routine. */
2160 if (operands[2] != const0_rtx)
2163 if (frv_expand_block_clear (operands))
2170 ;; The "membar" part of a __builtin_read* or __builtin_write* function.
2171 ;; Operand 0 is a volatile reference to the memory that the function reads
2172 ;; or writes. Operand 1 is the address being accessed, or zero if the
2173 ;; address isn't a known constant. Operand 2 describes the __builtin
2174 ;; function (either FRV_IO_READ or FRV_IO_WRITE).
2175 (define_insn "optional_membar_<mode>"
2176 [(set (match_operand:IMODE 0 "memory_operand" "=m")
2177 (unspec:IMODE [(match_operand 1 "const_int_operand" "")
2178 (match_operand 2 "const_int_operand" "")]
2179 UNSPEC_OPTIONAL_MEMBAR))]
2182 [(set_attr "length" "4")])
2184 ;; ::::::::::::::::::::
2186 ;; :: Reload CC registers
2188 ;; ::::::::::::::::::::
2190 ;; Use as a define_expand so that cse/gcse/combine can't accidentally
2191 ;; create movcc insns.
2193 (define_expand "movcc"
2194 [(parallel [(set (match_operand:CC 0 "move_destination_operand" "")
2195 (match_operand:CC 1 "move_source_operand" ""))
2196 (clobber (match_dup 2))])]
2200 if (! reload_in_progress && ! reload_completed)
2203 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2206 (define_insn "*internal_movcc"
2207 [(set (match_operand:CC 0 "move_destination_operand" "=t,d,d,m,d")
2208 (match_operand:CC 1 "move_source_operand" "d,d,m,d,t"))
2209 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2210 "reload_in_progress || reload_completed"
2217 [(set_attr "length" "4,4,4,4,20")
2218 (set_attr "type" "int,int,gload,gstore,multi")])
2220 ;; To move an ICC value to a GPR for a signed comparison, we create a value
2221 ;; that when compared to 0, sets the N and Z flags appropriately (we don't care
2222 ;; about the V and C flags, since these comparisons are signed).
2225 [(set (match_operand:CC 0 "integer_register_operand" "")
2226 (match_operand:CC 1 "icc_operand" ""))
2227 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2228 "reload_in_progress || reload_completed"
2232 rtx dest = simplify_gen_subreg (SImode, operands[0], CCmode, 0);
2233 rtx icc = operands[1];
2234 rtx icr = operands[2];
2238 emit_insn (gen_rtx_SET (VOIDmode, icr,
2239 gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
2241 emit_insn (gen_movsi (dest, const1_rtx));
2243 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2244 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2245 gen_rtx_SET (VOIDmode, dest,
2246 gen_rtx_NEG (SImode, dest))));
2248 emit_insn (gen_rtx_SET (VOIDmode, icr,
2249 gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
2251 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2252 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2253 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2255 operands[3] = get_insns ();
2259 ;; Reload CC_UNSmode for unsigned integer comparisons
2260 ;; Use define_expand so that cse/gcse/combine can't create movcc_uns insns
2262 (define_expand "movcc_uns"
2263 [(parallel [(set (match_operand:CC_UNS 0 "move_destination_operand" "")
2264 (match_operand:CC_UNS 1 "move_source_operand" ""))
2265 (clobber (match_dup 2))])]
2269 if (! reload_in_progress && ! reload_completed)
2271 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2274 (define_insn "*internal_movcc_uns"
2275 [(set (match_operand:CC_UNS 0 "move_destination_operand" "=t,d,d,m,d")
2276 (match_operand:CC_UNS 1 "move_source_operand" "d,d,m,d,t"))
2277 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2278 "reload_in_progress || reload_completed"
2285 [(set_attr "length" "4,4,4,4,20")
2286 (set_attr "type" "int,int,gload,gstore,multi")])
2288 ;; To move an ICC value to a GPR for an unsigned comparison, we create a value
2289 ;; that when compared to 1, sets the Z, V, and C flags appropriately (we don't
2290 ;; care about the N flag, since these comparisons are unsigned).
2293 [(set (match_operand:CC_UNS 0 "integer_register_operand" "")
2294 (match_operand:CC_UNS 1 "icc_operand" ""))
2295 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2296 "reload_in_progress || reload_completed"
2300 rtx dest = simplify_gen_subreg (SImode, operands[0], CC_UNSmode, 0);
2301 rtx icc = operands[1];
2302 rtx icr = operands[2];
2306 emit_insn (gen_rtx_SET (VOIDmode, icr,
2307 gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2309 emit_insn (gen_movsi (dest, const1_rtx));
2311 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2312 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2313 gen_addsi3 (dest, dest, dest)));
2315 emit_insn (gen_rtx_SET (VOIDmode, icr,
2316 gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2318 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2319 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2320 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2322 operands[3] = get_insns ();
2326 ;; Reload CC_NZmode. This is mostly the same as the CCmode and CC_UNSmode
2327 ;; handling, but it uses different sequences for moving between GPRs and ICCs.
2329 (define_expand "movcc_nz"
2330 [(parallel [(set (match_operand:CC_NZ 0 "move_destination_operand" "")
2331 (match_operand:CC_NZ 1 "move_source_operand" ""))
2332 (clobber (match_dup 2))])]
2336 if (!reload_in_progress && !reload_completed)
2338 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2341 (define_insn "*internal_movcc_nz"
2342 [(set (match_operand:CC_NZ 0 "move_destination_operand" "=t,d,d,m,d")
2343 (match_operand:CC_NZ 1 "move_source_operand" "d,d,m,d,t"))
2344 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2345 "reload_in_progress || reload_completed"
2352 [(set_attr "length" "4,4,4,4,20")
2353 (set_attr "type" "int,int,gload,gstore,multi")])
2355 ;; Set the destination to a value that, when compared with zero, will
2356 ;; restore the value of the Z and N flags. The values of the other
2357 ;; flags don't matter. The sequence is:
2361 ;; csub gr0,op0,op0,op2
2365 [(set (match_operand:CC_NZ 0 "integer_register_operand" "")
2366 (match_operand:CC_NZ 1 "icc_operand" ""))
2367 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2368 "reload_in_progress || reload_completed"
2372 (ge:CC_CCR (match_dup 1)
2374 (cond_exec (ne:CC_CCR (match_dup 2)
2377 (neg:SI (match_dup 3))))
2379 (eq:CC_CCR (match_dup 1)
2381 (cond_exec (ne:CC_CCR (match_dup 2)
2383 (set (match_dup 3) (const_int 0)))]
2384 "operands[3] = simplify_gen_subreg (SImode, operands[0], CC_NZmode, 0);")
2386 ;; Reload CC_FPmode for floating point comparisons
2387 ;; We use a define_expand here so that cse/gcse/combine can't accidentally
2388 ;; create movcc insns. If this was a named define_insn, we would not be able
2389 ;; to make it conditional on reload.
2391 (define_expand "movcc_fp"
2392 [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "")
2393 (match_operand:CC_FP 1 "move_source_operand" ""))]
2397 if (! reload_in_progress && ! reload_completed)
2401 (define_insn "*movcc_fp_internal"
2402 [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "=d,d,d,m")
2403 (match_operand:CC_FP 1 "move_source_operand" "u,d,m,d"))]
2404 "TARGET_HAS_FPRS && (reload_in_progress || reload_completed)"
2410 [(set_attr "length" "12,4,4,4")
2411 (set_attr "type" "multi,int,gload,gstore")])
2414 (define_expand "reload_incc_fp"
2415 [(match_operand:CC_FP 0 "fcc_operand" "=u")
2416 (match_operand:CC_FP 1 "gpr_or_memory_operand_with_scratch" "m")
2417 (match_operand:TI 2 "integer_register_operand" "=&d")]
2421 rtx cc_op2 = simplify_gen_subreg (CC_FPmode, operands[2], TImode, 0);
2422 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], TImode, 0);
2423 rtx temp1 = simplify_gen_subreg (SImode, operands[2], TImode, 4);
2424 rtx temp2 = simplify_gen_subreg (SImode, operands[2], TImode, 8);
2425 int shift = CC_SHIFT_RIGHT (REGNO (operands[0]));
2428 if (!gpr_or_memory_operand (operands[1], CC_FPmode))
2431 rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
2433 gcc_assert (GET_CODE (operands[1]) == MEM);
2435 addr = XEXP (operands[1], 0);
2437 gcc_assert (GET_CODE (addr) == PLUS);
2439 emit_move_insn (temp3, XEXP (addr, 1));
2441 operands[1] = replace_equiv_address (operands[1],
2442 gen_rtx_PLUS (GET_MODE (addr),
2447 emit_insn (gen_movcc_fp (cc_op2, operands[1]));
2449 emit_insn (gen_ashlsi3 (int_op2, int_op2, GEN_INT (shift)));
2451 mask = ~ ((HOST_WIDE_INT)CC_MASK << shift);
2452 emit_insn (gen_movsi (temp1, GEN_INT (mask)));
2453 emit_insn (gen_update_fcc (operands[0], int_op2, temp1, temp2));
2457 (define_expand "reload_outcc_fp"
2458 [(set (match_operand:CC_FP 2 "integer_register_operand" "=&d")
2459 (match_operand:CC_FP 1 "fcc_operand" "u"))
2460 (set (match_operand:CC_FP 0 "memory_operand" "=m")
2465 ;; Convert a FCC value to gpr
2466 (define_insn "read_fcc"
2467 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2468 (unspec:SI [(match_operand:CC_FP 1 "fcc_operand" "u")]
2472 [(set_attr "type" "spr")
2473 (set_attr "length" "4")])
2476 [(set (match_operand:CC_FP 0 "integer_register_operand" "")
2477 (match_operand:CC_FP 1 "fcc_operand" ""))]
2478 "reload_completed && TARGET_HAS_FPRS"
2482 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_FPmode, 0);
2483 int shift = CC_SHIFT_RIGHT (REGNO (operands[1]));
2487 emit_insn (gen_read_fcc (int_op0, operands[1]));
2489 emit_insn (gen_lshrsi3 (int_op0, int_op0, GEN_INT (shift)));
2491 emit_insn (gen_andsi3 (int_op0, int_op0, GEN_INT (CC_MASK)));
2493 operands[2] = get_insns ();
2497 ;; Move a gpr value to FCC.
2499 ;; Operand1 = reloaded value shifted appropriately
2500 ;; Operand2 = mask to eliminate current register
2501 ;; Operand3 = temporary to load/store ccr
2502 (define_insn "update_fcc"
2503 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
2504 (unspec:CC_FP [(match_operand:SI 1 "integer_register_operand" "d")
2505 (match_operand:SI 2 "integer_register_operand" "d")]
2507 (clobber (match_operand:SI 3 "integer_register_operand" "=&d"))]
2509 "movsg ccr, %3\;and %2, %3, %3\;or %1, %3, %3\;movgs %3, ccr"
2510 [(set_attr "type" "multi")
2511 (set_attr "length" "16")])
2513 ;; Reload CC_CCRmode for conditional execution registers
2514 (define_insn "movcc_ccr"
2515 [(set (match_operand:CC_CCR 0 "move_destination_operand" "=d,d,d,m,v,?w,C,d")
2516 (match_operand:CC_CCR 1 "move_source_operand" "C,d,m,d,n,n,C,L"))]
2527 [(set_attr "length" "8,4,4,4,8,12,4,4")
2528 (set_attr "type" "multi,int,gload,gstore,multi,multi,ccr,int")])
2530 (define_expand "reload_incc_ccr"
2531 [(match_operand:CC_CCR 0 "cr_operand" "=C")
2532 (match_operand:CC_CCR 1 "memory_operand" "m")
2533 (match_operand:CC_CCR 2 "integer_register_operand" "=&d")]
2537 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2538 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], CC_CCRmode, 0);
2539 rtx icr = (ICR_P (REGNO (operands[0]))
2540 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2542 emit_insn (gen_movcc_ccr (operands[2], operands[1]));
2543 emit_insn (gen_cmpsi_cc (icc, int_op2, const0_rtx));
2544 emit_insn (gen_movcc_ccr (icr, gen_rtx_NE (CC_CCRmode, icc, const0_rtx)));
2546 if (! ICR_P (REGNO (operands[0])))
2547 emit_insn (gen_movcc_ccr (operands[0], icr));
2552 (define_expand "reload_outcc_ccr"
2553 [(set (match_operand:CC_CCR 2 "integer_register_operand" "=&d")
2554 (match_operand:CC_CCR 1 "cr_operand" "C"))
2555 (set (match_operand:CC_CCR 0 "memory_operand" "=m")
2561 [(set (match_operand:CC_CCR 0 "integer_register_operand" "")
2562 (match_operand:CC_CCR 1 "cr_operand" ""))]
2567 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_CCRmode, 0);
2570 emit_move_insn (operands[0], const1_rtx);
2571 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2572 gen_rtx_EQ (CC_CCRmode,
2575 gen_rtx_SET (VOIDmode, int_op0,
2578 operands[2] = get_insns ();
2583 [(set (match_operand:CC_CCR 0 "cr_operand" "")
2584 (match_operand:CC_CCR 1 "const_int_operand" ""))]
2589 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2590 rtx r0 = gen_rtx_REG (SImode, GPR_FIRST);
2591 rtx icr = (ICR_P (REGNO (operands[0]))
2592 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2596 emit_insn (gen_cmpsi_cc (icc, r0, const0_rtx));
2598 emit_insn (gen_movcc_ccr (icr,
2599 gen_rtx_fmt_ee (((INTVAL (operands[1]) == 0)
2600 ? EQ : NE), CC_CCRmode,
2603 if (! ICR_P (REGNO (operands[0])))
2604 emit_insn (gen_movcc_ccr (operands[0], icr));
2606 operands[2] = get_insns ();
2611 ;; ::::::::::::::::::::
2615 ;; ::::::::::::::::::::
2617 ;; Signed conversions from a smaller integer to a larger integer
2619 ;; These operations are optional. If they are not
2620 ;; present GCC will synthesize them for itself
2621 ;; Even though frv does not provide these instructions, we define them
2622 ;; to allow load + sign extend to be collapsed together
2623 (define_insn "extendqihi2"
2624 [(set (match_operand:HI 0 "integer_register_operand" "=d,d")
2625 (sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2630 [(set_attr "length" "8,4")
2631 (set_attr "type" "multi,gload")])
2634 [(set (match_operand:HI 0 "integer_register_operand" "")
2635 (sign_extend:HI (match_operand:QI 1 "integer_register_operand" "")))]
2641 rtx op0 = gen_lowpart (SImode, operands[0]);
2642 rtx op1 = gen_lowpart (SImode, operands[1]);
2643 rtx shift = GEN_INT (24);
2645 operands[2] = gen_ashlsi3 (op0, op1, shift);
2646 operands[3] = gen_ashrsi3 (op0, op0, shift);
2649 (define_insn "extendqisi2"
2650 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2651 (sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2656 [(set_attr "length" "8,4")
2657 (set_attr "type" "multi,gload")])
2660 [(set (match_operand:SI 0 "integer_register_operand" "")
2661 (sign_extend:SI (match_operand:QI 1 "integer_register_operand" "")))]
2667 rtx op0 = gen_lowpart (SImode, operands[0]);
2668 rtx op1 = gen_lowpart (SImode, operands[1]);
2669 rtx shift = GEN_INT (24);
2671 operands[2] = gen_ashlsi3 (op0, op1, shift);
2672 operands[3] = gen_ashrsi3 (op0, op0, shift);
2675 ;;(define_insn "extendqidi2"
2676 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2677 ;; (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2679 ;; "extendqihi2 %0,%1"
2680 ;; [(set_attr "length" "4")])
2682 (define_insn "extendhisi2"
2683 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2684 (sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,m")))]
2689 [(set_attr "length" "8,4")
2690 (set_attr "type" "multi,gload")])
2693 [(set (match_operand:SI 0 "integer_register_operand" "")
2694 (sign_extend:SI (match_operand:HI 1 "integer_register_operand" "")))]
2700 rtx op0 = gen_lowpart (SImode, operands[0]);
2701 rtx op1 = gen_lowpart (SImode, operands[1]);
2702 rtx shift = GEN_INT (16);
2704 operands[2] = gen_ashlsi3 (op0, op1, shift);
2705 operands[3] = gen_ashrsi3 (op0, op0, shift);
2708 ;;(define_insn "extendhidi2"
2709 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2710 ;; (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2712 ;; "extendhihi2 %0,%1"
2713 ;; [(set_attr "length" "4")])
2715 ;;(define_insn "extendsidi2"
2716 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2717 ;; (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2719 ;; "extendsidi2 %0,%1"
2720 ;; [(set_attr "length" "4")])
2722 ;; Unsigned conversions from a smaller integer to a larger integer
2723 (define_insn "zero_extendqihi2"
2724 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
2726 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2732 [(set_attr "length" "4")
2733 (set_attr "type" "int,int,gload")])
2735 (define_insn "zero_extendqisi2"
2736 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
2738 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2744 [(set_attr "length" "4")
2745 (set_attr "type" "int,int,gload")])
2747 ;;(define_insn "zero_extendqidi2"
2748 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2749 ;; (zero_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2751 ;; "zero_extendqihi2 %0,%1"
2752 ;; [(set_attr "length" "4")])
2754 ;; Do not set the type for the sethi to "sethi", since the scheduler will think
2755 ;; the sethi takes 0 cycles as part of allowing sethi/setlo to be in the same
2756 ;; VLIW instruction.
2757 (define_insn "zero_extendhisi2"
2758 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2759 (zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "0,m")))]
2764 [(set_attr "length" "4")
2765 (set_attr "type" "int,gload")])
2767 ;;(define_insn "zero_extendhidi2"
2768 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2769 ;; (zero_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2771 ;; "zero_extendhihi2 %0,%1"
2772 ;; [(set_attr "length" "4")])
2774 ;;(define_insn "zero_extendsidi2"
2775 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2776 ;; (zero_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2778 ;; "zero_extendsidi2 %0,%1"
2779 ;; [(set_attr "length" "4")])
2781 ;;;; Convert between floating point types of different sizes.
2783 ;;(define_insn "extendsfdf2"
2784 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2785 ;; (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
2787 ;; "extendsfdf2 %0,%1"
2788 ;; [(set_attr "length" "4")])
2790 ;;(define_insn "truncdfsf2"
2791 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2792 ;; (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
2794 ;; "truncdfsf2 %0,%1"
2795 ;; [(set_attr "length" "4")])
2797 ;;;; Convert between signed integer types and floating point.
2798 (define_insn "floatsisf2"
2799 [(set (match_operand:SF 0 "fpr_operand" "=f")
2800 (float:SF (match_operand:SI 1 "fpr_operand" "f")))]
2803 [(set_attr "length" "4")
2804 (set_attr "type" "fsconv")])
2806 (define_insn "floatsidf2"
2807 [(set (match_operand:DF 0 "fpr_operand" "=h")
2808 (float:DF (match_operand:SI 1 "fpr_operand" "f")))]
2809 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2811 [(set_attr "length" "4")
2812 (set_attr "type" "fdconv")])
2814 ;;(define_insn "floatdisf2"
2815 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2816 ;; (float:SF (match_operand:DI 1 "register_operand" "r")))]
2818 ;; "floatdisf2 %0,%1"
2819 ;; [(set_attr "length" "4")])
2821 ;;(define_insn "floatdidf2"
2822 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2823 ;; (float:DF (match_operand:DI 1 "register_operand" "r")))]
2825 ;; "floatdidf2 %0,%1"
2826 ;; [(set_attr "length" "4")])
2828 (define_insn "fix_truncsfsi2"
2829 [(set (match_operand:SI 0 "fpr_operand" "=f")
2830 (fix:SI (match_operand:SF 1 "fpr_operand" "f")))]
2833 [(set_attr "length" "4")
2834 (set_attr "type" "fsconv")])
2836 (define_insn "fix_truncdfsi2"
2837 [(set (match_operand:SI 0 "fpr_operand" "=f")
2838 (fix:SI (match_operand:DF 1 "fpr_operand" "h")))]
2839 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2841 [(set_attr "length" "4")
2842 (set_attr "type" "fdconv")])
2844 ;;(define_insn "fix_truncsfdi2"
2845 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2846 ;; (fix:DI (match_operand:SF 1 "register_operand" "r")))]
2848 ;; "fix_truncsfdi2 %0,%1"
2849 ;; [(set_attr "length" "4")])
2851 ;;(define_insn "fix_truncdfdi2"
2852 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2853 ;; (fix:DI (match_operand:DF 1 "register_operand" "r")))]
2855 ;; "fix_truncdfdi2 %0,%1"
2856 ;; [(set_attr "length" "4")])
2858 ;;;; Convert between unsigned integer types and floating point.
2860 ;;(define_insn "floatunssisf2"
2861 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2862 ;; (unsigned_float:SF (match_operand:SI 1 "register_operand" "r")))]
2864 ;; "floatunssisf2 %0,%1"
2865 ;; [(set_attr "length" "4")])
2867 ;;(define_insn "floatunssidf2"
2868 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2869 ;; (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
2871 ;; "floatunssidf2 %0,%1"
2872 ;; [(set_attr "length" "4")])
2874 ;;(define_insn "floatunsdisf2"
2875 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2876 ;; (unsigned_float:SF (match_operand:DI 1 "register_operand" "r")))]
2878 ;; "floatunsdisf2 %0,%1"
2879 ;; [(set_attr "length" "4")])
2881 ;;(define_insn "floatunsdidf2"
2882 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2883 ;; (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
2885 ;; "floatunsdidf2 %0,%1"
2886 ;; [(set_attr "length" "4")])
2888 ;;(define_insn "fixuns_truncsfsi2"
2889 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2890 ;; (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
2892 ;; "fixuns_truncsfsi2 %0,%1"
2893 ;; [(set_attr "length" "4")])
2895 ;;(define_insn "fixuns_truncdfsi2"
2896 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2897 ;; (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
2899 ;; "fixuns_truncdfsi2 %0,%1"
2900 ;; [(set_attr "length" "4")])
2902 ;;(define_insn "fixuns_truncsfdi2"
2903 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2904 ;; (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
2906 ;; "fixuns_truncsfdi2 %0,%1"
2907 ;; [(set_attr "length" "4")])
2909 ;;(define_insn "fixuns_truncdfdi2"
2910 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2911 ;; (unsigned_fix:DI (match_operand:DF 1 "register_operand" "r")))]
2913 ;; "fixuns_truncdfdi2 %0,%1"
2914 ;; [(set_attr "length" "4")])
2917 ;; ::::::::::::::::::::
2919 ;; :: 32-bit Integer arithmetic
2921 ;; ::::::::::::::::::::
2924 (define_insn "addsi3"
2925 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2926 (plus:SI (match_operand:SI 1 "integer_register_operand" "%d")
2927 (match_operand:SI 2 "gpr_or_int12_operand" "dNOPQ")))]
2930 [(set_attr "length" "4")
2931 (set_attr "type" "int")])
2933 ;; Subtraction. No need to worry about constants, since the compiler
2934 ;; canonicalizes them into addsi3's. We prevent SUBREG's here to work around a
2935 ;; combine bug, that combines the 32x32->upper 32 bit multiply that uses a
2936 ;; SUBREG with a minus that shows up in modulus by constants.
2937 (define_insn "subsi3"
2938 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2939 (minus:SI (match_operand:SI 1 "gpr_no_subreg_operand" "d")
2940 (match_operand:SI 2 "gpr_no_subreg_operand" "d")))]
2943 [(set_attr "length" "4")
2944 (set_attr "type" "int")])
2946 ;; Signed multiplication producing 64-bit results from 32-bit inputs
2947 ;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
2948 ;; will do the 32x32->64 bit multiply and use the bottom word.
2949 (define_expand "mulsidi3"
2950 [(set (match_operand:DI 0 "integer_register_operand" "")
2951 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2952 (sign_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2956 if (GET_CODE (operands[2]) == CONST_INT)
2958 emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
2963 (define_insn "*mulsidi3_reg"
2964 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2965 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2966 (sign_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
2969 [(set_attr "length" "4")
2970 (set_attr "type" "mul")])
2972 (define_insn "mulsidi3_const"
2973 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2974 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
2975 (match_operand:SI 2 "int12_operand" "NOP")))]
2978 [(set_attr "length" "4")
2979 (set_attr "type" "mul")])
2981 ;; Unsigned multiplication producing 64-bit results from 32-bit inputs
2982 (define_expand "umulsidi3"
2983 [(set (match_operand:DI 0 "even_gpr_operand" "")
2984 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2985 (zero_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2989 if (GET_CODE (operands[2]) == CONST_INT)
2991 emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
2996 (define_insn "*mulsidi3_reg"
2997 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2998 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2999 (zero_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
3002 [(set_attr "length" "4")
3003 (set_attr "type" "mul")])
3005 (define_insn "umulsidi3_const"
3006 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3007 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
3008 (match_operand:SI 2 "int12_operand" "NOP")))]
3011 [(set_attr "length" "4")
3012 (set_attr "type" "mul")])
3015 (define_insn "divsi3"
3016 [(set (match_operand:SI 0 "register_operand" "=d,d")
3017 (div:SI (match_operand:SI 1 "register_operand" "d,d")
3018 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3021 [(set_attr "length" "4")
3022 (set_attr "type" "div")])
3024 ;; Unsigned Division
3025 (define_insn "udivsi3"
3026 [(set (match_operand:SI 0 "register_operand" "=d,d")
3027 (udiv:SI (match_operand:SI 1 "register_operand" "d,d")
3028 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3031 [(set_attr "length" "4")
3032 (set_attr "type" "div")])
3035 (define_insn "negsi2"
3036 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3037 (neg:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3040 [(set_attr "length" "4")
3041 (set_attr "type" "int")])
3043 ;; Find first one bit
3044 ;; (define_insn "ffssi2"
3045 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3046 ;; (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
3049 ;; [(set_attr "length" "4")])
3052 ;; ::::::::::::::::::::
3054 ;; :: 64-bit Integer arithmetic
3056 ;; ::::::::::::::::::::
3059 (define_insn_and_split "adddi3"
3060 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3061 (plus:DI (match_operand:DI 1 "integer_register_operand" "%e,0")
3062 (match_operand:DI 2 "gpr_or_int10_operand" "eJ,eJ")))
3063 (clobber (match_scratch:CC 3 "=t,t"))]
3074 for (op = 0; op < 3; op++)
3075 for (part = 0; part < 2; part++)
3076 parts[op][part] = simplify_gen_subreg (SImode, operands[op],
3077 DImode, part * UNITS_PER_WORD);
3079 operands[4] = gen_adddi3_lower (parts[0][1], parts[1][1], parts[2][1],
3081 operands[5] = gen_adddi3_upper (parts[0][0], parts[1][0], parts[2][0],
3082 copy_rtx (operands[3]));
3084 [(set_attr "length" "8")
3085 (set_attr "type" "multi")])
3087 ;; Subtraction No need to worry about constants, since the compiler
3088 ;; canonicalizes them into adddi3's.
3089 (define_insn_and_split "subdi3"
3090 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e")
3091 (minus:DI (match_operand:DI 1 "integer_register_operand" "e,0,e")
3092 (match_operand:DI 2 "integer_register_operand" "e,e,0")))
3093 (clobber (match_scratch:CC 3 "=t,t,t"))]
3101 rtx op0_high = gen_highpart (SImode, operands[0]);
3102 rtx op1_high = gen_highpart (SImode, operands[1]);
3103 rtx op2_high = gen_highpart (SImode, operands[2]);
3104 rtx op0_low = gen_lowpart (SImode, operands[0]);
3105 rtx op1_low = gen_lowpart (SImode, operands[1]);
3106 rtx op2_low = gen_lowpart (SImode, operands[2]);
3107 rtx op3 = operands[3];
3109 operands[4] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3110 operands[5] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3112 [(set_attr "length" "8")
3113 (set_attr "type" "multi")])
3115 ;; Patterns for addsi3/subdi3 after splitting
3116 (define_insn "adddi3_lower"
3117 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3118 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3119 (match_operand:SI 2 "gpr_or_int10_operand" "dJ")))
3120 (set (match_operand:CC 3 "icc_operand" "=t")
3121 (compare:CC (plus:SI (match_dup 1)
3125 "add%I2cc %1,%2,%0,%3"
3126 [(set_attr "length" "4")
3127 (set_attr "type" "int")])
3129 (define_insn "adddi3_upper"
3130 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3131 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3132 (plus:SI (match_operand:SI 2 "gpr_or_int10_operand" "dJ")
3133 (match_operand:CC 3 "icc_operand" "t"))))]
3135 "addx%I2 %1,%2,%0,%3"
3136 [(set_attr "length" "4")
3137 (set_attr "type" "int")])
3139 (define_insn "subdi3_lower"
3140 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3141 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3142 (match_operand:SI 2 "integer_register_operand" "d")))
3143 (set (match_operand:CC 3 "icc_operand" "=t")
3144 (compare:CC (plus:SI (match_dup 1)
3149 [(set_attr "length" "4")
3150 (set_attr "type" "int")])
3152 (define_insn "subdi3_upper"
3153 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3154 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3155 (minus:SI (match_operand:SI 2 "integer_register_operand" "d")
3156 (match_operand:CC 3 "icc_operand" "t"))))]
3159 [(set_attr "length" "4")
3160 (set_attr "type" "int")])
3162 (define_insn_and_split "negdi2"
3163 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3164 (neg:DI (match_operand:DI 1 "integer_register_operand" "e,0")))
3165 (clobber (match_scratch:CC 2 "=t,t"))]
3173 rtx op0_high = gen_highpart (SImode, operands[0]);
3174 rtx op1_high = gen_rtx_REG (SImode, GPR_FIRST);
3175 rtx op2_high = gen_highpart (SImode, operands[1]);
3176 rtx op0_low = gen_lowpart (SImode, operands[0]);
3177 rtx op1_low = op1_high;
3178 rtx op2_low = gen_lowpart (SImode, operands[1]);
3179 rtx op3 = operands[2];
3181 operands[3] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3182 operands[4] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3184 [(set_attr "length" "8")
3185 (set_attr "type" "multi")])
3187 ;; Multiplication (same size)
3188 ;; (define_insn "muldi3"
3189 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3190 ;; (mult:DI (match_operand:DI 1 "register_operand" "%r")
3191 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3193 ;; "muldi3 %0,%1,%2"
3194 ;; [(set_attr "length" "4")])
3197 ;; (define_insn "divdi3"
3198 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3199 ;; (div:DI (match_operand:DI 1 "register_operand" "r")
3200 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3202 ;; "divdi3 %0,%1,%2"
3203 ;; [(set_attr "length" "4")])
3205 ;; Undsgned Division
3206 ;; (define_insn "udivdi3"
3207 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3208 ;; (udiv:DI (match_operand:DI 1 "register_operand" "r")
3209 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3211 ;; "udivdi3 %0,%1,%2"
3212 ;; [(set_attr "length" "4")])
3215 ;; (define_insn "negdi2"
3216 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3217 ;; (neg:DI (match_operand:DI 1 "register_operand" "r")))]
3220 ;; [(set_attr "length" "4")])
3222 ;; Find first one bit
3223 ;; (define_insn "ffsdi2"
3224 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3225 ;; (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
3228 ;; [(set_attr "length" "4")])
3231 ;; ::::::::::::::::::::
3233 ;; :: 32-bit floating point arithmetic
3235 ;; ::::::::::::::::::::
3238 (define_insn "addsf3"
3239 [(set (match_operand:SF 0 "fpr_operand" "=f")
3240 (plus:SF (match_operand:SF 1 "fpr_operand" "%f")
3241 (match_operand:SF 2 "fpr_operand" "f")))]
3244 [(set_attr "length" "4")
3245 (set_attr "type" "fsadd")])
3248 (define_insn "subsf3"
3249 [(set (match_operand:SF 0 "fpr_operand" "=f")
3250 (minus:SF (match_operand:SF 1 "fpr_operand" "f")
3251 (match_operand:SF 2 "fpr_operand" "f")))]
3254 [(set_attr "length" "4")
3255 (set_attr "type" "fsadd")])
3258 (define_insn "mulsf3"
3259 [(set (match_operand:SF 0 "fpr_operand" "=f")
3260 (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3261 (match_operand:SF 2 "fpr_operand" "f")))]
3264 [(set_attr "length" "4")
3265 (set_attr "type" "fsmul")])
3267 ;; Multiplication with addition/subtraction
3268 (define_insn "*muladdsf4"
3269 [(set (match_operand:SF 0 "fpr_operand" "=f")
3270 (plus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3271 (match_operand:SF 2 "fpr_operand" "f"))
3272 (match_operand:SF 3 "fpr_operand" "0")))]
3273 "TARGET_HARD_FLOAT && TARGET_MULADD"
3275 [(set_attr "length" "4")
3276 (set_attr "type" "fsmadd")])
3278 (define_insn "*mulsubsf4"
3279 [(set (match_operand:SF 0 "fpr_operand" "=f")
3280 (minus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3281 (match_operand:SF 2 "fpr_operand" "f"))
3282 (match_operand:SF 3 "fpr_operand" "0")))]
3283 "TARGET_HARD_FLOAT && TARGET_MULADD"
3285 [(set_attr "length" "4")
3286 (set_attr "type" "fsmadd")])
3289 (define_insn "divsf3"
3290 [(set (match_operand:SF 0 "fpr_operand" "=f")
3291 (div:SF (match_operand:SF 1 "fpr_operand" "f")
3292 (match_operand:SF 2 "fpr_operand" "f")))]
3295 [(set_attr "length" "4")
3296 (set_attr "type" "fsdiv")])
3299 (define_insn "negsf2"
3300 [(set (match_operand:SF 0 "fpr_operand" "=f")
3301 (neg:SF (match_operand:SF 1 "fpr_operand" "f")))]
3304 [(set_attr "length" "4")
3305 (set_attr "type" "fsconv")])
3308 (define_insn "abssf2"
3309 [(set (match_operand:SF 0 "fpr_operand" "=f")
3310 (abs:SF (match_operand:SF 1 "fpr_operand" "f")))]
3313 [(set_attr "length" "4")
3314 (set_attr "type" "fsconv")])
3317 (define_insn "sqrtsf2"
3318 [(set (match_operand:SF 0 "fpr_operand" "=f")
3319 (sqrt:SF (match_operand:SF 1 "fpr_operand" "f")))]
3322 [(set_attr "length" "4")
3323 (set_attr "type" "sqrt_single")])
3326 ;; ::::::::::::::::::::
3328 ;; :: 64-bit floating point arithmetic
3330 ;; ::::::::::::::::::::
3333 (define_insn "adddf3"
3334 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3335 (plus:DF (match_operand:DF 1 "fpr_operand" "%h")
3336 (match_operand:DF 2 "fpr_operand" "h")))]
3337 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3339 [(set_attr "length" "4")
3340 (set_attr "type" "fdadd")])
3343 (define_insn "subdf3"
3344 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3345 (minus:DF (match_operand:DF 1 "fpr_operand" "h")
3346 (match_operand:DF 2 "fpr_operand" "h")))]
3347 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3349 [(set_attr "length" "4")
3350 (set_attr "type" "fdadd")])
3353 (define_insn "muldf3"
3354 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3355 (mult:DF (match_operand:DF 1 "fpr_operand" "%h")
3356 (match_operand:DF 2 "fpr_operand" "h")))]
3357 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3359 [(set_attr "length" "4")
3360 (set_attr "type" "fdmul")])
3362 ;; Multiplication with addition/subtraction
3363 (define_insn "*muladddf4"
3364 [(set (match_operand:DF 0 "fpr_operand" "=f")
3365 (plus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3366 (match_operand:DF 2 "fpr_operand" "f"))
3367 (match_operand:DF 3 "fpr_operand" "0")))]
3368 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3370 [(set_attr "length" "4")
3371 (set_attr "type" "fdmadd")])
3373 (define_insn "*mulsubdf4"
3374 [(set (match_operand:DF 0 "fpr_operand" "=f")
3375 (minus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3376 (match_operand:DF 2 "fpr_operand" "f"))
3377 (match_operand:DF 3 "fpr_operand" "0")))]
3378 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3380 [(set_attr "length" "4")
3381 (set_attr "type" "fdmadd")])
3384 (define_insn "divdf3"
3385 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3386 (div:DF (match_operand:DF 1 "fpr_operand" "h")
3387 (match_operand:DF 2 "fpr_operand" "h")))]
3388 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3390 [(set_attr "length" "4")
3391 (set_attr "type" "fddiv")])
3394 (define_insn "negdf2"
3395 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3396 (neg:DF (match_operand:DF 1 "fpr_operand" "h")))]
3397 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3399 [(set_attr "length" "4")
3400 (set_attr "type" "fdconv")])
3403 (define_insn "absdf2"
3404 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3405 (abs:DF (match_operand:DF 1 "fpr_operand" "h")))]
3406 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3408 [(set_attr "length" "4")
3409 (set_attr "type" "fdconv")])
3412 (define_insn "sqrtdf2"
3413 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3414 (sqrt:DF (match_operand:DF 1 "fpr_operand" "h")))]
3415 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3417 [(set_attr "length" "4")
3418 (set_attr "type" "sqrt_double")])
3421 ;; ::::::::::::::::::::
3423 ;; :: 32-bit Integer Shifts and Rotates
3425 ;; ::::::::::::::::::::
3427 ;; Arithmetic Shift Left
3428 (define_insn "ashlsi3"
3429 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3430 (ashift:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3431 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3434 [(set_attr "length" "4")
3435 (set_attr "type" "int")])
3437 ;; Arithmetic Shift Right
3438 (define_insn "ashrsi3"
3439 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3440 (ashiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3441 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3444 [(set_attr "length" "4")
3445 (set_attr "type" "int")])
3447 ;; Logical Shift Right
3448 (define_insn "lshrsi3"
3449 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3450 (lshiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3451 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3454 [(set_attr "length" "4")
3455 (set_attr "type" "int")])
3458 ;; (define_insn "rotlsi3"
3459 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3460 ;; (rotate:SI (match_operand:SI 1 "register_operand" "r")
3461 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3463 ;; "rotlsi3 %0,%1,%2"
3464 ;; [(set_attr "length" "4")])
3467 ;; (define_insn "rotrsi3"
3468 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3469 ;; (rotatert:SI (match_operand:SI 1 "register_operand" "r")
3470 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3472 ;; "rotrsi3 %0,%1,%2"
3473 ;; [(set_attr "length" "4")])
3476 ;; ::::::::::::::::::::
3478 ;; :: 64-bit Integer Shifts and Rotates
3480 ;; ::::::::::::::::::::
3482 ;; Arithmetic Shift Left
3483 ;; (define_insn "ashldi3"
3484 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3485 ;; (ashift:DI (match_operand:DI 1 "register_operand" "r")
3486 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3488 ;; "ashldi3 %0,%1,%2"
3489 ;; [(set_attr "length" "4")])
3491 ;; Arithmetic Shift Right
3492 ;; (define_insn "ashrdi3"
3493 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3494 ;; (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
3495 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3497 ;; "ashrdi3 %0,%1,%2"
3498 ;; [(set_attr "length" "4")])
3500 ;; Logical Shift Right
3501 ;; (define_insn "lshrdi3"
3502 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3503 ;; (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
3504 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3506 ;; "lshrdi3 %0,%1,%2"
3507 ;; [(set_attr "length" "4")])
3510 ;; (define_insn "rotldi3"
3511 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3512 ;; (rotate:DI (match_operand:DI 1 "register_operand" "r")
3513 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3515 ;; "rotldi3 %0,%1,%2"
3516 ;; [(set_attr "length" "4")])
3519 ;; (define_insn "rotrdi3"
3520 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3521 ;; (rotatert:DI (match_operand:DI 1 "register_operand" "r")
3522 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3524 ;; "rotrdi3 %0,%1,%2"
3525 ;; [(set_attr "length" "4")])
3528 ;; ::::::::::::::::::::
3530 ;; :: 32-Bit Integer Logical operations
3532 ;; ::::::::::::::::::::
3534 ;; Logical AND, 32-bit integers
3535 (define_insn "andsi3_media"
3536 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3537 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3538 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3543 [(set_attr "length" "4")
3544 (set_attr "type" "int,mlogic")])
3546 (define_insn "andsi3_nomedia"
3547 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3548 (and:SI (match_operand:SI 1 "integer_register_operand" "%d")
3549 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3552 [(set_attr "length" "4")
3553 (set_attr "type" "int")])
3555 (define_expand "andsi3"
3556 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3557 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3558 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3562 ;; Inclusive OR, 32-bit integers
3563 (define_insn "iorsi3_media"
3564 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3565 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3566 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3571 [(set_attr "length" "4")
3572 (set_attr "type" "int,mlogic")])
3574 (define_insn "iorsi3_nomedia"
3575 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3576 (ior:SI (match_operand:SI 1 "integer_register_operand" "%d")
3577 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3580 [(set_attr "length" "4")
3581 (set_attr "type" "int")])
3583 (define_expand "iorsi3"
3584 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3585 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3586 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3590 ;; Exclusive OR, 32-bit integers
3591 (define_insn "xorsi3_media"
3592 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3593 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3594 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3599 [(set_attr "length" "4")
3600 (set_attr "type" "int,mlogic")])
3602 (define_insn "xorsi3_nomedia"
3603 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3604 (xor:SI (match_operand:SI 1 "integer_register_operand" "%d")
3605 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3608 [(set_attr "length" "4")
3609 (set_attr "type" "int")])
3611 (define_expand "xorsi3"
3612 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3613 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3614 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3618 ;; One's complement, 32-bit integers
3619 (define_insn "one_cmplsi2_media"
3620 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3621 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
3626 [(set_attr "length" "4")
3627 (set_attr "type" "int,mlogic")])
3629 (define_insn "one_cmplsi2_nomedia"
3630 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3631 (not:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3634 [(set_attr "length" "4")
3635 (set_attr "type" "int")])
3637 (define_expand "one_cmplsi2"
3638 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3639 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")))]
3644 ;; ::::::::::::::::::::
3646 ;; :: 64-Bit Integer Logical operations
3648 ;; ::::::::::::::::::::
3650 ;; Logical AND, 64-bit integers
3651 ;; (define_insn "anddi3"
3652 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3653 ;; (and:DI (match_operand:DI 1 "register_operand" "%r")
3654 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3656 ;; "anddi3 %0,%1,%2"
3657 ;; [(set_attr "length" "4")])
3659 ;; Inclusive OR, 64-bit integers
3660 ;; (define_insn "iordi3"
3661 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3662 ;; (ior:DI (match_operand:DI 1 "register_operand" "%r")
3663 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3665 ;; "iordi3 %0,%1,%2"
3666 ;; [(set_attr "length" "4")])
3668 ;; Exclusive OR, 64-bit integers
3669 ;; (define_insn "xordi3"
3670 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3671 ;; (xor:DI (match_operand:DI 1 "register_operand" "%r")
3672 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3674 ;; "xordi3 %0,%1,%2"
3675 ;; [(set_attr "length" "4")])
3677 ;; One's complement, 64-bit integers
3678 ;; (define_insn "one_cmpldi2"
3679 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3680 ;; (not:DI (match_operand:DI 1 "register_operand" "r")))]
3683 ;; [(set_attr "length" "4")])
3686 ;; ::::::::::::::::::::
3688 ;; :: Combination of integer operation with comparison
3690 ;; ::::::::::::::::::::
3692 (define_insn "*combo_intop_compare1"
3693 [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3695 (match_operator:SI 1 "intop_compare_operator"
3696 [(match_operand:SI 2 "integer_register_operand" "d")
3697 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3700 "%O1%I3cc %2, %3, %., %0"
3701 [(set_attr "type" "int")
3702 (set_attr "length" "4")])
3704 (define_insn "*combo_intop_compare2"
3705 [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3707 (match_operator:SI 1 "intop_compare_operator"
3708 [(match_operand:SI 2 "integer_register_operand" "d")
3709 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3711 (set (match_operand:SI 4 "integer_register_operand" "=d")
3712 (match_operator:SI 5 "intop_compare_operator"
3715 "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3716 "%O1%I3cc %2, %3, %4, %0"
3717 [(set_attr "type" "int")
3718 (set_attr "length" "4")])
3720 ;; ::::::::::::::::::::
3724 ;; ::::::::::::::::::::
3726 ;; Note, we store the operands in the comparison insns, and use them later
3727 ;; when generating the branch or scc operation.
3729 ;; First the routines called by the machine independent part of the compiler
3730 (define_expand "cmpsi"
3732 (compare (match_operand:SI 0 "integer_register_operand" "")
3733 (match_operand:SI 1 "gpr_or_int10_operand" "")))]
3737 frv_compare_op0 = operands[0];
3738 frv_compare_op1 = operands[1];
3742 ;(define_expand "cmpdi"
3744 ; (compare (match_operand:DI 0 "register_operand" "")
3745 ; (match_operand:DI 1 "nonmemory_operand" "")))]
3749 ; frv_compare_op0 = operands[0];
3750 ; frv_compare_op1 = operands[1];
3754 (define_expand "cmpsf"
3756 (compare (match_operand:SF 0 "fpr_operand" "")
3757 (match_operand:SF 1 "fpr_operand" "")))]
3761 frv_compare_op0 = operands[0];
3762 frv_compare_op1 = operands[1];
3766 (define_expand "cmpdf"
3768 (compare (match_operand:DF 0 "fpr_operand" "")
3769 (match_operand:DF 1 "fpr_operand" "")))]
3770 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3773 frv_compare_op0 = operands[0];
3774 frv_compare_op1 = operands[1];
3778 ;; Now, the actual comparisons, generated by the branch and/or scc operations
3780 (define_insn "cmpsi_cc"
3781 [(set (match_operand:CC 0 "icc_operand" "=t,t")
3782 (compare:CC (match_operand:SI 1 "integer_register_operand" "d,d")
3783 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3786 [(set_attr "length" "4")
3787 (set_attr "type" "int")])
3789 (define_insn "*cmpsi_cc_uns"
3790 [(set (match_operand:CC_UNS 0 "icc_operand" "=t,t")
3791 (compare:CC_UNS (match_operand:SI 1 "integer_register_operand" "d,d")
3792 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3795 [(set_attr "length" "4")
3796 (set_attr "type" "int")])
3798 ;; The only requirement for a CC_NZmode GPR or memory value is that
3799 ;; comparing it against zero must set the Z and N flags appropriately.
3800 ;; The source operand is therefore a valid CC_NZmode value.
3801 (define_insn "*cmpsi_cc_nz"
3802 [(set (match_operand:CC_NZ 0 "nonimmediate_operand" "=t,d,m")
3803 (compare:CC_NZ (match_operand:SI 1 "integer_register_operand" "d,d,d")
3810 [(set_attr "length" "4,4,4")
3811 (set_attr "type" "int,int,gstore")])
3813 (define_insn "*cmpsf_cc_fp"
3814 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3815 (compare:CC_FP (match_operand:SF 1 "fpr_operand" "f")
3816 (match_operand:SF 2 "fpr_operand" "f")))]
3819 [(set_attr "length" "4")
3820 (set_attr "type" "fscmp")])
3822 (define_insn "*cmpdf_cc_fp"
3823 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3824 (compare:CC_FP (match_operand:DF 1 "even_fpr_operand" "h")
3825 (match_operand:DF 2 "even_fpr_operand" "h")))]
3826 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3828 [(set_attr "length" "4")
3829 (set_attr "type" "fdcmp")])
3832 ;; ::::::::::::::::::::
3836 ;; ::::::::::::::::::::
3838 ;; Define_expands called by the machine independent part of the compiler
3839 ;; to allocate a new comparison register. Each of these named patterns
3840 ;; must be present, and they cannot be amalgamated into one pattern.
3842 ;; If a fixed condition code register is being used, (as opposed to, say,
3843 ;; using cc0), then the expands should look like this:
3845 ;; (define_expand "<name_of_test>"
3846 ;; [(set (reg:CC <number_of_CC_register>)
3847 ;; (compare:CC (match_dup 1)
3850 ;; (if_then_else (eq:CC (reg:CC <number_of_CC_register>)
3852 ;; (label_ref (match_operand 0 "" ""))
3856 ;; operands[1] = frv_compare_op0;
3857 ;; operands[2] = frv_compare_op1;
3861 (define_expand "beq"
3862 [(use (match_operand 0 "" ""))]
3866 if (! frv_emit_cond_branch (EQ, operands[0]))
3872 (define_expand "bne"
3873 [(use (match_operand 0 "" ""))]
3877 if (! frv_emit_cond_branch (NE, operands[0]))
3883 (define_expand "blt"
3884 [(use (match_operand 0 "" ""))]
3888 if (! frv_emit_cond_branch (LT, operands[0]))
3894 (define_expand "ble"
3895 [(use (match_operand 0 "" ""))]
3899 if (! frv_emit_cond_branch (LE, operands[0]))
3905 (define_expand "bgt"
3906 [(use (match_operand 0 "" ""))]
3910 if (! frv_emit_cond_branch (GT, operands[0]))
3916 (define_expand "bge"
3917 [(use (match_operand 0 "" ""))]
3921 if (! frv_emit_cond_branch (GE, operands[0]))
3927 (define_expand "bltu"
3928 [(use (match_operand 0 "" ""))]
3932 if (! frv_emit_cond_branch (LTU, operands[0]))
3938 (define_expand "bleu"
3939 [(use (match_operand 0 "" ""))]
3943 if (! frv_emit_cond_branch (LEU, operands[0]))
3949 (define_expand "bgtu"
3950 [(use (match_operand 0 "" ""))]
3954 if (! frv_emit_cond_branch (GTU, operands[0]))
3960 (define_expand "bgeu"
3961 [(use (match_operand 0 "" ""))]
3965 if (! frv_emit_cond_branch (GEU, operands[0]))
3971 ;; Actual branches. We must allow for the (label_ref) and the (pc) to be
3972 ;; swapped. If they are swapped, it reverses the sense of the branch.
3974 ;; Note - unlike the define expands above, these patterns can be amalgamated
3975 ;; into one pattern for branch-if-true and one for branch-if-false. This does
3976 ;; require an operand operator to select the correct branch mnemonic.
3978 ;; If a fixed condition code register is being used, (as opposed to, say,
3979 ;; using cc0), then the expands could look like this:
3981 ;; (define_insn "*branch_true"
3983 ;; (if_then_else (match_operator:CC 0 "comparison_operator"
3984 ;; [(reg:CC <number_of_CC_register>)
3986 ;; (label_ref (match_operand 1 "" ""))
3990 ;; [(set_attr "length" "4")]
3993 ;; In the above example the %B is a directive to frv_print_operand()
3994 ;; to decode and print the correct branch mnemonic.
3996 (define_insn "*branch_int_true"
3998 (if_then_else (match_operator 0 "integer_relational_operator"
3999 [(match_operand 1 "icc_operand" "t")
4001 (label_ref (match_operand 2 "" ""))
4006 if (get_attr_length (insn) == 4)
4007 return \"b%c0 %1,%#,%l2\";
4009 return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
4011 [(set (attr "length")
4013 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4014 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4017 (set (attr "far_jump")
4019 (eq_attr "length" "4")
4021 (const_string "yes")))
4024 (eq_attr "length" "4")
4025 (const_string "branch")
4026 (const_string "multi")))])
4028 (define_insn "*branch_int_false"
4030 (if_then_else (match_operator 0 "integer_relational_operator"
4031 [(match_operand 1 "icc_operand" "t")
4034 (label_ref (match_operand 2 "" ""))))]
4038 if (get_attr_length (insn) == 4)
4039 return \"b%C0 %1,%#,%l2\";
4041 return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
4043 [(set (attr "length")
4045 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4046 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4049 (set (attr "far_jump")
4051 (eq_attr "length" "4")
4053 (const_string "yes")))
4056 (eq_attr "length" "4")
4057 (const_string "branch")
4058 (const_string "multi")))])
4060 (define_insn "*branch_fp_true"
4062 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
4063 [(match_operand 1 "fcc_operand" "u")
4065 (label_ref (match_operand 2 "" ""))
4070 if (get_attr_length (insn) == 4)
4071 return \"fb%f0 %1,%#,%l2\";
4073 return \"fb%F0 %1,%#,1f\;call %l2\\n1:\";
4075 [(set (attr "length")
4077 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4078 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4081 (set (attr "far_jump")
4083 (eq_attr "length" "4")
4085 (const_string "yes")))
4088 (eq_attr "length" "4")
4089 (const_string "branch")
4090 (const_string "multi")))])
4092 (define_insn "*branch_fp_false"
4094 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
4095 [(match_operand 1 "fcc_operand" "u")
4098 (label_ref (match_operand 2 "" ""))))]
4102 if (get_attr_length (insn) == 4)
4103 return \"fb%F0 %1,%#,%l2\";
4105 return \"fb%f0 %1,%#,1f\;call %l2\\n1:\";
4107 [(set (attr "length")
4109 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4110 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4113 (set (attr "far_jump")
4115 (eq_attr "length" "4")
4117 (const_string "yes")))
4120 (eq_attr "length" "4")
4121 (const_string "branch")
4122 (const_string "multi")))])
4125 ;; ::::::::::::::::::::
4127 ;; :: Set flag operations
4129 ;; ::::::::::::::::::::
4131 ;; Define_expands called by the machine independent part of the compiler
4132 ;; to allocate a new comparison register
4134 (define_expand "seq"
4135 [(match_operand:SI 0 "integer_register_operand" "")]
4139 if (! frv_emit_scc (EQ, operands[0]))
4145 (define_expand "sne"
4146 [(match_operand:SI 0 "integer_register_operand" "")]
4150 if (! frv_emit_scc (NE, operands[0]))
4156 (define_expand "slt"
4157 [(match_operand:SI 0 "integer_register_operand" "")]
4161 if (! frv_emit_scc (LT, operands[0]))
4167 (define_expand "sle"
4168 [(match_operand:SI 0 "integer_register_operand" "")]
4172 if (! frv_emit_scc (LE, operands[0]))
4178 (define_expand "sgt"
4179 [(match_operand:SI 0 "integer_register_operand" "")]
4183 if (! frv_emit_scc (GT, operands[0]))
4189 (define_expand "sge"
4190 [(match_operand:SI 0 "integer_register_operand" "")]
4194 if (! frv_emit_scc (GE, operands[0]))
4200 (define_expand "sltu"
4201 [(match_operand:SI 0 "integer_register_operand" "")]
4205 if (! frv_emit_scc (LTU, operands[0]))
4211 (define_expand "sleu"
4212 [(match_operand:SI 0 "integer_register_operand" "")]
4216 if (! frv_emit_scc (LEU, operands[0]))
4222 (define_expand "sgtu"
4223 [(match_operand:SI 0 "integer_register_operand" "")]
4227 if (! frv_emit_scc (GTU, operands[0]))
4233 (define_expand "sgeu"
4234 [(match_operand:SI 0 "integer_register_operand" "")]
4238 if (! frv_emit_scc (GEU, operands[0]))
4244 (define_insn "*scc_int"
4245 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4246 (match_operator:SI 1 "integer_relational_operator"
4247 [(match_operand 2 "icc_operand" "t")
4249 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4252 [(set_attr "length" "12")
4253 (set_attr "type" "multi")])
4255 (define_insn "*scc_float"
4256 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4257 (match_operator:SI 1 "float_relational_operator"
4258 [(match_operand:CC_FP 2 "fcc_operand" "u")
4260 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4263 [(set_attr "length" "12")
4264 (set_attr "type" "multi")])
4266 ;; XXX -- add reload_completed to the splits, because register allocation
4267 ;; currently isn't ready to see cond_exec packets.
4269 [(set (match_operand:SI 0 "integer_register_operand" "")
4270 (match_operator:SI 1 "relational_operator"
4271 [(match_operand 2 "cc_operand" "")
4273 (clobber (match_operand 3 "cr_operand" ""))]
4276 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4277 operands[3], (HOST_WIDE_INT) 1);")
4279 (define_insn "*scc_neg1_int"
4280 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4281 (neg:SI (match_operator:SI 1 "integer_relational_operator"
4282 [(match_operand 2 "icc_operand" "t")
4284 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4287 [(set_attr "length" "12")
4288 (set_attr "type" "multi")])
4290 (define_insn "*scc_neg1_float"
4291 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4292 (neg:SI (match_operator:SI 1 "float_relational_operator"
4293 [(match_operand:CC_FP 2 "fcc_operand" "u")
4295 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4298 [(set_attr "length" "12")
4299 (set_attr "type" "multi")])
4302 [(set (match_operand:SI 0 "integer_register_operand" "")
4303 (neg:SI (match_operator:SI 1 "relational_operator"
4304 [(match_operand 2 "cc_operand" "")
4306 (clobber (match_operand 3 "cr_operand" ""))]
4309 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4310 operands[3], (HOST_WIDE_INT) -1);")
4313 ;; ::::::::::::::::::::
4315 ;; :: Conditionally executed instructions
4317 ;; ::::::::::::::::::::
4319 ;; Convert ICC/FCC comparison into CCR bits so we can do conditional execution
4320 (define_insn "*ck_signed"
4321 [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4322 (match_operator:CC_CCR 1 "integer_relational_operator"
4323 [(match_operand 2 "icc_operand" "t")
4327 [(set_attr "length" "4")
4328 (set_attr "type" "ccr")])
4330 (define_insn "*fck_float"
4331 [(set (match_operand:CC_CCR 0 "fcr_operand" "=w")
4332 (match_operator:CC_CCR 1 "float_relational_operator"
4333 [(match_operand:CC_FP 2 "fcc_operand" "u")
4337 [(set_attr "length" "4")
4338 (set_attr "type" "ccr")])
4340 ;; Conditionally convert ICC/FCC comparison into CCR bits to provide && and ||
4341 ;; tests in conditional execution
4342 (define_insn "cond_exec_ck"
4343 [(set (match_operand:CC_CCR 0 "cr_operand" "=v,w")
4344 (if_then_else:CC_CCR (match_operator 1 "ccr_eqne_operator"
4345 [(match_operand 2 "cr_operand" "C,C")
4347 (match_operator 3 "relational_operator"
4348 [(match_operand 4 "cc_operand" "t,u")
4353 cck%c3 %4, %0, %2, %e1
4354 cfck%f3 %4, %0, %2, %e1"
4355 [(set_attr "length" "4")
4356 (set_attr "type" "ccr")])
4358 ;; Conditionally set a register to either 0 or another register
4359 (define_insn "*cond_exec_movqi"
4361 (match_operator 0 "ccr_eqne_operator"
4362 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4364 (set (match_operand:QI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4365 (match_operand:QI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4366 "register_operand(operands[2], QImode) || reg_or_0_operand (operands[3], QImode)"
4367 "* return output_condmove_single (operands, insn);"
4368 [(set_attr "length" "4")
4369 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4371 (define_insn "*cond_exec_movhi"
4373 (match_operator 0 "ccr_eqne_operator"
4374 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4376 (set (match_operand:HI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4377 (match_operand:HI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4378 "register_operand(operands[2], HImode) || reg_or_0_operand (operands[3], HImode)"
4379 "* return output_condmove_single (operands, insn);"
4380 [(set_attr "length" "4")
4381 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4383 (define_insn "*cond_exec_movsi"
4385 (match_operator 0 "ccr_eqne_operator"
4386 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C")
4388 (set (match_operand:SI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d,?f,?m")
4389 (match_operand:SI 3 "condexec_source_operand" "dO,U,dO,f,d,f,m,f")))]
4390 "register_operand(operands[2], SImode) || reg_or_0_operand (operands[3], SImode)"
4391 "* return output_condmove_single (operands, insn);"
4392 [(set_attr "length" "4")
4393 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg,fload,fstore")])
4396 (define_insn "*cond_exec_movsf_has_fprs"
4398 (match_operator 0 "ccr_eqne_operator"
4399 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C,C,C")
4401 (set (match_operand:SF 2 "condexec_dest_operand" "=f,?d,?d,?f,f,f,?d,U,?U,U")
4402 (match_operand:SF 3 "condexec_source_operand" "f,d,f,d,G,U,U,f,d,G")))]
4404 "* return output_condmove_single (operands, insn);"
4405 [(set_attr "length" "4")
4406 (set_attr "type" "fsconv,int,movgf,movfg,movgf,fload,gload,fstore,gstore,gstore")])
4408 (define_insn "*cond_exec_movsf_no_fprs"
4410 (match_operator 0 "ccr_eqne_operator"
4411 [(match_operand 1 "cr_operand" "C,C,C")
4413 (set (match_operand:SF 2 "condexec_dest_operand" "=d,d,U")
4414 (match_operand:SF 3 "condexec_source_operand" "d,U,dG")))]
4416 "* return output_condmove_single (operands, insn);"
4417 [(set_attr "length" "4")
4418 (set_attr "type" "int,gload,gstore")])
4420 (define_insn "*cond_exec_si_binary1"
4422 (match_operator 0 "ccr_eqne_operator"
4423 [(match_operand 1 "cr_operand" "C")
4425 (set (match_operand:SI 2 "integer_register_operand" "=d")
4426 (match_operator:SI 3 "condexec_si_binary_operator"
4427 [(match_operand:SI 4 "integer_register_operand" "d")
4428 (match_operand:SI 5 "integer_register_operand" "d")])))]
4432 switch (GET_CODE (operands[3]))
4434 case PLUS: return \"cadd %4, %z5, %2, %1, %e0\";
4435 case MINUS: return \"csub %4, %z5, %2, %1, %e0\";
4436 case AND: return \"cand %4, %z5, %2, %1, %e0\";
4437 case IOR: return \"cor %4, %z5, %2, %1, %e0\";
4438 case XOR: return \"cxor %4, %z5, %2, %1, %e0\";
4439 case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
4440 case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
4441 case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
4442 default: gcc_unreachable ();
4445 [(set_attr "length" "4")
4446 (set_attr "type" "int")])
4448 (define_insn "*cond_exec_si_binary2"
4450 (match_operator 0 "ccr_eqne_operator"
4451 [(match_operand 1 "cr_operand" "C")
4453 (set (match_operand:SI 2 "fpr_operand" "=f")
4454 (match_operator:SI 3 "condexec_si_media_operator"
4455 [(match_operand:SI 4 "fpr_operand" "f")
4456 (match_operand:SI 5 "fpr_operand" "f")])))]
4460 switch (GET_CODE (operands[3]))
4462 case AND: return \"cmand %4, %5, %2, %1, %e0\";
4463 case IOR: return \"cmor %4, %5, %2, %1, %e0\";
4464 case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
4465 default: gcc_unreachable ();
4468 [(set_attr "length" "4")
4469 (set_attr "type" "mlogic")])
4471 ;; Note, flow does not (currently) know how to handle an operation that uses
4472 ;; only part of the hard registers allocated for a multiregister value, such as
4473 ;; DImode in this case if the user is only interested in the lower 32-bits. So
4474 ;; we emit a USE of the entire register after the csmul instruction so it won't
4475 ;; get confused. See frv_ifcvt_modify_insn for more details.
4477 (define_insn "*cond_exec_si_smul"
4479 (match_operator 0 "ccr_eqne_operator"
4480 [(match_operand 1 "cr_operand" "C")
4482 (set (match_operand:DI 2 "even_gpr_operand" "=e")
4483 (mult:DI (sign_extend:DI (match_operand:SI 3 "integer_register_operand" "%d"))
4484 (sign_extend:DI (match_operand:SI 4 "integer_register_operand" "d")))))]
4486 "csmul %3, %4, %2, %1, %e0"
4487 [(set_attr "length" "4")
4488 (set_attr "type" "mul")])
4490 (define_insn "*cond_exec_si_divide"
4492 (match_operator 0 "ccr_eqne_operator"
4493 [(match_operand 1 "cr_operand" "C")
4495 (set (match_operand:SI 2 "integer_register_operand" "=d")
4496 (match_operator:SI 3 "condexec_si_divide_operator"
4497 [(match_operand:SI 4 "integer_register_operand" "d")
4498 (match_operand:SI 5 "integer_register_operand" "d")])))]
4502 switch (GET_CODE (operands[3]))
4504 case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
4505 case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
4506 default: gcc_unreachable ();
4509 [(set_attr "length" "4")
4510 (set_attr "type" "div")])
4512 (define_insn "*cond_exec_si_unary1"
4514 (match_operator 0 "ccr_eqne_operator"
4515 [(match_operand 1 "cr_operand" "C")
4517 (set (match_operand:SI 2 "integer_register_operand" "=d")
4518 (match_operator:SI 3 "condexec_si_unary_operator"
4519 [(match_operand:SI 4 "integer_register_operand" "d")])))]
4523 switch (GET_CODE (operands[3]))
4525 case NOT: return \"cnot %4, %2, %1, %e0\";
4526 case NEG: return \"csub %., %4, %2, %1, %e0\";
4527 default: gcc_unreachable ();
4530 [(set_attr "length" "4")
4531 (set_attr "type" "int")])
4533 (define_insn "*cond_exec_si_unary2"
4535 (match_operator 0 "ccr_eqne_operator"
4536 [(match_operand 1 "cr_operand" "C")
4538 (set (match_operand:SI 2 "fpr_operand" "=f")
4539 (not:SI (match_operand:SI 3 "fpr_operand" "f"))))]
4541 "cmnot %3, %2, %1, %e0"
4542 [(set_attr "length" "4")
4543 (set_attr "type" "mlogic")])
4545 (define_insn "*cond_exec_cmpsi_cc"
4547 (match_operator 0 "ccr_eqne_operator"
4548 [(match_operand 1 "cr_operand" "C")
4550 (set (match_operand:CC 2 "icc_operand" "=t")
4551 (compare:CC (match_operand:SI 3 "integer_register_operand" "d")
4552 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4554 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4555 "ccmp %3, %z4, %1, %e0"
4556 [(set_attr "length" "4")
4557 (set_attr "type" "int")])
4559 (define_insn "*cond_exec_cmpsi_cc_uns"
4561 (match_operator 0 "ccr_eqne_operator"
4562 [(match_operand 1 "cr_operand" "C")
4564 (set (match_operand:CC_UNS 2 "icc_operand" "=t")
4565 (compare:CC_UNS (match_operand:SI 3 "integer_register_operand" "d")
4566 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4568 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4569 "ccmp %3, %z4, %1, %e0"
4570 [(set_attr "length" "4")
4571 (set_attr "type" "int")])
4573 (define_insn "*cond_exec_cmpsi_cc_nz"
4575 (match_operator 0 "ccr_eqne_operator"
4576 [(match_operand 1 "cr_operand" "C")
4578 (set (match_operand:CC_NZ 2 "icc_operand" "=t")
4579 (compare:CC_NZ (match_operand:SI 3 "integer_register_operand" "d")
4582 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4583 "ccmp %3, %., %1, %e0"
4584 [(set_attr "length" "4")
4585 (set_attr "type" "int")])
4587 (define_insn "*cond_exec_sf_conv"
4589 (match_operator 0 "ccr_eqne_operator"
4590 [(match_operand 1 "cr_operand" "C")
4592 (set (match_operand:SF 2 "fpr_operand" "=f")
4593 (match_operator:SF 3 "condexec_sf_conv_operator"
4594 [(match_operand:SF 4 "fpr_operand" "f")])))]
4598 switch (GET_CODE (operands[3]))
4600 case ABS: return \"cfabss %4, %2, %1, %e0\";
4601 case NEG: return \"cfnegs %4, %2, %1, %e0\";
4602 default: gcc_unreachable ();
4605 [(set_attr "length" "4")
4606 (set_attr "type" "fsconv")])
4608 (define_insn "*cond_exec_sf_add"
4610 (match_operator 0 "ccr_eqne_operator"
4611 [(match_operand 1 "cr_operand" "C")
4613 (set (match_operand:SF 2 "fpr_operand" "=f")
4614 (match_operator:SF 3 "condexec_sf_add_operator"
4615 [(match_operand:SF 4 "fpr_operand" "f")
4616 (match_operand:SF 5 "fpr_operand" "f")])))]
4620 switch (GET_CODE (operands[3]))
4622 case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
4623 case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
4624 default: gcc_unreachable ();
4627 [(set_attr "length" "4")
4628 (set_attr "type" "fsadd")])
4630 (define_insn "*cond_exec_sf_mul"
4632 (match_operator 0 "ccr_eqne_operator"
4633 [(match_operand 1 "cr_operand" "C")
4635 (set (match_operand:SF 2 "fpr_operand" "=f")
4636 (mult:SF (match_operand:SF 3 "fpr_operand" "f")
4637 (match_operand:SF 4 "fpr_operand" "f"))))]
4639 "cfmuls %3, %4, %2, %1, %e0"
4640 [(set_attr "length" "4")
4641 (set_attr "type" "fsmul")])
4643 (define_insn "*cond_exec_sf_div"
4645 (match_operator 0 "ccr_eqne_operator"
4646 [(match_operand 1 "cr_operand" "C")
4648 (set (match_operand:SF 2 "fpr_operand" "=f")
4649 (div:SF (match_operand:SF 3 "fpr_operand" "f")
4650 (match_operand:SF 4 "fpr_operand" "f"))))]
4652 "cfdivs %3, %4, %2, %1, %e0"
4653 [(set_attr "length" "4")
4654 (set_attr "type" "fsdiv")])
4656 (define_insn "*cond_exec_sf_sqrt"
4658 (match_operator 0 "ccr_eqne_operator"
4659 [(match_operand 1 "cr_operand" "C")
4661 (set (match_operand:SF 2 "fpr_operand" "=f")
4662 (sqrt:SF (match_operand:SF 3 "fpr_operand" "f"))))]
4664 "cfsqrts %3, %2, %1, %e0"
4665 [(set_attr "length" "4")
4666 (set_attr "type" "fsdiv")])
4668 (define_insn "*cond_exec_cmpsi_cc_fp"
4670 (match_operator 0 "ccr_eqne_operator"
4671 [(match_operand 1 "cr_operand" "C")
4673 (set (match_operand:CC_FP 2 "fcc_operand" "=u")
4674 (compare:CC_FP (match_operand:SF 3 "fpr_operand" "f")
4675 (match_operand:SF 4 "fpr_operand" "f"))))]
4676 "reload_completed && TARGET_HARD_FLOAT
4677 && REGNO (operands[1]) == REGNO (operands[2]) - FCC_FIRST + FCR_FIRST"
4678 "cfcmps %3, %4, %2, %1, %e0"
4679 [(set_attr "length" "4")
4680 (set_attr "type" "fsconv")])
4683 ;; ::::::::::::::::::::
4685 ;; :: Logical operations on CR registers
4687 ;; ::::::::::::::::::::
4689 ;; We use UNSPEC to encode andcr/iorcr/etc. rather than the normal RTL
4690 ;; operations, since the RTL operations only have an idea of TRUE and FALSE,
4691 ;; while the CRs have TRUE, FALSE, and UNDEFINED.
4693 (define_expand "andcr"
4694 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4695 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4696 (match_operand:CC_CCR 2 "cr_operand" "")
4697 (const_int 0)] UNSPEC_CR_LOGIC))]
4701 (define_expand "orcr"
4702 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4703 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4704 (match_operand:CC_CCR 2 "cr_operand" "")
4705 (const_int 1)] UNSPEC_CR_LOGIC))]
4709 (define_expand "xorcr"
4710 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4711 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4712 (match_operand:CC_CCR 2 "cr_operand" "")
4713 (const_int 2)] UNSPEC_CR_LOGIC))]
4717 (define_expand "nandcr"
4718 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4719 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4720 (match_operand:CC_CCR 2 "cr_operand" "")
4721 (const_int 3)] UNSPEC_CR_LOGIC))]
4725 (define_expand "norcr"
4726 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4727 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4728 (match_operand:CC_CCR 2 "cr_operand" "")
4729 (const_int 4)] UNSPEC_CR_LOGIC))]
4733 (define_expand "andncr"
4734 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4735 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4736 (match_operand:CC_CCR 2 "cr_operand" "")
4737 (const_int 5)] UNSPEC_CR_LOGIC))]
4741 (define_expand "orncr"
4742 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4743 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4744 (match_operand:CC_CCR 2 "cr_operand" "")
4745 (const_int 6)] UNSPEC_CR_LOGIC))]
4749 (define_expand "nandncr"
4750 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4751 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4752 (match_operand:CC_CCR 2 "cr_operand" "")
4753 (const_int 7)] UNSPEC_CR_LOGIC))]
4757 (define_expand "norncr"
4758 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4759 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4760 (match_operand:CC_CCR 2 "cr_operand" "")
4761 (const_int 8)] UNSPEC_CR_LOGIC))]
4765 (define_expand "notcr"
4766 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4767 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4769 (const_int 9)] UNSPEC_CR_LOGIC))]
4773 (define_insn "*logical_cr"
4774 [(set (match_operand:CC_CCR 0 "cr_operand" "=C")
4775 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "C")
4776 (match_operand:CC_CCR 2 "cr_operand" "C")
4777 (match_operand:SI 3 "const_int_operand" "n")]
4782 switch (INTVAL (operands[3]))
4785 case 0: return \"andcr %1, %2, %0\";
4786 case 1: return \"orcr %1, %2, %0\";
4787 case 2: return \"xorcr %1, %2, %0\";
4788 case 3: return \"nandcr %1, %2, %0\";
4789 case 4: return \"norcr %1, %2, %0\";
4790 case 5: return \"andncr %1, %2, %0\";
4791 case 6: return \"orncr %1, %2, %0\";
4792 case 7: return \"nandncr %1, %2, %0\";
4793 case 8: return \"norncr %1, %2, %0\";
4794 case 9: return \"notcr %1, %0\";
4797 fatal_insn (\"logical_cr\", insn);
4799 [(set_attr "length" "4")
4800 (set_attr "type" "ccr")])
4803 ;; ::::::::::::::::::::
4805 ;; :: Conditional move instructions
4807 ;; ::::::::::::::::::::
4810 ;; - conditional moves based on floating-point comparisons require
4811 ;; TARGET_HARD_FLOAT, because an FPU is required to do the comparison.
4813 ;; - conditional moves between FPRs based on integer comparisons
4814 ;; require TARGET_HAS_FPRS.
4816 (define_expand "movqicc"
4817 [(set (match_operand:QI 0 "integer_register_operand" "")
4818 (if_then_else:QI (match_operand 1 "" "")
4819 (match_operand:QI 2 "gpr_or_int_operand" "")
4820 (match_operand:QI 3 "gpr_or_int_operand" "")))]
4824 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4830 (define_insn "*movqicc_internal1_int"
4831 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4832 (if_then_else:QI (match_operator 1 "integer_relational_operator"
4833 [(match_operand 2 "icc_operand" "t,t,t")
4835 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4836 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4837 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4840 [(set_attr "length" "8,8,12")
4841 (set_attr "type" "multi")])
4843 (define_insn "*movqicc_internal1_float"
4844 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4845 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4846 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4848 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4849 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4850 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4853 [(set_attr "length" "8,8,12")
4854 (set_attr "type" "multi")])
4856 (define_insn "*movqicc_internal2_int"
4857 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4858 (if_then_else:QI (match_operator 1 "integer_relational_operator"
4859 [(match_operand 2 "icc_operand" "t,t,t,t,t")
4861 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4862 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4863 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4864 "(INTVAL (operands[3]) == 0
4865 || INTVAL (operands[4]) == 0
4866 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4867 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4869 [(set_attr "length" "8,12,8,12,12")
4870 (set_attr "type" "multi")])
4872 (define_insn "*movqicc_internal2_float"
4873 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4874 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4875 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4877 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4878 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4879 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4881 && (INTVAL (operands[3]) == 0
4882 || INTVAL (operands[4]) == 0
4883 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4884 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4886 [(set_attr "length" "8,12,8,12,12")
4887 (set_attr "type" "multi")])
4890 [(set (match_operand:QI 0 "integer_register_operand" "")
4891 (if_then_else:QI (match_operator 1 "relational_operator"
4892 [(match_operand 2 "cc_operand" "")
4894 (match_operand:QI 3 "gpr_or_int_operand" "")
4895 (match_operand:QI 4 "gpr_or_int_operand" "")))
4896 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4899 "operands[6] = frv_split_cond_move (operands);")
4901 (define_expand "movhicc"
4902 [(set (match_operand:HI 0 "integer_register_operand" "")
4903 (if_then_else:HI (match_operand 1 "" "")
4904 (match_operand:HI 2 "gpr_or_int_operand" "")
4905 (match_operand:HI 3 "gpr_or_int_operand" "")))]
4909 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4915 (define_insn "*movhicc_internal1_int"
4916 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4917 (if_then_else:HI (match_operator 1 "integer_relational_operator"
4918 [(match_operand 2 "icc_operand" "t,t,t")
4920 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4921 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4922 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4925 [(set_attr "length" "8,8,12")
4926 (set_attr "type" "multi")])
4928 (define_insn "*movhicc_internal1_float"
4929 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4930 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4931 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4933 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4934 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4935 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4938 [(set_attr "length" "8,8,12")
4939 (set_attr "type" "multi")])
4941 (define_insn "*movhicc_internal2_int"
4942 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4943 (if_then_else:HI (match_operator 1 "integer_relational_operator"
4944 [(match_operand 2 "icc_operand" "t,t,t,t,t")
4946 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4947 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4948 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4949 "(INTVAL (operands[3]) == 0
4950 || INTVAL (operands[4]) == 0
4951 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4952 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4954 [(set_attr "length" "8,12,8,12,12")
4955 (set_attr "type" "multi")])
4957 (define_insn "*movhicc_internal2_float"
4958 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4959 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4960 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4962 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4963 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4964 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4966 && (INTVAL (operands[3]) == 0
4967 || INTVAL (operands[4]) == 0
4968 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4969 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4971 [(set_attr "length" "8,12,8,12,12")
4972 (set_attr "type" "multi")])
4975 [(set (match_operand:HI 0 "integer_register_operand" "")
4976 (if_then_else:HI (match_operator 1 "relational_operator"
4977 [(match_operand 2 "cc_operand" "")
4979 (match_operand:HI 3 "gpr_or_int_operand" "")
4980 (match_operand:HI 4 "gpr_or_int_operand" "")))
4981 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4984 "operands[6] = frv_split_cond_move (operands);")
4986 (define_expand "movsicc"
4987 [(set (match_operand:SI 0 "integer_register_operand" "")
4988 (if_then_else:SI (match_operand 1 "" "")
4989 (match_operand:SI 2 "gpr_or_int_operand" "")
4990 (match_operand:SI 3 "gpr_or_int_operand" "")))]
4994 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
5000 (define_insn "*movsicc_internal1_int"
5001 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
5002 (if_then_else:SI (match_operator 1 "integer_relational_operator"
5003 [(match_operand 2 "icc_operand" "t,t,t")
5005 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
5006 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
5007 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5010 [(set_attr "length" "8,8,12")
5011 (set_attr "type" "multi")])
5013 (define_insn "*movsicc_internal1_float"
5014 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
5015 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
5016 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
5018 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
5019 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
5020 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5023 [(set_attr "length" "8,8,12")
5024 (set_attr "type" "multi")])
5026 (define_insn "*movsicc_internal2_int"
5027 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
5028 (if_then_else:SI (match_operator 1 "integer_relational_operator"
5029 [(match_operand 2 "icc_operand" "t,t,t,t,t")
5031 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
5032 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
5033 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
5034 "(INTVAL (operands[3]) == 0
5035 || INTVAL (operands[4]) == 0
5036 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
5037 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
5039 [(set_attr "length" "8,12,8,12,12")
5040 (set_attr "type" "multi")])
5042 (define_insn "*movsicc_internal2_float"
5043 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
5044 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
5045 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
5047 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
5048 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
5049 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
5051 && (INTVAL (operands[3]) == 0
5052 || INTVAL (operands[4]) == 0
5053 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
5054 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
5056 [(set_attr "length" "8,12,8,12,12")
5057 (set_attr "type" "multi")])
5060 [(set (match_operand:SI 0 "integer_register_operand" "")
5061 (if_then_else:SI (match_operator 1 "relational_operator"
5062 [(match_operand 2 "cc_operand" "")
5064 (match_operand:SI 3 "gpr_or_int_operand" "")
5065 (match_operand:SI 4 "gpr_or_int_operand" "")))
5066 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
5069 "operands[6] = frv_split_cond_move (operands);")
5071 (define_expand "movsfcc"
5072 [(set (match_operand:SF 0 "register_operand" "")
5073 (if_then_else:SF (match_operand 1 "" "")
5074 (match_operand:SF 2 "register_operand" "")
5075 (match_operand:SF 3 "register_operand" "")))]
5079 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
5085 (define_insn "*movsfcc_has_fprs_int"
5086 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
5087 (if_then_else:SF (match_operator 1 "integer_relational_operator"
5088 [(match_operand 2 "icc_operand" "t,t,t,t,t,t")
5090 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
5091 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
5092 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
5095 [(set_attr "length" "8,8,12,12,12,12")
5096 (set_attr "type" "multi")])
5098 (define_insn "*movsfcc_hardfloat_float"
5099 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
5100 (if_then_else:SF (match_operator:CC_FP 1 "float_relational_operator"
5101 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u,u")
5103 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
5104 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
5105 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w,w"))]
5108 [(set_attr "length" "8,8,12,12,12,12")
5109 (set_attr "type" "multi")])
5111 (define_insn "*movsfcc_no_fprs_int"
5112 [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
5113 (if_then_else:SF (match_operator 1 "integer_relational_operator"
5114 [(match_operand 2 "icc_operand" "t,t,t")
5116 (match_operand:SF 3 "integer_register_operand" "0,d,d")
5117 (match_operand:SF 4 "integer_register_operand" "d,0,d")))
5118 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5121 [(set_attr "length" "8,8,12")
5122 (set_attr "type" "multi")])
5125 [(set (match_operand:SF 0 "register_operand" "")
5126 (if_then_else:SF (match_operator 1 "relational_operator"
5127 [(match_operand 2 "cc_operand" "")
5129 (match_operand:SF 3 "register_operand" "")
5130 (match_operand:SF 4 "register_operand" "")))
5131 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
5134 "operands[6] = frv_split_cond_move (operands);")
5137 ;; ::::::::::::::::::::
5139 ;; :: Minimum, maximum, and integer absolute value
5141 ;; ::::::::::::::::::::
5143 ;; These 'instructions' are provided to give the compiler a slightly better
5144 ;; nudge at register allocation, then it would if it constructed the
5145 ;; instructions from basic building blocks (since it indicates it prefers one
5146 ;; of the operands to be the same as the destination. It also helps the
5147 ;; earlier passes of the compiler, by not breaking things into small basic
5150 (define_expand "abssi2"
5151 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5152 (abs:SI (match_operand:SI 1 "integer_register_operand" "")))
5153 (clobber (match_dup 2))
5154 (clobber (match_dup 3))])]
5158 operands[2] = gen_reg_rtx (CCmode);
5159 operands[3] = gen_reg_rtx (CC_CCRmode);
5162 (define_insn_and_split "*abssi2_internal"
5163 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
5164 (abs:SI (match_operand:SI 1 "integer_register_operand" "0,d")))
5165 (clobber (match_operand:CC 2 "icc_operand" "=t,t"))
5166 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v,v"))]
5171 "operands[4] = frv_split_abs (operands);"
5172 [(set_attr "length" "12,16")
5173 (set_attr "type" "multi")])
5175 (define_expand "sminsi3"
5176 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5177 (smin:SI (match_operand:SI 1 "integer_register_operand" "")
5178 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5179 (clobber (match_dup 3))
5180 (clobber (match_dup 4))])]
5184 operands[3] = gen_reg_rtx (CCmode);
5185 operands[4] = gen_reg_rtx (CC_CCRmode);
5188 (define_expand "smaxsi3"
5189 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5190 (smax:SI (match_operand:SI 1 "integer_register_operand" "")
5191 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5192 (clobber (match_dup 3))
5193 (clobber (match_dup 4))])]
5197 operands[3] = gen_reg_rtx (CCmode);
5198 operands[4] = gen_reg_rtx (CC_CCRmode);
5201 (define_insn_and_split "*minmax_si_signed"
5202 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5203 (match_operator:SI 1 "minmax_operator"
5204 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5205 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5206 (clobber (match_operand:CC 4 "icc_operand" "=t,t,t"))
5207 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5212 "operands[6] = frv_split_minmax (operands);"
5213 [(set_attr "length" "12,12,16")
5214 (set_attr "type" "multi")])
5216 (define_expand "uminsi3"
5217 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5218 (umin:SI (match_operand:SI 1 "integer_register_operand" "")
5219 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5220 (clobber (match_dup 3))
5221 (clobber (match_dup 4))])]
5225 operands[3] = gen_reg_rtx (CC_UNSmode);
5226 operands[4] = gen_reg_rtx (CC_CCRmode);
5229 (define_expand "umaxsi3"
5230 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5231 (umax:SI (match_operand:SI 1 "integer_register_operand" "")
5232 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5233 (clobber (match_dup 3))
5234 (clobber (match_dup 4))])]
5238 operands[3] = gen_reg_rtx (CC_UNSmode);
5239 operands[4] = gen_reg_rtx (CC_CCRmode);
5242 (define_insn_and_split "*minmax_si_unsigned"
5243 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5244 (match_operator:SI 1 "minmax_operator"
5245 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5246 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5247 (clobber (match_operand:CC_UNS 4 "icc_operand" "=t,t,t"))
5248 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5253 "operands[6] = frv_split_minmax (operands);"
5254 [(set_attr "length" "12,12,16")
5255 (set_attr "type" "multi")])
5257 (define_expand "sminsf3"
5258 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5259 (smin:SF (match_operand:SF 1 "fpr_operand" "")
5260 (match_operand:SF 2 "fpr_operand" "")))
5261 (clobber (match_dup 3))
5262 (clobber (match_dup 4))])]
5263 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5266 operands[3] = gen_reg_rtx (CC_FPmode);
5267 operands[4] = gen_reg_rtx (CC_CCRmode);
5270 (define_expand "smaxsf3"
5271 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5272 (smax:SF (match_operand:SF 1 "fpr_operand" "")
5273 (match_operand:SF 2 "fpr_operand" "")))
5274 (clobber (match_dup 3))
5275 (clobber (match_dup 4))])]
5276 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5279 operands[3] = gen_reg_rtx (CC_FPmode);
5280 operands[4] = gen_reg_rtx (CC_CCRmode);
5283 (define_insn_and_split "*minmax_sf"
5284 [(set (match_operand:SF 0 "fpr_operand" "=f,f,f")
5285 (match_operator:SF 1 "minmax_operator"
5286 [(match_operand:SF 2 "fpr_operand" "%0,f,f")
5287 (match_operand:SF 3 "fpr_operand" "f,0,f")]))
5288 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5289 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5290 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5294 "operands[6] = frv_split_minmax (operands);"
5295 [(set_attr "length" "12,12,16")
5296 (set_attr "type" "multi")])
5298 (define_expand "smindf3"
5299 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5300 (smin:DF (match_operand:DF 1 "fpr_operand" "")
5301 (match_operand:DF 2 "fpr_operand" "")))
5302 (clobber (match_dup 3))
5303 (clobber (match_dup 4))])]
5304 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5307 operands[3] = gen_reg_rtx (CC_FPmode);
5308 operands[4] = gen_reg_rtx (CC_CCRmode);
5311 (define_expand "smaxdf3"
5312 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5313 (smax:DF (match_operand:DF 1 "fpr_operand" "")
5314 (match_operand:DF 2 "fpr_operand" "")))
5315 (clobber (match_dup 3))
5316 (clobber (match_dup 4))])]
5317 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5320 operands[3] = gen_reg_rtx (CC_FPmode);
5321 operands[4] = gen_reg_rtx (CC_CCRmode);
5324 (define_insn_and_split "*minmax_df"
5325 [(set (match_operand:DF 0 "fpr_operand" "=f,f,f")
5326 (match_operator:DF 1 "minmax_operator"
5327 [(match_operand:DF 2 "fpr_operand" "%0,f,f")
5328 (match_operand:DF 3 "fpr_operand" "f,0,f")]))
5329 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5330 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5331 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5335 "operands[6] = frv_split_minmax (operands);"
5336 [(set_attr "length" "12,12,16")
5337 (set_attr "type" "multi")])
5340 ;; ::::::::::::::::::::
5342 ;; :: Call and branch instructions
5344 ;; ::::::::::::::::::::
5346 ;; Subroutine call instruction returning no value. Operand 0 is the function
5347 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5348 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5349 ;; registers used as operands.
5351 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5352 ;; is supplied for the sake of some RISC machines which need to put this
5353 ;; information into the assembler code; they can put it in the RTL instead of
5356 (define_expand "call"
5357 [(use (match_operand:QI 0 "" ""))
5358 (use (match_operand 1 "" ""))
5359 (use (match_operand 2 "" ""))
5360 (use (match_operand 3 "" ""))]
5364 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5367 gcc_assert (GET_CODE (operands[0]) == MEM);
5369 addr = XEXP (operands[0], 0);
5370 if (! call_operand (addr, Pmode))
5371 addr = force_reg (Pmode, addr);
5374 operands[2] = const0_rtx;
5377 frv_expand_fdpic_call (operands, false, false);
5379 emit_call_insn (gen_call_internal (addr, operands[1], operands[2], lr));
5384 (define_insn "call_internal"
5385 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5386 (match_operand 1 "" ""))
5387 (use (match_operand 2 "" ""))
5388 (clobber (match_operand:SI 3 "lr_operand" "=l,l"))]
5393 [(set_attr "length" "4")
5394 (set_attr "type" "call,jumpl")])
5396 ;; The odd use of GR0 within the UNSPEC below prevents cseing or
5397 ;; hoisting function descriptor loads out of loops. This is almost
5398 ;; never desirable, since if we preserve the function descriptor in a
5399 ;; pair of registers, it takes two insns to move it to gr14/gr15, and
5400 ;; if it's in the stack, we just waste space with the store, since
5401 ;; we'll have to load back from memory anyway. And, in the worst
5402 ;; case, we may end up reusing a function descriptor still pointing at
5403 ;; a PLT entry, instead of to the resolved function, which means going
5404 ;; through the resolver for every call that uses the outdated value.
5407 ;; The explicit MEM inside the SPEC prevents the compiler from moving
5408 ;; the load before a branch after a NULL test, or before a store that
5409 ;; initializes a function descriptor.
5411 (define_insn "movdi_ldd"
5412 [(set (match_operand:DI 0 "fdpic_fptr_operand" "=e")
5413 (unspec:DI [(mem:DI (match_operand:SI 1 "ldd_address_operand" "p"))
5414 (reg:SI 0)] UNSPEC_LDD))]
5417 [(set_attr "length" "4")
5418 (set_attr "type" "gload")])
5420 (define_insn "call_fdpicdi"
5421 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5422 (match_operand 1 "" ""))
5423 (clobber (match_operand:SI 2 "lr_operand" "=l"))]
5426 [(set_attr "length" "4")
5427 (set_attr "type" "jumpl")])
5429 (define_insn "call_fdpicsi"
5430 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5431 (match_operand 1 "" ""))
5432 (use (match_operand 2 "" ""))
5433 (use (match_operand:SI 3 "fdpic_operand" "Z,Z"))
5434 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5439 [(set_attr "length" "4")
5440 (set_attr "type" "call,jumpl")])
5442 (define_expand "sibcall"
5443 [(use (match_operand:QI 0 "" ""))
5444 (use (match_operand 1 "" ""))
5445 (use (match_operand 2 "" ""))
5446 (use (match_operand 3 "" ""))]
5452 gcc_assert (GET_CODE (operands[0]) == MEM);
5454 addr = XEXP (operands[0], 0);
5455 if (! sibcall_operand (addr, Pmode))
5456 addr = force_reg (Pmode, addr);
5459 operands[2] = const0_rtx;
5462 frv_expand_fdpic_call (operands, false, true);
5464 emit_call_insn (gen_sibcall_internal (addr, operands[1], operands[2]));
5469 ;; It might seem that these sibcall patterns are missing references to
5470 ;; LR, but they're not necessary because sibcall_epilogue will make
5471 ;; sure LR is restored, and having LR here will set
5472 ;; regs_ever_used[REG_LR], forcing it to be saved on the stack, and
5473 ;; then restored in sibcalls and regular return code paths, even if
5474 ;; the function becomes a leaf function after tail-call elimination.
5476 ;; We must not use a call-saved register here. `W' limits ourselves
5477 ;; to gr14 or gr15, but since we're almost running out of constraint
5478 ;; letters, and most other call-clobbered registers are often used for
5479 ;; argument-passing, this will do.
5480 (define_insn "sibcall_internal"
5481 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" "WNOP"))
5482 (match_operand 1 "" ""))
5483 (use (match_operand 2 "" ""))
5487 [(set_attr "length" "4")
5488 (set_attr "type" "jumpl")])
5490 (define_insn "sibcall_fdpicdi"
5491 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5492 (match_operand 1 "" ""))
5496 [(set_attr "length" "4")
5497 (set_attr "type" "jumpl")])
5500 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5501 ;; register in which the value is returned. There are three more operands, the
5502 ;; same as the three operands of the `call' instruction (but with numbers
5503 ;; increased by one).
5505 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5507 (define_expand "call_value"
5508 [(use (match_operand 0 "" ""))
5509 (use (match_operand:QI 1 "" ""))
5510 (use (match_operand 2 "" ""))
5511 (use (match_operand 3 "" ""))
5512 (use (match_operand 4 "" ""))]
5516 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5519 gcc_assert (GET_CODE (operands[1]) == MEM);
5521 addr = XEXP (operands[1], 0);
5522 if (! call_operand (addr, Pmode))
5523 addr = force_reg (Pmode, addr);
5526 operands[3] = const0_rtx;
5529 frv_expand_fdpic_call (operands, true, false);
5531 emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
5537 (define_insn "call_value_internal"
5538 [(set (match_operand 0 "register_operand" "=d,d")
5539 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5540 (match_operand 2 "" "")))
5541 (use (match_operand 3 "" ""))
5542 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5547 [(set_attr "length" "4")
5548 (set_attr "type" "call,jumpl")])
5550 (define_insn "call_value_fdpicdi"
5551 [(set (match_operand 0 "register_operand" "=d")
5552 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5553 (match_operand 2 "" "")))
5554 (clobber (match_operand:SI 3 "lr_operand" "=l"))]
5557 [(set_attr "length" "4")
5558 (set_attr "type" "jumpl")])
5560 (define_insn "call_value_fdpicsi"
5561 [(set (match_operand 0 "register_operand" "=d,d")
5562 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5563 (match_operand 2 "" "")))
5564 (use (match_operand 3 "" ""))
5565 (use (match_operand:SI 4 "fdpic_operand" "Z,Z"))
5566 (clobber (match_operand:SI 5 "lr_operand" "=l,l"))]
5571 [(set_attr "length" "4")
5572 (set_attr "type" "call,jumpl")])
5574 (define_expand "sibcall_value"
5575 [(use (match_operand 0 "" ""))
5576 (use (match_operand:QI 1 "" ""))
5577 (use (match_operand 2 "" ""))
5578 (use (match_operand 3 "" ""))
5579 (use (match_operand 4 "" ""))]
5585 gcc_assert (GET_CODE (operands[1]) == MEM);
5587 addr = XEXP (operands[1], 0);
5588 if (! sibcall_operand (addr, Pmode))
5589 addr = force_reg (Pmode, addr);
5592 operands[3] = const0_rtx;
5595 frv_expand_fdpic_call (operands, true, true);
5597 emit_call_insn (gen_sibcall_value_internal (operands[0], addr, operands[2],
5602 (define_insn "sibcall_value_internal"
5603 [(set (match_operand 0 "register_operand" "=d")
5604 (call (mem:QI (match_operand:SI 1 "sibcall_operand" "WNOP"))
5605 (match_operand 2 "" "")))
5606 (use (match_operand 3 "" ""))
5610 [(set_attr "length" "4")
5611 (set_attr "type" "jumpl")])
5613 (define_insn "sibcall_value_fdpicdi"
5614 [(set (match_operand 0 "register_operand" "=d")
5615 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5616 (match_operand 2 "" "")))
5620 [(set_attr "length" "4")
5621 (set_attr "type" "jumpl")])
5623 ;; return instruction generated instead of jmp to epilog
5624 (define_expand "return"
5625 [(parallel [(return)
5627 (use (const_int 1))])]
5628 "direct_return_p ()"
5631 operands[0] = gen_rtx_REG (Pmode, LR_REGNO);
5634 ;; return instruction generated by the epilogue
5635 (define_expand "epilogue_return"
5636 [(parallel [(return)
5637 (use (match_operand:SI 0 "register_operand" ""))
5638 (use (const_int 0))])]
5642 (define_insn "*return_internal"
5644 (use (match_operand:SI 0 "register_operand" "l,d"))
5645 (use (match_operand:SI 1 "immediate_operand" "n,n"))]
5650 [(set_attr "length" "4")
5651 (set_attr "type" "jump,jumpl")])
5653 (define_insn "*return_true"
5655 (if_then_else (match_operator 0 "integer_relational_operator"
5656 [(match_operand 1 "icc_operand" "t")
5660 "direct_return_p ()"
5662 [(set_attr "length" "4")
5663 (set_attr "type" "jump")])
5665 (define_insn "*return_false"
5667 (if_then_else (match_operator 0 "integer_relational_operator"
5668 [(match_operand 1 "icc_operand" "t")
5672 "direct_return_p ()"
5674 [(set_attr "length" "4")
5675 (set_attr "type" "jump")])
5677 ;; A version of addsi3 for deallocating stack space at the end of the
5678 ;; epilogue. The addition is done in parallel with an (unspec_volatile),
5679 ;; which represents the clobbering of the deallocated space.
5680 (define_insn "stack_adjust"
5681 [(set (match_operand:SI 0 "register_operand" "=d")
5682 (plus:SI (match_operand:SI 1 "register_operand" "d")
5683 (match_operand:SI 2 "general_operand" "dNOP")))
5684 (unspec_volatile [(const_int 0)] UNSPEC_STACK_ADJUST)]
5687 [(set_attr "length" "4")
5688 (set_attr "type" "int")])
5690 ;; Normal unconditional jump
5692 ;; Use the "call" instruction for long branches, but prefer to use "bra" for
5693 ;; short ones since it does not force us to save the link register.
5695 ;; This define_insn uses the branch-shortening code to decide which
5696 ;; instruction it emits. Since the main branch-shortening interface is
5697 ;; through get_attr_length(), the two alternatives must be given different
5698 ;; lengths. Here we pretend that the far jump is 8 rather than 4 bytes
5699 ;; long, though both alternatives are really the same size.
5701 [(set (pc) (label_ref (match_operand 0 "" "")))]
5705 if (get_attr_length (insn) == 4)
5708 return \"call %l0\";
5710 [(set (attr "length")
5712 (and (ge (minus (match_dup 0) (pc)) (const_int -32768))
5713 (le (minus (match_dup 0) (pc)) (const_int 32764)))
5716 (set (attr "far_jump")
5718 (eq_attr "length" "4")
5720 (const_string "yes")))
5723 (eq_attr "length" "4")
5724 (const_string "jump")
5725 (const_string "call")))])
5727 ;; Indirect jump through a register
5728 (define_insn "indirect_jump"
5729 [(set (pc) (match_operand:SI 0 "register_operand" "d,l"))]
5734 [(set_attr "length" "4")
5735 (set_attr "type" "jumpl,branch")])
5737 ;; Instruction to jump to a variable address. This is a low-level capability
5738 ;; which can be used to implement a dispatch table when there is no `casesi'
5739 ;; pattern. Either the 'casesi' pattern or the 'tablejump' pattern, or both,
5740 ;; MUST be present in this file.
5742 ;; This pattern requires two operands: the address or offset, and a label which
5743 ;; should immediately precede the jump table. If the macro
5744 ;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
5745 ;; which counts from the address of the table; otherwise, it is an absolute
5746 ;; address to jump to. In either case, the first operand has mode `Pmode'.
5748 ;; The `tablejump' insn is always the last insn before the jump table it uses.
5749 ;; Its assembler code normally has no need to use the second operand, but you
5750 ;; should incorporate it in the RTL pattern so that the jump optimizer will not
5751 ;; delete the table as unreachable code.
5753 (define_expand "tablejump"
5754 [(parallel [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5755 (use (label_ref (match_operand 1 "" "")))])]
5759 (define_insn "tablejump_insn"
5760 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5761 (use (label_ref (match_operand 1 "" "")))]
5764 [(set_attr "length" "4")
5765 (set_attr "type" "jumpl")])
5767 ;; Implement switch statements when generating PIC code. Switches are
5768 ;; implemented by `tablejump' when not using -fpic.
5770 ;; Emit code here to do the range checking and make the index zero based.
5771 ;; operand 0 is the index
5772 ;; operand 1 is the lower bound
5773 ;; operand 2 is the range of indices (highest - lowest + 1)
5774 ;; operand 3 is the label that precedes the table itself
5775 ;; operand 4 is the fall through label
5777 (define_expand "casesi"
5778 [(use (match_operand:SI 0 "integer_register_operand" ""))
5779 (use (match_operand:SI 1 "const_int_operand" ""))
5780 (use (match_operand:SI 2 "const_int_operand" ""))
5781 (use (match_operand 3 "" ""))
5782 (use (match_operand 4 "" ""))]
5788 rtx low = operands[1];
5789 rtx range = operands[2];
5790 rtx table = operands[3];
5792 rtx fail = operands[4];
5797 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5799 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5801 /* If we can't generate an immediate instruction, promote to register. */
5802 if (! IN_RANGE_P (INTVAL (range), -2048, 2047))
5803 range = force_reg (SImode, range);
5805 /* If low bound is 0, we don't have to subtract it. */
5806 if (INTVAL (operands[1]) == 0)
5810 indx = gen_reg_rtx (SImode);
5811 if (IN_RANGE_P (INTVAL (low), -2047, 2048))
5812 emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
5814 emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
5817 /* Do an unsigned comparison (in the proper mode) between the index
5818 expression and the value which represents the length of the range.
5819 Since we just finished subtracting the lower bound of the range
5820 from the index expression, this comparison allows us to simultaneously
5821 check that the original index expression value is both greater than
5822 or equal to the minimum value of the range and less than or equal to
5823 the maximum value of the range. */
5825 emit_cmp_and_jump_insns (indx, range, GTU, NULL_RTX, SImode, 1, fail);
5827 /* Move the table address to a register. */
5828 treg = gen_reg_rtx (Pmode);
5829 emit_insn (gen_movsi (treg, gen_rtx_LABEL_REF (VOIDmode, table)));
5831 /* Scale index-low by wordsize. */
5832 scale = gen_reg_rtx (SImode);
5833 emit_insn (gen_ashlsi3 (scale, indx, const2_rtx));
5835 /* Load the address, add the start of the table back in,
5837 mem = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, scale, treg));
5838 reg2 = gen_reg_rtx (SImode);
5839 reg3 = gen_reg_rtx (SImode);
5840 emit_insn (gen_movsi (reg2, mem));
5841 emit_insn (gen_addsi3 (reg3, reg2, treg));
5842 emit_jump_insn (gen_tablejump_insn (reg3, table));
5847 ;; ::::::::::::::::::::
5849 ;; :: Prologue and Epilogue instructions
5851 ;; ::::::::::::::::::::
5853 ;; Called after register allocation to add any instructions needed for the
5854 ;; prologue. Using a prologue insn is favored compared to putting all of the
5855 ;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
5856 ;; to intermix instructions with the saves of the caller saved registers. In
5857 ;; some cases, it might be necessary to emit a barrier instruction as the last
5858 ;; insn to prevent such scheduling.
5859 (define_expand "prologue"
5864 frv_expand_prologue ();
5868 ;; Called after register allocation to add any instructions needed for the
5869 ;; epilogue. Using an epilogue insn is favored compared to putting all of the
5870 ;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
5871 ;; to intermix instructions with the restores of the caller saved registers.
5872 ;; In some cases, it might be necessary to emit a barrier instruction as the
5873 ;; first insn to prevent such scheduling.
5874 (define_expand "epilogue"
5879 frv_expand_epilogue (true);
5883 ;; This pattern, if defined, emits RTL for exit from a function without the final
5884 ;; branch back to the calling function. This pattern will be emitted before any
5885 ;; sibling call (aka tail call) sites.
5887 ;; The sibcall_epilogue pattern must not clobber any arguments used for
5888 ;; parameter passing or any stack slots for arguments passed to the current
5890 (define_expand "sibcall_epilogue"
5895 frv_expand_epilogue (false);
5899 ;; Set up the pic register to hold the address of the pic table
5900 (define_insn "pic_prologue"
5901 [(set (match_operand:SI 0 "integer_register_operand" "=d")
5902 (unspec_volatile:SI [(const_int 0)] UNSPEC_PIC_PROLOGUE))
5903 (clobber (match_operand:SI 1 "lr_operand" "=l"))
5904 (clobber (match_operand:SI 2 "integer_register_operand" "=d"))]
5908 static int frv_pic_labelno = 0;
5910 operands[3] = GEN_INT (frv_pic_labelno++);
5911 return \"call %P3\\n%P3:\;movsg %1, %0\;sethi #gprelhi(%P3), %2\;setlo #gprello(%P3), %2\;sub %0,%2,%0\";
5913 [(set_attr "length" "16")
5914 (set_attr "type" "multi")])
5916 ;; ::::::::::::::::::::
5918 ;; :: Miscellaneous instructions
5920 ;; ::::::::::::::::::::
5922 ;; No operation, needed in case the user uses -g but not -O.
5927 [(set_attr "length" "4")
5928 (set_attr "type" "int")])
5934 [(set_attr "length" "4")
5935 (set_attr "type" "fnop")])
5941 [(set_attr "length" "4")
5942 (set_attr "type" "mnop")])
5944 ;; Pseudo instruction that prevents the scheduler from moving code above this
5945 ;; point. Note, type unknown is used to make sure the VLIW instructions are
5946 ;; not continued past this point.
5947 (define_insn "blockage"
5948 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5951 [(set_attr "length" "0")
5952 (set_attr "type" "unknown")])
5954 ;; ::::::::::::::::::::
5956 ;; :: Media instructions
5958 ;; ::::::::::::::::::::
5960 ;; Unimplemented instructions:
5964 [(UNSPEC_MLOGIC 100)
5971 (UNSPEC_MUNPACKH 107)
5972 (UNSPEC_MDPACKH 108)
5977 (UNSPEC_MEXPDHW 113)
5978 (UNSPEC_MEXPDHD 114)
5985 (UNSPEC_MQMULXH 121)
5991 (UNSPEC_MRDACCG 127)
5993 (UNSPEC_MWTACCG 129)
5995 (UNSPEC_MCLRACC 131)
5996 (UNSPEC_MCLRACCA 132)
5999 (UNSPEC_MDUNPACKH 135)
6000 (UNSPEC_MDUNPACKH_INTERNAL 136)
6002 (UNSPEC_MBTOHE_INTERNAL 138)
6004 (UNSPEC_MBTOHE_INTERNAL 138)
6005 (UNSPEC_MQMACH2 139)
6006 (UNSPEC_MADDACC 140)
6007 (UNSPEC_MDADDACC 141)
6009 (UNSPEC_MDROTLI 143)
6012 (UNSPEC_MDCUTSSI 146)
6013 (UNSPEC_MQSATHS 147)
6014 (UNSPEC_MHSETLOS 148)
6015 (UNSPEC_MHSETLOH 149)
6016 (UNSPEC_MHSETHIS 150)
6017 (UNSPEC_MHSETHIH 151)
6018 (UNSPEC_MHDSETS 152)
6019 (UNSPEC_MHDSETH 153)
6020 (UNSPEC_MQLCLRHS 154)
6021 (UNSPEC_MQLMTHS 155)
6022 (UNSPEC_MQSLLHI 156)
6023 (UNSPEC_MQSRAHI 157)
6024 (UNSPEC_MASACCS 158)
6025 (UNSPEC_MDASACCS 159)
6028 ;; Logic operations: type "mlogic"
6030 (define_expand "mand"
6031 [(set (match_operand:SI 0 "fpr_operand" "")
6032 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6033 (match_operand:SI 2 "fpr_operand" "")
6037 "operands[3] = GEN_INT (FRV_BUILTIN_MAND);")
6039 (define_expand "mor"
6040 [(set (match_operand:SI 0 "fpr_operand" "")
6041 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6042 (match_operand:SI 2 "fpr_operand" "")
6046 "operands[3] = GEN_INT (FRV_BUILTIN_MOR);")
6048 (define_expand "mxor"
6049 [(set (match_operand:SI 0 "fpr_operand" "")
6050 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6051 (match_operand:SI 2 "fpr_operand" "")
6055 "operands[3] = GEN_INT (FRV_BUILTIN_MXOR);")
6057 (define_insn "*mlogic"
6058 [(set (match_operand:SI 0 "fpr_operand" "=f")
6059 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6060 (match_operand:SI 2 "fpr_operand" "f")
6061 (match_operand:SI 3 "const_int_operand" "n")]
6066 switch (INTVAL (operands[3]))
6069 case FRV_BUILTIN_MAND: return \"mand %1, %2, %0\";
6070 case FRV_BUILTIN_MOR: return \"mor %1, %2, %0\";
6071 case FRV_BUILTIN_MXOR: return \"mxor %1, %2, %0\";
6074 fatal_insn (\"Bad media insn, mlogic\", insn);
6076 [(set_attr "length" "4")
6077 (set_attr "type" "mlogic")])
6079 (define_insn "*cond_exec_mlogic"
6081 (match_operator 0 "ccr_eqne_operator"
6082 [(match_operand 1 "cr_operand" "C")
6084 (set (match_operand:SI 2 "fpr_operand" "=f")
6085 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6086 (match_operand:SI 4 "fpr_operand" "f")
6087 (match_operand:SI 5 "const_int_operand" "n")]
6092 switch (INTVAL (operands[5]))
6095 case FRV_BUILTIN_MAND: return \"cmand %3, %4, %2, %1, %e0\";
6096 case FRV_BUILTIN_MOR: return \"cmor %3, %4, %2, %1, %e0\";
6097 case FRV_BUILTIN_MXOR: return \"cmxor %3, %4, %2, %1, %e0\";
6100 fatal_insn (\"Bad media insn, cond_exec_mlogic\", insn);
6102 [(set_attr "length" "4")
6103 (set_attr "type" "mlogic")])
6105 ;; Logical not: type "mlogic"
6108 [(set (match_operand:SI 0 "fpr_operand" "=f")
6109 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MNOT))]
6112 [(set_attr "length" "4")
6113 (set_attr "type" "mlogic")])
6115 (define_insn "*cond_exec_mnot"
6117 (match_operator 0 "ccr_eqne_operator"
6118 [(match_operand 1 "cr_operand" "C")
6120 (set (match_operand:SI 2 "fpr_operand" "=f")
6121 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")] UNSPEC_MNOT)))]
6123 "cmnot %3, %2, %1, %e0"
6124 [(set_attr "length" "4")
6125 (set_attr "type" "mlogic")])
6127 ;; Dual average (halfword): type "maveh"
6129 (define_insn "maveh"
6130 [(set (match_operand:SI 0 "fpr_operand" "=f")
6131 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6132 (match_operand:SI 2 "fpr_operand" "f")]
6136 [(set_attr "length" "4")
6137 (set_attr "type" "maveh")])
6139 ;; Dual saturation (halfword): type "msath"
6141 (define_expand "msaths"
6142 [(set (match_operand:SI 0 "fpr_operand" "=f")
6143 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6144 (match_operand:SI 2 "fpr_operand" "f")
6148 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHS);")
6150 (define_expand "msathu"
6151 [(set (match_operand:SI 0 "fpr_operand" "=f")
6152 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6153 (match_operand:SI 2 "fpr_operand" "f")
6157 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHU);")
6159 (define_insn "*msath"
6160 [(set (match_operand:SI 0 "fpr_operand" "=f")
6161 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6162 (match_operand:SI 2 "fpr_operand" "f")
6163 (match_operand:SI 3 "const_int_operand" "n")]
6168 switch (INTVAL (operands[3]))
6171 case FRV_BUILTIN_MSATHS: return \"msaths %1, %2, %0\";
6172 case FRV_BUILTIN_MSATHU: return \"msathu %1, %2, %0\";
6175 fatal_insn (\"Bad media insn, msath\", insn);
6177 [(set_attr "length" "4")
6178 (set_attr "type" "msath")])
6180 ;; Dual addition/subtraction with saturation (halfword): type "maddh"
6182 (define_expand "maddhss"
6183 [(set (match_operand:SI 0 "fpr_operand" "=f")
6184 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6185 (match_operand:SI 2 "fpr_operand" "f")
6189 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHSS);")
6191 (define_expand "maddhus"
6192 [(set (match_operand:SI 0 "fpr_operand" "=f")
6193 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6194 (match_operand:SI 2 "fpr_operand" "f")
6198 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHUS);")
6200 (define_expand "msubhss"
6201 [(set (match_operand:SI 0 "fpr_operand" "=f")
6202 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6203 (match_operand:SI 2 "fpr_operand" "f")
6207 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHSS);")
6209 (define_expand "msubhus"
6210 [(set (match_operand:SI 0 "fpr_operand" "=f")
6211 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6212 (match_operand:SI 2 "fpr_operand" "f")
6216 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHUS);")
6218 (define_insn "*maddh"
6219 [(set (match_operand:SI 0 "fpr_operand" "=f")
6220 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6221 (match_operand:SI 2 "fpr_operand" "f")
6222 (match_operand:SI 3 "const_int_operand" "n")]
6227 switch (INTVAL (operands[3]))
6230 case FRV_BUILTIN_MADDHSS: return \"maddhss %1, %2, %0\";
6231 case FRV_BUILTIN_MADDHUS: return \"maddhus %1, %2, %0\";
6232 case FRV_BUILTIN_MSUBHSS: return \"msubhss %1, %2, %0\";
6233 case FRV_BUILTIN_MSUBHUS: return \"msubhus %1, %2, %0\";
6236 fatal_insn (\"Bad media insn, maddh\", insn);
6238 [(set_attr "length" "4")
6239 (set_attr "type" "maddh")])
6241 (define_insn "*cond_exec_maddh"
6243 (match_operator 0 "ccr_eqne_operator"
6244 [(match_operand 1 "cr_operand" "C")
6246 (set (match_operand:SI 2 "fpr_operand" "=f")
6247 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6248 (match_operand:SI 4 "fpr_operand" "f")
6249 (match_operand:SI 5 "const_int_operand" "n")]
6254 switch (INTVAL (operands[5]))
6257 case FRV_BUILTIN_MADDHSS: return \"cmaddhss %3, %4, %2, %1, %e0\";
6258 case FRV_BUILTIN_MADDHUS: return \"cmaddhus %3, %4, %2, %1, %e0\";
6259 case FRV_BUILTIN_MSUBHSS: return \"cmsubhss %3, %4, %2, %1, %e0\";
6260 case FRV_BUILTIN_MSUBHUS: return \"cmsubhus %3, %4, %2, %1, %e0\";
6263 fatal_insn (\"Bad media insn, cond_exec_maddh\", insn);
6265 [(set_attr "length" "4")
6266 (set_attr "type" "maddh")])
6268 ;; Quad addition/subtraction with saturation (halfword): type "mqaddh"
6270 (define_expand "mqaddhss"
6271 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6272 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6273 (match_operand:DI 2 "even_fpr_operand" "h")
6277 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHSS);")
6279 (define_expand "mqaddhus"
6280 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6281 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6282 (match_operand:DI 2 "even_fpr_operand" "h")
6286 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHUS);")
6288 (define_expand "mqsubhss"
6289 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6290 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6291 (match_operand:DI 2 "even_fpr_operand" "h")
6295 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHSS);")
6297 (define_expand "mqsubhus"
6298 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6299 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6300 (match_operand:DI 2 "even_fpr_operand" "h")
6304 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHUS);")
6306 (define_insn "*mqaddh"
6307 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6308 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6309 (match_operand:DI 2 "even_fpr_operand" "h")
6310 (match_operand:SI 3 "const_int_operand" "n")]
6315 switch (INTVAL (operands[3]))
6318 case FRV_BUILTIN_MQADDHSS: return \"mqaddhss %1, %2, %0\";
6319 case FRV_BUILTIN_MQADDHUS: return \"mqaddhus %1, %2, %0\";
6320 case FRV_BUILTIN_MQSUBHSS: return \"mqsubhss %1, %2, %0\";
6321 case FRV_BUILTIN_MQSUBHUS: return \"mqsubhus %1, %2, %0\";
6324 fatal_insn (\"Bad media insn, mqaddh\", insn);
6326 [(set_attr "length" "4")
6327 (set_attr "type" "mqaddh")])
6329 (define_insn "*cond_exec_mqaddh"
6331 (match_operator 0 "ccr_eqne_operator"
6332 [(match_operand 1 "cr_operand" "C")
6334 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6335 (unspec:DI [(match_operand:DI 3 "even_fpr_operand" "h")
6336 (match_operand:DI 4 "even_fpr_operand" "h")
6337 (match_operand:SI 5 "const_int_operand" "n")]
6342 switch (INTVAL (operands[5]))
6345 case FRV_BUILTIN_MQADDHSS: return \"cmqaddhss %3, %4, %2, %1, %e0\";
6346 case FRV_BUILTIN_MQADDHUS: return \"cmqaddhus %3, %4, %2, %1, %e0\";
6347 case FRV_BUILTIN_MQSUBHSS: return \"cmqsubhss %3, %4, %2, %1, %e0\";
6348 case FRV_BUILTIN_MQSUBHUS: return \"cmqsubhus %3, %4, %2, %1, %e0\";
6351 fatal_insn (\"Bad media insn, cond_exec_mqaddh\", insn);
6353 [(set_attr "length" "4")
6354 (set_attr "type" "mqaddh")])
6356 ;; Pack halfword: type "mpackh"
6358 (define_insn "mpackh"
6359 [(set (match_operand:SI 0 "fpr_operand" "=f")
6360 (unspec:SI [(match_operand:HI 1 "fpr_operand" "f")
6361 (match_operand:HI 2 "fpr_operand" "f")]
6365 [(set_attr "length" "4")
6366 (set_attr "type" "mpackh")])
6368 ;; Unpack halfword: type "mpackh"
6370 (define_insn "munpackh"
6371 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6372 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6376 [(set_attr "length" "4")
6377 (set_attr "type" "munpackh")])
6379 ;; Dual pack halfword: type "mdpackh"
6381 (define_insn "mdpackh"
6382 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6383 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6384 (match_operand:DI 2 "even_fpr_operand" "h")]
6387 "mdpackh %1, %2, %0"
6388 [(set_attr "length" "4")
6389 (set_attr "type" "mdpackh")])
6391 ;; Byte-halfword conversion: type "mbhconv"
6393 (define_insn "mbtoh"
6394 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6395 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6399 [(set_attr "length" "4")
6400 (set_attr "type" "mbhconv")])
6402 (define_insn "*cond_exec_mbtoh"
6404 (match_operator 0 "ccr_eqne_operator"
6405 [(match_operand 1 "cr_operand" "C")
6407 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6408 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")]
6411 "cmbtoh %3, %2, %1, %e0"
6412 [(set_attr "length" "4")
6413 (set_attr "type" "mbhconv")])
6415 (define_insn "mhtob"
6416 [(set (match_operand:SI 0 "fpr_operand" "=f")
6417 (unspec:SI [(match_operand:DI 1 "even_fpr_operand" "h")]
6421 [(set_attr "length" "4")
6422 (set_attr "type" "mbhconv")])
6424 (define_insn "*cond_exec_mhtob"
6426 (match_operator 0 "ccr_eqne_operator"
6427 [(match_operand 1 "cr_operand" "C")
6429 (set (match_operand:SI 2 "fpr_operand" "=f")
6430 (unspec:SI [(match_operand:DI 3 "even_fpr_operand" "h")]
6433 "cmhtob %3, %2, %1, %e0"
6434 [(set_attr "length" "4")
6435 (set_attr "type" "mbhconv")])
6437 ;; Rotate: type "mrot"
6439 (define_expand "mrotli"
6440 [(set (match_operand:SI 0 "fpr_operand" "")
6441 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6442 (match_operand:SI 2 "uint5_operand" "")
6446 "operands[3] = GEN_INT (FRV_BUILTIN_MROTLI);")
6448 (define_expand "mrotri"
6449 [(set (match_operand:SI 0 "fpr_operand" "")
6450 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6451 (match_operand:SI 2 "uint5_operand" "")
6455 "operands[3] = GEN_INT (FRV_BUILTIN_MROTRI);")
6457 (define_insn "*mrot"
6458 [(set (match_operand:SI 0 "fpr_operand" "=f")
6459 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6460 (match_operand:SI 2 "uint5_operand" "I")
6461 (match_operand:SI 3 "const_int_operand" "n")]
6466 switch (INTVAL (operands[3]))
6469 case FRV_BUILTIN_MROTLI: return \"mrotli %1, %2, %0\";
6470 case FRV_BUILTIN_MROTRI: return \"mrotri %1, %2, %0\";
6473 fatal_insn (\"Bad media insn, mrot\", insn);
6475 [(set_attr "length" "4")
6476 (set_attr "type" "mrot")])
6478 ;; Dual shift halfword: type "msh"
6480 (define_expand "msllhi"
6481 [(set (match_operand:SI 0 "fpr_operand" "")
6482 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6483 (match_operand:SI 2 "uint4_operand" "")
6487 "operands[3] = GEN_INT (FRV_BUILTIN_MSLLHI);")
6489 (define_expand "msrlhi"
6490 [(set (match_operand:SI 0 "fpr_operand" "")
6491 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6492 (match_operand:SI 2 "uint4_operand" "")
6496 "operands[3] = GEN_INT (FRV_BUILTIN_MSRLHI);")
6498 (define_expand "msrahi"
6499 [(set (match_operand:SI 0 "fpr_operand" "")
6500 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6501 (match_operand:SI 2 "uint4_operand" "")
6505 "operands[3] = GEN_INT (FRV_BUILTIN_MSRAHI);")
6507 (define_insn "*mshift"
6508 [(set (match_operand:SI 0 "fpr_operand" "=f")
6509 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6510 (match_operand:SI 2 "uint4_operand" "I")
6511 (match_operand:SI 3 "const_int_operand" "n")]
6516 switch (INTVAL (operands[3]))
6519 case FRV_BUILTIN_MSLLHI: return \"msllhi %1, %2, %0\";
6520 case FRV_BUILTIN_MSRLHI: return \"msrlhi %1, %2, %0\";
6521 case FRV_BUILTIN_MSRAHI: return \"msrahi %1, %2, %0\";
6524 fatal_insn (\"Bad media insn, mshift\", insn);
6526 [(set_attr "length" "4")
6527 (set_attr "type" "mshift")])
6529 ;; Expand halfword to word: type "mexpdhw"
6531 (define_insn "mexpdhw"
6532 [(set (match_operand:SI 0 "fpr_operand" "=f")
6533 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6534 (match_operand:SI 2 "uint1_operand" "I")]
6537 "mexpdhw %1, %2, %0"
6538 [(set_attr "length" "4")
6539 (set_attr "type" "mexpdhw")])
6541 (define_insn "*cond_exec_mexpdhw"
6543 (match_operator 0 "ccr_eqne_operator"
6544 [(match_operand 1 "cr_operand" "C")
6546 (set (match_operand:SI 2 "fpr_operand" "=f")
6547 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6548 (match_operand:SI 4 "uint1_operand" "I")]
6551 "cmexpdhw %3, %4, %2, %1, %e0"
6552 [(set_attr "length" "4")
6553 (set_attr "type" "mexpdhw")])
6555 ;; Expand halfword to double: type "mexpdhd"
6557 (define_insn "mexpdhd"
6558 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6559 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6560 (match_operand:SI 2 "uint1_operand" "I")]
6563 "mexpdhd %1, %2, %0"
6564 [(set_attr "length" "4")
6565 (set_attr "type" "mexpdhd")])
6567 (define_insn "*cond_exec_mexpdhd"
6569 (match_operator 0 "ccr_eqne_operator"
6570 [(match_operand 1 "cr_operand" "C")
6572 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6573 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6574 (match_operand:SI 4 "uint1_operand" "I")]
6577 "cmexpdhd %3, %4, %2, %1, %e0"
6578 [(set_attr "length" "4")
6579 (set_attr "type" "mexpdhd")])
6581 ;; FR cut: type "mwcut"
6583 (define_insn "mwcut"
6584 [(set (match_operand:SI 0 "fpr_operand" "=f")
6585 (unspec:SI [(match_operand:DI 1 "fpr_operand" "f")
6586 (match_operand:SI 2 "fpr_or_int6_operand" "fI")]
6589 "mwcut%i2 %1, %2, %0"
6590 [(set_attr "length" "4")
6591 (set_attr "type" "mwcut")])
6593 ;; Dual multiplication (halfword): type "mmulh"
6595 (define_expand "mmulhs"
6596 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6597 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6598 (match_operand:SI 2 "fpr_operand" "f")
6601 (set (match_operand:HI 3 "accg_operand" "=B")
6602 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6604 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHS);")
6606 (define_expand "mmulhu"
6607 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6608 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6609 (match_operand:SI 2 "fpr_operand" "f")
6612 (set (match_operand:HI 3 "accg_operand" "=B")
6613 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6615 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHU);")
6617 (define_insn "*mmulh"
6618 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6619 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6620 (match_operand:SI 2 "fpr_operand" "f")
6621 (match_operand:SI 3 "const_int_operand" "n")]
6623 (set (match_operand:HI 4 "accg_operand" "=B")
6624 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]
6628 switch (INTVAL (operands[3]))
6631 case FRV_BUILTIN_MMULHS: return \"mmulhs %1, %2, %0\";
6632 case FRV_BUILTIN_MMULHU: return \"mmulhu %1, %2, %0\";
6635 fatal_insn (\"Bad media insn, mmulh\", insn);
6637 [(set_attr "length" "4")
6638 (set_attr "type" "mmulh")])
6640 (define_insn "*cond_exec_mmulh"
6642 (match_operator 0 "ccr_eqne_operator"
6643 [(match_operand 1 "cr_operand" "C")
6645 (parallel [(set (match_operand:DI 2 "even_acc_operand" "=b")
6646 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6647 (match_operand:SI 4 "fpr_operand" "f")
6648 (match_operand:SI 5 "const_int_operand" "n")]
6650 (set (match_operand:HI 6 "accg_operand" "=B")
6651 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]))]
6655 switch (INTVAL (operands[5]))
6658 case FRV_BUILTIN_MMULHS: return \"cmmulhs %3, %4, %2, %1, %e0\";
6659 case FRV_BUILTIN_MMULHU: return \"cmmulhu %3, %4, %2, %1, %e0\";
6662 fatal_insn (\"Bad media insn, cond_exec_mmulh\", insn);
6664 [(set_attr "length" "4")
6665 (set_attr "type" "mmulh")])
6667 ;; Dual cross multiplication (halfword): type "mmulxh"
6669 (define_expand "mmulxhs"
6670 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6671 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6672 (match_operand:SI 2 "fpr_operand" "f")
6675 (set (match_operand:HI 3 "accg_operand" "=B")
6676 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6678 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHS);")
6680 (define_expand "mmulxhu"
6681 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6682 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6683 (match_operand:SI 2 "fpr_operand" "f")
6686 (set (match_operand:HI 3 "accg_operand" "=B")
6687 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6689 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHU);")
6691 (define_insn "*mmulxh"
6692 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6693 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6694 (match_operand:SI 2 "fpr_operand" "f")
6695 (match_operand:SI 3 "const_int_operand" "n")]
6697 (set (match_operand:HI 4 "accg_operand" "=B")
6698 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))]
6702 switch (INTVAL (operands[3]))
6705 case FRV_BUILTIN_MMULXHS: return \"mmulxhs %1, %2, %0\";
6706 case FRV_BUILTIN_MMULXHU: return \"mmulxhu %1, %2, %0\";
6709 fatal_insn (\"Bad media insn, mmulxh\", insn);
6711 [(set_attr "length" "4")
6712 (set_attr "type" "mmulxh")])
6714 ;; Dual product-sum (halfword): type "mmach"
6716 (define_expand "mmachs"
6717 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6718 (unspec:DI [(match_dup 0)
6719 (match_operand:SI 1 "fpr_operand" "f")
6720 (match_operand:SI 2 "fpr_operand" "f")
6721 (match_operand:HI 3 "accg_operand" "+B")
6725 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6727 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHS);")
6729 (define_expand "mmachu"
6730 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6731 (unspec:DI [(match_dup 0)
6732 (match_operand:SI 1 "fpr_operand" "f")
6733 (match_operand:SI 2 "fpr_operand" "f")
6734 (match_operand:HI 3 "accg_operand" "+B")
6738 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6740 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHU);")
6742 (define_insn "*mmach"
6743 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6744 (unspec:DI [(match_dup 0)
6745 (match_operand:SI 1 "fpr_operand" "f")
6746 (match_operand:SI 2 "fpr_operand" "f")
6747 (match_operand:HI 3 "accg_operand" "+B")
6748 (match_operand:SI 4 "const_int_operand" "n")]
6750 (set (match_dup 3) (unspec:HI [(const_int 0)] UNSPEC_MMACH))]
6754 switch (INTVAL (operands[4]))
6757 case FRV_BUILTIN_MMACHS: return \"mmachs %1, %2, %0\";
6758 case FRV_BUILTIN_MMACHU: return \"mmachu %1, %2, %0\";
6761 fatal_insn (\"Bad media insn, mmach\", insn);
6763 [(set_attr "length" "4")
6764 (set_attr "type" "mmach")])
6766 (define_insn "*cond_exec_mmach"
6768 (match_operator 0 "ccr_eqne_operator"
6769 [(match_operand 1 "cr_operand" "C")
6771 (parallel [(set (match_operand:DI 2 "even_acc_operand" "+b")
6772 (unspec:DI [(match_dup 2)
6773 (match_operand:SI 3 "fpr_operand" "f")
6774 (match_operand:SI 4 "fpr_operand" "f")
6775 (match_operand:HI 5 "accg_operand" "+B")
6776 (match_operand:SI 6 "const_int_operand" "n")]
6779 (unspec:HI [(const_int 0)] UNSPEC_MMACH))]))]
6783 switch (INTVAL (operands[6]))
6786 case FRV_BUILTIN_MMACHS: return \"cmmachs %3, %4, %2, %1, %e0\";
6787 case FRV_BUILTIN_MMACHU: return \"cmmachu %3, %4, %2, %1, %e0\";
6790 fatal_insn (\"Bad media insn, cond_exec_mmach\", insn);
6792 [(set_attr "length" "4")
6793 (set_attr "type" "mmach")])
6795 ;; Dual product-difference: type "mmrdh"
6797 (define_expand "mmrdhs"
6798 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6799 (unspec:DI [(match_dup 0)
6800 (match_operand:SI 1 "fpr_operand" "f")
6801 (match_operand:SI 2 "fpr_operand" "f")
6802 (match_operand:HI 3 "accg_operand" "+B")
6806 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6808 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHS);")
6810 (define_expand "mmrdhu"
6811 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6812 (unspec:DI [(match_dup 0)
6813 (match_operand:SI 1 "fpr_operand" "f")
6814 (match_operand:SI 2 "fpr_operand" "f")
6815 (match_operand:HI 3 "accg_operand" "+B")
6819 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6821 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHU);")
6823 (define_insn "*mmrdh"
6824 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6825 (unspec:DI [(match_dup 0)
6826 (match_operand:SI 1 "fpr_operand" "f")
6827 (match_operand:SI 2 "fpr_operand" "f")
6828 (match_operand:HI 3 "accg_operand" "+B")
6829 (match_operand:SI 4 "const_int_operand" "n")]
6832 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))]
6836 switch (INTVAL (operands[4]))
6839 case FRV_BUILTIN_MMRDHS: return \"mmrdhs %1, %2, %0\";
6840 case FRV_BUILTIN_MMRDHU: return \"mmrdhu %1, %2, %0\";
6843 fatal_insn (\"Bad media insn, mrdh\", insn);
6845 [(set_attr "length" "4")
6846 (set_attr "type" "mmrdh")])
6848 ;; Quad multiply (halfword): type "mqmulh"
6850 (define_expand "mqmulhs"
6851 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6852 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6853 (match_operand:DI 2 "even_fpr_operand" "h")
6856 (set (match_operand:V4QI 3 "accg_operand" "=B")
6857 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6859 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHS);")
6861 (define_expand "mqmulhu"
6862 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6863 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6864 (match_operand:DI 2 "even_fpr_operand" "h")
6867 (set (match_operand:V4QI 3 "accg_operand" "=B")
6868 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6870 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHU);")
6872 (define_insn "*mqmulh"
6873 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6874 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6875 (match_operand:DI 2 "even_fpr_operand" "h")
6876 (match_operand:SI 3 "const_int_operand" "n")]
6878 (set (match_operand:V4QI 4 "accg_operand" "=B")
6879 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]
6883 switch (INTVAL (operands[3]))
6886 case FRV_BUILTIN_MQMULHS: return \"mqmulhs %1, %2, %0\";
6887 case FRV_BUILTIN_MQMULHU: return \"mqmulhu %1, %2, %0\";
6890 fatal_insn (\"Bad media insn, mqmulh\", insn);
6892 [(set_attr "length" "4")
6893 (set_attr "type" "mqmulh")])
6895 (define_insn "*cond_exec_mqmulh"
6897 (match_operator 0 "ccr_eqne_operator"
6898 [(match_operand 1 "cr_operand" "C")
6900 (parallel [(set (match_operand:V4SI 2 "quad_acc_operand" "=A")
6901 (unspec:V4SI [(match_operand:DI 3 "even_fpr_operand" "h")
6902 (match_operand:DI 4 "even_fpr_operand" "h")
6903 (match_operand:SI 5 "const_int_operand" "n")]
6905 (set (match_operand:V4QI 6 "accg_operand" "=B")
6906 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]))]
6910 switch (INTVAL (operands[5]))
6913 case FRV_BUILTIN_MQMULHS: return \"cmqmulhs %3, %4, %2, %1, %e0\";
6914 case FRV_BUILTIN_MQMULHU: return \"cmqmulhu %3, %4, %2, %1, %e0\";
6917 fatal_insn (\"Bad media insn, cond_exec_mqmulh\", insn);
6919 [(set_attr "length" "4")
6920 (set_attr "type" "mqmulh")])
6922 ;; Quad cross multiply (halfword): type "mqmulxh"
6924 (define_expand "mqmulxhs"
6925 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6926 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6927 (match_operand:DI 2 "even_fpr_operand" "h")
6930 (set (match_operand:V4QI 3 "accg_operand" "=B")
6931 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6933 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHS);")
6935 (define_expand "mqmulxhu"
6936 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6937 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6938 (match_operand:DI 2 "even_fpr_operand" "h")
6941 (set (match_operand:V4QI 3 "accg_operand" "=B")
6942 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6944 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHU);")
6946 (define_insn "*mqmulxh"
6947 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6948 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6949 (match_operand:DI 2 "even_fpr_operand" "h")
6950 (match_operand:SI 3 "const_int_operand" "n")]
6952 (set (match_operand:V4QI 4 "accg_operand" "=B")
6953 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))]
6957 switch (INTVAL (operands[3]))
6960 case FRV_BUILTIN_MQMULXHS: return \"mqmulxhs %1, %2, %0\";
6961 case FRV_BUILTIN_MQMULXHU: return \"mqmulxhu %1, %2, %0\";
6964 fatal_insn (\"Bad media insn, mqmulxh\", insn);
6966 [(set_attr "length" "4")
6967 (set_attr "type" "mqmulxh")])
6969 ;; Quad product-sum (halfword): type "mqmach"
6971 (define_expand "mqmachs"
6972 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6973 (unspec:V4SI [(match_dup 0)
6974 (match_operand:DI 1 "even_fpr_operand" "h")
6975 (match_operand:DI 2 "even_fpr_operand" "h")
6976 (match_operand:V4QI 3 "accg_operand" "+B")
6980 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6982 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHS);")
6984 (define_expand "mqmachu"
6985 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6986 (unspec:V4SI [(match_dup 0)
6987 (match_operand:DI 1 "even_fpr_operand" "h")
6988 (match_operand:DI 2 "even_fpr_operand" "h")
6989 (match_operand:V4QI 3 "accg_operand" "+B")
6993 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6995 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHU);")
6997 (define_insn "*mqmach"
6998 [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6999 (unspec:V4SI [(match_dup 0)
7000 (match_operand:DI 1 "even_fpr_operand" "h")
7001 (match_operand:DI 2 "even_fpr_operand" "h")
7002 (match_operand:V4QI 3 "accg_operand" "+B")
7003 (match_operand:SI 4 "const_int_operand" "n")]
7006 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]
7010 switch (INTVAL (operands[4]))
7013 case FRV_BUILTIN_MQMACHS: return \"mqmachs %1, %2, %0\";
7014 case FRV_BUILTIN_MQMACHU: return \"mqmachu %1, %2, %0\";
7017 fatal_insn (\"Bad media insn, mqmach\", insn);
7019 [(set_attr "length" "4")
7020 (set_attr "type" "mqmach")])
7022 (define_insn "*cond_exec_mqmach"
7024 (match_operator 0 "ccr_eqne_operator"
7025 [(match_operand 1 "cr_operand" "C")
7027 (parallel [(set (match_operand:V4SI 2 "even_acc_operand" "+A")
7028 (unspec:V4SI [(match_dup 2)
7029 (match_operand:DI 3 "even_fpr_operand" "h")
7030 (match_operand:DI 4 "even_fpr_operand" "h")
7031 (match_operand:V4QI 5 "accg_operand" "+B")
7032 (match_operand:SI 6 "const_int_operand" "n")]
7035 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]))]
7039 switch (INTVAL (operands[6]))
7042 case FRV_BUILTIN_MQMACHS: return \"cmqmachs %3, %4, %2, %1, %e0\";
7043 case FRV_BUILTIN_MQMACHU: return \"cmqmachu %3, %4, %2, %1, %e0\";
7046 fatal_insn (\"Bad media insn, cond_exec_mqmach\", insn);
7048 [(set_attr "length" "4")
7049 (set_attr "type" "mqmach")])
7051 ;; Dual complex number product-sum (halfword)
7053 (define_expand "mcpxrs"
7054 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7055 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7056 (match_operand:SI 2 "fpr_operand" "f")
7059 (set (match_operand:QI 3 "accg_operand" "=B")
7060 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7062 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRS);")
7064 (define_expand "mcpxru"
7065 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7066 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7067 (match_operand:SI 2 "fpr_operand" "f")
7070 (set (match_operand:QI 3 "accg_operand" "=B")
7071 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7073 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRU);")
7075 (define_expand "mcpxis"
7076 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7077 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7078 (match_operand:SI 2 "fpr_operand" "f")
7081 (set (match_operand:QI 3 "accg_operand" "=B")
7082 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7084 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIS);")
7086 (define_expand "mcpxiu"
7087 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7088 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7089 (match_operand:SI 2 "fpr_operand" "f")
7092 (set (match_operand:QI 3 "accg_operand" "=B")
7093 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7095 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIU);")
7097 (define_insn "*mcpx"
7098 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7099 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7100 (match_operand:SI 2 "fpr_operand" "f")
7101 (match_operand:SI 3 "const_int_operand" "n")]
7103 (set (match_operand:QI 4 "accg_operand" "=B")
7104 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7108 switch (INTVAL (operands[3]))
7111 case FRV_BUILTIN_MCPXRS: return \"mcpxrs %1, %2, %0\";
7112 case FRV_BUILTIN_MCPXRU: return \"mcpxru %1, %2, %0\";
7113 case FRV_BUILTIN_MCPXIS: return \"mcpxis %1, %2, %0\";
7114 case FRV_BUILTIN_MCPXIU: return \"mcpxiu %1, %2, %0\";
7117 fatal_insn (\"Bad media insn, mcpx\", insn);
7119 [(set_attr "length" "4")
7120 (set_attr "type" "mcpx")])
7122 (define_insn "*cond_exec_mcpx"
7124 (match_operator 0 "ccr_eqne_operator"
7125 [(match_operand 1 "cr_operand" "C")
7127 (parallel [(set (match_operand:SI 2 "acc_operand" "=a")
7128 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
7129 (match_operand:SI 4 "fpr_operand" "f")
7130 (match_operand:SI 5 "const_int_operand" "n")]
7132 (set (match_operand:QI 6 "accg_operand" "=B")
7133 (unspec:QI [(const_int 0)] UNSPEC_MCPX))]))]
7137 switch (INTVAL (operands[5]))
7140 case FRV_BUILTIN_MCPXRS: return \"cmcpxrs %3, %4, %2, %1, %e0\";
7141 case FRV_BUILTIN_MCPXRU: return \"cmcpxru %3, %4, %2, %1, %e0\";
7142 case FRV_BUILTIN_MCPXIS: return \"cmcpxis %3, %4, %2, %1, %e0\";
7143 case FRV_BUILTIN_MCPXIU: return \"cmcpxiu %3, %4, %2, %1, %e0\";
7146 fatal_insn (\"Bad media insn, cond_exec_mcpx\", insn);
7148 [(set_attr "length" "4")
7149 (set_attr "type" "mcpx")])
7151 ;; Quad complex number product-sum (halfword): type "mqcpx"
7153 (define_expand "mqcpxrs"
7154 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7155 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7156 (match_operand:DI 2 "fpr_operand" "f")
7159 (set (match_operand:HI 3 "accg_operand" "=B")
7160 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7162 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRS);")
7164 (define_expand "mqcpxru"
7165 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7166 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7167 (match_operand:DI 2 "fpr_operand" "f")
7170 (set (match_operand:HI 3 "accg_operand" "=B")
7171 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7173 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRU);")
7175 (define_expand "mqcpxis"
7176 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7177 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7178 (match_operand:DI 2 "fpr_operand" "f")
7181 (set (match_operand:HI 3 "accg_operand" "=B")
7182 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7184 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIS);")
7186 (define_expand "mqcpxiu"
7187 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7188 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7189 (match_operand:DI 2 "fpr_operand" "f")
7192 (set (match_operand:HI 3 "accg_operand" "=B")
7193 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7195 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIU);")
7197 (define_insn "*mqcpx"
7198 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7199 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7200 (match_operand:DI 2 "fpr_operand" "f")
7201 (match_operand:SI 3 "const_int_operand" "n")]
7203 (set (match_operand:HI 4 "accg_operand" "=B")
7204 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))]
7208 switch (INTVAL (operands[3]))
7211 case FRV_BUILTIN_MQCPXRS: return \"mqcpxrs %1, %2, %0\";
7212 case FRV_BUILTIN_MQCPXRU: return \"mqcpxru %1, %2, %0\";
7213 case FRV_BUILTIN_MQCPXIS: return \"mqcpxis %1, %2, %0\";
7214 case FRV_BUILTIN_MQCPXIU: return \"mqcpxiu %1, %2, %0\";
7217 fatal_insn (\"Bad media insn, mqcpx\", insn);
7219 [(set_attr "length" "4")
7220 (set_attr "type" "mqcpx")])
7224 (define_expand "mcut"
7225 [(set (match_operand:SI 0 "fpr_operand" "=f")
7226 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7227 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7228 (match_operand:QI 3 "accg_operand" "B")
7232 "operands[4] = GEN_INT (FRV_BUILTIN_MCUT);")
7234 (define_expand "mcutss"
7235 [(set (match_operand:SI 0 "fpr_operand" "=f")
7236 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7237 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7238 (match_operand:QI 3 "accg_operand" "B")
7242 "operands[4] = GEN_INT (FRV_BUILTIN_MCUTSS);")
7244 (define_insn "*mcut"
7245 [(set (match_operand:SI 0 "fpr_operand" "=f")
7246 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7247 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7248 (match_operand:QI 3 "accg_operand" "B")
7249 (match_operand:SI 4 "const_int_operand" "n")]
7254 switch (INTVAL (operands[4]))
7257 case FRV_BUILTIN_MCUT: return \"mcut%i2 %1, %2, %0\";
7258 case FRV_BUILTIN_MCUTSS: return \"mcutss%i2 %1, %2, %0\";
7261 fatal_insn (\"Bad media insn, mcut\", insn);
7263 [(set_attr "length" "4")
7264 (set_attr "type" "mcut")])
7266 ;; Accumulator read: type "mrdacc"
7268 (define_insn "mrdacc"
7269 [(set (match_operand:SI 0 "fpr_operand" "=f")
7270 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")] UNSPEC_MRDACC))]
7273 [(set_attr "length" "4")
7274 (set_attr "type" "mrdacc")])
7276 (define_insn "mrdaccg"
7277 [(set (match_operand:SI 0 "fpr_operand" "=f")
7278 (unspec:SI [(match_operand:QI 1 "accg_operand" "B")] UNSPEC_MRDACCG))]
7281 [(set_attr "length" "4")
7282 (set_attr "type" "mrdacc")])
7284 ;; Accumulator write: type "mwtacc"
7286 (define_insn "mwtacc"
7287 [(set (match_operand:SI 0 "acc_operand" "=a")
7288 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACC))]
7291 [(set_attr "length" "4")
7292 (set_attr "type" "mwtacc")])
7294 (define_insn "mwtaccg"
7295 [(set (match_operand:QI 0 "accg_operand" "=B")
7296 (unspec:QI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACCG))]
7299 [(set_attr "length" "4")
7300 (set_attr "type" "mwtacc")])
7302 ;; Trap: This one executes on the control unit, not the media units.
7304 (define_insn "mtrap"
7305 [(unspec_volatile [(const_int 0)] UNSPEC_MTRAP)]
7308 [(set_attr "length" "4")
7309 (set_attr "type" "trap")])
7311 ;; Clear single accumulator: type "mclracc"
7313 (define_insn "mclracc_internal"
7314 [(set (match_operand:SI 0 "acc_operand" "=a")
7315 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7316 (set (match_operand:QI 1 "accg_operand" "=B")
7317 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))]
7320 [(set_attr "length" "4")
7321 (set_attr "type" "mclracc")])
7323 (define_expand "mclracc"
7324 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7325 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7327 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))])]
7331 if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
7334 operands[1] = frv_matching_accg_for_acc (operands[0]);
7337 ;; Clear all accumulators: type "mclracca"
7339 (define_insn "mclracca8_internal"
7340 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7341 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7342 (set (match_operand:V4SI 1 "quad_acc_operand" "=b")
7343 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7344 (set (match_operand:V4QI 2 "accg_operand" "=B")
7345 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7346 (set (match_operand:V4QI 3 "accg_operand" "=B")
7347 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7348 "TARGET_MEDIA && TARGET_ACC_8"
7350 [(set_attr "length" "4")
7351 (set_attr "type" "mclracca")])
7353 (define_insn "mclracca4_internal"
7354 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7355 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7356 (set (match_operand:V4QI 1 "accg_operand" "=B")
7357 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7358 "TARGET_MEDIA && TARGET_ACC_4"
7360 [(set_attr "length" "4")
7361 (set_attr "type" "mclracca")])
7363 (define_expand "mclracca8"
7364 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7365 (set (match_dup 1) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7366 (set (match_dup 2) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7367 (set (match_dup 3) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7368 "TARGET_MEDIA && TARGET_ACC_8"
7371 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7372 operands[1] = gen_rtx_REG (V4SImode, ACC_FIRST + (~3 & ACC_MASK));
7373 operands[2] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7374 operands[3] = gen_rtx_REG (V4QImode, ACCG_FIRST + (~3 & ACC_MASK));
7377 (define_expand "mclracca4"
7378 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7379 (set (match_dup 1) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7380 "TARGET_MEDIA && TARGET_ACC_4"
7383 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7384 operands[1] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7387 (define_insn "mcop1"
7388 [(set (match_operand:SI 0 "fpr_operand" "=f")
7389 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7390 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP1))]
7393 [(set_attr "length" "4")
7394 ;; What is the class of the insn ???
7395 (set_attr "type" "multi")])
7397 (define_insn "mcop2"
7398 [(set (match_operand:SI 0 "fpr_operand" "=f")
7399 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7400 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP2))]
7403 [(set_attr "length" "4")
7404 ;; What is the class of the insn ???
7405 (set_attr "type" "multi")])
7407 (define_insn "*mdunpackh_internal"
7408 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7409 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7410 UNSPEC_MDUNPACKH_INTERNAL))]
7413 [(set_attr "length" "4")
7414 (set_attr "type" "mdunpackh")])
7416 (define_insn_and_split "mdunpackh"
7417 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7418 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7420 (clobber (match_scratch:V4SI 2 "=x"))]
7425 (unspec:V4SI [(match_dup 1)] UNSPEC_MDUNPACKH_INTERNAL))
7432 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7433 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7434 operands[5] = frv_index_memory (operands[0], DImode, 1);
7435 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7437 [(set_attr "length" "20")
7438 (set_attr "type" "multi")])
7440 (define_insn "*mbtohe_internal"
7441 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7442 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7443 UNSPEC_MBTOHE_INTERNAL))]
7446 [(set_attr "length" "4")
7447 (set_attr "type" "mbhconve")])
7449 (define_insn_and_split "mbtohe"
7450 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7451 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7453 (clobber (match_scratch:V4SI 2 "=x"))]
7458 (unspec:V4SI [(match_dup 1)] UNSPEC_MBTOHE_INTERNAL))
7465 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7466 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7467 operands[5] = frv_index_memory (operands[0], DImode, 1);
7468 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7470 [(set_attr "length" "20")
7471 (set_attr "type" "multi")])
7473 ;; Quad product-sum (halfword) instructions only found on the FR400.
7476 (define_expand "mqxmachs"
7477 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7478 (unspec:V4SI [(match_dup 0)
7479 (match_operand:DI 1 "even_fpr_operand" "")
7480 (match_operand:DI 2 "even_fpr_operand" "")
7481 (match_operand:V4QI 3 "accg_operand" "")
7485 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7487 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACHS);")
7489 (define_expand "mqxmacxhs"
7490 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7491 (unspec:V4SI [(match_dup 0)
7492 (match_operand:DI 1 "even_fpr_operand" "")
7493 (match_operand:DI 2 "even_fpr_operand" "")
7494 (match_operand:V4QI 3 "accg_operand" "")
7498 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7500 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACXHS);")
7502 (define_expand "mqmacxhs"
7503 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7504 (unspec:V4SI [(match_dup 0)
7505 (match_operand:DI 1 "even_fpr_operand" "")
7506 (match_operand:DI 2 "even_fpr_operand" "")
7507 (match_operand:V4QI 3 "accg_operand" "")
7511 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7513 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACXHS);")
7515 (define_insn "*mqmach2"
7516 [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7517 (unspec:V4SI [(match_dup 0)
7518 (match_operand:DI 1 "even_fpr_operand" "h")
7519 (match_operand:DI 2 "even_fpr_operand" "h")
7520 (match_operand:V4QI 3 "accg_operand" "+B")
7521 (match_operand:SI 4 "const_int_operand" "n")]
7524 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))]
7528 switch (INTVAL (operands[4]))
7531 case FRV_BUILTIN_MQXMACHS: return \"mqxmachs %1, %2, %0\";
7532 case FRV_BUILTIN_MQXMACXHS: return \"mqxmacxhs %1, %2, %0\";
7533 case FRV_BUILTIN_MQMACXHS: return \"mqmacxhs %1, %2, %0\";
7536 fatal_insn (\"Bad media insn, mqmach2\", insn);
7538 [(set_attr "length" "4")
7539 (set_attr "type" "mqmach")])
7541 ;; Accumulator addition/subtraction: type "maddacc"
7543 (define_expand "maddaccs"
7544 [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7545 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7547 (set (match_operand:QI 2 "accg_operand" "")
7548 (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7552 "operands[4] = GEN_INT (FRV_BUILTIN_MADDACCS);")
7554 (define_expand "msubaccs"
7555 [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7556 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7558 (set (match_operand:QI 2 "accg_operand" "")
7559 (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7563 "operands[4] = GEN_INT (FRV_BUILTIN_MSUBACCS);")
7565 (define_insn "masaccs"
7566 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7567 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")]
7569 (set (match_operand:HI 2 "accg_operand" "=B")
7570 (unspec:HI [(match_operand:HI 3 "accg_operand" "B")]
7574 [(set_attr "length" "4")
7575 (set_attr "type" "maddacc")])
7577 (define_insn "*maddacc"
7578 [(set (match_operand:SI 0 "acc_operand" "=a")
7579 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "b")]
7581 (set (match_operand:QI 2 "accg_operand" "=B")
7582 (unspec:QI [(match_operand:HI 3 "accg_operand" "B")
7583 (match_operand:SI 4 "const_int_operand" "n")]
7588 switch (INTVAL (operands[4]))
7591 case FRV_BUILTIN_MADDACCS: return \"maddaccs %1, %0\";
7592 case FRV_BUILTIN_MSUBACCS: return \"msubaccs %1, %0\";
7595 fatal_insn (\"Bad media insn, maddacc\", insn);
7597 [(set_attr "length" "4")
7598 (set_attr "type" "maddacc")])
7600 ;; Dual accumulator addition/subtraction: type "mdaddacc"
7602 (define_expand "mdaddaccs"
7603 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7604 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7606 (set (match_operand:HI 2 "accg_operand" "")
7607 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7609 UNSPEC_MDADDACC))])]
7611 "operands[4] = GEN_INT (FRV_BUILTIN_MDADDACCS);")
7613 (define_expand "mdsubaccs"
7614 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7615 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7617 (set (match_operand:HI 2 "accg_operand" "")
7618 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7620 UNSPEC_MDADDACC))])]
7622 "operands[4] = GEN_INT (FRV_BUILTIN_MDSUBACCS);")
7624 (define_insn "mdasaccs"
7625 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
7626 (unspec:V4SI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7628 (set (match_operand:V4QI 2 "accg_operand" "=B")
7629 (unspec:V4QI [(match_operand:V4QI 3 "accg_operand" "B")]
7633 [(set_attr "length" "4")
7634 (set_attr "type" "mdaddacc")])
7636 (define_insn "*mdaddacc"
7637 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7638 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7640 (set (match_operand:HI 2 "accg_operand" "=B")
7641 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "B")
7642 (match_operand:SI 4 "const_int_operand" "n")]
7647 switch (INTVAL (operands[4]))
7650 case FRV_BUILTIN_MDADDACCS: return \"mdaddaccs %1, %0\";
7651 case FRV_BUILTIN_MDSUBACCS: return \"mdsubaccs %1, %0\";
7654 fatal_insn (\"Bad media insn, mdaddacc\", insn);
7656 [(set_attr "length" "4")
7657 (set_attr "type" "mdaddacc")])
7659 ;; Dual absolute (halfword): type "mabsh"
7661 (define_insn "mabshs"
7662 [(set (match_operand:SI 0 "fpr_operand" "=f")
7663 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MABSHS))]
7666 [(set_attr "length" "4")
7667 (set_attr "type" "mabsh")])
7669 ;; Dual rotate: type "mdrot"
7671 (define_insn "mdrotli"
7672 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7673 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7674 (match_operand:SI 2 "uint5_operand" "I")]
7677 "mdrotli %1, %2, %0"
7678 [(set_attr "length" "4")
7679 (set_attr "type" "mdrot")])
7681 ;; Dual coupling (concatenation): type "mcpl"
7683 (define_insn "mcplhi"
7684 [(set (match_operand:SI 0 "fpr_operand" "=f")
7685 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7686 (match_operand:SI 2 "uint4_operand" "I")]
7690 [(set_attr "length" "4")
7691 (set_attr "type" "mcpl")])
7693 (define_insn "mcpli"
7694 [(set (match_operand:SI 0 "fpr_operand" "=f")
7695 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7696 (match_operand:SI 2 "uint5_operand" "I")]
7700 [(set_attr "length" "4")
7701 (set_attr "type" "mcpl")])
7703 ;; Dual cut: type "mdcut"
7705 (define_insn "mdcutssi"
7706 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7707 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")
7708 (match_operand:SI 2 "int6_operand" "I")
7709 (match_operand:HI 3 "accg_operand" "B")]
7712 "mdcutssi %1, %2, %0"
7713 [(set_attr "length" "4")
7714 (set_attr "type" "mdcut")])
7716 ;; Quad saturate (halfword): type "mqsath"
7718 (define_insn "mqsaths"
7719 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7720 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7721 (match_operand:DI 2 "even_fpr_operand" "h")]
7724 "mqsaths %1, %2, %0"
7725 [(set_attr "length" "4")
7726 (set_attr "type" "mqsath")])
7728 ;; Quad limit instructions: type "mqlimh"
7730 (define_insn "mqlclrhs"
7731 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7732 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7733 (match_operand:DI 2 "even_fpr_operand" "h")]
7735 "TARGET_MEDIA_FR450"
7736 "mqlclrhs %1, %2, %0"
7737 [(set_attr "length" "4")
7738 (set_attr "type" "mqlimh")])
7740 (define_insn "mqlmths"
7741 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7742 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7743 (match_operand:DI 2 "even_fpr_operand" "h")]
7745 "TARGET_MEDIA_FR450"
7746 "mqlmths %1, %2, %0"
7747 [(set_attr "length" "4")
7748 (set_attr "type" "mqlimh")])
7750 (define_insn "mqsllhi"
7751 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7752 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7753 (match_operand:SI 2 "int6_operand" "I")]
7755 "TARGET_MEDIA_FR450"
7756 "mqsllhi %1, %2, %0"
7757 [(set_attr "length" "4")
7758 (set_attr "type" "mqshift")])
7760 (define_insn "mqsrahi"
7761 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7762 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7763 (match_operand:SI 2 "int6_operand" "I")]
7765 "TARGET_MEDIA_FR450"
7766 "mqsrahi %1, %2, %0"
7767 [(set_attr "length" "4")
7768 (set_attr "type" "mqshift")])
7770 ;; Set hi/lo instructions: type "mset"
7772 (define_insn "mhsetlos"
7773 [(set (match_operand:SI 0 "fpr_operand" "=f")
7774 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7775 (match_operand:SI 2 "int12_operand" "NOP")]
7779 [(set_attr "length" "4")
7780 (set_attr "type" "mset")])
7782 (define_insn "mhsetloh"
7783 [(set (match_operand:SI 0 "fpr_operand" "=f")
7784 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7785 (match_operand:SI 2 "int5_operand" "I")]
7789 [(set_attr "length" "4")
7790 (set_attr "type" "mset")])
7792 (define_insn "mhsethis"
7793 [(set (match_operand:SI 0 "fpr_operand" "=f")
7794 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7795 (match_operand:SI 2 "int12_operand" "NOP")]
7799 [(set_attr "length" "4")
7800 (set_attr "type" "mset")])
7802 (define_insn "mhsethih"
7803 [(set (match_operand:SI 0 "fpr_operand" "=f")
7804 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7805 (match_operand:SI 2 "int5_operand" "I")]
7809 [(set_attr "length" "4")
7810 (set_attr "type" "mset")])
7812 (define_insn "mhdsets"
7813 [(set (match_operand:SI 0 "fpr_operand" "=f")
7814 (unspec:SI [(match_operand:SI 1 "int12_operand" "NOP")]
7818 [(set_attr "length" "4")
7819 (set_attr "type" "mset")])
7821 (define_insn "mhdseth"
7822 [(set (match_operand:SI 0 "fpr_operand" "=f")
7823 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7824 (match_operand:SI 2 "int5_operand" "I")]
7828 [(set_attr "length" "4")
7829 (set_attr "type" "mset")])
7831 ;;-----------------------------------------------------------------------------
7833 (define_expand "symGOT2reg"
7834 [(match_operand:SI 0 "" "")
7835 (match_operand:SI 1 "" "")
7836 (match_operand:SI 2 "" "")
7837 (match_operand:SI 3 "" "")]
7843 insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1], operands[2], operands[3]));
7845 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7847 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7852 (define_expand "symGOT2reg_i"
7853 [(set (match_operand:SI 0 "" "")
7854 (mem:SI (plus:SI (match_operand:SI 2 "" "")
7855 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7856 (match_operand:SI 3 "" "")]
7861 (define_expand "symGOT2reg_hilo"
7863 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7864 (match_dup 4)] UNSPEC_GOT))))
7866 (lo_sum:SI (match_dup 6)
7867 (const:SI (unspec:SI [(match_dup 1)
7868 (match_operand:SI 3 "" "")]
7870 (set (match_operand:SI 0 "" "")
7871 (mem:SI (plus:SI (match_dup 5)
7872 (match_operand:SI 2 "" ""))))
7877 if (!can_create_pseudo_p ())
7878 operands[6] = operands[5] = operands[0];
7881 operands[6] = gen_reg_rtx (SImode);
7882 operands[5] = gen_reg_rtx (SImode);
7885 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7886 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7889 (define_expand "symGOTOFF2reg_hilo"
7891 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7892 (match_dup 4)] UNSPEC_GOT))))
7894 (lo_sum:SI (match_dup 6)
7895 (const:SI (unspec:SI [(match_dup 1)
7896 (match_operand:SI 3 "" "")]
7898 (set (match_operand:SI 0 "" "")
7899 (plus:SI (match_dup 5)
7900 (match_operand:SI 2 "" "")))
7905 if (!can_create_pseudo_p ())
7906 operands[6] = operands[5] = operands[0];
7909 operands[6] = gen_reg_rtx (SImode);
7910 operands[5] = gen_reg_rtx (SImode);
7913 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7914 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7917 (define_expand "symGOTOFF2reg"
7918 [(match_operand:SI 0 "" "")
7919 (match_operand:SI 1 "" "")
7920 (match_operand:SI 2 "" "")
7921 (match_operand:SI 3 "" "")]
7925 rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1], operands[2], operands[3]));
7927 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7932 (define_expand "symGOTOFF2reg_i"
7933 [(set (match_operand:SI 0 "" "")
7934 (plus:SI (match_operand:SI 2 "" "")
7936 (unspec:SI [(match_operand:SI 1 "" "")
7937 (match_operand:SI 3 "" "")]
7942 (define_expand "symGPREL2reg"
7943 [(match_operand:SI 0 "" "")
7944 (match_operand:SI 1 "" "")
7945 (match_operand:SI 2 "" "")
7946 (match_operand:SI 3 "" "")
7953 if (!can_create_pseudo_p ())
7954 operands[4] = operands[0];
7956 operands[4] = gen_reg_rtx (SImode);
7958 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7960 insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1],
7961 operands[4], operands[3]));
7963 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7968 (define_expand "symGPREL2reg_hilo"
7969 [(match_operand:SI 0 "" "")
7970 (match_operand:SI 1 "" "")
7971 (match_operand:SI 2 "" "")
7972 (match_operand:SI 3 "" "")
7979 if (!can_create_pseudo_p ())
7981 emit_insn (gen_symGOT2reg (operands[0], operands[1], operands[2],
7982 GEN_INT (R_FRV_GOT12)));
7986 operands[4] = gen_reg_rtx (SImode);
7988 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7990 insn = emit_insn (gen_symGOTOFF2reg_hilo (operands[0], operands[1],
7991 operands[4], operands[3]));
7993 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
8009 (UNSPEC_PREFETCH0 163)
8010 (UNSPEC_PREFETCH 164)
8011 (UNSPEC_IACCreadll 165)
8012 (UNSPEC_IACCreadl 166)
8013 (UNSPEC_IACCsetll 167)
8014 (UNSPEC_IACCsetl 168)
8023 [(set (match_operand:DI 0 "integer_register_operand" "=d")
8024 (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
8025 (match_operand:SI 2 "integer_register_operand" "d")]
8029 [(set_attr "length" "4")
8030 (set_attr "type" "mul")])
8033 [(set (match_operand:DI 0 "integer_register_operand" "=d")
8034 (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
8035 (match_operand:SI 2 "integer_register_operand" "d")]
8039 [(set_attr "length" "4")
8040 (set_attr "type" "mul")])
8042 (define_insn "smass"
8043 [(set (reg:DI IACC0_REG)
8044 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
8045 (match_operand:SI 1 "integer_register_operand" "d")
8048 "TARGET_FR405_BUILTINS"
8050 [(set_attr "length" "4")
8051 (set_attr "type" "macc")])
8053 (define_insn "smsss"
8054 [(set (reg:DI IACC0_REG)
8055 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
8056 (match_operand:SI 1 "integer_register_operand" "d")
8059 "TARGET_FR405_BUILTINS"
8061 [(set_attr "length" "4")
8062 (set_attr "type" "macc")])
8065 [(set (reg:DI IACC0_REG)
8066 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
8067 (match_operand:SI 1 "integer_register_operand" "d")]
8069 "TARGET_FR405_BUILTINS"
8071 [(set_attr "length" "4")
8072 (set_attr "type" "macc")])
8074 (define_insn "addss"
8075 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8076 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8077 (match_operand:SI 2 "integer_register_operand" "d")]
8079 "TARGET_FR405_BUILTINS"
8081 [(set_attr "length" "4")
8082 (set_attr "type" "int")])
8084 (define_insn "subss"
8085 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8086 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8087 (match_operand:SI 2 "integer_register_operand" "d")]
8089 "TARGET_FR405_BUILTINS"
8091 [(set_attr "length" "4")
8092 (set_attr "type" "int")])
8094 (define_insn "slass"
8095 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8096 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8097 (match_operand:SI 2 "integer_register_operand" "d")]
8099 "TARGET_FR405_BUILTINS"
8101 [(set_attr "length" "4")
8102 (set_attr "type" "int")])
8105 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8106 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8107 (match_operand:SI 2 "integer_register_operand" "d")]
8111 [(set_attr "length" "4")
8112 (set_attr "type" "scan")])
8114 (define_insn "scutss"
8115 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8116 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8119 "TARGET_FR405_BUILTINS"
8121 [(set_attr "length" "4")
8122 (set_attr "type" "cut")])
8124 (define_insn "frv_prefetch0"
8125 [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
8131 [(set_attr "length" "4")])
8133 (define_insn "frv_prefetch"
8134 [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
8138 "TARGET_FR500_FR550_BUILTINS"
8139 "nop.p\\n\\tnldub @(%0, gr0), gr0"
8140 [(set_attr "length" "8")])
8144 (define_insn "call_gettlsoff"
8145 [(set (match_operand:SI 0 "register_operand" "=D09")
8147 [(match_operand:SI 1 "symbolic_operand" "")]
8149 (clobber (reg:SI GR8_REG))
8150 (clobber (reg:SI LRREG))
8151 (use (match_operand:SI 2 "register_operand" "D15"))]
8153 "call #gettlsoff(%a1)"
8154 [(set_attr "length" "4")
8155 (set_attr "type" "load_or_call")])
8157 ;; We have to expand this like a libcall (it sort of actually is)
8158 ;; because otherwise sched may move, for example, an insn that sets up
8159 ;; GR8 for a subsequence call before the *tls_indirect_call insn, and
8160 ;; then reload won't be able to fix things up.
8161 (define_expand "tls_indirect_call"
8162 [(set (reg:DI GR8_REG)
8163 (match_operand:DI 2 "register_operand" ""))
8165 [(set (reg:SI GR9_REG)
8167 [(match_operand:SI 1 "symbolic_operand" "")
8169 UNSPEC_TLS_INDIRECT_CALL))
8170 (clobber (reg:SI GR8_REG))
8171 (clobber (reg:SI LRREG))
8172 (use (match_operand:SI 3 "register_operand" ""))])
8173 (set (match_operand:SI 0 "register_operand" "")
8177 (define_insn "*tls_indirect_call"
8178 [(set (reg:SI GR9_REG)
8180 [(match_operand:SI 0 "symbolic_operand" "")
8182 UNSPEC_TLS_INDIRECT_CALL))
8183 (clobber (reg:SI GR8_REG))
8184 (clobber (reg:SI LRREG))
8185 ;; If there was a way to represent the fact that we don't need GR9
8186 ;; or GR15 to be set before this instruction (it could be in
8187 ;; parallel), we could use it here. This change wouldn't apply to
8188 ;; call_gettlsoff, thought, since the linker may turn the latter
8189 ;; into ldi @(gr15,offset),gr9.
8190 (use (match_operand:SI 1 "register_operand" "D15"))]
8192 "calll #gettlsoff(%a0)@(gr8,gr0)"
8193 [(set_attr "length" "4")
8194 (set_attr "type" "jumpl")])
8196 (define_insn "tls_load_gottlsoff12"
8197 [(set (match_operand:SI 0 "register_operand" "=r")
8199 [(match_operand:SI 1 "symbolic_operand" "")
8200 (match_operand:SI 2 "register_operand" "r")]
8201 UNSPEC_TLS_LOAD_GOTTLSOFF12))]
8203 "ldi @(%2, #gottlsoff12(%1)), %0"
8204 [(set_attr "length" "4")])
8206 (define_expand "tlsoff_hilo"
8207 [(set (match_operand:SI 0 "register_operand" "=r")
8208 (high:SI (const:SI (unspec:SI
8209 [(match_operand:SI 1 "symbolic_operand" "")
8210 (match_operand:SI 2 "immediate_operand" "n")]
8213 (lo_sum:SI (match_dup 0)
8214 (const:SI (unspec:SI [(match_dup 1)
8215 (match_dup 3)] UNSPEC_GOT))))]
8219 operands[3] = GEN_INT (INTVAL (operands[2]) + 1);
8222 ;; Just like movdi_ldd, but with relaxation annotations.
8223 (define_insn "tls_tlsdesc_ldd"
8224 [(set (match_operand:DI 0 "register_operand" "=r")
8225 (unspec:DI [(mem:DI (unspec:SI
8226 [(match_operand:SI 1 "register_operand" "r")
8227 (match_operand:SI 2 "register_operand" "r")
8228 (match_operand:SI 3 "symbolic_operand" "")]
8229 UNSPEC_TLS_TLSDESC_LDD_AUX))]
8230 UNSPEC_TLS_TLSDESC_LDD))]
8232 "ldd #tlsdesc(%a3)@(%1,%2), %0"
8233 [(set_attr "length" "4")
8234 (set_attr "type" "gload")])
8236 (define_insn "tls_tlsoff_ld"
8237 [(set (match_operand:SI 0 "register_operand" "=r")
8239 [(match_operand:SI 1 "register_operand" "r")
8240 (match_operand:SI 2 "register_operand" "r")
8241 (match_operand:SI 3 "symbolic_operand" "")]
8242 UNSPEC_TLS_TLSOFF_LD)))]
8244 "ld #tlsoff(%a3)@(%1,%2), %0"
8245 [(set_attr "length" "4")
8246 (set_attr "type" "gload")])
8248 (define_insn "tls_lddi"
8249 [(set (match_operand:DI 0 "register_operand" "=r")
8250 (unspec:DI [(match_operand:SI 1 "symbolic_operand" "")
8251 (match_operand:SI 2 "register_operand" "d")]
8254 "lddi @(%2, #gottlsdesc12(%a1)), %0"
8255 [(set_attr "length" "4")
8256 (set_attr "type" "gload")])