1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
45 ;; Processor type -- this attribute must exactly match the processor_type
46 ;; enumeration in alpha.h.
48 (define_attr "cpu" "ev4,ev5,ev6"
49 (const (symbol_ref "alpha_cpu")))
51 ;; Define an insn type attribute. This is used in function unit delay
52 ;; computations, among other purposes. For the most part, we use the names
53 ;; defined in the EV4 documentation, but add a few that we have to know about
57 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
58 (const_string "iadd"))
60 ;; Describe a user's asm statement.
61 (define_asm_attributes
62 [(set_attr "type" "multi")])
64 ;; Define the operand size an insn operates on. Used primarily by mul
65 ;; and div operations that have size dependant timings.
67 (define_attr "opsize" "si,di,udi" (const_string "di"))
69 ;; The TRAP_TYPE attribute marks instructions that may generate traps
70 ;; (which are imprecise and may need a trapb if software completion
73 (define_attr "trap" "no,yes" (const_string "no"))
75 ;; The length of an instruction sequence in bytes.
77 (define_attr "length" "" (const_int 4))
79 ;; On EV4 there are two classes of resources to consider: resources needed
80 ;; to issue, and resources needed to execute. IBUS[01] are in the first
81 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
82 ;; (There are a few other register-like resources, but ...)
84 ; First, describe all of the issue constraints with single cycle delays.
85 ; All insns need a bus, but all except loads require one or the other.
86 (define_function_unit "ev4_ibus0" 1 0
87 (and (eq_attr "cpu" "ev4")
88 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
91 (define_function_unit "ev4_ibus1" 1 0
92 (and (eq_attr "cpu" "ev4")
93 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
96 ; Memory delivers its result in three cycles. Actually return one and
97 ; take care of this in adjust_cost, since we want to handle user-defined
99 (define_function_unit "ev4_abox" 1 0
100 (and (eq_attr "cpu" "ev4")
101 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
104 ; Branches have no delay cost, but do tie up the unit for two cycles.
105 (define_function_unit "ev4_bbox" 1 1
106 (and (eq_attr "cpu" "ev4")
107 (eq_attr "type" "ibr,fbr,jsr"))
110 ; Arithmetic insns are normally have their results available after
111 ; two cycles. There are a number of exceptions. They are encoded in
112 ; ADJUST_COST. Some of the other insns have similar exceptions.
113 (define_function_unit "ev4_ebox" 1 0
114 (and (eq_attr "cpu" "ev4")
115 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
118 (define_function_unit "imul" 1 0
119 (and (eq_attr "cpu" "ev4")
120 (and (eq_attr "type" "imul")
121 (eq_attr "opsize" "si")))
124 (define_function_unit "imul" 1 0
125 (and (eq_attr "cpu" "ev4")
126 (and (eq_attr "type" "imul")
127 (eq_attr "opsize" "!si")))
130 (define_function_unit "ev4_fbox" 1 0
131 (and (eq_attr "cpu" "ev4")
132 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
135 (define_function_unit "fdiv" 1 0
136 (and (eq_attr "cpu" "ev4")
137 (and (eq_attr "type" "fdiv")
138 (eq_attr "opsize" "si")))
141 (define_function_unit "fdiv" 1 0
142 (and (eq_attr "cpu" "ev4")
143 (and (eq_attr "type" "fdiv")
144 (eq_attr "opsize" "di")))
147 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
149 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
150 ;; with the combined resource EBOX.
152 (define_function_unit "ev5_ebox" 2 0
153 (and (eq_attr "cpu" "ev5")
154 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
157 ; Memory takes at least 2 clocks. Return one from here and fix up with
158 ; user-defined latencies in adjust_cost.
159 (define_function_unit "ev5_ebox" 2 0
160 (and (eq_attr "cpu" "ev5")
161 (eq_attr "type" "ild,fld,ldsym"))
164 ; Loads can dual issue with one another, but loads and stores do not mix.
165 (define_function_unit "ev5_e0" 1 0
166 (and (eq_attr "cpu" "ev5")
167 (eq_attr "type" "ild,fld,ldsym"))
169 [(eq_attr "type" "ist,fst")])
171 ; Stores, shifts, multiplies can only issue to E0
172 (define_function_unit "ev5_e0" 1 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "ist,fst,shift,imul"))
177 ; Motion video insns also issue only to E0, and take two ticks.
178 (define_function_unit "ev5_e0" 1 0
179 (and (eq_attr "cpu" "ev5")
180 (eq_attr "type" "mvi"))
183 ; Conditional moves always take 2 ticks.
184 (define_function_unit "ev5_ebox" 2 0
185 (and (eq_attr "cpu" "ev5")
186 (eq_attr "type" "icmov"))
189 ; Branches can only issue to E1
190 (define_function_unit "ev5_e1" 1 0
191 (and (eq_attr "cpu" "ev5")
192 (eq_attr "type" "ibr,jsr"))
195 ; Multiplies also use the integer multiplier.
196 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
197 ; cycles before an integer multiplication completes."
198 (define_function_unit "imul" 1 0
199 (and (eq_attr "cpu" "ev5")
200 (and (eq_attr "type" "imul")
201 (eq_attr "opsize" "si")))
204 (define_function_unit "imul" 1 0
205 (and (eq_attr "cpu" "ev5")
206 (and (eq_attr "type" "imul")
207 (eq_attr "opsize" "di")))
210 (define_function_unit "imul" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (and (eq_attr "type" "imul")
213 (eq_attr "opsize" "udi")))
216 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
217 ;; on either so we have to play the game again.
219 (define_function_unit "ev5_fbox" 2 0
220 (and (eq_attr "cpu" "ev5")
221 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
224 (define_function_unit "ev5_fm" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "fmul"))
229 ; Add and cmov as you would expect; fbr never produces a result;
230 ; fdiv issues through fa to the divider,
231 (define_function_unit "ev5_fa" 1 0
232 (and (eq_attr "cpu" "ev5")
233 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
236 ; ??? How to: "No instruction can be issued to pipe FA exactly five
237 ; cycles before a floating point divide completes."
238 (define_function_unit "fdiv" 1 0
239 (and (eq_attr "cpu" "ev5")
240 (and (eq_attr "type" "fdiv")
241 (eq_attr "opsize" "si")))
242 15 15) ; 15 to 31 data dependant
244 (define_function_unit "fdiv" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "fdiv")
247 (eq_attr "opsize" "di")))
248 22 22) ; 22 to 60 data dependant
250 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
252 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
253 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
255 ;; Conditional moves decompose into two independant primitives, each
256 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
258 (define_function_unit "ev6_ebox" 4 0
259 (and (eq_attr "cpu" "ev6")
260 (eq_attr "type" "icmov"))
263 (define_function_unit "ev6_ebox" 4 0
264 (and (eq_attr "cpu" "ev6")
265 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
268 ;; Integer loads take at least 3 clocks, and only issue to lower units.
269 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
270 (define_function_unit "ev6_l" 2 0
271 (and (eq_attr "cpu" "ev6")
272 (eq_attr "type" "ild,ldsym,ist,fst"))
275 ;; FP loads take at least 4 clocks. Return two from here...
276 (define_function_unit "ev6_l" 2 0
277 (and (eq_attr "cpu" "ev6")
278 (eq_attr "type" "fld"))
281 ;; Motion video insns also issue only to U0, and take three ticks.
282 (define_function_unit "ev6_u0" 1 0
283 (and (eq_attr "cpu" "ev6")
284 (eq_attr "type" "mvi"))
287 (define_function_unit "ev6_u" 2 0
288 (and (eq_attr "cpu" "ev6")
289 (eq_attr "type" "mvi"))
292 ;; Shifts issue to either upper pipe.
293 (define_function_unit "ev6_u" 2 0
294 (and (eq_attr "cpu" "ev6")
295 (eq_attr "type" "shift"))
298 ;; Multiplies issue only to U1, and all take 7 ticks.
299 ;; Rather than create a new function unit just for U1, reuse IMUL
300 (define_function_unit "imul" 1 0
301 (and (eq_attr "cpu" "ev6")
302 (eq_attr "type" "imul"))
305 (define_function_unit "ev6_u" 2 0
306 (and (eq_attr "cpu" "ev6")
307 (eq_attr "type" "imul"))
310 ;; Branches issue to either upper pipe
311 (define_function_unit "ev6_u" 2 0
312 (and (eq_attr "cpu" "ev6")
313 (eq_attr "type" "ibr"))
316 ;; Calls only issue to L0.
317 (define_function_unit "ev6_l0" 1 0
318 (and (eq_attr "cpu" "ev6")
319 (eq_attr "type" "jsr"))
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "jsr"))
327 ;; Ftoi/itof only issue to lower pipes
328 (define_function_unit "ev6_l" 2 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "ftoi"))
333 (define_function_unit "ev6_l" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "itof"))
338 ;; For the FPU we are very similar to EV5, except there's no insn that
339 ;; can issue to fm & fa, so we get to leave that out.
341 (define_function_unit "ev6_fm" 1 0
342 (and (eq_attr "cpu" "ev6")
343 (eq_attr "type" "fmul"))
346 (define_function_unit "ev6_fa" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
351 (define_function_unit "ev6_fa" 1 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "fcmov"))
356 (define_function_unit "fdiv" 1 0
357 (and (eq_attr "cpu" "ev6")
358 (and (eq_attr "type" "fdiv")
359 (eq_attr "opsize" "si")))
362 (define_function_unit "fdiv" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (and (eq_attr "type" "fdiv")
365 (eq_attr "opsize" "di")))
368 (define_function_unit "fsqrt" 1 0
369 (and (eq_attr "cpu" "ev6")
370 (and (eq_attr "type" "fsqrt")
371 (eq_attr "opsize" "si")))
374 (define_function_unit "fsqrt" 1 0
375 (and (eq_attr "cpu" "ev6")
376 (and (eq_attr "type" "fsqrt")
377 (eq_attr "opsize" "di")))
380 ; ??? The FPU communicates with memory and the integer register file
381 ; via two fp store units. We need a slot in the fst immediately, and
382 ; a slot in LOW after the operand data is ready. At which point the
383 ; data may be moved either to the store queue or the integer register
384 ; file and the insn retired.
387 ;; First define the arithmetic insns. Note that the 32-bit forms also
390 ;; Handle 32-64 bit extension from memory to a floating point register
391 ;; specially, since this ocurrs frequently in int->double conversions.
392 ;; This is done with a define_split after reload converting the plain
393 ;; sign-extension into a load+unspec, which of course results in lds+cvtlq.
395 ;; Note that while we must retain the =f case in the insn for reload's
396 ;; benefit, it should be eliminated after reload, so we should never emit
397 ;; code for that case. But we don't reject the possibility.
399 (define_insn "extendsidi2"
400 [(set (match_operand:DI 0 "register_operand" "=r,r,?f")
401 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
406 lds %0,%1\;cvtlq %0,%0"
407 [(set_attr "type" "iadd,ild,fld")
408 (set_attr "length" "*,*,8")])
410 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
412 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
413 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
415 [(set (match_dup 2) (match_dup 1))
416 (set (match_dup 0) (unspec:DI [(match_dup 2)] 4))]
417 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
420 [(set (match_operand:DI 0 "register_operand" "=f")
421 (unspec:DI [(match_operand:SI 1 "register_operand" "f")] 4))]
424 [(set_attr "type" "fadd")])
426 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
427 ;; generates better code. We have the anonymous addsi3 pattern below in
428 ;; case combine wants to make it.
429 (define_expand "addsi3"
430 [(set (match_operand:SI 0 "register_operand" "")
431 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
432 (match_operand:SI 2 "add_operand" "")))]
438 rtx op1 = gen_lowpart (DImode, operands[1]);
439 rtx op2 = gen_lowpart (DImode, operands[2]);
441 if (! cse_not_expected)
443 rtx tmp = gen_reg_rtx (DImode);
444 emit_insn (gen_adddi3 (tmp, op1, op2));
445 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
448 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
454 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
455 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
456 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
465 [(set (match_operand:SI 0 "register_operand" "")
466 (plus:SI (match_operand:SI 1 "register_operand" "")
467 (match_operand:SI 2 "const_int_operand" "")))]
468 "! add_operand (operands[2], SImode)"
469 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
470 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
473 HOST_WIDE_INT val = INTVAL (operands[2]);
474 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
475 HOST_WIDE_INT rest = val - low;
477 operands[3] = GEN_INT (rest);
478 operands[4] = GEN_INT (low);
482 [(set (match_operand:DI 0 "register_operand" "=r,r")
484 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
485 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
492 [(set (match_operand:DI 0 "register_operand" "")
494 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
495 (match_operand:SI 2 "const_int_operand" ""))))
496 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
497 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
498 && INTVAL (operands[2]) % 4 == 0"
499 [(set (match_dup 3) (match_dup 4))
500 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
505 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
511 operands[4] = GEN_INT (val);
512 operands[5] = GEN_INT (mult);
516 [(set (match_operand:DI 0 "register_operand" "")
518 (plus:SI (match_operator:SI 1 "comparison_operator"
519 [(match_operand 2 "" "")
520 (match_operand 3 "" "")])
521 (match_operand:SI 4 "add_operand" ""))))
522 (clobber (match_operand:DI 5 "register_operand" ""))]
524 [(set (match_dup 5) (match_dup 6))
525 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
528 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
529 operands[2], operands[3]);
530 operands[7] = gen_lowpart (SImode, operands[5]);
533 (define_insn "adddi3"
534 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
535 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
536 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
540 static const char * const pattern[4] = {
547 /* The NT stack unwind code can't handle a subq to adjust the stack
548 (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
549 the exception handling code will loop if a subq is used and an
552 The 19980616 change to emit prologues as RTL also confused some
553 versions of GDB, which also interprets prologues. This has been
554 fixed as of GDB 4.18, but it does not harm to unconditionally
557 int which = which_alternative;
559 if (operands[0] == stack_pointer_rtx
560 && GET_CODE (operands[2]) == CONST_INT
561 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
564 return pattern[which];
567 ;; ??? Allow large constants when basing off the frame pointer or some
568 ;; virtual register that may eliminate to the frame pointer. This is
569 ;; done because register elimination offsets will change the hi/lo split,
570 ;; and if we split before reload, we will require additional instructions.
573 [(set (match_operand:DI 0 "register_operand" "=r")
574 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
575 (match_operand:DI 2 "const_int_operand" "n")))]
576 "REG_OK_FP_BASE_P (operands[1])"
579 ;; Don't do this if we are adjusting SP since we don't want to do it
580 ;; in two steps. Don't split FP sources for the reason listed above.
582 [(set (match_operand:DI 0 "register_operand" "")
583 (plus:DI (match_operand:DI 1 "register_operand" "")
584 (match_operand:DI 2 "const_int_operand" "")))]
585 "! add_operand (operands[2], DImode)
586 && operands[0] != stack_pointer_rtx
587 && operands[1] != frame_pointer_rtx
588 && operands[1] != arg_pointer_rtx"
589 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
590 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
593 HOST_WIDE_INT val = INTVAL (operands[2]);
594 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
595 HOST_WIDE_INT rest = val - low;
597 operands[3] = GEN_INT (rest);
598 operands[4] = GEN_INT (low);
602 [(set (match_operand:SI 0 "register_operand" "=r,r")
603 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
604 (match_operand:SI 2 "const48_operand" "I,I"))
605 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
612 [(set (match_operand:DI 0 "register_operand" "=r,r")
614 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
615 (match_operand:SI 2 "const48_operand" "I,I"))
616 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
623 [(set (match_operand:DI 0 "register_operand" "")
625 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
626 [(match_operand 2 "" "")
627 (match_operand 3 "" "")])
628 (match_operand:SI 4 "const48_operand" ""))
629 (match_operand:SI 5 "sext_add_operand" ""))))
630 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
632 [(set (match_dup 6) (match_dup 7))
634 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
638 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
639 operands[2], operands[3]);
640 operands[8] = gen_lowpart (SImode, operands[6]);
644 [(set (match_operand:DI 0 "register_operand" "=r,r")
645 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
646 (match_operand:DI 2 "const48_operand" "I,I"))
647 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
653 ;; These variants of the above insns can occur if the third operand
654 ;; is the frame pointer, or other eliminable register. E.g. some
655 ;; register holding an offset from the stack pointer. This is a
656 ;; kludge, but there doesn't seem to be a way around it. Only
657 ;; recognize them while reloading.
660 [(set (match_operand:DI 0 "some_operand" "=r,&r")
661 (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "%r,r")
662 (match_operand:DI 2 "some_operand" "%r,r"))
663 (match_operand:DI 3 "some_operand" "IOKL,r")))]
668 [(set (match_operand:DI 0 "register_operand" "")
669 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
670 (match_operand:DI 2 "register_operand" ""))
671 (match_operand:DI 3 "add_operand" "")))]
673 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
674 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
678 [(set (match_operand:SI 0 "some_operand" "=r,&r")
679 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
680 (match_operand:SI 2 "const48_operand" "I,I"))
681 (match_operand:SI 3 "some_operand" "%r,r"))
682 (match_operand:SI 4 "some_operand" "IOKL,r")))]
687 [(set (match_operand:SI 0 "register_operand" "")
688 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
689 (match_operand:SI 2 "const48_operand" ""))
690 (match_operand:SI 3 "register_operand" ""))
691 (match_operand:SI 4 "add_operand" "rIOKL")))]
694 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
695 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
699 [(set (match_operand:DI 0 "some_operand" "=r,&r")
702 (mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
703 (match_operand:SI 2 "const48_operand" "I,I"))
704 (match_operand:SI 3 "some_operand" "%r,r"))
705 (match_operand:SI 4 "some_operand" "IO,r"))))]
710 [(set (match_operand:DI 0 "register_operand" "")
713 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
714 (match_operand:SI 2 "const48_operand" ""))
715 (match_operand:SI 3 "register_operand" ""))
716 (match_operand:SI 4 "sext_add_operand" ""))))]
719 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
720 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
721 "operands[5] = gen_lowpart (SImode, operands[0]);")
724 [(set (match_operand:DI 0 "some_operand" "=r,&r")
725 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ,rJ")
726 (match_operand:DI 2 "const48_operand" "I,I"))
727 (match_operand:DI 3 "some_operand" "%r,r"))
728 (match_operand:DI 4 "some_operand" "IOKL,r")))]
733 [(set (match_operand:DI 0 "register_operand" "")
734 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
735 (match_operand:DI 2 "const48_operand" ""))
736 (match_operand:DI 3 "register_operand" ""))
737 (match_operand:DI 4 "add_operand" "")))]
740 (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
741 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
744 (define_insn "negsi2"
745 [(set (match_operand:SI 0 "register_operand" "=r")
746 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
751 [(set (match_operand:DI 0 "register_operand" "=r")
752 (sign_extend:DI (neg:SI
753 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
757 (define_insn "negdi2"
758 [(set (match_operand:DI 0 "register_operand" "=r")
759 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
763 (define_expand "subsi3"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
766 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
772 rtx op1 = gen_lowpart (DImode, operands[1]);
773 rtx op2 = gen_lowpart (DImode, operands[2]);
775 if (! cse_not_expected)
777 rtx tmp = gen_reg_rtx (DImode);
778 emit_insn (gen_subdi3 (tmp, op1, op2));
779 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
782 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
788 [(set (match_operand:SI 0 "register_operand" "=r")
789 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
790 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
795 [(set (match_operand:DI 0 "register_operand" "=r")
796 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
797 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
801 (define_insn "subdi3"
802 [(set (match_operand:DI 0 "register_operand" "=r")
803 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
804 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
809 [(set (match_operand:SI 0 "register_operand" "=r")
810 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
811 (match_operand:SI 2 "const48_operand" "I"))
812 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
817 [(set (match_operand:DI 0 "register_operand" "=r")
819 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
820 (match_operand:SI 2 "const48_operand" "I"))
821 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
826 [(set (match_operand:DI 0 "register_operand" "=r")
827 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
828 (match_operand:DI 2 "const48_operand" "I"))
829 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
833 (define_insn "mulsi3"
834 [(set (match_operand:SI 0 "register_operand" "=r")
835 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
836 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
839 [(set_attr "type" "imul")
840 (set_attr "opsize" "si")])
843 [(set (match_operand:DI 0 "register_operand" "=r")
845 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
846 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
849 [(set_attr "type" "imul")
850 (set_attr "opsize" "si")])
852 (define_insn "muldi3"
853 [(set (match_operand:DI 0 "register_operand" "=r")
854 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
855 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
858 [(set_attr "type" "imul")])
860 (define_insn "umuldi3_highpart"
861 [(set (match_operand:DI 0 "register_operand" "=r")
864 (mult:TI (zero_extend:TI
865 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
867 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
871 [(set_attr "type" "imul")
872 (set_attr "opsize" "udi")])
875 [(set (match_operand:DI 0 "register_operand" "=r")
878 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
879 (match_operand:TI 2 "cint8_operand" "I"))
883 [(set_attr "type" "imul")
884 (set_attr "opsize" "udi")])
886 ;; The divide and remainder operations always take their inputs from
887 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
889 ;; ??? Force sign-extension here because some versions of OSF/1 don't
890 ;; do the right thing if the inputs are not properly sign-extended.
891 ;; But Linux, for instance, does not have this problem. Is it worth
892 ;; the complication here to eliminate the sign extension?
893 ;; Interix/NT has the same sign-extension problem.
895 (define_expand "divsi3"
897 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
899 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
900 (parallel [(set (reg:DI 27)
901 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
902 (clobber (reg:DI 23))
903 (clobber (reg:DI 28))])
904 (set (match_operand:SI 0 "nonimmediate_operand" "")
905 (subreg:SI (reg:DI 27) 0))]
909 (define_expand "udivsi3"
911 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
913 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
914 (parallel [(set (reg:DI 27)
915 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
916 (clobber (reg:DI 23))
917 (clobber (reg:DI 28))])
918 (set (match_operand:SI 0 "nonimmediate_operand" "")
919 (subreg:SI (reg:DI 27) 0))]
923 (define_expand "modsi3"
925 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
927 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
928 (parallel [(set (reg:DI 27)
929 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
930 (clobber (reg:DI 23))
931 (clobber (reg:DI 28))])
932 (set (match_operand:SI 0 "nonimmediate_operand" "")
933 (subreg:SI (reg:DI 27) 0))]
937 (define_expand "umodsi3"
939 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
941 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
942 (parallel [(set (reg:DI 27)
943 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
944 (clobber (reg:DI 23))
945 (clobber (reg:DI 28))])
946 (set (match_operand:SI 0 "nonimmediate_operand" "")
947 (subreg:SI (reg:DI 27) 0))]
951 (define_expand "divdi3"
952 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
953 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
954 (parallel [(set (reg:DI 27)
957 (clobber (reg:DI 23))
958 (clobber (reg:DI 28))])
959 (set (match_operand:DI 0 "nonimmediate_operand" "")
964 (define_expand "udivdi3"
965 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
966 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
967 (parallel [(set (reg:DI 27)
970 (clobber (reg:DI 23))
971 (clobber (reg:DI 28))])
972 (set (match_operand:DI 0 "nonimmediate_operand" "")
977 (define_expand "moddi3"
978 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
979 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
980 (parallel [(set (reg:DI 27)
983 (clobber (reg:DI 23))
984 (clobber (reg:DI 28))])
985 (set (match_operand:DI 0 "nonimmediate_operand" "")
990 (define_expand "umoddi3"
991 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
992 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
993 (parallel [(set (reg:DI 27)
996 (clobber (reg:DI 23))
997 (clobber (reg:DI 28))])
998 (set (match_operand:DI 0 "nonimmediate_operand" "")
1003 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1004 ;; expanded by the assembler.
1007 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
1008 [(reg:DI 24) (reg:DI 25)])))
1009 (clobber (reg:DI 23))
1010 (clobber (reg:DI 28))]
1013 [(set_attr "type" "jsr")
1014 (set_attr "length" "8")])
1018 (match_operator:DI 1 "divmod_operator"
1019 [(reg:DI 24) (reg:DI 25)]))
1020 (clobber (reg:DI 23))
1021 (clobber (reg:DI 28))]
1024 [(set_attr "type" "jsr")
1025 (set_attr "length" "8")])
1027 ;; Next are the basic logical operations. These only exist in DImode.
1029 (define_insn "anddi3"
1030 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1031 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1032 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1038 [(set_attr "type" "ilog,ilog,shift")])
1040 ;; There are times when we can split an AND into two AND insns. This occurs
1041 ;; when we can first clear any bytes and then clear anything else. For
1042 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1043 ;; Only do this when running on 64-bit host since the computations are
1044 ;; too messy otherwise.
1047 [(set (match_operand:DI 0 "register_operand" "")
1048 (and:DI (match_operand:DI 1 "register_operand" "")
1049 (match_operand:DI 2 "const_int_operand" "")))]
1050 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1051 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1052 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1055 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1056 unsigned HOST_WIDE_INT mask2 = mask1;
1059 /* For each byte that isn't all zeros, make it all ones. */
1060 for (i = 0; i < 64; i += 8)
1061 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1062 mask1 |= (HOST_WIDE_INT) 0xff << i;
1064 /* Now turn on any bits we've just turned off. */
1067 operands[3] = GEN_INT (mask1);
1068 operands[4] = GEN_INT (mask2);
1071 (define_insn "zero_extendqihi2"
1072 [(set (match_operand:HI 0 "register_operand" "=r")
1073 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1076 [(set_attr "type" "ilog")])
1079 [(set (match_operand:SI 0 "register_operand" "=r,r")
1080 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1085 [(set_attr "type" "ilog,ild")])
1088 [(set (match_operand:SI 0 "register_operand" "=r")
1089 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1092 [(set_attr "type" "ilog")])
1094 (define_expand "zero_extendqisi2"
1095 [(set (match_operand:SI 0 "register_operand" "")
1096 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1101 [(set (match_operand:DI 0 "register_operand" "=r,r")
1102 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1107 [(set_attr "type" "ilog,ild")])
1110 [(set (match_operand:DI 0 "register_operand" "=r")
1111 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1114 [(set_attr "type" "ilog")])
1116 (define_expand "zero_extendqidi2"
1117 [(set (match_operand:DI 0 "register_operand" "")
1118 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1123 [(set (match_operand:SI 0 "register_operand" "=r,r")
1124 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1129 [(set_attr "type" "shift,ild")])
1132 [(set (match_operand:SI 0 "register_operand" "=r")
1133 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1136 [(set_attr "type" "shift")])
1138 (define_expand "zero_extendhisi2"
1139 [(set (match_operand:SI 0 "register_operand" "")
1140 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1145 [(set (match_operand:DI 0 "register_operand" "=r,r")
1146 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1151 [(set_attr "type" "shift,ild")])
1154 [(set (match_operand:DI 0 "register_operand" "=r")
1155 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1158 [(set_attr "type" "shift")])
1160 (define_expand "zero_extendhidi2"
1161 [(set (match_operand:DI 0 "register_operand" "")
1162 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1166 (define_insn "zero_extendsidi2"
1167 [(set (match_operand:DI 0 "register_operand" "=r")
1168 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1171 [(set_attr "type" "shift")])
1174 [(set (match_operand:DI 0 "register_operand" "=r")
1175 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1176 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1179 [(set_attr "type" "ilog")])
1181 (define_insn "iordi3"
1182 [(set (match_operand:DI 0 "register_operand" "=r,r")
1183 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1184 (match_operand:DI 2 "or_operand" "rI,N")))]
1189 [(set_attr "type" "ilog")])
1191 (define_insn "one_cmpldi2"
1192 [(set (match_operand:DI 0 "register_operand" "=r")
1193 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1196 [(set_attr "type" "ilog")])
1199 [(set (match_operand:DI 0 "register_operand" "=r")
1200 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1201 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1204 [(set_attr "type" "ilog")])
1206 (define_insn "xordi3"
1207 [(set (match_operand:DI 0 "register_operand" "=r,r")
1208 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1209 (match_operand:DI 2 "or_operand" "rI,N")))]
1214 [(set_attr "type" "ilog")])
1217 [(set (match_operand:DI 0 "register_operand" "=r")
1218 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1219 (match_operand:DI 2 "register_operand" "rI"))))]
1222 [(set_attr "type" "ilog")])
1224 ;; Handle the FFS insn iff we support CIX.
1226 ;; These didn't make it into EV6 pass 2 as planned. Instead they
1227 ;; cropped cttz/ctlz/ctpop from the old CIX and renamed it FIX for
1228 ;; "Square Root and Floating Point Convert Extension".
1230 ;; I'm assured that these insns will make it into EV67 (first pass
1231 ;; due Summer 1999), presumably with a new AMASK bit, and presumably
1232 ;; will still be named CIX.
1234 (define_expand "ffsdi2"
1236 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1238 (plus:DI (match_dup 2) (const_int 1)))
1239 (set (match_operand:DI 0 "register_operand" "")
1240 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1241 (const_int 0) (match_dup 3)))]
1245 operands[2] = gen_reg_rtx (DImode);
1246 operands[3] = gen_reg_rtx (DImode);
1250 [(set (match_operand:DI 0 "register_operand" "=r")
1251 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1254 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1255 ; reuse the existing type name.
1256 [(set_attr "type" "mvi")])
1258 ;; Next come the shifts and the various extract and insert operations.
1260 (define_insn "ashldi3"
1261 [(set (match_operand:DI 0 "register_operand" "=r,r")
1262 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1263 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1267 switch (which_alternative)
1270 if (operands[2] == const1_rtx)
1271 return \"addq %r1,%r1,%0\";
1273 return \"s%P2addq %r1,0,%0\";
1275 return \"sll %r1,%2,%0\";
1280 [(set_attr "type" "iadd,shift")])
1282 ;; ??? The following pattern is made by combine, but earlier phases
1283 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1284 ;; with this in a better way at some point.
1286 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1288 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1289 ;; (match_operand:DI 2 "const_int_operand" "P"))
1291 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1294 ;; if (operands[2] == const1_rtx)
1295 ;; return \"addl %r1,%r1,%0\";
1297 ;; return \"s%P2addl %r1,0,%0\";
1299 ;; [(set_attr "type" "iadd")])
1301 (define_insn "lshrdi3"
1302 [(set (match_operand:DI 0 "register_operand" "=r")
1303 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1304 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1307 [(set_attr "type" "shift")])
1309 (define_insn "ashrdi3"
1310 [(set (match_operand:DI 0 "register_operand" "=r")
1311 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1312 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1315 [(set_attr "type" "shift")])
1317 (define_expand "extendqihi2"
1319 (ashift:DI (match_operand:QI 1 "some_operand" "")
1321 (set (match_operand:HI 0 "register_operand" "")
1322 (ashiftrt:DI (match_dup 2)
1329 emit_insn (gen_extendqihi2x (operands[0],
1330 force_reg (QImode, operands[1])));
1334 /* If we have an unaligned MEM, extend to DImode (which we do
1335 specially) and then copy to the result. */
1336 if (unaligned_memory_operand (operands[1], HImode))
1338 rtx temp = gen_reg_rtx (DImode);
1340 emit_insn (gen_extendqidi2 (temp, operands[1]));
1341 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1345 operands[0] = gen_lowpart (DImode, operands[0]);
1346 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1347 operands[2] = gen_reg_rtx (DImode);
1350 (define_insn "extendqidi2x"
1351 [(set (match_operand:DI 0 "register_operand" "=r")
1352 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1355 [(set_attr "type" "shift")])
1357 (define_insn "extendhidi2x"
1358 [(set (match_operand:DI 0 "register_operand" "=r")
1359 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1362 [(set_attr "type" "shift")])
1364 (define_insn "extendqisi2x"
1365 [(set (match_operand:SI 0 "register_operand" "=r")
1366 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1369 [(set_attr "type" "shift")])
1371 (define_insn "extendhisi2x"
1372 [(set (match_operand:SI 0 "register_operand" "=r")
1373 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1376 [(set_attr "type" "shift")])
1378 (define_insn "extendqihi2x"
1379 [(set (match_operand:HI 0 "register_operand" "=r")
1380 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1383 [(set_attr "type" "shift")])
1385 (define_expand "extendqisi2"
1387 (ashift:DI (match_operand:QI 1 "some_operand" "")
1389 (set (match_operand:SI 0 "register_operand" "")
1390 (ashiftrt:DI (match_dup 2)
1397 emit_insn (gen_extendqisi2x (operands[0],
1398 force_reg (QImode, operands[1])));
1402 /* If we have an unaligned MEM, extend to a DImode form of
1403 the result (which we do specially). */
1404 if (unaligned_memory_operand (operands[1], QImode))
1406 rtx temp = gen_reg_rtx (DImode);
1408 emit_insn (gen_extendqidi2 (temp, operands[1]));
1409 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1413 operands[0] = gen_lowpart (DImode, operands[0]);
1414 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1415 operands[2] = gen_reg_rtx (DImode);
1418 (define_expand "extendqidi2"
1420 (ashift:DI (match_operand:QI 1 "some_operand" "")
1422 (set (match_operand:DI 0 "register_operand" "")
1423 (ashiftrt:DI (match_dup 2)
1430 emit_insn (gen_extendqidi2x (operands[0],
1431 force_reg (QImode, operands[1])));
1435 if (unaligned_memory_operand (operands[1], QImode))
1438 = gen_unaligned_extendqidi (operands[0],
1439 get_unaligned_address (operands[1], 1));
1441 alpha_set_memflags (seq, operands[1]);
1446 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1447 operands[2] = gen_reg_rtx (DImode);
1450 (define_expand "extendhisi2"
1452 (ashift:DI (match_operand:HI 1 "some_operand" "")
1454 (set (match_operand:SI 0 "register_operand" "")
1455 (ashiftrt:DI (match_dup 2)
1462 emit_insn (gen_extendhisi2x (operands[0],
1463 force_reg (HImode, operands[1])));
1467 /* If we have an unaligned MEM, extend to a DImode form of
1468 the result (which we do specially). */
1469 if (unaligned_memory_operand (operands[1], HImode))
1471 rtx temp = gen_reg_rtx (DImode);
1473 emit_insn (gen_extendhidi2 (temp, operands[1]));
1474 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1478 operands[0] = gen_lowpart (DImode, operands[0]);
1479 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1480 operands[2] = gen_reg_rtx (DImode);
1483 (define_expand "extendhidi2"
1485 (ashift:DI (match_operand:HI 1 "some_operand" "")
1487 (set (match_operand:DI 0 "register_operand" "")
1488 (ashiftrt:DI (match_dup 2)
1495 emit_insn (gen_extendhidi2x (operands[0],
1496 force_reg (HImode, operands[1])));
1500 if (unaligned_memory_operand (operands[1], HImode))
1503 = gen_unaligned_extendhidi (operands[0],
1504 get_unaligned_address (operands[1], 2));
1506 alpha_set_memflags (seq, operands[1]);
1511 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1512 operands[2] = gen_reg_rtx (DImode);
1515 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1516 ;; as a pattern saves one instruction. The code is similar to that for
1517 ;; the unaligned loads (see below).
1519 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1520 (define_expand "unaligned_extendqidi"
1521 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1523 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1526 (ashift:DI (match_dup 3)
1527 (minus:DI (const_int 64)
1529 (and:DI (match_dup 2) (const_int 7))
1531 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1532 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1535 { operands[2] = gen_reg_rtx (DImode);
1536 operands[3] = gen_reg_rtx (DImode);
1537 operands[4] = gen_reg_rtx (DImode);
1540 (define_expand "unaligned_extendhidi"
1541 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1543 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1546 (ashift:DI (match_dup 3)
1547 (minus:DI (const_int 64)
1549 (and:DI (match_dup 2) (const_int 7))
1551 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1552 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1555 { operands[2] = gen_reg_rtx (DImode);
1556 operands[3] = gen_reg_rtx (DImode);
1557 operands[4] = gen_reg_rtx (DImode);
1561 [(set (match_operand:DI 0 "register_operand" "=r")
1562 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1563 (match_operand:DI 2 "mode_width_operand" "n")
1564 (match_operand:DI 3 "mul8_operand" "I")))]
1566 "ext%M2l %r1,%s3,%0"
1567 [(set_attr "type" "shift")])
1569 (define_insn "extxl"
1570 [(set (match_operand:DI 0 "register_operand" "=r")
1571 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1572 (match_operand:DI 2 "mode_width_operand" "n")
1573 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1577 [(set_attr "type" "shift")])
1579 ;; Combine has some strange notion of preserving existing undefined behaviour
1580 ;; in shifts larger than a word size. So capture these patterns that it
1581 ;; should have turned into zero_extracts.
1584 [(set (match_operand:DI 0 "register_operand" "=r")
1585 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1586 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1588 (match_operand:DI 3 "mode_mask_operand" "n")))]
1591 [(set_attr "type" "shift")])
1594 [(set (match_operand:DI 0 "register_operand" "=r")
1595 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1596 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1600 [(set_attr "type" "shift")])
1602 (define_insn "extqh"
1603 [(set (match_operand:DI 0 "register_operand" "=r")
1605 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1606 (minus:DI (const_int 64)
1609 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1614 [(set_attr "type" "shift")])
1616 (define_insn "extlh"
1617 [(set (match_operand:DI 0 "register_operand" "=r")
1619 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1620 (const_int 2147483647))
1621 (minus:DI (const_int 64)
1624 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1629 [(set_attr "type" "shift")])
1631 (define_insn "extwh"
1632 [(set (match_operand:DI 0 "register_operand" "=r")
1634 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1636 (minus:DI (const_int 64)
1639 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1644 [(set_attr "type" "shift")])
1646 ;; This converts an extXl into an extXh with an appropriate adjustment
1647 ;; to the address calculation.
1650 ;; [(set (match_operand:DI 0 "register_operand" "")
1651 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1652 ;; (match_operand:DI 2 "mode_width_operand" "")
1653 ;; (ashift:DI (match_operand:DI 3 "" "")
1655 ;; (match_operand:DI 4 "const_int_operand" "")))
1656 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1657 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1658 ;; [(set (match_dup 5) (match_dup 6))
1659 ;; (set (match_dup 0)
1660 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1661 ;; (ashift:DI (plus:DI (match_dup 5)
1667 ;; operands[6] = plus_constant (operands[3],
1668 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1669 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1673 [(set (match_operand:DI 0 "register_operand" "=r")
1674 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1675 (match_operand:DI 2 "mul8_operand" "I")))]
1678 [(set_attr "type" "shift")])
1681 [(set (match_operand:DI 0 "register_operand" "=r")
1682 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1683 (match_operand:DI 2 "mul8_operand" "I")))]
1686 [(set_attr "type" "shift")])
1689 [(set (match_operand:DI 0 "register_operand" "=r")
1690 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1691 (match_operand:DI 2 "mul8_operand" "I")))]
1694 [(set_attr "type" "shift")])
1696 (define_insn "insbl"
1697 [(set (match_operand:DI 0 "register_operand" "=r")
1698 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1699 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1703 [(set_attr "type" "shift")])
1705 (define_insn "inswl"
1706 [(set (match_operand:DI 0 "register_operand" "=r")
1707 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1708 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1712 [(set_attr "type" "shift")])
1714 (define_insn "insll"
1715 [(set (match_operand:DI 0 "register_operand" "=r")
1716 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1717 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1721 [(set_attr "type" "shift")])
1723 (define_insn "insql"
1724 [(set (match_operand:DI 0 "register_operand" "=r")
1725 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1726 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1730 [(set_attr "type" "shift")])
1732 ;; Combine has this sometimes habit of moving the and outside of the
1733 ;; shift, making life more interesting.
1736 [(set (match_operand:DI 0 "register_operand" "=r")
1737 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1738 (match_operand:DI 2 "mul8_operand" "I"))
1739 (match_operand:DI 3 "immediate_operand" "i")))]
1740 "HOST_BITS_PER_WIDE_INT == 64
1741 && GET_CODE (operands[3]) == CONST_INT
1742 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1743 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1744 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1745 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1746 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1747 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1750 #if HOST_BITS_PER_WIDE_INT == 64
1751 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1752 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1753 return \"insbl %1,%s2,%0\";
1754 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1755 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1756 return \"inswl %1,%s2,%0\";
1757 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1758 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1759 return \"insll %1,%s2,%0\";
1763 [(set_attr "type" "shift")])
1765 ;; We do not include the insXh insns because they are complex to express
1766 ;; and it does not appear that we would ever want to generate them.
1768 ;; Since we need them for block moves, though, cop out and use unspec.
1770 (define_insn "insxh"
1771 [(set (match_operand:DI 0 "register_operand" "=r")
1772 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1773 (match_operand:DI 2 "mode_width_operand" "n")
1774 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1777 [(set_attr "type" "shift")])
1779 (define_insn "mskxl"
1780 [(set (match_operand:DI 0 "register_operand" "=r")
1781 (and:DI (not:DI (ashift:DI
1782 (match_operand:DI 2 "mode_mask_operand" "n")
1784 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1786 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1789 [(set_attr "type" "shift")])
1791 ;; We do not include the mskXh insns because it does not appear we would
1792 ;; ever generate one.
1794 ;; Again, we do for block moves and we use unspec again.
1796 (define_insn "mskxh"
1797 [(set (match_operand:DI 0 "register_operand" "=r")
1798 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1799 (match_operand:DI 2 "mode_width_operand" "n")
1800 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1803 [(set_attr "type" "shift")])
1805 ;; Floating-point operations. All the double-precision insns can extend
1806 ;; from single, so indicate that. The exception are the ones that simply
1807 ;; play with the sign bits; it's not clear what to do there.
1809 (define_insn "abssf2"
1810 [(set (match_operand:SF 0 "register_operand" "=f")
1811 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1814 [(set_attr "type" "fcpys")])
1816 (define_insn "absdf2"
1817 [(set (match_operand:DF 0 "register_operand" "=f")
1818 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1821 [(set_attr "type" "fcpys")])
1823 (define_insn "negsf2"
1824 [(set (match_operand:SF 0 "register_operand" "=f")
1825 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1828 [(set_attr "type" "fadd")])
1830 (define_insn "negdf2"
1831 [(set (match_operand:DF 0 "register_operand" "=f")
1832 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1835 [(set_attr "type" "fadd")])
1838 [(set (match_operand:SF 0 "register_operand" "=&f")
1839 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1840 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1841 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1842 "add%,%)%& %R1,%R2,%0"
1843 [(set_attr "type" "fadd")
1844 (set_attr "trap" "yes")])
1846 (define_insn "addsf3"
1847 [(set (match_operand:SF 0 "register_operand" "=f")
1848 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1849 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1851 "add%,%)%& %R1,%R2,%0"
1852 [(set_attr "type" "fadd")
1853 (set_attr "trap" "yes")])
1856 [(set (match_operand:DF 0 "register_operand" "=&f")
1857 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1858 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1859 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1860 "add%-%)%& %R1,%R2,%0"
1861 [(set_attr "type" "fadd")
1862 (set_attr "trap" "yes")])
1864 (define_insn "adddf3"
1865 [(set (match_operand:DF 0 "register_operand" "=f")
1866 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1867 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1869 "add%-%)%& %R1,%R2,%0"
1870 [(set_attr "type" "fadd")
1871 (set_attr "trap" "yes")])
1874 [(set (match_operand:DF 0 "register_operand" "=f")
1875 (plus:DF (float_extend:DF
1876 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1877 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1878 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1879 "add%-%)%& %R1,%R2,%0"
1880 [(set_attr "type" "fadd")
1881 (set_attr "trap" "yes")])
1884 [(set (match_operand:DF 0 "register_operand" "=f")
1885 (plus:DF (float_extend:DF
1886 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1888 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1889 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1890 "add%-%)%& %R1,%R2,%0"
1891 [(set_attr "type" "fadd")
1892 (set_attr "trap" "yes")])
1894 ;; Define conversion operators between DFmode and SImode, using the cvtql
1895 ;; instruction. To allow combine et al to do useful things, we keep the
1896 ;; operation as a unit until after reload, at which point we split the
1899 ;; Note that we (attempt to) only consider this optimization when the
1900 ;; ultimate destination is memory. If we will be doing further integer
1901 ;; processing, it is cheaper to do the truncation in the int regs.
1903 (define_insn "*cvtql"
1904 [(set (match_operand:SI 0 "register_operand" "=f")
1905 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1908 [(set_attr "type" "fadd")
1909 (set_attr "trap" "yes")])
1912 [(set (match_operand:SI 0 "memory_operand" "")
1913 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1914 (clobber (match_scratch:DI 2 ""))
1915 (clobber (match_scratch:SI 3 ""))]
1916 "TARGET_FP && reload_completed"
1917 [(set (match_dup 2) (fix:DI (match_dup 1)))
1918 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1919 (set (match_dup 0) (match_dup 3))]
1923 [(set (match_operand:SI 0 "memory_operand" "")
1924 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1925 (clobber (match_scratch:DI 2 ""))]
1926 "TARGET_FP && reload_completed"
1927 [(set (match_dup 2) (fix:DI (match_dup 1)))
1928 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1929 (set (match_dup 0) (match_dup 3))]
1930 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1931 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1934 [(set (match_operand:SI 0 "memory_operand" "=m")
1935 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1936 (clobber (match_scratch:DI 2 "=&f"))
1937 (clobber (match_scratch:SI 3 "=&f"))]
1938 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1940 [(set_attr "type" "fadd")
1941 (set_attr "trap" "yes")])
1944 [(set (match_operand:SI 0 "memory_operand" "=m")
1945 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1946 (clobber (match_scratch:DI 2 "=f"))]
1947 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1949 [(set_attr "type" "fadd")
1950 (set_attr "trap" "yes")])
1953 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
1954 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1955 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1957 [(set_attr "type" "fadd")
1958 (set_attr "trap" "yes")])
1960 (define_insn "fix_truncdfdi2"
1961 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
1962 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1965 [(set_attr "type" "fadd")
1966 (set_attr "trap" "yes")])
1968 ;; Likewise between SFmode and SImode.
1971 [(set (match_operand:SI 0 "memory_operand" "")
1972 (subreg:SI (fix:DI (float_extend:DF
1973 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1974 (clobber (match_scratch:DI 2 ""))
1975 (clobber (match_scratch:SI 3 ""))]
1976 "TARGET_FP && reload_completed"
1977 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1978 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1979 (set (match_dup 0) (match_dup 3))]
1983 [(set (match_operand:SI 0 "memory_operand" "")
1984 (subreg:SI (fix:DI (float_extend:DF
1985 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1986 (clobber (match_scratch:DI 2 ""))]
1987 "TARGET_FP && reload_completed"
1988 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1989 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1990 (set (match_dup 0) (match_dup 3))]
1991 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1992 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1995 [(set (match_operand:SI 0 "memory_operand" "=m")
1996 (subreg:SI (fix:DI (float_extend:DF
1997 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
1998 (clobber (match_scratch:DI 2 "=&f"))
1999 (clobber (match_scratch:SI 3 "=&f"))]
2000 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2002 [(set_attr "type" "fadd")
2003 (set_attr "trap" "yes")])
2006 [(set (match_operand:SI 0 "memory_operand" "=m")
2007 (subreg:SI (fix:DI (float_extend:DF
2008 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2009 (clobber (match_scratch:DI 2 "=f"))]
2010 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2012 [(set_attr "type" "fadd")
2013 (set_attr "trap" "yes")])
2016 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2017 (fix:DI (float_extend:DF
2018 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2019 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2021 [(set_attr "type" "fadd")
2022 (set_attr "trap" "yes")])
2024 (define_insn "fix_truncsfdi2"
2025 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2026 (fix:DI (float_extend:DF
2027 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2030 [(set_attr "type" "fadd")
2031 (set_attr "trap" "yes")])
2034 [(set (match_operand:SF 0 "register_operand" "=&f")
2035 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2036 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2038 [(set_attr "type" "fadd")
2039 (set_attr "trap" "yes")])
2041 (define_insn "floatdisf2"
2042 [(set (match_operand:SF 0 "register_operand" "=f")
2043 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2046 [(set_attr "type" "fadd")
2047 (set_attr "trap" "yes")])
2050 [(set (match_operand:DF 0 "register_operand" "=&f")
2051 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2052 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2054 [(set_attr "type" "fadd")
2055 (set_attr "trap" "yes")])
2057 (define_insn "floatdidf2"
2058 [(set (match_operand:DF 0 "register_operand" "=f")
2059 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2062 [(set_attr "type" "fadd")
2063 (set_attr "trap" "yes")])
2065 (define_expand "extendsfdf2"
2066 [(use (match_operand:DF 0 "register_operand" ""))
2067 (use (match_operand:SF 1 "nonimmediate_operand" ""))]
2071 if (alpha_fptm >= ALPHA_FPTM_SU)
2072 emit_insn (gen_extendsfdf2_tp (operands[0],
2073 force_reg (SFmode, operands[1])));
2075 emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
2080 (define_insn "extendsfdf2_tp"
2081 [(set (match_operand:DF 0 "register_operand" "=&f")
2082 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2083 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2085 [(set_attr "type" "fadd")
2086 (set_attr "trap" "yes")])
2088 (define_insn "extendsfdf2_no_tp"
2089 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2090 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2091 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2096 [(set_attr "type" "fcpys,fld,fst")
2097 (set_attr "trap" "yes")])
2100 [(set (match_operand:SF 0 "register_operand" "=&f")
2101 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2102 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2103 "cvt%-%,%)%& %R1,%0"
2104 [(set_attr "type" "fadd")
2105 (set_attr "trap" "yes")])
2107 (define_insn "truncdfsf2"
2108 [(set (match_operand:SF 0 "register_operand" "=f")
2109 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2111 "cvt%-%,%)%& %R1,%0"
2112 [(set_attr "type" "fadd")
2113 (set_attr "trap" "yes")])
2116 [(set (match_operand:SF 0 "register_operand" "=&f")
2117 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2118 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2119 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2120 "div%,%)%& %R1,%R2,%0"
2121 [(set_attr "type" "fdiv")
2122 (set_attr "opsize" "si")
2123 (set_attr "trap" "yes")])
2125 (define_insn "divsf3"
2126 [(set (match_operand:SF 0 "register_operand" "=f")
2127 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2128 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2130 "div%,%)%& %R1,%R2,%0"
2131 [(set_attr "type" "fdiv")
2132 (set_attr "opsize" "si")
2133 (set_attr "trap" "yes")])
2136 [(set (match_operand:DF 0 "register_operand" "=&f")
2137 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2138 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2139 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2140 "div%-%)%& %R1,%R2,%0"
2141 [(set_attr "type" "fdiv")
2142 (set_attr "trap" "yes")])
2144 (define_insn "divdf3"
2145 [(set (match_operand:DF 0 "register_operand" "=f")
2146 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2147 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2149 "div%-%)%& %R1,%R2,%0"
2150 [(set_attr "type" "fdiv")
2151 (set_attr "trap" "yes")])
2154 [(set (match_operand:DF 0 "register_operand" "=f")
2155 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2156 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2157 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2158 "div%-%)%& %R1,%R2,%0"
2159 [(set_attr "type" "fdiv")
2160 (set_attr "trap" "yes")])
2163 [(set (match_operand:DF 0 "register_operand" "=f")
2164 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2166 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2167 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2168 "div%-%)%& %R1,%R2,%0"
2169 [(set_attr "type" "fdiv")
2170 (set_attr "trap" "yes")])
2173 [(set (match_operand:DF 0 "register_operand" "=f")
2174 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2175 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2176 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2177 "div%-%)%& %R1,%R2,%0"
2178 [(set_attr "type" "fdiv")
2179 (set_attr "trap" "yes")])
2182 [(set (match_operand:SF 0 "register_operand" "=&f")
2183 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2184 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2185 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2186 "mul%,%)%& %R1,%R2,%0"
2187 [(set_attr "type" "fmul")
2188 (set_attr "trap" "yes")])
2190 (define_insn "mulsf3"
2191 [(set (match_operand:SF 0 "register_operand" "=f")
2192 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2193 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2195 "mul%,%)%& %R1,%R2,%0"
2196 [(set_attr "type" "fmul")
2197 (set_attr "trap" "yes")])
2200 [(set (match_operand:DF 0 "register_operand" "=&f")
2201 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2202 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2203 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2204 "mul%-%)%& %R1,%R2,%0"
2205 [(set_attr "type" "fmul")
2206 (set_attr "trap" "yes")])
2208 (define_insn "muldf3"
2209 [(set (match_operand:DF 0 "register_operand" "=f")
2210 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2211 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2213 "mul%-%)%& %R1,%R2,%0"
2214 [(set_attr "type" "fmul")
2215 (set_attr "trap" "yes")])
2218 [(set (match_operand:DF 0 "register_operand" "=f")
2219 (mult:DF (float_extend:DF
2220 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2221 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2222 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2223 "mul%-%)%& %R1,%R2,%0"
2224 [(set_attr "type" "fmul")
2225 (set_attr "trap" "yes")])
2228 [(set (match_operand:DF 0 "register_operand" "=f")
2229 (mult:DF (float_extend:DF
2230 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2232 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2233 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2234 "mul%-%)%& %R1,%R2,%0"
2235 [(set_attr "type" "fmul")
2236 (set_attr "trap" "yes")])
2239 [(set (match_operand:SF 0 "register_operand" "=&f")
2240 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2241 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2242 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2243 "sub%,%)%& %R1,%R2,%0"
2244 [(set_attr "type" "fadd")
2245 (set_attr "trap" "yes")])
2247 (define_insn "subsf3"
2248 [(set (match_operand:SF 0 "register_operand" "=f")
2249 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2250 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2252 "sub%,%)%& %R1,%R2,%0"
2253 [(set_attr "type" "fadd")
2254 (set_attr "trap" "yes")])
2257 [(set (match_operand:DF 0 "register_operand" "=&f")
2258 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2259 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2260 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2261 "sub%-%)%& %R1,%R2,%0"
2262 [(set_attr "type" "fadd")
2263 (set_attr "trap" "yes")])
2265 (define_insn "subdf3"
2266 [(set (match_operand:DF 0 "register_operand" "=f")
2267 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2268 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2270 "sub%-%)%& %R1,%R2,%0"
2271 [(set_attr "type" "fadd")
2272 (set_attr "trap" "yes")])
2275 [(set (match_operand:DF 0 "register_operand" "=f")
2276 (minus:DF (float_extend:DF
2277 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2278 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2279 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2280 "sub%-%)%& %R1,%R2,%0"
2281 [(set_attr "type" "fadd")
2282 (set_attr "trap" "yes")])
2285 [(set (match_operand:DF 0 "register_operand" "=f")
2286 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2288 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2289 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2290 "sub%-%)%& %R1,%R2,%0"
2291 [(set_attr "type" "fadd")
2292 (set_attr "trap" "yes")])
2295 [(set (match_operand:DF 0 "register_operand" "=f")
2296 (minus:DF (float_extend:DF
2297 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2299 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2300 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2301 "sub%-%)%& %R1,%R2,%0"
2302 [(set_attr "type" "fadd")
2303 (set_attr "trap" "yes")])
2306 [(set (match_operand:SF 0 "register_operand" "=&f")
2307 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2308 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2310 [(set_attr "type" "fsqrt")
2311 (set_attr "opsize" "si")
2312 (set_attr "trap" "yes")])
2314 (define_insn "sqrtsf2"
2315 [(set (match_operand:SF 0 "register_operand" "=f")
2316 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2317 "TARGET_FP && TARGET_FIX"
2319 [(set_attr "type" "fsqrt")
2320 (set_attr "opsize" "si")
2321 (set_attr "trap" "yes")])
2324 [(set (match_operand:DF 0 "register_operand" "=&f")
2325 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2326 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2328 [(set_attr "type" "fsqrt")
2329 (set_attr "trap" "yes")])
2331 (define_insn "sqrtdf2"
2332 [(set (match_operand:DF 0 "register_operand" "=f")
2333 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2334 "TARGET_FP && TARGET_FIX"
2336 [(set_attr "type" "fsqrt")
2337 (set_attr "trap" "yes")])
2339 ;; Next are all the integer comparisons, and conditional moves and branches
2340 ;; and some of the related define_expand's and define_split's.
2343 [(set (match_operand:DI 0 "register_operand" "=r")
2344 (match_operator:DI 1 "alpha_comparison_operator"
2345 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2346 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2349 [(set_attr "type" "icmp")])
2352 [(set (match_operand:DI 0 "register_operand" "=r")
2353 (match_operator:DI 1 "alpha_swapped_comparison_operator"
2354 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2355 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2358 [(set_attr "type" "icmp")])
2360 ;; This pattern exists so conditional moves of SImode values are handled.
2361 ;; Comparisons are still done in DImode though.
2364 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2366 (match_operator 2 "signed_comparison_operator"
2367 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2368 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2369 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2370 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2371 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2377 [(set_attr "type" "icmov")])
2380 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2382 (match_operator 2 "signed_comparison_operator"
2383 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2384 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2385 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2386 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2387 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2393 [(set_attr "type" "icmov")])
2396 [(set (match_operand:DI 0 "register_operand" "=r,r")
2398 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2402 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2403 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2408 [(set_attr "type" "icmov")])
2411 [(set (match_operand:DI 0 "register_operand" "=r,r")
2413 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2417 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2418 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2423 [(set_attr "type" "icmov")])
2425 ;; For ABS, we have two choices, depending on whether the input and output
2426 ;; registers are the same or not.
2427 (define_expand "absdi2"
2428 [(set (match_operand:DI 0 "register_operand" "")
2429 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2432 { if (rtx_equal_p (operands[0], operands[1]))
2433 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2435 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2440 (define_expand "absdi2_same"
2441 [(set (match_operand:DI 1 "register_operand" "")
2442 (neg:DI (match_operand:DI 0 "register_operand" "")))
2444 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2450 (define_expand "absdi2_diff"
2451 [(set (match_operand:DI 0 "register_operand" "")
2452 (neg:DI (match_operand:DI 1 "register_operand" "")))
2454 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2461 [(set (match_operand:DI 0 "register_operand" "")
2462 (abs:DI (match_dup 0)))
2463 (clobber (match_operand:DI 2 "register_operand" ""))]
2465 [(set (match_dup 1) (neg:DI (match_dup 0)))
2466 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2467 (match_dup 0) (match_dup 1)))]
2471 [(set (match_operand:DI 0 "register_operand" "")
2472 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2473 "! rtx_equal_p (operands[0], operands[1])"
2474 [(set (match_dup 0) (neg:DI (match_dup 1)))
2475 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2476 (match_dup 0) (match_dup 1)))]
2480 [(set (match_operand:DI 0 "register_operand" "")
2481 (neg:DI (abs:DI (match_dup 0))))
2482 (clobber (match_operand:DI 2 "register_operand" ""))]
2484 [(set (match_dup 1) (neg:DI (match_dup 0)))
2485 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2486 (match_dup 0) (match_dup 1)))]
2490 [(set (match_operand:DI 0 "register_operand" "")
2491 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2492 "! rtx_equal_p (operands[0], operands[1])"
2493 [(set (match_dup 0) (neg:DI (match_dup 1)))
2494 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2495 (match_dup 0) (match_dup 1)))]
2498 (define_insn "sminqi3"
2499 [(set (match_operand:QI 0 "register_operand" "=r")
2500 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2501 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2504 [(set_attr "type" "mvi")])
2506 (define_insn "uminqi3"
2507 [(set (match_operand:QI 0 "register_operand" "=r")
2508 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2509 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2512 [(set_attr "type" "mvi")])
2514 (define_insn "smaxqi3"
2515 [(set (match_operand:QI 0 "register_operand" "=r")
2516 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2517 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2520 [(set_attr "type" "mvi")])
2522 (define_insn "umaxqi3"
2523 [(set (match_operand:QI 0 "register_operand" "=r")
2524 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2525 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2528 [(set_attr "type" "mvi")])
2530 (define_insn "sminhi3"
2531 [(set (match_operand:HI 0 "register_operand" "=r")
2532 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2533 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2536 [(set_attr "type" "mvi")])
2538 (define_insn "uminhi3"
2539 [(set (match_operand:HI 0 "register_operand" "=r")
2540 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2541 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2544 [(set_attr "type" "mvi")])
2546 (define_insn "smaxhi3"
2547 [(set (match_operand:HI 0 "register_operand" "=r")
2548 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2549 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2552 [(set_attr "type" "mvi")])
2554 (define_insn "umaxhi3"
2555 [(set (match_operand:HI 0 "register_operand" "=r")
2556 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2557 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2560 [(set_attr "type" "shift")])
2562 (define_expand "smaxdi3"
2564 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2565 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2566 (set (match_operand:DI 0 "register_operand" "")
2567 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2568 (match_dup 1) (match_dup 2)))]
2571 { operands[3] = gen_reg_rtx (DImode);
2575 [(set (match_operand:DI 0 "register_operand" "")
2576 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2577 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2578 (clobber (match_operand:DI 3 "register_operand" ""))]
2579 "operands[2] != const0_rtx"
2580 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2581 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2582 (match_dup 1) (match_dup 2)))]
2586 [(set (match_operand:DI 0 "register_operand" "=r")
2587 (smax:DI (match_operand:DI 1 "register_operand" "0")
2591 [(set_attr "type" "icmov")])
2593 (define_expand "smindi3"
2595 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2596 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2597 (set (match_operand:DI 0 "register_operand" "")
2598 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2599 (match_dup 1) (match_dup 2)))]
2602 { operands[3] = gen_reg_rtx (DImode);
2606 [(set (match_operand:DI 0 "register_operand" "")
2607 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2608 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2609 (clobber (match_operand:DI 3 "register_operand" ""))]
2610 "operands[2] != const0_rtx"
2611 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2612 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2613 (match_dup 1) (match_dup 2)))]
2617 [(set (match_operand:DI 0 "register_operand" "=r")
2618 (smin:DI (match_operand:DI 1 "register_operand" "0")
2622 [(set_attr "type" "icmov")])
2624 (define_expand "umaxdi3"
2626 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2627 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2628 (set (match_operand:DI 0 "register_operand" "")
2629 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2630 (match_dup 1) (match_dup 2)))]
2633 { operands[3] = gen_reg_rtx (DImode);
2637 [(set (match_operand:DI 0 "register_operand" "")
2638 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2639 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2640 (clobber (match_operand:DI 3 "register_operand" ""))]
2641 "operands[2] != const0_rtx"
2642 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2643 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2644 (match_dup 1) (match_dup 2)))]
2647 (define_expand "umindi3"
2649 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2650 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2651 (set (match_operand:DI 0 "register_operand" "")
2652 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2653 (match_dup 1) (match_dup 2)))]
2656 { operands[3] = gen_reg_rtx (DImode);
2660 [(set (match_operand:DI 0 "register_operand" "")
2661 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2662 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2663 (clobber (match_operand:DI 3 "register_operand" ""))]
2664 "operands[2] != const0_rtx"
2665 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2666 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2667 (match_dup 1) (match_dup 2)))]
2673 (match_operator 1 "signed_comparison_operator"
2674 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2676 (label_ref (match_operand 0 "" ""))
2680 [(set_attr "type" "ibr")])
2685 (match_operator 1 "signed_comparison_operator"
2687 (match_operand:DI 2 "register_operand" "r")])
2688 (label_ref (match_operand 0 "" ""))
2692 [(set_attr "type" "ibr")])
2697 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2701 (label_ref (match_operand 0 "" ""))
2705 [(set_attr "type" "ibr")])
2710 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2714 (label_ref (match_operand 0 "" ""))
2718 [(set_attr "type" "ibr")])
2724 (match_operator 1 "comparison_operator"
2725 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2727 (match_operand:DI 3 "const_int_operand" ""))
2729 (label_ref (match_operand 0 "" ""))
2731 (clobber (match_operand:DI 4 "register_operand" ""))])]
2732 "INTVAL (operands[3]) != 0"
2734 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2736 (if_then_else (match_op_dup 1
2737 [(zero_extract:DI (match_dup 4)
2741 (label_ref (match_dup 0))
2745 ;; The following are the corresponding floating-point insns. Recall
2746 ;; we need to have variants that expand the arguments from SF mode
2750 [(set (match_operand:DF 0 "register_operand" "=&f")
2751 (match_operator:DF 1 "alpha_comparison_operator"
2752 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2753 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2754 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2755 "cmp%-%C1%' %R2,%R3,%0"
2756 [(set_attr "type" "fadd")
2757 (set_attr "trap" "yes")])
2760 [(set (match_operand:DF 0 "register_operand" "=f")
2761 (match_operator:DF 1 "alpha_comparison_operator"
2762 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2763 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2764 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2765 "cmp%-%C1%' %R2,%R3,%0"
2766 [(set_attr "type" "fadd")
2767 (set_attr "trap" "yes")])
2770 [(set (match_operand:DF 0 "register_operand" "=&f")
2771 (match_operator:DF 1 "alpha_comparison_operator"
2773 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2774 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2775 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2776 "cmp%-%C1%' %R2,%R3,%0"
2777 [(set_attr "type" "fadd")
2778 (set_attr "trap" "yes")])
2781 [(set (match_operand:DF 0 "register_operand" "=f")
2782 (match_operator:DF 1 "alpha_comparison_operator"
2784 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2785 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2786 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2787 "cmp%-%C1%' %R2,%R3,%0"
2788 [(set_attr "type" "fadd")
2789 (set_attr "trap" "yes")])
2792 [(set (match_operand:DF 0 "register_operand" "=&f")
2793 (match_operator:DF 1 "alpha_comparison_operator"
2794 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2796 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2797 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2798 "cmp%-%C1%' %R2,%R3,%0"
2799 [(set_attr "type" "fadd")
2800 (set_attr "trap" "yes")])
2803 [(set (match_operand:DF 0 "register_operand" "=f")
2804 (match_operator:DF 1 "alpha_comparison_operator"
2805 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2807 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2808 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2809 "cmp%-%C1%' %R2,%R3,%0"
2810 [(set_attr "type" "fadd")
2811 (set_attr "trap" "yes")])
2814 [(set (match_operand:DF 0 "register_operand" "=&f")
2815 (match_operator:DF 1 "alpha_comparison_operator"
2817 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2819 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2820 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2821 "cmp%-%C1%' %R2,%R3,%0"
2822 [(set_attr "type" "fadd")
2823 (set_attr "trap" "yes")])
2826 [(set (match_operand:DF 0 "register_operand" "=f")
2827 (match_operator:DF 1 "alpha_comparison_operator"
2829 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2831 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2832 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2833 "cmp%-%C1%' %R2,%R3,%0"
2834 [(set_attr "type" "fadd")
2835 (set_attr "trap" "yes")])
2838 [(set (match_operand:DF 0 "register_operand" "=f,f")
2840 (match_operator 3 "signed_comparison_operator"
2841 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2842 (match_operand:DF 2 "fp0_operand" "G,G")])
2843 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2844 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2848 fcmov%D3 %R4,%R5,%0"
2849 [(set_attr "type" "fcmov")])
2852 [(set (match_operand:SF 0 "register_operand" "=f,f")
2854 (match_operator 3 "signed_comparison_operator"
2855 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2856 (match_operand:DF 2 "fp0_operand" "G,G")])
2857 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2858 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2862 fcmov%D3 %R4,%R5,%0"
2863 [(set_attr "type" "fcmov")])
2866 [(set (match_operand:DF 0 "register_operand" "=f,f")
2868 (match_operator 3 "signed_comparison_operator"
2869 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2870 (match_operand:DF 2 "fp0_operand" "G,G")])
2871 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2872 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2876 fcmov%D3 %R4,%R5,%0"
2877 [(set_attr "type" "fcmov")])
2880 [(set (match_operand:DF 0 "register_operand" "=f,f")
2882 (match_operator 3 "signed_comparison_operator"
2884 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2885 (match_operand:DF 2 "fp0_operand" "G,G")])
2886 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2887 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2891 fcmov%D3 %R4,%R5,%0"
2892 [(set_attr "type" "fcmov")])
2895 [(set (match_operand:SF 0 "register_operand" "=f,f")
2897 (match_operator 3 "signed_comparison_operator"
2899 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2900 (match_operand:DF 2 "fp0_operand" "G,G")])
2901 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2902 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2906 fcmov%D3 %R4,%R5,%0"
2907 [(set_attr "type" "fcmov")])
2910 [(set (match_operand:DF 0 "register_operand" "=f,f")
2912 (match_operator 3 "signed_comparison_operator"
2914 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2915 (match_operand:DF 2 "fp0_operand" "G,G")])
2916 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2917 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2921 fcmov%D3 %R4,%R5,%0"
2922 [(set_attr "type" "fcmov")])
2924 (define_expand "maxdf3"
2926 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2927 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2928 (set (match_operand:DF 0 "register_operand" "")
2929 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
2930 (match_dup 1) (match_dup 2)))]
2933 { operands[3] = gen_reg_rtx (DFmode);
2934 operands[4] = CONST0_RTX (DFmode);
2937 (define_expand "mindf3"
2939 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2940 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2941 (set (match_operand:DF 0 "register_operand" "")
2942 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
2943 (match_dup 1) (match_dup 2)))]
2946 { operands[3] = gen_reg_rtx (DFmode);
2947 operands[4] = CONST0_RTX (DFmode);
2950 (define_expand "maxsf3"
2952 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2953 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2954 (set (match_operand:SF 0 "register_operand" "")
2955 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
2956 (match_dup 1) (match_dup 2)))]
2959 { operands[3] = gen_reg_rtx (DFmode);
2960 operands[4] = CONST0_RTX (DFmode);
2963 (define_expand "minsf3"
2965 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2966 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2967 (set (match_operand:SF 0 "register_operand" "")
2968 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
2969 (match_dup 1) (match_dup 2)))]
2972 { operands[3] = gen_reg_rtx (DFmode);
2973 operands[4] = CONST0_RTX (DFmode);
2979 (match_operator 1 "signed_comparison_operator"
2980 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2981 (match_operand:DF 3 "fp0_operand" "G")])
2982 (label_ref (match_operand 0 "" ""))
2986 [(set_attr "type" "fbr")])
2991 (match_operator 1 "signed_comparison_operator"
2993 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2994 (match_operand:DF 3 "fp0_operand" "G")])
2995 (label_ref (match_operand 0 "" ""))
2999 [(set_attr "type" "fbr")])
3001 ;; These are the main define_expand's used to make conditional branches
3004 (define_expand "cmpdf"
3005 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3006 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3010 alpha_compare.op0 = operands[0];
3011 alpha_compare.op1 = operands[1];
3012 alpha_compare.fp_p = 1;
3016 (define_expand "cmpdi"
3017 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3018 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3022 alpha_compare.op0 = operands[0];
3023 alpha_compare.op1 = operands[1];
3024 alpha_compare.fp_p = 0;
3028 (define_expand "beq"
3030 (if_then_else (match_dup 1)
3031 (label_ref (match_operand 0 "" ""))
3034 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3036 (define_expand "bne"
3038 (if_then_else (match_dup 1)
3039 (label_ref (match_operand 0 "" ""))
3042 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3044 (define_expand "blt"
3046 (if_then_else (match_dup 1)
3047 (label_ref (match_operand 0 "" ""))
3050 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3052 (define_expand "ble"
3054 (if_then_else (match_dup 1)
3055 (label_ref (match_operand 0 "" ""))
3058 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3060 (define_expand "bgt"
3062 (if_then_else (match_dup 1)
3063 (label_ref (match_operand 0 "" ""))
3066 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3068 (define_expand "bge"
3070 (if_then_else (match_dup 1)
3071 (label_ref (match_operand 0 "" ""))
3074 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3076 (define_expand "bltu"
3078 (if_then_else (match_dup 1)
3079 (label_ref (match_operand 0 "" ""))
3082 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3084 (define_expand "bleu"
3086 (if_then_else (match_dup 1)
3087 (label_ref (match_operand 0 "" ""))
3090 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3092 (define_expand "bgtu"
3094 (if_then_else (match_dup 1)
3095 (label_ref (match_operand 0 "" ""))
3098 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3100 (define_expand "bgeu"
3102 (if_then_else (match_dup 1)
3103 (label_ref (match_operand 0 "" ""))
3106 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3108 (define_expand "seq"
3109 [(set (match_operand:DI 0 "register_operand" "")
3114 if (alpha_compare.fp_p)
3117 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3118 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3121 (define_expand "sne"
3122 [(set (match_operand:DI 0 "register_operand" "")
3124 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3128 if (alpha_compare.fp_p)
3131 if (alpha_compare.op1 == const0_rtx)
3133 emit_insn (gen_sgtu (operands[0]));
3137 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3138 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3141 (define_expand "slt"
3142 [(set (match_operand:DI 0 "register_operand" "")
3147 if (alpha_compare.fp_p)
3150 operands[1] = gen_rtx_LT (DImode, alpha_compare.op0, alpha_compare.op1);
3151 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3154 (define_expand "sle"
3155 [(set (match_operand:DI 0 "register_operand" "")
3160 if (alpha_compare.fp_p)
3163 operands[1] = gen_rtx_LE (DImode, alpha_compare.op0, alpha_compare.op1);
3164 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3167 (define_expand "sgt"
3168 [(set (match_operand:DI 0 "register_operand" "")
3173 if (alpha_compare.fp_p)
3176 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare.op1),
3178 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3181 (define_expand "sge"
3182 [(set (match_operand:DI 0 "register_operand" "")
3187 if (alpha_compare.fp_p)
3190 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare.op1),
3192 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3195 (define_expand "sltu"
3196 [(set (match_operand:DI 0 "register_operand" "")
3201 if (alpha_compare.fp_p)
3204 operands[1] = gen_rtx_LTU (DImode, alpha_compare.op0, alpha_compare.op1);
3205 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3208 (define_expand "sleu"
3209 [(set (match_operand:DI 0 "register_operand" "")
3214 if (alpha_compare.fp_p)
3217 operands[1] = gen_rtx_LEU (DImode, alpha_compare.op0, alpha_compare.op1);
3218 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3221 (define_expand "sgtu"
3222 [(set (match_operand:DI 0 "register_operand" "")
3227 if (alpha_compare.fp_p)
3230 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare.op1),
3232 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3235 (define_expand "sgeu"
3236 [(set (match_operand:DI 0 "register_operand" "")
3241 if (alpha_compare.fp_p)
3244 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare.op1),
3246 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3249 ;; These are the main define_expand's used to make conditional moves.
3251 (define_expand "movsicc"
3252 [(set (match_operand:SI 0 "register_operand" "")
3253 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3254 (match_operand:SI 2 "reg_or_8bit_operand" "")
3255 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3259 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3263 (define_expand "movdicc"
3264 [(set (match_operand:DI 0 "register_operand" "")
3265 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3266 (match_operand:DI 2 "reg_or_8bit_operand" "")
3267 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3271 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3275 (define_expand "movsfcc"
3276 [(set (match_operand:SF 0 "register_operand" "")
3277 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3278 (match_operand:SF 2 "reg_or_8bit_operand" "")
3279 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3283 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3287 (define_expand "movdfcc"
3288 [(set (match_operand:DF 0 "register_operand" "")
3289 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3290 (match_operand:DF 2 "reg_or_8bit_operand" "")
3291 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3295 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3299 ;; These define_split definitions are used in cases when comparisons have
3300 ;; not be stated in the correct way and we need to reverse the second
3301 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3302 ;; comparison that tests the result being reversed. We have one define_split
3303 ;; for each use of a comparison. They do not match valid insns and need
3304 ;; not generate valid insns.
3306 ;; We can also handle equality comparisons (and inequality comparisons in
3307 ;; cases where the resulting add cannot overflow) by doing an add followed by
3308 ;; a comparison with zero. This is faster since the addition takes one
3309 ;; less cycle than a compare when feeding into a conditional move.
3310 ;; For this case, we also have an SImode pattern since we can merge the add
3311 ;; and sign extend and the order doesn't matter.
3313 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3314 ;; operation could have been generated.
3317 [(set (match_operand:DI 0 "register_operand" "")
3319 (match_operator 1 "comparison_operator"
3320 [(match_operand:DI 2 "reg_or_0_operand" "")
3321 (match_operand:DI 3 "reg_or_cint_operand" "")])
3322 (match_operand:DI 4 "reg_or_cint_operand" "")
3323 (match_operand:DI 5 "reg_or_cint_operand" "")))
3324 (clobber (match_operand:DI 6 "register_operand" ""))]
3325 "operands[3] != const0_rtx"
3326 [(set (match_dup 6) (match_dup 7))
3328 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3330 { enum rtx_code code = GET_CODE (operands[1]);
3331 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3333 /* If we are comparing for equality with a constant and that constant
3334 appears in the arm when the register equals the constant, use the
3335 register since that is more likely to match (and to produce better code
3338 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3339 && rtx_equal_p (operands[4], operands[3]))
3340 operands[4] = operands[2];
3342 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3343 && rtx_equal_p (operands[5], operands[3]))
3344 operands[5] = operands[2];
3346 if (code == NE || code == EQ
3347 || (extended_count (operands[2], DImode, unsignedp) >= 1
3348 && extended_count (operands[3], DImode, unsignedp) >= 1))
3350 if (GET_CODE (operands[3]) == CONST_INT)
3351 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3352 GEN_INT (- INTVAL (operands[3])));
3354 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3356 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3359 else if (code == EQ || code == LE || code == LT
3360 || code == LEU || code == LTU)
3362 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3363 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3367 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3368 operands[2], operands[3]);
3369 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3374 [(set (match_operand:DI 0 "register_operand" "")
3376 (match_operator 1 "comparison_operator"
3377 [(match_operand:SI 2 "reg_or_0_operand" "")
3378 (match_operand:SI 3 "reg_or_cint_operand" "")])
3379 (match_operand:DI 4 "reg_or_8bit_operand" "")
3380 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3381 (clobber (match_operand:DI 6 "register_operand" ""))]
3382 "operands[3] != const0_rtx
3383 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3384 [(set (match_dup 6) (match_dup 7))
3386 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3388 { enum rtx_code code = GET_CODE (operands[1]);
3389 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3392 if ((code != NE && code != EQ
3393 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3394 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3397 if (GET_CODE (operands[3]) == CONST_INT)
3398 tem = gen_rtx_PLUS (SImode, operands[2],
3399 GEN_INT (- INTVAL (operands[3])));
3401 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3403 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3404 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3405 operands[6], const0_rtx);
3411 (match_operator 1 "comparison_operator"
3412 [(match_operand:DI 2 "reg_or_0_operand" "")
3413 (match_operand:DI 3 "reg_or_cint_operand" "")])
3414 (label_ref (match_operand 0 "" ""))
3416 (clobber (match_operand:DI 4 "register_operand" ""))]
3417 "operands[3] != const0_rtx"
3418 [(set (match_dup 4) (match_dup 5))
3419 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3421 { enum rtx_code code = GET_CODE (operands[1]);
3422 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3424 if (code == NE || code == EQ
3425 || (extended_count (operands[2], DImode, unsignedp) >= 1
3426 && extended_count (operands[3], DImode, unsignedp) >= 1))
3428 if (GET_CODE (operands[3]) == CONST_INT)
3429 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3430 GEN_INT (- INTVAL (operands[3])));
3432 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3434 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3437 else if (code == EQ || code == LE || code == LT
3438 || code == LEU || code == LTU)
3440 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3441 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3445 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3446 operands[2], operands[3]);
3447 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3454 (match_operator 1 "comparison_operator"
3455 [(match_operand:SI 2 "reg_or_0_operand" "")
3456 (match_operand:SI 3 "const_int_operand" "")])
3457 (label_ref (match_operand 0 "" ""))
3459 (clobber (match_operand:DI 4 "register_operand" ""))]
3460 "operands[3] != const0_rtx
3461 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3462 [(set (match_dup 4) (match_dup 5))
3463 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3467 if (GET_CODE (operands[3]) == CONST_INT)
3468 tem = gen_rtx_PLUS (SImode, operands[2],
3469 GEN_INT (- INTVAL (operands[3])));
3471 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3473 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3474 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3475 operands[4], const0_rtx);
3478 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3479 ;; This eliminates one, and sometimes two, insns when the AND can be done
3482 [(set (match_operand:DI 0 "register_operand" "")
3483 (match_operator 1 "comparison_operator"
3484 [(match_operand:DI 2 "register_operand" "")
3485 (match_operand:DI 3 "const_int_operand" "")]))
3486 (clobber (match_operand:DI 4 "register_operand" ""))]
3487 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3488 && (GET_CODE (operands[1]) == GTU
3489 || GET_CODE (operands[1]) == LEU
3490 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3491 && extended_count (operands[2], DImode, 1) > 0))"
3492 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3493 (set (match_dup 0) (match_dup 6))]
3496 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3497 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3498 || GET_CODE (operands[1]) == GT)
3500 DImode, operands[4], const0_rtx);
3503 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3504 ;; work differently, so we have different patterns for each.
3506 (define_expand "call"
3507 [(use (match_operand:DI 0 "" ""))
3508 (use (match_operand 1 "" ""))
3509 (use (match_operand 2 "" ""))
3510 (use (match_operand 3 "" ""))]
3513 { if (TARGET_WINDOWS_NT)
3514 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3515 else if (TARGET_OPEN_VMS)
3516 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3518 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3523 (define_expand "call_osf"
3524 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3525 (match_operand 1 "" ""))
3526 (clobber (reg:DI 27))
3527 (clobber (reg:DI 26))])]
3530 { if (GET_CODE (operands[0]) != MEM)
3533 operands[0] = XEXP (operands[0], 0);
3535 if (GET_CODE (operands[0]) != SYMBOL_REF
3536 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3538 rtx tem = gen_rtx_REG (DImode, 27);
3539 emit_move_insn (tem, operands[0]);
3544 (define_expand "call_nt"
3545 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3546 (match_operand 1 "" ""))
3547 (clobber (reg:DI 26))])]
3550 { if (GET_CODE (operands[0]) != MEM)
3553 operands[0] = XEXP (operands[0], 0);
3554 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3555 operands[0] = force_reg (DImode, operands[0]);
3559 ;; call openvms/alpha
3560 ;; op 0: symbol ref for called function
3561 ;; op 1: next_arg_reg (argument information value for R25)
3563 (define_expand "call_vms"
3564 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3565 (match_operand 1 "" ""))
3569 (clobber (reg:DI 27))])]
3572 { if (GET_CODE (operands[0]) != MEM)
3575 operands[0] = XEXP (operands[0], 0);
3577 /* Always load AI with argument information, then handle symbolic and
3578 indirect call differently. Load RA and set operands[2] to PV in
3581 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3582 if (GET_CODE (operands[0]) == SYMBOL_REF)
3584 extern char *savealloc ();
3585 char *linksym, *symbol = XSTR (operands[0], 0);
3590 linksym = savealloc (strlen (symbol) + 6);
3592 alpha_need_linkage (symbol, 0);
3595 strcpy (linksym+1, symbol);
3596 strcat (linksym, \"..lk\");
3597 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3599 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3602 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3606 emit_move_insn (gen_rtx_REG (Pmode, 26),
3607 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3609 operands[2] = operands[0];
3614 (define_expand "call_value"
3615 [(use (match_operand 0 "" ""))
3616 (use (match_operand:DI 1 "" ""))
3617 (use (match_operand 2 "" ""))
3618 (use (match_operand 3 "" ""))
3619 (use (match_operand 4 "" ""))]
3622 { if (TARGET_WINDOWS_NT)
3623 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3624 else if (TARGET_OPEN_VMS)
3625 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3628 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3633 (define_expand "call_value_osf"
3634 [(parallel [(set (match_operand 0 "" "")
3635 (call (mem:DI (match_operand 1 "" ""))
3636 (match_operand 2 "" "")))
3637 (clobber (reg:DI 27))
3638 (clobber (reg:DI 26))])]
3641 { if (GET_CODE (operands[1]) != MEM)
3644 operands[1] = XEXP (operands[1], 0);
3646 if (GET_CODE (operands[1]) != SYMBOL_REF
3647 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3649 rtx tem = gen_rtx_REG (DImode, 27);
3650 emit_move_insn (tem, operands[1]);
3655 (define_expand "call_value_nt"
3656 [(parallel [(set (match_operand 0 "" "")
3657 (call (mem:DI (match_operand 1 "" ""))
3658 (match_operand 2 "" "")))
3659 (clobber (reg:DI 26))])]
3662 { if (GET_CODE (operands[1]) != MEM)
3665 operands[1] = XEXP (operands[1], 0);
3666 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
3667 operands[1] = force_reg (DImode, operands[1]);
3670 (define_expand "call_value_vms"
3671 [(parallel [(set (match_operand 0 "" "")
3672 (call (mem:DI (match_operand:DI 1 "" ""))
3673 (match_operand 2 "" "")))
3677 (clobber (reg:DI 27))])]
3680 { if (GET_CODE (operands[1]) != MEM)
3683 operands[1] = XEXP (operands[1], 0);
3685 /* Always load AI with argument information, then handle symbolic and
3686 indirect call differently. Load RA and set operands[3] to PV in
3689 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3690 if (GET_CODE (operands[1]) == SYMBOL_REF)
3692 extern char *savealloc ();
3693 char *linksym, *symbol = XSTR (operands[1], 0);
3698 linksym = savealloc (strlen (symbol) + 6);
3700 alpha_need_linkage (symbol, 0);
3702 strcpy (linksym+1, symbol);
3703 strcat (linksym, \"..lk\");
3704 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3706 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3709 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3713 emit_move_insn (gen_rtx_REG (Pmode, 26),
3714 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
3716 operands[3] = operands[1];
3721 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3722 (match_operand 1 "" ""))
3723 (clobber (reg:DI 27))
3724 (clobber (reg:DI 26))]
3725 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3727 jsr $26,($27),0\;ldgp $29,0($26)
3729 jsr $26,%0\;ldgp $29,0($26)"
3730 [(set_attr "type" "jsr")
3731 (set_attr "length" "12,*,16")])
3734 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3735 (match_operand 1 "" ""))
3736 (clobber (reg:DI 26))]
3742 [(set_attr "type" "jsr")
3743 (set_attr "length" "*,*,12")])
3746 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3747 (match_operand 1 "" ""))
3748 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
3751 (clobber (reg:DI 27))]
3754 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
3755 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3756 [(set_attr "type" "jsr")
3757 (set_attr "length" "12,16")])
3759 ;; Call subroutine returning any type.
3761 (define_expand "untyped_call"
3762 [(parallel [(call (match_operand 0 "" "")
3764 (match_operand 1 "" "")
3765 (match_operand 2 "" "")])]
3771 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3773 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3775 rtx set = XVECEXP (operands[2], 0, i);
3776 emit_move_insn (SET_DEST (set), SET_SRC (set));
3779 /* The optimizer does not know that the call sets the function value
3780 registers we stored in the result block. We avoid problems by
3781 claiming that all hard registers are used and clobbered at this
3783 emit_insn (gen_blockage ());
3788 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3789 ;; all of memory. This blocks insns from being moved across this point.
3791 (define_insn "blockage"
3792 [(unspec_volatile [(const_int 0)] 1)]
3795 [(set_attr "length" "0")])
3799 (label_ref (match_operand 0 "" "")))]
3802 [(set_attr "type" "ibr")])
3804 (define_insn "return"
3808 [(set_attr "type" "ibr")])
3810 ;; Use a different pattern for functions which have non-trivial
3811 ;; epilogues so as not to confuse jump and reorg.
3812 (define_insn "return_internal"
3817 [(set_attr "type" "ibr")])
3819 (define_insn "indirect_jump"
3820 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
3823 [(set_attr "type" "ibr")])
3825 (define_expand "tablejump"
3826 [(use (match_operand:SI 0 "register_operand" ""))
3827 (use (match_operand:SI 1 "" ""))]
3831 if (TARGET_WINDOWS_NT)
3832 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
3833 else if (TARGET_OPEN_VMS)
3834 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
3836 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
3841 (define_expand "tablejump_osf"
3843 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3844 (parallel [(set (pc)
3845 (plus:DI (match_dup 3)
3846 (label_ref (match_operand 1 "" ""))))
3847 (clobber (match_scratch:DI 2 "=r"))])]
3850 { operands[3] = gen_reg_rtx (DImode); }")
3852 (define_expand "tablejump_nt"
3854 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3855 (parallel [(set (pc)
3857 (use (label_ref (match_operand 1 "" "")))])]
3860 { operands[3] = gen_reg_rtx (DImode); }")
3863 ;; tablejump, openVMS way
3865 ;; op 1: label preceding jump-table
3867 (define_expand "tablejump_vms"
3869 (match_operand:DI 0 "register_operand" ""))
3871 (plus:DI (match_dup 2)
3872 (label_ref (match_operand 1 "" ""))))]
3875 { operands[2] = gen_reg_rtx (DImode); }")
3879 (plus (match_operand:DI 0 "register_operand" "r")
3880 (label_ref (match_operand 1 "" ""))))
3881 (clobber (match_scratch:DI 2 "=r"))]
3882 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
3883 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3884 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3886 { rtx best_label = 0;
3887 rtx jump_table_insn = next_active_insn (operands[1]);
3889 if (GET_CODE (jump_table_insn) == JUMP_INSN
3890 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3892 rtx jump_table = PATTERN (jump_table_insn);
3893 int n_labels = XVECLEN (jump_table, 1);
3894 int best_count = -1;
3897 for (i = 0; i < n_labels; i++)
3901 for (j = i + 1; j < n_labels; j++)
3902 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3903 == XEXP (XVECEXP (jump_table, 1, j), 0))
3906 if (count > best_count)
3907 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3913 operands[3] = best_label;
3914 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
3917 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
3919 [(set_attr "type" "ibr")
3920 (set_attr "length" "8")])
3924 (match_operand:DI 0 "register_operand" "r"))
3925 (use (label_ref (match_operand 1 "" "")))]
3926 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
3927 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3928 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3930 { rtx best_label = 0;
3931 rtx jump_table_insn = next_active_insn (operands[1]);
3933 if (GET_CODE (jump_table_insn) == JUMP_INSN
3934 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3936 rtx jump_table = PATTERN (jump_table_insn);
3937 int n_labels = XVECLEN (jump_table, 1);
3938 int best_count = -1;
3941 for (i = 0; i < n_labels; i++)
3945 for (j = i + 1; j < n_labels; j++)
3946 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3947 == XEXP (XVECEXP (jump_table, 1, j), 0))
3950 if (count > best_count)
3951 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3957 operands[2] = best_label;
3958 return \"jmp $31,(%0),%2\";
3961 return \"jmp $31,(%0),0\";
3963 [(set_attr "type" "ibr")])
3966 ;; op 0 is table offset
3967 ;; op 1 is table label
3972 (plus (match_operand:DI 0 "register_operand" "r")
3973 (label_ref (match_operand 1 "" ""))))]
3976 [(set_attr "type" "ibr")])
3978 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
3979 ;; want to have to include pal.h in our .s file.
3981 ;; Technically the type for call_pal is jsr, but we use that for determining
3982 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
3985 [(unspec_volatile [(const_int 0)] 0)]
3988 [(set_attr "type" "ibr")])
3990 ;; Finally, we have the basic data motion insns. The byte and word insns
3991 ;; are done via define_expand. Start with the floating-point insns, since
3992 ;; they are simpler.
3995 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
3996 (match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r"))]
3998 && (register_operand (operands[0], SFmode)
3999 || reg_or_fp0_operand (operands[1], SFmode))"
4007 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4010 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
4011 (match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
4013 && (register_operand (operands[0], SFmode)
4014 || reg_or_fp0_operand (operands[1], SFmode))"
4024 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4027 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
4028 (match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r"))]
4030 && (register_operand (operands[0], DFmode)
4031 || reg_or_fp0_operand (operands[1], DFmode))"
4039 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4042 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
4043 (match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
4045 && (register_operand (operands[0], DFmode)
4046 || reg_or_fp0_operand (operands[1], DFmode))"
4056 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4058 (define_expand "movsf"
4059 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4060 (match_operand:SF 1 "general_operand" ""))]
4064 if (GET_CODE (operands[0]) == MEM
4065 && ! reg_or_fp0_operand (operands[1], SFmode))
4066 operands[1] = force_reg (SFmode, operands[1]);
4069 (define_expand "movdf"
4070 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4071 (match_operand:DF 1 "general_operand" ""))]
4075 if (GET_CODE (operands[0]) == MEM
4076 && ! reg_or_fp0_operand (operands[1], DFmode))
4077 operands[1] = force_reg (DFmode, operands[1]);
4081 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m")
4082 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f"))]
4083 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4084 && (register_operand (operands[0], SImode)
4085 || reg_or_0_operand (operands[1], SImode))"
4095 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4098 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m,r,*f")
4099 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f,f,*r"))]
4100 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4101 && (register_operand (operands[0], SImode)
4102 || reg_or_0_operand (operands[1], SImode))"
4114 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4117 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,m")
4118 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,m,f"))]
4119 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4120 && (register_operand (operands[0], SImode)
4121 || reg_or_0_operand (operands[1], SImode))"
4132 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4135 [(set (match_operand:HI 0 "register_operand" "=r,r")
4136 (match_operand:HI 1 "input_operand" "rJ,n"))]
4138 && (register_operand (operands[0], HImode)
4139 || register_operand (operands[1], HImode))"
4143 [(set_attr "type" "ilog,iadd")])
4146 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4147 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4149 && (register_operand (operands[0], HImode)
4150 || reg_or_0_operand (operands[1], HImode))"
4156 [(set_attr "type" "ilog,iadd,ild,ist")])
4159 [(set (match_operand:QI 0 "register_operand" "=r,r")
4160 (match_operand:QI 1 "input_operand" "rJ,n"))]
4162 && (register_operand (operands[0], QImode)
4163 || register_operand (operands[1], QImode))"
4167 [(set_attr "type" "ilog,iadd")])
4170 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4171 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4173 && (register_operand (operands[0], QImode)
4174 || reg_or_0_operand (operands[1], QImode))"
4180 [(set_attr "type" "ilog,iadd,ild,ist")])
4182 ;; We do two major things here: handle mem->mem and construct long
4185 (define_expand "movsi"
4186 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4187 (match_operand:SI 1 "general_operand" ""))]
4191 if (GET_CODE (operands[0]) == MEM
4192 && ! reg_or_0_operand (operands[1], SImode))
4193 operands[1] = force_reg (SImode, operands[1]);
4195 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4197 else if (GET_CODE (operands[1]) == CONST_INT)
4200 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4201 if (rtx_equal_p (operands[0], operands[1]))
4206 ;; Split a load of a large constant into the appropriate two-insn
4210 [(set (match_operand:SI 0 "register_operand" "")
4211 (match_operand:SI 1 "const_int_operand" ""))]
4212 "! add_operand (operands[1], SImode)"
4213 [(set (match_dup 0) (match_dup 2))
4214 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4217 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4219 if (tem == operands[0])
4226 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,Q")
4227 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))]
4229 && (register_operand (operands[0], DImode)
4230 || reg_or_0_operand (operands[1], DImode))"
4241 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4244 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
4245 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))]
4247 && (register_operand (operands[0], DImode)
4248 || reg_or_0_operand (operands[1], DImode))"
4261 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4263 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4264 ;; memory, and construct long 32-bit constants.
4266 (define_expand "movdi"
4267 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4268 (match_operand:DI 1 "general_operand" ""))]
4274 if (GET_CODE (operands[0]) == MEM
4275 && ! reg_or_0_operand (operands[1], DImode))
4276 operands[1] = force_reg (DImode, operands[1]);
4278 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4280 else if (GET_CODE (operands[1]) == CONST_INT
4281 && (tem = alpha_emit_set_const (operands[0], DImode,
4282 INTVAL (operands[1]), 3)) != 0)
4284 if (rtx_equal_p (tem, operands[0]))
4289 else if (CONSTANT_P (operands[1]))
4291 if (TARGET_BUILD_CONSTANTS)
4293 HOST_WIDE_INT i0, i1;
4295 if (GET_CODE (operands[1]) == CONST_INT)
4297 i0 = INTVAL (operands[1]);
4300 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4302 #if HOST_BITS_PER_WIDE_INT >= 64
4303 i0 = CONST_DOUBLE_LOW (operands[1]);
4306 i0 = CONST_DOUBLE_LOW (operands[1]);
4307 i1 = CONST_DOUBLE_HIGH (operands[1]);
4313 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4314 if (rtx_equal_p (tem, operands[0]))
4321 operands[1] = force_const_mem (DImode, operands[1]);
4322 if (reload_in_progress)
4324 emit_move_insn (operands[0], XEXP (operands[1], 0));
4325 operands[1] = copy_rtx (operands[1]);
4326 XEXP (operands[1], 0) = operands[0];
4329 operands[1] = validize_mem (operands[1]);
4336 ;; Split a load of a large constant into the appropriate two-insn
4340 [(set (match_operand:DI 0 "register_operand" "")
4341 (match_operand:DI 1 "const_int_operand" ""))]
4342 "! add_operand (operands[1], DImode)"
4343 [(set (match_dup 0) (match_dup 2))
4344 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4347 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4349 if (tem == operands[0])
4355 ;; These are the partial-word cases.
4357 ;; First we have the code to load an aligned word. Operand 0 is the register
4358 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4359 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4360 ;; number of bits within the word that the value is. Operand 3 is an SImode
4361 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4362 ;; same register. It is allowed to conflict with operand 1 as well.
4364 (define_expand "aligned_loadqi"
4365 [(set (match_operand:SI 3 "register_operand" "")
4366 (match_operand:SI 1 "memory_operand" ""))
4367 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4368 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4370 (match_operand:DI 2 "const_int_operand" "")))]
4375 (define_expand "aligned_loadhi"
4376 [(set (match_operand:SI 3 "register_operand" "")
4377 (match_operand:SI 1 "memory_operand" ""))
4378 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4379 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4381 (match_operand:DI 2 "const_int_operand" "")))]
4386 ;; Similar for unaligned loads, where we use the sequence from the
4387 ;; Alpha Architecture manual.
4389 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4390 ;; operand 3 can overlap the input and output registers.
4392 (define_expand "unaligned_loadqi"
4393 [(set (match_operand:DI 2 "register_operand" "")
4394 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4396 (set (match_operand:DI 3 "register_operand" "")
4398 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4399 (zero_extract:DI (match_dup 2)
4401 (ashift:DI (match_dup 3) (const_int 3))))]
4405 (define_expand "unaligned_loadhi"
4406 [(set (match_operand:DI 2 "register_operand" "")
4407 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4409 (set (match_operand:DI 3 "register_operand" "")
4411 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4412 (zero_extract:DI (match_dup 2)
4414 (ashift:DI (match_dup 3) (const_int 3))))]
4418 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4419 ;; aligned SImode MEM. Operand 1 is the register containing the
4420 ;; byte or word to store. Operand 2 is the number of bits within the word that
4421 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4423 (define_expand "aligned_store"
4424 [(set (match_operand:SI 3 "register_operand" "")
4425 (match_operand:SI 0 "memory_operand" ""))
4426 (set (subreg:DI (match_dup 3) 0)
4427 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4428 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4429 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4430 (match_operand:DI 2 "const_int_operand" "")))
4431 (set (subreg:DI (match_dup 4) 0)
4432 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4433 (set (match_dup 0) (match_dup 4))]
4436 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4437 << INTVAL (operands[2])));
4440 ;; For the unaligned byte and halfword cases, we use code similar to that
4441 ;; in the ;; Architecture book, but reordered to lower the number of registers
4442 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4443 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4444 ;; be the same temporary, if desired. If the address is in a register,
4445 ;; operand 2 can be that register.
4447 (define_expand "unaligned_storeqi"
4448 [(set (match_operand:DI 3 "register_operand" "")
4449 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4451 (set (match_operand:DI 2 "register_operand" "")
4454 (and:DI (not:DI (ashift:DI (const_int 255)
4455 (ashift:DI (match_dup 2) (const_int 3))))
4457 (set (match_operand:DI 4 "register_operand" "")
4458 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4459 (ashift:DI (match_dup 2) (const_int 3))))
4460 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4461 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4466 (define_expand "unaligned_storehi"
4467 [(set (match_operand:DI 3 "register_operand" "")
4468 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4470 (set (match_operand:DI 2 "register_operand" "")
4473 (and:DI (not:DI (ashift:DI (const_int 65535)
4474 (ashift:DI (match_dup 2) (const_int 3))))
4476 (set (match_operand:DI 4 "register_operand" "")
4477 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4478 (ashift:DI (match_dup 2) (const_int 3))))
4479 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4480 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4485 ;; Here are the define_expand's for QI and HI moves that use the above
4486 ;; patterns. We have the normal sets, plus the ones that need scratch
4487 ;; registers for reload.
4489 (define_expand "movqi"
4490 [(set (match_operand:QI 0 "nonimmediate_operand" "")
4491 (match_operand:QI 1 "general_operand" ""))]
4497 if (GET_CODE (operands[0]) == MEM
4498 && ! reg_or_0_operand (operands[1], QImode))
4499 operands[1] = force_reg (QImode, operands[1]);
4501 if (GET_CODE (operands[1]) == CONST_INT
4502 && ! input_operand (operands[1], QImode))
4504 operands[1] = alpha_emit_set_const (operands[0], QImode,
4505 INTVAL (operands[1]), 3);
4507 if (rtx_equal_p (operands[0], operands[1]))
4514 /* If the output is not a register, the input must be. */
4515 if (GET_CODE (operands[0]) == MEM)
4516 operands[1] = force_reg (QImode, operands[1]);
4518 /* Handle four memory cases, unaligned and aligned for either the input
4519 or the output. The only case where we can be called during reload is
4520 for aligned loads; all other cases require temporaries. */
4522 if (GET_CODE (operands[1]) == MEM
4523 || (GET_CODE (operands[1]) == SUBREG
4524 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4525 || (reload_in_progress && GET_CODE (operands[1]) == REG
4526 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4527 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4528 && GET_CODE (SUBREG_REG (operands[1])) == REG
4529 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4531 if (aligned_memory_operand (operands[1], QImode))
4533 if (reload_in_progress)
4535 emit_insn (gen_reload_inqi_help
4536 (operands[0], operands[1],
4537 gen_rtx_REG (SImode, REGNO (operands[0]))));
4541 rtx aligned_mem, bitnum;
4542 rtx scratch = gen_reg_rtx (SImode);
4544 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4546 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4552 /* Don't pass these as parameters since that makes the generated
4553 code depend on parameter evaluation order which will cause
4554 bootstrap failures. */
4556 rtx temp1 = gen_reg_rtx (DImode);
4557 rtx temp2 = gen_reg_rtx (DImode);
4559 = gen_unaligned_loadqi (operands[0],
4560 get_unaligned_address (operands[1], 0),
4563 alpha_set_memflags (seq, operands[1]);
4570 else if (GET_CODE (operands[0]) == MEM
4571 || (GET_CODE (operands[0]) == SUBREG
4572 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4573 || (reload_in_progress && GET_CODE (operands[0]) == REG
4574 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4575 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4576 && GET_CODE (SUBREG_REG (operands[0])) == REG
4577 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4579 if (aligned_memory_operand (operands[0], QImode))
4581 rtx aligned_mem, bitnum;
4582 rtx temp1 = gen_reg_rtx (SImode);
4583 rtx temp2 = gen_reg_rtx (SImode);
4585 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4587 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4592 rtx temp1 = gen_reg_rtx (DImode);
4593 rtx temp2 = gen_reg_rtx (DImode);
4594 rtx temp3 = gen_reg_rtx (DImode);
4596 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4597 operands[1], temp1, temp2, temp3);
4599 alpha_set_memflags (seq, operands[0]);
4607 (define_expand "movhi"
4608 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4609 (match_operand:HI 1 "general_operand" ""))]
4615 if (GET_CODE (operands[0]) == MEM
4616 && ! reg_or_0_operand (operands[1], HImode))
4617 operands[1] = force_reg (HImode, operands[1]);
4619 if (GET_CODE (operands[1]) == CONST_INT
4620 && ! input_operand (operands[1], HImode))
4622 operands[1] = alpha_emit_set_const (operands[0], HImode,
4623 INTVAL (operands[1]), 3);
4625 if (rtx_equal_p (operands[0], operands[1]))
4632 /* If the output is not a register, the input must be. */
4633 if (GET_CODE (operands[0]) == MEM)
4634 operands[1] = force_reg (HImode, operands[1]);
4636 /* Handle four memory cases, unaligned and aligned for either the input
4637 or the output. The only case where we can be called during reload is
4638 for aligned loads; all other cases require temporaries. */
4640 if (GET_CODE (operands[1]) == MEM
4641 || (GET_CODE (operands[1]) == SUBREG
4642 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4643 || (reload_in_progress && GET_CODE (operands[1]) == REG
4644 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4645 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4646 && GET_CODE (SUBREG_REG (operands[1])) == REG
4647 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4649 if (aligned_memory_operand (operands[1], HImode))
4651 if (reload_in_progress)
4653 emit_insn (gen_reload_inhi_help
4654 (operands[0], operands[1],
4655 gen_rtx_REG (SImode, REGNO (operands[0]))));
4659 rtx aligned_mem, bitnum;
4660 rtx scratch = gen_reg_rtx (SImode);
4662 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4664 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4670 /* Don't pass these as parameters since that makes the generated
4671 code depend on parameter evaluation order which will cause
4672 bootstrap failures. */
4674 rtx temp1 = gen_reg_rtx (DImode);
4675 rtx temp2 = gen_reg_rtx (DImode);
4677 = gen_unaligned_loadhi (operands[0],
4678 get_unaligned_address (operands[1], 0),
4681 alpha_set_memflags (seq, operands[1]);
4688 else if (GET_CODE (operands[0]) == MEM
4689 || (GET_CODE (operands[0]) == SUBREG
4690 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4691 || (reload_in_progress && GET_CODE (operands[0]) == REG
4692 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4693 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4694 && GET_CODE (SUBREG_REG (operands[0])) == REG
4695 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4697 if (aligned_memory_operand (operands[0], HImode))
4699 rtx aligned_mem, bitnum;
4700 rtx temp1 = gen_reg_rtx (SImode);
4701 rtx temp2 = gen_reg_rtx (SImode);
4703 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4705 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4710 rtx temp1 = gen_reg_rtx (DImode);
4711 rtx temp2 = gen_reg_rtx (DImode);
4712 rtx temp3 = gen_reg_rtx (DImode);
4714 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
4715 operands[1], temp1, temp2, temp3);
4717 alpha_set_memflags (seq, operands[0]);
4726 ;; Here are the versions for reload. Note that in the unaligned cases
4727 ;; we know that the operand must not be a pseudo-register because stack
4728 ;; slots are always aligned references.
4730 (define_expand "reload_inqi"
4731 [(parallel [(match_operand:QI 0 "register_operand" "=r")
4732 (match_operand:QI 1 "any_memory_operand" "m")
4733 (match_operand:TI 2 "register_operand" "=&r")])]
4739 if (GET_CODE (operands[1]) != MEM)
4742 if (aligned_memory_operand (operands[1], QImode))
4744 seq = gen_reload_inqi_help (operands[0], operands[1],
4745 gen_rtx_REG (SImode, REGNO (operands[2])));
4751 /* It is possible that one of the registers we got for operands[2]
4752 might coincide with that of operands[0] (which is why we made
4753 it TImode). Pick the other one to use as our scratch. */
4754 if (REGNO (operands[0]) == REGNO (operands[2]))
4755 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4757 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
4759 addr = get_unaligned_address (operands[1], 0);
4760 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
4761 gen_rtx_REG (DImode, REGNO (operands[0])));
4762 alpha_set_memflags (seq, operands[1]);
4768 (define_expand "reload_inhi"
4769 [(parallel [(match_operand:HI 0 "register_operand" "=r")
4770 (match_operand:HI 1 "any_memory_operand" "m")
4771 (match_operand:TI 2 "register_operand" "=&r")])]
4777 if (GET_CODE (operands[1]) != MEM)
4780 if (aligned_memory_operand (operands[1], HImode))
4782 seq = gen_reload_inhi_help (operands[0], operands[1],
4783 gen_rtx_REG (SImode, REGNO (operands[2])));
4789 /* It is possible that one of the registers we got for operands[2]
4790 might coincide with that of operands[0] (which is why we made
4791 it TImode). Pick the other one to use as our scratch. */
4792 if (REGNO (operands[0]) == REGNO (operands[2]))
4793 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4795 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
4797 addr = get_unaligned_address (operands[1], 0);
4798 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
4799 gen_rtx_REG (DImode, REGNO (operands[0])));
4800 alpha_set_memflags (seq, operands[1]);
4806 (define_expand "reload_outqi"
4807 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
4808 (match_operand:QI 1 "register_operand" "r")
4809 (match_operand:TI 2 "register_operand" "=&r")])]
4813 if (GET_CODE (operands[0]) != MEM)
4816 if (aligned_memory_operand (operands[0], QImode))
4818 emit_insn (gen_reload_outqi_help
4819 (operands[0], operands[1],
4820 gen_rtx_REG (SImode, REGNO (operands[2])),
4821 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
4825 rtx addr = get_unaligned_address (operands[0], 0);
4826 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4827 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4828 rtx scratch3 = scratch1;
4831 if (GET_CODE (addr) == REG)
4834 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
4835 scratch2, scratch3);
4836 alpha_set_memflags (seq, operands[0]);
4842 (define_expand "reload_outhi"
4843 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
4844 (match_operand:HI 1 "register_operand" "r")
4845 (match_operand:TI 2 "register_operand" "=&r")])]
4849 if (GET_CODE (operands[0]) != MEM)
4852 if (aligned_memory_operand (operands[0], HImode))
4854 emit_insn (gen_reload_outhi_help
4855 (operands[0], operands[1],
4856 gen_rtx_REG (SImode, REGNO (operands[2])),
4857 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
4861 rtx addr = get_unaligned_address (operands[0], 0);
4862 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4863 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4864 rtx scratch3 = scratch1;
4867 if (GET_CODE (addr) == REG)
4870 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
4871 scratch2, scratch3);
4872 alpha_set_memflags (seq, operands[0]);
4878 ;; Helpers for the above. The way reload is structured, we can't
4879 ;; always get a proper address for a stack slot during reload_foo
4880 ;; expansion, so we must delay our address manipulations until after.
4882 (define_insn "reload_inqi_help"
4883 [(set (match_operand:QI 0 "register_operand" "r")
4884 (match_operand:QI 1 "memory_operand" "m"))
4885 (clobber (match_operand:SI 2 "register_operand" "r"))]
4886 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4889 (define_insn "reload_inhi_help"
4890 [(set (match_operand:HI 0 "register_operand" "r")
4891 (match_operand:HI 1 "memory_operand" "m"))
4892 (clobber (match_operand:SI 2 "register_operand" "r"))]
4893 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4896 (define_insn "reload_outqi_help"
4897 [(set (match_operand:QI 0 "memory_operand" "m")
4898 (match_operand:QI 1 "register_operand" "r"))
4899 (clobber (match_operand:SI 2 "register_operand" "r"))
4900 (clobber (match_operand:SI 3 "register_operand" "r"))]
4901 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4904 (define_insn "reload_outhi_help"
4905 [(set (match_operand:HI 0 "memory_operand" "m")
4906 (match_operand:HI 1 "register_operand" "r"))
4907 (clobber (match_operand:SI 2 "register_operand" "r"))
4908 (clobber (match_operand:SI 3 "register_operand" "r"))]
4909 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4913 [(set (match_operand:QI 0 "register_operand" "r")
4914 (match_operand:QI 1 "memory_operand" "m"))
4915 (clobber (match_operand:SI 2 "register_operand" "r"))]
4916 "! TARGET_BWX && reload_completed"
4920 rtx aligned_mem, bitnum;
4921 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4922 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4928 [(set (match_operand:HI 0 "register_operand" "r")
4929 (match_operand:HI 1 "memory_operand" "m"))
4930 (clobber (match_operand:SI 2 "register_operand" "r"))]
4931 "! TARGET_BWX && reload_completed"
4935 rtx aligned_mem, bitnum;
4936 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4937 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4943 [(set (match_operand:QI 0 "memory_operand" "m")
4944 (match_operand:QI 1 "register_operand" "r"))
4945 (clobber (match_operand:SI 2 "register_operand" "r"))
4946 (clobber (match_operand:SI 3 "register_operand" "r"))]
4947 "! TARGET_BWX && reload_completed"
4951 rtx aligned_mem, bitnum;
4952 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4953 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4954 operands[2], operands[3]));
4959 [(set (match_operand:HI 0 "memory_operand" "m")
4960 (match_operand:HI 1 "register_operand" "r"))
4961 (clobber (match_operand:SI 2 "register_operand" "r"))
4962 (clobber (match_operand:SI 3 "register_operand" "r"))]
4963 "! TARGET_BWX && reload_completed"
4967 rtx aligned_mem, bitnum;
4968 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4969 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4970 operands[2], operands[3]));
4974 ;; Bit field extract patterns which use ext[wlq][lh]
4976 (define_expand "extv"
4977 [(set (match_operand:DI 0 "register_operand" "")
4978 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
4979 (match_operand:DI 2 "immediate_operand" "")
4980 (match_operand:DI 3 "immediate_operand" "")))]
4984 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4985 if (INTVAL (operands[3]) % 8 != 0
4986 || (INTVAL (operands[2]) != 16
4987 && INTVAL (operands[2]) != 32
4988 && INTVAL (operands[2]) != 64))
4991 /* From mips.md: extract_bit_field doesn't verify that our source
4992 matches the predicate, so we force it to be a MEM here. */
4993 if (GET_CODE (operands[1]) != MEM)
4996 alpha_expand_unaligned_load (operands[0], operands[1],
4997 INTVAL (operands[2]) / 8,
4998 INTVAL (operands[3]) / 8, 1);
5002 (define_expand "extzv"
5003 [(set (match_operand:DI 0 "register_operand" "")
5004 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5005 (match_operand:DI 2 "immediate_operand" "")
5006 (match_operand:DI 3 "immediate_operand" "")))]
5010 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5011 if (INTVAL (operands[3]) % 8 != 0
5012 || (INTVAL (operands[2]) != 8
5013 && INTVAL (operands[2]) != 16
5014 && INTVAL (operands[2]) != 32
5015 && INTVAL (operands[2]) != 64))
5018 if (GET_CODE (operands[1]) == MEM)
5020 /* Fail 8 bit fields, falling back on a simple byte load. */
5021 if (INTVAL (operands[2]) == 8)
5024 alpha_expand_unaligned_load (operands[0], operands[1],
5025 INTVAL (operands[2]) / 8,
5026 INTVAL (operands[3]) / 8, 0);
5031 (define_expand "insv"
5032 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5033 (match_operand:DI 1 "immediate_operand" "")
5034 (match_operand:DI 2 "immediate_operand" ""))
5035 (match_operand:DI 3 "register_operand" ""))]
5039 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5040 if (INTVAL (operands[2]) % 8 != 0
5041 || (INTVAL (operands[1]) != 16
5042 && INTVAL (operands[1]) != 32
5043 && INTVAL (operands[1]) != 64))
5046 /* From mips.md: store_bit_field doesn't verify that our source
5047 matches the predicate, so we force it to be a MEM here. */
5048 if (GET_CODE (operands[0]) != MEM)
5051 alpha_expand_unaligned_store (operands[0], operands[3],
5052 INTVAL (operands[1]) / 8,
5053 INTVAL (operands[2]) / 8);
5059 ;; Block move/clear, see alpha.c for more details.
5060 ;; Argument 0 is the destination
5061 ;; Argument 1 is the source
5062 ;; Argument 2 is the length
5063 ;; Argument 3 is the alignment
5065 (define_expand "movstrqi"
5066 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5067 (match_operand:BLK 1 "memory_operand" ""))
5068 (use (match_operand:DI 2 "immediate_operand" ""))
5069 (use (match_operand:DI 3 "immediate_operand" ""))])]
5073 if (alpha_expand_block_move (operands))
5079 (define_expand "clrstrqi"
5080 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5082 (use (match_operand:DI 1 "immediate_operand" ""))
5083 (use (match_operand:DI 2 "immediate_operand" ""))])]
5087 if (alpha_expand_block_clear (operands))
5093 ;; Subroutine of stack space allocation. Perform a stack probe.
5094 (define_expand "probe_stack"
5095 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5099 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5100 INTVAL (operands[0])));
5101 MEM_VOLATILE_P (operands[1]) = 1;
5103 operands[0] = const0_rtx;
5106 ;; This is how we allocate stack space. If we are allocating a
5107 ;; constant amount of space and we know it is less than 4096
5108 ;; bytes, we need do nothing.
5110 ;; If it is more than 4096 bytes, we need to probe the stack
5112 (define_expand "allocate_stack"
5114 (plus:DI (reg:DI 30)
5115 (match_operand:DI 1 "reg_or_cint_operand" "")))
5116 (set (match_operand:DI 0 "register_operand" "=r")
5121 if (GET_CODE (operands[1]) == CONST_INT
5122 && INTVAL (operands[1]) < 32768)
5124 if (INTVAL (operands[1]) >= 4096)
5126 /* We do this the same way as in the prologue and generate explicit
5127 probes. Then we update the stack by the constant. */
5131 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5132 while (probed + 8192 < INTVAL (operands[1]))
5133 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5135 if (probed + 4096 < INTVAL (operands[1]))
5136 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5139 operands[1] = GEN_INT (- INTVAL (operands[1]));
5140 operands[2] = virtual_stack_dynamic_rtx;
5145 rtx loop_label = gen_label_rtx ();
5146 rtx want = gen_reg_rtx (Pmode);
5147 rtx tmp = gen_reg_rtx (Pmode);
5150 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5151 force_reg (Pmode, operands[1])));
5152 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5154 if (GET_CODE (operands[1]) != CONST_INT)
5156 out_label = gen_label_rtx ();
5157 emit_insn (gen_cmpdi (want, tmp));
5158 emit_jump_insn (gen_bgeu (out_label));
5161 emit_label (loop_label);
5162 memref = gen_rtx_MEM (DImode, tmp);
5163 MEM_VOLATILE_P (memref) = 1;
5164 emit_move_insn (memref, const0_rtx);
5165 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5166 emit_insn (gen_cmpdi (tmp, want));
5167 emit_jump_insn (gen_bgtu (loop_label));
5169 gen_rtx_USE (VOIDmode, tmp);
5171 memref = gen_rtx_MEM (DImode, want);
5172 MEM_VOLATILE_P (memref) = 1;
5173 emit_move_insn (memref, const0_rtx);
5176 emit_label (out_label);
5178 emit_move_insn (stack_pointer_rtx, want);
5179 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5184 ;; This is used by alpha_expand_prolog to do the same thing as above,
5185 ;; except we cannot at that time generate new basic blocks, so we hide
5186 ;; the loop in this one insn.
5188 (define_insn "prologue_stack_probe_loop"
5189 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5190 (match_operand:DI 1 "register_operand" "r")] 5)]
5194 operands[2] = gen_label_rtx ();
5195 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5196 CODE_LABEL_NUMBER (operands[2]));
5198 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5200 [(set_attr "length" "16")
5201 (set_attr "type" "multi")])
5203 (define_expand "prologue"
5204 [(clobber (const_int 0))]
5206 "alpha_expand_prologue (); DONE;")
5208 (define_insn "init_fp"
5209 [(set (match_operand:DI 0 "register_operand" "r")
5210 (match_operand:DI 1 "register_operand" "r"))
5211 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "r")))]
5215 (define_expand "epilogue"
5216 [(clobber (const_int 0))]
5218 "alpha_expand_epilogue (); DONE;")
5220 (define_expand "eh_epilogue"
5221 [(use (match_operand:DI 0 "register_operand" "r"))
5222 (use (match_operand:DI 1 "register_operand" "r"))
5223 (use (match_operand:DI 2 "register_operand" "r"))]
5227 current_function->machine->eh_epilogue_sp_ofs = operands[1];
5228 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5230 rtx ra = gen_rtx_REG (Pmode, 26);
5231 emit_move_insn (ra, operands[2]);
5236 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5237 ;; the frame size into a register. We use this pattern to ensure
5238 ;; we get lda instead of addq.
5239 (define_insn "nt_lda"
5240 [(set (match_operand:DI 0 "register_operand" "r")
5241 (unspec:DI [(match_dup 0)
5242 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5246 (define_expand "builtin_longjmp"
5247 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5248 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5251 /* The elements of the buffer are, in order: */
5252 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5253 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5254 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5255 rtx pv = gen_rtx_REG (Pmode, 27);
5257 /* This bit is the same as expand_builtin_longjmp. */
5258 emit_move_insn (hard_frame_pointer_rtx, fp);
5259 emit_move_insn (pv, lab);
5260 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5261 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5262 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5264 /* Load the label we are jumping through into $27 so that we know
5265 where to look for it when we get back to setjmp's function for
5266 restoring the gp. */
5267 emit_indirect_jump (pv);
5271 (define_insn "builtin_setjmp_receiver"
5272 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5273 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5274 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5275 [(set_attr "length" "8")
5276 (set_attr "type" "multi")])
5279 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5280 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5281 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5282 [(set_attr "length" "12")
5283 (set_attr "type" "multi")])
5285 (define_insn "exception_receiver"
5286 [(unspec_volatile [(const_int 0)] 7)]
5287 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5288 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5289 [(set_attr "length" "12")
5290 (set_attr "type" "multi")])
5292 (define_expand "nonlocal_goto_receiver"
5293 [(unspec_volatile [(const_int 0)] 1)
5294 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5295 (unspec_volatile [(const_int 0)] 1)
5300 (define_insn "arg_home"
5301 [(unspec [(const_int 0)] 0)
5316 (clobber (mem:BLK (const_int 0)))
5317 (clobber (reg:DI 24))
5318 (clobber (reg:DI 25))
5319 (clobber (reg:DI 0))]
5321 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5322 [(set_attr "length" "16")
5323 (set_attr "type" "multi")])
5325 ;; Close the trap shadow of preceeding instructions. This is generated
5328 (define_insn "trapb"
5329 [(unspec_volatile [(const_int 0)] 4)]
5332 [(set_attr "type" "misc")])
5334 ;; No-op instructions used by machine-dependant reorg to preserve
5335 ;; alignment for instruction issue.
5341 [(set_attr "type" "ilog")])
5347 [(set_attr "type" "fcpys")])
5354 (define_insn "realign"
5355 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5357 ".align %0 #realign")
5359 ;; The call patterns are at the end of the file because their
5360 ;; wildcard operand0 interferes with nice recognition.
5363 [(set (match_operand 0 "" "")
5364 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5365 (match_operand 2 "" "")))
5366 (clobber (reg:DI 27))
5367 (clobber (reg:DI 26))]
5368 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5370 jsr $26,($27),0\;ldgp $29,0($26)
5372 jsr $26,%1\;ldgp $29,0($26)"
5373 [(set_attr "type" "jsr")
5374 (set_attr "length" "12,*,16")])
5377 [(set (match_operand 0 "" "")
5378 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5379 (match_operand 2 "" "")))
5380 (clobber (reg:DI 26))]
5386 [(set_attr "type" "jsr")
5387 (set_attr "length" "*,*,12")])
5390 [(set (match_operand 0 "" "")
5391 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
5392 (match_operand 2 "" "")))
5393 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
5396 (clobber (reg:DI 27))]
5399 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
5400 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
5401 [(set_attr "type" "jsr")
5402 (set_attr "length" "12,16")])
5405 ;; Peepholes go at the end.
5407 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5408 ;; reload when converting fp->int.
5411 ; [(set (match_operand:SI 0 "register_operand" "=r")
5412 ; (match_operand:SI 1 "memory_operand" "m"))
5413 ; (set (match_operand:DI 2 "register_operand" "=r")
5414 ; (sign_extend:DI (match_dup 0)))]
5415 ; "rtx_equal_p (operands[0], operands[2])
5416 ; || reg_dead_p (insn, operands[0])"
5417 ; [(set (match_dup 2)
5418 ; (sign_extend:DI (match_dup 1)))]
5422 ; [(set (match_operand:SI 0 "register_operand" "=r")
5423 ; (match_operand:SI 1 "hard_fp_register_operand" "f"))
5424 ; (set (match_operand:DI 2 "register_operand" "=r")
5425 ; (sign_extend:DI (match_dup 0)))]
5427 ; && (rtx_equal_p (operands[0], operands[2])
5428 ; || reg_dead_p (insn, operands[0]))"
5429 ; [(set (match_dup 2)
5430 ; (sign_extend:DI (match_dup 1)))]