1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "diagnostic-core.h"
37 #include "selftest-rtl.h"
38 #include "rtx-vector-builder.h"
40 /* Simplification and canonicalization of RTL. */
42 /* Much code operates on (low, high) pairs; the low value is an
43 unsigned wide int, the high value a signed wide int. We
44 occasionally need to sign extend from low to high as if low were a
46 #define HWI_SIGN_EXTEND(low) \
47 ((((HOST_WIDE_INT) low) < 0) ? HOST_WIDE_INT_M1 : HOST_WIDE_INT_0)
49 static bool plus_minus_operand_p (const_rtx
);
50 static rtx
simplify_plus_minus (enum rtx_code
, machine_mode
, rtx
, rtx
);
51 static rtx
simplify_associative_operation (enum rtx_code
, machine_mode
,
53 static rtx
simplify_relational_operation_1 (enum rtx_code
, machine_mode
,
54 machine_mode
, rtx
, rtx
);
55 static rtx
simplify_unary_operation_1 (enum rtx_code
, machine_mode
, rtx
);
56 static rtx
simplify_binary_operation_1 (enum rtx_code
, machine_mode
,
59 /* Negate I, which satisfies poly_int_rtx_p. MODE is the mode of I. */
62 neg_poly_int_rtx (machine_mode mode
, const_rtx i
)
64 return immed_wide_int_const (-wi::to_poly_wide (i
, mode
), mode
);
67 /* Test whether expression, X, is an immediate constant that represents
68 the most significant bit of machine mode MODE. */
71 mode_signbit_p (machine_mode mode
, const_rtx x
)
73 unsigned HOST_WIDE_INT val
;
75 scalar_int_mode int_mode
;
77 if (!is_int_mode (mode
, &int_mode
))
80 width
= GET_MODE_PRECISION (int_mode
);
84 if (width
<= HOST_BITS_PER_WIDE_INT
87 #if TARGET_SUPPORTS_WIDE_INT
88 else if (CONST_WIDE_INT_P (x
))
91 unsigned int elts
= CONST_WIDE_INT_NUNITS (x
);
92 if (elts
!= (width
+ HOST_BITS_PER_WIDE_INT
- 1) / HOST_BITS_PER_WIDE_INT
)
94 for (i
= 0; i
< elts
- 1; i
++)
95 if (CONST_WIDE_INT_ELT (x
, i
) != 0)
97 val
= CONST_WIDE_INT_ELT (x
, elts
- 1);
98 width
%= HOST_BITS_PER_WIDE_INT
;
100 width
= HOST_BITS_PER_WIDE_INT
;
103 else if (width
<= HOST_BITS_PER_DOUBLE_INT
104 && CONST_DOUBLE_AS_INT_P (x
)
105 && CONST_DOUBLE_LOW (x
) == 0)
107 val
= CONST_DOUBLE_HIGH (x
);
108 width
-= HOST_BITS_PER_WIDE_INT
;
112 /* X is not an integer constant. */
115 if (width
< HOST_BITS_PER_WIDE_INT
)
116 val
&= (HOST_WIDE_INT_1U
<< width
) - 1;
117 return val
== (HOST_WIDE_INT_1U
<< (width
- 1));
120 /* Test whether VAL is equal to the most significant bit of mode MODE
121 (after masking with the mode mask of MODE). Returns false if the
122 precision of MODE is too large to handle. */
125 val_signbit_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
128 scalar_int_mode int_mode
;
130 if (!is_int_mode (mode
, &int_mode
))
133 width
= GET_MODE_PRECISION (int_mode
);
134 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
137 val
&= GET_MODE_MASK (int_mode
);
138 return val
== (HOST_WIDE_INT_1U
<< (width
- 1));
141 /* Test whether the most significant bit of mode MODE is set in VAL.
142 Returns false if the precision of MODE is too large to handle. */
144 val_signbit_known_set_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
148 scalar_int_mode int_mode
;
149 if (!is_int_mode (mode
, &int_mode
))
152 width
= GET_MODE_PRECISION (int_mode
);
153 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
156 val
&= HOST_WIDE_INT_1U
<< (width
- 1);
160 /* Test whether the most significant bit of mode MODE is clear in VAL.
161 Returns false if the precision of MODE is too large to handle. */
163 val_signbit_known_clear_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
167 scalar_int_mode int_mode
;
168 if (!is_int_mode (mode
, &int_mode
))
171 width
= GET_MODE_PRECISION (int_mode
);
172 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
175 val
&= HOST_WIDE_INT_1U
<< (width
- 1);
179 /* Make a binary operation by properly ordering the operands and
180 seeing if the expression folds. */
183 simplify_gen_binary (enum rtx_code code
, machine_mode mode
, rtx op0
,
188 /* If this simplifies, do it. */
189 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
193 /* Put complex operands first and constants second if commutative. */
194 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
195 && swap_commutative_operands_p (op0
, op1
))
196 std::swap (op0
, op1
);
198 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
201 /* If X is a MEM referencing the constant pool, return the real value.
202 Otherwise return X. */
204 avoid_constant_pool_reference (rtx x
)
208 poly_int64 offset
= 0;
210 switch (GET_CODE (x
))
216 /* Handle float extensions of constant pool references. */
218 c
= avoid_constant_pool_reference (tmp
);
219 if (c
!= tmp
&& CONST_DOUBLE_AS_FLOAT_P (c
))
220 return const_double_from_real_value (*CONST_DOUBLE_REAL_VALUE (c
),
228 if (GET_MODE (x
) == BLKmode
)
233 /* Call target hook to avoid the effects of -fpic etc.... */
234 addr
= targetm
.delegitimize_address (addr
);
236 /* Split the address into a base and integer offset. */
237 addr
= strip_offset (addr
, &offset
);
239 if (GET_CODE (addr
) == LO_SUM
)
240 addr
= XEXP (addr
, 1);
242 /* If this is a constant pool reference, we can turn it into its
243 constant and hope that simplifications happen. */
244 if (GET_CODE (addr
) == SYMBOL_REF
245 && CONSTANT_POOL_ADDRESS_P (addr
))
247 c
= get_pool_constant (addr
);
248 cmode
= get_pool_mode (addr
);
250 /* If we're accessing the constant in a different mode than it was
251 originally stored, attempt to fix that up via subreg simplifications.
252 If that fails we have no choice but to return the original memory. */
253 if (known_eq (offset
, 0) && cmode
== GET_MODE (x
))
255 else if (known_in_range_p (offset
, 0, GET_MODE_SIZE (cmode
)))
257 rtx tem
= simplify_subreg (GET_MODE (x
), c
, cmode
, offset
);
258 if (tem
&& CONSTANT_P (tem
))
266 /* Simplify a MEM based on its attributes. This is the default
267 delegitimize_address target hook, and it's recommended that every
268 overrider call it. */
271 delegitimize_mem_from_attrs (rtx x
)
273 /* MEMs without MEM_OFFSETs may have been offset, so we can't just
274 use their base addresses as equivalent. */
277 && MEM_OFFSET_KNOWN_P (x
))
279 tree decl
= MEM_EXPR (x
);
280 machine_mode mode
= GET_MODE (x
);
281 poly_int64 offset
= 0;
283 switch (TREE_CODE (decl
))
293 case ARRAY_RANGE_REF
:
298 case VIEW_CONVERT_EXPR
:
300 poly_int64 bitsize
, bitpos
, bytepos
, toffset_val
= 0;
302 int unsignedp
, reversep
, volatilep
= 0;
305 = get_inner_reference (decl
, &bitsize
, &bitpos
, &toffset
, &mode
,
306 &unsignedp
, &reversep
, &volatilep
);
307 if (maybe_ne (bitsize
, GET_MODE_BITSIZE (mode
))
308 || !multiple_p (bitpos
, BITS_PER_UNIT
, &bytepos
)
309 || (toffset
&& !poly_int_tree_p (toffset
, &toffset_val
)))
312 offset
+= bytepos
+ toffset_val
;
318 && mode
== GET_MODE (x
)
320 && (TREE_STATIC (decl
)
321 || DECL_THREAD_LOCAL_P (decl
))
322 && DECL_RTL_SET_P (decl
)
323 && MEM_P (DECL_RTL (decl
)))
327 offset
+= MEM_OFFSET (x
);
329 newx
= DECL_RTL (decl
);
333 rtx n
= XEXP (newx
, 0), o
= XEXP (x
, 0);
334 poly_int64 n_offset
, o_offset
;
336 /* Avoid creating a new MEM needlessly if we already had
337 the same address. We do if there's no OFFSET and the
338 old address X is identical to NEWX, or if X is of the
339 form (plus NEWX OFFSET), or the NEWX is of the form
340 (plus Y (const_int Z)) and X is that with the offset
341 added: (plus Y (const_int Z+OFFSET)). */
342 n
= strip_offset (n
, &n_offset
);
343 o
= strip_offset (o
, &o_offset
);
344 if (!(known_eq (o_offset
, n_offset
+ offset
)
345 && rtx_equal_p (o
, n
)))
346 x
= adjust_address_nv (newx
, mode
, offset
);
348 else if (GET_MODE (x
) == GET_MODE (newx
)
349 && known_eq (offset
, 0))
357 /* Make a unary operation by first seeing if it folds and otherwise making
358 the specified operation. */
361 simplify_gen_unary (enum rtx_code code
, machine_mode mode
, rtx op
,
362 machine_mode op_mode
)
366 /* If this simplifies, use it. */
367 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
370 return gen_rtx_fmt_e (code
, mode
, op
);
373 /* Likewise for ternary operations. */
376 simplify_gen_ternary (enum rtx_code code
, machine_mode mode
,
377 machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
381 /* If this simplifies, use it. */
382 if ((tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
383 op0
, op1
, op2
)) != 0)
386 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
389 /* Likewise, for relational operations.
390 CMP_MODE specifies mode comparison is done in. */
393 simplify_gen_relational (enum rtx_code code
, machine_mode mode
,
394 machine_mode cmp_mode
, rtx op0
, rtx op1
)
398 if ((tem
= simplify_relational_operation (code
, mode
, cmp_mode
,
402 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
405 /* If FN is NULL, replace all occurrences of OLD_RTX in X with copy_rtx (DATA)
406 and simplify the result. If FN is non-NULL, call this callback on each
407 X, if it returns non-NULL, replace X with its return value and simplify the
411 simplify_replace_fn_rtx (rtx x
, const_rtx old_rtx
,
412 rtx (*fn
) (rtx
, const_rtx
, void *), void *data
)
414 enum rtx_code code
= GET_CODE (x
);
415 machine_mode mode
= GET_MODE (x
);
416 machine_mode op_mode
;
418 rtx op0
, op1
, op2
, newx
, op
;
422 if (__builtin_expect (fn
!= NULL
, 0))
424 newx
= fn (x
, old_rtx
, data
);
428 else if (rtx_equal_p (x
, old_rtx
))
429 return copy_rtx ((rtx
) data
);
431 switch (GET_RTX_CLASS (code
))
435 op_mode
= GET_MODE (op0
);
436 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
437 if (op0
== XEXP (x
, 0))
439 return simplify_gen_unary (code
, mode
, op0
, op_mode
);
443 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
444 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
445 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
447 return simplify_gen_binary (code
, mode
, op0
, op1
);
450 case RTX_COMM_COMPARE
:
453 op_mode
= GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
454 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
455 op1
= simplify_replace_fn_rtx (op1
, old_rtx
, fn
, data
);
456 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
458 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
461 case RTX_BITFIELD_OPS
:
463 op_mode
= GET_MODE (op0
);
464 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
465 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
466 op2
= simplify_replace_fn_rtx (XEXP (x
, 2), old_rtx
, fn
, data
);
467 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1) && op2
== XEXP (x
, 2))
469 if (op_mode
== VOIDmode
)
470 op_mode
= GET_MODE (op0
);
471 return simplify_gen_ternary (code
, mode
, op_mode
, op0
, op1
, op2
);
476 op0
= simplify_replace_fn_rtx (SUBREG_REG (x
), old_rtx
, fn
, data
);
477 if (op0
== SUBREG_REG (x
))
479 op0
= simplify_gen_subreg (GET_MODE (x
), op0
,
480 GET_MODE (SUBREG_REG (x
)),
482 return op0
? op0
: x
;
489 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
490 if (op0
== XEXP (x
, 0))
492 return replace_equiv_address_nv (x
, op0
);
494 else if (code
== LO_SUM
)
496 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
497 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
499 /* (lo_sum (high x) y) -> y where x and y have the same base. */
500 if (GET_CODE (op0
) == HIGH
)
502 rtx base0
, base1
, offset0
, offset1
;
503 split_const (XEXP (op0
, 0), &base0
, &offset0
);
504 split_const (op1
, &base1
, &offset1
);
505 if (rtx_equal_p (base0
, base1
))
509 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
511 return gen_rtx_LO_SUM (mode
, op0
, op1
);
520 fmt
= GET_RTX_FORMAT (code
);
521 for (i
= 0; fmt
[i
]; i
++)
526 newvec
= XVEC (newx
, i
);
527 for (j
= 0; j
< GET_NUM_ELEM (vec
); j
++)
529 op
= simplify_replace_fn_rtx (RTVEC_ELT (vec
, j
),
531 if (op
!= RTVEC_ELT (vec
, j
))
535 newvec
= shallow_copy_rtvec (vec
);
537 newx
= shallow_copy_rtx (x
);
538 XVEC (newx
, i
) = newvec
;
540 RTVEC_ELT (newvec
, j
) = op
;
548 op
= simplify_replace_fn_rtx (XEXP (x
, i
), old_rtx
, fn
, data
);
549 if (op
!= XEXP (x
, i
))
552 newx
= shallow_copy_rtx (x
);
561 /* Replace all occurrences of OLD_RTX in X with NEW_RTX and try to simplify the
562 resulting RTX. Return a new RTX which is as simplified as possible. */
565 simplify_replace_rtx (rtx x
, const_rtx old_rtx
, rtx new_rtx
)
567 return simplify_replace_fn_rtx (x
, old_rtx
, 0, new_rtx
);
570 /* Try to simplify a MODE truncation of OP, which has OP_MODE.
571 Only handle cases where the truncated value is inherently an rvalue.
573 RTL provides two ways of truncating a value:
575 1. a lowpart subreg. This form is only a truncation when both
576 the outer and inner modes (here MODE and OP_MODE respectively)
577 are scalar integers, and only then when the subreg is used as
580 It is only valid to form such truncating subregs if the
581 truncation requires no action by the target. The onus for
582 proving this is on the creator of the subreg -- e.g. the
583 caller to simplify_subreg or simplify_gen_subreg -- and typically
584 involves either TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode.
586 2. a TRUNCATE. This form handles both scalar and compound integers.
588 The first form is preferred where valid. However, the TRUNCATE
589 handling in simplify_unary_operation turns the second form into the
590 first form when TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode allow,
591 so it is generally safe to form rvalue truncations using:
593 simplify_gen_unary (TRUNCATE, ...)
595 and leave simplify_unary_operation to work out which representation
598 Because of the proof requirements on (1), simplify_truncation must
599 also use simplify_gen_unary (TRUNCATE, ...) to truncate parts of OP,
600 regardless of whether the outer truncation came from a SUBREG or a
601 TRUNCATE. For example, if the caller has proven that an SImode
606 is a no-op and can be represented as a subreg, it does not follow
607 that SImode truncations of X and Y are also no-ops. On a target
608 like 64-bit MIPS that requires SImode values to be stored in
609 sign-extended form, an SImode truncation of:
611 (and:DI (reg:DI X) (const_int 63))
613 is trivially a no-op because only the lower 6 bits can be set.
614 However, X is still an arbitrary 64-bit number and so we cannot
615 assume that truncating it too is a no-op. */
618 simplify_truncation (machine_mode mode
, rtx op
,
619 machine_mode op_mode
)
621 unsigned int precision
= GET_MODE_UNIT_PRECISION (mode
);
622 unsigned int op_precision
= GET_MODE_UNIT_PRECISION (op_mode
);
623 scalar_int_mode int_mode
, int_op_mode
, subreg_mode
;
625 gcc_assert (precision
<= op_precision
);
627 /* Optimize truncations of zero and sign extended values. */
628 if (GET_CODE (op
) == ZERO_EXTEND
629 || GET_CODE (op
) == SIGN_EXTEND
)
631 /* There are three possibilities. If MODE is the same as the
632 origmode, we can omit both the extension and the subreg.
633 If MODE is not larger than the origmode, we can apply the
634 truncation without the extension. Finally, if the outermode
635 is larger than the origmode, we can just extend to the appropriate
637 machine_mode origmode
= GET_MODE (XEXP (op
, 0));
638 if (mode
== origmode
)
640 else if (precision
<= GET_MODE_UNIT_PRECISION (origmode
))
641 return simplify_gen_unary (TRUNCATE
, mode
,
642 XEXP (op
, 0), origmode
);
644 return simplify_gen_unary (GET_CODE (op
), mode
,
645 XEXP (op
, 0), origmode
);
648 /* If the machine can perform operations in the truncated mode, distribute
649 the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
650 (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */
652 && (!WORD_REGISTER_OPERATIONS
|| precision
>= BITS_PER_WORD
)
653 && (GET_CODE (op
) == PLUS
654 || GET_CODE (op
) == MINUS
655 || GET_CODE (op
) == MULT
))
657 rtx op0
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0), op_mode
);
660 rtx op1
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 1), op_mode
);
662 return simplify_gen_binary (GET_CODE (op
), mode
, op0
, op1
);
666 /* Simplify (truncate:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C)) into
667 to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
668 the outer subreg is effectively a truncation to the original mode. */
669 if ((GET_CODE (op
) == LSHIFTRT
670 || GET_CODE (op
) == ASHIFTRT
)
671 /* Ensure that OP_MODE is at least twice as wide as MODE
672 to avoid the possibility that an outer LSHIFTRT shifts by more
673 than the sign extension's sign_bit_copies and introduces zeros
674 into the high bits of the result. */
675 && 2 * precision
<= op_precision
676 && CONST_INT_P (XEXP (op
, 1))
677 && GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
678 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
679 && UINTVAL (XEXP (op
, 1)) < precision
)
680 return simplify_gen_binary (ASHIFTRT
, mode
,
681 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
683 /* Likewise (truncate:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C)) into
684 to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
685 the outer subreg is effectively a truncation to the original mode. */
686 if ((GET_CODE (op
) == LSHIFTRT
687 || GET_CODE (op
) == ASHIFTRT
)
688 && CONST_INT_P (XEXP (op
, 1))
689 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
690 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
691 && UINTVAL (XEXP (op
, 1)) < precision
)
692 return simplify_gen_binary (LSHIFTRT
, mode
,
693 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
695 /* Likewise (truncate:QI (ashift:SI (zero_extend:SI (x:QI)) C)) into
696 to (ashift:QI (x:QI) C), where C is a suitable small constant and
697 the outer subreg is effectively a truncation to the original mode. */
698 if (GET_CODE (op
) == ASHIFT
699 && CONST_INT_P (XEXP (op
, 1))
700 && (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
701 || GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
)
702 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
703 && UINTVAL (XEXP (op
, 1)) < precision
)
704 return simplify_gen_binary (ASHIFT
, mode
,
705 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
707 /* Likewise (truncate:QI (and:SI (lshiftrt:SI (x:SI) C) C2)) into
708 (and:QI (lshiftrt:QI (truncate:QI (x:SI)) C) C2) for suitable C
710 if (GET_CODE (op
) == AND
711 && (GET_CODE (XEXP (op
, 0)) == LSHIFTRT
712 || GET_CODE (XEXP (op
, 0)) == ASHIFTRT
)
713 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
714 && CONST_INT_P (XEXP (op
, 1)))
716 rtx op0
= (XEXP (XEXP (op
, 0), 0));
717 rtx shift_op
= XEXP (XEXP (op
, 0), 1);
718 rtx mask_op
= XEXP (op
, 1);
719 unsigned HOST_WIDE_INT shift
= UINTVAL (shift_op
);
720 unsigned HOST_WIDE_INT mask
= UINTVAL (mask_op
);
722 if (shift
< precision
723 /* If doing this transform works for an X with all bits set,
724 it works for any X. */
725 && ((GET_MODE_MASK (mode
) >> shift
) & mask
)
726 == ((GET_MODE_MASK (op_mode
) >> shift
) & mask
)
727 && (op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, op_mode
))
728 && (op0
= simplify_gen_binary (LSHIFTRT
, mode
, op0
, shift_op
)))
730 mask_op
= GEN_INT (trunc_int_for_mode (mask
, mode
));
731 return simplify_gen_binary (AND
, mode
, op0
, mask_op
);
735 /* Turn (truncate:M1 (*_extract:M2 (reg:M2) (len) (pos))) into
736 (*_extract:M1 (truncate:M1 (reg:M2)) (len) (pos')) if possible without
738 if ((GET_CODE (op
) == ZERO_EXTRACT
|| GET_CODE (op
) == SIGN_EXTRACT
)
739 && REG_P (XEXP (op
, 0))
740 && GET_MODE (XEXP (op
, 0)) == GET_MODE (op
)
741 && CONST_INT_P (XEXP (op
, 1))
742 && CONST_INT_P (XEXP (op
, 2)))
744 rtx op0
= XEXP (op
, 0);
745 unsigned HOST_WIDE_INT len
= UINTVAL (XEXP (op
, 1));
746 unsigned HOST_WIDE_INT pos
= UINTVAL (XEXP (op
, 2));
747 if (BITS_BIG_ENDIAN
&& pos
>= op_precision
- precision
)
749 op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, GET_MODE (op0
));
752 pos
-= op_precision
- precision
;
753 return simplify_gen_ternary (GET_CODE (op
), mode
, mode
, op0
,
754 XEXP (op
, 1), GEN_INT (pos
));
757 else if (!BITS_BIG_ENDIAN
&& precision
>= len
+ pos
)
759 op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, GET_MODE (op0
));
761 return simplify_gen_ternary (GET_CODE (op
), mode
, mode
, op0
,
762 XEXP (op
, 1), XEXP (op
, 2));
766 /* Recognize a word extraction from a multi-word subreg. */
767 if ((GET_CODE (op
) == LSHIFTRT
768 || GET_CODE (op
) == ASHIFTRT
)
769 && SCALAR_INT_MODE_P (mode
)
770 && SCALAR_INT_MODE_P (op_mode
)
771 && precision
>= BITS_PER_WORD
772 && 2 * precision
<= op_precision
773 && CONST_INT_P (XEXP (op
, 1))
774 && (INTVAL (XEXP (op
, 1)) & (precision
- 1)) == 0
775 && UINTVAL (XEXP (op
, 1)) < op_precision
)
777 poly_int64 byte
= subreg_lowpart_offset (mode
, op_mode
);
778 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
779 return simplify_gen_subreg (mode
, XEXP (op
, 0), op_mode
,
781 ? byte
- shifted_bytes
782 : byte
+ shifted_bytes
));
785 /* If we have a TRUNCATE of a right shift of MEM, make a new MEM
786 and try replacing the TRUNCATE and shift with it. Don't do this
787 if the MEM has a mode-dependent address. */
788 if ((GET_CODE (op
) == LSHIFTRT
789 || GET_CODE (op
) == ASHIFTRT
)
790 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
791 && is_a
<scalar_int_mode
> (op_mode
, &int_op_mode
)
792 && MEM_P (XEXP (op
, 0))
793 && CONST_INT_P (XEXP (op
, 1))
794 && INTVAL (XEXP (op
, 1)) % GET_MODE_BITSIZE (int_mode
) == 0
795 && INTVAL (XEXP (op
, 1)) > 0
796 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (int_op_mode
)
797 && ! mode_dependent_address_p (XEXP (XEXP (op
, 0), 0),
798 MEM_ADDR_SPACE (XEXP (op
, 0)))
799 && ! MEM_VOLATILE_P (XEXP (op
, 0))
800 && (GET_MODE_SIZE (int_mode
) >= UNITS_PER_WORD
801 || WORDS_BIG_ENDIAN
== BYTES_BIG_ENDIAN
))
803 poly_int64 byte
= subreg_lowpart_offset (int_mode
, int_op_mode
);
804 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
805 return adjust_address_nv (XEXP (op
, 0), int_mode
,
807 ? byte
- shifted_bytes
808 : byte
+ shifted_bytes
));
811 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
812 (OP:SI foo:SI) if OP is NEG or ABS. */
813 if ((GET_CODE (op
) == ABS
814 || GET_CODE (op
) == NEG
)
815 && (GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
816 || GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
817 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
818 return simplify_gen_unary (GET_CODE (op
), mode
,
819 XEXP (XEXP (op
, 0), 0), mode
);
821 /* (truncate:A (subreg:B (truncate:C X) 0)) is
823 if (GET_CODE (op
) == SUBREG
824 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
825 && SCALAR_INT_MODE_P (op_mode
)
826 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op
)), &subreg_mode
)
827 && GET_CODE (SUBREG_REG (op
)) == TRUNCATE
828 && subreg_lowpart_p (op
))
830 rtx inner
= XEXP (SUBREG_REG (op
), 0);
831 if (GET_MODE_PRECISION (int_mode
) <= GET_MODE_PRECISION (subreg_mode
))
832 return simplify_gen_unary (TRUNCATE
, int_mode
, inner
,
835 /* If subreg above is paradoxical and C is narrower
836 than A, return (subreg:A (truncate:C X) 0). */
837 return simplify_gen_subreg (int_mode
, SUBREG_REG (op
), subreg_mode
, 0);
840 /* (truncate:A (truncate:B X)) is (truncate:A X). */
841 if (GET_CODE (op
) == TRUNCATE
)
842 return simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0),
843 GET_MODE (XEXP (op
, 0)));
845 /* (truncate:A (ior X C)) is (const_int -1) if C is equal to that already,
847 if (GET_CODE (op
) == IOR
848 && SCALAR_INT_MODE_P (mode
)
849 && SCALAR_INT_MODE_P (op_mode
)
850 && CONST_INT_P (XEXP (op
, 1))
851 && trunc_int_for_mode (INTVAL (XEXP (op
, 1)), mode
) == -1)
857 /* Try to simplify a unary operation CODE whose output mode is to be
858 MODE with input operand OP whose mode was originally OP_MODE.
859 Return zero if no simplification can be made. */
861 simplify_unary_operation (enum rtx_code code
, machine_mode mode
,
862 rtx op
, machine_mode op_mode
)
866 trueop
= avoid_constant_pool_reference (op
);
868 tem
= simplify_const_unary_operation (code
, mode
, trueop
, op_mode
);
872 return simplify_unary_operation_1 (code
, mode
, op
);
875 /* Return true if FLOAT or UNSIGNED_FLOAT operation OP is known
879 exact_int_to_float_conversion_p (const_rtx op
)
881 int out_bits
= significand_size (GET_MODE_INNER (GET_MODE (op
)));
882 machine_mode op0_mode
= GET_MODE (XEXP (op
, 0));
883 /* Constants shouldn't reach here. */
884 gcc_assert (op0_mode
!= VOIDmode
);
885 int in_prec
= GET_MODE_UNIT_PRECISION (op0_mode
);
886 int in_bits
= in_prec
;
887 if (HWI_COMPUTABLE_MODE_P (op0_mode
))
889 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (XEXP (op
, 0), op0_mode
);
890 if (GET_CODE (op
) == FLOAT
)
891 in_bits
-= num_sign_bit_copies (XEXP (op
, 0), op0_mode
);
892 else if (GET_CODE (op
) == UNSIGNED_FLOAT
)
893 in_bits
= wi::min_precision (wi::uhwi (nonzero
, in_prec
), UNSIGNED
);
896 in_bits
-= wi::ctz (wi::uhwi (nonzero
, in_prec
));
898 return in_bits
<= out_bits
;
901 /* Perform some simplifications we can do even if the operands
904 simplify_unary_operation_1 (enum rtx_code code
, machine_mode mode
, rtx op
)
906 enum rtx_code reversed
;
907 rtx temp
, elt
, base
, step
;
908 scalar_int_mode inner
, int_mode
, op_mode
, op0_mode
;
913 /* (not (not X)) == X. */
914 if (GET_CODE (op
) == NOT
)
917 /* (not (eq X Y)) == (ne X Y), etc. if BImode or the result of the
918 comparison is all ones. */
919 if (COMPARISON_P (op
)
920 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
921 && ((reversed
= reversed_comparison_code (op
, NULL
)) != UNKNOWN
))
922 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
923 XEXP (op
, 0), XEXP (op
, 1));
925 /* (not (plus X -1)) can become (neg X). */
926 if (GET_CODE (op
) == PLUS
927 && XEXP (op
, 1) == constm1_rtx
)
928 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
930 /* Similarly, (not (neg X)) is (plus X -1). Only do this for
931 modes that have CONSTM1_RTX, i.e. MODE_INT, MODE_PARTIAL_INT
932 and MODE_VECTOR_INT. */
933 if (GET_CODE (op
) == NEG
&& CONSTM1_RTX (mode
))
934 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
937 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
938 if (GET_CODE (op
) == XOR
939 && CONST_INT_P (XEXP (op
, 1))
940 && (temp
= simplify_unary_operation (NOT
, mode
,
941 XEXP (op
, 1), mode
)) != 0)
942 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
944 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
945 if (GET_CODE (op
) == PLUS
946 && CONST_INT_P (XEXP (op
, 1))
947 && mode_signbit_p (mode
, XEXP (op
, 1))
948 && (temp
= simplify_unary_operation (NOT
, mode
,
949 XEXP (op
, 1), mode
)) != 0)
950 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
953 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
954 operands other than 1, but that is not valid. We could do a
955 similar simplification for (not (lshiftrt C X)) where C is
956 just the sign bit, but this doesn't seem common enough to
958 if (GET_CODE (op
) == ASHIFT
959 && XEXP (op
, 0) == const1_rtx
)
961 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
962 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
965 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
966 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
967 so we can perform the above simplification. */
968 if (STORE_FLAG_VALUE
== -1
969 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
970 && GET_CODE (op
) == ASHIFTRT
971 && CONST_INT_P (XEXP (op
, 1))
972 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (int_mode
) - 1)
973 return simplify_gen_relational (GE
, int_mode
, VOIDmode
,
974 XEXP (op
, 0), const0_rtx
);
977 if (partial_subreg_p (op
)
978 && subreg_lowpart_p (op
)
979 && GET_CODE (SUBREG_REG (op
)) == ASHIFT
980 && XEXP (SUBREG_REG (op
), 0) == const1_rtx
)
982 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op
));
985 x
= gen_rtx_ROTATE (inner_mode
,
986 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
988 XEXP (SUBREG_REG (op
), 1));
989 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, x
);
994 /* Apply De Morgan's laws to reduce number of patterns for machines
995 with negating logical insns (and-not, nand, etc.). If result has
996 only one NOT, put it first, since that is how the patterns are
998 if (GET_CODE (op
) == IOR
|| GET_CODE (op
) == AND
)
1000 rtx in1
= XEXP (op
, 0), in2
= XEXP (op
, 1);
1001 machine_mode op_mode
;
1003 op_mode
= GET_MODE (in1
);
1004 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
1006 op_mode
= GET_MODE (in2
);
1007 if (op_mode
== VOIDmode
)
1009 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
1011 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
1012 std::swap (in1
, in2
);
1014 return gen_rtx_fmt_ee (GET_CODE (op
) == IOR
? AND
: IOR
,
1018 /* (not (bswap x)) -> (bswap (not x)). */
1019 if (GET_CODE (op
) == BSWAP
)
1021 rtx x
= simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
1022 return simplify_gen_unary (BSWAP
, mode
, x
, mode
);
1027 /* (neg (neg X)) == X. */
1028 if (GET_CODE (op
) == NEG
)
1029 return XEXP (op
, 0);
1031 /* (neg (x ? (neg y) : y)) == !x ? (neg y) : y.
1032 If comparison is not reversible use
1034 if (GET_CODE (op
) == IF_THEN_ELSE
)
1036 rtx cond
= XEXP (op
, 0);
1037 rtx true_rtx
= XEXP (op
, 1);
1038 rtx false_rtx
= XEXP (op
, 2);
1040 if ((GET_CODE (true_rtx
) == NEG
1041 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
1042 || (GET_CODE (false_rtx
) == NEG
1043 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
)))
1045 if (reversed_comparison_code (cond
, NULL
) != UNKNOWN
)
1046 temp
= reversed_comparison (cond
, mode
);
1050 std::swap (true_rtx
, false_rtx
);
1052 return simplify_gen_ternary (IF_THEN_ELSE
, mode
,
1053 mode
, temp
, true_rtx
, false_rtx
);
1057 /* (neg (plus X 1)) can become (not X). */
1058 if (GET_CODE (op
) == PLUS
1059 && XEXP (op
, 1) == const1_rtx
)
1060 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
1062 /* Similarly, (neg (not X)) is (plus X 1). */
1063 if (GET_CODE (op
) == NOT
)
1064 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
1067 /* (neg (minus X Y)) can become (minus Y X). This transformation
1068 isn't safe for modes with signed zeros, since if X and Y are
1069 both +0, (minus Y X) is the same as (minus X Y). If the
1070 rounding mode is towards +infinity (or -infinity) then the two
1071 expressions will be rounded differently. */
1072 if (GET_CODE (op
) == MINUS
1073 && !HONOR_SIGNED_ZEROS (mode
)
1074 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1075 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1), XEXP (op
, 0));
1077 if (GET_CODE (op
) == PLUS
1078 && !HONOR_SIGNED_ZEROS (mode
)
1079 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1081 /* (neg (plus A C)) is simplified to (minus -C A). */
1082 if (CONST_SCALAR_INT_P (XEXP (op
, 1))
1083 || CONST_DOUBLE_AS_FLOAT_P (XEXP (op
, 1)))
1085 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1), mode
);
1087 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 0));
1090 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
1091 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
1092 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
1095 /* (neg (mult A B)) becomes (mult A (neg B)).
1096 This works even for floating-point values. */
1097 if (GET_CODE (op
) == MULT
1098 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1100 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 1), mode
);
1101 return simplify_gen_binary (MULT
, mode
, XEXP (op
, 0), temp
);
1104 /* NEG commutes with ASHIFT since it is multiplication. Only do
1105 this if we can then eliminate the NEG (e.g., if the operand
1107 if (GET_CODE (op
) == ASHIFT
)
1109 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0), mode
);
1111 return simplify_gen_binary (ASHIFT
, mode
, temp
, XEXP (op
, 1));
1114 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
1115 C is equal to the width of MODE minus 1. */
1116 if (GET_CODE (op
) == ASHIFTRT
1117 && CONST_INT_P (XEXP (op
, 1))
1118 && INTVAL (XEXP (op
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
1119 return simplify_gen_binary (LSHIFTRT
, mode
,
1120 XEXP (op
, 0), XEXP (op
, 1));
1122 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
1123 C is equal to the width of MODE minus 1. */
1124 if (GET_CODE (op
) == LSHIFTRT
1125 && CONST_INT_P (XEXP (op
, 1))
1126 && INTVAL (XEXP (op
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
1127 return simplify_gen_binary (ASHIFTRT
, mode
,
1128 XEXP (op
, 0), XEXP (op
, 1));
1130 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
1131 if (GET_CODE (op
) == XOR
1132 && XEXP (op
, 1) == const1_rtx
1133 && nonzero_bits (XEXP (op
, 0), mode
) == 1)
1134 return plus_constant (mode
, XEXP (op
, 0), -1);
1136 /* (neg (lt x 0)) is (ashiftrt X C) if STORE_FLAG_VALUE is 1. */
1137 /* (neg (lt x 0)) is (lshiftrt X C) if STORE_FLAG_VALUE is -1. */
1138 if (GET_CODE (op
) == LT
1139 && XEXP (op
, 1) == const0_rtx
1140 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (op
, 0)), &inner
))
1142 int_mode
= as_a
<scalar_int_mode
> (mode
);
1143 int isize
= GET_MODE_PRECISION (inner
);
1144 if (STORE_FLAG_VALUE
== 1)
1146 temp
= simplify_gen_binary (ASHIFTRT
, inner
, XEXP (op
, 0),
1147 gen_int_shift_amount (inner
,
1149 if (int_mode
== inner
)
1151 if (GET_MODE_PRECISION (int_mode
) > isize
)
1152 return simplify_gen_unary (SIGN_EXTEND
, int_mode
, temp
, inner
);
1153 return simplify_gen_unary (TRUNCATE
, int_mode
, temp
, inner
);
1155 else if (STORE_FLAG_VALUE
== -1)
1157 temp
= simplify_gen_binary (LSHIFTRT
, inner
, XEXP (op
, 0),
1158 gen_int_shift_amount (inner
,
1160 if (int_mode
== inner
)
1162 if (GET_MODE_PRECISION (int_mode
) > isize
)
1163 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, temp
, inner
);
1164 return simplify_gen_unary (TRUNCATE
, int_mode
, temp
, inner
);
1168 if (vec_series_p (op
, &base
, &step
))
1170 /* Only create a new series if we can simplify both parts. In other
1171 cases this isn't really a simplification, and it's not necessarily
1172 a win to replace a vector operation with a scalar operation. */
1173 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
1174 base
= simplify_unary_operation (NEG
, inner_mode
, base
, inner_mode
);
1177 step
= simplify_unary_operation (NEG
, inner_mode
,
1180 return gen_vec_series (mode
, base
, step
);
1186 /* Don't optimize (lshiftrt (mult ...)) as it would interfere
1187 with the umulXi3_highpart patterns. */
1188 if (GET_CODE (op
) == LSHIFTRT
1189 && GET_CODE (XEXP (op
, 0)) == MULT
)
1192 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
1194 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
)))
1196 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1200 /* We can't handle truncation to a partial integer mode here
1201 because we don't know the real bitsize of the partial
1206 if (GET_MODE (op
) != VOIDmode
)
1208 temp
= simplify_truncation (mode
, op
, GET_MODE (op
));
1213 /* If we know that the value is already truncated, we can
1214 replace the TRUNCATE with a SUBREG. */
1215 if (known_eq (GET_MODE_NUNITS (mode
), 1)
1216 && (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
))
1217 || truncated_to_mode (mode
, op
)))
1219 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1224 /* A truncate of a comparison can be replaced with a subreg if
1225 STORE_FLAG_VALUE permits. This is like the previous test,
1226 but it works even if the comparison is done in a mode larger
1227 than HOST_BITS_PER_WIDE_INT. */
1228 if (HWI_COMPUTABLE_MODE_P (mode
)
1229 && COMPARISON_P (op
)
1230 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
1232 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1237 /* A truncate of a memory is just loading the low part of the memory
1238 if we are not changing the meaning of the address. */
1239 if (GET_CODE (op
) == MEM
1240 && !VECTOR_MODE_P (mode
)
1241 && !MEM_VOLATILE_P (op
)
1242 && !mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
)))
1244 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1251 case FLOAT_TRUNCATE
:
1252 if (DECIMAL_FLOAT_MODE_P (mode
))
1255 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
1256 if (GET_CODE (op
) == FLOAT_EXTEND
1257 && GET_MODE (XEXP (op
, 0)) == mode
)
1258 return XEXP (op
, 0);
1260 /* (float_truncate:SF (float_truncate:DF foo:XF))
1261 = (float_truncate:SF foo:XF).
1262 This may eliminate double rounding, so it is unsafe.
1264 (float_truncate:SF (float_extend:XF foo:DF))
1265 = (float_truncate:SF foo:DF).
1267 (float_truncate:DF (float_extend:XF foo:SF))
1268 = (float_extend:DF foo:SF). */
1269 if ((GET_CODE (op
) == FLOAT_TRUNCATE
1270 && flag_unsafe_math_optimizations
)
1271 || GET_CODE (op
) == FLOAT_EXTEND
)
1272 return simplify_gen_unary (GET_MODE_UNIT_SIZE (GET_MODE (XEXP (op
, 0)))
1273 > GET_MODE_UNIT_SIZE (mode
)
1274 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
1276 XEXP (op
, 0), mode
);
1278 /* (float_truncate (float x)) is (float x) */
1279 if ((GET_CODE (op
) == FLOAT
|| GET_CODE (op
) == UNSIGNED_FLOAT
)
1280 && (flag_unsafe_math_optimizations
1281 || exact_int_to_float_conversion_p (op
)))
1282 return simplify_gen_unary (GET_CODE (op
), mode
,
1284 GET_MODE (XEXP (op
, 0)));
1286 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
1287 (OP:SF foo:SF) if OP is NEG or ABS. */
1288 if ((GET_CODE (op
) == ABS
1289 || GET_CODE (op
) == NEG
)
1290 && GET_CODE (XEXP (op
, 0)) == FLOAT_EXTEND
1291 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
1292 return simplify_gen_unary (GET_CODE (op
), mode
,
1293 XEXP (XEXP (op
, 0), 0), mode
);
1295 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
1296 is (float_truncate:SF x). */
1297 if (GET_CODE (op
) == SUBREG
1298 && subreg_lowpart_p (op
)
1299 && GET_CODE (SUBREG_REG (op
)) == FLOAT_TRUNCATE
)
1300 return SUBREG_REG (op
);
1304 if (DECIMAL_FLOAT_MODE_P (mode
))
1307 /* (float_extend (float_extend x)) is (float_extend x)
1309 (float_extend (float x)) is (float x) assuming that double
1310 rounding can't happen.
1312 if (GET_CODE (op
) == FLOAT_EXTEND
1313 || ((GET_CODE (op
) == FLOAT
|| GET_CODE (op
) == UNSIGNED_FLOAT
)
1314 && exact_int_to_float_conversion_p (op
)))
1315 return simplify_gen_unary (GET_CODE (op
), mode
,
1317 GET_MODE (XEXP (op
, 0)));
1322 /* (abs (neg <foo>)) -> (abs <foo>) */
1323 if (GET_CODE (op
) == NEG
)
1324 return simplify_gen_unary (ABS
, mode
, XEXP (op
, 0),
1325 GET_MODE (XEXP (op
, 0)));
1327 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
1329 if (GET_MODE (op
) == VOIDmode
)
1332 /* If operand is something known to be positive, ignore the ABS. */
1333 if (GET_CODE (op
) == FFS
|| GET_CODE (op
) == ABS
1334 || val_signbit_known_clear_p (GET_MODE (op
),
1335 nonzero_bits (op
, GET_MODE (op
))))
1338 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
1339 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
1340 && (num_sign_bit_copies (op
, int_mode
)
1341 == GET_MODE_PRECISION (int_mode
)))
1342 return gen_rtx_NEG (int_mode
, op
);
1347 /* (ffs (*_extend <X>)) = (ffs <X>) */
1348 if (GET_CODE (op
) == SIGN_EXTEND
1349 || GET_CODE (op
) == ZERO_EXTEND
)
1350 return simplify_gen_unary (FFS
, mode
, XEXP (op
, 0),
1351 GET_MODE (XEXP (op
, 0)));
1355 switch (GET_CODE (op
))
1359 /* (popcount (zero_extend <X>)) = (popcount <X>) */
1360 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1361 GET_MODE (XEXP (op
, 0)));
1365 /* Rotations don't affect popcount. */
1366 if (!side_effects_p (XEXP (op
, 1)))
1367 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1368 GET_MODE (XEXP (op
, 0)));
1377 switch (GET_CODE (op
))
1383 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1384 GET_MODE (XEXP (op
, 0)));
1388 /* Rotations don't affect parity. */
1389 if (!side_effects_p (XEXP (op
, 1)))
1390 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1391 GET_MODE (XEXP (op
, 0)));
1395 /* (parity (parity x)) -> parity (x). */
1404 /* (bswap (bswap x)) -> x. */
1405 if (GET_CODE (op
) == BSWAP
)
1406 return XEXP (op
, 0);
1410 /* (float (sign_extend <X>)) = (float <X>). */
1411 if (GET_CODE (op
) == SIGN_EXTEND
)
1412 return simplify_gen_unary (FLOAT
, mode
, XEXP (op
, 0),
1413 GET_MODE (XEXP (op
, 0)));
1417 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1418 becomes just the MINUS if its mode is MODE. This allows
1419 folding switch statements on machines using casesi (such as
1421 if (GET_CODE (op
) == TRUNCATE
1422 && GET_MODE (XEXP (op
, 0)) == mode
1423 && GET_CODE (XEXP (op
, 0)) == MINUS
1424 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
1425 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
1426 return XEXP (op
, 0);
1428 /* Extending a widening multiplication should be canonicalized to
1429 a wider widening multiplication. */
1430 if (GET_CODE (op
) == MULT
)
1432 rtx lhs
= XEXP (op
, 0);
1433 rtx rhs
= XEXP (op
, 1);
1434 enum rtx_code lcode
= GET_CODE (lhs
);
1435 enum rtx_code rcode
= GET_CODE (rhs
);
1437 /* Widening multiplies usually extend both operands, but sometimes
1438 they use a shift to extract a portion of a register. */
1439 if ((lcode
== SIGN_EXTEND
1440 || (lcode
== ASHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1441 && (rcode
== SIGN_EXTEND
1442 || (rcode
== ASHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1444 machine_mode lmode
= GET_MODE (lhs
);
1445 machine_mode rmode
= GET_MODE (rhs
);
1448 if (lcode
== ASHIFTRT
)
1449 /* Number of bits not shifted off the end. */
1450 bits
= (GET_MODE_UNIT_PRECISION (lmode
)
1451 - INTVAL (XEXP (lhs
, 1)));
1452 else /* lcode == SIGN_EXTEND */
1453 /* Size of inner mode. */
1454 bits
= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1456 if (rcode
== ASHIFTRT
)
1457 bits
+= (GET_MODE_UNIT_PRECISION (rmode
)
1458 - INTVAL (XEXP (rhs
, 1)));
1459 else /* rcode == SIGN_EXTEND */
1460 bits
+= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1462 /* We can only widen multiplies if the result is mathematiclly
1463 equivalent. I.e. if overflow was impossible. */
1464 if (bits
<= GET_MODE_UNIT_PRECISION (GET_MODE (op
)))
1465 return simplify_gen_binary
1467 simplify_gen_unary (SIGN_EXTEND
, mode
, lhs
, lmode
),
1468 simplify_gen_unary (SIGN_EXTEND
, mode
, rhs
, rmode
));
1472 /* Check for a sign extension of a subreg of a promoted
1473 variable, where the promotion is sign-extended, and the
1474 target mode is the same as the variable's promotion. */
1475 if (GET_CODE (op
) == SUBREG
1476 && SUBREG_PROMOTED_VAR_P (op
)
1477 && SUBREG_PROMOTED_SIGNED_P (op
)
1478 && !paradoxical_subreg_p (mode
, GET_MODE (SUBREG_REG (op
))))
1480 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, SUBREG_REG (op
));
1485 /* (sign_extend:M (sign_extend:N <X>)) is (sign_extend:M <X>).
1486 (sign_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1487 if (GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
)
1489 gcc_assert (GET_MODE_UNIT_PRECISION (mode
)
1490 > GET_MODE_UNIT_PRECISION (GET_MODE (op
)));
1491 return simplify_gen_unary (GET_CODE (op
), mode
, XEXP (op
, 0),
1492 GET_MODE (XEXP (op
, 0)));
1495 /* (sign_extend:M (ashiftrt:N (ashift <X> (const_int I)) (const_int I)))
1496 is (sign_extend:M (subreg:O <X>)) if there is mode with
1497 GET_MODE_BITSIZE (N) - I bits.
1498 (sign_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1499 is similarly (zero_extend:M (subreg:O <X>)). */
1500 if ((GET_CODE (op
) == ASHIFTRT
|| GET_CODE (op
) == LSHIFTRT
)
1501 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1502 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1503 && CONST_INT_P (XEXP (op
, 1))
1504 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1505 && (op_mode
= as_a
<scalar_int_mode
> (GET_MODE (op
)),
1506 GET_MODE_PRECISION (op_mode
) > INTVAL (XEXP (op
, 1))))
1508 scalar_int_mode tmode
;
1509 gcc_assert (GET_MODE_PRECISION (int_mode
)
1510 > GET_MODE_PRECISION (op_mode
));
1511 if (int_mode_for_size (GET_MODE_PRECISION (op_mode
)
1512 - INTVAL (XEXP (op
, 1)), 1).exists (&tmode
))
1515 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1517 return simplify_gen_unary (GET_CODE (op
) == ASHIFTRT
1518 ? SIGN_EXTEND
: ZERO_EXTEND
,
1519 int_mode
, inner
, tmode
);
1523 /* (sign_extend:M (lshiftrt:N <X> (const_int I))) is better as
1524 (zero_extend:M (lshiftrt:N <X> (const_int I))) if I is not 0. */
1525 if (GET_CODE (op
) == LSHIFTRT
1526 && CONST_INT_P (XEXP (op
, 1))
1527 && XEXP (op
, 1) != const0_rtx
)
1528 return simplify_gen_unary (ZERO_EXTEND
, mode
, op
, GET_MODE (op
));
1530 /* (sign_extend:M (truncate:N (lshiftrt:O <X> (const_int I)))) where
1531 I is GET_MODE_PRECISION(O) - GET_MODE_PRECISION(N), simplifies to
1532 (ashiftrt:M <X> (const_int I)) if modes M and O are the same, and
1533 (truncate:M (ashiftrt:O <X> (const_int I))) if M is narrower than
1534 O, and (sign_extend:M (ashiftrt:O <X> (const_int I))) if M is
1536 if (GET_CODE (op
) == TRUNCATE
1537 && GET_CODE (XEXP (op
, 0)) == LSHIFTRT
1538 && CONST_INT_P (XEXP (XEXP (op
, 0), 1)))
1540 scalar_int_mode m_mode
, n_mode
, o_mode
;
1541 rtx old_shift
= XEXP (op
, 0);
1542 if (is_a
<scalar_int_mode
> (mode
, &m_mode
)
1543 && is_a
<scalar_int_mode
> (GET_MODE (op
), &n_mode
)
1544 && is_a
<scalar_int_mode
> (GET_MODE (old_shift
), &o_mode
)
1545 && GET_MODE_PRECISION (o_mode
) - GET_MODE_PRECISION (n_mode
)
1546 == INTVAL (XEXP (old_shift
, 1)))
1548 rtx new_shift
= simplify_gen_binary (ASHIFTRT
,
1549 GET_MODE (old_shift
),
1550 XEXP (old_shift
, 0),
1551 XEXP (old_shift
, 1));
1552 if (GET_MODE_PRECISION (m_mode
) > GET_MODE_PRECISION (o_mode
))
1553 return simplify_gen_unary (SIGN_EXTEND
, mode
, new_shift
,
1554 GET_MODE (new_shift
));
1555 if (mode
!= GET_MODE (new_shift
))
1556 return simplify_gen_unary (TRUNCATE
, mode
, new_shift
,
1557 GET_MODE (new_shift
));
1562 #if defined(POINTERS_EXTEND_UNSIGNED)
1563 /* As we do not know which address space the pointer is referring to,
1564 we can do this only if the target does not support different pointer
1565 or address modes depending on the address space. */
1566 if (target_default_pointer_address_modes_p ()
1567 && ! POINTERS_EXTEND_UNSIGNED
1568 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1570 || (GET_CODE (op
) == SUBREG
1571 && REG_P (SUBREG_REG (op
))
1572 && REG_POINTER (SUBREG_REG (op
))
1573 && GET_MODE (SUBREG_REG (op
)) == Pmode
))
1574 && !targetm
.have_ptr_extend ())
1577 = convert_memory_address_addr_space_1 (Pmode
, op
,
1578 ADDR_SPACE_GENERIC
, false,
1587 /* Check for a zero extension of a subreg of a promoted
1588 variable, where the promotion is zero-extended, and the
1589 target mode is the same as the variable's promotion. */
1590 if (GET_CODE (op
) == SUBREG
1591 && SUBREG_PROMOTED_VAR_P (op
)
1592 && SUBREG_PROMOTED_UNSIGNED_P (op
)
1593 && !paradoxical_subreg_p (mode
, GET_MODE (SUBREG_REG (op
))))
1595 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, SUBREG_REG (op
));
1600 /* Extending a widening multiplication should be canonicalized to
1601 a wider widening multiplication. */
1602 if (GET_CODE (op
) == MULT
)
1604 rtx lhs
= XEXP (op
, 0);
1605 rtx rhs
= XEXP (op
, 1);
1606 enum rtx_code lcode
= GET_CODE (lhs
);
1607 enum rtx_code rcode
= GET_CODE (rhs
);
1609 /* Widening multiplies usually extend both operands, but sometimes
1610 they use a shift to extract a portion of a register. */
1611 if ((lcode
== ZERO_EXTEND
1612 || (lcode
== LSHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1613 && (rcode
== ZERO_EXTEND
1614 || (rcode
== LSHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1616 machine_mode lmode
= GET_MODE (lhs
);
1617 machine_mode rmode
= GET_MODE (rhs
);
1620 if (lcode
== LSHIFTRT
)
1621 /* Number of bits not shifted off the end. */
1622 bits
= (GET_MODE_UNIT_PRECISION (lmode
)
1623 - INTVAL (XEXP (lhs
, 1)));
1624 else /* lcode == ZERO_EXTEND */
1625 /* Size of inner mode. */
1626 bits
= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1628 if (rcode
== LSHIFTRT
)
1629 bits
+= (GET_MODE_UNIT_PRECISION (rmode
)
1630 - INTVAL (XEXP (rhs
, 1)));
1631 else /* rcode == ZERO_EXTEND */
1632 bits
+= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1634 /* We can only widen multiplies if the result is mathematiclly
1635 equivalent. I.e. if overflow was impossible. */
1636 if (bits
<= GET_MODE_UNIT_PRECISION (GET_MODE (op
)))
1637 return simplify_gen_binary
1639 simplify_gen_unary (ZERO_EXTEND
, mode
, lhs
, lmode
),
1640 simplify_gen_unary (ZERO_EXTEND
, mode
, rhs
, rmode
));
1644 /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1645 if (GET_CODE (op
) == ZERO_EXTEND
)
1646 return simplify_gen_unary (ZERO_EXTEND
, mode
, XEXP (op
, 0),
1647 GET_MODE (XEXP (op
, 0)));
1649 /* (zero_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1650 is (zero_extend:M (subreg:O <X>)) if there is mode with
1651 GET_MODE_PRECISION (N) - I bits. */
1652 if (GET_CODE (op
) == LSHIFTRT
1653 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1654 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1655 && CONST_INT_P (XEXP (op
, 1))
1656 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1657 && (op_mode
= as_a
<scalar_int_mode
> (GET_MODE (op
)),
1658 GET_MODE_PRECISION (op_mode
) > INTVAL (XEXP (op
, 1))))
1660 scalar_int_mode tmode
;
1661 if (int_mode_for_size (GET_MODE_PRECISION (op_mode
)
1662 - INTVAL (XEXP (op
, 1)), 1).exists (&tmode
))
1665 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1667 return simplify_gen_unary (ZERO_EXTEND
, int_mode
,
1672 /* (zero_extend:M (subreg:N <X:O>)) is <X:O> (for M == O) or
1673 (zero_extend:M <X:O>), if X doesn't have any non-zero bits outside
1675 (zero_extend:SI (subreg:QI (and:SI (reg:SI) (const_int 63)) 0)) is
1676 (and:SI (reg:SI) (const_int 63)). */
1677 if (partial_subreg_p (op
)
1678 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1679 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op
)), &op0_mode
)
1680 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
1681 && GET_MODE_PRECISION (int_mode
) >= GET_MODE_PRECISION (op0_mode
)
1682 && subreg_lowpart_p (op
)
1683 && (nonzero_bits (SUBREG_REG (op
), op0_mode
)
1684 & ~GET_MODE_MASK (GET_MODE (op
))) == 0)
1686 if (GET_MODE_PRECISION (int_mode
) == GET_MODE_PRECISION (op0_mode
))
1687 return SUBREG_REG (op
);
1688 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, SUBREG_REG (op
),
1692 #if defined(POINTERS_EXTEND_UNSIGNED)
1693 /* As we do not know which address space the pointer is referring to,
1694 we can do this only if the target does not support different pointer
1695 or address modes depending on the address space. */
1696 if (target_default_pointer_address_modes_p ()
1697 && POINTERS_EXTEND_UNSIGNED
> 0
1698 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1700 || (GET_CODE (op
) == SUBREG
1701 && REG_P (SUBREG_REG (op
))
1702 && REG_POINTER (SUBREG_REG (op
))
1703 && GET_MODE (SUBREG_REG (op
)) == Pmode
))
1704 && !targetm
.have_ptr_extend ())
1707 = convert_memory_address_addr_space_1 (Pmode
, op
,
1708 ADDR_SPACE_GENERIC
, false,
1720 if (VECTOR_MODE_P (mode
)
1721 && vec_duplicate_p (op
, &elt
)
1722 && code
!= VEC_DUPLICATE
)
1724 /* Try applying the operator to ELT and see if that simplifies.
1725 We can duplicate the result if so.
1727 The reason we don't use simplify_gen_unary is that it isn't
1728 necessarily a win to convert things like:
1730 (neg:V (vec_duplicate:V (reg:S R)))
1734 (vec_duplicate:V (neg:S (reg:S R)))
1736 The first might be done entirely in vector registers while the
1737 second might need a move between register files. */
1738 temp
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1739 elt
, GET_MODE_INNER (GET_MODE (op
)));
1741 return gen_vec_duplicate (mode
, temp
);
1747 /* Try to compute the value of a unary operation CODE whose output mode is to
1748 be MODE with input operand OP whose mode was originally OP_MODE.
1749 Return zero if the value cannot be computed. */
1751 simplify_const_unary_operation (enum rtx_code code
, machine_mode mode
,
1752 rtx op
, machine_mode op_mode
)
1754 scalar_int_mode result_mode
;
1756 if (code
== VEC_DUPLICATE
)
1758 gcc_assert (VECTOR_MODE_P (mode
));
1759 if (GET_MODE (op
) != VOIDmode
)
1761 if (!VECTOR_MODE_P (GET_MODE (op
)))
1762 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE (op
));
1764 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE_INNER
1767 if (CONST_SCALAR_INT_P (op
) || CONST_DOUBLE_AS_FLOAT_P (op
))
1768 return gen_const_vec_duplicate (mode
, op
);
1769 if (GET_CODE (op
) == CONST_VECTOR
1770 && (CONST_VECTOR_DUPLICATE_P (op
)
1771 || CONST_VECTOR_NUNITS (op
).is_constant ()))
1773 unsigned int npatterns
= (CONST_VECTOR_DUPLICATE_P (op
)
1774 ? CONST_VECTOR_NPATTERNS (op
)
1775 : CONST_VECTOR_NUNITS (op
).to_constant ());
1776 gcc_assert (multiple_p (GET_MODE_NUNITS (mode
), npatterns
));
1777 rtx_vector_builder
builder (mode
, npatterns
, 1);
1778 for (unsigned i
= 0; i
< npatterns
; i
++)
1779 builder
.quick_push (CONST_VECTOR_ELT (op
, i
));
1780 return builder
.build ();
1784 if (VECTOR_MODE_P (mode
)
1785 && GET_CODE (op
) == CONST_VECTOR
1786 && known_eq (GET_MODE_NUNITS (mode
), CONST_VECTOR_NUNITS (op
)))
1788 gcc_assert (GET_MODE (op
) == op_mode
);
1790 rtx_vector_builder builder
;
1791 if (!builder
.new_unary_operation (mode
, op
, false))
1794 unsigned int count
= builder
.encoded_nelts ();
1795 for (unsigned int i
= 0; i
< count
; i
++)
1797 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1798 CONST_VECTOR_ELT (op
, i
),
1799 GET_MODE_INNER (op_mode
));
1800 if (!x
|| !valid_for_const_vector_p (mode
, x
))
1802 builder
.quick_push (x
);
1804 return builder
.build ();
1807 /* The order of these tests is critical so that, for example, we don't
1808 check the wrong mode (input vs. output) for a conversion operation,
1809 such as FIX. At some point, this should be simplified. */
1811 if (code
== FLOAT
&& CONST_SCALAR_INT_P (op
))
1815 if (op_mode
== VOIDmode
)
1817 /* CONST_INT have VOIDmode as the mode. We assume that all
1818 the bits of the constant are significant, though, this is
1819 a dangerous assumption as many times CONST_INTs are
1820 created and used with garbage in the bits outside of the
1821 precision of the implied mode of the const_int. */
1822 op_mode
= MAX_MODE_INT
;
1825 real_from_integer (&d
, mode
, rtx_mode_t (op
, op_mode
), SIGNED
);
1827 /* Avoid the folding if flag_signaling_nans is on and
1828 operand is a signaling NaN. */
1829 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1832 d
= real_value_truncate (mode
, d
);
1833 return const_double_from_real_value (d
, mode
);
1835 else if (code
== UNSIGNED_FLOAT
&& CONST_SCALAR_INT_P (op
))
1839 if (op_mode
== VOIDmode
)
1841 /* CONST_INT have VOIDmode as the mode. We assume that all
1842 the bits of the constant are significant, though, this is
1843 a dangerous assumption as many times CONST_INTs are
1844 created and used with garbage in the bits outside of the
1845 precision of the implied mode of the const_int. */
1846 op_mode
= MAX_MODE_INT
;
1849 real_from_integer (&d
, mode
, rtx_mode_t (op
, op_mode
), UNSIGNED
);
1851 /* Avoid the folding if flag_signaling_nans is on and
1852 operand is a signaling NaN. */
1853 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1856 d
= real_value_truncate (mode
, d
);
1857 return const_double_from_real_value (d
, mode
);
1860 if (CONST_SCALAR_INT_P (op
) && is_a
<scalar_int_mode
> (mode
, &result_mode
))
1862 unsigned int width
= GET_MODE_PRECISION (result_mode
);
1863 if (width
> MAX_BITSIZE_MODE_ANY_INT
)
1867 scalar_int_mode imode
= (op_mode
== VOIDmode
1869 : as_a
<scalar_int_mode
> (op_mode
));
1870 rtx_mode_t op0
= rtx_mode_t (op
, imode
);
1873 #if TARGET_SUPPORTS_WIDE_INT == 0
1874 /* This assert keeps the simplification from producing a result
1875 that cannot be represented in a CONST_DOUBLE but a lot of
1876 upstream callers expect that this function never fails to
1877 simplify something and so you if you added this to the test
1878 above the code would die later anyway. If this assert
1879 happens, you just need to make the port support wide int. */
1880 gcc_assert (width
<= HOST_BITS_PER_DOUBLE_INT
);
1886 result
= wi::bit_not (op0
);
1890 result
= wi::neg (op0
);
1894 result
= wi::abs (op0
);
1898 result
= wi::shwi (wi::ffs (op0
), result_mode
);
1902 if (wi::ne_p (op0
, 0))
1903 int_value
= wi::clz (op0
);
1904 else if (! CLZ_DEFINED_VALUE_AT_ZERO (imode
, int_value
))
1906 result
= wi::shwi (int_value
, result_mode
);
1910 result
= wi::shwi (wi::clrsb (op0
), result_mode
);
1914 if (wi::ne_p (op0
, 0))
1915 int_value
= wi::ctz (op0
);
1916 else if (! CTZ_DEFINED_VALUE_AT_ZERO (imode
, int_value
))
1918 result
= wi::shwi (int_value
, result_mode
);
1922 result
= wi::shwi (wi::popcount (op0
), result_mode
);
1926 result
= wi::shwi (wi::parity (op0
), result_mode
);
1930 result
= wide_int (op0
).bswap ();
1935 result
= wide_int::from (op0
, width
, UNSIGNED
);
1939 result
= wide_int::from (op0
, width
, SIGNED
);
1947 return immed_wide_int_const (result
, result_mode
);
1950 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
1951 && SCALAR_FLOAT_MODE_P (mode
)
1952 && SCALAR_FLOAT_MODE_P (GET_MODE (op
)))
1954 REAL_VALUE_TYPE d
= *CONST_DOUBLE_REAL_VALUE (op
);
1960 d
= real_value_abs (&d
);
1963 d
= real_value_negate (&d
);
1965 case FLOAT_TRUNCATE
:
1966 /* Don't perform the operation if flag_signaling_nans is on
1967 and the operand is a signaling NaN. */
1968 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1970 d
= real_value_truncate (mode
, d
);
1973 /* Don't perform the operation if flag_signaling_nans is on
1974 and the operand is a signaling NaN. */
1975 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1977 /* All this does is change the mode, unless changing
1979 if (GET_MODE_CLASS (mode
) != GET_MODE_CLASS (GET_MODE (op
)))
1980 real_convert (&d
, mode
, &d
);
1983 /* Don't perform the operation if flag_signaling_nans is on
1984 and the operand is a signaling NaN. */
1985 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1987 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
1994 real_to_target (tmp
, &d
, GET_MODE (op
));
1995 for (i
= 0; i
< 4; i
++)
1997 real_from_target (&d
, tmp
, mode
);
2003 return const_double_from_real_value (d
, mode
);
2005 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
2006 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
2007 && is_int_mode (mode
, &result_mode
))
2009 unsigned int width
= GET_MODE_PRECISION (result_mode
);
2010 if (width
> MAX_BITSIZE_MODE_ANY_INT
)
2013 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
2014 operators are intentionally left unspecified (to ease implementation
2015 by target backends), for consistency, this routine implements the
2016 same semantics for constant folding as used by the middle-end. */
2018 /* This was formerly used only for non-IEEE float.
2019 eggert@twinsun.com says it is safe for IEEE also. */
2021 const REAL_VALUE_TYPE
*x
= CONST_DOUBLE_REAL_VALUE (op
);
2022 wide_int wmax
, wmin
;
2023 /* This is part of the abi to real_to_integer, but we check
2024 things before making this call. */
2030 if (REAL_VALUE_ISNAN (*x
))
2033 /* Test against the signed upper bound. */
2034 wmax
= wi::max_value (width
, SIGNED
);
2035 real_from_integer (&t
, VOIDmode
, wmax
, SIGNED
);
2036 if (real_less (&t
, x
))
2037 return immed_wide_int_const (wmax
, mode
);
2039 /* Test against the signed lower bound. */
2040 wmin
= wi::min_value (width
, SIGNED
);
2041 real_from_integer (&t
, VOIDmode
, wmin
, SIGNED
);
2042 if (real_less (x
, &t
))
2043 return immed_wide_int_const (wmin
, mode
);
2045 return immed_wide_int_const (real_to_integer (x
, &fail
, width
),
2049 if (REAL_VALUE_ISNAN (*x
) || REAL_VALUE_NEGATIVE (*x
))
2052 /* Test against the unsigned upper bound. */
2053 wmax
= wi::max_value (width
, UNSIGNED
);
2054 real_from_integer (&t
, VOIDmode
, wmax
, UNSIGNED
);
2055 if (real_less (&t
, x
))
2056 return immed_wide_int_const (wmax
, mode
);
2058 return immed_wide_int_const (real_to_integer (x
, &fail
, width
),
2066 /* Handle polynomial integers. */
2067 else if (CONST_POLY_INT_P (op
))
2069 poly_wide_int result
;
2073 result
= -const_poly_int_value (op
);
2077 result
= ~const_poly_int_value (op
);
2083 return immed_wide_int_const (result
, mode
);
2089 /* Subroutine of simplify_binary_operation to simplify a binary operation
2090 CODE that can commute with byte swapping, with result mode MODE and
2091 operating on OP0 and OP1. CODE is currently one of AND, IOR or XOR.
2092 Return zero if no simplification or canonicalization is possible. */
2095 simplify_byte_swapping_operation (enum rtx_code code
, machine_mode mode
,
2100 /* (op (bswap x) C1)) -> (bswap (op x C2)) with C2 swapped. */
2101 if (GET_CODE (op0
) == BSWAP
&& CONST_SCALAR_INT_P (op1
))
2103 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0),
2104 simplify_gen_unary (BSWAP
, mode
, op1
, mode
));
2105 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
2108 /* (op (bswap x) (bswap y)) -> (bswap (op x y)). */
2109 if (GET_CODE (op0
) == BSWAP
&& GET_CODE (op1
) == BSWAP
)
2111 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2112 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
2118 /* Subroutine of simplify_binary_operation to simplify a commutative,
2119 associative binary operation CODE with result mode MODE, operating
2120 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
2121 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
2122 canonicalization is possible. */
2125 simplify_associative_operation (enum rtx_code code
, machine_mode mode
,
2130 /* Linearize the operator to the left. */
2131 if (GET_CODE (op1
) == code
)
2133 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
2134 if (GET_CODE (op0
) == code
)
2136 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
2137 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
2140 /* "a op (b op c)" becomes "(b op c) op a". */
2141 if (! swap_commutative_operands_p (op1
, op0
))
2142 return simplify_gen_binary (code
, mode
, op1
, op0
);
2144 std::swap (op0
, op1
);
2147 if (GET_CODE (op0
) == code
)
2149 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
2150 if (swap_commutative_operands_p (XEXP (op0
, 1), op1
))
2152 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
2153 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2156 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
2157 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
2159 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
2161 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
2162 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 0), op1
);
2164 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2170 /* Return a mask describing the COMPARISON. */
2172 comparison_to_mask (enum rtx_code comparison
)
2212 /* Return a comparison corresponding to the MASK. */
2213 static enum rtx_code
2214 mask_to_comparison (int mask
)
2254 /* Return true if CODE is valid for comparisons of mode MODE, false
2257 It is always safe to return false, even if the code was valid for the
2258 given mode as that will merely suppress optimizations. */
2261 comparison_code_valid_for_mode (enum rtx_code code
, enum machine_mode mode
)
2265 /* These are valid for integral, floating and vector modes. */
2272 return (INTEGRAL_MODE_P (mode
)
2273 || FLOAT_MODE_P (mode
)
2274 || VECTOR_MODE_P (mode
));
2276 /* These are valid for floating point modes. */
2285 return FLOAT_MODE_P (mode
);
2287 /* These are filtered out in simplify_logical_operation, but
2288 we check for them too as a matter of safety. They are valid
2289 for integral and vector modes. */
2294 return INTEGRAL_MODE_P (mode
) || VECTOR_MODE_P (mode
);
2301 /* Simplify a logical operation CODE with result mode MODE, operating on OP0
2302 and OP1, which should be both relational operations. Return 0 if no such
2303 simplification is possible. */
2305 simplify_logical_relational_operation (enum rtx_code code
, machine_mode mode
,
2308 /* We only handle IOR of two relational operations. */
2312 if (!(COMPARISON_P (op0
) && COMPARISON_P (op1
)))
2315 if (!(rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2316 && rtx_equal_p (XEXP (op0
, 1), XEXP (op1
, 1))))
2319 enum rtx_code code0
= GET_CODE (op0
);
2320 enum rtx_code code1
= GET_CODE (op1
);
2322 /* We don't handle unsigned comparisons currently. */
2323 if (code0
== LTU
|| code0
== GTU
|| code0
== LEU
|| code0
== GEU
)
2325 if (code1
== LTU
|| code1
== GTU
|| code1
== LEU
|| code1
== GEU
)
2328 int mask0
= comparison_to_mask (code0
);
2329 int mask1
= comparison_to_mask (code1
);
2331 int mask
= mask0
| mask1
;
2334 return const_true_rtx
;
2336 code
= mask_to_comparison (mask
);
2338 /* Many comparison codes are only valid for certain mode classes. */
2339 if (!comparison_code_valid_for_mode (code
, mode
))
2342 op0
= XEXP (op1
, 0);
2343 op1
= XEXP (op1
, 1);
2345 return simplify_gen_relational (code
, mode
, VOIDmode
, op0
, op1
);
2348 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
2349 and OP1. Return 0 if no simplification is possible.
2351 Don't use this for relational operations such as EQ or LT.
2352 Use simplify_relational_operation instead. */
2354 simplify_binary_operation (enum rtx_code code
, machine_mode mode
,
2357 rtx trueop0
, trueop1
;
2360 /* Relational operations don't work here. We must know the mode
2361 of the operands in order to do the comparison correctly.
2362 Assuming a full word can give incorrect results.
2363 Consider comparing 128 with -128 in QImode. */
2364 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMPARE
);
2365 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
);
2367 /* Make sure the constant is second. */
2368 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
2369 && swap_commutative_operands_p (op0
, op1
))
2370 std::swap (op0
, op1
);
2372 trueop0
= avoid_constant_pool_reference (op0
);
2373 trueop1
= avoid_constant_pool_reference (op1
);
2375 tem
= simplify_const_binary_operation (code
, mode
, trueop0
, trueop1
);
2378 tem
= simplify_binary_operation_1 (code
, mode
, op0
, op1
, trueop0
, trueop1
);
2383 /* If the above steps did not result in a simplification and op0 or op1
2384 were constant pool references, use the referenced constants directly. */
2385 if (trueop0
!= op0
|| trueop1
!= op1
)
2386 return simplify_gen_binary (code
, mode
, trueop0
, trueop1
);
2391 /* Subroutine of simplify_binary_operation_1 that looks for cases in
2392 which OP0 and OP1 are both vector series or vector duplicates
2393 (which are really just series with a step of 0). If so, try to
2394 form a new series by applying CODE to the bases and to the steps.
2395 Return null if no simplification is possible.
2397 MODE is the mode of the operation and is known to be a vector
2401 simplify_binary_operation_series (rtx_code code
, machine_mode mode
,
2405 if (vec_duplicate_p (op0
, &base0
))
2407 else if (!vec_series_p (op0
, &base0
, &step0
))
2411 if (vec_duplicate_p (op1
, &base1
))
2413 else if (!vec_series_p (op1
, &base1
, &step1
))
2416 /* Only create a new series if we can simplify both parts. In other
2417 cases this isn't really a simplification, and it's not necessarily
2418 a win to replace a vector operation with a scalar operation. */
2419 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
2420 rtx new_base
= simplify_binary_operation (code
, inner_mode
, base0
, base1
);
2424 rtx new_step
= simplify_binary_operation (code
, inner_mode
, step0
, step1
);
2428 return gen_vec_series (mode
, new_base
, new_step
);
2431 /* Subroutine of simplify_binary_operation_1. Un-distribute a binary
2432 operation CODE with result mode MODE, operating on OP0 and OP1.
2433 e.g. simplify (xor (and A C) (and (B C)) to (and (xor (A B) C).
2434 Returns NULL_RTX if no simplification is possible. */
2437 simplify_distributive_operation (enum rtx_code code
, machine_mode mode
,
2440 enum rtx_code op
= GET_CODE (op0
);
2441 gcc_assert (GET_CODE (op1
) == op
);
2443 if (rtx_equal_p (XEXP (op0
, 1), XEXP (op1
, 1))
2444 && ! side_effects_p (XEXP (op0
, 1)))
2445 return simplify_gen_binary (op
, mode
,
2446 simplify_gen_binary (code
, mode
,
2451 if (GET_RTX_CLASS (op
) == RTX_COMM_ARITH
)
2453 if (rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2454 && ! side_effects_p (XEXP (op0
, 0)))
2455 return simplify_gen_binary (op
, mode
,
2456 simplify_gen_binary (code
, mode
,
2460 if (rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 1))
2461 && ! side_effects_p (XEXP (op0
, 0)))
2462 return simplify_gen_binary (op
, mode
,
2463 simplify_gen_binary (code
, mode
,
2467 if (rtx_equal_p (XEXP (op0
, 1), XEXP (op1
, 0))
2468 && ! side_effects_p (XEXP (op0
, 1)))
2469 return simplify_gen_binary (op
, mode
,
2470 simplify_gen_binary (code
, mode
,
2479 /* Subroutine of simplify_binary_operation. Simplify a binary operation
2480 CODE with result mode MODE, operating on OP0 and OP1. If OP0 and/or
2481 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
2482 actual constants. */
2485 simplify_binary_operation_1 (enum rtx_code code
, machine_mode mode
,
2486 rtx op0
, rtx op1
, rtx trueop0
, rtx trueop1
)
2488 rtx tem
, reversed
, opleft
, opright
, elt0
, elt1
;
2490 scalar_int_mode int_mode
, inner_mode
;
2493 /* Even if we can't compute a constant result,
2494 there are some cases worth simplifying. */
2499 /* Maybe simplify x + 0 to x. The two expressions are equivalent
2500 when x is NaN, infinite, or finite and nonzero. They aren't
2501 when x is -0 and the rounding mode is not towards -infinity,
2502 since (-0) + 0 is then 0. */
2503 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
2506 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
2507 transformations are safe even for IEEE. */
2508 if (GET_CODE (op0
) == NEG
)
2509 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
2510 else if (GET_CODE (op1
) == NEG
)
2511 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
2513 /* (~a) + 1 -> -a */
2514 if (INTEGRAL_MODE_P (mode
)
2515 && GET_CODE (op0
) == NOT
2516 && trueop1
== const1_rtx
)
2517 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
2519 /* Handle both-operands-constant cases. We can only add
2520 CONST_INTs to constants since the sum of relocatable symbols
2521 can't be handled by most assemblers. Don't add CONST_INT
2522 to CONST_INT since overflow won't be computed properly if wider
2523 than HOST_BITS_PER_WIDE_INT. */
2525 if ((GET_CODE (op0
) == CONST
2526 || GET_CODE (op0
) == SYMBOL_REF
2527 || GET_CODE (op0
) == LABEL_REF
)
2528 && poly_int_rtx_p (op1
, &offset
))
2529 return plus_constant (mode
, op0
, offset
);
2530 else if ((GET_CODE (op1
) == CONST
2531 || GET_CODE (op1
) == SYMBOL_REF
2532 || GET_CODE (op1
) == LABEL_REF
)
2533 && poly_int_rtx_p (op0
, &offset
))
2534 return plus_constant (mode
, op1
, offset
);
2536 /* See if this is something like X * C - X or vice versa or
2537 if the multiplication is written as a shift. If so, we can
2538 distribute and make a new multiply, shift, or maybe just
2539 have X (if C is 2 in the example above). But don't make
2540 something more expensive than we had before. */
2542 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2544 rtx lhs
= op0
, rhs
= op1
;
2546 wide_int coeff0
= wi::one (GET_MODE_PRECISION (int_mode
));
2547 wide_int coeff1
= wi::one (GET_MODE_PRECISION (int_mode
));
2549 if (GET_CODE (lhs
) == NEG
)
2551 coeff0
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2552 lhs
= XEXP (lhs
, 0);
2554 else if (GET_CODE (lhs
) == MULT
2555 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
2557 coeff0
= rtx_mode_t (XEXP (lhs
, 1), int_mode
);
2558 lhs
= XEXP (lhs
, 0);
2560 else if (GET_CODE (lhs
) == ASHIFT
2561 && CONST_INT_P (XEXP (lhs
, 1))
2562 && INTVAL (XEXP (lhs
, 1)) >= 0
2563 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2565 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
2566 GET_MODE_PRECISION (int_mode
));
2567 lhs
= XEXP (lhs
, 0);
2570 if (GET_CODE (rhs
) == NEG
)
2572 coeff1
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2573 rhs
= XEXP (rhs
, 0);
2575 else if (GET_CODE (rhs
) == MULT
2576 && CONST_INT_P (XEXP (rhs
, 1)))
2578 coeff1
= rtx_mode_t (XEXP (rhs
, 1), int_mode
);
2579 rhs
= XEXP (rhs
, 0);
2581 else if (GET_CODE (rhs
) == ASHIFT
2582 && CONST_INT_P (XEXP (rhs
, 1))
2583 && INTVAL (XEXP (rhs
, 1)) >= 0
2584 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2586 coeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
2587 GET_MODE_PRECISION (int_mode
));
2588 rhs
= XEXP (rhs
, 0);
2591 if (rtx_equal_p (lhs
, rhs
))
2593 rtx orig
= gen_rtx_PLUS (int_mode
, op0
, op1
);
2595 bool speed
= optimize_function_for_speed_p (cfun
);
2597 coeff
= immed_wide_int_const (coeff0
+ coeff1
, int_mode
);
2599 tem
= simplify_gen_binary (MULT
, int_mode
, lhs
, coeff
);
2600 return (set_src_cost (tem
, int_mode
, speed
)
2601 <= set_src_cost (orig
, int_mode
, speed
) ? tem
: 0);
2605 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
2606 if (CONST_SCALAR_INT_P (op1
)
2607 && GET_CODE (op0
) == XOR
2608 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
2609 && mode_signbit_p (mode
, op1
))
2610 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2611 simplify_gen_binary (XOR
, mode
, op1
,
2614 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). */
2615 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2616 && GET_CODE (op0
) == MULT
2617 && GET_CODE (XEXP (op0
, 0)) == NEG
)
2621 in1
= XEXP (XEXP (op0
, 0), 0);
2622 in2
= XEXP (op0
, 1);
2623 return simplify_gen_binary (MINUS
, mode
, op1
,
2624 simplify_gen_binary (MULT
, mode
,
2628 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
2629 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
2631 if (COMPARISON_P (op0
)
2632 && ((STORE_FLAG_VALUE
== -1 && trueop1
== const1_rtx
)
2633 || (STORE_FLAG_VALUE
== 1 && trueop1
== constm1_rtx
))
2634 && (reversed
= reversed_comparison (op0
, mode
)))
2636 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
2638 /* If one of the operands is a PLUS or a MINUS, see if we can
2639 simplify this by the associative law.
2640 Don't use the associative law for floating point.
2641 The inaccuracy makes it nonassociative,
2642 and subtle programs can break if operations are associated. */
2644 if (INTEGRAL_MODE_P (mode
)
2645 && (plus_minus_operand_p (op0
)
2646 || plus_minus_operand_p (op1
))
2647 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2650 /* Reassociate floating point addition only when the user
2651 specifies associative math operations. */
2652 if (FLOAT_MODE_P (mode
)
2653 && flag_associative_math
)
2655 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2660 /* Handle vector series. */
2661 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
2663 tem
= simplify_binary_operation_series (code
, mode
, op0
, op1
);
2670 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
2671 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
2672 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
2673 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
2675 rtx xop00
= XEXP (op0
, 0);
2676 rtx xop10
= XEXP (op1
, 0);
2678 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
2681 if (REG_P (xop00
) && REG_P (xop10
)
2682 && REGNO (xop00
) == REGNO (xop10
)
2683 && GET_MODE (xop00
) == mode
2684 && GET_MODE (xop10
) == mode
2685 && GET_MODE_CLASS (mode
) == MODE_CC
)
2691 /* We can't assume x-x is 0 even with non-IEEE floating point,
2692 but since it is zero except in very strange circumstances, we
2693 will treat it as zero with -ffinite-math-only. */
2694 if (rtx_equal_p (trueop0
, trueop1
)
2695 && ! side_effects_p (op0
)
2696 && (!FLOAT_MODE_P (mode
) || !HONOR_NANS (mode
)))
2697 return CONST0_RTX (mode
);
2699 /* Change subtraction from zero into negation. (0 - x) is the
2700 same as -x when x is NaN, infinite, or finite and nonzero.
2701 But if the mode has signed zeros, and does not round towards
2702 -infinity, then 0 - 0 is 0, not -0. */
2703 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
2704 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
2706 /* (-1 - a) is ~a, unless the expression contains symbolic
2707 constants, in which case not retaining additions and
2708 subtractions could cause invalid assembly to be produced. */
2709 if (trueop0
== constm1_rtx
2710 && !contains_symbolic_reference_p (op1
))
2711 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
2713 /* Subtracting 0 has no effect unless the mode has signalling NaNs,
2714 or has signed zeros and supports rounding towards -infinity.
2715 In such a case, 0 - 0 is -0. */
2716 if (!(HONOR_SIGNED_ZEROS (mode
)
2717 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
2718 && !HONOR_SNANS (mode
)
2719 && trueop1
== CONST0_RTX (mode
))
2722 /* See if this is something like X * C - X or vice versa or
2723 if the multiplication is written as a shift. If so, we can
2724 distribute and make a new multiply, shift, or maybe just
2725 have X (if C is 2 in the example above). But don't make
2726 something more expensive than we had before. */
2728 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2730 rtx lhs
= op0
, rhs
= op1
;
2732 wide_int coeff0
= wi::one (GET_MODE_PRECISION (int_mode
));
2733 wide_int negcoeff1
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2735 if (GET_CODE (lhs
) == NEG
)
2737 coeff0
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2738 lhs
= XEXP (lhs
, 0);
2740 else if (GET_CODE (lhs
) == MULT
2741 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
2743 coeff0
= rtx_mode_t (XEXP (lhs
, 1), int_mode
);
2744 lhs
= XEXP (lhs
, 0);
2746 else if (GET_CODE (lhs
) == ASHIFT
2747 && CONST_INT_P (XEXP (lhs
, 1))
2748 && INTVAL (XEXP (lhs
, 1)) >= 0
2749 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2751 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
2752 GET_MODE_PRECISION (int_mode
));
2753 lhs
= XEXP (lhs
, 0);
2756 if (GET_CODE (rhs
) == NEG
)
2758 negcoeff1
= wi::one (GET_MODE_PRECISION (int_mode
));
2759 rhs
= XEXP (rhs
, 0);
2761 else if (GET_CODE (rhs
) == MULT
2762 && CONST_INT_P (XEXP (rhs
, 1)))
2764 negcoeff1
= wi::neg (rtx_mode_t (XEXP (rhs
, 1), int_mode
));
2765 rhs
= XEXP (rhs
, 0);
2767 else if (GET_CODE (rhs
) == ASHIFT
2768 && CONST_INT_P (XEXP (rhs
, 1))
2769 && INTVAL (XEXP (rhs
, 1)) >= 0
2770 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2772 negcoeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
2773 GET_MODE_PRECISION (int_mode
));
2774 negcoeff1
= -negcoeff1
;
2775 rhs
= XEXP (rhs
, 0);
2778 if (rtx_equal_p (lhs
, rhs
))
2780 rtx orig
= gen_rtx_MINUS (int_mode
, op0
, op1
);
2782 bool speed
= optimize_function_for_speed_p (cfun
);
2784 coeff
= immed_wide_int_const (coeff0
+ negcoeff1
, int_mode
);
2786 tem
= simplify_gen_binary (MULT
, int_mode
, lhs
, coeff
);
2787 return (set_src_cost (tem
, int_mode
, speed
)
2788 <= set_src_cost (orig
, int_mode
, speed
) ? tem
: 0);
2792 /* (a - (-b)) -> (a + b). True even for IEEE. */
2793 if (GET_CODE (op1
) == NEG
)
2794 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
2796 /* (-x - c) may be simplified as (-c - x). */
2797 if (GET_CODE (op0
) == NEG
2798 && (CONST_SCALAR_INT_P (op1
) || CONST_DOUBLE_AS_FLOAT_P (op1
)))
2800 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2802 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
2805 if ((GET_CODE (op0
) == CONST
2806 || GET_CODE (op0
) == SYMBOL_REF
2807 || GET_CODE (op0
) == LABEL_REF
)
2808 && poly_int_rtx_p (op1
, &offset
))
2809 return plus_constant (mode
, op0
, trunc_int_for_mode (-offset
, mode
));
2811 /* Don't let a relocatable value get a negative coeff. */
2812 if (poly_int_rtx_p (op1
) && GET_MODE (op0
) != VOIDmode
)
2813 return simplify_gen_binary (PLUS
, mode
,
2815 neg_poly_int_rtx (mode
, op1
));
2817 /* (x - (x & y)) -> (x & ~y) */
2818 if (INTEGRAL_MODE_P (mode
) && GET_CODE (op1
) == AND
)
2820 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
2822 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
2823 GET_MODE (XEXP (op1
, 1)));
2824 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2826 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
2828 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
2829 GET_MODE (XEXP (op1
, 0)));
2830 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2834 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
2835 by reversing the comparison code if valid. */
2836 if (STORE_FLAG_VALUE
== 1
2837 && trueop0
== const1_rtx
2838 && COMPARISON_P (op1
)
2839 && (reversed
= reversed_comparison (op1
, mode
)))
2842 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). */
2843 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2844 && GET_CODE (op1
) == MULT
2845 && GET_CODE (XEXP (op1
, 0)) == NEG
)
2849 in1
= XEXP (XEXP (op1
, 0), 0);
2850 in2
= XEXP (op1
, 1);
2851 return simplify_gen_binary (PLUS
, mode
,
2852 simplify_gen_binary (MULT
, mode
,
2857 /* Canonicalize (minus (neg A) (mult B C)) to
2858 (minus (mult (neg B) C) A). */
2859 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2860 && GET_CODE (op1
) == MULT
2861 && GET_CODE (op0
) == NEG
)
2865 in1
= simplify_gen_unary (NEG
, mode
, XEXP (op1
, 0), mode
);
2866 in2
= XEXP (op1
, 1);
2867 return simplify_gen_binary (MINUS
, mode
,
2868 simplify_gen_binary (MULT
, mode
,
2873 /* If one of the operands is a PLUS or a MINUS, see if we can
2874 simplify this by the associative law. This will, for example,
2875 canonicalize (minus A (plus B C)) to (minus (minus A B) C).
2876 Don't use the associative law for floating point.
2877 The inaccuracy makes it nonassociative,
2878 and subtle programs can break if operations are associated. */
2880 if (INTEGRAL_MODE_P (mode
)
2881 && (plus_minus_operand_p (op0
)
2882 || plus_minus_operand_p (op1
))
2883 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2886 /* Handle vector series. */
2887 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
2889 tem
= simplify_binary_operation_series (code
, mode
, op0
, op1
);
2896 if (trueop1
== constm1_rtx
)
2897 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2899 if (GET_CODE (op0
) == NEG
)
2901 rtx temp
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2902 /* If op1 is a MULT as well and simplify_unary_operation
2903 just moved the NEG to the second operand, simplify_gen_binary
2904 below could through simplify_associative_operation move
2905 the NEG around again and recurse endlessly. */
2907 && GET_CODE (op1
) == MULT
2908 && GET_CODE (temp
) == MULT
2909 && XEXP (op1
, 0) == XEXP (temp
, 0)
2910 && GET_CODE (XEXP (temp
, 1)) == NEG
2911 && XEXP (op1
, 1) == XEXP (XEXP (temp
, 1), 0))
2914 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), temp
);
2916 if (GET_CODE (op1
) == NEG
)
2918 rtx temp
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
2919 /* If op0 is a MULT as well and simplify_unary_operation
2920 just moved the NEG to the second operand, simplify_gen_binary
2921 below could through simplify_associative_operation move
2922 the NEG around again and recurse endlessly. */
2924 && GET_CODE (op0
) == MULT
2925 && GET_CODE (temp
) == MULT
2926 && XEXP (op0
, 0) == XEXP (temp
, 0)
2927 && GET_CODE (XEXP (temp
, 1)) == NEG
2928 && XEXP (op0
, 1) == XEXP (XEXP (temp
, 1), 0))
2931 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op1
, 0));
2934 /* Maybe simplify x * 0 to 0. The reduction is not valid if
2935 x is NaN, since x * 0 is then also NaN. Nor is it valid
2936 when the mode has signed zeros, since multiplying a negative
2937 number by 0 will give -0, not 0. */
2938 if (!HONOR_NANS (mode
)
2939 && !HONOR_SIGNED_ZEROS (mode
)
2940 && trueop1
== CONST0_RTX (mode
)
2941 && ! side_effects_p (op0
))
2944 /* In IEEE floating point, x*1 is not equivalent to x for
2946 if (!HONOR_SNANS (mode
)
2947 && trueop1
== CONST1_RTX (mode
))
2950 /* Convert multiply by constant power of two into shift. */
2951 if (CONST_SCALAR_INT_P (trueop1
))
2953 val
= wi::exact_log2 (rtx_mode_t (trueop1
, mode
));
2955 return simplify_gen_binary (ASHIFT
, mode
, op0
,
2956 gen_int_shift_amount (mode
, val
));
2959 /* x*2 is x+x and x*(-1) is -x */
2960 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
2961 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop1
))
2962 && !DECIMAL_FLOAT_MODE_P (GET_MODE (trueop1
))
2963 && GET_MODE (op0
) == mode
)
2965 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
2967 if (real_equal (d1
, &dconst2
))
2968 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
2970 if (!HONOR_SNANS (mode
)
2971 && real_equal (d1
, &dconstm1
))
2972 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2975 /* Optimize -x * -x as x * x. */
2976 if (FLOAT_MODE_P (mode
)
2977 && GET_CODE (op0
) == NEG
2978 && GET_CODE (op1
) == NEG
2979 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2980 && !side_effects_p (XEXP (op0
, 0)))
2981 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2983 /* Likewise, optimize abs(x) * abs(x) as x * x. */
2984 if (SCALAR_FLOAT_MODE_P (mode
)
2985 && GET_CODE (op0
) == ABS
2986 && GET_CODE (op1
) == ABS
2987 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2988 && !side_effects_p (XEXP (op0
, 0)))
2989 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2991 /* Reassociate multiplication, but for floating point MULTs
2992 only when the user specifies unsafe math optimizations. */
2993 if (! FLOAT_MODE_P (mode
)
2994 || flag_unsafe_math_optimizations
)
2996 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3003 if (trueop1
== CONST0_RTX (mode
))
3005 if (INTEGRAL_MODE_P (mode
)
3006 && trueop1
== CONSTM1_RTX (mode
)
3007 && !side_effects_p (op0
))
3009 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3011 /* A | (~A) -> -1 */
3012 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
3013 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
3014 && ! side_effects_p (op0
)
3015 && SCALAR_INT_MODE_P (mode
))
3018 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
3019 if (CONST_INT_P (op1
)
3020 && HWI_COMPUTABLE_MODE_P (mode
)
3021 && (nonzero_bits (op0
, mode
) & ~UINTVAL (op1
)) == 0
3022 && !side_effects_p (op0
))
3025 /* Canonicalize (X & C1) | C2. */
3026 if (GET_CODE (op0
) == AND
3027 && CONST_INT_P (trueop1
)
3028 && CONST_INT_P (XEXP (op0
, 1)))
3030 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
3031 HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
3032 HOST_WIDE_INT c2
= INTVAL (trueop1
);
3034 /* If (C1&C2) == C1, then (X&C1)|C2 becomes C2. */
3036 && !side_effects_p (XEXP (op0
, 0)))
3039 /* If (C1|C2) == ~0 then (X&C1)|C2 becomes X|C2. */
3040 if (((c1
|c2
) & mask
) == mask
)
3041 return simplify_gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
);
3044 /* Convert (A & B) | A to A. */
3045 if (GET_CODE (op0
) == AND
3046 && (rtx_equal_p (XEXP (op0
, 0), op1
)
3047 || rtx_equal_p (XEXP (op0
, 1), op1
))
3048 && ! side_effects_p (XEXP (op0
, 0))
3049 && ! side_effects_p (XEXP (op0
, 1)))
3052 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3053 mode size to (rotate A CX). */
3055 if (GET_CODE (op1
) == ASHIFT
3056 || GET_CODE (op1
) == SUBREG
)
3067 if (GET_CODE (opleft
) == ASHIFT
&& GET_CODE (opright
) == LSHIFTRT
3068 && rtx_equal_p (XEXP (opleft
, 0), XEXP (opright
, 0))
3069 && CONST_INT_P (XEXP (opleft
, 1))
3070 && CONST_INT_P (XEXP (opright
, 1))
3071 && (INTVAL (XEXP (opleft
, 1)) + INTVAL (XEXP (opright
, 1))
3072 == GET_MODE_UNIT_PRECISION (mode
)))
3073 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0), XEXP (opleft
, 1));
3075 /* Same, but for ashift that has been "simplified" to a wider mode
3076 by simplify_shift_const. */
3078 if (GET_CODE (opleft
) == SUBREG
3079 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
3080 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (opleft
)),
3082 && GET_CODE (SUBREG_REG (opleft
)) == ASHIFT
3083 && GET_CODE (opright
) == LSHIFTRT
3084 && GET_CODE (XEXP (opright
, 0)) == SUBREG
3085 && known_eq (SUBREG_BYTE (opleft
), SUBREG_BYTE (XEXP (opright
, 0)))
3086 && GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (inner_mode
)
3087 && rtx_equal_p (XEXP (SUBREG_REG (opleft
), 0),
3088 SUBREG_REG (XEXP (opright
, 0)))
3089 && CONST_INT_P (XEXP (SUBREG_REG (opleft
), 1))
3090 && CONST_INT_P (XEXP (opright
, 1))
3091 && (INTVAL (XEXP (SUBREG_REG (opleft
), 1))
3092 + INTVAL (XEXP (opright
, 1))
3093 == GET_MODE_PRECISION (int_mode
)))
3094 return gen_rtx_ROTATE (int_mode
, XEXP (opright
, 0),
3095 XEXP (SUBREG_REG (opleft
), 1));
3097 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
3098 a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
3099 the PLUS does not affect any of the bits in OP1: then we can do
3100 the IOR as a PLUS and we can associate. This is valid if OP1
3101 can be safely shifted left C bits. */
3102 if (CONST_INT_P (trueop1
) && GET_CODE (op0
) == ASHIFTRT
3103 && GET_CODE (XEXP (op0
, 0)) == PLUS
3104 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
3105 && CONST_INT_P (XEXP (op0
, 1))
3106 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
3108 int count
= INTVAL (XEXP (op0
, 1));
3109 HOST_WIDE_INT mask
= UINTVAL (trueop1
) << count
;
3111 if (mask
>> count
== INTVAL (trueop1
)
3112 && trunc_int_for_mode (mask
, mode
) == mask
3113 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
3114 return simplify_gen_binary (ASHIFTRT
, mode
,
3115 plus_constant (mode
, XEXP (op0
, 0),
3120 /* The following happens with bitfield merging.
3121 (X & C) | ((X | Y) & ~C) -> X | (Y & ~C) */
3122 if (GET_CODE (op0
) == AND
3123 && GET_CODE (op1
) == AND
3124 && CONST_INT_P (XEXP (op0
, 1))
3125 && CONST_INT_P (XEXP (op1
, 1))
3126 && (INTVAL (XEXP (op0
, 1))
3127 == ~INTVAL (XEXP (op1
, 1))))
3129 /* The IOR may be on both sides. */
3130 rtx top0
= NULL_RTX
, top1
= NULL_RTX
;
3131 if (GET_CODE (XEXP (op1
, 0)) == IOR
)
3132 top0
= op0
, top1
= op1
;
3133 else if (GET_CODE (XEXP (op0
, 0)) == IOR
)
3134 top0
= op1
, top1
= op0
;
3137 /* X may be on either side of the inner IOR. */
3139 if (rtx_equal_p (XEXP (top0
, 0),
3140 XEXP (XEXP (top1
, 0), 0)))
3141 tem
= XEXP (XEXP (top1
, 0), 1);
3142 else if (rtx_equal_p (XEXP (top0
, 0),
3143 XEXP (XEXP (top1
, 0), 1)))
3144 tem
= XEXP (XEXP (top1
, 0), 0);
3146 return simplify_gen_binary (IOR
, mode
, XEXP (top0
, 0),
3148 (AND
, mode
, tem
, XEXP (top1
, 1)));
3152 /* Convert (ior (and A C) (and B C)) into (and (ior A B) C). */
3153 if (GET_CODE (op0
) == GET_CODE (op1
)
3154 && (GET_CODE (op0
) == AND
3155 || GET_CODE (op0
) == IOR
3156 || GET_CODE (op0
) == LSHIFTRT
3157 || GET_CODE (op0
) == ASHIFTRT
3158 || GET_CODE (op0
) == ASHIFT
3159 || GET_CODE (op0
) == ROTATE
3160 || GET_CODE (op0
) == ROTATERT
))
3162 tem
= simplify_distributive_operation (code
, mode
, op0
, op1
);
3167 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3171 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3175 tem
= simplify_logical_relational_operation (code
, mode
, op0
, op1
);
3181 if (trueop1
== CONST0_RTX (mode
))
3183 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
3184 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
3185 if (rtx_equal_p (trueop0
, trueop1
)
3186 && ! side_effects_p (op0
)
3187 && GET_MODE_CLASS (mode
) != MODE_CC
)
3188 return CONST0_RTX (mode
);
3190 /* Canonicalize XOR of the most significant bit to PLUS. */
3191 if (CONST_SCALAR_INT_P (op1
)
3192 && mode_signbit_p (mode
, op1
))
3193 return simplify_gen_binary (PLUS
, mode
, op0
, op1
);
3194 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
3195 if (CONST_SCALAR_INT_P (op1
)
3196 && GET_CODE (op0
) == PLUS
3197 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
3198 && mode_signbit_p (mode
, XEXP (op0
, 1)))
3199 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
3200 simplify_gen_binary (XOR
, mode
, op1
,
3203 /* If we are XORing two things that have no bits in common,
3204 convert them into an IOR. This helps to detect rotation encoded
3205 using those methods and possibly other simplifications. */
3207 if (HWI_COMPUTABLE_MODE_P (mode
)
3208 && (nonzero_bits (op0
, mode
)
3209 & nonzero_bits (op1
, mode
)) == 0)
3210 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
3212 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3213 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3216 int num_negated
= 0;
3218 if (GET_CODE (op0
) == NOT
)
3219 num_negated
++, op0
= XEXP (op0
, 0);
3220 if (GET_CODE (op1
) == NOT
)
3221 num_negated
++, op1
= XEXP (op1
, 0);
3223 if (num_negated
== 2)
3224 return simplify_gen_binary (XOR
, mode
, op0
, op1
);
3225 else if (num_negated
== 1)
3226 return simplify_gen_unary (NOT
, mode
,
3227 simplify_gen_binary (XOR
, mode
, op0
, op1
),
3231 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3232 correspond to a machine insn or result in further simplifications
3233 if B is a constant. */
3235 if (GET_CODE (op0
) == AND
3236 && rtx_equal_p (XEXP (op0
, 1), op1
)
3237 && ! side_effects_p (op1
))
3238 return simplify_gen_binary (AND
, mode
,
3239 simplify_gen_unary (NOT
, mode
,
3240 XEXP (op0
, 0), mode
),
3243 else if (GET_CODE (op0
) == AND
3244 && rtx_equal_p (XEXP (op0
, 0), op1
)
3245 && ! side_effects_p (op1
))
3246 return simplify_gen_binary (AND
, mode
,
3247 simplify_gen_unary (NOT
, mode
,
3248 XEXP (op0
, 1), mode
),
3251 /* Given (xor (ior (xor A B) C) D), where B, C and D are
3252 constants, simplify to (xor (ior A C) (B&~C)^D), canceling
3253 out bits inverted twice and not set by C. Similarly, given
3254 (xor (and (xor A B) C) D), simplify without inverting C in
3255 the xor operand: (xor (and A C) (B&C)^D).
3257 else if ((GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == AND
)
3258 && GET_CODE (XEXP (op0
, 0)) == XOR
3259 && CONST_INT_P (op1
)
3260 && CONST_INT_P (XEXP (op0
, 1))
3261 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1)))
3263 enum rtx_code op
= GET_CODE (op0
);
3264 rtx a
= XEXP (XEXP (op0
, 0), 0);
3265 rtx b
= XEXP (XEXP (op0
, 0), 1);
3266 rtx c
= XEXP (op0
, 1);
3268 HOST_WIDE_INT bval
= INTVAL (b
);
3269 HOST_WIDE_INT cval
= INTVAL (c
);
3270 HOST_WIDE_INT dval
= INTVAL (d
);
3271 HOST_WIDE_INT xcval
;
3278 return simplify_gen_binary (XOR
, mode
,
3279 simplify_gen_binary (op
, mode
, a
, c
),
3280 gen_int_mode ((bval
& xcval
) ^ dval
,
3284 /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
3285 we can transform like this:
3286 (A&B)^C == ~(A&B)&C | ~C&(A&B)
3287 == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
3288 == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
3289 Attempt a few simplifications when B and C are both constants. */
3290 if (GET_CODE (op0
) == AND
3291 && CONST_INT_P (op1
)
3292 && CONST_INT_P (XEXP (op0
, 1)))
3294 rtx a
= XEXP (op0
, 0);
3295 rtx b
= XEXP (op0
, 1);
3297 HOST_WIDE_INT bval
= INTVAL (b
);
3298 HOST_WIDE_INT cval
= INTVAL (c
);
3300 /* Instead of computing ~A&C, we compute its negated value,
3301 ~(A|~C). If it yields -1, ~A&C is zero, so we can
3302 optimize for sure. If it does not simplify, we still try
3303 to compute ~A&C below, but since that always allocates
3304 RTL, we don't try that before committing to returning a
3305 simplified expression. */
3306 rtx n_na_c
= simplify_binary_operation (IOR
, mode
, a
,
3309 if ((~cval
& bval
) == 0)
3311 rtx na_c
= NULL_RTX
;
3313 na_c
= simplify_gen_unary (NOT
, mode
, n_na_c
, mode
);
3316 /* If ~A does not simplify, don't bother: we don't
3317 want to simplify 2 operations into 3, and if na_c
3318 were to simplify with na, n_na_c would have
3319 simplified as well. */
3320 rtx na
= simplify_unary_operation (NOT
, mode
, a
, mode
);
3322 na_c
= simplify_gen_binary (AND
, mode
, na
, c
);
3325 /* Try to simplify ~A&C | ~B&C. */
3326 if (na_c
!= NULL_RTX
)
3327 return simplify_gen_binary (IOR
, mode
, na_c
,
3328 gen_int_mode (~bval
& cval
, mode
));
3332 /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
3333 if (n_na_c
== CONSTM1_RTX (mode
))
3335 rtx a_nc_b
= simplify_gen_binary (AND
, mode
, a
,
3336 gen_int_mode (~cval
& bval
,
3338 return simplify_gen_binary (IOR
, mode
, a_nc_b
,
3339 gen_int_mode (~bval
& cval
,
3345 /* If we have (xor (and (xor A B) C) A) with C a constant we can instead
3346 do (ior (and A ~C) (and B C)) which is a machine instruction on some
3347 machines, and also has shorter instruction path length. */
3348 if (GET_CODE (op0
) == AND
3349 && GET_CODE (XEXP (op0
, 0)) == XOR
3350 && CONST_INT_P (XEXP (op0
, 1))
3351 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), trueop1
))
3354 rtx b
= XEXP (XEXP (op0
, 0), 1);
3355 rtx c
= XEXP (op0
, 1);
3356 rtx nc
= simplify_gen_unary (NOT
, mode
, c
, mode
);
3357 rtx a_nc
= simplify_gen_binary (AND
, mode
, a
, nc
);
3358 rtx bc
= simplify_gen_binary (AND
, mode
, b
, c
);
3359 return simplify_gen_binary (IOR
, mode
, a_nc
, bc
);
3361 /* Similarly, (xor (and (xor A B) C) B) as (ior (and A C) (and B ~C)) */
3362 else if (GET_CODE (op0
) == AND
3363 && GET_CODE (XEXP (op0
, 0)) == XOR
3364 && CONST_INT_P (XEXP (op0
, 1))
3365 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), trueop1
))
3367 rtx a
= XEXP (XEXP (op0
, 0), 0);
3369 rtx c
= XEXP (op0
, 1);
3370 rtx nc
= simplify_gen_unary (NOT
, mode
, c
, mode
);
3371 rtx b_nc
= simplify_gen_binary (AND
, mode
, b
, nc
);
3372 rtx ac
= simplify_gen_binary (AND
, mode
, a
, c
);
3373 return simplify_gen_binary (IOR
, mode
, ac
, b_nc
);
3376 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3377 comparison if STORE_FLAG_VALUE is 1. */
3378 if (STORE_FLAG_VALUE
== 1
3379 && trueop1
== const1_rtx
3380 && COMPARISON_P (op0
)
3381 && (reversed
= reversed_comparison (op0
, mode
)))
3384 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
3385 is (lt foo (const_int 0)), so we can perform the above
3386 simplification if STORE_FLAG_VALUE is 1. */
3388 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
3389 && STORE_FLAG_VALUE
== 1
3390 && trueop1
== const1_rtx
3391 && GET_CODE (op0
) == LSHIFTRT
3392 && CONST_INT_P (XEXP (op0
, 1))
3393 && INTVAL (XEXP (op0
, 1)) == GET_MODE_PRECISION (int_mode
) - 1)
3394 return gen_rtx_GE (int_mode
, XEXP (op0
, 0), const0_rtx
);
3396 /* (xor (comparison foo bar) (const_int sign-bit))
3397 when STORE_FLAG_VALUE is the sign bit. */
3398 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
3399 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
3400 && trueop1
== const_true_rtx
3401 && COMPARISON_P (op0
)
3402 && (reversed
= reversed_comparison (op0
, int_mode
)))
3405 /* Convert (xor (and A C) (and B C)) into (and (xor A B) C). */
3406 if (GET_CODE (op0
) == GET_CODE (op1
)
3407 && (GET_CODE (op0
) == AND
3408 || GET_CODE (op0
) == LSHIFTRT
3409 || GET_CODE (op0
) == ASHIFTRT
3410 || GET_CODE (op0
) == ASHIFT
3411 || GET_CODE (op0
) == ROTATE
3412 || GET_CODE (op0
) == ROTATERT
))
3414 tem
= simplify_distributive_operation (code
, mode
, op0
, op1
);
3419 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3423 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3429 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
3431 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
3433 if (HWI_COMPUTABLE_MODE_P (mode
))
3435 HOST_WIDE_INT nzop0
= nonzero_bits (trueop0
, mode
);
3436 HOST_WIDE_INT nzop1
;
3437 if (CONST_INT_P (trueop1
))
3439 HOST_WIDE_INT val1
= INTVAL (trueop1
);
3440 /* If we are turning off bits already known off in OP0, we need
3442 if ((nzop0
& ~val1
) == 0)
3445 nzop1
= nonzero_bits (trueop1
, mode
);
3446 /* If we are clearing all the nonzero bits, the result is zero. */
3447 if ((nzop1
& nzop0
) == 0
3448 && !side_effects_p (op0
) && !side_effects_p (op1
))
3449 return CONST0_RTX (mode
);
3451 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
)
3452 && GET_MODE_CLASS (mode
) != MODE_CC
)
3455 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
3456 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
3457 && ! side_effects_p (op0
)
3458 && GET_MODE_CLASS (mode
) != MODE_CC
)
3459 return CONST0_RTX (mode
);
3461 /* Transform (and (extend X) C) into (zero_extend (and X C)) if
3462 there are no nonzero bits of C outside of X's mode. */
3463 if ((GET_CODE (op0
) == SIGN_EXTEND
3464 || GET_CODE (op0
) == ZERO_EXTEND
)
3465 && CONST_INT_P (trueop1
)
3466 && HWI_COMPUTABLE_MODE_P (mode
)
3467 && (~GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))
3468 & UINTVAL (trueop1
)) == 0)
3470 machine_mode imode
= GET_MODE (XEXP (op0
, 0));
3471 tem
= simplify_gen_binary (AND
, imode
, XEXP (op0
, 0),
3472 gen_int_mode (INTVAL (trueop1
),
3474 return simplify_gen_unary (ZERO_EXTEND
, mode
, tem
, imode
);
3477 /* Transform (and (truncate X) C) into (truncate (and X C)). This way
3478 we might be able to further simplify the AND with X and potentially
3479 remove the truncation altogether. */
3480 if (GET_CODE (op0
) == TRUNCATE
&& CONST_INT_P (trueop1
))
3482 rtx x
= XEXP (op0
, 0);
3483 machine_mode xmode
= GET_MODE (x
);
3484 tem
= simplify_gen_binary (AND
, xmode
, x
,
3485 gen_int_mode (INTVAL (trueop1
), xmode
));
3486 return simplify_gen_unary (TRUNCATE
, mode
, tem
, xmode
);
3489 /* Canonicalize (A | C1) & C2 as (A & C2) | (C1 & C2). */
3490 if (GET_CODE (op0
) == IOR
3491 && CONST_INT_P (trueop1
)
3492 && CONST_INT_P (XEXP (op0
, 1)))
3494 HOST_WIDE_INT tmp
= INTVAL (trueop1
) & INTVAL (XEXP (op0
, 1));
3495 return simplify_gen_binary (IOR
, mode
,
3496 simplify_gen_binary (AND
, mode
,
3497 XEXP (op0
, 0), op1
),
3498 gen_int_mode (tmp
, mode
));
3501 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
3502 insn (and may simplify more). */
3503 if (GET_CODE (op0
) == XOR
3504 && rtx_equal_p (XEXP (op0
, 0), op1
)
3505 && ! side_effects_p (op1
))
3506 return simplify_gen_binary (AND
, mode
,
3507 simplify_gen_unary (NOT
, mode
,
3508 XEXP (op0
, 1), mode
),
3511 if (GET_CODE (op0
) == XOR
3512 && rtx_equal_p (XEXP (op0
, 1), op1
)
3513 && ! side_effects_p (op1
))
3514 return simplify_gen_binary (AND
, mode
,
3515 simplify_gen_unary (NOT
, mode
,
3516 XEXP (op0
, 0), mode
),
3519 /* Similarly for (~(A ^ B)) & A. */
3520 if (GET_CODE (op0
) == NOT
3521 && GET_CODE (XEXP (op0
, 0)) == XOR
3522 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
3523 && ! side_effects_p (op1
))
3524 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
3526 if (GET_CODE (op0
) == NOT
3527 && GET_CODE (XEXP (op0
, 0)) == XOR
3528 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
3529 && ! side_effects_p (op1
))
3530 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
3532 /* Convert (A | B) & A to A. */
3533 if (GET_CODE (op0
) == IOR
3534 && (rtx_equal_p (XEXP (op0
, 0), op1
)
3535 || rtx_equal_p (XEXP (op0
, 1), op1
))
3536 && ! side_effects_p (XEXP (op0
, 0))
3537 && ! side_effects_p (XEXP (op0
, 1)))
3540 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
3541 ((A & N) + B) & M -> (A + B) & M
3542 Similarly if (N & M) == 0,
3543 ((A | N) + B) & M -> (A + B) & M
3544 and for - instead of + and/or ^ instead of |.
3545 Also, if (N & M) == 0, then
3546 (A +- N) & M -> A & M. */
3547 if (CONST_INT_P (trueop1
)
3548 && HWI_COMPUTABLE_MODE_P (mode
)
3549 && ~UINTVAL (trueop1
)
3550 && (UINTVAL (trueop1
) & (UINTVAL (trueop1
) + 1)) == 0
3551 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
))
3556 pmop
[0] = XEXP (op0
, 0);
3557 pmop
[1] = XEXP (op0
, 1);
3559 if (CONST_INT_P (pmop
[1])
3560 && (UINTVAL (pmop
[1]) & UINTVAL (trueop1
)) == 0)
3561 return simplify_gen_binary (AND
, mode
, pmop
[0], op1
);
3563 for (which
= 0; which
< 2; which
++)
3566 switch (GET_CODE (tem
))
3569 if (CONST_INT_P (XEXP (tem
, 1))
3570 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
))
3571 == UINTVAL (trueop1
))
3572 pmop
[which
] = XEXP (tem
, 0);
3576 if (CONST_INT_P (XEXP (tem
, 1))
3577 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
)) == 0)
3578 pmop
[which
] = XEXP (tem
, 0);
3585 if (pmop
[0] != XEXP (op0
, 0) || pmop
[1] != XEXP (op0
, 1))
3587 tem
= simplify_gen_binary (GET_CODE (op0
), mode
,
3589 return simplify_gen_binary (code
, mode
, tem
, op1
);
3593 /* (and X (ior (not X) Y) -> (and X Y) */
3594 if (GET_CODE (op1
) == IOR
3595 && GET_CODE (XEXP (op1
, 0)) == NOT
3596 && rtx_equal_p (op0
, XEXP (XEXP (op1
, 0), 0)))
3597 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 1));
3599 /* (and (ior (not X) Y) X) -> (and X Y) */
3600 if (GET_CODE (op0
) == IOR
3601 && GET_CODE (XEXP (op0
, 0)) == NOT
3602 && rtx_equal_p (op1
, XEXP (XEXP (op0
, 0), 0)))
3603 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 1));
3605 /* (and X (ior Y (not X)) -> (and X Y) */
3606 if (GET_CODE (op1
) == IOR
3607 && GET_CODE (XEXP (op1
, 1)) == NOT
3608 && rtx_equal_p (op0
, XEXP (XEXP (op1
, 1), 0)))
3609 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 0));
3611 /* (and (ior Y (not X)) X) -> (and X Y) */
3612 if (GET_CODE (op0
) == IOR
3613 && GET_CODE (XEXP (op0
, 1)) == NOT
3614 && rtx_equal_p (op1
, XEXP (XEXP (op0
, 1), 0)))
3615 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 0));
3617 /* Convert (and (ior A C) (ior B C)) into (ior (and A B) C). */
3618 if (GET_CODE (op0
) == GET_CODE (op1
)
3619 && (GET_CODE (op0
) == AND
3620 || GET_CODE (op0
) == IOR
3621 || GET_CODE (op0
) == LSHIFTRT
3622 || GET_CODE (op0
) == ASHIFTRT
3623 || GET_CODE (op0
) == ASHIFT
3624 || GET_CODE (op0
) == ROTATE
3625 || GET_CODE (op0
) == ROTATERT
))
3627 tem
= simplify_distributive_operation (code
, mode
, op0
, op1
);
3632 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3636 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3642 /* 0/x is 0 (or x&0 if x has side-effects). */
3643 if (trueop0
== CONST0_RTX (mode
)
3644 && !cfun
->can_throw_non_call_exceptions
)
3646 if (side_effects_p (op1
))
3647 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3651 if (trueop1
== CONST1_RTX (mode
))
3653 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3657 /* Convert divide by power of two into shift. */
3658 if (CONST_INT_P (trueop1
)
3659 && (val
= exact_log2 (UINTVAL (trueop1
))) > 0)
3660 return simplify_gen_binary (LSHIFTRT
, mode
, op0
,
3661 gen_int_shift_amount (mode
, val
));
3665 /* Handle floating point and integers separately. */
3666 if (SCALAR_FLOAT_MODE_P (mode
))
3668 /* Maybe change 0.0 / x to 0.0. This transformation isn't
3669 safe for modes with NaNs, since 0.0 / 0.0 will then be
3670 NaN rather than 0.0. Nor is it safe for modes with signed
3671 zeros, since dividing 0 by a negative number gives -0.0 */
3672 if (trueop0
== CONST0_RTX (mode
)
3673 && !HONOR_NANS (mode
)
3674 && !HONOR_SIGNED_ZEROS (mode
)
3675 && ! side_effects_p (op1
))
3678 if (trueop1
== CONST1_RTX (mode
)
3679 && !HONOR_SNANS (mode
))
3682 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
3683 && trueop1
!= CONST0_RTX (mode
))
3685 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
3688 if (real_equal (d1
, &dconstm1
)
3689 && !HONOR_SNANS (mode
))
3690 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
3692 /* Change FP division by a constant into multiplication.
3693 Only do this with -freciprocal-math. */
3694 if (flag_reciprocal_math
3695 && !real_equal (d1
, &dconst0
))
3698 real_arithmetic (&d
, RDIV_EXPR
, &dconst1
, d1
);
3699 tem
= const_double_from_real_value (d
, mode
);
3700 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
3704 else if (SCALAR_INT_MODE_P (mode
))
3706 /* 0/x is 0 (or x&0 if x has side-effects). */
3707 if (trueop0
== CONST0_RTX (mode
)
3708 && !cfun
->can_throw_non_call_exceptions
)
3710 if (side_effects_p (op1
))
3711 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3715 if (trueop1
== CONST1_RTX (mode
))
3717 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3722 if (trueop1
== constm1_rtx
)
3724 rtx x
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3726 return simplify_gen_unary (NEG
, mode
, x
, mode
);
3732 /* 0%x is 0 (or x&0 if x has side-effects). */
3733 if (trueop0
== CONST0_RTX (mode
))
3735 if (side_effects_p (op1
))
3736 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3739 /* x%1 is 0 (of x&0 if x has side-effects). */
3740 if (trueop1
== CONST1_RTX (mode
))
3742 if (side_effects_p (op0
))
3743 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3744 return CONST0_RTX (mode
);
3746 /* Implement modulus by power of two as AND. */
3747 if (CONST_INT_P (trueop1
)
3748 && exact_log2 (UINTVAL (trueop1
)) > 0)
3749 return simplify_gen_binary (AND
, mode
, op0
,
3750 gen_int_mode (UINTVAL (trueop1
) - 1,
3755 /* 0%x is 0 (or x&0 if x has side-effects). */
3756 if (trueop0
== CONST0_RTX (mode
))
3758 if (side_effects_p (op1
))
3759 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3762 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
3763 if (trueop1
== CONST1_RTX (mode
) || trueop1
== constm1_rtx
)
3765 if (side_effects_p (op0
))
3766 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3767 return CONST0_RTX (mode
);
3773 if (trueop1
== CONST0_RTX (mode
))
3775 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
3776 prefer left rotation, if op1 is from bitsize / 2 + 1 to
3777 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
3779 #if defined(HAVE_rotate) && defined(HAVE_rotatert)
3780 if (CONST_INT_P (trueop1
)
3781 && IN_RANGE (INTVAL (trueop1
),
3782 GET_MODE_UNIT_PRECISION (mode
) / 2 + (code
== ROTATE
),
3783 GET_MODE_UNIT_PRECISION (mode
) - 1))
3785 int new_amount
= GET_MODE_UNIT_PRECISION (mode
) - INTVAL (trueop1
);
3786 rtx new_amount_rtx
= gen_int_shift_amount (mode
, new_amount
);
3787 return simplify_gen_binary (code
== ROTATE
? ROTATERT
: ROTATE
,
3788 mode
, op0
, new_amount_rtx
);
3793 if (trueop1
== CONST0_RTX (mode
))
3795 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3797 /* Rotating ~0 always results in ~0. */
3798 if (CONST_INT_P (trueop0
)
3799 && HWI_COMPUTABLE_MODE_P (mode
)
3800 && UINTVAL (trueop0
) == GET_MODE_MASK (mode
)
3801 && ! side_effects_p (op1
))
3807 scalar constants c1, c2
3808 size (M2) > size (M1)
3809 c1 == size (M2) - size (M1)
3811 ([a|l]shiftrt:M1 (subreg:M1 (lshiftrt:M2 (reg:M2) (const_int <c1>))
3815 (subreg:M1 ([a|l]shiftrt:M2 (reg:M2) (const_int <c1 + c2>))
3817 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
3818 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
3820 && CONST_INT_P (op1
)
3821 && GET_CODE (SUBREG_REG (op0
)) == LSHIFTRT
3822 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
3824 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1))
3825 && GET_MODE_BITSIZE (inner_mode
) > GET_MODE_BITSIZE (int_mode
)
3826 && (INTVAL (XEXP (SUBREG_REG (op0
), 1))
3827 == GET_MODE_BITSIZE (inner_mode
) - GET_MODE_BITSIZE (int_mode
))
3828 && subreg_lowpart_p (op0
))
3830 rtx tmp
= gen_int_shift_amount
3831 (inner_mode
, INTVAL (XEXP (SUBREG_REG (op0
), 1)) + INTVAL (op1
));
3833 /* Combine would usually zero out the value when combining two
3834 local shifts and the range becomes larger or equal to the mode.
3835 However since we fold away one of the shifts here combine won't
3836 see it so we should immediately zero the result if it's out of
3838 if (code
== LSHIFTRT
3839 && INTVAL (tmp
) >= GET_MODE_BITSIZE (inner_mode
))
3842 tmp
= simplify_gen_binary (code
,
3844 XEXP (SUBREG_REG (op0
), 0),
3847 return lowpart_subreg (int_mode
, tmp
, inner_mode
);
3850 if (SHIFT_COUNT_TRUNCATED
&& CONST_INT_P (op1
))
3852 val
= INTVAL (op1
) & (GET_MODE_UNIT_PRECISION (mode
) - 1);
3853 if (val
!= INTVAL (op1
))
3854 return simplify_gen_binary (code
, mode
, op0
,
3855 gen_int_shift_amount (mode
, val
));
3862 if (trueop1
== CONST0_RTX (mode
))
3864 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3866 goto canonicalize_shift
;
3869 if (trueop1
== CONST0_RTX (mode
))
3871 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3873 /* Optimize (lshiftrt (clz X) C) as (eq X 0). */
3874 if (GET_CODE (op0
) == CLZ
3875 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (op0
, 0)), &inner_mode
)
3876 && CONST_INT_P (trueop1
)
3877 && STORE_FLAG_VALUE
== 1
3878 && INTVAL (trueop1
) < GET_MODE_UNIT_PRECISION (mode
))
3880 unsigned HOST_WIDE_INT zero_val
= 0;
3882 if (CLZ_DEFINED_VALUE_AT_ZERO (inner_mode
, zero_val
)
3883 && zero_val
== GET_MODE_PRECISION (inner_mode
)
3884 && INTVAL (trueop1
) == exact_log2 (zero_val
))
3885 return simplify_gen_relational (EQ
, mode
, inner_mode
,
3886 XEXP (op0
, 0), const0_rtx
);
3888 goto canonicalize_shift
;
3891 if (HWI_COMPUTABLE_MODE_P (mode
)
3892 && mode_signbit_p (mode
, trueop1
)
3893 && ! side_effects_p (op0
))
3895 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3897 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3903 if (HWI_COMPUTABLE_MODE_P (mode
)
3904 && CONST_INT_P (trueop1
)
3905 && (UINTVAL (trueop1
) == GET_MODE_MASK (mode
) >> 1)
3906 && ! side_effects_p (op0
))
3908 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3910 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3916 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
3918 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3920 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3926 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
3928 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3930 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3943 /* ??? There are simplifications that can be done. */
3947 if (op1
== CONST0_RTX (GET_MODE_INNER (mode
)))
3948 return gen_vec_duplicate (mode
, op0
);
3949 if (valid_for_const_vector_p (mode
, op0
)
3950 && valid_for_const_vector_p (mode
, op1
))
3951 return gen_const_vec_series (mode
, op0
, op1
);
3955 if (!VECTOR_MODE_P (mode
))
3957 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
3958 gcc_assert (mode
== GET_MODE_INNER (GET_MODE (trueop0
)));
3959 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
3960 gcc_assert (XVECLEN (trueop1
, 0) == 1);
3962 /* We can't reason about selections made at runtime. */
3963 if (!CONST_INT_P (XVECEXP (trueop1
, 0, 0)))
3966 if (vec_duplicate_p (trueop0
, &elt0
))
3969 if (GET_CODE (trueop0
) == CONST_VECTOR
)
3970 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP
3973 /* Extract a scalar element from a nested VEC_SELECT expression
3974 (with optional nested VEC_CONCAT expression). Some targets
3975 (i386) extract scalar element from a vector using chain of
3976 nested VEC_SELECT expressions. When input operand is a memory
3977 operand, this operation can be simplified to a simple scalar
3978 load from an offseted memory address. */
3980 if (GET_CODE (trueop0
) == VEC_SELECT
3981 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 0)))
3982 .is_constant (&n_elts
)))
3984 rtx op0
= XEXP (trueop0
, 0);
3985 rtx op1
= XEXP (trueop0
, 1);
3987 int i
= INTVAL (XVECEXP (trueop1
, 0, 0));
3993 gcc_assert (GET_CODE (op1
) == PARALLEL
);
3994 gcc_assert (i
< n_elts
);
3996 /* Select element, pointed by nested selector. */
3997 elem
= INTVAL (XVECEXP (op1
, 0, i
));
3999 /* Handle the case when nested VEC_SELECT wraps VEC_CONCAT. */
4000 if (GET_CODE (op0
) == VEC_CONCAT
)
4002 rtx op00
= XEXP (op0
, 0);
4003 rtx op01
= XEXP (op0
, 1);
4005 machine_mode mode00
, mode01
;
4006 int n_elts00
, n_elts01
;
4008 mode00
= GET_MODE (op00
);
4009 mode01
= GET_MODE (op01
);
4011 /* Find out the number of elements of each operand.
4012 Since the concatenated result has a constant number
4013 of elements, the operands must too. */
4014 n_elts00
= GET_MODE_NUNITS (mode00
).to_constant ();
4015 n_elts01
= GET_MODE_NUNITS (mode01
).to_constant ();
4017 gcc_assert (n_elts
== n_elts00
+ n_elts01
);
4019 /* Select correct operand of VEC_CONCAT
4020 and adjust selector. */
4021 if (elem
< n_elts01
)
4032 vec
= rtvec_alloc (1);
4033 RTVEC_ELT (vec
, 0) = GEN_INT (elem
);
4035 tmp
= gen_rtx_fmt_ee (code
, mode
,
4036 tmp_op
, gen_rtx_PARALLEL (VOIDmode
, vec
));
4042 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
4043 gcc_assert (GET_MODE_INNER (mode
)
4044 == GET_MODE_INNER (GET_MODE (trueop0
)));
4045 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
4047 if (vec_duplicate_p (trueop0
, &elt0
))
4048 /* It doesn't matter which elements are selected by trueop1,
4049 because they are all the same. */
4050 return gen_vec_duplicate (mode
, elt0
);
4052 if (GET_CODE (trueop0
) == CONST_VECTOR
)
4054 unsigned n_elts
= XVECLEN (trueop1
, 0);
4055 rtvec v
= rtvec_alloc (n_elts
);
4058 gcc_assert (known_eq (n_elts
, GET_MODE_NUNITS (mode
)));
4059 for (i
= 0; i
< n_elts
; i
++)
4061 rtx x
= XVECEXP (trueop1
, 0, i
);
4063 if (!CONST_INT_P (x
))
4066 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
,
4070 return gen_rtx_CONST_VECTOR (mode
, v
);
4073 /* Recognize the identity. */
4074 if (GET_MODE (trueop0
) == mode
)
4076 bool maybe_ident
= true;
4077 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
4079 rtx j
= XVECEXP (trueop1
, 0, i
);
4080 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
4082 maybe_ident
= false;
4090 /* If we build {a,b} then permute it, build the result directly. */
4091 if (XVECLEN (trueop1
, 0) == 2
4092 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
4093 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
4094 && GET_CODE (trueop0
) == VEC_CONCAT
4095 && GET_CODE (XEXP (trueop0
, 0)) == VEC_CONCAT
4096 && GET_MODE (XEXP (trueop0
, 0)) == mode
4097 && GET_CODE (XEXP (trueop0
, 1)) == VEC_CONCAT
4098 && GET_MODE (XEXP (trueop0
, 1)) == mode
)
4100 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
4101 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
4104 gcc_assert (i0
< 4 && i1
< 4);
4105 subop0
= XEXP (XEXP (trueop0
, i0
/ 2), i0
% 2);
4106 subop1
= XEXP (XEXP (trueop0
, i1
/ 2), i1
% 2);
4108 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
4111 if (XVECLEN (trueop1
, 0) == 2
4112 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
4113 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
4114 && GET_CODE (trueop0
) == VEC_CONCAT
4115 && GET_MODE (trueop0
) == mode
)
4117 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
4118 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
4121 gcc_assert (i0
< 2 && i1
< 2);
4122 subop0
= XEXP (trueop0
, i0
);
4123 subop1
= XEXP (trueop0
, i1
);
4125 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
4128 /* If we select one half of a vec_concat, return that. */
4130 if (GET_CODE (trueop0
) == VEC_CONCAT
4131 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 0)))
4133 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 1)))
4135 && CONST_INT_P (XVECEXP (trueop1
, 0, 0)))
4137 rtx subop0
= XEXP (trueop0
, 0);
4138 rtx subop1
= XEXP (trueop0
, 1);
4139 machine_mode mode0
= GET_MODE (subop0
);
4140 machine_mode mode1
= GET_MODE (subop1
);
4141 int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
4142 if (i0
== 0 && !side_effects_p (op1
) && mode
== mode0
)
4144 bool success
= true;
4145 for (int i
= 1; i
< l0
; ++i
)
4147 rtx j
= XVECEXP (trueop1
, 0, i
);
4148 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
4157 if (i0
== l0
&& !side_effects_p (op0
) && mode
== mode1
)
4159 bool success
= true;
4160 for (int i
= 1; i
< l1
; ++i
)
4162 rtx j
= XVECEXP (trueop1
, 0, i
);
4163 if (!CONST_INT_P (j
) || INTVAL (j
) != i0
+ i
)
4174 /* Simplify vec_select of a subreg of X to just a vec_select of X
4175 when X has same component mode as vec_select. */
4176 unsigned HOST_WIDE_INT subreg_offset
= 0;
4177 if (GET_CODE (trueop0
) == SUBREG
4178 && GET_MODE_INNER (mode
)
4179 == GET_MODE_INNER (GET_MODE (SUBREG_REG (trueop0
)))
4180 && GET_MODE_NUNITS (mode
).is_constant (&l1
)
4181 && constant_multiple_p (subreg_memory_offset (trueop0
),
4182 GET_MODE_UNIT_BITSIZE (mode
),
4186 = GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0
)));
4187 bool success
= true;
4188 for (int i
= 0; i
!= l1
; i
++)
4190 rtx idx
= XVECEXP (trueop1
, 0, i
);
4191 if (!CONST_INT_P (idx
)
4192 || maybe_ge (UINTVAL (idx
) + subreg_offset
, nunits
))
4204 rtvec vec
= rtvec_alloc (l1
);
4205 for (int i
= 0; i
< l1
; i
++)
4207 = GEN_INT (INTVAL (XVECEXP (trueop1
, 0, i
))
4209 par
= gen_rtx_PARALLEL (VOIDmode
, vec
);
4211 return gen_rtx_VEC_SELECT (mode
, SUBREG_REG (trueop0
), par
);
4216 if (XVECLEN (trueop1
, 0) == 1
4217 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
4218 && GET_CODE (trueop0
) == VEC_CONCAT
)
4221 offset
= INTVAL (XVECEXP (trueop1
, 0, 0)) * GET_MODE_SIZE (mode
);
4223 /* Try to find the element in the VEC_CONCAT. */
4224 while (GET_MODE (vec
) != mode
4225 && GET_CODE (vec
) == VEC_CONCAT
)
4227 poly_int64 vec_size
;
4229 if (CONST_INT_P (XEXP (vec
, 0)))
4231 /* vec_concat of two const_ints doesn't make sense with
4232 respect to modes. */
4233 if (CONST_INT_P (XEXP (vec
, 1)))
4236 vec_size
= GET_MODE_SIZE (GET_MODE (trueop0
))
4237 - GET_MODE_SIZE (GET_MODE (XEXP (vec
, 1)));
4240 vec_size
= GET_MODE_SIZE (GET_MODE (XEXP (vec
, 0)));
4242 if (known_lt (offset
, vec_size
))
4243 vec
= XEXP (vec
, 0);
4244 else if (known_ge (offset
, vec_size
))
4247 vec
= XEXP (vec
, 1);
4251 vec
= avoid_constant_pool_reference (vec
);
4254 if (GET_MODE (vec
) == mode
)
4258 /* If we select elements in a vec_merge that all come from the same
4259 operand, select from that operand directly. */
4260 if (GET_CODE (op0
) == VEC_MERGE
)
4262 rtx trueop02
= avoid_constant_pool_reference (XEXP (op0
, 2));
4263 if (CONST_INT_P (trueop02
))
4265 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop02
);
4266 bool all_operand0
= true;
4267 bool all_operand1
= true;
4268 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
4270 rtx j
= XVECEXP (trueop1
, 0, i
);
4271 if (sel
& (HOST_WIDE_INT_1U
<< UINTVAL (j
)))
4272 all_operand1
= false;
4274 all_operand0
= false;
4276 if (all_operand0
&& !side_effects_p (XEXP (op0
, 1)))
4277 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 0), op1
);
4278 if (all_operand1
&& !side_effects_p (XEXP (op0
, 0)))
4279 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 1), op1
);
4283 /* If we have two nested selects that are inverses of each
4284 other, replace them with the source operand. */
4285 if (GET_CODE (trueop0
) == VEC_SELECT
4286 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
4288 rtx op0_subop1
= XEXP (trueop0
, 1);
4289 gcc_assert (GET_CODE (op0_subop1
) == PARALLEL
);
4290 gcc_assert (known_eq (XVECLEN (trueop1
, 0), GET_MODE_NUNITS (mode
)));
4292 /* Apply the outer ordering vector to the inner one. (The inner
4293 ordering vector is expressly permitted to be of a different
4294 length than the outer one.) If the result is { 0, 1, ..., n-1 }
4295 then the two VEC_SELECTs cancel. */
4296 for (int i
= 0; i
< XVECLEN (trueop1
, 0); ++i
)
4298 rtx x
= XVECEXP (trueop1
, 0, i
);
4299 if (!CONST_INT_P (x
))
4301 rtx y
= XVECEXP (op0_subop1
, 0, INTVAL (x
));
4302 if (!CONST_INT_P (y
) || i
!= INTVAL (y
))
4305 return XEXP (trueop0
, 0);
4311 machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
4312 ? GET_MODE (trueop0
)
4313 : GET_MODE_INNER (mode
));
4314 machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
4315 ? GET_MODE (trueop1
)
4316 : GET_MODE_INNER (mode
));
4318 gcc_assert (VECTOR_MODE_P (mode
));
4319 gcc_assert (known_eq (GET_MODE_SIZE (op0_mode
)
4320 + GET_MODE_SIZE (op1_mode
),
4321 GET_MODE_SIZE (mode
)));
4323 if (VECTOR_MODE_P (op0_mode
))
4324 gcc_assert (GET_MODE_INNER (mode
)
4325 == GET_MODE_INNER (op0_mode
));
4327 gcc_assert (GET_MODE_INNER (mode
) == op0_mode
);
4329 if (VECTOR_MODE_P (op1_mode
))
4330 gcc_assert (GET_MODE_INNER (mode
)
4331 == GET_MODE_INNER (op1_mode
));
4333 gcc_assert (GET_MODE_INNER (mode
) == op1_mode
);
4335 unsigned int n_elts
, in_n_elts
;
4336 if ((GET_CODE (trueop0
) == CONST_VECTOR
4337 || CONST_SCALAR_INT_P (trueop0
)
4338 || CONST_DOUBLE_AS_FLOAT_P (trueop0
))
4339 && (GET_CODE (trueop1
) == CONST_VECTOR
4340 || CONST_SCALAR_INT_P (trueop1
)
4341 || CONST_DOUBLE_AS_FLOAT_P (trueop1
))
4342 && GET_MODE_NUNITS (mode
).is_constant (&n_elts
)
4343 && GET_MODE_NUNITS (op0_mode
).is_constant (&in_n_elts
))
4345 rtvec v
= rtvec_alloc (n_elts
);
4347 for (i
= 0; i
< n_elts
; i
++)
4351 if (!VECTOR_MODE_P (op0_mode
))
4352 RTVEC_ELT (v
, i
) = trueop0
;
4354 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
4358 if (!VECTOR_MODE_P (op1_mode
))
4359 RTVEC_ELT (v
, i
) = trueop1
;
4361 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
4366 return gen_rtx_CONST_VECTOR (mode
, v
);
4369 /* Try to merge two VEC_SELECTs from the same vector into a single one.
4370 Restrict the transformation to avoid generating a VEC_SELECT with a
4371 mode unrelated to its operand. */
4372 if (GET_CODE (trueop0
) == VEC_SELECT
4373 && GET_CODE (trueop1
) == VEC_SELECT
4374 && rtx_equal_p (XEXP (trueop0
, 0), XEXP (trueop1
, 0))
4375 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
4377 rtx par0
= XEXP (trueop0
, 1);
4378 rtx par1
= XEXP (trueop1
, 1);
4379 int len0
= XVECLEN (par0
, 0);
4380 int len1
= XVECLEN (par1
, 0);
4381 rtvec vec
= rtvec_alloc (len0
+ len1
);
4382 for (int i
= 0; i
< len0
; i
++)
4383 RTVEC_ELT (vec
, i
) = XVECEXP (par0
, 0, i
);
4384 for (int i
= 0; i
< len1
; i
++)
4385 RTVEC_ELT (vec
, len0
+ i
) = XVECEXP (par1
, 0, i
);
4386 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (trueop0
, 0),
4387 gen_rtx_PARALLEL (VOIDmode
, vec
));
4396 if (mode
== GET_MODE (op0
)
4397 && mode
== GET_MODE (op1
)
4398 && vec_duplicate_p (op0
, &elt0
)
4399 && vec_duplicate_p (op1
, &elt1
))
4401 /* Try applying the operator to ELT and see if that simplifies.
4402 We can duplicate the result if so.
4404 The reason we don't use simplify_gen_binary is that it isn't
4405 necessarily a win to convert things like:
4407 (plus:V (vec_duplicate:V (reg:S R1))
4408 (vec_duplicate:V (reg:S R2)))
4412 (vec_duplicate:V (plus:S (reg:S R1) (reg:S R2)))
4414 The first might be done entirely in vector registers while the
4415 second might need a move between register files. */
4416 tem
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
4419 return gen_vec_duplicate (mode
, tem
);
4425 /* Return true if binary operation OP distributes over addition in operand
4426 OPNO, with the other operand being held constant. OPNO counts from 1. */
4429 distributes_over_addition_p (rtx_code op
, int opno
)
4447 simplify_const_binary_operation (enum rtx_code code
, machine_mode mode
,
4450 if (VECTOR_MODE_P (mode
)
4451 && code
!= VEC_CONCAT
4452 && GET_CODE (op0
) == CONST_VECTOR
4453 && GET_CODE (op1
) == CONST_VECTOR
)
4456 if (CONST_VECTOR_STEPPED_P (op0
)
4457 && CONST_VECTOR_STEPPED_P (op1
))
4458 /* We can operate directly on the encoding if:
4460 a3 - a2 == a2 - a1 && b3 - b2 == b2 - b1
4462 (a3 op b3) - (a2 op b2) == (a2 op b2) - (a1 op b1)
4464 Addition and subtraction are the supported operators
4465 for which this is true. */
4466 step_ok_p
= (code
== PLUS
|| code
== MINUS
);
4467 else if (CONST_VECTOR_STEPPED_P (op0
))
4468 /* We can operate directly on stepped encodings if:
4472 (a3 op c) - (a2 op c) == (a2 op c) - (a1 op c)
4474 which is true if (x -> x op c) distributes over addition. */
4475 step_ok_p
= distributes_over_addition_p (code
, 1);
4477 /* Similarly in reverse. */
4478 step_ok_p
= distributes_over_addition_p (code
, 2);
4479 rtx_vector_builder builder
;
4480 if (!builder
.new_binary_operation (mode
, op0
, op1
, step_ok_p
))
4483 unsigned int count
= builder
.encoded_nelts ();
4484 for (unsigned int i
= 0; i
< count
; i
++)
4486 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
4487 CONST_VECTOR_ELT (op0
, i
),
4488 CONST_VECTOR_ELT (op1
, i
));
4489 if (!x
|| !valid_for_const_vector_p (mode
, x
))
4491 builder
.quick_push (x
);
4493 return builder
.build ();
4496 if (VECTOR_MODE_P (mode
)
4497 && code
== VEC_CONCAT
4498 && (CONST_SCALAR_INT_P (op0
)
4499 || CONST_FIXED_P (op0
)
4500 || CONST_DOUBLE_AS_FLOAT_P (op0
))
4501 && (CONST_SCALAR_INT_P (op1
)
4502 || CONST_DOUBLE_AS_FLOAT_P (op1
)
4503 || CONST_FIXED_P (op1
)))
4505 /* Both inputs have a constant number of elements, so the result
4507 unsigned n_elts
= GET_MODE_NUNITS (mode
).to_constant ();
4508 rtvec v
= rtvec_alloc (n_elts
);
4510 gcc_assert (n_elts
>= 2);
4513 gcc_assert (GET_CODE (op0
) != CONST_VECTOR
);
4514 gcc_assert (GET_CODE (op1
) != CONST_VECTOR
);
4516 RTVEC_ELT (v
, 0) = op0
;
4517 RTVEC_ELT (v
, 1) = op1
;
4521 unsigned op0_n_elts
= GET_MODE_NUNITS (GET_MODE (op0
)).to_constant ();
4522 unsigned op1_n_elts
= GET_MODE_NUNITS (GET_MODE (op1
)).to_constant ();
4525 gcc_assert (GET_CODE (op0
) == CONST_VECTOR
);
4526 gcc_assert (GET_CODE (op1
) == CONST_VECTOR
);
4527 gcc_assert (op0_n_elts
+ op1_n_elts
== n_elts
);
4529 for (i
= 0; i
< op0_n_elts
; ++i
)
4530 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (op0
, i
);
4531 for (i
= 0; i
< op1_n_elts
; ++i
)
4532 RTVEC_ELT (v
, op0_n_elts
+i
) = CONST_VECTOR_ELT (op1
, i
);
4535 return gen_rtx_CONST_VECTOR (mode
, v
);
4538 if (SCALAR_FLOAT_MODE_P (mode
)
4539 && CONST_DOUBLE_AS_FLOAT_P (op0
)
4540 && CONST_DOUBLE_AS_FLOAT_P (op1
)
4541 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
4552 real_to_target (tmp0
, CONST_DOUBLE_REAL_VALUE (op0
),
4554 real_to_target (tmp1
, CONST_DOUBLE_REAL_VALUE (op1
),
4556 for (i
= 0; i
< 4; i
++)
4573 real_from_target (&r
, tmp0
, mode
);
4574 return const_double_from_real_value (r
, mode
);
4578 REAL_VALUE_TYPE f0
, f1
, value
, result
;
4579 const REAL_VALUE_TYPE
*opr0
, *opr1
;
4582 opr0
= CONST_DOUBLE_REAL_VALUE (op0
);
4583 opr1
= CONST_DOUBLE_REAL_VALUE (op1
);
4585 if (HONOR_SNANS (mode
)
4586 && (REAL_VALUE_ISSIGNALING_NAN (*opr0
)
4587 || REAL_VALUE_ISSIGNALING_NAN (*opr1
)))
4590 real_convert (&f0
, mode
, opr0
);
4591 real_convert (&f1
, mode
, opr1
);
4594 && real_equal (&f1
, &dconst0
)
4595 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
4598 if (MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
4599 && flag_trapping_math
4600 && REAL_VALUE_ISINF (f0
) && REAL_VALUE_ISINF (f1
))
4602 int s0
= REAL_VALUE_NEGATIVE (f0
);
4603 int s1
= REAL_VALUE_NEGATIVE (f1
);
4608 /* Inf + -Inf = NaN plus exception. */
4613 /* Inf - Inf = NaN plus exception. */
4618 /* Inf / Inf = NaN plus exception. */
4625 if (code
== MULT
&& MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
4626 && flag_trapping_math
4627 && ((REAL_VALUE_ISINF (f0
) && real_equal (&f1
, &dconst0
))
4628 || (REAL_VALUE_ISINF (f1
)
4629 && real_equal (&f0
, &dconst0
))))
4630 /* Inf * 0 = NaN plus exception. */
4633 inexact
= real_arithmetic (&value
, rtx_to_tree_code (code
),
4635 real_convert (&result
, mode
, &value
);
4637 /* Don't constant fold this floating point operation if
4638 the result has overflowed and flag_trapping_math. */
4640 if (flag_trapping_math
4641 && MODE_HAS_INFINITIES (mode
)
4642 && REAL_VALUE_ISINF (result
)
4643 && !REAL_VALUE_ISINF (f0
)
4644 && !REAL_VALUE_ISINF (f1
))
4645 /* Overflow plus exception. */
4648 /* Don't constant fold this floating point operation if the
4649 result may dependent upon the run-time rounding mode and
4650 flag_rounding_math is set, or if GCC's software emulation
4651 is unable to accurately represent the result. */
4653 if ((flag_rounding_math
4654 || (MODE_COMPOSITE_P (mode
) && !flag_unsafe_math_optimizations
))
4655 && (inexact
|| !real_identical (&result
, &value
)))
4658 return const_double_from_real_value (result
, mode
);
4662 /* We can fold some multi-word operations. */
4663 scalar_int_mode int_mode
;
4664 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
4665 && CONST_SCALAR_INT_P (op0
)
4666 && CONST_SCALAR_INT_P (op1
)
4667 && GET_MODE_PRECISION (int_mode
) <= MAX_BITSIZE_MODE_ANY_INT
)
4670 wi::overflow_type overflow
;
4671 rtx_mode_t pop0
= rtx_mode_t (op0
, int_mode
);
4672 rtx_mode_t pop1
= rtx_mode_t (op1
, int_mode
);
4674 #if TARGET_SUPPORTS_WIDE_INT == 0
4675 /* This assert keeps the simplification from producing a result
4676 that cannot be represented in a CONST_DOUBLE but a lot of
4677 upstream callers expect that this function never fails to
4678 simplify something and so you if you added this to the test
4679 above the code would die later anyway. If this assert
4680 happens, you just need to make the port support wide int. */
4681 gcc_assert (GET_MODE_PRECISION (int_mode
) <= HOST_BITS_PER_DOUBLE_INT
);
4686 result
= wi::sub (pop0
, pop1
);
4690 result
= wi::add (pop0
, pop1
);
4694 result
= wi::mul (pop0
, pop1
);
4698 result
= wi::div_trunc (pop0
, pop1
, SIGNED
, &overflow
);
4704 result
= wi::mod_trunc (pop0
, pop1
, SIGNED
, &overflow
);
4710 result
= wi::div_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
4716 result
= wi::mod_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
4722 result
= wi::bit_and (pop0
, pop1
);
4726 result
= wi::bit_or (pop0
, pop1
);
4730 result
= wi::bit_xor (pop0
, pop1
);
4734 result
= wi::smin (pop0
, pop1
);
4738 result
= wi::smax (pop0
, pop1
);
4742 result
= wi::umin (pop0
, pop1
);
4746 result
= wi::umax (pop0
, pop1
);
4753 wide_int wop1
= pop1
;
4754 if (SHIFT_COUNT_TRUNCATED
)
4755 wop1
= wi::umod_trunc (wop1
, GET_MODE_PRECISION (int_mode
));
4756 else if (wi::geu_p (wop1
, GET_MODE_PRECISION (int_mode
)))
4762 result
= wi::lrshift (pop0
, wop1
);
4766 result
= wi::arshift (pop0
, wop1
);
4770 result
= wi::lshift (pop0
, wop1
);
4781 if (wi::neg_p (pop1
))
4787 result
= wi::lrotate (pop0
, pop1
);
4791 result
= wi::rrotate (pop0
, pop1
);
4802 return immed_wide_int_const (result
, int_mode
);
4805 /* Handle polynomial integers. */
4806 if (NUM_POLY_INT_COEFFS
> 1
4807 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
4808 && poly_int_rtx_p (op0
)
4809 && poly_int_rtx_p (op1
))
4811 poly_wide_int result
;
4815 result
= wi::to_poly_wide (op0
, mode
) + wi::to_poly_wide (op1
, mode
);
4819 result
= wi::to_poly_wide (op0
, mode
) - wi::to_poly_wide (op1
, mode
);
4823 if (CONST_SCALAR_INT_P (op1
))
4824 result
= wi::to_poly_wide (op0
, mode
) * rtx_mode_t (op1
, mode
);
4830 if (CONST_SCALAR_INT_P (op1
))
4832 wide_int shift
= rtx_mode_t (op1
, mode
);
4833 if (SHIFT_COUNT_TRUNCATED
)
4834 shift
= wi::umod_trunc (shift
, GET_MODE_PRECISION (int_mode
));
4835 else if (wi::geu_p (shift
, GET_MODE_PRECISION (int_mode
)))
4837 result
= wi::to_poly_wide (op0
, mode
) << shift
;
4844 if (!CONST_SCALAR_INT_P (op1
)
4845 || !can_ior_p (wi::to_poly_wide (op0
, mode
),
4846 rtx_mode_t (op1
, mode
), &result
))
4853 return immed_wide_int_const (result
, int_mode
);
4861 /* Return a positive integer if X should sort after Y. The value
4862 returned is 1 if and only if X and Y are both regs. */
4865 simplify_plus_minus_op_data_cmp (rtx x
, rtx y
)
4869 result
= (commutative_operand_precedence (y
)
4870 - commutative_operand_precedence (x
));
4872 return result
+ result
;
4874 /* Group together equal REGs to do more simplification. */
4875 if (REG_P (x
) && REG_P (y
))
4876 return REGNO (x
) > REGNO (y
);
4881 /* Simplify and canonicalize a PLUS or MINUS, at least one of whose
4882 operands may be another PLUS or MINUS.
4884 Rather than test for specific case, we do this by a brute-force method
4885 and do all possible simplifications until no more changes occur. Then
4886 we rebuild the operation.
4888 May return NULL_RTX when no changes were made. */
4891 simplify_plus_minus (enum rtx_code code
, machine_mode mode
, rtx op0
,
4894 struct simplify_plus_minus_op_data
4901 int changed
, n_constants
, canonicalized
= 0;
4904 memset (ops
, 0, sizeof ops
);
4906 /* Set up the two operands and then expand them until nothing has been
4907 changed. If we run out of room in our array, give up; this should
4908 almost never happen. */
4913 ops
[1].neg
= (code
== MINUS
);
4920 for (i
= 0; i
< n_ops
; i
++)
4922 rtx this_op
= ops
[i
].op
;
4923 int this_neg
= ops
[i
].neg
;
4924 enum rtx_code this_code
= GET_CODE (this_op
);
4930 if (n_ops
== ARRAY_SIZE (ops
))
4933 ops
[n_ops
].op
= XEXP (this_op
, 1);
4934 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
4937 ops
[i
].op
= XEXP (this_op
, 0);
4939 /* If this operand was negated then we will potentially
4940 canonicalize the expression. Similarly if we don't
4941 place the operands adjacent we're re-ordering the
4942 expression and thus might be performing a
4943 canonicalization. Ignore register re-ordering.
4944 ??? It might be better to shuffle the ops array here,
4945 but then (plus (plus (A, B), plus (C, D))) wouldn't
4946 be seen as non-canonical. */
4949 && !(REG_P (ops
[i
].op
) && REG_P (ops
[n_ops
- 1].op
))))
4954 ops
[i
].op
= XEXP (this_op
, 0);
4955 ops
[i
].neg
= ! this_neg
;
4961 if (n_ops
!= ARRAY_SIZE (ops
)
4962 && GET_CODE (XEXP (this_op
, 0)) == PLUS
4963 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
4964 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
4966 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
4967 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
4968 ops
[n_ops
].neg
= this_neg
;
4976 /* ~a -> (-a - 1) */
4977 if (n_ops
!= ARRAY_SIZE (ops
))
4979 ops
[n_ops
].op
= CONSTM1_RTX (mode
);
4980 ops
[n_ops
++].neg
= this_neg
;
4981 ops
[i
].op
= XEXP (this_op
, 0);
4982 ops
[i
].neg
= !this_neg
;
4988 CASE_CONST_SCALAR_INT
:
4989 case CONST_POLY_INT
:
4993 ops
[i
].op
= neg_poly_int_rtx (mode
, this_op
);
5007 if (n_constants
> 1)
5010 gcc_assert (n_ops
>= 2);
5012 /* If we only have two operands, we can avoid the loops. */
5015 enum rtx_code code
= ops
[0].neg
|| ops
[1].neg
? MINUS
: PLUS
;
5018 /* Get the two operands. Be careful with the order, especially for
5019 the cases where code == MINUS. */
5020 if (ops
[0].neg
&& ops
[1].neg
)
5022 lhs
= gen_rtx_NEG (mode
, ops
[0].op
);
5025 else if (ops
[0].neg
)
5036 return simplify_const_binary_operation (code
, mode
, lhs
, rhs
);
5039 /* Now simplify each pair of operands until nothing changes. */
5042 /* Insertion sort is good enough for a small array. */
5043 for (i
= 1; i
< n_ops
; i
++)
5045 struct simplify_plus_minus_op_data save
;
5049 cmp
= simplify_plus_minus_op_data_cmp (ops
[j
].op
, ops
[i
].op
);
5052 /* Just swapping registers doesn't count as canonicalization. */
5058 ops
[j
+ 1] = ops
[j
];
5060 && simplify_plus_minus_op_data_cmp (ops
[j
].op
, save
.op
) > 0);
5065 for (i
= n_ops
- 1; i
> 0; i
--)
5066 for (j
= i
- 1; j
>= 0; j
--)
5068 rtx lhs
= ops
[j
].op
, rhs
= ops
[i
].op
;
5069 int lneg
= ops
[j
].neg
, rneg
= ops
[i
].neg
;
5071 if (lhs
!= 0 && rhs
!= 0)
5073 enum rtx_code ncode
= PLUS
;
5079 std::swap (lhs
, rhs
);
5081 else if (swap_commutative_operands_p (lhs
, rhs
))
5082 std::swap (lhs
, rhs
);
5084 if ((GET_CODE (lhs
) == CONST
|| CONST_INT_P (lhs
))
5085 && (GET_CODE (rhs
) == CONST
|| CONST_INT_P (rhs
)))
5087 rtx tem_lhs
, tem_rhs
;
5089 tem_lhs
= GET_CODE (lhs
) == CONST
? XEXP (lhs
, 0) : lhs
;
5090 tem_rhs
= GET_CODE (rhs
) == CONST
? XEXP (rhs
, 0) : rhs
;
5091 tem
= simplify_binary_operation (ncode
, mode
, tem_lhs
,
5094 if (tem
&& !CONSTANT_P (tem
))
5095 tem
= gen_rtx_CONST (GET_MODE (tem
), tem
);
5098 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
5102 /* Reject "simplifications" that just wrap the two
5103 arguments in a CONST. Failure to do so can result
5104 in infinite recursion with simplify_binary_operation
5105 when it calls us to simplify CONST operations.
5106 Also, if we find such a simplification, don't try
5107 any more combinations with this rhs: We must have
5108 something like symbol+offset, ie. one of the
5109 trivial CONST expressions we handle later. */
5110 if (GET_CODE (tem
) == CONST
5111 && GET_CODE (XEXP (tem
, 0)) == ncode
5112 && XEXP (XEXP (tem
, 0), 0) == lhs
5113 && XEXP (XEXP (tem
, 0), 1) == rhs
)
5116 if (GET_CODE (tem
) == NEG
)
5117 tem
= XEXP (tem
, 0), lneg
= !lneg
;
5118 if (poly_int_rtx_p (tem
) && lneg
)
5119 tem
= neg_poly_int_rtx (mode
, tem
), lneg
= 0;
5123 ops
[j
].op
= NULL_RTX
;
5133 /* Pack all the operands to the lower-numbered entries. */
5134 for (i
= 0, j
= 0; j
< n_ops
; j
++)
5143 /* If nothing changed, check that rematerialization of rtl instructions
5144 is still required. */
5147 /* Perform rematerialization if only all operands are registers and
5148 all operations are PLUS. */
5149 /* ??? Also disallow (non-global, non-frame) fixed registers to work
5150 around rs6000 and how it uses the CA register. See PR67145. */
5151 for (i
= 0; i
< n_ops
; i
++)
5153 || !REG_P (ops
[i
].op
)
5154 || (REGNO (ops
[i
].op
) < FIRST_PSEUDO_REGISTER
5155 && fixed_regs
[REGNO (ops
[i
].op
)]
5156 && !global_regs
[REGNO (ops
[i
].op
)]
5157 && ops
[i
].op
!= frame_pointer_rtx
5158 && ops
[i
].op
!= arg_pointer_rtx
5159 && ops
[i
].op
!= stack_pointer_rtx
))
5164 /* Create (minus -C X) instead of (neg (const (plus X C))). */
5166 && CONST_INT_P (ops
[1].op
)
5167 && CONSTANT_P (ops
[0].op
)
5169 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
5171 /* We suppressed creation of trivial CONST expressions in the
5172 combination loop to avoid recursion. Create one manually now.
5173 The combination loop should have ensured that there is exactly
5174 one CONST_INT, and the sort will have ensured that it is last
5175 in the array and that any other constant will be next-to-last. */
5178 && poly_int_rtx_p (ops
[n_ops
- 1].op
)
5179 && CONSTANT_P (ops
[n_ops
- 2].op
))
5181 rtx value
= ops
[n_ops
- 1].op
;
5182 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
5183 value
= neg_poly_int_rtx (mode
, value
);
5184 if (CONST_INT_P (value
))
5186 ops
[n_ops
- 2].op
= plus_constant (mode
, ops
[n_ops
- 2].op
,
5192 /* Put a non-negated operand first, if possible. */
5194 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
5197 ops
[0].op
= gen_rtx_NEG (mode
, ops
[0].op
);
5206 /* Now make the result by performing the requested operations. */
5209 for (i
= 1; i
< n_ops
; i
++)
5210 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
5211 mode
, result
, ops
[i
].op
);
5216 /* Check whether an operand is suitable for calling simplify_plus_minus. */
5218 plus_minus_operand_p (const_rtx x
)
5220 return GET_CODE (x
) == PLUS
5221 || GET_CODE (x
) == MINUS
5222 || (GET_CODE (x
) == CONST
5223 && GET_CODE (XEXP (x
, 0)) == PLUS
5224 && CONSTANT_P (XEXP (XEXP (x
, 0), 0))
5225 && CONSTANT_P (XEXP (XEXP (x
, 0), 1)));
5228 /* Like simplify_binary_operation except used for relational operators.
5229 MODE is the mode of the result. If MODE is VOIDmode, both operands must
5230 not also be VOIDmode.
5232 CMP_MODE specifies in which mode the comparison is done in, so it is
5233 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
5234 the operands or, if both are VOIDmode, the operands are compared in
5235 "infinite precision". */
5237 simplify_relational_operation (enum rtx_code code
, machine_mode mode
,
5238 machine_mode cmp_mode
, rtx op0
, rtx op1
)
5240 rtx tem
, trueop0
, trueop1
;
5242 if (cmp_mode
== VOIDmode
)
5243 cmp_mode
= GET_MODE (op0
);
5244 if (cmp_mode
== VOIDmode
)
5245 cmp_mode
= GET_MODE (op1
);
5247 tem
= simplify_const_relational_operation (code
, cmp_mode
, op0
, op1
);
5250 if (SCALAR_FLOAT_MODE_P (mode
))
5252 if (tem
== const0_rtx
)
5253 return CONST0_RTX (mode
);
5254 #ifdef FLOAT_STORE_FLAG_VALUE
5256 REAL_VALUE_TYPE val
;
5257 val
= FLOAT_STORE_FLAG_VALUE (mode
);
5258 return const_double_from_real_value (val
, mode
);
5264 if (VECTOR_MODE_P (mode
))
5266 if (tem
== const0_rtx
)
5267 return CONST0_RTX (mode
);
5268 #ifdef VECTOR_STORE_FLAG_VALUE
5270 rtx val
= VECTOR_STORE_FLAG_VALUE (mode
);
5271 if (val
== NULL_RTX
)
5273 if (val
== const1_rtx
)
5274 return CONST1_RTX (mode
);
5276 return gen_const_vec_duplicate (mode
, val
);
5282 /* For vector comparison with scalar int result, it is unknown
5283 if the target means here a comparison into an integral bitmask,
5284 or comparison where all comparisons true mean const_true_rtx
5285 whole result, or where any comparisons true mean const_true_rtx
5286 whole result. For const0_rtx all the cases are the same. */
5287 if (VECTOR_MODE_P (cmp_mode
)
5288 && SCALAR_INT_MODE_P (mode
)
5289 && tem
== const_true_rtx
)
5295 /* For the following tests, ensure const0_rtx is op1. */
5296 if (swap_commutative_operands_p (op0
, op1
)
5297 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
5298 std::swap (op0
, op1
), code
= swap_condition (code
);
5300 /* If op0 is a compare, extract the comparison arguments from it. */
5301 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
5302 return simplify_gen_relational (code
, mode
, VOIDmode
,
5303 XEXP (op0
, 0), XEXP (op0
, 1));
5305 if (GET_MODE_CLASS (cmp_mode
) == MODE_CC
5309 trueop0
= avoid_constant_pool_reference (op0
);
5310 trueop1
= avoid_constant_pool_reference (op1
);
5311 return simplify_relational_operation_1 (code
, mode
, cmp_mode
,
5315 /* This part of simplify_relational_operation is only used when CMP_MODE
5316 is not in class MODE_CC (i.e. it is a real comparison).
5318 MODE is the mode of the result, while CMP_MODE specifies in which
5319 mode the comparison is done in, so it is the mode of the operands. */
5322 simplify_relational_operation_1 (enum rtx_code code
, machine_mode mode
,
5323 machine_mode cmp_mode
, rtx op0
, rtx op1
)
5325 enum rtx_code op0code
= GET_CODE (op0
);
5327 if (op1
== const0_rtx
&& COMPARISON_P (op0
))
5329 /* If op0 is a comparison, extract the comparison arguments
5333 if (GET_MODE (op0
) == mode
)
5334 return simplify_rtx (op0
);
5336 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
5337 XEXP (op0
, 0), XEXP (op0
, 1));
5339 else if (code
== EQ
)
5341 enum rtx_code new_code
= reversed_comparison_code (op0
, NULL
);
5342 if (new_code
!= UNKNOWN
)
5343 return simplify_gen_relational (new_code
, mode
, VOIDmode
,
5344 XEXP (op0
, 0), XEXP (op0
, 1));
5348 /* (LTU/GEU (PLUS a C) C), where C is constant, can be simplified to
5349 (GEU/LTU a -C). Likewise for (LTU/GEU (PLUS a C) a). */
5350 if ((code
== LTU
|| code
== GEU
)
5351 && GET_CODE (op0
) == PLUS
5352 && CONST_INT_P (XEXP (op0
, 1))
5353 && (rtx_equal_p (op1
, XEXP (op0
, 0))
5354 || rtx_equal_p (op1
, XEXP (op0
, 1)))
5355 /* (LTU/GEU (PLUS a 0) 0) is not the same as (GEU/LTU a 0). */
5356 && XEXP (op0
, 1) != const0_rtx
)
5359 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
5360 return simplify_gen_relational ((code
== LTU
? GEU
: LTU
), mode
,
5361 cmp_mode
, XEXP (op0
, 0), new_cmp
);
5364 /* (GTU (PLUS a C) (C - 1)) where C is a non-zero constant can be
5365 transformed into (LTU a -C). */
5366 if (code
== GTU
&& GET_CODE (op0
) == PLUS
&& CONST_INT_P (op1
)
5367 && CONST_INT_P (XEXP (op0
, 1))
5368 && (UINTVAL (op1
) == UINTVAL (XEXP (op0
, 1)) - 1)
5369 && XEXP (op0
, 1) != const0_rtx
)
5372 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
5373 return simplify_gen_relational (LTU
, mode
, cmp_mode
,
5374 XEXP (op0
, 0), new_cmp
);
5377 /* Canonicalize (LTU/GEU (PLUS a b) b) as (LTU/GEU (PLUS a b) a). */
5378 if ((code
== LTU
|| code
== GEU
)
5379 && GET_CODE (op0
) == PLUS
5380 && rtx_equal_p (op1
, XEXP (op0
, 1))
5381 /* Don't recurse "infinitely" for (LTU/GEU (PLUS b b) b). */
5382 && !rtx_equal_p (op1
, XEXP (op0
, 0)))
5383 return simplify_gen_relational (code
, mode
, cmp_mode
, op0
,
5384 copy_rtx (XEXP (op0
, 0)));
5386 if (op1
== const0_rtx
)
5388 /* Canonicalize (GTU x 0) as (NE x 0). */
5390 return simplify_gen_relational (NE
, mode
, cmp_mode
, op0
, op1
);
5391 /* Canonicalize (LEU x 0) as (EQ x 0). */
5393 return simplify_gen_relational (EQ
, mode
, cmp_mode
, op0
, op1
);
5395 else if (op1
== const1_rtx
)
5400 /* Canonicalize (GE x 1) as (GT x 0). */
5401 return simplify_gen_relational (GT
, mode
, cmp_mode
,
5404 /* Canonicalize (GEU x 1) as (NE x 0). */
5405 return simplify_gen_relational (NE
, mode
, cmp_mode
,
5408 /* Canonicalize (LT x 1) as (LE x 0). */
5409 return simplify_gen_relational (LE
, mode
, cmp_mode
,
5412 /* Canonicalize (LTU x 1) as (EQ x 0). */
5413 return simplify_gen_relational (EQ
, mode
, cmp_mode
,
5419 else if (op1
== constm1_rtx
)
5421 /* Canonicalize (LE x -1) as (LT x 0). */
5423 return simplify_gen_relational (LT
, mode
, cmp_mode
, op0
, const0_rtx
);
5424 /* Canonicalize (GT x -1) as (GE x 0). */
5426 return simplify_gen_relational (GE
, mode
, cmp_mode
, op0
, const0_rtx
);
5429 /* (eq/ne (plus x cst1) cst2) simplifies to (eq/ne x (cst2 - cst1)) */
5430 if ((code
== EQ
|| code
== NE
)
5431 && (op0code
== PLUS
|| op0code
== MINUS
)
5433 && CONSTANT_P (XEXP (op0
, 1))
5434 && (INTEGRAL_MODE_P (cmp_mode
) || flag_unsafe_math_optimizations
))
5436 rtx x
= XEXP (op0
, 0);
5437 rtx c
= XEXP (op0
, 1);
5438 enum rtx_code invcode
= op0code
== PLUS
? MINUS
: PLUS
;
5439 rtx tem
= simplify_gen_binary (invcode
, cmp_mode
, op1
, c
);
5441 /* Detect an infinite recursive condition, where we oscillate at this
5442 simplification case between:
5443 A + B == C <---> C - B == A,
5444 where A, B, and C are all constants with non-simplifiable expressions,
5445 usually SYMBOL_REFs. */
5446 if (GET_CODE (tem
) == invcode
5448 && rtx_equal_p (c
, XEXP (tem
, 1)))
5451 return simplify_gen_relational (code
, mode
, cmp_mode
, x
, tem
);
5454 /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is
5455 the same as (zero_extract:SI FOO (const_int 1) BAR). */
5456 scalar_int_mode int_mode
, int_cmp_mode
;
5458 && op1
== const0_rtx
5459 && is_int_mode (mode
, &int_mode
)
5460 && is_a
<scalar_int_mode
> (cmp_mode
, &int_cmp_mode
)
5461 /* ??? Work-around BImode bugs in the ia64 backend. */
5462 && int_mode
!= BImode
5463 && int_cmp_mode
!= BImode
5464 && nonzero_bits (op0
, int_cmp_mode
) == 1
5465 && STORE_FLAG_VALUE
== 1)
5466 return GET_MODE_SIZE (int_mode
) > GET_MODE_SIZE (int_cmp_mode
)
5467 ? simplify_gen_unary (ZERO_EXTEND
, int_mode
, op0
, int_cmp_mode
)
5468 : lowpart_subreg (int_mode
, op0
, int_cmp_mode
);
5470 /* (eq/ne (xor x y) 0) simplifies to (eq/ne x y). */
5471 if ((code
== EQ
|| code
== NE
)
5472 && op1
== const0_rtx
5474 return simplify_gen_relational (code
, mode
, cmp_mode
,
5475 XEXP (op0
, 0), XEXP (op0
, 1));
5477 /* (eq/ne (xor x y) x) simplifies to (eq/ne y 0). */
5478 if ((code
== EQ
|| code
== NE
)
5480 && rtx_equal_p (XEXP (op0
, 0), op1
)
5481 && !side_effects_p (XEXP (op0
, 0)))
5482 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 1),
5485 /* Likewise (eq/ne (xor x y) y) simplifies to (eq/ne x 0). */
5486 if ((code
== EQ
|| code
== NE
)
5488 && rtx_equal_p (XEXP (op0
, 1), op1
)
5489 && !side_effects_p (XEXP (op0
, 1)))
5490 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
5493 /* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
5494 if ((code
== EQ
|| code
== NE
)
5496 && CONST_SCALAR_INT_P (op1
)
5497 && CONST_SCALAR_INT_P (XEXP (op0
, 1)))
5498 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
5499 simplify_gen_binary (XOR
, cmp_mode
,
5500 XEXP (op0
, 1), op1
));
5502 /* Simplify eq/ne (and/ior x y) x/y) for targets with a BICS instruction or
5503 constant folding if x/y is a constant. */
5504 if ((code
== EQ
|| code
== NE
)
5505 && (op0code
== AND
|| op0code
== IOR
)
5506 && !side_effects_p (op1
)
5507 && op1
!= CONST0_RTX (cmp_mode
))
5509 /* Both (eq/ne (and x y) x) and (eq/ne (ior x y) y) simplify to
5510 (eq/ne (and (not y) x) 0). */
5511 if ((op0code
== AND
&& rtx_equal_p (XEXP (op0
, 0), op1
))
5512 || (op0code
== IOR
&& rtx_equal_p (XEXP (op0
, 1), op1
)))
5514 rtx not_y
= simplify_gen_unary (NOT
, cmp_mode
, XEXP (op0
, 1),
5516 rtx lhs
= simplify_gen_binary (AND
, cmp_mode
, not_y
, XEXP (op0
, 0));
5518 return simplify_gen_relational (code
, mode
, cmp_mode
, lhs
,
5519 CONST0_RTX (cmp_mode
));
5522 /* Both (eq/ne (and x y) y) and (eq/ne (ior x y) x) simplify to
5523 (eq/ne (and (not x) y) 0). */
5524 if ((op0code
== AND
&& rtx_equal_p (XEXP (op0
, 1), op1
))
5525 || (op0code
== IOR
&& rtx_equal_p (XEXP (op0
, 0), op1
)))
5527 rtx not_x
= simplify_gen_unary (NOT
, cmp_mode
, XEXP (op0
, 0),
5529 rtx lhs
= simplify_gen_binary (AND
, cmp_mode
, not_x
, XEXP (op0
, 1));
5531 return simplify_gen_relational (code
, mode
, cmp_mode
, lhs
,
5532 CONST0_RTX (cmp_mode
));
5536 /* (eq/ne (bswap x) C1) simplifies to (eq/ne x C2) with C2 swapped. */
5537 if ((code
== EQ
|| code
== NE
)
5538 && GET_CODE (op0
) == BSWAP
5539 && CONST_SCALAR_INT_P (op1
))
5540 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
5541 simplify_gen_unary (BSWAP
, cmp_mode
,
5544 /* (eq/ne (bswap x) (bswap y)) simplifies to (eq/ne x y). */
5545 if ((code
== EQ
|| code
== NE
)
5546 && GET_CODE (op0
) == BSWAP
5547 && GET_CODE (op1
) == BSWAP
)
5548 return simplify_gen_relational (code
, mode
, cmp_mode
,
5549 XEXP (op0
, 0), XEXP (op1
, 0));
5551 if (op0code
== POPCOUNT
&& op1
== const0_rtx
)
5557 /* (eq (popcount x) (const_int 0)) -> (eq x (const_int 0)). */
5558 return simplify_gen_relational (EQ
, mode
, GET_MODE (XEXP (op0
, 0)),
5559 XEXP (op0
, 0), const0_rtx
);
5564 /* (ne (popcount x) (const_int 0)) -> (ne x (const_int 0)). */
5565 return simplify_gen_relational (NE
, mode
, GET_MODE (XEXP (op0
, 0)),
5566 XEXP (op0
, 0), const0_rtx
);
5585 /* Convert the known results for EQ, LT, GT, LTU, GTU contained in
5586 KNOWN_RESULT to a CONST_INT, based on the requested comparison CODE
5587 For KNOWN_RESULT to make sense it should be either CMP_EQ, or the
5588 logical OR of one of (CMP_LT, CMP_GT) and one of (CMP_LTU, CMP_GTU).
5589 For floating-point comparisons, assume that the operands were ordered. */
5592 comparison_result (enum rtx_code code
, int known_results
)
5598 return (known_results
& CMP_EQ
) ? const_true_rtx
: const0_rtx
;
5601 return (known_results
& CMP_EQ
) ? const0_rtx
: const_true_rtx
;
5605 return (known_results
& CMP_LT
) ? const_true_rtx
: const0_rtx
;
5608 return (known_results
& CMP_LT
) ? const0_rtx
: const_true_rtx
;
5612 return (known_results
& CMP_GT
) ? const_true_rtx
: const0_rtx
;
5615 return (known_results
& CMP_GT
) ? const0_rtx
: const_true_rtx
;
5618 return (known_results
& CMP_LTU
) ? const_true_rtx
: const0_rtx
;
5620 return (known_results
& CMP_LTU
) ? const0_rtx
: const_true_rtx
;
5623 return (known_results
& CMP_GTU
) ? const_true_rtx
: const0_rtx
;
5625 return (known_results
& CMP_GTU
) ? const0_rtx
: const_true_rtx
;
5628 return const_true_rtx
;
5636 /* Check if the given comparison (done in the given MODE) is actually
5637 a tautology or a contradiction. If the mode is VOIDmode, the
5638 comparison is done in "infinite precision". If no simplification
5639 is possible, this function returns zero. Otherwise, it returns
5640 either const_true_rtx or const0_rtx. */
5643 simplify_const_relational_operation (enum rtx_code code
,
5651 gcc_assert (mode
!= VOIDmode
5652 || (GET_MODE (op0
) == VOIDmode
5653 && GET_MODE (op1
) == VOIDmode
));
5655 /* If op0 is a compare, extract the comparison arguments from it. */
5656 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
5658 op1
= XEXP (op0
, 1);
5659 op0
= XEXP (op0
, 0);
5661 if (GET_MODE (op0
) != VOIDmode
)
5662 mode
= GET_MODE (op0
);
5663 else if (GET_MODE (op1
) != VOIDmode
)
5664 mode
= GET_MODE (op1
);
5669 /* We can't simplify MODE_CC values since we don't know what the
5670 actual comparison is. */
5671 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
5674 /* Make sure the constant is second. */
5675 if (swap_commutative_operands_p (op0
, op1
))
5677 std::swap (op0
, op1
);
5678 code
= swap_condition (code
);
5681 trueop0
= avoid_constant_pool_reference (op0
);
5682 trueop1
= avoid_constant_pool_reference (op1
);
5684 /* For integer comparisons of A and B maybe we can simplify A - B and can
5685 then simplify a comparison of that with zero. If A and B are both either
5686 a register or a CONST_INT, this can't help; testing for these cases will
5687 prevent infinite recursion here and speed things up.
5689 We can only do this for EQ and NE comparisons as otherwise we may
5690 lose or introduce overflow which we cannot disregard as undefined as
5691 we do not know the signedness of the operation on either the left or
5692 the right hand side of the comparison. */
5694 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
5695 && (code
== EQ
|| code
== NE
)
5696 && ! ((REG_P (op0
) || CONST_INT_P (trueop0
))
5697 && (REG_P (op1
) || CONST_INT_P (trueop1
)))
5698 && (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
)) != 0
5699 /* We cannot do this if tem is a nonzero address. */
5700 && ! nonzero_address_p (tem
))
5701 return simplify_const_relational_operation (signed_condition (code
),
5702 mode
, tem
, const0_rtx
);
5704 if (! HONOR_NANS (mode
) && code
== ORDERED
)
5705 return const_true_rtx
;
5707 if (! HONOR_NANS (mode
) && code
== UNORDERED
)
5710 /* For modes without NaNs, if the two operands are equal, we know the
5711 result except if they have side-effects. Even with NaNs we know
5712 the result of unordered comparisons and, if signaling NaNs are
5713 irrelevant, also the result of LT/GT/LTGT. */
5714 if ((! HONOR_NANS (trueop0
)
5715 || code
== UNEQ
|| code
== UNLE
|| code
== UNGE
5716 || ((code
== LT
|| code
== GT
|| code
== LTGT
)
5717 && ! HONOR_SNANS (trueop0
)))
5718 && rtx_equal_p (trueop0
, trueop1
)
5719 && ! side_effects_p (trueop0
))
5720 return comparison_result (code
, CMP_EQ
);
5722 /* If the operands are floating-point constants, see if we can fold
5724 if (CONST_DOUBLE_AS_FLOAT_P (trueop0
)
5725 && CONST_DOUBLE_AS_FLOAT_P (trueop1
)
5726 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0
)))
5728 const REAL_VALUE_TYPE
*d0
= CONST_DOUBLE_REAL_VALUE (trueop0
);
5729 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
5731 /* Comparisons are unordered iff at least one of the values is NaN. */
5732 if (REAL_VALUE_ISNAN (*d0
) || REAL_VALUE_ISNAN (*d1
))
5742 return const_true_rtx
;
5755 return comparison_result (code
,
5756 (real_equal (d0
, d1
) ? CMP_EQ
:
5757 real_less (d0
, d1
) ? CMP_LT
: CMP_GT
));
5760 /* Otherwise, see if the operands are both integers. */
5761 if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
5762 && CONST_SCALAR_INT_P (trueop0
) && CONST_SCALAR_INT_P (trueop1
))
5764 /* It would be nice if we really had a mode here. However, the
5765 largest int representable on the target is as good as
5767 machine_mode cmode
= (mode
== VOIDmode
) ? MAX_MODE_INT
: mode
;
5768 rtx_mode_t ptrueop0
= rtx_mode_t (trueop0
, cmode
);
5769 rtx_mode_t ptrueop1
= rtx_mode_t (trueop1
, cmode
);
5771 if (wi::eq_p (ptrueop0
, ptrueop1
))
5772 return comparison_result (code
, CMP_EQ
);
5775 int cr
= wi::lts_p (ptrueop0
, ptrueop1
) ? CMP_LT
: CMP_GT
;
5776 cr
|= wi::ltu_p (ptrueop0
, ptrueop1
) ? CMP_LTU
: CMP_GTU
;
5777 return comparison_result (code
, cr
);
5781 /* Optimize comparisons with upper and lower bounds. */
5782 scalar_int_mode int_mode
;
5783 if (CONST_INT_P (trueop1
)
5784 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5785 && HWI_COMPUTABLE_MODE_P (int_mode
)
5786 && !side_effects_p (trueop0
))
5789 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (trueop0
, int_mode
);
5790 HOST_WIDE_INT val
= INTVAL (trueop1
);
5791 HOST_WIDE_INT mmin
, mmax
;
5801 /* Get a reduced range if the sign bit is zero. */
5802 if (nonzero
<= (GET_MODE_MASK (int_mode
) >> 1))
5809 rtx mmin_rtx
, mmax_rtx
;
5810 get_mode_bounds (int_mode
, sign
, int_mode
, &mmin_rtx
, &mmax_rtx
);
5812 mmin
= INTVAL (mmin_rtx
);
5813 mmax
= INTVAL (mmax_rtx
);
5816 unsigned int sign_copies
5817 = num_sign_bit_copies (trueop0
, int_mode
);
5819 mmin
>>= (sign_copies
- 1);
5820 mmax
>>= (sign_copies
- 1);
5826 /* x >= y is always true for y <= mmin, always false for y > mmax. */
5828 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
5829 return const_true_rtx
;
5830 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
5835 return const_true_rtx
;
5840 /* x <= y is always true for y >= mmax, always false for y < mmin. */
5842 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
5843 return const_true_rtx
;
5844 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
5849 return const_true_rtx
;
5855 /* x == y is always false for y out of range. */
5856 if (val
< mmin
|| val
> mmax
)
5860 /* x > y is always false for y >= mmax, always true for y < mmin. */
5862 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
5864 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
5865 return const_true_rtx
;
5871 return const_true_rtx
;
5874 /* x < y is always false for y <= mmin, always true for y > mmax. */
5876 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
5878 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
5879 return const_true_rtx
;
5885 return const_true_rtx
;
5889 /* x != y is always true for y out of range. */
5890 if (val
< mmin
|| val
> mmax
)
5891 return const_true_rtx
;
5899 /* Optimize integer comparisons with zero. */
5900 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
5901 && trueop1
== const0_rtx
5902 && !side_effects_p (trueop0
))
5904 /* Some addresses are known to be nonzero. We don't know
5905 their sign, but equality comparisons are known. */
5906 if (nonzero_address_p (trueop0
))
5908 if (code
== EQ
|| code
== LEU
)
5910 if (code
== NE
|| code
== GTU
)
5911 return const_true_rtx
;
5914 /* See if the first operand is an IOR with a constant. If so, we
5915 may be able to determine the result of this comparison. */
5916 if (GET_CODE (op0
) == IOR
)
5918 rtx inner_const
= avoid_constant_pool_reference (XEXP (op0
, 1));
5919 if (CONST_INT_P (inner_const
) && inner_const
!= const0_rtx
)
5921 int sign_bitnum
= GET_MODE_PRECISION (int_mode
) - 1;
5922 int has_sign
= (HOST_BITS_PER_WIDE_INT
>= sign_bitnum
5923 && (UINTVAL (inner_const
)
5934 return const_true_rtx
;
5938 return const_true_rtx
;
5952 /* Optimize comparison of ABS with zero. */
5953 if (trueop1
== CONST0_RTX (mode
) && !side_effects_p (trueop0
)
5954 && (GET_CODE (trueop0
) == ABS
5955 || (GET_CODE (trueop0
) == FLOAT_EXTEND
5956 && GET_CODE (XEXP (trueop0
, 0)) == ABS
)))
5961 /* Optimize abs(x) < 0.0. */
5962 if (!INTEGRAL_MODE_P (mode
) && !HONOR_SNANS (mode
))
5967 /* Optimize abs(x) >= 0.0. */
5968 if (!INTEGRAL_MODE_P (mode
) && !HONOR_NANS (mode
))
5969 return const_true_rtx
;
5973 /* Optimize ! (abs(x) < 0.0). */
5974 return const_true_rtx
;
5984 /* Recognize expressions of the form (X CMP 0) ? VAL : OP (X)
5985 where OP is CLZ or CTZ and VAL is the value from CLZ_DEFINED_VALUE_AT_ZERO
5986 or CTZ_DEFINED_VALUE_AT_ZERO respectively and return OP (X) if the expression
5987 can be simplified to that or NULL_RTX if not.
5988 Assume X is compared against zero with CMP_CODE and the true
5989 arm is TRUE_VAL and the false arm is FALSE_VAL. */
5992 simplify_cond_clz_ctz (rtx x
, rtx_code cmp_code
, rtx true_val
, rtx false_val
)
5994 if (cmp_code
!= EQ
&& cmp_code
!= NE
)
5997 /* Result on X == 0 and X !=0 respectively. */
5998 rtx on_zero
, on_nonzero
;
6002 on_nonzero
= false_val
;
6006 on_zero
= false_val
;
6007 on_nonzero
= true_val
;
6010 rtx_code op_code
= GET_CODE (on_nonzero
);
6011 if ((op_code
!= CLZ
&& op_code
!= CTZ
)
6012 || !rtx_equal_p (XEXP (on_nonzero
, 0), x
)
6013 || !CONST_INT_P (on_zero
))
6016 HOST_WIDE_INT op_val
;
6017 scalar_int_mode mode ATTRIBUTE_UNUSED
6018 = as_a
<scalar_int_mode
> (GET_MODE (XEXP (on_nonzero
, 0)));
6019 if (((op_code
== CLZ
&& CLZ_DEFINED_VALUE_AT_ZERO (mode
, op_val
))
6020 || (op_code
== CTZ
&& CTZ_DEFINED_VALUE_AT_ZERO (mode
, op_val
)))
6021 && op_val
== INTVAL (on_zero
))
6027 /* Try to simplify X given that it appears within operand OP of a
6028 VEC_MERGE operation whose mask is MASK. X need not use the same
6029 vector mode as the VEC_MERGE, but it must have the same number of
6032 Return the simplified X on success, otherwise return NULL_RTX. */
6035 simplify_merge_mask (rtx x
, rtx mask
, int op
)
6037 gcc_assert (VECTOR_MODE_P (GET_MODE (x
)));
6038 poly_uint64 nunits
= GET_MODE_NUNITS (GET_MODE (x
));
6039 if (GET_CODE (x
) == VEC_MERGE
&& rtx_equal_p (XEXP (x
, 2), mask
))
6041 if (side_effects_p (XEXP (x
, 1 - op
)))
6044 return XEXP (x
, op
);
6047 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
6048 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
))
6050 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
6052 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), top0
,
6053 GET_MODE (XEXP (x
, 0)));
6056 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
6057 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
)
6058 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 1)))
6059 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 1))), nunits
))
6061 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
6062 rtx top1
= simplify_merge_mask (XEXP (x
, 1), mask
, op
);
6065 if (COMPARISON_P (x
))
6066 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
6067 GET_MODE (XEXP (x
, 0)) != VOIDmode
6068 ? GET_MODE (XEXP (x
, 0))
6069 : GET_MODE (XEXP (x
, 1)),
6070 top0
? top0
: XEXP (x
, 0),
6071 top1
? top1
: XEXP (x
, 1));
6073 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
6074 top0
? top0
: XEXP (x
, 0),
6075 top1
? top1
: XEXP (x
, 1));
6078 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_TERNARY
6079 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
6080 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
)
6081 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 1)))
6082 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 1))), nunits
)
6083 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 2)))
6084 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 2))), nunits
))
6086 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
6087 rtx top1
= simplify_merge_mask (XEXP (x
, 1), mask
, op
);
6088 rtx top2
= simplify_merge_mask (XEXP (x
, 2), mask
, op
);
6089 if (top0
|| top1
|| top2
)
6090 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
6091 GET_MODE (XEXP (x
, 0)),
6092 top0
? top0
: XEXP (x
, 0),
6093 top1
? top1
: XEXP (x
, 1),
6094 top2
? top2
: XEXP (x
, 2));
6100 /* Simplify CODE, an operation with result mode MODE and three operands,
6101 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
6102 a constant. Return 0 if no simplifications is possible. */
6105 simplify_ternary_operation (enum rtx_code code
, machine_mode mode
,
6106 machine_mode op0_mode
, rtx op0
, rtx op1
,
6109 bool any_change
= false;
6111 scalar_int_mode int_mode
, int_op0_mode
;
6112 unsigned int n_elts
;
6117 /* Simplify negations around the multiplication. */
6118 /* -a * -b + c => a * b + c. */
6119 if (GET_CODE (op0
) == NEG
)
6121 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
6123 op1
= tem
, op0
= XEXP (op0
, 0), any_change
= true;
6125 else if (GET_CODE (op1
) == NEG
)
6127 tem
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
6129 op0
= tem
, op1
= XEXP (op1
, 0), any_change
= true;
6132 /* Canonicalize the two multiplication operands. */
6133 /* a * -b + c => -b * a + c. */
6134 if (swap_commutative_operands_p (op0
, op1
))
6135 std::swap (op0
, op1
), any_change
= true;
6138 return gen_rtx_FMA (mode
, op0
, op1
, op2
);
6143 if (CONST_INT_P (op0
)
6144 && CONST_INT_P (op1
)
6145 && CONST_INT_P (op2
)
6146 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6147 && INTVAL (op1
) + INTVAL (op2
) <= GET_MODE_PRECISION (int_mode
)
6148 && HWI_COMPUTABLE_MODE_P (int_mode
))
6150 /* Extracting a bit-field from a constant */
6151 unsigned HOST_WIDE_INT val
= UINTVAL (op0
);
6152 HOST_WIDE_INT op1val
= INTVAL (op1
);
6153 HOST_WIDE_INT op2val
= INTVAL (op2
);
6154 if (!BITS_BIG_ENDIAN
)
6156 else if (is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
))
6157 val
>>= GET_MODE_PRECISION (int_op0_mode
) - op2val
- op1val
;
6159 /* Not enough information to calculate the bit position. */
6162 if (HOST_BITS_PER_WIDE_INT
!= op1val
)
6164 /* First zero-extend. */
6165 val
&= (HOST_WIDE_INT_1U
<< op1val
) - 1;
6166 /* If desired, propagate sign bit. */
6167 if (code
== SIGN_EXTRACT
6168 && (val
& (HOST_WIDE_INT_1U
<< (op1val
- 1)))
6170 val
|= ~ ((HOST_WIDE_INT_1U
<< op1val
) - 1);
6173 return gen_int_mode (val
, int_mode
);
6178 if (CONST_INT_P (op0
))
6179 return op0
!= const0_rtx
? op1
: op2
;
6181 /* Convert c ? a : a into "a". */
6182 if (rtx_equal_p (op1
, op2
) && ! side_effects_p (op0
))
6185 /* Convert a != b ? a : b into "a". */
6186 if (GET_CODE (op0
) == NE
6187 && ! side_effects_p (op0
)
6188 && ! HONOR_NANS (mode
)
6189 && ! HONOR_SIGNED_ZEROS (mode
)
6190 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
6191 && rtx_equal_p (XEXP (op0
, 1), op2
))
6192 || (rtx_equal_p (XEXP (op0
, 0), op2
)
6193 && rtx_equal_p (XEXP (op0
, 1), op1
))))
6196 /* Convert a == b ? a : b into "b". */
6197 if (GET_CODE (op0
) == EQ
6198 && ! side_effects_p (op0
)
6199 && ! HONOR_NANS (mode
)
6200 && ! HONOR_SIGNED_ZEROS (mode
)
6201 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
6202 && rtx_equal_p (XEXP (op0
, 1), op2
))
6203 || (rtx_equal_p (XEXP (op0
, 0), op2
)
6204 && rtx_equal_p (XEXP (op0
, 1), op1
))))
6207 /* Convert (!c) != {0,...,0} ? a : b into
6208 c != {0,...,0} ? b : a for vector modes. */
6209 if (VECTOR_MODE_P (GET_MODE (op1
))
6210 && GET_CODE (op0
) == NE
6211 && GET_CODE (XEXP (op0
, 0)) == NOT
6212 && GET_CODE (XEXP (op0
, 1)) == CONST_VECTOR
)
6214 rtx cv
= XEXP (op0
, 1);
6217 if (!CONST_VECTOR_NUNITS (cv
).is_constant (&nunits
))
6220 for (int i
= 0; i
< nunits
; ++i
)
6221 if (CONST_VECTOR_ELT (cv
, i
) != const0_rtx
)
6228 rtx new_op0
= gen_rtx_NE (GET_MODE (op0
),
6229 XEXP (XEXP (op0
, 0), 0),
6231 rtx retval
= gen_rtx_IF_THEN_ELSE (mode
, new_op0
, op2
, op1
);
6236 /* Convert x == 0 ? N : clz (x) into clz (x) when
6237 CLZ_DEFINED_VALUE_AT_ZERO is defined to N for the mode of x.
6238 Similarly for ctz (x). */
6239 if (COMPARISON_P (op0
) && !side_effects_p (op0
)
6240 && XEXP (op0
, 1) == const0_rtx
)
6243 = simplify_cond_clz_ctz (XEXP (op0
, 0), GET_CODE (op0
),
6249 if (COMPARISON_P (op0
) && ! side_effects_p (op0
))
6251 machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
6252 ? GET_MODE (XEXP (op0
, 1))
6253 : GET_MODE (XEXP (op0
, 0)));
6256 /* Look for happy constants in op1 and op2. */
6257 if (CONST_INT_P (op1
) && CONST_INT_P (op2
))
6259 HOST_WIDE_INT t
= INTVAL (op1
);
6260 HOST_WIDE_INT f
= INTVAL (op2
);
6262 if (t
== STORE_FLAG_VALUE
&& f
== 0)
6263 code
= GET_CODE (op0
);
6264 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
6267 tmp
= reversed_comparison_code (op0
, NULL
);
6275 return simplify_gen_relational (code
, mode
, cmp_mode
,
6276 XEXP (op0
, 0), XEXP (op0
, 1));
6279 temp
= simplify_relational_operation (GET_CODE (op0
), op0_mode
,
6280 cmp_mode
, XEXP (op0
, 0),
6283 /* See if any simplifications were possible. */
6286 if (CONST_INT_P (temp
))
6287 return temp
== const0_rtx
? op2
: op1
;
6289 return gen_rtx_IF_THEN_ELSE (mode
, temp
, op1
, op2
);
6295 gcc_assert (GET_MODE (op0
) == mode
);
6296 gcc_assert (GET_MODE (op1
) == mode
);
6297 gcc_assert (VECTOR_MODE_P (mode
));
6298 trueop2
= avoid_constant_pool_reference (op2
);
6299 if (CONST_INT_P (trueop2
)
6300 && GET_MODE_NUNITS (mode
).is_constant (&n_elts
))
6302 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop2
);
6303 unsigned HOST_WIDE_INT mask
;
6304 if (n_elts
== HOST_BITS_PER_WIDE_INT
)
6307 mask
= (HOST_WIDE_INT_1U
<< n_elts
) - 1;
6309 if (!(sel
& mask
) && !side_effects_p (op0
))
6311 if ((sel
& mask
) == mask
&& !side_effects_p (op1
))
6314 rtx trueop0
= avoid_constant_pool_reference (op0
);
6315 rtx trueop1
= avoid_constant_pool_reference (op1
);
6316 if (GET_CODE (trueop0
) == CONST_VECTOR
6317 && GET_CODE (trueop1
) == CONST_VECTOR
)
6319 rtvec v
= rtvec_alloc (n_elts
);
6322 for (i
= 0; i
< n_elts
; i
++)
6323 RTVEC_ELT (v
, i
) = ((sel
& (HOST_WIDE_INT_1U
<< i
))
6324 ? CONST_VECTOR_ELT (trueop0
, i
)
6325 : CONST_VECTOR_ELT (trueop1
, i
));
6326 return gen_rtx_CONST_VECTOR (mode
, v
);
6329 /* Replace (vec_merge (vec_merge a b m) c n) with (vec_merge b c n)
6330 if no element from a appears in the result. */
6331 if (GET_CODE (op0
) == VEC_MERGE
)
6333 tem
= avoid_constant_pool_reference (XEXP (op0
, 2));
6334 if (CONST_INT_P (tem
))
6336 unsigned HOST_WIDE_INT sel0
= UINTVAL (tem
);
6337 if (!(sel
& sel0
& mask
) && !side_effects_p (XEXP (op0
, 0)))
6338 return simplify_gen_ternary (code
, mode
, mode
,
6339 XEXP (op0
, 1), op1
, op2
);
6340 if (!(sel
& ~sel0
& mask
) && !side_effects_p (XEXP (op0
, 1)))
6341 return simplify_gen_ternary (code
, mode
, mode
,
6342 XEXP (op0
, 0), op1
, op2
);
6345 if (GET_CODE (op1
) == VEC_MERGE
)
6347 tem
= avoid_constant_pool_reference (XEXP (op1
, 2));
6348 if (CONST_INT_P (tem
))
6350 unsigned HOST_WIDE_INT sel1
= UINTVAL (tem
);
6351 if (!(~sel
& sel1
& mask
) && !side_effects_p (XEXP (op1
, 0)))
6352 return simplify_gen_ternary (code
, mode
, mode
,
6353 op0
, XEXP (op1
, 1), op2
);
6354 if (!(~sel
& ~sel1
& mask
) && !side_effects_p (XEXP (op1
, 1)))
6355 return simplify_gen_ternary (code
, mode
, mode
,
6356 op0
, XEXP (op1
, 0), op2
);
6360 /* Replace (vec_merge (vec_duplicate (vec_select a parallel (i))) a 1 << i)
6362 if (GET_CODE (op0
) == VEC_DUPLICATE
6363 && GET_CODE (XEXP (op0
, 0)) == VEC_SELECT
6364 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == PARALLEL
6365 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (op0
, 0))), 1))
6367 tem
= XVECEXP ((XEXP (XEXP (op0
, 0), 1)), 0, 0);
6368 if (CONST_INT_P (tem
) && CONST_INT_P (op2
))
6370 if (XEXP (XEXP (op0
, 0), 0) == op1
6371 && UINTVAL (op2
) == HOST_WIDE_INT_1U
<< UINTVAL (tem
))
6375 /* Replace (vec_merge (vec_duplicate (X)) (const_vector [A, B])
6377 with (vec_concat (X) (B)) if N == 1 or
6378 (vec_concat (A) (X)) if N == 2. */
6379 if (GET_CODE (op0
) == VEC_DUPLICATE
6380 && GET_CODE (op1
) == CONST_VECTOR
6381 && known_eq (CONST_VECTOR_NUNITS (op1
), 2)
6382 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6383 && IN_RANGE (sel
, 1, 2))
6385 rtx newop0
= XEXP (op0
, 0);
6386 rtx newop1
= CONST_VECTOR_ELT (op1
, 2 - sel
);
6388 std::swap (newop0
, newop1
);
6389 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6391 /* Replace (vec_merge (vec_duplicate x) (vec_concat (y) (z)) (const_int N))
6392 with (vec_concat x z) if N == 1, or (vec_concat y x) if N == 2.
6393 Only applies for vectors of two elements. */
6394 if (GET_CODE (op0
) == VEC_DUPLICATE
6395 && GET_CODE (op1
) == VEC_CONCAT
6396 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6397 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6398 && IN_RANGE (sel
, 1, 2))
6400 rtx newop0
= XEXP (op0
, 0);
6401 rtx newop1
= XEXP (op1
, 2 - sel
);
6402 rtx otherop
= XEXP (op1
, sel
- 1);
6404 std::swap (newop0
, newop1
);
6405 /* Don't want to throw away the other part of the vec_concat if
6406 it has side-effects. */
6407 if (!side_effects_p (otherop
))
6408 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6413 (vec_merge:outer (vec_duplicate:outer x:inner)
6414 (subreg:outer y:inner 0)
6417 with (vec_concat:outer x:inner y:inner) if N == 1,
6418 or (vec_concat:outer y:inner x:inner) if N == 2.
6420 Implicitly, this means we have a paradoxical subreg, but such
6421 a check is cheap, so make it anyway.
6423 Only applies for vectors of two elements. */
6424 if (GET_CODE (op0
) == VEC_DUPLICATE
6425 && GET_CODE (op1
) == SUBREG
6426 && GET_MODE (op1
) == GET_MODE (op0
)
6427 && GET_MODE (SUBREG_REG (op1
)) == GET_MODE (XEXP (op0
, 0))
6428 && paradoxical_subreg_p (op1
)
6429 && subreg_lowpart_p (op1
)
6430 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6431 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6432 && IN_RANGE (sel
, 1, 2))
6434 rtx newop0
= XEXP (op0
, 0);
6435 rtx newop1
= SUBREG_REG (op1
);
6437 std::swap (newop0
, newop1
);
6438 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6441 /* Same as above but with switched operands:
6442 Replace (vec_merge:outer (subreg:outer x:inner 0)
6443 (vec_duplicate:outer y:inner)
6446 with (vec_concat:outer x:inner y:inner) if N == 1,
6447 or (vec_concat:outer y:inner x:inner) if N == 2. */
6448 if (GET_CODE (op1
) == VEC_DUPLICATE
6449 && GET_CODE (op0
) == SUBREG
6450 && GET_MODE (op0
) == GET_MODE (op1
)
6451 && GET_MODE (SUBREG_REG (op0
)) == GET_MODE (XEXP (op1
, 0))
6452 && paradoxical_subreg_p (op0
)
6453 && subreg_lowpart_p (op0
)
6454 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6455 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6456 && IN_RANGE (sel
, 1, 2))
6458 rtx newop0
= SUBREG_REG (op0
);
6459 rtx newop1
= XEXP (op1
, 0);
6461 std::swap (newop0
, newop1
);
6462 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6465 /* Replace (vec_merge (vec_duplicate x) (vec_duplicate y)
6467 with (vec_concat x y) or (vec_concat y x) depending on value
6469 if (GET_CODE (op0
) == VEC_DUPLICATE
6470 && GET_CODE (op1
) == VEC_DUPLICATE
6471 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6472 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6473 && IN_RANGE (sel
, 1, 2))
6475 rtx newop0
= XEXP (op0
, 0);
6476 rtx newop1
= XEXP (op1
, 0);
6478 std::swap (newop0
, newop1
);
6480 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6484 if (rtx_equal_p (op0
, op1
)
6485 && !side_effects_p (op2
) && !side_effects_p (op1
))
6488 if (!side_effects_p (op2
))
6491 = may_trap_p (op0
) ? NULL_RTX
: simplify_merge_mask (op0
, op2
, 0);
6493 = may_trap_p (op1
) ? NULL_RTX
: simplify_merge_mask (op1
, op2
, 1);
6495 return simplify_gen_ternary (code
, mode
, mode
,
6497 top1
? top1
: op1
, op2
);
6509 /* Try to calculate NUM_BYTES bytes of the target memory image of X,
6510 starting at byte FIRST_BYTE. Return true on success and add the
6511 bytes to BYTES, such that each byte has BITS_PER_UNIT bits and such
6512 that the bytes follow target memory order. Leave BYTES unmodified
6515 MODE is the mode of X. The caller must reserve NUM_BYTES bytes in
6516 BYTES before calling this function. */
6519 native_encode_rtx (machine_mode mode
, rtx x
, vec
<target_unit
> &bytes
,
6520 unsigned int first_byte
, unsigned int num_bytes
)
6522 /* Check the mode is sensible. */
6523 gcc_assert (GET_MODE (x
) == VOIDmode
6524 ? is_a
<scalar_int_mode
> (mode
)
6525 : mode
== GET_MODE (x
));
6527 if (GET_CODE (x
) == CONST_VECTOR
)
6529 /* CONST_VECTOR_ELT follows target memory order, so no shuffling
6530 is necessary. The only complication is that MODE_VECTOR_BOOL
6531 vectors can have several elements per byte. */
6532 unsigned int elt_bits
= vector_element_size (GET_MODE_BITSIZE (mode
),
6533 GET_MODE_NUNITS (mode
));
6534 unsigned int elt
= first_byte
* BITS_PER_UNIT
/ elt_bits
;
6535 if (elt_bits
< BITS_PER_UNIT
)
6537 /* This is the only case in which elements can be smaller than
6539 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_BOOL
);
6540 for (unsigned int i
= 0; i
< num_bytes
; ++i
)
6542 target_unit value
= 0;
6543 for (unsigned int j
= 0; j
< BITS_PER_UNIT
; j
+= elt_bits
)
6545 value
|= (INTVAL (CONST_VECTOR_ELT (x
, elt
)) & 1) << j
;
6548 bytes
.quick_push (value
);
6553 unsigned int start
= bytes
.length ();
6554 unsigned int elt_bytes
= GET_MODE_UNIT_SIZE (mode
);
6555 /* Make FIRST_BYTE relative to ELT. */
6556 first_byte
%= elt_bytes
;
6557 while (num_bytes
> 0)
6559 /* Work out how many bytes we want from element ELT. */
6560 unsigned int chunk_bytes
= MIN (num_bytes
, elt_bytes
- first_byte
);
6561 if (!native_encode_rtx (GET_MODE_INNER (mode
),
6562 CONST_VECTOR_ELT (x
, elt
), bytes
,
6563 first_byte
, chunk_bytes
))
6565 bytes
.truncate (start
);
6570 num_bytes
-= chunk_bytes
;
6575 /* All subsequent cases are limited to scalars. */
6577 if (!is_a
<scalar_mode
> (mode
, &smode
))
6580 /* Make sure that the region is in range. */
6581 unsigned int end_byte
= first_byte
+ num_bytes
;
6582 unsigned int mode_bytes
= GET_MODE_SIZE (smode
);
6583 gcc_assert (end_byte
<= mode_bytes
);
6585 if (CONST_SCALAR_INT_P (x
))
6587 /* The target memory layout is affected by both BYTES_BIG_ENDIAN
6588 and WORDS_BIG_ENDIAN. Use the subreg machinery to get the lsb
6589 position of each byte. */
6590 rtx_mode_t
value (x
, smode
);
6591 wide_int_ref
value_wi (value
);
6592 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
6594 /* Always constant because the inputs are. */
6596 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
6597 /* Operate directly on the encoding rather than using
6598 wi::extract_uhwi, so that we preserve the sign or zero
6599 extension for modes that are not a whole number of bits in
6600 size. (Zero extension is only used for the combination of
6601 innermode == BImode && STORE_FLAG_VALUE == 1). */
6602 unsigned int elt
= lsb
/ HOST_BITS_PER_WIDE_INT
;
6603 unsigned int shift
= lsb
% HOST_BITS_PER_WIDE_INT
;
6604 unsigned HOST_WIDE_INT uhwi
= value_wi
.elt (elt
);
6605 bytes
.quick_push (uhwi
>> shift
);
6610 if (CONST_DOUBLE_P (x
))
6612 /* real_to_target produces an array of integers in target memory order.
6613 All integers before the last one have 32 bits; the last one may
6614 have 32 bits or fewer, depending on whether the mode bitsize
6615 is divisible by 32. Each of these integers is then laid out
6616 in target memory as any other integer would be. */
6617 long el32
[MAX_BITSIZE_MODE_ANY_MODE
/ 32];
6618 real_to_target (el32
, CONST_DOUBLE_REAL_VALUE (x
), smode
);
6620 /* The (maximum) number of target bytes per element of el32. */
6621 unsigned int bytes_per_el32
= 32 / BITS_PER_UNIT
;
6622 gcc_assert (bytes_per_el32
!= 0);
6624 /* Build up the integers in a similar way to the CONST_SCALAR_INT_P
6626 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
6628 unsigned int index
= byte
/ bytes_per_el32
;
6629 unsigned int subbyte
= byte
% bytes_per_el32
;
6630 unsigned int int_bytes
= MIN (bytes_per_el32
,
6631 mode_bytes
- index
* bytes_per_el32
);
6632 /* Always constant because the inputs are. */
6634 = subreg_size_lsb (1, int_bytes
, subbyte
).to_constant ();
6635 bytes
.quick_push ((unsigned long) el32
[index
] >> lsb
);
6640 if (GET_CODE (x
) == CONST_FIXED
)
6642 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
6644 /* Always constant because the inputs are. */
6646 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
6647 unsigned HOST_WIDE_INT piece
= CONST_FIXED_VALUE_LOW (x
);
6648 if (lsb
>= HOST_BITS_PER_WIDE_INT
)
6650 lsb
-= HOST_BITS_PER_WIDE_INT
;
6651 piece
= CONST_FIXED_VALUE_HIGH (x
);
6653 bytes
.quick_push (piece
>> lsb
);
6661 /* Read a vector of mode MODE from the target memory image given by BYTES,
6662 starting at byte FIRST_BYTE. The vector is known to be encodable using
6663 NPATTERNS interleaved patterns with NELTS_PER_PATTERN elements each,
6664 and BYTES is known to have enough bytes to supply NPATTERNS *
6665 NELTS_PER_PATTERN vector elements. Each element of BYTES contains
6666 BITS_PER_UNIT bits and the bytes are in target memory order.
6668 Return the vector on success, otherwise return NULL_RTX. */
6671 native_decode_vector_rtx (machine_mode mode
, vec
<target_unit
> bytes
,
6672 unsigned int first_byte
, unsigned int npatterns
,
6673 unsigned int nelts_per_pattern
)
6675 rtx_vector_builder
builder (mode
, npatterns
, nelts_per_pattern
);
6677 unsigned int elt_bits
= vector_element_size (GET_MODE_BITSIZE (mode
),
6678 GET_MODE_NUNITS (mode
));
6679 if (elt_bits
< BITS_PER_UNIT
)
6681 /* This is the only case in which elements can be smaller than a byte.
6682 Element 0 is always in the lsb of the containing byte. */
6683 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_BOOL
);
6684 for (unsigned int i
= 0; i
< builder
.encoded_nelts (); ++i
)
6686 unsigned int bit_index
= first_byte
* BITS_PER_UNIT
+ i
* elt_bits
;
6687 unsigned int byte_index
= bit_index
/ BITS_PER_UNIT
;
6688 unsigned int lsb
= bit_index
% BITS_PER_UNIT
;
6689 builder
.quick_push (bytes
[byte_index
] & (1 << lsb
)
6690 ? CONST1_RTX (BImode
)
6691 : CONST0_RTX (BImode
));
6696 for (unsigned int i
= 0; i
< builder
.encoded_nelts (); ++i
)
6698 rtx x
= native_decode_rtx (GET_MODE_INNER (mode
), bytes
, first_byte
);
6701 builder
.quick_push (x
);
6702 first_byte
+= elt_bits
/ BITS_PER_UNIT
;
6705 return builder
.build ();
6708 /* Read an rtx of mode MODE from the target memory image given by BYTES,
6709 starting at byte FIRST_BYTE. Each element of BYTES contains BITS_PER_UNIT
6710 bits and the bytes are in target memory order. The image has enough
6711 values to specify all bytes of MODE.
6713 Return the rtx on success, otherwise return NULL_RTX. */
6716 native_decode_rtx (machine_mode mode
, vec
<target_unit
> bytes
,
6717 unsigned int first_byte
)
6719 if (VECTOR_MODE_P (mode
))
6721 /* If we know at compile time how many elements there are,
6722 pull each element directly from BYTES. */
6724 if (GET_MODE_NUNITS (mode
).is_constant (&nelts
))
6725 return native_decode_vector_rtx (mode
, bytes
, first_byte
, nelts
, 1);
6729 scalar_int_mode imode
;
6730 if (is_a
<scalar_int_mode
> (mode
, &imode
)
6731 && GET_MODE_PRECISION (imode
) <= MAX_BITSIZE_MODE_ANY_INT
)
6733 /* Pull the bytes msb first, so that we can use simple
6734 shift-and-insert wide_int operations. */
6735 unsigned int size
= GET_MODE_SIZE (imode
);
6736 wide_int
result (wi::zero (GET_MODE_PRECISION (imode
)));
6737 for (unsigned int i
= 0; i
< size
; ++i
)
6739 unsigned int lsb
= (size
- i
- 1) * BITS_PER_UNIT
;
6740 /* Always constant because the inputs are. */
6741 unsigned int subbyte
6742 = subreg_size_offset_from_lsb (1, size
, lsb
).to_constant ();
6743 result
<<= BITS_PER_UNIT
;
6744 result
|= bytes
[first_byte
+ subbyte
];
6746 return immed_wide_int_const (result
, imode
);
6749 scalar_float_mode fmode
;
6750 if (is_a
<scalar_float_mode
> (mode
, &fmode
))
6752 /* We need to build an array of integers in target memory order.
6753 All integers before the last one have 32 bits; the last one may
6754 have 32 bits or fewer, depending on whether the mode bitsize
6755 is divisible by 32. */
6756 long el32
[MAX_BITSIZE_MODE_ANY_MODE
/ 32];
6757 unsigned int num_el32
= CEIL (GET_MODE_BITSIZE (fmode
), 32);
6758 memset (el32
, 0, num_el32
* sizeof (long));
6760 /* The (maximum) number of target bytes per element of el32. */
6761 unsigned int bytes_per_el32
= 32 / BITS_PER_UNIT
;
6762 gcc_assert (bytes_per_el32
!= 0);
6764 unsigned int mode_bytes
= GET_MODE_SIZE (fmode
);
6765 for (unsigned int byte
= 0; byte
< mode_bytes
; ++byte
)
6767 unsigned int index
= byte
/ bytes_per_el32
;
6768 unsigned int subbyte
= byte
% bytes_per_el32
;
6769 unsigned int int_bytes
= MIN (bytes_per_el32
,
6770 mode_bytes
- index
* bytes_per_el32
);
6771 /* Always constant because the inputs are. */
6773 = subreg_size_lsb (1, int_bytes
, subbyte
).to_constant ();
6774 el32
[index
] |= (unsigned long) bytes
[first_byte
+ byte
] << lsb
;
6777 real_from_target (&r
, el32
, fmode
);
6778 return const_double_from_real_value (r
, fmode
);
6781 if (ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
6783 scalar_mode smode
= as_a
<scalar_mode
> (mode
);
6789 unsigned int mode_bytes
= GET_MODE_SIZE (smode
);
6790 for (unsigned int byte
= 0; byte
< mode_bytes
; ++byte
)
6792 /* Always constant because the inputs are. */
6794 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
6795 unsigned HOST_WIDE_INT unit
= bytes
[first_byte
+ byte
];
6796 if (lsb
>= HOST_BITS_PER_WIDE_INT
)
6797 f
.data
.high
|= unit
<< (lsb
- HOST_BITS_PER_WIDE_INT
);
6799 f
.data
.low
|= unit
<< lsb
;
6801 return CONST_FIXED_FROM_FIXED_VALUE (f
, mode
);
6807 /* Simplify a byte offset BYTE into CONST_VECTOR X. The main purpose
6808 is to convert a runtime BYTE value into a constant one. */
6811 simplify_const_vector_byte_offset (rtx x
, poly_uint64 byte
)
6813 /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */
6814 machine_mode mode
= GET_MODE (x
);
6815 unsigned int elt_bits
= vector_element_size (GET_MODE_BITSIZE (mode
),
6816 GET_MODE_NUNITS (mode
));
6817 /* The number of bits needed to encode one element from each pattern. */
6818 unsigned int sequence_bits
= CONST_VECTOR_NPATTERNS (x
) * elt_bits
;
6820 /* Identify the start point in terms of a sequence number and a byte offset
6821 within that sequence. */
6822 poly_uint64 first_sequence
;
6823 unsigned HOST_WIDE_INT subbit
;
6824 if (can_div_trunc_p (byte
* BITS_PER_UNIT
, sequence_bits
,
6825 &first_sequence
, &subbit
))
6827 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
6828 if (nelts_per_pattern
== 1)
6829 /* This is a duplicated vector, so the value of FIRST_SEQUENCE
6831 byte
= subbit
/ BITS_PER_UNIT
;
6832 else if (nelts_per_pattern
== 2 && known_gt (first_sequence
, 0U))
6834 /* The subreg drops the first element from each pattern and
6835 only uses the second element. Find the first sequence
6836 that starts on a byte boundary. */
6837 subbit
+= least_common_multiple (sequence_bits
, BITS_PER_UNIT
);
6838 byte
= subbit
/ BITS_PER_UNIT
;
6844 /* Subroutine of simplify_subreg in which:
6846 - X is known to be a CONST_VECTOR
6847 - OUTERMODE is known to be a vector mode
6849 Try to handle the subreg by operating on the CONST_VECTOR encoding
6850 rather than on each individual element of the CONST_VECTOR.
6852 Return the simplified subreg on success, otherwise return NULL_RTX. */
6855 simplify_const_vector_subreg (machine_mode outermode
, rtx x
,
6856 machine_mode innermode
, unsigned int first_byte
)
6858 /* Paradoxical subregs of vectors have dubious semantics. */
6859 if (paradoxical_subreg_p (outermode
, innermode
))
6862 /* We can only preserve the semantics of a stepped pattern if the new
6863 vector element is the same as the original one. */
6864 if (CONST_VECTOR_STEPPED_P (x
)
6865 && GET_MODE_INNER (outermode
) != GET_MODE_INNER (innermode
))
6868 /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */
6869 unsigned int x_elt_bits
6870 = vector_element_size (GET_MODE_BITSIZE (innermode
),
6871 GET_MODE_NUNITS (innermode
));
6872 unsigned int out_elt_bits
6873 = vector_element_size (GET_MODE_BITSIZE (outermode
),
6874 GET_MODE_NUNITS (outermode
));
6876 /* The number of bits needed to encode one element from every pattern
6877 of the original vector. */
6878 unsigned int x_sequence_bits
= CONST_VECTOR_NPATTERNS (x
) * x_elt_bits
;
6880 /* The number of bits needed to encode one element from every pattern
6882 unsigned int out_sequence_bits
6883 = least_common_multiple (x_sequence_bits
, out_elt_bits
);
6885 /* Work out the number of interleaved patterns in the output vector
6886 and the number of encoded elements per pattern. */
6887 unsigned int out_npatterns
= out_sequence_bits
/ out_elt_bits
;
6888 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
6890 /* The encoding scheme requires the number of elements to be a multiple
6891 of the number of patterns, so that each pattern appears at least once
6892 and so that the same number of elements appear from each pattern. */
6893 bool ok_p
= multiple_p (GET_MODE_NUNITS (outermode
), out_npatterns
);
6894 unsigned int const_nunits
;
6895 if (GET_MODE_NUNITS (outermode
).is_constant (&const_nunits
)
6896 && (!ok_p
|| out_npatterns
* nelts_per_pattern
> const_nunits
))
6898 /* Either the encoding is invalid, or applying it would give us
6899 more elements than we need. Just encode each element directly. */
6900 out_npatterns
= const_nunits
;
6901 nelts_per_pattern
= 1;
6906 /* Get enough bytes of X to form the new encoding. */
6907 unsigned int buffer_bits
= out_npatterns
* nelts_per_pattern
* out_elt_bits
;
6908 unsigned int buffer_bytes
= CEIL (buffer_bits
, BITS_PER_UNIT
);
6909 auto_vec
<target_unit
, 128> buffer (buffer_bytes
);
6910 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, buffer_bytes
))
6913 /* Reencode the bytes as OUTERMODE. */
6914 return native_decode_vector_rtx (outermode
, buffer
, 0, out_npatterns
,
6918 /* Try to simplify a subreg of a constant by encoding the subreg region
6919 as a sequence of target bytes and reading them back in the new mode.
6920 Return the new value on success, otherwise return null.
6922 The subreg has outer mode OUTERMODE, inner mode INNERMODE, inner value X
6923 and byte offset FIRST_BYTE. */
6926 simplify_immed_subreg (fixed_size_mode outermode
, rtx x
,
6927 machine_mode innermode
, unsigned int first_byte
)
6929 unsigned int buffer_bytes
= GET_MODE_SIZE (outermode
);
6930 auto_vec
<target_unit
, 128> buffer (buffer_bytes
);
6932 /* Some ports misuse CCmode. */
6933 if (GET_MODE_CLASS (outermode
) == MODE_CC
&& CONST_INT_P (x
))
6936 /* Paradoxical subregs read undefined values for bytes outside of the
6937 inner value. However, we have traditionally always sign-extended
6938 integer constants and zero-extended others. */
6939 unsigned int inner_bytes
= buffer_bytes
;
6940 if (paradoxical_subreg_p (outermode
, innermode
))
6942 if (!GET_MODE_SIZE (innermode
).is_constant (&inner_bytes
))
6945 target_unit filler
= 0;
6946 if (CONST_SCALAR_INT_P (x
) && wi::neg_p (rtx_mode_t (x
, innermode
)))
6949 /* Add any leading bytes due to big-endian layout. The number of
6950 bytes must be constant because both modes have constant size. */
6951 unsigned int leading_bytes
6952 = -byte_lowpart_offset (outermode
, innermode
).to_constant ();
6953 for (unsigned int i
= 0; i
< leading_bytes
; ++i
)
6954 buffer
.quick_push (filler
);
6956 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, inner_bytes
))
6959 /* Add any trailing bytes due to little-endian layout. */
6960 while (buffer
.length () < buffer_bytes
)
6961 buffer
.quick_push (filler
);
6965 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, inner_bytes
))
6968 return native_decode_rtx (outermode
, buffer
, 0);
6971 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
6972 Return 0 if no simplifications are possible. */
6974 simplify_subreg (machine_mode outermode
, rtx op
,
6975 machine_mode innermode
, poly_uint64 byte
)
6977 /* Little bit of sanity checking. */
6978 gcc_assert (innermode
!= VOIDmode
);
6979 gcc_assert (outermode
!= VOIDmode
);
6980 gcc_assert (innermode
!= BLKmode
);
6981 gcc_assert (outermode
!= BLKmode
);
6983 gcc_assert (GET_MODE (op
) == innermode
6984 || GET_MODE (op
) == VOIDmode
);
6986 poly_uint64 outersize
= GET_MODE_SIZE (outermode
);
6987 if (!multiple_p (byte
, outersize
))
6990 poly_uint64 innersize
= GET_MODE_SIZE (innermode
);
6991 if (maybe_ge (byte
, innersize
))
6994 if (outermode
== innermode
&& known_eq (byte
, 0U))
6997 if (GET_CODE (op
) == CONST_VECTOR
)
6998 byte
= simplify_const_vector_byte_offset (op
, byte
);
7000 if (multiple_p (byte
, GET_MODE_UNIT_SIZE (innermode
)))
7004 if (VECTOR_MODE_P (outermode
)
7005 && GET_MODE_INNER (outermode
) == GET_MODE_INNER (innermode
)
7006 && vec_duplicate_p (op
, &elt
))
7007 return gen_vec_duplicate (outermode
, elt
);
7009 if (outermode
== GET_MODE_INNER (innermode
)
7010 && vec_duplicate_p (op
, &elt
))
7014 if (CONST_SCALAR_INT_P (op
)
7015 || CONST_DOUBLE_AS_FLOAT_P (op
)
7016 || CONST_FIXED_P (op
)
7017 || GET_CODE (op
) == CONST_VECTOR
)
7019 unsigned HOST_WIDE_INT cbyte
;
7020 if (byte
.is_constant (&cbyte
))
7022 if (GET_CODE (op
) == CONST_VECTOR
&& VECTOR_MODE_P (outermode
))
7024 rtx tmp
= simplify_const_vector_subreg (outermode
, op
,
7030 fixed_size_mode fs_outermode
;
7031 if (is_a
<fixed_size_mode
> (outermode
, &fs_outermode
))
7032 return simplify_immed_subreg (fs_outermode
, op
, innermode
, cbyte
);
7036 /* Changing mode twice with SUBREG => just change it once,
7037 or not at all if changing back op starting mode. */
7038 if (GET_CODE (op
) == SUBREG
)
7040 machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
7041 poly_uint64 innermostsize
= GET_MODE_SIZE (innermostmode
);
7044 if (outermode
== innermostmode
7045 && known_eq (byte
, 0U)
7046 && known_eq (SUBREG_BYTE (op
), 0))
7047 return SUBREG_REG (op
);
7049 /* Work out the memory offset of the final OUTERMODE value relative
7050 to the inner value of OP. */
7051 poly_int64 mem_offset
= subreg_memory_offset (outermode
,
7053 poly_int64 op_mem_offset
= subreg_memory_offset (op
);
7054 poly_int64 final_offset
= mem_offset
+ op_mem_offset
;
7056 /* See whether resulting subreg will be paradoxical. */
7057 if (!paradoxical_subreg_p (outermode
, innermostmode
))
7059 /* Bail out in case resulting subreg would be incorrect. */
7060 if (maybe_lt (final_offset
, 0)
7061 || maybe_ge (poly_uint64 (final_offset
), innermostsize
)
7062 || !multiple_p (final_offset
, outersize
))
7067 poly_int64 required_offset
= subreg_memory_offset (outermode
,
7069 if (maybe_ne (final_offset
, required_offset
))
7071 /* Paradoxical subregs always have byte offset 0. */
7075 /* Recurse for further possible simplifications. */
7076 newx
= simplify_subreg (outermode
, SUBREG_REG (op
), innermostmode
,
7080 if (validate_subreg (outermode
, innermostmode
,
7081 SUBREG_REG (op
), final_offset
))
7083 newx
= gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
7084 if (SUBREG_PROMOTED_VAR_P (op
)
7085 && SUBREG_PROMOTED_SIGN (op
) >= 0
7086 && GET_MODE_CLASS (outermode
) == MODE_INT
7087 && known_ge (outersize
, innersize
)
7088 && known_le (outersize
, innermostsize
)
7089 && subreg_lowpart_p (newx
))
7091 SUBREG_PROMOTED_VAR_P (newx
) = 1;
7092 SUBREG_PROMOTED_SET (newx
, SUBREG_PROMOTED_GET (op
));
7099 /* SUBREG of a hard register => just change the register number
7100 and/or mode. If the hard register is not valid in that mode,
7101 suppress this simplification. If the hard register is the stack,
7102 frame, or argument pointer, leave this as a SUBREG. */
7104 if (REG_P (op
) && HARD_REGISTER_P (op
))
7106 unsigned int regno
, final_regno
;
7109 final_regno
= simplify_subreg_regno (regno
, innermode
, byte
, outermode
);
7110 if (HARD_REGISTER_NUM_P (final_regno
))
7112 rtx x
= gen_rtx_REG_offset (op
, outermode
, final_regno
,
7113 subreg_memory_offset (outermode
,
7116 /* Propagate original regno. We don't have any way to specify
7117 the offset inside original regno, so do so only for lowpart.
7118 The information is used only by alias analysis that cannot
7119 grog partial register anyway. */
7121 if (known_eq (subreg_lowpart_offset (outermode
, innermode
), byte
))
7122 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
7127 /* If we have a SUBREG of a register that we are replacing and we are
7128 replacing it with a MEM, make a new MEM and try replacing the
7129 SUBREG with it. Don't do this if the MEM has a mode-dependent address
7130 or if we would be widening it. */
7133 && ! mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
))
7134 /* Allow splitting of volatile memory references in case we don't
7135 have instruction to move the whole thing. */
7136 && (! MEM_VOLATILE_P (op
)
7137 || ! have_insn_for (SET
, innermode
))
7138 && known_le (outersize
, innersize
))
7139 return adjust_address_nv (op
, outermode
, byte
);
7141 /* Handle complex or vector values represented as CONCAT or VEC_CONCAT
7143 if (GET_CODE (op
) == CONCAT
7144 || GET_CODE (op
) == VEC_CONCAT
)
7146 poly_uint64 final_offset
;
7149 machine_mode part_mode
= GET_MODE (XEXP (op
, 0));
7150 if (part_mode
== VOIDmode
)
7151 part_mode
= GET_MODE_INNER (GET_MODE (op
));
7152 poly_uint64 part_size
= GET_MODE_SIZE (part_mode
);
7153 if (known_lt (byte
, part_size
))
7155 part
= XEXP (op
, 0);
7156 final_offset
= byte
;
7158 else if (known_ge (byte
, part_size
))
7160 part
= XEXP (op
, 1);
7161 final_offset
= byte
- part_size
;
7166 if (maybe_gt (final_offset
+ outersize
, part_size
))
7169 part_mode
= GET_MODE (part
);
7170 if (part_mode
== VOIDmode
)
7171 part_mode
= GET_MODE_INNER (GET_MODE (op
));
7172 res
= simplify_subreg (outermode
, part
, part_mode
, final_offset
);
7175 if (validate_subreg (outermode
, part_mode
, part
, final_offset
))
7176 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
7181 (subreg (vec_merge (X)
7183 (const_int ((1 << N) | M)))
7184 (N * sizeof (outermode)))
7186 (subreg (X) (N * sizeof (outermode)))
7189 if (constant_multiple_p (byte
, GET_MODE_SIZE (outermode
), &idx
)
7190 && idx
< HOST_BITS_PER_WIDE_INT
7191 && GET_CODE (op
) == VEC_MERGE
7192 && GET_MODE_INNER (innermode
) == outermode
7193 && CONST_INT_P (XEXP (op
, 2))
7194 && (UINTVAL (XEXP (op
, 2)) & (HOST_WIDE_INT_1U
<< idx
)) != 0)
7195 return simplify_gen_subreg (outermode
, XEXP (op
, 0), innermode
, byte
);
7197 /* A SUBREG resulting from a zero extension may fold to zero if
7198 it extracts higher bits that the ZERO_EXTEND's source bits. */
7199 if (GET_CODE (op
) == ZERO_EXTEND
&& SCALAR_INT_MODE_P (innermode
))
7201 poly_uint64 bitpos
= subreg_lsb_1 (outermode
, innermode
, byte
);
7202 if (known_ge (bitpos
, GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0)))))
7203 return CONST0_RTX (outermode
);
7206 scalar_int_mode int_outermode
, int_innermode
;
7207 if (is_a
<scalar_int_mode
> (outermode
, &int_outermode
)
7208 && is_a
<scalar_int_mode
> (innermode
, &int_innermode
)
7209 && known_eq (byte
, subreg_lowpart_offset (int_outermode
, int_innermode
)))
7211 /* Handle polynomial integers. The upper bits of a paradoxical
7212 subreg are undefined, so this is safe regardless of whether
7213 we're truncating or extending. */
7214 if (CONST_POLY_INT_P (op
))
7217 = poly_wide_int::from (const_poly_int_value (op
),
7218 GET_MODE_PRECISION (int_outermode
),
7220 return immed_wide_int_const (val
, int_outermode
);
7223 if (GET_MODE_PRECISION (int_outermode
)
7224 < GET_MODE_PRECISION (int_innermode
))
7226 rtx tem
= simplify_truncation (int_outermode
, op
, int_innermode
);
7232 /* If OP is a vector comparison and the subreg is not changing the
7233 number of elements or the size of the elements, change the result
7234 of the comparison to the new mode. */
7235 if (COMPARISON_P (op
)
7236 && VECTOR_MODE_P (outermode
)
7237 && VECTOR_MODE_P (innermode
)
7238 && known_eq (GET_MODE_NUNITS (outermode
), GET_MODE_NUNITS (innermode
))
7239 && known_eq (GET_MODE_UNIT_SIZE (outermode
),
7240 GET_MODE_UNIT_SIZE (innermode
)))
7241 return simplify_gen_relational (GET_CODE (op
), outermode
, innermode
,
7242 XEXP (op
, 0), XEXP (op
, 1));
7246 /* Make a SUBREG operation or equivalent if it folds. */
7249 simplify_gen_subreg (machine_mode outermode
, rtx op
,
7250 machine_mode innermode
, poly_uint64 byte
)
7254 newx
= simplify_subreg (outermode
, op
, innermode
, byte
);
7258 if (GET_CODE (op
) == SUBREG
7259 || GET_CODE (op
) == CONCAT
7260 || GET_MODE (op
) == VOIDmode
)
7263 if (validate_subreg (outermode
, innermode
, op
, byte
))
7264 return gen_rtx_SUBREG (outermode
, op
, byte
);
7269 /* Generates a subreg to get the least significant part of EXPR (in mode
7270 INNER_MODE) to OUTER_MODE. */
7273 lowpart_subreg (machine_mode outer_mode
, rtx expr
,
7274 machine_mode inner_mode
)
7276 return simplify_gen_subreg (outer_mode
, expr
, inner_mode
,
7277 subreg_lowpart_offset (outer_mode
, inner_mode
));
7280 /* Simplify X, an rtx expression.
7282 Return the simplified expression or NULL if no simplifications
7285 This is the preferred entry point into the simplification routines;
7286 however, we still allow passes to call the more specific routines.
7288 Right now GCC has three (yes, three) major bodies of RTL simplification
7289 code that need to be unified.
7291 1. fold_rtx in cse.c. This code uses various CSE specific
7292 information to aid in RTL simplification.
7294 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
7295 it uses combine specific information to aid in RTL
7298 3. The routines in this file.
7301 Long term we want to only have one body of simplification code; to
7302 get to that state I recommend the following steps:
7304 1. Pour over fold_rtx & simplify_rtx and move any simplifications
7305 which are not pass dependent state into these routines.
7307 2. As code is moved by #1, change fold_rtx & simplify_rtx to
7308 use this routine whenever possible.
7310 3. Allow for pass dependent state to be provided to these
7311 routines and add simplifications based on the pass dependent
7312 state. Remove code from cse.c & combine.c that becomes
7315 It will take time, but ultimately the compiler will be easier to
7316 maintain and improve. It's totally silly that when we add a
7317 simplification that it needs to be added to 4 places (3 for RTL
7318 simplification and 1 for tree simplification. */
7321 simplify_rtx (const_rtx x
)
7323 const enum rtx_code code
= GET_CODE (x
);
7324 const machine_mode mode
= GET_MODE (x
);
7326 switch (GET_RTX_CLASS (code
))
7329 return simplify_unary_operation (code
, mode
,
7330 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
7331 case RTX_COMM_ARITH
:
7332 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7333 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
7338 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
7341 case RTX_BITFIELD_OPS
:
7342 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
7343 XEXP (x
, 0), XEXP (x
, 1),
7347 case RTX_COMM_COMPARE
:
7348 return simplify_relational_operation (code
, mode
,
7349 ((GET_MODE (XEXP (x
, 0))
7351 ? GET_MODE (XEXP (x
, 0))
7352 : GET_MODE (XEXP (x
, 1))),
7358 return simplify_subreg (mode
, SUBREG_REG (x
),
7359 GET_MODE (SUBREG_REG (x
)),
7366 /* Convert (lo_sum (high FOO) FOO) to FOO. */
7367 if (GET_CODE (XEXP (x
, 0)) == HIGH
7368 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
7381 namespace selftest
{
7383 /* Make a unique pseudo REG of mode MODE for use by selftests. */
7386 make_test_reg (machine_mode mode
)
7388 static int test_reg_num
= LAST_VIRTUAL_REGISTER
+ 1;
7390 return gen_rtx_REG (mode
, test_reg_num
++);
7394 test_scalar_int_ops (machine_mode mode
)
7396 rtx op0
= make_test_reg (mode
);
7397 rtx op1
= make_test_reg (mode
);
7398 rtx six
= GEN_INT (6);
7400 rtx neg_op0
= simplify_gen_unary (NEG
, mode
, op0
, mode
);
7401 rtx not_op0
= simplify_gen_unary (NOT
, mode
, op0
, mode
);
7402 rtx bswap_op0
= simplify_gen_unary (BSWAP
, mode
, op0
, mode
);
7404 rtx and_op0_op1
= simplify_gen_binary (AND
, mode
, op0
, op1
);
7405 rtx ior_op0_op1
= simplify_gen_binary (IOR
, mode
, op0
, op1
);
7406 rtx xor_op0_op1
= simplify_gen_binary (XOR
, mode
, op0
, op1
);
7408 rtx and_op0_6
= simplify_gen_binary (AND
, mode
, op0
, six
);
7409 rtx and_op1_6
= simplify_gen_binary (AND
, mode
, op1
, six
);
7411 /* Test some binary identities. */
7412 ASSERT_RTX_EQ (op0
, simplify_gen_binary (PLUS
, mode
, op0
, const0_rtx
));
7413 ASSERT_RTX_EQ (op0
, simplify_gen_binary (PLUS
, mode
, const0_rtx
, op0
));
7414 ASSERT_RTX_EQ (op0
, simplify_gen_binary (MINUS
, mode
, op0
, const0_rtx
));
7415 ASSERT_RTX_EQ (op0
, simplify_gen_binary (MULT
, mode
, op0
, const1_rtx
));
7416 ASSERT_RTX_EQ (op0
, simplify_gen_binary (MULT
, mode
, const1_rtx
, op0
));
7417 ASSERT_RTX_EQ (op0
, simplify_gen_binary (DIV
, mode
, op0
, const1_rtx
));
7418 ASSERT_RTX_EQ (op0
, simplify_gen_binary (AND
, mode
, op0
, constm1_rtx
));
7419 ASSERT_RTX_EQ (op0
, simplify_gen_binary (AND
, mode
, constm1_rtx
, op0
));
7420 ASSERT_RTX_EQ (op0
, simplify_gen_binary (IOR
, mode
, op0
, const0_rtx
));
7421 ASSERT_RTX_EQ (op0
, simplify_gen_binary (IOR
, mode
, const0_rtx
, op0
));
7422 ASSERT_RTX_EQ (op0
, simplify_gen_binary (XOR
, mode
, op0
, const0_rtx
));
7423 ASSERT_RTX_EQ (op0
, simplify_gen_binary (XOR
, mode
, const0_rtx
, op0
));
7424 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ASHIFT
, mode
, op0
, const0_rtx
));
7425 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ROTATE
, mode
, op0
, const0_rtx
));
7426 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ASHIFTRT
, mode
, op0
, const0_rtx
));
7427 ASSERT_RTX_EQ (op0
, simplify_gen_binary (LSHIFTRT
, mode
, op0
, const0_rtx
));
7428 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ROTATERT
, mode
, op0
, const0_rtx
));
7430 /* Test some self-inverse operations. */
7431 ASSERT_RTX_EQ (op0
, simplify_gen_unary (NEG
, mode
, neg_op0
, mode
));
7432 ASSERT_RTX_EQ (op0
, simplify_gen_unary (NOT
, mode
, not_op0
, mode
));
7433 ASSERT_RTX_EQ (op0
, simplify_gen_unary (BSWAP
, mode
, bswap_op0
, mode
));
7435 /* Test some reflexive operations. */
7436 ASSERT_RTX_EQ (op0
, simplify_gen_binary (AND
, mode
, op0
, op0
));
7437 ASSERT_RTX_EQ (op0
, simplify_gen_binary (IOR
, mode
, op0
, op0
));
7438 ASSERT_RTX_EQ (op0
, simplify_gen_binary (SMIN
, mode
, op0
, op0
));
7439 ASSERT_RTX_EQ (op0
, simplify_gen_binary (SMAX
, mode
, op0
, op0
));
7440 ASSERT_RTX_EQ (op0
, simplify_gen_binary (UMIN
, mode
, op0
, op0
));
7441 ASSERT_RTX_EQ (op0
, simplify_gen_binary (UMAX
, mode
, op0
, op0
));
7443 ASSERT_RTX_EQ (const0_rtx
, simplify_gen_binary (MINUS
, mode
, op0
, op0
));
7444 ASSERT_RTX_EQ (const0_rtx
, simplify_gen_binary (XOR
, mode
, op0
, op0
));
7446 /* Test simplify_distributive_operation. */
7447 ASSERT_RTX_EQ (simplify_gen_binary (AND
, mode
, xor_op0_op1
, six
),
7448 simplify_gen_binary (XOR
, mode
, and_op0_6
, and_op1_6
));
7449 ASSERT_RTX_EQ (simplify_gen_binary (AND
, mode
, ior_op0_op1
, six
),
7450 simplify_gen_binary (IOR
, mode
, and_op0_6
, and_op1_6
));
7451 ASSERT_RTX_EQ (simplify_gen_binary (AND
, mode
, and_op0_op1
, six
),
7452 simplify_gen_binary (AND
, mode
, and_op0_6
, and_op1_6
));
7455 /* Verify some simplifications involving scalar expressions. */
7460 for (unsigned int i
= 0; i
< NUM_MACHINE_MODES
; ++i
)
7462 machine_mode mode
= (machine_mode
) i
;
7463 if (SCALAR_INT_MODE_P (mode
) && mode
!= BImode
)
7464 test_scalar_int_ops (mode
);
7468 /* Test vector simplifications involving VEC_DUPLICATE in which the
7469 operands and result have vector mode MODE. SCALAR_REG is a pseudo
7470 register that holds one element of MODE. */
7473 test_vector_ops_duplicate (machine_mode mode
, rtx scalar_reg
)
7475 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
7476 rtx duplicate
= gen_rtx_VEC_DUPLICATE (mode
, scalar_reg
);
7477 poly_uint64 nunits
= GET_MODE_NUNITS (mode
);
7478 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
7480 /* Test some simple unary cases with VEC_DUPLICATE arguments. */
7481 rtx not_scalar_reg
= gen_rtx_NOT (inner_mode
, scalar_reg
);
7482 rtx duplicate_not
= gen_rtx_VEC_DUPLICATE (mode
, not_scalar_reg
);
7483 ASSERT_RTX_EQ (duplicate
,
7484 simplify_unary_operation (NOT
, mode
,
7485 duplicate_not
, mode
));
7487 rtx neg_scalar_reg
= gen_rtx_NEG (inner_mode
, scalar_reg
);
7488 rtx duplicate_neg
= gen_rtx_VEC_DUPLICATE (mode
, neg_scalar_reg
);
7489 ASSERT_RTX_EQ (duplicate
,
7490 simplify_unary_operation (NEG
, mode
,
7491 duplicate_neg
, mode
));
7493 /* Test some simple binary cases with VEC_DUPLICATE arguments. */
7494 ASSERT_RTX_EQ (duplicate
,
7495 simplify_binary_operation (PLUS
, mode
, duplicate
,
7496 CONST0_RTX (mode
)));
7498 ASSERT_RTX_EQ (duplicate
,
7499 simplify_binary_operation (MINUS
, mode
, duplicate
,
7500 CONST0_RTX (mode
)));
7502 ASSERT_RTX_PTR_EQ (CONST0_RTX (mode
),
7503 simplify_binary_operation (MINUS
, mode
, duplicate
,
7507 /* Test a scalar VEC_SELECT of a VEC_DUPLICATE. */
7508 rtx zero_par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, const0_rtx
));
7509 ASSERT_RTX_PTR_EQ (scalar_reg
,
7510 simplify_binary_operation (VEC_SELECT
, inner_mode
,
7511 duplicate
, zero_par
));
7513 unsigned HOST_WIDE_INT const_nunits
;
7514 if (nunits
.is_constant (&const_nunits
))
7516 /* And again with the final element. */
7517 rtx last_index
= gen_int_mode (const_nunits
- 1, word_mode
);
7518 rtx last_par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, last_index
));
7519 ASSERT_RTX_PTR_EQ (scalar_reg
,
7520 simplify_binary_operation (VEC_SELECT
, inner_mode
,
7521 duplicate
, last_par
));
7523 /* Test a scalar subreg of a VEC_MERGE of a VEC_DUPLICATE. */
7524 rtx vector_reg
= make_test_reg (mode
);
7525 for (unsigned HOST_WIDE_INT i
= 0; i
< const_nunits
; i
++)
7527 if (i
>= HOST_BITS_PER_WIDE_INT
)
7529 rtx mask
= GEN_INT ((HOST_WIDE_INT_1U
<< i
) | (i
+ 1));
7530 rtx vm
= gen_rtx_VEC_MERGE (mode
, duplicate
, vector_reg
, mask
);
7531 poly_uint64 offset
= i
* GET_MODE_SIZE (inner_mode
);
7532 ASSERT_RTX_EQ (scalar_reg
,
7533 simplify_gen_subreg (inner_mode
, vm
,
7538 /* Test a scalar subreg of a VEC_DUPLICATE. */
7539 poly_uint64 offset
= subreg_lowpart_offset (inner_mode
, mode
);
7540 ASSERT_RTX_EQ (scalar_reg
,
7541 simplify_gen_subreg (inner_mode
, duplicate
,
7544 machine_mode narrower_mode
;
7545 if (maybe_ne (nunits
, 2U)
7546 && multiple_p (nunits
, 2)
7547 && mode_for_vector (inner_mode
, 2).exists (&narrower_mode
)
7548 && VECTOR_MODE_P (narrower_mode
))
7550 /* Test VEC_DUPLICATE of a vector. */
7551 rtx_vector_builder
nbuilder (narrower_mode
, 2, 1);
7552 nbuilder
.quick_push (const0_rtx
);
7553 nbuilder
.quick_push (const1_rtx
);
7554 rtx_vector_builder
builder (mode
, 2, 1);
7555 builder
.quick_push (const0_rtx
);
7556 builder
.quick_push (const1_rtx
);
7557 ASSERT_RTX_EQ (builder
.build (),
7558 simplify_unary_operation (VEC_DUPLICATE
, mode
,
7562 /* Test VEC_SELECT of a vector. */
7564 = gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, const1_rtx
, const0_rtx
));
7565 rtx narrower_duplicate
7566 = gen_rtx_VEC_DUPLICATE (narrower_mode
, scalar_reg
);
7567 ASSERT_RTX_EQ (narrower_duplicate
,
7568 simplify_binary_operation (VEC_SELECT
, narrower_mode
,
7569 duplicate
, vec_par
));
7571 /* Test a vector subreg of a VEC_DUPLICATE. */
7572 poly_uint64 offset
= subreg_lowpart_offset (narrower_mode
, mode
);
7573 ASSERT_RTX_EQ (narrower_duplicate
,
7574 simplify_gen_subreg (narrower_mode
, duplicate
,
7579 /* Test vector simplifications involving VEC_SERIES in which the
7580 operands and result have vector mode MODE. SCALAR_REG is a pseudo
7581 register that holds one element of MODE. */
7584 test_vector_ops_series (machine_mode mode
, rtx scalar_reg
)
7586 /* Test unary cases with VEC_SERIES arguments. */
7587 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
7588 rtx duplicate
= gen_rtx_VEC_DUPLICATE (mode
, scalar_reg
);
7589 rtx neg_scalar_reg
= gen_rtx_NEG (inner_mode
, scalar_reg
);
7590 rtx series_0_r
= gen_rtx_VEC_SERIES (mode
, const0_rtx
, scalar_reg
);
7591 rtx series_0_nr
= gen_rtx_VEC_SERIES (mode
, const0_rtx
, neg_scalar_reg
);
7592 rtx series_nr_1
= gen_rtx_VEC_SERIES (mode
, neg_scalar_reg
, const1_rtx
);
7593 rtx series_r_m1
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, constm1_rtx
);
7594 rtx series_r_r
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, scalar_reg
);
7595 rtx series_nr_nr
= gen_rtx_VEC_SERIES (mode
, neg_scalar_reg
,
7597 ASSERT_RTX_EQ (series_0_r
,
7598 simplify_unary_operation (NEG
, mode
, series_0_nr
, mode
));
7599 ASSERT_RTX_EQ (series_r_m1
,
7600 simplify_unary_operation (NEG
, mode
, series_nr_1
, mode
));
7601 ASSERT_RTX_EQ (series_r_r
,
7602 simplify_unary_operation (NEG
, mode
, series_nr_nr
, mode
));
7604 /* Test that a VEC_SERIES with a zero step is simplified away. */
7605 ASSERT_RTX_EQ (duplicate
,
7606 simplify_binary_operation (VEC_SERIES
, mode
,
7607 scalar_reg
, const0_rtx
));
7609 /* Test PLUS and MINUS with VEC_SERIES. */
7610 rtx series_0_1
= gen_const_vec_series (mode
, const0_rtx
, const1_rtx
);
7611 rtx series_0_m1
= gen_const_vec_series (mode
, const0_rtx
, constm1_rtx
);
7612 rtx series_r_1
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, const1_rtx
);
7613 ASSERT_RTX_EQ (series_r_r
,
7614 simplify_binary_operation (PLUS
, mode
, series_0_r
,
7616 ASSERT_RTX_EQ (series_r_1
,
7617 simplify_binary_operation (PLUS
, mode
, duplicate
,
7619 ASSERT_RTX_EQ (series_r_m1
,
7620 simplify_binary_operation (PLUS
, mode
, duplicate
,
7622 ASSERT_RTX_EQ (series_0_r
,
7623 simplify_binary_operation (MINUS
, mode
, series_r_r
,
7625 ASSERT_RTX_EQ (series_r_m1
,
7626 simplify_binary_operation (MINUS
, mode
, duplicate
,
7628 ASSERT_RTX_EQ (series_r_1
,
7629 simplify_binary_operation (MINUS
, mode
, duplicate
,
7631 ASSERT_RTX_EQ (series_0_m1
,
7632 simplify_binary_operation (VEC_SERIES
, mode
, const0_rtx
,
7635 /* Test NEG on constant vector series. */
7636 ASSERT_RTX_EQ (series_0_m1
,
7637 simplify_unary_operation (NEG
, mode
, series_0_1
, mode
));
7638 ASSERT_RTX_EQ (series_0_1
,
7639 simplify_unary_operation (NEG
, mode
, series_0_m1
, mode
));
7641 /* Test PLUS and MINUS on constant vector series. */
7642 rtx scalar2
= gen_int_mode (2, inner_mode
);
7643 rtx scalar3
= gen_int_mode (3, inner_mode
);
7644 rtx series_1_1
= gen_const_vec_series (mode
, const1_rtx
, const1_rtx
);
7645 rtx series_0_2
= gen_const_vec_series (mode
, const0_rtx
, scalar2
);
7646 rtx series_1_3
= gen_const_vec_series (mode
, const1_rtx
, scalar3
);
7647 ASSERT_RTX_EQ (series_1_1
,
7648 simplify_binary_operation (PLUS
, mode
, series_0_1
,
7649 CONST1_RTX (mode
)));
7650 ASSERT_RTX_EQ (series_0_m1
,
7651 simplify_binary_operation (PLUS
, mode
, CONST0_RTX (mode
),
7653 ASSERT_RTX_EQ (series_1_3
,
7654 simplify_binary_operation (PLUS
, mode
, series_1_1
,
7656 ASSERT_RTX_EQ (series_0_1
,
7657 simplify_binary_operation (MINUS
, mode
, series_1_1
,
7658 CONST1_RTX (mode
)));
7659 ASSERT_RTX_EQ (series_1_1
,
7660 simplify_binary_operation (MINUS
, mode
, CONST1_RTX (mode
),
7662 ASSERT_RTX_EQ (series_1_1
,
7663 simplify_binary_operation (MINUS
, mode
, series_1_3
,
7666 /* Test MULT between constant vectors. */
7667 rtx vec2
= gen_const_vec_duplicate (mode
, scalar2
);
7668 rtx vec3
= gen_const_vec_duplicate (mode
, scalar3
);
7669 rtx scalar9
= gen_int_mode (9, inner_mode
);
7670 rtx series_3_9
= gen_const_vec_series (mode
, scalar3
, scalar9
);
7671 ASSERT_RTX_EQ (series_0_2
,
7672 simplify_binary_operation (MULT
, mode
, series_0_1
, vec2
));
7673 ASSERT_RTX_EQ (series_3_9
,
7674 simplify_binary_operation (MULT
, mode
, vec3
, series_1_3
));
7675 if (!GET_MODE_NUNITS (mode
).is_constant ())
7676 ASSERT_FALSE (simplify_binary_operation (MULT
, mode
, series_0_1
,
7679 /* Test ASHIFT between constant vectors. */
7680 ASSERT_RTX_EQ (series_0_2
,
7681 simplify_binary_operation (ASHIFT
, mode
, series_0_1
,
7682 CONST1_RTX (mode
)));
7683 if (!GET_MODE_NUNITS (mode
).is_constant ())
7684 ASSERT_FALSE (simplify_binary_operation (ASHIFT
, mode
, CONST1_RTX (mode
),
7688 /* Verify simplify_merge_mask works correctly. */
7691 test_vec_merge (machine_mode mode
)
7693 rtx op0
= make_test_reg (mode
);
7694 rtx op1
= make_test_reg (mode
);
7695 rtx op2
= make_test_reg (mode
);
7696 rtx op3
= make_test_reg (mode
);
7697 rtx op4
= make_test_reg (mode
);
7698 rtx op5
= make_test_reg (mode
);
7699 rtx mask1
= make_test_reg (SImode
);
7700 rtx mask2
= make_test_reg (SImode
);
7701 rtx vm1
= gen_rtx_VEC_MERGE (mode
, op0
, op1
, mask1
);
7702 rtx vm2
= gen_rtx_VEC_MERGE (mode
, op2
, op3
, mask1
);
7703 rtx vm3
= gen_rtx_VEC_MERGE (mode
, op4
, op5
, mask1
);
7705 /* Simple vec_merge. */
7706 ASSERT_EQ (op0
, simplify_merge_mask (vm1
, mask1
, 0));
7707 ASSERT_EQ (op1
, simplify_merge_mask (vm1
, mask1
, 1));
7708 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (vm1
, mask2
, 0));
7709 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (vm1
, mask2
, 1));
7711 /* Nested vec_merge.
7712 It's tempting to make this simplify right down to opN, but we don't
7713 because all the simplify_* functions assume that the operands have
7714 already been simplified. */
7715 rtx nvm
= gen_rtx_VEC_MERGE (mode
, vm1
, vm2
, mask1
);
7716 ASSERT_EQ (vm1
, simplify_merge_mask (nvm
, mask1
, 0));
7717 ASSERT_EQ (vm2
, simplify_merge_mask (nvm
, mask1
, 1));
7719 /* Intermediate unary op. */
7720 rtx unop
= gen_rtx_NOT (mode
, vm1
);
7721 ASSERT_RTX_EQ (gen_rtx_NOT (mode
, op0
),
7722 simplify_merge_mask (unop
, mask1
, 0));
7723 ASSERT_RTX_EQ (gen_rtx_NOT (mode
, op1
),
7724 simplify_merge_mask (unop
, mask1
, 1));
7726 /* Intermediate binary op. */
7727 rtx binop
= gen_rtx_PLUS (mode
, vm1
, vm2
);
7728 ASSERT_RTX_EQ (gen_rtx_PLUS (mode
, op0
, op2
),
7729 simplify_merge_mask (binop
, mask1
, 0));
7730 ASSERT_RTX_EQ (gen_rtx_PLUS (mode
, op1
, op3
),
7731 simplify_merge_mask (binop
, mask1
, 1));
7733 /* Intermediate ternary op. */
7734 rtx tenop
= gen_rtx_FMA (mode
, vm1
, vm2
, vm3
);
7735 ASSERT_RTX_EQ (gen_rtx_FMA (mode
, op0
, op2
, op4
),
7736 simplify_merge_mask (tenop
, mask1
, 0));
7737 ASSERT_RTX_EQ (gen_rtx_FMA (mode
, op1
, op3
, op5
),
7738 simplify_merge_mask (tenop
, mask1
, 1));
7741 rtx badop0
= gen_rtx_PRE_INC (mode
, op0
);
7742 rtx badvm
= gen_rtx_VEC_MERGE (mode
, badop0
, op1
, mask1
);
7743 ASSERT_EQ (badop0
, simplify_merge_mask (badvm
, mask1
, 0));
7744 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (badvm
, mask1
, 1));
7746 /* Called indirectly. */
7747 ASSERT_RTX_EQ (gen_rtx_VEC_MERGE (mode
, op0
, op3
, mask1
),
7748 simplify_rtx (nvm
));
7751 /* Test subregs of integer vector constant X, trying elements in
7752 the range [ELT_BIAS, ELT_BIAS + constant_lower_bound (NELTS)),
7753 where NELTS is the number of elements in X. Subregs involving
7754 elements [ELT_BIAS, ELT_BIAS + FIRST_VALID) are expected to fail. */
7757 test_vector_subregs_modes (rtx x
, poly_uint64 elt_bias
= 0,
7758 unsigned int first_valid
= 0)
7760 machine_mode inner_mode
= GET_MODE (x
);
7761 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7763 for (unsigned int modei
= 0; modei
< NUM_MACHINE_MODES
; ++modei
)
7765 machine_mode outer_mode
= (machine_mode
) modei
;
7766 if (!VECTOR_MODE_P (outer_mode
))
7769 unsigned int outer_nunits
;
7770 if (GET_MODE_INNER (outer_mode
) == int_mode
7771 && GET_MODE_NUNITS (outer_mode
).is_constant (&outer_nunits
)
7772 && multiple_p (GET_MODE_NUNITS (inner_mode
), outer_nunits
))
7774 /* Test subregs in which the outer mode is a smaller,
7775 constant-sized vector of the same element type. */
7777 = constant_lower_bound (GET_MODE_NUNITS (inner_mode
));
7778 for (unsigned int elt
= 0; elt
< limit
; elt
+= outer_nunits
)
7780 rtx expected
= NULL_RTX
;
7781 if (elt
>= first_valid
)
7783 rtx_vector_builder
builder (outer_mode
, outer_nunits
, 1);
7784 for (unsigned int i
= 0; i
< outer_nunits
; ++i
)
7785 builder
.quick_push (CONST_VECTOR_ELT (x
, elt
+ i
));
7786 expected
= builder
.build ();
7788 poly_uint64 byte
= (elt_bias
+ elt
) * GET_MODE_SIZE (int_mode
);
7789 ASSERT_RTX_EQ (expected
,
7790 simplify_subreg (outer_mode
, x
,
7794 else if (known_eq (GET_MODE_SIZE (outer_mode
),
7795 GET_MODE_SIZE (inner_mode
))
7796 && known_eq (elt_bias
, 0U)
7797 && (GET_MODE_CLASS (outer_mode
) != MODE_VECTOR_BOOL
7798 || known_eq (GET_MODE_BITSIZE (outer_mode
),
7799 GET_MODE_NUNITS (outer_mode
)))
7800 && (!FLOAT_MODE_P (outer_mode
)
7801 || (FLOAT_MODE_FORMAT (outer_mode
)->ieee_bits
7802 == GET_MODE_UNIT_PRECISION (outer_mode
)))
7803 && (GET_MODE_SIZE (inner_mode
).is_constant ()
7804 || !CONST_VECTOR_STEPPED_P (x
)))
7806 /* Try converting to OUTER_MODE and back. */
7807 rtx outer_x
= simplify_subreg (outer_mode
, x
, inner_mode
, 0);
7808 ASSERT_TRUE (outer_x
!= NULL_RTX
);
7809 ASSERT_RTX_EQ (x
, simplify_subreg (inner_mode
, outer_x
,
7814 if (BYTES_BIG_ENDIAN
== WORDS_BIG_ENDIAN
)
7816 /* Test each byte in the element range. */
7818 = constant_lower_bound (GET_MODE_SIZE (inner_mode
));
7819 for (unsigned int i
= 0; i
< limit
; ++i
)
7821 unsigned int elt
= i
/ GET_MODE_SIZE (int_mode
);
7822 rtx expected
= NULL_RTX
;
7823 if (elt
>= first_valid
)
7825 unsigned int byte_shift
= i
% GET_MODE_SIZE (int_mode
);
7826 if (BYTES_BIG_ENDIAN
)
7827 byte_shift
= GET_MODE_SIZE (int_mode
) - byte_shift
- 1;
7828 rtx_mode_t
vec_elt (CONST_VECTOR_ELT (x
, elt
), int_mode
);
7829 wide_int shifted_elt
7830 = wi::lrshift (vec_elt
, byte_shift
* BITS_PER_UNIT
);
7831 expected
= immed_wide_int_const (shifted_elt
, QImode
);
7833 poly_uint64 byte
= elt_bias
* GET_MODE_SIZE (int_mode
) + i
;
7834 ASSERT_RTX_EQ (expected
,
7835 simplify_subreg (QImode
, x
, inner_mode
, byte
));
7840 /* Test constant subregs of integer vector mode INNER_MODE, using 1
7841 element per pattern. */
7844 test_vector_subregs_repeating (machine_mode inner_mode
)
7846 poly_uint64 nunits
= GET_MODE_NUNITS (inner_mode
);
7847 unsigned int min_nunits
= constant_lower_bound (nunits
);
7848 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7849 unsigned int count
= gcd (min_nunits
, 8);
7851 rtx_vector_builder
builder (inner_mode
, count
, 1);
7852 for (unsigned int i
= 0; i
< count
; ++i
)
7853 builder
.quick_push (gen_int_mode (8 - i
, int_mode
));
7854 rtx x
= builder
.build ();
7856 test_vector_subregs_modes (x
);
7857 if (!nunits
.is_constant ())
7858 test_vector_subregs_modes (x
, nunits
- min_nunits
);
7861 /* Test constant subregs of integer vector mode INNER_MODE, using 2
7862 elements per pattern. */
7865 test_vector_subregs_fore_back (machine_mode inner_mode
)
7867 poly_uint64 nunits
= GET_MODE_NUNITS (inner_mode
);
7868 unsigned int min_nunits
= constant_lower_bound (nunits
);
7869 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7870 unsigned int count
= gcd (min_nunits
, 4);
7872 rtx_vector_builder
builder (inner_mode
, count
, 2);
7873 for (unsigned int i
= 0; i
< count
; ++i
)
7874 builder
.quick_push (gen_int_mode (i
, int_mode
));
7875 for (unsigned int i
= 0; i
< count
; ++i
)
7876 builder
.quick_push (gen_int_mode (-(int) i
, int_mode
));
7877 rtx x
= builder
.build ();
7879 test_vector_subregs_modes (x
);
7880 if (!nunits
.is_constant ())
7881 test_vector_subregs_modes (x
, nunits
- min_nunits
, count
);
7884 /* Test constant subregs of integer vector mode INNER_MODE, using 3
7885 elements per pattern. */
7888 test_vector_subregs_stepped (machine_mode inner_mode
)
7890 /* Build { 0, 1, 2, 3, ... }. */
7891 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
7892 rtx_vector_builder
builder (inner_mode
, 1, 3);
7893 for (unsigned int i
= 0; i
< 3; ++i
)
7894 builder
.quick_push (gen_int_mode (i
, int_mode
));
7895 rtx x
= builder
.build ();
7897 test_vector_subregs_modes (x
);
7900 /* Test constant subregs of integer vector mode INNER_MODE. */
7903 test_vector_subregs (machine_mode inner_mode
)
7905 test_vector_subregs_repeating (inner_mode
);
7906 test_vector_subregs_fore_back (inner_mode
);
7907 test_vector_subregs_stepped (inner_mode
);
7910 /* Verify some simplifications involving vectors. */
7915 for (unsigned int i
= 0; i
< NUM_MACHINE_MODES
; ++i
)
7917 machine_mode mode
= (machine_mode
) i
;
7918 if (VECTOR_MODE_P (mode
))
7920 rtx scalar_reg
= make_test_reg (GET_MODE_INNER (mode
));
7921 test_vector_ops_duplicate (mode
, scalar_reg
);
7922 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
7923 && maybe_gt (GET_MODE_NUNITS (mode
), 2))
7925 test_vector_ops_series (mode
, scalar_reg
);
7926 test_vector_subregs (mode
);
7928 test_vec_merge (mode
);
7933 template<unsigned int N
>
7934 struct simplify_const_poly_int_tests
7940 struct simplify_const_poly_int_tests
<1>
7942 static void run () {}
7945 /* Test various CONST_POLY_INT properties. */
7947 template<unsigned int N
>
7949 simplify_const_poly_int_tests
<N
>::run ()
7951 rtx x1
= gen_int_mode (poly_int64 (1, 1), QImode
);
7952 rtx x2
= gen_int_mode (poly_int64 (-80, 127), QImode
);
7953 rtx x3
= gen_int_mode (poly_int64 (-79, -128), QImode
);
7954 rtx x4
= gen_int_mode (poly_int64 (5, 4), QImode
);
7955 rtx x5
= gen_int_mode (poly_int64 (30, 24), QImode
);
7956 rtx x6
= gen_int_mode (poly_int64 (20, 16), QImode
);
7957 rtx x7
= gen_int_mode (poly_int64 (7, 4), QImode
);
7958 rtx x8
= gen_int_mode (poly_int64 (30, 24), HImode
);
7959 rtx x9
= gen_int_mode (poly_int64 (-30, -24), HImode
);
7960 rtx x10
= gen_int_mode (poly_int64 (-31, -24), HImode
);
7961 rtx two
= GEN_INT (2);
7962 rtx six
= GEN_INT (6);
7963 poly_uint64 offset
= subreg_lowpart_offset (QImode
, HImode
);
7965 /* These tests only try limited operation combinations. Fuller arithmetic
7966 testing is done directly on poly_ints. */
7967 ASSERT_EQ (simplify_unary_operation (NEG
, HImode
, x8
, HImode
), x9
);
7968 ASSERT_EQ (simplify_unary_operation (NOT
, HImode
, x8
, HImode
), x10
);
7969 ASSERT_EQ (simplify_unary_operation (TRUNCATE
, QImode
, x8
, HImode
), x5
);
7970 ASSERT_EQ (simplify_binary_operation (PLUS
, QImode
, x1
, x2
), x3
);
7971 ASSERT_EQ (simplify_binary_operation (MINUS
, QImode
, x3
, x1
), x2
);
7972 ASSERT_EQ (simplify_binary_operation (MULT
, QImode
, x4
, six
), x5
);
7973 ASSERT_EQ (simplify_binary_operation (MULT
, QImode
, six
, x4
), x5
);
7974 ASSERT_EQ (simplify_binary_operation (ASHIFT
, QImode
, x4
, two
), x6
);
7975 ASSERT_EQ (simplify_binary_operation (IOR
, QImode
, x4
, two
), x7
);
7976 ASSERT_EQ (simplify_subreg (HImode
, x5
, QImode
, 0), x8
);
7977 ASSERT_EQ (simplify_subreg (QImode
, x8
, HImode
, offset
), x5
);
7980 /* Run all of the selftests within this file. */
7983 simplify_rtx_c_tests ()
7987 simplify_const_poly_int_tests
<NUM_POLY_INT_COEFFS
>::run ();
7990 } // namespace selftest
7992 #endif /* CHECKING_P */