1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack
{
75 int first_gp_reg_save
; /* first callee saved GP register used */
76 int first_fp_reg_save
; /* first callee saved FP register used */
77 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
78 int lr_save_p
; /* true if the link reg needs to be saved */
79 int cr_save_p
; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask
; /* mask of vec registers to save */
81 int toc_save_p
; /* true if the TOC needs to be saved */
82 int push_p
; /* true if we need to allocate stack space */
83 int calls_p
; /* true if the function makes any calls */
84 int world_save_p
; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi
; /* which ABI to use */
87 int gp_save_offset
; /* offset to save GP regs from initial SP */
88 int fp_save_offset
; /* offset to save FP regs from initial SP */
89 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset
; /* offset to save LR from initial SP */
91 int cr_save_offset
; /* offset to save CR from initial SP */
92 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
94 int toc_save_offset
; /* offset to save the TOC pointer */
95 int varargs_save_offset
; /* offset to save the varargs registers */
96 int ehrd_offset
; /* offset to EH return data */
97 int reg_size
; /* register size (4 or 8) */
98 int varargs_size
; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size
; /* variable save area size */
100 int parm_size
; /* outgoing parameter size */
101 int save_size
; /* save area size */
102 int fixed_size
; /* fixed size of stack frame */
103 int gp_size
; /* size of saved GP registers */
104 int fp_size
; /* size of saved FP registers */
105 int altivec_size
; /* size of saved AltiVec registers */
106 int cr_size
; /* size to hold CR if not in save_size */
107 int lr_size
; /* size to hold LR if not in save_size */
108 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size
; /* size of altivec alignment padding if
111 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size
;
113 int toc_size
; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
115 int spe_64bit_regs_used
;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu
;
121 struct rs6000_cpu_select rs6000_select
[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint
;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups
;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str
;
138 int rs6000_sched_restricted_insns_priority
;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str
;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str
;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load
;
151 /* Size of long double */
152 const char *rs6000_long_double_size_string
;
153 int rs6000_long_double_type_size
;
155 /* Whether -mabi=altivec has appeared */
156 int rs6000_altivec_abi
;
158 /* Whether VRSAVE instructions should be generated. */
159 int rs6000_altivec_vrsave
;
161 /* String from -mvrsave= option. */
162 const char *rs6000_altivec_vrsave_string
;
164 /* Nonzero if we want SPE ABI extensions. */
167 /* Whether isel instructions should be generated. */
170 /* Whether SPE simd instructions should be generated. */
173 /* Nonzero if floating point operations are done in the GPRs. */
174 int rs6000_float_gprs
= 0;
176 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
177 int rs6000_darwin64_abi
;
179 /* String from -mfloat-gprs=. */
180 const char *rs6000_float_gprs_string
;
182 /* String from -misel=. */
183 const char *rs6000_isel_string
;
185 /* String from -mspe=. */
186 const char *rs6000_spe_string
;
188 /* Set to nonzero once AIX common-mode calls have been defined. */
189 static GTY(()) int common_mode_defined
;
191 /* Save information from a "cmpxx" operation until the branch or scc is
193 rtx rs6000_compare_op0
, rs6000_compare_op1
;
194 int rs6000_compare_fp_p
;
196 /* Label number of label created for -mrelocatable, to call to so we can
197 get the address of the GOT section */
198 int rs6000_pic_labelno
;
201 /* Which abi to adhere to */
202 const char *rs6000_abi_name
;
204 /* Semantics of the small data area */
205 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
207 /* Which small data model to use */
208 const char *rs6000_sdata_name
= (char *)0;
210 /* Counter for labels which are to be placed in .fixup. */
211 int fixuplabelno
= 0;
214 /* Bit size of immediate TLS offsets and string from which it is decoded. */
215 int rs6000_tls_size
= 32;
216 const char *rs6000_tls_size_string
;
218 /* ABI enumeration available for subtarget to use. */
219 enum rs6000_abi rs6000_current_abi
;
221 /* ABI string from -mabi= option. */
222 const char *rs6000_abi_string
;
224 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
228 const char *rs6000_debug_name
;
229 int rs6000_debug_stack
; /* debug stack applications */
230 int rs6000_debug_arg
; /* debug argument handling */
232 /* Value is TRUE if register/mode pair is accepatable. */
233 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
236 static GTY(()) tree opaque_V2SI_type_node
;
237 static GTY(()) tree opaque_V2SF_type_node
;
238 static GTY(()) tree opaque_p_V2SI_type_node
;
239 static GTY(()) tree V16QI_type_node
;
240 static GTY(()) tree V2SI_type_node
;
241 static GTY(()) tree V2SF_type_node
;
242 static GTY(()) tree V4HI_type_node
;
243 static GTY(()) tree V4SI_type_node
;
244 static GTY(()) tree V4SF_type_node
;
245 static GTY(()) tree V8HI_type_node
;
246 static GTY(()) tree unsigned_V16QI_type_node
;
247 static GTY(()) tree unsigned_V8HI_type_node
;
248 static GTY(()) tree unsigned_V4SI_type_node
;
249 static GTY(()) tree bool_char_type_node
; /* __bool char */
250 static GTY(()) tree bool_short_type_node
; /* __bool short */
251 static GTY(()) tree bool_int_type_node
; /* __bool int */
252 static GTY(()) tree pixel_type_node
; /* __pixel */
253 static GTY(()) tree bool_V16QI_type_node
; /* __vector __bool char */
254 static GTY(()) tree bool_V8HI_type_node
; /* __vector __bool short */
255 static GTY(()) tree bool_V4SI_type_node
; /* __vector __bool int */
256 static GTY(()) tree pixel_V8HI_type_node
; /* __vector __pixel */
258 int rs6000_warn_altivec_long
= 1; /* On by default. */
259 const char *rs6000_warn_altivec_long_switch
;
261 const char *rs6000_traceback_name
;
263 traceback_default
= 0,
269 /* Flag to say the TOC is initialized */
271 char toc_label_name
[10];
273 /* Alias set for saves and restores from the rs6000 stack. */
274 static GTY(()) int rs6000_sr_alias_set
;
276 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
277 The only place that looks at this is rs6000_set_default_type_attributes;
278 everywhere else should rely on the presence or absence of a longcall
279 attribute on the function declaration. Exception: init_cumulative_args
280 looks at it too, for libcalls. */
281 int rs6000_default_long_calls
;
282 const char *rs6000_longcall_switch
;
284 /* Control alignment for fields within structures. */
285 /* String from -malign-XXXXX. */
286 const char *rs6000_alignment_string
;
287 int rs6000_alignment_flags
;
289 struct builtin_description
291 /* mask is not const because we're going to alter it below. This
292 nonsense will go away when we rewrite the -march infrastructure
293 to give us more target flag bits. */
295 const enum insn_code icode
;
296 const char *const name
;
297 const enum rs6000_builtins code
;
300 /* Target cpu costs. */
302 struct processor_costs
{
303 const int mulsi
; /* cost of SImode multiplication. */
304 const int mulsi_const
; /* cost of SImode multiplication by constant. */
305 const int mulsi_const9
; /* cost of SImode mult by short constant. */
306 const int muldi
; /* cost of DImode multiplication. */
307 const int divsi
; /* cost of SImode division. */
308 const int divdi
; /* cost of DImode division. */
309 const int fp
; /* cost of simple SFmode and DFmode insns. */
310 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
311 const int sdiv
; /* cost of SFmode division (fdivs). */
312 const int ddiv
; /* cost of DFmode division (fdiv). */
315 const struct processor_costs
*rs6000_cost
;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost
= {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
334 /* Instruction size costs on 64bit processors. */
336 struct processor_costs size64_cost
= {
337 COSTS_N_INSNS (1), /* mulsi */
338 COSTS_N_INSNS (1), /* mulsi_const */
339 COSTS_N_INSNS (1), /* mulsi_const9 */
340 COSTS_N_INSNS (1), /* muldi */
341 COSTS_N_INSNS (1), /* divsi */
342 COSTS_N_INSNS (1), /* divdi */
343 COSTS_N_INSNS (1), /* fp */
344 COSTS_N_INSNS (1), /* dmul */
345 COSTS_N_INSNS (1), /* sdiv */
346 COSTS_N_INSNS (1), /* ddiv */
349 /* Instruction costs on RIOS1 processors. */
351 struct processor_costs rios1_cost
= {
352 COSTS_N_INSNS (5), /* mulsi */
353 COSTS_N_INSNS (4), /* mulsi_const */
354 COSTS_N_INSNS (3), /* mulsi_const9 */
355 COSTS_N_INSNS (5), /* muldi */
356 COSTS_N_INSNS (19), /* divsi */
357 COSTS_N_INSNS (19), /* divdi */
358 COSTS_N_INSNS (2), /* fp */
359 COSTS_N_INSNS (2), /* dmul */
360 COSTS_N_INSNS (19), /* sdiv */
361 COSTS_N_INSNS (19), /* ddiv */
364 /* Instruction costs on RIOS2 processors. */
366 struct processor_costs rios2_cost
= {
367 COSTS_N_INSNS (2), /* mulsi */
368 COSTS_N_INSNS (2), /* mulsi_const */
369 COSTS_N_INSNS (2), /* mulsi_const9 */
370 COSTS_N_INSNS (2), /* muldi */
371 COSTS_N_INSNS (13), /* divsi */
372 COSTS_N_INSNS (13), /* divdi */
373 COSTS_N_INSNS (2), /* fp */
374 COSTS_N_INSNS (2), /* dmul */
375 COSTS_N_INSNS (17), /* sdiv */
376 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost
= {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
394 /* Instruction costs on MPCCORE processors. */
396 struct processor_costs mpccore_cost
= {
397 COSTS_N_INSNS (2), /* mulsi */
398 COSTS_N_INSNS (2), /* mulsi_const */
399 COSTS_N_INSNS (2), /* mulsi_const9 */
400 COSTS_N_INSNS (2), /* muldi */
401 COSTS_N_INSNS (6), /* divsi */
402 COSTS_N_INSNS (6), /* divdi */
403 COSTS_N_INSNS (4), /* fp */
404 COSTS_N_INSNS (5), /* dmul */
405 COSTS_N_INSNS (10), /* sdiv */
406 COSTS_N_INSNS (17), /* ddiv */
409 /* Instruction costs on PPC403 processors. */
411 struct processor_costs ppc403_cost
= {
412 COSTS_N_INSNS (4), /* mulsi */
413 COSTS_N_INSNS (4), /* mulsi_const */
414 COSTS_N_INSNS (4), /* mulsi_const9 */
415 COSTS_N_INSNS (4), /* muldi */
416 COSTS_N_INSNS (33), /* divsi */
417 COSTS_N_INSNS (33), /* divdi */
418 COSTS_N_INSNS (11), /* fp */
419 COSTS_N_INSNS (11), /* dmul */
420 COSTS_N_INSNS (11), /* sdiv */
421 COSTS_N_INSNS (11), /* ddiv */
424 /* Instruction costs on PPC405 processors. */
426 struct processor_costs ppc405_cost
= {
427 COSTS_N_INSNS (5), /* mulsi */
428 COSTS_N_INSNS (4), /* mulsi_const */
429 COSTS_N_INSNS (3), /* mulsi_const9 */
430 COSTS_N_INSNS (5), /* muldi */
431 COSTS_N_INSNS (35), /* divsi */
432 COSTS_N_INSNS (35), /* divdi */
433 COSTS_N_INSNS (11), /* fp */
434 COSTS_N_INSNS (11), /* dmul */
435 COSTS_N_INSNS (11), /* sdiv */
436 COSTS_N_INSNS (11), /* ddiv */
439 /* Instruction costs on PPC440 processors. */
441 struct processor_costs ppc440_cost
= {
442 COSTS_N_INSNS (3), /* mulsi */
443 COSTS_N_INSNS (2), /* mulsi_const */
444 COSTS_N_INSNS (2), /* mulsi_const9 */
445 COSTS_N_INSNS (3), /* muldi */
446 COSTS_N_INSNS (34), /* divsi */
447 COSTS_N_INSNS (34), /* divdi */
448 COSTS_N_INSNS (5), /* fp */
449 COSTS_N_INSNS (5), /* dmul */
450 COSTS_N_INSNS (19), /* sdiv */
451 COSTS_N_INSNS (33), /* ddiv */
454 /* Instruction costs on PPC601 processors. */
456 struct processor_costs ppc601_cost
= {
457 COSTS_N_INSNS (5), /* mulsi */
458 COSTS_N_INSNS (5), /* mulsi_const */
459 COSTS_N_INSNS (5), /* mulsi_const9 */
460 COSTS_N_INSNS (5), /* muldi */
461 COSTS_N_INSNS (36), /* divsi */
462 COSTS_N_INSNS (36), /* divdi */
463 COSTS_N_INSNS (4), /* fp */
464 COSTS_N_INSNS (5), /* dmul */
465 COSTS_N_INSNS (17), /* sdiv */
466 COSTS_N_INSNS (31), /* ddiv */
469 /* Instruction costs on PPC603 processors. */
471 struct processor_costs ppc603_cost
= {
472 COSTS_N_INSNS (5), /* mulsi */
473 COSTS_N_INSNS (3), /* mulsi_const */
474 COSTS_N_INSNS (2), /* mulsi_const9 */
475 COSTS_N_INSNS (5), /* muldi */
476 COSTS_N_INSNS (37), /* divsi */
477 COSTS_N_INSNS (37), /* divdi */
478 COSTS_N_INSNS (3), /* fp */
479 COSTS_N_INSNS (4), /* dmul */
480 COSTS_N_INSNS (18), /* sdiv */
481 COSTS_N_INSNS (33), /* ddiv */
484 /* Instruction costs on PPC604 processors. */
486 struct processor_costs ppc604_cost
= {
487 COSTS_N_INSNS (4), /* mulsi */
488 COSTS_N_INSNS (4), /* mulsi_const */
489 COSTS_N_INSNS (4), /* mulsi_const9 */
490 COSTS_N_INSNS (4), /* muldi */
491 COSTS_N_INSNS (20), /* divsi */
492 COSTS_N_INSNS (20), /* divdi */
493 COSTS_N_INSNS (3), /* fp */
494 COSTS_N_INSNS (3), /* dmul */
495 COSTS_N_INSNS (18), /* sdiv */
496 COSTS_N_INSNS (32), /* ddiv */
499 /* Instruction costs on PPC604e processors. */
501 struct processor_costs ppc604e_cost
= {
502 COSTS_N_INSNS (2), /* mulsi */
503 COSTS_N_INSNS (2), /* mulsi_const */
504 COSTS_N_INSNS (2), /* mulsi_const9 */
505 COSTS_N_INSNS (2), /* muldi */
506 COSTS_N_INSNS (20), /* divsi */
507 COSTS_N_INSNS (20), /* divdi */
508 COSTS_N_INSNS (3), /* fp */
509 COSTS_N_INSNS (3), /* dmul */
510 COSTS_N_INSNS (18), /* sdiv */
511 COSTS_N_INSNS (32), /* ddiv */
514 /* Instruction costs on PPC620 processors. */
516 struct processor_costs ppc620_cost
= {
517 COSTS_N_INSNS (5), /* mulsi */
518 COSTS_N_INSNS (4), /* mulsi_const */
519 COSTS_N_INSNS (3), /* mulsi_const9 */
520 COSTS_N_INSNS (7), /* muldi */
521 COSTS_N_INSNS (21), /* divsi */
522 COSTS_N_INSNS (37), /* divdi */
523 COSTS_N_INSNS (3), /* fp */
524 COSTS_N_INSNS (3), /* dmul */
525 COSTS_N_INSNS (18), /* sdiv */
526 COSTS_N_INSNS (32), /* ddiv */
529 /* Instruction costs on PPC630 processors. */
531 struct processor_costs ppc630_cost
= {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (4), /* mulsi_const */
534 COSTS_N_INSNS (3), /* mulsi_const9 */
535 COSTS_N_INSNS (7), /* muldi */
536 COSTS_N_INSNS (21), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (3), /* dmul */
540 COSTS_N_INSNS (17), /* sdiv */
541 COSTS_N_INSNS (21), /* ddiv */
544 /* Instruction costs on PPC750 and PPC7400 processors. */
546 struct processor_costs ppc750_cost
= {
547 COSTS_N_INSNS (5), /* mulsi */
548 COSTS_N_INSNS (3), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (5), /* muldi */
551 COSTS_N_INSNS (17), /* divsi */
552 COSTS_N_INSNS (17), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (17), /* sdiv */
556 COSTS_N_INSNS (31), /* ddiv */
559 /* Instruction costs on PPC7450 processors. */
561 struct processor_costs ppc7450_cost
= {
562 COSTS_N_INSNS (4), /* mulsi */
563 COSTS_N_INSNS (3), /* mulsi_const */
564 COSTS_N_INSNS (3), /* mulsi_const9 */
565 COSTS_N_INSNS (4), /* muldi */
566 COSTS_N_INSNS (23), /* divsi */
567 COSTS_N_INSNS (23), /* divdi */
568 COSTS_N_INSNS (5), /* fp */
569 COSTS_N_INSNS (5), /* dmul */
570 COSTS_N_INSNS (21), /* sdiv */
571 COSTS_N_INSNS (35), /* ddiv */
574 /* Instruction costs on PPC8540 processors. */
576 struct processor_costs ppc8540_cost
= {
577 COSTS_N_INSNS (4), /* mulsi */
578 COSTS_N_INSNS (4), /* mulsi_const */
579 COSTS_N_INSNS (4), /* mulsi_const9 */
580 COSTS_N_INSNS (4), /* muldi */
581 COSTS_N_INSNS (19), /* divsi */
582 COSTS_N_INSNS (19), /* divdi */
583 COSTS_N_INSNS (4), /* fp */
584 COSTS_N_INSNS (4), /* dmul */
585 COSTS_N_INSNS (29), /* sdiv */
586 COSTS_N_INSNS (29), /* ddiv */
589 /* Instruction costs on POWER4 and POWER5 processors. */
591 struct processor_costs power4_cost
= {
592 COSTS_N_INSNS (3), /* mulsi */
593 COSTS_N_INSNS (2), /* mulsi_const */
594 COSTS_N_INSNS (2), /* mulsi_const9 */
595 COSTS_N_INSNS (4), /* muldi */
596 COSTS_N_INSNS (18), /* divsi */
597 COSTS_N_INSNS (34), /* divdi */
598 COSTS_N_INSNS (3), /* fp */
599 COSTS_N_INSNS (3), /* dmul */
600 COSTS_N_INSNS (17), /* sdiv */
601 COSTS_N_INSNS (17), /* ddiv */
605 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
606 static int num_insns_constant_wide (HOST_WIDE_INT
);
607 static void validate_condition_mode (enum rtx_code
, enum machine_mode
);
608 static rtx
rs6000_generate_compare (enum rtx_code
);
609 static void rs6000_maybe_dead (rtx
);
610 static void rs6000_emit_stack_tie (void);
611 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
612 static rtx
spe_synthesize_frame_save (rtx
);
613 static bool spe_func_has_64bit_regs_p (void);
614 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
616 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
617 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int);
618 static unsigned rs6000_hash_constant (rtx
);
619 static unsigned toc_hash_function (const void *);
620 static int toc_hash_eq (const void *, const void *);
621 static int constant_pool_expr_1 (rtx
, int *, int *);
622 static bool constant_pool_expr_p (rtx
);
623 static bool toc_relative_expr_p (rtx
);
624 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
625 static bool legitimate_indexed_address_p (rtx
, int);
626 static bool legitimate_indirect_address_p (rtx
, int);
627 static bool macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
);
628 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
629 static struct machine_function
* rs6000_init_machine_status (void);
630 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
631 #ifdef HAVE_GAS_HIDDEN
632 static void rs6000_assemble_visibility (tree
, int);
634 static int rs6000_ra_ever_killed (void);
635 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
636 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
637 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
638 static const char *rs6000_mangle_fundamental_type (tree
);
639 extern const struct attribute_spec rs6000_attribute_table
[];
640 static void rs6000_set_default_type_attributes (tree
);
641 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
642 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
643 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
645 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
646 static bool rs6000_return_in_memory (tree
, tree
);
647 static void rs6000_file_start (void);
649 static unsigned int rs6000_elf_section_type_flags (tree
, const char *, int);
650 static void rs6000_elf_asm_out_constructor (rtx
, int);
651 static void rs6000_elf_asm_out_destructor (rtx
, int);
652 static void rs6000_elf_select_section (tree
, int, unsigned HOST_WIDE_INT
);
653 static void rs6000_elf_unique_section (tree
, int);
654 static void rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
655 unsigned HOST_WIDE_INT
);
656 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
658 static bool rs6000_elf_in_small_data_p (tree
);
661 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
662 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
663 static void rs6000_xcoff_select_section (tree
, int, unsigned HOST_WIDE_INT
);
664 static void rs6000_xcoff_unique_section (tree
, int);
665 static void rs6000_xcoff_select_rtx_section (enum machine_mode
, rtx
,
666 unsigned HOST_WIDE_INT
);
667 static const char * rs6000_xcoff_strip_name_encoding (const char *);
668 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
669 static void rs6000_xcoff_file_start (void);
670 static void rs6000_xcoff_file_end (void);
673 static bool rs6000_binds_local_p (tree
);
675 static int rs6000_variable_issue (FILE *, int, rtx
, int);
676 static bool rs6000_rtx_costs (rtx
, int, int, int *);
677 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
678 static bool is_microcoded_insn (rtx
);
679 static int is_dispatch_slot_restricted (rtx
);
680 static bool is_cracked_insn (rtx
);
681 static bool is_branch_slot_insn (rtx
);
682 static int rs6000_adjust_priority (rtx
, int);
683 static int rs6000_issue_rate (void);
684 static bool rs6000_is_costly_dependence (rtx
, rtx
, rtx
, int, int);
685 static rtx
get_next_active_insn (rtx
, rtx
);
686 static bool insn_terminates_group_p (rtx
, enum group_termination
);
687 static bool is_costly_group (rtx
*, rtx
);
688 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
689 static int redefine_groups (FILE *, int, rtx
, rtx
);
690 static int pad_groups (FILE *, int, rtx
, rtx
);
691 static void rs6000_sched_finish (FILE *, int);
692 static int rs6000_use_sched_lookahead (void);
693 static tree
rs6000_builtin_mask_for_load (void);
695 static void rs6000_init_builtins (void);
696 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
697 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
698 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
699 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
700 static void altivec_init_builtins (void);
701 static void rs6000_common_init_builtins (void);
702 static void rs6000_init_libfuncs (void);
704 static void enable_mask_for_builtins (struct builtin_description
*, int,
705 enum rs6000_builtins
,
706 enum rs6000_builtins
);
707 static tree
build_opaque_vector_type (tree
, int);
708 static void spe_init_builtins (void);
709 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
710 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
711 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
712 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
713 static bool invalid_e500_subreg (rtx
, enum machine_mode
);
714 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
715 static rs6000_stack_t
*rs6000_stack_info (void);
716 static void debug_stack_info (rs6000_stack_t
*);
718 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
719 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
720 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
721 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
722 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
723 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
724 const char *, tree
, rtx
);
725 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
726 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
727 static void rs6000_parse_abi_options (void);
728 static void rs6000_parse_alignment_option (void);
729 static void rs6000_parse_tls_size_option (void);
730 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
731 static void rs6000_parse_float_gprs_option (void);
732 static int first_altivec_reg_to_save (void);
733 static unsigned int compute_vrsave_mask (void);
734 static void compute_save_world_info(rs6000_stack_t
*info_ptr
);
735 static void is_altivec_return_reg (rtx
, void *);
736 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
737 int easy_vector_constant (rtx
, enum machine_mode
);
738 static int easy_vector_same (rtx
, enum machine_mode
);
739 static int easy_vector_splat_const (int, enum machine_mode
);
740 static bool is_ev64_opaque_type (tree
);
741 static rtx
rs6000_dwarf_register_span (rtx
);
742 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
743 static rtx
rs6000_tls_get_addr (void);
744 static rtx
rs6000_got_sym (void);
745 static inline int rs6000_tls_symbol_ref_1 (rtx
*, void *);
746 static const char *rs6000_get_some_local_dynamic_name (void);
747 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
748 static rtx
rs6000_complex_function_value (enum machine_mode
);
749 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
750 enum machine_mode
, tree
);
751 static rtx
rs6000_darwin64_function_arg (CUMULATIVE_ARGS
*,
752 enum machine_mode
, tree
, int);
753 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
754 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
755 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
756 enum machine_mode
, tree
,
758 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
760 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
763 static void macho_branch_islands (void);
764 static void add_compiler_branch_island (tree
, tree
, int);
765 static int no_previous_def (tree function_name
);
766 static tree
get_prev_label (tree function_name
);
767 static void rs6000_darwin_file_start (void);
770 static tree
rs6000_build_builtin_va_list (void);
771 static tree
rs6000_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
772 static bool rs6000_must_pass_in_stack (enum machine_mode
, tree
);
773 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
774 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
776 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
778 static int get_vsel_insn (enum machine_mode
);
779 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
782 const int INSN_NOT_AVAILABLE
= -1;
783 static enum machine_mode
rs6000_eh_return_filter_mode (void);
785 /* Hash table stuff for keeping track of TOC entries. */
787 struct toc_hash_struct
GTY(())
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
792 enum machine_mode key_mode
;
796 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
798 /* Default register names. */
799 char rs6000_reg_names
[][8] =
801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
812 /* AltiVec registers. */
813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
822 #ifdef TARGET_REGNAMES
823 static const char alt_reg_names
[][8] =
825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
836 /* AltiVec registers. */
837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
847 #ifndef MASK_STRICT_ALIGN
848 #define MASK_STRICT_ALIGN 0
850 #ifndef TARGET_PROFILE_KERNEL
851 #define TARGET_PROFILE_KERNEL 0
854 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
857 /* Return 1 for a symbol ref for a thread-local storage symbol. */
858 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
859 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
861 /* Initialize the GCC target structure. */
862 #undef TARGET_ATTRIBUTE_TABLE
863 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
864 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
865 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
867 #undef TARGET_ASM_ALIGNED_DI_OP
868 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
870 /* Default unaligned ops are only provided for ELF. Find the ops needed
871 for non-ELF systems. */
872 #ifndef OBJECT_FORMAT_ELF
874 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
876 #undef TARGET_ASM_UNALIGNED_HI_OP
877 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
878 #undef TARGET_ASM_UNALIGNED_SI_OP
879 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
880 #undef TARGET_ASM_UNALIGNED_DI_OP
881 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
884 #undef TARGET_ASM_UNALIGNED_HI_OP
885 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
886 #undef TARGET_ASM_UNALIGNED_SI_OP
887 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
888 #undef TARGET_ASM_UNALIGNED_DI_OP
889 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
890 #undef TARGET_ASM_ALIGNED_DI_OP
891 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
895 /* This hook deals with fixups for relocatable code and DI-mode objects
897 #undef TARGET_ASM_INTEGER
898 #define TARGET_ASM_INTEGER rs6000_assemble_integer
900 #ifdef HAVE_GAS_HIDDEN
901 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
902 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
905 #undef TARGET_HAVE_TLS
906 #define TARGET_HAVE_TLS HAVE_AS_TLS
908 #undef TARGET_CANNOT_FORCE_CONST_MEM
909 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
911 #undef TARGET_ASM_FUNCTION_PROLOGUE
912 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
913 #undef TARGET_ASM_FUNCTION_EPILOGUE
914 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
916 #undef TARGET_SCHED_VARIABLE_ISSUE
917 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
919 #undef TARGET_SCHED_ISSUE_RATE
920 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
921 #undef TARGET_SCHED_ADJUST_COST
922 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
923 #undef TARGET_SCHED_ADJUST_PRIORITY
924 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
925 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
926 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
927 #undef TARGET_SCHED_FINISH
928 #define TARGET_SCHED_FINISH rs6000_sched_finish
930 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
931 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
933 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
934 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
936 #undef TARGET_INIT_BUILTINS
937 #define TARGET_INIT_BUILTINS rs6000_init_builtins
939 #undef TARGET_EXPAND_BUILTIN
940 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
942 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
943 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
945 #undef TARGET_INIT_LIBFUNCS
946 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
949 #undef TARGET_BINDS_LOCAL_P
950 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
953 #undef TARGET_ASM_OUTPUT_MI_THUNK
954 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
956 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
957 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
959 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
960 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
962 #undef TARGET_RTX_COSTS
963 #define TARGET_RTX_COSTS rs6000_rtx_costs
964 #undef TARGET_ADDRESS_COST
965 #define TARGET_ADDRESS_COST hook_int_rtx_0
967 #undef TARGET_VECTOR_OPAQUE_P
968 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
970 #undef TARGET_DWARF_REGISTER_SPAN
971 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
973 /* On rs6000, function arguments are promoted, as are function return
975 #undef TARGET_PROMOTE_FUNCTION_ARGS
976 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
977 #undef TARGET_PROMOTE_FUNCTION_RETURN
978 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
980 #undef TARGET_RETURN_IN_MEMORY
981 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
983 #undef TARGET_SETUP_INCOMING_VARARGS
984 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
986 /* Always strict argument naming on rs6000. */
987 #undef TARGET_STRICT_ARGUMENT_NAMING
988 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
989 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
990 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
991 #undef TARGET_SPLIT_COMPLEX_ARG
992 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
993 #undef TARGET_MUST_PASS_IN_STACK
994 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
995 #undef TARGET_PASS_BY_REFERENCE
996 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
997 #undef TARGET_ARG_PARTIAL_BYTES
998 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1000 #undef TARGET_BUILD_BUILTIN_VA_LIST
1001 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1003 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1004 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1006 #undef TARGET_EH_RETURN_FILTER_MODE
1007 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1009 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1010 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1012 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1013 The PowerPC architecture requires only weak consistency among
1014 processors--that is, memory accesses between processors need not be
1015 sequentially consistent and memory accesses among processors can occur
1016 in any order. The ability to order memory accesses weakly provides
1017 opportunities for more efficient use of the system bus. Unless a
1018 dependency exists, the 604e allows read operations to precede store
1020 #undef TARGET_RELAXED_ORDERING
1021 #define TARGET_RELAXED_ORDERING true
1023 struct gcc_target targetm
= TARGET_INITIALIZER
;
1026 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1029 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1031 /* The GPRs can hold any mode, but values bigger than one register
1032 cannot go past R31. */
1033 if (INT_REGNO_P (regno
))
1034 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1036 /* The float registers can only hold floating modes and DImode. */
1037 if (FP_REGNO_P (regno
))
1039 (GET_MODE_CLASS (mode
) == MODE_FLOAT
1040 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1041 || (GET_MODE_CLASS (mode
) == MODE_INT
1042 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
);
1044 /* The CR register can only hold CC modes. */
1045 if (CR_REGNO_P (regno
))
1046 return GET_MODE_CLASS (mode
) == MODE_CC
;
1048 if (XER_REGNO_P (regno
))
1049 return mode
== PSImode
;
1051 /* AltiVec only in AldyVec registers. */
1052 if (ALTIVEC_REGNO_P (regno
))
1053 return ALTIVEC_VECTOR_MODE (mode
);
1055 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1056 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1059 /* We cannot put TImode anywhere except general register and it must be
1060 able to fit within the register set. */
1062 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1065 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1067 rs6000_init_hard_regno_mode_ok (void)
1071 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1072 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1073 if (rs6000_hard_regno_mode_ok (r
, m
))
1074 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1077 /* If not otherwise specified by a target, make 'long double' equivalent to
1080 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1081 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1084 /* Override command line options. Mostly we process the processor
1085 type and sometimes adjust other TARGET_ options. */
1088 rs6000_override_options (const char *default_cpu
)
1091 struct rs6000_cpu_select
*ptr
;
1094 /* Simplifications for entries below. */
1097 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1098 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1101 /* This table occasionally claims that a processor does not support
1102 a particular feature even though it does, but the feature is slower
1103 than the alternative. Thus, it shouldn't be relied on as a
1104 complete description of the processor's support.
1106 Please keep this list in order, and don't forget to update the
1107 documentation in invoke.texi when adding a new processor or
1111 const char *const name
; /* Canonical processor name. */
1112 const enum processor_type processor
; /* Processor type enum value. */
1113 const int target_enable
; /* Target flags to enable. */
1114 } const processor_target_table
[]
1115 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1116 {"403", PROCESSOR_PPC403
,
1117 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1118 {"405", PROCESSOR_PPC405
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1119 {"405fp", PROCESSOR_PPC405
, POWERPC_BASE_MASK
},
1120 {"440", PROCESSOR_PPC440
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1121 {"440fp", PROCESSOR_PPC440
, POWERPC_BASE_MASK
},
1122 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1123 {"601", PROCESSOR_PPC601
,
1124 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1125 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1126 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1127 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1128 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1129 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1130 {"620", PROCESSOR_PPC620
,
1131 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1132 {"630", PROCESSOR_PPC630
,
1133 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1134 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1135 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1136 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1137 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1138 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1139 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1140 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1141 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1142 /* 8548 has a dummy entry for now. */
1143 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1144 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1145 {"970", PROCESSOR_POWER4
,
1146 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1147 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1148 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1149 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1150 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1151 {"G5", PROCESSOR_POWER4
,
1152 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1153 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1154 {"power2", PROCESSOR_POWER
,
1155 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1156 {"power3", PROCESSOR_PPC630
,
1157 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1158 {"power4", PROCESSOR_POWER4
,
1159 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1160 {"power5", PROCESSOR_POWER5
,
1161 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1162 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1163 {"powerpc64", PROCESSOR_POWERPC64
,
1164 POWERPC_BASE_MASK
| MASK_POWERPC64
},
1165 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1166 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1167 {"rios2", PROCESSOR_RIOS2
,
1168 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1169 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1170 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1171 {"rs64a", PROCESSOR_RS64A
, POWERPC_BASE_MASK
| MASK_POWERPC64
},
1174 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1176 /* Some OSs don't support saving the high part of 64-bit registers on
1177 context switch. Other OSs don't support saving Altivec registers.
1178 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1179 settings; if the user wants either, the user must explicitly specify
1180 them and we won't interfere with the user's specification. */
1183 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1184 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
1185 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1189 rs6000_init_hard_regno_mode_ok ();
1191 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1192 #ifdef OS_MISSING_POWERPC64
1193 if (OS_MISSING_POWERPC64
)
1194 set_masks
&= ~MASK_POWERPC64
;
1196 #ifdef OS_MISSING_ALTIVEC
1197 if (OS_MISSING_ALTIVEC
)
1198 set_masks
&= ~MASK_ALTIVEC
;
1201 /* Don't override these by the processor default if given explicitly. */
1202 set_masks
&= ~(target_flags_explicit
1203 & (MASK_MULTIPLE
| MASK_STRING
| MASK_SOFT_FLOAT
));
1205 /* Identify the processor type. */
1206 rs6000_select
[0].string
= default_cpu
;
1207 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1209 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1211 ptr
= &rs6000_select
[i
];
1212 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1214 for (j
= 0; j
< ptt_size
; j
++)
1215 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1217 if (ptr
->set_tune_p
)
1218 rs6000_cpu
= processor_target_table
[j
].processor
;
1220 if (ptr
->set_arch_p
)
1222 target_flags
&= ~set_masks
;
1223 target_flags
|= (processor_target_table
[j
].target_enable
1230 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1237 /* If we are optimizing big endian systems for space, use the load/store
1238 multiple and string instructions. */
1239 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1240 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1242 /* Don't allow -mmultiple or -mstring on little endian systems
1243 unless the cpu is a 750, because the hardware doesn't support the
1244 instructions used in little endian mode, and causes an alignment
1245 trap. The 750 does not cause an alignment trap (except when the
1246 target is unaligned). */
1248 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1250 if (TARGET_MULTIPLE
)
1252 target_flags
&= ~MASK_MULTIPLE
;
1253 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1254 warning ("-mmultiple is not supported on little endian systems");
1259 target_flags
&= ~MASK_STRING
;
1260 if ((target_flags_explicit
& MASK_STRING
) != 0)
1261 warning ("-mstring is not supported on little endian systems");
1265 /* Set debug flags */
1266 if (rs6000_debug_name
)
1268 if (! strcmp (rs6000_debug_name
, "all"))
1269 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1270 else if (! strcmp (rs6000_debug_name
, "stack"))
1271 rs6000_debug_stack
= 1;
1272 else if (! strcmp (rs6000_debug_name
, "arg"))
1273 rs6000_debug_arg
= 1;
1275 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1278 if (rs6000_traceback_name
)
1280 if (! strncmp (rs6000_traceback_name
, "full", 4))
1281 rs6000_traceback
= traceback_full
;
1282 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1283 rs6000_traceback
= traceback_part
;
1284 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1285 rs6000_traceback
= traceback_none
;
1287 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1288 rs6000_traceback_name
);
1291 /* Set size of long double */
1292 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1293 if (rs6000_long_double_size_string
)
1296 int size
= strtol (rs6000_long_double_size_string
, &tail
, 10);
1297 if (*tail
!= '\0' || (size
!= 64 && size
!= 128))
1298 error ("Unknown switch -mlong-double-%s",
1299 rs6000_long_double_size_string
);
1301 rs6000_long_double_type_size
= size
;
1304 /* Set Altivec ABI as default for powerpc64 linux. */
1305 if (TARGET_ELF
&& TARGET_64BIT
)
1307 rs6000_altivec_abi
= 1;
1308 rs6000_altivec_vrsave
= 1;
1311 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1312 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1314 rs6000_darwin64_abi
= 1;
1315 /* Setting to empty string is same as "-mone-byte-bool". */
1317 darwin_one_byte_bool
= "";
1321 /* Handle -mabi= options. */
1322 rs6000_parse_abi_options ();
1324 /* Handle -malign-XXXXX option. */
1325 rs6000_parse_alignment_option ();
1327 rs6000_parse_float_gprs_option ();
1329 /* Handle generic -mFOO=YES/NO options. */
1330 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string
,
1331 &rs6000_altivec_vrsave
);
1332 rs6000_parse_yes_no_option ("isel", rs6000_isel_string
,
1334 rs6000_parse_yes_no_option ("spe", rs6000_spe_string
, &rs6000_spe
);
1336 /* Handle -mtls-size option. */
1337 rs6000_parse_tls_size_option ();
1339 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1340 SUBTARGET_OVERRIDE_OPTIONS
;
1342 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1343 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1345 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1346 SUB3TARGET_OVERRIDE_OPTIONS
;
1352 error ("AltiVec and E500 instructions cannot coexist");
1354 /* The e500 does not have string instructions, and we set
1355 MASK_STRING above when optimizing for size. */
1356 if ((target_flags
& MASK_STRING
) != 0)
1357 target_flags
= target_flags
& ~MASK_STRING
;
1359 /* No SPE means 64-bit long doubles, even if an E500. */
1360 if (rs6000_spe_string
!= 0
1361 && !strcmp (rs6000_spe_string
, "no"))
1362 rs6000_long_double_type_size
= 64;
1364 else if (rs6000_select
[1].string
!= NULL
)
1366 /* For the powerpc-eabispe configuration, we set all these by
1367 default, so let's unset them if we manually set another
1368 CPU that is not the E500. */
1369 if (rs6000_abi_string
== 0)
1371 if (rs6000_spe_string
== 0)
1373 if (rs6000_float_gprs_string
== 0)
1374 rs6000_float_gprs
= 0;
1375 if (rs6000_isel_string
== 0)
1377 if (rs6000_long_double_size_string
== 0)
1378 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1381 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1382 && rs6000_cpu
!= PROCESSOR_POWER5
);
1383 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1384 || rs6000_cpu
== PROCESSOR_POWER5
);
1386 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1387 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1388 bits in target_flags so TARGET_SWITCHES cannot be used.
1389 Assumption here is that rs6000_longcall_switch points into the
1390 text of the complete option, rather than being a copy, so we can
1391 scan back for the presence or absence of the no- modifier. */
1392 if (rs6000_longcall_switch
)
1394 const char *base
= rs6000_longcall_switch
;
1395 while (base
[-1] != 'm') base
--;
1397 if (*rs6000_longcall_switch
!= '\0')
1398 error ("invalid option %qs", base
);
1399 rs6000_default_long_calls
= (base
[0] != 'n');
1402 /* Handle -m(no-)warn-altivec-long similarly. */
1403 if (rs6000_warn_altivec_long_switch
)
1405 const char *base
= rs6000_warn_altivec_long_switch
;
1406 while (base
[-1] != 'm') base
--;
1408 if (*rs6000_warn_altivec_long_switch
!= '\0')
1409 error ("invalid option %qs", base
);
1410 rs6000_warn_altivec_long
= (base
[0] != 'n');
1413 /* Handle -mprioritize-restricted-insns option. */
1414 rs6000_sched_restricted_insns_priority
1415 = (rs6000_sched_groups
? 1 : 0);
1416 if (rs6000_sched_restricted_insns_priority_str
)
1417 rs6000_sched_restricted_insns_priority
=
1418 atoi (rs6000_sched_restricted_insns_priority_str
);
1420 /* Handle -msched-costly-dep option. */
1421 rs6000_sched_costly_dep
1422 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1423 if (rs6000_sched_costly_dep_str
)
1425 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1426 rs6000_sched_costly_dep
= no_dep_costly
;
1427 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1428 rs6000_sched_costly_dep
= all_deps_costly
;
1429 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1430 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1431 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1432 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1434 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1437 /* Handle -minsert-sched-nops option. */
1438 rs6000_sched_insert_nops
1439 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1440 if (rs6000_sched_insert_nops_str
)
1442 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1443 rs6000_sched_insert_nops
= sched_finish_none
;
1444 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1445 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1446 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1447 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1449 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1452 #ifdef TARGET_REGNAMES
1453 /* If the user desires alternate register names, copy in the
1454 alternate names now. */
1455 if (TARGET_REGNAMES
)
1456 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1459 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1460 If -maix-struct-return or -msvr4-struct-return was explicitly
1461 used, don't override with the ABI default. */
1462 if ((target_flags_explicit
& MASK_AIX_STRUCT_RET
) == 0)
1464 if (DEFAULT_ABI
== ABI_V4
&& !DRAFT_V4_STRUCT_RET
)
1465 target_flags
= (target_flags
& ~MASK_AIX_STRUCT_RET
);
1467 target_flags
|= MASK_AIX_STRUCT_RET
;
1470 if (TARGET_LONG_DOUBLE_128
1471 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
))
1472 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1474 /* Allocate an alias set for register saves & restores from stack. */
1475 rs6000_sr_alias_set
= new_alias_set ();
1478 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1480 /* We can only guarantee the availability of DI pseudo-ops when
1481 assembling for 64-bit targets. */
1484 targetm
.asm_out
.aligned_op
.di
= NULL
;
1485 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1488 /* Set branch target alignment, if not optimizing for size. */
1491 if (rs6000_sched_groups
)
1493 if (align_functions
<= 0)
1494 align_functions
= 16;
1495 if (align_jumps
<= 0)
1497 if (align_loops
<= 0)
1500 if (align_jumps_max_skip
<= 0)
1501 align_jumps_max_skip
= 15;
1502 if (align_loops_max_skip
<= 0)
1503 align_loops_max_skip
= 15;
1506 /* Arrange to save and restore machine status around nested functions. */
1507 init_machine_status
= rs6000_init_machine_status
;
1509 /* We should always be splitting complex arguments, but we can't break
1510 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1511 if (DEFAULT_ABI
!= ABI_AIX
)
1512 targetm
.calls
.split_complex_arg
= NULL
;
1514 /* Initialize rs6000_cost with the appropriate target costs. */
1516 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1520 case PROCESSOR_RIOS1
:
1521 rs6000_cost
= &rios1_cost
;
1524 case PROCESSOR_RIOS2
:
1525 rs6000_cost
= &rios2_cost
;
1528 case PROCESSOR_RS64A
:
1529 rs6000_cost
= &rs64a_cost
;
1532 case PROCESSOR_MPCCORE
:
1533 rs6000_cost
= &mpccore_cost
;
1536 case PROCESSOR_PPC403
:
1537 rs6000_cost
= &ppc403_cost
;
1540 case PROCESSOR_PPC405
:
1541 rs6000_cost
= &ppc405_cost
;
1544 case PROCESSOR_PPC440
:
1545 rs6000_cost
= &ppc440_cost
;
1548 case PROCESSOR_PPC601
:
1549 rs6000_cost
= &ppc601_cost
;
1552 case PROCESSOR_PPC603
:
1553 rs6000_cost
= &ppc603_cost
;
1556 case PROCESSOR_PPC604
:
1557 rs6000_cost
= &ppc604_cost
;
1560 case PROCESSOR_PPC604e
:
1561 rs6000_cost
= &ppc604e_cost
;
1564 case PROCESSOR_PPC620
:
1565 rs6000_cost
= &ppc620_cost
;
1568 case PROCESSOR_PPC630
:
1569 rs6000_cost
= &ppc630_cost
;
1572 case PROCESSOR_PPC750
:
1573 case PROCESSOR_PPC7400
:
1574 rs6000_cost
= &ppc750_cost
;
1577 case PROCESSOR_PPC7450
:
1578 rs6000_cost
= &ppc7450_cost
;
1581 case PROCESSOR_PPC8540
:
1582 rs6000_cost
= &ppc8540_cost
;
1585 case PROCESSOR_POWER4
:
1586 case PROCESSOR_POWER5
:
1587 rs6000_cost
= &power4_cost
;
1595 /* Implement targetm.vectorize.builtin_mask_for_load. */
1597 rs6000_builtin_mask_for_load (void)
1600 return altivec_builtin_mask_for_load
;
1605 /* Handle generic options of the form -mfoo=yes/no.
1606 NAME is the option name.
1607 VALUE is the option value.
1608 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1609 whether the option value is 'yes' or 'no' respectively. */
1611 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
1615 else if (!strcmp (value
, "yes"))
1617 else if (!strcmp (value
, "no"))
1620 error ("unknown -m%s= option specified: '%s'", name
, value
);
1623 /* Handle -mabi= options. */
1625 rs6000_parse_abi_options (void)
1627 if (rs6000_abi_string
== 0)
1629 else if (! strcmp (rs6000_abi_string
, "altivec"))
1631 rs6000_altivec_abi
= 1;
1634 else if (! strcmp (rs6000_abi_string
, "no-altivec"))
1635 rs6000_altivec_abi
= 0;
1636 else if (! strcmp (rs6000_abi_string
, "spe"))
1639 rs6000_altivec_abi
= 0;
1640 if (!TARGET_SPE_ABI
)
1641 error ("not configured for ABI: '%s'", rs6000_abi_string
);
1644 /* These are here for testing during development only, do not
1645 document in the manual please. */
1646 else if (! strcmp (rs6000_abi_string
, "d64"))
1648 rs6000_darwin64_abi
= 1;
1649 warning ("Using darwin64 ABI");
1651 else if (! strcmp (rs6000_abi_string
, "d32"))
1653 rs6000_darwin64_abi
= 0;
1654 warning ("Using old darwin ABI");
1657 else if (! strcmp (rs6000_abi_string
, "no-spe"))
1660 error ("unknown ABI specified: '%s'", rs6000_abi_string
);
1663 /* Handle -mfloat-gprs= options. */
1665 rs6000_parse_float_gprs_option (void)
1667 if (rs6000_float_gprs_string
== 0)
1669 else if (! strcmp (rs6000_float_gprs_string
, "yes")
1670 || ! strcmp (rs6000_float_gprs_string
, "single"))
1671 rs6000_float_gprs
= 1;
1672 else if (! strcmp (rs6000_float_gprs_string
, "double"))
1673 rs6000_float_gprs
= 2;
1674 else if (! strcmp (rs6000_float_gprs_string
, "no"))
1675 rs6000_float_gprs
= 0;
1677 error ("invalid option for -mfloat-gprs");
1680 /* Handle -malign-XXXXXX options. */
1682 rs6000_parse_alignment_option (void)
1684 if (rs6000_alignment_string
== 0)
1686 else if (! strcmp (rs6000_alignment_string
, "power"))
1687 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
1688 else if (! strcmp (rs6000_alignment_string
, "natural"))
1689 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1691 error ("unknown -malign-XXXXX option specified: '%s'",
1692 rs6000_alignment_string
);
1695 /* Validate and record the size specified with the -mtls-size option. */
1698 rs6000_parse_tls_size_option (void)
1700 if (rs6000_tls_size_string
== 0)
1702 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
1703 rs6000_tls_size
= 16;
1704 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
1705 rs6000_tls_size
= 32;
1706 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
1707 rs6000_tls_size
= 64;
1709 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
1713 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1717 /* Do anything needed at the start of the asm file. */
1720 rs6000_file_start (void)
1724 const char *start
= buffer
;
1725 struct rs6000_cpu_select
*ptr
;
1726 const char *default_cpu
= TARGET_CPU_DEFAULT
;
1727 FILE *file
= asm_out_file
;
1729 default_file_start ();
1731 #ifdef TARGET_BI_ARCH
1732 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
1736 if (flag_verbose_asm
)
1738 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
1739 rs6000_select
[0].string
= default_cpu
;
1741 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1743 ptr
= &rs6000_select
[i
];
1744 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1746 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
1751 #ifdef USING_ELFOS_H
1752 switch (rs6000_sdata
)
1754 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
1755 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
1756 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
1757 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
1760 if (rs6000_sdata
&& g_switch_value
)
1762 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
1772 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
1780 /* Return nonzero if this function is known to have a null epilogue. */
1783 direct_return (void)
1785 if (reload_completed
)
1787 rs6000_stack_t
*info
= rs6000_stack_info ();
1789 if (info
->first_gp_reg_save
== 32
1790 && info
->first_fp_reg_save
== 64
1791 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
1792 && ! info
->lr_save_p
1793 && ! info
->cr_save_p
1794 && info
->vrsave_mask
== 0
1802 /* Returns 1 always. */
1805 any_operand (rtx op ATTRIBUTE_UNUSED
,
1806 enum machine_mode mode ATTRIBUTE_UNUSED
)
1811 /* Returns 1 always. */
1814 any_parallel_operand (rtx op ATTRIBUTE_UNUSED
,
1815 enum machine_mode mode ATTRIBUTE_UNUSED
)
1820 /* Returns 1 if op is the count register. */
1823 count_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1825 if (GET_CODE (op
) != REG
)
1828 if (REGNO (op
) == COUNT_REGISTER_REGNUM
)
1831 if (REGNO (op
) > FIRST_PSEUDO_REGISTER
)
1837 /* Returns 1 if op is an altivec register. */
1840 altivec_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1842 return (register_operand (op
, mode
)
1843 && (GET_CODE (op
) != REG
1844 || REGNO (op
) > FIRST_PSEUDO_REGISTER
1845 || ALTIVEC_REGNO_P (REGNO (op
))));
1849 xer_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1851 if (GET_CODE (op
) != REG
)
1854 if (XER_REGNO_P (REGNO (op
)))
1860 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1861 by such constants completes more quickly. */
1864 s8bit_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1866 return (GET_CODE (op
) == CONST_INT
1867 && (INTVAL (op
) >= -128 && INTVAL (op
) <= 127));
1870 /* Return 1 if OP is a constant that can fit in a D field. */
1873 short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1875 return (GET_CODE (op
) == CONST_INT
1876 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I'));
1879 /* Similar for an unsigned D field. */
1882 u_short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1884 return (GET_CODE (op
) == CONST_INT
1885 && CONST_OK_FOR_LETTER_P (INTVAL (op
) & GET_MODE_MASK (mode
), 'K'));
1888 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1891 non_short_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1893 return (GET_CODE (op
) == CONST_INT
1894 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x8000) >= 0x10000);
1897 /* Returns 1 if OP is a CONST_INT that is a positive value
1898 and an exact power of 2. */
1901 exact_log2_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1903 return (GET_CODE (op
) == CONST_INT
1905 && exact_log2 (INTVAL (op
)) >= 0);
1908 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1912 gpc_reg_operand (rtx op
, enum machine_mode mode
)
1914 return (register_operand (op
, mode
)
1915 && (GET_CODE (op
) != REG
1916 || (REGNO (op
) >= ARG_POINTER_REGNUM
1917 && !XER_REGNO_P (REGNO (op
)))
1918 || REGNO (op
) < MQ_REGNO
));
1921 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1925 cc_reg_operand (rtx op
, enum machine_mode mode
)
1927 return (register_operand (op
, mode
)
1928 && (GET_CODE (op
) != REG
1929 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
1930 || CR_REGNO_P (REGNO (op
))));
1933 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1934 CR field that isn't CR0. */
1937 cc_reg_not_cr0_operand (rtx op
, enum machine_mode mode
)
1939 return (register_operand (op
, mode
)
1940 && (GET_CODE (op
) != REG
1941 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
1942 || CR_REGNO_NOT_CR0_P (REGNO (op
))));
1945 /* Returns 1 if OP is either a constant integer valid for a D-field or
1946 a non-special register. If a register, it must be in the proper
1947 mode unless MODE is VOIDmode. */
1950 reg_or_short_operand (rtx op
, enum machine_mode mode
)
1952 return short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
1955 /* Similar, except check if the negation of the constant would be
1956 valid for a D-field. Don't allow a constant zero, since all the
1957 patterns that call this predicate use "addic r1,r2,-constant" on
1958 a constant value to set a carry when r2 is greater or equal to
1959 "constant". That doesn't work for zero. */
1962 reg_or_neg_short_operand (rtx op
, enum machine_mode mode
)
1964 if (GET_CODE (op
) == CONST_INT
)
1965 return CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P') && INTVAL (op
) != 0;
1967 return gpc_reg_operand (op
, mode
);
1970 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1971 a non-special register. If a register, it must be in the proper
1972 mode unless MODE is VOIDmode. */
1975 reg_or_aligned_short_operand (rtx op
, enum machine_mode mode
)
1977 if (gpc_reg_operand (op
, mode
))
1979 else if (short_cint_operand (op
, mode
) && !(INTVAL (op
) & 3))
1986 /* Return 1 if the operand is either a register or an integer whose
1987 high-order 16 bits are zero. */
1990 reg_or_u_short_operand (rtx op
, enum machine_mode mode
)
1992 return u_short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
1995 /* Return 1 is the operand is either a non-special register or ANY
1996 constant integer. */
1999 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
2001 return (GET_CODE (op
) == CONST_INT
|| gpc_reg_operand (op
, mode
));
2004 /* Return 1 is the operand is either a non-special register or ANY
2005 32-bit signed constant integer. */
2008 reg_or_arith_cint_operand (rtx op
, enum machine_mode mode
)
2010 return (gpc_reg_operand (op
, mode
)
2011 || (GET_CODE (op
) == CONST_INT
2012 #if HOST_BITS_PER_WIDE_INT != 32
2013 && ((unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x80000000)
2014 < (unsigned HOST_WIDE_INT
) 0x100000000ll
)
2019 /* Return 1 is the operand is either a non-special register or a 32-bit
2020 signed constant integer valid for 64-bit addition. */
2023 reg_or_add_cint64_operand (rtx op
, enum machine_mode mode
)
2025 return (gpc_reg_operand (op
, mode
)
2026 || (GET_CODE (op
) == CONST_INT
2027 #if HOST_BITS_PER_WIDE_INT == 32
2028 && INTVAL (op
) < 0x7fff8000
2030 && ((unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x80008000)
2036 /* Return 1 is the operand is either a non-special register or a 32-bit
2037 signed constant integer valid for 64-bit subtraction. */
2040 reg_or_sub_cint64_operand (rtx op
, enum machine_mode mode
)
2042 return (gpc_reg_operand (op
, mode
)
2043 || (GET_CODE (op
) == CONST_INT
2044 #if HOST_BITS_PER_WIDE_INT == 32
2045 && (- INTVAL (op
)) < 0x7fff8000
2047 && ((unsigned HOST_WIDE_INT
) ((- INTVAL (op
)) + 0x80008000)
2053 /* Return 1 is the operand is either a non-special register or ANY
2054 32-bit unsigned constant integer. */
2057 reg_or_logical_cint_operand (rtx op
, enum machine_mode mode
)
2059 if (GET_CODE (op
) == CONST_INT
)
2061 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
2063 if (GET_MODE_BITSIZE (mode
) <= 32)
2066 if (INTVAL (op
) < 0)
2070 return ((INTVAL (op
) & GET_MODE_MASK (mode
)
2071 & (~ (unsigned HOST_WIDE_INT
) 0xffffffff)) == 0);
2073 else if (GET_CODE (op
) == CONST_DOUBLE
)
2075 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2079 return CONST_DOUBLE_HIGH (op
) == 0;
2082 return gpc_reg_operand (op
, mode
);
2085 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2088 got_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2090 return (GET_CODE (op
) == SYMBOL_REF
2091 || GET_CODE (op
) == CONST
2092 || GET_CODE (op
) == LABEL_REF
);
2095 /* Return 1 if the operand is a simple references that can be loaded via
2096 the GOT (labels involving addition aren't allowed). */
2099 got_no_const_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2101 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
);
2104 /* Return the number of instructions it takes to form a constant in an
2105 integer register. */
2108 num_insns_constant_wide (HOST_WIDE_INT value
)
2110 /* signed constant loadable with {cal|addi} */
2111 if (CONST_OK_FOR_LETTER_P (value
, 'I'))
2114 /* constant loadable with {cau|addis} */
2115 else if (CONST_OK_FOR_LETTER_P (value
, 'L'))
2118 #if HOST_BITS_PER_WIDE_INT == 64
2119 else if (TARGET_POWERPC64
)
2121 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2122 HOST_WIDE_INT high
= value
>> 31;
2124 if (high
== 0 || high
== -1)
2130 return num_insns_constant_wide (high
) + 1;
2132 return (num_insns_constant_wide (high
)
2133 + num_insns_constant_wide (low
) + 1);
2142 num_insns_constant (rtx op
, enum machine_mode mode
)
2144 if (GET_CODE (op
) == CONST_INT
)
2146 #if HOST_BITS_PER_WIDE_INT == 64
2147 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2148 && mask64_operand (op
, mode
))
2152 return num_insns_constant_wide (INTVAL (op
));
2155 else if (GET_CODE (op
) == CONST_DOUBLE
&& mode
== SFmode
)
2160 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2161 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2162 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2165 else if (GET_CODE (op
) == CONST_DOUBLE
)
2171 int endian
= (WORDS_BIG_ENDIAN
== 0);
2173 if (mode
== VOIDmode
|| mode
== DImode
)
2175 high
= CONST_DOUBLE_HIGH (op
);
2176 low
= CONST_DOUBLE_LOW (op
);
2180 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2181 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2183 low
= l
[1 - endian
];
2187 return (num_insns_constant_wide (low
)
2188 + num_insns_constant_wide (high
));
2192 if (high
== 0 && low
>= 0)
2193 return num_insns_constant_wide (low
);
2195 else if (high
== -1 && low
< 0)
2196 return num_insns_constant_wide (low
);
2198 else if (mask64_operand (op
, mode
))
2202 return num_insns_constant_wide (high
) + 1;
2205 return (num_insns_constant_wide (high
)
2206 + num_insns_constant_wide (low
) + 1);
2214 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2215 register with one instruction per word. We only do this if we can
2216 safely read CONST_DOUBLE_{LOW,HIGH}. */
2219 easy_fp_constant (rtx op
, enum machine_mode mode
)
2221 if (GET_CODE (op
) != CONST_DOUBLE
2222 || GET_MODE (op
) != mode
2223 || (GET_MODE_CLASS (mode
) != MODE_FLOAT
&& mode
!= DImode
))
2226 /* Consider all constants with -msoft-float to be easy. */
2227 if ((TARGET_SOFT_FLOAT
|| TARGET_E500_SINGLE
)
2231 /* If we are using V.4 style PIC, consider all constants to be hard. */
2232 if (flag_pic
&& DEFAULT_ABI
== ABI_V4
)
2235 #ifdef TARGET_RELOCATABLE
2236 /* Similarly if we are using -mrelocatable, consider all constants
2238 if (TARGET_RELOCATABLE
)
2247 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2248 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
2250 return (num_insns_constant_wide ((HOST_WIDE_INT
) k
[0]) == 1
2251 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[1]) == 1
2252 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[2]) == 1
2253 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[3]) == 1);
2256 else if (mode
== DFmode
)
2261 if (TARGET_E500_DOUBLE
)
2264 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2265 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
2267 return (num_insns_constant_wide ((HOST_WIDE_INT
) k
[0]) == 1
2268 && num_insns_constant_wide ((HOST_WIDE_INT
) k
[1]) == 1);
2271 else if (mode
== SFmode
)
2276 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2277 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2279 return num_insns_constant_wide (l
) == 1;
2282 else if (mode
== DImode
)
2283 return ((TARGET_POWERPC64
2284 && GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_LOW (op
) == 0)
2285 || (num_insns_constant (op
, DImode
) <= 2));
2287 else if (mode
== SImode
)
2293 /* Returns the constant for the splat instruction, if exists. */
2296 easy_vector_splat_const (int cst
, enum machine_mode mode
)
2301 if (EASY_VECTOR_15 (cst
)
2302 || EASY_VECTOR_15_ADD_SELF (cst
))
2304 if ((cst
& 0xffff) != ((cst
>> 16) & 0xffff))
2310 if (EASY_VECTOR_15 (cst
)
2311 || EASY_VECTOR_15_ADD_SELF (cst
))
2313 if ((cst
& 0xff) != ((cst
>> 8) & 0xff))
2319 if (EASY_VECTOR_15 (cst
)
2320 || EASY_VECTOR_15_ADD_SELF (cst
))
2329 /* Return nonzero if all elements of a vector have the same value. */
2332 easy_vector_same (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2336 units
= CONST_VECTOR_NUNITS (op
);
2338 cst
= INTVAL (CONST_VECTOR_ELT (op
, 0));
2339 for (i
= 1; i
< units
; ++i
)
2340 if (INTVAL (CONST_VECTOR_ELT (op
, i
)) != cst
)
2342 if (i
== units
&& easy_vector_splat_const (cst
, mode
))
2347 /* Return 1 if the operand is a CONST_INT and can be put into a
2348 register without using memory. */
2351 easy_vector_constant (rtx op
, enum machine_mode mode
)
2355 if (GET_CODE (op
) != CONST_VECTOR
2360 if (zero_constant (op
, mode
)
2361 && ((TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
2362 || (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))))
2365 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2368 if (TARGET_SPE
&& mode
== V1DImode
)
2371 cst
= INTVAL (CONST_VECTOR_ELT (op
, 0));
2372 cst2
= INTVAL (CONST_VECTOR_ELT (op
, 1));
2374 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2376 evmergelo r0, r0, r0
2379 I don't know how efficient it would be to allow bigger constants,
2380 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2381 instructions is better than a 64-bit memory load, but I don't
2382 have the e500 timing specs. */
2383 if (TARGET_SPE
&& mode
== V2SImode
2384 && cst
>= -0x7fff && cst
<= 0x7fff
2385 && cst2
>= -0x7fff && cst2
<= 0x7fff)
2389 && easy_vector_same (op
, mode
))
2391 cst
= easy_vector_splat_const (cst
, mode
);
2392 if (EASY_VECTOR_15_ADD_SELF (cst
)
2393 || EASY_VECTOR_15 (cst
))
2399 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2402 easy_vector_constant_add_self (rtx op
, enum machine_mode mode
)
2406 && GET_CODE (op
) == CONST_VECTOR
2407 && easy_vector_same (op
, mode
))
2409 cst
= easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op
, 0)), mode
);
2410 if (EASY_VECTOR_15_ADD_SELF (cst
))
2416 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2419 gen_easy_vector_constant_add_self (rtx op
)
2423 units
= GET_MODE_NUNITS (GET_MODE (op
));
2424 v
= rtvec_alloc (units
);
2426 for (i
= 0; i
< units
; i
++)
2428 GEN_INT (INTVAL (CONST_VECTOR_ELT (op
, i
)) >> 1);
2429 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op
), v
);
2433 output_vec_const_move (rtx
*operands
)
2436 enum machine_mode mode
;
2442 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2443 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2444 mode
= GET_MODE (dest
);
2448 if (zero_constant (vec
, mode
))
2449 return "vxor %0,%0,%0";
2450 else if (easy_vector_constant (vec
, mode
))
2452 operands
[1] = GEN_INT (cst
);
2456 if (EASY_VECTOR_15 (cst
))
2458 operands
[1] = GEN_INT (cst
);
2459 return "vspltisw %0,%1";
2461 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2467 if (EASY_VECTOR_15 (cst
))
2469 operands
[1] = GEN_INT (cst
);
2470 return "vspltish %0,%1";
2472 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2478 if (EASY_VECTOR_15 (cst
))
2480 operands
[1] = GEN_INT (cst
);
2481 return "vspltisb %0,%1";
2483 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2496 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2497 pattern of V1DI, V4HI, and V2SF.
2499 FIXME: We should probably return # and add post reload
2500 splitters for these, but this way is so easy ;-). */
2501 operands
[1] = GEN_INT (cst
);
2502 operands
[2] = GEN_INT (cst2
);
2504 return "li %0,%1\n\tevmergelo %0,%0,%0";
2506 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2512 /* Return 1 if the operand is the constant 0. This works for scalars
2513 as well as vectors. */
2515 zero_constant (rtx op
, enum machine_mode mode
)
2517 return op
== CONST0_RTX (mode
);
2520 /* Return 1 if the operand is 0.0. */
2522 zero_fp_constant (rtx op
, enum machine_mode mode
)
2524 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
2527 /* Return 1 if the operand is in volatile memory. Note that during
2528 the RTL generation phase, memory_operand does not return TRUE for
2529 volatile memory references. So this function allows us to
2530 recognize volatile references where its safe. */
2533 volatile_mem_operand (rtx op
, enum machine_mode mode
)
2535 if (GET_CODE (op
) != MEM
)
2538 if (!MEM_VOLATILE_P (op
))
2541 if (mode
!= GET_MODE (op
))
2544 if (reload_completed
)
2545 return memory_operand (op
, mode
);
2547 if (reload_in_progress
)
2548 return strict_memory_address_p (mode
, XEXP (op
, 0));
2550 return memory_address_p (mode
, XEXP (op
, 0));
2553 /* Return 1 if the operand is an offsettable memory operand. */
2556 offsettable_mem_operand (rtx op
, enum machine_mode mode
)
2558 return ((GET_CODE (op
) == MEM
)
2559 && offsettable_address_p (reload_completed
|| reload_in_progress
,
2560 mode
, XEXP (op
, 0)));
2563 /* Return 1 if the operand is either an easy FP constant (see above) or
2567 mem_or_easy_const_operand (rtx op
, enum machine_mode mode
)
2569 return memory_operand (op
, mode
) || easy_fp_constant (op
, mode
);
2572 /* Return 1 if the operand is either a non-special register or an item
2573 that can be used as the operand of a `mode' add insn. */
2576 add_operand (rtx op
, enum machine_mode mode
)
2578 if (GET_CODE (op
) == CONST_INT
)
2579 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
2580 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
2582 return gpc_reg_operand (op
, mode
);
2585 /* Return 1 if OP is a constant but not a valid add_operand. */
2588 non_add_cint_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2590 return (GET_CODE (op
) == CONST_INT
2591 && !CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
2592 && !CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
2595 /* Return 1 if the operand is a non-special register or a constant that
2596 can be used as the operand of an OR or XOR insn on the RS/6000. */
2599 logical_operand (rtx op
, enum machine_mode mode
)
2601 HOST_WIDE_INT opl
, oph
;
2603 if (gpc_reg_operand (op
, mode
))
2606 if (GET_CODE (op
) == CONST_INT
)
2608 opl
= INTVAL (op
) & GET_MODE_MASK (mode
);
2610 #if HOST_BITS_PER_WIDE_INT <= 32
2611 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
&& opl
< 0)
2615 else if (GET_CODE (op
) == CONST_DOUBLE
)
2617 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
2620 opl
= CONST_DOUBLE_LOW (op
);
2621 oph
= CONST_DOUBLE_HIGH (op
);
2628 return ((opl
& ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0
2629 || (opl
& ~ (unsigned HOST_WIDE_INT
) 0xffff0000) == 0);
2632 /* Return 1 if C is a constant that is not a logical operand (as
2633 above), but could be split into one. */
2636 non_logical_cint_operand (rtx op
, enum machine_mode mode
)
2638 return ((GET_CODE (op
) == CONST_INT
|| GET_CODE (op
) == CONST_DOUBLE
)
2639 && ! logical_operand (op
, mode
)
2640 && reg_or_logical_cint_operand (op
, mode
));
2643 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2644 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2645 Reject all ones and all zeros, since these should have been optimized
2646 away and confuse the making of MB and ME. */
2649 mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2651 HOST_WIDE_INT c
, lsb
;
2653 if (GET_CODE (op
) != CONST_INT
)
2658 /* Fail in 64-bit mode if the mask wraps around because the upper
2659 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2660 if (TARGET_POWERPC64
&& (c
& 0x80000001) == 0x80000001)
2663 /* We don't change the number of transitions by inverting,
2664 so make sure we start with the LS bit zero. */
2668 /* Reject all zeros or all ones. */
2672 /* Find the first transition. */
2675 /* Invert to look for a second transition. */
2678 /* Erase first transition. */
2681 /* Find the second transition (if any). */
2684 /* Match if all the bits above are 1's (or c is zero). */
2688 /* Return 1 for the PowerPC64 rlwinm corner case. */
2691 mask_operand_wrap (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2693 HOST_WIDE_INT c
, lsb
;
2695 if (GET_CODE (op
) != CONST_INT
)
2700 if ((c
& 0x80000001) != 0x80000001)
2714 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2715 It is if there are no more than one 1->0 or 0->1 transitions.
2716 Reject all zeros, since zero should have been optimized away and
2717 confuses the making of MB and ME. */
2720 mask64_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2722 if (GET_CODE (op
) == CONST_INT
)
2724 HOST_WIDE_INT c
, lsb
;
2728 /* Reject all zeros. */
2732 /* We don't change the number of transitions by inverting,
2733 so make sure we start with the LS bit zero. */
2737 /* Find the transition, and check that all bits above are 1's. */
2740 /* Match if all the bits above are 1's (or c is zero). */
2747 mask64_1or2_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2750 if (GET_CODE (op
) == CONST_INT
)
2752 HOST_WIDE_INT c
, lsb
;
2757 /* Disallow all zeros. */
2761 /* We can use a single rlwinm insn if no upper bits of C are set
2762 AND there are zero, one or two transitions in the _whole_ of
2764 one_ok
= !(c
& ~(HOST_WIDE_INT
)0xffffffff);
2766 /* We don't change the number of transitions by inverting,
2767 so make sure we start with the LS bit zero. */
2771 /* Find the first transition. */
2774 /* Invert to look for a second transition. */
2777 /* Erase first transition. */
2780 /* Find the second transition. */
2783 /* Invert to look for a third transition. */
2786 /* Erase second transition. */
2789 if (one_ok
&& !(allow_one
|| c
))
2792 /* Find the third transition (if any). */
2795 /* Match if all the bits above are 1's (or c is zero). */
2801 /* Like mask64_operand, but allow up to three transitions. This
2802 predicate is used by insn patterns that generate two rldicl or
2803 rldicr machine insns. */
2804 int mask64_2_operand (rtx op
, enum machine_mode mode
)
2806 return mask64_1or2_operand (op
, mode
, false);
2809 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2810 implement ANDing by the mask IN. */
2812 build_mask64_2_operands (rtx in
, rtx
*out
)
2814 #if HOST_BITS_PER_WIDE_INT >= 64
2815 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
2818 if (GET_CODE (in
) != CONST_INT
)
2824 /* Assume c initially something like 0x00fff000000fffff. The idea
2825 is to rotate the word so that the middle ^^^^^^ group of zeros
2826 is at the MS end and can be cleared with an rldicl mask. We then
2827 rotate back and clear off the MS ^^ group of zeros with a
2829 c
= ~c
; /* c == 0xff000ffffff00000 */
2830 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
2831 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
2832 c
= ~c
; /* c == 0x00fff000000fffff */
2833 c
&= -lsb
; /* c == 0x00fff00000000000 */
2834 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2835 c
= ~c
; /* c == 0xff000fffffffffff */
2836 c
&= -lsb
; /* c == 0xff00000000000000 */
2838 while ((lsb
>>= 1) != 0)
2839 shift
++; /* shift == 44 on exit from loop */
2840 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
2841 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
2842 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
2846 /* Assume c initially something like 0xff000f0000000000. The idea
2847 is to rotate the word so that the ^^^ middle group of zeros
2848 is at the LS end and can be cleared with an rldicr mask. We then
2849 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2851 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
2852 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
2853 c
= ~c
; /* c == 0x00fff0ffffffffff */
2854 c
&= -lsb
; /* c == 0x00fff00000000000 */
2855 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2856 c
= ~c
; /* c == 0xff000fffffffffff */
2857 c
&= -lsb
; /* c == 0xff00000000000000 */
2859 while ((lsb
>>= 1) != 0)
2860 shift
++; /* shift == 44 on exit from loop */
2861 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
2862 m1
>>= shift
; /* m1 == 0x0000000000000fff */
2863 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
2866 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2867 masks will be all 1's. We are guaranteed more than one transition. */
2868 out
[0] = GEN_INT (64 - shift
);
2869 out
[1] = GEN_INT (m1
);
2870 out
[2] = GEN_INT (shift
);
2871 out
[3] = GEN_INT (m2
);
2879 /* Return 1 if the operand is either a non-special register or a constant
2880 that can be used as the operand of a PowerPC64 logical AND insn. */
2883 and64_operand (rtx op
, enum machine_mode mode
)
2885 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2886 return (gpc_reg_operand (op
, mode
) || mask64_operand (op
, mode
));
2888 return (logical_operand (op
, mode
) || mask64_operand (op
, mode
));
2891 /* Like the above, but also match constants that can be implemented
2892 with two rldicl or rldicr insns. */
2895 and64_2_operand (rtx op
, enum machine_mode mode
)
2897 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2898 return gpc_reg_operand (op
, mode
) || mask64_1or2_operand (op
, mode
, true);
2900 return logical_operand (op
, mode
) || mask64_1or2_operand (op
, mode
, true);
2903 /* Return 1 if the operand is either a non-special register or a
2904 constant that can be used as the operand of an RS/6000 logical AND insn. */
2907 and_operand (rtx op
, enum machine_mode mode
)
2909 if (fixed_regs
[CR0_REGNO
]) /* CR0 not available, don't do andi./andis. */
2910 return (gpc_reg_operand (op
, mode
) || mask_operand (op
, mode
));
2912 return (logical_operand (op
, mode
) || mask_operand (op
, mode
));
2915 /* Return 1 if the operand is a general register or memory operand. */
2918 reg_or_mem_operand (rtx op
, enum machine_mode mode
)
2920 return (gpc_reg_operand (op
, mode
)
2921 || memory_operand (op
, mode
)
2922 || macho_lo_sum_memory_operand (op
, mode
)
2923 || volatile_mem_operand (op
, mode
));
2926 /* Return 1 if the operand is a general register or memory operand without
2927 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2931 lwa_operand (rtx op
, enum machine_mode mode
)
2935 if (reload_completed
&& GET_CODE (inner
) == SUBREG
)
2936 inner
= SUBREG_REG (inner
);
2938 return gpc_reg_operand (inner
, mode
)
2939 || (memory_operand (inner
, mode
)
2940 && GET_CODE (XEXP (inner
, 0)) != PRE_INC
2941 && GET_CODE (XEXP (inner
, 0)) != PRE_DEC
2942 && (GET_CODE (XEXP (inner
, 0)) != PLUS
2943 || GET_CODE (XEXP (XEXP (inner
, 0), 1)) != CONST_INT
2944 || INTVAL (XEXP (XEXP (inner
, 0), 1)) % 4 == 0));
2947 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2950 symbol_ref_operand (rtx op
, enum machine_mode mode
)
2952 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
2955 return (GET_CODE (op
) == SYMBOL_REF
2956 && (DEFAULT_ABI
!= ABI_AIX
|| SYMBOL_REF_FUNCTION_P (op
)));
2959 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2960 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2963 call_operand (rtx op
, enum machine_mode mode
)
2965 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
2968 return (GET_CODE (op
) == SYMBOL_REF
2969 || (GET_CODE (op
) == REG
2970 && (REGNO (op
) == LINK_REGISTER_REGNUM
2971 || REGNO (op
) == COUNT_REGISTER_REGNUM
2972 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
2975 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2979 current_file_function_operand (rtx op
,
2980 enum machine_mode mode ATTRIBUTE_UNUSED
)
2982 return (GET_CODE (op
) == SYMBOL_REF
2983 && (DEFAULT_ABI
!= ABI_AIX
|| SYMBOL_REF_FUNCTION_P (op
))
2984 && (SYMBOL_REF_LOCAL_P (op
)
2985 || (DECL_RTL_SET_P (current_function_decl
)
2986 && op
== XEXP (DECL_RTL (current_function_decl
), 0))));
2989 /* Return 1 if this operand is a valid input for a move insn. */
2992 input_operand (rtx op
, enum machine_mode mode
)
2994 /* Memory is always valid. */
2995 if (memory_operand (op
, mode
))
2998 /* For floating-point, easy constants are valid. */
2999 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3001 && easy_fp_constant (op
, mode
))
3004 /* Allow any integer constant. */
3005 if (GET_MODE_CLASS (mode
) == MODE_INT
3006 && (GET_CODE (op
) == CONST_INT
3007 || GET_CODE (op
) == CONST_DOUBLE
))
3010 /* Allow easy vector constants. */
3011 if (GET_CODE (op
) == CONST_VECTOR
3012 && easy_vector_constant (op
, mode
))
3015 /* For floating-point or multi-word mode, the only remaining valid type
3017 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3018 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3019 return register_operand (op
, mode
);
3021 /* The only cases left are integral modes one word or smaller (we
3022 do not get called for MODE_CC values). These can be in any
3024 if (register_operand (op
, mode
))
3027 /* A SYMBOL_REF referring to the TOC is valid. */
3028 if (legitimate_constant_pool_address_p (op
))
3031 /* A constant pool expression (relative to the TOC) is valid */
3032 if (toc_relative_expr_p (op
))
3035 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
3037 if (DEFAULT_ABI
== ABI_V4
3038 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
)
3039 && small_data_operand (op
, Pmode
))
3045 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3047 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
3049 /* Reject (subreg:SI (reg:DF)). */
3050 if (GET_CODE (op
) == SUBREG
3052 && REG_P (SUBREG_REG (op
))
3053 && GET_MODE (SUBREG_REG (op
)) == DFmode
)
3056 /* Reject (subreg:DF (reg:DI)). */
3057 if (GET_CODE (op
) == SUBREG
3059 && REG_P (SUBREG_REG (op
))
3060 && GET_MODE (SUBREG_REG (op
)) == DImode
)
3066 /* Just like nonimmediate_operand, but return 0 for invalid SUBREG's
3069 rs6000_nonimmediate_operand (rtx op
, enum machine_mode mode
)
3071 if (TARGET_E500_DOUBLE
3072 && GET_CODE (op
) == SUBREG
3073 && invalid_e500_subreg (op
, mode
))
3076 return nonimmediate_operand (op
, mode
);
3079 /* Darwin, AIX increases natural record alignment to doubleword if the first
3080 field is an FP double while the FP fields remain word aligned. */
3083 rs6000_special_round_type_align (tree type
, int computed
, int specified
)
3085 tree field
= TYPE_FIELDS (type
);
3087 /* Skip all non field decls */
3088 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3089 field
= TREE_CHAIN (field
);
3091 if (field
== NULL
|| field
== type
|| DECL_MODE (field
) != DFmode
)
3092 return MAX (computed
, specified
);
3094 return MAX (MAX (computed
, specified
), 64);
3097 /* Return 1 for an operand in small memory on V.4/eabi. */
3100 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
3101 enum machine_mode mode ATTRIBUTE_UNUSED
)
3106 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
3109 if (DEFAULT_ABI
!= ABI_V4
)
3112 if (GET_CODE (op
) == SYMBOL_REF
)
3115 else if (GET_CODE (op
) != CONST
3116 || GET_CODE (XEXP (op
, 0)) != PLUS
3117 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
3118 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
3123 rtx sum
= XEXP (op
, 0);
3124 HOST_WIDE_INT summand
;
3126 /* We have to be careful here, because it is the referenced address
3127 that must be 32k from _SDA_BASE_, not just the symbol. */
3128 summand
= INTVAL (XEXP (sum
, 1));
3129 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
3132 sym_ref
= XEXP (sum
, 0);
3135 return SYMBOL_REF_SMALL_P (sym_ref
);
3141 /* Return true, if operand is a memory operand and has a
3142 displacement divisible by 4. */
3145 word_offset_memref_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3150 if (!memory_operand (op
, mode
))
3153 addr
= XEXP (op
, 0);
3154 if (GET_CODE (addr
) == PLUS
3155 && GET_CODE (XEXP (addr
, 0)) == REG
3156 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3157 off
= INTVAL (XEXP (addr
, 1));
3159 return (off
% 4) == 0;
3162 /* Return true if either operand is a general purpose register. */
3165 gpr_or_gpr_p (rtx op0
, rtx op1
)
3167 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3168 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3172 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3175 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
3177 switch (GET_CODE(op
))
3180 if (RS6000_SYMBOL_REF_TLS_P (op
))
3182 else if (CONSTANT_POOL_ADDRESS_P (op
))
3184 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
3192 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
3201 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
3202 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
3204 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
3213 constant_pool_expr_p (rtx op
)
3217 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
3221 toc_relative_expr_p (rtx op
)
3225 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
3229 legitimate_constant_pool_address_p (rtx x
)
3232 && GET_CODE (x
) == PLUS
3233 && GET_CODE (XEXP (x
, 0)) == REG
3234 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3235 && constant_pool_expr_p (XEXP (x
, 1)));
3239 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3241 return (DEFAULT_ABI
== ABI_V4
3242 && !flag_pic
&& !TARGET_TOC
3243 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3244 && small_data_operand (x
, mode
));
3247 /* SPE offset addressing is limited to 5-bits worth of double words. */
3248 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3251 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3253 unsigned HOST_WIDE_INT offset
, extra
;
3255 if (GET_CODE (x
) != PLUS
)
3257 if (GET_CODE (XEXP (x
, 0)) != REG
)
3259 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3261 if (legitimate_constant_pool_address_p (x
))
3263 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3266 offset
= INTVAL (XEXP (x
, 1));
3274 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3275 which leaves the only valid constant offset of zero, which by
3276 canonicalization rules is also invalid. */
3283 /* SPE vector modes. */
3284 return SPE_CONST_OFFSET_OK (offset
);
3287 if (TARGET_E500_DOUBLE
)
3288 return SPE_CONST_OFFSET_OK (offset
);
3291 /* On e500v2, we may have:
3293 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3295 Which gets addressed with evldd instructions. */
3296 if (TARGET_E500_DOUBLE
)
3297 return SPE_CONST_OFFSET_OK (offset
);
3299 if (mode
== DFmode
|| !TARGET_POWERPC64
)
3301 else if (offset
& 3)
3307 if (mode
== TFmode
|| !TARGET_POWERPC64
)
3309 else if (offset
& 3)
3320 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3324 legitimate_indexed_address_p (rtx x
, int strict
)
3328 if (GET_CODE (x
) != PLUS
)
3334 if (!REG_P (op0
) || !REG_P (op1
))
3337 return ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3338 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3339 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3340 && INT_REG_OK_FOR_INDEX_P (op0
, strict
)));
3344 legitimate_indirect_address_p (rtx x
, int strict
)
3346 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3350 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3352 if (!TARGET_MACHO
|| !flag_pic
3353 || mode
!= SImode
|| GET_CODE(x
) != MEM
)
3357 if (GET_CODE (x
) != LO_SUM
)
3359 if (GET_CODE (XEXP (x
, 0)) != REG
)
3361 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3365 return CONSTANT_P (x
);
3369 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3371 if (GET_CODE (x
) != LO_SUM
)
3373 if (GET_CODE (XEXP (x
, 0)) != REG
)
3375 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3377 /* Restrict addressing for DI because of our SUBREG hackery. */
3378 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
3382 if (TARGET_ELF
|| TARGET_MACHO
)
3384 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3388 if (GET_MODE_NUNITS (mode
) != 1)
3390 if (GET_MODE_BITSIZE (mode
) > 64
3391 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
3392 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
&& mode
== DFmode
)))
3395 return CONSTANT_P (x
);
3402 /* Try machine-dependent ways of modifying an illegitimate address
3403 to be legitimate. If we find one, return the new, valid address.
3404 This is used from only one place: `memory_address' in explow.c.
3406 OLDX is the address as it was before break_out_memory_refs was
3407 called. In some cases it is useful to look at this to decide what
3410 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3412 It is always safe for this function to do nothing. It exists to
3413 recognize opportunities to optimize the output.
3415 On RS/6000, first check for the sum of a register with a constant
3416 integer that is out of range. If so, generate code to add the
3417 constant with the low-order 16 bits masked to the register and force
3418 this result into another register (this can be done with `cau').
3419 Then generate an address of REG+(CONST&0xffff), allowing for the
3420 possibility of bit 16 being a one.
3422 Then check for the sum of a register and something not constant, try to
3423 load the other things into a register and return the sum. */
3426 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3427 enum machine_mode mode
)
3429 if (GET_CODE (x
) == SYMBOL_REF
)
3431 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3433 return rs6000_legitimize_tls_address (x
, model
);
3436 if (GET_CODE (x
) == PLUS
3437 && GET_CODE (XEXP (x
, 0)) == REG
3438 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3439 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000)
3441 HOST_WIDE_INT high_int
, low_int
;
3443 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3444 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3445 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3446 GEN_INT (high_int
)), 0);
3447 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3449 else if (GET_CODE (x
) == PLUS
3450 && GET_CODE (XEXP (x
, 0)) == REG
3451 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3452 && GET_MODE_NUNITS (mode
) == 1
3453 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3455 || (((mode
!= DImode
&& mode
!= DFmode
) || TARGET_E500_DOUBLE
)
3457 && (TARGET_POWERPC64
|| mode
!= DImode
)
3460 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3461 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3463 else if (ALTIVEC_VECTOR_MODE (mode
))
3467 /* Make sure both operands are registers. */
3468 if (GET_CODE (x
) == PLUS
)
3469 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3470 force_reg (Pmode
, XEXP (x
, 1)));
3472 reg
= force_reg (Pmode
, x
);
3475 else if (SPE_VECTOR_MODE (mode
)
3476 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
3477 || mode
== DImode
)))
3481 /* We accept [reg + reg] and [reg + OFFSET]. */
3483 if (GET_CODE (x
) == PLUS
)
3485 rtx op1
= XEXP (x
, 0);
3486 rtx op2
= XEXP (x
, 1);
3488 op1
= force_reg (Pmode
, op1
);
3490 if (GET_CODE (op2
) != REG
3491 && (GET_CODE (op2
) != CONST_INT
3492 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))))
3493 op2
= force_reg (Pmode
, op2
);
3495 return gen_rtx_PLUS (Pmode
, op1
, op2
);
3498 return force_reg (Pmode
, x
);
3504 && GET_CODE (x
) != CONST_INT
3505 && GET_CODE (x
) != CONST_DOUBLE
3507 && GET_MODE_NUNITS (mode
) == 1
3508 && (GET_MODE_BITSIZE (mode
) <= 32
3509 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) && mode
== DFmode
)))
3511 rtx reg
= gen_reg_rtx (Pmode
);
3512 emit_insn (gen_elf_high (reg
, x
));
3513 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3515 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3518 && ! MACHO_DYNAMIC_NO_PIC_P
3520 && GET_CODE (x
) != CONST_INT
3521 && GET_CODE (x
) != CONST_DOUBLE
3523 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) || mode
!= DFmode
)
3527 rtx reg
= gen_reg_rtx (Pmode
);
3528 emit_insn (gen_macho_high (reg
, x
));
3529 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3532 && constant_pool_expr_p (x
)
3533 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3535 return create_TOC_reference (x
);
3541 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3542 We need to emit DTP-relative relocations. */
3545 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3550 fputs ("\t.long\t", file
);
3553 fputs (DOUBLE_INT_ASM_OP
, file
);
3558 output_addr_const (file
, x
);
3559 fputs ("@dtprel+0x8000", file
);
3562 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3564 static GTY(()) rtx rs6000_tls_symbol
;
3566 rs6000_tls_get_addr (void)
3568 if (!rs6000_tls_symbol
)
3569 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3571 return rs6000_tls_symbol
;
3574 /* Construct the SYMBOL_REF for TLS GOT references. */
3576 static GTY(()) rtx rs6000_got_symbol
;
3578 rs6000_got_sym (void)
3580 if (!rs6000_got_symbol
)
3582 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3583 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3584 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3587 return rs6000_got_symbol
;
3590 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3591 this (thread-local) address. */
3594 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3598 dest
= gen_reg_rtx (Pmode
);
3599 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3605 tlsreg
= gen_rtx_REG (Pmode
, 13);
3606 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3610 tlsreg
= gen_rtx_REG (Pmode
, 2);
3611 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3615 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3619 tmp
= gen_reg_rtx (Pmode
);
3622 tlsreg
= gen_rtx_REG (Pmode
, 13);
3623 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3627 tlsreg
= gen_rtx_REG (Pmode
, 2);
3628 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3632 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3634 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3639 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3642 got
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
3646 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3649 rtx gsym
= rs6000_got_sym ();
3650 got
= gen_reg_rtx (Pmode
);
3652 rs6000_emit_move (got
, gsym
, Pmode
);
3656 static int tls_got_labelno
= 0;
3657 rtx tempLR
, lab
, tmp3
, mem
;
3660 ASM_GENERATE_INTERNAL_LABEL (buf
, "LTLS", tls_got_labelno
++);
3661 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
3662 tempLR
= gen_reg_rtx (Pmode
);
3663 tmp1
= gen_reg_rtx (Pmode
);
3664 tmp2
= gen_reg_rtx (Pmode
);
3665 tmp3
= gen_reg_rtx (Pmode
);
3666 mem
= gen_const_mem (Pmode
, tmp1
);
3668 first
= emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, lab
,
3670 emit_move_insn (tmp1
, tempLR
);
3671 emit_move_insn (tmp2
, mem
);
3672 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3673 last
= emit_move_insn (got
, tmp3
);
3674 REG_NOTES (last
) = gen_rtx_EXPR_LIST (REG_EQUAL
, gsym
,
3676 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
3678 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
,
3684 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3686 r3
= gen_rtx_REG (Pmode
, 3);
3688 insn
= gen_tls_gd_64 (r3
, got
, addr
);
3690 insn
= gen_tls_gd_32 (r3
, got
, addr
);
3693 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3694 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3695 insn
= emit_call_insn (insn
);
3696 CONST_OR_PURE_CALL_P (insn
) = 1;
3697 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3698 insn
= get_insns ();
3700 emit_libcall_block (insn
, dest
, r3
, addr
);
3702 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3704 r3
= gen_rtx_REG (Pmode
, 3);
3706 insn
= gen_tls_ld_64 (r3
, got
);
3708 insn
= gen_tls_ld_32 (r3
, got
);
3711 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3712 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3713 insn
= emit_call_insn (insn
);
3714 CONST_OR_PURE_CALL_P (insn
) = 1;
3715 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3716 insn
= get_insns ();
3718 tmp1
= gen_reg_rtx (Pmode
);
3719 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3721 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
3722 if (rs6000_tls_size
== 16)
3725 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
3727 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
3729 else if (rs6000_tls_size
== 32)
3731 tmp2
= gen_reg_rtx (Pmode
);
3733 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
3735 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
3738 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
3740 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
3744 tmp2
= gen_reg_rtx (Pmode
);
3746 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
3748 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
3750 insn
= gen_rtx_SET (Pmode
, dest
,
3751 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
3757 /* IE, or 64 bit offset LE. */
3758 tmp2
= gen_reg_rtx (Pmode
);
3760 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
3762 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
3765 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
3767 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
3775 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3776 instruction definitions. */
3779 rs6000_tls_symbol_ref (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3781 return RS6000_SYMBOL_REF_TLS_P (x
);
3784 /* Return 1 if X contains a thread-local symbol. */
3787 rs6000_tls_referenced_p (rtx x
)
3789 if (! TARGET_HAVE_TLS
)
3792 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
3795 /* Return 1 if *X is a thread-local symbol. This is the same as
3796 rs6000_tls_symbol_ref except for the type of the unused argument. */
3799 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
3801 return RS6000_SYMBOL_REF_TLS_P (*x
);
3804 /* The convention appears to be to define this wherever it is used.
3805 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3806 is now used here. */
3807 #ifndef REG_MODE_OK_FOR_BASE_P
3808 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3811 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3812 replace the input X, or the original X if no replacement is called for.
3813 The output parameter *WIN is 1 if the calling macro should goto WIN,
3816 For RS/6000, we wish to handle large displacements off a base
3817 register by splitting the addend across an addiu/addis and the mem insn.
3818 This cuts number of extra insns needed from 3 to 1.
3820 On Darwin, we use this to generate code for floating point constants.
3821 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3822 The Darwin code is inside #if TARGET_MACHO because only then is
3823 machopic_function_base_name() defined. */
3825 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3826 int opnum
, int type
,
3827 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3829 /* We must recognize output that we have already generated ourselves. */
3830 if (GET_CODE (x
) == PLUS
3831 && GET_CODE (XEXP (x
, 0)) == PLUS
3832 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3833 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3834 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3836 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3837 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3838 opnum
, (enum reload_type
)type
);
3844 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
3845 && GET_CODE (x
) == LO_SUM
3846 && GET_CODE (XEXP (x
, 0)) == PLUS
3847 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
3848 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
3849 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
3850 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
3851 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
3852 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
3853 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
3855 /* Result of previous invocation of this function on Darwin
3856 floating point constant. */
3857 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3858 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3859 opnum
, (enum reload_type
)type
);
3865 /* Force ld/std non-word aligned offset into base register by wrapping
3867 if (GET_CODE (x
) == PLUS
3868 && GET_CODE (XEXP (x
, 0)) == REG
3869 && REGNO (XEXP (x
, 0)) < 32
3870 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3871 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3872 && (INTVAL (XEXP (x
, 1)) & 3) != 0
3873 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
3874 && TARGET_POWERPC64
)
3876 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
3877 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3878 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3879 opnum
, (enum reload_type
) type
);
3884 if (GET_CODE (x
) == PLUS
3885 && GET_CODE (XEXP (x
, 0)) == REG
3886 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
3887 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3888 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3889 && !SPE_VECTOR_MODE (mode
)
3890 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
3892 && !ALTIVEC_VECTOR_MODE (mode
))
3894 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
3895 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
3897 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3899 /* Check for 32-bit overflow. */
3900 if (high
+ low
!= val
)
3906 /* Reload the high part into a base reg; leave the low part
3907 in the mem directly. */
3909 x
= gen_rtx_PLUS (GET_MODE (x
),
3910 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
3914 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3915 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3916 opnum
, (enum reload_type
)type
);
3922 if (GET_CODE (x
) == SYMBOL_REF
3923 && DEFAULT_ABI
== ABI_DARWIN
3924 && !ALTIVEC_VECTOR_MODE (mode
)
3925 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
3926 /* Don't do this for TFmode, since the result isn't offsettable.
3927 The same goes for DImode without 64-bit gprs. */
3929 && (mode
!= DImode
|| TARGET_POWERPC64
))
3933 rtx offset
= gen_rtx_CONST (Pmode
,
3934 gen_rtx_MINUS (Pmode
, x
,
3935 machopic_function_base_sym ()));
3936 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3937 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3938 gen_rtx_HIGH (Pmode
, offset
)), offset
);
3941 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3942 gen_rtx_HIGH (Pmode
, x
), x
);
3944 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3945 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3946 opnum
, (enum reload_type
)type
);
3953 && constant_pool_expr_p (x
)
3954 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
3956 (x
) = create_TOC_reference (x
);
3964 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3965 that is a valid memory address for an instruction.
3966 The MODE argument is the machine mode for the MEM expression
3967 that wants to use this address.
3969 On the RS/6000, there are four valid address: a SYMBOL_REF that
3970 refers to a constant pool entry of an address (or the sum of it
3971 plus a constant), a short (16-bit signed) constant plus a register,
3972 the sum of two registers, or a register indirect, possibly with an
3973 auto-increment. For DFmode and DImode with a constant plus register,
3974 we must ensure that both words are addressable or PowerPC64 with offset
3977 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3978 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3979 adjacent memory cells are accessed by adding word-sized offsets
3980 during assembly output. */
3982 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
3984 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3986 && ALTIVEC_VECTOR_MODE (mode
)
3987 && GET_CODE (x
) == AND
3988 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3989 && INTVAL (XEXP (x
, 1)) == -16)
3992 if (RS6000_SYMBOL_REF_TLS_P (x
))
3994 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
3996 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
3997 && !ALTIVEC_VECTOR_MODE (mode
)
3998 && !SPE_VECTOR_MODE (mode
)
3999 /* Restrict addressing for DI because of our SUBREG hackery. */
4000 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
4002 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
4004 if (legitimate_small_data_p (mode
, x
))
4006 if (legitimate_constant_pool_address_p (x
))
4008 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4010 && GET_CODE (x
) == PLUS
4011 && GET_CODE (XEXP (x
, 0)) == REG
4012 && (XEXP (x
, 0) == virtual_stack_vars_rtx
4013 || XEXP (x
, 0) == arg_pointer_rtx
)
4014 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4016 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
4020 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4022 || ((mode
!= DFmode
|| TARGET_E500_DOUBLE
) && mode
!= TFmode
))
4023 && (TARGET_POWERPC64
|| mode
!= DImode
)
4024 && legitimate_indexed_address_p (x
, reg_ok_strict
))
4026 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
4031 /* Go to LABEL if ADDR (a legitimate address expression)
4032 has an effect that depends on the machine mode it is used for.
4034 On the RS/6000 this is true of all integral offsets (since AltiVec
4035 modes don't allow them) or is a pre-increment or decrement.
4037 ??? Except that due to conceptual problems in offsettable_address_p
4038 we can't really report the problems of integral offsets. So leave
4039 this assuming that the adjustable offset must be valid for the
4040 sub-words of a TFmode operand, which is what we had before. */
4043 rs6000_mode_dependent_address (rtx addr
)
4045 switch (GET_CODE (addr
))
4048 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4050 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
4051 return val
+ 12 + 0x8000 >= 0x10000;
4060 return TARGET_UPDATE
;
4069 /* Return number of consecutive hard regs needed starting at reg REGNO
4070 to hold something of mode MODE.
4071 This is ordinarily the length in words of a value of mode MODE
4072 but can be less for certain modes in special long registers.
4074 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4075 scalar instructions. The upper 32 bits are only available to the
4078 POWER and PowerPC GPRs hold 32 bits worth;
4079 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4082 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
4084 if (FP_REGNO_P (regno
))
4085 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4087 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
4090 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
4091 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
4093 if (ALTIVEC_REGNO_P (regno
))
4095 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
4097 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4100 /* Change register usage conditional on target flags. */
4102 rs6000_conditional_register_usage (void)
4106 /* Set MQ register fixed (already call_used) if not POWER
4107 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4112 /* 64-bit AIX reserves GPR13 for thread-private data. */
4114 fixed_regs
[13] = call_used_regs
[13]
4115 = call_really_used_regs
[13] = 1;
4117 /* Conditionally disable FPRs. */
4118 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
4119 for (i
= 32; i
< 64; i
++)
4120 fixed_regs
[i
] = call_used_regs
[i
]
4121 = call_really_used_regs
[i
] = 1;
4123 if (DEFAULT_ABI
== ABI_V4
4124 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4126 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4128 if (DEFAULT_ABI
== ABI_V4
4129 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4131 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4132 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4133 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4135 if (DEFAULT_ABI
== ABI_DARWIN
4136 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
4137 global_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4138 = fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4139 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4140 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4142 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
4143 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4144 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4147 global_regs
[VSCR_REGNO
] = 1;
4151 global_regs
[SPEFSCR_REGNO
] = 1;
4152 fixed_regs
[FIXED_SCRATCH
]
4153 = call_used_regs
[FIXED_SCRATCH
]
4154 = call_really_used_regs
[FIXED_SCRATCH
] = 1;
4157 if (! TARGET_ALTIVEC
)
4159 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
4160 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4161 call_really_used_regs
[VRSAVE_REGNO
] = 1;
4164 if (TARGET_ALTIVEC_ABI
)
4165 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
4166 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4169 /* Try to output insns to set TARGET equal to the constant C if it can
4170 be done in less than N insns. Do all computations in MODE.
4171 Returns the place where the output has been placed if it can be
4172 done and the insns have been emitted. If it would take more than N
4173 insns, zero is returned and no insns and emitted. */
4176 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
4177 rtx source
, int n ATTRIBUTE_UNUSED
)
4179 rtx result
, insn
, set
;
4180 HOST_WIDE_INT c0
, c1
;
4182 if (mode
== QImode
|| mode
== HImode
)
4185 dest
= gen_reg_rtx (mode
);
4186 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
4189 else if (mode
== SImode
)
4191 result
= no_new_pseudos
? dest
: gen_reg_rtx (SImode
);
4193 emit_insn (gen_rtx_SET (VOIDmode
, result
,
4194 GEN_INT (INTVAL (source
)
4195 & (~ (HOST_WIDE_INT
) 0xffff))));
4196 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
4197 gen_rtx_IOR (SImode
, result
,
4198 GEN_INT (INTVAL (source
) & 0xffff))));
4201 else if (mode
== DImode
)
4203 if (GET_CODE (source
) == CONST_INT
)
4205 c0
= INTVAL (source
);
4208 else if (GET_CODE (source
) == CONST_DOUBLE
)
4210 #if HOST_BITS_PER_WIDE_INT >= 64
4211 c0
= CONST_DOUBLE_LOW (source
);
4214 c0
= CONST_DOUBLE_LOW (source
);
4215 c1
= CONST_DOUBLE_HIGH (source
);
4221 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4226 insn
= get_last_insn ();
4227 set
= single_set (insn
);
4228 if (! CONSTANT_P (SET_SRC (set
)))
4229 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4234 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4235 fall back to a straight forward decomposition. We do this to avoid
4236 exponential run times encountered when looking for longer sequences
4237 with rs6000_emit_set_const. */
4239 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4241 if (!TARGET_POWERPC64
)
4243 rtx operand1
, operand2
;
4245 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4247 operand2
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
4249 emit_move_insn (operand1
, GEN_INT (c1
));
4250 emit_move_insn (operand2
, GEN_INT (c2
));
4254 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4257 ud2
= (c1
& 0xffff0000) >> 16;
4258 #if HOST_BITS_PER_WIDE_INT >= 64
4262 ud4
= (c2
& 0xffff0000) >> 16;
4264 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4265 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4268 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4270 emit_move_insn (dest
, GEN_INT (ud1
));
4273 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4274 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4277 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4280 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4282 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4284 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4285 || (ud4
== 0 && ! (ud3
& 0x8000)))
4288 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4291 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4294 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud2
)));
4295 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (16)));
4297 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4302 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4305 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4308 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud3
)));
4310 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (32)));
4312 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
,
4313 GEN_INT (ud2
<< 16)));
4315 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
4321 /* Helper for the following. Get rid of [r+r] memory refs
4322 in cases where it won't work (TImode, TFmode). */
4325 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4327 if (GET_CODE (operands
[0]) == MEM
4328 && GET_CODE (XEXP (operands
[0], 0)) != REG
4329 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
4330 && ! reload_in_progress
)
4332 = replace_equiv_address (operands
[0],
4333 copy_addr_to_reg (XEXP (operands
[0], 0)));
4335 if (GET_CODE (operands
[1]) == MEM
4336 && GET_CODE (XEXP (operands
[1], 0)) != REG
4337 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
4338 && ! reload_in_progress
)
4340 = replace_equiv_address (operands
[1],
4341 copy_addr_to_reg (XEXP (operands
[1], 0)));
4344 /* Emit a move from SOURCE to DEST in mode MODE. */
4346 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4350 operands
[1] = source
;
4352 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4353 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4354 && ! FLOAT_MODE_P (mode
)
4355 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4357 /* FIXME. This should never happen. */
4358 /* Since it seems that it does, do the safe thing and convert
4360 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4362 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4363 && ! FLOAT_MODE_P (mode
)
4364 && ((CONST_DOUBLE_HIGH (operands
[1]) == 0
4365 && CONST_DOUBLE_LOW (operands
[1]) >= 0)
4366 || (CONST_DOUBLE_HIGH (operands
[1]) == -1
4367 && CONST_DOUBLE_LOW (operands
[1]) < 0)))
4370 /* Check if GCC is setting up a block move that will end up using FP
4371 registers as temporaries. We must make sure this is acceptable. */
4372 if (GET_CODE (operands
[0]) == MEM
4373 && GET_CODE (operands
[1]) == MEM
4375 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4376 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4377 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4378 ? 32 : MEM_ALIGN (operands
[0])))
4379 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4381 : MEM_ALIGN (operands
[1]))))
4382 && ! MEM_VOLATILE_P (operands
[0])
4383 && ! MEM_VOLATILE_P (operands
[1]))
4385 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4386 adjust_address (operands
[1], SImode
, 0));
4387 emit_move_insn (adjust_address (operands
[0], SImode
, 4),
4388 adjust_address (operands
[1], SImode
, 4));
4392 if (!no_new_pseudos
&& GET_CODE (operands
[0]) == MEM
4393 && !gpc_reg_operand (operands
[1], mode
))
4394 operands
[1] = force_reg (mode
, operands
[1]);
4396 if (mode
== SFmode
&& ! TARGET_POWERPC
4397 && TARGET_HARD_FLOAT
&& TARGET_FPRS
4398 && GET_CODE (operands
[0]) == MEM
)
4402 if (reload_in_progress
|| reload_completed
)
4403 regnum
= true_regnum (operands
[1]);
4404 else if (GET_CODE (operands
[1]) == REG
)
4405 regnum
= REGNO (operands
[1]);
4409 /* If operands[1] is a register, on POWER it may have
4410 double-precision data in it, so truncate it to single
4412 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4415 newreg
= (no_new_pseudos
? operands
[1] : gen_reg_rtx (mode
));
4416 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4417 operands
[1] = newreg
;
4421 /* Recognize the case where operand[1] is a reference to thread-local
4422 data and load its address to a register. */
4423 if (GET_CODE (operands
[1]) == SYMBOL_REF
)
4425 enum tls_model model
= SYMBOL_REF_TLS_MODEL (operands
[1]);
4427 operands
[1] = rs6000_legitimize_tls_address (operands
[1], model
);
4430 /* Handle the case where reload calls us with an invalid address. */
4431 if (reload_in_progress
&& mode
== Pmode
4432 && (! general_operand (operands
[1], mode
)
4433 || ! nonimmediate_operand (operands
[0], mode
)))
4436 /* 128-bit constant floating-point values on Darwin should really be
4437 loaded as two parts. */
4438 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
4439 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
4440 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
4442 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4443 know how to get a DFmode SUBREG of a TFmode. */
4444 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
, 0),
4445 simplify_gen_subreg (DImode
, operands
[1], mode
, 0),
4447 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
,
4448 GET_MODE_SIZE (DImode
)),
4449 simplify_gen_subreg (DImode
, operands
[1], mode
,
4450 GET_MODE_SIZE (DImode
)),
4455 /* FIXME: In the long term, this switch statement should go away
4456 and be replaced by a sequence of tests based on things like
4462 if (CONSTANT_P (operands
[1])
4463 && GET_CODE (operands
[1]) != CONST_INT
)
4464 operands
[1] = force_const_mem (mode
, operands
[1]);
4468 rs6000_eliminate_indexed_memrefs (operands
);
4473 if (CONSTANT_P (operands
[1])
4474 && ! easy_fp_constant (operands
[1], mode
))
4475 operands
[1] = force_const_mem (mode
, operands
[1]);
4486 if (CONSTANT_P (operands
[1])
4487 && !easy_vector_constant (operands
[1], mode
))
4488 operands
[1] = force_const_mem (mode
, operands
[1]);
4493 /* Use default pattern for address of ELF small data */
4496 && DEFAULT_ABI
== ABI_V4
4497 && (GET_CODE (operands
[1]) == SYMBOL_REF
4498 || GET_CODE (operands
[1]) == CONST
)
4499 && small_data_operand (operands
[1], mode
))
4501 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4505 if (DEFAULT_ABI
== ABI_V4
4506 && mode
== Pmode
&& mode
== SImode
4507 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4509 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4513 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4517 && CONSTANT_P (operands
[1])
4518 && GET_CODE (operands
[1]) != HIGH
4519 && GET_CODE (operands
[1]) != CONST_INT
)
4521 rtx target
= (no_new_pseudos
? operands
[0] : gen_reg_rtx (mode
));
4523 /* If this is a function address on -mcall-aixdesc,
4524 convert it to the address of the descriptor. */
4525 if (DEFAULT_ABI
== ABI_AIX
4526 && GET_CODE (operands
[1]) == SYMBOL_REF
4527 && XSTR (operands
[1], 0)[0] == '.')
4529 const char *name
= XSTR (operands
[1], 0);
4531 while (*name
== '.')
4533 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4534 CONSTANT_POOL_ADDRESS_P (new_ref
)
4535 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
4536 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
4537 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
4538 SYMBOL_REF_DECL (new_ref
) = SYMBOL_REF_DECL (operands
[1]);
4539 operands
[1] = new_ref
;
4542 if (DEFAULT_ABI
== ABI_DARWIN
)
4545 if (MACHO_DYNAMIC_NO_PIC_P
)
4547 /* Take care of any required data indirection. */
4548 operands
[1] = rs6000_machopic_legitimize_pic_address (
4549 operands
[1], mode
, operands
[0]);
4550 if (operands
[0] != operands
[1])
4551 emit_insn (gen_rtx_SET (VOIDmode
,
4552 operands
[0], operands
[1]));
4556 emit_insn (gen_macho_high (target
, operands
[1]));
4557 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
4561 emit_insn (gen_elf_high (target
, operands
[1]));
4562 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
4566 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4567 and we have put it in the TOC, we just need to make a TOC-relative
4570 && GET_CODE (operands
[1]) == SYMBOL_REF
4571 && constant_pool_expr_p (operands
[1])
4572 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
4573 get_pool_mode (operands
[1])))
4575 operands
[1] = create_TOC_reference (operands
[1]);
4577 else if (mode
== Pmode
4578 && CONSTANT_P (operands
[1])
4579 && ((GET_CODE (operands
[1]) != CONST_INT
4580 && ! easy_fp_constant (operands
[1], mode
))
4581 || (GET_CODE (operands
[1]) == CONST_INT
4582 && num_insns_constant (operands
[1], mode
) > 2)
4583 || (GET_CODE (operands
[0]) == REG
4584 && FP_REGNO_P (REGNO (operands
[0]))))
4585 && GET_CODE (operands
[1]) != HIGH
4586 && ! legitimate_constant_pool_address_p (operands
[1])
4587 && ! toc_relative_expr_p (operands
[1]))
4589 /* Emit a USE operation so that the constant isn't deleted if
4590 expensive optimizations are turned on because nobody
4591 references it. This should only be done for operands that
4592 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4593 This should not be done for operands that contain LABEL_REFs.
4594 For now, we just handle the obvious case. */
4595 if (GET_CODE (operands
[1]) != LABEL_REF
)
4596 emit_insn (gen_rtx_USE (VOIDmode
, operands
[1]));
4599 /* Darwin uses a special PIC legitimizer. */
4600 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
4603 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
4605 if (operands
[0] != operands
[1])
4606 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4611 /* If we are to limit the number of things we put in the TOC and
4612 this is a symbol plus a constant we can add in one insn,
4613 just put the symbol in the TOC and add the constant. Don't do
4614 this if reload is in progress. */
4615 if (GET_CODE (operands
[1]) == CONST
4616 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
4617 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
4618 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
4619 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
4620 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
4621 && ! side_effects_p (operands
[0]))
4624 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
4625 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
4627 sym
= force_reg (mode
, sym
);
4629 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
4631 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
4635 operands
[1] = force_const_mem (mode
, operands
[1]);
4638 && constant_pool_expr_p (XEXP (operands
[1], 0))
4639 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4640 get_pool_constant (XEXP (operands
[1], 0)),
4641 get_pool_mode (XEXP (operands
[1], 0))))
4644 = gen_const_mem (mode
,
4645 create_TOC_reference (XEXP (operands
[1], 0)));
4646 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
4652 rs6000_eliminate_indexed_memrefs (operands
);
4656 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4658 gen_rtx_SET (VOIDmode
,
4659 operands
[0], operands
[1]),
4660 gen_rtx_CLOBBER (VOIDmode
,
4661 gen_rtx_SCRATCH (SImode
)))));
4670 /* Above, we may have called force_const_mem which may have returned
4671 an invalid address. If we can, fix this up; otherwise, reload will
4672 have to deal with it. */
4673 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
4674 operands
[1] = validize_mem (operands
[1]);
4677 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4680 /* Nonzero if we can use a floating-point register to pass this arg. */
4681 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4682 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4683 && (CUM)->fregno <= FP_ARG_MAX_REG \
4684 && TARGET_HARD_FLOAT && TARGET_FPRS)
4686 /* Nonzero if we can use an AltiVec register to pass this arg. */
4687 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4688 (ALTIVEC_VECTOR_MODE (MODE) \
4689 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4690 && TARGET_ALTIVEC_ABI \
4693 /* Return a nonzero value to say to return the function value in
4694 memory, just as large structures are always returned. TYPE will be
4695 the data type of the value, and FNTYPE will be the type of the
4696 function doing the returning, or @code{NULL} for libcalls.
4698 The AIX ABI for the RS/6000 specifies that all structures are
4699 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4700 specifies that structures <= 8 bytes are returned in r3/r4, but a
4701 draft put them in memory, and GCC used to implement the draft
4702 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4703 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4704 compatibility can change DRAFT_V4_STRUCT_RET to override the
4705 default, and -m switches get the final word. See
4706 rs6000_override_options for more details.
4708 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4709 long double support is enabled. These values are returned in memory.
4711 int_size_in_bytes returns -1 for variable size objects, which go in
4712 memory always. The cast to unsigned makes -1 > 8. */
4715 rs6000_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
4717 /* In the darwin64 abi, try to use registers for larger structs
4719 if (AGGREGATE_TYPE_P (type
)
4720 && rs6000_darwin64_abi
4721 && TREE_CODE (type
) == RECORD_TYPE
4722 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 32)
4723 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 0))
4726 if (AGGREGATE_TYPE_P (type
)
4727 && (TARGET_AIX_STRUCT_RET
4728 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
4731 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4732 modes only exist for GCC vector types if -maltivec. */
4733 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
4734 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
4737 /* Return synthetic vectors in memory. */
4738 if (TREE_CODE (type
) == VECTOR_TYPE
4739 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
4741 static bool warned_for_return_big_vectors
= false;
4742 if (!warned_for_return_big_vectors
)
4744 warning ("GCC vector returned by reference: "
4745 "non-standard ABI extension with no compatibility guarantee");
4746 warned_for_return_big_vectors
= true;
4751 if (DEFAULT_ABI
== ABI_V4
&& TYPE_MODE (type
) == TFmode
)
4757 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4758 for a call to a function whose data type is FNTYPE.
4759 For a library call, FNTYPE is 0.
4761 For incoming args we set the number of arguments in the prototype large
4762 so we never return a PARALLEL. */
4765 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
4766 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
4767 int libcall
, int n_named_args
)
4769 static CUMULATIVE_ARGS zero_cumulative
;
4771 *cum
= zero_cumulative
;
4773 cum
->fregno
= FP_ARG_MIN_REG
;
4774 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
4775 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4776 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
4777 ? CALL_LIBCALL
: CALL_NORMAL
);
4778 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
4779 cum
->stdarg
= fntype
4780 && (TYPE_ARG_TYPES (fntype
) != 0
4781 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4782 != void_type_node
));
4784 cum
->nargs_prototype
= 0;
4785 if (incoming
|| cum
->prototype
)
4786 cum
->nargs_prototype
= n_named_args
;
4788 /* Check for a longcall attribute. */
4789 if ((!fntype
&& rs6000_default_long_calls
)
4791 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
4792 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
4793 cum
->call_cookie
|= CALL_LONG
;
4795 if (TARGET_DEBUG_ARG
)
4797 fprintf (stderr
, "\ninit_cumulative_args:");
4800 tree ret_type
= TREE_TYPE (fntype
);
4801 fprintf (stderr
, " ret code = %s,",
4802 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
4805 if (cum
->call_cookie
& CALL_LONG
)
4806 fprintf (stderr
, " longcall,");
4808 fprintf (stderr
, " proto = %d, nargs = %d\n",
4809 cum
->prototype
, cum
->nargs_prototype
);
4814 && TARGET_ALTIVEC_ABI
4815 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
4817 error ("Cannot return value in vector register because"
4818 " altivec instructions are disabled, use -maltivec"
4819 " to enable them.");
4823 /* Return true if TYPE must be passed on the stack and not in registers. */
4826 rs6000_must_pass_in_stack (enum machine_mode mode
, tree type
)
4828 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
4829 return must_pass_in_stack_var_size (mode
, type
);
4831 return must_pass_in_stack_var_size_or_pad (mode
, type
);
4834 /* If defined, a C expression which determines whether, and in which
4835 direction, to pad out an argument with extra space. The value
4836 should be of type `enum direction': either `upward' to pad above
4837 the argument, `downward' to pad below, or `none' to inhibit
4840 For the AIX ABI structs are always stored left shifted in their
4844 function_arg_padding (enum machine_mode mode
, tree type
)
4846 #ifndef AGGREGATE_PADDING_FIXED
4847 #define AGGREGATE_PADDING_FIXED 0
4849 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4850 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4853 if (!AGGREGATE_PADDING_FIXED
)
4855 /* GCC used to pass structures of the same size as integer types as
4856 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4857 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4858 passed padded downward, except that -mstrict-align further
4859 muddied the water in that multi-component structures of 2 and 4
4860 bytes in size were passed padded upward.
4862 The following arranges for best compatibility with previous
4863 versions of gcc, but removes the -mstrict-align dependency. */
4864 if (BYTES_BIG_ENDIAN
)
4866 HOST_WIDE_INT size
= 0;
4868 if (mode
== BLKmode
)
4870 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4871 size
= int_size_in_bytes (type
);
4874 size
= GET_MODE_SIZE (mode
);
4876 if (size
== 1 || size
== 2 || size
== 4)
4882 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
4884 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
4888 /* Fall back to the default. */
4889 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
4892 /* If defined, a C expression that gives the alignment boundary, in bits,
4893 of an argument with the specified mode and type. If it is not defined,
4894 PARM_BOUNDARY is used for all arguments.
4896 V.4 wants long longs to be double word aligned.
4897 Doubleword align SPE vectors.
4898 Quadword align Altivec vectors.
4899 Quadword align large synthetic vector types. */
4902 function_arg_boundary (enum machine_mode mode
, tree type
)
4904 if (DEFAULT_ABI
== ABI_V4
&& GET_MODE_SIZE (mode
) == 8)
4906 else if (SPE_VECTOR_MODE (mode
)
4907 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4908 && int_size_in_bytes (type
) >= 8
4909 && int_size_in_bytes (type
) < 16))
4911 else if (ALTIVEC_VECTOR_MODE (mode
)
4912 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4913 && int_size_in_bytes (type
) >= 16))
4916 return PARM_BOUNDARY
;
4919 /* Compute the size (in words) of a function argument. */
4921 static unsigned long
4922 rs6000_arg_size (enum machine_mode mode
, tree type
)
4926 if (mode
!= BLKmode
)
4927 size
= GET_MODE_SIZE (mode
);
4929 size
= int_size_in_bytes (type
);
4932 return (size
+ 3) >> 2;
4934 return (size
+ 7) >> 3;
4937 /* The darwin64 ABI calls for us to recurse down through structs,
4938 applying the same rules to struct elements as if a reference to
4939 each were being passed directly. */
4942 darwin64_function_arg_advance (CUMULATIVE_ARGS
*cum
, tree type
,
4943 int named
, int depth
)
4948 switch (TREE_CODE (type
))
4951 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
4952 if (TREE_CODE (f
) == FIELD_DECL
)
4954 ftype
= TREE_TYPE (f
);
4955 function_arg_advance (cum
, TYPE_MODE (ftype
), ftype
,
4961 tot
= int_size_in_bytes (type
);
4964 ftype
= TREE_TYPE (type
);
4965 tot
/= int_size_in_bytes (ftype
);
4967 for (i
= 0; i
< tot
; ++i
)
4969 function_arg_advance (cum
, TYPE_MODE (ftype
), ftype
,
4979 /* Update the data in CUM to advance over an argument
4980 of mode MODE and data type TYPE.
4981 (TYPE is null for libcalls where that information may not be available.)
4983 Note that for args passed by reference, function_arg will be called
4984 with MODE and TYPE set to that of the pointer to the arg, not the arg
4988 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4989 tree type
, int named
, int depth
)
4991 /* Only tick off an argument if we're not recursing. */
4993 cum
->nargs_prototype
--;
4995 if (TARGET_ALTIVEC_ABI
4996 && (ALTIVEC_VECTOR_MODE (mode
)
4997 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4998 && int_size_in_bytes (type
) == 16)))
5002 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5005 if (!TARGET_ALTIVEC
)
5006 error ("Cannot pass argument in vector register because"
5007 " altivec instructions are disabled, use -maltivec"
5008 " to enable them.");
5010 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5011 even if it is going to be passed in a vector register.
5012 Darwin does the same for variable-argument functions. */
5013 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5014 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
5024 /* Vector parameters must be 16-byte aligned. This places
5025 them at 2 mod 4 in terms of words in 32-bit mode, since
5026 the parameter save area starts at offset 24 from the
5027 stack. In 64-bit mode, they just have to start on an
5028 even word, since the parameter save area is 16-byte
5029 aligned. Space for GPRs is reserved even if the argument
5030 will be passed in memory. */
5032 align
= (2 - cum
->words
) & 3;
5034 align
= cum
->words
& 1;
5035 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
5037 if (TARGET_DEBUG_ARG
)
5039 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
5041 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
5042 cum
->nargs_prototype
, cum
->prototype
,
5043 GET_MODE_NAME (mode
));
5047 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
5049 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
5052 else if (rs6000_darwin64_abi
5054 && (TREE_CODE (type
) == RECORD_TYPE
5055 || TREE_CODE (type
) == ARRAY_TYPE
))
5056 darwin64_function_arg_advance (cum
, type
, named
, depth
);
5058 else if (DEFAULT_ABI
== ABI_V4
)
5060 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5061 && (mode
== SFmode
|| mode
== DFmode
))
5063 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
5068 cum
->words
+= cum
->words
& 1;
5069 cum
->words
+= rs6000_arg_size (mode
, type
);
5074 int n_words
= rs6000_arg_size (mode
, type
);
5075 int gregno
= cum
->sysv_gregno
;
5077 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5078 (r7,r8) or (r9,r10). As does any other 2 word item such
5079 as complex int due to a historical mistake. */
5081 gregno
+= (1 - gregno
) & 1;
5083 /* Multi-reg args are not split between registers and stack. */
5084 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5086 /* Long long and SPE vectors are aligned on the stack.
5087 So are other 2 word items such as complex int due to
5088 a historical mistake. */
5090 cum
->words
+= cum
->words
& 1;
5091 cum
->words
+= n_words
;
5094 /* Note: continuing to accumulate gregno past when we've started
5095 spilling to the stack indicates the fact that we've started
5096 spilling to the stack to expand_builtin_saveregs. */
5097 cum
->sysv_gregno
= gregno
+ n_words
;
5100 if (TARGET_DEBUG_ARG
)
5102 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5103 cum
->words
, cum
->fregno
);
5104 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
5105 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
5106 fprintf (stderr
, "mode = %4s, named = %d\n",
5107 GET_MODE_NAME (mode
), named
);
5112 int n_words
= rs6000_arg_size (mode
, type
);
5113 int align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5115 /* The simple alignment calculation here works because
5116 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
5117 If we ever want to handle alignments larger than 8 bytes for
5118 32-bit or 16 bytes for 64-bit, then we'll need to take into
5119 account the offset to the start of the parm save area. */
5120 align
&= cum
->words
;
5121 cum
->words
+= align
+ n_words
;
5123 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5124 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5125 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5127 if (TARGET_DEBUG_ARG
)
5129 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5130 cum
->words
, cum
->fregno
);
5131 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
5132 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
5133 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
5134 named
, align
, depth
);
5140 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
5146 r1
= gen_rtx_REG (DImode
, gregno
);
5147 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5148 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
5150 else if (mode
== DCmode
)
5152 r1
= gen_rtx_REG (DImode
, gregno
);
5153 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5154 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5155 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5156 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
5162 /* Determine where to put a SIMD argument on the SPE. */
5164 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5167 int gregno
= cum
->sysv_gregno
;
5169 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5170 are passed and returned in a pair of GPRs for ABI compatibility. */
5171 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DCmode
))
5173 int n_words
= rs6000_arg_size (mode
, type
);
5175 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5177 gregno
+= (1 - gregno
) & 1;
5179 /* Multi-reg args are not split between registers and stack. */
5180 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5183 return spe_build_register_parallel (mode
, gregno
);
5187 int n_words
= rs6000_arg_size (mode
, type
);
5189 /* SPE vectors are put in odd registers. */
5190 if (n_words
== 2 && (gregno
& 1) == 0)
5193 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
5196 enum machine_mode m
= SImode
;
5198 r1
= gen_rtx_REG (m
, gregno
);
5199 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
5200 r2
= gen_rtx_REG (m
, gregno
+ 1);
5201 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
5202 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
5209 if (gregno
<= GP_ARG_MAX_REG
)
5210 return gen_rtx_REG (mode
, gregno
);
5216 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5217 the register(s) to be used for each field and subfield of a struct
5218 being passed by value, along with the offset of where the
5219 register's value may be found in the block. */
5222 rs6000_darwin64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5223 tree type
, int named
)
5225 tree f
, ftype
, offset
;
5226 rtx rvec
[FIRST_PSEUDO_REGISTER
], sub
, suboff
, roffset
;
5227 int k
= 0, i
, j
, bytepos
, subbytepos
, tot
;
5228 CUMULATIVE_ARGS saved_cum
= *cum
;
5229 enum machine_mode submode
;
5231 switch (TREE_CODE (type
))
5234 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5235 if (TREE_CODE (f
) == FIELD_DECL
)
5237 ftype
= TREE_TYPE (f
);
5238 offset
= DECL_FIELD_OFFSET (f
);
5239 bytepos
= int_bit_position (f
) / BITS_PER_UNIT
;
5240 /* Force substructs to be handled as BLKmode even if
5241 they're small enough to be recorded as DImode, so we
5242 drill through to non-record fields. */
5243 submode
= TYPE_MODE (ftype
);
5244 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5246 sub
= function_arg (cum
, submode
, ftype
, named
);
5247 if (sub
== NULL_RTX
)
5249 if (GET_CODE (sub
) == PARALLEL
)
5251 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
5253 rtx subsub
= XVECEXP (sub
, 0, i
);
5254 suboff
= XEXP (subsub
, 1);
5255 subbytepos
= INTVAL (suboff
);
5256 subbytepos
+= bytepos
;
5257 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
5258 subsub
= XEXP (subsub
, 0);
5259 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
5264 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
5265 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
5267 /* Now do an arg advance to get all the cumulative arg
5268 stuff set correctly for the next subfield. Note that it
5269 has no lasting effect, because it is being done on a
5270 temporary copy of the cumulative arg data. */
5271 function_arg_advance (cum
, submode
, ftype
, named
, 1);
5276 tot
= rs6000_arg_size (mode
, type
);
5281 for (j
= 0; j
< tot
; ++j
)
5283 sub
= gen_rtx_REG ((TARGET_64BIT
? DImode
: SImode
), GP_ARG_MIN_REG
+ cum
->words
++);
5284 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
5285 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
5286 if (cum
->words
>= GP_ARG_NUM_REG
)
5288 bytepos
+= (TARGET_64BIT
? 8 : 4);
5293 tot
= int_size_in_bytes (type
);
5296 ftype
= TREE_TYPE (type
);
5297 tot
/= int_size_in_bytes (ftype
);
5300 for (j
= 0; j
< tot
; ++j
)
5302 /* Force substructs to be handled as BLKmode even if
5303 they're small enough to be recorded as DImode, so we
5304 drill through to non-record fields. */
5305 submode
= TYPE_MODE (ftype
);
5306 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5308 sub
= function_arg (cum
, submode
, ftype
, named
);
5309 if (sub
== NULL_RTX
)
5311 if (GET_CODE (sub
) == PARALLEL
)
5313 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
5315 rtx subsub
= XVECEXP (sub
, 0, i
);
5317 suboff
= XEXP (subsub
, 1);
5318 subbytepos
= INTVAL (suboff
);
5319 subbytepos
+= bytepos
;
5320 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
5321 subsub
= XEXP (subsub
, 0);
5322 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
5327 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
5328 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
5330 /* Now do an arg advance to get all the cumulative arg
5331 stuff set correctly for the next subfield. Note that it
5332 has no lasting effect, because it is being done on a
5333 temporary copy of the cumulative arg data. */
5334 function_arg_advance (cum
, submode
, ftype
, named
, 1);
5335 bytepos
+= int_size_in_bytes (ftype
);
5345 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5350 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5353 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
5357 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5359 if (align_words
>= GP_ARG_NUM_REG
)
5362 n_units
= rs6000_arg_size (mode
, type
);
5364 /* Optimize the simple case where the arg fits in one gpr, except in
5365 the case of BLKmode due to assign_parms assuming that registers are
5366 BITS_PER_WORD wide. */
5368 || (n_units
== 1 && mode
!= BLKmode
))
5369 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5372 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
5373 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5374 using a magic NULL_RTX component.
5375 FIXME: This is not strictly correct. Only some of the arg
5376 belongs in memory, not all of it. However, there isn't any way
5377 to do this currently, apart from building rtx descriptions for
5378 the pieces of memory we want stored. Due to bugs in the generic
5379 code we can't use the normal function_arg_partial_nregs scheme
5380 with the PARALLEL arg description we emit here.
5381 In any case, the code to store the whole arg to memory is often
5382 more efficient than code to store pieces, and we know that space
5383 is available in the right place for the whole arg. */
5384 /* FIXME: This should be fixed since the conversion to
5385 TARGET_ARG_PARTIAL_BYTES. */
5386 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5391 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
5392 rtx off
= GEN_INT (i
++ * 4);
5393 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5395 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
5397 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5400 /* Determine where to put an argument to a function.
5401 Value is zero to push the argument on the stack,
5402 or a hard register in which to store the argument.
5404 MODE is the argument's machine mode.
5405 TYPE is the data type of the argument (as a tree).
5406 This is null for libcalls where that information may
5408 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5409 the preceding args and about the function being called.
5410 NAMED is nonzero if this argument is a named parameter
5411 (otherwise it is an extra parameter matching an ellipsis).
5413 On RS/6000 the first eight words of non-FP are normally in registers
5414 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5415 Under V.4, the first 8 FP args are in registers.
5417 If this is floating-point and no prototype is specified, we use
5418 both an FP and integer register (or possibly FP reg and stack). Library
5419 functions (when CALL_LIBCALL is set) always have the proper types for args,
5420 so we can pass the FP value just in one register. emit_library_function
5421 doesn't support PARALLEL anyway.
5423 Note that for args passed by reference, function_arg will be called
5424 with MODE and TYPE set to that of the pointer to the arg, not the arg
5428 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5429 tree type
, int named
)
5431 enum rs6000_abi abi
= DEFAULT_ABI
;
5433 /* Return a marker to indicate whether CR1 needs to set or clear the
5434 bit that V.4 uses to say fp args were passed in registers.
5435 Assume that we don't need the marker for software floating point,
5436 or compiler generated library calls. */
5437 if (mode
== VOIDmode
)
5440 && cum
->nargs_prototype
< 0
5441 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
5442 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))
5444 /* For the SPE, we need to crxor CR6 always. */
5446 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
5447 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5448 return GEN_INT (cum
->call_cookie
5449 | ((cum
->fregno
== FP_ARG_MIN_REG
)
5450 ? CALL_V4_SET_FP_ARGS
5451 : CALL_V4_CLEAR_FP_ARGS
));
5454 return GEN_INT (cum
->call_cookie
);
5458 && rs6000_darwin64_abi
5459 && (TREE_CODE (type
) == RECORD_TYPE
5460 || TREE_CODE (type
) == UNION_TYPE
5461 || TREE_CODE (type
) == ARRAY_TYPE
))
5463 rtx rslt
= rs6000_darwin64_function_arg (cum
, mode
, type
, named
);
5464 if (rslt
!= NULL_RTX
)
5466 /* Else fall through to usual handling. */
5469 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5470 if (TARGET_64BIT
&& ! cum
->prototype
)
5472 /* Vector parameters get passed in vector register
5473 and also in GPRs or memory, in absence of prototype. */
5476 align_words
= (cum
->words
+ 1) & ~1;
5478 if (align_words
>= GP_ARG_NUM_REG
)
5484 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5486 return gen_rtx_PARALLEL (mode
,
5488 gen_rtx_EXPR_LIST (VOIDmode
,
5490 gen_rtx_EXPR_LIST (VOIDmode
,
5491 gen_rtx_REG (mode
, cum
->vregno
),
5495 return gen_rtx_REG (mode
, cum
->vregno
);
5496 else if (TARGET_ALTIVEC_ABI
5497 && (ALTIVEC_VECTOR_MODE (mode
)
5498 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5499 && int_size_in_bytes (type
) == 16)))
5501 if (named
|| abi
== ABI_V4
)
5505 /* Vector parameters to varargs functions under AIX or Darwin
5506 get passed in memory and possibly also in GPRs. */
5507 int align
, align_words
, n_words
;
5508 enum machine_mode part_mode
;
5510 /* Vector parameters must be 16-byte aligned. This places them at
5511 2 mod 4 in terms of words in 32-bit mode, since the parameter
5512 save area starts at offset 24 from the stack. In 64-bit mode,
5513 they just have to start on an even word, since the parameter
5514 save area is 16-byte aligned. */
5516 align
= (2 - cum
->words
) & 3;
5518 align
= cum
->words
& 1;
5519 align_words
= cum
->words
+ align
;
5521 /* Out of registers? Memory, then. */
5522 if (align_words
>= GP_ARG_NUM_REG
)
5525 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5526 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5528 /* The vector value goes in GPRs. Only the part of the
5529 value in GPRs is reported here. */
5531 n_words
= rs6000_arg_size (mode
, type
);
5532 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
5533 /* Fortunately, there are only two possibilities, the value
5534 is either wholly in GPRs or half in GPRs and half not. */
5537 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
5540 else if (TARGET_SPE_ABI
&& TARGET_SPE
5541 && (SPE_VECTOR_MODE (mode
)
5542 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
5543 || mode
== DCmode
))))
5544 return rs6000_spe_function_arg (cum
, mode
, type
);
5546 else if (abi
== ABI_V4
)
5548 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5549 && (mode
== SFmode
|| mode
== DFmode
))
5551 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
5552 return gen_rtx_REG (mode
, cum
->fregno
);
5558 int n_words
= rs6000_arg_size (mode
, type
);
5559 int gregno
= cum
->sysv_gregno
;
5561 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5562 (r7,r8) or (r9,r10). As does any other 2 word item such
5563 as complex int due to a historical mistake. */
5565 gregno
+= (1 - gregno
) & 1;
5567 /* Multi-reg args are not split between registers and stack. */
5568 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5571 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5572 return rs6000_mixed_function_arg (mode
, type
,
5573 gregno
- GP_ARG_MIN_REG
);
5574 return gen_rtx_REG (mode
, gregno
);
5579 int align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5580 int align_words
= cum
->words
+ (cum
->words
& align
);
5582 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
5584 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5588 enum machine_mode fmode
= mode
;
5589 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
5591 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
5593 /* Currently, we only ever need one reg here because complex
5594 doubles are split. */
5595 if (cum
->fregno
!= FP_ARG_MAX_REG
|| fmode
!= TFmode
)
5598 /* Long double split over regs and memory. */
5602 /* Do we also need to pass this arg in the parameter save
5605 && (cum
->nargs_prototype
<= 0
5606 || (DEFAULT_ABI
== ABI_AIX
5608 && align_words
>= GP_ARG_NUM_REG
)));
5610 if (!needs_psave
&& mode
== fmode
)
5611 return gen_rtx_REG (fmode
, cum
->fregno
);
5616 /* Describe the part that goes in gprs or the stack.
5617 This piece must come first, before the fprs. */
5618 if (align_words
< GP_ARG_NUM_REG
)
5620 unsigned long n_words
= rs6000_arg_size (mode
, type
);
5622 if (align_words
+ n_words
> GP_ARG_NUM_REG
5623 || (TARGET_32BIT
&& TARGET_POWERPC64
))
5625 /* If this is partially on the stack, then we only
5626 include the portion actually in registers here. */
5627 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
5630 if (align_words
+ n_words
> GP_ARG_NUM_REG
5631 && (TARGET_32BIT
&& TARGET_POWERPC64
))
5632 /* Not all of the arg fits in gprs. Say that it
5633 goes in memory too, using a magic NULL_RTX
5634 component. Also see comment in
5635 rs6000_mixed_function_arg for why the normal
5636 function_arg_partial_nregs scheme doesn't work
5638 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
5642 r
= gen_rtx_REG (rmode
,
5643 GP_ARG_MIN_REG
+ align_words
);
5644 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
5645 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5647 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
5651 /* The whole arg fits in gprs. */
5652 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5653 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5657 /* It's entirely in memory. */
5658 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5661 /* Describe where this piece goes in the fprs. */
5662 r
= gen_rtx_REG (fmode
, cum
->fregno
);
5663 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5665 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5667 else if (align_words
< GP_ARG_NUM_REG
)
5669 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5670 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5672 if (mode
== BLKmode
)
5675 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5682 /* For an arg passed partly in registers and partly in memory, this is
5683 the number of registers used. For args passed entirely in registers
5684 or entirely in memory, zero. When an arg is described by a PARALLEL,
5685 perhaps using more than one register type, this function returns the
5686 number of bytes of registers used by the PARALLEL. */
5689 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5690 tree type
, bool named
)
5697 if (DEFAULT_ABI
== ABI_V4
)
5700 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
5701 && cum
->nargs_prototype
>= 0)
5704 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5705 parm_offset
= TARGET_32BIT
? 2 : 0;
5706 align_words
= cum
->words
+ ((parm_offset
- cum
->words
) & align
);
5708 if (USE_FP_FOR_ARG_P (cum
, mode
, type
)
5709 /* If we are passing this arg in gprs as well, then this function
5710 should return the number of gprs (or memory) partially passed,
5711 *not* the number of fprs. */
5713 && (cum
->nargs_prototype
<= 0
5714 || (DEFAULT_ABI
== ABI_AIX
5716 && align_words
>= GP_ARG_NUM_REG
))))
5718 if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3) > FP_ARG_MAX_REG
+ 1)
5719 ret
= FP_ARG_MAX_REG
+ 1 - cum
->fregno
;
5720 else if (cum
->nargs_prototype
>= 0)
5724 if (align_words
< GP_ARG_NUM_REG
5725 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
5726 ret
= GP_ARG_NUM_REG
- align_words
;
5728 ret
*= (TARGET_32BIT
? 4 : 8);
5730 if (ret
!= 0 && TARGET_DEBUG_ARG
)
5731 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
5736 /* A C expression that indicates when an argument must be passed by
5737 reference. If nonzero for an argument, a copy of that argument is
5738 made in memory and a pointer to the argument is passed instead of
5739 the argument itself. The pointer is passed in whatever way is
5740 appropriate for passing a pointer to that type.
5742 Under V.4, aggregates and long double are passed by reference.
5744 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5745 reference unless the AltiVec vector extension ABI is in force.
5747 As an extension to all ABIs, variable sized types are passed by
5751 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5752 enum machine_mode mode
, tree type
,
5753 bool named ATTRIBUTE_UNUSED
)
5755 if (DEFAULT_ABI
== ABI_V4
&& mode
== TFmode
)
5757 if (TARGET_DEBUG_ARG
)
5758 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
5765 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
5767 if (TARGET_DEBUG_ARG
)
5768 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
5772 if (int_size_in_bytes (type
) < 0)
5774 if (TARGET_DEBUG_ARG
)
5775 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
5779 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5780 modes only exist for GCC vector types if -maltivec. */
5781 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
5783 if (TARGET_DEBUG_ARG
)
5784 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
5788 /* Pass synthetic vectors in memory. */
5789 if (TREE_CODE (type
) == VECTOR_TYPE
5790 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5792 static bool warned_for_pass_big_vectors
= false;
5793 if (TARGET_DEBUG_ARG
)
5794 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
5795 if (!warned_for_pass_big_vectors
)
5797 warning ("GCC vector passed by reference: "
5798 "non-standard ABI extension with no compatibility guarantee");
5799 warned_for_pass_big_vectors
= true;
5808 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
5811 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
5816 for (i
= 0; i
< nregs
; i
++)
5818 rtx tem
= adjust_address_nv (x
, reg_mode
, i
*GET_MODE_SIZE(reg_mode
));
5819 if (reload_completed
)
5821 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
5824 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
5825 i
* GET_MODE_SIZE(reg_mode
));
5828 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
5830 if (tem
== NULL_RTX
)
5833 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
5837 /* Perform any needed actions needed for a function that is receiving a
5838 variable number of arguments.
5842 MODE and TYPE are the mode and type of the current parameter.
5844 PRETEND_SIZE is a variable that should be set to the amount of stack
5845 that must be pushed by the prolog to pretend that our caller pushed
5848 Normally, this macro will push all remaining incoming registers on the
5849 stack and set PRETEND_SIZE to the length of the registers pushed. */
5852 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5853 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5856 CUMULATIVE_ARGS next_cum
;
5857 int reg_size
= TARGET_32BIT
? 4 : 8;
5858 rtx save_area
= NULL_RTX
, mem
;
5859 int first_reg_offset
, set
;
5861 /* Skip the last named argument. */
5863 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
5865 if (DEFAULT_ABI
== ABI_V4
)
5868 save_area
= plus_constant (virtual_stack_vars_rtx
,
5869 - RS6000_VARARGS_SIZE
);
5871 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
5875 first_reg_offset
= next_cum
.words
;
5876 save_area
= virtual_incoming_args_rtx
;
5878 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5879 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
5882 set
= get_varargs_alias_set ();
5883 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
)
5885 mem
= gen_rtx_MEM (BLKmode
,
5886 plus_constant (save_area
,
5887 first_reg_offset
* reg_size
)),
5888 set_mem_alias_set (mem
, set
);
5889 set_mem_align (mem
, BITS_PER_WORD
);
5891 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
5892 GP_ARG_NUM_REG
- first_reg_offset
);
5895 /* Save FP registers if needed. */
5896 if (DEFAULT_ABI
== ABI_V4
5897 && TARGET_HARD_FLOAT
&& TARGET_FPRS
5899 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
)
5901 int fregno
= next_cum
.fregno
;
5902 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
5903 rtx lab
= gen_label_rtx ();
5904 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
) * 8);
5907 (gen_rtx_SET (VOIDmode
,
5909 gen_rtx_IF_THEN_ELSE (VOIDmode
,
5910 gen_rtx_NE (VOIDmode
, cr1
,
5912 gen_rtx_LABEL_REF (VOIDmode
, lab
),
5915 while (fregno
<= FP_ARG_V4_MAX_REG
)
5917 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
5918 set_mem_alias_set (mem
, set
);
5919 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
5920 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
5929 /* Create the va_list data type. */
5932 rs6000_build_builtin_va_list (void)
5934 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
5936 /* For AIX, prefer 'char *' because that's what the system
5937 header files like. */
5938 if (DEFAULT_ABI
!= ABI_V4
)
5939 return build_pointer_type (char_type_node
);
5941 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5942 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5944 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
5945 unsigned_char_type_node
);
5946 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
5947 unsigned_char_type_node
);
5948 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5950 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
5951 short_unsigned_type_node
);
5952 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
5954 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
5957 DECL_FIELD_CONTEXT (f_gpr
) = record
;
5958 DECL_FIELD_CONTEXT (f_fpr
) = record
;
5959 DECL_FIELD_CONTEXT (f_res
) = record
;
5960 DECL_FIELD_CONTEXT (f_ovf
) = record
;
5961 DECL_FIELD_CONTEXT (f_sav
) = record
;
5963 TREE_CHAIN (record
) = type_decl
;
5964 TYPE_NAME (record
) = type_decl
;
5965 TYPE_FIELDS (record
) = f_gpr
;
5966 TREE_CHAIN (f_gpr
) = f_fpr
;
5967 TREE_CHAIN (f_fpr
) = f_res
;
5968 TREE_CHAIN (f_res
) = f_ovf
;
5969 TREE_CHAIN (f_ovf
) = f_sav
;
5971 layout_type (record
);
5973 /* The correct type is an array type of one element. */
5974 return build_array_type (record
, build_index_type (size_zero_node
));
5977 /* Implement va_start. */
5980 rs6000_va_start (tree valist
, rtx nextarg
)
5982 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
5983 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5984 tree gpr
, fpr
, ovf
, sav
, t
;
5986 /* Only SVR4 needs something special. */
5987 if (DEFAULT_ABI
!= ABI_V4
)
5989 std_expand_builtin_va_start (valist
, nextarg
);
5993 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
5994 f_fpr
= TREE_CHAIN (f_gpr
);
5995 f_res
= TREE_CHAIN (f_fpr
);
5996 f_ovf
= TREE_CHAIN (f_res
);
5997 f_sav
= TREE_CHAIN (f_ovf
);
5999 valist
= build_va_arg_indirect_ref (valist
);
6000 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6001 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6002 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6003 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6005 /* Count number of gp and fp argument registers used. */
6006 words
= current_function_args_info
.words
;
6007 n_gpr
= MIN (current_function_args_info
.sysv_gregno
- GP_ARG_MIN_REG
,
6009 n_fpr
= MIN (current_function_args_info
.fregno
- FP_ARG_MIN_REG
,
6012 if (TARGET_DEBUG_ARG
)
6013 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
6014 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
6015 words
, n_gpr
, n_fpr
);
6017 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
6018 build_int_cst (NULL_TREE
, n_gpr
));
6019 TREE_SIDE_EFFECTS (t
) = 1;
6020 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6022 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
6023 build_int_cst (NULL_TREE
, n_fpr
));
6024 TREE_SIDE_EFFECTS (t
) = 1;
6025 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6027 /* Find the overflow area. */
6028 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
6030 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
6031 build_int_cst (NULL_TREE
, words
* UNITS_PER_WORD
));
6032 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
6033 TREE_SIDE_EFFECTS (t
) = 1;
6034 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6036 /* Find the register save area. */
6037 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
6038 t
= build (PLUS_EXPR
, TREE_TYPE (sav
), t
,
6039 build_int_cst (NULL_TREE
, -RS6000_VARARGS_SIZE
));
6040 t
= build (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
6041 TREE_SIDE_EFFECTS (t
) = 1;
6042 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6045 /* Implement va_arg. */
6048 rs6000_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
6050 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6051 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
6052 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
6053 tree lab_false
, lab_over
, addr
;
6055 tree ptrtype
= build_pointer_type (type
);
6057 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6059 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
6060 return build_va_arg_indirect_ref (t
);
6063 if (DEFAULT_ABI
!= ABI_V4
)
6065 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
6067 tree elem_type
= TREE_TYPE (type
);
6068 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
6069 int elem_size
= GET_MODE_SIZE (elem_mode
);
6071 if (elem_size
< UNITS_PER_WORD
)
6073 tree real_part
, imag_part
;
6074 tree post
= NULL_TREE
;
6076 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6078 /* Copy the value into a temporary, lest the formal temporary
6079 be reused out from under us. */
6080 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
6081 append_to_statement_list (post
, pre_p
);
6083 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6086 return build (COMPLEX_EXPR
, type
, real_part
, imag_part
);
6090 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6093 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6094 f_fpr
= TREE_CHAIN (f_gpr
);
6095 f_res
= TREE_CHAIN (f_fpr
);
6096 f_ovf
= TREE_CHAIN (f_res
);
6097 f_sav
= TREE_CHAIN (f_ovf
);
6099 valist
= build_va_arg_indirect_ref (valist
);
6100 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6101 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6102 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6103 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6105 size
= int_size_in_bytes (type
);
6106 rsize
= (size
+ 3) / 4;
6109 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6110 && (TYPE_MODE (type
) == SFmode
|| TYPE_MODE (type
) == DFmode
))
6112 /* FP args go in FP registers, if present. */
6117 if (TYPE_MODE (type
) == DFmode
)
6122 /* Otherwise into GP registers. */
6131 /* Pull the value out of the saved registers.... */
6134 addr
= create_tmp_var (ptr_type_node
, "addr");
6135 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
6137 /* AltiVec vectors never go in registers when -mabi=altivec. */
6138 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
6142 lab_false
= create_artificial_label ();
6143 lab_over
= create_artificial_label ();
6145 /* Long long and SPE vectors are aligned in the registers.
6146 As are any other 2 gpr item such as complex int due to a
6147 historical mistake. */
6151 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), reg
,
6152 size_int (n_reg
- 1));
6153 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, u
);
6156 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
6157 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
6158 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
6159 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
6160 gimplify_and_add (t
, pre_p
);
6164 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
6166 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, size_int (n_reg
));
6167 u
= build1 (CONVERT_EXPR
, integer_type_node
, u
);
6168 u
= build2 (MULT_EXPR
, integer_type_node
, u
, size_int (sav_scale
));
6169 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
, u
);
6171 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
6172 gimplify_and_add (t
, pre_p
);
6174 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
6175 gimplify_and_add (t
, pre_p
);
6177 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
6178 append_to_statement_list (t
, pre_p
);
6182 /* Ensure that we don't find any more args in regs.
6183 Alignment has taken care of the n_reg == 2 case. */
6184 t
= build (MODIFY_EXPR
, TREE_TYPE (reg
), reg
, size_int (8));
6185 gimplify_and_add (t
, pre_p
);
6189 /* ... otherwise out of the overflow area. */
6191 /* Care for on-stack alignment if needed. */
6195 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
6196 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
6197 build_int_cst (NULL_TREE
, -align
));
6199 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
6201 u
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
6202 gimplify_and_add (u
, pre_p
);
6204 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6205 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
6206 gimplify_and_add (t
, pre_p
);
6210 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
6211 append_to_statement_list (t
, pre_p
);
6214 addr
= fold_convert (ptrtype
, addr
);
6215 return build_va_arg_indirect_ref (addr
);
6220 #define def_builtin(MASK, NAME, TYPE, CODE) \
6222 if ((MASK) & target_flags) \
6223 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
6227 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6229 static const struct builtin_description bdesc_3arg
[] =
6231 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
6232 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
6233 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
6234 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
6235 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
6236 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
6237 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
6238 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
6239 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
6240 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
6241 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
6242 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
6243 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
6244 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
6245 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
6246 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
6247 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
6248 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
6249 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
6250 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
6251 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
6252 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
6253 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
6256 /* DST operations: void foo (void *, const int, const char). */
6258 static const struct builtin_description bdesc_dst
[] =
6260 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
6261 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
6262 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
6263 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
}
6266 /* Simple binary operations: VECc = foo (VECa, VECb). */
6268 static struct builtin_description bdesc_2arg
[] =
6270 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
6271 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
6272 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
6273 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
6274 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
6275 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
6276 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
6277 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
6278 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
6279 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
6280 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
6281 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
6282 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
6283 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
6284 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
6285 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
6286 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
6287 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
6288 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
6289 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
6290 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
6291 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
6292 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
6293 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
6294 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
6295 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
6296 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
6297 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
6298 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
6299 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
6300 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
6301 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
6302 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
6303 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
6304 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
6305 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
6306 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
6307 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
6308 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
6309 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
6310 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
6311 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
6312 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
6313 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
6314 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
6315 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
6316 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
6317 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
6318 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
6319 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
6320 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
6321 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
6322 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
6323 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
6324 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
6325 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
6326 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
6327 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
6328 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
6329 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
6330 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
6331 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
6332 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
6333 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
6334 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
6335 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
6336 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
6337 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
6338 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
6339 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhss
, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS
},
6340 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
6341 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwss
, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS
},
6342 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
6343 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
6344 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
6345 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
6346 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
6347 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
6348 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
6349 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
6350 { MASK_ALTIVEC
, CODE_FOR_altivec_vslb
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
6351 { MASK_ALTIVEC
, CODE_FOR_altivec_vslh
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
6352 { MASK_ALTIVEC
, CODE_FOR_altivec_vslw
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
6353 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
6354 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
6355 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
6356 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
6357 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
6358 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrb
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
6359 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrh
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
6360 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrw
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
6361 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrab
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
6362 { MASK_ALTIVEC
, CODE_FOR_altivec_vsrah
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
6363 { MASK_ALTIVEC
, CODE_FOR_altivec_vsraw
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
6364 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
6365 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
6366 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
6367 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
6368 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
6369 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
6370 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
6371 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
6372 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
6373 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
6374 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
6375 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
6376 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
6377 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
6378 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
6379 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
6380 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
6381 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
6382 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
6384 /* Place holder, leave as first spe builtin. */
6385 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
6386 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
6387 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
6388 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
6389 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
6390 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
6391 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
6392 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
6393 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
6394 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
6395 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
6396 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
6397 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
6398 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
6399 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
6400 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
6401 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
6402 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
6403 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
6404 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
6405 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
6406 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
6407 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
6408 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
6409 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
6410 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
6411 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
6412 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
6413 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
6414 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
6415 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
6416 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
6417 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
6418 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
6419 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
6420 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
6421 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
6422 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
6423 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
6424 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
6425 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
6426 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
6427 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
6428 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
6429 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
6430 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
6431 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
6432 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
6433 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
6434 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
6435 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
6436 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
6437 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
6438 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
6439 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
6440 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
6441 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
6442 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
6443 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
6444 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
6445 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
6446 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
6447 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
6448 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
6449 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
6450 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
6451 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
6452 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
6453 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
6454 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
6455 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
6456 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
6457 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
6458 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
6459 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
6460 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
6461 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
6462 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
6463 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
6464 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
6465 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
6466 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
6467 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
6468 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
6469 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
6470 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
6471 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
6472 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
6473 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
6474 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
6475 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
6476 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
6477 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
6478 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
6479 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
6480 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
6481 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
6482 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
6483 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
6484 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
6485 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
6486 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
6487 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
6488 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
6489 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
6490 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
6491 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
6492 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
6493 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
6495 /* SPE binary operations expecting a 5-bit unsigned literal. */
6496 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
6498 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
6499 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
6500 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
6501 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
6502 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
6503 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
6504 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
6505 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
6506 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
6507 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
6508 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
6509 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
6510 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
6511 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
6512 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
6513 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
6514 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
6515 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
6516 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
6517 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
6518 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
6519 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
6520 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
6521 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
6522 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
6523 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
6525 /* Place-holder. Leave as last binary SPE builtin. */
6526 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
},
6529 /* AltiVec predicates. */
6531 struct builtin_description_predicates
6533 const unsigned int mask
;
6534 const enum insn_code icode
;
6536 const char *const name
;
6537 const enum rs6000_builtins code
;
6540 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
6542 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
6543 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
6544 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
6545 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
6546 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
6547 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
6548 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
6549 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
6550 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
6551 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
6552 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
6553 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
6554 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
}
6557 /* SPE predicates. */
6558 static struct builtin_description bdesc_spe_predicates
[] =
6560 /* Place-holder. Leave as first. */
6561 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
6562 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
6563 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
6564 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
6565 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
6566 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
6567 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
6568 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
6569 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
6570 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
6571 /* Place-holder. Leave as last. */
6572 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
6575 /* SPE evsel predicates. */
6576 static struct builtin_description bdesc_spe_evsel
[] =
6578 /* Place-holder. Leave as first. */
6579 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
6580 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
6581 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
6582 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
6583 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
6584 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
6585 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
6586 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
6587 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
6588 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
6589 /* Place-holder. Leave as last. */
6590 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
6593 /* ABS* operations. */
6595 static const struct builtin_description bdesc_abs
[] =
6597 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
6598 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
6599 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
6600 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
6601 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
6602 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
6603 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
6606 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6609 static struct builtin_description bdesc_1arg
[] =
6611 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
6612 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
6613 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
6614 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
6615 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
6616 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
6617 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
6618 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
6619 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
6620 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
6621 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
6622 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
6623 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
6624 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
6625 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
6626 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
6627 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
6629 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6630 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6631 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
6632 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
6633 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
6634 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
6635 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
6636 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
6637 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
6638 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
6639 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
6640 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
6641 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
6642 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
6643 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
6644 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
6645 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
6646 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
6647 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
6648 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
6649 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
6650 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
6651 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
6652 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
6653 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
6654 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
6655 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
6656 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
6657 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
6658 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
6660 /* Place-holder. Leave as last unary SPE builtin. */
6661 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
6665 rs6000_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6668 tree arg0
= TREE_VALUE (arglist
);
6669 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6670 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6671 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6673 if (icode
== CODE_FOR_nothing
)
6674 /* Builtin not supported on this processor. */
6677 /* If we got invalid arguments bail out before generating bad rtl. */
6678 if (arg0
== error_mark_node
)
6681 if (icode
== CODE_FOR_altivec_vspltisb
6682 || icode
== CODE_FOR_altivec_vspltish
6683 || icode
== CODE_FOR_altivec_vspltisw
6684 || icode
== CODE_FOR_spe_evsplatfi
6685 || icode
== CODE_FOR_spe_evsplati
)
6687 /* Only allow 5-bit *signed* literals. */
6688 if (GET_CODE (op0
) != CONST_INT
6689 || INTVAL (op0
) > 0x1f
6690 || INTVAL (op0
) < -0x1f)
6692 error ("argument 1 must be a 5-bit signed literal");
6698 || GET_MODE (target
) != tmode
6699 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6700 target
= gen_reg_rtx (tmode
);
6702 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6703 op0
= copy_to_mode_reg (mode0
, op0
);
6705 pat
= GEN_FCN (icode
) (target
, op0
);
6714 altivec_expand_abs_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6716 rtx pat
, scratch1
, scratch2
;
6717 tree arg0
= TREE_VALUE (arglist
);
6718 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6719 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6720 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6722 /* If we have invalid arguments, bail out before generating bad rtl. */
6723 if (arg0
== error_mark_node
)
6727 || GET_MODE (target
) != tmode
6728 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6729 target
= gen_reg_rtx (tmode
);
6731 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6732 op0
= copy_to_mode_reg (mode0
, op0
);
6734 scratch1
= gen_reg_rtx (mode0
);
6735 scratch2
= gen_reg_rtx (mode0
);
6737 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
6746 rs6000_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6749 tree arg0
= TREE_VALUE (arglist
);
6750 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6751 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6752 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6753 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6754 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6755 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6757 if (icode
== CODE_FOR_nothing
)
6758 /* Builtin not supported on this processor. */
6761 /* If we got invalid arguments bail out before generating bad rtl. */
6762 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6765 if (icode
== CODE_FOR_altivec_vcfux
6766 || icode
== CODE_FOR_altivec_vcfsx
6767 || icode
== CODE_FOR_altivec_vctsxs
6768 || icode
== CODE_FOR_altivec_vctuxs
6769 || icode
== CODE_FOR_altivec_vspltb
6770 || icode
== CODE_FOR_altivec_vsplth
6771 || icode
== CODE_FOR_altivec_vspltw
6772 || icode
== CODE_FOR_spe_evaddiw
6773 || icode
== CODE_FOR_spe_evldd
6774 || icode
== CODE_FOR_spe_evldh
6775 || icode
== CODE_FOR_spe_evldw
6776 || icode
== CODE_FOR_spe_evlhhesplat
6777 || icode
== CODE_FOR_spe_evlhhossplat
6778 || icode
== CODE_FOR_spe_evlhhousplat
6779 || icode
== CODE_FOR_spe_evlwhe
6780 || icode
== CODE_FOR_spe_evlwhos
6781 || icode
== CODE_FOR_spe_evlwhou
6782 || icode
== CODE_FOR_spe_evlwhsplat
6783 || icode
== CODE_FOR_spe_evlwwsplat
6784 || icode
== CODE_FOR_spe_evrlwi
6785 || icode
== CODE_FOR_spe_evslwi
6786 || icode
== CODE_FOR_spe_evsrwis
6787 || icode
== CODE_FOR_spe_evsubifw
6788 || icode
== CODE_FOR_spe_evsrwiu
)
6790 /* Only allow 5-bit unsigned literals. */
6792 if (TREE_CODE (arg1
) != INTEGER_CST
6793 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
6795 error ("argument 2 must be a 5-bit unsigned literal");
6801 || GET_MODE (target
) != tmode
6802 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6803 target
= gen_reg_rtx (tmode
);
6805 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6806 op0
= copy_to_mode_reg (mode0
, op0
);
6807 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6808 op1
= copy_to_mode_reg (mode1
, op1
);
6810 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6819 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
6820 tree arglist
, rtx target
)
6823 tree cr6_form
= TREE_VALUE (arglist
);
6824 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
6825 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6826 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6827 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6828 enum machine_mode tmode
= SImode
;
6829 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6830 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6833 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
6835 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6839 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
6844 /* If we have invalid arguments, bail out before generating bad rtl. */
6845 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6849 || GET_MODE (target
) != tmode
6850 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6851 target
= gen_reg_rtx (tmode
);
6853 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6854 op0
= copy_to_mode_reg (mode0
, op0
);
6855 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6856 op1
= copy_to_mode_reg (mode1
, op1
);
6858 scratch
= gen_reg_rtx (mode0
);
6860 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
6861 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
6866 /* The vec_any* and vec_all* predicates use the same opcodes for two
6867 different operations, but the bits in CR6 will be different
6868 depending on what information we want. So we have to play tricks
6869 with CR6 to get the right bits out.
6871 If you think this is disgusting, look at the specs for the
6872 AltiVec predicates. */
6874 switch (cr6_form_int
)
6877 emit_insn (gen_cr6_test_for_zero (target
));
6880 emit_insn (gen_cr6_test_for_zero_reverse (target
));
6883 emit_insn (gen_cr6_test_for_lt (target
));
6886 emit_insn (gen_cr6_test_for_lt_reverse (target
));
6889 error ("argument 1 of __builtin_altivec_predicate is out of range");
6897 altivec_expand_lv_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6900 tree arg0
= TREE_VALUE (arglist
);
6901 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6902 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6903 enum machine_mode mode0
= Pmode
;
6904 enum machine_mode mode1
= Pmode
;
6905 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6906 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6908 if (icode
== CODE_FOR_nothing
)
6909 /* Builtin not supported on this processor. */
6912 /* If we got invalid arguments bail out before generating bad rtl. */
6913 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6917 || GET_MODE (target
) != tmode
6918 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6919 target
= gen_reg_rtx (tmode
);
6921 op1
= copy_to_mode_reg (mode1
, op1
);
6923 if (op0
== const0_rtx
)
6925 addr
= gen_rtx_MEM (tmode
, op1
);
6929 op0
= copy_to_mode_reg (mode0
, op0
);
6930 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
6933 pat
= GEN_FCN (icode
) (target
, addr
);
6943 spe_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6945 tree arg0
= TREE_VALUE (arglist
);
6946 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6947 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6948 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6949 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6950 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6952 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
6953 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
6954 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
6956 /* Invalid arguments. Bail before doing anything stoopid! */
6957 if (arg0
== error_mark_node
6958 || arg1
== error_mark_node
6959 || arg2
== error_mark_node
)
6962 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
6963 op0
= copy_to_mode_reg (mode2
, op0
);
6964 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
6965 op1
= copy_to_mode_reg (mode0
, op1
);
6966 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
6967 op2
= copy_to_mode_reg (mode1
, op2
);
6969 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
6976 altivec_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6978 tree arg0
= TREE_VALUE (arglist
);
6979 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6980 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6981 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6982 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6983 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6985 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6986 enum machine_mode mode1
= Pmode
;
6987 enum machine_mode mode2
= Pmode
;
6989 /* Invalid arguments. Bail before doing anything stoopid! */
6990 if (arg0
== error_mark_node
6991 || arg1
== error_mark_node
6992 || arg2
== error_mark_node
)
6995 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
6996 op0
= copy_to_mode_reg (tmode
, op0
);
6998 op2
= copy_to_mode_reg (mode2
, op2
);
7000 if (op1
== const0_rtx
)
7002 addr
= gen_rtx_MEM (tmode
, op2
);
7006 op1
= copy_to_mode_reg (mode1
, op1
);
7007 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
7010 pat
= GEN_FCN (icode
) (addr
, op0
);
7017 rs6000_expand_ternop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7020 tree arg0
= TREE_VALUE (arglist
);
7021 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7022 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7023 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7024 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7025 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7026 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7027 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7028 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7029 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
7031 if (icode
== CODE_FOR_nothing
)
7032 /* Builtin not supported on this processor. */
7035 /* If we got invalid arguments bail out before generating bad rtl. */
7036 if (arg0
== error_mark_node
7037 || arg1
== error_mark_node
7038 || arg2
== error_mark_node
)
7041 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
7042 || icode
== CODE_FOR_altivec_vsldoi_v4si
7043 || icode
== CODE_FOR_altivec_vsldoi_v8hi
7044 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
7046 /* Only allow 4-bit unsigned literals. */
7048 if (TREE_CODE (arg2
) != INTEGER_CST
7049 || TREE_INT_CST_LOW (arg2
) & ~0xf)
7051 error ("argument 3 must be a 4-bit unsigned literal");
7057 || GET_MODE (target
) != tmode
7058 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7059 target
= gen_reg_rtx (tmode
);
7061 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7062 op0
= copy_to_mode_reg (mode0
, op0
);
7063 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7064 op1
= copy_to_mode_reg (mode1
, op1
);
7065 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
7066 op2
= copy_to_mode_reg (mode2
, op2
);
7068 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
7076 /* Expand the lvx builtins. */
7078 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
7080 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7081 tree arglist
= TREE_OPERAND (exp
, 1);
7082 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7084 enum machine_mode tmode
, mode0
;
7086 enum insn_code icode
;
7090 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
7091 icode
= CODE_FOR_altivec_lvx_v16qi
;
7093 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
7094 icode
= CODE_FOR_altivec_lvx_v8hi
;
7096 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
7097 icode
= CODE_FOR_altivec_lvx_v4si
;
7099 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
7100 icode
= CODE_FOR_altivec_lvx_v4sf
;
7109 arg0
= TREE_VALUE (arglist
);
7110 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7111 tmode
= insn_data
[icode
].operand
[0].mode
;
7112 mode0
= insn_data
[icode
].operand
[1].mode
;
7115 || GET_MODE (target
) != tmode
7116 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7117 target
= gen_reg_rtx (tmode
);
7119 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7120 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7122 pat
= GEN_FCN (icode
) (target
, op0
);
7129 /* Expand the stvx builtins. */
7131 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7134 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7135 tree arglist
= TREE_OPERAND (exp
, 1);
7136 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7138 enum machine_mode mode0
, mode1
;
7140 enum insn_code icode
;
7144 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
7145 icode
= CODE_FOR_altivec_stvx_v16qi
;
7147 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
7148 icode
= CODE_FOR_altivec_stvx_v8hi
;
7150 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
7151 icode
= CODE_FOR_altivec_stvx_v4si
;
7153 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
7154 icode
= CODE_FOR_altivec_stvx_v4sf
;
7161 arg0
= TREE_VALUE (arglist
);
7162 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7163 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7164 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7165 mode0
= insn_data
[icode
].operand
[0].mode
;
7166 mode1
= insn_data
[icode
].operand
[1].mode
;
7168 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7169 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7170 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7171 op1
= copy_to_mode_reg (mode1
, op1
);
7173 pat
= GEN_FCN (icode
) (op0
, op1
);
7181 /* Expand the dst builtins. */
7183 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7186 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7187 tree arglist
= TREE_OPERAND (exp
, 1);
7188 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7189 tree arg0
, arg1
, arg2
;
7190 enum machine_mode mode0
, mode1
, mode2
;
7191 rtx pat
, op0
, op1
, op2
;
7192 struct builtin_description
*d
;
7197 /* Handle DST variants. */
7198 d
= (struct builtin_description
*) bdesc_dst
;
7199 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
7200 if (d
->code
== fcode
)
7202 arg0
= TREE_VALUE (arglist
);
7203 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7204 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7205 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7206 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7207 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7208 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7209 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
7210 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
7212 /* Invalid arguments, bail out before generating bad rtl. */
7213 if (arg0
== error_mark_node
7214 || arg1
== error_mark_node
7215 || arg2
== error_mark_node
)
7220 if (TREE_CODE (arg2
) != INTEGER_CST
7221 || TREE_INT_CST_LOW (arg2
) & ~0x3)
7223 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
7227 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
7228 op0
= copy_to_mode_reg (Pmode
, op0
);
7229 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
7230 op1
= copy_to_mode_reg (mode1
, op1
);
7232 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
7242 /* Expand the builtin in EXP and store the result in TARGET. Store
7243 true in *EXPANDEDP if we found a builtin to expand. */
7245 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
7247 struct builtin_description
*d
;
7248 struct builtin_description_predicates
*dp
;
7250 enum insn_code icode
;
7251 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7252 tree arglist
= TREE_OPERAND (exp
, 1);
7255 enum machine_mode tmode
, mode0
;
7256 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7258 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
7262 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
7266 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
7274 case ALTIVEC_BUILTIN_STVX
:
7275 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, arglist
);
7276 case ALTIVEC_BUILTIN_STVEBX
:
7277 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, arglist
);
7278 case ALTIVEC_BUILTIN_STVEHX
:
7279 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, arglist
);
7280 case ALTIVEC_BUILTIN_STVEWX
:
7281 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, arglist
);
7282 case ALTIVEC_BUILTIN_STVXL
:
7283 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, arglist
);
7285 case ALTIVEC_BUILTIN_MFVSCR
:
7286 icode
= CODE_FOR_altivec_mfvscr
;
7287 tmode
= insn_data
[icode
].operand
[0].mode
;
7290 || GET_MODE (target
) != tmode
7291 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7292 target
= gen_reg_rtx (tmode
);
7294 pat
= GEN_FCN (icode
) (target
);
7300 case ALTIVEC_BUILTIN_MTVSCR
:
7301 icode
= CODE_FOR_altivec_mtvscr
;
7302 arg0
= TREE_VALUE (arglist
);
7303 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7304 mode0
= insn_data
[icode
].operand
[0].mode
;
7306 /* If we got invalid arguments bail out before generating bad rtl. */
7307 if (arg0
== error_mark_node
)
7310 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7311 op0
= copy_to_mode_reg (mode0
, op0
);
7313 pat
= GEN_FCN (icode
) (op0
);
7318 case ALTIVEC_BUILTIN_DSSALL
:
7319 emit_insn (gen_altivec_dssall ());
7322 case ALTIVEC_BUILTIN_DSS
:
7323 icode
= CODE_FOR_altivec_dss
;
7324 arg0
= TREE_VALUE (arglist
);
7326 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7327 mode0
= insn_data
[icode
].operand
[0].mode
;
7329 /* If we got invalid arguments bail out before generating bad rtl. */
7330 if (arg0
== error_mark_node
)
7333 if (TREE_CODE (arg0
) != INTEGER_CST
7334 || TREE_INT_CST_LOW (arg0
) & ~0x3)
7336 error ("argument to dss must be a 2-bit unsigned literal");
7340 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7341 op0
= copy_to_mode_reg (mode0
, op0
);
7343 emit_insn (gen_altivec_dss (op0
));
7346 case ALTIVEC_BUILTIN_COMPILETIME_ERROR
:
7347 arg0
= TREE_VALUE (arglist
);
7348 while (TREE_CODE (arg0
) == NOP_EXPR
|| TREE_CODE (arg0
) == ADDR_EXPR
7349 || TREE_CODE (arg0
) == ARRAY_REF
)
7350 arg0
= TREE_OPERAND (arg0
, 0);
7351 error ("invalid parameter combination for %qs AltiVec intrinsic",
7352 TREE_STRING_POINTER (arg0
));
7357 /* Expand abs* operations. */
7358 d
= (struct builtin_description
*) bdesc_abs
;
7359 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
7360 if (d
->code
== fcode
)
7361 return altivec_expand_abs_builtin (d
->icode
, arglist
, target
);
7363 /* Expand the AltiVec predicates. */
7364 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
7365 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
7366 if (dp
->code
== fcode
)
7367 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
7370 /* LV* are funky. We initialized them differently. */
7373 case ALTIVEC_BUILTIN_LVSL
:
7374 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
7376 case ALTIVEC_BUILTIN_LVSR
:
7377 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
7379 case ALTIVEC_BUILTIN_LVEBX
:
7380 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
7382 case ALTIVEC_BUILTIN_LVEHX
:
7383 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
7385 case ALTIVEC_BUILTIN_LVEWX
:
7386 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
7388 case ALTIVEC_BUILTIN_LVXL
:
7389 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
7391 case ALTIVEC_BUILTIN_LVX
:
7392 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
7403 /* Binops that need to be initialized manually, but can be expanded
7404 automagically by rs6000_expand_binop_builtin. */
7405 static struct builtin_description bdesc_2arg_spe
[] =
7407 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
7408 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
7409 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
7410 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
7411 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
7412 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
7413 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
7414 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
7415 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
7416 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
7417 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
7418 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
7419 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
7420 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
7421 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
7422 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
7423 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
7424 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
7425 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
7426 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
7427 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
7428 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
7431 /* Expand the builtin in EXP and store the result in TARGET. Store
7432 true in *EXPANDEDP if we found a builtin to expand.
7434 This expands the SPE builtins that are not simple unary and binary
7437 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
7439 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7440 tree arglist
= TREE_OPERAND (exp
, 1);
7442 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7443 enum insn_code icode
;
7444 enum machine_mode tmode
, mode0
;
7446 struct builtin_description
*d
;
7451 /* Syntax check for a 5-bit unsigned immediate. */
7454 case SPE_BUILTIN_EVSTDD
:
7455 case SPE_BUILTIN_EVSTDH
:
7456 case SPE_BUILTIN_EVSTDW
:
7457 case SPE_BUILTIN_EVSTWHE
:
7458 case SPE_BUILTIN_EVSTWHO
:
7459 case SPE_BUILTIN_EVSTWWE
:
7460 case SPE_BUILTIN_EVSTWWO
:
7461 arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7462 if (TREE_CODE (arg1
) != INTEGER_CST
7463 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7465 error ("argument 2 must be a 5-bit unsigned literal");
7473 /* The evsplat*i instructions are not quite generic. */
7476 case SPE_BUILTIN_EVSPLATFI
:
7477 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
7479 case SPE_BUILTIN_EVSPLATI
:
7480 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
7486 d
= (struct builtin_description
*) bdesc_2arg_spe
;
7487 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
7488 if (d
->code
== fcode
)
7489 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7491 d
= (struct builtin_description
*) bdesc_spe_predicates
;
7492 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
7493 if (d
->code
== fcode
)
7494 return spe_expand_predicate_builtin (d
->icode
, arglist
, target
);
7496 d
= (struct builtin_description
*) bdesc_spe_evsel
;
7497 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
7498 if (d
->code
== fcode
)
7499 return spe_expand_evsel_builtin (d
->icode
, arglist
, target
);
7503 case SPE_BUILTIN_EVSTDDX
:
7504 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, arglist
);
7505 case SPE_BUILTIN_EVSTDHX
:
7506 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, arglist
);
7507 case SPE_BUILTIN_EVSTDWX
:
7508 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, arglist
);
7509 case SPE_BUILTIN_EVSTWHEX
:
7510 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, arglist
);
7511 case SPE_BUILTIN_EVSTWHOX
:
7512 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, arglist
);
7513 case SPE_BUILTIN_EVSTWWEX
:
7514 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, arglist
);
7515 case SPE_BUILTIN_EVSTWWOX
:
7516 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, arglist
);
7517 case SPE_BUILTIN_EVSTDD
:
7518 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, arglist
);
7519 case SPE_BUILTIN_EVSTDH
:
7520 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, arglist
);
7521 case SPE_BUILTIN_EVSTDW
:
7522 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, arglist
);
7523 case SPE_BUILTIN_EVSTWHE
:
7524 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, arglist
);
7525 case SPE_BUILTIN_EVSTWHO
:
7526 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, arglist
);
7527 case SPE_BUILTIN_EVSTWWE
:
7528 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, arglist
);
7529 case SPE_BUILTIN_EVSTWWO
:
7530 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, arglist
);
7531 case SPE_BUILTIN_MFSPEFSCR
:
7532 icode
= CODE_FOR_spe_mfspefscr
;
7533 tmode
= insn_data
[icode
].operand
[0].mode
;
7536 || GET_MODE (target
) != tmode
7537 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7538 target
= gen_reg_rtx (tmode
);
7540 pat
= GEN_FCN (icode
) (target
);
7545 case SPE_BUILTIN_MTSPEFSCR
:
7546 icode
= CODE_FOR_spe_mtspefscr
;
7547 arg0
= TREE_VALUE (arglist
);
7548 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7549 mode0
= insn_data
[icode
].operand
[0].mode
;
7551 if (arg0
== error_mark_node
)
7554 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7555 op0
= copy_to_mode_reg (mode0
, op0
);
7557 pat
= GEN_FCN (icode
) (op0
);
7570 spe_expand_predicate_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7572 rtx pat
, scratch
, tmp
;
7573 tree form
= TREE_VALUE (arglist
);
7574 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
7575 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7576 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7577 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7578 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7579 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7583 if (TREE_CODE (form
) != INTEGER_CST
)
7585 error ("argument 1 of __builtin_spe_predicate must be a constant");
7589 form_int
= TREE_INT_CST_LOW (form
);
7594 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7598 || GET_MODE (target
) != SImode
7599 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
7600 target
= gen_reg_rtx (SImode
);
7602 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7603 op0
= copy_to_mode_reg (mode0
, op0
);
7604 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7605 op1
= copy_to_mode_reg (mode1
, op1
);
7607 scratch
= gen_reg_rtx (CCmode
);
7609 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7614 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7615 _lower_. We use one compare, but look in different bits of the
7616 CR for each variant.
7618 There are 2 elements in each SPE simd type (upper/lower). The CR
7619 bits are set as follows:
7621 BIT0 | BIT 1 | BIT 2 | BIT 3
7622 U | L | (U | L) | (U & L)
7624 So, for an "all" relationship, BIT 3 would be set.
7625 For an "any" relationship, BIT 2 would be set. Etc.
7627 Following traditional nomenclature, these bits map to:
7629 BIT0 | BIT 1 | BIT 2 | BIT 3
7632 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7637 /* All variant. OV bit. */
7639 /* We need to get to the OV bit, which is the ORDERED bit. We
7640 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7641 that's ugly and will trigger a validate_condition_mode abort.
7642 So let's just use another pattern. */
7643 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
7645 /* Any variant. EQ bit. */
7649 /* Upper variant. LT bit. */
7653 /* Lower variant. GT bit. */
7658 error ("argument 1 of __builtin_spe_predicate is out of range");
7662 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
7663 emit_move_insn (target
, tmp
);
7668 /* The evsel builtins look like this:
7670 e = __builtin_spe_evsel_OP (a, b, c, d);
7674 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7675 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7679 spe_expand_evsel_builtin (enum insn_code icode
, tree arglist
, rtx target
)
7682 tree arg0
= TREE_VALUE (arglist
);
7683 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7684 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
7685 tree arg3
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist
))));
7686 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
7687 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
7688 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
7689 rtx op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
7690 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7691 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7696 if (arg0
== error_mark_node
|| arg1
== error_mark_node
7697 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
7701 || GET_MODE (target
) != mode0
7702 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
7703 target
= gen_reg_rtx (mode0
);
7705 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7706 op0
= copy_to_mode_reg (mode0
, op0
);
7707 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7708 op1
= copy_to_mode_reg (mode0
, op1
);
7709 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
7710 op2
= copy_to_mode_reg (mode0
, op2
);
7711 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
7712 op3
= copy_to_mode_reg (mode0
, op3
);
7714 /* Generate the compare. */
7715 scratch
= gen_reg_rtx (CCmode
);
7716 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
7721 if (mode0
== V2SImode
)
7722 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
7724 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
7729 /* Expand an expression EXP that calls a built-in function,
7730 with result going to TARGET if that's convenient
7731 (and in mode MODE if that's convenient).
7732 SUBTARGET may be used as the target for computing one of EXP's operands.
7733 IGNORE is nonzero if the value is to be ignored. */
7736 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
7737 enum machine_mode mode ATTRIBUTE_UNUSED
,
7738 int ignore ATTRIBUTE_UNUSED
)
7740 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7741 tree arglist
= TREE_OPERAND (exp
, 1);
7742 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7743 struct builtin_description
*d
;
7748 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
7749 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7751 int icode
= (int) CODE_FOR_altivec_lvsr
;
7752 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7753 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
7757 if (!TARGET_ALTIVEC
)
7760 arg
= TREE_VALUE (arglist
);
7761 if (TREE_CODE (TREE_TYPE (arg
)) != POINTER_TYPE
)
7763 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
7764 addr
= memory_address (mode
, op
);
7765 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7769 /* For the load case need to negate the address. */
7770 op
= gen_reg_rtx (GET_MODE (addr
));
7771 emit_insn (gen_rtx_SET (VOIDmode
, op
,
7772 gen_rtx_NEG (GET_MODE (addr
), addr
)));
7774 op
= gen_rtx_MEM (mode
, op
);
7777 || GET_MODE (target
) != tmode
7778 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7779 target
= gen_reg_rtx (tmode
);
7781 /*pat = gen_altivec_lvsr (target, op);*/
7782 pat
= GEN_FCN (icode
) (target
, op
);
7792 ret
= altivec_expand_builtin (exp
, target
, &success
);
7799 ret
= spe_expand_builtin (exp
, target
, &success
);
7805 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7807 /* Handle simple unary operations. */
7808 d
= (struct builtin_description
*) bdesc_1arg
;
7809 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
7810 if (d
->code
== fcode
)
7811 return rs6000_expand_unop_builtin (d
->icode
, arglist
, target
);
7813 /* Handle simple binary operations. */
7814 d
= (struct builtin_description
*) bdesc_2arg
;
7815 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
7816 if (d
->code
== fcode
)
7817 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7819 /* Handle simple ternary operations. */
7820 d
= (struct builtin_description
*) bdesc_3arg
;
7821 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
7822 if (d
->code
== fcode
)
7823 return rs6000_expand_ternop_builtin (d
->icode
, arglist
, target
);
7831 build_opaque_vector_type (tree node
, int nunits
)
7833 node
= copy_node (node
);
7834 TYPE_MAIN_VARIANT (node
) = node
;
7835 return build_vector_type (node
, nunits
);
7839 rs6000_init_builtins (void)
7841 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
7842 V2SF_type_node
= build_vector_type (float_type_node
, 2);
7843 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
7844 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
7845 V4SF_type_node
= build_vector_type (float_type_node
, 4);
7846 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
7847 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
7849 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
7850 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
7851 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
7853 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
7854 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
7855 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
7857 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7858 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7859 'vector unsigned short'. */
7861 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
7862 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7863 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
7864 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7866 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7867 get_identifier ("__bool char"),
7868 bool_char_type_node
));
7869 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7870 get_identifier ("__bool short"),
7871 bool_short_type_node
));
7872 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7873 get_identifier ("__bool int"),
7874 bool_int_type_node
));
7875 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7876 get_identifier ("__pixel"),
7879 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
7880 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
7881 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
7882 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
7884 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7885 get_identifier ("__vector unsigned char"),
7886 unsigned_V16QI_type_node
));
7887 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7888 get_identifier ("__vector signed char"),
7890 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7891 get_identifier ("__vector __bool char"),
7892 bool_V16QI_type_node
));
7894 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7895 get_identifier ("__vector unsigned short"),
7896 unsigned_V8HI_type_node
));
7897 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7898 get_identifier ("__vector signed short"),
7900 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7901 get_identifier ("__vector __bool short"),
7902 bool_V8HI_type_node
));
7904 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7905 get_identifier ("__vector unsigned int"),
7906 unsigned_V4SI_type_node
));
7907 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7908 get_identifier ("__vector signed int"),
7910 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7911 get_identifier ("__vector __bool int"),
7912 bool_V4SI_type_node
));
7914 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7915 get_identifier ("__vector float"),
7917 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7918 get_identifier ("__vector __pixel"),
7919 pixel_V8HI_type_node
));
7922 spe_init_builtins ();
7924 altivec_init_builtins ();
7925 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7926 rs6000_common_init_builtins ();
7929 /* Search through a set of builtins and enable the mask bits.
7930 DESC is an array of builtins.
7931 SIZE is the total number of builtins.
7932 START is the builtin enum at which to start.
7933 END is the builtin enum at which to end. */
7935 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
7936 enum rs6000_builtins start
,
7937 enum rs6000_builtins end
)
7941 for (i
= 0; i
< size
; ++i
)
7942 if (desc
[i
].code
== start
)
7948 for (; i
< size
; ++i
)
7950 /* Flip all the bits on. */
7951 desc
[i
].mask
= target_flags
;
7952 if (desc
[i
].code
== end
)
7958 spe_init_builtins (void)
7960 tree endlink
= void_list_node
;
7961 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
7962 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
7963 struct builtin_description
*d
;
7966 tree v2si_ftype_4_v2si
7967 = build_function_type
7968 (opaque_V2SI_type_node
,
7969 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7970 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7971 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7972 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7975 tree v2sf_ftype_4_v2sf
7976 = build_function_type
7977 (opaque_V2SF_type_node
,
7978 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7979 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7980 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7981 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7984 tree int_ftype_int_v2si_v2si
7985 = build_function_type
7987 tree_cons (NULL_TREE
, integer_type_node
,
7988 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7989 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7992 tree int_ftype_int_v2sf_v2sf
7993 = build_function_type
7995 tree_cons (NULL_TREE
, integer_type_node
,
7996 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7997 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8000 tree void_ftype_v2si_puint_int
8001 = build_function_type (void_type_node
,
8002 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8003 tree_cons (NULL_TREE
, puint_type_node
,
8004 tree_cons (NULL_TREE
,
8008 tree void_ftype_v2si_puint_char
8009 = build_function_type (void_type_node
,
8010 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8011 tree_cons (NULL_TREE
, puint_type_node
,
8012 tree_cons (NULL_TREE
,
8016 tree void_ftype_v2si_pv2si_int
8017 = build_function_type (void_type_node
,
8018 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8019 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8020 tree_cons (NULL_TREE
,
8024 tree void_ftype_v2si_pv2si_char
8025 = build_function_type (void_type_node
,
8026 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8027 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8028 tree_cons (NULL_TREE
,
8033 = build_function_type (void_type_node
,
8034 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
8037 = build_function_type (integer_type_node
, endlink
);
8039 tree v2si_ftype_pv2si_int
8040 = build_function_type (opaque_V2SI_type_node
,
8041 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
8042 tree_cons (NULL_TREE
, integer_type_node
,
8045 tree v2si_ftype_puint_int
8046 = build_function_type (opaque_V2SI_type_node
,
8047 tree_cons (NULL_TREE
, puint_type_node
,
8048 tree_cons (NULL_TREE
, integer_type_node
,
8051 tree v2si_ftype_pushort_int
8052 = build_function_type (opaque_V2SI_type_node
,
8053 tree_cons (NULL_TREE
, pushort_type_node
,
8054 tree_cons (NULL_TREE
, integer_type_node
,
8057 tree v2si_ftype_signed_char
8058 = build_function_type (opaque_V2SI_type_node
,
8059 tree_cons (NULL_TREE
, signed_char_type_node
,
8062 /* The initialization of the simple binary and unary builtins is
8063 done in rs6000_common_init_builtins, but we have to enable the
8064 mask bits here manually because we have run out of `target_flags'
8065 bits. We really need to redesign this mask business. */
8067 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
8068 ARRAY_SIZE (bdesc_2arg
),
8071 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
8072 ARRAY_SIZE (bdesc_1arg
),
8074 SPE_BUILTIN_EVSUBFUSIAAW
);
8075 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
8076 ARRAY_SIZE (bdesc_spe_predicates
),
8077 SPE_BUILTIN_EVCMPEQ
,
8078 SPE_BUILTIN_EVFSTSTLT
);
8079 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
8080 ARRAY_SIZE (bdesc_spe_evsel
),
8081 SPE_BUILTIN_EVSEL_CMPGTS
,
8082 SPE_BUILTIN_EVSEL_FSTSTEQ
);
8084 (*lang_hooks
.decls
.pushdecl
)
8085 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
8086 opaque_V2SI_type_node
));
8088 /* Initialize irregular SPE builtins. */
8090 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
8091 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
8092 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
8093 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
8094 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
8095 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
8096 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
8097 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
8098 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
8099 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
8100 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
8101 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
8102 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
8103 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
8104 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
8105 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
8106 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
8107 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
8110 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
8111 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
8112 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
8113 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
8114 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
8115 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
8116 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
8117 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
8118 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
8119 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
8120 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
8121 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
8122 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
8123 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
8124 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
8125 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
8126 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
8127 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
8128 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
8129 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
8130 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
8131 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
8134 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8135 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
8139 switch (insn_data
[d
->icode
].operand
[1].mode
)
8142 type
= int_ftype_int_v2si_v2si
;
8145 type
= int_ftype_int_v2sf_v2sf
;
8151 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8154 /* Evsel predicates. */
8155 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8156 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
8160 switch (insn_data
[d
->icode
].operand
[1].mode
)
8163 type
= v2si_ftype_4_v2si
;
8166 type
= v2sf_ftype_4_v2sf
;
8172 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8177 altivec_init_builtins (void)
8179 struct builtin_description
*d
;
8180 struct builtin_description_predicates
*dp
;
8182 tree pfloat_type_node
= build_pointer_type (float_type_node
);
8183 tree pint_type_node
= build_pointer_type (integer_type_node
);
8184 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
8185 tree pchar_type_node
= build_pointer_type (char_type_node
);
8187 tree pvoid_type_node
= build_pointer_type (void_type_node
);
8189 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
8190 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
8191 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
8192 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
8194 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
8196 tree int_ftype_int_v4si_v4si
8197 = build_function_type_list (integer_type_node
,
8198 integer_type_node
, V4SI_type_node
,
8199 V4SI_type_node
, NULL_TREE
);
8200 tree v4sf_ftype_pcfloat
8201 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
8202 tree void_ftype_pfloat_v4sf
8203 = build_function_type_list (void_type_node
,
8204 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
8205 tree v4si_ftype_pcint
8206 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
8207 tree void_ftype_pint_v4si
8208 = build_function_type_list (void_type_node
,
8209 pint_type_node
, V4SI_type_node
, NULL_TREE
);
8210 tree v8hi_ftype_pcshort
8211 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
8212 tree void_ftype_pshort_v8hi
8213 = build_function_type_list (void_type_node
,
8214 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
8215 tree v16qi_ftype_pcchar
8216 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
8217 tree void_ftype_pchar_v16qi
8218 = build_function_type_list (void_type_node
,
8219 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
8220 tree void_ftype_v4si
8221 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
8222 tree v8hi_ftype_void
8223 = build_function_type (V8HI_type_node
, void_list_node
);
8224 tree void_ftype_void
8225 = build_function_type (void_type_node
, void_list_node
);
8227 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
8229 tree v16qi_ftype_long_pcvoid
8230 = build_function_type_list (V16QI_type_node
,
8231 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8232 tree v8hi_ftype_long_pcvoid
8233 = build_function_type_list (V8HI_type_node
,
8234 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8235 tree v4si_ftype_long_pcvoid
8236 = build_function_type_list (V4SI_type_node
,
8237 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
8239 tree void_ftype_v4si_long_pvoid
8240 = build_function_type_list (void_type_node
,
8241 V4SI_type_node
, long_integer_type_node
,
8242 pvoid_type_node
, NULL_TREE
);
8243 tree void_ftype_v16qi_long_pvoid
8244 = build_function_type_list (void_type_node
,
8245 V16QI_type_node
, long_integer_type_node
,
8246 pvoid_type_node
, NULL_TREE
);
8247 tree void_ftype_v8hi_long_pvoid
8248 = build_function_type_list (void_type_node
,
8249 V8HI_type_node
, long_integer_type_node
,
8250 pvoid_type_node
, NULL_TREE
);
8251 tree int_ftype_int_v8hi_v8hi
8252 = build_function_type_list (integer_type_node
,
8253 integer_type_node
, V8HI_type_node
,
8254 V8HI_type_node
, NULL_TREE
);
8255 tree int_ftype_int_v16qi_v16qi
8256 = build_function_type_list (integer_type_node
,
8257 integer_type_node
, V16QI_type_node
,
8258 V16QI_type_node
, NULL_TREE
);
8259 tree int_ftype_int_v4sf_v4sf
8260 = build_function_type_list (integer_type_node
,
8261 integer_type_node
, V4SF_type_node
,
8262 V4SF_type_node
, NULL_TREE
);
8263 tree v4si_ftype_v4si
8264 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8265 tree v8hi_ftype_v8hi
8266 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8267 tree v16qi_ftype_v16qi
8268 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8269 tree v4sf_ftype_v4sf
8270 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8271 tree void_ftype_pcvoid_int_int
8272 = build_function_type_list (void_type_node
,
8273 pcvoid_type_node
, integer_type_node
,
8274 integer_type_node
, NULL_TREE
);
8275 tree int_ftype_pcchar
8276 = build_function_type_list (integer_type_node
,
8277 pcchar_type_node
, NULL_TREE
);
8279 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
8280 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
8281 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
8282 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
8283 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
8284 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
8285 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
8286 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
8287 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
8288 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
8289 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
8290 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
8291 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
8292 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
8293 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
8294 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
8295 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
8296 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
8297 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
8298 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
8299 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
8300 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
8301 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
8302 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
8303 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
8304 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
8305 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
8306 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
8307 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
8308 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
8309 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
8310 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
8312 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
8313 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_compiletime_error", int_ftype_pcchar
,
8314 ALTIVEC_BUILTIN_COMPILETIME_ERROR
);
8316 /* Add the DST variants. */
8317 d
= (struct builtin_description
*) bdesc_dst
;
8318 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
8319 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
8321 /* Initialize the predicates. */
8322 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
8323 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8325 enum machine_mode mode1
;
8328 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
8333 type
= int_ftype_int_v4si_v4si
;
8336 type
= int_ftype_int_v8hi_v8hi
;
8339 type
= int_ftype_int_v16qi_v16qi
;
8342 type
= int_ftype_int_v4sf_v4sf
;
8348 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
8351 /* Initialize the abs* operators. */
8352 d
= (struct builtin_description
*) bdesc_abs
;
8353 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8355 enum machine_mode mode0
;
8358 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8363 type
= v4si_ftype_v4si
;
8366 type
= v8hi_ftype_v8hi
;
8369 type
= v16qi_ftype_v16qi
;
8372 type
= v4sf_ftype_v4sf
;
8378 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8385 /* Initialize target builtin that implements
8386 targetm.vectorize.builtin_mask_for_load. */
8388 decl
= lang_hooks
.builtin_function ("__builtin_altivec_mask_for_load",
8389 v16qi_ftype_long_pcvoid
,
8390 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
8391 BUILT_IN_MD
, NULL
, NULL_TREE
);
8392 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8393 altivec_builtin_mask_for_load
= decl
;
8398 rs6000_common_init_builtins (void)
8400 struct builtin_description
*d
;
8403 tree v4sf_ftype_v4sf_v4sf_v16qi
8404 = build_function_type_list (V4SF_type_node
,
8405 V4SF_type_node
, V4SF_type_node
,
8406 V16QI_type_node
, NULL_TREE
);
8407 tree v4si_ftype_v4si_v4si_v16qi
8408 = build_function_type_list (V4SI_type_node
,
8409 V4SI_type_node
, V4SI_type_node
,
8410 V16QI_type_node
, NULL_TREE
);
8411 tree v8hi_ftype_v8hi_v8hi_v16qi
8412 = build_function_type_list (V8HI_type_node
,
8413 V8HI_type_node
, V8HI_type_node
,
8414 V16QI_type_node
, NULL_TREE
);
8415 tree v16qi_ftype_v16qi_v16qi_v16qi
8416 = build_function_type_list (V16QI_type_node
,
8417 V16QI_type_node
, V16QI_type_node
,
8418 V16QI_type_node
, NULL_TREE
);
8420 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
8422 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
8423 tree v16qi_ftype_int
8424 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
8425 tree v8hi_ftype_v16qi
8426 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
8427 tree v4sf_ftype_v4sf
8428 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8430 tree v2si_ftype_v2si_v2si
8431 = build_function_type_list (opaque_V2SI_type_node
,
8432 opaque_V2SI_type_node
,
8433 opaque_V2SI_type_node
, NULL_TREE
);
8435 tree v2sf_ftype_v2sf_v2sf
8436 = build_function_type_list (opaque_V2SF_type_node
,
8437 opaque_V2SF_type_node
,
8438 opaque_V2SF_type_node
, NULL_TREE
);
8440 tree v2si_ftype_int_int
8441 = build_function_type_list (opaque_V2SI_type_node
,
8442 integer_type_node
, integer_type_node
,
8445 tree v2si_ftype_v2si
8446 = build_function_type_list (opaque_V2SI_type_node
,
8447 opaque_V2SI_type_node
, NULL_TREE
);
8449 tree v2sf_ftype_v2sf
8450 = build_function_type_list (opaque_V2SF_type_node
,
8451 opaque_V2SF_type_node
, NULL_TREE
);
8453 tree v2sf_ftype_v2si
8454 = build_function_type_list (opaque_V2SF_type_node
,
8455 opaque_V2SI_type_node
, NULL_TREE
);
8457 tree v2si_ftype_v2sf
8458 = build_function_type_list (opaque_V2SI_type_node
,
8459 opaque_V2SF_type_node
, NULL_TREE
);
8461 tree v2si_ftype_v2si_char
8462 = build_function_type_list (opaque_V2SI_type_node
,
8463 opaque_V2SI_type_node
,
8464 char_type_node
, NULL_TREE
);
8466 tree v2si_ftype_int_char
8467 = build_function_type_list (opaque_V2SI_type_node
,
8468 integer_type_node
, char_type_node
, NULL_TREE
);
8470 tree v2si_ftype_char
8471 = build_function_type_list (opaque_V2SI_type_node
,
8472 char_type_node
, NULL_TREE
);
8474 tree int_ftype_int_int
8475 = build_function_type_list (integer_type_node
,
8476 integer_type_node
, integer_type_node
,
8479 tree v4si_ftype_v4si_v4si
8480 = build_function_type_list (V4SI_type_node
,
8481 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8482 tree v4sf_ftype_v4si_int
8483 = build_function_type_list (V4SF_type_node
,
8484 V4SI_type_node
, integer_type_node
, NULL_TREE
);
8485 tree v4si_ftype_v4sf_int
8486 = build_function_type_list (V4SI_type_node
,
8487 V4SF_type_node
, integer_type_node
, NULL_TREE
);
8488 tree v4si_ftype_v4si_int
8489 = build_function_type_list (V4SI_type_node
,
8490 V4SI_type_node
, integer_type_node
, NULL_TREE
);
8491 tree v8hi_ftype_v8hi_int
8492 = build_function_type_list (V8HI_type_node
,
8493 V8HI_type_node
, integer_type_node
, NULL_TREE
);
8494 tree v16qi_ftype_v16qi_int
8495 = build_function_type_list (V16QI_type_node
,
8496 V16QI_type_node
, integer_type_node
, NULL_TREE
);
8497 tree v16qi_ftype_v16qi_v16qi_int
8498 = build_function_type_list (V16QI_type_node
,
8499 V16QI_type_node
, V16QI_type_node
,
8500 integer_type_node
, NULL_TREE
);
8501 tree v8hi_ftype_v8hi_v8hi_int
8502 = build_function_type_list (V8HI_type_node
,
8503 V8HI_type_node
, V8HI_type_node
,
8504 integer_type_node
, NULL_TREE
);
8505 tree v4si_ftype_v4si_v4si_int
8506 = build_function_type_list (V4SI_type_node
,
8507 V4SI_type_node
, V4SI_type_node
,
8508 integer_type_node
, NULL_TREE
);
8509 tree v4sf_ftype_v4sf_v4sf_int
8510 = build_function_type_list (V4SF_type_node
,
8511 V4SF_type_node
, V4SF_type_node
,
8512 integer_type_node
, NULL_TREE
);
8513 tree v4sf_ftype_v4sf_v4sf
8514 = build_function_type_list (V4SF_type_node
,
8515 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8516 tree v4sf_ftype_v4sf_v4sf_v4si
8517 = build_function_type_list (V4SF_type_node
,
8518 V4SF_type_node
, V4SF_type_node
,
8519 V4SI_type_node
, NULL_TREE
);
8520 tree v4sf_ftype_v4sf_v4sf_v4sf
8521 = build_function_type_list (V4SF_type_node
,
8522 V4SF_type_node
, V4SF_type_node
,
8523 V4SF_type_node
, NULL_TREE
);
8524 tree v4si_ftype_v4si_v4si_v4si
8525 = build_function_type_list (V4SI_type_node
,
8526 V4SI_type_node
, V4SI_type_node
,
8527 V4SI_type_node
, NULL_TREE
);
8528 tree v8hi_ftype_v8hi_v8hi
8529 = build_function_type_list (V8HI_type_node
,
8530 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8531 tree v8hi_ftype_v8hi_v8hi_v8hi
8532 = build_function_type_list (V8HI_type_node
,
8533 V8HI_type_node
, V8HI_type_node
,
8534 V8HI_type_node
, NULL_TREE
);
8535 tree v4si_ftype_v8hi_v8hi_v4si
8536 = build_function_type_list (V4SI_type_node
,
8537 V8HI_type_node
, V8HI_type_node
,
8538 V4SI_type_node
, NULL_TREE
);
8539 tree v4si_ftype_v16qi_v16qi_v4si
8540 = build_function_type_list (V4SI_type_node
,
8541 V16QI_type_node
, V16QI_type_node
,
8542 V4SI_type_node
, NULL_TREE
);
8543 tree v16qi_ftype_v16qi_v16qi
8544 = build_function_type_list (V16QI_type_node
,
8545 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8546 tree v4si_ftype_v4sf_v4sf
8547 = build_function_type_list (V4SI_type_node
,
8548 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8549 tree v8hi_ftype_v16qi_v16qi
8550 = build_function_type_list (V8HI_type_node
,
8551 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8552 tree v4si_ftype_v8hi_v8hi
8553 = build_function_type_list (V4SI_type_node
,
8554 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8555 tree v8hi_ftype_v4si_v4si
8556 = build_function_type_list (V8HI_type_node
,
8557 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8558 tree v16qi_ftype_v8hi_v8hi
8559 = build_function_type_list (V16QI_type_node
,
8560 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8561 tree v4si_ftype_v16qi_v4si
8562 = build_function_type_list (V4SI_type_node
,
8563 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
8564 tree v4si_ftype_v16qi_v16qi
8565 = build_function_type_list (V4SI_type_node
,
8566 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8567 tree v4si_ftype_v8hi_v4si
8568 = build_function_type_list (V4SI_type_node
,
8569 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
8570 tree v4si_ftype_v8hi
8571 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
8572 tree int_ftype_v4si_v4si
8573 = build_function_type_list (integer_type_node
,
8574 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
8575 tree int_ftype_v4sf_v4sf
8576 = build_function_type_list (integer_type_node
,
8577 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
8578 tree int_ftype_v16qi_v16qi
8579 = build_function_type_list (integer_type_node
,
8580 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
8581 tree int_ftype_v8hi_v8hi
8582 = build_function_type_list (integer_type_node
,
8583 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
8585 /* Add the simple ternary operators. */
8586 d
= (struct builtin_description
*) bdesc_3arg
;
8587 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
8590 enum machine_mode mode0
, mode1
, mode2
, mode3
;
8593 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8596 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8597 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8598 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8599 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
8601 /* When all four are of the same mode. */
8602 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
8607 type
= v4si_ftype_v4si_v4si_v4si
;
8610 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
8613 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
8616 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8622 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
8627 type
= v4si_ftype_v4si_v4si_v16qi
;
8630 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
8633 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
8636 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
8642 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
8643 && mode3
== V4SImode
)
8644 type
= v4si_ftype_v16qi_v16qi_v4si
;
8645 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
8646 && mode3
== V4SImode
)
8647 type
= v4si_ftype_v8hi_v8hi_v4si
;
8648 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
8649 && mode3
== V4SImode
)
8650 type
= v4sf_ftype_v4sf_v4sf_v4si
;
8652 /* vchar, vchar, vchar, 4 bit literal. */
8653 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
8655 type
= v16qi_ftype_v16qi_v16qi_int
;
8657 /* vshort, vshort, vshort, 4 bit literal. */
8658 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
8660 type
= v8hi_ftype_v8hi_v8hi_int
;
8662 /* vint, vint, vint, 4 bit literal. */
8663 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
8665 type
= v4si_ftype_v4si_v4si_int
;
8667 /* vfloat, vfloat, vfloat, 4 bit literal. */
8668 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
8670 type
= v4sf_ftype_v4sf_v4sf_int
;
8675 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8678 /* Add the simple binary operators. */
8679 d
= (struct builtin_description
*) bdesc_2arg
;
8680 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
8682 enum machine_mode mode0
, mode1
, mode2
;
8685 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8688 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8689 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8690 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8692 /* When all three operands are of the same mode. */
8693 if (mode0
== mode1
&& mode1
== mode2
)
8698 type
= v4sf_ftype_v4sf_v4sf
;
8701 type
= v4si_ftype_v4si_v4si
;
8704 type
= v16qi_ftype_v16qi_v16qi
;
8707 type
= v8hi_ftype_v8hi_v8hi
;
8710 type
= v2si_ftype_v2si_v2si
;
8713 type
= v2sf_ftype_v2sf_v2sf
;
8716 type
= int_ftype_int_int
;
8723 /* A few other combos we really don't want to do manually. */
8725 /* vint, vfloat, vfloat. */
8726 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
8727 type
= v4si_ftype_v4sf_v4sf
;
8729 /* vshort, vchar, vchar. */
8730 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8731 type
= v8hi_ftype_v16qi_v16qi
;
8733 /* vint, vshort, vshort. */
8734 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8735 type
= v4si_ftype_v8hi_v8hi
;
8737 /* vshort, vint, vint. */
8738 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
8739 type
= v8hi_ftype_v4si_v4si
;
8741 /* vchar, vshort, vshort. */
8742 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8743 type
= v16qi_ftype_v8hi_v8hi
;
8745 /* vint, vchar, vint. */
8746 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
8747 type
= v4si_ftype_v16qi_v4si
;
8749 /* vint, vchar, vchar. */
8750 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8751 type
= v4si_ftype_v16qi_v16qi
;
8753 /* vint, vshort, vint. */
8754 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
8755 type
= v4si_ftype_v8hi_v4si
;
8757 /* vint, vint, 5 bit literal. */
8758 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
8759 type
= v4si_ftype_v4si_int
;
8761 /* vshort, vshort, 5 bit literal. */
8762 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
8763 type
= v8hi_ftype_v8hi_int
;
8765 /* vchar, vchar, 5 bit literal. */
8766 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
8767 type
= v16qi_ftype_v16qi_int
;
8769 /* vfloat, vint, 5 bit literal. */
8770 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
8771 type
= v4sf_ftype_v4si_int
;
8773 /* vint, vfloat, 5 bit literal. */
8774 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
8775 type
= v4si_ftype_v4sf_int
;
8777 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
8778 type
= v2si_ftype_int_int
;
8780 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
8781 type
= v2si_ftype_v2si_char
;
8783 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
8784 type
= v2si_ftype_int_char
;
8787 else if (mode0
== SImode
)
8792 type
= int_ftype_v4si_v4si
;
8795 type
= int_ftype_v4sf_v4sf
;
8798 type
= int_ftype_v16qi_v16qi
;
8801 type
= int_ftype_v8hi_v8hi
;
8811 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8814 /* Add the simple unary operators. */
8815 d
= (struct builtin_description
*) bdesc_1arg
;
8816 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
8818 enum machine_mode mode0
, mode1
;
8821 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8824 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8825 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8827 if (mode0
== V4SImode
&& mode1
== QImode
)
8828 type
= v4si_ftype_int
;
8829 else if (mode0
== V8HImode
&& mode1
== QImode
)
8830 type
= v8hi_ftype_int
;
8831 else if (mode0
== V16QImode
&& mode1
== QImode
)
8832 type
= v16qi_ftype_int
;
8833 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
8834 type
= v4sf_ftype_v4sf
;
8835 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
8836 type
= v8hi_ftype_v16qi
;
8837 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
8838 type
= v4si_ftype_v8hi
;
8839 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
8840 type
= v2si_ftype_v2si
;
8841 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
8842 type
= v2sf_ftype_v2sf
;
8843 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
8844 type
= v2sf_ftype_v2si
;
8845 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
8846 type
= v2si_ftype_v2sf
;
8847 else if (mode0
== V2SImode
&& mode1
== QImode
)
8848 type
= v2si_ftype_char
;
8852 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8857 rs6000_init_libfuncs (void)
8859 if (!TARGET_HARD_FLOAT
)
8862 if (DEFAULT_ABI
!= ABI_V4
)
8864 if (TARGET_XCOFF
&& ! TARGET_POWER2
&& ! TARGET_POWERPC
)
8866 /* AIX library routines for float->int conversion. */
8867 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
8868 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
8869 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
8870 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
8873 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8874 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
8875 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
8876 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
8877 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
8881 /* 32-bit SVR4 quad floating point routines. */
8883 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
8884 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
8885 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
8886 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
8887 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
8888 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
8889 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
8891 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
8892 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
8893 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
8894 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
8895 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
8896 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
8898 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
8899 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
8900 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
8901 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
8902 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
8903 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
8904 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
8909 /* Expand a block clear operation, and return 1 if successful. Return 0
8910 if we should let the compiler generate normal code.
8912 operands[0] is the destination
8913 operands[1] is the length
8914 operands[2] is the alignment */
8917 expand_block_clear (rtx operands
[])
8919 rtx orig_dest
= operands
[0];
8920 rtx bytes_rtx
= operands
[1];
8921 rtx align_rtx
= operands
[2];
8922 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
8923 HOST_WIDE_INT align
;
8924 HOST_WIDE_INT bytes
;
8929 /* If this is not a fixed size move, just call memcpy */
8933 /* If this is not a fixed size alignment, abort */
8934 if (GET_CODE (align_rtx
) != CONST_INT
)
8936 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
8938 /* Anything to clear? */
8939 bytes
= INTVAL (bytes_rtx
);
8943 /* Use the builtin memset after a point, to avoid huge code bloat.
8944 When optimize_size, avoid any significant code bloat; calling
8945 memset is about 4 instructions, so allow for one instruction to
8946 load zero and three to do clearing. */
8947 if (TARGET_ALTIVEC
&& align
>= 128)
8949 else if (TARGET_POWERPC64
&& align
>= 32)
8954 if (optimize_size
&& bytes
> 3 * clear_step
)
8956 if (! optimize_size
&& bytes
> 8 * clear_step
)
8959 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
8961 enum machine_mode mode
= BLKmode
;
8964 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
8969 else if (bytes
>= 8 && TARGET_POWERPC64
8970 /* 64-bit loads and stores require word-aligned
8972 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
8977 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
8978 { /* move 4 bytes */
8982 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
8983 { /* move 2 bytes */
8987 else /* move 1 byte at a time */
8993 dest
= adjust_address (orig_dest
, mode
, offset
);
8995 emit_move_insn (dest
, CONST0_RTX (mode
));
9002 /* Expand a block move operation, and return 1 if successful. Return 0
9003 if we should let the compiler generate normal code.
9005 operands[0] is the destination
9006 operands[1] is the source
9007 operands[2] is the length
9008 operands[3] is the alignment */
9010 #define MAX_MOVE_REG 4
9013 expand_block_move (rtx operands
[])
9015 rtx orig_dest
= operands
[0];
9016 rtx orig_src
= operands
[1];
9017 rtx bytes_rtx
= operands
[2];
9018 rtx align_rtx
= operands
[3];
9019 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
9024 rtx stores
[MAX_MOVE_REG
];
9027 /* If this is not a fixed size move, just call memcpy */
9031 /* If this is not a fixed size alignment, abort */
9032 if (GET_CODE (align_rtx
) != CONST_INT
)
9034 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
9036 /* Anything to move? */
9037 bytes
= INTVAL (bytes_rtx
);
9041 /* store_one_arg depends on expand_block_move to handle at least the size of
9042 reg_parm_stack_space. */
9043 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
9046 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
9049 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
9050 rtx (*mov
) (rtx
, rtx
);
9052 enum machine_mode mode
= BLKmode
;
9055 /* Altivec first, since it will be faster than a string move
9056 when it applies, and usually not significantly larger. */
9057 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
9061 gen_func
.mov
= gen_movv4si
;
9063 else if (TARGET_STRING
9064 && bytes
> 24 /* move up to 32 bytes at a time */
9072 && ! fixed_regs
[12])
9074 move_bytes
= (bytes
> 32) ? 32 : bytes
;
9075 gen_func
.movmemsi
= gen_movmemsi_8reg
;
9077 else if (TARGET_STRING
9078 && bytes
> 16 /* move up to 24 bytes at a time */
9084 && ! fixed_regs
[10])
9086 move_bytes
= (bytes
> 24) ? 24 : bytes
;
9087 gen_func
.movmemsi
= gen_movmemsi_6reg
;
9089 else if (TARGET_STRING
9090 && bytes
> 8 /* move up to 16 bytes at a time */
9096 move_bytes
= (bytes
> 16) ? 16 : bytes
;
9097 gen_func
.movmemsi
= gen_movmemsi_4reg
;
9099 else if (bytes
>= 8 && TARGET_POWERPC64
9100 /* 64-bit loads and stores require word-aligned
9102 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
9106 gen_func
.mov
= gen_movdi
;
9108 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
9109 { /* move up to 8 bytes at a time */
9110 move_bytes
= (bytes
> 8) ? 8 : bytes
;
9111 gen_func
.movmemsi
= gen_movmemsi_2reg
;
9113 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
9114 { /* move 4 bytes */
9117 gen_func
.mov
= gen_movsi
;
9119 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
9120 { /* move 2 bytes */
9123 gen_func
.mov
= gen_movhi
;
9125 else if (TARGET_STRING
&& bytes
> 1)
9126 { /* move up to 4 bytes at a time */
9127 move_bytes
= (bytes
> 4) ? 4 : bytes
;
9128 gen_func
.movmemsi
= gen_movmemsi_1reg
;
9130 else /* move 1 byte at a time */
9134 gen_func
.mov
= gen_movqi
;
9137 src
= adjust_address (orig_src
, mode
, offset
);
9138 dest
= adjust_address (orig_dest
, mode
, offset
);
9140 if (mode
!= BLKmode
)
9142 rtx tmp_reg
= gen_reg_rtx (mode
);
9144 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
9145 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
9148 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
9151 for (i
= 0; i
< num_reg
; i
++)
9152 emit_insn (stores
[i
]);
9156 if (mode
== BLKmode
)
9158 /* Move the address into scratch registers. The movmemsi
9159 patterns require zero offset. */
9160 if (!REG_P (XEXP (src
, 0)))
9162 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
9163 src
= replace_equiv_address (src
, src_reg
);
9165 set_mem_size (src
, GEN_INT (move_bytes
));
9167 if (!REG_P (XEXP (dest
, 0)))
9169 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
9170 dest
= replace_equiv_address (dest
, dest_reg
);
9172 set_mem_size (dest
, GEN_INT (move_bytes
));
9174 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
9175 GEN_INT (move_bytes
& 31),
9184 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9185 known to be a PARALLEL. */
9187 save_world_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9192 int count
= XVECLEN (op
, 0);
9198 if (GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9199 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
)
9202 for (i
=1; i
<= 18; i
++)
9204 elt
= XVECEXP (op
, 0, index
++);
9205 if (GET_CODE (elt
) != SET
9206 || GET_CODE (SET_DEST (elt
)) != MEM
9207 || ! memory_operand (SET_DEST (elt
), DFmode
)
9208 || GET_CODE (SET_SRC (elt
)) != REG
9209 || GET_MODE (SET_SRC (elt
)) != DFmode
)
9213 for (i
=1; i
<= 12; i
++)
9215 elt
= XVECEXP (op
, 0, index
++);
9216 if (GET_CODE (elt
) != SET
9217 || GET_CODE (SET_DEST (elt
)) != MEM
9218 || GET_CODE (SET_SRC (elt
)) != REG
9219 || GET_MODE (SET_SRC (elt
)) != V4SImode
)
9223 for (i
=1; i
<= 19; i
++)
9225 elt
= XVECEXP (op
, 0, index
++);
9226 if (GET_CODE (elt
) != SET
9227 || GET_CODE (SET_DEST (elt
)) != MEM
9228 || ! memory_operand (SET_DEST (elt
), Pmode
)
9229 || GET_CODE (SET_SRC (elt
)) != REG
9230 || GET_MODE (SET_SRC (elt
)) != Pmode
)
9234 elt
= XVECEXP (op
, 0, index
++);
9235 if (GET_CODE (elt
) != SET
9236 || GET_CODE (SET_DEST (elt
)) != MEM
9237 || ! memory_operand (SET_DEST (elt
), Pmode
)
9238 || GET_CODE (SET_SRC (elt
)) != REG
9239 || REGNO (SET_SRC (elt
)) != CR2_REGNO
9240 || GET_MODE (SET_SRC (elt
)) != Pmode
)
9243 if (GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9244 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9245 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
)
9250 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9251 known to be a PARALLEL. */
9253 restore_world_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9258 int count
= XVECLEN (op
, 0);
9264 if (GET_CODE (XVECEXP (op
, 0, index
++)) != RETURN
9265 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9266 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
9267 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
)
9270 elt
= XVECEXP (op
, 0, index
++);
9271 if (GET_CODE (elt
) != SET
9272 || GET_CODE (SET_SRC (elt
)) != MEM
9273 || ! memory_operand (SET_SRC (elt
), Pmode
)
9274 || GET_CODE (SET_DEST (elt
)) != REG
9275 || REGNO (SET_DEST (elt
)) != CR2_REGNO
9276 || GET_MODE (SET_DEST (elt
)) != Pmode
)
9279 for (i
=1; i
<= 19; i
++)
9281 elt
= XVECEXP (op
, 0, index
++);
9282 if (GET_CODE (elt
) != SET
9283 || GET_CODE (SET_SRC (elt
)) != MEM
9284 || ! memory_operand (SET_SRC (elt
), Pmode
)
9285 || GET_CODE (SET_DEST (elt
)) != REG
9286 || GET_MODE (SET_DEST (elt
)) != Pmode
)
9290 for (i
=1; i
<= 12; i
++)
9292 elt
= XVECEXP (op
, 0, index
++);
9293 if (GET_CODE (elt
) != SET
9294 || GET_CODE (SET_SRC (elt
)) != MEM
9295 || GET_CODE (SET_DEST (elt
)) != REG
9296 || GET_MODE (SET_DEST (elt
)) != V4SImode
)
9300 for (i
=1; i
<= 18; i
++)
9302 elt
= XVECEXP (op
, 0, index
++);
9303 if (GET_CODE (elt
) != SET
9304 || GET_CODE (SET_SRC (elt
)) != MEM
9305 || ! memory_operand (SET_SRC (elt
), DFmode
)
9306 || GET_CODE (SET_DEST (elt
)) != REG
9307 || GET_MODE (SET_DEST (elt
)) != DFmode
)
9311 if (GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9312 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9313 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9314 || GET_CODE (XVECEXP (op
, 0, index
++)) != CLOBBER
9315 || GET_CODE (XVECEXP (op
, 0, index
++)) != USE
)
9321 /* Return 1 if OP is a load multiple operation. It is known to be a
9322 PARALLEL and the first section will be tested. */
9325 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9327 int count
= XVECLEN (op
, 0);
9328 unsigned int dest_regno
;
9332 /* Perform a quick check so we don't blow up below. */
9334 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9335 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
9336 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
9339 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
9340 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
9342 for (i
= 1; i
< count
; i
++)
9344 rtx elt
= XVECEXP (op
, 0, i
);
9346 if (GET_CODE (elt
) != SET
9347 || GET_CODE (SET_DEST (elt
)) != REG
9348 || GET_MODE (SET_DEST (elt
)) != SImode
9349 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
9350 || GET_CODE (SET_SRC (elt
)) != MEM
9351 || GET_MODE (SET_SRC (elt
)) != SImode
9352 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
9353 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
9354 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
9355 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != i
* 4)
9362 /* Similar, but tests for store multiple. Here, the second vector element
9363 is a CLOBBER. It will be tested later. */
9366 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9368 int count
= XVECLEN (op
, 0) - 1;
9369 unsigned int src_regno
;
9373 /* Perform a quick check so we don't blow up below. */
9375 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9376 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
9377 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
9380 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
9381 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
9383 for (i
= 1; i
< count
; i
++)
9385 rtx elt
= XVECEXP (op
, 0, i
+ 1);
9387 if (GET_CODE (elt
) != SET
9388 || GET_CODE (SET_SRC (elt
)) != REG
9389 || GET_MODE (SET_SRC (elt
)) != SImode
9390 || REGNO (SET_SRC (elt
)) != src_regno
+ i
9391 || GET_CODE (SET_DEST (elt
)) != MEM
9392 || GET_MODE (SET_DEST (elt
)) != SImode
9393 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
9394 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
9395 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
9396 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != i
* 4)
9403 /* Return a string to perform a load_multiple operation.
9404 operands[0] is the vector.
9405 operands[1] is the source address.
9406 operands[2] is the first destination register. */
9409 rs6000_output_load_multiple (rtx operands
[3])
9411 /* We have to handle the case where the pseudo used to contain the address
9412 is assigned to one of the output registers. */
9414 int words
= XVECLEN (operands
[0], 0);
9417 if (XVECLEN (operands
[0], 0) == 1)
9418 return "{l|lwz} %2,0(%1)";
9420 for (i
= 0; i
< words
; i
++)
9421 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
9422 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
9426 xop
[0] = GEN_INT (4 * (words
-1));
9427 xop
[1] = operands
[1];
9428 xop
[2] = operands
[2];
9429 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
9434 xop
[0] = GEN_INT (4 * (words
-1));
9435 xop
[1] = operands
[1];
9436 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
9437 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
9442 for (j
= 0; j
< words
; j
++)
9445 xop
[0] = GEN_INT (j
* 4);
9446 xop
[1] = operands
[1];
9447 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
9448 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
9450 xop
[0] = GEN_INT (i
* 4);
9451 xop
[1] = operands
[1];
9452 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
9457 return "{lsi|lswi} %2,%1,%N0";
9460 /* Return 1 for a parallel vrsave operation. */
9463 vrsave_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9465 int count
= XVECLEN (op
, 0);
9466 unsigned int dest_regno
, src_regno
;
9470 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9471 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
9472 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC_VOLATILE
)
9475 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
9476 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
9478 if (dest_regno
!= VRSAVE_REGNO
9479 && src_regno
!= VRSAVE_REGNO
)
9482 for (i
= 1; i
< count
; i
++)
9484 rtx elt
= XVECEXP (op
, 0, i
);
9486 if (GET_CODE (elt
) != CLOBBER
9487 && GET_CODE (elt
) != SET
)
9494 /* Return 1 for an PARALLEL suitable for mfcr. */
9497 mfcr_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9499 int count
= XVECLEN (op
, 0);
9502 /* Perform a quick check so we don't blow up below. */
9504 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9505 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
9506 || XVECLEN (SET_SRC (XVECEXP (op
, 0, 0)), 0) != 2)
9509 for (i
= 0; i
< count
; i
++)
9511 rtx exp
= XVECEXP (op
, 0, i
);
9516 src_reg
= XVECEXP (SET_SRC (exp
), 0, 0);
9518 if (GET_CODE (src_reg
) != REG
9519 || GET_MODE (src_reg
) != CCmode
9520 || ! CR_REGNO_P (REGNO (src_reg
)))
9523 if (GET_CODE (exp
) != SET
9524 || GET_CODE (SET_DEST (exp
)) != REG
9525 || GET_MODE (SET_DEST (exp
)) != SImode
9526 || ! INT_REGNO_P (REGNO (SET_DEST (exp
))))
9528 unspec
= SET_SRC (exp
);
9529 maskval
= 1 << (MAX_CR_REGNO
- REGNO (src_reg
));
9531 if (GET_CODE (unspec
) != UNSPEC
9532 || XINT (unspec
, 1) != UNSPEC_MOVESI_FROM_CR
9533 || XVECLEN (unspec
, 0) != 2
9534 || XVECEXP (unspec
, 0, 0) != src_reg
9535 || GET_CODE (XVECEXP (unspec
, 0, 1)) != CONST_INT
9536 || INTVAL (XVECEXP (unspec
, 0, 1)) != maskval
)
9542 /* Return 1 for an PARALLEL suitable for mtcrf. */
9545 mtcrf_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9547 int count
= XVECLEN (op
, 0);
9551 /* Perform a quick check so we don't blow up below. */
9553 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9554 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
9555 || XVECLEN (SET_SRC (XVECEXP (op
, 0, 0)), 0) != 2)
9557 src_reg
= XVECEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0, 0);
9559 if (GET_CODE (src_reg
) != REG
9560 || GET_MODE (src_reg
) != SImode
9561 || ! INT_REGNO_P (REGNO (src_reg
)))
9564 for (i
= 0; i
< count
; i
++)
9566 rtx exp
= XVECEXP (op
, 0, i
);
9570 if (GET_CODE (exp
) != SET
9571 || GET_CODE (SET_DEST (exp
)) != REG
9572 || GET_MODE (SET_DEST (exp
)) != CCmode
9573 || ! CR_REGNO_P (REGNO (SET_DEST (exp
))))
9575 unspec
= SET_SRC (exp
);
9576 maskval
= 1 << (MAX_CR_REGNO
- REGNO (SET_DEST (exp
)));
9578 if (GET_CODE (unspec
) != UNSPEC
9579 || XINT (unspec
, 1) != UNSPEC_MOVESI_TO_CR
9580 || XVECLEN (unspec
, 0) != 2
9581 || XVECEXP (unspec
, 0, 0) != src_reg
9582 || GET_CODE (XVECEXP (unspec
, 0, 1)) != CONST_INT
9583 || INTVAL (XVECEXP (unspec
, 0, 1)) != maskval
)
9589 /* Return 1 for an PARALLEL suitable for lmw. */
9592 lmw_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9594 int count
= XVECLEN (op
, 0);
9595 unsigned int dest_regno
;
9597 unsigned int base_regno
;
9598 HOST_WIDE_INT offset
;
9601 /* Perform a quick check so we don't blow up below. */
9603 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9604 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
9605 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
9608 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
9609 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
9612 || count
!= 32 - (int) dest_regno
)
9615 if (legitimate_indirect_address_p (src_addr
, 0))
9618 base_regno
= REGNO (src_addr
);
9619 if (base_regno
== 0)
9622 else if (rs6000_legitimate_offset_address_p (SImode
, src_addr
, 0))
9624 offset
= INTVAL (XEXP (src_addr
, 1));
9625 base_regno
= REGNO (XEXP (src_addr
, 0));
9630 for (i
= 0; i
< count
; i
++)
9632 rtx elt
= XVECEXP (op
, 0, i
);
9635 HOST_WIDE_INT newoffset
;
9637 if (GET_CODE (elt
) != SET
9638 || GET_CODE (SET_DEST (elt
)) != REG
9639 || GET_MODE (SET_DEST (elt
)) != SImode
9640 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
9641 || GET_CODE (SET_SRC (elt
)) != MEM
9642 || GET_MODE (SET_SRC (elt
)) != SImode
)
9644 newaddr
= XEXP (SET_SRC (elt
), 0);
9645 if (legitimate_indirect_address_p (newaddr
, 0))
9650 else if (rs6000_legitimate_offset_address_p (SImode
, newaddr
, 0))
9652 addr_reg
= XEXP (newaddr
, 0);
9653 newoffset
= INTVAL (XEXP (newaddr
, 1));
9657 if (REGNO (addr_reg
) != base_regno
9658 || newoffset
!= offset
+ 4 * i
)
9665 /* Return 1 for an PARALLEL suitable for stmw. */
9668 stmw_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9670 int count
= XVECLEN (op
, 0);
9671 unsigned int src_regno
;
9673 unsigned int base_regno
;
9674 HOST_WIDE_INT offset
;
9677 /* Perform a quick check so we don't blow up below. */
9679 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
9680 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
9681 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
9684 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
9685 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
9688 || count
!= 32 - (int) src_regno
)
9691 if (legitimate_indirect_address_p (dest_addr
, 0))
9694 base_regno
= REGNO (dest_addr
);
9695 if (base_regno
== 0)
9698 else if (rs6000_legitimate_offset_address_p (SImode
, dest_addr
, 0))
9700 offset
= INTVAL (XEXP (dest_addr
, 1));
9701 base_regno
= REGNO (XEXP (dest_addr
, 0));
9706 for (i
= 0; i
< count
; i
++)
9708 rtx elt
= XVECEXP (op
, 0, i
);
9711 HOST_WIDE_INT newoffset
;
9713 if (GET_CODE (elt
) != SET
9714 || GET_CODE (SET_SRC (elt
)) != REG
9715 || GET_MODE (SET_SRC (elt
)) != SImode
9716 || REGNO (SET_SRC (elt
)) != src_regno
+ i
9717 || GET_CODE (SET_DEST (elt
)) != MEM
9718 || GET_MODE (SET_DEST (elt
)) != SImode
)
9720 newaddr
= XEXP (SET_DEST (elt
), 0);
9721 if (legitimate_indirect_address_p (newaddr
, 0))
9726 else if (rs6000_legitimate_offset_address_p (SImode
, newaddr
, 0))
9728 addr_reg
= XEXP (newaddr
, 0);
9729 newoffset
= INTVAL (XEXP (newaddr
, 1));
9733 if (REGNO (addr_reg
) != base_regno
9734 || newoffset
!= offset
+ 4 * i
)
9741 /* A validation routine: say whether CODE, a condition code, and MODE
9742 match. The other alternatives either don't make sense or should
9743 never be generated. */
9746 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
9748 if ((GET_RTX_CLASS (code
) != RTX_COMPARE
9749 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
)
9750 || GET_MODE_CLASS (mode
) != MODE_CC
)
9753 /* These don't make sense. */
9754 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
9755 && mode
== CCUNSmode
)
9758 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
9759 && mode
!= CCUNSmode
)
9762 if (mode
!= CCFPmode
9763 && (code
== ORDERED
|| code
== UNORDERED
9764 || code
== UNEQ
|| code
== LTGT
9765 || code
== UNGT
|| code
== UNLT
9766 || code
== UNGE
|| code
== UNLE
))
9769 /* These should never be generated except for
9770 flag_finite_math_only. */
9771 if (mode
== CCFPmode
9772 && ! flag_finite_math_only
9773 && (code
== LE
|| code
== GE
9774 || code
== UNEQ
|| code
== LTGT
9775 || code
== UNGT
|| code
== UNLT
))
9778 /* These are invalid; the information is not there. */
9779 if (mode
== CCEQmode
9780 && code
!= EQ
&& code
!= NE
)
9784 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9785 We only check the opcode against the mode of the CC value here. */
9788 branch_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9790 enum rtx_code code
= GET_CODE (op
);
9791 enum machine_mode cc_mode
;
9793 if (!COMPARISON_P (op
))
9796 cc_mode
= GET_MODE (XEXP (op
, 0));
9797 if (GET_MODE_CLASS (cc_mode
) != MODE_CC
)
9800 validate_condition_mode (code
, cc_mode
);
9805 /* Return 1 if OP is a comparison operation that is valid for a branch
9806 insn and which is true if the corresponding bit in the CC register
9810 branch_positive_comparison_operator (rtx op
, enum machine_mode mode
)
9814 if (! branch_comparison_operator (op
, mode
))
9817 code
= GET_CODE (op
);
9818 return (code
== EQ
|| code
== LT
|| code
== GT
9819 || code
== LTU
|| code
== GTU
9820 || code
== UNORDERED
);
9823 /* Return 1 if OP is a comparison operation that is valid for an scc
9824 insn: it must be a positive comparison. */
9827 scc_comparison_operator (rtx op
, enum machine_mode mode
)
9829 return branch_positive_comparison_operator (op
, mode
);
9833 trap_comparison_operator (rtx op
, enum machine_mode mode
)
9835 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
9837 return COMPARISON_P (op
);
9841 boolean_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9843 enum rtx_code code
= GET_CODE (op
);
9844 return (code
== AND
|| code
== IOR
|| code
== XOR
);
9848 boolean_or_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9850 enum rtx_code code
= GET_CODE (op
);
9851 return (code
== IOR
|| code
== XOR
);
9855 min_max_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9857 enum rtx_code code
= GET_CODE (op
);
9858 return (code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
);
9861 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9862 mask required to convert the result of a rotate insn into a shift
9863 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9866 includes_lshift_p (rtx shiftop
, rtx andop
)
9868 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9870 shift_mask
<<= INTVAL (shiftop
);
9872 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9875 /* Similar, but for right shift. */
9878 includes_rshift_p (rtx shiftop
, rtx andop
)
9880 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
9882 shift_mask
>>= INTVAL (shiftop
);
9884 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
9887 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9888 to perform a left shift. It must have exactly SHIFTOP least
9889 significant 0's, then one or more 1's, then zero or more 0's. */
9892 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
9894 if (GET_CODE (andop
) == CONST_INT
)
9896 HOST_WIDE_INT c
, lsb
, shift_mask
;
9899 if (c
== 0 || c
== ~0)
9903 shift_mask
<<= INTVAL (shiftop
);
9905 /* Find the least significant one bit. */
9908 /* It must coincide with the LSB of the shift mask. */
9909 if (-lsb
!= shift_mask
)
9912 /* Invert to look for the next transition (if any). */
9915 /* Remove the low group of ones (originally low group of zeros). */
9918 /* Again find the lsb, and check we have all 1's above. */
9922 else if (GET_CODE (andop
) == CONST_DOUBLE
9923 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
9925 HOST_WIDE_INT low
, high
, lsb
;
9926 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
9928 low
= CONST_DOUBLE_LOW (andop
);
9929 if (HOST_BITS_PER_WIDE_INT
< 64)
9930 high
= CONST_DOUBLE_HIGH (andop
);
9932 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
9933 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
9936 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9938 shift_mask_high
= ~0;
9939 if (INTVAL (shiftop
) > 32)
9940 shift_mask_high
<<= INTVAL (shiftop
) - 32;
9944 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
9951 return high
== -lsb
;
9954 shift_mask_low
= ~0;
9955 shift_mask_low
<<= INTVAL (shiftop
);
9959 if (-lsb
!= shift_mask_low
)
9962 if (HOST_BITS_PER_WIDE_INT
< 64)
9967 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
9970 return high
== -lsb
;
9974 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
9980 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9981 to perform a left shift. It must have SHIFTOP or more least
9982 significant 0's, with the remainder of the word 1's. */
9985 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
9987 if (GET_CODE (andop
) == CONST_INT
)
9989 HOST_WIDE_INT c
, lsb
, shift_mask
;
9992 shift_mask
<<= INTVAL (shiftop
);
9995 /* Find the least significant one bit. */
9998 /* It must be covered by the shift mask.
9999 This test also rejects c == 0. */
10000 if ((lsb
& shift_mask
) == 0)
10003 /* Check we have all 1's above the transition, and reject all 1's. */
10004 return c
== -lsb
&& lsb
!= 1;
10006 else if (GET_CODE (andop
) == CONST_DOUBLE
10007 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
10009 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
10011 low
= CONST_DOUBLE_LOW (andop
);
10013 if (HOST_BITS_PER_WIDE_INT
< 64)
10015 HOST_WIDE_INT high
, shift_mask_high
;
10017 high
= CONST_DOUBLE_HIGH (andop
);
10021 shift_mask_high
= ~0;
10022 if (INTVAL (shiftop
) > 32)
10023 shift_mask_high
<<= INTVAL (shiftop
) - 32;
10025 lsb
= high
& -high
;
10027 if ((lsb
& shift_mask_high
) == 0)
10030 return high
== -lsb
;
10036 shift_mask_low
= ~0;
10037 shift_mask_low
<<= INTVAL (shiftop
);
10041 if ((lsb
& shift_mask_low
) == 0)
10044 return low
== -lsb
&& lsb
!= 1;
10050 /* Return 1 if operands will generate a valid arguments to rlwimi
10051 instruction for insert with right shift in 64-bit mode. The mask may
10052 not start on the first bit or stop on the last bit because wrap-around
10053 effects of instruction do not correspond to semantics of RTL insn. */
10056 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
10058 if (INTVAL (startop
) < 64
10059 && INTVAL (startop
) > 32
10060 && (INTVAL (sizeop
) + INTVAL (startop
) < 64)
10061 && (INTVAL (sizeop
) + INTVAL (startop
) > 33)
10062 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) < 96)
10063 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) >= 64)
10064 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
10070 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10071 for lfq and stfq insns iff the registers are hard registers. */
10074 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
10076 /* We might have been passed a SUBREG. */
10077 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
10080 /* We might have been passed non floating point registers. */
10081 if (!FP_REGNO_P (REGNO (reg1
))
10082 || !FP_REGNO_P (REGNO (reg2
)))
10085 return (REGNO (reg1
) == REGNO (reg2
) - 1);
10088 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10089 addr1 and addr2 must be in consecutive memory locations
10090 (addr2 == addr1 + 8). */
10093 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
10099 /* The mems cannot be volatile. */
10100 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
10103 addr1
= XEXP (mem1
, 0);
10104 addr2
= XEXP (mem2
, 0);
10106 /* Extract an offset (if used) from the first addr. */
10107 if (GET_CODE (addr1
) == PLUS
)
10109 /* If not a REG, return zero. */
10110 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
10114 reg1
= REGNO (XEXP (addr1
, 0));
10115 /* The offset must be constant! */
10116 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
10118 offset1
= INTVAL (XEXP (addr1
, 1));
10121 else if (GET_CODE (addr1
) != REG
)
10125 reg1
= REGNO (addr1
);
10126 /* This was a simple (mem (reg)) expression. Offset is 0. */
10130 /* Make sure the second address is a (mem (plus (reg) (const_int)))
10131 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
10132 register as addr1. */
10133 if (offset1
== -8 && GET_CODE (addr2
) == REG
&& reg1
== REGNO (addr2
))
10135 if (GET_CODE (addr2
) != PLUS
)
10138 if (GET_CODE (XEXP (addr2
, 0)) != REG
10139 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
10142 if (reg1
!= REGNO (XEXP (addr2
, 0)))
10145 /* The offset for the second addr must be 8 more than the first addr. */
10146 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 8)
10149 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10154 /* Return the register class of a scratch register needed to copy IN into
10155 or out of a register in CLASS in MODE. If it can be done directly,
10156 NO_REGS is returned. */
10159 secondary_reload_class (enum reg_class
class,
10160 enum machine_mode mode ATTRIBUTE_UNUSED
,
10165 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
10167 && MACHOPIC_INDIRECT
10171 /* We cannot copy a symbolic operand directly into anything
10172 other than BASE_REGS for TARGET_ELF. So indicate that a
10173 register from BASE_REGS is needed as an intermediate
10176 On Darwin, pic addresses require a load from memory, which
10177 needs a base register. */
10178 if (class != BASE_REGS
10179 && (GET_CODE (in
) == SYMBOL_REF
10180 || GET_CODE (in
) == HIGH
10181 || GET_CODE (in
) == LABEL_REF
10182 || GET_CODE (in
) == CONST
))
10186 if (GET_CODE (in
) == REG
)
10188 regno
= REGNO (in
);
10189 if (regno
>= FIRST_PSEUDO_REGISTER
)
10191 regno
= true_regnum (in
);
10192 if (regno
>= FIRST_PSEUDO_REGISTER
)
10196 else if (GET_CODE (in
) == SUBREG
)
10198 regno
= true_regnum (in
);
10199 if (regno
>= FIRST_PSEUDO_REGISTER
)
10205 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10207 if (class == GENERAL_REGS
|| class == BASE_REGS
10208 || (regno
>= 0 && INT_REGNO_P (regno
)))
10211 /* Constants, memory, and FP registers can go into FP registers. */
10212 if ((regno
== -1 || FP_REGNO_P (regno
))
10213 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
10216 /* Memory, and AltiVec registers can go into AltiVec registers. */
10217 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
10218 && class == ALTIVEC_REGS
)
10221 /* We can copy among the CR registers. */
10222 if ((class == CR_REGS
|| class == CR0_REGS
)
10223 && regno
>= 0 && CR_REGNO_P (regno
))
10226 /* Otherwise, we need GENERAL_REGS. */
10227 return GENERAL_REGS
;
10230 /* Given a comparison operation, return the bit number in CCR to test. We
10231 know this is a valid comparison.
10233 SCC_P is 1 if this is for an scc. That means that %D will have been
10234 used instead of %C, so the bits will be in different places.
10236 Return -1 if OP isn't a valid comparison for some reason. */
10239 ccr_bit (rtx op
, int scc_p
)
10241 enum rtx_code code
= GET_CODE (op
);
10242 enum machine_mode cc_mode
;
10247 if (!COMPARISON_P (op
))
10250 reg
= XEXP (op
, 0);
10252 if (GET_CODE (reg
) != REG
10253 || ! CR_REGNO_P (REGNO (reg
)))
10256 cc_mode
= GET_MODE (reg
);
10257 cc_regnum
= REGNO (reg
);
10258 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
10260 validate_condition_mode (code
, cc_mode
);
10262 /* When generating a sCOND operation, only positive conditions are
10264 if (scc_p
&& code
!= EQ
&& code
!= GT
&& code
!= LT
&& code
!= UNORDERED
10265 && code
!= GTU
&& code
!= LTU
)
10271 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
10273 return base_bit
+ 2;
10274 case GT
: case GTU
: case UNLE
:
10275 return base_bit
+ 1;
10276 case LT
: case LTU
: case UNGE
:
10278 case ORDERED
: case UNORDERED
:
10279 return base_bit
+ 3;
10282 /* If scc, we will have done a cror to put the bit in the
10283 unordered position. So test that bit. For integer, this is ! LT
10284 unless this is an scc insn. */
10285 return scc_p
? base_bit
+ 3 : base_bit
;
10288 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
10295 /* Return the GOT register. */
10298 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
10300 /* The second flow pass currently (June 1999) can't update
10301 regs_ever_live without disturbing other parts of the compiler, so
10302 update it here to make the prolog/epilogue code happy. */
10303 if (no_new_pseudos
&& ! regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
])
10304 regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
10306 current_function_uses_pic_offset_table
= 1;
10308 return pic_offset_table_rtx
;
10311 /* Function to init struct machine_function.
10312 This will be called, via a pointer variable,
10313 from push_function_context. */
10315 static struct machine_function
*
10316 rs6000_init_machine_status (void)
10318 return ggc_alloc_cleared (sizeof (machine_function
));
10321 /* These macros test for integers and extract the low-order bits. */
10323 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10324 && GET_MODE (X) == VOIDmode)
10326 #define INT_LOWPART(X) \
10327 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10330 extract_MB (rtx op
)
10333 unsigned long val
= INT_LOWPART (op
);
10335 /* If the high bit is zero, the value is the first 1 bit we find
10337 if ((val
& 0x80000000) == 0)
10339 if ((val
& 0xffffffff) == 0)
10343 while (((val
<<= 1) & 0x80000000) == 0)
10348 /* If the high bit is set and the low bit is not, or the mask is all
10349 1's, the value is zero. */
10350 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
10353 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10356 while (((val
>>= 1) & 1) != 0)
10363 extract_ME (rtx op
)
10366 unsigned long val
= INT_LOWPART (op
);
10368 /* If the low bit is zero, the value is the first 1 bit we find from
10370 if ((val
& 1) == 0)
10372 if ((val
& 0xffffffff) == 0)
10376 while (((val
>>= 1) & 1) == 0)
10382 /* If the low bit is set and the high bit is not, or the mask is all
10383 1's, the value is 31. */
10384 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
10387 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10390 while (((val
<<= 1) & 0x80000000) != 0)
10396 /* Locate some local-dynamic symbol still in use by this function
10397 so that we can print its name in some tls_ld pattern. */
10399 static const char *
10400 rs6000_get_some_local_dynamic_name (void)
10404 if (cfun
->machine
->some_ld_name
)
10405 return cfun
->machine
->some_ld_name
;
10407 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10409 && for_each_rtx (&PATTERN (insn
),
10410 rs6000_get_some_local_dynamic_name_1
, 0))
10411 return cfun
->machine
->some_ld_name
;
10416 /* Helper function for rs6000_get_some_local_dynamic_name. */
10419 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10423 if (GET_CODE (x
) == SYMBOL_REF
)
10425 const char *str
= XSTR (x
, 0);
10426 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10428 cfun
->machine
->some_ld_name
= str
;
10436 /* Write out a function code label. */
10439 rs6000_output_function_entry (FILE *file
, const char *fname
)
10441 if (fname
[0] != '.')
10443 switch (DEFAULT_ABI
)
10452 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
10461 RS6000_OUTPUT_BASENAME (file
, fname
);
10463 assemble_name (file
, fname
);
10466 /* Print an operand. Recognize special options, documented below. */
10469 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10470 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10472 #define SMALL_DATA_RELOC "sda21"
10473 #define SMALL_DATA_REG 0
10477 print_operand (FILE *file
, rtx x
, int code
)
10481 unsigned HOST_WIDE_INT uval
;
10486 /* Write out an instruction after the call which may be replaced
10487 with glue code by the loader. This depends on the AIX version. */
10488 asm_fprintf (file
, RS6000_CALL_GLUE
);
10491 /* %a is output_address. */
10494 /* If X is a constant integer whose low-order 5 bits are zero,
10495 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10496 in the AIX assembler where "sri" with a zero shift count
10497 writes a trash instruction. */
10498 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
10505 /* If constant, low-order 16 bits of constant, unsigned.
10506 Otherwise, write normally. */
10508 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
10510 print_operand (file
, x
, 0);
10514 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10515 for 64-bit mask direction. */
10516 putc (((INT_LOWPART(x
) & 1) == 0 ? 'r' : 'l'), file
);
10519 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10523 /* X is a CR register. Print the number of the GT bit of the CR. */
10524 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10525 output_operand_lossage ("invalid %%E value");
10527 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
10531 /* Like 'J' but get to the EQ bit. */
10532 if (GET_CODE (x
) != REG
)
10535 /* Bit 1 is EQ bit. */
10536 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 2;
10538 /* If we want bit 31, write a shift count of zero, not 32. */
10539 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10543 /* X is a CR register. Print the number of the EQ bit of the CR */
10544 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10545 output_operand_lossage ("invalid %%E value");
10547 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
10551 /* X is a CR register. Print the shift count needed to move it
10552 to the high-order four bits. */
10553 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10554 output_operand_lossage ("invalid %%f value");
10556 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
10560 /* Similar, but print the count for the rotate in the opposite
10562 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10563 output_operand_lossage ("invalid %%F value");
10565 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
10569 /* X is a constant integer. If it is negative, print "m",
10570 otherwise print "z". This is to make an aze or ame insn. */
10571 if (GET_CODE (x
) != CONST_INT
)
10572 output_operand_lossage ("invalid %%G value");
10573 else if (INTVAL (x
) >= 0)
10580 /* If constant, output low-order five bits. Otherwise, write
10583 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
10585 print_operand (file
, x
, 0);
10589 /* If constant, output low-order six bits. Otherwise, write
10592 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
10594 print_operand (file
, x
, 0);
10598 /* Print `i' if this is a constant, else nothing. */
10604 /* Write the bit number in CCR for jump. */
10605 i
= ccr_bit (x
, 0);
10607 output_operand_lossage ("invalid %%j code");
10609 fprintf (file
, "%d", i
);
10613 /* Similar, but add one for shift count in rlinm for scc and pass
10614 scc flag to `ccr_bit'. */
10615 i
= ccr_bit (x
, 1);
10617 output_operand_lossage ("invalid %%J code");
10619 /* If we want bit 31, write a shift count of zero, not 32. */
10620 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10624 /* X must be a constant. Write the 1's complement of the
10627 output_operand_lossage ("invalid %%k value");
10629 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
10633 /* X must be a symbolic constant on ELF. Write an
10634 expression suitable for an 'addi' that adds in the low 16
10635 bits of the MEM. */
10636 if (GET_CODE (x
) != CONST
)
10638 print_operand_address (file
, x
);
10639 fputs ("@l", file
);
10643 if (GET_CODE (XEXP (x
, 0)) != PLUS
10644 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
10645 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
10646 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
10647 output_operand_lossage ("invalid %%K value");
10648 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
10649 fputs ("@l", file
);
10650 /* For GNU as, there must be a non-alphanumeric character
10651 between 'l' and the number. The '-' is added by
10652 print_operand() already. */
10653 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
10655 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
10659 /* %l is output_asm_label. */
10662 /* Write second word of DImode or DFmode reference. Works on register
10663 or non-indexed memory only. */
10664 if (GET_CODE (x
) == REG
)
10665 fputs (reg_names
[REGNO (x
) + 1], file
);
10666 else if (GET_CODE (x
) == MEM
)
10668 /* Handle possible auto-increment. Since it is pre-increment and
10669 we have already done it, we can just use an offset of word. */
10670 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10671 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10672 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
10675 output_address (XEXP (adjust_address_nv (x
, SImode
,
10679 if (small_data_operand (x
, GET_MODE (x
)))
10680 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10681 reg_names
[SMALL_DATA_REG
]);
10686 /* MB value for a mask operand. */
10687 if (! mask_operand (x
, SImode
))
10688 output_operand_lossage ("invalid %%m value");
10690 fprintf (file
, "%d", extract_MB (x
));
10694 /* ME value for a mask operand. */
10695 if (! mask_operand (x
, SImode
))
10696 output_operand_lossage ("invalid %%M value");
10698 fprintf (file
, "%d", extract_ME (x
));
10701 /* %n outputs the negative of its operand. */
10704 /* Write the number of elements in the vector times 4. */
10705 if (GET_CODE (x
) != PARALLEL
)
10706 output_operand_lossage ("invalid %%N value");
10708 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
10712 /* Similar, but subtract 1 first. */
10713 if (GET_CODE (x
) != PARALLEL
)
10714 output_operand_lossage ("invalid %%O value");
10716 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
10720 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10722 || INT_LOWPART (x
) < 0
10723 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
10724 output_operand_lossage ("invalid %%p value");
10726 fprintf (file
, "%d", i
);
10730 /* The operand must be an indirect memory reference. The result
10731 is the register name. */
10732 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
10733 || REGNO (XEXP (x
, 0)) >= 32)
10734 output_operand_lossage ("invalid %%P value");
10736 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
10740 /* This outputs the logical code corresponding to a boolean
10741 expression. The expression may have one or both operands
10742 negated (if one, only the first one). For condition register
10743 logical operations, it will also treat the negated
10744 CR codes as NOTs, but not handle NOTs of them. */
10746 const char *const *t
= 0;
10748 enum rtx_code code
= GET_CODE (x
);
10749 static const char * const tbl
[3][3] = {
10750 { "and", "andc", "nor" },
10751 { "or", "orc", "nand" },
10752 { "xor", "eqv", "xor" } };
10756 else if (code
== IOR
)
10758 else if (code
== XOR
)
10761 output_operand_lossage ("invalid %%q value");
10763 if (GET_CODE (XEXP (x
, 0)) != NOT
)
10767 if (GET_CODE (XEXP (x
, 1)) == NOT
)
10785 /* X is a CR register. Print the mask for `mtcrf'. */
10786 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
10787 output_operand_lossage ("invalid %%R value");
10789 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
10793 /* Low 5 bits of 32 - value */
10795 output_operand_lossage ("invalid %%s value");
10797 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
10801 /* PowerPC64 mask position. All 0's is excluded.
10802 CONST_INT 32-bit mask is considered sign-extended so any
10803 transition must occur within the CONST_INT, not on the boundary. */
10804 if (! mask64_operand (x
, DImode
))
10805 output_operand_lossage ("invalid %%S value");
10807 uval
= INT_LOWPART (x
);
10809 if (uval
& 1) /* Clear Left */
10811 #if HOST_BITS_PER_WIDE_INT > 64
10812 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10816 else /* Clear Right */
10819 #if HOST_BITS_PER_WIDE_INT > 64
10820 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
10828 fprintf (file
, "%d", i
);
10832 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10833 if (GET_CODE (x
) != REG
|| GET_MODE (x
) != CCmode
)
10836 /* Bit 3 is OV bit. */
10837 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
10839 /* If we want bit 31, write a shift count of zero, not 32. */
10840 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
10844 /* Print the symbolic name of a branch target register. */
10845 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LINK_REGISTER_REGNUM
10846 && REGNO (x
) != COUNT_REGISTER_REGNUM
))
10847 output_operand_lossage ("invalid %%T value");
10848 else if (REGNO (x
) == LINK_REGISTER_REGNUM
)
10849 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
10851 fputs ("ctr", file
);
10855 /* High-order 16 bits of constant for use in unsigned operand. */
10857 output_operand_lossage ("invalid %%u value");
10859 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10860 (INT_LOWPART (x
) >> 16) & 0xffff);
10864 /* High-order 16 bits of constant for use in signed operand. */
10866 output_operand_lossage ("invalid %%v value");
10868 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
10869 (INT_LOWPART (x
) >> 16) & 0xffff);
10873 /* Print `u' if this has an auto-increment or auto-decrement. */
10874 if (GET_CODE (x
) == MEM
10875 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
10876 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
))
10881 /* Print the trap code for this operand. */
10882 switch (GET_CODE (x
))
10885 fputs ("eq", file
); /* 4 */
10888 fputs ("ne", file
); /* 24 */
10891 fputs ("lt", file
); /* 16 */
10894 fputs ("le", file
); /* 20 */
10897 fputs ("gt", file
); /* 8 */
10900 fputs ("ge", file
); /* 12 */
10903 fputs ("llt", file
); /* 2 */
10906 fputs ("lle", file
); /* 6 */
10909 fputs ("lgt", file
); /* 1 */
10912 fputs ("lge", file
); /* 5 */
10920 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10923 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
10924 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
10926 print_operand (file
, x
, 0);
10930 /* MB value for a PowerPC64 rldic operand. */
10931 val
= (GET_CODE (x
) == CONST_INT
10932 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
10937 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
10938 if ((val
<<= 1) < 0)
10941 #if HOST_BITS_PER_WIDE_INT == 32
10942 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
10943 i
+= 32; /* zero-extend high-part was all 0's */
10944 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
10946 val
= CONST_DOUBLE_LOW (x
);
10953 for ( ; i
< 64; i
++)
10954 if ((val
<<= 1) < 0)
10959 fprintf (file
, "%d", i
+ 1);
10963 if (GET_CODE (x
) == MEM
10964 && legitimate_indexed_address_p (XEXP (x
, 0), 0))
10969 /* Like 'L', for third word of TImode */
10970 if (GET_CODE (x
) == REG
)
10971 fputs (reg_names
[REGNO (x
) + 2], file
);
10972 else if (GET_CODE (x
) == MEM
)
10974 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
10975 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
10976 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
10978 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
10979 if (small_data_operand (x
, GET_MODE (x
)))
10980 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
10981 reg_names
[SMALL_DATA_REG
]);
10986 /* X is a SYMBOL_REF. Write out the name preceded by a
10987 period and without any trailing data in brackets. Used for function
10988 names. If we are configured for System V (or the embedded ABI) on
10989 the PowerPC, do not emit the period, since those systems do not use
10990 TOCs and the like. */
10991 if (GET_CODE (x
) != SYMBOL_REF
)
10994 /* Mark the decl as referenced so that cgraph will output the
10996 if (SYMBOL_REF_DECL (x
))
10997 mark_decl_referenced (SYMBOL_REF_DECL (x
));
10999 /* For macho, check to see if we need a stub. */
11002 const char *name
= XSTR (x
, 0);
11004 if (MACHOPIC_INDIRECT
11005 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
11006 name
= machopic_indirection_name (x
, /*stub_p=*/true);
11008 assemble_name (file
, name
);
11010 else if (!DOT_SYMBOLS
)
11011 assemble_name (file
, XSTR (x
, 0));
11013 rs6000_output_function_entry (file
, XSTR (x
, 0));
11017 /* Like 'L', for last word of TImode. */
11018 if (GET_CODE (x
) == REG
)
11019 fputs (reg_names
[REGNO (x
) + 3], file
);
11020 else if (GET_CODE (x
) == MEM
)
11022 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11023 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11024 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
11026 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
11027 if (small_data_operand (x
, GET_MODE (x
)))
11028 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11029 reg_names
[SMALL_DATA_REG
]);
11033 /* Print AltiVec or SPE memory operand. */
11038 if (GET_CODE (x
) != MEM
)
11045 /* Handle [reg]. */
11046 if (GET_CODE (tmp
) == REG
)
11048 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
11051 /* Handle [reg+UIMM]. */
11052 else if (GET_CODE (tmp
) == PLUS
&&
11053 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
11057 if (GET_CODE (XEXP (tmp
, 0)) != REG
)
11060 x
= INTVAL (XEXP (tmp
, 1));
11061 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
11065 /* Fall through. Must be [reg+reg]. */
11068 && GET_CODE (tmp
) == AND
11069 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
11070 && INTVAL (XEXP (tmp
, 1)) == -16)
11071 tmp
= XEXP (tmp
, 0);
11072 if (GET_CODE (tmp
) == REG
)
11073 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
11074 else if (GET_CODE (tmp
) == PLUS
&& GET_CODE (XEXP (tmp
, 1)) == REG
)
11076 if (REGNO (XEXP (tmp
, 0)) == 0)
11077 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
11078 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
11080 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
11081 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
11089 if (GET_CODE (x
) == REG
)
11090 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
11091 else if (GET_CODE (x
) == MEM
)
11093 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11094 know the width from the mode. */
11095 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
11096 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
11097 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
11098 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11099 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
11100 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
11102 output_address (XEXP (x
, 0));
11105 output_addr_const (file
, x
);
11109 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
11113 output_operand_lossage ("invalid %%xn code");
11117 /* Print the address of an operand. */
11120 print_operand_address (FILE *file
, rtx x
)
11122 if (GET_CODE (x
) == REG
)
11123 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
11124 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
11125 || GET_CODE (x
) == LABEL_REF
)
11127 output_addr_const (file
, x
);
11128 if (small_data_operand (x
, GET_MODE (x
)))
11129 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11130 reg_names
[SMALL_DATA_REG
]);
11131 else if (TARGET_TOC
)
11134 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
11136 if (REGNO (XEXP (x
, 0)) == 0)
11137 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
11138 reg_names
[ REGNO (XEXP (x
, 0)) ]);
11140 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
11141 reg_names
[ REGNO (XEXP (x
, 1)) ]);
11143 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11144 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
11145 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
11147 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
11148 && CONSTANT_P (XEXP (x
, 1)))
11150 output_addr_const (file
, XEXP (x
, 1));
11151 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
11155 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
11156 && CONSTANT_P (XEXP (x
, 1)))
11158 fprintf (file
, "lo16(");
11159 output_addr_const (file
, XEXP (x
, 1));
11160 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
11163 else if (legitimate_constant_pool_address_p (x
))
11165 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
11167 rtx contains_minus
= XEXP (x
, 1);
11171 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11172 turn it into (sym) for output_addr_const. */
11173 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
11174 contains_minus
= XEXP (contains_minus
, 0);
11176 minus
= XEXP (contains_minus
, 0);
11177 symref
= XEXP (minus
, 0);
11178 XEXP (contains_minus
, 0) = symref
;
11183 name
= XSTR (symref
, 0);
11184 newname
= alloca (strlen (name
) + sizeof ("@toc"));
11185 strcpy (newname
, name
);
11186 strcat (newname
, "@toc");
11187 XSTR (symref
, 0) = newname
;
11189 output_addr_const (file
, XEXP (x
, 1));
11191 XSTR (symref
, 0) = name
;
11192 XEXP (contains_minus
, 0) = minus
;
11195 output_addr_const (file
, XEXP (x
, 1));
11197 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
11203 /* Target hook for assembling integer objects. The PowerPC version has
11204 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11205 is defined. It also needs to handle DI-mode objects on 64-bit
11209 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11211 #ifdef RELOCATABLE_NEEDS_FIXUP
11212 /* Special handling for SI values. */
11213 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
11215 extern int in_toc_section (void);
11216 static int recurse
= 0;
11218 /* For -mrelocatable, we mark all addresses that need to be fixed up
11219 in the .fixup section. */
11220 if (TARGET_RELOCATABLE
11221 && !in_toc_section ()
11222 && !in_text_section ()
11223 && !in_unlikely_text_section ()
11225 && GET_CODE (x
) != CONST_INT
11226 && GET_CODE (x
) != CONST_DOUBLE
11232 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
11234 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
11235 fprintf (asm_out_file
, "\t.long\t(");
11236 output_addr_const (asm_out_file
, x
);
11237 fprintf (asm_out_file
, ")@fixup\n");
11238 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
11239 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
11240 fprintf (asm_out_file
, "\t.long\t");
11241 assemble_name (asm_out_file
, buf
);
11242 fprintf (asm_out_file
, "\n\t.previous\n");
11246 /* Remove initial .'s to turn a -mcall-aixdesc function
11247 address into the address of the descriptor, not the function
11249 else if (GET_CODE (x
) == SYMBOL_REF
11250 && XSTR (x
, 0)[0] == '.'
11251 && DEFAULT_ABI
== ABI_AIX
)
11253 const char *name
= XSTR (x
, 0);
11254 while (*name
== '.')
11257 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
11261 #endif /* RELOCATABLE_NEEDS_FIXUP */
11262 return default_assemble_integer (x
, size
, aligned_p
);
11265 #ifdef HAVE_GAS_HIDDEN
11266 /* Emit an assembler directive to set symbol visibility for DECL to
11267 VISIBILITY_TYPE. */
11270 rs6000_assemble_visibility (tree decl
, int vis
)
11272 /* Functions need to have their entry point symbol visibility set as
11273 well as their descriptor symbol visibility. */
11274 if (DEFAULT_ABI
== ABI_AIX
11276 && TREE_CODE (decl
) == FUNCTION_DECL
)
11278 static const char * const visibility_types
[] = {
11279 NULL
, "internal", "hidden", "protected"
11282 const char *name
, *type
;
11284 name
= ((* targetm
.strip_name_encoding
)
11285 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
11286 type
= visibility_types
[vis
];
11288 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
11289 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
11292 default_assemble_visibility (decl
, vis
);
11297 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
11299 /* Reversal of FP compares takes care -- an ordered compare
11300 becomes an unordered compare and vice versa. */
11301 if (mode
== CCFPmode
11302 && (!flag_finite_math_only
11303 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
11304 || code
== UNEQ
|| code
== LTGT
))
11305 return reverse_condition_maybe_unordered (code
);
11307 return reverse_condition (code
);
11310 /* Generate a compare for CODE. Return a brand-new rtx that
11311 represents the result of the compare. */
11314 rs6000_generate_compare (enum rtx_code code
)
11316 enum machine_mode comp_mode
;
11317 rtx compare_result
;
11319 if (rs6000_compare_fp_p
)
11320 comp_mode
= CCFPmode
;
11321 else if (code
== GTU
|| code
== LTU
11322 || code
== GEU
|| code
== LEU
)
11323 comp_mode
= CCUNSmode
;
11324 else if ((code
== EQ
|| code
== NE
)
11325 && GET_CODE (rs6000_compare_op0
) == SUBREG
11326 && GET_CODE (rs6000_compare_op1
) == SUBREG
11327 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
11328 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
11329 /* These are unsigned values, perhaps there will be a later
11330 ordering compare that can be shared with this one.
11331 Unfortunately we cannot detect the signedness of the operands
11332 for non-subregs. */
11333 comp_mode
= CCUNSmode
;
11335 comp_mode
= CCmode
;
11337 /* First, the compare. */
11338 compare_result
= gen_reg_rtx (comp_mode
);
11340 /* SPE FP compare instructions on the GPRs. Yuck! */
11341 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
11342 && rs6000_compare_fp_p
)
11344 rtx cmp
, or1
, or2
, or_result
, compare_result2
;
11345 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
11347 if (op_mode
== VOIDmode
)
11348 op_mode
= GET_MODE (rs6000_compare_op1
);
11350 /* Note: The E500 comparison instructions set the GT bit (x +
11351 1), on success. This explains the mess. */
11355 case EQ
: case UNEQ
: case NE
: case LTGT
:
11356 if (op_mode
== SFmode
)
11357 cmp
= flag_unsafe_math_optimizations
11358 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
11359 rs6000_compare_op1
)
11360 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
11361 rs6000_compare_op1
);
11362 else if (op_mode
== DFmode
)
11363 cmp
= flag_unsafe_math_optimizations
11364 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
11365 rs6000_compare_op1
)
11366 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
11367 rs6000_compare_op1
);
11370 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
11371 if (op_mode
== SFmode
)
11372 cmp
= flag_unsafe_math_optimizations
11373 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
11374 rs6000_compare_op1
)
11375 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
11376 rs6000_compare_op1
);
11377 else if (op_mode
== DFmode
)
11378 cmp
= flag_unsafe_math_optimizations
11379 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
11380 rs6000_compare_op1
)
11381 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
11382 rs6000_compare_op1
);
11385 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
11386 if (op_mode
== SFmode
)
11387 cmp
= flag_unsafe_math_optimizations
11388 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
11389 rs6000_compare_op1
)
11390 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
11391 rs6000_compare_op1
);
11392 else if (op_mode
== DFmode
)
11393 cmp
= flag_unsafe_math_optimizations
11394 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
11395 rs6000_compare_op1
)
11396 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
11397 rs6000_compare_op1
);
11404 /* Synthesize LE and GE from LT/GT || EQ. */
11405 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
11411 case LE
: code
= LT
; break;
11412 case GE
: code
= GT
; break;
11413 case LEU
: code
= LT
; break;
11414 case GEU
: code
= GT
; break;
11418 or1
= gen_reg_rtx (SImode
);
11419 or2
= gen_reg_rtx (SImode
);
11420 or_result
= gen_reg_rtx (CCEQmode
);
11421 compare_result2
= gen_reg_rtx (CCFPmode
);
11424 if (op_mode
== SFmode
)
11425 cmp
= flag_unsafe_math_optimizations
11426 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
11427 rs6000_compare_op1
)
11428 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
11429 rs6000_compare_op1
);
11430 else if (op_mode
== DFmode
)
11431 cmp
= flag_unsafe_math_optimizations
11432 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
11433 rs6000_compare_op1
)
11434 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
11435 rs6000_compare_op1
);
11439 or1
= gen_rtx_GT (SImode
, compare_result
, const0_rtx
);
11440 or2
= gen_rtx_GT (SImode
, compare_result2
, const0_rtx
);
11442 /* OR them together. */
11443 cmp
= gen_rtx_SET (VOIDmode
, or_result
,
11444 gen_rtx_COMPARE (CCEQmode
,
11445 gen_rtx_IOR (SImode
, or1
, or2
),
11447 compare_result
= or_result
;
11452 if (code
== NE
|| code
== LTGT
)
11462 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11463 CLOBBERs to match cmptf_internal2 pattern. */
11464 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
11465 && GET_MODE (rs6000_compare_op0
) == TFmode
11466 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
11467 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
11468 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
11470 gen_rtx_SET (VOIDmode
,
11472 gen_rtx_COMPARE (comp_mode
,
11473 rs6000_compare_op0
,
11474 rs6000_compare_op1
)),
11475 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11476 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11477 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11478 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11479 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11480 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11481 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
11482 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
11484 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
11485 gen_rtx_COMPARE (comp_mode
,
11486 rs6000_compare_op0
,
11487 rs6000_compare_op1
)));
11490 /* Some kinds of FP comparisons need an OR operation;
11491 under flag_unsafe_math_optimizations we don't bother. */
11492 if (rs6000_compare_fp_p
11493 && ! flag_unsafe_math_optimizations
11494 && ! (TARGET_HARD_FLOAT
&& TARGET_E500
&& !TARGET_FPRS
)
11495 && (code
== LE
|| code
== GE
11496 || code
== UNEQ
|| code
== LTGT
11497 || code
== UNGT
|| code
== UNLT
))
11499 enum rtx_code or1
, or2
;
11500 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
11501 rtx or_result
= gen_reg_rtx (CCEQmode
);
11505 case LE
: or1
= LT
; or2
= EQ
; break;
11506 case GE
: or1
= GT
; or2
= EQ
; break;
11507 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
11508 case LTGT
: or1
= LT
; or2
= GT
; break;
11509 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
11510 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
11513 validate_condition_mode (or1
, comp_mode
);
11514 validate_condition_mode (or2
, comp_mode
);
11515 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
11516 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
11517 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
11518 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
11520 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
11522 compare_result
= or_result
;
11526 validate_condition_mode (code
, GET_MODE (compare_result
));
11528 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
11532 /* Emit the RTL for an sCOND pattern. */
11535 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
11538 enum machine_mode op_mode
;
11539 enum rtx_code cond_code
;
11541 condition_rtx
= rs6000_generate_compare (code
);
11542 cond_code
= GET_CODE (condition_rtx
);
11544 if (TARGET_E500
&& rs6000_compare_fp_p
11545 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
11549 PUT_MODE (condition_rtx
, SImode
);
11550 t
= XEXP (condition_rtx
, 0);
11552 if (cond_code
!= NE
&& cond_code
!= EQ
)
11555 if (cond_code
== NE
)
11556 emit_insn (gen_e500_flip_eq_bit (t
, t
));
11558 emit_insn (gen_move_from_CR_eq_bit (result
, t
));
11562 if (cond_code
== NE
11563 || cond_code
== GE
|| cond_code
== LE
11564 || cond_code
== GEU
|| cond_code
== LEU
11565 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
11567 rtx not_result
= gen_reg_rtx (CCEQmode
);
11568 rtx not_op
, rev_cond_rtx
;
11569 enum machine_mode cc_mode
;
11571 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
11573 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
11574 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
11575 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
11576 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
11577 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
11580 op_mode
= GET_MODE (rs6000_compare_op0
);
11581 if (op_mode
== VOIDmode
)
11582 op_mode
= GET_MODE (rs6000_compare_op1
);
11584 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
11586 PUT_MODE (condition_rtx
, DImode
);
11587 convert_move (result
, condition_rtx
, 0);
11591 PUT_MODE (condition_rtx
, SImode
);
11592 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
11596 /* Emit a branch of kind CODE to location LOC. */
11599 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
11601 rtx condition_rtx
, loc_ref
;
11603 condition_rtx
= rs6000_generate_compare (code
);
11604 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
11605 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
11606 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
11607 loc_ref
, pc_rtx
)));
11610 /* Return the string to output a conditional branch to LABEL, which is
11611 the operand number of the label, or -1 if the branch is really a
11612 conditional return.
11614 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11615 condition code register and its mode specifies what kind of
11616 comparison we made.
11618 REVERSED is nonzero if we should reverse the sense of the comparison.
11620 INSN is the insn. */
11623 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
11625 static char string
[64];
11626 enum rtx_code code
= GET_CODE (op
);
11627 rtx cc_reg
= XEXP (op
, 0);
11628 enum machine_mode mode
= GET_MODE (cc_reg
);
11629 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
11630 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
11631 int really_reversed
= reversed
^ need_longbranch
;
11637 validate_condition_mode (code
, mode
);
11639 /* Work out which way this really branches. We could use
11640 reverse_condition_maybe_unordered here always but this
11641 makes the resulting assembler clearer. */
11642 if (really_reversed
)
11644 /* Reversal of FP compares takes care -- an ordered compare
11645 becomes an unordered compare and vice versa. */
11646 if (mode
== CCFPmode
)
11647 code
= reverse_condition_maybe_unordered (code
);
11649 code
= reverse_condition (code
);
11652 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
11654 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11657 /* Opposite of GT. */
11659 else if (code
== NE
)
11667 /* Not all of these are actually distinct opcodes, but
11668 we distinguish them for clarity of the resulting assembler. */
11669 case NE
: case LTGT
:
11670 ccode
= "ne"; break;
11671 case EQ
: case UNEQ
:
11672 ccode
= "eq"; break;
11674 ccode
= "ge"; break;
11675 case GT
: case GTU
: case UNGT
:
11676 ccode
= "gt"; break;
11678 ccode
= "le"; break;
11679 case LT
: case LTU
: case UNLT
:
11680 ccode
= "lt"; break;
11681 case UNORDERED
: ccode
= "un"; break;
11682 case ORDERED
: ccode
= "nu"; break;
11683 case UNGE
: ccode
= "nl"; break;
11684 case UNLE
: ccode
= "ng"; break;
11689 /* Maybe we have a guess as to how likely the branch is.
11690 The old mnemonics don't have a way to specify this information. */
11692 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
11693 if (note
!= NULL_RTX
)
11695 /* PROB is the difference from 50%. */
11696 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
11698 /* Only hint for highly probable/improbable branches on newer
11699 cpus as static prediction overrides processor dynamic
11700 prediction. For older cpus we may as well always hint, but
11701 assume not taken for branches that are very close to 50% as a
11702 mispredicted taken branch is more expensive than a
11703 mispredicted not-taken branch. */
11704 if (rs6000_always_hint
11705 || abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48)
11707 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
11708 && ((prob
> 0) ^ need_longbranch
))
11716 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
11718 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
11720 /* We need to escape any '%' characters in the reg_names string.
11721 Assume they'd only be the first character.... */
11722 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
11724 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
11728 /* If the branch distance was too far, we may have to use an
11729 unconditional branch to go the distance. */
11730 if (need_longbranch
)
11731 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
11733 s
+= sprintf (s
, ",%s", label
);
11739 /* Return the string to flip the EQ bit on a CR. */
11741 output_e500_flip_eq_bit (rtx dst
, rtx src
)
11743 static char string
[64];
11746 if (GET_CODE (dst
) != REG
|| ! CR_REGNO_P (REGNO (dst
))
11747 || GET_CODE (src
) != REG
|| ! CR_REGNO_P (REGNO (src
)))
11751 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 2;
11752 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 2;
11754 sprintf (string
, "crnot %d,%d", a
, b
);
11758 /* Return insn index for the vector compare instruction for given CODE,
11759 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11763 get_vec_cmp_insn (enum rtx_code code
,
11764 enum machine_mode dest_mode
,
11765 enum machine_mode op_mode
)
11767 if (!TARGET_ALTIVEC
)
11768 return INSN_NOT_AVAILABLE
;
11773 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11774 return UNSPEC_VCMPEQUB
;
11775 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11776 return UNSPEC_VCMPEQUH
;
11777 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11778 return UNSPEC_VCMPEQUW
;
11779 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11780 return UNSPEC_VCMPEQFP
;
11783 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11784 return UNSPEC_VCMPGEFP
;
11786 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11787 return UNSPEC_VCMPGTSB
;
11788 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11789 return UNSPEC_VCMPGTSH
;
11790 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11791 return UNSPEC_VCMPGTSW
;
11792 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
11793 return UNSPEC_VCMPGTFP
;
11796 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
11797 return UNSPEC_VCMPGTUB
;
11798 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
11799 return UNSPEC_VCMPGTUH
;
11800 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
11801 return UNSPEC_VCMPGTUW
;
11806 return INSN_NOT_AVAILABLE
;
11809 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11810 DMODE is expected destination mode. This is a recursive function. */
11813 rs6000_emit_vector_compare (enum rtx_code rcode
,
11815 enum machine_mode dmode
)
11819 enum machine_mode dest_mode
;
11820 enum machine_mode op_mode
= GET_MODE (op1
);
11822 #ifdef ENABLE_CHECKING
11823 if (!TARGET_ALTIVEC
)
11826 if (GET_MODE (op0
) != GET_MODE (op1
))
11830 /* Floating point vector compare instructions uses destination V4SImode.
11831 Move destination to appropriate mode later. */
11832 if (dmode
== V4SFmode
)
11833 dest_mode
= V4SImode
;
11837 mask
= gen_reg_rtx (dest_mode
);
11838 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
11840 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
11842 bool swap_operands
= false;
11843 bool try_again
= false;
11848 swap_operands
= true;
11853 swap_operands
= true;
11857 /* Treat A != B as ~(A==B). */
11859 enum insn_code nor_code
;
11860 rtx eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
11863 nor_code
= one_cmpl_optab
->handlers
[(int)dest_mode
].insn_code
;
11864 if (nor_code
== CODE_FOR_nothing
)
11866 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
11868 if (dmode
!= dest_mode
)
11870 rtx temp
= gen_reg_rtx (dest_mode
);
11871 convert_move (temp
, mask
, 0);
11881 /* Try GT/GTU/LT/LTU OR EQ */
11884 enum insn_code ior_code
;
11885 enum rtx_code new_code
;
11889 else if (rcode
== GEU
)
11891 else if (rcode
== LE
)
11893 else if (rcode
== LEU
)
11898 c_rtx
= rs6000_emit_vector_compare (new_code
,
11899 op0
, op1
, dest_mode
);
11900 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
11903 ior_code
= ior_optab
->handlers
[(int)dest_mode
].insn_code
;
11904 if (ior_code
== CODE_FOR_nothing
)
11906 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
11907 if (dmode
!= dest_mode
)
11909 rtx temp
= gen_reg_rtx (dest_mode
);
11910 convert_move (temp
, mask
, 0);
11922 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
11923 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
11924 /* You only get two chances. */
11937 emit_insn (gen_rtx_fmt_ee (SET
,
11940 gen_rtx_fmt_Ei (UNSPEC
, dest_mode
,
11941 gen_rtvec (2, op0
, op1
),
11943 if (dmode
!= dest_mode
)
11945 rtx temp
= gen_reg_rtx (dest_mode
);
11946 convert_move (temp
, mask
, 0);
11952 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11953 valid insn doesn exist for given mode. */
11956 get_vsel_insn (enum machine_mode mode
)
11961 return UNSPEC_VSEL4SI
;
11964 return UNSPEC_VSEL4SF
;
11967 return UNSPEC_VSEL8HI
;
11970 return UNSPEC_VSEL16QI
;
11973 return INSN_NOT_AVAILABLE
;
11976 return INSN_NOT_AVAILABLE
;
11979 /* Emit vector select insn where DEST is destination using
11980 operands OP1, OP2 and MASK. */
11983 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
11986 enum machine_mode dest_mode
= GET_MODE (dest
);
11987 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
11989 temp
= gen_reg_rtx (dest_mode
);
11991 t
= gen_rtx_fmt_ee (SET
, VOIDmode
, temp
,
11992 gen_rtx_fmt_Ei (UNSPEC
, dest_mode
,
11993 gen_rtvec (3, op1
, op2
, mask
),
11996 emit_move_insn (dest
, temp
);
12000 /* Emit vector conditional expression.
12001 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12002 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12005 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
12006 rtx cond
, rtx cc_op0
, rtx cc_op1
)
12008 enum machine_mode dest_mode
= GET_MODE (dest
);
12009 enum rtx_code rcode
= GET_CODE (cond
);
12012 if (!TARGET_ALTIVEC
)
12015 /* Get the vector mask for the given relational operations. */
12016 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
12018 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
12023 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12024 operands of the last comparison is nonzero/true, FALSE_COND if it
12025 is zero/false. Return 0 if the hardware has no such operation. */
12028 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
12030 enum rtx_code code
= GET_CODE (op
);
12031 rtx op0
= rs6000_compare_op0
;
12032 rtx op1
= rs6000_compare_op1
;
12033 REAL_VALUE_TYPE c1
;
12034 enum machine_mode compare_mode
= GET_MODE (op0
);
12035 enum machine_mode result_mode
= GET_MODE (dest
);
12037 bool is_against_zero
;
12039 /* These modes should always match. */
12040 if (GET_MODE (op1
) != compare_mode
12041 /* In the isel case however, we can use a compare immediate, so
12042 op1 may be a small constant. */
12043 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
12045 if (GET_MODE (true_cond
) != result_mode
)
12047 if (GET_MODE (false_cond
) != result_mode
)
12050 /* First, work out if the hardware can do this at all, or
12051 if it's too slow.... */
12052 if (! rs6000_compare_fp_p
)
12055 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
12058 else if (TARGET_E500
&& TARGET_HARD_FLOAT
&& !TARGET_FPRS
12059 && GET_MODE_CLASS (compare_mode
) == MODE_FLOAT
)
12062 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
12064 /* A floating-point subtract might overflow, underflow, or produce
12065 an inexact result, thus changing the floating-point flags, so it
12066 can't be generated if we care about that. It's safe if one side
12067 of the construct is zero, since then no subtract will be
12069 if (GET_MODE_CLASS (compare_mode
) == MODE_FLOAT
12070 && flag_trapping_math
&& ! is_against_zero
)
12073 /* Eliminate half of the comparisons by switching operands, this
12074 makes the remaining code simpler. */
12075 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
12076 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
12078 code
= reverse_condition_maybe_unordered (code
);
12080 true_cond
= false_cond
;
12084 /* UNEQ and LTGT take four instructions for a comparison with zero,
12085 it'll probably be faster to use a branch here too. */
12086 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
12089 if (GET_CODE (op1
) == CONST_DOUBLE
)
12090 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
12092 /* We're going to try to implement comparisons by performing
12093 a subtract, then comparing against zero. Unfortunately,
12094 Inf - Inf is NaN which is not zero, and so if we don't
12095 know that the operand is finite and the comparison
12096 would treat EQ different to UNORDERED, we can't do it. */
12097 if (HONOR_INFINITIES (compare_mode
)
12098 && code
!= GT
&& code
!= UNGE
12099 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
12100 /* Constructs of the form (a OP b ? a : b) are safe. */
12101 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
12102 || (! rtx_equal_p (op0
, true_cond
)
12103 && ! rtx_equal_p (op1
, true_cond
))))
12106 /* At this point we know we can use fsel. */
12108 /* Reduce the comparison to a comparison against zero. */
12109 if (! is_against_zero
)
12111 temp
= gen_reg_rtx (compare_mode
);
12112 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12113 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
12115 op1
= CONST0_RTX (compare_mode
);
12118 /* If we don't care about NaNs we can reduce some of the comparisons
12119 down to faster ones. */
12120 if (! HONOR_NANS (compare_mode
))
12126 true_cond
= false_cond
;
12139 /* Now, reduce everything down to a GE. */
12146 temp
= gen_reg_rtx (compare_mode
);
12147 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
12152 temp
= gen_reg_rtx (compare_mode
);
12153 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
12158 temp
= gen_reg_rtx (compare_mode
);
12159 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12160 gen_rtx_NEG (compare_mode
,
12161 gen_rtx_ABS (compare_mode
, op0
))));
12166 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12167 temp
= gen_reg_rtx (result_mode
);
12168 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12169 gen_rtx_IF_THEN_ELSE (result_mode
,
12170 gen_rtx_GE (VOIDmode
,
12172 true_cond
, false_cond
)));
12173 false_cond
= true_cond
;
12176 temp
= gen_reg_rtx (compare_mode
);
12177 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
12182 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12183 temp
= gen_reg_rtx (result_mode
);
12184 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12185 gen_rtx_IF_THEN_ELSE (result_mode
,
12186 gen_rtx_GE (VOIDmode
,
12188 true_cond
, false_cond
)));
12189 true_cond
= false_cond
;
12192 temp
= gen_reg_rtx (compare_mode
);
12193 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
12201 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
12202 gen_rtx_IF_THEN_ELSE (result_mode
,
12203 gen_rtx_GE (VOIDmode
,
12205 true_cond
, false_cond
)));
12209 /* Same as above, but for ints (isel). */
12212 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
12214 rtx condition_rtx
, cr
;
12216 /* All isel implementations thus far are 32-bits. */
12217 if (GET_MODE (rs6000_compare_op0
) != SImode
)
12220 /* We still have to do the compare, because isel doesn't do a
12221 compare, it just looks at the CRx bits set by a previous compare
12223 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
12224 cr
= XEXP (condition_rtx
, 0);
12226 if (GET_MODE (cr
) == CCmode
)
12227 emit_insn (gen_isel_signed (dest
, condition_rtx
,
12228 true_cond
, false_cond
, cr
));
12230 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
12231 true_cond
, false_cond
, cr
));
12237 output_isel (rtx
*operands
)
12239 enum rtx_code code
;
12241 code
= GET_CODE (operands
[1]);
12242 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
12244 PUT_CODE (operands
[1], reverse_condition (code
));
12245 return "isel %0,%3,%2,%j1";
12248 return "isel %0,%2,%3,%j1";
12252 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
12254 enum machine_mode mode
= GET_MODE (op0
);
12258 if (code
== SMAX
|| code
== SMIN
)
12263 if (code
== SMAX
|| code
== UMAX
)
12264 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
12265 op0
, op1
, mode
, 0);
12267 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
12268 op1
, op0
, mode
, 0);
12269 if (target
== NULL_RTX
)
12271 if (target
!= dest
)
12272 emit_move_insn (dest
, target
);
12275 /* Emit instructions to move SRC to DST. Called by splitters for
12276 multi-register moves. It will emit at most one instruction for
12277 each register that is accessed; that is, it won't emit li/lis pairs
12278 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12282 rs6000_split_multireg_move (rtx dst
, rtx src
)
12284 /* The register number of the first register being moved. */
12286 /* The mode that is to be moved. */
12287 enum machine_mode mode
;
12288 /* The mode that the move is being done in, and its size. */
12289 enum machine_mode reg_mode
;
12291 /* The number of registers that will be moved. */
12294 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
12295 mode
= GET_MODE (dst
);
12296 nregs
= HARD_REGNO_NREGS (reg
, mode
);
12297 if (FP_REGNO_P (reg
))
12299 else if (ALTIVEC_REGNO_P (reg
))
12300 reg_mode
= V16QImode
;
12302 reg_mode
= word_mode
;
12303 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
12305 if (reg_mode_size
* nregs
!= GET_MODE_SIZE (mode
))
12308 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
12310 /* Move register range backwards, if we might have destructive
12313 for (i
= nregs
- 1; i
>= 0; i
--)
12314 emit_insn (gen_rtx_SET (VOIDmode
,
12315 simplify_gen_subreg (reg_mode
, dst
, mode
,
12316 i
* reg_mode_size
),
12317 simplify_gen_subreg (reg_mode
, src
, mode
,
12318 i
* reg_mode_size
)));
12324 bool used_update
= false;
12326 if (MEM_P (src
) && INT_REGNO_P (reg
))
12330 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
12331 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
12334 breg
= XEXP (XEXP (src
, 0), 0);
12335 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
12336 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
12337 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
12338 emit_insn (TARGET_32BIT
12339 ? gen_addsi3 (breg
, breg
, delta_rtx
)
12340 : gen_adddi3 (breg
, breg
, delta_rtx
));
12341 src
= gen_rtx_MEM (mode
, breg
);
12343 else if (! offsettable_memref_p (src
))
12345 rtx newsrc
, basereg
;
12346 basereg
= gen_rtx_REG (Pmode
, reg
);
12347 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
12348 newsrc
= gen_rtx_MEM (GET_MODE (src
), basereg
);
12349 MEM_COPY_ATTRIBUTES (newsrc
, src
);
12353 breg
= XEXP (src
, 0);
12354 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
12355 breg
= XEXP (breg
, 0);
12357 /* If the base register we are using to address memory is
12358 also a destination reg, then change that register last. */
12360 && REGNO (breg
) >= REGNO (dst
)
12361 && REGNO (breg
) < REGNO (dst
) + nregs
)
12362 j
= REGNO (breg
) - REGNO (dst
);
12365 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
12369 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
12370 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
12373 breg
= XEXP (XEXP (dst
, 0), 0);
12374 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
12375 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
12376 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
12378 /* We have to update the breg before doing the store.
12379 Use store with update, if available. */
12383 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
12384 emit_insn (TARGET_32BIT
12385 ? (TARGET_POWERPC64
12386 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
12387 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
12388 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
12389 used_update
= true;
12392 emit_insn (TARGET_32BIT
12393 ? gen_addsi3 (breg
, breg
, delta_rtx
)
12394 : gen_adddi3 (breg
, breg
, delta_rtx
));
12395 dst
= gen_rtx_MEM (mode
, breg
);
12397 else if (! offsettable_memref_p (dst
))
12401 for (i
= 0; i
< nregs
; i
++)
12403 /* Calculate index to next subword. */
12408 /* If compiler already emitted move of first word by
12409 store with update, no need to do anything. */
12410 if (j
== 0 && used_update
)
12413 emit_insn (gen_rtx_SET (VOIDmode
,
12414 simplify_gen_subreg (reg_mode
, dst
, mode
,
12415 j
* reg_mode_size
),
12416 simplify_gen_subreg (reg_mode
, src
, mode
,
12417 j
* reg_mode_size
)));
12423 /* This page contains routines that are used to determine what the
12424 function prologue and epilogue code will do and write them out. */
12426 /* Return the first fixed-point register that is required to be
12427 saved. 32 if none. */
12430 first_reg_to_save (void)
12434 /* Find lowest numbered live register. */
12435 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
12436 if (regs_ever_live
[first_reg
]
12437 && (! call_used_regs
[first_reg
]
12438 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
12439 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
12440 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
12441 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
12446 && current_function_uses_pic_offset_table
12447 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
12448 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
12454 /* Similar, for FP regs. */
12457 first_fp_reg_to_save (void)
12461 /* Find lowest numbered live register. */
12462 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
12463 if (regs_ever_live
[first_reg
])
12469 /* Similar, for AltiVec regs. */
12472 first_altivec_reg_to_save (void)
12476 /* Stack frame remains as is unless we are in AltiVec ABI. */
12477 if (! TARGET_ALTIVEC_ABI
)
12478 return LAST_ALTIVEC_REGNO
+ 1;
12480 /* Find lowest numbered live register. */
12481 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12482 if (regs_ever_live
[i
])
12488 /* Return a 32-bit mask of the AltiVec registers we need to set in
12489 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12490 the 32-bit word is 0. */
12492 static unsigned int
12493 compute_vrsave_mask (void)
12495 unsigned int i
, mask
= 0;
12497 /* First, find out if we use _any_ altivec registers. */
12498 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12499 if (regs_ever_live
[i
])
12500 mask
|= ALTIVEC_REG_BIT (i
);
12505 /* Next, remove the argument registers from the set. These must
12506 be in the VRSAVE mask set by the caller, so we don't need to add
12507 them in again. More importantly, the mask we compute here is
12508 used to generate CLOBBERs in the set_vrsave insn, and we do not
12509 wish the argument registers to die. */
12510 for (i
= cfun
->args_info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
12511 mask
&= ~ALTIVEC_REG_BIT (i
);
12513 /* Similarly, remove the return value from the set. */
12516 diddle_return_value (is_altivec_return_reg
, &yes
);
12518 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
12524 /* For a very restricted set of circumstances, we can cut down the
12525 size of prologues/epilogues by calling our own save/restore-the-world
12529 compute_save_world_info (rs6000_stack_t
*info_ptr
)
12531 info_ptr
->world_save_p
= 1;
12532 info_ptr
->world_save_p
12533 = (WORLD_SAVE_P (info_ptr
)
12534 && DEFAULT_ABI
== ABI_DARWIN
12535 && ! (current_function_calls_setjmp
&& flag_exceptions
)
12536 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
12537 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
12538 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
12539 && info_ptr
->cr_save_p
);
12541 /* This will not work in conjunction with sibcalls. Make sure there
12542 are none. (This check is expensive, but seldom executed.) */
12543 if (WORLD_SAVE_P (info_ptr
))
12546 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
12547 if ( GET_CODE (insn
) == CALL_INSN
12548 && SIBLING_CALL_P (insn
))
12550 info_ptr
->world_save_p
= 0;
12555 if (WORLD_SAVE_P (info_ptr
))
12557 /* Even if we're not touching VRsave, make sure there's room on the
12558 stack for it, if it looks like we're calling SAVE_WORLD, which
12559 will attempt to save it. */
12560 info_ptr
->vrsave_size
= 4;
12562 /* "Save" the VRsave register too if we're saving the world. */
12563 if (info_ptr
->vrsave_mask
== 0)
12564 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
12566 /* Because the Darwin register save/restore routines only handle
12567 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12568 check and abort if there's something worng. */
12569 if (info_ptr
->first_fp_reg_save
< FIRST_SAVED_FP_REGNO
12570 || info_ptr
->first_altivec_reg_save
< FIRST_SAVED_ALTIVEC_REGNO
)
12578 is_altivec_return_reg (rtx reg
, void *xyes
)
12580 bool *yes
= (bool *) xyes
;
12581 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
12586 /* Calculate the stack information for the current function. This is
12587 complicated by having two separate calling sequences, the AIX calling
12588 sequence and the V.4 calling sequence.
12590 AIX (and Darwin/Mac OS X) stack frames look like:
12592 SP----> +---------------------------------------+
12593 | back chain to caller | 0 0
12594 +---------------------------------------+
12595 | saved CR | 4 8 (8-11)
12596 +---------------------------------------+
12598 +---------------------------------------+
12599 | reserved for compilers | 12 24
12600 +---------------------------------------+
12601 | reserved for binders | 16 32
12602 +---------------------------------------+
12603 | saved TOC pointer | 20 40
12604 +---------------------------------------+
12605 | Parameter save area (P) | 24 48
12606 +---------------------------------------+
12607 | Alloca space (A) | 24+P etc.
12608 +---------------------------------------+
12609 | Local variable space (L) | 24+P+A
12610 +---------------------------------------+
12611 | Float/int conversion temporary (X) | 24+P+A+L
12612 +---------------------------------------+
12613 | Save area for AltiVec registers (W) | 24+P+A+L+X
12614 +---------------------------------------+
12615 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12616 +---------------------------------------+
12617 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12618 +---------------------------------------+
12619 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12620 +---------------------------------------+
12621 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12622 +---------------------------------------+
12623 old SP->| back chain to caller's caller |
12624 +---------------------------------------+
12626 The required alignment for AIX configurations is two words (i.e., 8
12630 V.4 stack frames look like:
12632 SP----> +---------------------------------------+
12633 | back chain to caller | 0
12634 +---------------------------------------+
12635 | caller's saved LR | 4
12636 +---------------------------------------+
12637 | Parameter save area (P) | 8
12638 +---------------------------------------+
12639 | Alloca space (A) | 8+P
12640 +---------------------------------------+
12641 | Varargs save area (V) | 8+P+A
12642 +---------------------------------------+
12643 | Local variable space (L) | 8+P+A+V
12644 +---------------------------------------+
12645 | Float/int conversion temporary (X) | 8+P+A+V+L
12646 +---------------------------------------+
12647 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12648 +---------------------------------------+
12649 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12650 +---------------------------------------+
12651 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12652 +---------------------------------------+
12653 | SPE: area for 64-bit GP registers |
12654 +---------------------------------------+
12655 | SPE alignment padding |
12656 +---------------------------------------+
12657 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12658 +---------------------------------------+
12659 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12660 +---------------------------------------+
12661 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12662 +---------------------------------------+
12663 old SP->| back chain to caller's caller |
12664 +---------------------------------------+
12666 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12667 given. (But note below and in sysv4.h that we require only 8 and
12668 may round up the size of our stack frame anyways. The historical
12669 reason is early versions of powerpc-linux which didn't properly
12670 align the stack at program startup. A happy side-effect is that
12671 -mno-eabi libraries can be used with -meabi programs.)
12673 The EABI configuration defaults to the V.4 layout. However,
12674 the stack alignment requirements may differ. If -mno-eabi is not
12675 given, the required stack alignment is 8 bytes; if -mno-eabi is
12676 given, the required alignment is 16 bytes. (But see V.4 comment
12679 #ifndef ABI_STACK_BOUNDARY
12680 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12683 static rs6000_stack_t
*
12684 rs6000_stack_info (void)
12686 static rs6000_stack_t info
, zero_info
;
12687 rs6000_stack_t
*info_ptr
= &info
;
12688 int reg_size
= TARGET_32BIT
? 4 : 8;
12691 HOST_WIDE_INT non_fixed_size
;
12693 /* Zero all fields portably. */
12698 /* Cache value so we don't rescan instruction chain over and over. */
12699 if (cfun
->machine
->insn_chain_scanned_p
== 0)
12700 cfun
->machine
->insn_chain_scanned_p
12701 = spe_func_has_64bit_regs_p () + 1;
12702 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
12705 /* Select which calling sequence. */
12706 info_ptr
->abi
= DEFAULT_ABI
;
12708 /* Calculate which registers need to be saved & save area size. */
12709 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
12710 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12711 even if it currently looks like we won't. */
12712 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
12713 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
12714 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
12715 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
12716 info_ptr
->gp_size
= reg_size
* (32 - RS6000_PIC_OFFSET_TABLE_REGNUM
);
12718 info_ptr
->gp_size
= reg_size
* (32 - info_ptr
->first_gp_reg_save
);
12720 /* For the SPE, we have an additional upper 32-bits on each GPR.
12721 Ideally we should save the entire 64-bits only when the upper
12722 half is used in SIMD instructions. Since we only record
12723 registers live (not the size they are used in), this proves
12724 difficult because we'd have to traverse the instruction chain at
12725 the right time, taking reload into account. This is a real pain,
12726 so we opt to save the GPRs in 64-bits always if but one register
12727 gets used in 64-bits. Otherwise, all the registers in the frame
12728 get saved in 32-bits.
12730 So... since when we save all GPRs (except the SP) in 64-bits, the
12731 traditional GP save area will be empty. */
12732 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12733 info_ptr
->gp_size
= 0;
12735 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
12736 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
12738 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
12739 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
12740 - info_ptr
->first_altivec_reg_save
);
12742 /* Does this function call anything? */
12743 info_ptr
->calls_p
= (! current_function_is_leaf
12744 || cfun
->machine
->ra_needs_full_frame
);
12746 /* Determine if we need to save the link register. */
12747 if (rs6000_ra_ever_killed ()
12748 || (DEFAULT_ABI
== ABI_AIX
12749 && current_function_profile
12750 && !TARGET_PROFILE_KERNEL
)
12751 #ifdef TARGET_RELOCATABLE
12752 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
12754 || (info_ptr
->first_fp_reg_save
!= 64
12755 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
12756 || info_ptr
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
12757 || (DEFAULT_ABI
== ABI_V4
&& current_function_calls_alloca
)
12758 || (DEFAULT_ABI
== ABI_DARWIN
12760 && current_function_uses_pic_offset_table
)
12761 || info_ptr
->calls_p
)
12763 info_ptr
->lr_save_p
= 1;
12764 regs_ever_live
[LINK_REGISTER_REGNUM
] = 1;
12767 /* Determine if we need to save the condition code registers. */
12768 if (regs_ever_live
[CR2_REGNO
]
12769 || regs_ever_live
[CR3_REGNO
]
12770 || regs_ever_live
[CR4_REGNO
])
12772 info_ptr
->cr_save_p
= 1;
12773 if (DEFAULT_ABI
== ABI_V4
)
12774 info_ptr
->cr_size
= reg_size
;
12777 /* If the current function calls __builtin_eh_return, then we need
12778 to allocate stack space for registers that will hold data for
12779 the exception handler. */
12780 if (current_function_calls_eh_return
)
12783 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
12786 /* SPE saves EH registers in 64-bits. */
12787 ehrd_size
= i
* (TARGET_SPE_ABI
12788 && info_ptr
->spe_64bit_regs_used
!= 0
12789 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
12794 /* Determine various sizes. */
12795 info_ptr
->reg_size
= reg_size
;
12796 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
12797 info_ptr
->varargs_size
= RS6000_VARARGS_AREA
;
12798 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
12799 info_ptr
->parm_size
= RS6000_ALIGN (current_function_outgoing_args_size
,
12800 TARGET_ALTIVEC
? 16 : 8);
12802 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12803 info_ptr
->spe_gp_size
= 8 * (32 - info_ptr
->first_gp_reg_save
);
12805 info_ptr
->spe_gp_size
= 0;
12807 if (TARGET_ALTIVEC_ABI
)
12808 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
12810 info_ptr
->vrsave_mask
= 0;
12812 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
12813 info_ptr
->vrsave_size
= 4;
12815 info_ptr
->vrsave_size
= 0;
12817 compute_save_world_info (info_ptr
);
12819 /* Calculate the offsets. */
12820 switch (DEFAULT_ABI
)
12828 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
12829 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
12831 if (TARGET_ALTIVEC_ABI
)
12833 info_ptr
->vrsave_save_offset
12834 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
12836 /* Align stack so vector save area is on a quadword boundary. */
12837 if (info_ptr
->altivec_size
!= 0)
12838 info_ptr
->altivec_padding_size
12839 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
12841 info_ptr
->altivec_padding_size
= 0;
12843 info_ptr
->altivec_save_offset
12844 = info_ptr
->vrsave_save_offset
12845 - info_ptr
->altivec_padding_size
12846 - info_ptr
->altivec_size
;
12848 /* Adjust for AltiVec case. */
12849 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
12852 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
12853 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
12854 info_ptr
->lr_save_offset
= 2*reg_size
;
12858 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
12859 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
12860 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
12862 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
12864 /* Align stack so SPE GPR save area is aligned on a
12865 double-word boundary. */
12866 if (info_ptr
->spe_gp_size
!= 0)
12867 info_ptr
->spe_padding_size
12868 = 8 - (-info_ptr
->cr_save_offset
% 8);
12870 info_ptr
->spe_padding_size
= 0;
12872 info_ptr
->spe_gp_save_offset
12873 = info_ptr
->cr_save_offset
12874 - info_ptr
->spe_padding_size
12875 - info_ptr
->spe_gp_size
;
12877 /* Adjust for SPE case. */
12878 info_ptr
->toc_save_offset
12879 = info_ptr
->spe_gp_save_offset
- info_ptr
->toc_size
;
12881 else if (TARGET_ALTIVEC_ABI
)
12883 info_ptr
->vrsave_save_offset
12884 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
12886 /* Align stack so vector save area is on a quadword boundary. */
12887 if (info_ptr
->altivec_size
!= 0)
12888 info_ptr
->altivec_padding_size
12889 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
12891 info_ptr
->altivec_padding_size
= 0;
12893 info_ptr
->altivec_save_offset
12894 = info_ptr
->vrsave_save_offset
12895 - info_ptr
->altivec_padding_size
12896 - info_ptr
->altivec_size
;
12898 /* Adjust for AltiVec case. */
12899 info_ptr
->toc_save_offset
12900 = info_ptr
->altivec_save_offset
- info_ptr
->toc_size
;
12903 info_ptr
->toc_save_offset
= info_ptr
->cr_save_offset
- info_ptr
->toc_size
;
12904 info_ptr
->ehrd_offset
= info_ptr
->toc_save_offset
- ehrd_size
;
12905 info_ptr
->lr_save_offset
= reg_size
;
12909 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
12910 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
12911 + info_ptr
->gp_size
12912 + info_ptr
->altivec_size
12913 + info_ptr
->altivec_padding_size
12914 + info_ptr
->spe_gp_size
12915 + info_ptr
->spe_padding_size
12917 + info_ptr
->cr_size
12918 + info_ptr
->lr_size
12919 + info_ptr
->vrsave_size
12920 + info_ptr
->toc_size
,
12923 non_fixed_size
= (info_ptr
->vars_size
12924 + info_ptr
->parm_size
12925 + info_ptr
->save_size
12926 + info_ptr
->varargs_size
);
12928 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
12929 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
12931 /* Determine if we need to allocate any stack frame:
12933 For AIX we need to push the stack if a frame pointer is needed
12934 (because the stack might be dynamically adjusted), if we are
12935 debugging, if we make calls, or if the sum of fp_save, gp_save,
12936 and local variables are more than the space needed to save all
12937 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12938 + 18*8 = 288 (GPR13 reserved).
12940 For V.4 we don't have the stack cushion that AIX uses, but assume
12941 that the debugger can handle stackless frames. */
12943 if (info_ptr
->calls_p
)
12944 info_ptr
->push_p
= 1;
12946 else if (DEFAULT_ABI
== ABI_V4
)
12947 info_ptr
->push_p
= non_fixed_size
!= 0;
12949 else if (frame_pointer_needed
)
12950 info_ptr
->push_p
= 1;
12952 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
12953 info_ptr
->push_p
= 1;
12956 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
12958 /* Zero offsets if we're not saving those registers. */
12959 if (info_ptr
->fp_size
== 0)
12960 info_ptr
->fp_save_offset
= 0;
12962 if (info_ptr
->gp_size
== 0)
12963 info_ptr
->gp_save_offset
= 0;
12965 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
12966 info_ptr
->altivec_save_offset
= 0;
12968 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
12969 info_ptr
->vrsave_save_offset
= 0;
12971 if (! TARGET_SPE_ABI
12972 || info_ptr
->spe_64bit_regs_used
== 0
12973 || info_ptr
->spe_gp_size
== 0)
12974 info_ptr
->spe_gp_save_offset
= 0;
12976 if (! info_ptr
->lr_save_p
)
12977 info_ptr
->lr_save_offset
= 0;
12979 if (! info_ptr
->cr_save_p
)
12980 info_ptr
->cr_save_offset
= 0;
12982 if (! info_ptr
->toc_save_p
)
12983 info_ptr
->toc_save_offset
= 0;
12988 /* Return true if the current function uses any GPRs in 64-bit SIMD
12992 spe_func_has_64bit_regs_p (void)
12996 /* Functions that save and restore all the call-saved registers will
12997 need to save/restore the registers in 64-bits. */
12998 if (current_function_calls_eh_return
12999 || current_function_calls_setjmp
13000 || current_function_has_nonlocal_goto
)
13003 insns
= get_insns ();
13005 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
13011 /* FIXME: This should be implemented with attributes...
13013 (set_attr "spe64" "true")....then,
13014 if (get_spe64(insn)) return true;
13016 It's the only reliable way to do the stuff below. */
13018 i
= PATTERN (insn
);
13019 if (GET_CODE (i
) == SET
)
13021 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
13023 if (SPE_VECTOR_MODE (mode
))
13025 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
13035 debug_stack_info (rs6000_stack_t
*info
)
13037 const char *abi_string
;
13040 info
= rs6000_stack_info ();
13042 fprintf (stderr
, "\nStack information for function %s:\n",
13043 ((current_function_decl
&& DECL_NAME (current_function_decl
))
13044 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
13049 default: abi_string
= "Unknown"; break;
13050 case ABI_NONE
: abi_string
= "NONE"; break;
13051 case ABI_AIX
: abi_string
= "AIX"; break;
13052 case ABI_DARWIN
: abi_string
= "Darwin"; break;
13053 case ABI_V4
: abi_string
= "V.4"; break;
13056 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
13058 if (TARGET_ALTIVEC_ABI
)
13059 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
13061 if (TARGET_SPE_ABI
)
13062 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
13064 if (info
->first_gp_reg_save
!= 32)
13065 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
13067 if (info
->first_fp_reg_save
!= 64)
13068 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
13070 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
13071 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
13072 info
->first_altivec_reg_save
);
13074 if (info
->lr_save_p
)
13075 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
13077 if (info
->cr_save_p
)
13078 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
13080 if (info
->toc_save_p
)
13081 fprintf (stderr
, "\ttoc_save_p = %5d\n", info
->toc_save_p
);
13083 if (info
->vrsave_mask
)
13084 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
13087 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
13090 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
13092 if (info
->gp_save_offset
)
13093 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
13095 if (info
->fp_save_offset
)
13096 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
13098 if (info
->altivec_save_offset
)
13099 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
13100 info
->altivec_save_offset
);
13102 if (info
->spe_gp_save_offset
)
13103 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
13104 info
->spe_gp_save_offset
);
13106 if (info
->vrsave_save_offset
)
13107 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
13108 info
->vrsave_save_offset
);
13110 if (info
->lr_save_offset
)
13111 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
13113 if (info
->cr_save_offset
)
13114 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
13116 if (info
->toc_save_offset
)
13117 fprintf (stderr
, "\ttoc_save_offset = %5d\n", info
->toc_save_offset
);
13119 if (info
->varargs_save_offset
)
13120 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
13122 if (info
->total_size
)
13123 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
13126 if (info
->varargs_size
)
13127 fprintf (stderr
, "\tvarargs_size = %5d\n", info
->varargs_size
);
13129 if (info
->vars_size
)
13130 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
13133 if (info
->parm_size
)
13134 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
13136 if (info
->fixed_size
)
13137 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
13140 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
13142 if (info
->spe_gp_size
)
13143 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
13146 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
13148 if (info
->altivec_size
)
13149 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
13151 if (info
->vrsave_size
)
13152 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
13154 if (info
->altivec_padding_size
)
13155 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
13156 info
->altivec_padding_size
);
13158 if (info
->spe_padding_size
)
13159 fprintf (stderr
, "\tspe_padding_size = %5d\n",
13160 info
->spe_padding_size
);
13163 fprintf (stderr
, "\tlr_size = %5d\n", info
->lr_size
);
13166 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
13168 if (info
->toc_size
)
13169 fprintf (stderr
, "\ttoc_size = %5d\n", info
->toc_size
);
13171 if (info
->save_size
)
13172 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
13174 if (info
->reg_size
!= 4)
13175 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
13177 fprintf (stderr
, "\n");
13181 rs6000_return_addr (int count
, rtx frame
)
13183 /* Currently we don't optimize very well between prolog and body
13184 code and for PIC code the code can be actually quite bad, so
13185 don't try to be too clever here. */
13186 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
13188 cfun
->machine
->ra_needs_full_frame
= 1;
13195 plus_constant (copy_to_reg
13196 (gen_rtx_MEM (Pmode
,
13197 memory_address (Pmode
, frame
))),
13198 RETURN_ADDRESS_OFFSET
)));
13201 cfun
->machine
->ra_need_lr
= 1;
13202 return get_hard_reg_initial_val (Pmode
, LINK_REGISTER_REGNUM
);
13205 /* Say whether a function is a candidate for sibcall handling or not.
13206 We do not allow indirect calls to be optimized into sibling calls.
13207 Also, we can't do it if there are any vector parameters; there's
13208 nowhere to put the VRsave code so it works; note that functions with
13209 vector parameters are required to have a prototype, so the argument
13210 type info must be available here. (The tail recursion case can work
13211 with vector parameters, but there's no way to distinguish here.) */
13213 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
13218 if (TARGET_ALTIVEC_VRSAVE
)
13220 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
13221 type
; type
= TREE_CHAIN (type
))
13223 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
13227 if (DEFAULT_ABI
== ABI_DARWIN
13228 || (*targetm
.binds_local_p
) (decl
))
13230 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
13232 if (!lookup_attribute ("longcall", attr_list
)
13233 || lookup_attribute ("shortcall", attr_list
))
13241 rs6000_ra_ever_killed (void)
13247 if (current_function_is_thunk
)
13250 /* regs_ever_live has LR marked as used if any sibcalls are present,
13251 but this should not force saving and restoring in the
13252 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13253 clobbers LR, so that is inappropriate. */
13255 /* Also, the prologue can generate a store into LR that
13256 doesn't really count, like this:
13259 bcl to set PIC register
13263 When we're called from the epilogue, we need to avoid counting
13264 this as a store. */
13266 push_topmost_sequence ();
13267 top
= get_insns ();
13268 pop_topmost_sequence ();
13269 reg
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
13271 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
13275 if (FIND_REG_INC_NOTE (insn
, reg
))
13277 else if (GET_CODE (insn
) == CALL_INSN
13278 && !SIBLING_CALL_P (insn
))
13280 else if (set_of (reg
, insn
) != NULL_RTX
13281 && !prologue_epilogue_contains (insn
))
13288 /* Add a REG_MAYBE_DEAD note to the insn. */
13290 rs6000_maybe_dead (rtx insn
)
13292 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
13297 /* Emit instructions needed to load the TOC register.
13298 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13299 a constant pool; or for SVR4 -fpic. */
13302 rs6000_emit_load_toc_table (int fromprolog
)
13305 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
13307 if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
13309 rtx temp
= (fromprolog
13310 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
13311 : gen_reg_rtx (Pmode
));
13312 insn
= emit_insn (gen_load_toc_v4_pic_si (temp
));
13314 rs6000_maybe_dead (insn
);
13315 insn
= emit_move_insn (dest
, temp
);
13317 rs6000_maybe_dead (insn
);
13319 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
13322 rtx tempLR
= (fromprolog
13323 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
13324 : gen_reg_rtx (Pmode
));
13325 rtx temp0
= (fromprolog
13326 ? gen_rtx_REG (Pmode
, 0)
13327 : gen_reg_rtx (Pmode
));
13334 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
13335 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13337 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
13338 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13340 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR
,
13342 rs6000_maybe_dead (emit_move_insn (dest
, tempLR
));
13343 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
,
13350 static int reload_toc_labelno
= 0;
13352 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
13354 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCG", reload_toc_labelno
++);
13355 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13357 emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, symF
, tocsym
));
13358 emit_move_insn (dest
, tempLR
);
13359 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
13361 insn
= emit_insn (gen_addsi3 (dest
, temp0
, dest
));
13363 rs6000_maybe_dead (insn
);
13365 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
13367 /* This is for AIX code running in non-PIC ELF32. */
13370 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
13371 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
13373 insn
= emit_insn (gen_elf_high (dest
, realsym
));
13375 rs6000_maybe_dead (insn
);
13376 insn
= emit_insn (gen_elf_low (dest
, dest
, realsym
));
13378 rs6000_maybe_dead (insn
);
13380 else if (DEFAULT_ABI
== ABI_AIX
)
13383 insn
= emit_insn (gen_load_toc_aix_si (dest
));
13385 insn
= emit_insn (gen_load_toc_aix_di (dest
));
13387 rs6000_maybe_dead (insn
);
13393 /* Emit instructions to restore the link register after determining where
13394 its value has been stored. */
13397 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
13399 rs6000_stack_t
*info
= rs6000_stack_info ();
13402 operands
[0] = source
;
13403 operands
[1] = scratch
;
13405 if (info
->lr_save_p
)
13407 rtx frame_rtx
= stack_pointer_rtx
;
13408 HOST_WIDE_INT sp_offset
= 0;
13411 if (frame_pointer_needed
13412 || current_function_calls_alloca
13413 || info
->total_size
> 32767)
13415 emit_move_insn (operands
[1], gen_rtx_MEM (Pmode
, frame_rtx
));
13416 frame_rtx
= operands
[1];
13418 else if (info
->push_p
)
13419 sp_offset
= info
->total_size
;
13421 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
13422 tmp
= gen_rtx_MEM (Pmode
, tmp
);
13423 emit_move_insn (tmp
, operands
[0]);
13426 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
), operands
[0]);
13429 static GTY(()) int set
= -1;
13432 get_TOC_alias_set (void)
13435 set
= new_alias_set ();
13439 /* This returns nonzero if the current function uses the TOC. This is
13440 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13441 is generated by the ABI_V4 load_toc_* patterns. */
13448 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13451 rtx pat
= PATTERN (insn
);
13454 if (GET_CODE (pat
) == PARALLEL
)
13455 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
13457 rtx sub
= XVECEXP (pat
, 0, i
);
13458 if (GET_CODE (sub
) == USE
)
13460 sub
= XEXP (sub
, 0);
13461 if (GET_CODE (sub
) == UNSPEC
13462 && XINT (sub
, 1) == UNSPEC_TOC
)
13472 create_TOC_reference (rtx symbol
)
13474 return gen_rtx_PLUS (Pmode
,
13475 gen_rtx_REG (Pmode
, TOC_REGISTER
),
13476 gen_rtx_CONST (Pmode
,
13477 gen_rtx_MINUS (Pmode
, symbol
,
13478 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
13481 /* If _Unwind_* has been called from within the same module,
13482 toc register is not guaranteed to be saved to 40(1) on function
13483 entry. Save it there in that case. */
13486 rs6000_aix_emit_builtin_unwind_init (void)
13489 rtx stack_top
= gen_reg_rtx (Pmode
);
13490 rtx opcode_addr
= gen_reg_rtx (Pmode
);
13491 rtx opcode
= gen_reg_rtx (SImode
);
13492 rtx tocompare
= gen_reg_rtx (SImode
);
13493 rtx no_toc_save_needed
= gen_label_rtx ();
13495 mem
= gen_rtx_MEM (Pmode
, hard_frame_pointer_rtx
);
13496 emit_move_insn (stack_top
, mem
);
13498 mem
= gen_rtx_MEM (Pmode
,
13499 gen_rtx_PLUS (Pmode
, stack_top
,
13500 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
13501 emit_move_insn (opcode_addr
, mem
);
13502 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
13503 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
13504 : 0xE8410028, SImode
));
13506 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
13507 SImode
, NULL_RTX
, NULL_RTX
,
13508 no_toc_save_needed
);
13510 mem
= gen_rtx_MEM (Pmode
,
13511 gen_rtx_PLUS (Pmode
, stack_top
,
13512 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
13513 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
13514 emit_label (no_toc_save_needed
);
13517 /* This ties together stack memory (MEM with an alias set of
13518 rs6000_sr_alias_set) and the change to the stack pointer. */
13521 rs6000_emit_stack_tie (void)
13523 rtx mem
= gen_rtx_MEM (BLKmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
13525 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13526 emit_insn (gen_stack_tie (mem
));
13529 /* Emit the correct code for allocating stack space, as insns.
13530 If COPY_R12, make sure a copy of the old frame is left in r12.
13531 The generated code may use hard register 0 as a temporary. */
13534 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
)
13537 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
13538 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
13539 rtx todec
= gen_int_mode (-size
, Pmode
);
13541 if (INTVAL (todec
) != -size
)
13543 warning("stack frame too large");
13544 emit_insn (gen_trap ());
13548 if (current_function_limit_stack
)
13550 if (REG_P (stack_limit_rtx
)
13551 && REGNO (stack_limit_rtx
) > 1
13552 && REGNO (stack_limit_rtx
) <= 31)
13554 emit_insn (TARGET_32BIT
13555 ? gen_addsi3 (tmp_reg
,
13558 : gen_adddi3 (tmp_reg
,
13562 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
13565 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
13567 && DEFAULT_ABI
== ABI_V4
)
13569 rtx toload
= gen_rtx_CONST (VOIDmode
,
13570 gen_rtx_PLUS (Pmode
,
13574 emit_insn (gen_elf_high (tmp_reg
, toload
));
13575 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
13576 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
13580 warning ("stack limit expression is not supported");
13583 if (copy_r12
|| ! TARGET_UPDATE
)
13584 emit_move_insn (gen_rtx_REG (Pmode
, 12), stack_reg
);
13590 /* Need a note here so that try_split doesn't get confused. */
13591 if (get_last_insn() == NULL_RTX
)
13592 emit_note (NOTE_INSN_DELETED
);
13593 insn
= emit_move_insn (tmp_reg
, todec
);
13594 try_split (PATTERN (insn
), insn
, 0);
13598 insn
= emit_insn (TARGET_32BIT
13599 ? gen_movsi_update (stack_reg
, stack_reg
,
13601 : gen_movdi_di_update (stack_reg
, stack_reg
,
13602 todec
, stack_reg
));
13606 insn
= emit_insn (TARGET_32BIT
13607 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
13608 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
13609 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
13610 gen_rtx_REG (Pmode
, 12));
13613 RTX_FRAME_RELATED_P (insn
) = 1;
13615 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13616 gen_rtx_SET (VOIDmode
, stack_reg
,
13617 gen_rtx_PLUS (Pmode
, stack_reg
,
13622 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13623 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13624 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13625 deduce these equivalences by itself so it wasn't necessary to hold
13626 its hand so much. */
13629 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
13630 rtx reg2
, rtx rreg
)
13634 /* copy_rtx will not make unique copies of registers, so we need to
13635 ensure we don't have unwanted sharing here. */
13637 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
13640 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
13642 real
= copy_rtx (PATTERN (insn
));
13644 if (reg2
!= NULL_RTX
)
13645 real
= replace_rtx (real
, reg2
, rreg
);
13647 real
= replace_rtx (real
, reg
,
13648 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
13649 STACK_POINTER_REGNUM
),
13652 /* We expect that 'real' is either a SET or a PARALLEL containing
13653 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13654 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13656 if (GET_CODE (real
) == SET
)
13660 temp
= simplify_rtx (SET_SRC (set
));
13662 SET_SRC (set
) = temp
;
13663 temp
= simplify_rtx (SET_DEST (set
));
13665 SET_DEST (set
) = temp
;
13666 if (GET_CODE (SET_DEST (set
)) == MEM
)
13668 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
13670 XEXP (SET_DEST (set
), 0) = temp
;
13673 else if (GET_CODE (real
) == PARALLEL
)
13676 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
13677 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
13679 rtx set
= XVECEXP (real
, 0, i
);
13681 temp
= simplify_rtx (SET_SRC (set
));
13683 SET_SRC (set
) = temp
;
13684 temp
= simplify_rtx (SET_DEST (set
));
13686 SET_DEST (set
) = temp
;
13687 if (GET_CODE (SET_DEST (set
)) == MEM
)
13689 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
13691 XEXP (SET_DEST (set
), 0) = temp
;
13693 RTX_FRAME_RELATED_P (set
) = 1;
13700 real
= spe_synthesize_frame_save (real
);
13702 RTX_FRAME_RELATED_P (insn
) = 1;
13703 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13708 /* Given an SPE frame note, return a PARALLEL of SETs with the
13709 original note, plus a synthetic register save. */
13712 spe_synthesize_frame_save (rtx real
)
13714 rtx synth
, offset
, reg
, real2
;
13716 if (GET_CODE (real
) != SET
13717 || GET_MODE (SET_SRC (real
)) != V2SImode
)
13720 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13721 frame related note. The parallel contains a set of the register
13722 being saved, and another set to a synthetic register (n+1200).
13723 This is so we can differentiate between 64-bit and 32-bit saves.
13724 Words cannot describe this nastiness. */
13726 if (GET_CODE (SET_DEST (real
)) != MEM
13727 || GET_CODE (XEXP (SET_DEST (real
), 0)) != PLUS
13728 || GET_CODE (SET_SRC (real
)) != REG
)
13732 (set (mem (plus (reg x) (const y)))
13735 (set (mem (plus (reg x) (const y+4)))
13739 real2
= copy_rtx (real
);
13740 PUT_MODE (SET_DEST (real2
), SImode
);
13741 reg
= SET_SRC (real2
);
13742 real2
= replace_rtx (real2
, reg
, gen_rtx_REG (SImode
, REGNO (reg
)));
13743 synth
= copy_rtx (real2
);
13745 if (BYTES_BIG_ENDIAN
)
13747 offset
= XEXP (XEXP (SET_DEST (real2
), 0), 1);
13748 real2
= replace_rtx (real2
, offset
, GEN_INT (INTVAL (offset
) + 4));
13751 reg
= SET_SRC (synth
);
13753 synth
= replace_rtx (synth
, reg
,
13754 gen_rtx_REG (SImode
, REGNO (reg
) + 1200));
13756 offset
= XEXP (XEXP (SET_DEST (synth
), 0), 1);
13757 synth
= replace_rtx (synth
, offset
,
13758 GEN_INT (INTVAL (offset
)
13759 + (BYTES_BIG_ENDIAN
? 0 : 4)));
13761 RTX_FRAME_RELATED_P (synth
) = 1;
13762 RTX_FRAME_RELATED_P (real2
) = 1;
13763 if (BYTES_BIG_ENDIAN
)
13764 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, synth
, real2
));
13766 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, real2
, synth
));
13771 /* Returns an insn that has a vrsave set operation with the
13772 appropriate CLOBBERs. */
13775 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
13778 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
13779 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
13782 = gen_rtx_SET (VOIDmode
,
13784 gen_rtx_UNSPEC_VOLATILE (SImode
,
13785 gen_rtvec (2, reg
, vrsave
),
13790 /* We need to clobber the registers in the mask so the scheduler
13791 does not move sets to VRSAVE before sets of AltiVec registers.
13793 However, if the function receives nonlocal gotos, reload will set
13794 all call saved registers live. We will end up with:
13796 (set (reg 999) (mem))
13797 (parallel [ (set (reg vrsave) (unspec blah))
13798 (clobber (reg 999))])
13800 The clobber will cause the store into reg 999 to be dead, and
13801 flow will attempt to delete an epilogue insn. In this case, we
13802 need an unspec use/set of the register. */
13804 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13805 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
13807 if (!epiloguep
|| call_used_regs
[i
])
13808 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
13809 gen_rtx_REG (V4SImode
, i
));
13812 rtx reg
= gen_rtx_REG (V4SImode
, i
);
13815 = gen_rtx_SET (VOIDmode
,
13817 gen_rtx_UNSPEC (V4SImode
,
13818 gen_rtvec (1, reg
), 27));
13822 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
13824 for (i
= 0; i
< nclobs
; ++i
)
13825 XVECEXP (insn
, 0, i
) = clobs
[i
];
13830 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13831 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13834 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
13835 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
13837 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
13838 rtx replacea
, replaceb
;
13840 int_rtx
= GEN_INT (offset
);
13842 /* Some cases that need register indexed addressing. */
13843 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
13844 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
13846 && SPE_VECTOR_MODE (mode
)
13847 && !SPE_CONST_OFFSET_OK (offset
)))
13849 /* Whomever calls us must make sure r11 is available in the
13850 flow path of instructions in the prologue. */
13851 offset_rtx
= gen_rtx_REG (Pmode
, 11);
13852 emit_move_insn (offset_rtx
, int_rtx
);
13854 replacea
= offset_rtx
;
13855 replaceb
= int_rtx
;
13859 offset_rtx
= int_rtx
;
13860 replacea
= NULL_RTX
;
13861 replaceb
= NULL_RTX
;
13864 reg
= gen_rtx_REG (mode
, regno
);
13865 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
13866 mem
= gen_rtx_MEM (mode
, addr
);
13867 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13869 insn
= emit_move_insn (mem
, reg
);
13871 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
13874 /* Emit an offset memory reference suitable for a frame store, while
13875 converting to a valid addressing mode. */
13878 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
13880 rtx int_rtx
, offset_rtx
;
13882 int_rtx
= GEN_INT (offset
);
13884 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
13885 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
13887 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
13888 emit_move_insn (offset_rtx
, int_rtx
);
13891 offset_rtx
= int_rtx
;
13893 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
13896 #ifndef TARGET_FIX_AND_CONTINUE
13897 #define TARGET_FIX_AND_CONTINUE 0
13900 /* Emit function prologue as insns. */
13903 rs6000_emit_prologue (void)
13905 rs6000_stack_t
*info
= rs6000_stack_info ();
13906 enum machine_mode reg_mode
= Pmode
;
13907 int reg_size
= TARGET_32BIT
? 4 : 8;
13908 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
13909 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
13910 rtx frame_reg_rtx
= sp_reg_rtx
;
13911 rtx cr_save_rtx
= NULL_RTX
;
13913 int saving_FPRs_inline
;
13914 int using_store_multiple
;
13915 HOST_WIDE_INT sp_offset
= 0;
13917 if (TARGET_FIX_AND_CONTINUE
)
13919 /* gdb on darwin arranges to forward a function from the old
13920 address by modifying the first 4 instructions of the function
13921 to branch to the overriding function. This is necessary to
13922 permit function pointers that point to the old function to
13923 actually forward to the new function. */
13924 emit_insn (gen_nop ());
13925 emit_insn (gen_nop ());
13926 emit_insn (gen_nop ());
13927 emit_insn (gen_nop ());
13930 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13932 reg_mode
= V2SImode
;
13936 using_store_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
13937 && (!TARGET_SPE_ABI
13938 || info
->spe_64bit_regs_used
== 0)
13939 && info
->first_gp_reg_save
< 31);
13940 saving_FPRs_inline
= (info
->first_fp_reg_save
== 64
13941 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
13942 || current_function_calls_eh_return
13943 || cfun
->machine
->ra_need_lr
);
13945 /* For V.4, update stack before we do any saving and set back pointer. */
13947 && (DEFAULT_ABI
== ABI_V4
13948 || current_function_calls_eh_return
))
13950 if (info
->total_size
< 32767)
13951 sp_offset
= info
->total_size
;
13953 frame_reg_rtx
= frame_ptr_rtx
;
13954 rs6000_emit_allocate_stack (info
->total_size
,
13955 (frame_reg_rtx
!= sp_reg_rtx
13956 && (info
->cr_save_p
13958 || info
->first_fp_reg_save
< 64
13959 || info
->first_gp_reg_save
< 32
13961 if (frame_reg_rtx
!= sp_reg_rtx
)
13962 rs6000_emit_stack_tie ();
13965 /* Handle world saves specially here. */
13966 if (WORLD_SAVE_P (info
))
13972 /* save_world expects lr in r0. */
13973 if (info
->lr_save_p
)
13975 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
13976 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
13977 RTX_FRAME_RELATED_P (insn
) = 1;
13980 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13981 assumptions about the offsets of various bits of the stack
13982 frame. Abort if things aren't what they should be. */
13983 if (info
->gp_save_offset
!= -220
13984 || info
->fp_save_offset
!= -144
13985 || info
->lr_save_offset
!= 8
13986 || info
->cr_save_offset
!= 4
13988 || !info
->lr_save_p
13989 || (current_function_calls_eh_return
&& info
->ehrd_offset
!= -432)
13990 || (info
->vrsave_save_offset
!= -224
13991 || info
->altivec_save_offset
!= (-224 -16 -192)))
13994 treg
= gen_rtx_REG (SImode
, 11);
13995 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
13997 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13998 in R11. It also clobbers R12, so beware! */
14000 /* Preserve CR2 for save_world prologues */
14002 sz
+= 32 - info
->first_gp_reg_save
;
14003 sz
+= 64 - info
->first_fp_reg_save
;
14004 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
14005 p
= rtvec_alloc (sz
);
14007 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
14008 gen_rtx_REG (Pmode
,
14009 LINK_REGISTER_REGNUM
));
14010 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
14011 gen_rtx_SYMBOL_REF (Pmode
,
14013 /* We do floats first so that the instruction pattern matches
14015 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14017 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14018 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14019 GEN_INT (info
->fp_save_offset
14020 + sp_offset
+ 8 * i
));
14021 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
14022 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14024 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14026 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
14028 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
14029 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14030 GEN_INT (info
->altivec_save_offset
14031 + sp_offset
+ 16 * i
));
14032 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
14033 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14035 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14037 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14039 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14040 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14041 GEN_INT (info
->gp_save_offset
14042 + sp_offset
+ reg_size
* i
));
14043 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14044 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14046 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14050 /* CR register traditionally saved as CR2. */
14051 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
14052 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14053 GEN_INT (info
->cr_save_offset
14055 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14056 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14058 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14060 /* Prevent any attempt to delete the setting of r0 and treg! */
14061 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
14062 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, treg
);
14063 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
, sp_reg_rtx
);
14065 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14066 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14067 NULL_RTX
, NULL_RTX
);
14069 if (current_function_calls_eh_return
)
14074 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
14075 if (regno
== INVALID_REGNUM
)
14077 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
14078 info
->ehrd_offset
+ sp_offset
14079 + reg_size
* (int) i
,
14085 /* Save AltiVec registers if needed. */
14086 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
14090 /* There should be a non inline version of this, for when we
14091 are saving lots of vector registers. */
14092 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14093 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
14095 rtx areg
, savereg
, mem
;
14098 offset
= info
->altivec_save_offset
+ sp_offset
14099 + 16 * (i
- info
->first_altivec_reg_save
);
14101 savereg
= gen_rtx_REG (V4SImode
, i
);
14103 areg
= gen_rtx_REG (Pmode
, 0);
14104 emit_move_insn (areg
, GEN_INT (offset
));
14106 /* AltiVec addressing mode is [reg+reg]. */
14107 mem
= gen_rtx_MEM (V4SImode
,
14108 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
14110 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14112 insn
= emit_move_insn (mem
, savereg
);
14114 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14115 areg
, GEN_INT (offset
));
14119 /* VRSAVE is a bit vector representing which AltiVec registers
14120 are used. The OS uses this to determine which vector
14121 registers to save on a context switch. We need to save
14122 VRSAVE on the stack frame, add whatever AltiVec registers we
14123 used in this function, and do the corresponding magic in the
14126 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
14127 && !WORLD_SAVE_P (info
) && info
->vrsave_mask
!= 0)
14129 rtx reg
, mem
, vrsave
;
14132 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14133 as frame_reg_rtx and r11 as the static chain pointer for
14134 nested functions. */
14135 reg
= gen_rtx_REG (SImode
, 0);
14136 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
14138 emit_insn (gen_get_vrsave_internal (reg
));
14140 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
14143 offset
= info
->vrsave_save_offset
+ sp_offset
;
14145 = gen_rtx_MEM (SImode
,
14146 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, GEN_INT (offset
)));
14147 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14148 insn
= emit_move_insn (mem
, reg
);
14150 /* Include the registers in the mask. */
14151 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
14153 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
14156 /* If we use the link register, get it into r0. */
14157 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
14159 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
14160 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
14161 RTX_FRAME_RELATED_P (insn
) = 1;
14164 /* If we need to save CR, put it into r12. */
14165 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
14169 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
14170 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
14171 RTX_FRAME_RELATED_P (insn
) = 1;
14172 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14173 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14174 But that's OK. All we have to do is specify that _one_ condition
14175 code register is saved in this stack slot. The thrower's epilogue
14176 will then restore all the call-saved registers.
14177 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14178 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
14179 gen_rtx_REG (SImode
, CR2_REGNO
));
14180 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14185 /* Do any required saving of fpr's. If only one or two to save, do
14186 it ourselves. Otherwise, call function. */
14187 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
14190 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14191 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
14192 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
14193 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
14194 info
->first_fp_reg_save
+ i
,
14195 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
14198 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
14202 const char *alloc_rname
;
14204 p
= rtvec_alloc (2 + 64 - info
->first_fp_reg_save
);
14206 RTVEC_ELT (p
, 0) = gen_rtx_CLOBBER (VOIDmode
,
14207 gen_rtx_REG (Pmode
,
14208 LINK_REGISTER_REGNUM
));
14209 sprintf (rname
, "%s%d%s", SAVE_FP_PREFIX
,
14210 info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
);
14211 alloc_rname
= ggc_strdup (rname
);
14212 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
14213 gen_rtx_SYMBOL_REF (Pmode
,
14215 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14217 rtx addr
, reg
, mem
;
14218 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14219 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14220 GEN_INT (info
->fp_save_offset
14221 + sp_offset
+ 8*i
));
14222 mem
= gen_rtx_MEM (DFmode
, addr
);
14223 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14225 RTVEC_ELT (p
, i
+ 2) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14227 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14228 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14229 NULL_RTX
, NULL_RTX
);
14232 /* Save GPRs. This is done as a PARALLEL if we are using
14233 the store-multiple instructions. */
14234 if (!WORLD_SAVE_P (info
) && using_store_multiple
)
14238 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
14239 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14241 rtx addr
, reg
, mem
;
14242 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14243 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14244 GEN_INT (info
->gp_save_offset
14247 mem
= gen_rtx_MEM (reg_mode
, addr
);
14248 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14250 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
14252 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14253 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14254 NULL_RTX
, NULL_RTX
);
14256 else if (!WORLD_SAVE_P (info
))
14259 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14260 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
14261 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
14262 || (i
+info
->first_gp_reg_save
14263 == RS6000_PIC_OFFSET_TABLE_REGNUM
14264 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
14265 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14266 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14267 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
14269 rtx addr
, reg
, mem
;
14270 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14272 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14274 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
14277 if (!SPE_CONST_OFFSET_OK (offset
))
14279 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
14280 emit_move_insn (b
, GEN_INT (offset
));
14283 b
= GEN_INT (offset
);
14285 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
14286 mem
= gen_rtx_MEM (V2SImode
, addr
);
14287 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14288 insn
= emit_move_insn (mem
, reg
);
14290 if (GET_CODE (b
) == CONST_INT
)
14291 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14292 NULL_RTX
, NULL_RTX
);
14294 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14295 b
, GEN_INT (offset
));
14299 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14300 GEN_INT (info
->gp_save_offset
14303 mem
= gen_rtx_MEM (reg_mode
, addr
);
14304 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14306 insn
= emit_move_insn (mem
, reg
);
14307 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14308 NULL_RTX
, NULL_RTX
);
14313 /* ??? There's no need to emit actual instructions here, but it's the
14314 easiest way to get the frame unwind information emitted. */
14315 if (!WORLD_SAVE_P (info
) && current_function_calls_eh_return
)
14317 unsigned int i
, regno
;
14319 /* In AIX ABI we need to pretend we save r2 here. */
14322 rtx addr
, reg
, mem
;
14324 reg
= gen_rtx_REG (reg_mode
, 2);
14325 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14326 GEN_INT (sp_offset
+ 5 * reg_size
));
14327 mem
= gen_rtx_MEM (reg_mode
, addr
);
14328 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14330 insn
= emit_move_insn (mem
, reg
);
14331 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14332 NULL_RTX
, NULL_RTX
);
14333 PATTERN (insn
) = gen_blockage ();
14338 regno
= EH_RETURN_DATA_REGNO (i
);
14339 if (regno
== INVALID_REGNUM
)
14342 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
14343 info
->ehrd_offset
+ sp_offset
14344 + reg_size
* (int) i
,
14349 /* Save lr if we used it. */
14350 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
14352 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14353 GEN_INT (info
->lr_save_offset
+ sp_offset
));
14354 rtx reg
= gen_rtx_REG (Pmode
, 0);
14355 rtx mem
= gen_rtx_MEM (Pmode
, addr
);
14356 /* This should not be of rs6000_sr_alias_set, because of
14357 __builtin_return_address. */
14359 insn
= emit_move_insn (mem
, reg
);
14360 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14361 NULL_RTX
, NULL_RTX
);
14364 /* Save CR if we use any that must be preserved. */
14365 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
14367 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14368 GEN_INT (info
->cr_save_offset
+ sp_offset
));
14369 rtx mem
= gen_rtx_MEM (SImode
, addr
);
14370 /* See the large comment above about why CR2_REGNO is used. */
14371 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
14373 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14375 /* If r12 was used to hold the original sp, copy cr into r0 now
14377 if (REGNO (frame_reg_rtx
) == 12)
14381 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
14382 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
14383 RTX_FRAME_RELATED_P (insn
) = 1;
14384 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
14385 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14390 insn
= emit_move_insn (mem
, cr_save_rtx
);
14392 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
14393 NULL_RTX
, NULL_RTX
);
14396 /* Update stack and set back pointer unless this is V.4,
14397 for which it was done previously. */
14398 if (!WORLD_SAVE_P (info
) && info
->push_p
14399 && !(DEFAULT_ABI
== ABI_V4
|| current_function_calls_eh_return
))
14400 rs6000_emit_allocate_stack (info
->total_size
, FALSE
);
14402 /* Set frame pointer, if needed. */
14403 if (frame_pointer_needed
)
14405 insn
= emit_move_insn (gen_rtx_REG (Pmode
, FRAME_POINTER_REGNUM
),
14407 RTX_FRAME_RELATED_P (insn
) = 1;
14410 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14411 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
14412 || (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1
14413 && regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
]))
14415 /* If emit_load_toc_table will use the link register, we need to save
14416 it. We use R12 for this purpose because emit_load_toc_table
14417 can use register 0. This allows us to use a plain 'blr' to return
14418 from the procedure more often. */
14419 int save_LR_around_toc_setup
= (TARGET_ELF
14420 && DEFAULT_ABI
!= ABI_AIX
14422 && ! info
->lr_save_p
14423 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
14424 if (save_LR_around_toc_setup
)
14426 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
14428 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
14429 rs6000_maybe_dead (insn
);
14430 RTX_FRAME_RELATED_P (insn
) = 1;
14432 rs6000_emit_load_toc_table (TRUE
);
14434 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
14435 rs6000_maybe_dead (insn
);
14436 RTX_FRAME_RELATED_P (insn
) = 1;
14439 rs6000_emit_load_toc_table (TRUE
);
14443 if (DEFAULT_ABI
== ABI_DARWIN
14444 && flag_pic
&& current_function_uses_pic_offset_table
)
14446 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
14447 rtx src
= machopic_function_base_sym ();
14449 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr
, src
)));
14451 insn
= emit_move_insn (gen_rtx_REG (Pmode
,
14452 RS6000_PIC_OFFSET_TABLE_REGNUM
),
14454 rs6000_maybe_dead (insn
);
14459 /* Write function prologue. */
14462 rs6000_output_function_prologue (FILE *file
,
14463 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
14465 rs6000_stack_t
*info
= rs6000_stack_info ();
14467 if (TARGET_DEBUG_STACK
)
14468 debug_stack_info (info
);
14470 /* Write .extern for any function we will call to save and restore
14472 if (info
->first_fp_reg_save
< 64
14473 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
14474 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14475 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
14476 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32,
14477 RESTORE_FP_SUFFIX
);
14479 /* Write .extern for AIX common mode routines, if needed. */
14480 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
14482 fputs ("\t.extern __mulh\n", file
);
14483 fputs ("\t.extern __mull\n", file
);
14484 fputs ("\t.extern __divss\n", file
);
14485 fputs ("\t.extern __divus\n", file
);
14486 fputs ("\t.extern __quoss\n", file
);
14487 fputs ("\t.extern __quous\n", file
);
14488 common_mode_defined
= 1;
14491 if (! HAVE_prologue
)
14495 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14496 the "toplevel" insn chain. */
14497 emit_note (NOTE_INSN_DELETED
);
14498 rs6000_emit_prologue ();
14499 emit_note (NOTE_INSN_DELETED
);
14501 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14505 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
14507 INSN_ADDRESSES_NEW (insn
, addr
);
14512 if (TARGET_DEBUG_STACK
)
14513 debug_rtx_list (get_insns (), 100);
14514 final (get_insns (), file
, FALSE
, FALSE
);
14518 rs6000_pic_labelno
++;
14521 /* Emit function epilogue as insns.
14523 At present, dwarf2out_frame_debug_expr doesn't understand
14524 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14525 anywhere in the epilogue. Most of the insns below would in any case
14526 need special notes to explain where r11 is in relation to the stack. */
14529 rs6000_emit_epilogue (int sibcall
)
14531 rs6000_stack_t
*info
;
14532 int restoring_FPRs_inline
;
14533 int using_load_multiple
;
14534 int using_mfcr_multiple
;
14535 int use_backchain_to_restore_sp
;
14537 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
14538 rtx frame_reg_rtx
= sp_reg_rtx
;
14539 enum machine_mode reg_mode
= Pmode
;
14540 int reg_size
= TARGET_32BIT
? 4 : 8;
14543 info
= rs6000_stack_info ();
14545 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14547 reg_mode
= V2SImode
;
14551 using_load_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
14552 && (!TARGET_SPE_ABI
14553 || info
->spe_64bit_regs_used
== 0)
14554 && info
->first_gp_reg_save
< 31);
14555 restoring_FPRs_inline
= (sibcall
14556 || current_function_calls_eh_return
14557 || info
->first_fp_reg_save
== 64
14558 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
14559 use_backchain_to_restore_sp
= (frame_pointer_needed
14560 || current_function_calls_alloca
14561 || info
->total_size
> 32767);
14562 using_mfcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
14563 || rs6000_cpu
== PROCESSOR_PPC603
14564 || rs6000_cpu
== PROCESSOR_PPC750
14567 if (WORLD_SAVE_P (info
))
14571 const char *alloc_rname
;
14574 /* eh_rest_world_r10 will return to the location saved in the LR
14575 stack slot (which is not likely to be our caller.)
14576 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14577 rest_world is similar, except any R10 parameter is ignored.
14578 The exception-handling stuff that was here in 2.95 is no
14579 longer necessary. */
14583 + 32 - info
->first_gp_reg_save
14584 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
14585 + 63 + 1 - info
->first_fp_reg_save
);
14587 strcpy (rname
, ((current_function_calls_eh_return
) ?
14588 "*eh_rest_world_r10" : "*rest_world"));
14589 alloc_rname
= ggc_strdup (rname
);
14592 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
14593 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
14594 gen_rtx_REG (Pmode
,
14595 LINK_REGISTER_REGNUM
));
14597 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
14598 /* The instruction pattern requires a clobber here;
14599 it is shared with the restVEC helper. */
14601 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
14604 /* CR register traditionally saved as CR2. */
14605 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
14606 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14607 GEN_INT (info
->cr_save_offset
));
14608 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14609 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14611 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14614 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14616 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
14617 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14618 GEN_INT (info
->gp_save_offset
14620 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14621 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14623 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14625 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
14627 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
14628 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14629 GEN_INT (info
->altivec_save_offset
14631 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
14632 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14634 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14636 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
14638 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
14639 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14640 GEN_INT (info
->fp_save_offset
14642 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
14643 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14645 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
14648 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
14650 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
14652 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
14654 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
14656 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
14657 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14662 /* If we have a frame pointer, a call to alloca, or a large stack
14663 frame, restore the old stack pointer using the backchain. Otherwise,
14664 we know what size to update it with. */
14665 if (use_backchain_to_restore_sp
)
14667 /* Under V.4, don't reset the stack pointer until after we're done
14668 loading the saved registers. */
14669 if (DEFAULT_ABI
== ABI_V4
)
14670 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
14672 emit_move_insn (frame_reg_rtx
,
14673 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
14676 else if (info
->push_p
)
14678 if (DEFAULT_ABI
== ABI_V4
14679 || current_function_calls_eh_return
)
14680 sp_offset
= info
->total_size
;
14683 emit_insn (TARGET_32BIT
14684 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
14685 GEN_INT (info
->total_size
))
14686 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
14687 GEN_INT (info
->total_size
)));
14691 /* Restore AltiVec registers if needed. */
14692 if (TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
14696 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14697 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
14699 rtx addr
, areg
, mem
;
14701 areg
= gen_rtx_REG (Pmode
, 0);
14703 (areg
, GEN_INT (info
->altivec_save_offset
14705 + 16 * (i
- info
->first_altivec_reg_save
)));
14707 /* AltiVec addressing mode is [reg+reg]. */
14708 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
14709 mem
= gen_rtx_MEM (V4SImode
, addr
);
14710 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14712 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
14716 /* Restore VRSAVE if needed. */
14717 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
14718 && info
->vrsave_mask
!= 0)
14720 rtx addr
, mem
, reg
;
14722 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14723 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
14724 mem
= gen_rtx_MEM (SImode
, addr
);
14725 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14726 reg
= gen_rtx_REG (SImode
, 12);
14727 emit_move_insn (reg
, mem
);
14729 emit_insn (generate_set_vrsave (reg
, info
, 1));
14732 /* Get the old lr if we saved it. */
14733 if (info
->lr_save_p
)
14735 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
14736 info
->lr_save_offset
+ sp_offset
);
14738 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14740 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
14743 /* Get the old cr if we saved it. */
14744 if (info
->cr_save_p
)
14746 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14747 GEN_INT (info
->cr_save_offset
+ sp_offset
));
14748 rtx mem
= gen_rtx_MEM (SImode
, addr
);
14750 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14752 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
14755 /* Set LR here to try to overlap restores below. */
14756 if (info
->lr_save_p
)
14757 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
),
14758 gen_rtx_REG (Pmode
, 0));
14760 /* Load exception handler data registers, if needed. */
14761 if (current_function_calls_eh_return
)
14763 unsigned int i
, regno
;
14767 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14768 GEN_INT (sp_offset
+ 5 * reg_size
));
14769 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14771 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14773 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
14780 regno
= EH_RETURN_DATA_REGNO (i
);
14781 if (regno
== INVALID_REGNUM
)
14784 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
14785 info
->ehrd_offset
+ sp_offset
14786 + reg_size
* (int) i
);
14787 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14789 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
14793 /* Restore GPRs. This is done as a PARALLEL if we are using
14794 the load-multiple instructions. */
14795 if (using_load_multiple
)
14798 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
14799 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14801 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14802 GEN_INT (info
->gp_save_offset
14805 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14807 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14810 gen_rtx_SET (VOIDmode
,
14811 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
14814 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14817 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
14818 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
14819 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
14820 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14821 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
14822 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
14823 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14824 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
14826 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14827 GEN_INT (info
->gp_save_offset
14830 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
14832 /* Restore 64-bit quantities for SPE. */
14833 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
14835 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
14838 if (!SPE_CONST_OFFSET_OK (offset
))
14840 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
14841 emit_move_insn (b
, GEN_INT (offset
));
14844 b
= GEN_INT (offset
);
14846 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
14847 mem
= gen_rtx_MEM (V2SImode
, addr
);
14850 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14852 emit_move_insn (gen_rtx_REG (reg_mode
,
14853 info
->first_gp_reg_save
+ i
), mem
);
14856 /* Restore fpr's if we need to do it without calling a function. */
14857 if (restoring_FPRs_inline
)
14858 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14859 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
14860 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
14863 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
14864 GEN_INT (info
->fp_save_offset
14867 mem
= gen_rtx_MEM (DFmode
, addr
);
14868 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14870 emit_move_insn (gen_rtx_REG (DFmode
,
14871 info
->first_fp_reg_save
+ i
),
14875 /* If we saved cr, restore it here. Just those that were used. */
14876 if (info
->cr_save_p
)
14878 rtx r12_rtx
= gen_rtx_REG (SImode
, 12);
14881 if (using_mfcr_multiple
)
14883 for (i
= 0; i
< 8; i
++)
14884 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14890 if (using_mfcr_multiple
&& count
> 1)
14895 p
= rtvec_alloc (count
);
14898 for (i
= 0; i
< 8; i
++)
14899 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14901 rtvec r
= rtvec_alloc (2);
14902 RTVEC_ELT (r
, 0) = r12_rtx
;
14903 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
14904 RTVEC_ELT (p
, ndx
) =
14905 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
14906 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
14909 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
14914 for (i
= 0; i
< 8; i
++)
14915 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
14917 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
14923 /* If this is V.4, unwind the stack pointer after all of the loads
14924 have been done. We need to emit a block here so that sched
14925 doesn't decide to move the sp change before the register restores
14926 (which may not have any obvious dependency on the stack). This
14927 doesn't hurt performance, because there is no scheduling that can
14928 be done after this point. */
14929 if (DEFAULT_ABI
== ABI_V4
14930 || current_function_calls_eh_return
)
14932 if (frame_reg_rtx
!= sp_reg_rtx
)
14933 rs6000_emit_stack_tie ();
14935 if (use_backchain_to_restore_sp
)
14937 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
14939 else if (sp_offset
!= 0)
14941 emit_insn (TARGET_32BIT
14942 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
14943 GEN_INT (sp_offset
))
14944 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
14945 GEN_INT (sp_offset
)));
14949 if (current_function_calls_eh_return
)
14951 rtx sa
= EH_RETURN_STACKADJ_RTX
;
14952 emit_insn (TARGET_32BIT
14953 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
14954 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
14960 if (! restoring_FPRs_inline
)
14961 p
= rtvec_alloc (3 + 64 - info
->first_fp_reg_save
);
14963 p
= rtvec_alloc (2);
14965 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
14966 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
14967 gen_rtx_REG (Pmode
,
14968 LINK_REGISTER_REGNUM
));
14970 /* If we have to restore more than two FP registers, branch to the
14971 restore function. It will return to our caller. */
14972 if (! restoring_FPRs_inline
)
14976 const char *alloc_rname
;
14978 sprintf (rname
, "%s%d%s", RESTORE_FP_PREFIX
,
14979 info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
14980 alloc_rname
= ggc_strdup (rname
);
14981 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
,
14982 gen_rtx_SYMBOL_REF (Pmode
,
14985 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
14988 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
14989 GEN_INT (info
->fp_save_offset
+ 8*i
));
14990 mem
= gen_rtx_MEM (DFmode
, addr
);
14991 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
14993 RTVEC_ELT (p
, i
+3) =
14994 gen_rtx_SET (VOIDmode
,
14995 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
15000 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15004 /* Write function epilogue. */
15007 rs6000_output_function_epilogue (FILE *file
,
15008 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
15010 rs6000_stack_t
*info
= rs6000_stack_info ();
15012 if (! HAVE_epilogue
)
15014 rtx insn
= get_last_insn ();
15015 /* If the last insn was a BARRIER, we don't have to write anything except
15016 the trace table. */
15017 if (GET_CODE (insn
) == NOTE
)
15018 insn
= prev_nonnote_insn (insn
);
15019 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
15021 /* This is slightly ugly, but at least we don't have two
15022 copies of the epilogue-emitting code. */
15025 /* A NOTE_INSN_DELETED is supposed to be at the start
15026 and end of the "toplevel" insn chain. */
15027 emit_note (NOTE_INSN_DELETED
);
15028 rs6000_emit_epilogue (FALSE
);
15029 emit_note (NOTE_INSN_DELETED
);
15031 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15035 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
15037 INSN_ADDRESSES_NEW (insn
, addr
);
15042 if (TARGET_DEBUG_STACK
)
15043 debug_rtx_list (get_insns (), 100);
15044 final (get_insns (), file
, FALSE
, FALSE
);
15050 macho_branch_islands ();
15051 /* Mach-O doesn't support labels at the end of objects, so if
15052 it looks like we might want one, insert a NOP. */
15054 rtx insn
= get_last_insn ();
15057 && NOTE_LINE_NUMBER (insn
) != NOTE_INSN_DELETED_LABEL
)
15058 insn
= PREV_INSN (insn
);
15062 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED_LABEL
)))
15063 fputs ("\tnop\n", file
);
15067 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15070 We don't output a traceback table if -finhibit-size-directive was
15071 used. The documentation for -finhibit-size-directive reads
15072 ``don't output a @code{.size} assembler directive, or anything
15073 else that would cause trouble if the function is split in the
15074 middle, and the two halves are placed at locations far apart in
15075 memory.'' The traceback table has this property, since it
15076 includes the offset from the start of the function to the
15077 traceback table itself.
15079 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15080 different traceback table. */
15081 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
15082 && rs6000_traceback
!= traceback_none
)
15084 const char *fname
= NULL
;
15085 const char *language_string
= lang_hooks
.name
;
15086 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
15088 int optional_tbtab
;
15090 if (rs6000_traceback
== traceback_full
)
15091 optional_tbtab
= 1;
15092 else if (rs6000_traceback
== traceback_part
)
15093 optional_tbtab
= 0;
15095 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
15097 if (optional_tbtab
)
15099 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
15100 while (*fname
== '.') /* V.4 encodes . in the name */
15103 /* Need label immediately before tbtab, so we can compute
15104 its offset from the function start. */
15105 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
15106 ASM_OUTPUT_LABEL (file
, fname
);
15109 /* The .tbtab pseudo-op can only be used for the first eight
15110 expressions, since it can't handle the possibly variable
15111 length fields that follow. However, if you omit the optional
15112 fields, the assembler outputs zeros for all optional fields
15113 anyways, giving each variable length field is minimum length
15114 (as defined in sys/debug.h). Thus we can not use the .tbtab
15115 pseudo-op at all. */
15117 /* An all-zero word flags the start of the tbtab, for debuggers
15118 that have to find it by searching forward from the entry
15119 point or from the current pc. */
15120 fputs ("\t.long 0\n", file
);
15122 /* Tbtab format type. Use format type 0. */
15123 fputs ("\t.byte 0,", file
);
15125 /* Language type. Unfortunately, there does not seem to be any
15126 official way to discover the language being compiled, so we
15127 use language_string.
15128 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15129 Java is 13. Objective-C is 14. */
15130 if (! strcmp (language_string
, "GNU C"))
15132 else if (! strcmp (language_string
, "GNU F77")
15133 || ! strcmp (language_string
, "GNU F95"))
15135 else if (! strcmp (language_string
, "GNU Pascal"))
15137 else if (! strcmp (language_string
, "GNU Ada"))
15139 else if (! strcmp (language_string
, "GNU C++"))
15141 else if (! strcmp (language_string
, "GNU Java"))
15143 else if (! strcmp (language_string
, "GNU Objective-C"))
15147 fprintf (file
, "%d,", i
);
15149 /* 8 single bit fields: global linkage (not set for C extern linkage,
15150 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15151 from start of procedure stored in tbtab, internal function, function
15152 has controlled storage, function has no toc, function uses fp,
15153 function logs/aborts fp operations. */
15154 /* Assume that fp operations are used if any fp reg must be saved. */
15155 fprintf (file
, "%d,",
15156 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
15158 /* 6 bitfields: function is interrupt handler, name present in
15159 proc table, function calls alloca, on condition directives
15160 (controls stack walks, 3 bits), saves condition reg, saves
15162 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15163 set up as a frame pointer, even when there is no alloca call. */
15164 fprintf (file
, "%d,",
15165 ((optional_tbtab
<< 6)
15166 | ((optional_tbtab
& frame_pointer_needed
) << 5)
15167 | (info
->cr_save_p
<< 1)
15168 | (info
->lr_save_p
)));
15170 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15172 fprintf (file
, "%d,",
15173 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
15175 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15176 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
15178 if (optional_tbtab
)
15180 /* Compute the parameter info from the function decl argument
15183 int next_parm_info_bit
= 31;
15185 for (decl
= DECL_ARGUMENTS (current_function_decl
);
15186 decl
; decl
= TREE_CHAIN (decl
))
15188 rtx parameter
= DECL_INCOMING_RTL (decl
);
15189 enum machine_mode mode
= GET_MODE (parameter
);
15191 if (GET_CODE (parameter
) == REG
)
15193 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
15199 if (mode
== SFmode
)
15201 else if (mode
== DFmode
|| mode
== TFmode
)
15206 /* If only one bit will fit, don't or in this entry. */
15207 if (next_parm_info_bit
> 0)
15208 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
15209 next_parm_info_bit
-= 2;
15213 fixed_parms
+= ((GET_MODE_SIZE (mode
)
15214 + (UNITS_PER_WORD
- 1))
15216 next_parm_info_bit
-= 1;
15222 /* Number of fixed point parameters. */
15223 /* This is actually the number of words of fixed point parameters; thus
15224 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15225 fprintf (file
, "%d,", fixed_parms
);
15227 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15229 /* This is actually the number of fp registers that hold parameters;
15230 and thus the maximum value is 13. */
15231 /* Set parameters on stack bit if parameters are not in their original
15232 registers, regardless of whether they are on the stack? Xlc
15233 seems to set the bit when not optimizing. */
15234 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
15236 if (! optional_tbtab
)
15239 /* Optional fields follow. Some are variable length. */
15241 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15242 11 double float. */
15243 /* There is an entry for each parameter in a register, in the order that
15244 they occur in the parameter list. Any intervening arguments on the
15245 stack are ignored. If the list overflows a long (max possible length
15246 34 bits) then completely leave off all elements that don't fit. */
15247 /* Only emit this long if there was at least one parameter. */
15248 if (fixed_parms
|| float_parms
)
15249 fprintf (file
, "\t.long %d\n", parm_info
);
15251 /* Offset from start of code to tb table. */
15252 fputs ("\t.long ", file
);
15253 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
15255 RS6000_OUTPUT_BASENAME (file
, fname
);
15257 assemble_name (file
, fname
);
15259 rs6000_output_function_entry (file
, fname
);
15262 /* Interrupt handler mask. */
15263 /* Omit this long, since we never set the interrupt handler bit
15266 /* Number of CTL (controlled storage) anchors. */
15267 /* Omit this long, since the has_ctl bit is never set above. */
15269 /* Displacement into stack of each CTL anchor. */
15270 /* Omit this list of longs, because there are no CTL anchors. */
15272 /* Length of function name. */
15275 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
15277 /* Function name. */
15278 assemble_string (fname
, strlen (fname
));
15280 /* Register for alloca automatic storage; this is always reg 31.
15281 Only emit this if the alloca bit was set above. */
15282 if (frame_pointer_needed
)
15283 fputs ("\t.byte 31\n", file
);
15285 fputs ("\t.align 2\n", file
);
15289 /* A C compound statement that outputs the assembler code for a thunk
15290 function, used to implement C++ virtual function calls with
15291 multiple inheritance. The thunk acts as a wrapper around a virtual
15292 function, adjusting the implicit object parameter before handing
15293 control off to the real function.
15295 First, emit code to add the integer DELTA to the location that
15296 contains the incoming first argument. Assume that this argument
15297 contains a pointer, and is the one used to pass the `this' pointer
15298 in C++. This is the incoming argument *before* the function
15299 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15300 values of all other incoming arguments.
15302 After the addition, emit code to jump to FUNCTION, which is a
15303 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15304 not touch the return address. Hence returning from FUNCTION will
15305 return to whoever called the current `thunk'.
15307 The effect must be as if FUNCTION had been called directly with the
15308 adjusted first argument. This macro is responsible for emitting
15309 all of the code for a thunk function; output_function_prologue()
15310 and output_function_epilogue() are not invoked.
15312 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15313 been extracted from it.) It might possibly be useful on some
15314 targets, but probably not.
15316 If you do not define this macro, the target-independent code in the
15317 C++ frontend will generate a less efficient heavyweight thunk that
15318 calls FUNCTION instead of jumping to it. The generic approach does
15319 not support varargs. */
15322 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
15323 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
15326 rtx
this, insn
, funexp
;
15328 reload_completed
= 1;
15329 epilogue_completed
= 1;
15330 no_new_pseudos
= 1;
15331 reset_block_changes ();
15333 /* Mark the end of the (empty) prologue. */
15334 emit_note (NOTE_INSN_PROLOGUE_END
);
15336 /* Find the "this" pointer. If the function returns a structure,
15337 the structure return pointer is in r3. */
15338 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
15339 this = gen_rtx_REG (Pmode
, 4);
15341 this = gen_rtx_REG (Pmode
, 3);
15343 /* Apply the constant offset, if required. */
15346 rtx delta_rtx
= GEN_INT (delta
);
15347 emit_insn (TARGET_32BIT
15348 ? gen_addsi3 (this, this, delta_rtx
)
15349 : gen_adddi3 (this, this, delta_rtx
));
15352 /* Apply the offset from the vtable, if required. */
15355 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
15356 rtx tmp
= gen_rtx_REG (Pmode
, 12);
15358 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
15359 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
15361 emit_insn (TARGET_32BIT
15362 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
15363 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
15364 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
15368 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
15370 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
15372 emit_insn (TARGET_32BIT
15373 ? gen_addsi3 (this, this, tmp
)
15374 : gen_adddi3 (this, this, tmp
));
15377 /* Generate a tail call to the target function. */
15378 if (!TREE_USED (function
))
15380 assemble_external (function
);
15381 TREE_USED (function
) = 1;
15383 funexp
= XEXP (DECL_RTL (function
), 0);
15384 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
15387 if (MACHOPIC_INDIRECT
)
15388 funexp
= machopic_indirect_call_target (funexp
);
15391 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15392 generate sibcall RTL explicitly to avoid constraint abort. */
15393 insn
= emit_call_insn (
15394 gen_rtx_PARALLEL (VOIDmode
,
15396 gen_rtx_CALL (VOIDmode
,
15397 funexp
, const0_rtx
),
15398 gen_rtx_USE (VOIDmode
, const0_rtx
),
15399 gen_rtx_USE (VOIDmode
,
15400 gen_rtx_REG (SImode
,
15401 LINK_REGISTER_REGNUM
)),
15402 gen_rtx_RETURN (VOIDmode
))));
15403 SIBLING_CALL_P (insn
) = 1;
15406 /* Run just enough of rest_of_compilation to get the insns emitted.
15407 There's not really enough bulk here to make other passes such as
15408 instruction scheduling worth while. Note that use_thunk calls
15409 assemble_start_function and assemble_end_function. */
15410 insn
= get_insns ();
15411 insn_locators_initialize ();
15412 shorten_branches (insn
);
15413 final_start_function (insn
, file
, 1);
15414 final (insn
, file
, 1, 0);
15415 final_end_function ();
15417 reload_completed
= 0;
15418 epilogue_completed
= 0;
15419 no_new_pseudos
= 0;
15422 /* A quick summary of the various types of 'constant-pool tables'
15425 Target Flags Name One table per
15426 AIX (none) AIX TOC object file
15427 AIX -mfull-toc AIX TOC object file
15428 AIX -mminimal-toc AIX minimal TOC translation unit
15429 SVR4/EABI (none) SVR4 SDATA object file
15430 SVR4/EABI -fpic SVR4 pic object file
15431 SVR4/EABI -fPIC SVR4 PIC translation unit
15432 SVR4/EABI -mrelocatable EABI TOC function
15433 SVR4/EABI -maix AIX TOC object file
15434 SVR4/EABI -maix -mminimal-toc
15435 AIX minimal TOC translation unit
15437 Name Reg. Set by entries contains:
15438 made by addrs? fp? sum?
15440 AIX TOC 2 crt0 as Y option option
15441 AIX minimal TOC 30 prolog gcc Y Y option
15442 SVR4 SDATA 13 crt0 gcc N Y N
15443 SVR4 pic 30 prolog ld Y not yet N
15444 SVR4 PIC 30 prolog gcc Y option option
15445 EABI TOC 30 prolog gcc Y option option
15449 /* Hash functions for the hash table. */
15452 rs6000_hash_constant (rtx k
)
15454 enum rtx_code code
= GET_CODE (k
);
15455 enum machine_mode mode
= GET_MODE (k
);
15456 unsigned result
= (code
<< 3) ^ mode
;
15457 const char *format
;
15460 format
= GET_RTX_FORMAT (code
);
15461 flen
= strlen (format
);
15467 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
15470 if (mode
!= VOIDmode
)
15471 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
15483 for (; fidx
< flen
; fidx
++)
15484 switch (format
[fidx
])
15489 const char *str
= XSTR (k
, fidx
);
15490 len
= strlen (str
);
15491 result
= result
* 613 + len
;
15492 for (i
= 0; i
< len
; i
++)
15493 result
= result
* 613 + (unsigned) str
[i
];
15498 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
15502 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
15505 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
15506 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
15510 for (i
= 0; i
< sizeof(HOST_WIDE_INT
)/sizeof(unsigned); i
++)
15511 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
15525 toc_hash_function (const void *hash_entry
)
15527 const struct toc_hash_struct
*thc
=
15528 (const struct toc_hash_struct
*) hash_entry
;
15529 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
15532 /* Compare H1 and H2 for equivalence. */
15535 toc_hash_eq (const void *h1
, const void *h2
)
15537 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
15538 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
15540 if (((const struct toc_hash_struct
*) h1
)->key_mode
15541 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
15544 return rtx_equal_p (r1
, r2
);
15547 /* These are the names given by the C++ front-end to vtables, and
15548 vtable-like objects. Ideally, this logic should not be here;
15549 instead, there should be some programmatic way of inquiring as
15550 to whether or not an object is a vtable. */
15552 #define VTABLE_NAME_P(NAME) \
15553 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15554 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15555 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15556 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15557 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15560 rs6000_output_symbol_ref (FILE *file
, rtx x
)
15562 /* Currently C++ toc references to vtables can be emitted before it
15563 is decided whether the vtable is public or private. If this is
15564 the case, then the linker will eventually complain that there is
15565 a reference to an unknown section. Thus, for vtables only,
15566 we emit the TOC reference to reference the symbol and not the
15568 const char *name
= XSTR (x
, 0);
15570 if (VTABLE_NAME_P (name
))
15572 RS6000_OUTPUT_BASENAME (file
, name
);
15575 assemble_name (file
, name
);
15578 /* Output a TOC entry. We derive the entry name from what is being
15582 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
15585 const char *name
= buf
;
15586 const char *real_name
;
15593 /* When the linker won't eliminate them, don't output duplicate
15594 TOC entries (this happens on AIX if there is any kind of TOC,
15595 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15597 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
15599 struct toc_hash_struct
*h
;
15602 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15603 time because GGC is not initialized at that point. */
15604 if (toc_hash_table
== NULL
)
15605 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
15606 toc_hash_eq
, NULL
);
15608 h
= ggc_alloc (sizeof (*h
));
15610 h
->key_mode
= mode
;
15611 h
->labelno
= labelno
;
15613 found
= htab_find_slot (toc_hash_table
, h
, 1);
15614 if (*found
== NULL
)
15616 else /* This is indeed a duplicate.
15617 Set this label equal to that label. */
15619 fputs ("\t.set ", file
);
15620 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
15621 fprintf (file
, "%d,", labelno
);
15622 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
15623 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
15629 /* If we're going to put a double constant in the TOC, make sure it's
15630 aligned properly when strict alignment is on. */
15631 if (GET_CODE (x
) == CONST_DOUBLE
15632 && STRICT_ALIGNMENT
15633 && GET_MODE_BITSIZE (mode
) >= 64
15634 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
15635 ASM_OUTPUT_ALIGN (file
, 3);
15638 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
15640 /* Handle FP constants specially. Note that if we have a minimal
15641 TOC, things we put here aren't actually in the TOC, so we can allow
15643 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == TFmode
)
15645 REAL_VALUE_TYPE rv
;
15648 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15649 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
15653 if (TARGET_MINIMAL_TOC
)
15654 fputs (DOUBLE_INT_ASM_OP
, file
);
15656 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15657 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15658 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15659 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
15660 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15661 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15666 if (TARGET_MINIMAL_TOC
)
15667 fputs ("\t.long ", file
);
15669 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15670 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15671 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15672 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15673 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
15674 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
15678 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
15680 REAL_VALUE_TYPE rv
;
15683 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15684 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
15688 if (TARGET_MINIMAL_TOC
)
15689 fputs (DOUBLE_INT_ASM_OP
, file
);
15691 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
15692 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15693 fprintf (file
, "0x%lx%08lx\n",
15694 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15699 if (TARGET_MINIMAL_TOC
)
15700 fputs ("\t.long ", file
);
15702 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
15703 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15704 fprintf (file
, "0x%lx,0x%lx\n",
15705 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
15709 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
15711 REAL_VALUE_TYPE rv
;
15714 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
15715 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
15719 if (TARGET_MINIMAL_TOC
)
15720 fputs (DOUBLE_INT_ASM_OP
, file
);
15722 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
15723 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
15728 if (TARGET_MINIMAL_TOC
)
15729 fputs ("\t.long ", file
);
15731 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
15732 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
15736 else if (GET_MODE (x
) == VOIDmode
15737 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
15739 unsigned HOST_WIDE_INT low
;
15740 HOST_WIDE_INT high
;
15742 if (GET_CODE (x
) == CONST_DOUBLE
)
15744 low
= CONST_DOUBLE_LOW (x
);
15745 high
= CONST_DOUBLE_HIGH (x
);
15748 #if HOST_BITS_PER_WIDE_INT == 32
15751 high
= (low
& 0x80000000) ? ~0 : 0;
15755 low
= INTVAL (x
) & 0xffffffff;
15756 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
15760 /* TOC entries are always Pmode-sized, but since this
15761 is a bigendian machine then if we're putting smaller
15762 integer constants in the TOC we have to pad them.
15763 (This is still a win over putting the constants in
15764 a separate constant pool, because then we'd have
15765 to have both a TOC entry _and_ the actual constant.)
15767 For a 32-bit target, CONST_INT values are loaded and shifted
15768 entirely within `low' and can be stored in one TOC entry. */
15770 if (TARGET_64BIT
&& POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
15771 abort ();/* It would be easy to make this work, but it doesn't now. */
15773 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
15775 #if HOST_BITS_PER_WIDE_INT == 32
15776 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
15777 POINTER_SIZE
, &low
, &high
, 0);
15780 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
15781 high
= (HOST_WIDE_INT
) low
>> 32;
15788 if (TARGET_MINIMAL_TOC
)
15789 fputs (DOUBLE_INT_ASM_OP
, file
);
15791 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
15792 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15793 fprintf (file
, "0x%lx%08lx\n",
15794 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15799 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
15801 if (TARGET_MINIMAL_TOC
)
15802 fputs ("\t.long ", file
);
15804 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
15805 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15806 fprintf (file
, "0x%lx,0x%lx\n",
15807 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
15811 if (TARGET_MINIMAL_TOC
)
15812 fputs ("\t.long ", file
);
15814 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
15815 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
15821 if (GET_CODE (x
) == CONST
)
15823 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
15826 base
= XEXP (XEXP (x
, 0), 0);
15827 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
15830 if (GET_CODE (base
) == SYMBOL_REF
)
15831 name
= XSTR (base
, 0);
15832 else if (GET_CODE (base
) == LABEL_REF
)
15833 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (base
, 0)));
15834 else if (GET_CODE (base
) == CODE_LABEL
)
15835 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
15839 real_name
= (*targetm
.strip_name_encoding
) (name
);
15840 if (TARGET_MINIMAL_TOC
)
15841 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
15844 fprintf (file
, "\t.tc %s", real_name
);
15847 fprintf (file
, ".N%d", - offset
);
15849 fprintf (file
, ".P%d", offset
);
15851 fputs ("[TC],", file
);
15854 /* Currently C++ toc references to vtables can be emitted before it
15855 is decided whether the vtable is public or private. If this is
15856 the case, then the linker will eventually complain that there is
15857 a TOC reference to an unknown section. Thus, for vtables only,
15858 we emit the TOC reference to reference the symbol and not the
15860 if (VTABLE_NAME_P (name
))
15862 RS6000_OUTPUT_BASENAME (file
, name
);
15864 fprintf (file
, "%d", offset
);
15865 else if (offset
> 0)
15866 fprintf (file
, "+%d", offset
);
15869 output_addr_const (file
, x
);
15873 /* Output an assembler pseudo-op to write an ASCII string of N characters
15874 starting at P to FILE.
15876 On the RS/6000, we have to do this using the .byte operation and
15877 write out special characters outside the quoted string.
15878 Also, the assembler is broken; very long strings are truncated,
15879 so we must artificially break them up early. */
15882 output_ascii (FILE *file
, const char *p
, int n
)
15885 int i
, count_string
;
15886 const char *for_string
= "\t.byte \"";
15887 const char *for_decimal
= "\t.byte ";
15888 const char *to_close
= NULL
;
15891 for (i
= 0; i
< n
; i
++)
15894 if (c
>= ' ' && c
< 0177)
15897 fputs (for_string
, file
);
15900 /* Write two quotes to get one. */
15908 for_decimal
= "\"\n\t.byte ";
15912 if (count_string
>= 512)
15914 fputs (to_close
, file
);
15916 for_string
= "\t.byte \"";
15917 for_decimal
= "\t.byte ";
15925 fputs (for_decimal
, file
);
15926 fprintf (file
, "%d", c
);
15928 for_string
= "\n\t.byte \"";
15929 for_decimal
= ", ";
15935 /* Now close the string if we have written one. Then end the line. */
15937 fputs (to_close
, file
);
15940 /* Generate a unique section name for FILENAME for a section type
15941 represented by SECTION_DESC. Output goes into BUF.
15943 SECTION_DESC can be any string, as long as it is different for each
15944 possible section type.
15946 We name the section in the same manner as xlc. The name begins with an
15947 underscore followed by the filename (after stripping any leading directory
15948 names) with the last period replaced by the string SECTION_DESC. If
15949 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15953 rs6000_gen_section_name (char **buf
, const char *filename
,
15954 const char *section_desc
)
15956 const char *q
, *after_last_slash
, *last_period
= 0;
15960 after_last_slash
= filename
;
15961 for (q
= filename
; *q
; q
++)
15964 after_last_slash
= q
+ 1;
15965 else if (*q
== '.')
15969 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
15970 *buf
= (char *) xmalloc (len
);
15975 for (q
= after_last_slash
; *q
; q
++)
15977 if (q
== last_period
)
15979 strcpy (p
, section_desc
);
15980 p
+= strlen (section_desc
);
15984 else if (ISALNUM (*q
))
15988 if (last_period
== 0)
15989 strcpy (p
, section_desc
);
15994 /* Emit profile function. */
15997 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
15999 if (TARGET_PROFILE_KERNEL
)
16002 if (DEFAULT_ABI
== ABI_AIX
)
16004 #ifndef NO_PROFILE_COUNTERS
16005 # define NO_PROFILE_COUNTERS 0
16007 if (NO_PROFILE_COUNTERS
)
16008 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
16012 const char *label_name
;
16015 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
16016 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
16017 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
16019 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
16023 else if (DEFAULT_ABI
== ABI_DARWIN
)
16025 const char *mcount_name
= RS6000_MCOUNT
;
16026 int caller_addr_regno
= LINK_REGISTER_REGNUM
;
16028 /* Be conservative and always set this, at least for now. */
16029 current_function_uses_pic_offset_table
= 1;
16032 /* For PIC code, set up a stub and collect the caller's address
16033 from r0, which is where the prologue puts it. */
16034 if (MACHOPIC_INDIRECT
16035 && current_function_uses_pic_offset_table
)
16036 caller_addr_regno
= 0;
16038 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
16040 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
16044 /* Write function profiler code. */
16047 output_function_profiler (FILE *file
, int labelno
)
16052 switch (DEFAULT_ABI
)
16061 warning ("no profiling of 64-bit code for this ABI");
16064 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
16065 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
16068 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
16069 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
16070 reg_names
[0], save_lr
, reg_names
[1]);
16071 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
16072 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
16073 assemble_name (file
, buf
);
16074 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
16076 else if (flag_pic
> 1)
16078 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
16079 reg_names
[0], save_lr
, reg_names
[1]);
16080 /* Now, we need to get the address of the label. */
16081 fputs ("\tbl 1f\n\t.long ", file
);
16082 assemble_name (file
, buf
);
16083 fputs ("-.\n1:", file
);
16084 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
16085 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
16086 reg_names
[0], reg_names
[11]);
16087 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
16088 reg_names
[0], reg_names
[0], reg_names
[11]);
16092 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
16093 assemble_name (file
, buf
);
16094 fputs ("@ha\n", file
);
16095 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
16096 reg_names
[0], save_lr
, reg_names
[1]);
16097 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
16098 assemble_name (file
, buf
);
16099 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
16102 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16103 fprintf (file
, "\tbl %s%s\n",
16104 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
16109 if (!TARGET_PROFILE_KERNEL
)
16111 /* Don't do anything, done in output_profile_hook (). */
16118 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
16119 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
16121 if (cfun
->static_chain_decl
!= NULL
)
16123 asm_fprintf (file
, "\tstd %s,24(%s)\n",
16124 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
16125 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
16126 asm_fprintf (file
, "\tld %s,24(%s)\n",
16127 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
16130 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
16137 /* Power4 load update and store update instructions are cracked into a
16138 load or store and an integer insn which are executed in the same cycle.
16139 Branches have their own dispatch slot which does not count against the
16140 GCC issue rate, but it changes the program flow so there are no other
16141 instructions to issue in this cycle. */
16144 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
16145 int verbose ATTRIBUTE_UNUSED
,
16146 rtx insn
, int more
)
16148 if (GET_CODE (PATTERN (insn
)) == USE
16149 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16152 if (rs6000_sched_groups
)
16154 if (is_microcoded_insn (insn
))
16156 else if (is_cracked_insn (insn
))
16157 return more
> 2 ? more
- 2 : 0;
16163 /* Adjust the cost of a scheduling dependency. Return the new cost of
16164 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16167 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
16169 if (! recog_memoized (insn
))
16172 if (REG_NOTE_KIND (link
) != 0)
16175 if (REG_NOTE_KIND (link
) == 0)
16177 /* Data dependency; DEP_INSN writes a register that INSN reads
16178 some cycles later. */
16180 /* Separate a load from a narrower, dependent store. */
16181 if (rs6000_sched_groups
16182 && GET_CODE (PATTERN (insn
)) == SET
16183 && GET_CODE (PATTERN (dep_insn
)) == SET
16184 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
16185 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
16186 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
16187 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
16190 switch (get_attr_type (insn
))
16193 /* Tell the first scheduling pass about the latency between
16194 a mtctr and bctr (and mtlr and br/blr). The first
16195 scheduling pass will not know about this latency since
16196 the mtctr instruction, which has the latency associated
16197 to it, will be generated by reload. */
16198 return TARGET_POWER
? 5 : 4;
16200 /* Leave some extra cycles between a compare and its
16201 dependent branch, to inhibit expensive mispredicts. */
16202 if ((rs6000_cpu_attr
== CPU_PPC603
16203 || rs6000_cpu_attr
== CPU_PPC604
16204 || rs6000_cpu_attr
== CPU_PPC604E
16205 || rs6000_cpu_attr
== CPU_PPC620
16206 || rs6000_cpu_attr
== CPU_PPC630
16207 || rs6000_cpu_attr
== CPU_PPC750
16208 || rs6000_cpu_attr
== CPU_PPC7400
16209 || rs6000_cpu_attr
== CPU_PPC7450
16210 || rs6000_cpu_attr
== CPU_POWER4
16211 || rs6000_cpu_attr
== CPU_POWER5
)
16212 && recog_memoized (dep_insn
)
16213 && (INSN_CODE (dep_insn
) >= 0)
16214 && (get_attr_type (dep_insn
) == TYPE_CMP
16215 || get_attr_type (dep_insn
) == TYPE_COMPARE
16216 || get_attr_type (dep_insn
) == TYPE_DELAYED_COMPARE
16217 || get_attr_type (dep_insn
) == TYPE_IMUL_COMPARE
16218 || get_attr_type (dep_insn
) == TYPE_LMUL_COMPARE
16219 || get_attr_type (dep_insn
) == TYPE_FPCOMPARE
16220 || get_attr_type (dep_insn
) == TYPE_CR_LOGICAL
16221 || get_attr_type (dep_insn
) == TYPE_DELAYED_CR
))
16226 /* Fall out to return default cost. */
16232 /* The function returns a true if INSN is microcoded.
16233 Return false otherwise. */
16236 is_microcoded_insn (rtx insn
)
16238 if (!insn
|| !INSN_P (insn
)
16239 || GET_CODE (PATTERN (insn
)) == USE
16240 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16243 if (rs6000_sched_groups
)
16245 enum attr_type type
= get_attr_type (insn
);
16246 if (type
== TYPE_LOAD_EXT_U
16247 || type
== TYPE_LOAD_EXT_UX
16248 || type
== TYPE_LOAD_UX
16249 || type
== TYPE_STORE_UX
16250 || type
== TYPE_MFCR
)
16257 /* The function returns a nonzero value if INSN can be scheduled only
16258 as the first insn in a dispatch group ("dispatch-slot restricted").
16259 In this case, the returned value indicates how many dispatch slots
16260 the insn occupies (at the beginning of the group).
16261 Return 0 otherwise. */
16264 is_dispatch_slot_restricted (rtx insn
)
16266 enum attr_type type
;
16268 if (!rs6000_sched_groups
)
16272 || insn
== NULL_RTX
16273 || GET_CODE (insn
) == NOTE
16274 || GET_CODE (PATTERN (insn
)) == USE
16275 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16278 type
= get_attr_type (insn
);
16285 case TYPE_DELAYED_CR
:
16286 case TYPE_CR_LOGICAL
:
16294 if (rs6000_cpu
== PROCESSOR_POWER5
16295 && is_cracked_insn (insn
))
16301 /* The function returns true if INSN is cracked into 2 instructions
16302 by the processor (and therefore occupies 2 issue slots). */
16305 is_cracked_insn (rtx insn
)
16307 if (!insn
|| !INSN_P (insn
)
16308 || GET_CODE (PATTERN (insn
)) == USE
16309 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16312 if (rs6000_sched_groups
)
16314 enum attr_type type
= get_attr_type (insn
);
16315 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
16316 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
16317 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
16318 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
16319 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
16320 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
16321 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
16322 || type
== TYPE_INSERT_WORD
)
16329 /* The function returns true if INSN can be issued only from
16330 the branch slot. */
16333 is_branch_slot_insn (rtx insn
)
16335 if (!insn
|| !INSN_P (insn
)
16336 || GET_CODE (PATTERN (insn
)) == USE
16337 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
16340 if (rs6000_sched_groups
)
16342 enum attr_type type
= get_attr_type (insn
);
16343 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
16351 /* A C statement (sans semicolon) to update the integer scheduling
16352 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16353 INSN earlier, reduce the priority to execute INSN later. Do not
16354 define this macro if you do not need to adjust the scheduling
16355 priorities of insns. */
16358 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
16360 /* On machines (like the 750) which have asymmetric integer units,
16361 where one integer unit can do multiply and divides and the other
16362 can't, reduce the priority of multiply/divide so it is scheduled
16363 before other integer operations. */
16366 if (! INSN_P (insn
))
16369 if (GET_CODE (PATTERN (insn
)) == USE
)
16372 switch (rs6000_cpu_attr
) {
16374 switch (get_attr_type (insn
))
16381 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
16382 priority
, priority
);
16383 if (priority
>= 0 && priority
< 0x01000000)
16390 if (is_dispatch_slot_restricted (insn
)
16391 && reload_completed
16392 && current_sched_info
->sched_max_insns_priority
16393 && rs6000_sched_restricted_insns_priority
)
16396 /* Prioritize insns that can be dispatched only in the first
16398 if (rs6000_sched_restricted_insns_priority
== 1)
16399 /* Attach highest priority to insn. This means that in
16400 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16401 precede 'priority' (critical path) considerations. */
16402 return current_sched_info
->sched_max_insns_priority
;
16403 else if (rs6000_sched_restricted_insns_priority
== 2)
16404 /* Increase priority of insn by a minimal amount. This means that in
16405 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16406 considerations precede dispatch-slot restriction considerations. */
16407 return (priority
+ 1);
16413 /* Return how many instructions the machine can issue per cycle. */
16416 rs6000_issue_rate (void)
16418 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16419 if (!reload_completed
)
16422 switch (rs6000_cpu_attr
) {
16423 case CPU_RIOS1
: /* ? */
16425 case CPU_PPC601
: /* ? */
16448 /* Return how many instructions to look ahead for better insn
16452 rs6000_use_sched_lookahead (void)
16454 if (rs6000_cpu_attr
== CPU_PPC8540
)
16459 /* Determine is PAT refers to memory. */
16462 is_mem_ref (rtx pat
)
16468 if (GET_CODE (pat
) == MEM
)
16471 /* Recursively process the pattern. */
16472 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
16474 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
16477 ret
|= is_mem_ref (XEXP (pat
, i
));
16478 else if (fmt
[i
] == 'E')
16479 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
16480 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
16486 /* Determine if PAT is a PATTERN of a load insn. */
16489 is_load_insn1 (rtx pat
)
16491 if (!pat
|| pat
== NULL_RTX
)
16494 if (GET_CODE (pat
) == SET
)
16495 return is_mem_ref (SET_SRC (pat
));
16497 if (GET_CODE (pat
) == PARALLEL
)
16501 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
16502 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
16509 /* Determine if INSN loads from memory. */
16512 is_load_insn (rtx insn
)
16514 if (!insn
|| !INSN_P (insn
))
16517 if (GET_CODE (insn
) == CALL_INSN
)
16520 return is_load_insn1 (PATTERN (insn
));
16523 /* Determine if PAT is a PATTERN of a store insn. */
16526 is_store_insn1 (rtx pat
)
16528 if (!pat
|| pat
== NULL_RTX
)
16531 if (GET_CODE (pat
) == SET
)
16532 return is_mem_ref (SET_DEST (pat
));
16534 if (GET_CODE (pat
) == PARALLEL
)
16538 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
16539 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
16546 /* Determine if INSN stores to memory. */
16549 is_store_insn (rtx insn
)
16551 if (!insn
|| !INSN_P (insn
))
16554 return is_store_insn1 (PATTERN (insn
));
16557 /* Returns whether the dependence between INSN and NEXT is considered
16558 costly by the given target. */
16561 rs6000_is_costly_dependence (rtx insn
, rtx next
, rtx link
, int cost
,
16564 /* If the flag is not enbled - no dependence is considered costly;
16565 allow all dependent insns in the same group.
16566 This is the most aggressive option. */
16567 if (rs6000_sched_costly_dep
== no_dep_costly
)
16570 /* If the flag is set to 1 - a dependence is always considered costly;
16571 do not allow dependent instructions in the same group.
16572 This is the most conservative option. */
16573 if (rs6000_sched_costly_dep
== all_deps_costly
)
16576 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
16577 && is_load_insn (next
)
16578 && is_store_insn (insn
))
16579 /* Prevent load after store in the same group. */
16582 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
16583 && is_load_insn (next
)
16584 && is_store_insn (insn
)
16585 && (!link
|| (int) REG_NOTE_KIND (link
) == 0))
16586 /* Prevent load after store in the same group if it is a true
16590 /* The flag is set to X; dependences with latency >= X are considered costly,
16591 and will not be scheduled in the same group. */
16592 if (rs6000_sched_costly_dep
<= max_dep_latency
16593 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
16599 /* Return the next insn after INSN that is found before TAIL is reached,
16600 skipping any "non-active" insns - insns that will not actually occupy
16601 an issue slot. Return NULL_RTX if such an insn is not found. */
16604 get_next_active_insn (rtx insn
, rtx tail
)
16608 if (!insn
|| insn
== tail
)
16611 next_insn
= NEXT_INSN (insn
);
16614 && next_insn
!= tail
16615 && (GET_CODE(next_insn
) == NOTE
16616 || GET_CODE (PATTERN (next_insn
)) == USE
16617 || GET_CODE (PATTERN (next_insn
)) == CLOBBER
))
16619 next_insn
= NEXT_INSN (next_insn
);
16622 if (!next_insn
|| next_insn
== tail
)
16628 /* Return whether the presence of INSN causes a dispatch group termination
16629 of group WHICH_GROUP.
16631 If WHICH_GROUP == current_group, this function will return true if INSN
16632 causes the termination of the current group (i.e, the dispatch group to
16633 which INSN belongs). This means that INSN will be the last insn in the
16634 group it belongs to.
16636 If WHICH_GROUP == previous_group, this function will return true if INSN
16637 causes the termination of the previous group (i.e, the dispatch group that
16638 precedes the group to which INSN belongs). This means that INSN will be
16639 the first insn in the group it belongs to). */
16642 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
16644 enum attr_type type
;
16649 type
= get_attr_type (insn
);
16651 if (is_microcoded_insn (insn
))
16654 if (which_group
== current_group
)
16656 if (is_branch_slot_insn (insn
))
16660 else if (which_group
== previous_group
)
16662 if (is_dispatch_slot_restricted (insn
))
16670 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16671 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16674 is_costly_group (rtx
*group_insns
, rtx next_insn
)
16679 int issue_rate
= rs6000_issue_rate ();
16681 for (i
= 0; i
< issue_rate
; i
++)
16683 rtx insn
= group_insns
[i
];
16686 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
16688 rtx next
= XEXP (link
, 0);
16689 if (next
== next_insn
)
16691 cost
= insn_cost (insn
, link
, next_insn
);
16692 if (rs6000_is_costly_dependence (insn
, next_insn
, link
, cost
, 0))
16701 /* Utility of the function redefine_groups.
16702 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16703 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16704 to keep it "far" (in a separate group) from GROUP_INSNS, following
16705 one of the following schemes, depending on the value of the flag
16706 -minsert_sched_nops = X:
16707 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16708 in order to force NEXT_INSN into a separate group.
16709 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16710 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16711 insertion (has a group just ended, how many vacant issue slots remain in the
16712 last group, and how many dispatch groups were encountered so far). */
16715 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
16716 rtx next_insn
, bool *group_end
, int can_issue_more
,
16721 int issue_rate
= rs6000_issue_rate ();
16722 bool end
= *group_end
;
16725 if (next_insn
== NULL_RTX
)
16726 return can_issue_more
;
16728 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
16729 return can_issue_more
;
16731 force
= is_costly_group (group_insns
, next_insn
);
16733 return can_issue_more
;
16735 if (sched_verbose
> 6)
16736 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
16737 *group_count
,can_issue_more
);
16739 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
16742 can_issue_more
= 0;
16744 /* Since only a branch can be issued in the last issue_slot, it is
16745 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16746 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16747 in this case the last nop will start a new group and the branch
16748 will be forced to the new group. */
16749 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
16752 while (can_issue_more
> 0)
16755 emit_insn_before (nop
, next_insn
);
16763 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
16765 int n_nops
= rs6000_sched_insert_nops
;
16767 /* Nops can't be issued from the branch slot, so the effective
16768 issue_rate for nops is 'issue_rate - 1'. */
16769 if (can_issue_more
== 0)
16770 can_issue_more
= issue_rate
;
16772 if (can_issue_more
== 0)
16774 can_issue_more
= issue_rate
- 1;
16777 for (i
= 0; i
< issue_rate
; i
++)
16779 group_insns
[i
] = 0;
16786 emit_insn_before (nop
, next_insn
);
16787 if (can_issue_more
== issue_rate
- 1) /* new group begins */
16790 if (can_issue_more
== 0)
16792 can_issue_more
= issue_rate
- 1;
16795 for (i
= 0; i
< issue_rate
; i
++)
16797 group_insns
[i
] = 0;
16803 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16806 /* Is next_insn going to start a new group? */
16809 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
16810 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
16811 || (can_issue_more
< issue_rate
&&
16812 insn_terminates_group_p (next_insn
, previous_group
)));
16813 if (*group_end
&& end
)
16816 if (sched_verbose
> 6)
16817 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
16818 *group_count
, can_issue_more
);
16819 return can_issue_more
;
16822 return can_issue_more
;
16825 /* This function tries to synch the dispatch groups that the compiler "sees"
16826 with the dispatch groups that the processor dispatcher is expected to
16827 form in practice. It tries to achieve this synchronization by forcing the
16828 estimated processor grouping on the compiler (as opposed to the function
16829 'pad_goups' which tries to force the scheduler's grouping on the processor).
16831 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16832 examines the (estimated) dispatch groups that will be formed by the processor
16833 dispatcher. It marks these group boundaries to reflect the estimated
16834 processor grouping, overriding the grouping that the scheduler had marked.
16835 Depending on the value of the flag '-minsert-sched-nops' this function can
16836 force certain insns into separate groups or force a certain distance between
16837 them by inserting nops, for example, if there exists a "costly dependence"
16840 The function estimates the group boundaries that the processor will form as
16841 folllows: It keeps track of how many vacant issue slots are available after
16842 each insn. A subsequent insn will start a new group if one of the following
16844 - no more vacant issue slots remain in the current dispatch group.
16845 - only the last issue slot, which is the branch slot, is vacant, but the next
16846 insn is not a branch.
16847 - only the last 2 or less issue slots, including the branch slot, are vacant,
16848 which means that a cracked insn (which occupies two issue slots) can't be
16849 issued in this group.
16850 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16851 start a new group. */
16854 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
16856 rtx insn
, next_insn
;
16858 int can_issue_more
;
16861 int group_count
= 0;
16865 issue_rate
= rs6000_issue_rate ();
16866 group_insns
= alloca (issue_rate
* sizeof (rtx
));
16867 for (i
= 0; i
< issue_rate
; i
++)
16869 group_insns
[i
] = 0;
16871 can_issue_more
= issue_rate
;
16873 insn
= get_next_active_insn (prev_head_insn
, tail
);
16876 while (insn
!= NULL_RTX
)
16878 slot
= (issue_rate
- can_issue_more
);
16879 group_insns
[slot
] = insn
;
16881 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
16882 if (insn_terminates_group_p (insn
, current_group
))
16883 can_issue_more
= 0;
16885 next_insn
= get_next_active_insn (insn
, tail
);
16886 if (next_insn
== NULL_RTX
)
16887 return group_count
+ 1;
16889 /* Is next_insn going to start a new group? */
16891 = (can_issue_more
== 0
16892 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
16893 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
16894 || (can_issue_more
< issue_rate
&&
16895 insn_terminates_group_p (next_insn
, previous_group
)));
16897 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
16898 next_insn
, &group_end
, can_issue_more
,
16904 can_issue_more
= 0;
16905 for (i
= 0; i
< issue_rate
; i
++)
16907 group_insns
[i
] = 0;
16911 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
16912 PUT_MODE(next_insn
, VOIDmode
);
16913 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
16914 PUT_MODE (next_insn
, TImode
);
16917 if (can_issue_more
== 0)
16918 can_issue_more
= issue_rate
;
16921 return group_count
;
16924 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16925 dispatch group boundaries that the scheduler had marked. Pad with nops
16926 any dispatch groups which have vacant issue slots, in order to force the
16927 scheduler's grouping on the processor dispatcher. The function
16928 returns the number of dispatch groups found. */
16931 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
16933 rtx insn
, next_insn
;
16936 int can_issue_more
;
16938 int group_count
= 0;
16940 /* Initialize issue_rate. */
16941 issue_rate
= rs6000_issue_rate ();
16942 can_issue_more
= issue_rate
;
16944 insn
= get_next_active_insn (prev_head_insn
, tail
);
16945 next_insn
= get_next_active_insn (insn
, tail
);
16947 while (insn
!= NULL_RTX
)
16950 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
16952 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
16954 if (next_insn
== NULL_RTX
)
16959 /* If the scheduler had marked group termination at this location
16960 (between insn and next_indn), and neither insn nor next_insn will
16961 force group termination, pad the group with nops to force group
16964 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
16965 && !insn_terminates_group_p (insn
, current_group
)
16966 && !insn_terminates_group_p (next_insn
, previous_group
))
16968 if (!is_branch_slot_insn(next_insn
))
16971 while (can_issue_more
)
16974 emit_insn_before (nop
, next_insn
);
16979 can_issue_more
= issue_rate
;
16984 next_insn
= get_next_active_insn (insn
, tail
);
16987 return group_count
;
16990 /* The following function is called at the end of scheduling BB.
16991 After reload, it inserts nops at insn group bundling. */
16994 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
16999 fprintf (dump
, "=== Finishing schedule.\n");
17001 if (reload_completed
&& rs6000_sched_groups
)
17003 if (rs6000_sched_insert_nops
== sched_finish_none
)
17006 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
17007 n_groups
= pad_groups (dump
, sched_verbose
,
17008 current_sched_info
->prev_head
,
17009 current_sched_info
->next_tail
);
17011 n_groups
= redefine_groups (dump
, sched_verbose
,
17012 current_sched_info
->prev_head
,
17013 current_sched_info
->next_tail
);
17015 if (sched_verbose
>= 6)
17017 fprintf (dump
, "ngroups = %d\n", n_groups
);
17018 print_rtl (dump
, current_sched_info
->prev_head
);
17019 fprintf (dump
, "Done finish_sched\n");
17024 /* Length in units of the trampoline for entering a nested function. */
17027 rs6000_trampoline_size (void)
17031 switch (DEFAULT_ABI
)
17037 ret
= (TARGET_32BIT
) ? 12 : 24;
17042 ret
= (TARGET_32BIT
) ? 40 : 48;
17049 /* Emit RTL insns to initialize the variable parts of a trampoline.
17050 FNADDR is an RTX for the address of the function's pure code.
17051 CXT is an RTX for the static chain value for the function. */
17054 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
17056 enum machine_mode pmode
= Pmode
;
17057 int regsize
= (TARGET_32BIT
) ? 4 : 8;
17058 rtx ctx_reg
= force_reg (pmode
, cxt
);
17060 switch (DEFAULT_ABI
)
17065 /* Macros to shorten the code expansions below. */
17066 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17067 #define MEM_PLUS(addr,offset) \
17068 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17070 /* Under AIX, just build the 3 word function descriptor */
17073 rtx fn_reg
= gen_reg_rtx (pmode
);
17074 rtx toc_reg
= gen_reg_rtx (pmode
);
17075 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
17076 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
17077 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
17078 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
17079 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
17083 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17086 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
17087 FALSE
, VOIDmode
, 4,
17089 GEN_INT (rs6000_trampoline_size ()), SImode
,
17099 /* Table of valid machine attributes. */
17101 const struct attribute_spec rs6000_attribute_table
[] =
17103 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17104 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
17105 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
17106 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
17107 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17108 SUBTARGET_ATTRIBUTE_TABLE
,
17110 { NULL
, 0, 0, false, false, false, NULL
}
17113 /* Handle the "altivec" attribute. The attribute may have
17114 arguments as follows:
17116 __attribute__((altivec(vector__)))
17117 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17118 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17120 and may appear more than once (e.g., 'vector bool char') in a
17121 given declaration. */
17124 rs6000_handle_altivec_attribute (tree
*node
,
17125 tree name ATTRIBUTE_UNUSED
,
17127 int flags ATTRIBUTE_UNUSED
,
17128 bool *no_add_attrs
)
17130 tree type
= *node
, result
= NULL_TREE
;
17131 enum machine_mode mode
;
17134 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
17135 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
17136 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
17139 while (POINTER_TYPE_P (type
)
17140 || TREE_CODE (type
) == FUNCTION_TYPE
17141 || TREE_CODE (type
) == METHOD_TYPE
17142 || TREE_CODE (type
) == ARRAY_TYPE
)
17143 type
= TREE_TYPE (type
);
17145 mode
= TYPE_MODE (type
);
17147 /* Check for invalid AltiVec type qualifiers. */
17148 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
17151 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17152 else if (rs6000_warn_altivec_long
)
17153 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
17155 else if (type
== long_long_unsigned_type_node
17156 || type
== long_long_integer_type_node
)
17157 error ("use of %<long long%> in AltiVec types is invalid");
17158 else if (type
== double_type_node
)
17159 error ("use of %<double%> in AltiVec types is invalid");
17160 else if (type
== long_double_type_node
)
17161 error ("use of %<long double%> in AltiVec types is invalid");
17162 else if (type
== boolean_type_node
)
17163 error ("use of boolean types in AltiVec types is invalid");
17164 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
17165 error ("use of %<complex%> in AltiVec types is invalid");
17167 switch (altivec_type
)
17170 unsigned_p
= TYPE_UNSIGNED (type
);
17174 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
17177 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
17180 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
17182 case SFmode
: result
= V4SF_type_node
; break;
17183 /* If the user says 'vector int bool', we may be handed the 'bool'
17184 attribute _before_ the 'vector' attribute, and so select the
17185 proper type in the 'b' case below. */
17186 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
17194 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
17195 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
17196 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
17203 case V8HImode
: result
= pixel_V8HI_type_node
;
17209 if (result
&& result
!= type
&& TYPE_READONLY (type
))
17210 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
17212 *no_add_attrs
= true; /* No need to hang on to the attribute. */
17215 *node
= reconstruct_complex_type (*node
, result
);
17220 /* AltiVec defines four built-in scalar types that serve as vector
17221 elements; we must teach the compiler how to mangle them. */
17223 static const char *
17224 rs6000_mangle_fundamental_type (tree type
)
17226 if (type
== bool_char_type_node
) return "U6__boolc";
17227 if (type
== bool_short_type_node
) return "U6__bools";
17228 if (type
== pixel_type_node
) return "u7__pixel";
17229 if (type
== bool_int_type_node
) return "U6__booli";
17231 /* For all other types, use normal C++ mangling. */
17235 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17236 struct attribute_spec.handler. */
17239 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
17240 tree args ATTRIBUTE_UNUSED
,
17241 int flags ATTRIBUTE_UNUSED
,
17242 bool *no_add_attrs
)
17244 if (TREE_CODE (*node
) != FUNCTION_TYPE
17245 && TREE_CODE (*node
) != FIELD_DECL
17246 && TREE_CODE (*node
) != TYPE_DECL
)
17248 warning ("%qs attribute only applies to functions",
17249 IDENTIFIER_POINTER (name
));
17250 *no_add_attrs
= true;
17256 /* Set longcall attributes on all functions declared when
17257 rs6000_default_long_calls is true. */
17259 rs6000_set_default_type_attributes (tree type
)
17261 if (rs6000_default_long_calls
17262 && (TREE_CODE (type
) == FUNCTION_TYPE
17263 || TREE_CODE (type
) == METHOD_TYPE
))
17264 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
17266 TYPE_ATTRIBUTES (type
));
17269 /* Return a reference suitable for calling a function with the
17270 longcall attribute. */
17273 rs6000_longcall_ref (rtx call_ref
)
17275 const char *call_name
;
17278 if (GET_CODE (call_ref
) != SYMBOL_REF
)
17281 /* System V adds '.' to the internal name, so skip them. */
17282 call_name
= XSTR (call_ref
, 0);
17283 if (*call_name
== '.')
17285 while (*call_name
== '.')
17288 node
= get_identifier (call_name
);
17289 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
17292 return force_reg (Pmode
, call_ref
);
17295 #ifdef USING_ELFOS_H
17297 /* A C statement or statements to switch to the appropriate section
17298 for output of RTX in mode MODE. You can assume that RTX is some
17299 kind of constant in RTL. The argument MODE is redundant except in
17300 the case of a `const_int' rtx. Select the section by calling
17301 `text_section' or one of the alternatives for other sections.
17303 Do not define this macro if you put all constants in the read-only
17307 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
17308 unsigned HOST_WIDE_INT align
)
17310 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
17313 default_elf_select_rtx_section (mode
, x
, align
);
17316 /* A C statement or statements to switch to the appropriate
17317 section for output of DECL. DECL is either a `VAR_DECL' node
17318 or a constant of some sort. RELOC indicates whether forming
17319 the initial value of DECL requires link-time relocations. */
17322 rs6000_elf_select_section (tree decl
, int reloc
,
17323 unsigned HOST_WIDE_INT align
)
17325 /* Pretend that we're always building for a shared library when
17326 ABI_AIX, because otherwise we end up with dynamic relocations
17327 in read-only sections. This happens for function pointers,
17328 references to vtables in typeinfo, and probably other cases. */
17329 default_elf_select_section_1 (decl
, reloc
, align
,
17330 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17333 /* A C statement to build up a unique section name, expressed as a
17334 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17335 RELOC indicates whether the initial value of EXP requires
17336 link-time relocations. If you do not define this macro, GCC will use
17337 the symbol name prefixed by `.' as the section name. Note - this
17338 macro can now be called for uninitialized data items as well as
17339 initialized data and functions. */
17342 rs6000_elf_unique_section (tree decl
, int reloc
)
17344 /* As above, pretend that we're always building for a shared library
17345 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17346 default_unique_section_1 (decl
, reloc
,
17347 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17350 /* For a SYMBOL_REF, set generic flags and then perform some
17351 target-specific processing.
17353 When the AIX ABI is requested on a non-AIX system, replace the
17354 function name with the real name (with a leading .) rather than the
17355 function descriptor name. This saves a lot of overriding code to
17356 read the prefixes. */
17359 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
17361 default_encode_section_info (decl
, rtl
, first
);
17364 && TREE_CODE (decl
) == FUNCTION_DECL
17366 && DEFAULT_ABI
== ABI_AIX
)
17368 rtx sym_ref
= XEXP (rtl
, 0);
17369 size_t len
= strlen (XSTR (sym_ref
, 0));
17370 char *str
= alloca (len
+ 2);
17372 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
17373 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
17378 rs6000_elf_in_small_data_p (tree decl
)
17380 if (rs6000_sdata
== SDATA_NONE
)
17383 /* We want to merge strings, so we never consider them small data. */
17384 if (TREE_CODE (decl
) == STRING_CST
)
17387 /* Functions are never in the small data area. */
17388 if (TREE_CODE (decl
) == FUNCTION_DECL
)
17391 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
17393 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
17394 if (strcmp (section
, ".sdata") == 0
17395 || strcmp (section
, ".sdata2") == 0
17396 || strcmp (section
, ".sbss") == 0
17397 || strcmp (section
, ".sbss2") == 0
17398 || strcmp (section
, ".PPC.EMB.sdata0") == 0
17399 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
17404 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
17407 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
17408 /* If it's not public, and we're not going to reference it there,
17409 there's no need to put it in the small data section. */
17410 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
17417 #endif /* USING_ELFOS_H */
17420 /* Return a REG that occurs in ADDR with coefficient 1.
17421 ADDR can be effectively incremented by incrementing REG.
17423 r0 is special and we must not select it as an address
17424 register by this routine since our caller will try to
17425 increment the returned register via an "la" instruction. */
17428 find_addr_reg (rtx addr
)
17430 while (GET_CODE (addr
) == PLUS
)
17432 if (GET_CODE (XEXP (addr
, 0)) == REG
17433 && REGNO (XEXP (addr
, 0)) != 0)
17434 addr
= XEXP (addr
, 0);
17435 else if (GET_CODE (XEXP (addr
, 1)) == REG
17436 && REGNO (XEXP (addr
, 1)) != 0)
17437 addr
= XEXP (addr
, 1);
17438 else if (CONSTANT_P (XEXP (addr
, 0)))
17439 addr
= XEXP (addr
, 1);
17440 else if (CONSTANT_P (XEXP (addr
, 1)))
17441 addr
= XEXP (addr
, 0);
17445 if (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0)
17451 rs6000_fatal_bad_address (rtx op
)
17453 fatal_insn ("bad address", op
);
17458 static tree branch_island_list
= 0;
17460 /* Remember to generate a branch island for far calls to the given
17464 add_compiler_branch_island (tree label_name
, tree function_name
,
17467 tree branch_island
= build_tree_list (function_name
, label_name
);
17468 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
17469 TREE_CHAIN (branch_island
) = branch_island_list
;
17470 branch_island_list
= branch_island
;
17473 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17474 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17475 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17476 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17478 /* Generate far-jump branch islands for everything on the
17479 branch_island_list. Invoked immediately after the last instruction
17480 of the epilogue has been emitted; the branch-islands must be
17481 appended to, and contiguous with, the function body. Mach-O stubs
17482 are generated in machopic_output_stub(). */
17485 macho_branch_islands (void)
17488 tree branch_island
;
17490 for (branch_island
= branch_island_list
;
17492 branch_island
= TREE_CHAIN (branch_island
))
17494 const char *label
=
17495 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
17497 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
17498 char name_buf
[512];
17499 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17500 if (name
[0] == '*' || name
[0] == '&')
17501 strcpy (name_buf
, name
+1);
17505 strcpy (name_buf
+1, name
);
17507 strcpy (tmp_buf
, "\n");
17508 strcat (tmp_buf
, label
);
17509 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17510 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
17511 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
17512 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17515 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
17516 strcat (tmp_buf
, label
);
17517 strcat (tmp_buf
, "_pic\n");
17518 strcat (tmp_buf
, label
);
17519 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
17521 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
17522 strcat (tmp_buf
, name_buf
);
17523 strcat (tmp_buf
, " - ");
17524 strcat (tmp_buf
, label
);
17525 strcat (tmp_buf
, "_pic)\n");
17527 strcat (tmp_buf
, "\tmtlr r0\n");
17529 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
17530 strcat (tmp_buf
, name_buf
);
17531 strcat (tmp_buf
, " - ");
17532 strcat (tmp_buf
, label
);
17533 strcat (tmp_buf
, "_pic)\n");
17535 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
17539 strcat (tmp_buf
, ":\nlis r12,hi16(");
17540 strcat (tmp_buf
, name_buf
);
17541 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
17542 strcat (tmp_buf
, name_buf
);
17543 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
17545 output_asm_insn (tmp_buf
, 0);
17546 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17547 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
17548 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
17549 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17552 branch_island_list
= 0;
17555 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17556 already there or not. */
17559 no_previous_def (tree function_name
)
17561 tree branch_island
;
17562 for (branch_island
= branch_island_list
;
17564 branch_island
= TREE_CHAIN (branch_island
))
17565 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
17570 /* GET_PREV_LABEL gets the label name from the previous definition of
17574 get_prev_label (tree function_name
)
17576 tree branch_island
;
17577 for (branch_island
= branch_island_list
;
17579 branch_island
= TREE_CHAIN (branch_island
))
17580 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
17581 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
17585 /* INSN is either a function call or a millicode call. It may have an
17586 unconditional jump in its delay slot.
17588 CALL_DEST is the routine we are calling. */
17591 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
17592 int cookie_operand_number
)
17594 static char buf
[256];
17595 if (GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
17596 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
17599 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
17601 if (no_previous_def (funname
))
17603 int line_number
= 0;
17604 rtx label_rtx
= gen_label_rtx ();
17605 char *label_buf
, temp_buf
[256];
17606 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
17607 CODE_LABEL_NUMBER (label_rtx
));
17608 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
17609 labelname
= get_identifier (label_buf
);
17610 for (; insn
&& GET_CODE (insn
) != NOTE
; insn
= PREV_INSN (insn
));
17612 line_number
= NOTE_LINE_NUMBER (insn
);
17613 add_compiler_branch_island (labelname
, funname
, line_number
);
17616 labelname
= get_prev_label (funname
);
17618 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17619 instruction will reach 'foo', otherwise link as 'bl L42'".
17620 "L42" should be a 'branch island', that will do a far jump to
17621 'foo'. Branch islands are generated in
17622 macho_branch_islands(). */
17623 sprintf (buf
, "jbsr %%z%d,%.246s",
17624 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
17627 sprintf (buf
, "bl %%z%d", dest_operand_number
);
17631 /* Generate PIC and indirect symbol stubs. */
17634 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
17636 unsigned int length
;
17637 char *symbol_name
, *lazy_ptr_name
;
17638 char *local_label_0
;
17639 static int label
= 0;
17641 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17642 symb
= (*targetm
.strip_name_encoding
) (symb
);
17645 length
= strlen (symb
);
17646 symbol_name
= alloca (length
+ 32);
17647 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
17649 lazy_ptr_name
= alloca (length
+ 32);
17650 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
17653 machopic_picsymbol_stub1_section ();
17655 machopic_symbol_stub1_section ();
17659 fprintf (file
, "\t.align 5\n");
17661 fprintf (file
, "%s:\n", stub
);
17662 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17665 local_label_0
= alloca (sizeof("\"L0000000000$spb\""));
17666 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
17668 fprintf (file
, "\tmflr r0\n");
17669 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
17670 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
17671 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
17672 lazy_ptr_name
, local_label_0
);
17673 fprintf (file
, "\tmtlr r0\n");
17674 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
17675 (TARGET_64BIT
? "ldu" : "lwzu"),
17676 lazy_ptr_name
, local_label_0
);
17677 fprintf (file
, "\tmtctr r12\n");
17678 fprintf (file
, "\tbctr\n");
17682 fprintf (file
, "\t.align 4\n");
17684 fprintf (file
, "%s:\n", stub
);
17685 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17687 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
17688 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
17689 (TARGET_64BIT
? "ldu" : "lwzu"),
17691 fprintf (file
, "\tmtctr r12\n");
17692 fprintf (file
, "\tbctr\n");
17695 machopic_lazy_symbol_ptr_section ();
17696 fprintf (file
, "%s:\n", lazy_ptr_name
);
17697 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
17698 fprintf (file
, "%sdyld_stub_binding_helper\n",
17699 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
17702 /* Legitimize PIC addresses. If the address is already
17703 position-independent, we return ORIG. Newly generated
17704 position-independent addresses go into a reg. This is REG if non
17705 zero, otherwise we allocate register(s) as necessary. */
17707 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17710 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
17715 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
17716 reg
= gen_reg_rtx (Pmode
);
17718 if (GET_CODE (orig
) == CONST
)
17720 if (GET_CODE (XEXP (orig
, 0)) == PLUS
17721 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
17724 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
17726 /* Use a different reg for the intermediate value, as
17727 it will be marked UNCHANGING. */
17728 rtx reg_temp
= no_new_pseudos
? reg
: gen_reg_rtx (Pmode
);
17731 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
17734 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
17740 if (GET_CODE (offset
) == CONST_INT
)
17742 if (SMALL_INT (offset
))
17743 return plus_constant (base
, INTVAL (offset
));
17744 else if (! reload_in_progress
&& ! reload_completed
)
17745 offset
= force_reg (Pmode
, offset
);
17748 rtx mem
= force_const_mem (Pmode
, orig
);
17749 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
17752 return gen_rtx_PLUS (Pmode
, base
, offset
);
17755 /* Fall back on generic machopic code. */
17756 return machopic_legitimize_pic_address (orig
, mode
, reg
);
17759 /* This is just a placeholder to make linking work without having to
17760 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17761 ever needed for Darwin (not too likely!) this would have to get a
17762 real definition. */
17769 /* Output a .machine directive for the Darwin assembler, and call
17770 the generic start_file routine. */
17773 rs6000_darwin_file_start (void)
17775 static const struct
17781 { "ppc64", "ppc64", MASK_64BIT
},
17782 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
17783 { "power4", "ppc970", 0 },
17784 { "G5", "ppc970", 0 },
17785 { "7450", "ppc7450", 0 },
17786 { "7400", "ppc7400", MASK_ALTIVEC
},
17787 { "G4", "ppc7400", 0 },
17788 { "750", "ppc750", 0 },
17789 { "740", "ppc750", 0 },
17790 { "G3", "ppc750", 0 },
17791 { "604e", "ppc604e", 0 },
17792 { "604", "ppc604", 0 },
17793 { "603e", "ppc603", 0 },
17794 { "603", "ppc603", 0 },
17795 { "601", "ppc601", 0 },
17796 { NULL
, "ppc", 0 } };
17797 const char *cpu_id
= "";
17800 rs6000_file_start();
17802 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17803 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
17804 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
17805 && rs6000_select
[i
].string
[0] != '\0')
17806 cpu_id
= rs6000_select
[i
].string
;
17808 /* Look through the mapping array. Pick the first name that either
17809 matches the argument, has a bit set in IF_SET that is also set
17810 in the target flags, or has a NULL name. */
17813 while (mapping
[i
].arg
!= NULL
17814 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
17815 && (mapping
[i
].if_set
& target_flags
) == 0)
17818 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
17821 #endif /* TARGET_MACHO */
17824 static unsigned int
17825 rs6000_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
17827 return default_section_type_flags_1 (decl
, name
, reloc
,
17828 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
17831 /* Record an element in the table of global constructors. SYMBOL is
17832 a SYMBOL_REF of the function to be called; PRIORITY is a number
17833 between 0 and MAX_INIT_PRIORITY.
17835 This differs from default_named_section_asm_out_constructor in
17836 that we have special handling for -mrelocatable. */
17839 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
17841 const char *section
= ".ctors";
17844 if (priority
!= DEFAULT_INIT_PRIORITY
)
17846 sprintf (buf
, ".ctors.%.5u",
17847 /* Invert the numbering so the linker puts us in the proper
17848 order; constructors are run from right to left, and the
17849 linker sorts in increasing order. */
17850 MAX_INIT_PRIORITY
- priority
);
17854 named_section_flags (section
, SECTION_WRITE
);
17855 assemble_align (POINTER_SIZE
);
17857 if (TARGET_RELOCATABLE
)
17859 fputs ("\t.long (", asm_out_file
);
17860 output_addr_const (asm_out_file
, symbol
);
17861 fputs (")@fixup\n", asm_out_file
);
17864 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
17868 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
17870 const char *section
= ".dtors";
17873 if (priority
!= DEFAULT_INIT_PRIORITY
)
17875 sprintf (buf
, ".dtors.%.5u",
17876 /* Invert the numbering so the linker puts us in the proper
17877 order; constructors are run from right to left, and the
17878 linker sorts in increasing order. */
17879 MAX_INIT_PRIORITY
- priority
);
17883 named_section_flags (section
, SECTION_WRITE
);
17884 assemble_align (POINTER_SIZE
);
17886 if (TARGET_RELOCATABLE
)
17888 fputs ("\t.long (", asm_out_file
);
17889 output_addr_const (asm_out_file
, symbol
);
17890 fputs (")@fixup\n", asm_out_file
);
17893 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
17897 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
17901 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
17902 ASM_OUTPUT_LABEL (file
, name
);
17903 fputs (DOUBLE_INT_ASM_OP
, file
);
17904 rs6000_output_function_entry (file
, name
);
17905 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
17908 fputs ("\t.size\t", file
);
17909 assemble_name (file
, name
);
17910 fputs (",24\n\t.type\t.", file
);
17911 assemble_name (file
, name
);
17912 fputs (",@function\n", file
);
17913 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
17915 fputs ("\t.globl\t.", file
);
17916 assemble_name (file
, name
);
17921 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
17922 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
17923 rs6000_output_function_entry (file
, name
);
17924 fputs (":\n", file
);
17928 if (TARGET_RELOCATABLE
17929 && (get_pool_size () != 0 || current_function_profile
)
17934 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
17936 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
17937 fprintf (file
, "\t.long ");
17938 assemble_name (file
, buf
);
17940 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
17941 assemble_name (file
, buf
);
17945 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
17946 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
17948 if (DEFAULT_ABI
== ABI_AIX
)
17950 const char *desc_name
, *orig_name
;
17952 orig_name
= (*targetm
.strip_name_encoding
) (name
);
17953 desc_name
= orig_name
;
17954 while (*desc_name
== '.')
17957 if (TREE_PUBLIC (decl
))
17958 fprintf (file
, "\t.globl %s\n", desc_name
);
17960 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
17961 fprintf (file
, "%s:\n", desc_name
);
17962 fprintf (file
, "\t.long %s\n", orig_name
);
17963 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
17964 if (DEFAULT_ABI
== ABI_AIX
)
17965 fputs ("\t.long 0\n", file
);
17966 fprintf (file
, "\t.previous\n");
17968 ASM_OUTPUT_LABEL (file
, name
);
17974 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
17976 fputs (GLOBAL_ASM_OP
, stream
);
17977 RS6000_OUTPUT_BASENAME (stream
, name
);
17978 putc ('\n', stream
);
17982 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
17983 tree decl ATTRIBUTE_UNUSED
)
17986 static const char * const suffix
[3] = { "PR", "RO", "RW" };
17988 if (flags
& SECTION_CODE
)
17990 else if (flags
& SECTION_WRITE
)
17995 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
17996 (flags
& SECTION_CODE
) ? "." : "",
17997 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
18001 rs6000_xcoff_select_section (tree decl
, int reloc
,
18002 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
18004 if (decl_readonly_section_1 (decl
, reloc
, 1))
18006 if (TREE_PUBLIC (decl
))
18007 read_only_data_section ();
18009 read_only_private_data_section ();
18013 if (TREE_PUBLIC (decl
))
18016 private_data_section ();
18021 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
18025 /* Use select_section for private and uninitialized data. */
18026 if (!TREE_PUBLIC (decl
)
18027 || DECL_COMMON (decl
)
18028 || DECL_INITIAL (decl
) == NULL_TREE
18029 || DECL_INITIAL (decl
) == error_mark_node
18030 || (flag_zero_initialized_in_bss
18031 && initializer_zerop (DECL_INITIAL (decl
))))
18034 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
18035 name
= (*targetm
.strip_name_encoding
) (name
);
18036 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
18039 /* Select section for constant in constant pool.
18041 On RS/6000, all constants are in the private read-only data area.
18042 However, if this is being placed in the TOC it must be output as a
18046 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
18047 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
18049 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
18052 read_only_private_data_section ();
18055 /* Remove any trailing [DS] or the like from the symbol name. */
18057 static const char *
18058 rs6000_xcoff_strip_name_encoding (const char *name
)
18063 len
= strlen (name
);
18064 if (name
[len
- 1] == ']')
18065 return ggc_alloc_string (name
, len
- 4);
18070 /* Section attributes. AIX is always PIC. */
18072 static unsigned int
18073 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
18075 unsigned int align
;
18076 unsigned int flags
= default_section_type_flags_1 (decl
, name
, reloc
, 1);
18078 /* Align to at least UNIT size. */
18079 if (flags
& SECTION_CODE
)
18080 align
= MIN_UNITS_PER_WORD
;
18082 /* Increase alignment of large objects if not already stricter. */
18083 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
18084 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
18085 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
18087 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
18090 /* Output at beginning of assembler file.
18092 Initialize the section names for the RS/6000 at this point.
18094 Specify filename, including full path, to assembler.
18096 We want to go into the TOC section so at least one .toc will be emitted.
18097 Also, in order to output proper .bs/.es pairs, we need at least one static
18098 [RW] section emitted.
18100 Finally, declare mcount when profiling to make the assembler happy. */
18103 rs6000_xcoff_file_start (void)
18105 rs6000_gen_section_name (&xcoff_bss_section_name
,
18106 main_input_filename
, ".bss_");
18107 rs6000_gen_section_name (&xcoff_private_data_section_name
,
18108 main_input_filename
, ".rw_");
18109 rs6000_gen_section_name (&xcoff_read_only_section_name
,
18110 main_input_filename
, ".ro_");
18112 fputs ("\t.file\t", asm_out_file
);
18113 output_quoted_string (asm_out_file
, main_input_filename
);
18114 fputc ('\n', asm_out_file
);
18115 if (write_symbols
!= NO_DEBUG
)
18116 private_data_section ();
18119 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
18120 rs6000_file_start ();
18123 /* Output at end of assembler file.
18124 On the RS/6000, referencing data should automatically pull in text. */
18127 rs6000_xcoff_file_end (void)
18130 fputs ("_section_.text:\n", asm_out_file
);
18132 fputs (TARGET_32BIT
18133 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18136 #endif /* TARGET_XCOFF */
18139 /* Cross-module name binding. Darwin does not support overriding
18140 functions at dynamic-link time. */
18143 rs6000_binds_local_p (tree decl
)
18145 return default_binds_local_p_1 (decl
, 0);
18149 /* Compute a (partial) cost for rtx X. Return true if the complete
18150 cost has been computed, and false if subexpressions should be
18151 scanned. In either case, *TOTAL contains the cost result. */
18154 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
18156 enum machine_mode mode
= GET_MODE (x
);
18160 /* On the RS/6000, if it is valid in the insn, it is free. */
18162 if (((outer_code
== SET
18163 || outer_code
== PLUS
18164 || outer_code
== MINUS
)
18165 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18166 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')))
18167 || (outer_code
== AND
18168 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18169 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18170 mode
== SImode
? 'L' : 'J'))
18171 || mask_operand (x
, VOIDmode
)))
18172 || ((outer_code
== IOR
|| outer_code
== XOR
)
18173 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18174 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18175 mode
== SImode
? 'L' : 'J'))))
18176 || outer_code
== ASHIFT
18177 || outer_code
== ASHIFTRT
18178 || outer_code
== LSHIFTRT
18179 || outer_code
== ROTATE
18180 || outer_code
== ROTATERT
18181 || outer_code
== ZERO_EXTRACT
18182 || (outer_code
== MULT
18183 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
18184 || ((outer_code
== DIV
|| outer_code
== UDIV
18185 || outer_code
== MOD
|| outer_code
== UMOD
)
18186 && exact_log2 (INTVAL (x
)) >= 0)
18187 || (outer_code
== COMPARE
18188 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18189 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')))
18190 || (outer_code
== EQ
18191 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
18192 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18193 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
18194 mode
== SImode
? 'L' : 'J'))))
18195 || (outer_code
== GTU
18196 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
18197 || (outer_code
== LTU
18198 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'P')))
18203 else if ((outer_code
== PLUS
18204 && reg_or_add_cint64_operand (x
, VOIDmode
))
18205 || (outer_code
== MINUS
18206 && reg_or_sub_cint64_operand (x
, VOIDmode
))
18207 || ((outer_code
== SET
18208 || outer_code
== IOR
18209 || outer_code
== XOR
)
18211 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
18213 *total
= COSTS_N_INSNS (1);
18220 && ((outer_code
== AND
18221 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
18222 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')
18223 || mask64_operand (x
, DImode
)))
18224 || ((outer_code
== IOR
|| outer_code
== XOR
)
18225 && CONST_DOUBLE_HIGH (x
) == 0
18226 && (CONST_DOUBLE_LOW (x
)
18227 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)))
18232 else if (mode
== DImode
18233 && (outer_code
== SET
18234 || outer_code
== IOR
18235 || outer_code
== XOR
)
18236 && CONST_DOUBLE_HIGH (x
) == 0)
18238 *total
= COSTS_N_INSNS (1);
18247 /* When optimizing for size, MEM should be slightly more expensive
18248 than generating address, e.g., (plus (reg) (const)).
18249 L1 cache latency is about two instructions. */
18250 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18258 if (mode
== DFmode
)
18260 if (GET_CODE (XEXP (x
, 0)) == MULT
)
18262 /* FNMA accounted in outer NEG. */
18263 if (outer_code
== NEG
)
18264 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
18266 *total
= rs6000_cost
->dmul
;
18269 *total
= rs6000_cost
->fp
;
18271 else if (mode
== SFmode
)
18273 /* FNMA accounted in outer NEG. */
18274 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
18277 *total
= rs6000_cost
->fp
;
18279 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
18281 /* The rs6000 doesn't have shift-and-add instructions. */
18282 rs6000_rtx_costs (XEXP (x
, 0), MULT
, PLUS
, total
);
18283 *total
+= COSTS_N_INSNS (1);
18286 *total
= COSTS_N_INSNS (1);
18290 if (mode
== DFmode
)
18292 if (GET_CODE (XEXP (x
, 0)) == MULT
)
18294 /* FNMA accounted in outer NEG. */
18295 if (outer_code
== NEG
)
18298 *total
= rs6000_cost
->dmul
;
18301 *total
= rs6000_cost
->fp
;
18303 else if (mode
== SFmode
)
18305 /* FNMA accounted in outer NEG. */
18306 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
18309 *total
= rs6000_cost
->fp
;
18311 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
18313 /* The rs6000 doesn't have shift-and-sub instructions. */
18314 rs6000_rtx_costs (XEXP (x
, 0), MULT
, MINUS
, total
);
18315 *total
+= COSTS_N_INSNS (1);
18318 *total
= COSTS_N_INSNS (1);
18322 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
18323 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x
, 1)), 'I'))
18325 if (INTVAL (XEXP (x
, 1)) >= -256
18326 && INTVAL (XEXP (x
, 1)) <= 255)
18327 *total
= rs6000_cost
->mulsi_const9
;
18329 *total
= rs6000_cost
->mulsi_const
;
18331 /* FMA accounted in outer PLUS/MINUS. */
18332 else if ((mode
== DFmode
|| mode
== SFmode
)
18333 && (outer_code
== PLUS
|| outer_code
== MINUS
))
18335 else if (mode
== DFmode
)
18336 *total
= rs6000_cost
->dmul
;
18337 else if (mode
== SFmode
)
18338 *total
= rs6000_cost
->fp
;
18339 else if (mode
== DImode
)
18340 *total
= rs6000_cost
->muldi
;
18342 *total
= rs6000_cost
->mulsi
;
18347 if (FLOAT_MODE_P (mode
))
18349 *total
= mode
== DFmode
? rs6000_cost
->ddiv
18350 : rs6000_cost
->sdiv
;
18357 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
18358 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
18360 if (code
== DIV
|| code
== MOD
)
18362 *total
= COSTS_N_INSNS (2);
18365 *total
= COSTS_N_INSNS (1);
18369 if (GET_MODE (XEXP (x
, 1)) == DImode
)
18370 *total
= rs6000_cost
->divdi
;
18372 *total
= rs6000_cost
->divsi
;
18374 /* Add in shift and subtract for MOD. */
18375 if (code
== MOD
|| code
== UMOD
)
18376 *total
+= COSTS_N_INSNS (2);
18380 *total
= COSTS_N_INSNS (4);
18384 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
18395 *total
= COSTS_N_INSNS (1);
18403 /* Handle mul_highpart. */
18404 if (outer_code
== TRUNCATE
18405 && GET_CODE (XEXP (x
, 0)) == MULT
)
18407 if (mode
== DImode
)
18408 *total
= rs6000_cost
->muldi
;
18410 *total
= rs6000_cost
->mulsi
;
18413 else if (outer_code
== AND
)
18416 *total
= COSTS_N_INSNS (1);
18421 if (GET_CODE (XEXP (x
, 0)) == MEM
)
18424 *total
= COSTS_N_INSNS (1);
18430 if (!FLOAT_MODE_P (mode
))
18432 *total
= COSTS_N_INSNS (1);
18438 case UNSIGNED_FLOAT
:
18442 case FLOAT_TRUNCATE
:
18443 *total
= rs6000_cost
->fp
;
18447 switch (XINT (x
, 1))
18450 *total
= rs6000_cost
->fp
;
18462 *total
= COSTS_N_INSNS (1);
18465 else if (FLOAT_MODE_P (mode
)
18466 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18468 *total
= rs6000_cost
->fp
;
18476 /* Carry bit requires mode == Pmode.
18477 NEG or PLUS already counted so only add one. */
18479 && (outer_code
== NEG
|| outer_code
== PLUS
))
18481 *total
= COSTS_N_INSNS (1);
18484 if (outer_code
== SET
)
18486 if (XEXP (x
, 1) == const0_rtx
)
18488 *total
= COSTS_N_INSNS (2);
18491 else if (mode
== Pmode
)
18493 *total
= COSTS_N_INSNS (3);
18502 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
18504 *total
= COSTS_N_INSNS (2);
18508 if (outer_code
== COMPARE
)
18522 /* A C expression returning the cost of moving data from a register of class
18523 CLASS1 to one of CLASS2. */
18526 rs6000_register_move_cost (enum machine_mode mode
,
18527 enum reg_class from
, enum reg_class to
)
18529 /* Moves from/to GENERAL_REGS. */
18530 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
18531 || reg_classes_intersect_p (from
, GENERAL_REGS
))
18533 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
18536 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
18537 return (rs6000_memory_move_cost (mode
, from
, 0)
18538 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
18540 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18542 else if (from
== CR_REGS
)
18546 /* A move will cost one instruction per GPR moved. */
18547 return 2 * HARD_REGNO_NREGS (0, mode
);
18550 /* Moving between two similar registers is just one instruction. */
18551 else if (reg_classes_intersect_p (to
, from
))
18552 return mode
== TFmode
? 4 : 2;
18554 /* Everything else has to go through GENERAL_REGS. */
18556 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
18557 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
18560 /* A C expressions returning the cost of moving data of MODE from a register to
18564 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
18565 int in ATTRIBUTE_UNUSED
)
18567 if (reg_classes_intersect_p (class, GENERAL_REGS
))
18568 return 4 * HARD_REGNO_NREGS (0, mode
);
18569 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
18570 return 4 * HARD_REGNO_NREGS (32, mode
);
18571 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
18572 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO
, mode
);
18574 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
18577 /* Return an RTX representing where to find the function value of a
18578 function returning MODE. */
18580 rs6000_complex_function_value (enum machine_mode mode
)
18582 unsigned int regno
;
18584 enum machine_mode inner
= GET_MODE_INNER (mode
);
18585 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
18587 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18588 regno
= FP_ARG_RETURN
;
18591 regno
= GP_ARG_RETURN
;
18593 /* 32-bit is OK since it'll go in r3/r4. */
18594 if (TARGET_32BIT
&& inner_bytes
>= 4)
18595 return gen_rtx_REG (mode
, regno
);
18598 if (inner_bytes
>= 8)
18599 return gen_rtx_REG (mode
, regno
);
18601 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
18603 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
18604 GEN_INT (inner_bytes
));
18605 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
18608 /* Compose a PARALLEL for a darwin64 struct being returned by
18612 rs6000_darwin64_function_value (CUMULATIVE_ARGS
*cum
, tree valtype
)
18615 rtx rvec
[FIRST_PSEUDO_REGISTER
], sub
, roffset
, suboff
;
18616 int k
= 0, bytepos
, tot
, elt
, i
, subbytepos
;
18617 enum machine_mode fmode
;
18619 switch (TREE_CODE (valtype
))
18622 for (f
= TYPE_FIELDS (valtype
); f
; f
= TREE_CHAIN (f
))
18623 if (TREE_CODE (f
) == FIELD_DECL
)
18625 ftype
= TREE_TYPE (f
);
18626 fmode
= TYPE_MODE (ftype
);
18627 bytepos
= int_bit_position (f
) / BITS_PER_UNIT
;
18628 if (USE_FP_FOR_ARG_P (cum
, fmode
, ftype
))
18630 sub
= gen_rtx_REG (fmode
, cum
->fregno
++);
18631 cum
->sysv_gregno
++;
18633 else if (USE_ALTIVEC_FOR_ARG_P (cum
, fmode
, ftype
, 1))
18635 sub
= gen_rtx_REG (fmode
, cum
->vregno
++);
18636 cum
->sysv_gregno
++;
18638 else if (fmode
== BLKmode
18639 && (TREE_CODE (ftype
) == RECORD_TYPE
18640 || TREE_CODE (ftype
) == ARRAY_TYPE
))
18641 sub
= rs6000_darwin64_function_value (cum
, ftype
);
18643 sub
= gen_rtx_REG (fmode
, cum
->sysv_gregno
++);
18644 if (sub
== NULL_RTX
)
18646 else if (GET_CODE (sub
) == PARALLEL
)
18648 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
18650 rtx subsub
= XVECEXP (sub
, 0, i
);
18652 suboff
= XEXP (subsub
, 1);
18653 subbytepos
= INTVAL (suboff
);
18654 subbytepos
+= bytepos
;
18655 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
18656 subsub
= XEXP (subsub
, 0);
18657 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
18662 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
18663 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
18667 return gen_rtx_PARALLEL (TYPE_MODE (valtype
), gen_rtvec_v (k
, rvec
));
18672 /* If passing by value won't work, give up. */
18673 if (int_size_in_bytes (valtype
) <= 0)
18675 ftype
= TREE_TYPE (valtype
);
18676 fmode
= TYPE_MODE (ftype
);
18677 tot
= int_size_in_bytes (valtype
) / int_size_in_bytes (ftype
);
18679 for (elt
= 0; elt
< tot
; ++elt
)
18681 if (USE_FP_FOR_ARG_P (cum
, fmode
, ftype
))
18683 sub
= gen_rtx_REG (fmode
, cum
->fregno
++);
18684 cum
->sysv_gregno
++;
18686 else if (USE_ALTIVEC_FOR_ARG_P (cum
, fmode
, ftype
, 1))
18688 sub
= gen_rtx_REG (fmode
, cum
->vregno
++);
18689 cum
->sysv_gregno
++;
18691 else if (fmode
== BLKmode
18692 && (TREE_CODE (ftype
) == RECORD_TYPE
18693 || TREE_CODE (ftype
) == ARRAY_TYPE
))
18694 sub
= rs6000_darwin64_function_value (cum
, ftype
);
18696 sub
= gen_rtx_REG (fmode
, cum
->sysv_gregno
++);
18697 if (sub
== NULL_RTX
)
18699 else if (GET_CODE (sub
) == PARALLEL
)
18701 for (i
= 0; i
< XVECLEN (sub
, 0); i
++)
18703 rtx subsub
= XVECEXP (sub
, 0, i
);
18705 suboff
= XEXP (subsub
, 1);
18706 subbytepos
= INTVAL (suboff
);
18707 subbytepos
+= bytepos
;
18708 roffset
= gen_rtx_CONST_INT (SImode
, subbytepos
);
18709 subsub
= XEXP (subsub
, 0);
18710 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, subsub
, roffset
);
18715 roffset
= gen_rtx_CONST_INT (SImode
, bytepos
);
18716 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, sub
, roffset
);
18718 bytepos
+= int_size_in_bytes (ftype
);
18721 return gen_rtx_PARALLEL (TYPE_MODE (valtype
), gen_rtvec_v (k
, rvec
));
18730 /* Define how to find the value returned by a function.
18731 VALTYPE is the data type of the value (as a tree).
18732 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18733 otherwise, FUNC is 0.
18735 On the SPE, both FPs and vectors are returned in r3.
18737 On RS/6000 an integer value is in r3 and a floating-point value is in
18738 fp1, unless -msoft-float. */
18741 rs6000_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
18743 enum machine_mode mode
;
18744 unsigned int regno
;
18746 /* Special handling for structs in darwin64. */
18747 if (rs6000_darwin64_abi
18748 && TYPE_MODE (valtype
) == BLKmode
18749 && (TREE_CODE (valtype
) == RECORD_TYPE
18750 || TREE_CODE (valtype
) == ARRAY_TYPE
))
18752 CUMULATIVE_ARGS valcum
;
18755 valcum
.sysv_gregno
= GP_ARG_RETURN
;
18756 valcum
.fregno
= FP_ARG_MIN_REG
;
18757 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
18758 valret
= rs6000_darwin64_function_value (&valcum
, valtype
);
18761 /* Otherwise fall through to standard ABI rules. */
18764 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
18766 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18767 return gen_rtx_PARALLEL (DImode
,
18769 gen_rtx_EXPR_LIST (VOIDmode
,
18770 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
18772 gen_rtx_EXPR_LIST (VOIDmode
,
18773 gen_rtx_REG (SImode
,
18774 GP_ARG_RETURN
+ 1),
18778 if ((INTEGRAL_TYPE_P (valtype
)
18779 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
18780 || POINTER_TYPE_P (valtype
))
18781 mode
= TARGET_32BIT
? SImode
: DImode
;
18783 mode
= TYPE_MODE (valtype
);
18785 if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18786 regno
= FP_ARG_RETURN
;
18787 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
18788 && targetm
.calls
.split_complex_arg
)
18789 return rs6000_complex_function_value (mode
);
18790 else if (TREE_CODE (valtype
) == VECTOR_TYPE
18791 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
18792 && ALTIVEC_VECTOR_MODE (mode
))
18793 regno
= ALTIVEC_ARG_RETURN
;
18794 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
18795 && (mode
== DFmode
|| mode
== DCmode
))
18796 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
18798 regno
= GP_ARG_RETURN
;
18800 return gen_rtx_REG (mode
, regno
);
18803 /* Define how to find the value returned by a library function
18804 assuming the value has mode MODE. */
18806 rs6000_libcall_value (enum machine_mode mode
)
18808 unsigned int regno
;
18810 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
18812 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18813 return gen_rtx_PARALLEL (DImode
,
18815 gen_rtx_EXPR_LIST (VOIDmode
,
18816 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
18818 gen_rtx_EXPR_LIST (VOIDmode
,
18819 gen_rtx_REG (SImode
,
18820 GP_ARG_RETURN
+ 1),
18824 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
18825 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
18826 regno
= FP_ARG_RETURN
;
18827 else if (ALTIVEC_VECTOR_MODE (mode
)
18828 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
18829 regno
= ALTIVEC_ARG_RETURN
;
18830 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
18831 return rs6000_complex_function_value (mode
);
18832 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
18833 && (mode
== DFmode
|| mode
== DCmode
))
18834 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
18836 regno
= GP_ARG_RETURN
;
18838 return gen_rtx_REG (mode
, regno
);
18841 /* Define the offset between two registers, FROM to be eliminated and its
18842 replacement TO, at the start of a routine. */
18844 rs6000_initial_elimination_offset (int from
, int to
)
18846 rs6000_stack_t
*info
= rs6000_stack_info ();
18847 HOST_WIDE_INT offset
;
18849 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
18850 offset
= info
->push_p
? 0 : -info
->total_size
;
18851 else if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
18852 offset
= info
->total_size
;
18853 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
18854 offset
= info
->push_p
? info
->total_size
: 0;
18855 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
18863 /* Return true if TYPE is of type __ev64_opaque__. */
18866 is_ev64_opaque_type (tree type
)
18869 && (type
== opaque_V2SI_type_node
18870 || type
== opaque_V2SF_type_node
18871 || type
== opaque_p_V2SI_type_node
));
18875 rs6000_dwarf_register_span (rtx reg
)
18880 && (SPE_VECTOR_MODE (GET_MODE (reg
))
18881 || (TARGET_E500_DOUBLE
&& GET_MODE (reg
) == DFmode
)))
18886 regno
= REGNO (reg
);
18888 /* The duality of the SPE register size wreaks all kinds of havoc.
18889 This is a way of distinguishing r0 in 32-bits from r0 in
18892 gen_rtx_PARALLEL (VOIDmode
,
18895 gen_rtx_REG (SImode
, regno
+ 1200),
18896 gen_rtx_REG (SImode
, regno
))
18898 gen_rtx_REG (SImode
, regno
),
18899 gen_rtx_REG (SImode
, regno
+ 1200)));
18902 /* Map internal gcc register numbers to DWARF2 register numbers. */
18905 rs6000_dbx_register_number (unsigned int regno
)
18907 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
18909 if (regno
== MQ_REGNO
)
18911 if (regno
== LINK_REGISTER_REGNUM
)
18913 if (regno
== COUNT_REGISTER_REGNUM
)
18915 if (CR_REGNO_P (regno
))
18916 return regno
- CR0_REGNO
+ 86;
18917 if (regno
== XER_REGNO
)
18919 if (ALTIVEC_REGNO_P (regno
))
18920 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
18921 if (regno
== VRSAVE_REGNO
)
18923 if (regno
== VSCR_REGNO
)
18925 if (regno
== SPE_ACC_REGNO
)
18927 if (regno
== SPEFSCR_REGNO
)
18929 /* SPE high reg number. We get these values of regno from
18930 rs6000_dwarf_register_span. */
18931 if (regno
>= 1200 && regno
< 1232)
18937 /* target hook eh_return_filter_mode */
18938 static enum machine_mode
18939 rs6000_eh_return_filter_mode (void)
18941 return TARGET_32BIT
? SImode
: word_mode
;
18944 /* Target hook for vector_mode_supported_p. */
18946 rs6000_vector_mode_supported_p (enum machine_mode mode
)
18949 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
18952 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
18959 #include "gt-rs6000.h"