1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
35 #include "basic-block.h"
43 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
44 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 #ifndef REGISTER_MOVE_COST
82 #define REGISTER_MOVE_COST(m, x, y) 2
86 #define LOCAL_REGNO(REGNO) 0
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx
*reg_last_reload_reg
;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload
;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload
;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx
*reg_equiv_constant
;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx
*reg_equiv_memory_loc
;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx
*reg_equiv_address
;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static unsigned int *reg_max_ref_width
;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx
*reg_equiv_init
;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber
;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid
;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead
;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs
;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global
;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET
*pseudo_previous_regs
;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET
*pseudo_forbidden_regs
;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs
;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg
;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels
;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok
;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok
;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
239 /* Width allocated so far for that stack slot. */
240 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos
;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted
;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid
;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed
;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress
= 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
265 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack
;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj
;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj
;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj
;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain
*reload_insn_chain
;
292 extern tree current_function_decl
;
294 extern union tree_node
*current_function_decl
;
297 /* List of all insns needing reloads. */
298 static struct insn_chain
*insns_need_reload
;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from
; /* Register number to be eliminated. */
308 int to
; /* Register number used as replacement. */
309 int initial_offset
; /* Initial difference between values. */
310 int can_eliminate
; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset
; /* Current offset between the two regs. */
314 int previous_offset
; /* Offset at end of previous insn. */
315 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx
; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx
; /* REG rtx for the replacement. */
324 static struct elim_table
*reg_eliminate
= 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1
[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
344 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset
;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable
;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants
;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at
;
365 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
367 /* Number of labels in the current function. */
369 static int num_labels
;
371 static void replace_pseudos_in_call_usage
PARAMS((rtx
*,
374 static void maybe_fix_stack_asms
PARAMS ((void));
375 static void copy_reloads
PARAMS ((struct insn_chain
*));
376 static void calculate_needs_all_insns
PARAMS ((int));
377 static int find_reg
PARAMS ((struct insn_chain
*, int));
378 static void find_reload_regs
PARAMS ((struct insn_chain
*));
379 static void select_reload_regs
PARAMS ((void));
380 static void delete_caller_save_insns
PARAMS ((void));
382 static void spill_failure
PARAMS ((rtx
, enum reg_class
));
383 static void count_spilled_pseudo
PARAMS ((int, int, int));
384 static void delete_dead_insn
PARAMS ((rtx
));
385 static void alter_reg
PARAMS ((int, int));
386 static void set_label_offsets
PARAMS ((rtx
, rtx
, int));
387 static void check_eliminable_occurrences
PARAMS ((rtx
));
388 static void elimination_effects
PARAMS ((rtx
, enum machine_mode
));
389 static int eliminate_regs_in_insn
PARAMS ((rtx
, int));
390 static void update_eliminable_offsets
PARAMS ((void));
391 static void mark_not_eliminable
PARAMS ((rtx
, rtx
, void *));
392 static void set_initial_elim_offsets
PARAMS ((void));
393 static void verify_initial_elim_offsets
PARAMS ((void));
394 static void set_initial_label_offsets
PARAMS ((void));
395 static void set_offsets_for_label
PARAMS ((rtx
));
396 static void init_elim_table
PARAMS ((void));
397 static void update_eliminables
PARAMS ((HARD_REG_SET
*));
398 static void spill_hard_reg
PARAMS ((unsigned int, int));
399 static int finish_spills
PARAMS ((int));
400 static void ior_hard_reg_set
PARAMS ((HARD_REG_SET
*, HARD_REG_SET
*));
401 static void scan_paradoxical_subregs
PARAMS ((rtx
));
402 static void count_pseudo
PARAMS ((int));
403 static void order_regs_for_reload
PARAMS ((struct insn_chain
*));
404 static void reload_as_needed
PARAMS ((int));
405 static void forget_old_reloads_1
PARAMS ((rtx
, rtx
, void *));
406 static int reload_reg_class_lower
PARAMS ((const PTR
, const PTR
));
407 static void mark_reload_reg_in_use
PARAMS ((unsigned int, int,
410 static void clear_reload_reg_in_use
PARAMS ((unsigned int, int,
413 static int reload_reg_free_p
PARAMS ((unsigned int, int,
415 static int reload_reg_free_for_value_p
PARAMS ((int, int, int,
417 rtx
, rtx
, int, int));
418 static int free_for_value_p
PARAMS ((int, enum machine_mode
, int,
419 enum reload_type
, rtx
, rtx
,
421 static int reload_reg_reaches_end_p
PARAMS ((unsigned int, int,
423 static int allocate_reload_reg
PARAMS ((struct insn_chain
*, int,
425 static int conflicts_with_override
PARAMS ((rtx
));
426 static void failed_reload
PARAMS ((rtx
, int));
427 static int set_reload_reg
PARAMS ((int, int));
428 static void choose_reload_regs_init
PARAMS ((struct insn_chain
*, rtx
*));
429 static void choose_reload_regs
PARAMS ((struct insn_chain
*));
430 static void merge_assigned_reloads
PARAMS ((rtx
));
431 static void emit_input_reload_insns
PARAMS ((struct insn_chain
*,
432 struct reload
*, rtx
, int));
433 static void emit_output_reload_insns
PARAMS ((struct insn_chain
*,
434 struct reload
*, int));
435 static void do_input_reload
PARAMS ((struct insn_chain
*,
436 struct reload
*, int));
437 static void do_output_reload
PARAMS ((struct insn_chain
*,
438 struct reload
*, int));
439 static void emit_reload_insns
PARAMS ((struct insn_chain
*));
440 static void delete_output_reload
PARAMS ((rtx
, int, int));
441 static void delete_address_reloads
PARAMS ((rtx
, rtx
));
442 static void delete_address_reloads_1
PARAMS ((rtx
, rtx
, rtx
));
443 static rtx inc_for_reload
PARAMS ((rtx
, rtx
, rtx
, int));
444 static int constraint_accepts_reg_p
PARAMS ((const char *, rtx
));
445 static void reload_cse_regs_1
PARAMS ((rtx
));
446 static int reload_cse_noop_set_p
PARAMS ((rtx
));
447 static int reload_cse_simplify_set
PARAMS ((rtx
, rtx
));
448 static int reload_cse_simplify_operands
PARAMS ((rtx
));
449 static void reload_combine
PARAMS ((void));
450 static void reload_combine_note_use
PARAMS ((rtx
*, rtx
));
451 static void reload_combine_note_store
PARAMS ((rtx
, rtx
, void *));
452 static void reload_cse_move2add
PARAMS ((rtx
));
453 static void move2add_note_store
PARAMS ((rtx
, rtx
, void *));
455 static void add_auto_inc_notes
PARAMS ((rtx
, rtx
));
457 static HOST_WIDE_INT sext_for_mode
PARAMS ((enum machine_mode
,
459 static void failed_reload
PARAMS ((rtx
, int));
460 static int set_reload_reg
PARAMS ((int, int));
461 static void reload_cse_delete_noop_set
PARAMS ((rtx
, rtx
));
462 static void reload_cse_simplify
PARAMS ((rtx
));
463 extern void dump_needs
PARAMS ((struct insn_chain
*));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode
,
480 LAST_VIRTUAL_REGISTER
+ 1),
482 spill_indirect_levels
= 0;
484 while (memory_address_p (QImode
, tem
))
486 spill_indirect_levels
++;
487 tem
= gen_rtx_MEM (Pmode
, tem
);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
493 indirect_symref_ok
= memory_address_p (QImode
, tem
);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
499 tem
= gen_rtx_PLUS (Pmode
,
500 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
501 gen_rtx_REG (Pmode
, i
));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem
= plus_constant (tem
, 4);
506 if (memory_address_p (QImode
, tem
))
508 double_reg_address_ok
= 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack
);
515 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
517 INIT_REG_SET (&spilled_pseudos
);
518 INIT_REG_SET (&pseudos_counted
);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain
*unused_insn_chains
= 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain
*c
;
530 if (unused_insn_chains
== 0)
532 c
= (struct insn_chain
*)
533 obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
534 INIT_REG_SET (&c
->live_throughout
);
535 INIT_REG_SET (&c
->dead_or_set
);
539 c
= unused_insn_chains
;
540 unused_insn_chains
= c
->next
;
542 c
->is_caller_save_insn
= 0;
543 c
->need_operand_change
= 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to
, from
)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from
, FIRST_PSEUDO_REGISTER
, regno
,
562 int r
= reg_renumber
[regno
];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed
)
576 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
578 SET_HARD_REG_BIT (*to
, r
+ nregs
);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
)
589 enum machine_mode mem_mode
;
603 int regno
= REGNO (x
);
605 if (regno
< FIRST_PSEUDO_REGISTER
)
608 x
= eliminate_regs (x
, mem_mode
, usage
);
612 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
);
616 if (reg_equiv_constant
[regno
])
617 *loc
= reg_equiv_constant
[regno
];
618 else if (reg_equiv_mem
[regno
])
619 *loc
= reg_equiv_mem
[regno
];
620 else if (reg_equiv_address
[regno
])
621 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
622 else if (GET_CODE (regno_reg_rtx
[regno
]) != REG
623 || REGNO (regno_reg_rtx
[regno
]) != regno
)
624 *loc
= regno_reg_rtx
[regno
];
630 else if (code
== MEM
)
632 replace_pseudos_in_call_usage (& XEXP (x
, 0), GET_MODE (x
), usage
);
636 /* Process each of our operands recursively. */
637 fmt
= GET_RTX_FORMAT (code
);
638 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
640 replace_pseudos_in_call_usage (&XEXP (x
, i
), mem_mode
, usage
);
641 else if (*fmt
== 'E')
642 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
643 replace_pseudos_in_call_usage (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination
;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed
;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first
, global
)
677 register struct elim_table
*ep
;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr
= NULL_PTR
;
682 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid
= get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot
, 0, sizeof spill_stack_slot
);
705 memset ((char *) spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label
)
721 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
722 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
723 regs_ever_live
[i
] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
736 reg_equiv_memory_loc
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
737 reg_equiv_mem
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
738 reg_equiv_init
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
739 reg_equiv_address
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
740 reg_max_ref_width
= (unsigned int *) xcalloc (max_regno
, sizeof (int));
741 reg_old_renumber
= (short *) xcalloc (max_regno
, sizeof (short));
742 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
743 pseudo_forbidden_regs
744 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
746 = (HARD_REG_SET
*) xcalloc (max_regno
, sizeof (HARD_REG_SET
));
748 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
750 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
751 Also find all paradoxical subregs and find largest such for each pseudo.
752 On machines with small register classes, record hard registers that
753 are used for user variables. These can never be used for spills.
754 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
755 caller-saved registers must be marked live. */
757 num_eliminable_invariants
= 0;
758 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
760 rtx set
= single_set (insn
);
762 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
763 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
764 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
765 if (! call_used_regs
[i
])
766 regs_ever_live
[i
] = 1;
768 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
770 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
772 #ifdef LEGITIMATE_PIC_OPERAND_P
773 && (! function_invariant_p (XEXP (note
, 0))
775 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
779 rtx x
= XEXP (note
, 0);
780 i
= REGNO (SET_DEST (set
));
781 if (i
> LAST_VIRTUAL_REGISTER
)
783 if (GET_CODE (x
) == MEM
)
785 /* If the operand is a PLUS, the MEM may be shared,
786 so make sure we have an unshared copy here. */
787 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
790 reg_equiv_memory_loc
[i
] = x
;
792 else if (function_invariant_p (x
))
794 if (GET_CODE (x
) == PLUS
)
796 /* This is PLUS of frame pointer and a constant,
797 and might be shared. Unshare it. */
798 reg_equiv_constant
[i
] = copy_rtx (x
);
799 num_eliminable_invariants
++;
801 else if (x
== frame_pointer_rtx
802 || x
== arg_pointer_rtx
)
804 reg_equiv_constant
[i
] = x
;
805 num_eliminable_invariants
++;
807 else if (LEGITIMATE_CONSTANT_P (x
))
808 reg_equiv_constant
[i
] = x
;
810 reg_equiv_memory_loc
[i
]
811 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
816 /* If this register is being made equivalent to a MEM
817 and the MEM is not SET_SRC, the equivalencing insn
818 is one with the MEM as a SET_DEST and it occurs later.
819 So don't mark this insn now. */
820 if (GET_CODE (x
) != MEM
821 || rtx_equal_p (SET_SRC (set
), x
))
823 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
828 /* If this insn is setting a MEM from a register equivalent to it,
829 this is the equivalencing insn. */
830 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
831 && GET_CODE (SET_SRC (set
)) == REG
832 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
833 && rtx_equal_p (SET_DEST (set
),
834 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
835 reg_equiv_init
[REGNO (SET_SRC (set
))]
836 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
837 reg_equiv_init
[REGNO (SET_SRC (set
))]);
840 scan_paradoxical_subregs (PATTERN (insn
));
845 num_labels
= max_label_num () - get_first_label_num ();
847 /* Allocate the tables used to store offset information at labels. */
848 /* We used to use alloca here, but the size of what it would try to
849 allocate would occasionally cause it to exceed the stack limit and
850 cause a core dump. */
851 real_known_ptr
= xmalloc (num_labels
);
853 = (int (*)[NUM_ELIMINABLE_REGS
])
854 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
856 offsets_known_at
= real_known_ptr
- get_first_label_num ();
858 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
860 /* Alter each pseudo-reg rtx to contain its hard reg number.
861 Assign stack slots to the pseudos that lack hard regs or equivalents.
862 Do not touch virtual registers. */
864 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
867 /* If we have some registers we think can be eliminated, scan all insns to
868 see if there is an insn that sets one of these registers to something
869 other than itself plus a constant. If so, the register cannot be
870 eliminated. Doing this scan here eliminates an extra pass through the
871 main reload loop in the most common case where register elimination
873 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
874 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
875 || GET_CODE (insn
) == CALL_INSN
)
876 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
878 maybe_fix_stack_asms ();
880 insns_need_reload
= 0;
881 something_needs_elimination
= 0;
883 /* Initialize to -1, which means take the first spill register. */
886 /* Spill any hard regs that we know we can't eliminate. */
887 CLEAR_HARD_REG_SET (used_spill_regs
);
888 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
889 if (! ep
->can_eliminate
)
890 spill_hard_reg (ep
->from
, 1);
892 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
893 if (frame_pointer_needed
)
894 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
896 finish_spills (global
);
898 /* From now on, we may need to generate moves differently. We may also
899 allow modifications of insns which cause them to not be recognized.
900 Any such modifications will be cleaned up during reload itself. */
901 reload_in_progress
= 1;
903 /* This loop scans the entire function each go-round
904 and repeats until one repetition spills no additional hard regs. */
907 int something_changed
;
910 HOST_WIDE_INT starting_frame_size
;
912 /* Round size of stack frame to stack_alignment_needed. This must be done
913 here because the stack size may be a part of the offset computation
914 for register elimination, and there might have been new stack slots
915 created in the last iteration of this loop. */
916 if (cfun
->stack_alignment_needed
)
917 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
919 starting_frame_size
= get_frame_size ();
921 set_initial_elim_offsets ();
922 set_initial_label_offsets ();
924 /* For each pseudo register that has an equivalent location defined,
925 try to eliminate any eliminable registers (such as the frame pointer)
926 assuming initial offsets for the replacement register, which
929 If the resulting location is directly addressable, substitute
930 the MEM we just got directly for the old REG.
932 If it is not addressable but is a constant or the sum of a hard reg
933 and constant, it is probably not addressable because the constant is
934 out of range, in that case record the address; we will generate
935 hairy code to compute the address in a register each time it is
936 needed. Similarly if it is a hard register, but one that is not
937 valid as an address register.
939 If the location is not addressable, but does not have one of the
940 above forms, assign a stack slot. We have to do this to avoid the
941 potential of producing lots of reloads if, e.g., a location involves
942 a pseudo that didn't get a hard register and has an equivalent memory
943 location that also involves a pseudo that didn't get a hard register.
945 Perhaps at some point we will improve reload_when_needed handling
946 so this problem goes away. But that's very hairy. */
948 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
949 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
951 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
953 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
955 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
956 else if (CONSTANT_P (XEXP (x
, 0))
957 || (GET_CODE (XEXP (x
, 0)) == REG
958 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
959 || (GET_CODE (XEXP (x
, 0)) == PLUS
960 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
961 && (REGNO (XEXP (XEXP (x
, 0), 0))
962 < FIRST_PSEUDO_REGISTER
)
963 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
964 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
967 /* Make a new stack slot. Then indicate that something
968 changed so we go back and recompute offsets for
969 eliminable registers because the allocation of memory
970 below might change some offset. reg_equiv_{mem,address}
971 will be set up for this pseudo on the next pass around
973 reg_equiv_memory_loc
[i
] = 0;
974 reg_equiv_init
[i
] = 0;
979 if (caller_save_needed
)
982 /* If we allocated another stack slot, redo elimination bookkeeping. */
983 if (starting_frame_size
!= get_frame_size ())
986 if (caller_save_needed
)
988 save_call_clobbered_regs ();
989 /* That might have allocated new insn_chain structures. */
990 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
993 calculate_needs_all_insns (global
);
995 CLEAR_REG_SET (&spilled_pseudos
);
998 something_changed
= 0;
1000 /* If we allocated any new memory locations, make another pass
1001 since it might have changed elimination offsets. */
1002 if (starting_frame_size
!= get_frame_size ())
1003 something_changed
= 1;
1006 HARD_REG_SET to_spill
;
1007 CLEAR_HARD_REG_SET (to_spill
);
1008 update_eliminables (&to_spill
);
1009 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1010 if (TEST_HARD_REG_BIT (to_spill
, i
))
1012 spill_hard_reg (i
, 1);
1015 /* Regardless of the state of spills, if we previously had
1016 a register that we thought we could eliminate, but no can
1017 not eliminate, we must run another pass.
1019 Consider pseudos which have an entry in reg_equiv_* which
1020 reference an eliminable register. We must make another pass
1021 to update reg_equiv_* so that we do not substitute in the
1022 old value from when we thought the elimination could be
1024 something_changed
= 1;
1028 select_reload_regs ();
1032 if (insns_need_reload
!= 0 || did_spill
)
1033 something_changed
|= finish_spills (global
);
1035 if (! something_changed
)
1038 if (caller_save_needed
)
1039 delete_caller_save_insns ();
1041 obstack_free (&reload_obstack
, reload_firstobj
);
1044 /* If global-alloc was run, notify it of any register eliminations we have
1047 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1048 if (ep
->can_eliminate
)
1049 mark_elimination (ep
->from
, ep
->to
);
1051 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1052 If that insn didn't set the register (i.e., it copied the register to
1053 memory), just delete that insn instead of the equivalencing insn plus
1054 anything now dead. If we call delete_dead_insn on that insn, we may
1055 delete the insn that actually sets the register if the register dies
1056 there and that is incorrect. */
1058 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1060 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1063 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1065 rtx equiv_insn
= XEXP (list
, 0);
1066 if (GET_CODE (equiv_insn
) == NOTE
)
1068 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1069 delete_dead_insn (equiv_insn
);
1072 PUT_CODE (equiv_insn
, NOTE
);
1073 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1074 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1080 /* Use the reload registers where necessary
1081 by generating move instructions to move the must-be-register
1082 values into or out of the reload registers. */
1084 if (insns_need_reload
!= 0 || something_needs_elimination
1085 || something_needs_operands_changed
)
1087 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1089 reload_as_needed (global
);
1091 if (old_frame_size
!= get_frame_size ())
1095 verify_initial_elim_offsets ();
1098 /* If we were able to eliminate the frame pointer, show that it is no
1099 longer live at the start of any basic block. If it ls live by
1100 virtue of being in a pseudo, that pseudo will be marked live
1101 and hence the frame pointer will be known to be live via that
1104 if (! frame_pointer_needed
)
1105 for (i
= 0; i
< n_basic_blocks
; i
++)
1106 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i
)->global_live_at_start
,
1107 HARD_FRAME_POINTER_REGNUM
);
1109 /* Come here (with failure set nonzero) if we can't get enough spill regs
1110 and we decide not to abort about it. */
1113 CLEAR_REG_SET (&spilled_pseudos
);
1114 reload_in_progress
= 0;
1116 /* Now eliminate all pseudo regs by modifying them into
1117 their equivalent memory references.
1118 The REG-rtx's for the pseudos are modified in place,
1119 so all insns that used to refer to them now refer to memory.
1121 For a reg that has a reg_equiv_address, all those insns
1122 were changed by reloading so that no insns refer to it any longer;
1123 but the DECL_RTL of a variable decl may refer to it,
1124 and if so this causes the debugging info to mention the variable. */
1126 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1131 int is_readonly
= 0;
1133 if (reg_equiv_memory_loc
[i
])
1135 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1136 is_scalar
= MEM_SCALAR_P (reg_equiv_memory_loc
[i
]);
1137 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1140 if (reg_equiv_mem
[i
])
1141 addr
= XEXP (reg_equiv_mem
[i
], 0);
1143 if (reg_equiv_address
[i
])
1144 addr
= reg_equiv_address
[i
];
1148 if (reg_renumber
[i
] < 0)
1150 rtx reg
= regno_reg_rtx
[i
];
1151 PUT_CODE (reg
, MEM
);
1152 XEXP (reg
, 0) = addr
;
1153 REG_USERVAR_P (reg
) = 0;
1154 RTX_UNCHANGING_P (reg
) = is_readonly
;
1155 MEM_IN_STRUCT_P (reg
) = in_struct
;
1156 MEM_SCALAR_P (reg
) = is_scalar
;
1157 /* We have no alias information about this newly created
1159 MEM_ALIAS_SET (reg
) = 0;
1161 else if (reg_equiv_mem
[i
])
1162 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1166 /* We must set reload_completed now since the cleanup_subreg_operands call
1167 below will re-recognize each insn and reload may have generated insns
1168 which are only valid during and after reload. */
1169 reload_completed
= 1;
1171 /* Make a pass over all the insns and delete all USEs which we inserted
1172 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1173 notes. Delete all CLOBBER insns that don't refer to the return value
1174 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1175 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1176 and regenerate REG_INC notes that may have been moved around. */
1178 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1183 if (GET_CODE (insn
) == CALL_INSN
)
1184 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn
),
1186 CALL_INSN_FUNCTION_USAGE (insn
));
1188 if ((GET_CODE (PATTERN (insn
)) == USE
1189 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1190 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1191 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != REG
1192 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1194 PUT_CODE (insn
, NOTE
);
1195 NOTE_SOURCE_FILE (insn
) = 0;
1196 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1200 pnote
= ®_NOTES (insn
);
1203 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1204 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1205 || REG_NOTE_KIND (*pnote
) == REG_INC
1206 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1207 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1208 *pnote
= XEXP (*pnote
, 1);
1210 pnote
= &XEXP (*pnote
, 1);
1214 add_auto_inc_notes (insn
, PATTERN (insn
));
1217 /* And simplify (subreg (reg)) if it appears as an operand. */
1218 cleanup_subreg_operands (insn
);
1221 /* If we are doing stack checking, give a warning if this function's
1222 frame size is larger than we expect. */
1223 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1225 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1226 static int verbose_warned
= 0;
1228 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1229 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1230 size
+= UNITS_PER_WORD
;
1232 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1234 warning ("frame size too large for reliable stack checking");
1235 if (! verbose_warned
)
1237 warning ("try reducing the number of local variables");
1243 /* Indicate that we no longer have known memory locations or constants. */
1244 if (reg_equiv_constant
)
1245 free (reg_equiv_constant
);
1246 reg_equiv_constant
= 0;
1247 if (reg_equiv_memory_loc
)
1248 free (reg_equiv_memory_loc
);
1249 reg_equiv_memory_loc
= 0;
1252 free (real_known_ptr
);
1256 free (reg_equiv_mem
);
1257 free (reg_equiv_init
);
1258 free (reg_equiv_address
);
1259 free (reg_max_ref_width
);
1260 free (reg_old_renumber
);
1261 free (pseudo_previous_regs
);
1262 free (pseudo_forbidden_regs
);
1264 CLEAR_HARD_REG_SET (used_spill_regs
);
1265 for (i
= 0; i
< n_spills
; i
++)
1266 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1268 /* Free all the insn_chain structures at once. */
1269 obstack_free (&reload_obstack
, reload_startobj
);
1270 unused_insn_chains
= 0;
1275 /* Yet another special case. Unfortunately, reg-stack forces people to
1276 write incorrect clobbers in asm statements. These clobbers must not
1277 cause the register to appear in bad_spill_regs, otherwise we'll call
1278 fatal_insn later. We clear the corresponding regnos in the live
1279 register sets to avoid this.
1280 The whole thing is rather sick, I'm afraid. */
1283 maybe_fix_stack_asms ()
1286 const char *constraints
[MAX_RECOG_OPERANDS
];
1287 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1288 struct insn_chain
*chain
;
1290 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1293 HARD_REG_SET clobbered
, allowed
;
1296 if (! INSN_P (chain
->insn
)
1297 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1299 pat
= PATTERN (chain
->insn
);
1300 if (GET_CODE (pat
) != PARALLEL
)
1303 CLEAR_HARD_REG_SET (clobbered
);
1304 CLEAR_HARD_REG_SET (allowed
);
1306 /* First, make a mask of all stack regs that are clobbered. */
1307 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1309 rtx t
= XVECEXP (pat
, 0, i
);
1310 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1311 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1314 /* Get the operand values and constraints out of the insn. */
1315 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1316 constraints
, operand_mode
);
1318 /* For every operand, see what registers are allowed. */
1319 for (i
= 0; i
< noperands
; i
++)
1321 const char *p
= constraints
[i
];
1322 /* For every alternative, we compute the class of registers allowed
1323 for reloading in CLS, and merge its contents into the reg set
1325 int cls
= (int) NO_REGS
;
1331 if (c
== '\0' || c
== ',' || c
== '#')
1333 /* End of one alternative - mark the regs in the current
1334 class, and reset the class. */
1335 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1340 } while (c
!= '\0' && c
!= ',');
1348 case '=': case '+': case '*': case '%': case '?': case '!':
1349 case '0': case '1': case '2': case '3': case '4': case 'm':
1350 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1351 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1352 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1357 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1362 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1366 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1371 /* Those of the registers which are clobbered, but allowed by the
1372 constraints, must be usable as reload registers. So clear them
1373 out of the life information. */
1374 AND_HARD_REG_SET (allowed
, clobbered
);
1375 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1376 if (TEST_HARD_REG_BIT (allowed
, i
))
1378 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1379 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1386 /* Copy the global variables n_reloads and rld into the corresponding elts
1389 copy_reloads (chain
)
1390 struct insn_chain
*chain
;
1392 chain
->n_reloads
= n_reloads
;
1394 = (struct reload
*) obstack_alloc (&reload_obstack
,
1395 n_reloads
* sizeof (struct reload
));
1396 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1397 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1400 /* Walk the chain of insns, and determine for each whether it needs reloads
1401 and/or eliminations. Build the corresponding insns_need_reload list, and
1402 set something_needs_elimination as appropriate. */
1404 calculate_needs_all_insns (global
)
1407 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1408 struct insn_chain
*chain
, *next
= 0;
1410 something_needs_elimination
= 0;
1412 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1413 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1415 rtx insn
= chain
->insn
;
1419 /* Clear out the shortcuts. */
1420 chain
->n_reloads
= 0;
1421 chain
->need_elim
= 0;
1422 chain
->need_reload
= 0;
1423 chain
->need_operand_change
= 0;
1425 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1426 include REG_LABEL), we need to see what effects this has on the
1427 known offsets at labels. */
1429 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1430 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1431 set_label_offsets (insn
, insn
, 0);
1435 rtx old_body
= PATTERN (insn
);
1436 int old_code
= INSN_CODE (insn
);
1437 rtx old_notes
= REG_NOTES (insn
);
1438 int did_elimination
= 0;
1439 int operands_changed
= 0;
1440 rtx set
= single_set (insn
);
1442 /* Skip insns that only set an equivalence. */
1443 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1444 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1445 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1448 /* If needed, eliminate any eliminable registers. */
1449 if (num_eliminable
|| num_eliminable_invariants
)
1450 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1452 /* Analyze the instruction. */
1453 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1454 global
, spill_reg_order
);
1456 /* If a no-op set needs more than one reload, this is likely
1457 to be something that needs input address reloads. We
1458 can't get rid of this cleanly later, and it is of no use
1459 anyway, so discard it now.
1460 We only do this when expensive_optimizations is enabled,
1461 since this complements reload inheritance / output
1462 reload deletion, and it can make debugging harder. */
1463 if (flag_expensive_optimizations
&& n_reloads
> 1)
1465 rtx set
= single_set (insn
);
1467 && SET_SRC (set
) == SET_DEST (set
)
1468 && GET_CODE (SET_SRC (set
)) == REG
1469 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1471 PUT_CODE (insn
, NOTE
);
1472 NOTE_SOURCE_FILE (insn
) = 0;
1473 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1474 /* Delete it from the reload chain */
1476 chain
->prev
->next
= next
;
1478 reload_insn_chain
= next
;
1480 next
->prev
= chain
->prev
;
1481 chain
->next
= unused_insn_chains
;
1482 unused_insn_chains
= chain
;
1487 update_eliminable_offsets ();
1489 /* Remember for later shortcuts which insns had any reloads or
1490 register eliminations. */
1491 chain
->need_elim
= did_elimination
;
1492 chain
->need_reload
= n_reloads
> 0;
1493 chain
->need_operand_change
= operands_changed
;
1495 /* Discard any register replacements done. */
1496 if (did_elimination
)
1498 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1499 PATTERN (insn
) = old_body
;
1500 INSN_CODE (insn
) = old_code
;
1501 REG_NOTES (insn
) = old_notes
;
1502 something_needs_elimination
= 1;
1505 something_needs_operands_changed
|= operands_changed
;
1509 copy_reloads (chain
);
1510 *pprev_reload
= chain
;
1511 pprev_reload
= &chain
->next_need_reload
;
1518 /* Comparison function for qsort to decide which of two reloads
1519 should be handled first. *P1 and *P2 are the reload numbers. */
1522 reload_reg_class_lower (r1p
, r2p
)
1526 register int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1529 /* Consider required reloads before optional ones. */
1530 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1534 /* Count all solitary classes before non-solitary ones. */
1535 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1536 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1540 /* Aside from solitaires, consider all multi-reg groups first. */
1541 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1545 /* Consider reloads in order of increasing reg-class number. */
1546 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1550 /* If reloads are equally urgent, sort by reload number,
1551 so that the results of qsort leave nothing to chance. */
1555 /* The cost of spilling each hard reg. */
1556 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1558 /* When spilling multiple hard registers, we use SPILL_COST for the first
1559 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1560 only the first hard reg for a multi-reg pseudo. */
1561 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1563 /* Update the spill cost arrays, considering that pseudo REG is live. */
1569 int n_refs
= REG_N_REFS (reg
);
1570 int r
= reg_renumber
[reg
];
1573 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1574 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1577 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1582 spill_add_cost
[r
] += n_refs
;
1584 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1586 spill_cost
[r
+ nregs
] += n_refs
;
1589 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1590 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1593 order_regs_for_reload (chain
)
1594 struct insn_chain
*chain
;
1597 HARD_REG_SET used_by_pseudos
;
1598 HARD_REG_SET used_by_pseudos2
;
1600 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1602 memset (spill_cost
, 0, sizeof spill_cost
);
1603 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1605 /* Count number of uses of each hard reg by pseudo regs allocated to it
1606 and then order them by decreasing use. First exclude hard registers
1607 that are live in or across this insn. */
1609 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1611 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1612 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1614 /* Now find out which pseudos are allocated to it, and update
1616 CLEAR_REG_SET (&pseudos_counted
);
1618 EXECUTE_IF_SET_IN_REG_SET
1619 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
1623 EXECUTE_IF_SET_IN_REG_SET
1624 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
1628 CLEAR_REG_SET (&pseudos_counted
);
1631 /* Vector of reload-numbers showing the order in which the reloads should
1633 static short reload_order
[MAX_RELOADS
];
1635 /* This is used to keep track of the spill regs used in one insn. */
1636 static HARD_REG_SET used_spill_regs_local
;
1638 /* We decided to spill hard register SPILLED, which has a size of
1639 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1640 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1641 update SPILL_COST/SPILL_ADD_COST. */
1644 count_spilled_pseudo (spilled
, spilled_nregs
, reg
)
1645 int spilled
, spilled_nregs
, reg
;
1647 int r
= reg_renumber
[reg
];
1648 int nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1650 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1651 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1654 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1656 spill_add_cost
[r
] -= REG_N_REFS (reg
);
1658 spill_cost
[r
+ nregs
] -= REG_N_REFS (reg
);
1661 /* Find reload register to use for reload number ORDER. */
1664 find_reg (chain
, order
)
1665 struct insn_chain
*chain
;
1668 int rnum
= reload_order
[order
];
1669 struct reload
*rl
= rld
+ rnum
;
1670 int best_cost
= INT_MAX
;
1674 HARD_REG_SET not_usable
;
1675 HARD_REG_SET used_by_other_reload
;
1677 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1678 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1679 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1681 CLEAR_HARD_REG_SET (used_by_other_reload
);
1682 for (k
= 0; k
< order
; k
++)
1684 int other
= reload_order
[k
];
1686 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1687 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1688 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1691 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1693 unsigned int regno
= i
;
1695 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1696 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1697 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1699 int this_cost
= spill_cost
[regno
];
1701 unsigned int this_nregs
= HARD_REGNO_NREGS (regno
, rl
->mode
);
1703 for (j
= 1; j
< this_nregs
; j
++)
1705 this_cost
+= spill_add_cost
[regno
+ j
];
1706 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1707 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1712 if (rl
->in
&& GET_CODE (rl
->in
) == REG
&& REGNO (rl
->in
) == regno
)
1714 if (rl
->out
&& GET_CODE (rl
->out
) == REG
&& REGNO (rl
->out
) == regno
)
1716 if (this_cost
< best_cost
1717 /* Among registers with equal cost, prefer caller-saved ones, or
1718 use REG_ALLOC_ORDER if it is defined. */
1719 || (this_cost
== best_cost
1720 #ifdef REG_ALLOC_ORDER
1721 && (inv_reg_alloc_order
[regno
]
1722 < inv_reg_alloc_order
[best_reg
])
1724 && call_used_regs
[regno
]
1725 && ! call_used_regs
[best_reg
]
1730 best_cost
= this_cost
;
1738 fprintf (rtl_dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1740 rl
->nregs
= HARD_REGNO_NREGS (best_reg
, rl
->mode
);
1741 rl
->regno
= best_reg
;
1743 EXECUTE_IF_SET_IN_REG_SET
1744 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
,
1746 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1749 EXECUTE_IF_SET_IN_REG_SET
1750 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
,
1752 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1755 for (i
= 0; i
< rl
->nregs
; i
++)
1757 if (spill_cost
[best_reg
+ i
] != 0
1758 || spill_add_cost
[best_reg
+ i
] != 0)
1760 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1765 /* Find more reload regs to satisfy the remaining need of an insn, which
1767 Do it by ascending class number, since otherwise a reg
1768 might be spilled for a big class and might fail to count
1769 for a smaller class even though it belongs to that class. */
1772 find_reload_regs (chain
)
1773 struct insn_chain
*chain
;
1777 /* In order to be certain of getting the registers we need,
1778 we must sort the reloads into order of increasing register class.
1779 Then our grabbing of reload registers will parallel the process
1780 that provided the reload registers. */
1781 for (i
= 0; i
< chain
->n_reloads
; i
++)
1783 /* Show whether this reload already has a hard reg. */
1784 if (chain
->rld
[i
].reg_rtx
)
1786 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1787 chain
->rld
[i
].regno
= regno
;
1789 = HARD_REGNO_NREGS (regno
, GET_MODE (chain
->rld
[i
].reg_rtx
));
1792 chain
->rld
[i
].regno
= -1;
1793 reload_order
[i
] = i
;
1796 n_reloads
= chain
->n_reloads
;
1797 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1799 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1802 fprintf (rtl_dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1804 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1806 /* Compute the order of preference for hard registers to spill. */
1808 order_regs_for_reload (chain
);
1810 for (i
= 0; i
< n_reloads
; i
++)
1812 int r
= reload_order
[i
];
1814 /* Ignore reloads that got marked inoperative. */
1815 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1816 && ! rld
[r
].optional
1817 && rld
[r
].regno
== -1)
1818 if (! find_reg (chain
, i
))
1820 spill_failure (chain
->insn
, rld
[r
].class);
1826 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1827 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1829 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1833 select_reload_regs ()
1835 struct insn_chain
*chain
;
1837 /* Try to satisfy the needs for each insn. */
1838 for (chain
= insns_need_reload
; chain
!= 0;
1839 chain
= chain
->next_need_reload
)
1840 find_reload_regs (chain
);
1843 /* Delete all insns that were inserted by emit_caller_save_insns during
1846 delete_caller_save_insns ()
1848 struct insn_chain
*c
= reload_insn_chain
;
1852 while (c
!= 0 && c
->is_caller_save_insn
)
1854 struct insn_chain
*next
= c
->next
;
1857 if (insn
== BLOCK_HEAD (c
->block
))
1858 BLOCK_HEAD (c
->block
) = NEXT_INSN (insn
);
1859 if (insn
== BLOCK_END (c
->block
))
1860 BLOCK_END (c
->block
) = PREV_INSN (insn
);
1861 if (c
== reload_insn_chain
)
1862 reload_insn_chain
= next
;
1864 if (NEXT_INSN (insn
) != 0)
1865 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1866 if (PREV_INSN (insn
) != 0)
1867 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1870 next
->prev
= c
->prev
;
1872 c
->prev
->next
= next
;
1873 c
->next
= unused_insn_chains
;
1874 unused_insn_chains
= c
;
1882 /* Handle the failure to find a register to spill.
1883 INSN should be one of the insns which needed this particular spill reg. */
1886 spill_failure (insn
, class)
1888 enum reg_class
class;
1890 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1891 if (asm_noperands (PATTERN (insn
)) >= 0)
1892 error_for_asm (insn
, "Can't find a register in class `%s' while reloading `asm'.",
1893 reg_class_names
[class]);
1896 error ("Unable to find a register to spill in class `%s'.",
1897 reg_class_names
[class]);
1898 fatal_insn ("This is the insn:", insn
);
1902 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1903 data that is dead in INSN. */
1906 delete_dead_insn (insn
)
1909 rtx prev
= prev_real_insn (insn
);
1912 /* If the previous insn sets a register that dies in our insn, delete it
1914 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1915 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
1916 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1917 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1918 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1919 delete_dead_insn (prev
);
1921 PUT_CODE (insn
, NOTE
);
1922 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1923 NOTE_SOURCE_FILE (insn
) = 0;
1926 /* Modify the home of pseudo-reg I.
1927 The new home is present in reg_renumber[I].
1929 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1930 or it may be -1, meaning there is none or it is not relevant.
1931 This is used so that all pseudos spilled from a given hard reg
1932 can share one stack slot. */
1935 alter_reg (i
, from_reg
)
1939 /* When outputting an inline function, this can happen
1940 for a reg that isn't actually used. */
1941 if (regno_reg_rtx
[i
] == 0)
1944 /* If the reg got changed to a MEM at rtl-generation time,
1946 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
1949 /* Modify the reg-rtx to contain the new hard reg
1950 number or else to contain its pseudo reg number. */
1951 REGNO (regno_reg_rtx
[i
])
1952 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1954 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1955 allocate a stack slot for it. */
1957 if (reg_renumber
[i
] < 0
1958 && REG_N_REFS (i
) > 0
1959 && reg_equiv_constant
[i
] == 0
1960 && reg_equiv_memory_loc
[i
] == 0)
1963 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1964 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1967 /* Each pseudo reg has an inherent size which comes from its own mode,
1968 and a total size which provides room for paradoxical subregs
1969 which refer to the pseudo reg in wider modes.
1971 We can use a slot already allocated if it provides both
1972 enough inherent space and enough total space.
1973 Otherwise, we allocate a new slot, making sure that it has no less
1974 inherent space, and no less total space, then the previous slot. */
1977 /* No known place to spill from => no slot to reuse. */
1978 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1979 inherent_size
== total_size
? 0 : -1);
1980 if (BYTES_BIG_ENDIAN
)
1981 /* Cancel the big-endian correction done in assign_stack_local.
1982 Get the address of the beginning of the slot.
1983 This is so we can do a big-endian correction unconditionally
1985 adjust
= inherent_size
- total_size
;
1987 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
1989 /* Nothing can alias this slot except this pseudo. */
1990 MEM_ALIAS_SET (x
) = new_alias_set ();
1993 /* Reuse a stack slot if possible. */
1994 else if (spill_stack_slot
[from_reg
] != 0
1995 && spill_stack_slot_width
[from_reg
] >= total_size
1996 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1998 x
= spill_stack_slot
[from_reg
];
2000 /* Allocate a bigger slot. */
2003 /* Compute maximum size needed, both for inherent size
2004 and for total size. */
2005 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2008 if (spill_stack_slot
[from_reg
])
2010 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2012 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2013 if (spill_stack_slot_width
[from_reg
] > total_size
)
2014 total_size
= spill_stack_slot_width
[from_reg
];
2017 /* Make a slot with that size. */
2018 x
= assign_stack_local (mode
, total_size
,
2019 inherent_size
== total_size
? 0 : -1);
2022 /* All pseudos mapped to this slot can alias each other. */
2023 if (spill_stack_slot
[from_reg
])
2024 MEM_ALIAS_SET (x
) = MEM_ALIAS_SET (spill_stack_slot
[from_reg
]);
2026 MEM_ALIAS_SET (x
) = new_alias_set ();
2028 if (BYTES_BIG_ENDIAN
)
2030 /* Cancel the big-endian correction done in assign_stack_local.
2031 Get the address of the beginning of the slot.
2032 This is so we can do a big-endian correction unconditionally
2034 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2036 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2039 plus_constant (XEXP (x
, 0), adjust
));
2042 spill_stack_slot
[from_reg
] = stack_slot
;
2043 spill_stack_slot_width
[from_reg
] = total_size
;
2046 /* On a big endian machine, the "address" of the slot
2047 is the address of the low part that fits its inherent mode. */
2048 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2049 adjust
+= (total_size
- inherent_size
);
2051 /* If we have any adjustment to make, or if the stack slot is the
2052 wrong mode, make a new stack slot. */
2053 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2055 rtx
new = gen_rtx_MEM (GET_MODE (regno_reg_rtx
[i
]),
2056 plus_constant (XEXP (x
, 0), adjust
));
2058 MEM_COPY_ATTRIBUTES (new, x
);
2062 /* Save the stack slot for later. */
2063 reg_equiv_memory_loc
[i
] = x
;
2067 /* Mark the slots in regs_ever_live for the hard regs
2068 used by pseudo-reg number REGNO. */
2071 mark_home_live (regno
)
2074 register int i
, lim
;
2076 i
= reg_renumber
[regno
];
2079 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2081 regs_ever_live
[i
++] = 1;
2084 /* This function handles the tracking of elimination offsets around branches.
2086 X is a piece of RTL being scanned.
2088 INSN is the insn that it came from, if any.
2090 INITIAL_P is non-zero if we are to set the offset to be the initial
2091 offset and zero if we are setting the offset of the label to be the
2095 set_label_offsets (x
, insn
, initial_p
)
2100 enum rtx_code code
= GET_CODE (x
);
2103 struct elim_table
*p
;
2108 if (LABEL_REF_NONLOCAL_P (x
))
2113 /* ... fall through ... */
2116 /* If we know nothing about this label, set the desired offsets. Note
2117 that this sets the offset at a label to be the offset before a label
2118 if we don't know anything about the label. This is not correct for
2119 the label after a BARRIER, but is the best guess we can make. If
2120 we guessed wrong, we will suppress an elimination that might have
2121 been possible had we been able to guess correctly. */
2123 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2125 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2126 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2127 = (initial_p
? reg_eliminate
[i
].initial_offset
2128 : reg_eliminate
[i
].offset
);
2129 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2132 /* Otherwise, if this is the definition of a label and it is
2133 preceded by a BARRIER, set our offsets to the known offset of
2137 && (tem
= prev_nonnote_insn (insn
)) != 0
2138 && GET_CODE (tem
) == BARRIER
)
2139 set_offsets_for_label (insn
);
2141 /* If neither of the above cases is true, compare each offset
2142 with those previously recorded and suppress any eliminations
2143 where the offsets disagree. */
2145 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2146 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2147 != (initial_p
? reg_eliminate
[i
].initial_offset
2148 : reg_eliminate
[i
].offset
))
2149 reg_eliminate
[i
].can_eliminate
= 0;
2154 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2156 /* ... fall through ... */
2160 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2161 and hence must have all eliminations at their initial offsets. */
2162 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2163 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2164 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2170 /* Each of the labels in the parallel or address vector must be
2171 at their initial offsets. We want the first field for PARALLEL
2172 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2174 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2175 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2180 /* We only care about setting PC. If the source is not RETURN,
2181 IF_THEN_ELSE, or a label, disable any eliminations not at
2182 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2183 isn't one of those possibilities. For branches to a label,
2184 call ourselves recursively.
2186 Note that this can disable elimination unnecessarily when we have
2187 a non-local goto since it will look like a non-constant jump to
2188 someplace in the current function. This isn't a significant
2189 problem since such jumps will normally be when all elimination
2190 pairs are back to their initial offsets. */
2192 if (SET_DEST (x
) != pc_rtx
)
2195 switch (GET_CODE (SET_SRC (x
)))
2202 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2206 tem
= XEXP (SET_SRC (x
), 1);
2207 if (GET_CODE (tem
) == LABEL_REF
)
2208 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2209 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2212 tem
= XEXP (SET_SRC (x
), 2);
2213 if (GET_CODE (tem
) == LABEL_REF
)
2214 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2215 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2223 /* If we reach here, all eliminations must be at their initial
2224 offset because we are doing a jump to a variable address. */
2225 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2226 if (p
->offset
!= p
->initial_offset
)
2227 p
->can_eliminate
= 0;
2235 /* Scan X and replace any eliminable registers (such as fp) with a
2236 replacement (such as sp), plus an offset.
2238 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2239 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2240 MEM, we are allowed to replace a sum of a register and the constant zero
2241 with the register, which we cannot do outside a MEM. In addition, we need
2242 to record the fact that a register is referenced outside a MEM.
2244 If INSN is an insn, it is the insn containing X. If we replace a REG
2245 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2246 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2247 the REG is being modified.
2249 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2250 That's used when we eliminate in expressions stored in notes.
2251 This means, do not set ref_outside_mem even if the reference
2254 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2255 replacements done assuming all offsets are at their initial values. If
2256 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2257 encounter, return the actual location so that find_reloads will do
2258 the proper thing. */
2261 eliminate_regs (x
, mem_mode
, insn
)
2263 enum machine_mode mem_mode
;
2266 enum rtx_code code
= GET_CODE (x
);
2267 struct elim_table
*ep
;
2274 if (! current_function_decl
)
2293 /* This is only for the benefit of the debugging backends, which call
2294 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2295 removed after CSE. */
2296 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2297 if (GET_CODE (new) == MEM
)
2298 return XEXP (new, 0);
2304 /* First handle the case where we encounter a bare register that
2305 is eliminable. Replace it with a PLUS. */
2306 if (regno
< FIRST_PSEUDO_REGISTER
)
2308 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2310 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2311 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2314 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2315 && reg_equiv_constant
[regno
]
2316 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2317 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2321 /* You might think handling MINUS in a manner similar to PLUS is a
2322 good idea. It is not. It has been tried multiple times and every
2323 time the change has had to have been reverted.
2325 Other parts of reload know a PLUS is special (gen_reload for example)
2326 and require special code to handle code a reloaded PLUS operand.
2328 Also consider backends where the flags register is clobbered by a
2329 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2330 lea instruction comes to mind). If we try to reload a MINUS, we
2331 may kill the flags register that was holding a useful value.
2333 So, please before trying to handle MINUS, consider reload as a
2334 whole instead of this little section as well as the backend issues. */
2336 /* If this is the sum of an eliminable register and a constant, rework
2338 if (GET_CODE (XEXP (x
, 0)) == REG
2339 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2340 && CONSTANT_P (XEXP (x
, 1)))
2342 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2344 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2346 /* The only time we want to replace a PLUS with a REG (this
2347 occurs when the constant operand of the PLUS is the negative
2348 of the offset) is when we are inside a MEM. We won't want
2349 to do so at other times because that would change the
2350 structure of the insn in a way that reload can't handle.
2351 We special-case the commonest situation in
2352 eliminate_regs_in_insn, so just replace a PLUS with a
2353 PLUS here, unless inside a MEM. */
2354 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2355 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2358 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2359 plus_constant (XEXP (x
, 1),
2360 ep
->previous_offset
));
2363 /* If the register is not eliminable, we are done since the other
2364 operand is a constant. */
2368 /* If this is part of an address, we want to bring any constant to the
2369 outermost PLUS. We will do this by doing register replacement in
2370 our operands and seeing if a constant shows up in one of them.
2372 Note that there is no risk of modifying the structure of the insn,
2373 since we only get called for its operands, thus we are either
2374 modifying the address inside a MEM, or something like an address
2375 operand of a load-address insn. */
2378 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2379 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2381 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2383 /* If one side is a PLUS and the other side is a pseudo that
2384 didn't get a hard register but has a reg_equiv_constant,
2385 we must replace the constant here since it may no longer
2386 be in the position of any operand. */
2387 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2388 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2389 && reg_renumber
[REGNO (new1
)] < 0
2390 && reg_equiv_constant
!= 0
2391 && reg_equiv_constant
[REGNO (new1
)] != 0)
2392 new1
= reg_equiv_constant
[REGNO (new1
)];
2393 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2394 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2395 && reg_renumber
[REGNO (new0
)] < 0
2396 && reg_equiv_constant
[REGNO (new0
)] != 0)
2397 new0
= reg_equiv_constant
[REGNO (new0
)];
2399 new = form_sum (new0
, new1
);
2401 /* As above, if we are not inside a MEM we do not want to
2402 turn a PLUS into something else. We might try to do so here
2403 for an addition of 0 if we aren't optimizing. */
2404 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2405 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2413 /* If this is the product of an eliminable register and a
2414 constant, apply the distribute law and move the constant out
2415 so that we have (plus (mult ..) ..). This is needed in order
2416 to keep load-address insns valid. This case is pathological.
2417 We ignore the possibility of overflow here. */
2418 if (GET_CODE (XEXP (x
, 0)) == REG
2419 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2420 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2421 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2423 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2426 /* Refs inside notes don't count for this purpose. */
2427 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2428 || GET_CODE (insn
) == INSN_LIST
)))
2429 ep
->ref_outside_mem
= 1;
2432 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2433 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2436 /* ... fall through ... */
2440 /* See comments before PLUS about handling MINUS. */
2442 case DIV
: case UDIV
:
2443 case MOD
: case UMOD
:
2444 case AND
: case IOR
: case XOR
:
2445 case ROTATERT
: case ROTATE
:
2446 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2448 case GE
: case GT
: case GEU
: case GTU
:
2449 case LE
: case LT
: case LEU
: case LTU
:
2451 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2453 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2455 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2456 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2461 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2464 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2465 if (new != XEXP (x
, 0))
2467 /* If this is a REG_DEAD note, it is not valid anymore.
2468 Using the eliminated version could result in creating a
2469 REG_DEAD note for the stack or frame pointer. */
2470 if (GET_MODE (x
) == REG_DEAD
)
2472 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2475 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2479 /* ... fall through ... */
2482 /* Now do eliminations in the rest of the chain. If this was
2483 an EXPR_LIST, this might result in allocating more memory than is
2484 strictly needed, but it simplifies the code. */
2487 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2488 if (new != XEXP (x
, 1))
2489 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2497 case STRICT_LOW_PART
:
2499 case SIGN_EXTEND
: case ZERO_EXTEND
:
2500 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2501 case FLOAT
: case FIX
:
2502 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2506 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2507 if (new != XEXP (x
, 0))
2508 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2512 /* Similar to above processing, but preserve SUBREG_WORD.
2513 Convert (subreg (mem)) to (mem) if not paradoxical.
2514 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2515 pseudo didn't get a hard reg, we must replace this with the
2516 eliminated version of the memory location because push_reloads
2517 may do the replacement in certain circumstances. */
2518 if (GET_CODE (SUBREG_REG (x
)) == REG
2519 && (GET_MODE_SIZE (GET_MODE (x
))
2520 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2521 && reg_equiv_memory_loc
!= 0
2522 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2524 new = SUBREG_REG (x
);
2527 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2529 if (new != XEXP (x
, 0))
2531 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2532 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2534 if (GET_CODE (new) == MEM
2535 && ((x_size
< new_size
2536 #ifdef WORD_REGISTER_OPERATIONS
2537 /* On these machines, combine can create rtl of the form
2538 (set (subreg:m1 (reg:m2 R) 0) ...)
2539 where m1 < m2, and expects something interesting to
2540 happen to the entire word. Moreover, it will use the
2541 (reg:m2 R) later, expecting all bits to be preserved.
2542 So if the number of words is the same, preserve the
2543 subreg so that push_reloads can see it. */
2544 && ! ((x_size
-1)/UNITS_PER_WORD
== (new_size
-1)/UNITS_PER_WORD
)
2547 || (x_size
== new_size
))
2550 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
2551 enum machine_mode mode
= GET_MODE (x
);
2553 if (BYTES_BIG_ENDIAN
)
2554 offset
+= (MIN (UNITS_PER_WORD
,
2555 GET_MODE_SIZE (GET_MODE (new)))
2556 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
2558 PUT_MODE (new, mode
);
2559 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
2563 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_WORD (x
));
2569 /* This is only for the benefit of the debugging backends, which call
2570 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2571 removed after CSE. */
2572 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2573 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
2575 /* Our only special processing is to pass the mode of the MEM to our
2576 recursive call and copy the flags. While we are here, handle this
2577 case more efficiently. */
2578 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), insn
);
2579 if (new != XEXP (x
, 0))
2581 new = gen_rtx_MEM (GET_MODE (x
), new);
2582 MEM_COPY_ATTRIBUTES (new, x
);
2589 /* Handle insn_list USE that a call to a pure function may generate. */
2590 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2591 if (new != XEXP (x
, 0))
2592 return gen_rtx_USE (GET_MODE (x
), new);
2604 /* Process each of our operands recursively. If any have changed, make a
2606 fmt
= GET_RTX_FORMAT (code
);
2607 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2611 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
2612 if (new != XEXP (x
, i
) && ! copied
)
2614 rtx new_x
= rtx_alloc (code
);
2616 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2617 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
2623 else if (*fmt
== 'E')
2626 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2628 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
2629 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2631 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2635 rtx new_x
= rtx_alloc (code
);
2637 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2638 + (sizeof (new_x
->fld
[0])
2639 * GET_RTX_LENGTH (code
))));
2643 XVEC (x
, i
) = new_v
;
2646 XVECEXP (x
, i
, j
) = new;
2654 /* Scan rtx X for modifications of elimination target registers. Update
2655 the table of eliminables to reflect the changed state. MEM_MODE is
2656 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2659 elimination_effects (x
, mem_mode
)
2661 enum machine_mode mem_mode
;
2664 enum rtx_code code
= GET_CODE (x
);
2665 struct elim_table
*ep
;
2691 /* First handle the case where we encounter a bare register that
2692 is eliminable. Replace it with a PLUS. */
2693 if (regno
< FIRST_PSEUDO_REGISTER
)
2695 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2697 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2700 ep
->ref_outside_mem
= 1;
2705 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2706 && reg_equiv_constant
[regno
]
2707 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2708 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2717 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2718 if (ep
->to_rtx
== XEXP (x
, 0))
2720 int size
= GET_MODE_SIZE (mem_mode
);
2722 /* If more bytes than MEM_MODE are pushed, account for them. */
2723 #ifdef PUSH_ROUNDING
2724 if (ep
->to_rtx
== stack_pointer_rtx
)
2725 size
= PUSH_ROUNDING (size
);
2727 if (code
== PRE_DEC
|| code
== POST_DEC
)
2729 else if (code
== PRE_INC
|| code
== POST_INC
)
2731 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2732 && GET_CODE (XEXP (x
, 1)) == PLUS
2733 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2734 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2735 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2738 /* These two aren't unary operators. */
2739 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2742 /* Fall through to generic unary operation case. */
2743 case STRICT_LOW_PART
:
2745 case SIGN_EXTEND
: case ZERO_EXTEND
:
2746 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2747 case FLOAT
: case FIX
:
2748 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2752 elimination_effects (XEXP (x
, 0), mem_mode
);
2756 if (GET_CODE (SUBREG_REG (x
)) == REG
2757 && (GET_MODE_SIZE (GET_MODE (x
))
2758 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2759 && reg_equiv_memory_loc
!= 0
2760 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2763 elimination_effects (SUBREG_REG (x
), mem_mode
);
2767 /* If using a register that is the source of an eliminate we still
2768 think can be performed, note it cannot be performed since we don't
2769 know how this register is used. */
2770 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2771 if (ep
->from_rtx
== XEXP (x
, 0))
2772 ep
->can_eliminate
= 0;
2774 elimination_effects (XEXP (x
, 0), mem_mode
);
2778 /* If clobbering a register that is the replacement register for an
2779 elimination we still think can be performed, note that it cannot
2780 be performed. Otherwise, we need not be concerned about it. */
2781 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2782 if (ep
->to_rtx
== XEXP (x
, 0))
2783 ep
->can_eliminate
= 0;
2785 elimination_effects (XEXP (x
, 0), mem_mode
);
2789 /* Check for setting a register that we know about. */
2790 if (GET_CODE (SET_DEST (x
)) == REG
)
2792 /* See if this is setting the replacement register for an
2795 If DEST is the hard frame pointer, we do nothing because we
2796 assume that all assignments to the frame pointer are for
2797 non-local gotos and are being done at a time when they are valid
2798 and do not disturb anything else. Some machines want to
2799 eliminate a fake argument pointer (or even a fake frame pointer)
2800 with either the real frame or the stack pointer. Assignments to
2801 the hard frame pointer must not prevent this elimination. */
2803 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2805 if (ep
->to_rtx
== SET_DEST (x
)
2806 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2808 /* If it is being incremented, adjust the offset. Otherwise,
2809 this elimination can't be done. */
2810 rtx src
= SET_SRC (x
);
2812 if (GET_CODE (src
) == PLUS
2813 && XEXP (src
, 0) == SET_DEST (x
)
2814 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2815 ep
->offset
-= INTVAL (XEXP (src
, 1));
2817 ep
->can_eliminate
= 0;
2821 elimination_effects (SET_DEST (x
), 0);
2822 elimination_effects (SET_SRC (x
), 0);
2826 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2829 /* Our only special processing is to pass the mode of the MEM to our
2831 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2838 fmt
= GET_RTX_FORMAT (code
);
2839 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2842 elimination_effects (XEXP (x
, i
), mem_mode
);
2843 else if (*fmt
== 'E')
2844 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2845 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2849 /* Descend through rtx X and verify that no references to eliminable registers
2850 remain. If any do remain, mark the involved register as not
2854 check_eliminable_occurrences (x
)
2864 code
= GET_CODE (x
);
2866 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2868 struct elim_table
*ep
;
2870 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2871 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2872 ep
->can_eliminate
= 0;
2876 fmt
= GET_RTX_FORMAT (code
);
2877 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2880 check_eliminable_occurrences (XEXP (x
, i
));
2881 else if (*fmt
== 'E')
2884 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2885 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2890 /* Scan INSN and eliminate all eliminable registers in it.
2892 If REPLACE is nonzero, do the replacement destructively. Also
2893 delete the insn as dead it if it is setting an eliminable register.
2895 If REPLACE is zero, do all our allocations in reload_obstack.
2897 If no eliminations were done and this insn doesn't require any elimination
2898 processing (these are not identical conditions: it might be updating sp,
2899 but not referencing fp; this needs to be seen during reload_as_needed so
2900 that the offset between fp and sp can be taken into consideration), zero
2901 is returned. Otherwise, 1 is returned. */
2904 eliminate_regs_in_insn (insn
, replace
)
2908 int icode
= recog_memoized (insn
);
2909 rtx old_body
= PATTERN (insn
);
2910 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2911 rtx old_set
= single_set (insn
);
2915 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2916 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2917 struct elim_table
*ep
;
2919 if (! insn_is_asm
&& icode
< 0)
2921 if (GET_CODE (PATTERN (insn
)) == USE
2922 || GET_CODE (PATTERN (insn
)) == CLOBBER
2923 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2924 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2925 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
)
2930 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
2931 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2933 /* Check for setting an eliminable register. */
2934 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2935 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2937 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2938 /* If this is setting the frame pointer register to the
2939 hardware frame pointer register and this is an elimination
2940 that will be done (tested above), this insn is really
2941 adjusting the frame pointer downward to compensate for
2942 the adjustment done before a nonlocal goto. */
2943 if (ep
->from
== FRAME_POINTER_REGNUM
2944 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2946 rtx src
= SET_SRC (old_set
);
2947 int offset
= 0, ok
= 0;
2948 rtx prev_insn
, prev_set
;
2950 if (src
== ep
->to_rtx
)
2952 else if (GET_CODE (src
) == PLUS
2953 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2954 && XEXP (src
, 1) == ep
->to_rtx
)
2955 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2956 else if (GET_CODE (src
) == PLUS
2957 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2958 && XEXP (src
, 0) == ep
->to_rtx
)
2959 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2960 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
2961 && (prev_set
= single_set (prev_insn
)) != 0
2962 && rtx_equal_p (SET_DEST (prev_set
), src
))
2964 src
= SET_SRC (prev_set
);
2965 if (src
== ep
->to_rtx
)
2967 else if (GET_CODE (src
) == PLUS
2968 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2969 && XEXP (src
, 1) == ep
->to_rtx
)
2970 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2971 else if (GET_CODE (src
) == PLUS
2972 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2973 && XEXP (src
, 0) == ep
->to_rtx
)
2974 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2982 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2984 /* First see if this insn remains valid when we
2985 make the change. If not, keep the INSN_CODE
2986 the same and let reload fit it up. */
2987 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2988 validate_change (insn
, &SET_DEST (old_set
),
2990 if (! apply_change_group ())
2992 SET_SRC (old_set
) = src
;
2993 SET_DEST (old_set
) = ep
->to_rtx
;
3003 /* In this case this insn isn't serving a useful purpose. We
3004 will delete it in reload_as_needed once we know that this
3005 elimination is, in fact, being done.
3007 If REPLACE isn't set, we can't delete this insn, but needn't
3008 process it since it won't be used unless something changes. */
3011 delete_dead_insn (insn
);
3019 /* We allow one special case which happens to work on all machines we
3020 currently support: a single set with the source being a PLUS of an
3021 eliminable register and a constant. */
3023 && GET_CODE (SET_DEST (old_set
)) == REG
3024 && GET_CODE (SET_SRC (old_set
)) == PLUS
3025 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3026 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
3027 && REGNO (XEXP (SET_SRC (old_set
), 0)) < FIRST_PSEUDO_REGISTER
)
3029 rtx reg
= XEXP (SET_SRC (old_set
), 0);
3030 int offset
= INTVAL (XEXP (SET_SRC (old_set
), 1));
3032 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3033 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3035 offset
+= ep
->offset
;
3040 /* We assume here that if we need a PARALLEL with
3041 CLOBBERs for this assignment, we can do with the
3042 MATCH_SCRATCHes that add_clobbers allocates.
3043 There's not much we can do if that doesn't work. */
3044 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3048 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3051 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3053 vec
->elem
[0] = PATTERN (insn
);
3054 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3055 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3057 if (INSN_CODE (insn
) < 0)
3062 new_body
= old_body
;
3065 new_body
= copy_insn (old_body
);
3066 if (REG_NOTES (insn
))
3067 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3069 PATTERN (insn
) = new_body
;
3070 old_set
= single_set (insn
);
3072 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
3073 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3076 /* This can't have an effect on elimination offsets, so skip right
3082 /* Determine the effects of this insn on elimination offsets. */
3083 elimination_effects (old_body
, 0);
3085 /* Eliminate all eliminable registers occurring in operands that
3086 can be handled by reload. */
3087 extract_insn (insn
);
3089 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3091 orig_operand
[i
] = recog_data
.operand
[i
];
3092 substed_operand
[i
] = recog_data
.operand
[i
];
3094 /* For an asm statement, every operand is eliminable. */
3095 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3097 /* Check for setting a register that we know about. */
3098 if (recog_data
.operand_type
[i
] != OP_IN
3099 && GET_CODE (orig_operand
[i
]) == REG
)
3101 /* If we are assigning to a register that can be eliminated, it
3102 must be as part of a PARALLEL, since the code above handles
3103 single SETs. We must indicate that we can no longer
3104 eliminate this reg. */
3105 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3107 if (ep
->from_rtx
== orig_operand
[i
] && ep
->can_eliminate
)
3108 ep
->can_eliminate
= 0;
3111 substed_operand
[i
] = eliminate_regs (recog_data
.operand
[i
], 0,
3112 replace
? insn
: NULL_RTX
);
3113 if (substed_operand
[i
] != orig_operand
[i
])
3114 val
= any_changes
= 1;
3115 /* Terminate the search in check_eliminable_occurrences at
3117 *recog_data
.operand_loc
[i
] = 0;
3119 /* If an output operand changed from a REG to a MEM and INSN is an
3120 insn, write a CLOBBER insn. */
3121 if (recog_data
.operand_type
[i
] != OP_IN
3122 && GET_CODE (orig_operand
[i
]) == REG
3123 && GET_CODE (substed_operand
[i
]) == MEM
3125 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3130 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3131 *recog_data
.dup_loc
[i
]
3132 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3134 /* If any eliminable remain, they aren't eliminable anymore. */
3135 check_eliminable_occurrences (old_body
);
3137 /* Substitute the operands; the new values are in the substed_operand
3139 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3140 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3141 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3142 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3144 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3145 re-recognize the insn. We do this in case we had a simple addition
3146 but now can do this as a load-address. This saves an insn in this
3148 If re-recognition fails, the old insn code number will still be used,
3149 and some register operands may have changed into PLUS expressions.
3150 These will be handled by find_reloads by loading them into a register
3155 /* If we aren't replacing things permanently and we changed something,
3156 make another copy to ensure that all the RTL is new. Otherwise
3157 things can go wrong if find_reload swaps commutative operands
3158 and one is inside RTL that has been copied while the other is not. */
3159 new_body
= old_body
;
3162 new_body
= copy_insn (old_body
);
3163 if (REG_NOTES (insn
))
3164 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3166 PATTERN (insn
) = new_body
;
3168 /* If we had a move insn but now we don't, rerecognize it. This will
3169 cause spurious re-recognition if the old move had a PARALLEL since
3170 the new one still will, but we can't call single_set without
3171 having put NEW_BODY into the insn and the re-recognition won't
3172 hurt in this rare case. */
3173 /* ??? Why this huge if statement - why don't we just rerecognize the
3177 && ((GET_CODE (SET_SRC (old_set
)) == REG
3178 && (GET_CODE (new_body
) != SET
3179 || GET_CODE (SET_SRC (new_body
)) != REG
))
3180 /* If this was a load from or store to memory, compare
3181 the MEM in recog_data.operand to the one in the insn.
3182 If they are not equal, then rerecognize the insn. */
3184 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3185 && SET_SRC (old_set
) != recog_data
.operand
[1])
3186 || (GET_CODE (SET_DEST (old_set
)) == MEM
3187 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3188 /* If this was an add insn before, rerecognize. */
3189 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3191 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3193 INSN_CODE (insn
) = icode
;
3197 /* Restore the old body. If there were any changes to it, we made a copy
3198 of it while the changes were still in place, so we'll correctly return
3199 a modified insn below. */
3202 /* Restore the old body. */
3203 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3204 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3205 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3206 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3209 /* Update all elimination pairs to reflect the status after the current
3210 insn. The changes we make were determined by the earlier call to
3211 elimination_effects.
3213 We also detect a cases where register elimination cannot be done,
3214 namely, if a register would be both changed and referenced outside a MEM
3215 in the resulting insn since such an insn is often undefined and, even if
3216 not, we cannot know what meaning will be given to it. Note that it is
3217 valid to have a register used in an address in an insn that changes it
3218 (presumably with a pre- or post-increment or decrement).
3220 If anything changes, return nonzero. */
3222 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3224 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3225 ep
->can_eliminate
= 0;
3227 ep
->ref_outside_mem
= 0;
3229 if (ep
->previous_offset
!= ep
->offset
)
3234 /* If we changed something, perform elimination in REG_NOTES. This is
3235 needed even when REPLACE is zero because a REG_DEAD note might refer
3236 to a register that we eliminate and could cause a different number
3237 of spill registers to be needed in the final reload pass than in
3239 if (val
&& REG_NOTES (insn
) != 0)
3240 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3245 /* Loop through all elimination pairs.
3246 Recalculate the number not at initial offset.
3248 Compute the maximum offset (minimum offset if the stack does not
3249 grow downward) for each elimination pair. */
3252 update_eliminable_offsets ()
3254 struct elim_table
*ep
;
3256 num_not_at_initial_offset
= 0;
3257 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3259 ep
->previous_offset
= ep
->offset
;
3260 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3261 num_not_at_initial_offset
++;
3265 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3266 replacement we currently believe is valid, mark it as not eliminable if X
3267 modifies DEST in any way other than by adding a constant integer to it.
3269 If DEST is the frame pointer, we do nothing because we assume that
3270 all assignments to the hard frame pointer are nonlocal gotos and are being
3271 done at a time when they are valid and do not disturb anything else.
3272 Some machines want to eliminate a fake argument pointer with either the
3273 frame or stack pointer. Assignments to the hard frame pointer must not
3274 prevent this elimination.
3276 Called via note_stores from reload before starting its passes to scan
3277 the insns of the function. */
3280 mark_not_eliminable (dest
, x
, data
)
3283 void *data ATTRIBUTE_UNUSED
;
3285 register unsigned int i
;
3287 /* A SUBREG of a hard register here is just changing its mode. We should
3288 not see a SUBREG of an eliminable hard register, but check just in
3290 if (GET_CODE (dest
) == SUBREG
)
3291 dest
= SUBREG_REG (dest
);
3293 if (dest
== hard_frame_pointer_rtx
)
3296 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3297 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3298 && (GET_CODE (x
) != SET
3299 || GET_CODE (SET_SRC (x
)) != PLUS
3300 || XEXP (SET_SRC (x
), 0) != dest
3301 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3303 reg_eliminate
[i
].can_eliminate_previous
3304 = reg_eliminate
[i
].can_eliminate
= 0;
3309 /* Verify that the initial elimination offsets did not change since the
3310 last call to set_initial_elim_offsets. This is used to catch cases
3311 where something illegal happened during reload_as_needed that could
3312 cause incorrect code to be generated if we did not check for it. */
3315 verify_initial_elim_offsets ()
3319 #ifdef ELIMINABLE_REGS
3320 struct elim_table
*ep
;
3322 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3324 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3325 if (t
!= ep
->initial_offset
)
3329 INITIAL_FRAME_POINTER_OFFSET (t
);
3330 if (t
!= reg_eliminate
[0].initial_offset
)
3335 /* Reset all offsets on eliminable registers to their initial values. */
3338 set_initial_elim_offsets ()
3340 struct elim_table
*ep
= reg_eliminate
;
3342 #ifdef ELIMINABLE_REGS
3343 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3345 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3346 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3349 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3350 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3353 num_not_at_initial_offset
= 0;
3356 /* Initialize the known label offsets.
3357 Set a known offset for each forced label to be at the initial offset
3358 of each elimination. We do this because we assume that all
3359 computed jumps occur from a location where each elimination is
3360 at its initial offset.
3361 For all other labels, show that we don't know the offsets. */
3364 set_initial_label_offsets ()
3367 memset ((char *) &offsets_known_at
[get_first_label_num ()], 0, num_labels
);
3369 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3371 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3374 /* Set all elimination offsets to the known values for the code label given
3378 set_offsets_for_label (insn
)
3382 int label_nr
= CODE_LABEL_NUMBER (insn
);
3383 struct elim_table
*ep
;
3385 num_not_at_initial_offset
= 0;
3386 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3388 ep
->offset
= ep
->previous_offset
= offsets_at
[label_nr
][i
];
3389 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3390 num_not_at_initial_offset
++;
3394 /* See if anything that happened changes which eliminations are valid.
3395 For example, on the Sparc, whether or not the frame pointer can
3396 be eliminated can depend on what registers have been used. We need
3397 not check some conditions again (such as flag_omit_frame_pointer)
3398 since they can't have changed. */
3401 update_eliminables (pset
)
3404 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3405 int previous_frame_pointer_needed
= frame_pointer_needed
;
3407 struct elim_table
*ep
;
3409 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3410 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3411 #ifdef ELIMINABLE_REGS
3412 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3415 ep
->can_eliminate
= 0;
3417 /* Look for the case where we have discovered that we can't replace
3418 register A with register B and that means that we will now be
3419 trying to replace register A with register C. This means we can
3420 no longer replace register C with register B and we need to disable
3421 such an elimination, if it exists. This occurs often with A == ap,
3422 B == sp, and C == fp. */
3424 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3426 struct elim_table
*op
;
3427 register int new_to
= -1;
3429 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3431 /* Find the current elimination for ep->from, if there is a
3433 for (op
= reg_eliminate
;
3434 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3435 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3441 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3443 for (op
= reg_eliminate
;
3444 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3445 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3446 op
->can_eliminate
= 0;
3450 /* See if any registers that we thought we could eliminate the previous
3451 time are no longer eliminable. If so, something has changed and we
3452 must spill the register. Also, recompute the number of eliminable
3453 registers and see if the frame pointer is needed; it is if there is
3454 no elimination of the frame pointer that we can perform. */
3456 frame_pointer_needed
= 1;
3457 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3459 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3460 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3461 frame_pointer_needed
= 0;
3463 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3465 ep
->can_eliminate_previous
= 0;
3466 SET_HARD_REG_BIT (*pset
, ep
->from
);
3471 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3472 /* If we didn't need a frame pointer last time, but we do now, spill
3473 the hard frame pointer. */
3474 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3475 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3479 /* Initialize the table of registers to eliminate. */
3484 struct elim_table
*ep
;
3485 #ifdef ELIMINABLE_REGS
3486 struct elim_table_1
*ep1
;
3490 reg_eliminate
= (struct elim_table
*)
3491 xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3493 /* Does this function require a frame pointer? */
3495 frame_pointer_needed
= (! flag_omit_frame_pointer
3496 #ifdef EXIT_IGNORE_STACK
3497 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3498 and restore sp for alloca. So we can't eliminate
3499 the frame pointer in that case. At some point,
3500 we should improve this by emitting the
3501 sp-adjusting insns for this case. */
3502 || (current_function_calls_alloca
3503 && EXIT_IGNORE_STACK
)
3505 || FRAME_POINTER_REQUIRED
);
3509 #ifdef ELIMINABLE_REGS
3510 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3511 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3513 ep
->from
= ep1
->from
;
3515 ep
->can_eliminate
= ep
->can_eliminate_previous
3516 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3517 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3520 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3521 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3522 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3523 = ! frame_pointer_needed
;
3526 /* Count the number of eliminable registers and build the FROM and TO
3527 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3528 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3529 We depend on this. */
3530 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3532 num_eliminable
+= ep
->can_eliminate
;
3533 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3534 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3538 /* Kick all pseudos out of hard register REGNO.
3540 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3541 because we found we can't eliminate some register. In the case, no pseudos
3542 are allowed to be in the register, even if they are only in a block that
3543 doesn't require spill registers, unlike the case when we are spilling this
3544 hard reg to produce another spill register.
3546 Return nonzero if any pseudos needed to be kicked out. */
3549 spill_hard_reg (regno
, cant_eliminate
)
3557 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3558 regs_ever_live
[regno
] = 1;
3561 /* Spill every pseudo reg that was allocated to this reg
3562 or to something that overlaps this reg. */
3564 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3565 if (reg_renumber
[i
] >= 0
3566 && (unsigned int) reg_renumber
[i
] <= regno
3567 && ((unsigned int) reg_renumber
[i
]
3568 + HARD_REGNO_NREGS ((unsigned int) reg_renumber
[i
],
3569 PSEUDO_REGNO_MODE (i
))
3571 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3574 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3575 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3578 ior_hard_reg_set (set1
, set2
)
3579 HARD_REG_SET
*set1
, *set2
;
3581 IOR_HARD_REG_SET (*set1
, *set2
);
3584 /* After find_reload_regs has been run for all insn that need reloads,
3585 and/or spill_hard_regs was called, this function is used to actually
3586 spill pseudo registers and try to reallocate them. It also sets up the
3587 spill_regs array for use by choose_reload_regs. */
3590 finish_spills (global
)
3593 struct insn_chain
*chain
;
3594 int something_changed
= 0;
3597 /* Build the spill_regs array for the function. */
3598 /* If there are some registers still to eliminate and one of the spill regs
3599 wasn't ever used before, additional stack space may have to be
3600 allocated to store this register. Thus, we may have changed the offset
3601 between the stack and frame pointers, so mark that something has changed.
3603 One might think that we need only set VAL to 1 if this is a call-used
3604 register. However, the set of registers that must be saved by the
3605 prologue is not identical to the call-used set. For example, the
3606 register used by the call insn for the return PC is a call-used register,
3607 but must be saved by the prologue. */
3610 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3611 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3613 spill_reg_order
[i
] = n_spills
;
3614 spill_regs
[n_spills
++] = i
;
3615 if (num_eliminable
&& ! regs_ever_live
[i
])
3616 something_changed
= 1;
3617 regs_ever_live
[i
] = 1;
3620 spill_reg_order
[i
] = -1;
3622 EXECUTE_IF_SET_IN_REG_SET
3623 (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
,
3625 /* Record the current hard register the pseudo is allocated to in
3626 pseudo_previous_regs so we avoid reallocating it to the same
3627 hard reg in a later pass. */
3628 if (reg_renumber
[i
] < 0)
3631 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3632 /* Mark it as no longer having a hard register home. */
3633 reg_renumber
[i
] = -1;
3634 /* We will need to scan everything again. */
3635 something_changed
= 1;
3638 /* Retry global register allocation if possible. */
3641 memset ((char *) pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3642 /* For every insn that needs reloads, set the registers used as spill
3643 regs in pseudo_forbidden_regs for every pseudo live across the
3645 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3647 EXECUTE_IF_SET_IN_REG_SET
3648 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
3650 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3651 &chain
->used_spill_regs
);
3653 EXECUTE_IF_SET_IN_REG_SET
3654 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
3656 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3657 &chain
->used_spill_regs
);
3661 /* Retry allocating the spilled pseudos. For each reg, merge the
3662 various reg sets that indicate which hard regs can't be used,
3663 and call retry_global_alloc.
3664 We change spill_pseudos here to only contain pseudos that did not
3665 get a new hard register. */
3666 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3667 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3669 HARD_REG_SET forbidden
;
3670 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3671 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3672 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3673 retry_global_alloc (i
, forbidden
);
3674 if (reg_renumber
[i
] >= 0)
3675 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3679 /* Fix up the register information in the insn chain.
3680 This involves deleting those of the spilled pseudos which did not get
3681 a new hard register home from the live_{before,after} sets. */
3682 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3684 HARD_REG_SET used_by_pseudos
;
3685 HARD_REG_SET used_by_pseudos2
;
3687 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3688 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3690 /* Mark any unallocated hard regs as available for spills. That
3691 makes inheritance work somewhat better. */
3692 if (chain
->need_reload
)
3694 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3695 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3696 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3698 /* Save the old value for the sanity test below. */
3699 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3701 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3702 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3703 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3704 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3706 /* Make sure we only enlarge the set. */
3707 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3713 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3714 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3716 int regno
= reg_renumber
[i
];
3717 if (reg_old_renumber
[i
] == regno
)
3720 alter_reg (i
, reg_old_renumber
[i
]);
3721 reg_old_renumber
[i
] = regno
;
3725 fprintf (rtl_dump_file
, " Register %d now on stack.\n\n", i
);
3727 fprintf (rtl_dump_file
, " Register %d now in %d.\n\n",
3728 i
, reg_renumber
[i
]);
3732 return something_changed
;
3735 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3736 Also mark any hard registers used to store user variables as
3737 forbidden from being used for spill registers. */
3740 scan_paradoxical_subregs (x
)
3744 register const char *fmt
;
3745 register enum rtx_code code
= GET_CODE (x
);
3751 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3752 && REG_USERVAR_P (x
))
3753 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3769 if (GET_CODE (SUBREG_REG (x
)) == REG
3770 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3771 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3772 = GET_MODE_SIZE (GET_MODE (x
));
3779 fmt
= GET_RTX_FORMAT (code
);
3780 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3783 scan_paradoxical_subregs (XEXP (x
, i
));
3784 else if (fmt
[i
] == 'E')
3787 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3788 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3793 /* Reload pseudo-registers into hard regs around each insn as needed.
3794 Additional register load insns are output before the insn that needs it
3795 and perhaps store insns after insns that modify the reloaded pseudo reg.
3797 reg_last_reload_reg and reg_reloaded_contents keep track of
3798 which registers are already available in reload registers.
3799 We update these for the reloads that we perform,
3800 as the insns are scanned. */
3803 reload_as_needed (live_known
)
3806 struct insn_chain
*chain
;
3807 #if defined (AUTO_INC_DEC)
3812 memset ((char *) spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3813 memset ((char *) spill_reg_store
, 0, sizeof spill_reg_store
);
3814 reg_last_reload_reg
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
3815 reg_has_output_reload
= (char *) xmalloc (max_regno
);
3816 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3818 set_initial_elim_offsets ();
3820 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3823 rtx insn
= chain
->insn
;
3824 rtx old_next
= NEXT_INSN (insn
);
3826 /* If we pass a label, copy the offsets from the label information
3827 into the current offsets of each elimination. */
3828 if (GET_CODE (insn
) == CODE_LABEL
)
3829 set_offsets_for_label (insn
);
3831 else if (INSN_P (insn
))
3833 rtx oldpat
= PATTERN (insn
);
3835 /* If this is a USE and CLOBBER of a MEM, ensure that any
3836 references to eliminable registers have been removed. */
3838 if ((GET_CODE (PATTERN (insn
)) == USE
3839 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3840 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
3841 XEXP (XEXP (PATTERN (insn
), 0), 0)
3842 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3843 GET_MODE (XEXP (PATTERN (insn
), 0)),
3846 /* If we need to do register elimination processing, do so.
3847 This might delete the insn, in which case we are done. */
3848 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3850 eliminate_regs_in_insn (insn
, 1);
3851 if (GET_CODE (insn
) == NOTE
)
3853 update_eliminable_offsets ();
3858 /* If need_elim is nonzero but need_reload is zero, one might think
3859 that we could simply set n_reloads to 0. However, find_reloads
3860 could have done some manipulation of the insn (such as swapping
3861 commutative operands), and these manipulations are lost during
3862 the first pass for every insn that needs register elimination.
3863 So the actions of find_reloads must be redone here. */
3865 if (! chain
->need_elim
&& ! chain
->need_reload
3866 && ! chain
->need_operand_change
)
3868 /* First find the pseudo regs that must be reloaded for this insn.
3869 This info is returned in the tables reload_... (see reload.h).
3870 Also modify the body of INSN by substituting RELOAD
3871 rtx's for those pseudo regs. */
3874 memset (reg_has_output_reload
, 0, max_regno
);
3875 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3877 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3881 if (num_eliminable
&& chain
->need_elim
)
3882 update_eliminable_offsets ();
3886 rtx next
= NEXT_INSN (insn
);
3889 prev
= PREV_INSN (insn
);
3891 /* Now compute which reload regs to reload them into. Perhaps
3892 reusing reload regs from previous insns, or else output
3893 load insns to reload them. Maybe output store insns too.
3894 Record the choices of reload reg in reload_reg_rtx. */
3895 choose_reload_regs (chain
);
3897 /* Merge any reloads that we didn't combine for fear of
3898 increasing the number of spill registers needed but now
3899 discover can be safely merged. */
3900 if (SMALL_REGISTER_CLASSES
)
3901 merge_assigned_reloads (insn
);
3903 /* Generate the insns to reload operands into or out of
3904 their reload regs. */
3905 emit_reload_insns (chain
);
3907 /* Substitute the chosen reload regs from reload_reg_rtx
3908 into the insn's body (or perhaps into the bodies of other
3909 load and store insn that we just made for reloading
3910 and that we moved the structure into). */
3911 subst_reloads (insn
);
3913 /* If this was an ASM, make sure that all the reload insns
3914 we have generated are valid. If not, give an error
3917 if (asm_noperands (PATTERN (insn
)) >= 0)
3918 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3919 if (p
!= insn
&& INSN_P (p
)
3920 && (recog_memoized (p
) < 0
3921 || (extract_insn (p
), ! constrain_operands (1))))
3923 error_for_asm (insn
,
3924 "`asm' operand requires impossible reload");
3926 NOTE_SOURCE_FILE (p
) = 0;
3927 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
3930 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3931 is no longer validly lying around to save a future reload.
3932 Note that this does not detect pseudos that were reloaded
3933 for this insn in order to be stored in
3934 (obeying register constraints). That is correct; such reload
3935 registers ARE still valid. */
3936 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3938 /* There may have been CLOBBER insns placed after INSN. So scan
3939 between INSN and NEXT and use them to forget old reloads. */
3940 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3941 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
3942 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3945 /* Likewise for regs altered by auto-increment in this insn.
3946 REG_INC notes have been changed by reloading:
3947 find_reloads_address_1 records substitutions for them,
3948 which have been performed by subst_reloads above. */
3949 for (i
= n_reloads
- 1; i
>= 0; i
--)
3951 rtx in_reg
= rld
[i
].in_reg
;
3954 enum rtx_code code
= GET_CODE (in_reg
);
3955 /* PRE_INC / PRE_DEC will have the reload register ending up
3956 with the same value as the stack slot, but that doesn't
3957 hold true for POST_INC / POST_DEC. Either we have to
3958 convert the memory access to a true POST_INC / POST_DEC,
3959 or we can't use the reload register for inheritance. */
3960 if ((code
== POST_INC
|| code
== POST_DEC
)
3961 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3962 REGNO (rld
[i
].reg_rtx
))
3963 /* Make sure it is the inc/dec pseudo, and not
3964 some other (e.g. output operand) pseudo. */
3965 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3966 == REGNO (XEXP (in_reg
, 0))))
3969 rtx reload_reg
= rld
[i
].reg_rtx
;
3970 enum machine_mode mode
= GET_MODE (reload_reg
);
3974 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
3976 /* We really want to ignore REG_INC notes here, so
3977 use PATTERN (p) as argument to reg_set_p . */
3978 if (reg_set_p (reload_reg
, PATTERN (p
)))
3980 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
3985 n
= validate_replace_rtx (reload_reg
,
3986 gen_rtx (code
, mode
,
3990 /* We must also verify that the constraints
3991 are met after the replacement. */
3994 n
= constrain_operands (1);
3998 /* If the constraints were not met, then
3999 undo the replacement. */
4002 validate_replace_rtx (gen_rtx (code
, mode
,
4014 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4016 /* Mark this as having an output reload so that the
4017 REG_INC processing code below won't invalidate
4018 the reload for inheritance. */
4019 SET_HARD_REG_BIT (reg_is_output_reload
,
4020 REGNO (reload_reg
));
4021 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4024 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4027 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4028 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4029 REGNO (rld
[i
].reg_rtx
))
4030 /* Make sure it is the inc/dec pseudo, and not
4031 some other (e.g. output operand) pseudo. */
4032 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4033 == REGNO (XEXP (in_reg
, 0))))
4035 SET_HARD_REG_BIT (reg_is_output_reload
,
4036 REGNO (rld
[i
].reg_rtx
));
4037 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4041 /* If a pseudo that got a hard register is auto-incremented,
4042 we must purge records of copying it into pseudos without
4044 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4045 if (REG_NOTE_KIND (x
) == REG_INC
)
4047 /* See if this pseudo reg was reloaded in this insn.
4048 If so, its last-reload info is still valid
4049 because it is based on this insn's reload. */
4050 for (i
= 0; i
< n_reloads
; i
++)
4051 if (rld
[i
].out
== XEXP (x
, 0))
4055 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4059 /* A reload reg's contents are unknown after a label. */
4060 if (GET_CODE (insn
) == CODE_LABEL
)
4061 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4063 /* Don't assume a reload reg is still good after a call insn
4064 if it is a call-used reg. */
4065 else if (GET_CODE (insn
) == CALL_INSN
)
4066 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4070 free (reg_last_reload_reg
);
4071 free (reg_has_output_reload
);
4074 /* Discard all record of any value reloaded from X,
4075 or reloaded in X from someplace else;
4076 unless X is an output reload reg of the current insn.
4078 X may be a hard reg (the reload reg)
4079 or it may be a pseudo reg that was reloaded from. */
4082 forget_old_reloads_1 (x
, ignored
, data
)
4084 rtx ignored ATTRIBUTE_UNUSED
;
4085 void *data ATTRIBUTE_UNUSED
;
4091 /* note_stores does give us subregs of hard regs. */
4092 while (GET_CODE (x
) == SUBREG
)
4094 offset
+= SUBREG_WORD (x
);
4098 if (GET_CODE (x
) != REG
)
4101 regno
= REGNO (x
) + offset
;
4103 if (regno
>= FIRST_PSEUDO_REGISTER
)
4109 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4110 /* Storing into a spilled-reg invalidates its contents.
4111 This can happen if a block-local pseudo is allocated to that reg
4112 and it wasn't spilled because this block's total need is 0.
4113 Then some insn might have an optional reload and use this reg. */
4114 for (i
= 0; i
< nr
; i
++)
4115 /* But don't do this if the reg actually serves as an output
4116 reload reg in the current instruction. */
4118 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4120 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4121 spill_reg_store
[regno
+ i
] = 0;
4125 /* Since value of X has changed,
4126 forget any value previously copied from it. */
4129 /* But don't forget a copy if this is the output reload
4130 that establishes the copy's validity. */
4131 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4132 reg_last_reload_reg
[regno
+ nr
] = 0;
4135 /* The following HARD_REG_SETs indicate when each hard register is
4136 used for a reload of various parts of the current insn. */
4138 /* If reg is unavailable for all reloads. */
4139 static HARD_REG_SET reload_reg_unavailable
;
4140 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4141 static HARD_REG_SET reload_reg_used
;
4142 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4143 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4144 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4145 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4146 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4147 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4148 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4149 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4150 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4151 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4152 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4153 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4154 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4155 static HARD_REG_SET reload_reg_used_in_op_addr
;
4156 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4157 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4158 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4159 static HARD_REG_SET reload_reg_used_in_insn
;
4160 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4161 static HARD_REG_SET reload_reg_used_in_other_addr
;
4163 /* If reg is in use as a reload reg for any sort of reload. */
4164 static HARD_REG_SET reload_reg_used_at_all
;
4166 /* If reg is use as an inherited reload. We just mark the first register
4168 static HARD_REG_SET reload_reg_used_for_inherit
;
4170 /* Records which hard regs are used in any way, either as explicit use or
4171 by being allocated to a pseudo during any point of the current insn. */
4172 static HARD_REG_SET reg_used_in_insn
;
4174 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4175 TYPE. MODE is used to indicate how many consecutive regs are
4179 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4182 enum reload_type type
;
4183 enum machine_mode mode
;
4185 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4188 for (i
= regno
; i
< nregs
+ regno
; i
++)
4193 SET_HARD_REG_BIT (reload_reg_used
, i
);
4196 case RELOAD_FOR_INPUT_ADDRESS
:
4197 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4200 case RELOAD_FOR_INPADDR_ADDRESS
:
4201 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4204 case RELOAD_FOR_OUTPUT_ADDRESS
:
4205 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4208 case RELOAD_FOR_OUTADDR_ADDRESS
:
4209 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4212 case RELOAD_FOR_OPERAND_ADDRESS
:
4213 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4216 case RELOAD_FOR_OPADDR_ADDR
:
4217 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4220 case RELOAD_FOR_OTHER_ADDRESS
:
4221 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4224 case RELOAD_FOR_INPUT
:
4225 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4228 case RELOAD_FOR_OUTPUT
:
4229 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4232 case RELOAD_FOR_INSN
:
4233 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4237 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4241 /* Similarly, but show REGNO is no longer in use for a reload. */
4244 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4247 enum reload_type type
;
4248 enum machine_mode mode
;
4250 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4251 unsigned int start_regno
, end_regno
, r
;
4253 /* A complication is that for some reload types, inheritance might
4254 allow multiple reloads of the same types to share a reload register.
4255 We set check_opnum if we have to check only reloads with the same
4256 operand number, and check_any if we have to check all reloads. */
4257 int check_opnum
= 0;
4259 HARD_REG_SET
*used_in_set
;
4264 used_in_set
= &reload_reg_used
;
4267 case RELOAD_FOR_INPUT_ADDRESS
:
4268 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4271 case RELOAD_FOR_INPADDR_ADDRESS
:
4273 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4276 case RELOAD_FOR_OUTPUT_ADDRESS
:
4277 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4280 case RELOAD_FOR_OUTADDR_ADDRESS
:
4282 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4285 case RELOAD_FOR_OPERAND_ADDRESS
:
4286 used_in_set
= &reload_reg_used_in_op_addr
;
4289 case RELOAD_FOR_OPADDR_ADDR
:
4291 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4294 case RELOAD_FOR_OTHER_ADDRESS
:
4295 used_in_set
= &reload_reg_used_in_other_addr
;
4299 case RELOAD_FOR_INPUT
:
4300 used_in_set
= &reload_reg_used_in_input
[opnum
];
4303 case RELOAD_FOR_OUTPUT
:
4304 used_in_set
= &reload_reg_used_in_output
[opnum
];
4307 case RELOAD_FOR_INSN
:
4308 used_in_set
= &reload_reg_used_in_insn
;
4313 /* We resolve conflicts with remaining reloads of the same type by
4314 excluding the intervals of of reload registers by them from the
4315 interval of freed reload registers. Since we only keep track of
4316 one set of interval bounds, we might have to exclude somewhat
4317 more then what would be necessary if we used a HARD_REG_SET here.
4318 But this should only happen very infrequently, so there should
4319 be no reason to worry about it. */
4321 start_regno
= regno
;
4322 end_regno
= regno
+ nregs
;
4323 if (check_opnum
|| check_any
)
4325 for (i
= n_reloads
- 1; i
>= 0; i
--)
4327 if (rld
[i
].when_needed
== type
4328 && (check_any
|| rld
[i
].opnum
== opnum
)
4331 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4332 unsigned int conflict_end
4334 + HARD_REGNO_NREGS (conflict_start
, rld
[i
].mode
));
4336 /* If there is an overlap with the first to-be-freed register,
4337 adjust the interval start. */
4338 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4339 start_regno
= conflict_end
;
4340 /* Otherwise, if there is a conflict with one of the other
4341 to-be-freed registers, adjust the interval end. */
4342 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4343 end_regno
= conflict_start
;
4348 for (r
= start_regno
; r
< end_regno
; r
++)
4349 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4352 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4353 specified by OPNUM and TYPE. */
4356 reload_reg_free_p (regno
, opnum
, type
)
4359 enum reload_type type
;
4363 /* In use for a RELOAD_OTHER means it's not available for anything. */
4364 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4365 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4371 /* In use for anything means we can't use it for RELOAD_OTHER. */
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4373 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4377 for (i
= 0; i
< reload_n_operands
; i
++)
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4382 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4388 case RELOAD_FOR_INPUT
:
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4390 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4396 /* If it is used for some other input, can't use it. */
4397 for (i
= 0; i
< reload_n_operands
; i
++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4401 /* If it is used in a later operand's address, can't use it. */
4402 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4409 case RELOAD_FOR_INPUT_ADDRESS
:
4410 /* Can't use a register if it is used for an input address for this
4411 operand or used as an input in an earlier one. */
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4413 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4416 for (i
= 0; i
< opnum
; i
++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4422 case RELOAD_FOR_INPADDR_ADDRESS
:
4423 /* Can't use a register if it is used for an input address
4424 for this operand or used as an input in an earlier
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4429 for (i
= 0; i
< opnum
; i
++)
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4435 case RELOAD_FOR_OUTPUT_ADDRESS
:
4436 /* Can't use a register if it is used for an output address for this
4437 operand or used as an output in this or a later operand. */
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4441 for (i
= opnum
; i
< reload_n_operands
; i
++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4447 case RELOAD_FOR_OUTADDR_ADDRESS
:
4448 /* Can't use a register if it is used for an output address
4449 for this operand or used as an output in this or a
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4454 for (i
= opnum
; i
< reload_n_operands
; i
++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4460 case RELOAD_FOR_OPERAND_ADDRESS
:
4461 for (i
= 0; i
< reload_n_operands
; i
++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4465 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4466 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4468 case RELOAD_FOR_OPADDR_ADDR
:
4469 for (i
= 0; i
< reload_n_operands
; i
++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4473 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4475 case RELOAD_FOR_OUTPUT
:
4476 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4477 outputs, or an operand address for this or an earlier output. */
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4481 for (i
= 0; i
< reload_n_operands
; i
++)
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4485 for (i
= 0; i
<= opnum
; i
++)
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4492 case RELOAD_FOR_INSN
:
4493 for (i
= 0; i
< reload_n_operands
; i
++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4498 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4499 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4501 case RELOAD_FOR_OTHER_ADDRESS
:
4502 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4507 /* Return 1 if the value in reload reg REGNO, as used by a reload
4508 needed for the part of the insn specified by OPNUM and TYPE,
4509 is still available in REGNO at the end of the insn.
4511 We can assume that the reload reg was already tested for availability
4512 at the time it is needed, and we should not check this again,
4513 in case the reg has already been marked in use. */
4516 reload_reg_reaches_end_p (regno
, opnum
, type
)
4519 enum reload_type type
;
4526 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4527 its value must reach the end. */
4530 /* If this use is for part of the insn,
4531 its value reaches if no subsequent part uses the same register.
4532 Just like the above function, don't try to do this with lots
4535 case RELOAD_FOR_OTHER_ADDRESS
:
4536 /* Here we check for everything else, since these don't conflict
4537 with anything else and everything comes later. */
4539 for (i
= 0; i
< reload_n_operands
; i
++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4548 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4549 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4550 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4552 case RELOAD_FOR_INPUT_ADDRESS
:
4553 case RELOAD_FOR_INPADDR_ADDRESS
:
4554 /* Similar, except that we check only for this and subsequent inputs
4555 and the address of only subsequent inputs and we do not need
4556 to check for RELOAD_OTHER objects since they are known not to
4559 for (i
= opnum
; i
< reload_n_operands
; i
++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4563 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4568 for (i
= 0; i
< reload_n_operands
; i
++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4577 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4578 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4579 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4581 case RELOAD_FOR_INPUT
:
4582 /* Similar to input address, except we start at the next operand for
4583 both input and input address and we do not check for
4584 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4587 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4589 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4593 /* ... fall through ... */
4595 case RELOAD_FOR_OPERAND_ADDRESS
:
4596 /* Check outputs and their addresses. */
4598 for (i
= 0; i
< reload_n_operands
; i
++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4604 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4606 case RELOAD_FOR_OPADDR_ADDR
:
4607 for (i
= 0; i
< reload_n_operands
; i
++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4613 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4614 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4615 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4617 case RELOAD_FOR_INSN
:
4618 /* These conflict with other outputs with RELOAD_OTHER. So
4619 we need only check for output addresses. */
4623 /* ... fall through ... */
4625 case RELOAD_FOR_OUTPUT
:
4626 case RELOAD_FOR_OUTPUT_ADDRESS
:
4627 case RELOAD_FOR_OUTADDR_ADDRESS
:
4628 /* We already know these can't conflict with a later output. So the
4629 only thing to check are later output addresses. */
4630 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4631 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4632 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4641 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4644 This function uses the same algorithm as reload_reg_free_p above. */
4647 reloads_conflict (r1
, r2
)
4650 enum reload_type r1_type
= rld
[r1
].when_needed
;
4651 enum reload_type r2_type
= rld
[r2
].when_needed
;
4652 int r1_opnum
= rld
[r1
].opnum
;
4653 int r2_opnum
= rld
[r2
].opnum
;
4655 /* RELOAD_OTHER conflicts with everything. */
4656 if (r2_type
== RELOAD_OTHER
)
4659 /* Otherwise, check conflicts differently for each type. */
4663 case RELOAD_FOR_INPUT
:
4664 return (r2_type
== RELOAD_FOR_INSN
4665 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4666 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4667 || r2_type
== RELOAD_FOR_INPUT
4668 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4669 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4670 && r2_opnum
> r1_opnum
));
4672 case RELOAD_FOR_INPUT_ADDRESS
:
4673 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4674 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4676 case RELOAD_FOR_INPADDR_ADDRESS
:
4677 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4678 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4680 case RELOAD_FOR_OUTPUT_ADDRESS
:
4681 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4682 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4684 case RELOAD_FOR_OUTADDR_ADDRESS
:
4685 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4686 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4688 case RELOAD_FOR_OPERAND_ADDRESS
:
4689 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4690 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4692 case RELOAD_FOR_OPADDR_ADDR
:
4693 return (r2_type
== RELOAD_FOR_INPUT
4694 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4696 case RELOAD_FOR_OUTPUT
:
4697 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4698 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4699 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4700 && r2_opnum
<= r1_opnum
));
4702 case RELOAD_FOR_INSN
:
4703 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4704 || r2_type
== RELOAD_FOR_INSN
4705 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4707 case RELOAD_FOR_OTHER_ADDRESS
:
4708 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4718 /* Indexed by reload number, 1 if incoming value
4719 inherited from previous insns. */
4720 char reload_inherited
[MAX_RELOADS
];
4722 /* For an inherited reload, this is the insn the reload was inherited from,
4723 if we know it. Otherwise, this is 0. */
4724 rtx reload_inheritance_insn
[MAX_RELOADS
];
4726 /* If non-zero, this is a place to get the value of the reload,
4727 rather than using reload_in. */
4728 rtx reload_override_in
[MAX_RELOADS
];
4730 /* For each reload, the hard register number of the register used,
4731 or -1 if we did not need a register for this reload. */
4732 int reload_spill_index
[MAX_RELOADS
];
4734 /* Subroutine of free_for_value_p, used to check a single register.
4735 START_REGNO is the starting regno of the full reload register
4736 (possibly comprising multiple hard registers) that we are considering. */
4739 reload_reg_free_for_value_p (start_regno
, regno
, opnum
, type
, value
, out
,
4740 reloadnum
, ignore_address_reloads
)
4741 int start_regno
, regno
;
4743 enum reload_type type
;
4746 int ignore_address_reloads
;
4749 /* Set if we see an input reload that must not share its reload register
4750 with any new earlyclobber, but might otherwise share the reload
4751 register with an output or input-output reload. */
4752 int check_earlyclobber
= 0;
4756 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4759 if (out
== const0_rtx
)
4765 /* We use some pseudo 'time' value to check if the lifetimes of the
4766 new register use would overlap with the one of a previous reload
4767 that is not read-only or uses a different value.
4768 The 'time' used doesn't have to be linear in any shape or form, just
4770 Some reload types use different 'buckets' for each operand.
4771 So there are MAX_RECOG_OPERANDS different time values for each
4773 We compute TIME1 as the time when the register for the prospective
4774 new reload ceases to be live, and TIME2 for each existing
4775 reload as the time when that the reload register of that reload
4777 Where there is little to be gained by exact lifetime calculations,
4778 we just make conservative assumptions, i.e. a longer lifetime;
4779 this is done in the 'default:' cases. */
4782 case RELOAD_FOR_OTHER_ADDRESS
:
4783 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4784 time1
= copy
? 0 : 1;
4787 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4789 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4790 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4791 respectively, to the time values for these, we get distinct time
4792 values. To get distinct time values for each operand, we have to
4793 multiply opnum by at least three. We round that up to four because
4794 multiply by four is often cheaper. */
4795 case RELOAD_FOR_INPADDR_ADDRESS
:
4796 time1
= opnum
* 4 + 2;
4798 case RELOAD_FOR_INPUT_ADDRESS
:
4799 time1
= opnum
* 4 + 3;
4801 case RELOAD_FOR_INPUT
:
4802 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4803 executes (inclusive). */
4804 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4806 case RELOAD_FOR_OPADDR_ADDR
:
4808 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4809 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4811 case RELOAD_FOR_OPERAND_ADDRESS
:
4812 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4814 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4816 case RELOAD_FOR_OUTADDR_ADDRESS
:
4817 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4819 case RELOAD_FOR_OUTPUT_ADDRESS
:
4820 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4823 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4826 for (i
= 0; i
< n_reloads
; i
++)
4828 rtx reg
= rld
[i
].reg_rtx
;
4829 if (reg
&& GET_CODE (reg
) == REG
4830 && ((unsigned) regno
- true_regnum (reg
)
4831 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
4834 rtx other_input
= rld
[i
].in
;
4836 /* If the other reload loads the same input value, that
4837 will not cause a conflict only if it's loading it into
4838 the same register. */
4839 if (true_regnum (reg
) != start_regno
)
4840 other_input
= NULL_RTX
;
4841 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4842 || rld
[i
].out
|| out
)
4845 switch (rld
[i
].when_needed
)
4847 case RELOAD_FOR_OTHER_ADDRESS
:
4850 case RELOAD_FOR_INPADDR_ADDRESS
:
4851 /* find_reloads makes sure that a
4852 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4853 by at most one - the first -
4854 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4855 address reload is inherited, the address address reload
4856 goes away, so we can ignore this conflict. */
4857 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4858 && ignore_address_reloads
4859 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4860 Then the address address is still needed to store
4861 back the new address. */
4862 && ! rld
[reloadnum
].out
)
4864 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4865 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4867 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4868 && ignore_address_reloads
4869 /* Unless we are reloading an auto_inc expression. */
4870 && ! rld
[reloadnum
].out
)
4872 time2
= rld
[i
].opnum
* 4 + 2;
4874 case RELOAD_FOR_INPUT_ADDRESS
:
4875 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4876 && ignore_address_reloads
4877 && ! rld
[reloadnum
].out
)
4879 time2
= rld
[i
].opnum
* 4 + 3;
4881 case RELOAD_FOR_INPUT
:
4882 time2
= rld
[i
].opnum
* 4 + 4;
4883 check_earlyclobber
= 1;
4885 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4886 == MAX_RECOG_OPERAND * 4 */
4887 case RELOAD_FOR_OPADDR_ADDR
:
4888 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4889 && ignore_address_reloads
4890 && ! rld
[reloadnum
].out
)
4892 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4894 case RELOAD_FOR_OPERAND_ADDRESS
:
4895 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4896 check_earlyclobber
= 1;
4898 case RELOAD_FOR_INSN
:
4899 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4901 case RELOAD_FOR_OUTPUT
:
4902 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4903 instruction is executed. */
4904 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4906 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4907 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4909 case RELOAD_FOR_OUTADDR_ADDRESS
:
4910 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4911 && ignore_address_reloads
4912 && ! rld
[reloadnum
].out
)
4914 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4916 case RELOAD_FOR_OUTPUT_ADDRESS
:
4917 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4920 /* If there is no conflict in the input part, handle this
4921 like an output reload. */
4922 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4924 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4925 /* Earlyclobbered outputs must conflict with inputs. */
4926 if (earlyclobber_operand_p (rld
[i
].out
))
4927 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4932 /* RELOAD_OTHER might be live beyond instruction execution,
4933 but this is not obvious when we set time2 = 1. So check
4934 here if there might be a problem with the new reload
4935 clobbering the register used by the RELOAD_OTHER. */
4943 && (! rld
[i
].in
|| rld
[i
].out
4944 || ! rtx_equal_p (other_input
, value
)))
4945 || (out
&& rld
[reloadnum
].out_reg
4946 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
4952 /* Earlyclobbered outputs must conflict with inputs. */
4953 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
4959 /* Return 1 if the value in reload reg REGNO, as used by a reload
4960 needed for the part of the insn specified by OPNUM and TYPE,
4961 may be used to load VALUE into it.
4963 MODE is the mode in which the register is used, this is needed to
4964 determine how many hard regs to test.
4966 Other read-only reloads with the same value do not conflict
4967 unless OUT is non-zero and these other reloads have to live while
4968 output reloads live.
4969 If OUT is CONST0_RTX, this is a special case: it means that the
4970 test should not be for using register REGNO as reload register, but
4971 for copying from register REGNO into the reload register.
4973 RELOADNUM is the number of the reload we want to load this value for;
4974 a reload does not conflict with itself.
4976 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4977 reloads that load an address for the very reload we are considering.
4979 The caller has to make sure that there is no conflict with the return
4983 free_for_value_p (regno
, mode
, opnum
, type
, value
, out
, reloadnum
,
4984 ignore_address_reloads
)
4986 enum machine_mode mode
;
4988 enum reload_type type
;
4991 int ignore_address_reloads
;
4993 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4995 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
4996 value
, out
, reloadnum
,
4997 ignore_address_reloads
))
5002 /* Determine whether the reload reg X overlaps any rtx'es used for
5003 overriding inheritance. Return nonzero if so. */
5006 conflicts_with_override (x
)
5010 for (i
= 0; i
< n_reloads
; i
++)
5011 if (reload_override_in
[i
]
5012 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5017 /* Give an error message saying we failed to find a reload for INSN,
5018 and clear out reload R. */
5020 failed_reload (insn
, r
)
5024 if (asm_noperands (PATTERN (insn
)) < 0)
5025 /* It's the compiler's fault. */
5026 fatal_insn ("Could not find a spill register", insn
);
5028 /* It's the user's fault; the operand's mode and constraint
5029 don't match. Disable this reload so we don't crash in final. */
5030 error_for_asm (insn
,
5031 "`asm' operand constraint incompatible with operand size");
5035 rld
[r
].optional
= 1;
5036 rld
[r
].secondary_p
= 1;
5039 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5040 for reload R. If it's valid, get an rtx for it. Return nonzero if
5043 set_reload_reg (i
, r
)
5047 rtx reg
= spill_reg_rtx
[i
];
5049 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5050 spill_reg_rtx
[i
] = reg
5051 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5053 regno
= true_regnum (reg
);
5055 /* Detect when the reload reg can't hold the reload mode.
5056 This used to be one `if', but Sequent compiler can't handle that. */
5057 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5059 enum machine_mode test_mode
= VOIDmode
;
5061 test_mode
= GET_MODE (rld
[r
].in
);
5062 /* If rld[r].in has VOIDmode, it means we will load it
5063 in whatever mode the reload reg has: to wit, rld[r].mode.
5064 We have already tested that for validity. */
5065 /* Aside from that, we need to test that the expressions
5066 to reload from or into have modes which are valid for this
5067 reload register. Otherwise the reload insns would be invalid. */
5068 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5069 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5070 if (! (rld
[r
].out
!= 0
5071 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5073 /* The reg is OK. */
5076 /* Mark as in use for this insn the reload regs we use
5078 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5079 rld
[r
].when_needed
, rld
[r
].mode
);
5081 rld
[r
].reg_rtx
= reg
;
5082 reload_spill_index
[r
] = spill_regs
[i
];
5089 /* Find a spill register to use as a reload register for reload R.
5090 LAST_RELOAD is non-zero if this is the last reload for the insn being
5093 Set rld[R].reg_rtx to the register allocated.
5095 We return 1 if successful, or 0 if we couldn't find a spill reg and
5096 we didn't change anything. */
5099 allocate_reload_reg (chain
, r
, last_reload
)
5100 struct insn_chain
*chain ATTRIBUTE_UNUSED
;
5106 /* If we put this reload ahead, thinking it is a group,
5107 then insist on finding a group. Otherwise we can grab a
5108 reg that some other reload needs.
5109 (That can happen when we have a 68000 DATA_OR_FP_REG
5110 which is a group of data regs or one fp reg.)
5111 We need not be so restrictive if there are no more reloads
5114 ??? Really it would be nicer to have smarter handling
5115 for that kind of reg class, where a problem like this is normal.
5116 Perhaps those classes should be avoided for reloading
5117 by use of more alternatives. */
5119 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5121 /* If we want a single register and haven't yet found one,
5122 take any reg in the right class and not in use.
5123 If we want a consecutive group, here is where we look for it.
5125 We use two passes so we can first look for reload regs to
5126 reuse, which are already in use for other reloads in this insn,
5127 and only then use additional registers.
5128 I think that maximizing reuse is needed to make sure we don't
5129 run out of reload regs. Suppose we have three reloads, and
5130 reloads A and B can share regs. These need two regs.
5131 Suppose A and B are given different regs.
5132 That leaves none for C. */
5133 for (pass
= 0; pass
< 2; pass
++)
5135 /* I is the index in spill_regs.
5136 We advance it round-robin between insns to use all spill regs
5137 equally, so that inherited reloads have a chance
5138 of leapfrogging each other. */
5142 for (count
= 0; count
< n_spills
; count
++)
5144 int class = (int) rld
[r
].class;
5150 regnum
= spill_regs
[i
];
5152 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5155 /* We check reload_reg_used to make sure we
5156 don't clobber the return register. */
5157 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5158 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5159 rld
[r
].when_needed
, rld
[r
].in
,
5161 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5162 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5163 /* Look first for regs to share, then for unshared. But
5164 don't share regs used for inherited reloads; they are
5165 the ones we want to preserve. */
5167 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5169 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5172 int nr
= HARD_REGNO_NREGS (regnum
, rld
[r
].mode
);
5173 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5174 (on 68000) got us two FP regs. If NR is 1,
5175 we would reject both of them. */
5178 /* If we need only one reg, we have already won. */
5181 /* But reject a single reg if we demand a group. */
5186 /* Otherwise check that as many consecutive regs as we need
5187 are available here. */
5190 int regno
= regnum
+ nr
- 1;
5191 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5192 && spill_reg_order
[regno
] >= 0
5193 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5194 rld
[r
].when_needed
)))
5203 /* If we found something on pass 1, omit pass 2. */
5204 if (count
< n_spills
)
5208 /* We should have found a spill register by now. */
5209 if (count
>= n_spills
)
5212 /* I is the index in SPILL_REG_RTX of the reload register we are to
5213 allocate. Get an rtx for it and find its register number. */
5215 return set_reload_reg (i
, r
);
5218 /* Initialize all the tables needed to allocate reload registers.
5219 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5220 is the array we use to restore the reg_rtx field for every reload. */
5223 choose_reload_regs_init (chain
, save_reload_reg_rtx
)
5224 struct insn_chain
*chain
;
5225 rtx
*save_reload_reg_rtx
;
5229 for (i
= 0; i
< n_reloads
; i
++)
5230 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5232 memset (reload_inherited
, 0, MAX_RELOADS
);
5233 memset ((char *) reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5234 memset ((char *) reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5236 CLEAR_HARD_REG_SET (reload_reg_used
);
5237 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5240 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5241 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5243 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5246 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5247 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5248 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5249 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5250 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5251 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5254 for (i
= 0; i
< reload_n_operands
; i
++)
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5260 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5261 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5264 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5266 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5268 for (i
= 0; i
< n_reloads
; i
++)
5269 /* If we have already decided to use a certain register,
5270 don't use it in another way. */
5272 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5273 rld
[i
].when_needed
, rld
[i
].mode
);
5276 /* Assign hard reg targets for the pseudo-registers we must reload
5277 into hard regs for this insn.
5278 Also output the instructions to copy them in and out of the hard regs.
5280 For machines with register classes, we are responsible for
5281 finding a reload reg in the proper class. */
5284 choose_reload_regs (chain
)
5285 struct insn_chain
*chain
;
5287 rtx insn
= chain
->insn
;
5289 unsigned int max_group_size
= 1;
5290 enum reg_class group_class
= NO_REGS
;
5291 int pass
, win
, inheritance
;
5293 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5295 /* In order to be certain of getting the registers we need,
5296 we must sort the reloads into order of increasing register class.
5297 Then our grabbing of reload registers will parallel the process
5298 that provided the reload registers.
5300 Also note whether any of the reloads wants a consecutive group of regs.
5301 If so, record the maximum size of the group desired and what
5302 register class contains all the groups needed by this insn. */
5304 for (j
= 0; j
< n_reloads
; j
++)
5306 reload_order
[j
] = j
;
5307 reload_spill_index
[j
] = -1;
5309 if (rld
[j
].nregs
> 1)
5311 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5313 = reg_class_superunion
[(int) rld
[j
].class][(int)group_class
];
5316 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5320 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5322 /* If -O, try first with inheritance, then turning it off.
5323 If not -O, don't do inheritance.
5324 Using inheritance when not optimizing leads to paradoxes
5325 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5326 because one side of the comparison might be inherited. */
5328 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5330 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5332 /* Process the reloads in order of preference just found.
5333 Beyond this point, subregs can be found in reload_reg_rtx.
5335 This used to look for an existing reloaded home for all of the
5336 reloads, and only then perform any new reloads. But that could lose
5337 if the reloads were done out of reg-class order because a later
5338 reload with a looser constraint might have an old home in a register
5339 needed by an earlier reload with a tighter constraint.
5341 To solve this, we make two passes over the reloads, in the order
5342 described above. In the first pass we try to inherit a reload
5343 from a previous insn. If there is a later reload that needs a
5344 class that is a proper subset of the class being processed, we must
5345 also allocate a spill register during the first pass.
5347 Then make a second pass over the reloads to allocate any reloads
5348 that haven't been given registers yet. */
5350 for (j
= 0; j
< n_reloads
; j
++)
5352 register int r
= reload_order
[j
];
5353 rtx search_equiv
= NULL_RTX
;
5355 /* Ignore reloads that got marked inoperative. */
5356 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5357 && ! rld
[r
].secondary_p
)
5360 /* If find_reloads chose to use reload_in or reload_out as a reload
5361 register, we don't need to chose one. Otherwise, try even if it
5362 found one since we might save an insn if we find the value lying
5364 Try also when reload_in is a pseudo without a hard reg. */
5365 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5366 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5367 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5368 && GET_CODE (rld
[r
].in
) != MEM
5369 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5372 #if 0 /* No longer needed for correct operation.
5373 It might give better code, or might not; worth an experiment? */
5374 /* If this is an optional reload, we can't inherit from earlier insns
5375 until we are sure that any non-optional reloads have been allocated.
5376 The following code takes advantage of the fact that optional reloads
5377 are at the end of reload_order. */
5378 if (rld
[r
].optional
!= 0)
5379 for (i
= 0; i
< j
; i
++)
5380 if ((rld
[reload_order
[i
]].out
!= 0
5381 || rld
[reload_order
[i
]].in
!= 0
5382 || rld
[reload_order
[i
]].secondary_p
)
5383 && ! rld
[reload_order
[i
]].optional
5384 && rld
[reload_order
[i
]].reg_rtx
== 0)
5385 allocate_reload_reg (chain
, reload_order
[i
], 0);
5388 /* First see if this pseudo is already available as reloaded
5389 for a previous insn. We cannot try to inherit for reloads
5390 that are smaller than the maximum number of registers needed
5391 for groups unless the register we would allocate cannot be used
5394 We could check here to see if this is a secondary reload for
5395 an object that is already in a register of the desired class.
5396 This would avoid the need for the secondary reload register.
5397 But this is complex because we can't easily determine what
5398 objects might want to be loaded via this reload. So let a
5399 register be allocated here. In `emit_reload_insns' we suppress
5400 one of the loads in the case described above. */
5405 register int regno
= -1;
5406 enum machine_mode mode
= VOIDmode
;
5410 else if (GET_CODE (rld
[r
].in
) == REG
)
5412 regno
= REGNO (rld
[r
].in
);
5413 mode
= GET_MODE (rld
[r
].in
);
5415 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
5417 regno
= REGNO (rld
[r
].in_reg
);
5418 mode
= GET_MODE (rld
[r
].in_reg
);
5420 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5421 && GET_CODE (SUBREG_REG (rld
[r
].in_reg
)) == REG
)
5423 word
= SUBREG_WORD (rld
[r
].in_reg
);
5424 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5425 if (regno
< FIRST_PSEUDO_REGISTER
)
5427 mode
= GET_MODE (rld
[r
].in_reg
);
5430 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5431 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5432 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5433 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5434 && GET_CODE (XEXP (rld
[r
].in_reg
, 0)) == REG
)
5436 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5437 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5438 rld
[r
].out
= rld
[r
].in
;
5442 /* This won't work, since REGNO can be a pseudo reg number.
5443 Also, it takes much more hair to keep track of all the things
5444 that can invalidate an inherited reload of part of a pseudoreg. */
5445 else if (GET_CODE (rld
[r
].in
) == SUBREG
5446 && GET_CODE (SUBREG_REG (rld
[r
].in
)) == REG
)
5447 regno
= REGNO (SUBREG_REG (rld
[r
].in
)) + SUBREG_WORD (rld
[r
].in
);
5450 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5452 enum reg_class
class = rld
[r
].class, last_class
;
5453 rtx last_reg
= reg_last_reload_reg
[regno
];
5454 enum machine_mode need_mode
;
5456 i
= REGNO (last_reg
) + word
;
5457 last_class
= REGNO_REG_CLASS (i
);
5463 = smallest_mode_for_size (GET_MODE_SIZE (mode
)
5464 + word
* UNITS_PER_WORD
,
5465 GET_MODE_CLASS (mode
));
5468 #ifdef CLASS_CANNOT_CHANGE_MODE
5470 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
], i
)
5471 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg
),
5473 : (GET_MODE_SIZE (GET_MODE (last_reg
))
5474 >= GET_MODE_SIZE (need_mode
)))
5476 (GET_MODE_SIZE (GET_MODE (last_reg
))
5477 >= GET_MODE_SIZE (need_mode
))
5479 && reg_reloaded_contents
[i
] == regno
5480 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5481 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5482 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5483 /* Even if we can't use this register as a reload
5484 register, we might use it for reload_override_in,
5485 if copying it to the desired class is cheap
5487 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5488 < MEMORY_MOVE_COST (mode
, class, 1))
5489 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5490 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5494 #ifdef SECONDARY_MEMORY_NEEDED
5495 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5500 && (rld
[r
].nregs
== max_group_size
5501 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5503 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5504 rld
[r
].when_needed
, rld
[r
].in
,
5507 /* If a group is needed, verify that all the subsequent
5508 registers still have their values intact. */
5509 int nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5512 for (k
= 1; k
< nr
; k
++)
5513 if (reg_reloaded_contents
[i
+ k
] != regno
5514 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5521 last_reg
= (GET_MODE (last_reg
) == mode
5522 ? last_reg
: gen_rtx_REG (mode
, i
));
5524 /* We found a register that contains the
5525 value we need. If this register is the
5526 same as an `earlyclobber' operand of the
5527 current insn, just mark it as a place to
5528 reload from since we can't use it as the
5529 reload register itself. */
5531 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5532 if (reg_overlap_mentioned_for_reload_p
5533 (reg_last_reload_reg
[regno
],
5534 reload_earlyclobbers
[i1
]))
5537 if (i1
!= n_earlyclobbers
5538 || ! (free_for_value_p (i
, rld
[r
].mode
,
5540 rld
[r
].when_needed
, rld
[r
].in
,
5542 /* Don't use it if we'd clobber a pseudo reg. */
5543 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5545 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5546 /* Don't clobber the frame pointer. */
5547 || (i
== HARD_FRAME_POINTER_REGNUM
5549 /* Don't really use the inherited spill reg
5550 if we need it wider than we've got it. */
5551 || (GET_MODE_SIZE (rld
[r
].mode
)
5552 > GET_MODE_SIZE (mode
))
5553 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5556 /* If find_reloads chose reload_out as reload
5557 register, stay with it - that leaves the
5558 inherited register for subsequent reloads. */
5559 || (rld
[r
].out
&& rld
[r
].reg_rtx
5560 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5562 if (! rld
[r
].optional
)
5564 reload_override_in
[r
] = last_reg
;
5565 reload_inheritance_insn
[r
]
5566 = reg_reloaded_insn
[i
];
5572 /* We can use this as a reload reg. */
5573 /* Mark the register as in use for this part of
5575 mark_reload_reg_in_use (i
,
5579 rld
[r
].reg_rtx
= last_reg
;
5580 reload_inherited
[r
] = 1;
5581 reload_inheritance_insn
[r
]
5582 = reg_reloaded_insn
[i
];
5583 reload_spill_index
[r
] = i
;
5584 for (k
= 0; k
< nr
; k
++)
5585 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5593 /* Here's another way to see if the value is already lying around. */
5596 && ! reload_inherited
[r
]
5598 && (CONSTANT_P (rld
[r
].in
)
5599 || GET_CODE (rld
[r
].in
) == PLUS
5600 || GET_CODE (rld
[r
].in
) == REG
5601 || GET_CODE (rld
[r
].in
) == MEM
)
5602 && (rld
[r
].nregs
== max_group_size
5603 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5604 search_equiv
= rld
[r
].in
;
5605 /* If this is an output reload from a simple move insn, look
5606 if an equivalence for the input is available. */
5607 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5609 rtx set
= single_set (insn
);
5612 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5613 && CONSTANT_P (SET_SRC (set
)))
5614 search_equiv
= SET_SRC (set
);
5620 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5621 -1, NULL_PTR
, 0, rld
[r
].mode
);
5626 if (GET_CODE (equiv
) == REG
)
5627 regno
= REGNO (equiv
);
5628 else if (GET_CODE (equiv
) == SUBREG
)
5630 /* This must be a SUBREG of a hard register.
5631 Make a new REG since this might be used in an
5632 address and not all machines support SUBREGs
5634 regno
= REGNO (SUBREG_REG (equiv
)) + SUBREG_WORD (equiv
);
5635 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5641 /* If we found a spill reg, reject it unless it is free
5642 and of the desired class. */
5644 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
5645 && ! free_for_value_p (regno
, rld
[r
].mode
,
5646 rld
[r
].opnum
, rld
[r
].when_needed
,
5647 rld
[r
].in
, rld
[r
].out
, r
, 1))
5648 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5652 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5655 /* We found a register that contains the value we need.
5656 If this register is the same as an `earlyclobber' operand
5657 of the current insn, just mark it as a place to reload from
5658 since we can't use it as the reload register itself. */
5661 for (i
= 0; i
< n_earlyclobbers
; i
++)
5662 if (reg_overlap_mentioned_for_reload_p (equiv
,
5663 reload_earlyclobbers
[i
]))
5665 if (! rld
[r
].optional
)
5666 reload_override_in
[r
] = equiv
;
5671 /* If the equiv register we have found is explicitly clobbered
5672 in the current insn, it depends on the reload type if we
5673 can use it, use it for reload_override_in, or not at all.
5674 In particular, we then can't use EQUIV for a
5675 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5679 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 0))
5680 switch (rld
[r
].when_needed
)
5682 case RELOAD_FOR_OTHER_ADDRESS
:
5683 case RELOAD_FOR_INPADDR_ADDRESS
:
5684 case RELOAD_FOR_INPUT_ADDRESS
:
5685 case RELOAD_FOR_OPADDR_ADDR
:
5688 case RELOAD_FOR_INPUT
:
5689 case RELOAD_FOR_OPERAND_ADDRESS
:
5690 if (! rld
[r
].optional
)
5691 reload_override_in
[r
] = equiv
;
5697 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5698 switch (rld
[r
].when_needed
)
5700 case RELOAD_FOR_OTHER_ADDRESS
:
5701 case RELOAD_FOR_INPADDR_ADDRESS
:
5702 case RELOAD_FOR_INPUT_ADDRESS
:
5703 case RELOAD_FOR_OPADDR_ADDR
:
5704 case RELOAD_FOR_OPERAND_ADDRESS
:
5705 case RELOAD_FOR_INPUT
:
5708 if (! rld
[r
].optional
)
5709 reload_override_in
[r
] = equiv
;
5717 /* If we found an equivalent reg, say no code need be generated
5718 to load it, and use it as our reload reg. */
5719 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
5721 int nr
= HARD_REGNO_NREGS (regno
, rld
[r
].mode
);
5723 rld
[r
].reg_rtx
= equiv
;
5724 reload_inherited
[r
] = 1;
5726 /* If reg_reloaded_valid is not set for this register,
5727 there might be a stale spill_reg_store lying around.
5728 We must clear it, since otherwise emit_reload_insns
5729 might delete the store. */
5730 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5731 spill_reg_store
[regno
] = NULL_RTX
;
5732 /* If any of the hard registers in EQUIV are spill
5733 registers, mark them as in use for this insn. */
5734 for (k
= 0; k
< nr
; k
++)
5736 i
= spill_reg_order
[regno
+ k
];
5739 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5742 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5749 /* If we found a register to use already, or if this is an optional
5750 reload, we are done. */
5751 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5755 /* No longer needed for correct operation. Might or might
5756 not give better code on the average. Want to experiment? */
5758 /* See if there is a later reload that has a class different from our
5759 class that intersects our class or that requires less register
5760 than our reload. If so, we must allocate a register to this
5761 reload now, since that reload might inherit a previous reload
5762 and take the only available register in our class. Don't do this
5763 for optional reloads since they will force all previous reloads
5764 to be allocated. Also don't do this for reloads that have been
5767 for (i
= j
+ 1; i
< n_reloads
; i
++)
5769 int s
= reload_order
[i
];
5771 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5772 && ! rld
[s
].secondary_p
)
5776 if ((rld
[s
].class != rld
[r
].class
5777 && reg_classes_intersect_p (rld
[r
].class,
5779 || rld
[s
].nregs
< rld
[r
].nregs
)
5786 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5790 /* Now allocate reload registers for anything non-optional that
5791 didn't get one yet. */
5792 for (j
= 0; j
< n_reloads
; j
++)
5794 register int r
= reload_order
[j
];
5796 /* Ignore reloads that got marked inoperative. */
5797 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5800 /* Skip reloads that already have a register allocated or are
5802 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5805 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5809 /* If that loop got all the way, we have won. */
5816 /* Loop around and try without any inheritance. */
5821 /* First undo everything done by the failed attempt
5822 to allocate with inheritance. */
5823 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5825 /* Some sanity tests to verify that the reloads found in the first
5826 pass are identical to the ones we have now. */
5827 if (chain
->n_reloads
!= n_reloads
)
5830 for (i
= 0; i
< n_reloads
; i
++)
5832 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5834 if (chain
->rld
[i
].when_needed
!= rld
[i
].when_needed
)
5836 for (j
= 0; j
< n_spills
; j
++)
5837 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5838 if (! set_reload_reg (j
, i
))
5839 failed_reload (chain
->insn
, i
);
5843 /* If we thought we could inherit a reload, because it seemed that
5844 nothing else wanted the same reload register earlier in the insn,
5845 verify that assumption, now that all reloads have been assigned.
5846 Likewise for reloads where reload_override_in has been set. */
5848 /* If doing expensive optimizations, do one preliminary pass that doesn't
5849 cancel any inheritance, but removes reloads that have been needed only
5850 for reloads that we know can be inherited. */
5851 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5853 for (j
= 0; j
< n_reloads
; j
++)
5855 register int r
= reload_order
[j
];
5857 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5858 check_reg
= rld
[r
].reg_rtx
;
5859 else if (reload_override_in
[r
]
5860 && (GET_CODE (reload_override_in
[r
]) == REG
5861 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5862 check_reg
= reload_override_in
[r
];
5865 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5866 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5867 (reload_inherited
[r
]
5868 ? rld
[r
].out
: const0_rtx
),
5873 reload_inherited
[r
] = 0;
5874 reload_override_in
[r
] = 0;
5876 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5877 reload_override_in, then we do not need its related
5878 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5879 likewise for other reload types.
5880 We handle this by removing a reload when its only replacement
5881 is mentioned in reload_in of the reload we are going to inherit.
5882 A special case are auto_inc expressions; even if the input is
5883 inherited, we still need the address for the output. We can
5884 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5885 If we suceeded removing some reload and we are doing a preliminary
5886 pass just to remove such reloads, make another pass, since the
5887 removal of one reload might allow us to inherit another one. */
5889 && rld
[r
].out
!= rld
[r
].in
5890 && remove_address_replacements (rld
[r
].in
) && pass
)
5895 /* Now that reload_override_in is known valid,
5896 actually override reload_in. */
5897 for (j
= 0; j
< n_reloads
; j
++)
5898 if (reload_override_in
[j
])
5899 rld
[j
].in
= reload_override_in
[j
];
5901 /* If this reload won't be done because it has been cancelled or is
5902 optional and not inherited, clear reload_reg_rtx so other
5903 routines (such as subst_reloads) don't get confused. */
5904 for (j
= 0; j
< n_reloads
; j
++)
5905 if (rld
[j
].reg_rtx
!= 0
5906 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5907 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5908 && ! rld
[j
].secondary_p
)))
5910 int regno
= true_regnum (rld
[j
].reg_rtx
);
5912 if (spill_reg_order
[regno
] >= 0)
5913 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5914 rld
[j
].when_needed
, rld
[j
].mode
);
5916 reload_spill_index
[j
] = -1;
5919 /* Record which pseudos and which spill regs have output reloads. */
5920 for (j
= 0; j
< n_reloads
; j
++)
5922 register int r
= reload_order
[j
];
5924 i
= reload_spill_index
[r
];
5926 /* I is nonneg if this reload uses a register.
5927 If rld[r].reg_rtx is 0, this is an optional reload
5928 that we opted to ignore. */
5929 if (rld
[r
].out_reg
!= 0 && GET_CODE (rld
[r
].out_reg
) == REG
5930 && rld
[r
].reg_rtx
!= 0)
5932 register int nregno
= REGNO (rld
[r
].out_reg
);
5935 if (nregno
< FIRST_PSEUDO_REGISTER
)
5936 nr
= HARD_REGNO_NREGS (nregno
, rld
[r
].mode
);
5939 reg_has_output_reload
[nregno
+ nr
] = 1;
5943 nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5945 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
5948 if (rld
[r
].when_needed
!= RELOAD_OTHER
5949 && rld
[r
].when_needed
!= RELOAD_FOR_OUTPUT
5950 && rld
[r
].when_needed
!= RELOAD_FOR_INSN
)
5956 /* Deallocate the reload register for reload R. This is called from
5957 remove_address_replacements. */
5960 deallocate_reload_reg (r
)
5965 if (! rld
[r
].reg_rtx
)
5967 regno
= true_regnum (rld
[r
].reg_rtx
);
5969 if (spill_reg_order
[regno
] >= 0)
5970 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
5972 reload_spill_index
[r
] = -1;
5975 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5976 reloads of the same item for fear that we might not have enough reload
5977 registers. However, normally they will get the same reload register
5978 and hence actually need not be loaded twice.
5980 Here we check for the most common case of this phenomenon: when we have
5981 a number of reloads for the same object, each of which were allocated
5982 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5983 reload, and is not modified in the insn itself. If we find such,
5984 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5985 This will not increase the number of spill registers needed and will
5986 prevent redundant code. */
5989 merge_assigned_reloads (insn
)
5994 /* Scan all the reloads looking for ones that only load values and
5995 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5996 assigned and not modified by INSN. */
5998 for (i
= 0; i
< n_reloads
; i
++)
6000 int conflicting_input
= 0;
6001 int max_input_address_opnum
= -1;
6002 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6004 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6005 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6006 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6009 /* Look at all other reloads. Ensure that the only use of this
6010 reload_reg_rtx is in a reload that just loads the same value
6011 as we do. Note that any secondary reloads must be of the identical
6012 class since the values, modes, and result registers are the
6013 same, so we need not do anything with any secondary reloads. */
6015 for (j
= 0; j
< n_reloads
; j
++)
6017 if (i
== j
|| rld
[j
].reg_rtx
== 0
6018 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6022 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6023 && rld
[j
].opnum
> max_input_address_opnum
)
6024 max_input_address_opnum
= rld
[j
].opnum
;
6026 /* If the reload regs aren't exactly the same (e.g, different modes)
6027 or if the values are different, we can't merge this reload.
6028 But if it is an input reload, we might still merge
6029 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6031 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6032 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6033 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6035 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6036 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6037 || rld
[i
].opnum
> rld
[j
].opnum
)
6038 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6040 conflicting_input
= 1;
6041 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6042 min_conflicting_input_opnum
= rld
[j
].opnum
;
6046 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6047 we, in fact, found any matching reloads. */
6050 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6052 for (j
= 0; j
< n_reloads
; j
++)
6053 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6054 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6055 && (! conflicting_input
6056 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6057 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6059 rld
[i
].when_needed
= RELOAD_OTHER
;
6061 reload_spill_index
[j
] = -1;
6062 transfer_replacements (i
, j
);
6065 /* If this is now RELOAD_OTHER, look for any reloads that load
6066 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6067 if they were for inputs, RELOAD_OTHER for outputs. Note that
6068 this test is equivalent to looking for reloads for this operand
6071 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6072 for (j
= 0; j
< n_reloads
; j
++)
6074 && rld
[i
].when_needed
!= RELOAD_OTHER
6075 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6078 = ((rld
[i
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6079 || rld
[i
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6080 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6085 /* These arrays are filled by emit_reload_insns and its subroutines. */
6086 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6087 static rtx other_input_address_reload_insns
= 0;
6088 static rtx other_input_reload_insns
= 0;
6089 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6090 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6091 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6092 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6093 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6094 static rtx operand_reload_insns
= 0;
6095 static rtx other_operand_reload_insns
= 0;
6096 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6098 /* Values to be put in spill_reg_store are put here first. */
6099 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6100 static HARD_REG_SET reg_reloaded_died
;
6102 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6103 has the number J. OLD contains the value to be used as input. */
6106 emit_input_reload_insns (chain
, rl
, old
, j
)
6107 struct insn_chain
*chain
;
6112 rtx insn
= chain
->insn
;
6113 register rtx reloadreg
= rl
->reg_rtx
;
6114 rtx oldequiv_reg
= 0;
6117 enum machine_mode mode
;
6120 /* Determine the mode to reload in.
6121 This is very tricky because we have three to choose from.
6122 There is the mode the insn operand wants (rl->inmode).
6123 There is the mode of the reload register RELOADREG.
6124 There is the intrinsic mode of the operand, which we could find
6125 by stripping some SUBREGs.
6126 It turns out that RELOADREG's mode is irrelevant:
6127 we can change that arbitrarily.
6129 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6130 then the reload reg may not support QImode moves, so use SImode.
6131 If foo is in memory due to spilling a pseudo reg, this is safe,
6132 because the QImode value is in the least significant part of a
6133 slot big enough for a SImode. If foo is some other sort of
6134 memory reference, then it is impossible to reload this case,
6135 so previous passes had better make sure this never happens.
6137 Then consider a one-word union which has SImode and one of its
6138 members is a float, being fetched as (SUBREG:SF union:SI).
6139 We must fetch that as SFmode because we could be loading into
6140 a float-only register. In this case OLD's mode is correct.
6142 Consider an immediate integer: it has VOIDmode. Here we need
6143 to get a mode from something else.
6145 In some cases, there is a fourth mode, the operand's
6146 containing mode. If the insn specifies a containing mode for
6147 this operand, it overrides all others.
6149 I am not sure whether the algorithm here is always right,
6150 but it does the right things in those cases. */
6152 mode
= GET_MODE (old
);
6153 if (mode
== VOIDmode
)
6156 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6157 /* If we need a secondary register for this operation, see if
6158 the value is already in a register in that class. Don't
6159 do this if the secondary register will be used as a scratch
6162 if (rl
->secondary_in_reload
>= 0
6163 && rl
->secondary_in_icode
== CODE_FOR_nothing
6166 = find_equiv_reg (old
, insn
,
6167 rld
[rl
->secondary_in_reload
].class,
6168 -1, NULL_PTR
, 0, mode
);
6171 /* If reloading from memory, see if there is a register
6172 that already holds the same value. If so, reload from there.
6173 We can pass 0 as the reload_reg_p argument because
6174 any other reload has either already been emitted,
6175 in which case find_equiv_reg will see the reload-insn,
6176 or has yet to be emitted, in which case it doesn't matter
6177 because we will use this equiv reg right away. */
6179 if (oldequiv
== 0 && optimize
6180 && (GET_CODE (old
) == MEM
6181 || (GET_CODE (old
) == REG
6182 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6183 && reg_renumber
[REGNO (old
)] < 0)))
6184 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
6185 -1, NULL_PTR
, 0, mode
);
6189 unsigned int regno
= true_regnum (oldequiv
);
6191 /* Don't use OLDEQUIV if any other reload changes it at an
6192 earlier stage of this insn or at this stage. */
6193 if (! free_for_value_p (regno
, rl
->mode
, rl
->opnum
, rl
->when_needed
,
6194 rl
->in
, const0_rtx
, j
, 0))
6197 /* If it is no cheaper to copy from OLDEQUIV into the
6198 reload register than it would be to move from memory,
6199 don't use it. Likewise, if we need a secondary register
6203 && ((REGNO_REG_CLASS (regno
) != rl
->class
6204 && (REGISTER_MOVE_COST (mode
, REGNO_REG_CLASS (regno
),
6206 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
6207 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6208 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6212 #ifdef SECONDARY_MEMORY_NEEDED
6213 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6221 /* delete_output_reload is only invoked properly if old contains
6222 the original pseudo register. Since this is replaced with a
6223 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6224 find the pseudo in RELOAD_IN_REG. */
6226 && reload_override_in
[j
]
6227 && GET_CODE (rl
->in_reg
) == REG
)
6234 else if (GET_CODE (oldequiv
) == REG
)
6235 oldequiv_reg
= oldequiv
;
6236 else if (GET_CODE (oldequiv
) == SUBREG
)
6237 oldequiv_reg
= SUBREG_REG (oldequiv
);
6239 /* If we are reloading from a register that was recently stored in
6240 with an output-reload, see if we can prove there was
6241 actually no need to store the old value in it. */
6243 if (optimize
&& GET_CODE (oldequiv
) == REG
6244 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6245 && spill_reg_store
[REGNO (oldequiv
)]
6246 && GET_CODE (old
) == REG
6247 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6248 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6250 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6252 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6253 then load RELOADREG from OLDEQUIV. Note that we cannot use
6254 gen_lowpart_common since it can do the wrong thing when
6255 RELOADREG has a multi-word mode. Note that RELOADREG
6256 must always be a REG here. */
6258 if (GET_MODE (reloadreg
) != mode
)
6259 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6260 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6261 oldequiv
= SUBREG_REG (oldequiv
);
6262 if (GET_MODE (oldequiv
) != VOIDmode
6263 && mode
!= GET_MODE (oldequiv
))
6264 oldequiv
= gen_rtx_SUBREG (mode
, oldequiv
, 0);
6266 /* Switch to the right place to emit the reload insns. */
6267 switch (rl
->when_needed
)
6270 where
= &other_input_reload_insns
;
6272 case RELOAD_FOR_INPUT
:
6273 where
= &input_reload_insns
[rl
->opnum
];
6275 case RELOAD_FOR_INPUT_ADDRESS
:
6276 where
= &input_address_reload_insns
[rl
->opnum
];
6278 case RELOAD_FOR_INPADDR_ADDRESS
:
6279 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6281 case RELOAD_FOR_OUTPUT_ADDRESS
:
6282 where
= &output_address_reload_insns
[rl
->opnum
];
6284 case RELOAD_FOR_OUTADDR_ADDRESS
:
6285 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6287 case RELOAD_FOR_OPERAND_ADDRESS
:
6288 where
= &operand_reload_insns
;
6290 case RELOAD_FOR_OPADDR_ADDR
:
6291 where
= &other_operand_reload_insns
;
6293 case RELOAD_FOR_OTHER_ADDRESS
:
6294 where
= &other_input_address_reload_insns
;
6300 push_to_sequence (*where
);
6302 /* Auto-increment addresses must be reloaded in a special way. */
6303 if (rl
->out
&& ! rl
->out_reg
)
6305 /* We are not going to bother supporting the case where a
6306 incremented register can't be copied directly from
6307 OLDEQUIV since this seems highly unlikely. */
6308 if (rl
->secondary_in_reload
>= 0)
6311 if (reload_inherited
[j
])
6312 oldequiv
= reloadreg
;
6314 old
= XEXP (rl
->in_reg
, 0);
6316 if (optimize
&& GET_CODE (oldequiv
) == REG
6317 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6318 && spill_reg_store
[REGNO (oldequiv
)]
6319 && GET_CODE (old
) == REG
6320 && (dead_or_set_p (insn
,
6321 spill_reg_stored_to
[REGNO (oldequiv
)])
6322 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6324 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6326 /* Prevent normal processing of this reload. */
6328 /* Output a special code sequence for this case. */
6329 new_spill_reg_store
[REGNO (reloadreg
)]
6330 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6334 /* If we are reloading a pseudo-register that was set by the previous
6335 insn, see if we can get rid of that pseudo-register entirely
6336 by redirecting the previous insn into our reload register. */
6338 else if (optimize
&& GET_CODE (old
) == REG
6339 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6340 && dead_or_set_p (insn
, old
)
6341 /* This is unsafe if some other reload
6342 uses the same reg first. */
6343 && ! conflicts_with_override (reloadreg
)
6344 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6345 rl
->when_needed
, old
, rl
->out
, j
, 0))
6347 rtx temp
= PREV_INSN (insn
);
6348 while (temp
&& GET_CODE (temp
) == NOTE
)
6349 temp
= PREV_INSN (temp
);
6351 && GET_CODE (temp
) == INSN
6352 && GET_CODE (PATTERN (temp
)) == SET
6353 && SET_DEST (PATTERN (temp
)) == old
6354 /* Make sure we can access insn_operand_constraint. */
6355 && asm_noperands (PATTERN (temp
)) < 0
6356 /* This is unsafe if prev insn rejects our reload reg. */
6357 && constraint_accepts_reg_p (insn_data
[recog_memoized (temp
)].operand
[0].constraint
,
6359 /* This is unsafe if operand occurs more than once in current
6360 insn. Perhaps some occurrences aren't reloaded. */
6361 && count_occurrences (PATTERN (insn
), old
, 0) == 1
6362 /* Don't risk splitting a matching pair of operands. */
6363 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6365 /* Store into the reload register instead of the pseudo. */
6366 SET_DEST (PATTERN (temp
)) = reloadreg
;
6368 /* If the previous insn is an output reload, the source is
6369 a reload register, and its spill_reg_store entry will
6370 contain the previous destination. This is now
6372 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6373 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6375 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6376 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6379 /* If these are the only uses of the pseudo reg,
6380 pretend for GDB it lives in the reload reg we used. */
6381 if (REG_N_DEATHS (REGNO (old
)) == 1
6382 && REG_N_SETS (REGNO (old
)) == 1)
6384 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6385 alter_reg (REGNO (old
), -1);
6391 /* We can't do that, so output an insn to load RELOADREG. */
6393 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6394 /* If we have a secondary reload, pick up the secondary register
6395 and icode, if any. If OLDEQUIV and OLD are different or
6396 if this is an in-out reload, recompute whether or not we
6397 still need a secondary register and what the icode should
6398 be. If we still need a secondary register and the class or
6399 icode is different, go back to reloading from OLD if using
6400 OLDEQUIV means that we got the wrong type of register. We
6401 cannot have different class or icode due to an in-out reload
6402 because we don't make such reloads when both the input and
6403 output need secondary reload registers. */
6405 if (! special
&& rl
->secondary_in_reload
>= 0)
6407 rtx second_reload_reg
= 0;
6408 int secondary_reload
= rl
->secondary_in_reload
;
6409 rtx real_oldequiv
= oldequiv
;
6412 enum insn_code icode
;
6414 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6415 and similarly for OLD.
6416 See comments in get_secondary_reload in reload.c. */
6417 /* If it is a pseudo that cannot be replaced with its
6418 equivalent MEM, we must fall back to reload_in, which
6419 will have all the necessary substitutions registered.
6420 Likewise for a pseudo that can't be replaced with its
6421 equivalent constant.
6423 Take extra care for subregs of such pseudos. Note that
6424 we cannot use reg_equiv_mem in this case because it is
6425 not in the right mode. */
6428 if (GET_CODE (tmp
) == SUBREG
)
6429 tmp
= SUBREG_REG (tmp
);
6430 if (GET_CODE (tmp
) == REG
6431 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6432 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6433 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6435 if (! reg_equiv_mem
[REGNO (tmp
)]
6436 || num_not_at_initial_offset
6437 || GET_CODE (oldequiv
) == SUBREG
)
6438 real_oldequiv
= rl
->in
;
6440 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6444 if (GET_CODE (tmp
) == SUBREG
)
6445 tmp
= SUBREG_REG (tmp
);
6446 if (GET_CODE (tmp
) == REG
6447 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6448 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6449 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6451 if (! reg_equiv_mem
[REGNO (tmp
)]
6452 || num_not_at_initial_offset
6453 || GET_CODE (old
) == SUBREG
)
6456 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6459 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6460 icode
= rl
->secondary_in_icode
;
6462 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6463 || (rl
->in
!= 0 && rl
->out
!= 0))
6465 enum reg_class new_class
6466 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6467 mode
, real_oldequiv
);
6469 if (new_class
== NO_REGS
)
6470 second_reload_reg
= 0;
6473 enum insn_code new_icode
;
6474 enum machine_mode new_mode
;
6476 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6477 REGNO (second_reload_reg
)))
6478 oldequiv
= old
, real_oldequiv
= real_old
;
6481 new_icode
= reload_in_optab
[(int) mode
];
6482 if (new_icode
!= CODE_FOR_nothing
6483 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6484 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6486 || (insn_data
[(int) new_icode
].operand
[1].predicate
6487 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6488 (real_oldequiv
, mode
)))))
6489 new_icode
= CODE_FOR_nothing
;
6491 if (new_icode
== CODE_FOR_nothing
)
6494 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6496 if (GET_MODE (second_reload_reg
) != new_mode
)
6498 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6500 oldequiv
= old
, real_oldequiv
= real_old
;
6503 = gen_rtx_REG (new_mode
,
6504 REGNO (second_reload_reg
));
6510 /* If we still need a secondary reload register, check
6511 to see if it is being used as a scratch or intermediate
6512 register and generate code appropriately. If we need
6513 a scratch register, use REAL_OLDEQUIV since the form of
6514 the insn may depend on the actual address if it is
6517 if (second_reload_reg
)
6519 if (icode
!= CODE_FOR_nothing
)
6521 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6522 second_reload_reg
));
6527 /* See if we need a scratch register to load the
6528 intermediate register (a tertiary reload). */
6529 enum insn_code tertiary_icode
6530 = rld
[secondary_reload
].secondary_in_icode
;
6532 if (tertiary_icode
!= CODE_FOR_nothing
)
6534 rtx third_reload_reg
6535 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6537 emit_insn ((GEN_FCN (tertiary_icode
)
6538 (second_reload_reg
, real_oldequiv
,
6539 third_reload_reg
)));
6542 gen_reload (second_reload_reg
, real_oldequiv
,
6546 oldequiv
= second_reload_reg
;
6552 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6554 rtx real_oldequiv
= oldequiv
;
6556 if ((GET_CODE (oldequiv
) == REG
6557 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6558 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6559 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6560 || (GET_CODE (oldequiv
) == SUBREG
6561 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6562 && (REGNO (SUBREG_REG (oldequiv
))
6563 >= FIRST_PSEUDO_REGISTER
)
6564 && ((reg_equiv_memory_loc
6565 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6566 || (reg_equiv_constant
6567 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6568 || (CONSTANT_P (oldequiv
)
6569 && PREFERRED_RELOAD_CLASS (oldequiv
,
6570 REGNO_REG_CLASS (REGNO (reloadreg
))) == NO_REGS
))
6571 real_oldequiv
= rl
->in
;
6572 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6576 /* End this sequence. */
6577 *where
= get_insns ();
6580 /* Update reload_override_in so that delete_address_reloads_1
6581 can see the actual register usage. */
6583 reload_override_in
[j
] = oldequiv
;
6586 /* Generate insns to for the output reload RL, which is for the insn described
6587 by CHAIN and has the number J. */
6589 emit_output_reload_insns (chain
, rl
, j
)
6590 struct insn_chain
*chain
;
6594 rtx reloadreg
= rl
->reg_rtx
;
6595 rtx insn
= chain
->insn
;
6598 enum machine_mode mode
= GET_MODE (old
);
6601 if (rl
->when_needed
== RELOAD_OTHER
)
6604 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6606 /* Determine the mode to reload in.
6607 See comments above (for input reloading). */
6609 if (mode
== VOIDmode
)
6611 /* VOIDmode should never happen for an output. */
6612 if (asm_noperands (PATTERN (insn
)) < 0)
6613 /* It's the compiler's fault. */
6614 fatal_insn ("VOIDmode on an output", insn
);
6615 error_for_asm (insn
, "output operand is constant in `asm'");
6616 /* Prevent crash--use something we know is valid. */
6618 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6621 if (GET_MODE (reloadreg
) != mode
)
6622 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6624 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6626 /* If we need two reload regs, set RELOADREG to the intermediate
6627 one, since it will be stored into OLD. We might need a secondary
6628 register only for an input reload, so check again here. */
6630 if (rl
->secondary_out_reload
>= 0)
6634 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
6635 && reg_equiv_mem
[REGNO (old
)] != 0)
6636 real_old
= reg_equiv_mem
[REGNO (old
)];
6638 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6642 rtx second_reloadreg
= reloadreg
;
6643 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6645 /* See if RELOADREG is to be used as a scratch register
6646 or as an intermediate register. */
6647 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6649 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6650 (real_old
, second_reloadreg
, reloadreg
)));
6655 /* See if we need both a scratch and intermediate reload
6658 int secondary_reload
= rl
->secondary_out_reload
;
6659 enum insn_code tertiary_icode
6660 = rld
[secondary_reload
].secondary_out_icode
;
6662 if (GET_MODE (reloadreg
) != mode
)
6663 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6665 if (tertiary_icode
!= CODE_FOR_nothing
)
6668 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6671 /* Copy primary reload reg to secondary reload reg.
6672 (Note that these have been swapped above, then
6673 secondary reload reg to OLD using our insn.) */
6675 /* If REAL_OLD is a paradoxical SUBREG, remove it
6676 and try to put the opposite SUBREG on
6678 if (GET_CODE (real_old
) == SUBREG
6679 && (GET_MODE_SIZE (GET_MODE (real_old
))
6680 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6681 && 0 != (tem
= gen_lowpart_common
6682 (GET_MODE (SUBREG_REG (real_old
)),
6684 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6686 gen_reload (reloadreg
, second_reloadreg
,
6687 rl
->opnum
, rl
->when_needed
);
6688 emit_insn ((GEN_FCN (tertiary_icode
)
6689 (real_old
, reloadreg
, third_reloadreg
)));
6694 /* Copy between the reload regs here and then to
6697 gen_reload (reloadreg
, second_reloadreg
,
6698 rl
->opnum
, rl
->when_needed
);
6704 /* Output the last reload insn. */
6709 /* Don't output the last reload if OLD is not the dest of
6710 INSN and is in the src and is clobbered by INSN. */
6711 if (! flag_expensive_optimizations
6712 || GET_CODE (old
) != REG
6713 || !(set
= single_set (insn
))
6714 || rtx_equal_p (old
, SET_DEST (set
))
6715 || !reg_mentioned_p (old
, SET_SRC (set
))
6716 || !regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0))
6717 gen_reload (old
, reloadreg
, rl
->opnum
,
6721 /* Look at all insns we emitted, just to be safe. */
6722 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6725 rtx pat
= PATTERN (p
);
6727 /* If this output reload doesn't come from a spill reg,
6728 clear any memory of reloaded copies of the pseudo reg.
6729 If this output reload comes from a spill reg,
6730 reg_has_output_reload will make this do nothing. */
6731 note_stores (pat
, forget_old_reloads_1
, NULL
);
6733 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6735 rtx set
= single_set (insn
);
6736 if (reload_spill_index
[j
] < 0
6738 && SET_SRC (set
) == rl
->reg_rtx
)
6740 int src
= REGNO (SET_SRC (set
));
6742 reload_spill_index
[j
] = src
;
6743 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6744 if (find_regno_note (insn
, REG_DEAD
, src
))
6745 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6747 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6749 int s
= rl
->secondary_out_reload
;
6750 set
= single_set (p
);
6751 /* If this reload copies only to the secondary reload
6752 register, the secondary reload does the actual
6754 if (s
>= 0 && set
== NULL_RTX
)
6755 /* We can't tell what function the secondary reload
6756 has and where the actual store to the pseudo is
6757 made; leave new_spill_reg_store alone. */
6760 && SET_SRC (set
) == rl
->reg_rtx
6761 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6763 /* Usually the next instruction will be the
6764 secondary reload insn; if we can confirm
6765 that it is, setting new_spill_reg_store to
6766 that insn will allow an extra optimization. */
6767 rtx s_reg
= rld
[s
].reg_rtx
;
6768 rtx next
= NEXT_INSN (p
);
6769 rld
[s
].out
= rl
->out
;
6770 rld
[s
].out_reg
= rl
->out_reg
;
6771 set
= single_set (next
);
6772 if (set
&& SET_SRC (set
) == s_reg
6773 && ! new_spill_reg_store
[REGNO (s_reg
)])
6775 SET_HARD_REG_BIT (reg_is_output_reload
,
6777 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6781 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6786 if (rl
->when_needed
== RELOAD_OTHER
)
6788 emit_insns (other_output_reload_insns
[rl
->opnum
]);
6789 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6792 output_reload_insns
[rl
->opnum
] = get_insns ();
6797 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6798 and has the number J. */
6800 do_input_reload (chain
, rl
, j
)
6801 struct insn_chain
*chain
;
6805 int expect_occurrences
= 1;
6806 rtx insn
= chain
->insn
;
6807 rtx old
= (rl
->in
&& GET_CODE (rl
->in
) == MEM
6808 ? rl
->in_reg
: rl
->in
);
6811 /* AUTO_INC reloads need to be handled even if inherited. We got an
6812 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6813 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6814 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6815 && rl
->reg_rtx
!= 0)
6816 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6818 /* When inheriting a wider reload, we have a MEM in rl->in,
6819 e.g. inheriting a SImode output reload for
6820 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6821 if (optimize
&& reload_inherited
[j
] && rl
->in
6822 && GET_CODE (rl
->in
) == MEM
6823 && GET_CODE (rl
->in_reg
) == MEM
6824 && reload_spill_index
[j
] >= 0
6825 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6828 = count_occurrences (PATTERN (insn
), rl
->in
, 0) == 1 ? 0 : -1;
6829 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6832 /* If we are reloading a register that was recently stored in with an
6833 output-reload, see if we can prove there was
6834 actually no need to store the old value in it. */
6837 && (reload_inherited
[j
] || reload_override_in
[j
])
6839 && GET_CODE (rl
->reg_rtx
) == REG
6840 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6842 /* There doesn't seem to be any reason to restrict this to pseudos
6843 and doing so loses in the case where we are copying from a
6844 register of the wrong class. */
6845 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6846 >= FIRST_PSEUDO_REGISTER
)
6848 /* The insn might have already some references to stackslots
6849 replaced by MEMs, while reload_out_reg still names the
6851 && (dead_or_set_p (insn
,
6852 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6853 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6855 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6858 /* Do output reloading for reload RL, which is for the insn described by
6859 CHAIN and has the number J.
6860 ??? At some point we need to support handling output reloads of
6861 JUMP_INSNs or insns that set cc0. */
6863 do_output_reload (chain
, rl
, j
)
6864 struct insn_chain
*chain
;
6869 rtx insn
= chain
->insn
;
6870 /* If this is an output reload that stores something that is
6871 not loaded in this same reload, see if we can eliminate a previous
6873 rtx pseudo
= rl
->out_reg
;
6876 && GET_CODE (pseudo
) == REG
6877 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6878 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6879 && reg_last_reload_reg
[REGNO (pseudo
)])
6881 int pseudo_no
= REGNO (pseudo
);
6882 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6884 /* We don't need to test full validity of last_regno for
6885 inherit here; we only want to know if the store actually
6886 matches the pseudo. */
6887 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6888 && reg_reloaded_contents
[last_regno
] == pseudo_no
6889 && spill_reg_store
[last_regno
]
6890 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6891 delete_output_reload (insn
, j
, last_regno
);
6896 || rl
->reg_rtx
== old
6897 || rl
->reg_rtx
== 0)
6900 /* An output operand that dies right away does need a reload,
6901 but need not be copied from it. Show the new location in the
6903 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
6904 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6906 XEXP (note
, 0) = rl
->reg_rtx
;
6909 /* Likewise for a SUBREG of an operand that dies. */
6910 else if (GET_CODE (old
) == SUBREG
6911 && GET_CODE (SUBREG_REG (old
)) == REG
6912 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
6915 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
6919 else if (GET_CODE (old
) == SCRATCH
)
6920 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6921 but we don't want to make an output reload. */
6924 /* If is a JUMP_INSN, we can't support output reloads yet. */
6925 if (GET_CODE (insn
) == JUMP_INSN
)
6928 emit_output_reload_insns (chain
, rld
+ j
, j
);
6931 /* Output insns to reload values in and out of the chosen reload regs. */
6934 emit_reload_insns (chain
)
6935 struct insn_chain
*chain
;
6937 rtx insn
= chain
->insn
;
6940 rtx following_insn
= NEXT_INSN (insn
);
6941 rtx before_insn
= PREV_INSN (insn
);
6943 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6945 for (j
= 0; j
< reload_n_operands
; j
++)
6946 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6947 = inpaddr_address_reload_insns
[j
]
6948 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6949 = outaddr_address_reload_insns
[j
]
6950 = other_output_reload_insns
[j
] = 0;
6951 other_input_address_reload_insns
= 0;
6952 other_input_reload_insns
= 0;
6953 operand_reload_insns
= 0;
6954 other_operand_reload_insns
= 0;
6956 /* Dump reloads into the dump file. */
6959 fprintf (rtl_dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
6960 debug_reload_to_stream (rtl_dump_file
);
6963 /* Now output the instructions to copy the data into and out of the
6964 reload registers. Do these in the order that the reloads were reported,
6965 since reloads of base and index registers precede reloads of operands
6966 and the operands may need the base and index registers reloaded. */
6968 for (j
= 0; j
< n_reloads
; j
++)
6971 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6972 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
6974 do_input_reload (chain
, rld
+ j
, j
);
6975 do_output_reload (chain
, rld
+ j
, j
);
6978 /* Now write all the insns we made for reloads in the order expected by
6979 the allocation functions. Prior to the insn being reloaded, we write
6980 the following reloads:
6982 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6984 RELOAD_OTHER reloads.
6986 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6987 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6988 RELOAD_FOR_INPUT reload for the operand.
6990 RELOAD_FOR_OPADDR_ADDRS reloads.
6992 RELOAD_FOR_OPERAND_ADDRESS reloads.
6994 After the insn being reloaded, we write the following:
6996 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6997 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6998 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6999 reloads for the operand. The RELOAD_OTHER output reloads are
7000 output in descending order by reload number. */
7002 emit_insns_before (other_input_address_reload_insns
, insn
);
7003 emit_insns_before (other_input_reload_insns
, insn
);
7005 for (j
= 0; j
< reload_n_operands
; j
++)
7007 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
7008 emit_insns_before (input_address_reload_insns
[j
], insn
);
7009 emit_insns_before (input_reload_insns
[j
], insn
);
7012 emit_insns_before (other_operand_reload_insns
, insn
);
7013 emit_insns_before (operand_reload_insns
, insn
);
7015 for (j
= 0; j
< reload_n_operands
; j
++)
7017 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7018 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7019 emit_insns_before (output_reload_insns
[j
], following_insn
);
7020 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7023 /* Keep basic block info up to date. */
7026 if (BLOCK_HEAD (chain
->block
) == insn
)
7027 BLOCK_HEAD (chain
->block
) = NEXT_INSN (before_insn
);
7028 if (BLOCK_END (chain
->block
) == insn
)
7029 BLOCK_END (chain
->block
) = PREV_INSN (following_insn
);
7032 /* For all the spill regs newly reloaded in this instruction,
7033 record what they were reloaded from, so subsequent instructions
7034 can inherit the reloads.
7036 Update spill_reg_store for the reloads of this insn.
7037 Copy the elements that were updated in the loop above. */
7039 for (j
= 0; j
< n_reloads
; j
++)
7041 register int r
= reload_order
[j
];
7042 register int i
= reload_spill_index
[r
];
7044 /* If this is a non-inherited input reload from a pseudo, we must
7045 clear any memory of a previous store to the same pseudo. Only do
7046 something if there will not be an output reload for the pseudo
7048 if (rld
[r
].in_reg
!= 0
7049 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7051 rtx reg
= rld
[r
].in_reg
;
7053 if (GET_CODE (reg
) == SUBREG
)
7054 reg
= SUBREG_REG (reg
);
7056 if (GET_CODE (reg
) == REG
7057 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7058 && ! reg_has_output_reload
[REGNO (reg
)])
7060 int nregno
= REGNO (reg
);
7062 if (reg_last_reload_reg
[nregno
])
7064 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7066 if (reg_reloaded_contents
[last_regno
] == nregno
)
7067 spill_reg_store
[last_regno
] = 0;
7072 /* I is nonneg if this reload used a register.
7073 If rld[r].reg_rtx is 0, this is an optional reload
7074 that we opted to ignore. */
7076 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7078 int nr
= HARD_REGNO_NREGS (i
, GET_MODE (rld
[r
].reg_rtx
));
7080 int part_reaches_end
= 0;
7081 int all_reaches_end
= 1;
7083 /* For a multi register reload, we need to check if all or part
7084 of the value lives to the end. */
7085 for (k
= 0; k
< nr
; k
++)
7087 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7088 rld
[r
].when_needed
))
7089 part_reaches_end
= 1;
7091 all_reaches_end
= 0;
7094 /* Ignore reloads that don't reach the end of the insn in
7096 if (all_reaches_end
)
7098 /* First, clear out memory of what used to be in this spill reg.
7099 If consecutive registers are used, clear them all. */
7101 for (k
= 0; k
< nr
; k
++)
7102 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7104 /* Maybe the spill reg contains a copy of reload_out. */
7106 && (GET_CODE (rld
[r
].out
) == REG
7110 || GET_CODE (rld
[r
].out_reg
) == REG
))
7112 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7116 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7117 register int nregno
= REGNO (out
);
7118 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7119 : HARD_REGNO_NREGS (nregno
,
7120 GET_MODE (rld
[r
].reg_rtx
)));
7122 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7123 spill_reg_stored_to
[i
] = out
;
7124 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7126 /* If NREGNO is a hard register, it may occupy more than
7127 one register. If it does, say what is in the
7128 rest of the registers assuming that both registers
7129 agree on how many words the object takes. If not,
7130 invalidate the subsequent registers. */
7132 if (nregno
< FIRST_PSEUDO_REGISTER
)
7133 for (k
= 1; k
< nnr
; k
++)
7134 reg_last_reload_reg
[nregno
+ k
]
7136 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
7137 REGNO (rld
[r
].reg_rtx
) + k
)
7140 /* Now do the inverse operation. */
7141 for (k
= 0; k
< nr
; k
++)
7143 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7144 reg_reloaded_contents
[i
+ k
]
7145 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7148 reg_reloaded_insn
[i
+ k
] = insn
;
7149 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7153 /* Maybe the spill reg contains a copy of reload_in. Only do
7154 something if there will not be an output reload for
7155 the register being reloaded. */
7156 else if (rld
[r
].out_reg
== 0
7158 && ((GET_CODE (rld
[r
].in
) == REG
7159 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7160 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7161 || (GET_CODE (rld
[r
].in_reg
) == REG
7162 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7163 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7165 register int nregno
;
7168 if (GET_CODE (rld
[r
].in
) == REG
7169 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7170 nregno
= REGNO (rld
[r
].in
);
7171 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
7172 nregno
= REGNO (rld
[r
].in_reg
);
7174 nregno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
7176 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7177 : HARD_REGNO_NREGS (nregno
,
7178 GET_MODE (rld
[r
].reg_rtx
)));
7180 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7182 if (nregno
< FIRST_PSEUDO_REGISTER
)
7183 for (k
= 1; k
< nnr
; k
++)
7184 reg_last_reload_reg
[nregno
+ k
]
7186 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
7187 REGNO (rld
[r
].reg_rtx
) + k
)
7190 /* Unless we inherited this reload, show we haven't
7191 recently done a store.
7192 Previous stores of inherited auto_inc expressions
7193 also have to be discarded. */
7194 if (! reload_inherited
[r
]
7195 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7196 spill_reg_store
[i
] = 0;
7198 for (k
= 0; k
< nr
; k
++)
7200 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7201 reg_reloaded_contents
[i
+ k
]
7202 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7205 reg_reloaded_insn
[i
+ k
] = insn
;
7206 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7211 /* However, if part of the reload reaches the end, then we must
7212 invalidate the old info for the part that survives to the end. */
7213 else if (part_reaches_end
)
7215 for (k
= 0; k
< nr
; k
++)
7216 if (reload_reg_reaches_end_p (i
+ k
,
7218 rld
[r
].when_needed
))
7219 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7223 /* The following if-statement was #if 0'd in 1.34 (or before...).
7224 It's reenabled in 1.35 because supposedly nothing else
7225 deals with this problem. */
7227 /* If a register gets output-reloaded from a non-spill register,
7228 that invalidates any previous reloaded copy of it.
7229 But forget_old_reloads_1 won't get to see it, because
7230 it thinks only about the original insn. So invalidate it here. */
7231 if (i
< 0 && rld
[r
].out
!= 0
7232 && (GET_CODE (rld
[r
].out
) == REG
7233 || (GET_CODE (rld
[r
].out
) == MEM
7234 && GET_CODE (rld
[r
].out_reg
) == REG
)))
7236 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7237 ? rld
[r
].out
: rld
[r
].out_reg
);
7238 register int nregno
= REGNO (out
);
7239 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7241 rtx src_reg
, store_insn
= NULL_RTX
;
7243 reg_last_reload_reg
[nregno
] = 0;
7245 /* If we can find a hard register that is stored, record
7246 the storing insn so that we may delete this insn with
7247 delete_output_reload. */
7248 src_reg
= rld
[r
].reg_rtx
;
7250 /* If this is an optional reload, try to find the source reg
7251 from an input reload. */
7254 rtx set
= single_set (insn
);
7255 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7259 src_reg
= SET_SRC (set
);
7261 for (k
= 0; k
< n_reloads
; k
++)
7263 if (rld
[k
].in
== src_reg
)
7265 src_reg
= rld
[k
].reg_rtx
;
7272 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7273 if (src_reg
&& GET_CODE (src_reg
) == REG
7274 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7276 int src_regno
= REGNO (src_reg
);
7277 int nr
= HARD_REGNO_NREGS (src_regno
, rld
[r
].mode
);
7278 /* The place where to find a death note varies with
7279 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7280 necessarily checked exactly in the code that moves
7281 notes, so just check both locations. */
7282 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7284 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7287 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7288 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7289 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7290 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7291 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7292 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7293 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7295 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7297 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7299 reg_last_reload_reg
[nregno
] = src_reg
;
7304 int num_regs
= HARD_REGNO_NREGS (nregno
, GET_MODE (rld
[r
].out
));
7306 while (num_regs
-- > 0)
7307 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7311 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7314 /* Emit code to perform a reload from IN (which may be a reload register) to
7315 OUT (which may also be a reload register). IN or OUT is from operand
7316 OPNUM with reload type TYPE.
7318 Returns first insn emitted. */
7321 gen_reload (out
, in
, opnum
, type
)
7325 enum reload_type type
;
7327 rtx last
= get_last_insn ();
7330 /* If IN is a paradoxical SUBREG, remove it and try to put the
7331 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7332 if (GET_CODE (in
) == SUBREG
7333 && (GET_MODE_SIZE (GET_MODE (in
))
7334 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7335 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7336 in
= SUBREG_REG (in
), out
= tem
;
7337 else if (GET_CODE (out
) == SUBREG
7338 && (GET_MODE_SIZE (GET_MODE (out
))
7339 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7340 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7341 out
= SUBREG_REG (out
), in
= tem
;
7343 /* How to do this reload can get quite tricky. Normally, we are being
7344 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7345 register that didn't get a hard register. In that case we can just
7346 call emit_move_insn.
7348 We can also be asked to reload a PLUS that adds a register or a MEM to
7349 another register, constant or MEM. This can occur during frame pointer
7350 elimination and while reloading addresses. This case is handled by
7351 trying to emit a single insn to perform the add. If it is not valid,
7352 we use a two insn sequence.
7354 Finally, we could be called to handle an 'o' constraint by putting
7355 an address into a register. In that case, we first try to do this
7356 with a named pattern of "reload_load_address". If no such pattern
7357 exists, we just emit a SET insn and hope for the best (it will normally
7358 be valid on machines that use 'o').
7360 This entire process is made complex because reload will never
7361 process the insns we generate here and so we must ensure that
7362 they will fit their constraints and also by the fact that parts of
7363 IN might be being reloaded separately and replaced with spill registers.
7364 Because of this, we are, in some sense, just guessing the right approach
7365 here. The one listed above seems to work.
7367 ??? At some point, this whole thing needs to be rethought. */
7369 if (GET_CODE (in
) == PLUS
7370 && (GET_CODE (XEXP (in
, 0)) == REG
7371 || GET_CODE (XEXP (in
, 0)) == SUBREG
7372 || GET_CODE (XEXP (in
, 0)) == MEM
)
7373 && (GET_CODE (XEXP (in
, 1)) == REG
7374 || GET_CODE (XEXP (in
, 1)) == SUBREG
7375 || CONSTANT_P (XEXP (in
, 1))
7376 || GET_CODE (XEXP (in
, 1)) == MEM
))
7378 /* We need to compute the sum of a register or a MEM and another
7379 register, constant, or MEM, and put it into the reload
7380 register. The best possible way of doing this is if the machine
7381 has a three-operand ADD insn that accepts the required operands.
7383 The simplest approach is to try to generate such an insn and see if it
7384 is recognized and matches its constraints. If so, it can be used.
7386 It might be better not to actually emit the insn unless it is valid,
7387 but we need to pass the insn as an operand to `recog' and
7388 `extract_insn' and it is simpler to emit and then delete the insn if
7389 not valid than to dummy things up. */
7391 rtx op0
, op1
, tem
, insn
;
7394 op0
= find_replacement (&XEXP (in
, 0));
7395 op1
= find_replacement (&XEXP (in
, 1));
7397 /* Since constraint checking is strict, commutativity won't be
7398 checked, so we need to do that here to avoid spurious failure
7399 if the add instruction is two-address and the second operand
7400 of the add is the same as the reload reg, which is frequently
7401 the case. If the insn would be A = B + A, rearrange it so
7402 it will be A = A + B as constrain_operands expects. */
7404 if (GET_CODE (XEXP (in
, 1)) == REG
7405 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7406 tem
= op0
, op0
= op1
, op1
= tem
;
7408 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7409 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7411 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7412 code
= recog_memoized (insn
);
7416 extract_insn (insn
);
7417 /* We want constrain operands to treat this insn strictly in
7418 its validity determination, i.e., the way it would after reload
7420 if (constrain_operands (1))
7424 delete_insns_since (last
);
7426 /* If that failed, we must use a conservative two-insn sequence.
7428 Use a move to copy one operand into the reload register. Prefer
7429 to reload a constant, MEM or pseudo since the move patterns can
7430 handle an arbitrary operand. If OP1 is not a constant, MEM or
7431 pseudo and OP1 is not a valid operand for an add instruction, then
7434 After reloading one of the operands into the reload register, add
7435 the reload register to the output register.
7437 If there is another way to do this for a specific machine, a
7438 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7441 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7443 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7444 || (GET_CODE (op1
) == REG
7445 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7446 || (code
!= CODE_FOR_nothing
7447 && ! ((*insn_data
[code
].operand
[2].predicate
)
7448 (op1
, insn_data
[code
].operand
[2].mode
))))
7449 tem
= op0
, op0
= op1
, op1
= tem
;
7451 gen_reload (out
, op0
, opnum
, type
);
7453 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7454 This fixes a problem on the 32K where the stack pointer cannot
7455 be used as an operand of an add insn. */
7457 if (rtx_equal_p (op0
, op1
))
7460 insn
= emit_insn (gen_add2_insn (out
, op1
));
7462 /* If that failed, copy the address register to the reload register.
7463 Then add the constant to the reload register. */
7465 code
= recog_memoized (insn
);
7469 extract_insn (insn
);
7470 /* We want constrain operands to treat this insn strictly in
7471 its validity determination, i.e., the way it would after reload
7473 if (constrain_operands (1))
7475 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7477 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7482 delete_insns_since (last
);
7484 gen_reload (out
, op1
, opnum
, type
);
7485 insn
= emit_insn (gen_add2_insn (out
, op0
));
7486 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7489 #ifdef SECONDARY_MEMORY_NEEDED
7490 /* If we need a memory location to do the move, do it that way. */
7491 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7492 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7493 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7494 REGNO_REG_CLASS (REGNO (out
)),
7497 /* Get the memory to use and rewrite both registers to its mode. */
7498 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7500 if (GET_MODE (loc
) != GET_MODE (out
))
7501 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7503 if (GET_MODE (loc
) != GET_MODE (in
))
7504 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7506 gen_reload (loc
, in
, opnum
, type
);
7507 gen_reload (out
, loc
, opnum
, type
);
7511 /* If IN is a simple operand, use gen_move_insn. */
7512 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7513 emit_insn (gen_move_insn (out
, in
));
7515 #ifdef HAVE_reload_load_address
7516 else if (HAVE_reload_load_address
)
7517 emit_insn (gen_reload_load_address (out
, in
));
7520 /* Otherwise, just write (set OUT IN) and hope for the best. */
7522 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7524 /* Return the first insn emitted.
7525 We can not just return get_last_insn, because there may have
7526 been multiple instructions emitted. Also note that gen_move_insn may
7527 emit more than one insn itself, so we can not assume that there is one
7528 insn emitted per emit_insn_before call. */
7530 return last
? NEXT_INSN (last
) : get_insns ();
7533 /* Delete a previously made output-reload
7534 whose result we now believe is not needed.
7535 First we double-check.
7537 INSN is the insn now being processed.
7538 LAST_RELOAD_REG is the hard register number for which we want to delete
7539 the last output reload.
7540 J is the reload-number that originally used REG. The caller has made
7541 certain that reload J doesn't use REG any longer for input. */
7544 delete_output_reload (insn
, j
, last_reload_reg
)
7547 int last_reload_reg
;
7549 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7550 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7553 int n_inherited
= 0;
7557 /* Get the raw pseudo-register referred to. */
7559 while (GET_CODE (reg
) == SUBREG
)
7560 reg
= SUBREG_REG (reg
);
7561 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7563 /* This is unsafe if the operand occurs more often in the current
7564 insn than it is inherited. */
7565 for (k
= n_reloads
- 1; k
>= 0; k
--)
7567 rtx reg2
= rld
[k
].in
;
7570 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7571 reg2
= rld
[k
].in_reg
;
7573 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7574 reg2
= XEXP (rld
[k
].in_reg
, 0);
7576 while (GET_CODE (reg2
) == SUBREG
)
7577 reg2
= SUBREG_REG (reg2
);
7578 if (rtx_equal_p (reg2
, reg
))
7580 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7583 reg2
= rld
[k
].out_reg
;
7586 while (GET_CODE (reg2
) == SUBREG
)
7587 reg2
= XEXP (reg2
, 0);
7588 if (rtx_equal_p (reg2
, reg
))
7595 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7597 n_occurrences
+= count_occurrences (PATTERN (insn
), substed
, 0);
7598 if (n_occurrences
> n_inherited
)
7601 /* If the pseudo-reg we are reloading is no longer referenced
7602 anywhere between the store into it and here,
7603 and no jumps or labels intervene, then the value can get
7604 here through the reload reg alone.
7605 Otherwise, give up--return. */
7606 for (i1
= NEXT_INSN (output_reload_insn
);
7607 i1
!= insn
; i1
= NEXT_INSN (i1
))
7609 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7611 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7612 && reg_mentioned_p (reg
, PATTERN (i1
)))
7614 /* If this is USE in front of INSN, we only have to check that
7615 there are no more references than accounted for by inheritance. */
7616 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7618 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7619 i1
= NEXT_INSN (i1
);
7621 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7627 /* The caller has already checked that REG dies or is set in INSN.
7628 It has also checked that we are optimizing, and thus some inaccurancies
7629 in the debugging information are acceptable.
7630 So we could just delete output_reload_insn.
7631 But in some cases we can improve the debugging information without
7632 sacrificing optimization - maybe even improving the code:
7633 See if the pseudo reg has been completely replaced
7634 with reload regs. If so, delete the store insn
7635 and forget we had a stack slot for the pseudo. */
7636 if (rld
[j
].out
!= rld
[j
].in
7637 && REG_N_DEATHS (REGNO (reg
)) == 1
7638 && REG_N_SETS (REGNO (reg
)) == 1
7639 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7640 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7644 /* We know that it was used only between here
7645 and the beginning of the current basic block.
7646 (We also know that the last use before INSN was
7647 the output reload we are thinking of deleting, but never mind that.)
7648 Search that range; see if any ref remains. */
7649 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7651 rtx set
= single_set (i2
);
7653 /* Uses which just store in the pseudo don't count,
7654 since if they are the only uses, they are dead. */
7655 if (set
!= 0 && SET_DEST (set
) == reg
)
7657 if (GET_CODE (i2
) == CODE_LABEL
7658 || GET_CODE (i2
) == JUMP_INSN
)
7660 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7661 && reg_mentioned_p (reg
, PATTERN (i2
)))
7663 /* Some other ref remains; just delete the output reload we
7665 delete_address_reloads (output_reload_insn
, insn
);
7666 PUT_CODE (output_reload_insn
, NOTE
);
7667 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7668 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7673 /* Delete the now-dead stores into this pseudo. */
7674 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7676 rtx set
= single_set (i2
);
7678 if (set
!= 0 && SET_DEST (set
) == reg
)
7680 delete_address_reloads (i2
, insn
);
7681 /* This might be a basic block head,
7682 thus don't use delete_insn. */
7683 PUT_CODE (i2
, NOTE
);
7684 NOTE_SOURCE_FILE (i2
) = 0;
7685 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
7687 if (GET_CODE (i2
) == CODE_LABEL
7688 || GET_CODE (i2
) == JUMP_INSN
)
7692 /* For the debugging info,
7693 say the pseudo lives in this reload reg. */
7694 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7695 alter_reg (REGNO (reg
), -1);
7697 delete_address_reloads (output_reload_insn
, insn
);
7698 PUT_CODE (output_reload_insn
, NOTE
);
7699 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7700 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7704 /* We are going to delete DEAD_INSN. Recursively delete loads of
7705 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7706 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7708 delete_address_reloads (dead_insn
, current_insn
)
7709 rtx dead_insn
, current_insn
;
7711 rtx set
= single_set (dead_insn
);
7712 rtx set2
, dst
, prev
, next
;
7715 rtx dst
= SET_DEST (set
);
7716 if (GET_CODE (dst
) == MEM
)
7717 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7719 /* If we deleted the store from a reloaded post_{in,de}c expression,
7720 we can delete the matching adds. */
7721 prev
= PREV_INSN (dead_insn
);
7722 next
= NEXT_INSN (dead_insn
);
7723 if (! prev
|| ! next
)
7725 set
= single_set (next
);
7726 set2
= single_set (prev
);
7728 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7729 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7730 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7732 dst
= SET_DEST (set
);
7733 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7734 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7735 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7736 || (INTVAL (XEXP (SET_SRC (set
), 1))
7737 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7743 /* Subfunction of delete_address_reloads: process registers found in X. */
7745 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
7746 rtx dead_insn
, x
, current_insn
;
7748 rtx prev
, set
, dst
, i2
;
7750 enum rtx_code code
= GET_CODE (x
);
7754 const char *fmt
= GET_RTX_FORMAT (code
);
7755 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7758 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7759 else if (fmt
[i
] == 'E')
7761 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7762 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7769 if (spill_reg_order
[REGNO (x
)] < 0)
7772 /* Scan backwards for the insn that sets x. This might be a way back due
7774 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7776 code
= GET_CODE (prev
);
7777 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7779 if (GET_RTX_CLASS (code
) != 'i')
7781 if (reg_set_p (x
, PATTERN (prev
)))
7783 if (reg_referenced_p (x
, PATTERN (prev
)))
7786 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7788 /* Check that PREV only sets the reload register. */
7789 set
= single_set (prev
);
7792 dst
= SET_DEST (set
);
7793 if (GET_CODE (dst
) != REG
7794 || ! rtx_equal_p (dst
, x
))
7796 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7798 /* Check if DST was used in a later insn -
7799 it might have been inherited. */
7800 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7802 if (GET_CODE (i2
) == CODE_LABEL
)
7806 if (reg_referenced_p (dst
, PATTERN (i2
)))
7808 /* If there is a reference to the register in the current insn,
7809 it might be loaded in a non-inherited reload. If no other
7810 reload uses it, that means the register is set before
7812 if (i2
== current_insn
)
7814 for (j
= n_reloads
- 1; j
>= 0; j
--)
7815 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7816 || reload_override_in
[j
] == dst
)
7818 for (j
= n_reloads
- 1; j
>= 0; j
--)
7819 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
7826 if (GET_CODE (i2
) == JUMP_INSN
)
7828 /* If DST is still live at CURRENT_INSN, check if it is used for
7829 any reload. Note that even if CURRENT_INSN sets DST, we still
7830 have to check the reloads. */
7831 if (i2
== current_insn
)
7833 for (j
= n_reloads
- 1; j
>= 0; j
--)
7834 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7835 || reload_override_in
[j
] == dst
)
7837 /* ??? We can't finish the loop here, because dst might be
7838 allocated to a pseudo in this block if no reload in this
7839 block needs any of the clsses containing DST - see
7840 spill_hard_reg. There is no easy way to tell this, so we
7841 have to scan till the end of the basic block. */
7843 if (reg_set_p (dst
, PATTERN (i2
)))
7847 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
7848 reg_reloaded_contents
[REGNO (dst
)] = -1;
7849 /* Can't use delete_insn here because PREV might be a basic block head. */
7850 PUT_CODE (prev
, NOTE
);
7851 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
7852 NOTE_SOURCE_FILE (prev
) = 0;
7855 /* Output reload-insns to reload VALUE into RELOADREG.
7856 VALUE is an autoincrement or autodecrement RTX whose operand
7857 is a register or memory location;
7858 so reloading involves incrementing that location.
7859 IN is either identical to VALUE, or some cheaper place to reload from.
7861 INC_AMOUNT is the number to increment or decrement by (always positive).
7862 This cannot be deduced from VALUE.
7864 Return the instruction that stores into RELOADREG. */
7867 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
7872 /* REG or MEM to be copied and incremented. */
7873 rtx incloc
= XEXP (value
, 0);
7874 /* Nonzero if increment after copying. */
7875 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7881 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
7883 /* No hard register is equivalent to this register after
7884 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7885 we could inc/dec that register as well (maybe even using it for
7886 the source), but I'm not sure it's worth worrying about. */
7887 if (GET_CODE (incloc
) == REG
)
7888 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7890 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7891 inc_amount
= -inc_amount
;
7893 inc
= GEN_INT (inc_amount
);
7895 /* If this is post-increment, first copy the location to the reload reg. */
7896 if (post
&& real_in
!= reloadreg
)
7897 emit_insn (gen_move_insn (reloadreg
, real_in
));
7901 /* See if we can directly increment INCLOC. Use a method similar to
7902 that in gen_reload. */
7904 last
= get_last_insn ();
7905 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7906 gen_rtx_PLUS (GET_MODE (incloc
),
7909 code
= recog_memoized (add_insn
);
7912 extract_insn (add_insn
);
7913 if (constrain_operands (1))
7915 /* If this is a pre-increment and we have incremented the value
7916 where it lives, copy the incremented value to RELOADREG to
7917 be used as an address. */
7920 emit_insn (gen_move_insn (reloadreg
, incloc
));
7925 delete_insns_since (last
);
7928 /* If couldn't do the increment directly, must increment in RELOADREG.
7929 The way we do this depends on whether this is pre- or post-increment.
7930 For pre-increment, copy INCLOC to the reload register, increment it
7931 there, then save back. */
7935 if (in
!= reloadreg
)
7936 emit_insn (gen_move_insn (reloadreg
, real_in
));
7937 emit_insn (gen_add2_insn (reloadreg
, inc
));
7938 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7943 Because this might be a jump insn or a compare, and because RELOADREG
7944 may not be available after the insn in an input reload, we must do
7945 the incrementation before the insn being reloaded for.
7947 We have already copied IN to RELOADREG. Increment the copy in
7948 RELOADREG, save that back, then decrement RELOADREG so it has
7949 the original value. */
7951 emit_insn (gen_add2_insn (reloadreg
, inc
));
7952 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7953 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
7959 /* Return 1 if we are certain that the constraint-string STRING allows
7960 the hard register REG. Return 0 if we can't be sure of this. */
7963 constraint_accepts_reg_p (string
, reg
)
7968 int regno
= true_regnum (reg
);
7971 /* Initialize for first alternative. */
7973 /* Check that each alternative contains `g' or `r'. */
7975 switch (c
= *string
++)
7978 /* If an alternative lacks `g' or `r', we lose. */
7981 /* If an alternative lacks `g' or `r', we lose. */
7984 /* Initialize for next alternative. */
7989 /* Any general reg wins for this alternative. */
7990 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
7994 /* Any reg in specified class wins for this alternative. */
7996 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
7998 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
8004 /* INSN is a no-op; delete it.
8005 If this sets the return value of the function, we must keep a USE around,
8006 in case this is in a different basic block than the final USE. Otherwise,
8007 we could loose important register lifeness information on
8008 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8009 spills: subsequent passes assume that spill registers are dead at the end
8011 VALUE must be the return value in such a case, NULL otherwise. */
8013 reload_cse_delete_noop_set (insn
, value
)
8018 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8019 INSN_CODE (insn
) = -1;
8020 REG_NOTES (insn
) = NULL_RTX
;
8024 PUT_CODE (insn
, NOTE
);
8025 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8026 NOTE_SOURCE_FILE (insn
) = 0;
8030 /* See whether a single set SET is a noop. */
8032 reload_cse_noop_set_p (set
)
8035 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
8038 /* Try to simplify INSN. */
8040 reload_cse_simplify (insn
)
8043 rtx body
= PATTERN (insn
);
8045 if (GET_CODE (body
) == SET
)
8049 /* Simplify even if we may think it is a no-op.
8050 We may think a memory load of a value smaller than WORD_SIZE
8051 is redundant because we haven't taken into account possible
8052 implicit extension. reload_cse_simplify_set() will bring
8053 this out, so it's safer to simplify before we delete. */
8054 count
+= reload_cse_simplify_set (body
, insn
);
8056 if (!count
&& reload_cse_noop_set_p (body
))
8058 rtx value
= SET_DEST (body
);
8059 if (! REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8061 reload_cse_delete_noop_set (insn
, value
);
8066 apply_change_group ();
8068 reload_cse_simplify_operands (insn
);
8070 else if (GET_CODE (body
) == PARALLEL
)
8074 rtx value
= NULL_RTX
;
8076 /* If every action in a PARALLEL is a noop, we can delete
8077 the entire PARALLEL. */
8078 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8080 rtx part
= XVECEXP (body
, 0, i
);
8081 if (GET_CODE (part
) == SET
)
8083 if (! reload_cse_noop_set_p (part
))
8085 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8089 value
= SET_DEST (part
);
8092 else if (GET_CODE (part
) != CLOBBER
)
8098 reload_cse_delete_noop_set (insn
, value
);
8099 /* We're done with this insn. */
8103 /* It's not a no-op, but we can try to simplify it. */
8104 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8105 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8106 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8109 apply_change_group ();
8111 reload_cse_simplify_operands (insn
);
8115 /* Do a very simple CSE pass over the hard registers.
8117 This function detects no-op moves where we happened to assign two
8118 different pseudo-registers to the same hard register, and then
8119 copied one to the other. Reload will generate a useless
8120 instruction copying a register to itself.
8122 This function also detects cases where we load a value from memory
8123 into two different registers, and (if memory is more expensive than
8124 registers) changes it to simply copy the first register into the
8127 Another optimization is performed that scans the operands of each
8128 instruction to see whether the value is already available in a
8129 hard register. It then replaces the operand with the hard register
8130 if possible, much like an optional reload would. */
8133 reload_cse_regs_1 (first
)
8139 init_alias_analysis ();
8141 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8144 reload_cse_simplify (insn
);
8146 cselib_process_insn (insn
);
8150 end_alias_analysis ();
8154 /* Call cse / combine like post-reload optimization phases.
8155 FIRST is the first instruction. */
8157 reload_cse_regs (first
)
8160 reload_cse_regs_1 (first
);
8162 reload_cse_move2add (first
);
8163 if (flag_expensive_optimizations
)
8164 reload_cse_regs_1 (first
);
8167 /* Try to simplify a single SET instruction. SET is the set pattern.
8168 INSN is the instruction it came from.
8169 This function only handles one case: if we set a register to a value
8170 which is not a register, we try to find that value in some other register
8171 and change the set into a register copy. */
8174 reload_cse_simplify_set (set
, insn
)
8181 enum reg_class dclass
;
8184 struct elt_loc_list
*l
;
8185 #ifdef LOAD_EXTEND_OP
8186 enum rtx_code extend_op
= NIL
;
8189 dreg
= true_regnum (SET_DEST (set
));
8193 src
= SET_SRC (set
);
8194 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8197 dclass
= REGNO_REG_CLASS (dreg
);
8199 #ifdef LOAD_EXTEND_OP
8200 /* When replacing a memory with a register, we need to honor assumptions
8201 that combine made wrt the contents of sign bits. We'll do this by
8202 generating an extend instruction instead of a reg->reg copy. Thus
8203 the destination must be a register that we can widen. */
8204 if (GET_CODE (src
) == MEM
8205 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
8206 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != NIL
8207 && GET_CODE (SET_DEST (set
)) != REG
)
8211 /* If memory loads are cheaper than register copies, don't change them. */
8212 if (GET_CODE (src
) == MEM
)
8213 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
8214 else if (CONSTANT_P (src
))
8215 old_cost
= rtx_cost (src
, SET
);
8216 else if (GET_CODE (src
) == REG
)
8217 old_cost
= REGISTER_MOVE_COST (GET_MODE (src
),
8218 REGNO_REG_CLASS (REGNO (src
)), dclass
);
8221 old_cost
= rtx_cost (src
, SET
);
8223 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
8226 for (l
= val
->locs
; l
; l
= l
->next
)
8228 rtx this_rtx
= l
->loc
;
8231 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
8233 #ifdef LOAD_EXTEND_OP
8234 if (extend_op
!= NIL
)
8236 HOST_WIDE_INT this_val
;
8238 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8239 constants, such as SYMBOL_REF, cannot be extended. */
8240 if (GET_CODE (this_rtx
) != CONST_INT
)
8243 this_val
= INTVAL (this_rtx
);
8247 this_val
&= GET_MODE_MASK (GET_MODE (src
));
8250 /* ??? In theory we're already extended. */
8251 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
8256 this_rtx
= GEN_INT (this_val
);
8259 this_cost
= rtx_cost (this_rtx
, SET
);
8261 else if (GET_CODE (this_rtx
) == REG
)
8263 #ifdef LOAD_EXTEND_OP
8264 if (extend_op
!= NIL
)
8266 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
8267 this_cost
= rtx_cost (this_rtx
, SET
);
8271 this_cost
= REGISTER_MOVE_COST (GET_MODE (this_rtx
),
8272 REGNO_REG_CLASS (REGNO (this_rtx
)),
8278 /* If equal costs, prefer registers over anything else. That
8279 tends to lead to smaller instructions on some machines. */
8280 if (this_cost
< old_cost
8281 || (this_cost
== old_cost
8282 && GET_CODE (this_rtx
) == REG
8283 && GET_CODE (SET_SRC (set
)) != REG
))
8285 #ifdef LOAD_EXTEND_OP
8286 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
8287 && extend_op
!= NIL
)
8289 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
8290 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
8291 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
8295 validate_change (insn
, &SET_SRC (set
), copy_rtx (this_rtx
), 1);
8296 old_cost
= this_cost
, did_change
= 1;
8303 /* Try to replace operands in INSN with equivalent values that are already
8304 in registers. This can be viewed as optional reloading.
8306 For each non-register operand in the insn, see if any hard regs are
8307 known to be equivalent to that operand. Record the alternatives which
8308 can accept these hard registers. Among all alternatives, select the
8309 ones which are better or equal to the one currently matching, where
8310 "better" is in terms of '?' and '!' constraints. Among the remaining
8311 alternatives, select the one which replaces most operands with
8315 reload_cse_simplify_operands (insn
)
8320 /* For each operand, all registers that are equivalent to it. */
8321 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
8323 const char *constraints
[MAX_RECOG_OPERANDS
];
8325 /* Vector recording how bad an alternative is. */
8326 int *alternative_reject
;
8327 /* Vector recording how many registers can be introduced by choosing
8328 this alternative. */
8329 int *alternative_nregs
;
8330 /* Array of vectors recording, for each operand and each alternative,
8331 which hard register to substitute, or -1 if the operand should be
8333 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
8334 /* Array of alternatives, sorted in order of decreasing desirability. */
8335 int *alternative_order
;
8336 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
8338 extract_insn (insn
);
8340 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
8343 /* Figure out which alternative currently matches. */
8344 if (! constrain_operands (1))
8345 fatal_insn_not_found (insn
);
8347 alternative_reject
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8348 alternative_nregs
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8349 alternative_order
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8350 memset ((char *)alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
8351 memset ((char *)alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
8353 /* For each operand, find out which regs are equivalent. */
8354 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8357 struct elt_loc_list
*l
;
8359 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
8361 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8362 right, so avoid the problem here. Likewise if we have a constant
8363 and the insn pattern doesn't tell us the mode we need. */
8364 if (GET_CODE (recog_data
.operand
[i
]) == CODE_LABEL
8365 || (CONSTANT_P (recog_data
.operand
[i
])
8366 && recog_data
.operand_mode
[i
] == VOIDmode
))
8369 v
= cselib_lookup (recog_data
.operand
[i
], recog_data
.operand_mode
[i
], 0);
8373 for (l
= v
->locs
; l
; l
= l
->next
)
8374 if (GET_CODE (l
->loc
) == REG
)
8375 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
8378 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8380 enum machine_mode mode
;
8384 op_alt_regno
[i
] = (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8385 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
8386 op_alt_regno
[i
][j
] = -1;
8388 p
= constraints
[i
] = recog_data
.constraints
[i
];
8389 mode
= recog_data
.operand_mode
[i
];
8391 /* Add the reject values for each alternative given by the constraints
8392 for this operand. */
8400 alternative_reject
[j
] += 3;
8402 alternative_reject
[j
] += 300;
8405 /* We won't change operands which are already registers. We
8406 also don't want to modify output operands. */
8407 regno
= true_regnum (recog_data
.operand
[i
]);
8409 || constraints
[i
][0] == '='
8410 || constraints
[i
][0] == '+')
8413 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
8415 int class = (int) NO_REGS
;
8417 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
8420 REGNO (reg
) = regno
;
8421 PUT_MODE (reg
, mode
);
8423 /* We found a register equal to this operand. Now look for all
8424 alternatives that can accept this register and have not been
8425 assigned a register they can use yet. */
8434 case '=': case '+': case '?':
8435 case '#': case '&': case '!':
8437 case '0': case '1': case '2': case '3': case '4':
8438 case '5': case '6': case '7': case '8': case '9':
8439 case 'm': case '<': case '>': case 'V': case 'o':
8440 case 'E': case 'F': case 'G': case 'H':
8441 case 's': case 'i': case 'n':
8442 case 'I': case 'J': case 'K': case 'L':
8443 case 'M': case 'N': case 'O': case 'P':
8445 /* These don't say anything we care about. */
8449 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
8454 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
8457 case ',': case '\0':
8458 /* See if REGNO fits this alternative, and set it up as the
8459 replacement register if we don't have one for this
8460 alternative yet and the operand being replaced is not
8461 a cheap CONST_INT. */
8462 if (op_alt_regno
[i
][j
] == -1
8463 && reg_fits_class_p (reg
, class, 0, mode
)
8464 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
8465 || (rtx_cost (recog_data
.operand
[i
], SET
)
8466 > rtx_cost (reg
, SET
))))
8468 alternative_nregs
[j
]++;
8469 op_alt_regno
[i
][j
] = regno
;
8481 /* Record all alternatives which are better or equal to the currently
8482 matching one in the alternative_order array. */
8483 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
8484 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
8485 alternative_order
[j
++] = i
;
8486 recog_data
.n_alternatives
= j
;
8488 /* Sort it. Given a small number of alternatives, a dumb algorithm
8489 won't hurt too much. */
8490 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
8493 int best_reject
= alternative_reject
[alternative_order
[i
]];
8494 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
8497 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
8499 int this_reject
= alternative_reject
[alternative_order
[j
]];
8500 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
8502 if (this_reject
< best_reject
8503 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
8506 best_reject
= this_reject
;
8507 best_nregs
= this_nregs
;
8511 tmp
= alternative_order
[best
];
8512 alternative_order
[best
] = alternative_order
[i
];
8513 alternative_order
[i
] = tmp
;
8516 /* Substitute the operands as determined by op_alt_regno for the best
8518 j
= alternative_order
[0];
8520 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8522 enum machine_mode mode
= recog_data
.operand_mode
[i
];
8523 if (op_alt_regno
[i
][j
] == -1)
8526 validate_change (insn
, recog_data
.operand_loc
[i
],
8527 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
8530 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
8532 int op
= recog_data
.dup_num
[i
];
8533 enum machine_mode mode
= recog_data
.operand_mode
[op
];
8535 if (op_alt_regno
[op
][j
] == -1)
8538 validate_change (insn
, recog_data
.dup_loc
[i
],
8539 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
8542 return apply_change_group ();
8545 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8547 This code might also be useful when reload gave up on reg+reg addresssing
8548 because of clashes between the return register and INDEX_REG_CLASS. */
8550 /* The maximum number of uses of a register we can keep track of to
8551 replace them with reg+reg addressing. */
8552 #define RELOAD_COMBINE_MAX_USES 6
8554 /* INSN is the insn where a register has ben used, and USEP points to the
8555 location of the register within the rtl. */
8556 struct reg_use
{ rtx insn
, *usep
; };
8558 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8559 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8560 indicates where it becomes live again.
8561 Otherwise, USE_INDEX is the index of the last encountered use of the
8562 register (which is first among these we have seen since we scan backwards),
8563 OFFSET contains the constant offset that is added to the register in
8564 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8565 last, of these uses.
8566 STORE_RUID is always meaningful if we only want to use a value in a
8567 register in a different place: it denotes the next insn in the insn
8568 stream (i.e. the last ecountered) that sets or clobbers the register. */
8571 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
8576 } reg_state
[FIRST_PSEUDO_REGISTER
];
8578 /* Reverse linear uid. This is increased in reload_combine while scanning
8579 the instructions from last to first. It is used to set last_label_ruid
8580 and the store_ruid / use_ruid fields in reg_state. */
8581 static int reload_combine_ruid
;
8583 #define LABEL_LIVE(LABEL) \
8584 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8590 int first_index_reg
= -1, last_index_reg
;
8593 int last_label_ruid
;
8594 int min_labelno
, n_labels
;
8595 HARD_REG_SET ever_live_at_start
, *label_live
;
8597 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8598 reload has already used it where appropriate, so there is no use in
8599 trying to generate it now. */
8600 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
8603 /* To avoid wasting too much time later searching for an index register,
8604 determine the minimum and maximum index register numbers. */
8605 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8606 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
8608 if (first_index_reg
== -1)
8609 first_index_reg
= r
;
8614 /* If no index register is available, we can quit now. */
8615 if (first_index_reg
== -1)
8618 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8619 information is a bit fuzzy immediately after reload, but it's
8620 still good enough to determine which registers are live at a jump
8622 min_labelno
= get_first_label_num ();
8623 n_labels
= max_label_num () - min_labelno
;
8624 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
8625 CLEAR_HARD_REG_SET (ever_live_at_start
);
8627 for (i
= n_basic_blocks
- 1; i
>= 0; i
--)
8629 insn
= BLOCK_HEAD (i
);
8630 if (GET_CODE (insn
) == CODE_LABEL
)
8634 REG_SET_TO_HARD_REG_SET (live
,
8635 BASIC_BLOCK (i
)->global_live_at_start
);
8636 compute_use_by_pseudos (&live
,
8637 BASIC_BLOCK (i
)->global_live_at_start
);
8638 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
8639 IOR_HARD_REG_SET (ever_live_at_start
, live
);
8643 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8644 last_label_ruid
= reload_combine_ruid
= 0;
8645 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8647 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8649 reg_state
[r
].use_index
= -1;
8651 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8654 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
8658 /* We cannot do our optimization across labels. Invalidating all the use
8659 information we have would be costly, so we just note where the label
8660 is and then later disable any optimization that would cross it. */
8661 if (GET_CODE (insn
) == CODE_LABEL
)
8662 last_label_ruid
= reload_combine_ruid
;
8663 else if (GET_CODE (insn
) == BARRIER
)
8664 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8665 if (! fixed_regs
[r
])
8666 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8668 if (! INSN_P (insn
))
8671 reload_combine_ruid
++;
8673 /* Look for (set (REGX) (CONST_INT))
8674 (set (REGX) (PLUS (REGX) (REGY)))
8676 ... (MEM (REGX)) ...
8678 (set (REGZ) (CONST_INT))
8680 ... (MEM (PLUS (REGZ) (REGY)))... .
8682 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8683 and that we know all uses of REGX before it dies. */
8684 set
= single_set (insn
);
8686 && GET_CODE (SET_DEST (set
)) == REG
8687 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
8688 GET_MODE (SET_DEST (set
)))
8690 && GET_CODE (SET_SRC (set
)) == PLUS
8691 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
8692 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
8693 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
8695 rtx reg
= SET_DEST (set
);
8696 rtx plus
= SET_SRC (set
);
8697 rtx base
= XEXP (plus
, 1);
8698 rtx prev
= prev_nonnote_insn (insn
);
8699 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
8700 unsigned int regno
= REGNO (reg
);
8701 rtx const_reg
= NULL_RTX
;
8702 rtx reg_sum
= NULL_RTX
;
8704 /* Now, we need an index register.
8705 We'll set index_reg to this index register, const_reg to the
8706 register that is to be loaded with the constant
8707 (denoted as REGZ in the substitution illustration above),
8708 and reg_sum to the register-register that we want to use to
8709 substitute uses of REG (typically in MEMs) with.
8710 First check REG and BASE for being index registers;
8711 we can use them even if they are not dead. */
8712 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
8713 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8721 /* Otherwise, look for a free index register. Since we have
8722 checked above that neiter REG nor BASE are index registers,
8723 if we find anything at all, it will be different from these
8725 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
8727 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8729 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
8730 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
8731 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
8733 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
8735 const_reg
= index_reg
;
8736 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
8742 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8743 (REGY), i.e. BASE, is not clobbered before the last use we'll
8746 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
8747 && rtx_equal_p (SET_DEST (prev_set
), reg
)
8748 && reg_state
[regno
].use_index
>= 0
8749 && (reg_state
[REGNO (base
)].store_ruid
8750 <= reg_state
[regno
].use_ruid
)
8755 /* Change destination register and, if necessary, the
8756 constant value in PREV, the constant loading instruction. */
8757 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
8758 if (reg_state
[regno
].offset
!= const0_rtx
)
8759 validate_change (prev
,
8760 &SET_SRC (prev_set
),
8761 GEN_INT (INTVAL (SET_SRC (prev_set
))
8762 + INTVAL (reg_state
[regno
].offset
)),
8765 /* Now for every use of REG that we have recorded, replace REG
8767 for (i
= reg_state
[regno
].use_index
;
8768 i
< RELOAD_COMBINE_MAX_USES
; i
++)
8769 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
8770 reg_state
[regno
].reg_use
[i
].usep
,
8773 if (apply_change_group ())
8777 /* Delete the reg-reg addition. */
8778 PUT_CODE (insn
, NOTE
);
8779 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8780 NOTE_SOURCE_FILE (insn
) = 0;
8782 if (reg_state
[regno
].offset
!= const0_rtx
)
8783 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8785 for (np
= ®_NOTES (prev
); *np
;)
8787 if (REG_NOTE_KIND (*np
) == REG_EQUAL
8788 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
8789 *np
= XEXP (*np
, 1);
8791 np
= &XEXP (*np
, 1);
8794 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
8795 reg_state
[REGNO (const_reg
)].store_ruid
8796 = reload_combine_ruid
;
8802 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
8804 if (GET_CODE (insn
) == CALL_INSN
)
8808 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8809 if (call_used_regs
[r
])
8811 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8812 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8815 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
8816 link
= XEXP (link
, 1))
8818 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
8819 if (GET_CODE (usage_rtx
) == REG
)
8822 unsigned int start_reg
= REGNO (usage_rtx
);
8823 unsigned int num_regs
=
8824 HARD_REGNO_NREGS (start_reg
, GET_MODE (usage_rtx
));
8825 unsigned int end_reg
= start_reg
+ num_regs
- 1;
8826 for (i
= start_reg
; i
<= end_reg
; i
++)
8827 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
8829 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8830 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8833 reg_state
[i
].use_index
= -1;
8838 else if (GET_CODE (insn
) == JUMP_INSN
8839 && GET_CODE (PATTERN (insn
)) != RETURN
)
8841 /* Non-spill registers might be used at the call destination in
8842 some unknown fashion, so we have to mark the unknown use. */
8845 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
8846 && JUMP_LABEL (insn
))
8847 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
8849 live
= &ever_live_at_start
;
8851 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8852 if (TEST_HARD_REG_BIT (*live
, i
))
8853 reg_state
[i
].use_index
= -1;
8856 reload_combine_note_use (&PATTERN (insn
), insn
);
8857 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
8859 if (REG_NOTE_KIND (note
) == REG_INC
8860 && GET_CODE (XEXP (note
, 0)) == REG
)
8862 int regno
= REGNO (XEXP (note
, 0));
8864 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
8865 reg_state
[regno
].use_index
= -1;
8873 /* Check if DST is a register or a subreg of a register; if it is,
8874 update reg_state[regno].store_ruid and reg_state[regno].use_index
8875 accordingly. Called via note_stores from reload_combine. */
8878 reload_combine_note_store (dst
, set
, data
)
8880 void *data ATTRIBUTE_UNUSED
;
8884 enum machine_mode mode
= GET_MODE (dst
);
8886 if (GET_CODE (dst
) == SUBREG
)
8888 regno
= SUBREG_WORD (dst
);
8889 dst
= SUBREG_REG (dst
);
8891 if (GET_CODE (dst
) != REG
)
8893 regno
+= REGNO (dst
);
8895 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8896 careful with registers / register parts that are not full words.
8898 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8899 if (GET_CODE (set
) != SET
8900 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
8901 || GET_CODE (SET_DEST (set
)) == SIGN_EXTRACT
8902 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
8904 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8906 reg_state
[i
].use_index
= -1;
8907 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8912 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8914 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8915 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8920 /* XP points to a piece of rtl that has to be checked for any uses of
8922 *XP is the pattern of INSN, or a part of it.
8923 Called from reload_combine, and recursively by itself. */
8925 reload_combine_note_use (xp
, insn
)
8929 enum rtx_code code
= x
->code
;
8932 rtx offset
= const0_rtx
; /* For the REG case below. */
8937 if (GET_CODE (SET_DEST (x
)) == REG
)
8939 reload_combine_note_use (&SET_SRC (x
), insn
);
8945 /* If this is the USE of a return value, we can't change it. */
8946 if (GET_CODE (XEXP (x
, 0)) == REG
&& REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
8948 /* Mark the return register as used in an unknown fashion. */
8949 rtx reg
= XEXP (x
, 0);
8950 int regno
= REGNO (reg
);
8951 int nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8953 while (--nregs
>= 0)
8954 reg_state
[regno
+ nregs
].use_index
= -1;
8960 if (GET_CODE (SET_DEST (x
)) == REG
)
8965 /* We are interested in (plus (reg) (const_int)) . */
8966 if (GET_CODE (XEXP (x
, 0)) != REG
8967 || GET_CODE (XEXP (x
, 1)) != CONST_INT
)
8969 offset
= XEXP (x
, 1);
8974 int regno
= REGNO (x
);
8978 /* Some spurious USEs of pseudo registers might remain.
8979 Just ignore them. */
8980 if (regno
>= FIRST_PSEUDO_REGISTER
)
8983 nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8985 /* We can't substitute into multi-hard-reg uses. */
8988 while (--nregs
>= 0)
8989 reg_state
[regno
+ nregs
].use_index
= -1;
8993 /* If this register is already used in some unknown fashion, we
8995 If we decrement the index from zero to -1, we can't store more
8996 uses, so this register becomes used in an unknown fashion. */
8997 use_index
= --reg_state
[regno
].use_index
;
9001 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
9003 /* We have found another use for a register that is already
9004 used later. Check if the offsets match; if not, mark the
9005 register as used in an unknown fashion. */
9006 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
9008 reg_state
[regno
].use_index
= -1;
9014 /* This is the first use of this register we have seen since we
9015 marked it as dead. */
9016 reg_state
[regno
].offset
= offset
;
9017 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
9019 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
9020 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
9028 /* Recursively process the components of X. */
9029 fmt
= GET_RTX_FORMAT (code
);
9030 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9033 reload_combine_note_use (&XEXP (x
, i
), insn
);
9034 else if (fmt
[i
] == 'E')
9036 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9037 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
9042 /* See if we can reduce the cost of a constant by replacing a move
9043 with an add. We track situations in which a register is set to a
9044 constant or to a register plus a constant. */
9045 /* We cannot do our optimization across labels. Invalidating all the
9046 information about register contents we have would be costly, so we
9047 use move2add_last_label_luid to note where the label is and then
9048 later disable any optimization that would cross it.
9049 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9050 reg_set_luid[n] is greater than last_label_luid[n] . */
9051 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
9053 /* If reg_base_reg[n] is negative, register n has been set to
9054 reg_offset[n] in mode reg_mode[n] .
9055 If reg_base_reg[n] is non-negative, register n has been set to the
9056 sum of reg_offset[n] and the value of register reg_base_reg[n]
9057 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9058 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
9059 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
9060 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
9062 /* move2add_luid is linearily increased while scanning the instructions
9063 from first to last. It is used to set reg_set_luid in
9064 reload_cse_move2add and move2add_note_store. */
9065 static int move2add_luid
;
9067 /* move2add_last_label_luid is set whenever a label is found. Labels
9068 invalidate all previously collected reg_offset data. */
9069 static int move2add_last_label_luid
;
9071 /* Generate a CONST_INT and force it in the range of MODE. */
9073 static HOST_WIDE_INT
9074 sext_for_mode (mode
, value
)
9075 enum machine_mode mode
;
9076 HOST_WIDE_INT value
;
9078 HOST_WIDE_INT cval
= value
& GET_MODE_MASK (mode
);
9079 int width
= GET_MODE_BITSIZE (mode
);
9081 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9083 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
9084 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
9085 cval
|= (HOST_WIDE_INT
) -1 << width
;
9090 /* ??? We don't know how zero / sign extension is handled, hence we
9091 can't go from a narrower to a wider mode. */
9092 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9093 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9094 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9095 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9096 GET_MODE_BITSIZE (INMODE))))
9099 reload_cse_move2add (first
)
9105 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9106 reg_set_luid
[i
] = 0;
9108 move2add_last_label_luid
= 0;
9110 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
9114 if (GET_CODE (insn
) == CODE_LABEL
)
9116 move2add_last_label_luid
= move2add_luid
;
9117 /* We're going to increment move2add_luid twice after a
9118 label, so that we can use move2add_last_label_luid + 1 as
9119 the luid for constants. */
9123 if (! INSN_P (insn
))
9125 pat
= PATTERN (insn
);
9126 /* For simplicity, we only perform this optimization on
9127 straightforward SETs. */
9128 if (GET_CODE (pat
) == SET
9129 && GET_CODE (SET_DEST (pat
)) == REG
)
9131 rtx reg
= SET_DEST (pat
);
9132 int regno
= REGNO (reg
);
9133 rtx src
= SET_SRC (pat
);
9135 /* Check if we have valid information on the contents of this
9136 register in the mode of REG. */
9137 if (reg_set_luid
[regno
] > move2add_last_label_luid
9138 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
]))
9140 /* Try to transform (set (REGX) (CONST_INT A))
9142 (set (REGX) (CONST_INT B))
9144 (set (REGX) (CONST_INT A))
9146 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9148 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
9151 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9153 - reg_offset
[regno
]));
9154 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9155 use (set (reg) (reg)) instead.
9156 We don't delete this insn, nor do we convert it into a
9157 note, to avoid losing register notes or the return
9158 value flag. jump2 already knowns how to get rid of
9160 if (new_src
== const0_rtx
)
9161 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
9162 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
9163 && have_add2_insn (GET_MODE (reg
)))
9164 success
= validate_change (insn
, &PATTERN (insn
),
9165 gen_add2_insn (reg
, new_src
), 0);
9166 reg_set_luid
[regno
] = move2add_luid
;
9167 reg_mode
[regno
] = GET_MODE (reg
);
9168 reg_offset
[regno
] = INTVAL (src
);
9172 /* Try to transform (set (REGX) (REGY))
9173 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9176 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9179 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9181 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9182 else if (GET_CODE (src
) == REG
9183 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
9184 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
9185 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
9186 reg_mode
[REGNO (src
)]))
9188 rtx next
= next_nonnote_insn (insn
);
9191 set
= single_set (next
);
9193 && SET_DEST (set
) == reg
9194 && GET_CODE (SET_SRC (set
)) == PLUS
9195 && XEXP (SET_SRC (set
), 0) == reg
9196 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
9198 rtx src3
= XEXP (SET_SRC (set
), 1);
9199 HOST_WIDE_INT added_offset
= INTVAL (src3
);
9200 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
9201 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
9202 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9208 if (new_src
== const0_rtx
)
9209 /* See above why we create (set (reg) (reg)) here. */
9211 = validate_change (next
, &SET_SRC (set
), reg
, 0);
9212 else if ((rtx_cost (new_src
, PLUS
)
9213 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
))
9214 && have_add2_insn (GET_MODE (reg
)))
9216 = validate_change (next
, &PATTERN (next
),
9217 gen_add2_insn (reg
, new_src
), 0);
9220 /* INSN might be the first insn in a basic block
9221 if the preceding insn is a conditional jump
9222 or a possible-throwing call. */
9223 PUT_CODE (insn
, NOTE
);
9224 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9225 NOTE_SOURCE_FILE (insn
) = 0;
9228 reg_mode
[regno
] = GET_MODE (reg
);
9229 reg_offset
[regno
] = sext_for_mode (GET_MODE (reg
),
9238 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9240 if (REG_NOTE_KIND (note
) == REG_INC
9241 && GET_CODE (XEXP (note
, 0)) == REG
)
9243 /* Reset the information about this register. */
9244 int regno
= REGNO (XEXP (note
, 0));
9245 if (regno
< FIRST_PSEUDO_REGISTER
)
9246 reg_set_luid
[regno
] = 0;
9249 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
9250 /* If this is a CALL_INSN, all call used registers are stored with
9252 if (GET_CODE (insn
) == CALL_INSN
)
9254 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9256 if (call_used_regs
[i
])
9257 /* Reset the information about this register. */
9258 reg_set_luid
[i
] = 0;
9264 /* SET is a SET or CLOBBER that sets DST.
9265 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9266 Called from reload_cse_move2add via note_stores. */
9269 move2add_note_store (dst
, set
, data
)
9271 void *data ATTRIBUTE_UNUSED
;
9273 unsigned int regno
= 0;
9275 enum machine_mode mode
= GET_MODE (dst
);
9277 if (GET_CODE (dst
) == SUBREG
)
9279 regno
= SUBREG_WORD (dst
);
9280 dst
= SUBREG_REG (dst
);
9283 /* Some targets do argument pushes without adding REG_INC notes. */
9285 if (GET_CODE (dst
) == MEM
)
9287 dst
= XEXP (dst
, 0);
9288 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_DEC
9289 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
9290 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
9293 if (GET_CODE (dst
) != REG
)
9296 regno
+= REGNO (dst
);
9298 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
9299 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
9300 && GET_CODE (SET_DEST (set
)) != SIGN_EXTRACT
9301 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
9303 rtx src
= SET_SRC (set
);
9305 HOST_WIDE_INT offset
;
9307 /* This may be different from mode, if SET_DEST (set) is a
9309 enum machine_mode dst_mode
= GET_MODE (dst
);
9311 switch (GET_CODE (src
))
9314 if (GET_CODE (XEXP (src
, 0)) == REG
)
9316 base_reg
= XEXP (src
, 0);
9318 if (GET_CODE (XEXP (src
, 1)) == CONST_INT
)
9319 offset
= INTVAL (XEXP (src
, 1));
9320 else if (GET_CODE (XEXP (src
, 1)) == REG
9321 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
9322 > move2add_last_label_luid
)
9323 && (MODES_OK_FOR_MOVE2ADD
9324 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
9326 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
9327 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
9328 /* Maybe the first register is known to be a
9330 else if (reg_set_luid
[REGNO (base_reg
)]
9331 > move2add_last_label_luid
9332 && (MODES_OK_FOR_MOVE2ADD
9333 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
9334 && reg_base_reg
[REGNO (base_reg
)] < 0)
9336 offset
= reg_offset
[REGNO (base_reg
)];
9337 base_reg
= XEXP (src
, 1);
9356 /* Start tracking the register as a constant. */
9357 reg_base_reg
[regno
] = -1;
9358 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
9359 /* We assign the same luid to all registers set to constants. */
9360 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
9361 reg_mode
[regno
] = mode
;
9366 /* Invalidate the contents of the register. */
9367 reg_set_luid
[regno
] = 0;
9371 base_regno
= REGNO (base_reg
);
9372 /* If information about the base register is not valid, set it
9373 up as a new base register, pretending its value is known
9374 starting from the current insn. */
9375 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
9377 reg_base_reg
[base_regno
] = base_regno
;
9378 reg_offset
[base_regno
] = 0;
9379 reg_set_luid
[base_regno
] = move2add_luid
;
9380 reg_mode
[base_regno
] = mode
;
9382 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
9383 reg_mode
[base_regno
]))
9386 reg_mode
[regno
] = mode
;
9388 /* Copy base information from our base register. */
9389 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
9390 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
9392 /* Compute the sum of the offsets or constants. */
9393 reg_offset
[regno
] = sext_for_mode (dst_mode
,
9395 + reg_offset
[base_regno
]);
9399 unsigned int endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
9401 for (i
= regno
; i
< endregno
; i
++)
9402 /* Reset the information about this register. */
9403 reg_set_luid
[i
] = 0;
9409 add_auto_inc_notes (insn
, x
)
9413 enum rtx_code code
= GET_CODE (x
);
9417 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9420 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
9424 /* Scan all the operand sub-expressions. */
9425 fmt
= GET_RTX_FORMAT (code
);
9426 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9429 add_auto_inc_notes (insn
, XEXP (x
, i
));
9430 else if (fmt
[i
] == 'E')
9431 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9432 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));