1 ;; Predicate definitions for Renesas / SuperH SH.
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; TODO: Add a comment here.
23 (define_predicate "trapping_target_operand"
24 (match_code "if_then_else")
26 rtx cond, mem, res, tar, and_expr;
28 if (GET_MODE (op) != PDImode)
34 || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
37 if (!rtx_equal_p (XEXP (mem, 0), tar)
38 || GET_MODE (tar) != Pmode)
40 if (GET_CODE (cond) == CONST)
42 cond = XEXP (cond, 0);
43 if (!satisfies_constraint_Csy (tar))
45 if (GET_CODE (tar) == CONST)
48 else if (!arith_reg_operand (tar, VOIDmode)
49 && ! satisfies_constraint_Csy (tar))
51 if (GET_CODE (cond) != EQ)
53 and_expr = XEXP (cond, 0);
54 return (GET_CODE (and_expr) == AND
55 && rtx_equal_p (XEXP (and_expr, 0), tar)
56 && CONST_INT_P (XEXP (and_expr, 1))
57 && CONST_INT_P (XEXP (cond, 1))
58 && INTVAL (XEXP (and_expr, 1)) == 3
59 && INTVAL (XEXP (cond, 1)) == 3);
62 ;; TODO: Add a comment here.
64 (define_predicate "and_operand"
65 (match_code "subreg,reg,const_int")
67 if (logical_operand (op, mode))
70 /* Check mshflo.l / mshflhi.l opportunities. */
73 && satisfies_constraint_J16 (op))
79 ;; Like arith_reg_dest, but this predicate is defined with
80 ;; define_special_predicate, not define_predicate.
82 (define_special_predicate "any_arith_reg_dest"
83 (match_code "subreg,reg")
85 return arith_reg_dest (op, mode);
88 ;; Like register_operand, but this predicate is defined with
89 ;; define_special_predicate, not define_predicate.
91 (define_special_predicate "any_register_operand"
92 (match_code "subreg,reg")
94 return register_operand (op, mode);
97 ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
99 (define_predicate "arith_operand"
100 (match_code "subreg,reg,const_int,truncate")
102 if (arith_reg_operand (op, mode))
107 /* FIXME: We should be checking whether the CONST_INT fits in a
108 signed 16-bit here, but this causes reload_cse to crash when
109 attempting to transform a sequence of two 64-bit sets of the
110 same register from literal constants into a set and an add,
111 when the difference is too wide for an add. */
113 || satisfies_constraint_Css (op))
115 else if (GET_CODE (op) == TRUNCATE
116 && REG_P (XEXP (op, 0))
117 && ! system_reg_operand (XEXP (op, 0), VOIDmode)
118 && (mode == VOIDmode || mode == GET_MODE (op))
119 && (GET_MODE_SIZE (GET_MODE (op))
120 < GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
121 && (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
122 || GET_MODE_SIZE (GET_MODE (op)) == 4))
123 return register_operand (XEXP (op, 0), VOIDmode);
127 else if (satisfies_constraint_I08 (op))
133 ;; Like above, but for DImode destinations: forbid paradoxical DImode
134 ;; subregs, because this would lead to missing sign extensions when
135 ;; truncating from DImode to SImode.
137 (define_predicate "arith_reg_dest"
138 (match_code "subreg,reg")
140 if (mode == DImode && GET_CODE (op) == SUBREG
141 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
144 return arith_reg_operand (op, mode);
147 ;; Returns 1 if OP is a normal arithmetic register.
149 (define_predicate "arith_reg_operand"
150 (match_code "subreg,reg,sign_extend")
152 if (register_operand (op, mode))
158 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
159 regno = REGNO (SUBREG_REG (op));
163 return (regno != T_REG && regno != PR_REG
164 && ! TARGET_REGISTER_P (regno)
165 && (regno != FPUL_REG || TARGET_SH4)
166 && regno != MACH_REG && regno != MACL_REG);
168 /* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
169 We allow SImode here, as not using an FP register is just a matter of
170 proper register allocation. */
172 && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
173 && GET_MODE (XEXP (op, 0)) == SImode
174 && GET_CODE (XEXP (op, 0)) != SUBREG)
175 return register_operand (XEXP (op, 0), VOIDmode);
176 #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
177 if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
178 && GET_MODE (XEXP (op, 0)) == HImode
179 && REG_P (XEXP (op, 0))
180 && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
181 return register_operand (XEXP (op, 0), VOIDmode);
183 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
184 && GET_CODE (op) == SUBREG
185 && GET_MODE (SUBREG_REG (op)) == DImode
186 && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
187 && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
188 && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
189 return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
193 ;; Returns 1 if OP is a valid source operand for a compare insn.
195 (define_predicate "arith_reg_or_0_operand"
196 (match_code "subreg,reg,const_int,const_vector")
198 if (arith_reg_operand (op, mode))
201 if (satisfies_constraint_Z (op))
207 ;; TODO: Add a comment here.
209 (define_predicate "binary_float_operator"
210 (and (match_code "plus,minus,mult,div")
211 (match_test "GET_MODE (op) == mode")))
213 ;; TODO: Add a comment here.
215 (define_predicate "binary_logical_operator"
216 (and (match_code "and,ior,xor")
217 (match_test "GET_MODE (op) == mode")))
219 ;; Return 1 of OP is an address suitable for a cache manipulation operation.
220 ;; MODE has the meaning as in address_operand.
222 (define_special_predicate "cache_address_operand"
223 (match_code "plus,reg")
225 if (GET_CODE (op) == PLUS)
227 if (!REG_P (XEXP (op, 0)))
229 if (!CONST_INT_P (XEXP (op, 1))
230 || (INTVAL (XEXP (op, 1)) & 31))
233 else if (!REG_P (op))
235 return address_operand (op, mode);
238 ;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
240 (define_predicate "cmp_operand"
241 (match_code "subreg,reg,const_int")
243 if (satisfies_constraint_N (op))
246 && mode != DImode && GET_CODE (op) == SUBREG
247 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
249 return arith_reg_operand (op, mode);
252 ;; TODO: Add a comment here.
254 (define_predicate "cmpsi_operand"
255 (match_code "subreg,reg,const_int")
257 if (REG_P (op) && REGNO (op) == T_REG
258 && GET_MODE (op) == SImode
261 return arith_operand (op, mode);
264 ;; TODO: Add a comment here.
266 (define_predicate "commutative_float_operator"
267 (and (match_code "plus,mult")
268 (match_test "GET_MODE (op) == mode")))
270 ;; TODO: Add a comment here.
272 (define_predicate "equality_comparison_operator"
273 (match_code "eq,ne"))
275 ;; TODO: Add a comment here.
277 (define_predicate "extend_reg_operand"
278 (match_code "subreg,reg,truncate")
280 return (GET_CODE (op) == TRUNCATE
282 : arith_reg_operand) (op, mode);
285 ;; TODO: Add a comment here.
287 (define_predicate "extend_reg_or_0_operand"
288 (match_code "subreg,reg,truncate,const_int")
290 return (GET_CODE (op) == TRUNCATE
292 : arith_reg_or_0_operand) (op, mode);
295 ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
297 (define_predicate "ext_dest_operand"
298 (match_code "subreg,reg")
300 return arith_reg_operand (op, mode);
303 ;; TODO: Add a comment here.
305 (define_predicate "fp_arith_reg_dest"
306 (match_code "subreg,reg")
308 if (mode == DImode && GET_CODE (op) == SUBREG
309 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
311 return fp_arith_reg_operand (op, mode);
314 ;; TODO: Add a comment here.
316 (define_predicate "fp_arith_reg_operand"
317 (match_code "subreg,reg")
319 if (register_operand (op, mode))
325 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
326 regno = REGNO (SUBREG_REG (op));
330 return (regno >= FIRST_PSEUDO_REGISTER
331 || FP_REGISTER_P (regno));
336 ;; TODO: Add a comment here.
338 (define_predicate "fpscr_operand"
342 && (REGNO (op) == FPSCR_REG
343 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
344 && !(reload_in_progress || reload_completed)))
345 && GET_MODE (op) == PSImode);
348 ;; Returns true if OP is an operand that is either the fpul hard reg or
349 ;; a pseudo. This prevents combine from propagating function arguments
350 ;; in hard regs into insns that need the operand in fpul. If it's a pseudo
351 ;; reload can fix it up.
352 (define_predicate "fpul_operand"
356 return fp_arith_reg_operand (op, mode);
359 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
360 && GET_MODE (op) == mode);
363 ;; Returns true if OP is a valid fpul input operand for the fsca insn.
364 ;; The value in fpul is a fixed-point value and its scaling is described
365 ;; in the fsca insn by a mult:SF. To allow pre-scaled fixed-point inputs
366 ;; in fpul we have to permit things like
368 ;; (fix:SF (float:SF (reg:SI)))
369 (define_predicate "fpul_fsca_operand"
370 (match_code "fix,reg")
372 if (fpul_operand (op, SImode))
374 if (GET_CODE (op) == FIX && GET_MODE (op) == SImode
375 && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode)
376 return fpul_fsca_operand (XEXP (XEXP (op, 0), 0),
377 GET_MODE (XEXP (XEXP (op, 0), 0)));
381 ;; Returns true if OP is a valid constant scale factor for the fsca insn.
382 (define_predicate "fsca_scale_factor"
383 (and (match_code "const_double")
384 (match_test "op == sh_fsca_int2sf ()")))
386 ;; TODO: Add a comment here.
388 (define_predicate "general_extend_operand"
389 (match_code "subreg,reg,mem,truncate")
391 return (GET_CODE (op) == TRUNCATE
393 : nonimmediate_operand) (op, mode);
396 ;; Returns 1 if OP is a simple register address.
397 (define_predicate "simple_mem_operand"
398 (and (match_code "mem")
399 (match_test "arith_reg_operand (XEXP (op, 0), SImode)")))
401 ;; Returns 1 if OP is a valid displacement address.
402 (define_predicate "displacement_mem_operand"
403 (and (match_code "mem")
404 (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
405 (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)")
406 (match_test "sh_legitimate_index_p (GET_MODE (op),
407 XEXP (XEXP (op, 0), 1),
408 TARGET_SH2A, true)")))
410 ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.
411 (define_predicate "zero_extend_movu_operand"
412 (and (match_operand 0 "displacement_mem_operand")
413 (match_test "GET_MODE (op) == QImode || GET_MODE (op) == HImode")))
415 ;; Returns 1 if the operand can be used in a zero_extend.
416 (define_predicate "zero_extend_operand"
417 (ior (and (match_test "TARGET_SHMEDIA")
418 (match_operand 0 "general_extend_operand"))
419 (and (match_test "! TARGET_SHMEDIA")
420 (match_operand 0 "arith_reg_operand"))
421 (and (match_test "TARGET_SH2A")
422 (match_operand 0 "zero_extend_movu_operand"))))
424 ;; Returns 1 if OP can be source of a simple move operation. Same as
425 ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
426 ;; are subregs of system registers.
428 (define_predicate "general_movsrc_operand"
429 (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
431 if (t_reg_operand (op, mode))
436 rtx inside = XEXP (op, 0);
438 /* Disallow mems with GBR address here. They have to go through
439 separate special patterns. */
440 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
441 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
442 && REGNO (XEXP (inside, 0)) == GBR_REG))
445 if (GET_CODE (inside) == CONST)
446 inside = XEXP (inside, 0);
448 if (GET_CODE (inside) == LABEL_REF)
451 if (GET_CODE (inside) == PLUS
452 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
453 && CONST_INT_P (XEXP (inside, 1)))
456 /* Only post inc allowed. */
457 if (GET_CODE (inside) == PRE_DEC)
461 if ((mode == QImode || mode == HImode)
462 && mode == GET_MODE (op)
464 || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
466 rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
468 if (GET_CODE (x) == PLUS
469 && REG_P (XEXP (x, 0))
470 && CONST_INT_P (XEXP (x, 1)))
471 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
475 && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
476 && sh_rep_vec (op, mode))
478 if (TARGET_SHMEDIA && 1
479 && GET_CODE (op) == SUBREG && GET_MODE (op) == mode
480 && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
481 /* FIXME */ abort (); /* return 1; */
482 return general_operand (op, mode);
485 ;; Returns 1 if OP is a MEM that does not use displacement addressing.
487 (define_predicate "movsrc_no_disp_mem_operand"
490 return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
493 ;; Returns 1 if OP can be a destination of a move. Same as
494 ;; general_operand, but no preinc allowed.
496 (define_predicate "general_movdst_operand"
497 (match_code "subreg,reg,mem")
499 if (t_reg_operand (op, mode))
504 rtx inside = XEXP (op, 0);
505 /* Disallow mems with GBR address here. They have to go through
506 separate special patterns. */
507 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
508 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
509 && REGNO (XEXP (inside, 0)) == GBR_REG))
513 /* Only pre dec allowed. */
514 if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
516 if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
517 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
518 && ! (reload_in_progress || reload_completed))
521 if ((mode == QImode || mode == HImode)
522 && mode == GET_MODE (op)
524 || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
526 rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
528 if (GET_CODE (x) == PLUS
529 && REG_P (XEXP (x, 0))
530 && CONST_INT_P (XEXP (x, 1)))
531 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
534 return general_operand (op, mode);
537 ;; Returns 1 if OP is a POST_INC on stack pointer register.
539 (define_predicate "sh_no_delay_pop_operand"
543 inside = XEXP (op, 0);
545 if (GET_CODE (op) == MEM && GET_MODE (op) == SImode
546 && GET_CODE (inside) == POST_INC
547 && GET_CODE (XEXP (inside, 0)) == REG
548 && REGNO (XEXP (inside, 0)) == SP_REG)
554 ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
556 (define_predicate "unaligned_load_operand"
561 if (!MEM_P (op) || GET_MODE (op) != mode)
564 inside = XEXP (op, 0);
566 if (GET_CODE (inside) == POST_INC)
567 inside = XEXP (inside, 0);
575 ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner
577 (define_predicate "mem_index_disp_operand"
580 rtx plus0_rtx, plus1_rtx, mult_rtx;
582 plus0_rtx = XEXP (op, 0);
583 if (GET_CODE (plus0_rtx) != PLUS)
586 plus1_rtx = XEXP (plus0_rtx, 0);
587 if (GET_CODE (plus1_rtx) != PLUS)
589 if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1))))
592 mult_rtx = XEXP (plus1_rtx, 0);
593 if (GET_CODE (mult_rtx) != MULT)
595 if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0)))
596 || ! CONST_INT_P (XEXP (mult_rtx, 1)))
599 return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0
600 && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
603 ;; TODO: Add a comment here.
605 (define_predicate "greater_comparison_operator"
606 (match_code "gt,ge,gtu,geu"))
608 ;; TODO: Add a comment here.
610 (define_predicate "inqhi_operand"
611 (match_code "truncate")
613 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
616 /* Can't use true_regnum here because copy_cost wants to know about
617 SECONDARY_INPUT_RELOAD_CLASS. */
618 return REG_P (op) && FP_REGISTER_P (REGNO (op));
621 ;; TODO: Add a comment here.
623 (define_special_predicate "int_gpr_dest"
624 (match_code "subreg,reg")
626 enum machine_mode op_mode = GET_MODE (op);
628 if (GET_MODE_CLASS (op_mode) != MODE_INT
629 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
631 if (! reload_completed)
633 return true_regnum (op) <= LAST_GENERAL_REG;
636 ;; TODO: Add a comment here.
638 (define_predicate "less_comparison_operator"
639 (match_code "lt,le,ltu,leu"))
641 ;; Returns 1 if OP is a valid source operand for a logical operation.
643 (define_predicate "logical_operand"
644 (match_code "subreg,reg,const_int")
647 && mode != DImode && GET_CODE (op) == SUBREG
648 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
651 if (arith_reg_operand (op, mode))
656 if (satisfies_constraint_I10 (op))
661 else if (satisfies_constraint_K08 (op))
667 ;; Like logical_operand but allows additional constant values which can be
668 ;; done with zero extensions. Used for the second operand of and insns.
669 (define_predicate "logical_and_operand"
670 (match_code "subreg,reg,const_int")
672 if (logical_operand (op, mode))
676 && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op)))
682 ;; TODO: Add a comment here.
684 (define_predicate "logical_operator"
685 (match_code "and,ior,xor"))
687 ;; Like arith_reg_operand, but for register source operands of narrow
688 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
690 (define_predicate "logical_reg_operand"
691 (match_code "subreg,reg")
694 && GET_CODE (op) == SUBREG
695 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
698 return arith_reg_operand (op, mode);
701 ;; TODO: Add a comment here.
703 (define_predicate "mextr_bit_offset"
704 (match_code "const_int")
708 if (!CONST_INT_P (op))
711 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
714 ;; TODO: Add a comment here.
716 (define_predicate "minuend_operand"
717 (match_code "subreg,reg,truncate,const_int")
719 return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
722 ;; TODO: Add a comment here.
724 (define_predicate "noncommutative_float_operator"
725 (and (match_code "minus,div")
726 (match_test "GET_MODE (op) == mode")))
728 ;; UNORDERED is only supported on SHMEDIA.
730 (define_predicate "sh_float_comparison_operator"
731 (ior (match_operand 0 "ordered_comparison_operator")
732 (and (match_test "TARGET_SHMEDIA")
733 (match_code "unordered"))))
735 (define_predicate "shmedia_cbranch_comparison_operator"
736 (ior (match_operand 0 "equality_comparison_operator")
737 (match_operand 0 "greater_comparison_operator")))
739 ;; TODO: Add a comment here.
741 (define_predicate "sh_const_vec"
742 (match_code "const_vector")
746 if (GET_CODE (op) != CONST_VECTOR
747 || (GET_MODE (op) != mode && mode != VOIDmode))
749 i = XVECLEN (op, 0) - 1;
751 if (!CONST_INT_P (XVECEXP (op, 0, i)))
756 ;; Determine if OP is a constant vector matching MODE with only one
757 ;; element that is not a sign extension. Two byte-sized elements
760 (define_predicate "sh_1el_vec"
761 (match_code "const_vector")
764 int i, last, least, sign_ix;
767 if (GET_CODE (op) != CONST_VECTOR
768 || (GET_MODE (op) != mode && mode != VOIDmode))
770 /* Determine numbers of last and of least significant elements. */
771 last = XVECLEN (op, 0) - 1;
772 least = TARGET_LITTLE_ENDIAN ? 0 : last;
773 if (!CONST_INT_P (XVECEXP (op, 0, least)))
776 if (GET_MODE_UNIT_SIZE (mode) == 1)
777 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
778 if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
780 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
781 sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
782 ? constm1_rtx : const0_rtx);
783 i = XVECLEN (op, 0) - 1;
785 if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
791 ;; Like register_operand, but take into account that SHMEDIA can use
792 ;; the constant zero like a general register.
794 (define_predicate "sh_register_operand"
795 (match_code "reg,subreg,const_int,const_double")
797 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
799 return register_operand (op, mode);
802 ;; TODO: Add a comment here.
804 (define_predicate "sh_rep_vec"
805 (match_code "const_vector,parallel")
810 if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
811 || (GET_MODE (op) != mode && mode != VOIDmode))
813 i = XVECLEN (op, 0) - 2;
814 x = XVECEXP (op, 0, i + 1);
815 if (GET_MODE_UNIT_SIZE (mode) == 1)
817 y = XVECEXP (op, 0, i);
818 for (i -= 2; i >= 0; i -= 2)
819 if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
820 || ! rtx_equal_p (XVECEXP (op, 0, i), y))
825 if (XVECEXP (op, 0, i) != x)
830 ;; TODO: Add a comment here.
832 (define_predicate "shift_count_operand"
833 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend")
835 /* Allow T_REG as shift count for dynamic shifts, although it is not
836 really possible. It will then be copied to a general purpose reg. */
837 if (! TARGET_SHMEDIA)
838 return const_int_operand (op, mode) || arith_reg_operand (op, mode)
839 || (TARGET_DYNSHIFT && t_reg_operand (op, mode));
841 return (CONSTANT_P (op)
843 ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
844 : nonmemory_operand (op, mode))
845 : shift_count_reg_operand (op, mode));
848 ;; TODO: Add a comment here.
850 (define_predicate "shift_count_reg_operand"
851 (match_code "subreg,reg,zero_extend,sign_extend")
853 if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
854 || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
855 && (mode == VOIDmode || mode == GET_MODE (op))
856 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
857 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
862 while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
863 || GET_CODE (op) == TRUNCATE)
864 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
865 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
868 return arith_reg_operand (op, mode);
871 ;; Predicates for matching operands that are constant shift
872 ;; amounts 1, 2, 8, 16.
873 (define_predicate "p27_shift_count_operand"
874 (and (match_code "const_int")
875 (match_test "satisfies_constraint_P27 (op)")))
877 (define_predicate "not_p27_shift_count_operand"
878 (and (match_code "const_int")
879 (match_test "! satisfies_constraint_P27 (op)")))
881 ;; For right shifts the constant 1 is a special case because the shlr insn
882 ;; clobbers the T_REG and is handled by the T_REG clobbering version of the
883 ;; insn, which is also used for non-P27 shift sequences.
884 (define_predicate "p27_rshift_count_operand"
885 (and (match_code "const_int")
886 (match_test "satisfies_constraint_P27 (op)")
887 (match_test "! satisfies_constraint_M (op)")))
889 (define_predicate "not_p27_rshift_count_operand"
890 (and (match_code "const_int")
891 (ior (match_test "! satisfies_constraint_P27 (op)")
892 (match_test "satisfies_constraint_M (op)"))))
894 ;; TODO: Add a comment here.
896 (define_predicate "shift_operator"
897 (match_code "ashift,ashiftrt,lshiftrt"))
899 ;; TODO: Add a comment here.
901 (define_predicate "symbol_ref_operand"
902 (match_code "symbol_ref"))
904 ;; Same as target_reg_operand, except that label_refs and symbol_refs
905 ;; are accepted before reload.
907 (define_special_predicate "target_operand"
908 (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
910 if (mode != VOIDmode && mode != Pmode)
913 if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
914 && satisfies_constraint_Csy (op))
915 return ! reload_completed;
917 return target_reg_operand (op, mode);
920 ;; Accept pseudos and branch target registers.
922 (define_special_predicate "target_reg_operand"
923 (match_code "subreg,reg")
926 ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
927 : mode != GET_MODE (op))
930 if (GET_CODE (op) == SUBREG)
936 /* We must protect ourselves from matching pseudos that are virtual
937 register, because they will eventually be replaced with hardware
938 registers that aren't branch-target registers. */
939 if (REGNO (op) > LAST_VIRTUAL_REGISTER
940 || TARGET_REGISTER_P (REGNO (op)))
946 ;; TODO: Add a comment here.
948 (define_special_predicate "trunc_hi_operand"
949 (match_code "subreg,reg,truncate")
951 enum machine_mode op_mode = GET_MODE (op);
953 if (op_mode != SImode && op_mode != DImode
954 && op_mode != V4HImode && op_mode != V2SImode)
956 return extend_reg_operand (op, mode);
959 ;; Return 1 of OP is an address suitable for an unaligned access instruction.
961 (define_special_predicate "ua_address_operand"
962 (match_code "subreg,reg,plus")
964 if (GET_CODE (op) == PLUS
965 && (! satisfies_constraint_I06 (XEXP (op, 1))))
967 return address_operand (op, QImode);
970 ;; TODO: Add a comment here.
972 (define_predicate "ua_offset"
973 (match_code "const_int")
975 return satisfies_constraint_I06 (op);
978 ;; TODO: Add a comment here.
980 (define_predicate "unary_float_operator"
981 (and (match_code "abs,neg,sqrt")
982 (match_test "GET_MODE (op) == mode")))
984 ;; Return 1 if OP is a valid source operand for xor.
986 (define_predicate "xor_operand"
987 (match_code "subreg,reg,const_int")
989 if (CONST_INT_P (op))
990 return (TARGET_SHMEDIA
991 ? (satisfies_constraint_I06 (op)
992 || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
993 : satisfies_constraint_K08 (op));
995 && mode != DImode && GET_CODE (op) == SUBREG
996 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
998 return arith_reg_operand (op, mode);
1001 (define_predicate "bitwise_memory_operand"
1006 if (REG_P (XEXP (op, 0)))
1009 if (GET_CODE (XEXP (op, 0)) == PLUS
1010 && REG_P (XEXP (XEXP (op, 0), 0))
1011 && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))
1017 ;; The atomic_* operand predicates are used for the atomic patterns.
1018 ;; Depending on the particular pattern some operands can be immediate
1019 ;; values. Using these predicates avoids the usage of 'force_reg' in the
1021 (define_predicate "atomic_arith_operand"
1022 (ior (match_code "subreg,reg")
1023 (and (match_test "satisfies_constraint_I08 (op)")
1024 (match_test "mode != QImode")
1025 (match_test "mode != HImode")
1026 (match_test "TARGET_SH4A_ARCH"))))
1028 (define_predicate "atomic_logical_operand"
1029 (ior (match_code "subreg,reg")
1030 (and (match_test "satisfies_constraint_K08 (op)")
1031 (match_test "mode != QImode")
1032 (match_test "mode != HImode")
1033 (match_test "TARGET_SH4A_ARCH"))))
1035 ;; A predicate describing the T bit register in any form.
1036 (define_predicate "t_reg_operand"
1037 (match_code "reg,subreg,sign_extend,zero_extend")
1039 switch (GET_CODE (op))
1042 return REGNO (op) == T_REG;
1045 return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG;
1049 return GET_CODE (XEXP (op, 0)) == SUBREG
1050 && REG_P (SUBREG_REG (XEXP (op, 0)))
1051 && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
1058 ;; A predicate describing a negated T bit register.
1059 (define_predicate "negt_reg_operand"
1060 (match_code "subreg,xor")
1062 switch (GET_CODE (op))
1065 return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))
1066 && satisfies_constraint_M (XEXP (op, 1));
1069 return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)));
1076 ;; A predicate that returns true if OP is a valid construct around the T bit
1077 ;; that can be used as an operand for conditional branches.
1078 (define_predicate "cbranch_treg_value"
1079 (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend")
1081 return sh_eval_treg_value (op) >= 0;
1084 ;; Returns true of OP is arith_reg_operand or t_reg_operand.
1085 (define_predicate "arith_reg_or_t_reg_operand"
1086 (ior (match_operand 0 "arith_reg_operand")
1087 (match_operand 0 "t_reg_operand")))
1089 ;; A predicate describing the negated value of the T bit register shifted
1091 (define_predicate "negt_reg_shl31_operand"
1092 (match_code "plus,minus,if_then_else")
1094 /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand")
1095 (const_int -2147483648)) ;; 0xffffffff80000000
1096 (const_int -2147483648))
1098 if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1))
1099 && GET_CODE (XEXP (op, 0)) == MULT
1100 && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode)
1101 && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1)))
1104 /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000
1105 (mult:SI (match_operand:SI 1 "t_reg_operand")
1106 (const_int -2147483648)))
1108 if (GET_CODE (op) == MINUS
1109 && satisfies_constraint_Jhb (XEXP (op, 0))
1110 && GET_CODE (XEXP (op, 1)) == MULT
1111 && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode)
1112 && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1)))
1115 /* (if_then_else:SI (match_operand:SI 1 "t_reg_operand")
1117 (const_int -2147483648)) ;; 0xffffffff80000000
1119 if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode)
1120 && satisfies_constraint_Z (XEXP (op, 1))
1121 && satisfies_constraint_Jhb (XEXP (op, 2)))
1127 ;; A predicate that determines whether a given constant is a valid
1128 ;; displacement for a gbr load/store of the specified mode.
1129 (define_predicate "gbr_displacement"
1130 (match_code "const_int")
1132 const int mode_sz = GET_MODE_SIZE (mode);
1133 const int move_sz = mode_sz > GET_MODE_SIZE (SImode)
1134 ? GET_MODE_SIZE (SImode)
1136 int max_disp = 255 * move_sz;
1137 if (mode_sz > move_sz)
1138 max_disp -= mode_sz - move_sz;
1140 return INTVAL (op) >= 0 && INTVAL (op) <= max_disp;
1143 ;; A predicate that determines whether OP is a valid GBR addressing mode
1144 ;; memory reference.
1145 (define_predicate "gbr_address_mem"
1148 rtx addr = XEXP (op, 0);
1150 if (REG_P (addr) && REGNO (addr) == GBR_REG)
1152 if (GET_CODE (addr) == PLUS
1153 && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG
1154 && gbr_displacement (XEXP (addr, 1), mode))