| blob | b0ac47dbd36b21e5f8909d1449eb174b57c4285b |
1 ;; Machine description for Sunplus S+CORE
2 ;; Copyright (C) 2005, 2007, 2010, 2011
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Sunnorth.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ; branch conditional branch
25 ; jump unconditional jump
26 ; call unconditional call
27 ; load load instruction(s)
28 ; store store instruction(s)
29 ; cmp integer compare
30 ; arith integer arithmetic instruction
31 ; move data movement within same register set
32 ; const load constant
33 ; nop no operation
34 ; mul integer multiply
35 ; div integer divide
36 ; cndmv conditional moves
37 ; fce transfer from hi/lo registers
38 ; tce transfer to hi/lo registers
39 ; fsr transfer from special registers
40 ; tsr transfer to special registers
42 (define_constants
43 [(CC_REGNUM 33)
44 (T_REGNUM 34)
45 (RA_REGNUM 3)
46 (SP_REGNUM 0)
47 (AT_REGNUM 1)
48 (FP_REGNUM 2)
49 (RT_REGNUM 4)
50 (GP_REGNUM 28)
51 (EH_REGNUM 29)
52 (HI_REGNUM 48)
53 (LO_REGNUM 49)
54 (CN_REGNUM 50)
55 (LC_REGNUM 51)
56 (SC_REGNUM 52)])
58 (define_constants
59 [(BITTST 0)
60 (CPLOAD 1)
61 (CPRESTORE 2)
63 (SCB 3)
64 (SCW 4)
65 (SCE 5)
66 (SCLC 6)
68 (LCB 7)
69 (LCW 8)
70 (LCE 9)
72 (SFFS 10)])
74 (define_attr "type"
75 "unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr"
76 (const_string "unknown"))
78 (define_attr "mode" "unknown,QI,HI,SI,DI"
79 (const_string "unknown"))
81 (define_attr "length" "" (const_int 4))
83 (define_attr "up_c" "yes,no"
84 (const_string "no"))
86 (include "constraints.md")
87 (include "score-generic.md")
88 (include "predicates.md")
90 (define_expand "movqi"
91 [(set (match_operand:QI 0 "nonimmediate_operand")
92 (match_operand:QI 1 "general_operand"))]
93 ""
94 {
95 if (MEM_P (operands[0])
96 && !register_operand (operands[1], QImode))
97 {
98 operands[1] = force_reg (QImode, operands[1]);
99 }
100 })
102 (define_insn "*movqi_insns_score7"
103 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
104 (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
105 "(!MEM_P (operands[0]) || register_operand (operands[1], QImode))
106 && (TARGET_SCORE7 || TARGET_SCORE7D)"
107 {
108 switch (which_alternative)
109 {
110 case 0: return score_limm (operands);
111 case 1: return score_move (operands);
112 case 2: return score_linsn (operands, SCORE_BYTE, false);
113 case 3: return score_sinsn (operands, SCORE_BYTE);
114 case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
115 case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
116 case 6: return \"mfsr\t%0, %1\";
117 case 7: return \"mtsr\t%1, %0\";
118 default: gcc_unreachable ();
119 }
120 }
121 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
122 (set_attr "mode" "QI")])
124 (define_expand "movhi"
125 [(set (match_operand:HI 0 "nonimmediate_operand")
126 (match_operand:HI 1 "general_operand"))]
127 ""
128 {
129 if (MEM_P (operands[0])
130 && !register_operand (operands[1], HImode))
131 {
132 operands[1] = force_reg (HImode, operands[1]);
133 }
134 })
136 (define_insn "*movhi_insns_score7"
137 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
138 (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
139 "(!MEM_P (operands[0]) || register_operand (operands[1], HImode))
140 && (TARGET_SCORE7 || TARGET_SCORE7D)"
141 {
142 switch (which_alternative)
143 {
144 case 0: return score_limm (operands);
145 case 1: return score_move (operands);
146 case 2: return score_linsn (operands, SCORE_HWORD, false);
147 case 3: return score_sinsn (operands, SCORE_HWORD);
148 case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
149 case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
150 case 6: return \"mfsr\t%0, %1\";
151 case 7: return \"mtsr\t%1, %0\";
152 default: gcc_unreachable ();
153 }
154 }
155 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
156 (set_attr "mode" "HI")])
158 (define_expand "movsi"
159 [(set (match_operand:SI 0 "nonimmediate_operand")
160 (match_operand:SI 1 "general_operand"))]
161 ""
162 {
163 if (MEM_P (operands[0])
164 && !register_operand (operands[1], SImode))
165 {
166 operands[1] = force_reg (SImode, operands[1]);
167 }
168 })
170 (define_insn "*movsi_insns_score7"
171 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")
172 (match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]
173 "(!MEM_P (operands[0]) || register_operand (operands[1], SImode))
174 && (TARGET_SCORE7 || TARGET_SCORE7D)"
175 {
176 switch (which_alternative)
177 {
178 case 0:
179 if (GET_CODE (operands[1]) != CONST_INT)
180 return \"la\t%0, %1\";
181 else
182 return score_limm (operands);
183 case 1: return score_move (operands);
184 case 2: return score_linsn (operands, SCORE_WORD, false);
185 case 3: return score_sinsn (operands, SCORE_WORD);
186 case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
187 case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
188 case 6: return \"mfsr\t%0, %1\";
189 case 7: return \"mtsr\t%1, %0\";
190 case 8: return \"mfcr\t%0, %1\";
191 case 9: return \"mtcr\t%1, %0\";
192 default: gcc_unreachable ();
193 }
194 }
195 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")
196 (set_attr "mode" "SI")])
198 (define_insn_and_split "movdi"
199 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")
200 (match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]
201 ""
202 "#"
203 "reload_completed"
204 [(const_int 0)]
205 {
206 score_movdi (operands);
207 DONE;
208 })
210 (define_expand "movsf"
211 [(set (match_operand:SF 0 "nonimmediate_operand")
212 (match_operand:SF 1 "general_operand"))]
213 ""
214 {
215 if (MEM_P (operands[0])
216 && !register_operand (operands[1], SFmode))
217 {
218 operands[1] = force_reg (SFmode, operands[1]);
219 }
220 })
222 (define_insn "*movsf_insns_score7"
223 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
224 (match_operand:SF 1 "general_operand" "i,d,m,d"))]
225 "(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))
226 && (TARGET_SCORE7 || TARGET_SCORE7D)"
227 {
228 switch (which_alternative)
229 {
230 case 0: return \"li\t%0, %D1\";;
231 case 1: return score_move (operands);
232 case 2: return score_linsn (operands, SCORE_WORD, false);
233 case 3: return score_sinsn (operands, SCORE_WORD);
234 default: gcc_unreachable ();
235 }
236 }
237 [(set_attr "type" "arith,move,load,store")
238 (set_attr "mode" "SI")])
240 (define_insn_and_split "movdf"
241 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,m")
242 (match_operand:DF 1 "general_operand" "i,d,m,d"))]
243 ""
244 "#"
245 "reload_completed"
246 [(const_int 0)]
247 {
248 score_movdi (operands);
249 DONE;
250 })
252 (define_expand "addsi3"
253 [(set (match_operand:SI 0 "score_register_operand" )
254 (plus:SI (match_operand:SI 1 "score_register_operand")
255 (match_operand:SI 2 "arith_operand")))]
256 ""
257 ""
258 )
260 (define_insn "*addsi3_score7"
261 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
262 (plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
263 (match_operand:SI 2 "arith_operand" "I,L,N,d")))]
264 "(TARGET_SCORE7 || TARGET_SCORE7D)"
265 {
266 switch (which_alternative)
267 {
268 case 0: return \"addis\t%0, %U2\";
269 case 1: return score_select_add_imm (operands, false);
270 case 2: return \"addri\t%0, %1, %c2\";
271 case 3: return score_select (operands, "add", true, "", false);
272 default: gcc_unreachable ();
273 }
274 }
275 [(set_attr "type" "arith")
276 (set_attr "mode" "SI")])
278 (define_insn "*addsi3_cmp_score7"
279 [(set (reg:CC_NZ CC_REGNUM)
280 (compare:CC_NZ (plus:SI
281 (match_operand:SI 1 "register_operand" "0,0,d,d")
282 (match_operand:SI 2 "arith_operand" "I,L,N,d"))
283 (const_int 0)))
284 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
285 "(TARGET_SCORE7 || TARGET_SCORE7D)"
286 {
287 switch (which_alternative)
288 {
289 case 0: return \"addis.c\t%0, %U2\";
290 case 1: return score_select_add_imm (operands, true);
291 case 2: return \"addri.c\t%0, %1, %c2\";
292 case 3: return score_select (operands, "add", true, "", true);
293 default: gcc_unreachable ();
294 }
295 }
296 [(set_attr "type" "arith")
297 (set_attr "up_c" "yes")
298 (set_attr "mode" "SI")])
300 (define_insn "*addsi3_ucc_score7"
301 [(set (reg:CC_NZ CC_REGNUM)
302 (compare:CC_NZ (plus:SI
303 (match_operand:SI 1 "register_operand" "0,0,d,d")
304 (match_operand:SI 2 "arith_operand" "I,L,N,d"))
305 (const_int 0)))
306 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
307 (plus:SI (match_dup 1) (match_dup 2)))]
308 "(TARGET_SCORE7 || TARGET_SCORE7D)"
309 {
310 switch (which_alternative)
311 {
312 case 0: return \"addis.c\t%0, %U2\";
313 case 1: return score_select_add_imm (operands, true);
314 case 2: return \"addri.c\t%0, %1, %c2\";
315 case 3: return score_select (operands, "add", true, "", true);
316 default: gcc_unreachable ();
317 }
318 }
319 [(set_attr "type" "arith")
320 (set_attr "up_c" "yes")
321 (set_attr "mode" "SI")])
323 (define_expand "adddi3"
324 [(parallel
325 [(set (match_operand:DI 0 "score_register_operand")
326 (plus:DI (match_operand:DI 1 "score_register_operand")
327 (match_operand:DI 2 "score_register_operand")))
328 (clobber (reg:CC CC_REGNUM))])]
329 ""
330 ""
331 )
333 (define_insn "*adddi3_score7"
334 [(set (match_operand:DI 0 "register_operand" "=e,d")
335 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
336 (match_operand:DI 2 "register_operand" "e,d")))
337 (clobber (reg:CC CC_REGNUM))]
338 "(TARGET_SCORE7 || TARGET_SCORE7D)"
339 "@
340 add! %L0, %L2\;addc! %H0, %H2
341 add.c %L0, %L1, %L2\;addc %H0, %H1, %H2"
342 [(set_attr "type" "arith")
343 (set_attr "mode" "DI")])
345 (define_expand "subsi3"
346 [(set (match_operand:SI 0 "score_register_operand")
347 (minus:SI (match_operand:SI 1 "score_register_operand")
348 (match_operand:SI 2 "score_register_operand")))]
349 ""
350 ""
351 )
353 (define_insn "*subsi3_score7"
354 [(set (match_operand:SI 0 "register_operand" "=d")
355 (minus:SI (match_operand:SI 1 "register_operand" "d")
356 (match_operand:SI 2 "register_operand" "d")))]
357 "(TARGET_SCORE7 || TARGET_SCORE7D)"
358 {
359 return score_select (operands, "sub", false, "", false);
360 }
361 [(set_attr "type" "arith")
362 (set_attr "mode" "SI")])
364 (define_insn "*subsi3_cmp_score7"
365 [(set (reg:CC_NZ CC_REGNUM)
366 (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
367 (match_operand:SI 2 "register_operand" "d"))
368 (const_int 0)))
369 (clobber (match_scratch:SI 0 "=d"))]
370 "(TARGET_SCORE7 || TARGET_SCORE7D)"
371 {
372 return score_select (operands, "sub", false, "", true);
373 }
374 [(set_attr "type" "arith")
375 (set_attr "up_c" "yes")
376 (set_attr "mode" "SI")])
378 (define_peephole2
379 [(set (match_operand:SI 0 "g32reg_operand" "")
380 (minus:SI (match_operand:SI 1 "g32reg_operand" "")
381 (match_operand:SI 2 "g32reg_operand" "")))
382 (set (reg:CC CC_REGNUM)
383 (compare:CC (match_dup 1) (match_dup 2)))]
384 ""
385 [(set (reg:CC CC_REGNUM)
386 (compare:CC (match_dup 1) (match_dup 2)))
387 (set (match_dup 0)
388 (minus:SI (match_dup 1) (match_dup 2)))])
390 (define_insn "subsi3_ucc_pcmp"
391 [(parallel
392 [(set (reg:CC CC_REGNUM)
393 (compare:CC (match_operand:SI 1 "score_register_operand" "d")
394 (match_operand:SI 2 "score_register_operand" "d")))
395 (set (match_operand:SI 0 "score_register_operand" "=d")
396 (minus:SI (match_dup 1) (match_dup 2)))])]
397 ""
398 {
399 return score_select (operands, "sub", false, "", true);
400 }
401 [(set_attr "type" "arith")
402 (set_attr "length" "4")
403 (set_attr "up_c" "yes")
404 (set_attr "mode" "SI")])
406 (define_insn "subsi3_ucc"
407 [(set (reg:CC_NZ CC_REGNUM)
408 (compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")
409 (match_operand:SI 2 "score_register_operand" "d"))
410 (const_int 0)))
411 (set (match_operand:SI 0 "score_register_operand" "=d")
412 (minus:SI (match_dup 1) (match_dup 2)))]
413 ""
414 {
415 return score_select (operands, "sub", false, "", true);
416 }
417 [(set_attr "type" "arith")
418 (set_attr "length" "4")
419 (set_attr "up_c" "yes")
420 (set_attr "mode" "SI")])
422 (define_expand "subdi3"
423 [(parallel
424 [(set (match_operand:DI 0 "score_register_operand")
425 (minus:DI (match_operand:DI 1 "score_register_operand")
426 (match_operand:DI 2 "score_register_operand")))
427 (clobber (reg:CC CC_REGNUM))])]
428 ""
429 ""
430 )
432 (define_insn "*subdi3_score7"
433 [(set (match_operand:DI 0 "register_operand" "=e,d")
434 (minus:DI (match_operand:DI 1 "register_operand" "0,d")
435 (match_operand:DI 2 "register_operand" "e,d")))
436 (clobber (reg:CC CC_REGNUM))]
437 "(TARGET_SCORE7 || TARGET_SCORE7D)"
438 "@
439 sub! %L0, %L2\;subc %H0, %H1, %H2
440 sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2"
441 [(set_attr "type" "arith")
442 (set_attr "mode" "DI")])
444 (define_expand "andsi3"
445 [(set (match_operand:SI 0 "score_register_operand")
446 (and:SI (match_operand:SI 1 "score_register_operand")
447 (match_operand:SI 2 "arith_operand")))]
448 ""
449 ""
450 )
452 (define_insn "*andsi3_score7"
453 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
454 (and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
455 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]
456 "(TARGET_SCORE7 || TARGET_SCORE7D)"
457 {
458 switch (which_alternative)
459 {
460 case 0: return \"andis\t%0, %U2\";
461 case 1: return \"andi\t%0, %c2";
462 case 2: return \"andri\t%0, %1, %c2\";
463 case 3: return score_select (operands, "and", true, "", false);
464 default: gcc_unreachable ();
465 }
466 }
467 [(set_attr "type" "arith")
468 (set_attr "mode" "SI")])
470 (define_insn "andsi3_cmp_score7"
471 [(set (reg:CC_NZ CC_REGNUM)
472 (compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")
473 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
474 (const_int 0)))
475 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
476 "(TARGET_SCORE7 || TARGET_SCORE7D)"
477 {
478 switch (which_alternative)
479 {
480 case 0: return \"andis.c\t%0, %U2\";
481 case 1: return \"andi.c\t%0, %c2";
482 case 2: return \"andri.c\t%0, %1, %c2\";
483 case 3: return score_select (operands, "and", true, "", true);
484 default: gcc_unreachable ();
485 }
486 }
487 [(set_attr "type" "arith")
488 (set_attr "up_c" "yes")
489 (set_attr "mode" "SI")])
491 (define_insn "*andsi3_ucc_score7"
492 [(set (reg:CC_NZ CC_REGNUM)
493 (compare:CC_NZ (and:SI
494 (match_operand:SI 1 "register_operand" "0,0,d,d")
495 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
496 (const_int 0)))
497 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
498 (and:SI (match_dup 1) (match_dup 2)))]
499 "(TARGET_SCORE7 || TARGET_SCORE7D)"
500 {
501 switch (which_alternative)
502 {
503 case 0: return \"andis.c\t%0, %U2\";
504 case 1: return \"andi.c\t%0, %c2";
505 case 2: return \"andri.c\t%0, %1, %c2\";
506 case 3: return score_select (operands, "and", true, "", true);
507 default: gcc_unreachable ();
508 }
509 }
510 [(set_attr "type" "arith")
511 (set_attr "up_c" "yes")
512 (set_attr "mode" "SI")])
514 (define_insn_and_split "*zero_extract_andi"
515 [(set (reg:CC CC_REGNUM)
516 (compare:CC (zero_extract:SI
517 (match_operand:SI 0 "score_register_operand" "d")
518 (match_operand:SI 1 "const_uimm5" "")
519 (match_operand:SI 2 "const_uimm5" ""))
520 (const_int 0)))]
521 ""
522 "#"
523 ""
524 [(const_int 1)]
525 {
526 score_zero_extract_andi (operands);
527 DONE;
528 })
530 (define_expand "iorsi3"
531 [(set (match_operand:SI 0 "score_register_operand")
532 (ior:SI (match_operand:SI 1 "score_register_operand")
533 (match_operand:SI 2 "arith_operand")))]
534 ""
535 ""
536 )
538 (define_insn "*iorsi3_score7"
539 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
540 (ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
541 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]
542 "(TARGET_SCORE7 || TARGET_SCORE7D)"
543 {
544 switch (which_alternative)
545 {
546 case 0: return \"oris\t%0, %U2\";
547 case 1: return \"ori\t%0, %c2\";
548 case 2: return \"orri\t%0, %1, %c2\";
549 case 3: return score_select (operands, "or", true, "", false);
550 default: gcc_unreachable ();
551 }
552 }
553 [(set_attr "type" "arith")
554 (set_attr "mode" "SI")])
556 (define_insn "*iorsi3_ucc_score7"
557 [(set (reg:CC_NZ CC_REGNUM)
558 (compare:CC_NZ (ior:SI
559 (match_operand:SI 1 "register_operand" "0,0,d,d")
560 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
561 (const_int 0)))
562 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
563 (ior:SI (match_dup 1) (match_dup 2)))]
564 "(TARGET_SCORE7 || TARGET_SCORE7D)"
565 {
566 switch (which_alternative)
567 {
568 case 0: return \"oris.c\t%0, %U2\";
569 case 1: return \"ori.c\t%0, %c2\";
570 case 2: return \"orri.c\t%0, %1, %c2\";
571 case 3: return score_select (operands, "or", true, "", true);
572 default: gcc_unreachable ();
573 }
574 }
575 [(set_attr "type" "arith")
576 (set_attr "up_c" "yes")
577 (set_attr "mode" "SI")])
579 (define_insn "*iorsi3_cmp_score7"
580 [(set (reg:CC_NZ CC_REGNUM)
581 (compare:CC_NZ (ior:SI
582 (match_operand:SI 1 "register_operand" "0,0,d,d")
583 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
584 (const_int 0)))
585 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
586 "(TARGET_SCORE7 || TARGET_SCORE7D)"
587 {
588 switch (which_alternative)
589 {
590 case 0: return \"oris.c\t%0, %U2\";
591 case 1: return \"ori.c\t%0, %c2\";
592 case 2: return \"orri.c\t%0, %1, %c2\";
593 case 3: return score_select (operands, "or", true, "", true);
594 default: gcc_unreachable ();
595 }
596 }
597 [(set_attr "type" "arith")
598 (set_attr "up_c" "yes")
599 (set_attr "mode" "SI")])
601 (define_expand "xorsi3"
602 [(set (match_operand:SI 0 "score_register_operand")
603 (xor:SI (match_operand:SI 1 "score_register_operand")
604 (match_operand:SI 2 "score_register_operand")))]
605 ""
606 ""
607 )
609 (define_insn "*xorsi3_score7"
610 [(set (match_operand:SI 0 "register_operand" "=d")
611 (xor:SI (match_operand:SI 1 "register_operand" "d")
612 (match_operand:SI 2 "register_operand" "d")))]
613 "(TARGET_SCORE7 || TARGET_SCORE7D)"
614 {
615 return score_select (operands, "xor", true, "", false);
616 }
617 [(set_attr "type" "arith")
618 (set_attr "mode" "SI")])
620 (define_insn "*xorsi3_ucc_score7"
621 [(set (reg:CC_NZ CC_REGNUM)
622 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
623 (match_operand:SI 2 "register_operand" "d"))
624 (const_int 0)))
625 (set (match_operand:SI 0 "register_operand" "=d")
626 (xor:SI (match_dup 1) (match_dup 2)))]
627 "(TARGET_SCORE7 || TARGET_SCORE7D)"
628 {
629 return score_select (operands, "xor", true, "", true);
630 }
631 [(set_attr "type" "arith")
632 (set_attr "up_c" "yes")
633 (set_attr "mode" "SI")])
635 (define_insn "*xorsi3_cmp_score7"
636 [(set (reg:CC_NZ CC_REGNUM)
637 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
638 (match_operand:SI 2 "register_operand" "d"))
639 (const_int 0)))
640 (clobber (match_scratch:SI 0 "=d"))]
641 ""
642 {
643 return score_select (operands, "xor", true, "", true);
644 }
645 [(set_attr "type" "arith")
646 (set_attr "up_c" "yes")
647 (set_attr "mode" "SI")])
649 (define_expand "extendqisi2"
650 [(set (match_operand:SI 0 "score_register_operand")
651 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
652 ""
653 ""
654 )
656 (define_insn "*extendqisi2_score7"
657 [(set (match_operand:SI 0 "register_operand" "=d,d")
658 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
659 "(TARGET_SCORE7 || TARGET_SCORE7D)"
660 {
661 switch (which_alternative)
662 {
663 case 0: return \"extsb\t%0, %1\";
664 case 1: return score_linsn (operands, SCORE_BYTE, true);
665 default: gcc_unreachable ();
666 }
667 }
668 [(set_attr "type" "arith,load")
669 (set_attr "mode" "SI")])
671 (define_insn "*extendqisi2_ucc_score7"
672 [(set (reg:CC_N CC_REGNUM)
673 (compare:CC_N (ashiftrt:SI
674 (ashift:SI (match_operand:SI 1 "register_operand" "d")
675 (const_int 24))
676 (const_int 24))
677 (const_int 0)))
678 (set (match_operand:SI 0 "register_operand" "=d")
679 (sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]
680 "(TARGET_SCORE7 || TARGET_SCORE7D)"
681 "extsb.c %0, %1"
682 [(set_attr "type" "arith")
683 (set_attr "up_c" "yes")
684 (set_attr "mode" "SI")])
686 (define_insn "*extendqisi2_cmp_score7"
687 [(set (reg:CC_N CC_REGNUM)
688 (compare:CC_N (ashiftrt:SI
689 (ashift:SI (match_operand:SI 1 "register_operand" "d")
690 (const_int 24))
691 (const_int 24))
692 (const_int 0)))
693 (clobber (match_scratch:SI 0 "=d"))]
694 "(TARGET_SCORE7 || TARGET_SCORE7D)"
695 "extsb.c %0, %1"
696 [(set_attr "type" "arith")
697 (set_attr "up_c" "yes")
698 (set_attr "mode" "SI")])
700 (define_expand "extendhisi2"
701 [(set (match_operand:SI 0 "score_register_operand")
702 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
703 ""
704 ""
705 )
707 (define_insn "*extendhisi2_score7"
708 [(set (match_operand:SI 0 "register_operand" "=d,d")
709 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
710 "(TARGET_SCORE7 || TARGET_SCORE7D)"
711 {
712 switch (which_alternative)
713 {
714 case 0: return \"extsh\t%0, %1\";
715 case 1: return score_linsn (operands, SCORE_HWORD, true);
716 default: gcc_unreachable ();
717 }
718 }
719 [(set_attr "type" "arith, load")
720 (set_attr "mode" "SI")])
722 (define_insn "*extendhisi2_ucc_score7"
723 [(set (reg:CC_N CC_REGNUM)
724 (compare:CC_N (ashiftrt:SI
725 (ashift:SI (match_operand:SI 1 "register_operand" "d")
726 (const_int 16))
727 (const_int 16))
728 (const_int 0)))
729 (set (match_operand:SI 0 "register_operand" "=d")
730 (sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]
731 "(TARGET_SCORE7 || TARGET_SCORE7D)"
732 "extsh.c %0, %1"
733 [(set_attr "type" "arith")
734 (set_attr "up_c" "yes")
735 (set_attr "mode" "SI")])
737 (define_insn "*extendhisi2_cmp_score7"
738 [(set (reg:CC_N CC_REGNUM)
739 (compare:CC_N (ashiftrt:SI
740 (ashift:SI (match_operand:SI 1 "register_operand" "d")
741 (const_int 16))
742 (const_int 16))
743 (const_int 0)))
744 (clobber (match_scratch:SI 0 "=d"))]
745 "(TARGET_SCORE7 || TARGET_SCORE7D)"
746 "extsh.c %0, %1"
747 [(set_attr "type" "arith")
748 (set_attr "up_c" "yes")
749 (set_attr "mode" "SI")])
751 (define_expand "zero_extendqisi2"
752 [(set (match_operand:SI 0 "score_register_operand")
753 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
754 ""
755 ""
756 )
758 (define_insn "*zero_extendqisi2_score7"
759 [(set (match_operand:SI 0 "register_operand" "=d,d")
760 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
761 "(TARGET_SCORE7 || TARGET_SCORE7D)"
762 {
763 switch (which_alternative)
764 {
765 case 0: return \"extzb\t%0, %1\";
766 case 1: return score_linsn (operands, SCORE_BYTE, false);
767 default: gcc_unreachable ();
768 }
769 }
770 [(set_attr "type" "arith, load")
771 (set_attr "mode" "SI")])
773 (define_insn "*zero_extendqisi2_ucc_score7"
774 [(set (reg:CC_N CC_REGNUM)
775 (compare:CC_N (lshiftrt:SI
776 (ashift:SI (match_operand:SI 1 "register_operand" "d")
777 (const_int 24))
778 (const_int 24))
779 (const_int 0)))
780 (set (match_operand:SI 0 "register_operand" "=d")
781 (zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]
782 "(TARGET_SCORE7 || TARGET_SCORE7D)"
783 "extzb.c %0, %1"
784 [(set_attr "type" "arith")
785 (set_attr "up_c" "yes")
786 (set_attr "mode" "SI")])
788 (define_insn "*zero_extendqisi2_cmp_score7"
789 [(set (reg:CC_N CC_REGNUM)
790 (compare:CC_N (lshiftrt:SI
791 (ashift:SI (match_operand:SI 1 "register_operand" "d")
792 (const_int 24))
793 (const_int 24))
794 (const_int 0)))
795 (clobber (match_scratch:SI 0 "=d"))]
796 "(TARGET_SCORE7 || TARGET_SCORE7D)"
797 "extzb.c %0, %1"
798 [(set_attr "type" "arith")
799 (set_attr "up_c" "yes")
800 (set_attr "mode" "SI")])
802 (define_expand "zero_extendhisi2"
803 [(set (match_operand:SI 0 "score_register_operand")
804 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
805 ""
806 ""
807 )
809 (define_insn "*zero_extendhisi2_score7"
810 [(set (match_operand:SI 0 "register_operand" "=d,d")
811 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
812 "(TARGET_SCORE7 || TARGET_SCORE7D)"
813 {
814 switch (which_alternative)
815 {
816 case 0: return \"extzh\t%0, %1\";
817 case 1: return score_linsn (operands, SCORE_HWORD, false);
818 default: gcc_unreachable ();
819 }
820 }
821 [(set_attr "type" "arith, load")
822 (set_attr "mode" "SI")])
824 (define_insn "*zero_extendhisi2_ucc_score7"
825 [(set (reg:CC_N CC_REGNUM)
826 (compare:CC_N (lshiftrt:SI
827 (ashift:SI (match_operand:SI 1 "register_operand" "d")
828 (const_int 16))
829 (const_int 16))
830 (const_int 0)))
831 (set (match_operand:SI 0 "register_operand" "=d")
832 (zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]
833 "(TARGET_SCORE7 || TARGET_SCORE7D)"
834 "extzh.c %0, %1"
835 [(set_attr "type" "arith")
836 (set_attr "up_c" "yes")
837 (set_attr "mode" "SI")])
839 (define_insn "*zero_extendhisi2_cmp_score7"
840 [(set (reg:CC_N CC_REGNUM)
841 (compare:CC_N (lshiftrt:SI
842 (ashift:SI (match_operand:SI 1 "register_operand" "d")
843 (const_int 16))
844 (const_int 16))
845 (const_int 0)))
846 (clobber (match_scratch:SI 0 "=d"))]
847 "(TARGET_SCORE7 || TARGET_SCORE7D)"
848 "extzh.c %0, %1"
849 [(set_attr "type" "arith")
850 (set_attr "up_c" "yes")
851 (set_attr "mode" "SI")])
853 (define_expand "mulsi3"
854 [(set (match_operand:SI 0 "score_register_operand")
855 (mult:SI (match_operand:SI 1 "score_register_operand")
856 (match_operand:SI 2 "score_register_operand")))]
857 ""
858 {
859 if (TARGET_SCORE7 || TARGET_SCORE7D)
860 emit_insn (gen_mulsi3_score7 (operands[0], operands[1], operands[2]));
861 DONE;
862 })
864 (define_insn "mulsi3_score7"
865 [(set (match_operand:SI 0 "register_operand" "=l")
866 (mult:SI (match_operand:SI 1 "register_operand" "d")
867 (match_operand:SI 2 "register_operand" "d")))
868 (clobber (reg:SI HI_REGNUM))]
869 "(TARGET_SCORE7 || TARGET_SCORE7D)"
870 "mul %1, %2"
871 [(set_attr "type" "mul")
872 (set_attr "mode" "SI")])
874 (define_expand "mulsidi3"
875 [(set (match_operand:DI 0 "score_register_operand")
876 (mult:DI (sign_extend:DI
877 (match_operand:SI 1 "score_register_operand"))
878 (sign_extend:DI
879 (match_operand:SI 2 "score_register_operand"))))]
880 ""
881 {
882 if (TARGET_SCORE7 || TARGET_SCORE7D)
883 emit_insn (gen_mulsidi3_score7 (operands[0], operands[1], operands[2]));
884 DONE;
885 })
887 (define_insn "mulsidi3_score7"
888 [(set (match_operand:DI 0 "register_operand" "=x")
889 (mult:DI (sign_extend:DI
890 (match_operand:SI 1 "register_operand" "d"))
891 (sign_extend:DI
892 (match_operand:SI 2 "register_operand" "d"))))]
893 "(TARGET_SCORE7 || TARGET_SCORE7D)"
894 "mul %1, %2"
895 [(set_attr "type" "mul")
896 (set_attr "mode" "DI")])
898 (define_expand "umulsidi3"
899 [(set (match_operand:DI 0 "score_register_operand")
900 (mult:DI (zero_extend:DI
901 (match_operand:SI 1 "score_register_operand"))
902 (zero_extend:DI
903 (match_operand:SI 2 "score_register_operand"))))]
904 ""
905 {
906 if (TARGET_SCORE7 || TARGET_SCORE7D)
907 emit_insn (gen_umulsidi3_score7 (operands[0], operands[1], operands[2]));
908 DONE;
909 })
911 (define_insn "umulsidi3_score7"
912 [(set (match_operand:DI 0 "register_operand" "=x")
913 (mult:DI (zero_extend:DI
914 (match_operand:SI 1 "register_operand" "d"))
915 (zero_extend:DI
916 (match_operand:SI 2 "register_operand" "d"))))]
917 "(TARGET_SCORE7 || TARGET_SCORE7D)"
918 "mulu %1, %2"
919 [(set_attr "type" "mul")
920 (set_attr "mode" "DI")])
922 (define_expand "divmodsi4"
923 [(parallel
924 [(set (match_operand:SI 0 "score_register_operand")
925 (div:SI (match_operand:SI 1 "score_register_operand")
926 (match_operand:SI 2 "score_register_operand")))
927 (set (match_operand:SI 3 "score_register_operand")
928 (mod:SI (match_dup 1) (match_dup 2)))])]
929 ""
930 ""
931 )
933 (define_insn "*divmodsi4_score7"
934 [(set (match_operand:SI 0 "register_operand" "=l")
935 (div:SI (match_operand:SI 1 "register_operand" "d")
936 (match_operand:SI 2 "register_operand" "d")))
937 (set (match_operand:SI 3 "register_operand" "=h")
938 (mod:SI (match_dup 1) (match_dup 2)))]
939 "(TARGET_SCORE7 || TARGET_SCORE7D)"
940 "div %1, %2"
941 [(set_attr "type" "div")
942 (set_attr "mode" "SI")])
944 (define_expand "udivmodsi4"
945 [(parallel
946 [(set (match_operand:SI 0 "score_register_operand")
947 (udiv:SI (match_operand:SI 1 "score_register_operand")
948 (match_operand:SI 2 "score_register_operand")))
949 (set (match_operand:SI 3 "score_register_operand")
950 (umod:SI (match_dup 1) (match_dup 2)))])]
951 ""
952 ""
953 )
955 (define_insn "*udivmodsi4_score7"
956 [(set (match_operand:SI 0 "register_operand" "=l")
957 (udiv:SI (match_operand:SI 1 "register_operand" "d")
958 (match_operand:SI 2 "register_operand" "d")))
959 (set (match_operand:SI 3 "register_operand" "=h")
960 (umod:SI (match_dup 1) (match_dup 2)))]
961 "(TARGET_SCORE7 || TARGET_SCORE7D)"
962 "divu %1, %2"
963 [(set_attr "type" "div")
964 (set_attr "mode" "SI")])
966 (define_expand "ashlsi3"
967 [(set (match_operand:SI 0 "score_register_operand")
968 (ashift:SI (match_operand:SI 1 "score_register_operand")
969 (match_operand:SI 2 "arith_operand")))]
970 ""
971 ""
972 )
974 (define_insn "*ashlsi3_score7"
975 [(set (match_operand:SI 0 "register_operand" "=d,d")
976 (ashift:SI (match_operand:SI 1 "register_operand" "d,d")
977 (match_operand:SI 2 "arith_operand" "J,d")))]
978 "(TARGET_SCORE7 || TARGET_SCORE7D)"
979 "@
980 slli %0, %1, %c2
981 sll %0, %1, %2"
982 [(set_attr "type" "arith")
983 (set_attr "mode" "SI")])
985 (define_insn "*ashlsi3_ucc_score7"
986 [(set (reg:CC_NZ CC_REGNUM)
987 (compare:CC_NZ (ashift:SI
988 (match_operand:SI 1 "register_operand" "d,d")
989 (match_operand:SI 2 "arith_operand" "J,d"))
990 (const_int 0)))
991 (set (match_operand:SI 0 "register_operand" "=d,d")
992 (ashift:SI (match_dup 1) (match_dup 2)))]
993 "(TARGET_SCORE7 || TARGET_SCORE7D)"
994 {
995 switch (which_alternative)
996 {
997 case 0: return score_select (operands, "slli", false, "c", true);
998 case 1: return score_select (operands, "sll", false, "", true);
999 default: gcc_unreachable ();
1000 }
1001 }
1002 [(set_attr "type" "arith")
1003 (set_attr "up_c" "yes")
1004 (set_attr "mode" "SI")])
1006 (define_insn "*ashlsi3_cmp_score7"
1007 [(set (reg:CC_NZ CC_REGNUM)
1008 (compare:CC_NZ (ashift:SI
1009 (match_operand:SI 1 "register_operand" "d,d")
1010 (match_operand:SI 2 "arith_operand" "J,d"))
1011 (const_int 0)))
1012 (clobber (match_scratch:SI 0 "=d,d"))]
1013 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1014 {
1015 switch (which_alternative)
1016 {
1017 case 0: return score_select (operands, "slli", false, "c", true);
1018 case 1: return score_select (operands, "sll", false, "", true);
1019 default: gcc_unreachable ();
1020 }
1021 }
1022 [(set_attr "type" "arith")
1023 (set_attr "up_c" "yes")
1024 (set_attr "mode" "SI")])
1026 (define_expand "ashrsi3"
1027 [(set (match_operand:SI 0 "score_register_operand")
1028 (ashiftrt:SI (match_operand:SI 1 "score_register_operand")
1029 (match_operand:SI 2 "arith_operand")))]
1030 ""
1031 ""
1032 )
1034 (define_insn "*ashrsi3_score7"
1035 [(set (match_operand:SI 0 "register_operand" "=d,d")
1036 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
1037 (match_operand:SI 2 "arith_operand" "J,d")))]
1038 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1039 "@
1040 srai %0, %1, %c2
1041 sra %0, %1, %2"
1042 [(set_attr "type" "arith")
1043 (set_attr "mode" "SI")])
1045 (define_insn "*ashrsi3_ucc_score7"
1046 [(set (reg:CC_NZ CC_REGNUM)
1047 (compare:CC_NZ (ashiftrt:SI
1048 (match_operand:SI 1 "register_operand" "d,d")
1049 (match_operand:SI 2 "arith_operand" "J,d"))
1050 (const_int 0)))
1051 (set (match_operand:SI 0 "register_operand" "=d,d")
1052 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
1053 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1054 {
1055 switch (which_alternative)
1056 {
1057 case 0: return \"srai.c\t%0, %1, %c2\";
1058 case 1: return score_select (operands, "sra", false, "", true);
1059 default: gcc_unreachable ();
1060 }
1061 }
1062 [(set_attr "type" "arith")
1063 (set_attr "up_c" "yes")
1064 (set_attr "mode" "SI")])
1066 (define_insn "*ashrsi3_cmp_score7"
1067 [(set (reg:CC_NZ CC_REGNUM)
1068 (compare:CC_NZ (ashiftrt:SI
1069 (match_operand:SI 1 "register_operand" "d,d")
1070 (match_operand:SI 2 "arith_operand" "J,d"))
1071 (const_int 0)))
1072 (clobber (match_scratch:SI 0 "=d,d"))]
1073 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1074 {
1075 switch (which_alternative)
1076 {
1077 case 0: return \"srai.c\t%0, %1, %c2\";
1078 case 1: return score_select (operands, "sra", false, "", true);
1079 default: gcc_unreachable ();
1080 }
1081 }
1082 [(set_attr "type" "arith")
1083 (set_attr "up_c" "yes")
1084 (set_attr "mode" "SI")])
1086 (define_expand "lshrsi3"
1087 [(set (match_operand:SI 0 "score_register_operand")
1088 (lshiftrt:SI (match_operand:SI 1 "score_register_operand")
1089 (match_operand:SI 2 "arith_operand")))]
1090 ""
1091 ""
1092 )
1094 (define_insn "*lshrsi3_score7"
1095 [(set (match_operand:SI 0 "register_operand" "=d,d")
1096 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
1097 (match_operand:SI 2 "arith_operand" "J,d")))]
1098 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1099 "@
1100 srli %0, %1, %c2
1101 srl %0, %1, %2"
1102 [(set_attr "type" "arith")
1103 (set_attr "mode" "SI")])
1105 (define_insn "*lshrsi3_ucc_score7"
1106 [(set (reg:CC_NZ CC_REGNUM)
1107 (compare:CC_NZ (lshiftrt:SI
1108 (match_operand:SI 1 "register_operand" "d,d")
1109 (match_operand:SI 2 "arith_operand" "J,d"))
1110 (const_int 0)))
1111 (set (match_operand:SI 0 "register_operand" "=d,d")
1112 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
1113 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1114 {
1115 switch (which_alternative)
1116 {
1117 case 0: return score_select (operands, "srli", false, "c", true);
1118 case 1: return score_select (operands, "srl", false, "", true);
1119 default: gcc_unreachable ();
1120 }
1121 }
1122 [(set_attr "type" "arith")
1123 (set_attr "up_c" "yes")
1124 (set_attr "mode" "SI")])
1126 (define_insn "*lshrsi3_cmp_score7"
1127 [(set (reg:CC_NZ CC_REGNUM)
1128 (compare:CC_NZ (lshiftrt:SI
1129 (match_operand:SI 1 "register_operand" "d,d")
1130 (match_operand:SI 2 "arith_operand" "J,d"))
1131 (const_int 0)))
1132 (clobber (match_scratch:SI 0 "=d,d"))]
1133 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1134 {
1135 switch (which_alternative)
1136 {
1137 case 0: return score_select (operands, "srli", false, "c", true);
1138 case 1: return score_select (operands, "srl", false, "", true);
1139 default: gcc_unreachable ();
1140 }
1141 }
1142 [(set_attr "type" "arith")
1143 (set_attr "up_c" "yes")
1144 (set_attr "mode" "SI")])
1146 (define_expand "negsi2"
1147 [(set (match_operand:SI 0 "score_register_operand")
1148 (neg:SI (match_operand:SI 1 "score_register_operand")))]
1149 ""
1150 ""
1151 )
1153 (define_insn "*negsi2_score7"
1154 [(set (match_operand:SI 0 "register_operand" "=d")
1155 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1156 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1157 "neg %0, %1"
1158 [(set_attr "type" "arith")
1159 (set_attr "mode" "SI")])
1161 (define_insn "*negsi2_cmp_score7"
1162 [(set (reg:CC_NZ CC_REGNUM)
1163 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
1164 (const_int 0)))
1165 (clobber (match_scratch:SI 0 "=e,d"))]
1166 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1167 "@
1168 neg! %0, %1
1169 neg.c %0, %1"
1170 [(set_attr "type" "arith")
1171 (set_attr "up_c" "yes")
1172 (set_attr "mode" "SI")])
1174 (define_insn "*negsi2_ucc_score7"
1175 [(set (reg:CC_NZ CC_REGNUM)
1176 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
1177 (const_int 0)))
1178 (set (match_operand:SI 0 "register_operand" "=e,d")
1179 (neg:SI (match_dup 1)))]
1180 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1181 "@
1182 neg! %0, %1
1183 neg.c %0, %1"
1184 [(set_attr "type" "arith")
1185 (set_attr "up_c" "yes")
1186 (set_attr "mode" "SI")])
1188 (define_expand "one_cmplsi2"
1189 [(set (match_operand:SI 0 "score_register_operand")
1190 (not:SI (match_operand:SI 1 "score_register_operand")))]
1191 ""
1192 ""
1193 )
1195 (define_insn "*one_cmplsi2_score7"
1196 [(set (match_operand:SI 0 "register_operand" "=d")
1197 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1198 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1199 "not\t%0, %1"
1200 [(set_attr "type" "arith")
1201 (set_attr "mode" "SI")])
1203 (define_insn "*one_cmplsi2_ucc_score7"
1204 [(set (reg:CC_NZ CC_REGNUM)
1205 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
1206 (const_int 0)))
1207 (set (match_operand:SI 0 "register_operand" "=e,d")
1208 (not:SI (match_dup 1)))]
1209 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1210 "@
1211 not! %0, %1
1212 not.c %0, %1"
1213 [(set_attr "type" "arith")
1214 (set_attr "up_c" "yes")
1215 (set_attr "mode" "SI")])
1217 (define_insn "*one_cmplsi2_cmp_score7"
1218 [(set (reg:CC_NZ CC_REGNUM)
1219 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
1220 (const_int 0)))
1221 (clobber (match_scratch:SI 0 "=e,d"))]
1222 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1223 "@
1224 not! %0, %1
1225 not.c %0, %1"
1226 [(set_attr "type" "arith")
1227 (set_attr "up_c" "yes")
1228 (set_attr "mode" "SI")])
1230 (define_expand "rotlsi3"
1231 [(parallel
1232 [(set (match_operand:SI 0 "score_register_operand")
1233 (rotate:SI (match_operand:SI 1 "score_register_operand")
1234 (match_operand:SI 2 "arith_operand")))
1235 (clobber (reg:CC CC_REGNUM))])]
1236 ""
1237 ""
1238 )
1240 (define_insn "*rotlsi3_score7"
1241 [(set (match_operand:SI 0 "register_operand" "=d,d")
1242 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
1243 (match_operand:SI 2 "arith_operand" "J,d")))
1244 (clobber (reg:CC CC_REGNUM))]
1245 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1246 "@
1247 roli.c %0, %1, %c2
1248 rol.c %0, %1, %2"
1249 [(set_attr "type" "arith")
1250 (set_attr "mode" "SI")])
1252 (define_expand "rotrsi3"
1253 [(parallel
1254 [(set (match_operand:SI 0 "score_register_operand")
1255 (rotatert:SI (match_operand:SI 1 "score_register_operand")
1256 (match_operand:SI 2 "arith_operand")))
1257 (clobber (reg:CC CC_REGNUM))])]
1258 ""
1259 ""
1260 )
1262 (define_insn "*rotrsi3_score7"
1263 [(set (match_operand:SI 0 "register_operand" "=d,d")
1264 (rotatert:SI (match_operand:SI 1 "register_operand" "d,d")
1265 (match_operand:SI 2 "arith_operand" "J,d")))
1266 (clobber (reg:CC CC_REGNUM))]
1267 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1268 "@
1269 rori.c %0, %1, %c2
1270 ror.c %0, %1, %2"
1271 [(set_attr "type" "arith")
1272 (set_attr "mode" "SI")])
1274 (define_expand "cbranchsi4"
1275 [(set (reg:CC CC_REGNUM)
1276 (compare:CC (match_operand:SI 1 "score_register_operand" "")
1277 (match_operand:SI 2 "arith_operand" "")))
1278 (set (pc)
1279 (if_then_else
1280 (match_operator 0 "ordered_comparison_operator"
1281 [(reg:CC CC_REGNUM)
1282 (const_int 0)])
1283 (label_ref (match_operand 3 "" ""))
1284 (pc)))]
1285 ""
1286 "")
1288 (define_insn "cmpsi_nz_score7"
1289 [(set (reg:CC_NZ CC_REGNUM)
1290 (compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")
1291 (match_operand:SI 1 "arith_operand" "L,e,d")))]
1292 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1293 "@
1294 cmpi.c %0, %c1
1295 cmp! %0, %1
1296 cmp.c %0, %1"
1297 [(set_attr "type" "cmp")
1298 (set_attr "up_c" "yes")
1299 (set_attr "mode" "SI")])
1301 (define_insn "cmpsi_n_score7"
1302 [(set (reg:CC_N CC_REGNUM)
1303 (compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")
1304 (match_operand:SI 1 "arith_operand" "L,e,d")))]
1305 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1306 "@
1307 cmpi.c %0, %c1
1308 cmp! %0, %1
1309 cmp.c %0, %1"
1310 [(set_attr "type" "cmp")
1311 (set_attr "up_c" "yes")
1312 (set_attr "mode" "SI")])
1314 (define_insn "*cmpsi_to_addsi_score7"
1315 [(set (reg:CC_NZ CC_REGNUM)
1316 (compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")
1317 (neg:SI (match_operand:SI 2 "register_operand" "e,d"))))
1318 (clobber (match_scratch:SI 0 "=e,d"))]
1319 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1320 "@
1321 add! %0, %2
1322 add.c %0, %1, %2"
1323 [(set_attr "type" "cmp")
1324 (set_attr "up_c" "yes")
1325 (set_attr "mode" "SI")])
1327 (define_insn "cmpsi_cc_score7"
1328 [(set (reg:CC CC_REGNUM)
1329 (compare:CC (match_operand:SI 0 "register_operand" "d,e,d")
1330 (match_operand:SI 1 "arith_operand" "L,e,d")))]
1331 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1332 "@
1333 cmpi.c %0, %c1
1334 cmp! %0, %1
1335 cmp.c %0, %1"
1336 [(set_attr "type" "cmp")
1337 (set_attr "up_c" "yes")
1338 (set_attr "mode" "SI")])
1340 (define_insn "*branch_n_score7"
1341 [(set (pc)
1342 (if_then_else
1343 (match_operator 0 "branch_n_operator"
1344 [(reg:CC_N CC_REGNUM)
1345 (const_int 0)])
1346 (label_ref (match_operand 1 "" ""))
1347 (pc)))]
1348 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1349 "b%C0 %1"
1350 [(set_attr "type" "branch")])
1352 (define_insn "*branch_nz_score7"
1353 [(set (pc)
1354 (if_then_else
1355 (match_operator 0 "branch_nz_operator"
1356 [(reg:CC_NZ CC_REGNUM)
1357 (const_int 0)])
1358 (label_ref (match_operand 1 "" ""))
1359 (pc)))]
1360 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1361 "b%C0 %1"
1362 [(set_attr "type" "branch")])
1364 (define_insn "*branch_cc_score7"
1365 [(set (pc)
1366 (if_then_else
1367 (match_operator 0 "comparison_operator"
1368 [(reg:CC CC_REGNUM)
1369 (const_int 0)])
1370 (label_ref (match_operand 1 "" ""))
1371 (pc)))]
1372 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1373 "b%C0 %1"
1374 [(set_attr "type" "branch")])
1376 (define_insn "jump"
1377 [(set (pc)
1378 (label_ref (match_operand 0 "" "")))]
1379 ""
1380 {
1381 if (!flag_pic)
1382 return \"j\t%0\";
1383 else
1384 return \"b\t%0\";
1385 }
1386 [(set_attr "type" "jump")
1387 (set_attr "length" "4")])
1389 (define_expand "sibcall"
1390 [(parallel [(call (match_operand 0 "" "")
1391 (match_operand 1 "" ""))
1392 (use (match_operand 2 "" ""))])]
1393 ""
1394 {
1395 score_call (operands, true);
1396 DONE;
1397 })
1399 (define_insn "sibcall_internal_score7"
1400 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
1401 (match_operand 1 "" ""))
1402 (clobber (reg:SI RT_REGNUM))]
1403 "(TARGET_SCORE7 || TARGET_SCORE7D)
1404 && SIBLING_CALL_P (insn)"
1405 {
1406 if (!flag_pic)
1407 switch (which_alternative)
1408 {
1409 case 0: return \"br%S0\t%0\";
1410 case 1: return \"j\t%0\";
1411 default: gcc_unreachable ();
1412 }
1413 else
1414 switch (which_alternative)
1415 {
1416 case 0: return \"mv\tr29, %0\;br\tr29\";
1417 case 1: return \"la\tr29, %0\;br\tr29\";
1418 default: gcc_unreachable ();
1419 }
1420 }
1421 [(set_attr "type" "call")])
1423 (define_expand "sibcall_value"
1424 [(parallel [(set (match_operand 0 "" "")
1425 (call (match_operand 1 "" "") (match_operand 2 "" "")))
1426 (use (match_operand 3 "" ""))])]
1427 ""
1428 {
1429 score_call_value (operands, true);
1430 DONE;
1431 })
1433 (define_insn "sibcall_value_internal_score7"
1434 [(set (match_operand 0 "register_operand" "=d,d")
1435 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
1436 (match_operand 2 "" "")))
1437 (clobber (reg:SI RT_REGNUM))]
1438 "(TARGET_SCORE7 || TARGET_SCORE7D)
1439 && SIBLING_CALL_P (insn)"
1440 {
1441 if (!flag_pic)
1442 switch (which_alternative)
1443 {
1444 case 0: return \"br%S1\t%1\";
1445 case 1: return \"j\t%1\";
1446 default: gcc_unreachable ();
1447 }
1448 else
1449 switch (which_alternative)
1450 {
1451 case 0: return \"mv\tr29, %1\;br\tr29\";
1452 case 1: return \"la\tr29, %1\;br\tr29\";
1453 default: gcc_unreachable ();
1454 }
1455 }
1456 [(set_attr "type" "call")])
1458 (define_expand "call"
1459 [(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))
1460 (use (match_operand 2 "" ""))])]
1461 ""
1462 {
1463 score_call (operands, false);
1464 DONE;
1465 })
1467 (define_insn "call_internal_score7"
1468 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
1469 (match_operand 1 "" ""))
1470 (clobber (reg:SI RA_REGNUM))]
1471 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1472 {
1473 if (!flag_pic)
1474 switch (which_alternative)
1475 {
1476 case 0: return \"brl%S0\t%0\";
1477 case 1: return \"jl\t%0\";
1478 default: gcc_unreachable ();
1479 }
1480 else
1481 switch (which_alternative)
1482 {
1483 case 0: return \"mv\tr29, %0\;brl\tr29\";
1484 case 1: return \"la\tr29, %0\;brl\tr29\";
1485 default: gcc_unreachable ();
1486 }
1487 }
1488 [(set_attr "type" "call")])
1490 (define_expand "call_value"
1491 [(parallel [(set (match_operand 0 "" "")
1492 (call (match_operand 1 "" "") (match_operand 2 "" "")))
1493 (use (match_operand 3 "" ""))])]
1494 ""
1495 {
1496 score_call_value (operands, false);
1497 DONE;
1498 })
1500 (define_insn "call_value_internal_score7"
1501 [(set (match_operand 0 "register_operand" "=d,d")
1502 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
1503 (match_operand 2 "" "")))
1504 (clobber (reg:SI RA_REGNUM))]
1505 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1506 {
1507 if (!flag_pic)
1508 switch (which_alternative)
1509 {
1510 case 0: return \"brl%S1\t%1\";
1511 case 1: return \"jl\t%1\";
1512 default: gcc_unreachable ();
1513 }
1514 else
1515 switch (which_alternative)
1516 {
1517 case 0: return \"mv\tr29, %1\;brl\tr29\";
1518 case 1: return \"la\tr29, %1\;brl\tr29\";
1519 default: gcc_unreachable ();
1520 }
1521 }
1522 [(set_attr "type" "call")])
1524 (define_expand "indirect_jump"
1525 [(set (pc) (match_operand 0 "score_register_operand" "d"))]
1526 ""
1527 {
1528 rtx dest;
1529 dest = operands[0];
1530 if (GET_CODE (dest) != REG
1531 || GET_MODE (dest) != Pmode)
1532 operands[0] = copy_to_mode_reg (Pmode, dest);
1534 emit_jump_insn (gen_indirect_jump_internal_score (operands[0]));
1535 DONE;
1536 })
1538 (define_insn "indirect_jump_internal_score"
1539 [(set (pc) (match_operand:SI 0 "score_register_operand" "d"))]
1540 ""
1541 "br%S0 %0"
1542 [(set_attr "type" "jump")])
1544 (define_expand "tablejump"
1545 [(set (pc)
1546 (match_operand 0 "score_register_operand" "d"))
1547 (use (label_ref (match_operand 1 "" "")))]
1548 ""
1549 {
1550 if (TARGET_SCORE7 || TARGET_SCORE7D)
1551 emit_jump_insn (gen_tablejump_internal_score7 (operands[0], operands[1]));
1553 DONE;
1554 })
1556 (define_insn "tablejump_internal_score7"
1557 [(set (pc)
1558 (match_operand:SI 0 "register_operand" "d"))
1559 (use (label_ref (match_operand 1 "" "")))]
1560 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1561 {
1562 if (flag_pic)
1563 return \"mv\tr29, %0\;.cpadd\tr29\;br\tr29\";
1564 else
1565 return \"br%S0\t%0\";
1566 }
1567 [(set_attr "type" "jump")])
1569 (define_expand "prologue"
1570 [(const_int 1)]
1571 ""
1572 {
1573 score_prologue ();
1574 DONE;
1575 })
1577 (define_expand "epilogue"
1578 [(const_int 2)]
1579 ""
1580 {
1581 score_epilogue (false);
1582 DONE;
1583 })
1585 (define_expand "sibcall_epilogue"
1586 [(const_int 2)]
1587 ""
1588 {
1589 score_epilogue (true);
1590 DONE;
1591 })
1593 (define_insn "return_internal_score7"
1594 [(return)
1595 (use (match_operand 0 "pmode_register_operand" "d"))]
1596 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1597 "br%S0\t%0")
1599 (define_insn "nop"
1600 [(const_int 0)]
1601 ""
1602 "#nop!"
1603 )
1605 (define_insn "cpload_score7"
1606 [(unspec_volatile:SI [(const_int 1)] CPLOAD)]
1607 "(TARGET_SCORE7 || TARGET_SCORE7D)
1608 && flag_pic"
1609 ".cpload\tr29"
1610 )
1612 (define_insn "cprestore_use_fp_score7"
1613 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
1614 (use (reg:SI FP_REGNUM))]
1615 "(TARGET_SCORE7 || TARGET_SCORE7D)
1616 && flag_pic"
1617 ".cprestore\tr2, %0"
1618 )
1620 (define_insn "cprestore_use_sp_score7"
1621 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
1622 (use (reg:SI SP_REGNUM))]
1623 "(TARGET_SCORE7 || TARGET_SCORE7D)
1624 && flag_pic"
1625 ".cprestore\tr0, %0"
1626 )
1628 (define_insn "pushsi_score7"
1629 [(set (match_operand:SI 0 "push_operand" "=<")
1630 (match_operand:SI 1 "register_operand" "d"))]
1631 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1632 "push!\t%1, [r0]"
1633 [(set_attr "type" "store")
1634 (set_attr "mode" "SI")])
1636 (define_insn "popsi_score7"
1637 [(set (match_operand:SI 0 "register_operand" "=d")
1638 (match_operand:SI 1 "pop_operand" ">"))]
1639 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1640 "pop!\t%0, [r0]"
1641 [(set_attr "type" "store")
1642 (set_attr "mode" "SI")])
1644 (define_peephole2
1645 [(set (match_operand:SI 0 "g32reg_operand" "")
1646 (match_operand:SI 1 "loreg_operand" ""))
1647 (set (match_operand:SI 2 "g32reg_operand" "")
1648 (match_operand:SI 3 "hireg_operand" ""))]
1649 ""
1650 [(parallel
1651 [(set (match_dup 0) (match_dup 1))
1652 (set (match_dup 2) (match_dup 3))])])
1654 (define_peephole2
1655 [(set (match_operand:SI 0 "g32reg_operand" "")
1656 (match_operand:SI 1 "hireg_operand" ""))
1657 (set (match_operand:SI 2 "g32reg_operand" "")
1658 (match_operand:SI 3 "loreg_operand" ""))]
1659 ""
1660 [(parallel
1661 [(set (match_dup 2) (match_dup 3))
1662 (set (match_dup 0) (match_dup 1))])])
1664 (define_insn "movhilo"
1665 [(parallel
1666 [(set (match_operand:SI 0 "register_operand" "=d")
1667 (match_operand:SI 1 "loreg_operand" ""))
1668 (set (match_operand:SI 2 "register_operand" "=d")
1669 (match_operand:SI 3 "hireg_operand" ""))])]
1670 ""
1671 "mfcehl\t%2, %0"
1672 [(set_attr "type" "fce")
1673 (set_attr "mode" "SI")])
1675 (define_expand "movsicc"
1676 [(set (match_operand:SI 0 "register_operand" "")
1677 (if_then_else:SI (match_operator 1 "comparison_operator"
1678 [(reg:CC CC_REGNUM) (const_int 0)])
1679 (match_operand:SI 2 "register_operand" "")
1680 (match_operand:SI 3 "register_operand" "")))]
1681 ""
1682 {
1683 score_movsicc (operands);
1684 })
1686 (define_insn "movsicc_internal_score7"
1687 [(set (match_operand:SI 0 "register_operand" "=d")
1688 (if_then_else:SI (match_operator 1 "comparison_operator"
1689 [(reg:CC CC_REGNUM) (const_int 0)])
1690 (match_operand:SI 2 "arith_operand" "d")
1691 (match_operand:SI 3 "arith_operand" "0")))]
1692 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1693 "mv%C1\t%0, %2"
1694 [(set_attr "type" "cndmv")
1695 (set_attr "mode" "SI")])
1697 (define_insn "zero_extract_bittst_score7"
1698 [(set (reg:CC_NZ CC_REGNUM)
1699 (compare:CC_NZ (unspec:SI
1700 [(match_operand:SI 0 "register_operand" "*e,d")
1701 (match_operand:SI 1 "const_uimm5" "")]
1702 BITTST)
1703 (const_int 0)))]
1704 "(TARGET_SCORE7 || TARGET_SCORE7D)"
1705 "@
1706 bittst!\t%0, %c1
1707 bittst.c\t%0, %c1"
1708 [(set_attr "type" "arith")
1709 (set_attr "up_c" "yes")
1710 (set_attr "mode" "SI")])
1712 (define_insn "andsi3_extzh"
1713 [(set (match_operand:SI 0 "register_operand" "=d")
1714 (and:SI (match_operand:SI 1 "register_operand" "d")
1715 (const_int 65535)))]
1716 ""
1717 "extzh\t%0, %1"
1718 [(set_attr "type" "arith")
1719 (set_attr "length" "4")
1720 (set_attr "mode" "SI")])
1722 (define_insn "clzsi2"
1723 [(set (match_operand:SI 0 "register_operand" "=d")
1724 (clz:SI (match_operand:SI 1 "register_operand" "d")))]
1725 "(TARGET_SCORE7D)"
1726 "clz\t%0, %1"
1727 [(set_attr "type" "arith")
1728 (set_attr "mode" "SI")])
1730 (define_insn "smaxsi3"
1731 [(set (match_operand:SI 0 "register_operand" "=d")
1732 (smax:SI (match_operand:SI 1 "register_operand" "d")
1733 (match_operand:SI 2 "register_operand" "d")))]
1734 "(TARGET_SCORE7D)"
1735 "max\t%0, %1, %2"
1736 [(set_attr "type" "arith")
1737 (set_attr "mode" "SI")])
1739 (define_insn "sminsi3"
1740 [(set (match_operand:SI 0 "register_operand" "=d")
1741 (smin:SI (match_operand:SI 1 "register_operand" "d")
1742 (match_operand:SI 2 "register_operand" "d")))]
1743 "(TARGET_SCORE7D)"
1744 "min\t%0, %1, %2"
1745 [(set_attr "type" "arith")
1746 (set_attr "mode" "SI")])
1748 (define_insn "abssi2"
1749 [(set (match_operand:SI 0 "register_operand" "=d")
1750 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1751 "(TARGET_SCORE7D)"
1752 "abs\t%0, %1"
1753 [(set_attr "type" "arith")
1754 (set_attr "mode" "SI")])
1756 (define_insn "sffs"
1757 [(set (match_operand:SI 0 "register_operand" "=d")
1758 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]
1759 "(TARGET_SCORE7D)"
1760 "bitrev\t%0, %1, r0\;clz\t%0, %0\;addi\t%0, 0x1"
1761 [(set_attr "type" "arith")
1762 (set_attr "mode" "SI")])
1764 (define_expand "ffssi2"
1765 [(set (match_operand:SI 0 "register_operand")
1766 (ffs:SI (match_operand:SI 1 "register_operand")))]
1767 "(TARGET_SCORE7D)"
1768 {
1769 emit_insn (gen_sffs (operands[0], operands[1]));
1770 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),
1771 gen_rtx_COMPARE (CC_NZmode, operands[0],
1772 GEN_INT (33))));
1773 if (TARGET_SCORE7D)
1774 emit_insn (gen_movsicc_internal_score7 (operands[0],
1775 gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
1776 GEN_INT (0),
1777 operands[0]));
1778 DONE;
1779 })
1781 (define_peephole2
1782 [(set (match_operand:SI 0 "loreg_operand" "")
1783 (match_operand:SI 1 "register_operand" ""))
1784 (set (match_operand:SI 2 "hireg_operand" "")
1785 (match_operand:SI 3 "register_operand" ""))]
1786 "(TARGET_SCORE7D)"
1787 [(parallel
1788 [(set (match_dup 0) (match_dup 1))
1789 (set (match_dup 2) (match_dup 3))])])
1791 (define_peephole2
1792 [(set (match_operand:SI 0 "hireg_operand" "")
1793 (match_operand:SI 1 "register_operand" ""))
1794 (set (match_operand:SI 2 "loreg_operand" "")
1795 (match_operand:SI 3 "register_operand" ""))]
1796 "(TARGET_SCORE7D)"
1797 [(parallel
1798 [(set (match_dup 2) (match_dup 3))
1799 (set (match_dup 0) (match_dup 1))])])
1801 (define_insn "movtohilo"
1802 [(parallel
1803 [(set (match_operand:SI 0 "loreg_operand" "=l")
1804 (match_operand:SI 1 "register_operand" "d"))
1805 (set (match_operand:SI 2 "hireg_operand" "=h")
1806 (match_operand:SI 3 "register_operand" "d"))])]
1807 "(TARGET_SCORE7D)"
1808 "mtcehl\t%3, %1"
1809 [(set_attr "type" "fce")
1810 (set_attr "mode" "SI")])
1812 (define_insn "mulsi3addsi"
1813 [(set (match_operand:SI 0 "register_operand" "=l,l,d")
1814 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1815 (match_operand:SI 3 "register_operand" "d,d,d"))
1816 (match_operand:SI 1 "register_operand" "0,d,l")))
1817 (clobber (reg:SI HI_REGNUM))]
1818 "(TARGET_SCORE7D)"
1819 "@
1820 mad\t%2, %3
1821 mtcel%S1\t%1\;mad\t%2, %3
1822 mad\t%2, %3\;mfcel%S0\t%0"
1823 [(set_attr "mode" "SI")])
1825 (define_insn "mulsi3subsi"
1826 [(set (match_operand:SI 0 "register_operand" "=l,l,d")
1827 (minus:SI (match_operand:SI 1 "register_operand" "0,d,l")
1828 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1829 (match_operand:SI 3 "register_operand" "d,d,d"))))
1830 (clobber (reg:SI HI_REGNUM))]
1831 "(TARGET_SCORE7D)"
1832 "@
1833 msb\t%2, %3
1834 mtcel%S1\t%1\;msb\t%2, %3
1835 msb\t%2, %3\;mfcel%S0\t%0"
1836 [(set_attr "mode" "SI")])
1838 (define_insn "mulsidi3adddi"
1839 [(set (match_operand:DI 0 "register_operand" "=x")
1840 (plus:DI (mult:DI
1841 (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
1842 (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))
1843 (match_operand:DI 1 "register_operand" "0")))]
1844 "(TARGET_SCORE7D)"
1845 "mad\t%2, %3"
1846 [(set_attr "mode" "DI")])
1848 (define_insn "umulsidi3adddi"
1849 [(set (match_operand:DI 0 "register_operand" "=x")
1850 (plus:DI (mult:DI
1851 (zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))
1852 (zero_extend:DI (match_operand:SI 3 "register_operand" "d")))
1853 (match_operand:DI 1 "register_operand" "0")))]
1854 "(TARGET_SCORE7D)"
1855 "madu\t%2, %3"
1856 [(set_attr "mode" "DI")])
1858 (define_insn "mulsidi3subdi"
1859 [(set (match_operand:DI 0 "register_operand" "=x")
1860 (minus:DI
1861 (match_operand:DI 1 "register_operand" "0")
1862 (mult:DI
1863 (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
1864 (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]
1865 "(TARGET_SCORE7D)"
1866 "msb\t%2, %3"
1867 [(set_attr "mode" "DI")])
1869 (define_insn "umulsidi3subdi"
1870 [(set (match_operand:DI 0 "register_operand" "=x")
1871 (minus:DI
1872 (match_operand:DI 1 "register_operand" "0")
1873 (mult:DI (zero_extend:DI
1874 (match_operand:SI 2 "register_operand" "%d"))
1875 (zero_extend:DI
1876 (match_operand:SI 3 "register_operand" "d")))))]
1877 "(TARGET_SCORE7D)"
1878 "msbu\t%2, %3"
1879 [(set_attr "mode" "DI")])