1 ;; Constraint definitions for ARM and Thumb
2 ;; Copyright (C) 2006-2017 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The following register constraints have been used:
22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
23 ;; - in Thumb state: h, b
24 ;; - in both states: l, c, k, q, Cs, Ts, US
25 ;; In ARM state, 'l' is an alias for 'r'
26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
28 ;; The following normal constraints have been used:
29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
30 ;; in Thumb-1 state: I, J, K, L, M, N, O
31 ;; 'H' was previously used for FPA.
33 ;; The following multi-letter normal constraints have been used:
34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp, Dz
35 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
36 ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
39 ;; The following memory constraints have been used:
40 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
42 ;; in Thumb state: Uu, Uw
46 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
47 "The VFP registers @code{s0}-@code{s31}.")
49 (define_register_constraint "w"
50 "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
51 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
53 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
54 "The VFP registers @code{d0}-@code{d7}.")
56 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
57 "The Intel iWMMX co-processor registers.")
59 (define_register_constraint "z"
60 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
61 "The Intel iWMMX GR registers.")
63 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
64 "In Thumb state the core registers @code{r0}-@code{r7}.")
66 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
67 "In Thumb state the core registers @code{r8}-@code{r15}.")
69 (define_constraint "j"
70 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
71 (and (match_test "TARGET_HAVE_MOVT")
72 (ior (and (match_code "high")
73 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
74 (and (match_code "const_int")
75 (match_test "(ival & 0xffff0000) == 0")))))
77 (define_constraint "Pj"
78 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
79 (and (match_code "const_int")
80 (and (match_test "TARGET_THUMB2")
81 (match_test "(ival & 0xfffff000) == 0"))))
83 (define_constraint "PJ"
84 "@internal A constant that satisfies the Pj constrant if negated."
85 (and (match_code "const_int")
86 (and (match_test "TARGET_THUMB2")
87 (match_test "((-ival) & 0xfffff000) == 0"))))
89 (define_register_constraint "k" "STACK_REG"
90 "@internal The stack register.")
92 (define_register_constraint "q" "(TARGET_ARM && TARGET_LDRD) ? CORE_REGS : GENERAL_REGS"
93 "@internal In ARM state with LDRD support, core registers, otherwise general registers.")
95 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
97 Thumb only. The union of the low registers and the stack register.")
99 (define_register_constraint "c" "CC_REG"
100 "@internal The condition code register.")
102 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
103 "@internal The caller save registers. Useful for sibcalls.")
105 (define_constraint "I"
106 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
107 Data Processing instruction. In Thumb-1 state a constant in the range
109 (and (match_code "const_int")
110 (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
111 : ival >= 0 && ival <= 255")))
113 (define_constraint "J"
114 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
115 state a constant in the range @minus{}255-@minus{}1."
116 (and (match_code "const_int")
117 (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
118 : (ival >= -255 && ival <= -1)")))
120 (define_constraint "K"
121 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
122 inverted. In Thumb-1 state a constant that satisfies the @code{I}
123 constraint multiplied by any power of 2."
124 (and (match_code "const_int")
125 (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
126 : thumb_shiftable_const (ival)")))
128 (define_constraint "L"
129 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
130 negated. In Thumb-1 state a constant in the range @minus{}7-7."
131 (and (match_code "const_int")
132 (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
133 : (ival >= -7 && ival <= 7)")))
135 ;; The ARM state version is internal...
136 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
138 (define_constraint "M"
139 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
140 (and (match_code "const_int")
141 (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
142 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
143 : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
145 (define_constraint "N"
146 "Thumb-1 state a constant in the range 0-31."
147 (and (match_code "const_int")
148 (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
150 (define_constraint "O"
151 "In Thumb-1 state a constant that is a multiple of 4 in the range
153 (and (match_code "const_int")
154 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
155 && ((ival & 3) == 0)")))
157 (define_constraint "Pa"
158 "@internal In Thumb-1 state a constant in the range -510 to +510"
159 (and (match_code "const_int")
160 (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
161 && (ival > 255 || ival < -255)")))
163 (define_constraint "Pb"
164 "@internal In Thumb-1 state a constant in the range -262 to +262"
165 (and (match_code "const_int")
166 (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
167 && (ival > 255 || ival < -255)")))
169 (define_constraint "Pc"
170 "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
171 (and (match_code "const_int")
172 (match_test "TARGET_THUMB1
173 && ival > 1020 && ival <= 1275")))
175 (define_constraint "Pd"
176 "@internal In Thumb state a constant in the range 0 to 7"
177 (and (match_code "const_int")
178 (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
180 (define_constraint "Pe"
181 "@internal In Thumb-1 state a constant in the range 256 to +510"
182 (and (match_code "const_int")
183 (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
185 (define_constraint "Pf"
186 "Memory models except relaxed, consume or release ones."
187 (and (match_code "const_int")
188 (match_test "!is_mm_relaxed (memmodel_from_int (ival))
189 && !is_mm_consume (memmodel_from_int (ival))
190 && !is_mm_release (memmodel_from_int (ival))")))
192 (define_constraint "Ps"
193 "@internal In Thumb-2 state a constant in the range -255 to +255"
194 (and (match_code "const_int")
195 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
197 (define_constraint "Pt"
198 "@internal In Thumb-2 state a constant in the range -7 to +7"
199 (and (match_code "const_int")
200 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
202 (define_constraint "Pu"
203 "@internal In Thumb-2 state a constant in the range +1 to +8"
204 (and (match_code "const_int")
205 (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
207 (define_constraint "Pv"
208 "@internal In Thumb-2 state a constant in the range -255 to 0"
209 (and (match_code "const_int")
210 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
212 (define_constraint "Pw"
213 "@internal In Thumb-2 state a constant in the range -255 to -1"
214 (and (match_code "const_int")
215 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
217 (define_constraint "Px"
218 "@internal In Thumb-2 state a constant in the range -7 to -1"
219 (and (match_code "const_int")
220 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
222 (define_constraint "Py"
223 "@internal In Thumb-2 state a constant in the range 0 to 255"
224 (and (match_code "const_int")
225 (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
227 (define_constraint "Pz"
228 "@internal In Thumb-2 state the constant 0"
229 (and (match_code "const_int")
230 (match_test "TARGET_THUMB2 && (ival == 0)")))
232 (define_constraint "G"
233 "In ARM/Thumb-2 state the floating-point constant 0."
234 (and (match_code "const_double")
235 (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
237 (define_constraint "Dz"
239 In ARM/Thumb-2 state a vector of constant zeros."
240 (and (match_code "const_vector")
241 (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
243 (define_constraint "Da"
245 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
246 be generated with two Data Processing insns."
247 (and (match_code "const_double,const_int,const_vector")
248 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
250 (define_constraint "Db"
252 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
253 be generated with three Data Processing insns."
254 (and (match_code "const_double,const_int,const_vector")
255 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
257 (define_constraint "Dc"
259 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
260 be generated with four Data Processing insns. This pattern is disabled
261 if optimizing for space or when we have load-delay slots to fill."
262 (and (match_code "const_double,const_int,const_vector")
263 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
264 && !(optimize_size || arm_ld_sched)")))
266 (define_constraint "Dd"
268 In ARM/Thumb-2 state a const_int that can be used by insn adddi."
269 (and (match_code "const_int")
270 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
272 (define_constraint "De"
274 In ARM/Thumb-2 state a const_int that can be used by insn anddi."
275 (and (match_code "const_int")
276 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)")))
278 (define_constraint "Df"
280 In ARM/Thumb-2 state a const_int that can be used by insn iordi."
281 (and (match_code "const_int")
282 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)")))
284 (define_constraint "Dg"
286 In ARM/Thumb-2 state a const_int that can be used by insn xordi."
287 (and (match_code "const_int")
288 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)")))
290 (define_constraint "Di"
292 In ARM/Thumb-2 state a const_int or const_double where both the high
293 and low SImode words can be generated as immediates in 32-bit instructions."
294 (and (match_code "const_double,const_int")
295 (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
297 (define_constraint "Dn"
299 In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
300 Neon vmov immediate instruction."
301 (and (match_code "const_vector,const_int")
302 (match_test "TARGET_32BIT
303 && imm_for_neon_mov_operand (op, GET_MODE (op))")))
305 (define_constraint "Dl"
307 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
309 (and (match_code "const_vector")
310 (match_test "TARGET_32BIT
311 && imm_for_neon_logic_operand (op, GET_MODE (op))")))
313 (define_constraint "DL"
315 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
317 (and (match_code "const_vector")
318 (match_test "TARGET_32BIT
319 && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
321 (define_constraint "Do"
323 In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
324 (and (match_code "const_int")
325 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
327 (define_constraint "Dv"
329 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
331 (and (match_code "const_double")
332 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
334 (define_constraint "Dy"
336 In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
338 (and (match_code "const_double")
339 (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
341 (define_constraint "Dt"
343 In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
344 (and (match_code "const_double")
345 (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
347 (define_constraint "Dp"
349 In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
350 (and (match_code "const_double")
351 (match_test "TARGET_32BIT
352 && vfp3_const_double_for_bits (op) > 0")))
354 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
355 "For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.")
357 (define_memory_constraint "Ua"
359 An address valid for loading/storing register exclusive"
360 (match_operand 0 "mem_noofs_operand"))
362 (define_memory_constraint "Uh"
364 An address suitable for byte and half-word loads which does not point inside a constant pool"
365 (and (match_code "mem")
366 (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
368 (define_memory_constraint "Ut"
370 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
371 types wider than TImode."
372 (and (match_code "mem")
373 (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
375 (define_memory_constraint "Uv"
377 In ARM/Thumb-2 state a valid VFP load/store address."
378 (and (match_code "mem")
379 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
381 (define_memory_constraint "Uy"
383 In ARM/Thumb-2 state a valid iWMMX load/store address."
384 (and (match_code "mem")
385 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
387 (define_memory_constraint "Un"
389 In ARM/Thumb-2 state a valid address for Neon doubleword vector
390 load/store instructions."
391 (and (match_code "mem")
392 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
394 (define_memory_constraint "Um"
396 In ARM/Thumb-2 state a valid address for Neon element and structure
397 load/store instructions."
398 (and (match_code "mem")
399 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
401 (define_memory_constraint "Us"
403 In ARM/Thumb-2 state a valid address for non-offset loads/stores of
404 quad-word values in four ARM registers."
405 (and (match_code "mem")
406 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
408 (define_memory_constraint "Uq"
410 In ARM state an address valid in ldrsb instructions."
411 (and (match_code "mem")
412 (match_test "TARGET_ARM
413 && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
415 && !arm_is_constant_pool_ref (op)")))
417 (define_memory_constraint "Q"
419 An address that is a single base register."
420 (and (match_code "mem")
421 (match_test "REG_P (XEXP (op, 0))")))
423 (define_memory_constraint "Uu"
425 In Thumb state an address that is valid in 16bit encoding."
426 (and (match_code "mem")
427 (match_test "TARGET_THUMB
428 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
431 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
432 ; are actually LDM/STM instructions, so cannot be used to access unaligned
434 (define_memory_constraint "Uw"
436 In Thumb state an address that is valid in 16bit encoding, and that can be
437 used for unaligned accesses."
438 (and (match_code "mem")
439 (match_test "TARGET_THUMB
440 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
442 && GET_CODE (XEXP (op, 0)) != POST_INC")))
444 (define_constraint "US"
446 US is a symbol reference."
447 (match_code "symbol_ref")
450 (define_memory_constraint "Uz"
452 A memory access that is accessible as an LDC/STC operand"
453 (and (match_code "mem")
454 (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
456 ;; We used to have constraint letters for S and R in ARM state, but
457 ;; all uses of these now appear to have been removed.
459 ;; Additionally, we used to have a Q constraint in Thumb state, but
460 ;; this wasn't really a valid memory constraint. Again, all uses of
461 ;; this now seem to have been removed.