1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2016 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
125 #include "addresses.h"
128 #include "rtl-error.h"
132 #include "print-rtl.h"
134 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
135 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 static int bb_reload_num
;
139 /* The current insn being processed and corresponding its single set
140 (NULL otherwise), its data (basic block, the insn data, the insn
141 static data, and the mode of each operand). */
142 static rtx_insn
*curr_insn
;
143 static rtx curr_insn_set
;
144 static basic_block curr_bb
;
145 static lra_insn_recog_data_t curr_id
;
146 static struct lra_static_insn_data
*curr_static_id
;
147 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
148 /* Mode of the register substituted by its equivalence with VOIDmode
149 (e.g. constant) and whose subreg is given operand of the current
150 insn. VOIDmode in all other cases. */
151 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
155 /* Start numbers for new registers and insns at the current constraints
157 static int new_regno_start
;
158 static int new_insn_uid_start
;
160 /* If LOC is nonnull, strip any outer subreg from it. */
162 strip_subreg (rtx
*loc
)
164 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
167 /* Return hard regno of REGNO or if it is was not assigned to a hard
168 register, use a hard register from its allocno class. */
170 get_try_hard_regno (int regno
)
173 enum reg_class rclass
;
175 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
176 hard_regno
= lra_get_regno_hard_regno (regno
);
179 rclass
= lra_get_allocno_class (regno
);
180 if (rclass
== NO_REGS
)
182 return ira_class_hard_regs
[rclass
][0];
185 /* Return final hard regno (plus offset) which will be after
186 elimination. We do this for matching constraints because the final
187 hard regno could have a different class. */
189 get_final_hard_regno (int hard_regno
, int offset
)
193 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
194 return hard_regno
+ offset
;
197 /* Return hard regno of X after removing subreg and making
198 elimination. If X is not a register or subreg of register, return
199 -1. For pseudo use its assignment. */
201 get_hard_regno (rtx x
)
204 int offset
, hard_regno
;
207 if (GET_CODE (x
) == SUBREG
)
208 reg
= SUBREG_REG (x
);
211 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
212 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
216 if (GET_CODE (x
) == SUBREG
)
217 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
218 SUBREG_BYTE (x
), GET_MODE (x
));
219 return get_final_hard_regno (hard_regno
, offset
);
222 /* If REGNO is a hard register or has been allocated a hard register,
223 return the class of that register. If REGNO is a reload pseudo
224 created by the current constraints pass, return its allocno class.
225 Return NO_REGS otherwise. */
226 static enum reg_class
227 get_reg_class (int regno
)
231 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
232 hard_regno
= lra_get_regno_hard_regno (regno
);
235 hard_regno
= get_final_hard_regno (hard_regno
, 0);
236 return REGNO_REG_CLASS (hard_regno
);
238 if (regno
>= new_regno_start
)
239 return lra_get_allocno_class (regno
);
243 /* Return true if REG satisfies (or will satisfy) reg class constraint
244 CL. Use elimination first if REG is a hard register. If REG is a
245 reload pseudo created by this constraints pass, assume that it will
246 be allocated a hard register from its allocno class, but allow that
247 class to be narrowed to CL if it is currently a superset of CL.
249 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
250 REGNO (reg), or NO_REGS if no change in its class was needed. */
252 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
254 enum reg_class rclass
, common_class
;
255 machine_mode reg_mode
;
256 int class_size
, hard_regno
, nregs
, i
, j
;
257 int regno
= REGNO (reg
);
259 if (new_class
!= NULL
)
260 *new_class
= NO_REGS
;
261 if (regno
< FIRST_PSEUDO_REGISTER
)
264 rtx
*final_loc
= &final_reg
;
266 lra_eliminate_reg_if_possible (final_loc
);
267 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
269 reg_mode
= GET_MODE (reg
);
270 rclass
= get_reg_class (regno
);
271 if (regno
< new_regno_start
272 /* Do not allow the constraints for reload instructions to
273 influence the classes of new pseudos. These reloads are
274 typically moves that have many alternatives, and restricting
275 reload pseudos for one alternative may lead to situations
276 where other reload pseudos are no longer allocatable. */
277 || (INSN_UID (curr_insn
) >= new_insn_uid_start
278 && curr_insn_set
!= NULL
279 && ((OBJECT_P (SET_SRC (curr_insn_set
))
280 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
281 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
282 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
283 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
284 /* When we don't know what class will be used finally for reload
285 pseudos, we use ALL_REGS. */
286 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
287 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
288 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
289 lra_no_alloc_regs
)));
292 common_class
= ira_reg_class_subset
[rclass
][cl
];
293 if (new_class
!= NULL
)
294 *new_class
= common_class
;
295 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
298 /* Check that there are enough allocatable regs. */
299 class_size
= ira_class_hard_regs_num
[common_class
];
300 for (i
= 0; i
< class_size
; i
++)
302 hard_regno
= ira_class_hard_regs
[common_class
][i
];
303 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
306 for (j
= 0; j
< nregs
; j
++)
307 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
308 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
318 /* Return true if REGNO satisfies a memory constraint. */
322 return get_reg_class (regno
) == NO_REGS
;
325 /* Return 1 if ADDR is a valid memory address for mode MODE in address
326 space AS, and check that each pseudo has the proper kind of hard
329 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
330 rtx addr
, addr_space_t as
)
332 #ifdef GO_IF_LEGITIMATE_ADDRESS
333 lra_assert (ADDR_SPACE_GENERIC_P (as
));
334 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
340 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
345 /* Temporarily eliminates registers in an address (for the lifetime of
347 class address_eliminator
{
349 address_eliminator (struct address_info
*ad
);
350 ~address_eliminator ();
353 struct address_info
*m_ad
;
361 address_eliminator::address_eliminator (struct address_info
*ad
)
363 m_base_loc (strip_subreg (ad
->base_term
)),
364 m_base_reg (NULL_RTX
),
365 m_index_loc (strip_subreg (ad
->index_term
)),
366 m_index_reg (NULL_RTX
)
368 if (m_base_loc
!= NULL
)
370 m_base_reg
= *m_base_loc
;
371 lra_eliminate_reg_if_possible (m_base_loc
);
372 if (m_ad
->base_term2
!= NULL
)
373 *m_ad
->base_term2
= *m_ad
->base_term
;
375 if (m_index_loc
!= NULL
)
377 m_index_reg
= *m_index_loc
;
378 lra_eliminate_reg_if_possible (m_index_loc
);
382 address_eliminator::~address_eliminator ()
384 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
386 *m_base_loc
= m_base_reg
;
387 if (m_ad
->base_term2
!= NULL
)
388 *m_ad
->base_term2
= *m_ad
->base_term
;
390 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
391 *m_index_loc
= m_index_reg
;
394 /* Return true if the eliminated form of AD is a legitimate target address. */
396 valid_address_p (struct address_info
*ad
)
398 address_eliminator
eliminator (ad
);
399 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
402 /* Return true if the eliminated form of memory reference OP satisfies
403 extra (special) memory constraint CONSTRAINT. */
405 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
407 struct address_info ad
;
409 decompose_mem_address (&ad
, op
);
410 address_eliminator
eliminator (&ad
);
411 return constraint_satisfied_p (op
, constraint
);
414 /* Return true if the eliminated form of address AD satisfies extra
415 address constraint CONSTRAINT. */
417 satisfies_address_constraint_p (struct address_info
*ad
,
418 enum constraint_num constraint
)
420 address_eliminator
eliminator (ad
);
421 return constraint_satisfied_p (*ad
->outer
, constraint
);
424 /* Return true if the eliminated form of address OP satisfies extra
425 address constraint CONSTRAINT. */
427 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
429 struct address_info ad
;
431 decompose_lea_address (&ad
, &op
);
432 return satisfies_address_constraint_p (&ad
, constraint
);
435 /* Initiate equivalences for LRA. As we keep original equivalences
436 before any elimination, we need to make copies otherwise any change
437 in insns might change the equivalences. */
439 lra_init_equiv (void)
441 ira_expand_reg_equiv ();
442 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
446 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
447 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
448 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
449 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
453 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
455 /* Update equivalence for REGNO. We need to this as the equivalence
456 might contain other pseudos which are changed by their
459 update_equiv (int regno
)
463 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
464 ira_reg_equiv
[regno
].memory
465 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
467 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
468 ira_reg_equiv
[regno
].invariant
469 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
473 /* If we have decided to substitute X with another value, return that
474 value, otherwise return X. */
481 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
482 || ! ira_reg_equiv
[regno
].defined_p
483 || ! ira_reg_equiv
[regno
].profitable_p
484 || lra_get_regno_hard_regno (regno
) >= 0)
486 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
488 if (targetm
.cannot_substitute_mem_equiv_p (res
))
492 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
494 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
499 /* If we have decided to substitute X with the equivalent value,
500 return that value after elimination for INSN, otherwise return
503 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
505 rtx res
= get_equiv (x
);
507 if (x
== res
|| CONSTANT_P (res
))
509 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
510 false, false, 0, true);
513 /* Set up curr_operand_mode. */
515 init_curr_operand_mode (void)
517 int nop
= curr_static_id
->n_operands
;
518 for (int i
= 0; i
< nop
; i
++)
520 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
521 if (mode
== VOIDmode
)
523 /* The .md mode for address operands is the mode of the
524 addressed value rather than the mode of the address itself. */
525 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
528 mode
= curr_static_id
->operand
[i
].mode
;
530 curr_operand_mode
[i
] = mode
;
536 /* The page contains code to reuse input reloads. */
538 /* Structure describes input reload of the current insns. */
541 /* Reloaded value. */
543 /* Reload pseudo used. */
547 /* The number of elements in the following array. */
548 static int curr_insn_input_reloads_num
;
549 /* Array containing info about input reloads. It is used to find the
550 same input reload and reuse the reload pseudo in this case. */
551 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
553 /* Initiate data concerning reuse of input reloads for the current
556 init_curr_insn_input_reloads (void)
558 curr_insn_input_reloads_num
= 0;
561 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
562 created input reload pseudo (only if TYPE is not OP_OUT). Don't
563 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
564 wrapped up in SUBREG. The result pseudo is returned through
565 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
566 reused the already created input reload pseudo. Use TITLE to
567 describe new registers for debug purposes. */
569 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
570 enum reg_class rclass
, bool in_subreg_p
,
571 const char *title
, rtx
*result_reg
)
574 enum reg_class new_class
;
579 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
582 /* Prevent reuse value of expression with side effects,
583 e.g. volatile memory. */
584 if (! side_effects_p (original
))
585 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
586 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
587 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
589 rtx reg
= curr_insn_input_reloads
[i
].reg
;
591 /* If input is equal to original and both are VOIDmode,
592 GET_MODE (reg) might be still different from mode.
593 Ensure we don't return *result_reg with wrong mode. */
594 if (GET_MODE (reg
) != mode
)
598 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
600 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
601 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
605 if (lra_dump_file
!= NULL
)
607 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
608 dump_value_slim (lra_dump_file
, original
, 1);
610 if (new_class
!= lra_get_allocno_class (regno
))
611 lra_change_class (regno
, new_class
, ", change to", false);
612 if (lra_dump_file
!= NULL
)
613 fprintf (lra_dump_file
, "\n");
616 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
617 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
618 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
619 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
625 /* The page contains code to extract memory address parts. */
627 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
629 ok_for_index_p_nonstrict (rtx reg
)
631 unsigned regno
= REGNO (reg
);
633 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
636 /* A version of regno_ok_for_base_p for use here, when all pseudos
637 should count as OK. Arguments as for regno_ok_for_base_p. */
639 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
640 enum rtx_code outer_code
, enum rtx_code index_code
)
642 unsigned regno
= REGNO (reg
);
644 if (regno
>= FIRST_PSEUDO_REGISTER
)
646 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
651 /* The page contains major code to choose the current insn alternative
652 and generate reloads for it. */
654 /* Return the offset from REGNO of the least significant register
657 This function is used to tell whether two registers satisfy
658 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
660 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
661 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
663 lra_constraint_offset (int regno
, machine_mode mode
)
665 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
666 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
667 && SCALAR_INT_MODE_P (mode
))
668 return hard_regno_nregs
[regno
][mode
] - 1;
672 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
673 if they are the same hard reg, and has special hacks for
674 auto-increment and auto-decrement. This is specifically intended for
675 process_alt_operands to use in determining whether two operands
676 match. X is the operand whose number is the lower of the two.
678 It is supposed that X is the output operand and Y is the input
679 operand. Y_HARD_REGNO is the final hard regno of register Y or
680 register in subreg Y as we know it now. Otherwise, it is a
683 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
686 RTX_CODE code
= GET_CODE (x
);
691 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
692 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
696 i
= get_hard_regno (x
);
700 if ((j
= y_hard_regno
) < 0)
703 i
+= lra_constraint_offset (i
, GET_MODE (x
));
704 j
+= lra_constraint_offset (j
, GET_MODE (y
));
709 /* If two operands must match, because they are really a single
710 operand of an assembler insn, then two post-increments are invalid
711 because the assembler insn would increment only once. On the
712 other hand, a post-increment matches ordinary indexing if the
713 post-increment is the output operand. */
714 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
715 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
717 /* Two pre-increments are invalid because the assembler insn would
718 increment only once. On the other hand, a pre-increment matches
719 ordinary indexing if the pre-increment is the input operand. */
720 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
721 || GET_CODE (y
) == PRE_MODIFY
)
722 return operands_match_p (x
, XEXP (y
, 0), -1);
726 if (code
== REG
&& REG_P (y
))
727 return REGNO (x
) == REGNO (y
);
729 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
730 && x
== SUBREG_REG (y
))
732 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
733 && SUBREG_REG (x
) == y
)
736 /* Now we have disposed of all the cases in which different rtx
738 if (code
!= GET_CODE (y
))
741 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
742 if (GET_MODE (x
) != GET_MODE (y
))
751 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
753 return XSTR (x
, 0) == XSTR (y
, 0);
759 /* Compare the elements. If any pair of corresponding elements fail
760 to match, return false for the whole things. */
762 fmt
= GET_RTX_FORMAT (code
);
763 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
769 if (XWINT (x
, i
) != XWINT (y
, i
))
774 if (XINT (x
, i
) != XINT (y
, i
))
779 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
788 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
790 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
792 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
798 /* It is believed that rtx's at this level will never
799 contain anything but integers and other rtx's, except for
800 within LABEL_REFs and SYMBOL_REFs. */
808 /* True if X is a constant that can be forced into the constant pool.
809 MODE is the mode of the operand, or VOIDmode if not known. */
810 #define CONST_POOL_OK_P(MODE, X) \
811 ((MODE) != VOIDmode \
813 && GET_CODE (X) != HIGH \
814 && !targetm.cannot_force_const_mem (MODE, X))
816 /* True if C is a non-empty register class that has too few registers
817 to be safely used as a reload target class. */
818 #define SMALL_REGISTER_CLASS_P(C) \
819 (ira_class_hard_regs_num [(C)] == 1 \
820 || (ira_class_hard_regs_num [(C)] >= 1 \
821 && targetm.class_likely_spilled_p (C)))
823 /* If REG is a reload pseudo, try to make its class satisfying CL. */
825 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
827 enum reg_class rclass
;
829 /* Do not make more accurate class from reloads generated. They are
830 mostly moves with a lot of constraints. Making more accurate
831 class may results in very narrow class and impossibility of find
832 registers for several reloads of one insn. */
833 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
835 if (GET_CODE (reg
) == SUBREG
)
836 reg
= SUBREG_REG (reg
);
837 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
839 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
840 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
843 /* Searches X for any reference to a reg with the same value as REGNO,
844 returning the rtx of the reference found if any. Otherwise,
847 regno_val_use_in (unsigned int regno
, rtx x
)
853 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
856 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
857 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
861 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
864 else if (fmt
[i
] == 'E')
865 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
866 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
873 /* Generate reloads for matching OUT and INS (array of input operand
874 numbers with end marker -1) with reg class GOAL_CLASS. Add input
875 and output reloads correspondingly to the lists *BEFORE and *AFTER.
876 OUT might be negative. In this case we generate input reloads for
877 matched input operands INS. EARLY_CLOBBER_P is a flag that the
878 output operand is early clobbered for chosen alternative. */
880 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
881 rtx_insn
**before
, rtx_insn
**after
, bool early_clobber_p
)
884 rtx new_in_reg
, new_out_reg
, reg
;
885 machine_mode inmode
, outmode
;
886 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
887 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
889 inmode
= curr_operand_mode
[ins
[0]];
890 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
891 push_to_sequence (*before
);
892 if (inmode
!= outmode
)
894 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
897 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
899 if (SCALAR_INT_MODE_P (inmode
))
900 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
902 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
903 LRA_SUBREG_P (new_out_reg
) = 1;
904 /* If the input reg is dying here, we can use the same hard
905 register for REG and IN_RTX. We do it only for original
906 pseudos as reload pseudos can die although original
907 pseudos still live where reload pseudos dies. */
908 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
909 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
910 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
915 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
917 if (SCALAR_INT_MODE_P (outmode
))
918 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
920 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
921 /* NEW_IN_REG is non-paradoxical subreg. We don't want
922 NEW_OUT_REG living above. We add clobber clause for
923 this. This is just a temporary clobber. We can remove
924 it at the end of LRA work. */
925 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
926 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
927 LRA_SUBREG_P (new_in_reg
) = 1;
928 if (GET_CODE (in_rtx
) == SUBREG
)
930 rtx subreg_reg
= SUBREG_REG (in_rtx
);
932 /* If SUBREG_REG is dying here and sub-registers IN_RTX
933 and NEW_IN_REG are similar, we can use the same hard
934 register for REG and SUBREG_REG. */
935 if (REG_P (subreg_reg
)
936 && (int) REGNO (subreg_reg
) < lra_new_regno_start
937 && GET_MODE (subreg_reg
) == outmode
938 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
939 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
940 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
946 /* Pseudos have values -- see comments for lra_reg_info.
947 Different pseudos with the same value do not conflict even if
948 they live in the same place. When we create a pseudo we
949 assign value of original pseudo (if any) from which we
950 created the new pseudo. If we create the pseudo from the
951 input pseudo, the new pseudo will have no conflict with the
952 input pseudo which is wrong when the input pseudo lives after
953 the insn and as the new pseudo value is changed by the insn
954 output. Therefore we create the new pseudo from the output
955 except the case when we have single matched dying input
958 We cannot reuse the current output register because we might
959 have a situation like "a <- a op b", where the constraints
960 force the second input operand ("b") to match the output
961 operand ("a"). "b" must then be copied into a new register
962 so that it doesn't clobber the current value of "a".
964 We can not use the same value if the output pseudo is
965 early clobbered or the input pseudo is mentioned in the
966 output, e.g. as an address part in memory, because
967 output reload will actually extend the pseudo liveness.
968 We don't care about eliminable hard regs here as we are
969 interesting only in pseudos. */
971 new_in_reg
= new_out_reg
972 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
973 && (int) REGNO (in_rtx
) < lra_new_regno_start
974 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
976 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
977 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
978 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
981 /* In operand can be got from transformations before processing insn
982 constraints. One example of such transformations is subreg
983 reloading (see function simplify_operand_subreg). The new
984 pseudos created by the transformations might have inaccurate
985 class (ALL_REGS) and we should make their classes more
987 narrow_reload_pseudo_class (in_rtx
, goal_class
);
988 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
989 *before
= get_insns ();
991 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
994 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
995 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
996 *curr_id
->operand_loc
[in
] = new_in_reg
;
998 lra_update_dups (curr_id
, ins
);
1001 /* See a comment for the input operand above. */
1002 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1003 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1006 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1008 *after
= get_insns ();
1011 *curr_id
->operand_loc
[out
] = new_out_reg
;
1012 lra_update_dup (curr_id
, out
);
1015 /* Return register class which is union of all reg classes in insn
1016 constraint alternative string starting with P. */
1017 static enum reg_class
1018 reg_class_from_constraints (const char *p
)
1021 enum reg_class op_class
= NO_REGS
;
1024 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1031 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1035 enum constraint_num cn
= lookup_constraint (p
);
1036 enum reg_class cl
= reg_class_for_constraint (cn
);
1039 if (insn_extra_address_constraint (cn
))
1041 = (reg_class_subunion
1042 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1043 ADDRESS
, SCRATCH
)]);
1047 op_class
= reg_class_subunion
[op_class
][cl
];
1050 while ((p
+= len
), c
);
1054 /* If OP is a register, return the class of the register as per
1055 get_reg_class, otherwise return NO_REGS. */
1056 static inline enum reg_class
1057 get_op_class (rtx op
)
1059 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1062 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1063 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1064 SUBREG for VAL to make them equal. */
1066 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1068 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1070 /* Usually size of mem_pseudo is greater than val size but in
1071 rare cases it can be less as it can be defined by target
1072 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1075 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1076 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1078 LRA_SUBREG_P (val
) = 1;
1082 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1083 LRA_SUBREG_P (mem_pseudo
) = 1;
1086 return to_p
? gen_move_insn (mem_pseudo
, val
)
1087 : gen_move_insn (val
, mem_pseudo
);
1090 /* Process a special case insn (register move), return true if we
1091 don't need to process it anymore. INSN should be a single set
1092 insn. Set up that RTL was changed through CHANGE_P and macro
1093 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1096 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1099 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1101 enum reg_class dclass
, sclass
, secondary_class
;
1102 secondary_reload_info sri
;
1104 lra_assert (curr_insn_set
!= NULL_RTX
);
1105 dreg
= dest
= SET_DEST (curr_insn_set
);
1106 sreg
= src
= SET_SRC (curr_insn_set
);
1107 if (GET_CODE (dest
) == SUBREG
)
1108 dreg
= SUBREG_REG (dest
);
1109 if (GET_CODE (src
) == SUBREG
)
1110 sreg
= SUBREG_REG (src
);
1111 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1113 sclass
= dclass
= NO_REGS
;
1115 dclass
= get_reg_class (REGNO (dreg
));
1116 if (dclass
== ALL_REGS
)
1117 /* ALL_REGS is used for new pseudos created by transformations
1118 like reload of SUBREG_REG (see function
1119 simplify_operand_subreg). We don't know their class yet. We
1120 should figure out the class from processing the insn
1121 constraints not in this fast path function. Even if ALL_REGS
1122 were a right class for the pseudo, secondary_... hooks usually
1123 are not define for ALL_REGS. */
1126 sclass
= get_reg_class (REGNO (sreg
));
1127 if (sclass
== ALL_REGS
)
1128 /* See comments above. */
1130 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1132 #ifdef SECONDARY_MEMORY_NEEDED
1133 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1134 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1135 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1136 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1144 if (! REG_P (dreg
) || ! REG_P (sreg
))
1146 sri
.prev_sri
= NULL
;
1147 sri
.icode
= CODE_FOR_nothing
;
1149 secondary_class
= NO_REGS
;
1150 /* Set up hard register for a reload pseudo for hook
1151 secondary_reload because some targets just ignore unassigned
1152 pseudos in the hook. */
1153 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1155 dregno
= REGNO (dreg
);
1156 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1160 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1162 sregno
= REGNO (sreg
);
1163 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1167 if (sclass
!= NO_REGS
)
1169 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1170 (reg_class_t
) sclass
,
1171 GET_MODE (src
), &sri
);
1172 if (sclass
== NO_REGS
1173 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1174 && dclass
!= NO_REGS
))
1176 enum reg_class old_sclass
= secondary_class
;
1177 secondary_reload_info old_sri
= sri
;
1179 sri
.prev_sri
= NULL
;
1180 sri
.icode
= CODE_FOR_nothing
;
1183 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1184 (reg_class_t
) dclass
,
1185 GET_MODE (src
), &sri
);
1186 /* Check the target hook consistency. */
1188 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1189 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1190 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1193 reg_renumber
[sregno
] = -1;
1195 reg_renumber
[dregno
] = -1;
1196 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1200 if (secondary_class
!= NO_REGS
)
1201 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1205 if (sri
.icode
== CODE_FOR_nothing
)
1206 lra_emit_move (new_reg
, src
);
1209 enum reg_class scratch_class
;
1211 scratch_class
= (reg_class_from_constraints
1212 (insn_data
[sri
.icode
].operand
[2].constraint
));
1213 scratch_reg
= (lra_create_new_reg_with_unique_value
1214 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1215 scratch_class
, "scratch"));
1216 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1219 before
= get_insns ();
1221 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1222 if (new_reg
!= NULL_RTX
)
1223 SET_SRC (curr_insn_set
) = new_reg
;
1226 if (lra_dump_file
!= NULL
)
1228 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1229 dump_insn_slim (lra_dump_file
, curr_insn
);
1231 lra_set_insn_deleted (curr_insn
);
1237 /* The following data describe the result of process_alt_operands.
1238 The data are used in curr_insn_transform to generate reloads. */
1240 /* The chosen reg classes which should be used for the corresponding
1242 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1243 /* True if the operand should be the same as another operand and that
1244 other operand does not need a reload. */
1245 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1246 /* True if the operand does not need a reload. */
1247 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1248 /* True if the operand can be offsetable memory. */
1249 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1250 /* The number of an operand to which given operand can be matched to. */
1251 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1252 /* The number of elements in the following array. */
1253 static int goal_alt_dont_inherit_ops_num
;
1254 /* Numbers of operands whose reload pseudos should not be inherited. */
1255 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1256 /* True if the insn commutative operands should be swapped. */
1257 static bool goal_alt_swapped
;
1258 /* The chosen insn alternative. */
1259 static int goal_alt_number
;
1261 /* True if the corresponding operand is the result of an equivalence
1263 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1265 /* The following five variables are used to choose the best insn
1266 alternative. They reflect final characteristics of the best
1269 /* Number of necessary reloads and overall cost reflecting the
1270 previous value and other unpleasantness of the best alternative. */
1271 static int best_losers
, best_overall
;
1272 /* Overall number hard registers used for reloads. For example, on
1273 some targets we need 2 general registers to reload DFmode and only
1274 one floating point register. */
1275 static int best_reload_nregs
;
1276 /* Overall number reflecting distances of previous reloading the same
1277 value. The distances are counted from the current BB start. It is
1278 used to improve inheritance chances. */
1279 static int best_reload_sum
;
1281 /* True if the current insn should have no correspondingly input or
1283 static bool no_input_reloads_p
, no_output_reloads_p
;
1285 /* True if we swapped the commutative operands in the current
1287 static int curr_swapped
;
1289 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1290 register of class CL. Add any input reloads to list BEFORE. AFTER
1291 is nonnull if *LOC is an automodified value; handle that case by
1292 adding the required output reloads to list AFTER. Return true if
1293 the RTL was changed.
1295 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1296 register. Return false if the address register is correct. */
1298 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1302 enum reg_class rclass
, new_class
;
1306 bool subreg_p
, before_p
= false;
1308 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1311 reg
= SUBREG_REG (*loc
);
1312 mode
= GET_MODE (reg
);
1314 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1315 between two registers with different classes, but there normally will
1316 be "mov" which transfers element of vector register into the general
1317 register, and this normally will be a subreg which should be reloaded
1318 as a whole. This is particularly likely to be triggered when
1319 -fno-split-wide-types specified. */
1321 || in_class_p (reg
, cl
, &new_class
)
1322 || GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (ptr_mode
))
1323 loc
= &SUBREG_REG (*loc
);
1327 mode
= GET_MODE (reg
);
1332 /* Always reload memory in an address even if the target supports
1334 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1339 regno
= REGNO (reg
);
1340 rclass
= get_reg_class (regno
);
1342 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1344 if (lra_dump_file
!= NULL
)
1346 fprintf (lra_dump_file
,
1347 "Changing pseudo %d in address of insn %u on equiv ",
1348 REGNO (reg
), INSN_UID (curr_insn
));
1349 dump_value_slim (lra_dump_file
, *loc
, 1);
1350 fprintf (lra_dump_file
, "\n");
1352 *loc
= copy_rtx (*loc
);
1354 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1359 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1360 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1363 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1367 lra_change_class (regno
, new_class
, " Change to", true);
1375 push_to_sequence (*before
);
1376 lra_emit_move (new_reg
, reg
);
1377 *before
= get_insns ();
1384 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1386 *after
= get_insns ();
1392 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1393 the insn to be inserted before curr insn. AFTER returns the
1394 the insn to be inserted after curr insn. ORIGREG and NEWREG
1395 are the original reg and new reg for reload. */
1397 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1402 push_to_sequence (*before
);
1403 lra_emit_move (newreg
, origreg
);
1404 *before
= get_insns ();
1410 lra_emit_move (origreg
, newreg
);
1412 *after
= get_insns ();
1417 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1419 /* Make reloads for subreg in operand NOP with internal subreg mode
1420 REG_MODE, add new reloads for further processing. Return true if
1421 any change was done. */
1423 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1426 rtx_insn
*before
, *after
;
1427 machine_mode mode
, innermode
;
1429 rtx operand
= *curr_id
->operand_loc
[nop
];
1430 enum reg_class regclass
;
1433 before
= after
= NULL
;
1435 if (GET_CODE (operand
) != SUBREG
)
1438 mode
= GET_MODE (operand
);
1439 reg
= SUBREG_REG (operand
);
1440 innermode
= GET_MODE (reg
);
1441 type
= curr_static_id
->operand
[nop
].type
;
1442 /* If we change address for paradoxical subreg of memory, the
1443 address might violate the necessary alignment or the access might
1444 be slow. So take this into consideration. We should not worry
1445 about access beyond allocated memory for paradoxical memory
1446 subregs as we don't substitute such equiv memory (see processing
1447 equivalences in function lra_constraints) and because for spilled
1448 pseudos we allocate stack memory enough for the biggest
1449 corresponding paradoxical subreg. */
1451 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1452 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1454 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1456 alter_subreg (curr_id
->operand_loc
[nop
], false);
1457 subst
= *curr_id
->operand_loc
[nop
];
1458 lra_assert (MEM_P (subst
));
1459 if (! valid_address_p (innermode
, XEXP (reg
, 0),
1460 MEM_ADDR_SPACE (reg
))
1461 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1462 MEM_ADDR_SPACE (subst
)))
1464 else if ((get_constraint_type (lookup_constraint
1465 (curr_static_id
->operand
[nop
].constraint
))
1466 != CT_SPECIAL_MEMORY
)
1467 /* We still can reload address and if the address is
1468 valid, we can remove subreg without reloading its
1470 && valid_address_p (GET_MODE (subst
),
1472 [ira_class_hard_regs
1473 [base_reg_class (GET_MODE (subst
),
1474 MEM_ADDR_SPACE (subst
),
1475 ADDRESS
, SCRATCH
)][0]],
1476 MEM_ADDR_SPACE (subst
)))
1479 /* If the address was valid and became invalid, prefer to reload
1480 the memory. Typical case is when the index scale should
1481 correspond the memory. */
1482 *curr_id
->operand_loc
[nop
] = old
;
1484 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1486 alter_subreg (curr_id
->operand_loc
[nop
], false);
1489 else if (CONSTANT_P (reg
))
1491 /* Try to simplify subreg of constant. It is usually result of
1492 equivalence substitution. */
1493 if (innermode
== VOIDmode
1494 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1495 innermode
= curr_static_id
->operand
[nop
].mode
;
1496 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1497 SUBREG_BYTE (operand
))) != NULL_RTX
)
1499 *curr_id
->operand_loc
[nop
] = new_reg
;
1503 /* Put constant into memory when we have mixed modes. It generates
1504 a better code in most cases as it does not need a secondary
1505 reload memory. It also prevents LRA looping when LRA is using
1506 secondary reload memory again and again. */
1507 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1508 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1510 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1511 alter_subreg (curr_id
->operand_loc
[nop
], false);
1514 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1515 if there may be a problem accessing OPERAND in the outer
1518 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1519 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1520 /* Don't reload paradoxical subregs because we could be looping
1521 having repeatedly final regno out of hard regs range. */
1522 && (hard_regno_nregs
[hard_regno
][innermode
]
1523 >= hard_regno_nregs
[hard_regno
][mode
])
1524 && simplify_subreg_regno (hard_regno
, innermode
,
1525 SUBREG_BYTE (operand
), mode
) < 0
1526 /* Don't reload subreg for matching reload. It is actually
1527 valid subreg in LRA. */
1528 && ! LRA_SUBREG_P (operand
))
1529 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1531 enum reg_class rclass
;
1534 /* There is a big probability that we will get the same class
1535 for the new pseudo and we will get the same insn which
1536 means infinite looping. So spill the new pseudo. */
1539 /* The class will be defined later in curr_insn_transform. */
1541 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1543 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1544 rclass
, TRUE
, "subreg reg", &new_reg
))
1546 bool insert_before
, insert_after
;
1547 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1549 insert_before
= (type
!= OP_OUT
1550 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1551 insert_after
= (type
!= OP_IN
);
1552 insert_move_for_subreg (insert_before
? &before
: NULL
,
1553 insert_after
? &after
: NULL
,
1556 SUBREG_REG (operand
) = new_reg
;
1557 lra_process_new_insns (curr_insn
, before
, after
,
1558 "Inserting subreg reload");
1561 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1562 IRA allocates hardreg to the inner pseudo reg according to its mode
1563 instead of the outermode, so the size of the hardreg may not be enough
1564 to contain the outermode operand, in that case we may need to insert
1565 reload for the reg. For the following two types of paradoxical subreg,
1566 we need to insert reload:
1567 1. If the op_type is OP_IN, and the hardreg could not be paired with
1568 other hardreg to contain the outermode operand
1569 (checked by in_hard_reg_set_p), we need to insert the reload.
1570 2. If the op_type is OP_OUT or OP_INOUT.
1572 Here is a paradoxical subreg example showing how the reload is generated:
1574 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1575 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1577 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1578 here, if reg107 is assigned to hardreg R15, because R15 is the last
1579 hardreg, compiler cannot find another hardreg to pair with R15 to
1580 contain TImode data. So we insert a TImode reload reg180 for it.
1581 After reload is inserted:
1583 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1584 (reg:DI 107 [ __comp ])) -1
1585 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1586 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1588 Two reload hard registers will be allocated to reg180 to save TImode data
1590 else if (REG_P (reg
)
1591 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1592 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1593 && (hard_regno_nregs
[hard_regno
][innermode
]
1594 < hard_regno_nregs
[hard_regno
][mode
])
1595 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1597 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1600 /* The class will be defined later in curr_insn_transform. */
1601 enum reg_class rclass
1602 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1604 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1605 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1608 bool insert_before
, insert_after
;
1610 PUT_MODE (new_reg
, mode
);
1611 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1612 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1614 insert_before
= (type
!= OP_OUT
);
1615 insert_after
= (type
!= OP_IN
);
1616 insert_move_for_subreg (insert_before
? &before
: NULL
,
1617 insert_after
? &after
: NULL
,
1620 SUBREG_REG (operand
) = new_reg
;
1621 lra_process_new_insns (curr_insn
, before
, after
,
1622 "Inserting paradoxical subreg reload");
1628 /* Return TRUE if X refers for a hard register from SET. */
1630 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1632 int i
, j
, x_hard_regno
;
1639 code
= GET_CODE (x
);
1640 mode
= GET_MODE (x
);
1644 code
= GET_CODE (x
);
1645 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1646 mode
= GET_MODE (x
);
1651 x_hard_regno
= get_hard_regno (x
);
1652 return (x_hard_regno
>= 0
1653 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1657 struct address_info ad
;
1659 decompose_mem_address (&ad
, x
);
1660 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1662 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1665 fmt
= GET_RTX_FORMAT (code
);
1666 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1670 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1673 else if (fmt
[i
] == 'E')
1675 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1676 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1683 /* Return true if OP is a spilled pseudo. */
1685 spilled_pseudo_p (rtx op
)
1688 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1691 /* Return true if X is a general constant. */
1693 general_constant_p (rtx x
)
1695 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1699 reg_in_class_p (rtx reg
, enum reg_class cl
)
1702 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1703 return in_class_p (reg
, cl
, NULL
);
1706 /* Return true if SET of RCLASS contains no hard regs which can be
1709 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1711 enum machine_mode mode
)
1715 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1716 COPY_HARD_REG_SET (temp
, set
);
1717 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1718 return (hard_reg_set_subset_p
1719 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1722 /* Major function to choose the current insn alternative and what
1723 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1724 negative we should consider only this alternative. Return false if
1725 we can not choose the alternative or find how to reload the
1728 process_alt_operands (int only_alternative
)
1731 int nop
, overall
, nalt
;
1732 int n_alternatives
= curr_static_id
->n_alternatives
;
1733 int n_operands
= curr_static_id
->n_operands
;
1734 /* LOSERS counts the operands that don't fit this alternative and
1735 would require loading. */
1737 /* REJECT is a count of how undesirable this alternative says it is
1738 if any reloading is required. If the alternative matches exactly
1739 then REJECT is ignored, but otherwise it gets this much counted
1740 against it in addition to the reloading needed. */
1743 /* The number of elements in the following array. */
1744 int early_clobbered_regs_num
;
1745 /* Numbers of operands which are early clobber registers. */
1746 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1747 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1748 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1749 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1750 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1751 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1752 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1753 /* The number of elements in the following array. */
1754 int curr_alt_dont_inherit_ops_num
;
1755 /* Numbers of operands whose reload pseudos should not be inherited. */
1756 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1758 /* The register when the operand is a subreg of register, otherwise the
1760 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1761 /* The register if the operand is a register or subreg of register,
1763 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1764 int hard_regno
[MAX_RECOG_OPERANDS
];
1765 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1766 int reload_nregs
, reload_sum
;
1770 /* Calculate some data common for all alternatives to speed up the
1772 for (nop
= 0; nop
< n_operands
; nop
++)
1776 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1777 /* The real hard regno of the operand after the allocation. */
1778 hard_regno
[nop
] = get_hard_regno (op
);
1780 operand_reg
[nop
] = reg
= op
;
1781 biggest_mode
[nop
] = GET_MODE (op
);
1782 if (GET_CODE (op
) == SUBREG
)
1784 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1785 if (GET_MODE_SIZE (biggest_mode
[nop
])
1786 < GET_MODE_SIZE (GET_MODE (reg
)))
1787 biggest_mode
[nop
] = GET_MODE (reg
);
1790 operand_reg
[nop
] = NULL_RTX
;
1791 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1792 || ((int) REGNO (reg
)
1793 == lra_get_elimination_hard_regno (REGNO (reg
))))
1794 no_subreg_reg_operand
[nop
] = reg
;
1796 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1797 /* Just use natural mode for elimination result. It should
1798 be enough for extra constraints hooks. */
1799 = regno_reg_rtx
[hard_regno
[nop
]];
1802 /* The constraints are made of several alternatives. Each operand's
1803 constraint looks like foo,bar,... with commas separating the
1804 alternatives. The first alternatives for all operands go
1805 together, the second alternatives go together, etc.
1807 First loop over alternatives. */
1808 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1809 if (only_alternative
>= 0)
1810 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1812 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1814 /* Loop over operands for one constraint alternative. */
1815 if (!TEST_BIT (preferred
, nalt
))
1818 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1819 for (nop
= 0; nop
< n_operands
; nop
++)
1821 int inc
= (curr_static_id
1822 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1823 if (lra_dump_file
!= NULL
&& inc
!= 0)
1824 fprintf (lra_dump_file
,
1825 " Staticly defined alt reject+=%d\n", inc
);
1828 early_clobbered_regs_num
= 0;
1830 for (nop
= 0; nop
< n_operands
; nop
++)
1834 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1835 bool win
, did_match
, offmemok
, early_clobber_p
;
1836 /* false => this operand can be reloaded somehow for this
1839 /* true => this operand can be reloaded if the alternative
1842 /* True if a constant forced into memory would be OK for
1845 enum reg_class this_alternative
, this_costly_alternative
;
1846 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1847 bool this_alternative_match_win
, this_alternative_win
;
1848 bool this_alternative_offmemok
;
1851 enum constraint_num cn
;
1853 opalt_num
= nalt
* n_operands
+ nop
;
1854 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1856 /* Fast track for no constraints at all. */
1857 curr_alt
[nop
] = NO_REGS
;
1858 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1859 curr_alt_win
[nop
] = true;
1860 curr_alt_match_win
[nop
] = false;
1861 curr_alt_offmemok
[nop
] = false;
1862 curr_alt_matches
[nop
] = -1;
1866 op
= no_subreg_reg_operand
[nop
];
1867 mode
= curr_operand_mode
[nop
];
1869 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1872 early_clobber_p
= false;
1873 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1875 this_costly_alternative
= this_alternative
= NO_REGS
;
1876 /* We update set of possible hard regs besides its class
1877 because reg class might be inaccurate. For example,
1878 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1879 is translated in HI_REGS because classes are merged by
1880 pairs and there is no accurate intermediate class. */
1881 CLEAR_HARD_REG_SET (this_alternative_set
);
1882 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1883 this_alternative_win
= false;
1884 this_alternative_match_win
= false;
1885 this_alternative_offmemok
= false;
1886 this_alternative_matches
= -1;
1888 /* An empty constraint should be excluded by the fast
1890 lra_assert (*p
!= 0 && *p
!= ',');
1893 /* Scan this alternative's specs for this operand; set WIN
1894 if the operand fits any letter in this alternative.
1895 Otherwise, clear BADOP if this operand could fit some
1896 letter after reloads, or set WINREG if this operand could
1897 fit after reloads provided the constraint allows some
1902 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1912 early_clobber_p
= true;
1916 op_reject
+= LRA_MAX_REJECT
;
1919 op_reject
+= LRA_LOSER_COST_FACTOR
;
1923 /* Ignore rest of this alternative. */
1927 case '0': case '1': case '2': case '3': case '4':
1928 case '5': case '6': case '7': case '8': case '9':
1933 m
= strtoul (p
, &end
, 10);
1936 lra_assert (nop
> m
);
1938 this_alternative_matches
= m
;
1939 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1940 /* We are supposed to match a previous operand.
1941 If we do, we win if that one did. If we do
1942 not, count both of the operands as losers.
1943 (This is too conservative, since most of the
1944 time only a single reload insn will be needed
1945 to make the two operands win. As a result,
1946 this alternative may be rejected when it is
1947 actually desirable.) */
1949 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1950 *curr_id
->operand_loc
[m
], m_hregno
))
1952 /* We should reject matching of an early
1953 clobber operand if the matching operand is
1954 not dying in the insn. */
1955 if (! curr_static_id
->operand
[m
].early_clobber
1956 || operand_reg
[nop
] == NULL_RTX
1957 || (find_regno_note (curr_insn
, REG_DEAD
,
1959 || REGNO (op
) == REGNO (operand_reg
[m
])))
1964 /* If we are matching a non-offsettable
1965 address where an offsettable address was
1966 expected, then we must reject this
1967 combination, because we can't reload
1969 if (curr_alt_offmemok
[m
]
1970 && MEM_P (*curr_id
->operand_loc
[m
])
1971 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1976 /* Operands don't match. Both operands must
1977 allow a reload register, otherwise we
1978 cannot make them match. */
1979 if (curr_alt
[m
] == NO_REGS
)
1981 /* Retroactively mark the operand we had to
1982 match as a loser, if it wasn't already and
1983 it wasn't matched to a register constraint
1984 (e.g it might be matched by memory). */
1986 && (operand_reg
[m
] == NULL_RTX
1987 || hard_regno
[m
] < 0))
1991 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1992 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1995 /* Prefer matching earlyclobber alternative as
1996 it results in less hard regs required for
1997 the insn than a non-matching earlyclobber
1999 if (curr_static_id
->operand
[m
].early_clobber
)
2001 if (lra_dump_file
!= NULL
)
2004 " %d Matching earlyclobber alt:"
2009 /* Otherwise we prefer no matching
2010 alternatives because it gives more freedom
2012 else if (operand_reg
[nop
] == NULL_RTX
2013 || (find_regno_note (curr_insn
, REG_DEAD
,
2014 REGNO (operand_reg
[nop
]))
2017 if (lra_dump_file
!= NULL
)
2020 " %d Matching alt: reject+=2\n",
2025 /* If we have to reload this operand and some
2026 previous operand also had to match the same
2027 thing as this operand, we don't know how to do
2029 if (!match_p
|| !curr_alt_win
[m
])
2031 for (i
= 0; i
< nop
; i
++)
2032 if (curr_alt_matches
[i
] == m
)
2040 /* This can be fixed with reloads if the operand
2041 we are supposed to match can be fixed with
2044 this_alternative
= curr_alt
[m
];
2045 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2046 winreg
= this_alternative
!= NO_REGS
;
2052 || general_constant_p (op
)
2053 || spilled_pseudo_p (op
))
2059 cn
= lookup_constraint (p
);
2060 switch (get_constraint_type (cn
))
2063 cl
= reg_class_for_constraint (cn
);
2069 if (CONST_INT_P (op
)
2070 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2076 && satisfies_memory_constraint_p (op
, cn
))
2078 else if (spilled_pseudo_p (op
))
2081 /* If we didn't already win, we can reload constants
2082 via force_const_mem or put the pseudo value into
2083 memory, or make other memory by reloading the
2084 address like for 'o'. */
2085 if (CONST_POOL_OK_P (mode
, op
)
2086 || MEM_P (op
) || REG_P (op
)
2087 /* We can restore the equiv insn by a
2089 || equiv_substition_p
[nop
])
2096 /* If we didn't already win, we can reload the address
2097 into a base register. */
2098 if (satisfies_address_constraint_p (op
, cn
))
2100 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2106 if (constraint_satisfied_p (op
, cn
))
2110 case CT_SPECIAL_MEMORY
:
2112 && satisfies_memory_constraint_p (op
, cn
))
2114 else if (spilled_pseudo_p (op
))
2121 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2122 IOR_HARD_REG_SET (this_alternative_set
,
2123 reg_class_contents
[cl
]);
2126 this_costly_alternative
2127 = reg_class_subunion
[this_costly_alternative
][cl
];
2128 IOR_HARD_REG_SET (this_costly_alternative_set
,
2129 reg_class_contents
[cl
]);
2131 if (mode
== BLKmode
)
2136 if (hard_regno
[nop
] >= 0
2137 && in_hard_reg_set_p (this_alternative_set
,
2138 mode
, hard_regno
[nop
]))
2140 else if (hard_regno
[nop
] < 0
2141 && in_class_p (op
, this_alternative
, NULL
))
2146 if (c
!= ' ' && c
!= '\t')
2147 costly_p
= c
== '*';
2149 while ((p
+= len
), c
);
2151 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2152 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2153 /* Record which operands fit this alternative. */
2156 this_alternative_win
= true;
2157 if (operand_reg
[nop
] != NULL_RTX
)
2159 if (hard_regno
[nop
] >= 0)
2161 if (in_hard_reg_set_p (this_costly_alternative_set
,
2162 mode
, hard_regno
[nop
]))
2164 if (lra_dump_file
!= NULL
)
2165 fprintf (lra_dump_file
,
2166 " %d Costly set: reject++\n",
2173 /* Prefer won reg to spilled pseudo under other
2174 equal conditions for possibe inheritance. */
2177 if (lra_dump_file
!= NULL
)
2180 " %d Non pseudo reload: reject++\n",
2184 if (in_class_p (operand_reg
[nop
],
2185 this_costly_alternative
, NULL
))
2187 if (lra_dump_file
!= NULL
)
2190 " %d Non pseudo costly reload:"
2196 /* We simulate the behavior of old reload here.
2197 Although scratches need hard registers and it
2198 might result in spilling other pseudos, no reload
2199 insns are generated for the scratches. So it
2200 might cost something but probably less than old
2201 reload pass believes. */
2204 if (lra_dump_file
!= NULL
)
2205 fprintf (lra_dump_file
,
2206 " %d Scratch win: reject+=2\n",
2213 this_alternative_match_win
= true;
2216 int const_to_mem
= 0;
2219 reject
+= op_reject
;
2220 /* Never do output reload of stack pointer. It makes
2221 impossible to do elimination when SP is changed in
2223 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2224 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2227 /* If this alternative asks for a specific reg class, see if there
2228 is at least one allocatable register in that class. */
2230 = (this_alternative
== NO_REGS
2231 || (hard_reg_set_subset_p
2232 (reg_class_contents
[this_alternative
],
2233 lra_no_alloc_regs
)));
2235 /* For asms, verify that the class for this alternative is possible
2236 for the mode that is specified. */
2237 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2240 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2241 if (HARD_REGNO_MODE_OK (i
, mode
)
2242 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2245 if (i
== FIRST_PSEUDO_REGISTER
)
2249 /* If this operand accepts a register, and if the
2250 register class has at least one allocatable register,
2251 then this operand can be reloaded. */
2252 if (winreg
&& !no_regs_p
)
2257 if (lra_dump_file
!= NULL
)
2258 fprintf (lra_dump_file
,
2259 " alt=%d: Bad operand -- refuse\n",
2264 /* If not assigned pseudo has a class which a subset of
2265 required reg class, it is a less costly alternative
2266 as the pseudo still can get a hard reg of necessary
2268 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2269 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2270 && ira_class_subset_p
[this_alternative
][cl
])
2272 if (lra_dump_file
!= NULL
)
2275 " %d Super set class reg: reject-=3\n", nop
);
2279 this_alternative_offmemok
= offmemok
;
2280 if (this_costly_alternative
!= NO_REGS
)
2282 if (lra_dump_file
!= NULL
)
2283 fprintf (lra_dump_file
,
2284 " %d Costly loser: reject++\n", nop
);
2287 /* If the operand is dying, has a matching constraint,
2288 and satisfies constraints of the matched operand
2289 which failed to satisfy the own constraints, most probably
2290 the reload for this operand will be gone. */
2291 if (this_alternative_matches
>= 0
2292 && !curr_alt_win
[this_alternative_matches
]
2294 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2295 && (hard_regno
[nop
] >= 0
2296 ? in_hard_reg_set_p (this_alternative_set
,
2297 mode
, hard_regno
[nop
])
2298 : in_class_p (op
, this_alternative
, NULL
)))
2300 if (lra_dump_file
!= NULL
)
2303 " %d Dying matched operand reload: reject++\n",
2309 /* Strict_low_part requires to reload the register
2310 not the sub-register. In this case we should
2311 check that a final reload hard reg can hold the
2313 if (curr_static_id
->operand
[nop
].strict_low
2315 && hard_regno
[nop
] < 0
2316 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2317 && ira_class_hard_regs_num
[this_alternative
] > 0
2318 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2319 [this_alternative
][0],
2321 (*curr_id
->operand_loc
[nop
])))
2323 if (lra_dump_file
!= NULL
)
2326 " alt=%d: Strict low subreg reload -- refuse\n",
2332 if (operand_reg
[nop
] != NULL_RTX
2333 /* Output operands and matched input operands are
2334 not inherited. The following conditions do not
2335 exactly describe the previous statement but they
2336 are pretty close. */
2337 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2338 && (this_alternative_matches
< 0
2339 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2341 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2345 /* The value of reload_sum has sense only if we
2346 process insns in their order. It happens only on
2347 the first constraints sub-pass when we do most of
2349 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2350 reload_sum
+= last_reload
- bb_reload_num
;
2352 /* If this is a constant that is reloaded into the
2353 desired class by copying it to memory first, count
2354 that as another reload. This is consistent with
2355 other code and is required to avoid choosing another
2356 alternative when the constant is moved into memory.
2357 Note that the test here is precisely the same as in
2358 the code below that calls force_const_mem. */
2359 if (CONST_POOL_OK_P (mode
, op
)
2360 && ((targetm
.preferred_reload_class
2361 (op
, this_alternative
) == NO_REGS
)
2362 || no_input_reloads_p
))
2369 /* Alternative loses if it requires a type of reload not
2370 permitted for this insn. We can always reload
2371 objects with a REG_UNUSED note. */
2372 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2373 && no_output_reloads_p
2374 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2375 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2376 && no_input_reloads_p
&& ! const_to_mem
)
2377 || (this_alternative_matches
>= 0
2378 && (no_input_reloads_p
2379 || (no_output_reloads_p
2380 && (curr_static_id
->operand
2381 [this_alternative_matches
].type
!= OP_IN
)
2382 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2383 no_subreg_reg_operand
2384 [this_alternative_matches
])))))
2386 if (lra_dump_file
!= NULL
)
2389 " alt=%d: No input/otput reload -- refuse\n",
2394 /* Alternative loses if it required class pseudo can not
2395 hold value of required mode. Such insns can be
2396 described by insn definitions with mode iterators. */
2397 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2398 && ! hard_reg_set_empty_p (this_alternative_set
)
2399 /* It is common practice for constraints to use a
2400 class which does not have actually enough regs to
2401 hold the value (e.g. x86 AREG for mode requiring
2402 more one general reg). Therefore we have 2
2403 conditions to check that the reload pseudo can
2404 not hold the mode value. */
2405 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2406 [this_alternative
][0],
2407 GET_MODE (*curr_id
->operand_loc
[nop
]))
2408 /* The above condition is not enough as the first
2409 reg in ira_class_hard_regs can be not aligned for
2410 multi-words mode values. */
2411 && (prohibited_class_reg_set_mode_p
2412 (this_alternative
, this_alternative_set
,
2413 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2415 if (lra_dump_file
!= NULL
)
2416 fprintf (lra_dump_file
,
2417 " alt=%d: reload pseudo for op %d "
2418 " can not hold the mode value -- refuse\n",
2423 /* Check strong discouragement of reload of non-constant
2424 into class THIS_ALTERNATIVE. */
2425 if (! CONSTANT_P (op
) && ! no_regs_p
2426 && (targetm
.preferred_reload_class
2427 (op
, this_alternative
) == NO_REGS
2428 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2429 && (targetm
.preferred_output_reload_class
2430 (op
, this_alternative
) == NO_REGS
))))
2432 if (lra_dump_file
!= NULL
)
2433 fprintf (lra_dump_file
,
2434 " %d Non-prefered reload: reject+=%d\n",
2435 nop
, LRA_MAX_REJECT
);
2436 reject
+= LRA_MAX_REJECT
;
2439 if (! (MEM_P (op
) && offmemok
)
2440 && ! (const_to_mem
&& constmemok
))
2442 /* We prefer to reload pseudos over reloading other
2443 things, since such reloads may be able to be
2444 eliminated later. So bump REJECT in other cases.
2445 Don't do this in the case where we are forcing a
2446 constant into memory and it will then win since
2447 we don't want to have a different alternative
2449 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2451 if (lra_dump_file
!= NULL
)
2454 " %d Non-pseudo reload: reject+=2\n",
2461 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2463 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2465 if (lra_dump_file
!= NULL
)
2468 " %d Small class reload: reject+=%d\n",
2469 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2470 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2474 /* We are trying to spill pseudo into memory. It is
2475 usually more costly than moving to a hard register
2476 although it might takes the same number of
2478 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2480 if (lra_dump_file
!= NULL
)
2483 " %d Spill pseudo into memory: reject+=3\n",
2486 if (VECTOR_MODE_P (mode
))
2488 /* Spilling vectors into memory is usually more
2489 costly as they contain big values. */
2490 if (lra_dump_file
!= NULL
)
2493 " %d Spill vector pseudo: reject+=2\n",
2499 #ifdef SECONDARY_MEMORY_NEEDED
2500 /* If reload requires moving value through secondary
2501 memory, it will need one more insn at least. */
2502 if (this_alternative
!= NO_REGS
2503 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2504 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2505 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2507 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2508 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2512 /* Input reloads can be inherited more often than output
2513 reloads can be removed, so penalize output
2515 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2517 if (lra_dump_file
!= NULL
)
2520 " %d Non input pseudo reload: reject++\n",
2526 if (early_clobber_p
&& ! scratch_p
)
2528 if (lra_dump_file
!= NULL
)
2529 fprintf (lra_dump_file
,
2530 " %d Early clobber: reject++\n", nop
);
2533 /* ??? We check early clobbers after processing all operands
2534 (see loop below) and there we update the costs more.
2535 Should we update the cost (may be approximately) here
2536 because of early clobber register reloads or it is a rare
2537 or non-important thing to be worth to do it. */
2538 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2539 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2541 if (lra_dump_file
!= NULL
)
2542 fprintf (lra_dump_file
,
2543 " alt=%d,overall=%d,losers=%d -- refuse\n",
2544 nalt
, overall
, losers
);
2548 curr_alt
[nop
] = this_alternative
;
2549 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2550 curr_alt_win
[nop
] = this_alternative_win
;
2551 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2552 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2553 curr_alt_matches
[nop
] = this_alternative_matches
;
2555 if (this_alternative_matches
>= 0
2556 && !did_match
&& !this_alternative_win
)
2557 curr_alt_win
[this_alternative_matches
] = false;
2559 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2560 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2562 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2563 /* Prevent processing non-move insns. */
2564 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2565 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2566 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2567 && REG_P (no_subreg_reg_operand
[0])
2568 && REG_P (no_subreg_reg_operand
[1])
2569 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2570 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2571 || (! curr_alt_win
[0] && curr_alt_win
[1]
2572 && REG_P (no_subreg_reg_operand
[1])
2573 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2574 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2575 && REG_P (no_subreg_reg_operand
[0])
2576 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2577 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2578 no_subreg_reg_operand
[1])
2579 || (targetm
.preferred_reload_class
2580 (no_subreg_reg_operand
[1],
2581 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2582 /* If it is a result of recent elimination in move
2583 insn we can transform it into an add still by
2584 using this alternative. */
2585 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2587 /* We have a move insn and a new reload insn will be similar
2588 to the current insn. We should avoid such situation as it
2589 results in LRA cycling. */
2590 overall
+= LRA_MAX_REJECT
;
2593 curr_alt_dont_inherit_ops_num
= 0;
2594 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2596 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2597 HARD_REG_SET temp_set
;
2599 i
= early_clobbered_nops
[nop
];
2600 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2601 || hard_regno
[i
] < 0)
2603 lra_assert (operand_reg
[i
] != NULL_RTX
);
2604 clobbered_hard_regno
= hard_regno
[i
];
2605 CLEAR_HARD_REG_SET (temp_set
);
2606 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2607 first_conflict_j
= last_conflict_j
= -1;
2608 for (j
= 0; j
< n_operands
; j
++)
2610 /* We don't want process insides of match_operator and
2611 match_parallel because otherwise we would process
2612 their operands once again generating a wrong
2614 || curr_static_id
->operand
[j
].is_operator
)
2616 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2617 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2619 /* If we don't reload j-th operand, check conflicts. */
2620 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2621 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2623 if (first_conflict_j
< 0)
2624 first_conflict_j
= j
;
2625 last_conflict_j
= j
;
2627 if (last_conflict_j
< 0)
2629 /* If earlyclobber operand conflicts with another
2630 non-matching operand which is actually the same register
2631 as the earlyclobber operand, it is better to reload the
2632 another operand as an operand matching the earlyclobber
2633 operand can be also the same. */
2634 if (first_conflict_j
== last_conflict_j
2635 && operand_reg
[last_conflict_j
] != NULL_RTX
2636 && ! curr_alt_match_win
[last_conflict_j
]
2637 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2639 curr_alt_win
[last_conflict_j
] = false;
2640 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2643 /* Early clobber was already reflected in REJECT. */
2644 lra_assert (reject
> 0);
2645 if (lra_dump_file
!= NULL
)
2648 " %d Conflict early clobber reload: reject--\n",
2651 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2655 /* We need to reload early clobbered register and the
2656 matched registers. */
2657 for (j
= 0; j
< n_operands
; j
++)
2658 if (curr_alt_matches
[j
] == i
)
2660 curr_alt_match_win
[j
] = false;
2662 overall
+= LRA_LOSER_COST_FACTOR
;
2664 if (! curr_alt_match_win
[i
])
2665 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2668 /* Remember pseudos used for match reloads are never
2670 lra_assert (curr_alt_matches
[i
] >= 0);
2671 curr_alt_win
[curr_alt_matches
[i
]] = false;
2673 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2675 /* Early clobber was already reflected in REJECT. */
2676 lra_assert (reject
> 0);
2677 if (lra_dump_file
!= NULL
)
2680 " %d Matched conflict early clobber reloads:"
2684 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2687 if (lra_dump_file
!= NULL
)
2688 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2689 nalt
, overall
, losers
, reload_nregs
);
2691 /* If this alternative can be made to work by reloading, and it
2692 needs less reloading than the others checked so far, record
2693 it as the chosen goal for reloading. */
2694 if ((best_losers
!= 0 && losers
== 0)
2695 || (((best_losers
== 0 && losers
== 0)
2696 || (best_losers
!= 0 && losers
!= 0))
2697 && (best_overall
> overall
2698 || (best_overall
== overall
2699 /* If the cost of the reloads is the same,
2700 prefer alternative which requires minimal
2701 number of reload regs. */
2702 && (reload_nregs
< best_reload_nregs
2703 || (reload_nregs
== best_reload_nregs
2704 && (best_reload_sum
< reload_sum
2705 || (best_reload_sum
== reload_sum
2706 && nalt
< goal_alt_number
))))))))
2708 for (nop
= 0; nop
< n_operands
; nop
++)
2710 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2711 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2712 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2713 goal_alt
[nop
] = curr_alt
[nop
];
2714 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2716 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2717 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2718 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2719 goal_alt_swapped
= curr_swapped
;
2720 best_overall
= overall
;
2721 best_losers
= losers
;
2722 best_reload_nregs
= reload_nregs
;
2723 best_reload_sum
= reload_sum
;
2724 goal_alt_number
= nalt
;
2727 /* Everything is satisfied. Do not process alternatives
2736 /* Make reload base reg from address AD. */
2738 base_to_reg (struct address_info
*ad
)
2742 rtx new_inner
= NULL_RTX
;
2743 rtx new_reg
= NULL_RTX
;
2745 rtx_insn
*last_insn
= get_last_insn();
2747 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2748 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2749 get_index_code (ad
));
2750 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2752 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2753 ad
->disp_term
== NULL
2754 ? gen_int_mode (0, ad
->mode
)
2756 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2758 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base_term
));
2759 code
= recog_memoized (insn
);
2762 delete_insns_since (last_insn
);
2769 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2771 base_plus_disp_to_reg (struct address_info
*ad
)
2776 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2777 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2778 get_index_code (ad
));
2779 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2781 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2785 /* Make reload of index part of address AD. Return the new
2788 index_part_to_reg (struct address_info
*ad
)
2792 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2793 INDEX_REG_CLASS
, "index term");
2794 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2795 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2799 /* Return true if we can add a displacement to address AD, even if that
2800 makes the address invalid. The fix-up code requires any new address
2801 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2803 can_add_disp_p (struct address_info
*ad
)
2805 return (!ad
->autoinc_p
2806 && ad
->segment
== NULL
2807 && ad
->base
== ad
->base_term
2808 && ad
->disp
== ad
->disp_term
);
2811 /* Make equiv substitution in address AD. Return true if a substitution
2814 equiv_address_substitution (struct address_info
*ad
)
2816 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2817 HOST_WIDE_INT disp
, scale
;
2820 base_term
= strip_subreg (ad
->base_term
);
2821 if (base_term
== NULL
)
2822 base_reg
= new_base_reg
= NULL_RTX
;
2825 base_reg
= *base_term
;
2826 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2828 index_term
= strip_subreg (ad
->index_term
);
2829 if (index_term
== NULL
)
2830 index_reg
= new_index_reg
= NULL_RTX
;
2833 index_reg
= *index_term
;
2834 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2836 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2840 if (lra_dump_file
!= NULL
)
2842 fprintf (lra_dump_file
, "Changing address in insn %d ",
2843 INSN_UID (curr_insn
));
2844 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2846 if (base_reg
!= new_base_reg
)
2848 if (REG_P (new_base_reg
))
2850 *base_term
= new_base_reg
;
2853 else if (GET_CODE (new_base_reg
) == PLUS
2854 && REG_P (XEXP (new_base_reg
, 0))
2855 && CONST_INT_P (XEXP (new_base_reg
, 1))
2856 && can_add_disp_p (ad
))
2858 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2859 *base_term
= XEXP (new_base_reg
, 0);
2862 if (ad
->base_term2
!= NULL
)
2863 *ad
->base_term2
= *ad
->base_term
;
2865 if (index_reg
!= new_index_reg
)
2867 if (REG_P (new_index_reg
))
2869 *index_term
= new_index_reg
;
2872 else if (GET_CODE (new_index_reg
) == PLUS
2873 && REG_P (XEXP (new_index_reg
, 0))
2874 && CONST_INT_P (XEXP (new_index_reg
, 1))
2875 && can_add_disp_p (ad
)
2876 && (scale
= get_index_scale (ad
)))
2878 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2879 *index_term
= XEXP (new_index_reg
, 0);
2885 if (ad
->disp
!= NULL
)
2886 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2889 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2890 update_address (ad
);
2894 if (lra_dump_file
!= NULL
)
2897 fprintf (lra_dump_file
, " -- no change\n");
2900 fprintf (lra_dump_file
, " on equiv ");
2901 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2902 fprintf (lra_dump_file
, "\n");
2908 /* Major function to make reloads for an address in operand NOP or
2909 check its correctness (If CHECK_ONLY_P is true). The supported
2912 1) an address that existed before LRA started, at which point it
2913 must have been valid. These addresses are subject to elimination
2914 and may have become invalid due to the elimination offset being out
2917 2) an address created by forcing a constant to memory
2918 (force_const_to_mem). The initial form of these addresses might
2919 not be valid, and it is this function's job to make them valid.
2921 3) a frame address formed from a register and a (possibly zero)
2922 constant offset. As above, these addresses might not be valid and
2923 this function must make them so.
2925 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2926 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2927 address. Return true for any RTL change.
2929 The function is a helper function which does not produce all
2930 transformations (when CHECK_ONLY_P is false) which can be
2931 necessary. It does just basic steps. To do all necessary
2932 transformations use function process_address. */
2934 process_address_1 (int nop
, bool check_only_p
,
2935 rtx_insn
**before
, rtx_insn
**after
)
2937 struct address_info ad
;
2939 HOST_WIDE_INT scale
;
2940 rtx op
= *curr_id
->operand_loc
[nop
];
2941 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2942 enum constraint_num cn
= lookup_constraint (constraint
);
2943 bool change_p
= false;
2946 && GET_MODE (op
) == BLKmode
2947 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
2950 if (insn_extra_address_constraint (cn
))
2951 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2952 else if (MEM_P (op
))
2953 decompose_mem_address (&ad
, op
);
2954 else if (GET_CODE (op
) == SUBREG
2955 && MEM_P (SUBREG_REG (op
)))
2956 decompose_mem_address (&ad
, SUBREG_REG (op
));
2959 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2960 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2961 when INDEX_REG_CLASS is a single register class. */
2962 if (ad
.base_term
!= NULL
2963 && ad
.index_term
!= NULL
2964 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
2965 && REG_P (*ad
.base_term
)
2966 && REG_P (*ad
.index_term
)
2967 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
2968 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
2970 std::swap (ad
.base
, ad
.index
);
2971 std::swap (ad
.base_term
, ad
.index_term
);
2974 change_p
= equiv_address_substitution (&ad
);
2975 if (ad
.base_term
!= NULL
2976 && (process_addr_reg
2977 (ad
.base_term
, check_only_p
, before
,
2979 && !(REG_P (*ad
.base_term
)
2980 && find_regno_note (curr_insn
, REG_DEAD
,
2981 REGNO (*ad
.base_term
)) != NULL_RTX
)
2983 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2984 get_index_code (&ad
)))))
2987 if (ad
.base_term2
!= NULL
)
2988 *ad
.base_term2
= *ad
.base_term
;
2990 if (ad
.index_term
!= NULL
2991 && process_addr_reg (ad
.index_term
, check_only_p
,
2992 before
, NULL
, INDEX_REG_CLASS
))
2995 /* Target hooks sometimes don't treat extra-constraint addresses as
2996 legitimate address_operands, so handle them specially. */
2997 if (insn_extra_address_constraint (cn
)
2998 && satisfies_address_constraint_p (&ad
, cn
))
3004 /* There are three cases where the shape of *AD.INNER may now be invalid:
3006 1) the original address was valid, but either elimination or
3007 equiv_address_substitution was applied and that made
3008 the address invalid.
3010 2) the address is an invalid symbolic address created by
3013 3) the address is a frame address with an invalid offset.
3015 4) the address is a frame address with an invalid base.
3017 All these cases involve a non-autoinc address, so there is no
3018 point revalidating other types. */
3019 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3022 /* Any index existed before LRA started, so we can assume that the
3023 presence and shape of the index is valid. */
3024 push_to_sequence (*before
);
3025 lra_assert (ad
.disp
== ad
.disp_term
);
3026 if (ad
.base
== NULL
)
3028 if (ad
.index
== NULL
)
3031 rtx_insn
*last
= get_last_insn ();
3033 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3035 rtx addr
= *ad
.inner
;
3037 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3040 /* addr => lo_sum (new_base, addr), case (2) above. */
3041 insn
= emit_insn (gen_rtx_SET
3043 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3044 code
= recog_memoized (insn
);
3047 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3048 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3050 /* Try to put lo_sum into register. */
3051 insn
= emit_insn (gen_rtx_SET
3053 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3054 code
= recog_memoized (insn
);
3057 *ad
.inner
= new_reg
;
3058 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3068 delete_insns_since (last
);
3073 /* addr => new_base, case (2) above. */
3074 lra_emit_move (new_reg
, addr
);
3076 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3078 insn
= NEXT_INSN (insn
))
3079 if (recog_memoized (insn
) < 0)
3081 if (insn
!= NULL_RTX
)
3083 /* Do nothing if we cannot generate right insns.
3084 This is analogous to reload pass behavior. */
3085 delete_insns_since (last
);
3089 *ad
.inner
= new_reg
;
3094 /* index * scale + disp => new base + index * scale,
3096 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3097 GET_CODE (*ad
.index
));
3099 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3100 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3101 lra_emit_move (new_reg
, *ad
.disp
);
3102 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3103 new_reg
, *ad
.index
);
3106 else if (ad
.index
== NULL
)
3111 rtx_insn
*insns
, *last_insn
;
3112 /* Try to reload base into register only if the base is invalid
3113 for the address but with valid offset, case (4) above. */
3115 new_reg
= base_to_reg (&ad
);
3117 /* base + disp => new base, cases (1) and (3) above. */
3118 /* Another option would be to reload the displacement into an
3119 index register. However, postreload has code to optimize
3120 address reloads that have the same base and different
3121 displacements, so reloading into an index register would
3122 not necessarily be a win. */
3123 if (new_reg
== NULL_RTX
)
3124 new_reg
= base_plus_disp_to_reg (&ad
);
3125 insns
= get_insns ();
3126 last_insn
= get_last_insn ();
3127 /* If we generated at least two insns, try last insn source as
3128 an address. If we succeed, we generate one less insn. */
3129 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3130 && GET_CODE (SET_SRC (set
)) == PLUS
3131 && REG_P (XEXP (SET_SRC (set
), 0))
3132 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3134 *ad
.inner
= SET_SRC (set
);
3135 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3137 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3138 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3139 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3140 get_index_code (&ad
));
3141 regno
= REGNO (*ad
.base_term
);
3142 if (regno
>= FIRST_PSEUDO_REGISTER
3143 && cl
!= lra_get_allocno_class (regno
))
3144 lra_change_class (regno
, cl
, " Change to", true);
3145 new_reg
= SET_SRC (set
);
3146 delete_insns_since (PREV_INSN (last_insn
));
3149 /* Try if target can split displacement into legitimite new disp
3150 and offset. If it's the case, we replace the last insn with
3151 insns for base + offset => new_reg and set new_reg + new disp
3153 last_insn
= get_last_insn ();
3154 if ((set
= single_set (last_insn
)) != NULL_RTX
3155 && GET_CODE (SET_SRC (set
)) == PLUS
3156 && REG_P (XEXP (SET_SRC (set
), 0))
3157 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3158 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3160 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3161 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3164 rtx_insn
*new_insns
;
3166 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3167 new_insns
= get_insns ();
3169 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3170 delete_insns_since (PREV_INSN (last_insn
));
3171 add_insn (new_insns
);
3172 insns
= get_insns ();
3177 *ad
.inner
= new_reg
;
3179 else if (ad
.disp_term
!= NULL
)
3181 /* base + scale * index + disp => new base + scale * index,
3183 new_reg
= base_plus_disp_to_reg (&ad
);
3184 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3185 new_reg
, *ad
.index
);
3187 else if ((scale
= get_index_scale (&ad
)) == 1)
3189 /* The last transformation to one reg will be made in
3190 curr_insn_transform function. */
3194 else if (scale
!= 0)
3196 /* base + scale * index => base + new_reg,
3198 Index part of address may become invalid. For example, we
3199 changed pseudo on the equivalent memory and a subreg of the
3200 pseudo onto the memory of different mode for which the scale is
3202 new_reg
= index_part_to_reg (&ad
);
3203 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3204 *ad
.base_term
, new_reg
);
3208 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3210 rtx addr
= *ad
.inner
;
3212 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3213 /* addr => new_base. */
3214 lra_emit_move (new_reg
, addr
);
3215 *ad
.inner
= new_reg
;
3217 *before
= get_insns ();
3222 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3223 Use process_address_1 as a helper function. Return true for any
3226 If CHECK_ONLY_P is true, just check address correctness. Return
3227 false if the address correct. */
3229 process_address (int nop
, bool check_only_p
,
3230 rtx_insn
**before
, rtx_insn
**after
)
3234 while (process_address_1 (nop
, check_only_p
, before
, after
))
3243 /* Emit insns to reload VALUE into a new register. VALUE is an
3244 auto-increment or auto-decrement RTX whose operand is a register or
3245 memory location; so reloading involves incrementing that location.
3246 IN is either identical to VALUE, or some cheaper place to reload
3247 value being incremented/decremented from.
3249 INC_AMOUNT is the number to increment or decrement by (always
3250 positive and ignored for POST_MODIFY/PRE_MODIFY).
3252 Return pseudo containing the result. */
3254 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3256 /* REG or MEM to be copied and incremented. */
3257 rtx incloc
= XEXP (value
, 0);
3258 /* Nonzero if increment after copying. */
3259 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3260 || GET_CODE (value
) == POST_MODIFY
);
3265 rtx real_in
= in
== value
? incloc
: in
;
3269 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3271 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3272 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3273 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3274 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3275 inc
= XEXP (XEXP (value
, 1), 1);
3279 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3280 inc_amount
= -inc_amount
;
3282 inc
= GEN_INT (inc_amount
);
3285 if (! post
&& REG_P (incloc
))
3288 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3291 if (real_in
!= result
)
3293 /* First copy the location to the result register. */
3294 lra_assert (REG_P (result
));
3295 emit_insn (gen_move_insn (result
, real_in
));
3298 /* We suppose that there are insns to add/sub with the constant
3299 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3300 old reload worked with this assumption. If the assumption
3301 becomes wrong, we should use approach in function
3302 base_plus_disp_to_reg. */
3305 /* See if we can directly increment INCLOC. */
3306 last
= get_last_insn ();
3307 add_insn
= emit_insn (plus_p
3308 ? gen_add2_insn (incloc
, inc
)
3309 : gen_sub2_insn (incloc
, inc
));
3311 code
= recog_memoized (add_insn
);
3314 if (! post
&& result
!= incloc
)
3315 emit_insn (gen_move_insn (result
, incloc
));
3318 delete_insns_since (last
);
3321 /* If couldn't do the increment directly, must increment in RESULT.
3322 The way we do this depends on whether this is pre- or
3323 post-increment. For pre-increment, copy INCLOC to the reload
3324 register, increment it there, then save back. */
3327 if (real_in
!= result
)
3328 emit_insn (gen_move_insn (result
, real_in
));
3330 emit_insn (gen_add2_insn (result
, inc
));
3332 emit_insn (gen_sub2_insn (result
, inc
));
3333 if (result
!= incloc
)
3334 emit_insn (gen_move_insn (incloc
, result
));
3340 Because this might be a jump insn or a compare, and because
3341 RESULT may not be available after the insn in an input
3342 reload, we must do the incrementing before the insn being
3345 We have already copied IN to RESULT. Increment the copy in
3346 RESULT, save that back, then decrement RESULT so it has
3347 the original value. */
3349 emit_insn (gen_add2_insn (result
, inc
));
3351 emit_insn (gen_sub2_insn (result
, inc
));
3352 emit_insn (gen_move_insn (incloc
, result
));
3353 /* Restore non-modified value for the result. We prefer this
3354 way because it does not require an additional hard
3358 if (CONST_INT_P (inc
))
3359 emit_insn (gen_add2_insn (result
,
3360 gen_int_mode (-INTVAL (inc
),
3361 GET_MODE (result
))));
3363 emit_insn (gen_sub2_insn (result
, inc
));
3366 emit_insn (gen_add2_insn (result
, inc
));
3371 /* Return true if the current move insn does not need processing as we
3372 already know that it satisfies its constraints. */
3374 simple_move_p (void)
3377 enum reg_class dclass
, sclass
;
3379 lra_assert (curr_insn_set
!= NULL_RTX
);
3380 dest
= SET_DEST (curr_insn_set
);
3381 src
= SET_SRC (curr_insn_set
);
3382 return ((dclass
= get_op_class (dest
)) != NO_REGS
3383 && (sclass
= get_op_class (src
)) != NO_REGS
3384 /* The backend guarantees that register moves of cost 2
3385 never need reloads. */
3386 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3389 /* Swap operands NOP and NOP + 1. */
3391 swap_operands (int nop
)
3393 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3394 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3395 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3396 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3397 /* Swap the duplicates too. */
3398 lra_update_dup (curr_id
, nop
);
3399 lra_update_dup (curr_id
, nop
+ 1);
3402 /* Main entry point of the constraint code: search the body of the
3403 current insn to choose the best alternative. It is mimicking insn
3404 alternative cost calculation model of former reload pass. That is
3405 because machine descriptions were written to use this model. This
3406 model can be changed in future. Make commutative operand exchange
3409 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3410 constraints. Return true if any change happened during function
3413 If CHECK_ONLY_P is true then don't do any transformation. Just
3414 check that the insn satisfies all constraints. If the insn does
3415 not satisfy any constraint, return true. */
3417 curr_insn_transform (bool check_only_p
)
3423 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3424 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3425 rtx_insn
*before
, *after
;
3427 /* Flag that the insn has been changed through a transformation. */
3430 #ifdef SECONDARY_MEMORY_NEEDED
3433 int max_regno_before
;
3434 int reused_alternative_num
;
3436 curr_insn_set
= single_set (curr_insn
);
3437 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3440 no_input_reloads_p
= no_output_reloads_p
= false;
3441 goal_alt_number
= -1;
3442 change_p
= sec_mem_p
= false;
3443 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3444 reloads; neither are insns that SET cc0. Insns that use CC0 are
3445 not allowed to have any input reloads. */
3446 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3447 no_output_reloads_p
= true;
3449 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3450 no_input_reloads_p
= true;
3451 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3452 no_output_reloads_p
= true;
3454 n_operands
= curr_static_id
->n_operands
;
3455 n_alternatives
= curr_static_id
->n_alternatives
;
3457 /* Just return "no reloads" if insn has no operands with
3459 if (n_operands
== 0 || n_alternatives
== 0)
3462 max_regno_before
= max_reg_num ();
3464 for (i
= 0; i
< n_operands
; i
++)
3466 goal_alt_matched
[i
][0] = -1;
3467 goal_alt_matches
[i
] = -1;
3470 commutative
= curr_static_id
->commutative
;
3472 /* Now see what we need for pseudos that didn't get hard regs or got
3473 the wrong kind of hard reg. For this, we must consider all the
3474 operands together against the register constraints. */
3476 best_losers
= best_overall
= INT_MAX
;
3477 best_reload_sum
= 0;
3479 curr_swapped
= false;
3480 goal_alt_swapped
= false;
3483 /* Make equivalence substitution and memory subreg elimination
3484 before address processing because an address legitimacy can
3485 depend on memory mode. */
3486 for (i
= 0; i
< n_operands
; i
++)
3489 bool op_change_p
= false;
3491 if (curr_static_id
->operand
[i
].is_operator
)
3494 old
= op
= *curr_id
->operand_loc
[i
];
3495 if (GET_CODE (old
) == SUBREG
)
3496 old
= SUBREG_REG (old
);
3497 subst
= get_equiv_with_elimination (old
, curr_insn
);
3498 original_subreg_reg_mode
[i
] = VOIDmode
;
3499 equiv_substition_p
[i
] = false;
3502 equiv_substition_p
[i
] = true;
3503 subst
= copy_rtx (subst
);
3504 lra_assert (REG_P (old
));
3505 if (GET_CODE (op
) != SUBREG
)
3506 *curr_id
->operand_loc
[i
] = subst
;
3509 SUBREG_REG (op
) = subst
;
3510 if (GET_MODE (subst
) == VOIDmode
)
3511 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3513 if (lra_dump_file
!= NULL
)
3515 fprintf (lra_dump_file
,
3516 "Changing pseudo %d in operand %i of insn %u on equiv ",
3517 REGNO (old
), i
, INSN_UID (curr_insn
));
3518 dump_value_slim (lra_dump_file
, subst
, 1);
3519 fprintf (lra_dump_file
, "\n");
3521 op_change_p
= change_p
= true;
3523 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3526 lra_update_dup (curr_id
, i
);
3530 /* Reload address registers and displacements. We do it before
3531 finding an alternative because of memory constraints. */
3532 before
= after
= NULL
;
3533 for (i
= 0; i
< n_operands
; i
++)
3534 if (! curr_static_id
->operand
[i
].is_operator
3535 && process_address (i
, check_only_p
, &before
, &after
))
3540 lra_update_dup (curr_id
, i
);
3544 /* If we've changed the instruction then any alternative that
3545 we chose previously may no longer be valid. */
3546 lra_set_used_insn_alternative (curr_insn
, -1);
3548 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3549 && check_and_process_move (&change_p
, &sec_mem_p
))
3554 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3555 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3556 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3557 reused_alternative_num
, INSN_UID (curr_insn
));
3559 if (process_alt_operands (reused_alternative_num
))
3563 return ! alt_p
|| best_losers
!= 0;
3565 /* If insn is commutative (it's safe to exchange a certain pair of
3566 operands) then we need to try each alternative twice, the second
3567 time matching those two operands as if we had exchanged them. To
3568 do this, really exchange them in operands.
3570 If we have just tried the alternatives the second time, return
3571 operands to normal and drop through. */
3573 if (reused_alternative_num
< 0 && commutative
>= 0)
3575 curr_swapped
= !curr_swapped
;
3578 swap_operands (commutative
);
3582 swap_operands (commutative
);
3585 if (! alt_p
&& ! sec_mem_p
)
3587 /* No alternative works with reloads?? */
3588 if (INSN_CODE (curr_insn
) >= 0)
3589 fatal_insn ("unable to generate reloads for:", curr_insn
);
3590 error_for_asm (curr_insn
,
3591 "inconsistent operand constraints in an %<asm%>");
3592 /* Avoid further trouble with this insn. */
3593 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3594 lra_invalidate_insn_data (curr_insn
);
3598 /* If the best alternative is with operands 1 and 2 swapped, swap
3599 them. Update the operand numbers of any reloads already
3602 if (goal_alt_swapped
)
3604 if (lra_dump_file
!= NULL
)
3605 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3606 INSN_UID (curr_insn
));
3608 /* Swap the duplicates too. */
3609 swap_operands (commutative
);
3613 #ifdef SECONDARY_MEMORY_NEEDED
3614 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3615 too conservatively. So we use the secondary memory only if there
3616 is no any alternative without reloads. */
3617 use_sec_mem_p
= false;
3619 use_sec_mem_p
= true;
3622 for (i
= 0; i
< n_operands
; i
++)
3623 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3625 use_sec_mem_p
= i
< n_operands
;
3630 int in
= -1, out
= -1;
3631 rtx new_reg
, src
, dest
, rld
;
3632 machine_mode sec_mode
, rld_mode
;
3634 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3635 dest
= SET_DEST (curr_insn_set
);
3636 src
= SET_SRC (curr_insn_set
);
3637 for (i
= 0; i
< n_operands
; i
++)
3638 if (*curr_id
->operand_loc
[i
] == dest
)
3640 else if (*curr_id
->operand_loc
[i
] == src
)
3642 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3643 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3644 out
= curr_static_id
->dup_num
[i
];
3645 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3646 in
= curr_static_id
->dup_num
[i
];
3647 lra_assert (out
>= 0 && in
>= 0
3648 && curr_static_id
->operand
[out
].type
== OP_OUT
3649 && curr_static_id
->operand
[in
].type
== OP_IN
);
3650 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3652 rld_mode
= GET_MODE (rld
);
3653 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3654 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3656 sec_mode
= rld_mode
;
3658 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3659 NO_REGS
, "secondary");
3660 /* If the mode is changed, it should be wider. */
3661 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3662 if (sec_mode
!= rld_mode
)
3664 /* If the target says specifically to use another mode for
3665 secondary memory moves we can not reuse the original
3667 after
= emit_spill_move (false, new_reg
, dest
);
3668 lra_process_new_insns (curr_insn
, NULL
, after
,
3669 "Inserting the sec. move");
3670 /* We may have non null BEFORE here (e.g. after address
3672 push_to_sequence (before
);
3673 before
= emit_spill_move (true, new_reg
, src
);
3675 before
= get_insns ();
3677 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3678 lra_set_insn_deleted (curr_insn
);
3680 else if (dest
== rld
)
3682 *curr_id
->operand_loc
[out
] = new_reg
;
3683 lra_update_dup (curr_id
, out
);
3684 after
= emit_spill_move (false, new_reg
, dest
);
3685 lra_process_new_insns (curr_insn
, NULL
, after
,
3686 "Inserting the sec. move");
3690 *curr_id
->operand_loc
[in
] = new_reg
;
3691 lra_update_dup (curr_id
, in
);
3692 /* See comments above. */
3693 push_to_sequence (before
);
3694 before
= emit_spill_move (true, new_reg
, src
);
3696 before
= get_insns ();
3698 lra_process_new_insns (curr_insn
, before
, NULL
,
3699 "Inserting the sec. move");
3701 lra_update_insn_regno_info (curr_insn
);
3706 lra_assert (goal_alt_number
>= 0);
3707 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3709 if (lra_dump_file
!= NULL
)
3713 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3714 goal_alt_number
, INSN_UID (curr_insn
));
3715 for (i
= 0; i
< n_operands
; i
++)
3717 p
= (curr_static_id
->operand_alternative
3718 [goal_alt_number
* n_operands
+ i
].constraint
);
3721 fprintf (lra_dump_file
, " (%d) ", i
);
3722 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3723 fputc (*p
, lra_dump_file
);
3725 if (INSN_CODE (curr_insn
) >= 0
3726 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3727 fprintf (lra_dump_file
, " {%s}", p
);
3728 if (curr_id
->sp_offset
!= 0)
3729 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3730 curr_id
->sp_offset
);
3731 fprintf (lra_dump_file
, "\n");
3734 /* Right now, for any pair of operands I and J that are required to
3735 match, with J < I, goal_alt_matches[I] is J. Add I to
3736 goal_alt_matched[J]. */
3738 for (i
= 0; i
< n_operands
; i
++)
3739 if ((j
= goal_alt_matches
[i
]) >= 0)
3741 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3743 /* We allow matching one output operand and several input
3746 || (curr_static_id
->operand
[j
].type
== OP_OUT
3747 && curr_static_id
->operand
[i
].type
== OP_IN
3748 && (curr_static_id
->operand
3749 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3750 goal_alt_matched
[j
][k
] = i
;
3751 goal_alt_matched
[j
][k
+ 1] = -1;
3754 for (i
= 0; i
< n_operands
; i
++)
3755 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3757 /* Any constants that aren't allowed and can't be reloaded into
3758 registers are here changed into memory references. */
3759 for (i
= 0; i
< n_operands
; i
++)
3760 if (goal_alt_win
[i
])
3763 enum reg_class new_class
;
3764 rtx reg
= *curr_id
->operand_loc
[i
];
3766 if (GET_CODE (reg
) == SUBREG
)
3767 reg
= SUBREG_REG (reg
);
3769 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3771 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3773 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3776 lra_change_class (regno
, new_class
, " Change to", true);
3782 const char *constraint
;
3784 rtx op
= *curr_id
->operand_loc
[i
];
3785 rtx subreg
= NULL_RTX
;
3786 machine_mode mode
= curr_operand_mode
[i
];
3788 if (GET_CODE (op
) == SUBREG
)
3791 op
= SUBREG_REG (op
);
3792 mode
= GET_MODE (op
);
3795 if (CONST_POOL_OK_P (mode
, op
)
3796 && ((targetm
.preferred_reload_class
3797 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3798 || no_input_reloads_p
))
3800 rtx tem
= force_const_mem (mode
, op
);
3803 if (subreg
!= NULL_RTX
)
3804 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3806 *curr_id
->operand_loc
[i
] = tem
;
3807 lra_update_dup (curr_id
, i
);
3808 process_address (i
, false, &before
, &after
);
3810 /* If the alternative accepts constant pool refs directly
3811 there will be no reload needed at all. */
3812 if (subreg
!= NULL_RTX
)
3814 /* Skip alternatives before the one requested. */
3815 constraint
= (curr_static_id
->operand_alternative
3816 [goal_alt_number
* n_operands
+ i
].constraint
);
3818 (c
= *constraint
) && c
!= ',' && c
!= '#';
3819 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3821 enum constraint_num cn
= lookup_constraint (constraint
);
3822 if ((insn_extra_memory_constraint (cn
)
3823 || insn_extra_special_memory_constraint (cn
))
3824 && satisfies_memory_constraint_p (tem
, cn
))
3827 if (c
== '\0' || c
== ',' || c
== '#')
3830 goal_alt_win
[i
] = true;
3834 for (i
= 0; i
< n_operands
; i
++)
3837 bool optional_p
= false;
3839 rtx op
= *curr_id
->operand_loc
[i
];
3841 if (goal_alt_win
[i
])
3843 if (goal_alt
[i
] == NO_REGS
3845 /* When we assign NO_REGS it means that we will not
3846 assign a hard register to the scratch pseudo by
3847 assigment pass and the scratch pseudo will be
3848 spilled. Spilled scratch pseudos are transformed
3849 back to scratches at the LRA end. */
3850 && lra_former_scratch_operand_p (curr_insn
, i
)
3851 && lra_former_scratch_p (REGNO (op
)))
3853 int regno
= REGNO (op
);
3854 lra_change_class (regno
, NO_REGS
, " Change to", true);
3855 if (lra_get_regno_hard_regno (regno
) >= 0)
3856 /* We don't have to mark all insn affected by the
3857 spilled pseudo as there is only one such insn, the
3859 reg_renumber
[regno
] = -1;
3860 lra_assert (bitmap_single_bit_set_p
3861 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
3863 /* We can do an optional reload. If the pseudo got a hard
3864 reg, we might improve the code through inheritance. If
3865 it does not get a hard register we coalesce memory/memory
3866 moves later. Ignore move insns to avoid cycling. */
3868 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3869 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3870 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3871 && regno
< new_regno_start
3872 && ! lra_former_scratch_p (regno
)
3873 && reg_renumber
[regno
] < 0
3874 /* Check that the optional reload pseudo will be able to
3875 hold given mode value. */
3876 && ! (prohibited_class_reg_set_mode_p
3877 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
3878 PSEUDO_REGNO_MODE (regno
)))
3879 && (curr_insn_set
== NULL_RTX
3880 || !((REG_P (SET_SRC (curr_insn_set
))
3881 || MEM_P (SET_SRC (curr_insn_set
))
3882 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3883 && (REG_P (SET_DEST (curr_insn_set
))
3884 || MEM_P (SET_DEST (curr_insn_set
))
3885 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3891 /* Operands that match previous ones have already been handled. */
3892 if (goal_alt_matches
[i
] >= 0)
3895 /* We should not have an operand with a non-offsettable address
3896 appearing where an offsettable address will do. It also may
3897 be a case when the address should be special in other words
3898 not a general one (e.g. it needs no index reg). */
3899 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3901 enum reg_class rclass
;
3902 rtx
*loc
= &XEXP (op
, 0);
3903 enum rtx_code code
= GET_CODE (*loc
);
3905 push_to_sequence (before
);
3906 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3908 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3909 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3910 /* This value does not matter for MODIFY. */
3911 GET_MODE_SIZE (GET_MODE (op
)));
3912 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3913 "offsetable address", &new_reg
))
3914 lra_emit_move (new_reg
, *loc
);
3915 before
= get_insns ();
3918 lra_update_dup (curr_id
, i
);
3920 else if (goal_alt_matched
[i
][0] == -1)
3924 int hard_regno
, byte
;
3925 enum op_type type
= curr_static_id
->operand
[i
].type
;
3927 loc
= curr_id
->operand_loc
[i
];
3928 mode
= curr_operand_mode
[i
];
3929 if (GET_CODE (*loc
) == SUBREG
)
3931 reg
= SUBREG_REG (*loc
);
3932 byte
= SUBREG_BYTE (*loc
);
3934 /* Strict_low_part requires reload the register not
3935 the sub-register. */
3936 && (curr_static_id
->operand
[i
].strict_low
3937 || (GET_MODE_SIZE (mode
)
3938 <= GET_MODE_SIZE (GET_MODE (reg
))
3940 = get_try_hard_regno (REGNO (reg
))) >= 0
3941 && (simplify_subreg_regno
3943 GET_MODE (reg
), byte
, mode
) < 0)
3944 && (goal_alt
[i
] == NO_REGS
3945 || (simplify_subreg_regno
3946 (ira_class_hard_regs
[goal_alt
[i
]][0],
3947 GET_MODE (reg
), byte
, mode
) >= 0)))))
3951 loc
= &SUBREG_REG (*loc
);
3952 mode
= GET_MODE (*loc
);
3956 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3957 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3960 push_to_sequence (before
);
3961 lra_emit_move (new_reg
, old
);
3962 before
= get_insns ();
3967 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3970 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3972 after
= get_insns ();
3976 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3977 if (goal_alt_dont_inherit_ops
[j
] == i
)
3979 lra_set_regno_unique_value (REGNO (new_reg
));
3982 lra_update_dup (curr_id
, i
);
3984 else if (curr_static_id
->operand
[i
].type
== OP_IN
3985 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3988 /* generate reloads for input and matched outputs. */
3989 match_inputs
[0] = i
;
3990 match_inputs
[1] = -1;
3991 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3992 goal_alt
[i
], &before
, &after
,
3993 curr_static_id
->operand_alternative
3994 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
3997 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3998 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4000 /* Generate reloads for output and matched inputs. */
4001 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
,
4002 curr_static_id
->operand_alternative
4003 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4004 else if (curr_static_id
->operand
[i
].type
== OP_IN
4005 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4008 /* Generate reloads for matched inputs. */
4009 match_inputs
[0] = i
;
4010 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4011 match_inputs
[j
+ 1] = k
;
4012 match_inputs
[j
+ 1] = -1;
4013 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
, false);
4016 /* We must generate code in any case when function
4017 process_alt_operands decides that it is possible. */
4021 lra_assert (REG_P (op
));
4023 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4024 if (GET_CODE (op
) == SUBREG
)
4025 op
= SUBREG_REG (op
);
4026 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4027 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4028 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
4029 if (lra_dump_file
!= NULL
)
4030 fprintf (lra_dump_file
,
4031 " Making reload reg %d for reg %d optional\n",
4035 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4036 || max_regno_before
!= max_reg_num ())
4040 lra_update_operator_dups (curr_id
);
4041 /* Something changes -- process the insn. */
4042 lra_update_insn_regno_info (curr_insn
);
4044 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4048 /* Return true if INSN satisfies all constraints. In other words, no
4049 reload insns are needed. */
4051 lra_constrain_insn (rtx_insn
*insn
)
4053 int saved_new_regno_start
= new_regno_start
;
4054 int saved_new_insn_uid_start
= new_insn_uid_start
;
4058 curr_id
= lra_get_insn_recog_data (curr_insn
);
4059 curr_static_id
= curr_id
->insn_static_data
;
4060 new_insn_uid_start
= get_max_uid ();
4061 new_regno_start
= max_reg_num ();
4062 change_p
= curr_insn_transform (true);
4063 new_regno_start
= saved_new_regno_start
;
4064 new_insn_uid_start
= saved_new_insn_uid_start
;
4068 /* Return true if X is in LIST. */
4070 in_list_p (rtx x
, rtx list
)
4072 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4073 if (XEXP (list
, 0) == x
)
4078 /* Return true if X contains an allocatable hard register (if
4079 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4081 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4087 code
= GET_CODE (x
);
4090 int regno
= REGNO (x
);
4091 HARD_REG_SET alloc_regs
;
4095 if (regno
>= FIRST_PSEUDO_REGISTER
)
4096 regno
= lra_get_regno_hard_regno (regno
);
4099 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4100 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4104 if (regno
< FIRST_PSEUDO_REGISTER
)
4108 return lra_get_regno_hard_regno (regno
) < 0;
4111 fmt
= GET_RTX_FORMAT (code
);
4112 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4116 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4119 else if (fmt
[i
] == 'E')
4121 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4122 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4129 /* Process all regs in location *LOC and change them on equivalent
4130 substitution. Return true if any change was done. */
4132 loc_equivalence_change_p (rtx
*loc
)
4134 rtx subst
, reg
, x
= *loc
;
4135 bool result
= false;
4136 enum rtx_code code
= GET_CODE (x
);
4142 reg
= SUBREG_REG (x
);
4143 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4144 && GET_MODE (subst
) == VOIDmode
)
4146 /* We cannot reload debug location. Simplify subreg here
4147 while we know the inner mode. */
4148 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4149 GET_MODE (reg
), SUBREG_BYTE (x
));
4153 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4159 /* Scan all the operand sub-expressions. */
4160 fmt
= GET_RTX_FORMAT (code
);
4161 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4164 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4165 else if (fmt
[i
] == 'E')
4166 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4168 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4173 /* Similar to loc_equivalence_change_p, but for use as
4174 simplify_replace_fn_rtx callback. DATA is insn for which the
4175 elimination is done. If it null we don't do the elimination. */
4177 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4182 rtx subst
= (data
== NULL
4183 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4190 /* Maximum number of generated reload insns per an insn. It is for
4191 preventing this pass cycling in a bug case. */
4192 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4194 /* The current iteration number of this LRA pass. */
4195 int lra_constraint_iter
;
4197 /* True if we substituted equiv which needs checking register
4198 allocation correctness because the equivalent value contains
4199 allocatable hard registers or when we restore multi-register
4201 bool lra_risky_transformations_p
;
4203 /* Return true if REGNO is referenced in more than one block. */
4205 multi_block_pseudo_p (int regno
)
4207 basic_block bb
= NULL
;
4211 if (regno
< FIRST_PSEUDO_REGISTER
)
4214 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4216 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4217 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4222 /* Return true if LIST contains a deleted insn. */
4224 contains_deleted_insn_p (rtx_insn_list
*list
)
4226 for (; list
!= NULL_RTX
; list
= list
->next ())
4227 if (NOTE_P (list
->insn ())
4228 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4233 /* Return true if X contains a pseudo dying in INSN. */
4235 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4242 return (insn
!= NULL_RTX
4243 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4244 code
= GET_CODE (x
);
4245 fmt
= GET_RTX_FORMAT (code
);
4246 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4250 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4253 else if (fmt
[i
] == 'E')
4255 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4256 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4263 /* Return true if INSN contains a dying pseudo in INSN right hand
4266 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4268 rtx set
= single_set (insn
);
4270 gcc_assert (set
!= NULL
);
4271 return dead_pseudo_p (SET_SRC (set
), insn
);
4274 /* Return true if any init insn of REGNO contains a dying pseudo in
4275 insn right hand side. */
4277 init_insn_rhs_dead_pseudo_p (int regno
)
4279 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4283 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4284 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4289 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4290 reverse only if we have one init insn with given REGNO as a
4293 reverse_equiv_p (int regno
)
4295 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4300 if (! INSN_P (insns
->insn ())
4301 || insns
->next () != NULL
)
4303 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4305 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4308 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4309 call this function only for non-reverse equivalence. */
4311 contains_reloaded_insn_p (int regno
)
4314 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4316 for (; list
!= NULL
; list
= list
->next ())
4317 if ((set
= single_set (list
->insn ())) == NULL_RTX
4318 || ! REG_P (SET_DEST (set
))
4319 || (int) REGNO (SET_DEST (set
)) != regno
)
4324 /* Entry function of LRA constraint pass. Return true if the
4325 constraint pass did change the code. */
4327 lra_constraints (bool first_p
)
4330 int i
, hard_regno
, new_insns_num
;
4331 unsigned int min_len
, new_min_len
, uid
;
4332 rtx set
, x
, reg
, dest_reg
;
4333 basic_block last_bb
;
4334 bitmap_head equiv_insn_bitmap
;
4337 lra_constraint_iter
++;
4338 if (lra_dump_file
!= NULL
)
4339 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4340 lra_constraint_iter
);
4342 if (pic_offset_table_rtx
4343 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4344 lra_risky_transformations_p
= true;
4346 lra_risky_transformations_p
= false;
4347 new_insn_uid_start
= get_max_uid ();
4348 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4349 /* Mark used hard regs for target stack size calulations. */
4350 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4351 if (lra_reg_info
[i
].nrefs
!= 0
4352 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4356 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4357 for (j
= 0; j
< nregs
; j
++)
4358 df_set_regs_ever_live (hard_regno
+ j
, true);
4360 /* Do elimination before the equivalence processing as we can spill
4361 some pseudos during elimination. */
4362 lra_eliminate (false, first_p
);
4363 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4364 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4365 if (lra_reg_info
[i
].nrefs
!= 0)
4367 ira_reg_equiv
[i
].profitable_p
= true;
4368 reg
= regno_reg_rtx
[i
];
4369 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4371 bool pseudo_p
= contains_reg_p (x
, false, false);
4373 /* After RTL transformation, we can not guarantee that
4374 pseudo in the substitution was not reloaded which might
4375 make equivalence invalid. For example, in reverse
4382 the memory address register was reloaded before the 2nd
4384 if ((! first_p
&& pseudo_p
)
4385 /* We don't use DF for compilation speed sake. So it
4386 is problematic to update live info when we use an
4387 equivalence containing pseudos in more than one
4389 || (pseudo_p
&& multi_block_pseudo_p (i
))
4390 /* If an init insn was deleted for some reason, cancel
4391 the equiv. We could update the equiv insns after
4392 transformations including an equiv insn deletion
4393 but it is not worthy as such cases are extremely
4395 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4396 /* If it is not a reverse equivalence, we check that a
4397 pseudo in rhs of the init insn is not dying in the
4398 insn. Otherwise, the live info at the beginning of
4399 the corresponding BB might be wrong after we
4400 removed the insn. When the equiv can be a
4401 constant, the right hand side of the init insn can
4403 || (! reverse_equiv_p (i
)
4404 && (init_insn_rhs_dead_pseudo_p (i
)
4405 /* If we reloaded the pseudo in an equivalence
4406 init insn, we can not remove the equiv init
4407 insns and the init insns might write into
4408 const memory in this case. */
4409 || contains_reloaded_insn_p (i
)))
4410 /* Prevent access beyond equivalent memory for
4411 paradoxical subregs. */
4413 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4414 > GET_MODE_SIZE (GET_MODE (x
))))
4415 || (pic_offset_table_rtx
4416 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4417 && (targetm
.preferred_reload_class
4418 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4419 || contains_symbol_ref_p (x
))))
4420 ira_reg_equiv
[i
].defined_p
= false;
4421 if (contains_reg_p (x
, false, true))
4422 ira_reg_equiv
[i
].profitable_p
= false;
4423 if (get_equiv (reg
) != reg
)
4424 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4427 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4429 /* We should add all insns containing pseudos which should be
4430 substituted by their equivalences. */
4431 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4432 lra_push_insn_by_uid (uid
);
4433 min_len
= lra_insn_stack_length ();
4437 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4439 curr_insn
= lra_pop_insn ();
4441 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4442 if (curr_bb
!= last_bb
)
4445 bb_reload_num
= lra_curr_reload_num
;
4447 if (min_len
> new_min_len
)
4449 min_len
= new_min_len
;
4452 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4454 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4455 MAX_RELOAD_INSNS_NUMBER
);
4457 if (DEBUG_INSN_P (curr_insn
))
4459 /* We need to check equivalence in debug insn and change
4460 pseudo to the equivalent value if necessary. */
4461 curr_id
= lra_get_insn_recog_data (curr_insn
);
4462 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4464 rtx old
= *curr_id
->operand_loc
[0];
4465 *curr_id
->operand_loc
[0]
4466 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4467 loc_equivalence_callback
, curr_insn
);
4468 if (old
!= *curr_id
->operand_loc
[0])
4470 lra_update_insn_regno_info (curr_insn
);
4475 else if (INSN_P (curr_insn
))
4477 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4479 dest_reg
= SET_DEST (set
);
4480 /* The equivalence pseudo could be set up as SUBREG in a
4481 case when it is a call restore insn in a mode
4482 different from the pseudo mode. */
4483 if (GET_CODE (dest_reg
) == SUBREG
)
4484 dest_reg
= SUBREG_REG (dest_reg
);
4485 if ((REG_P (dest_reg
)
4486 && (x
= get_equiv (dest_reg
)) != dest_reg
4487 /* Remove insns which set up a pseudo whose value
4488 can not be changed. Such insns might be not in
4489 init_insns because we don't update equiv data
4490 during insn transformations.
4492 As an example, let suppose that a pseudo got
4493 hard register and on the 1st pass was not
4494 changed to equivalent constant. We generate an
4495 additional insn setting up the pseudo because of
4496 secondary memory movement. Then the pseudo is
4497 spilled and we use the equiv constant. In this
4498 case we should remove the additional insn and
4499 this insn is not init_insns list. */
4500 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4501 /* Check that this is actually an insn setting
4502 up the equivalence. */
4503 || in_list_p (curr_insn
,
4505 [REGNO (dest_reg
)].init_insns
)))
4506 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4507 && in_list_p (curr_insn
,
4509 [REGNO (SET_SRC (set
))].init_insns
)))
4511 /* This is equiv init insn of pseudo which did not get a
4512 hard register -- remove the insn. */
4513 if (lra_dump_file
!= NULL
)
4515 fprintf (lra_dump_file
,
4516 " Removing equiv init insn %i (freq=%d)\n",
4517 INSN_UID (curr_insn
),
4518 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4519 dump_insn_slim (lra_dump_file
, curr_insn
);
4521 if (contains_reg_p (x
, true, false))
4522 lra_risky_transformations_p
= true;
4523 lra_set_insn_deleted (curr_insn
);
4527 curr_id
= lra_get_insn_recog_data (curr_insn
);
4528 curr_static_id
= curr_id
->insn_static_data
;
4529 init_curr_insn_input_reloads ();
4530 init_curr_operand_mode ();
4531 if (curr_insn_transform (false))
4533 /* Check non-transformed insns too for equiv change as USE
4534 or CLOBBER don't need reloads but can contain pseudos
4535 being changed on their equivalences. */
4536 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4537 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4539 lra_update_insn_regno_info (curr_insn
);
4544 bitmap_clear (&equiv_insn_bitmap
);
4545 /* If we used a new hard regno, changed_p should be true because the
4546 hard reg is assigned to a new pseudo. */
4547 if (flag_checking
&& !changed_p
)
4549 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4550 if (lra_reg_info
[i
].nrefs
!= 0
4551 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4553 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4555 for (j
= 0; j
< nregs
; j
++)
4556 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4562 /* Initiate the LRA constraint pass. It is done once per
4565 lra_constraints_init (void)
4569 /* Finalize the LRA constraint pass. It is done once per
4572 lra_constraints_finish (void)
4578 /* This page contains code to do inheritance/split
4581 /* Number of reloads passed so far in current EBB. */
4582 static int reloads_num
;
4584 /* Number of calls passed so far in current EBB. */
4585 static int calls_num
;
4587 /* Current reload pseudo check for validity of elements in
4589 static int curr_usage_insns_check
;
4591 /* Info about last usage of registers in EBB to do inheritance/split
4592 transformation. Inheritance transformation is done from a spilled
4593 pseudo and split transformations from a hard register or a pseudo
4594 assigned to a hard register. */
4597 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4598 value INSNS is valid. The insns is chain of optional debug insns
4599 and a finishing non-debug insn using the corresponding reg. The
4600 value is also used to mark the registers which are set up in the
4601 current insn. The negated insn uid is used for this. */
4603 /* Value of global reloads_num at the last insn in INSNS. */
4605 /* Value of global reloads_nums at the last insn in INSNS. */
4607 /* It can be true only for splitting. And it means that the restore
4608 insn should be put after insn given by the following member. */
4610 /* Next insns in the current EBB which use the original reg and the
4611 original reg value is not changed between the current insn and
4612 the next insns. In order words, e.g. for inheritance, if we need
4613 to use the original reg value again in the next insns we can try
4614 to use the value in a hard register from a reload insn of the
4619 /* Map: regno -> corresponding pseudo usage insns. */
4620 static struct usage_insns
*usage_insns
;
4623 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4625 usage_insns
[regno
].check
= curr_usage_insns_check
;
4626 usage_insns
[regno
].insns
= insn
;
4627 usage_insns
[regno
].reloads_num
= reloads_num
;
4628 usage_insns
[regno
].calls_num
= calls_num
;
4629 usage_insns
[regno
].after_p
= after_p
;
4632 /* The function is used to form list REGNO usages which consists of
4633 optional debug insns finished by a non-debug insn using REGNO.
4634 RELOADS_NUM is current number of reload insns processed so far. */
4636 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
4638 rtx next_usage_insns
;
4640 if (usage_insns
[regno
].check
== curr_usage_insns_check
4641 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4642 && DEBUG_INSN_P (insn
))
4644 /* Check that we did not add the debug insn yet. */
4645 if (next_usage_insns
!= insn
4646 && (GET_CODE (next_usage_insns
) != INSN_LIST
4647 || XEXP (next_usage_insns
, 0) != insn
))
4648 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4651 else if (NONDEBUG_INSN_P (insn
))
4652 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4654 usage_insns
[regno
].check
= 0;
4657 /* Return first non-debug insn in list USAGE_INSNS. */
4659 skip_usage_debug_insns (rtx usage_insns
)
4663 /* Skip debug insns. */
4664 for (insn
= usage_insns
;
4665 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4666 insn
= XEXP (insn
, 1))
4668 return safe_as_a
<rtx_insn
*> (insn
);
4671 /* Return true if we need secondary memory moves for insn in
4672 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4675 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4676 rtx usage_insns ATTRIBUTE_UNUSED
)
4678 #ifndef SECONDARY_MEMORY_NEEDED
4685 if (inher_cl
== ALL_REGS
4686 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4688 lra_assert (INSN_P (insn
));
4689 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4691 dest
= SET_DEST (set
);
4694 lra_assert (inher_cl
!= NO_REGS
);
4695 cl
= get_reg_class (REGNO (dest
));
4696 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4697 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4701 /* Registers involved in inheritance/split in the current EBB
4702 (inheritance/split pseudos and original registers). */
4703 static bitmap_head check_only_regs
;
4705 /* Do inheritance transformations for insn INSN, which defines (if
4706 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4707 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4708 form as the "insns" field of usage_insns. Return true if we
4709 succeed in such transformation.
4711 The transformations look like:
4714 ... p <- i (new insn)
4716 <- ... p ... <- ... i ...
4718 ... i <- p (new insn)
4719 <- ... p ... <- ... i ...
4721 <- ... p ... <- ... i ...
4722 where p is a spilled original pseudo and i is a new inheritance pseudo.
4725 The inheritance pseudo has the smallest class of two classes CL and
4726 class of ORIGINAL REGNO. */
4728 inherit_reload_reg (bool def_p
, int original_regno
,
4729 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4731 if (optimize_function_for_size_p (cfun
))
4734 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4735 rtx original_reg
= regno_reg_rtx
[original_regno
];
4736 rtx new_reg
, usage_insn
;
4737 rtx_insn
*new_insns
;
4739 lra_assert (! usage_insns
[original_regno
].after_p
);
4740 if (lra_dump_file
!= NULL
)
4741 fprintf (lra_dump_file
,
4742 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4743 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4745 if (lra_dump_file
!= NULL
)
4747 fprintf (lra_dump_file
,
4748 " Rejecting inheritance for %d "
4749 "because of disjoint classes %s and %s\n",
4750 original_regno
, reg_class_names
[cl
],
4751 reg_class_names
[rclass
]);
4752 fprintf (lra_dump_file
,
4753 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4757 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4758 /* We don't use a subset of two classes because it can be
4759 NO_REGS. This transformation is still profitable in most
4760 cases even if the classes are not intersected as register
4761 move is probably cheaper than a memory load. */
4762 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4764 if (lra_dump_file
!= NULL
)
4765 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4766 reg_class_names
[cl
], reg_class_names
[rclass
]);
4770 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4772 /* Reject inheritance resulting in secondary memory moves.
4773 Otherwise, there is a danger in LRA cycling. Also such
4774 transformation will be unprofitable. */
4775 if (lra_dump_file
!= NULL
)
4777 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4778 rtx set
= single_set (insn
);
4780 lra_assert (set
!= NULL_RTX
);
4782 rtx dest
= SET_DEST (set
);
4784 lra_assert (REG_P (dest
));
4785 fprintf (lra_dump_file
,
4786 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4787 "as secondary mem is needed\n",
4788 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4789 original_regno
, reg_class_names
[rclass
]);
4790 fprintf (lra_dump_file
,
4791 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4795 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4796 rclass
, "inheritance");
4799 lra_emit_move (original_reg
, new_reg
);
4801 lra_emit_move (new_reg
, original_reg
);
4802 new_insns
= get_insns ();
4804 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4806 if (lra_dump_file
!= NULL
)
4808 fprintf (lra_dump_file
,
4809 " Rejecting inheritance %d->%d "
4810 "as it results in 2 or more insns:\n",
4811 original_regno
, REGNO (new_reg
));
4812 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4813 fprintf (lra_dump_file
,
4814 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4818 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
4819 lra_update_insn_regno_info (insn
);
4821 /* We now have a new usage insn for original regno. */
4822 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4823 if (lra_dump_file
!= NULL
)
4824 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4825 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4826 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4827 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4828 bitmap_set_bit (&check_only_regs
, original_regno
);
4829 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4831 lra_process_new_insns (insn
, NULL
, new_insns
,
4832 "Add original<-inheritance");
4834 lra_process_new_insns (insn
, new_insns
, NULL
,
4835 "Add inheritance<-original");
4836 while (next_usage_insns
!= NULL_RTX
)
4838 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4840 usage_insn
= next_usage_insns
;
4841 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4842 next_usage_insns
= NULL
;
4846 usage_insn
= XEXP (next_usage_insns
, 0);
4847 lra_assert (DEBUG_INSN_P (usage_insn
));
4848 next_usage_insns
= XEXP (next_usage_insns
, 1);
4850 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
4851 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4852 if (lra_dump_file
!= NULL
)
4854 fprintf (lra_dump_file
,
4855 " Inheritance reuse change %d->%d (bb%d):\n",
4856 original_regno
, REGNO (new_reg
),
4857 BLOCK_FOR_INSN (usage_insn
)->index
);
4858 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
4861 if (lra_dump_file
!= NULL
)
4862 fprintf (lra_dump_file
,
4863 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4867 /* Return true if we need a caller save/restore for pseudo REGNO which
4868 was assigned to a hard register. */
4870 need_for_call_save_p (int regno
)
4872 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4873 return (usage_insns
[regno
].calls_num
< calls_num
4874 && (overlaps_hard_reg_set_p
4876 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4877 ? lra_reg_info
[regno
].actual_call_used_reg_set
4878 : call_used_reg_set
,
4879 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4880 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4881 PSEUDO_REGNO_MODE (regno
))));
4884 /* Global registers occurring in the current EBB. */
4885 static bitmap_head ebb_global_regs
;
4887 /* Return true if we need a split for hard register REGNO or pseudo
4888 REGNO which was assigned to a hard register.
4889 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4890 used for reloads since the EBB end. It is an approximation of the
4891 used hard registers in the split range. The exact value would
4892 require expensive calculations. If we were aggressive with
4893 splitting because of the approximation, the split pseudo will save
4894 the same hard register assignment and will be removed in the undo
4895 pass. We still need the approximation because too aggressive
4896 splitting would result in too inaccurate cost calculation in the
4897 assignment pass because of too many generated moves which will be
4898 probably removed in the undo pass. */
4900 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4902 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4904 lra_assert (hard_regno
>= 0);
4905 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4906 /* Don't split eliminable hard registers, otherwise we can
4907 split hard registers like hard frame pointer, which
4908 lives on BB start/end according to DF-infrastructure,
4909 when there is a pseudo assigned to the register and
4910 living in the same BB. */
4911 && (regno
>= FIRST_PSEUDO_REGISTER
4912 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4913 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4914 /* Don't split call clobbered hard regs living through
4915 calls, otherwise we might have a check problem in the
4916 assign sub-pass as in the most cases (exception is a
4917 situation when lra_risky_transformations_p value is
4918 true) the assign pass assumes that all pseudos living
4919 through calls are assigned to call saved hard regs. */
4920 && (regno
>= FIRST_PSEUDO_REGISTER
4921 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4922 || usage_insns
[regno
].calls_num
== calls_num
)
4923 /* We need at least 2 reloads to make pseudo splitting
4924 profitable. We should provide hard regno splitting in
4925 any case to solve 1st insn scheduling problem when
4926 moving hard register definition up might result in
4927 impossibility to find hard register for reload pseudo of
4928 small register class. */
4929 && (usage_insns
[regno
].reloads_num
4930 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4931 && (regno
< FIRST_PSEUDO_REGISTER
4932 /* For short living pseudos, spilling + inheritance can
4933 be considered a substitution for splitting.
4934 Therefore we do not splitting for local pseudos. It
4935 decreases also aggressiveness of splitting. The
4936 minimal number of references is chosen taking into
4937 account that for 2 references splitting has no sense
4938 as we can just spill the pseudo. */
4939 || (regno
>= FIRST_PSEUDO_REGISTER
4940 && lra_reg_info
[regno
].nrefs
> 3
4941 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4942 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4945 /* Return class for the split pseudo created from original pseudo with
4946 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4947 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4948 results in no secondary memory movements. */
4949 static enum reg_class
4950 choose_split_class (enum reg_class allocno_class
,
4951 int hard_regno ATTRIBUTE_UNUSED
,
4952 machine_mode mode ATTRIBUTE_UNUSED
)
4954 #ifndef SECONDARY_MEMORY_NEEDED
4955 return allocno_class
;
4958 enum reg_class cl
, best_cl
= NO_REGS
;
4959 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4960 = REGNO_REG_CLASS (hard_regno
);
4962 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4963 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4964 return allocno_class
;
4966 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4968 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4969 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4970 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4971 && (best_cl
== NO_REGS
4972 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4978 /* Do split transformations for insn INSN, which defines or uses
4979 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4980 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4981 "insns" field of usage_insns.
4983 The transformations look like:
4986 ... s <- p (new insn -- save)
4988 ... p <- s (new insn -- restore)
4989 <- ... p ... <- ... p ...
4991 <- ... p ... <- ... p ...
4992 ... s <- p (new insn -- save)
4994 ... p <- s (new insn -- restore)
4995 <- ... p ... <- ... p ...
4997 where p is an original pseudo got a hard register or a hard
4998 register and s is a new split pseudo. The save is put before INSN
4999 if BEFORE_P is true. Return true if we succeed in such
5002 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5003 rtx next_usage_insns
)
5005 enum reg_class rclass
;
5007 int hard_regno
, nregs
;
5008 rtx new_reg
, usage_insn
;
5009 rtx_insn
*restore
, *save
;
5014 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5016 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5017 hard_regno
= original_regno
;
5018 call_save_p
= false;
5020 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5021 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5022 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5023 as part of a multi-word register. In that case, or if the biggest
5024 mode was larger than a register, just use the reg_rtx. Otherwise,
5025 limit the size to that of the biggest access in the function. */
5026 if (mode
== VOIDmode
5027 || GET_MODE_SIZE (mode
) > GET_MODE_SIZE (reg_rtx_mode
))
5029 original_reg
= regno_reg_rtx
[hard_regno
];
5030 mode
= reg_rtx_mode
;
5033 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5037 mode
= PSEUDO_REGNO_MODE (original_regno
);
5038 hard_regno
= reg_renumber
[original_regno
];
5039 nregs
= hard_regno_nregs
[hard_regno
][mode
];
5040 rclass
= lra_get_allocno_class (original_regno
);
5041 original_reg
= regno_reg_rtx
[original_regno
];
5042 call_save_p
= need_for_call_save_p (original_regno
);
5044 lra_assert (hard_regno
>= 0);
5045 if (lra_dump_file
!= NULL
)
5046 fprintf (lra_dump_file
,
5047 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5051 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5052 hard_regno_nregs
[hard_regno
][mode
],
5054 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5058 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5059 if (rclass
== NO_REGS
)
5061 if (lra_dump_file
!= NULL
)
5063 fprintf (lra_dump_file
,
5064 " Rejecting split of %d(%s): "
5065 "no good reg class for %d(%s)\n",
5067 reg_class_names
[lra_get_allocno_class (original_regno
)],
5069 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5072 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5076 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5077 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5079 save
= emit_spill_move (true, new_reg
, original_reg
);
5080 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5082 if (lra_dump_file
!= NULL
)
5086 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5087 original_regno
, REGNO (new_reg
));
5088 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5089 fprintf (lra_dump_file
,
5090 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5094 restore
= emit_spill_move (false, new_reg
, original_reg
);
5095 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5097 if (lra_dump_file
!= NULL
)
5099 fprintf (lra_dump_file
,
5100 " Rejecting split %d->%d "
5101 "resulting in > 2 restore insns:\n",
5102 original_regno
, REGNO (new_reg
));
5103 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5104 fprintf (lra_dump_file
,
5105 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5109 after_p
= usage_insns
[original_regno
].after_p
;
5110 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
5111 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5112 bitmap_set_bit (&check_only_regs
, original_regno
);
5113 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
5116 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5118 usage_insn
= next_usage_insns
;
5121 usage_insn
= XEXP (next_usage_insns
, 0);
5122 lra_assert (DEBUG_INSN_P (usage_insn
));
5123 next_usage_insns
= XEXP (next_usage_insns
, 1);
5124 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5125 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5126 if (lra_dump_file
!= NULL
)
5128 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5129 original_regno
, REGNO (new_reg
));
5130 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5133 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5134 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5135 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5136 after_p
? NULL
: restore
,
5137 after_p
? restore
: NULL
,
5139 ? "Add reg<-save" : "Add reg<-split");
5140 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5141 before_p
? NULL
: save
,
5143 ? "Add save<-reg" : "Add split<-reg");
5145 /* If we are trying to split multi-register. We should check
5146 conflicts on the next assignment sub-pass. IRA can allocate on
5147 sub-register levels, LRA do this on pseudos level right now and
5148 this discrepancy may create allocation conflicts after
5150 lra_risky_transformations_p
= true;
5151 if (lra_dump_file
!= NULL
)
5152 fprintf (lra_dump_file
,
5153 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5157 /* Recognize that we need a split transformation for insn INSN, which
5158 defines or uses REGNO in its insn biggest MODE (we use it only if
5159 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5160 hard registers which might be used for reloads since the EBB end.
5161 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5162 uid before starting INSN processing. Return true if we succeed in
5163 such transformation. */
5165 split_if_necessary (int regno
, machine_mode mode
,
5166 HARD_REG_SET potential_reload_hard_regs
,
5167 bool before_p
, rtx_insn
*insn
, int max_uid
)
5171 rtx next_usage_insns
;
5173 if (regno
< FIRST_PSEUDO_REGISTER
)
5174 nregs
= hard_regno_nregs
[regno
][mode
];
5175 for (i
= 0; i
< nregs
; i
++)
5176 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5177 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5178 /* To avoid processing the register twice or more. */
5179 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5180 && INSN_UID (next_usage_insns
) < max_uid
)
5181 || (GET_CODE (next_usage_insns
) == INSN_LIST
5182 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5183 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5184 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5189 /* Check only registers living at the current program point in the
5191 static bitmap_head live_regs
;
5193 /* Update live info in EBB given by its HEAD and TAIL insns after
5194 inheritance/split transformation. The function removes dead moves
5197 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5202 rtx_insn
*prev_insn
;
5205 basic_block last_bb
, prev_bb
, curr_bb
;
5207 struct lra_insn_reg
*reg
;
5211 last_bb
= BLOCK_FOR_INSN (tail
);
5213 for (curr_insn
= tail
;
5214 curr_insn
!= PREV_INSN (head
);
5215 curr_insn
= prev_insn
)
5217 prev_insn
= PREV_INSN (curr_insn
);
5218 /* We need to process empty blocks too. They contain
5219 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5220 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5222 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5223 if (curr_bb
!= prev_bb
)
5225 if (prev_bb
!= NULL
)
5227 /* Update df_get_live_in (prev_bb): */
5228 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5229 if (bitmap_bit_p (&live_regs
, j
))
5230 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5232 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5234 if (curr_bb
!= last_bb
)
5236 /* Update df_get_live_out (curr_bb): */
5237 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5239 live_p
= bitmap_bit_p (&live_regs
, j
);
5241 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5242 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5248 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5250 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5254 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5256 if (! NONDEBUG_INSN_P (curr_insn
))
5258 curr_id
= lra_get_insn_recog_data (curr_insn
);
5259 curr_static_id
= curr_id
->insn_static_data
;
5261 if ((set
= single_set (curr_insn
)) != NULL_RTX
5262 && REG_P (SET_DEST (set
))
5263 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5264 && SET_DEST (set
) != pic_offset_table_rtx
5265 && bitmap_bit_p (&check_only_regs
, regno
)
5266 && ! bitmap_bit_p (&live_regs
, regno
))
5268 /* See which defined values die here. */
5269 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5270 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5271 bitmap_clear_bit (&live_regs
, reg
->regno
);
5272 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5273 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5274 bitmap_clear_bit (&live_regs
, reg
->regno
);
5275 if (curr_id
->arg_hard_regs
!= NULL
)
5276 /* Make clobbered argument hard registers die. */
5277 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5278 if (regno
>= FIRST_PSEUDO_REGISTER
)
5279 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5280 /* Mark each used value as live. */
5281 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5282 if (reg
->type
!= OP_OUT
5283 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5284 bitmap_set_bit (&live_regs
, reg
->regno
);
5285 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5286 if (reg
->type
!= OP_OUT
5287 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5288 bitmap_set_bit (&live_regs
, reg
->regno
);
5289 if (curr_id
->arg_hard_regs
!= NULL
)
5290 /* Make used argument hard registers live. */
5291 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5292 if (regno
< FIRST_PSEUDO_REGISTER
5293 && bitmap_bit_p (&check_only_regs
, regno
))
5294 bitmap_set_bit (&live_regs
, regno
);
5295 /* It is quite important to remove dead move insns because it
5296 means removing dead store. We don't need to process them for
5300 if (lra_dump_file
!= NULL
)
5302 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5303 dump_insn_slim (lra_dump_file
, curr_insn
);
5305 lra_set_insn_deleted (curr_insn
);
5310 /* The structure describes info to do an inheritance for the current
5311 insn. We need to collect such info first before doing the
5312 transformations because the transformations change the insn
5313 internal representation. */
5316 /* Original regno. */
5318 /* Subsequent insns which can inherit original reg value. */
5322 /* Array containing all info for doing inheritance from the current
5324 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5326 /* Number elements in the previous array. */
5327 static int to_inherit_num
;
5329 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5330 structure to_inherit. */
5332 add_to_inherit (int regno
, rtx insns
)
5336 for (i
= 0; i
< to_inherit_num
; i
++)
5337 if (to_inherit
[i
].regno
== regno
)
5339 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5340 to_inherit
[to_inherit_num
].regno
= regno
;
5341 to_inherit
[to_inherit_num
++].insns
= insns
;
5344 /* Return the last non-debug insn in basic block BB, or the block begin
5347 get_last_insertion_point (basic_block bb
)
5351 FOR_BB_INSNS_REVERSE (bb
, insn
)
5352 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5357 /* Set up RES by registers living on edges FROM except the edge (FROM,
5358 TO) or by registers set up in a jump insn in BB FROM. */
5360 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5363 struct lra_insn_reg
*reg
;
5367 lra_assert (to
!= NULL
);
5369 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5371 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5372 last
= get_last_insertion_point (from
);
5373 if (! JUMP_P (last
))
5375 curr_id
= lra_get_insn_recog_data (last
);
5376 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5377 if (reg
->type
!= OP_IN
)
5378 bitmap_set_bit (res
, reg
->regno
);
5381 /* Used as a temporary results of some bitmap calculations. */
5382 static bitmap_head temp_bitmap
;
5384 /* We split for reloads of small class of hard regs. The following
5385 defines how many hard regs the class should have to be qualified as
5386 small. The code is mostly oriented to x86/x86-64 architecture
5387 where some insns need to use only specific register or pair of
5388 registers and these register can live in RTL explicitly, e.g. for
5389 parameter passing. */
5390 static const int max_small_class_regs_num
= 2;
5392 /* Do inheritance/split transformations in EBB starting with HEAD and
5393 finishing on TAIL. We process EBB insns in the reverse order.
5394 Return true if we did any inheritance/split transformation in the
5397 We should avoid excessive splitting which results in worse code
5398 because of inaccurate cost calculations for spilling new split
5399 pseudos in such case. To achieve this we do splitting only if
5400 register pressure is high in given basic block and there are reload
5401 pseudos requiring hard registers. We could do more register
5402 pressure calculations at any given program point to avoid necessary
5403 splitting even more but it is to expensive and the current approach
5404 works well enough. */
5406 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5408 int i
, src_regno
, dst_regno
, nregs
;
5409 bool change_p
, succ_p
, update_reloads_num_p
;
5410 rtx_insn
*prev_insn
, *last_insn
;
5411 rtx next_usage_insns
, set
;
5413 struct lra_insn_reg
*reg
;
5414 basic_block last_processed_bb
, curr_bb
= NULL
;
5415 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5419 bool head_p
, after_p
;
5422 curr_usage_insns_check
++;
5423 reloads_num
= calls_num
= 0;
5424 bitmap_clear (&check_only_regs
);
5425 last_processed_bb
= NULL
;
5426 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5427 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5428 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5429 /* We don't process new insns generated in the loop. */
5430 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5432 prev_insn
= PREV_INSN (curr_insn
);
5433 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5434 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5435 if (last_processed_bb
!= curr_bb
)
5437 /* We are at the end of BB. Add qualified living
5438 pseudos for potential splitting. */
5439 to_process
= df_get_live_out (curr_bb
);
5440 if (last_processed_bb
!= NULL
)
5442 /* We are somewhere in the middle of EBB. */
5443 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5445 to_process
= &temp_bitmap
;
5447 last_processed_bb
= curr_bb
;
5448 last_insn
= get_last_insertion_point (curr_bb
);
5449 after_p
= (! JUMP_P (last_insn
)
5450 && (! CALL_P (last_insn
)
5451 || (find_reg_note (last_insn
,
5452 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5453 && ! SIBLING_CALL_P (last_insn
))));
5454 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5455 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5457 if ((int) j
>= lra_constraint_new_regno_start
)
5459 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5461 if (j
< FIRST_PSEUDO_REGISTER
)
5462 SET_HARD_REG_BIT (live_hard_regs
, j
);
5464 add_to_hard_reg_set (&live_hard_regs
,
5465 PSEUDO_REGNO_MODE (j
),
5467 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5471 src_regno
= dst_regno
= -1;
5472 if (NONDEBUG_INSN_P (curr_insn
)
5473 && (set
= single_set (curr_insn
)) != NULL_RTX
5474 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5476 src_regno
= REGNO (SET_SRC (set
));
5477 dst_regno
= REGNO (SET_DEST (set
));
5479 update_reloads_num_p
= true;
5480 if (src_regno
< lra_constraint_new_regno_start
5481 && src_regno
>= FIRST_PSEUDO_REGISTER
5482 && reg_renumber
[src_regno
] < 0
5483 && dst_regno
>= lra_constraint_new_regno_start
5484 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5486 /* 'reload_pseudo <- original_pseudo'. */
5487 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5489 update_reloads_num_p
= false;
5491 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5492 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5493 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5494 curr_insn
, next_usage_insns
);
5498 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5499 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5500 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5501 reg_class_contents
[cl
]);
5503 else if (src_regno
>= lra_constraint_new_regno_start
5504 && dst_regno
< lra_constraint_new_regno_start
5505 && dst_regno
>= FIRST_PSEUDO_REGISTER
5506 && reg_renumber
[dst_regno
] < 0
5507 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5508 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5509 && (next_usage_insns
5510 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5512 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5514 update_reloads_num_p
= false;
5515 /* 'original_pseudo <- reload_pseudo'. */
5516 if (! JUMP_P (curr_insn
)
5517 && inherit_reload_reg (true, dst_regno
, cl
,
5518 curr_insn
, next_usage_insns
))
5521 usage_insns
[dst_regno
].check
= 0;
5522 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5523 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5524 reg_class_contents
[cl
]);
5526 else if (INSN_P (curr_insn
))
5529 int max_uid
= get_max_uid ();
5531 curr_id
= lra_get_insn_recog_data (curr_insn
);
5532 curr_static_id
= curr_id
->insn_static_data
;
5534 /* Process insn definitions. */
5535 for (iter
= 0; iter
< 2; iter
++)
5536 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5539 if (reg
->type
!= OP_IN
5540 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5542 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5543 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5544 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5545 && (next_usage_insns
5546 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5548 struct lra_insn_reg
*r
;
5550 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5551 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5553 /* Don't do inheritance if the pseudo is also
5554 used in the insn. */
5556 /* We can not do inheritance right now
5557 because the current insn reg info (chain
5558 regs) can change after that. */
5559 add_to_inherit (dst_regno
, next_usage_insns
);
5561 /* We can not process one reg twice here because of
5562 usage_insns invalidation. */
5563 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5564 || reg_renumber
[dst_regno
] >= 0)
5565 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5569 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5570 potential_reload_hard_regs
,
5571 false, curr_insn
, max_uid
))
5573 CLEAR_HARD_REG_SET (s
);
5574 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5575 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5577 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5578 reg_renumber
[dst_regno
]);
5579 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5581 /* We should invalidate potential inheritance or
5582 splitting for the current insn usages to the next
5583 usage insns (see code below) as the output pseudo
5585 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5586 && reg_renumber
[dst_regno
] < 0)
5587 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5588 && (dst_regno
< FIRST_PSEUDO_REGISTER
5589 || reg_renumber
[dst_regno
] >= 0)))
5591 /* Invalidate and mark definitions. */
5592 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5593 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5596 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5597 for (i
= 0; i
< nregs
; i
++)
5598 usage_insns
[dst_regno
+ i
].check
5599 = -(int) INSN_UID (curr_insn
);
5603 /* Process clobbered call regs. */
5604 if (curr_id
->arg_hard_regs
!= NULL
)
5605 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5606 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5607 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
5608 = -(int) INSN_UID (curr_insn
);
5609 if (! JUMP_P (curr_insn
))
5610 for (i
= 0; i
< to_inherit_num
; i
++)
5611 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5612 ALL_REGS
, curr_insn
,
5613 to_inherit
[i
].insns
))
5615 if (CALL_P (curr_insn
))
5617 rtx cheap
, pat
, dest
;
5619 int regno
, hard_regno
;
5622 if ((cheap
= find_reg_note (curr_insn
,
5623 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5624 && ((cheap
= XEXP (cheap
, 0)), true)
5625 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5626 && (hard_regno
= reg_renumber
[regno
]) >= 0
5627 /* If there are pending saves/restores, the
5628 optimization is not worth. */
5629 && usage_insns
[regno
].calls_num
== calls_num
- 1
5630 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5632 /* Restore the pseudo from the call result as
5633 REG_RETURNED note says that the pseudo value is
5634 in the call result and the pseudo is an argument
5636 pat
= PATTERN (curr_insn
);
5637 if (GET_CODE (pat
) == PARALLEL
)
5638 pat
= XVECEXP (pat
, 0, 0);
5639 dest
= SET_DEST (pat
);
5640 /* For multiple return values dest is PARALLEL.
5641 Currently we handle only single return value case. */
5645 emit_move_insn (cheap
, copy_rtx (dest
));
5646 restore
= get_insns ();
5648 lra_process_new_insns (curr_insn
, NULL
, restore
,
5649 "Inserting call parameter restore");
5650 /* We don't need to save/restore of the pseudo from
5652 usage_insns
[regno
].calls_num
= calls_num
;
5653 bitmap_set_bit (&check_only_regs
, regno
);
5658 /* Process insn usages. */
5659 for (iter
= 0; iter
< 2; iter
++)
5660 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5663 if ((reg
->type
!= OP_OUT
5664 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5665 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5667 if (src_regno
>= FIRST_PSEUDO_REGISTER
5668 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5670 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5671 && (next_usage_insns
5672 = usage_insns
[src_regno
].insns
) != NULL_RTX
5673 && NONDEBUG_INSN_P (curr_insn
))
5674 add_to_inherit (src_regno
, next_usage_insns
);
5675 else if (usage_insns
[src_regno
].check
5676 != -(int) INSN_UID (curr_insn
))
5677 /* Add usages but only if the reg is not set up
5678 in the same insn. */
5679 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5681 else if (src_regno
< FIRST_PSEUDO_REGISTER
5682 || reg_renumber
[src_regno
] >= 0)
5685 rtx_insn
*use_insn
= curr_insn
;
5687 before_p
= (JUMP_P (curr_insn
)
5688 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5689 if (NONDEBUG_INSN_P (curr_insn
)
5690 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5691 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5692 potential_reload_hard_regs
,
5693 before_p
, curr_insn
, max_uid
))
5696 lra_risky_transformations_p
= true;
5699 usage_insns
[src_regno
].check
= 0;
5701 use_insn
= PREV_INSN (curr_insn
);
5703 if (NONDEBUG_INSN_P (curr_insn
))
5705 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5706 add_to_hard_reg_set (&live_hard_regs
,
5707 reg
->biggest_mode
, src_regno
);
5709 add_to_hard_reg_set (&live_hard_regs
,
5710 PSEUDO_REGNO_MODE (src_regno
),
5711 reg_renumber
[src_regno
]);
5713 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5716 /* Process used call regs. */
5717 if (curr_id
->arg_hard_regs
!= NULL
)
5718 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5719 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5721 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5722 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5724 for (i
= 0; i
< to_inherit_num
; i
++)
5726 src_regno
= to_inherit
[i
].regno
;
5727 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5728 curr_insn
, to_inherit
[i
].insns
))
5731 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5734 if (update_reloads_num_p
5735 && NONDEBUG_INSN_P (curr_insn
)
5736 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5739 if ((REG_P (SET_DEST (set
))
5740 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5741 && reg_renumber
[regno
] < 0
5742 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5743 || (REG_P (SET_SRC (set
))
5744 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5745 && reg_renumber
[regno
] < 0
5746 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5748 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5750 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5751 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5752 reg_class_contents
[cl
]);
5755 /* We reached the start of the current basic block. */
5756 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5757 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5759 /* We reached the beginning of the current block -- do
5760 rest of spliting in the current BB. */
5761 to_process
= df_get_live_in (curr_bb
);
5762 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5764 /* We are somewhere in the middle of EBB. */
5765 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5766 curr_bb
, &temp_bitmap
);
5767 to_process
= &temp_bitmap
;
5770 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5772 if ((int) j
>= lra_constraint_new_regno_start
)
5774 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5775 && usage_insns
[j
].check
== curr_usage_insns_check
5776 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5778 if (need_for_split_p (potential_reload_hard_regs
, j
))
5780 if (lra_dump_file
!= NULL
&& head_p
)
5782 fprintf (lra_dump_file
,
5783 " ----------------------------------\n");
5786 if (split_reg (false, j
, bb_note (curr_bb
),
5790 usage_insns
[j
].check
= 0;
5798 /* This value affects EBB forming. If probability of edge from EBB to
5799 a BB is not greater than the following value, we don't add the BB
5801 #define EBB_PROBABILITY_CUTOFF \
5802 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
5804 /* Current number of inheritance/split iteration. */
5805 int lra_inheritance_iter
;
5807 /* Entry function for inheritance/split pass. */
5809 lra_inheritance (void)
5812 basic_block bb
, start_bb
;
5815 lra_inheritance_iter
++;
5816 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5818 timevar_push (TV_LRA_INHERITANCE
);
5819 if (lra_dump_file
!= NULL
)
5820 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5821 lra_inheritance_iter
);
5822 curr_usage_insns_check
= 0;
5823 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5824 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5825 usage_insns
[i
].check
= 0;
5826 bitmap_initialize (&check_only_regs
, ®_obstack
);
5827 bitmap_initialize (&live_regs
, ®_obstack
);
5828 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5829 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5830 FOR_EACH_BB_FN (bb
, cfun
)
5833 if (lra_dump_file
!= NULL
)
5834 fprintf (lra_dump_file
, "EBB");
5835 /* Form a EBB starting with BB. */
5836 bitmap_clear (&ebb_global_regs
);
5837 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5840 if (lra_dump_file
!= NULL
)
5841 fprintf (lra_dump_file
, " %d", bb
->index
);
5842 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5843 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5845 e
= find_fallthru_edge (bb
->succs
);
5848 if (e
->probability
< EBB_PROBABILITY_CUTOFF
)
5852 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5853 if (lra_dump_file
!= NULL
)
5854 fprintf (lra_dump_file
, "\n");
5855 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5856 /* Remember that the EBB head and tail can change in
5858 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5860 bitmap_clear (&ebb_global_regs
);
5861 bitmap_clear (&temp_bitmap
);
5862 bitmap_clear (&live_regs
);
5863 bitmap_clear (&check_only_regs
);
5866 timevar_pop (TV_LRA_INHERITANCE
);
5871 /* This page contains code to undo failed inheritance/split
5874 /* Current number of iteration undoing inheritance/split. */
5875 int lra_undo_inheritance_iter
;
5877 /* Fix BB live info LIVE after removing pseudos created on pass doing
5878 inheritance/split which are REMOVED_PSEUDOS. */
5880 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5885 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5886 if (bitmap_clear_bit (live
, regno
))
5887 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5890 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5895 if (GET_CODE (reg
) == SUBREG
)
5896 reg
= SUBREG_REG (reg
);
5902 /* Delete a move INSN with destination reg DREGNO and a previous
5903 clobber insn with the same regno. The inheritance/split code can
5904 generate moves with preceding clobber and when we delete such moves
5905 we should delete the clobber insn too to keep the correct life
5908 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
5910 rtx_insn
*prev_insn
= PREV_INSN (insn
);
5912 lra_set_insn_deleted (insn
);
5913 lra_assert (dregno
>= 0);
5914 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
5915 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
5916 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
5917 lra_set_insn_deleted (prev_insn
);
5920 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5921 return true if we did any change. The undo transformations for
5922 inheritance looks like
5926 p <- i, i <- p, and i <- i3
5927 where p is original pseudo from which inheritance pseudo i was
5928 created, i and i3 are removed inheritance pseudos, i2 is another
5929 not removed inheritance pseudo. All split pseudos or other
5930 occurrences of removed inheritance pseudos are changed on the
5931 corresponding original pseudos.
5933 The function also schedules insns changed and created during
5934 inheritance/split pass for processing by the subsequent constraint
5937 remove_inheritance_pseudos (bitmap remove_pseudos
)
5940 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5942 rtx_insn
*prev_insn
;
5943 bool change_p
, done_p
;
5945 change_p
= ! bitmap_empty_p (remove_pseudos
);
5946 /* We can not finish the function right away if CHANGE_P is true
5947 because we need to marks insns affected by previous
5948 inheritance/split pass for processing by the subsequent
5950 FOR_EACH_BB_FN (bb
, cfun
)
5952 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5953 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5954 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5956 if (! INSN_P (curr_insn
))
5959 sregno
= dregno
= -1;
5960 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5961 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5963 dregno
= get_regno (SET_DEST (set
));
5964 sregno
= get_regno (SET_SRC (set
));
5967 if (sregno
>= 0 && dregno
>= 0)
5969 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5970 && (lra_reg_info
[sregno
].restore_regno
== dregno
5971 || (bitmap_bit_p (remove_pseudos
, dregno
)
5972 && (lra_reg_info
[sregno
].restore_regno
5973 == lra_reg_info
[dregno
].restore_regno
))))
5974 || (bitmap_bit_p (remove_pseudos
, dregno
)
5975 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5976 /* One of the following cases:
5977 original <- removed inheritance pseudo
5978 removed inherit pseudo <- another removed inherit pseudo
5979 removed inherit pseudo <- original pseudo
5981 removed_split_pseudo <- original_reg
5982 original_reg <- removed_split_pseudo */
5984 if (lra_dump_file
!= NULL
)
5986 fprintf (lra_dump_file
, " Removing %s:\n",
5987 bitmap_bit_p (&lra_split_regs
, sregno
)
5988 || bitmap_bit_p (&lra_split_regs
, dregno
)
5989 ? "split" : "inheritance");
5990 dump_insn_slim (lra_dump_file
, curr_insn
);
5992 delete_move_and_clobber (curr_insn
, dregno
);
5995 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5996 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5998 /* Search the following pattern:
5999 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6000 original_pseudo <- inherit_or_split_pseudo1
6001 where the 2nd insn is the current insn and
6002 inherit_or_split_pseudo2 is not removed. If it is found,
6003 change the current insn onto:
6004 original_pseudo <- inherit_or_split_pseudo2. */
6005 for (prev_insn
= PREV_INSN (curr_insn
);
6006 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6007 prev_insn
= PREV_INSN (prev_insn
))
6009 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6010 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6011 /* There should be no subregs in insn we are
6012 searching because only the original reg might
6013 be in subreg when we changed the mode of
6014 load/store for splitting. */
6015 && REG_P (SET_DEST (prev_set
))
6016 && REG_P (SET_SRC (prev_set
))
6017 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6018 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6019 >= FIRST_PSEUDO_REGISTER
)
6020 /* As we consider chain of inheritance or
6021 splitting described in above comment we should
6022 check that sregno and prev_sregno were
6023 inheritance/split pseudos created from the
6024 same original regno. */
6025 && (lra_reg_info
[sregno
].restore_regno
6026 == lra_reg_info
[prev_sregno
].restore_regno
)
6027 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6029 lra_assert (GET_MODE (SET_SRC (prev_set
))
6030 == GET_MODE (regno_reg_rtx
[sregno
]));
6031 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6032 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6034 SET_SRC (set
) = SET_SRC (prev_set
);
6035 /* As we are finishing with processing the insn
6036 here, check the destination too as it might
6037 inheritance pseudo for another pseudo. */
6038 if (bitmap_bit_p (remove_pseudos
, dregno
)
6039 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6041 = lra_reg_info
[dregno
].restore_regno
) >= 0)
6043 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6044 SUBREG_REG (SET_DEST (set
))
6045 = regno_reg_rtx
[restore_regno
];
6047 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
6049 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6050 lra_set_used_insn_alternative_by_uid
6051 (INSN_UID (curr_insn
), -1);
6053 if (lra_dump_file
!= NULL
)
6055 fprintf (lra_dump_file
, " Change reload insn:\n");
6056 dump_insn_slim (lra_dump_file
, curr_insn
);
6063 struct lra_insn_reg
*reg
;
6064 bool restored_regs_p
= false;
6065 bool kept_regs_p
= false;
6067 curr_id
= lra_get_insn_recog_data (curr_insn
);
6068 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6071 restore_regno
= lra_reg_info
[regno
].restore_regno
;
6072 if (restore_regno
>= 0)
6074 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6076 lra_substitute_pseudo_within_insn
6077 (curr_insn
, regno
, regno_reg_rtx
[restore_regno
],
6079 restored_regs_p
= true;
6085 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6087 /* The instruction has changed since the previous
6088 constraints pass. */
6089 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6090 lra_set_used_insn_alternative_by_uid
6091 (INSN_UID (curr_insn
), -1);
6093 else if (restored_regs_p
)
6094 /* The instruction has been restored to the form that
6095 it had during the previous constraints pass. */
6096 lra_update_insn_regno_info (curr_insn
);
6097 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6099 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6100 dump_insn_slim (lra_dump_file
, curr_insn
);
6108 /* If optional reload pseudos failed to get a hard register or was not
6109 inherited, it is better to remove optional reloads. We do this
6110 transformation after undoing inheritance to figure out necessity to
6111 remove optional reloads easier. Return true if we do any
6114 undo_optional_reloads (void)
6116 bool change_p
, keep_p
;
6117 unsigned int regno
, uid
;
6118 bitmap_iterator bi
, bi2
;
6121 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
6123 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
6124 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6125 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6128 /* Keep optional reloads from previous subpasses. */
6129 if (lra_reg_info
[regno
].restore_regno
< 0
6130 /* If the original pseudo changed its allocation, just
6131 removing the optional pseudo is dangerous as the original
6132 pseudo will have longer live range. */
6133 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
6135 else if (reg_renumber
[regno
] >= 0)
6136 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6138 insn
= lra_insn_recog_data
[uid
]->insn
;
6139 if ((set
= single_set (insn
)) == NULL_RTX
)
6141 src
= SET_SRC (set
);
6142 dest
= SET_DEST (set
);
6143 if (! REG_P (src
) || ! REG_P (dest
))
6145 if (REGNO (dest
) == regno
6146 /* Ignore insn for optional reloads itself. */
6147 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
6148 /* Check only inheritance on last inheritance pass. */
6149 && (int) REGNO (src
) >= new_regno_start
6150 /* Check that the optional reload was inherited. */
6151 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6159 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
6160 if (lra_dump_file
!= NULL
)
6161 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6164 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
6165 bitmap_initialize (&insn_bitmap
, ®_obstack
);
6166 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
6168 if (lra_dump_file
!= NULL
)
6169 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6170 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6171 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
6173 insn
= lra_insn_recog_data
[uid
]->insn
;
6174 if ((set
= single_set (insn
)) != NULL_RTX
)
6176 src
= SET_SRC (set
);
6177 dest
= SET_DEST (set
);
6178 if (REG_P (src
) && REG_P (dest
)
6179 && ((REGNO (src
) == regno
6180 && (lra_reg_info
[regno
].restore_regno
6181 == (int) REGNO (dest
)))
6182 || (REGNO (dest
) == regno
6183 && (lra_reg_info
[regno
].restore_regno
6184 == (int) REGNO (src
)))))
6186 if (lra_dump_file
!= NULL
)
6188 fprintf (lra_dump_file
, " Deleting move %u\n",
6190 dump_insn_slim (lra_dump_file
, insn
);
6192 delete_move_and_clobber (insn
, REGNO (dest
));
6195 /* We should not worry about generation memory-memory
6196 moves here as if the corresponding inheritance did
6197 not work (inheritance pseudo did not get a hard reg),
6198 we remove the inheritance pseudo and the optional
6201 lra_substitute_pseudo_within_insn
6202 (insn
, regno
, regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
],
6204 lra_update_insn_regno_info (insn
);
6205 if (lra_dump_file
!= NULL
)
6207 fprintf (lra_dump_file
,
6208 " Restoring original insn:\n");
6209 dump_insn_slim (lra_dump_file
, insn
);
6213 /* Clear restore_regnos. */
6214 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6215 lra_reg_info
[regno
].restore_regno
= -1;
6216 bitmap_clear (&insn_bitmap
);
6217 bitmap_clear (&removed_optional_reload_pseudos
);
6221 /* Entry function for undoing inheritance/split transformation. Return true
6222 if we did any RTL change in this pass. */
6224 lra_undo_inheritance (void)
6227 int restore_regno
, hard_regno
;
6228 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6229 bitmap_head remove_pseudos
;
6233 lra_undo_inheritance_iter
++;
6234 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6236 if (lra_dump_file
!= NULL
)
6237 fprintf (lra_dump_file
,
6238 "\n********** Undoing inheritance #%d: **********\n\n",
6239 lra_undo_inheritance_iter
);
6240 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6241 n_inherit
= n_all_inherit
= 0;
6242 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6243 if (lra_reg_info
[regno
].restore_regno
>= 0)
6246 if (reg_renumber
[regno
] < 0
6247 /* If the original pseudo changed its allocation, just
6248 removing inheritance is dangerous as for changing
6249 allocation we used shorter live-ranges. */
6250 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
6251 bitmap_set_bit (&remove_pseudos
, regno
);
6255 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6256 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6257 n_inherit
, n_all_inherit
,
6258 (double) n_inherit
/ n_all_inherit
* 100);
6259 n_split
= n_all_split
= 0;
6260 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6261 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6264 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6265 ? reg_renumber
[restore_regno
] : restore_regno
);
6266 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6267 bitmap_set_bit (&remove_pseudos
, regno
);
6271 if (lra_dump_file
!= NULL
)
6272 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6273 regno
, restore_regno
);
6276 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6277 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6278 n_split
, n_all_split
,
6279 (double) n_split
/ n_all_split
* 100);
6280 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6281 bitmap_clear (&remove_pseudos
);
6282 /* Clear restore_regnos. */
6283 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6284 lra_reg_info
[regno
].restore_regno
= -1;
6285 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6286 lra_reg_info
[regno
].restore_regno
= -1;
6287 change_p
= undo_optional_reloads () || change_p
;