gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2014 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "stor-layout.h"
  85 #include "tm_p.h"
  86 #include "flags.h"
  87 #include "regs.h"
  88 #include "hard-reg-set.h"
  89 #include "predict.h"
  90 #include "vec.h"
  91 #include "hashtab.h"
  92 #include "hash-set.h"
  93 #include "machmode.h"
  94 #include "input.h"
  95 #include "function.h"
  96 #include "dominance.h"
  97 #include "cfg.h"
  98 #include "cfgrtl.h"
  99 #include "cfgcleanup.h"
 100 #include "basic-block.h"
 101 #include "insn-config.h"
 102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
 103 #include "expr.h"
 104 #include "insn-attr.h"
 105 #include "recog.h"
 106 #include "diagnostic-core.h"
 107 #include "target.h"
 108 #include "insn-codes.h"
 109 #include "optabs.h"
 110 #include "rtlhooks-def.h"
 111 #include "params.h"
 112 #include "tree-pass.h"
 113 #include "df.h"
 114 #include "valtrack.h"
 115 #include "hash-map.h"
 116 #include "is-a.h"
 117 #include "plugin-api.h"
 118 #include "ipa-ref.h"
 119 #include "cgraph.h"
 120 #include "obstack.h"
 121 #include "statistics.h"
 122 #include "params.h"
 123 #include "rtl-iter.h"
 124
 125 /* Number of attempts to combine instructions in this function.  */
 126
 127 static int combine_attempts;
 128
 129 /* Number of attempts that got as far as substitution in this function.  */
 130
 131 static int combine_merges;
 132
 133 /* Number of instructions combined with added SETs in this function.  */
 134
 135 static int combine_extras;
 136
 137 /* Number of instructions combined in this function.  */
 138
 139 static int combine_successes;
 140
 141 /* Totals over entire compilation.  */
 142
 143 static int total_attempts, total_merges, total_extras, total_successes;
 144
 145 /* combine_instructions may try to replace the right hand side of the
 146    second instruction with the value of an associated REG_EQUAL note
 147    before throwing it at try_combine.  That is problematic when there
 148    is a REG_DEAD note for a register used in the old right hand side
 149    and can cause distribute_notes to do wrong things.  This is the
 150    second instruction if it has been so modified, null otherwise.  */
 151
 152 static rtx_insn *i2mod;
 153
 154 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 155
 156 static rtx i2mod_old_rhs;
 157
 158 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 159
 160 static rtx i2mod_new_rhs;
 161 \f
 162 typedef struct reg_stat_struct {
 163   /* Record last point of death of (hard or pseudo) register n.  */
 164   rtx_insn                      *last_death;
 165
 166   /* Record last point of modification of (hard or pseudo) register n.  */
 167   rtx_insn                      *last_set;
 168
 169   /* The next group of fields allows the recording of the last value assigned
 170      to (hard or pseudo) register n.  We use this information to see if an
 171      operation being processed is redundant given a prior operation performed
 172      on the register.  For example, an `and' with a constant is redundant if
 173      all the zero bits are already known to be turned off.
 174
 175      We use an approach similar to that used by cse, but change it in the
 176      following ways:
 177
 178      (1) We do not want to reinitialize at each label.
 179      (2) It is useful, but not critical, to know the actual value assigned
 180          to a register.  Often just its form is helpful.
 181
 182      Therefore, we maintain the following fields:
 183
 184      last_set_value             the last value assigned
 185      last_set_label             records the value of label_tick when the
 186                                 register was assigned
 187      last_set_table_tick        records the value of label_tick when a
 188                                 value using the register is assigned
 189      last_set_invalid           set to nonzero when it is not valid
 190                                 to use the value of this register in some
 191                                 register's value
 192
 193      To understand the usage of these tables, it is important to understand
 194      the distinction between the value in last_set_value being valid and
 195      the register being validly contained in some other expression in the
 196      table.
 197
 198      (The next two parameters are out of date).
 199
 200      reg_stat[i].last_set_value is valid if it is nonzero, and either
 201      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 202
 203      Register I may validly appear in any expression returned for the value
 204      of another register if reg_n_sets[i] is 1.  It may also appear in the
 205      value for register J if reg_stat[j].last_set_invalid is zero, or
 206      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 207
 208      If an expression is found in the table containing a register which may
 209      not validly appear in an expression, the register is replaced by
 210      something that won't match, (clobber (const_int 0)).  */
 211
 212   /* Record last value assigned to (hard or pseudo) register n.  */
 213
 214   rtx                           last_set_value;
 215
 216   /* Record the value of label_tick when an expression involving register n
 217      is placed in last_set_value.  */
 218
 219   int                           last_set_table_tick;
 220
 221   /* Record the value of label_tick when the value for register n is placed in
 222      last_set_value.  */
 223
 224   int                           last_set_label;
 225
 226   /* These fields are maintained in parallel with last_set_value and are
 227      used to store the mode in which the register was last set, the bits
 228      that were known to be zero when it was last set, and the number of
 229      sign bits copies it was known to have when it was last set.  */
 230
 231   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 232   char                          last_set_sign_bit_copies;
 233   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 234
 235   /* Set nonzero if references to register n in expressions should not be
 236      used.  last_set_invalid is set nonzero when this register is being
 237      assigned to and last_set_table_tick == label_tick.  */
 238
 239   char                          last_set_invalid;
 240
 241   /* Some registers that are set more than once and used in more than one
 242      basic block are nevertheless always set in similar ways.  For example,
 243      a QImode register may be loaded from memory in two places on a machine
 244      where byte loads zero extend.
 245
 246      We record in the following fields if a register has some leading bits
 247      that are always equal to the sign bit, and what we know about the
 248      nonzero bits of a register, specifically which bits are known to be
 249      zero.
 250
 251      If an entry is zero, it means that we don't know anything special.  */
 252
 253   unsigned char                 sign_bit_copies;
 254
 255   unsigned HOST_WIDE_INT        nonzero_bits;
 256
 257   /* Record the value of the label_tick when the last truncation
 258      happened.  The field truncated_to_mode is only valid if
 259      truncation_label == label_tick.  */
 260
 261   int                           truncation_label;
 262
 263   /* Record the last truncation seen for this register.  If truncation
 264      is not a nop to this mode we might be able to save an explicit
 265      truncation if we know that value already contains a truncated
 266      value.  */
 267
 268   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 269 } reg_stat_type;
 270
 271
 272 static vec<reg_stat_type> reg_stat;
 273
 274 /* Record the luid of the last insn that invalidated memory
 275    (anything that writes memory, and subroutine calls, but not pushes).  */
 276
 277 static int mem_last_set;
 278
 279 /* Record the luid of the last CALL_INSN
 280    so we can tell whether a potential combination crosses any calls.  */
 281
 282 static int last_call_luid;
 283
 284 /* When `subst' is called, this is the insn that is being modified
 285    (by combining in a previous insn).  The PATTERN of this insn
 286    is still the old pattern partially modified and it should not be
 287    looked at, but this may be used to examine the successors of the insn
 288    to judge whether a simplification is valid.  */
 289
 290 static rtx_insn *subst_insn;
 291
 292 /* This is the lowest LUID that `subst' is currently dealing with.
 293    get_last_value will not return a value if the register was set at or
 294    after this LUID.  If not for this mechanism, we could get confused if
 295    I2 or I1 in try_combine were an insn that used the old value of a register
 296    to obtain a new value.  In that case, we might erroneously get the
 297    new value of the register when we wanted the old one.  */
 298
 299 static int subst_low_luid;
 300
 301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 302    must consider all these registers to be always live.  */
 303
 304 static HARD_REG_SET newpat_used_regs;
 305
 306 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 307    insn is the earlier than I2 or I3, combine should rescan starting at
 308    that location.  */
 309
 310 static rtx_insn *added_links_insn;
 311
 312 /* Basic block in which we are performing combines.  */
 313 static basic_block this_basic_block;
 314 static bool optimize_this_for_speed_p;
 315
 316 \f
 317 /* Length of the currently allocated uid_insn_cost array.  */
 318
 319 static int max_uid_known;
 320
 321 /* The following array records the insn_rtx_cost for every insn
 322    in the instruction stream.  */
 323
 324 static int *uid_insn_cost;
 325
 326 /* The following array records the LOG_LINKS for every insn in the
 327    instruction stream as struct insn_link pointers.  */
 328
 329 struct insn_link {
 330   rtx_insn *insn;
 331   struct insn_link *next;
 332 };
 333
 334 static struct insn_link **uid_log_links;
 335
 336 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 337 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 338
 339 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 340   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 341
 342 /* Links for LOG_LINKS are allocated from this obstack.  */
 343
 344 static struct obstack insn_link_obstack;
 345
 346 /* Allocate a link.  */
 347
 348 static inline struct insn_link *
 349 alloc_insn_link (rtx_insn *insn, struct insn_link *next)
 350 {
 351   struct insn_link *l
 352     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 353                                           sizeof (struct insn_link));
 354   l->insn = insn;
 355   l->next = next;
 356   return l;
 357 }
 358
 359 /* Incremented for each basic block.  */
 360
 361 static int label_tick;
 362
 363 /* Reset to label_tick for each extended basic block in scanning order.  */
 364
 365 static int label_tick_ebb_start;
 366
 367 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 368    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 369
 370 static machine_mode nonzero_bits_mode;
 371
 372 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 373    be safely used.  It is zero while computing them and after combine has
 374    completed.  This former test prevents propagating values based on
 375    previously set values, which can be incorrect if a variable is modified
 376    in a loop.  */
 377
 378 static int nonzero_sign_valid;
 379
 380 \f
 381 /* Record one modification to rtl structure
 382    to be undone by storing old_contents into *where.  */
 383
 384 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 385
 386 struct undo
 387 {
 388   struct undo *next;
 389   enum undo_kind kind;
 390   union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
 391   union { rtx *r; int *i; struct insn_link **l; } where;
 392 };
 393
 394 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 395    num_undo says how many are currently recorded.
 396
 397    other_insn is nonzero if we have modified some other insn in the process
 398    of working on subst_insn.  It must be verified too.  */
 399
 400 struct undobuf
 401 {
 402   struct undo *undos;
 403   struct undo *frees;
 404   rtx_insn *other_insn;
 405 };
 406
 407 static struct undobuf undobuf;
 408
 409 /* Number of times the pseudo being substituted for
 410    was found and replaced.  */
 411
 412 static int n_occurrences;
 413
 414 static rtx reg_nonzero_bits_for_combine (const_rtx, machine_mode, const_rtx,
 415                                          machine_mode,
 416                                          unsigned HOST_WIDE_INT,
 417                                          unsigned HOST_WIDE_INT *);
 418 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, machine_mode, const_rtx,
 419                                                 machine_mode,
 420                                                 unsigned int, unsigned int *);
 421 static void do_SUBST (rtx *, rtx);
 422 static void do_SUBST_INT (int *, int);
 423 static void init_reg_last (void);
 424 static void setup_incoming_promotions (rtx_insn *);
 425 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 426 static int cant_combine_insn_p (rtx_insn *);
 427 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
 428                           rtx_insn *, rtx_insn *, rtx *, rtx *);
 429 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *);
 430 static int contains_muldiv (rtx);
 431 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
 432                               int *, rtx_insn *);
 433 static void undo_all (void);
 434 static void undo_commit (void);
 435 static rtx *find_split_point (rtx *, rtx_insn *, bool);
 436 static rtx subst (rtx, rtx, rtx, int, int, int);
 437 static rtx combine_simplify_rtx (rtx, machine_mode, int, int);
 438 static rtx simplify_if_then_else (rtx);
 439 static rtx simplify_set (rtx);
 440 static rtx simplify_logical (rtx);
 441 static rtx expand_compound_operation (rtx);
 442 static const_rtx expand_field_assignment (const_rtx);
 443 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT,
 444                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 445 static rtx extract_left_shift (rtx, int);
 446 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 447                               unsigned HOST_WIDE_INT *);
 448 static rtx canon_reg_for_combine (rtx, rtx);
 449 static rtx force_to_mode (rtx, machine_mode,
 450                           unsigned HOST_WIDE_INT, int);
 451 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 452 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 453 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 454 static rtx make_field_assignment (rtx);
 455 static rtx apply_distributive_law (rtx);
 456 static rtx distribute_and_simplify_rtx (rtx, int);
 457 static rtx simplify_and_const_int_1 (machine_mode, rtx,
 458                                      unsigned HOST_WIDE_INT);
 459 static rtx simplify_and_const_int (rtx, machine_mode, rtx,
 460                                    unsigned HOST_WIDE_INT);
 461 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 462                             HOST_WIDE_INT, machine_mode, int *);
 463 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
 464 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
 465                                  int);
 466 static int recog_for_combine (rtx *, rtx_insn *, rtx *);
 467 static rtx gen_lowpart_for_combine (machine_mode, rtx);
 468 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
 469                                              rtx, rtx *);
 470 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 471 static void update_table_tick (rtx);
 472 static void record_value_for_reg (rtx, rtx_insn *, rtx);
 473 static void check_promoted_subreg (rtx_insn *, rtx);
 474 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 475 static void record_dead_and_set_regs (rtx_insn *);
 476 static int get_last_value_validate (rtx *, rtx_insn *, int, int);
 477 static rtx get_last_value (const_rtx);
 478 static int use_crosses_set_p (const_rtx, int);
 479 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 480 static int reg_dead_at_p (rtx, rtx_insn *);
 481 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
 482 static int reg_bitfield_target_p (rtx, rtx);
 483 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx);
 484 static void distribute_links (struct insn_link *);
 485 static void mark_used_regs_combine (rtx);
 486 static void record_promoted_value (rtx_insn *, rtx);
 487 static bool unmentioned_reg_p (rtx, rtx);
 488 static void record_truncated_values (rtx *, void *);
 489 static bool reg_truncated_to_mode (machine_mode, const_rtx);
 490 static rtx gen_lowpart_or_truncate (machine_mode, rtx);
 491 \f
 492
 493 /* It is not safe to use ordinary gen_lowpart in combine.
 494    See comments in gen_lowpart_for_combine.  */
 495 #undef RTL_HOOKS_GEN_LOWPART
 496 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 497
 498 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 499 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 500 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 501
 502 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 503 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 504
 505 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 506 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 507
 508 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 509 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 510
 511 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 512
 513 \f
 514 /* Convenience wrapper for the canonicalize_comparison target hook.
 515    Target hooks cannot use enum rtx_code.  */
 516 static inline void
 517 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 518                                 bool op0_preserve_value)
 519 {
 520   int code_int = (int)*code;
 521   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 522   *code = (enum rtx_code)code_int;
 523 }
 524
 525 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 526    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 527    This is a wrapper around split_insns which ensures that the
 528    reg_stat vector is made larger if the splitter creates a new
 529    register.  */
 530
 531 static rtx_insn *
 532 combine_split_insns (rtx pattern, rtx insn)
 533 {
 534   rtx_insn *ret;
 535   unsigned int nregs;
 536
 537   ret = safe_as_a <rtx_insn *> (split_insns (pattern, insn));
 538   nregs = max_reg_num ();
 539   if (nregs > reg_stat.length ())
 540     reg_stat.safe_grow_cleared (nregs);
 541   return ret;
 542 }
 543
 544 /* This is used by find_single_use to locate an rtx in LOC that
 545    contains exactly one use of DEST, which is typically either a REG
 546    or CC0.  It returns a pointer to the innermost rtx expression
 547    containing DEST.  Appearances of DEST that are being used to
 548    totally replace it are not counted.  */
 549
 550 static rtx *
 551 find_single_use_1 (rtx dest, rtx *loc)
 552 {
 553   rtx x = *loc;
 554   enum rtx_code code = GET_CODE (x);
 555   rtx *result = NULL;
 556   rtx *this_result;
 557   int i;
 558   const char *fmt;
 559
 560   switch (code)
 561     {
 562     case CONST:
 563     case LABEL_REF:
 564     case SYMBOL_REF:
 565     CASE_CONST_ANY:
 566     case CLOBBER:
 567       return 0;
 568
 569     case SET:
 570       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 571          of a REG that occupies all of the REG, the insn uses DEST if
 572          it is mentioned in the destination or the source.  Otherwise, we
 573          need just check the source.  */
 574       if (GET_CODE (SET_DEST (x)) != CC0
 575           && GET_CODE (SET_DEST (x)) != PC
 576           && !REG_P (SET_DEST (x))
 577           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 578                 && REG_P (SUBREG_REG (SET_DEST (x)))
 579                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 580                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 581                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 582                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 583         break;
 584
 585       return find_single_use_1 (dest, &SET_SRC (x));
 586
 587     case MEM:
 588     case SUBREG:
 589       return find_single_use_1 (dest, &XEXP (x, 0));
 590
 591     default:
 592       break;
 593     }
 594
 595   /* If it wasn't one of the common cases above, check each expression and
 596      vector of this code.  Look for a unique usage of DEST.  */
 597
 598   fmt = GET_RTX_FORMAT (code);
 599   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 600     {
 601       if (fmt[i] == 'e')
 602         {
 603           if (dest == XEXP (x, i)
 604               || (REG_P (dest) && REG_P (XEXP (x, i))
 605                   && REGNO (dest) == REGNO (XEXP (x, i))))
 606             this_result = loc;
 607           else
 608             this_result = find_single_use_1 (dest, &XEXP (x, i));
 609
 610           if (result == NULL)
 611             result = this_result;
 612           else if (this_result)
 613             /* Duplicate usage.  */
 614             return NULL;
 615         }
 616       else if (fmt[i] == 'E')
 617         {
 618           int j;
 619
 620           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 621             {
 622               if (XVECEXP (x, i, j) == dest
 623                   || (REG_P (dest)
 624                       && REG_P (XVECEXP (x, i, j))
 625                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 626                 this_result = loc;
 627               else
 628                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 629
 630               if (result == NULL)
 631                 result = this_result;
 632               else if (this_result)
 633                 return NULL;
 634             }
 635         }
 636     }
 637
 638   return result;
 639 }
 640
 641
 642 /* See if DEST, produced in INSN, is used only a single time in the
 643    sequel.  If so, return a pointer to the innermost rtx expression in which
 644    it is used.
 645
 646    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 647
 648    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 649    care about REG_DEAD notes or LOG_LINKS.
 650
 651    Otherwise, we find the single use by finding an insn that has a
 652    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 653    only referenced once in that insn, we know that it must be the first
 654    and last insn referencing DEST.  */
 655
 656 static rtx *
 657 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
 658 {
 659   basic_block bb;
 660   rtx_insn *next;
 661   rtx *result;
 662   struct insn_link *link;
 663
 664 #ifdef HAVE_cc0
 665   if (dest == cc0_rtx)
 666     {
 667       next = NEXT_INSN (insn);
 668       if (next == 0
 669           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 670         return 0;
 671
 672       result = find_single_use_1 (dest, &PATTERN (next));
 673       if (result && ploc)
 674         *ploc = next;
 675       return result;
 676     }
 677 #endif
 678
 679   if (!REG_P (dest))
 680     return 0;
 681
 682   bb = BLOCK_FOR_INSN (insn);
 683   for (next = NEXT_INSN (insn);
 684        next && BLOCK_FOR_INSN (next) == bb;
 685        next = NEXT_INSN (next))
 686     if (INSN_P (next) && dead_or_set_p (next, dest))
 687       {
 688         FOR_EACH_LOG_LINK (link, next)
 689           if (link->insn == insn)
 690             break;
 691
 692         if (link)
 693           {
 694             result = find_single_use_1 (dest, &PATTERN (next));
 695             if (ploc)
 696               *ploc = next;
 697             return result;
 698           }
 699       }
 700
 701   return 0;
 702 }
 703 \f
 704 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 705    insn.  The substitution can be undone by undo_all.  If INTO is already
 706    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 707    also call SUBST, we have to compute it before we put anything into
 708    the undo table.  */
 709
 710 static void
 711 do_SUBST (rtx *into, rtx newval)
 712 {
 713   struct undo *buf;
 714   rtx oldval = *into;
 715
 716   if (oldval == newval)
 717     return;
 718
 719   /* We'd like to catch as many invalid transformations here as
 720      possible.  Unfortunately, there are way too many mode changes
 721      that are perfectly valid, so we'd waste too much effort for
 722      little gain doing the checks here.  Focus on catching invalid
 723      transformations involving integer constants.  */
 724   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 725       && CONST_INT_P (newval))
 726     {
 727       /* Sanity check that we're replacing oldval with a CONST_INT
 728          that is a valid sign-extension for the original mode.  */
 729       gcc_assert (INTVAL (newval)
 730                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 731
 732       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 733          CONST_INT is not valid, because after the replacement, the
 734          original mode would be gone.  Unfortunately, we can't tell
 735          when do_SUBST is called to replace the operand thereof, so we
 736          perform this test on oldval instead, checking whether an
 737          invalid replacement took place before we got here.  */
 738       gcc_assert (!(GET_CODE (oldval) == SUBREG
 739                     && CONST_INT_P (SUBREG_REG (oldval))));
 740       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 741                     && CONST_INT_P (XEXP (oldval, 0))));
 742     }
 743
 744   if (undobuf.frees)
 745     buf = undobuf.frees, undobuf.frees = buf->next;
 746   else
 747     buf = XNEW (struct undo);
 748
 749   buf->kind = UNDO_RTX;
 750   buf->where.r = into;
 751   buf->old_contents.r = oldval;
 752   *into = newval;
 753
 754   buf->next = undobuf.undos, undobuf.undos = buf;
 755 }
 756
 757 #define SUBST(INTO, NEWVAL)     do_SUBST (&(INTO), (NEWVAL))
 758
 759 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 760    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 761    not safe.  */
 762
 763 static void
 764 do_SUBST_INT (int *into, int newval)
 765 {
 766   struct undo *buf;
 767   int oldval = *into;
 768
 769   if (oldval == newval)
 770     return;
 771
 772   if (undobuf.frees)
 773     buf = undobuf.frees, undobuf.frees = buf->next;
 774   else
 775     buf = XNEW (struct undo);
 776
 777   buf->kind = UNDO_INT;
 778   buf->where.i = into;
 779   buf->old_contents.i = oldval;
 780   *into = newval;
 781
 782   buf->next = undobuf.undos, undobuf.undos = buf;
 783 }
 784
 785 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT (&(INTO), (NEWVAL))
 786
 787 /* Similar to SUBST, but just substitute the mode.  This is used when
 788    changing the mode of a pseudo-register, so that any other
 789    references to the entry in the regno_reg_rtx array will change as
 790    well.  */
 791
 792 static void
 793 do_SUBST_MODE (rtx *into, machine_mode newval)
 794 {
 795   struct undo *buf;
 796   machine_mode oldval = GET_MODE (*into);
 797
 798   if (oldval == newval)
 799     return;
 800
 801   if (undobuf.frees)
 802     buf = undobuf.frees, undobuf.frees = buf->next;
 803   else
 804     buf = XNEW (struct undo);
 805
 806   buf->kind = UNDO_MODE;
 807   buf->where.r = into;
 808   buf->old_contents.m = oldval;
 809   adjust_reg_mode (*into, newval);
 810
 811   buf->next = undobuf.undos, undobuf.undos = buf;
 812 }
 813
 814 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE (&(INTO), (NEWVAL))
 815
 816 #ifndef HAVE_cc0
 817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 818
 819 static void
 820 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 821 {
 822   struct undo *buf;
 823   struct insn_link * oldval = *into;
 824
 825   if (oldval == newval)
 826     return;
 827
 828   if (undobuf.frees)
 829     buf = undobuf.frees, undobuf.frees = buf->next;
 830   else
 831     buf = XNEW (struct undo);
 832
 833   buf->kind = UNDO_LINKS;
 834   buf->where.l = into;
 835   buf->old_contents.l = oldval;
 836   *into = newval;
 837
 838   buf->next = undobuf.undos, undobuf.undos = buf;
 839 }
 840
 841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 842 #endif
 843 \f
 844 /* Subroutine of try_combine.  Determine whether the replacement patterns
 845    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 846    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 847    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 848    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 849    of all the instructions can be estimated and the replacements are more
 850    expensive than the original sequence.  */
 851
 852 static bool
 853 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
 854                        rtx newpat, rtx newi2pat, rtx newotherpat)
 855 {
 856   int i0_cost, i1_cost, i2_cost, i3_cost;
 857   int new_i2_cost, new_i3_cost;
 858   int old_cost, new_cost;
 859
 860   /* Lookup the original insn_rtx_costs.  */
 861   i2_cost = INSN_COST (i2);
 862   i3_cost = INSN_COST (i3);
 863
 864   if (i1)
 865     {
 866       i1_cost = INSN_COST (i1);
 867       if (i0)
 868         {
 869           i0_cost = INSN_COST (i0);
 870           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 871                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 872         }
 873       else
 874         {
 875           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 876                       ? i1_cost + i2_cost + i3_cost : 0);
 877           i0_cost = 0;
 878         }
 879     }
 880   else
 881     {
 882       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 883       i1_cost = i0_cost = 0;
 884     }
 885
 886   /* Calculate the replacement insn_rtx_costs.  */
 887   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 888   if (newi2pat)
 889     {
 890       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 891       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 892                  ? new_i2_cost + new_i3_cost : 0;
 893     }
 894   else
 895     {
 896       new_cost = new_i3_cost;
 897       new_i2_cost = 0;
 898     }
 899
 900   if (undobuf.other_insn)
 901     {
 902       int old_other_cost, new_other_cost;
 903
 904       old_other_cost = INSN_COST (undobuf.other_insn);
 905       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 906       if (old_other_cost > 0 && new_other_cost > 0)
 907         {
 908           old_cost += old_other_cost;
 909           new_cost += new_other_cost;
 910         }
 911       else
 912         old_cost = 0;
 913     }
 914
 915   /* Disallow this combination if both new_cost and old_cost are greater than
 916      zero, and new_cost is greater than old cost.  */
 917   if (old_cost > 0 && new_cost > old_cost)
 918     {
 919       if (dump_file)
 920         {
 921           if (i0)
 922             {
 923               fprintf (dump_file,
 924                        "rejecting combination of insns %d, %d, %d and %d\n",
 925                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 926                        INSN_UID (i3));
 927               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 928                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 929             }
 930           else if (i1)
 931             {
 932               fprintf (dump_file,
 933                        "rejecting combination of insns %d, %d and %d\n",
 934                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 935               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 936                        i1_cost, i2_cost, i3_cost, old_cost);
 937             }
 938           else
 939             {
 940               fprintf (dump_file,
 941                        "rejecting combination of insns %d and %d\n",
 942                        INSN_UID (i2), INSN_UID (i3));
 943               fprintf (dump_file, "original costs %d + %d = %d\n",
 944                        i2_cost, i3_cost, old_cost);
 945             }
 946
 947           if (newi2pat)
 948             {
 949               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 950                        new_i2_cost, new_i3_cost, new_cost);
 951             }
 952           else
 953             fprintf (dump_file, "replacement cost %d\n", new_cost);
 954         }
 955
 956       return false;
 957     }
 958
 959   /* Update the uid_insn_cost array with the replacement costs.  */
 960   INSN_COST (i2) = new_i2_cost;
 961   INSN_COST (i3) = new_i3_cost;
 962   if (i1)
 963     {
 964       INSN_COST (i1) = 0;
 965       if (i0)
 966         INSN_COST (i0) = 0;
 967     }
 968
 969   return true;
 970 }
 971
 972
 973 /* Delete any insns that copy a register to itself.  */
 974
 975 static void
 976 delete_noop_moves (void)
 977 {
 978   rtx_insn *insn, *next;
 979   basic_block bb;
 980
 981   FOR_EACH_BB_FN (bb, cfun)
 982     {
 983       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 984         {
 985           next = NEXT_INSN (insn);
 986           if (INSN_P (insn) && noop_move_p (insn))
 987             {
 988               if (dump_file)
 989                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 990
 991               delete_insn_and_edges (insn);
 992             }
 993         }
 994     }
 995 }
 996
 997 \f
 998 /* Fill in log links field for all insns.  */
 999
1000 static void
1001 create_log_links (void)
1002 {
1003   basic_block bb;
1004   rtx_insn **next_use;
1005   rtx_insn *insn;
1006   df_ref def, use;
1007
1008   next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1009
1010   /* Pass through each block from the end, recording the uses of each
1011      register and establishing log links when def is encountered.
1012      Note that we do not clear next_use array in order to save time,
1013      so we have to test whether the use is in the same basic block as def.
1014
1015      There are a few cases below when we do not consider the definition or
1016      usage -- these are taken from original flow.c did. Don't ask me why it is
1017      done this way; I don't know and if it works, I don't want to know.  */
1018
1019   FOR_EACH_BB_FN (bb, cfun)
1020     {
1021       FOR_BB_INSNS_REVERSE (bb, insn)
1022         {
1023           if (!NONDEBUG_INSN_P (insn))
1024             continue;
1025
1026           /* Log links are created only once.  */
1027           gcc_assert (!LOG_LINKS (insn));
1028
1029           FOR_EACH_INSN_DEF (def, insn)
1030             {
1031               int regno = DF_REF_REGNO (def);
1032               rtx_insn *use_insn;
1033
1034               if (!next_use[regno])
1035                 continue;
1036
1037               /* Do not consider if it is pre/post modification in MEM.  */
1038               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1039                 continue;
1040
1041               /* Do not make the log link for frame pointer.  */
1042               if ((regno == FRAME_POINTER_REGNUM
1043                    && (! reload_completed || frame_pointer_needed))
1044 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1045                   || (regno == HARD_FRAME_POINTER_REGNUM
1046                       && (! reload_completed || frame_pointer_needed))
1047 #endif
1048 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1049                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1050 #endif
1051                   )
1052                 continue;
1053
1054               use_insn = next_use[regno];
1055               if (BLOCK_FOR_INSN (use_insn) == bb)
1056                 {
1057                   /* flow.c claimed:
1058
1059                      We don't build a LOG_LINK for hard registers contained
1060                      in ASM_OPERANDs.  If these registers get replaced,
1061                      we might wind up changing the semantics of the insn,
1062                      even if reload can make what appear to be valid
1063                      assignments later.  */
1064                   if (regno >= FIRST_PSEUDO_REGISTER
1065                       || asm_noperands (PATTERN (use_insn)) < 0)
1066                     {
1067                       /* Don't add duplicate links between instructions.  */
1068                       struct insn_link *links;
1069                       FOR_EACH_LOG_LINK (links, use_insn)
1070                         if (insn == links->insn)
1071                           break;
1072
1073                       if (!links)
1074                         LOG_LINKS (use_insn)
1075                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1076                     }
1077                 }
1078               next_use[regno] = NULL;
1079             }
1080
1081           FOR_EACH_INSN_USE (use, insn)
1082             {
1083               int regno = DF_REF_REGNO (use);
1084
1085               /* Do not consider the usage of the stack pointer
1086                  by function call.  */
1087               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1088                 continue;
1089
1090               next_use[regno] = insn;
1091             }
1092         }
1093     }
1094
1095   free (next_use);
1096 }
1097
1098 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1099    true if we found a LOG_LINK that proves that A feeds B.  This only works
1100    if there are no instructions between A and B which could have a link
1101    depending on A, since in that case we would not record a link for B.
1102    We also check the implicit dependency created by a cc0 setter/user
1103    pair.  */
1104
1105 static bool
1106 insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1107 {
1108   struct insn_link *links;
1109   FOR_EACH_LOG_LINK (links, b)
1110     if (links->insn == a)
1111       return true;
1112 #ifdef HAVE_cc0
1113   if (sets_cc0_p (a))
1114     return true;
1115 #endif
1116   return false;
1117 }
1118 \f
1119 /* Main entry point for combiner.  F is the first insn of the function.
1120    NREGS is the first unused pseudo-reg number.
1121
1122    Return nonzero if the combiner has turned an indirect jump
1123    instruction into a direct jump.  */
1124 static int
1125 combine_instructions (rtx_insn *f, unsigned int nregs)
1126 {
1127   rtx_insn *insn, *next;
1128 #ifdef HAVE_cc0
1129   rtx_insn *prev;
1130 #endif
1131   struct insn_link *links, *nextlinks;
1132   rtx_insn *first;
1133   basic_block last_bb;
1134
1135   int new_direct_jump_p = 0;
1136
1137   for (first = f; first && !INSN_P (first); )
1138     first = NEXT_INSN (first);
1139   if (!first)
1140     return 0;
1141
1142   combine_attempts = 0;
1143   combine_merges = 0;
1144   combine_extras = 0;
1145   combine_successes = 0;
1146
1147   rtl_hooks = combine_rtl_hooks;
1148
1149   reg_stat.safe_grow_cleared (nregs);
1150
1151   init_recog_no_volatile ();
1152
1153   /* Allocate array for insn info.  */
1154   max_uid_known = get_max_uid ();
1155   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1156   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1157   gcc_obstack_init (&insn_link_obstack);
1158
1159   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1160
1161   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1162      problems when, for example, we have j <<= 1 in a loop.  */
1163
1164   nonzero_sign_valid = 0;
1165   label_tick = label_tick_ebb_start = 1;
1166
1167   /* Scan all SETs and see if we can deduce anything about what
1168      bits are known to be zero for some registers and how many copies
1169      of the sign bit are known to exist for those registers.
1170
1171      Also set any known values so that we can use it while searching
1172      for what bits are known to be set.  */
1173
1174   setup_incoming_promotions (first);
1175   /* Allow the entry block and the first block to fall into the same EBB.
1176      Conceptually the incoming promotions are assigned to the entry block.  */
1177   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1178
1179   create_log_links ();
1180   FOR_EACH_BB_FN (this_basic_block, cfun)
1181     {
1182       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1183       last_call_luid = 0;
1184       mem_last_set = -1;
1185
1186       label_tick++;
1187       if (!single_pred_p (this_basic_block)
1188           || single_pred (this_basic_block) != last_bb)
1189         label_tick_ebb_start = label_tick;
1190       last_bb = this_basic_block;
1191
1192       FOR_BB_INSNS (this_basic_block, insn)
1193         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1194           {
1195 #ifdef AUTO_INC_DEC
1196             rtx links;
1197 #endif
1198
1199             subst_low_luid = DF_INSN_LUID (insn);
1200             subst_insn = insn;
1201
1202             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1203                          insn);
1204             record_dead_and_set_regs (insn);
1205
1206 #ifdef AUTO_INC_DEC
1207             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1208               if (REG_NOTE_KIND (links) == REG_INC)
1209                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1210                                                   insn);
1211 #endif
1212
1213             /* Record the current insn_rtx_cost of this instruction.  */
1214             if (NONJUMP_INSN_P (insn))
1215               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1216                                                 optimize_this_for_speed_p);
1217             if (dump_file)
1218               fprintf (dump_file, "insn_cost %d: %d\n",
1219                        INSN_UID (insn), INSN_COST (insn));
1220           }
1221     }
1222
1223   nonzero_sign_valid = 1;
1224
1225   /* Now scan all the insns in forward order.  */
1226   label_tick = label_tick_ebb_start = 1;
1227   init_reg_last ();
1228   setup_incoming_promotions (first);
1229   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1230   int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS);
1231
1232   FOR_EACH_BB_FN (this_basic_block, cfun)
1233     {
1234       rtx_insn *last_combined_insn = NULL;
1235       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1236       last_call_luid = 0;
1237       mem_last_set = -1;
1238
1239       label_tick++;
1240       if (!single_pred_p (this_basic_block)
1241           || single_pred (this_basic_block) != last_bb)
1242         label_tick_ebb_start = label_tick;
1243       last_bb = this_basic_block;
1244
1245       rtl_profile_for_bb (this_basic_block);
1246       for (insn = BB_HEAD (this_basic_block);
1247            insn != NEXT_INSN (BB_END (this_basic_block));
1248            insn = next ? next : NEXT_INSN (insn))
1249         {
1250           next = 0;
1251           if (!NONDEBUG_INSN_P (insn))
1252             continue;
1253
1254           while (last_combined_insn
1255                  && last_combined_insn->deleted ())
1256             last_combined_insn = PREV_INSN (last_combined_insn);
1257           if (last_combined_insn == NULL_RTX
1258               || BARRIER_P (last_combined_insn)
1259               || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1260               || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1261             last_combined_insn = insn;
1262
1263           /* See if we know about function return values before this
1264              insn based upon SUBREG flags.  */
1265           check_promoted_subreg (insn, PATTERN (insn));
1266
1267           /* See if we can find hardregs and subreg of pseudos in
1268              narrower modes.  This could help turning TRUNCATEs
1269              into SUBREGs.  */
1270           note_uses (&PATTERN (insn), record_truncated_values, NULL);
1271
1272           /* Try this insn with each insn it links back to.  */
1273
1274           FOR_EACH_LOG_LINK (links, insn)
1275             if ((next = try_combine (insn, links->insn, NULL,
1276                                      NULL, &new_direct_jump_p,
1277                                      last_combined_insn)) != 0)
1278               {
1279                 statistics_counter_event (cfun, "two-insn combine", 1);
1280                 goto retry;
1281               }
1282
1283           /* Try each sequence of three linked insns ending with this one.  */
1284
1285           if (max_combine >= 3)
1286             FOR_EACH_LOG_LINK (links, insn)
1287               {
1288                 rtx_insn *link = links->insn;
1289
1290                 /* If the linked insn has been replaced by a note, then there
1291                    is no point in pursuing this chain any further.  */
1292                 if (NOTE_P (link))
1293                   continue;
1294
1295                 FOR_EACH_LOG_LINK (nextlinks, link)
1296                   if ((next = try_combine (insn, link, nextlinks->insn,
1297                                            NULL, &new_direct_jump_p,
1298                                            last_combined_insn)) != 0)
1299                     {
1300                       statistics_counter_event (cfun, "three-insn combine", 1);
1301                       goto retry;
1302                     }
1303               }
1304
1305 #ifdef HAVE_cc0
1306           /* Try to combine a jump insn that uses CC0
1307              with a preceding insn that sets CC0, and maybe with its
1308              logical predecessor as well.
1309              This is how we make decrement-and-branch insns.
1310              We need this special code because data flow connections
1311              via CC0 do not get entered in LOG_LINKS.  */
1312
1313           if (JUMP_P (insn)
1314               && (prev = prev_nonnote_insn (insn)) != 0
1315               && NONJUMP_INSN_P (prev)
1316               && sets_cc0_p (PATTERN (prev)))
1317             {
1318               if ((next = try_combine (insn, prev, NULL, NULL,
1319                                        &new_direct_jump_p,
1320                                        last_combined_insn)) != 0)
1321                 goto retry;
1322
1323               FOR_EACH_LOG_LINK (nextlinks, prev)
1324                   if ((next = try_combine (insn, prev, nextlinks->insn,
1325                                            NULL, &new_direct_jump_p,
1326                                            last_combined_insn)) != 0)
1327                     goto retry;
1328             }
1329
1330           /* Do the same for an insn that explicitly references CC0.  */
1331           if (NONJUMP_INSN_P (insn)
1332               && (prev = prev_nonnote_insn (insn)) != 0
1333               && NONJUMP_INSN_P (prev)
1334               && sets_cc0_p (PATTERN (prev))
1335               && GET_CODE (PATTERN (insn)) == SET
1336               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1337             {
1338               if ((next = try_combine (insn, prev, NULL, NULL,
1339                                        &new_direct_jump_p,
1340                                        last_combined_insn)) != 0)
1341                 goto retry;
1342
1343               FOR_EACH_LOG_LINK (nextlinks, prev)
1344                   if ((next = try_combine (insn, prev, nextlinks->insn,
1345                                            NULL, &new_direct_jump_p,
1346                                            last_combined_insn)) != 0)
1347                     goto retry;
1348             }
1349
1350           /* Finally, see if any of the insns that this insn links to
1351              explicitly references CC0.  If so, try this insn, that insn,
1352              and its predecessor if it sets CC0.  */
1353           FOR_EACH_LOG_LINK (links, insn)
1354               if (NONJUMP_INSN_P (links->insn)
1355                   && GET_CODE (PATTERN (links->insn)) == SET
1356                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1357                   && (prev = prev_nonnote_insn (links->insn)) != 0
1358                   && NONJUMP_INSN_P (prev)
1359                   && sets_cc0_p (PATTERN (prev))
1360                   && (next = try_combine (insn, links->insn,
1361                                           prev, NULL, &new_direct_jump_p,
1362                                           last_combined_insn)) != 0)
1363                 goto retry;
1364 #endif
1365
1366           /* Try combining an insn with two different insns whose results it
1367              uses.  */
1368           if (max_combine >= 3)
1369             FOR_EACH_LOG_LINK (links, insn)
1370               for (nextlinks = links->next; nextlinks;
1371                    nextlinks = nextlinks->next)
1372                 if ((next = try_combine (insn, links->insn,
1373                                          nextlinks->insn, NULL,
1374                                          &new_direct_jump_p,
1375                                          last_combined_insn)) != 0)
1376
1377                   {
1378                     statistics_counter_event (cfun, "three-insn combine", 1);
1379                     goto retry;
1380                   }
1381
1382           /* Try four-instruction combinations.  */
1383           if (max_combine >= 4)
1384             FOR_EACH_LOG_LINK (links, insn)
1385               {
1386                 struct insn_link *next1;
1387                 rtx_insn *link = links->insn;
1388
1389                 /* If the linked insn has been replaced by a note, then there
1390                    is no point in pursuing this chain any further.  */
1391                 if (NOTE_P (link))
1392                   continue;
1393
1394                 FOR_EACH_LOG_LINK (next1, link)
1395                   {
1396                     rtx_insn *link1 = next1->insn;
1397                     if (NOTE_P (link1))
1398                       continue;
1399                     /* I0 -> I1 -> I2 -> I3.  */
1400                     FOR_EACH_LOG_LINK (nextlinks, link1)
1401                       if ((next = try_combine (insn, link, link1,
1402                                                nextlinks->insn,
1403                                                &new_direct_jump_p,
1404                                                last_combined_insn)) != 0)
1405                         {
1406                           statistics_counter_event (cfun, "four-insn combine", 1);
1407                           goto retry;
1408                         }
1409                     /* I0, I1 -> I2, I2 -> I3.  */
1410                     for (nextlinks = next1->next; nextlinks;
1411                          nextlinks = nextlinks->next)
1412                       if ((next = try_combine (insn, link, link1,
1413                                                nextlinks->insn,
1414                                                &new_direct_jump_p,
1415                                                last_combined_insn)) != 0)
1416                         {
1417                           statistics_counter_event (cfun, "four-insn combine", 1);
1418                           goto retry;
1419                         }
1420                   }
1421
1422                 for (next1 = links->next; next1; next1 = next1->next)
1423                   {
1424                     rtx_insn *link1 = next1->insn;
1425                     if (NOTE_P (link1))
1426                       continue;
1427                     /* I0 -> I2; I1, I2 -> I3.  */
1428                     FOR_EACH_LOG_LINK (nextlinks, link)
1429                       if ((next = try_combine (insn, link, link1,
1430                                                nextlinks->insn,
1431                                                &new_direct_jump_p,
1432                                                last_combined_insn)) != 0)
1433                         {
1434                           statistics_counter_event (cfun, "four-insn combine", 1);
1435                           goto retry;
1436                         }
1437                     /* I0 -> I1; I1, I2 -> I3.  */
1438                     FOR_EACH_LOG_LINK (nextlinks, link1)
1439                       if ((next = try_combine (insn, link, link1,
1440                                                nextlinks->insn,
1441                                                &new_direct_jump_p,
1442                                                last_combined_insn)) != 0)
1443                         {
1444                           statistics_counter_event (cfun, "four-insn combine", 1);
1445                           goto retry;
1446                         }
1447                   }
1448               }
1449
1450           /* Try this insn with each REG_EQUAL note it links back to.  */
1451           FOR_EACH_LOG_LINK (links, insn)
1452             {
1453               rtx set, note;
1454               rtx_insn *temp = links->insn;
1455               if ((set = single_set (temp)) != 0
1456                   && (note = find_reg_equal_equiv_note (temp)) != 0
1457                   && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1458                   /* Avoid using a register that may already been marked
1459                      dead by an earlier instruction.  */
1460                   && ! unmentioned_reg_p (note, SET_SRC (set))
1461                   && (GET_MODE (note) == VOIDmode
1462                       ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1463                       : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1464                 {
1465                   /* Temporarily replace the set's source with the
1466                      contents of the REG_EQUAL note.  The insn will
1467                      be deleted or recognized by try_combine.  */
1468                   rtx orig = SET_SRC (set);
1469                   SET_SRC (set) = note;
1470                   i2mod = temp;
1471                   i2mod_old_rhs = copy_rtx (orig);
1472                   i2mod_new_rhs = copy_rtx (note);
1473                   next = try_combine (insn, i2mod, NULL, NULL,
1474                                       &new_direct_jump_p,
1475                                       last_combined_insn);
1476                   i2mod = NULL;
1477                   if (next)
1478                     {
1479                       statistics_counter_event (cfun, "insn-with-note combine", 1);
1480                       goto retry;
1481                     }
1482                   SET_SRC (set) = orig;
1483                 }
1484             }
1485
1486           if (!NOTE_P (insn))
1487             record_dead_and_set_regs (insn);
1488
1489 retry:
1490           ;
1491         }
1492     }
1493
1494   default_rtl_profile ();
1495   clear_bb_flags ();
1496   new_direct_jump_p |= purge_all_dead_edges ();
1497   delete_noop_moves ();
1498
1499   /* Clean up.  */
1500   obstack_free (&insn_link_obstack, NULL);
1501   free (uid_log_links);
1502   free (uid_insn_cost);
1503   reg_stat.release ();
1504
1505   {
1506     struct undo *undo, *next;
1507     for (undo = undobuf.frees; undo; undo = next)
1508       {
1509         next = undo->next;
1510         free (undo);
1511       }
1512     undobuf.frees = 0;
1513   }
1514
1515   total_attempts += combine_attempts;
1516   total_merges += combine_merges;
1517   total_extras += combine_extras;
1518   total_successes += combine_successes;
1519
1520   nonzero_sign_valid = 0;
1521   rtl_hooks = general_rtl_hooks;
1522
1523   /* Make recognizer allow volatile MEMs again.  */
1524   init_recog ();
1525
1526   return new_direct_jump_p;
1527 }
1528
1529 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1530
1531 static void
1532 init_reg_last (void)
1533 {
1534   unsigned int i;
1535   reg_stat_type *p;
1536
1537   FOR_EACH_VEC_ELT (reg_stat, i, p)
1538     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1539 }
1540 \f
1541 /* Set up any promoted values for incoming argument registers.  */
1542
1543 static void
1544 setup_incoming_promotions (rtx_insn *first)
1545 {
1546   tree arg;
1547   bool strictly_local = false;
1548
1549   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1550        arg = DECL_CHAIN (arg))
1551     {
1552       rtx x, reg = DECL_INCOMING_RTL (arg);
1553       int uns1, uns3;
1554       machine_mode mode1, mode2, mode3, mode4;
1555
1556       /* Only continue if the incoming argument is in a register.  */
1557       if (!REG_P (reg))
1558         continue;
1559
1560       /* Determine, if possible, whether all call sites of the current
1561          function lie within the current compilation unit.  (This does
1562          take into account the exporting of a function via taking its
1563          address, and so forth.)  */
1564       strictly_local = cgraph_node::local_info (current_function_decl)->local;
1565
1566       /* The mode and signedness of the argument before any promotions happen
1567          (equal to the mode of the pseudo holding it at that stage).  */
1568       mode1 = TYPE_MODE (TREE_TYPE (arg));
1569       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1570
1571       /* The mode and signedness of the argument after any source language and
1572          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1573       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1574       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1575
1576       /* The mode and signedness of the argument as it is actually passed,
1577          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1578       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1579                                      TREE_TYPE (cfun->decl), 0);
1580
1581       /* The mode of the register in which the argument is being passed.  */
1582       mode4 = GET_MODE (reg);
1583
1584       /* Eliminate sign extensions in the callee when:
1585          (a) A mode promotion has occurred;  */
1586       if (mode1 == mode3)
1587         continue;
1588       /* (b) The mode of the register is the same as the mode of
1589              the argument as it is passed; */
1590       if (mode3 != mode4)
1591         continue;
1592       /* (c) There's no language level extension;  */
1593       if (mode1 == mode2)
1594         ;
1595       /* (c.1) All callers are from the current compilation unit.  If that's
1596          the case we don't have to rely on an ABI, we only have to know
1597          what we're generating right now, and we know that we will do the
1598          mode1 to mode2 promotion with the given sign.  */
1599       else if (!strictly_local)
1600         continue;
1601       /* (c.2) The combination of the two promotions is useful.  This is
1602          true when the signs match, or if the first promotion is unsigned.
1603          In the later case, (sign_extend (zero_extend x)) is the same as
1604          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1605       else if (uns1)
1606         uns3 = true;
1607       else if (uns3)
1608         continue;
1609
1610       /* Record that the value was promoted from mode1 to mode3,
1611          so that any sign extension at the head of the current
1612          function may be eliminated.  */
1613       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1614       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1615       record_value_for_reg (reg, first, x);
1616     }
1617 }
1618
1619 /* Called via note_stores.  If X is a pseudo that is narrower than
1620    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1621
1622    If we are setting only a portion of X and we can't figure out what
1623    portion, assume all bits will be used since we don't know what will
1624    be happening.
1625
1626    Similarly, set how many bits of X are known to be copies of the sign bit
1627    at all locations in the function.  This is the smallest number implied
1628    by any set of X.  */
1629
1630 static void
1631 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1632 {
1633   rtx_insn *insn = (rtx_insn *) data;
1634   unsigned int num;
1635
1636   if (REG_P (x)
1637       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1638       /* If this register is undefined at the start of the file, we can't
1639          say what its contents were.  */
1640       && ! REGNO_REG_SET_P
1641            (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1642       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1643     {
1644       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1645
1646       if (set == 0 || GET_CODE (set) == CLOBBER)
1647         {
1648           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1649           rsp->sign_bit_copies = 1;
1650           return;
1651         }
1652
1653       /* If this register is being initialized using itself, and the
1654          register is uninitialized in this basic block, and there are
1655          no LOG_LINKS which set the register, then part of the
1656          register is uninitialized.  In that case we can't assume
1657          anything about the number of nonzero bits.
1658
1659          ??? We could do better if we checked this in
1660          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1661          could avoid making assumptions about the insn which initially
1662          sets the register, while still using the information in other
1663          insns.  We would have to be careful to check every insn
1664          involved in the combination.  */
1665
1666       if (insn
1667           && reg_referenced_p (x, PATTERN (insn))
1668           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1669                                REGNO (x)))
1670         {
1671           struct insn_link *link;
1672
1673           FOR_EACH_LOG_LINK (link, insn)
1674             if (dead_or_set_p (link->insn, x))
1675               break;
1676           if (!link)
1677             {
1678               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1679               rsp->sign_bit_copies = 1;
1680               return;
1681             }
1682         }
1683
1684       /* If this is a complex assignment, see if we can convert it into a
1685          simple assignment.  */
1686       set = expand_field_assignment (set);
1687
1688       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1689          set what we know about X.  */
1690
1691       if (SET_DEST (set) == x
1692           || (paradoxical_subreg_p (SET_DEST (set))
1693               && SUBREG_REG (SET_DEST (set)) == x))
1694         {
1695           rtx src = SET_SRC (set);
1696
1697 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1698           /* If X is narrower than a word and SRC is a non-negative
1699              constant that would appear negative in the mode of X,
1700              sign-extend it for use in reg_stat[].nonzero_bits because some
1701              machines (maybe most) will actually do the sign-extension
1702              and this is the conservative approach.
1703
1704              ??? For 2.5, try to tighten up the MD files in this regard
1705              instead of this kludge.  */
1706
1707           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1708               && CONST_INT_P (src)
1709               && INTVAL (src) > 0
1710               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1711             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1712 #endif
1713
1714           /* Don't call nonzero_bits if it cannot change anything.  */
1715           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1716             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1717           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1718           if (rsp->sign_bit_copies == 0
1719               || rsp->sign_bit_copies > num)
1720             rsp->sign_bit_copies = num;
1721         }
1722       else
1723         {
1724           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1725           rsp->sign_bit_copies = 1;
1726         }
1727     }
1728 }
1729 \f
1730 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1731    optionally insns that were previously combined into I3 or that will be
1732    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1733    INSN, SUCC, SUCC2, I3.
1734
1735    Return 0 if the combination is not allowed for any reason.
1736
1737    If the combination is allowed, *PDEST will be set to the single
1738    destination of INSN and *PSRC to the single source, and this function
1739    will return 1.  */
1740
1741 static int
1742 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1743                rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1744                rtx *pdest, rtx *psrc)
1745 {
1746   int i;
1747   const_rtx set = 0;
1748   rtx src, dest;
1749   rtx_insn *p;
1750 #ifdef AUTO_INC_DEC
1751   rtx link;
1752 #endif
1753   bool all_adjacent = true;
1754   int (*is_volatile_p) (const_rtx);
1755
1756   if (succ)
1757     {
1758       if (succ2)
1759         {
1760           if (next_active_insn (succ2) != i3)
1761             all_adjacent = false;
1762           if (next_active_insn (succ) != succ2)
1763             all_adjacent = false;
1764         }
1765       else if (next_active_insn (succ) != i3)
1766         all_adjacent = false;
1767       if (next_active_insn (insn) != succ)
1768         all_adjacent = false;
1769     }
1770   else if (next_active_insn (insn) != i3)
1771     all_adjacent = false;
1772
1773   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1774      or a PARALLEL consisting of such a SET and CLOBBERs.
1775
1776      If INSN has CLOBBER parallel parts, ignore them for our processing.
1777      By definition, these happen during the execution of the insn.  When it
1778      is merged with another insn, all bets are off.  If they are, in fact,
1779      needed and aren't also supplied in I3, they may be added by
1780      recog_for_combine.  Otherwise, it won't match.
1781
1782      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1783      note.
1784
1785      Get the source and destination of INSN.  If more than one, can't
1786      combine.  */
1787
1788   if (GET_CODE (PATTERN (insn)) == SET)
1789     set = PATTERN (insn);
1790   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1791            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1792     {
1793       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1794         {
1795           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1796
1797           switch (GET_CODE (elt))
1798             {
1799             /* This is important to combine floating point insns
1800                for the SH4 port.  */
1801             case USE:
1802               /* Combining an isolated USE doesn't make sense.
1803                  We depend here on combinable_i3pat to reject them.  */
1804               /* The code below this loop only verifies that the inputs of
1805                  the SET in INSN do not change.  We call reg_set_between_p
1806                  to verify that the REG in the USE does not change between
1807                  I3 and INSN.
1808                  If the USE in INSN was for a pseudo register, the matching
1809                  insn pattern will likely match any register; combining this
1810                  with any other USE would only be safe if we knew that the
1811                  used registers have identical values, or if there was
1812                  something to tell them apart, e.g. different modes.  For
1813                  now, we forgo such complicated tests and simply disallow
1814                  combining of USES of pseudo registers with any other USE.  */
1815               if (REG_P (XEXP (elt, 0))
1816                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1817                 {
1818                   rtx i3pat = PATTERN (i3);
1819                   int i = XVECLEN (i3pat, 0) - 1;
1820                   unsigned int regno = REGNO (XEXP (elt, 0));
1821
1822                   do
1823                     {
1824                       rtx i3elt = XVECEXP (i3pat, 0, i);
1825
1826                       if (GET_CODE (i3elt) == USE
1827                           && REG_P (XEXP (i3elt, 0))
1828                           && (REGNO (XEXP (i3elt, 0)) == regno
1829                               ? reg_set_between_p (XEXP (elt, 0),
1830                                                    PREV_INSN (insn), i3)
1831                               : regno >= FIRST_PSEUDO_REGISTER))
1832                         return 0;
1833                     }
1834                   while (--i >= 0);
1835                 }
1836               break;
1837
1838               /* We can ignore CLOBBERs.  */
1839             case CLOBBER:
1840               break;
1841
1842             case SET:
1843               /* Ignore SETs whose result isn't used but not those that
1844                  have side-effects.  */
1845               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1846                   && insn_nothrow_p (insn)
1847                   && !side_effects_p (elt))
1848                 break;
1849
1850               /* If we have already found a SET, this is a second one and
1851                  so we cannot combine with this insn.  */
1852               if (set)
1853                 return 0;
1854
1855               set = elt;
1856               break;
1857
1858             default:
1859               /* Anything else means we can't combine.  */
1860               return 0;
1861             }
1862         }
1863
1864       if (set == 0
1865           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1866              so don't do anything with it.  */
1867           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1868         return 0;
1869     }
1870   else
1871     return 0;
1872
1873   if (set == 0)
1874     return 0;
1875
1876   /* The simplification in expand_field_assignment may call back to
1877      get_last_value, so set safe guard here.  */
1878   subst_low_luid = DF_INSN_LUID (insn);
1879
1880   set = expand_field_assignment (set);
1881   src = SET_SRC (set), dest = SET_DEST (set);
1882
1883   /* Don't eliminate a store in the stack pointer.  */
1884   if (dest == stack_pointer_rtx
1885       /* Don't combine with an insn that sets a register to itself if it has
1886          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1887       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1888       /* Can't merge an ASM_OPERANDS.  */
1889       || GET_CODE (src) == ASM_OPERANDS
1890       /* Can't merge a function call.  */
1891       || GET_CODE (src) == CALL
1892       /* Don't eliminate a function call argument.  */
1893       || (CALL_P (i3)
1894           && (find_reg_fusage (i3, USE, dest)
1895               || (REG_P (dest)
1896                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1897                   && global_regs[REGNO (dest)])))
1898       /* Don't substitute into an incremented register.  */
1899       || FIND_REG_INC_NOTE (i3, dest)
1900       || (succ && FIND_REG_INC_NOTE (succ, dest))
1901       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1902       /* Don't substitute into a non-local goto, this confuses CFG.  */
1903       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1904       /* Make sure that DEST is not used after SUCC but before I3.  */
1905       || (!all_adjacent
1906           && ((succ2
1907                && (reg_used_between_p (dest, succ2, i3)
1908                    || reg_used_between_p (dest, succ, succ2)))
1909               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1910       /* Make sure that the value that is to be substituted for the register
1911          does not use any registers whose values alter in between.  However,
1912          If the insns are adjacent, a use can't cross a set even though we
1913          think it might (this can happen for a sequence of insns each setting
1914          the same destination; last_set of that register might point to
1915          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1916          equivalent to the memory so the substitution is valid even if there
1917          are intervening stores.  Also, don't move a volatile asm or
1918          UNSPEC_VOLATILE across any other insns.  */
1919       || (! all_adjacent
1920           && (((!MEM_P (src)
1921                 || ! find_reg_note (insn, REG_EQUIV, src))
1922                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1923               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1924               || GET_CODE (src) == UNSPEC_VOLATILE))
1925       /* Don't combine across a CALL_INSN, because that would possibly
1926          change whether the life span of some REGs crosses calls or not,
1927          and it is a pain to update that information.
1928          Exception: if source is a constant, moving it later can't hurt.
1929          Accept that as a special case.  */
1930       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1931     return 0;
1932
1933   /* DEST must either be a REG or CC0.  */
1934   if (REG_P (dest))
1935     {
1936       /* If register alignment is being enforced for multi-word items in all
1937          cases except for parameters, it is possible to have a register copy
1938          insn referencing a hard register that is not allowed to contain the
1939          mode being copied and which would not be valid as an operand of most
1940          insns.  Eliminate this problem by not combining with such an insn.
1941
1942          Also, on some machines we don't want to extend the life of a hard
1943          register.  */
1944
1945       if (REG_P (src)
1946           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1947                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1948               /* Don't extend the life of a hard register unless it is
1949                  user variable (if we have few registers) or it can't
1950                  fit into the desired register (meaning something special
1951                  is going on).
1952                  Also avoid substituting a return register into I3, because
1953                  reload can't handle a conflict with constraints of other
1954                  inputs.  */
1955               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1956                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1957         return 0;
1958     }
1959   else if (GET_CODE (dest) != CC0)
1960     return 0;
1961
1962
1963   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1964     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1965       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1966         {
1967           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1968
1969           /* If the clobber represents an earlyclobber operand, we must not
1970              substitute an expression containing the clobbered register.
1971              As we do not analyze the constraint strings here, we have to
1972              make the conservative assumption.  However, if the register is
1973              a fixed hard reg, the clobber cannot represent any operand;
1974              we leave it up to the machine description to either accept or
1975              reject use-and-clobber patterns.  */
1976           if (!REG_P (reg)
1977               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1978               || !fixed_regs[REGNO (reg)])
1979             if (reg_overlap_mentioned_p (reg, src))
1980               return 0;
1981         }
1982
1983   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1984      or not), reject, unless nothing volatile comes between it and I3 */
1985
1986   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1987     {
1988       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1989       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1990         return 0;
1991       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1992         return 0;
1993       /* We'll check insns between INSN and I3 below.  */
1994     }
1995
1996   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1997      to be an explicit register variable, and was chosen for a reason.  */
1998
1999   if (GET_CODE (src) == ASM_OPERANDS
2000       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2001     return 0;
2002
2003   /* If INSN contains volatile references (specifically volatile MEMs),
2004      we cannot combine across any other volatile references.
2005      Even if INSN doesn't contain volatile references, any intervening
2006      volatile insn might affect machine state.  */
2007
2008   is_volatile_p = volatile_refs_p (PATTERN (insn))
2009     ? volatile_refs_p
2010     : volatile_insn_p;
2011
2012   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2013     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2014       return 0;
2015
2016   /* If INSN contains an autoincrement or autodecrement, make sure that
2017      register is not used between there and I3, and not already used in
2018      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
2019      Also insist that I3 not be a jump; if it were one
2020      and the incremented register were spilled, we would lose.  */
2021
2022 #ifdef AUTO_INC_DEC
2023   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2024     if (REG_NOTE_KIND (link) == REG_INC
2025         && (JUMP_P (i3)
2026             || reg_used_between_p (XEXP (link, 0), insn, i3)
2027             || (pred != NULL_RTX
2028                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2029             || (pred2 != NULL_RTX
2030                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2031             || (succ != NULL_RTX
2032                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2033             || (succ2 != NULL_RTX
2034                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2035             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2036       return 0;
2037 #endif
2038
2039 #ifdef HAVE_cc0
2040   /* Don't combine an insn that follows a CC0-setting insn.
2041      An insn that uses CC0 must not be separated from the one that sets it.
2042      We do, however, allow I2 to follow a CC0-setting insn if that insn
2043      is passed as I1; in that case it will be deleted also.
2044      We also allow combining in this case if all the insns are adjacent
2045      because that would leave the two CC0 insns adjacent as well.
2046      It would be more logical to test whether CC0 occurs inside I1 or I2,
2047      but that would be much slower, and this ought to be equivalent.  */
2048
2049   p = prev_nonnote_insn (insn);
2050   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2051       && ! all_adjacent)
2052     return 0;
2053 #endif
2054
2055   /* If we get here, we have passed all the tests and the combination is
2056      to be allowed.  */
2057
2058   *pdest = dest;
2059   *psrc = src;
2060
2061   return 1;
2062 }
2063 \f
2064 /* LOC is the location within I3 that contains its pattern or the component
2065    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2066
2067    One problem is if I3 modifies its output, as opposed to replacing it
2068    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2069    doing so would produce an insn that is not equivalent to the original insns.
2070
2071    Consider:
2072
2073          (set (reg:DI 101) (reg:DI 100))
2074          (set (subreg:SI (reg:DI 101) 0) <foo>)
2075
2076    This is NOT equivalent to:
2077
2078          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2079                     (set (reg:DI 101) (reg:DI 100))])
2080
2081    Not only does this modify 100 (in which case it might still be valid
2082    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2083
2084    We can also run into a problem if I2 sets a register that I1
2085    uses and I1 gets directly substituted into I3 (not via I2).  In that
2086    case, we would be getting the wrong value of I2DEST into I3, so we
2087    must reject the combination.  This case occurs when I2 and I1 both
2088    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2089    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2090    of a SET must prevent combination from occurring.  The same situation
2091    can occur for I0, in which case I0_NOT_IN_SRC is set.
2092
2093    Before doing the above check, we first try to expand a field assignment
2094    into a set of logical operations.
2095
2096    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2097    we place a register that is both set and used within I3.  If more than one
2098    such register is detected, we fail.
2099
2100    Return 1 if the combination is valid, zero otherwise.  */
2101
2102 static int
2103 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2104                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2105 {
2106   rtx x = *loc;
2107
2108   if (GET_CODE (x) == SET)
2109     {
2110       rtx set = x ;
2111       rtx dest = SET_DEST (set);
2112       rtx src = SET_SRC (set);
2113       rtx inner_dest = dest;
2114       rtx subdest;
2115
2116       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2117              || GET_CODE (inner_dest) == SUBREG
2118              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2119         inner_dest = XEXP (inner_dest, 0);
2120
2121       /* Check for the case where I3 modifies its output, as discussed
2122          above.  We don't want to prevent pseudos from being combined
2123          into the address of a MEM, so only prevent the combination if
2124          i1 or i2 set the same MEM.  */
2125       if ((inner_dest != dest &&
2126            (!MEM_P (inner_dest)
2127             || rtx_equal_p (i2dest, inner_dest)
2128             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2129             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2130            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2131                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2132                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2133
2134           /* This is the same test done in can_combine_p except we can't test
2135              all_adjacent; we don't have to, since this instruction will stay
2136              in place, thus we are not considering increasing the lifetime of
2137              INNER_DEST.
2138
2139              Also, if this insn sets a function argument, combining it with
2140              something that might need a spill could clobber a previous
2141              function argument; the all_adjacent test in can_combine_p also
2142              checks this; here, we do a more specific test for this case.  */
2143
2144           || (REG_P (inner_dest)
2145               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2146               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2147                                         GET_MODE (inner_dest))))
2148           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2149           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2150         return 0;
2151
2152       /* If DEST is used in I3, it is being killed in this insn, so
2153          record that for later.  We have to consider paradoxical
2154          subregs here, since they kill the whole register, but we
2155          ignore partial subregs, STRICT_LOW_PART, etc.
2156          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2157          STACK_POINTER_REGNUM, since these are always considered to be
2158          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2159       subdest = dest;
2160       if (GET_CODE (subdest) == SUBREG
2161           && (GET_MODE_SIZE (GET_MODE (subdest))
2162               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2163         subdest = SUBREG_REG (subdest);
2164       if (pi3dest_killed
2165           && REG_P (subdest)
2166           && reg_referenced_p (subdest, PATTERN (i3))
2167           && REGNO (subdest) != FRAME_POINTER_REGNUM
2168 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2169           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2170 #endif
2171 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2172           && (REGNO (subdest) != ARG_POINTER_REGNUM
2173               || ! fixed_regs [REGNO (subdest)])
2174 #endif
2175           && REGNO (subdest) != STACK_POINTER_REGNUM)
2176         {
2177           if (*pi3dest_killed)
2178             return 0;
2179
2180           *pi3dest_killed = subdest;
2181         }
2182     }
2183
2184   else if (GET_CODE (x) == PARALLEL)
2185     {
2186       int i;
2187
2188       for (i = 0; i < XVECLEN (x, 0); i++)
2189         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2190                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2191           return 0;
2192     }
2193
2194   return 1;
2195 }
2196 \f
2197 /* Return 1 if X is an arithmetic expression that contains a multiplication
2198    and division.  We don't count multiplications by powers of two here.  */
2199
2200 static int
2201 contains_muldiv (rtx x)
2202 {
2203   switch (GET_CODE (x))
2204     {
2205     case MOD:  case DIV:  case UMOD:  case UDIV:
2206       return 1;
2207
2208     case MULT:
2209       return ! (CONST_INT_P (XEXP (x, 1))
2210                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2211     default:
2212       if (BINARY_P (x))
2213         return contains_muldiv (XEXP (x, 0))
2214             || contains_muldiv (XEXP (x, 1));
2215
2216       if (UNARY_P (x))
2217         return contains_muldiv (XEXP (x, 0));
2218
2219       return 0;
2220     }
2221 }
2222 \f
2223 /* Determine whether INSN can be used in a combination.  Return nonzero if
2224    not.  This is used in try_combine to detect early some cases where we
2225    can't perform combinations.  */
2226
2227 static int
2228 cant_combine_insn_p (rtx_insn *insn)
2229 {
2230   rtx set;
2231   rtx src, dest;
2232
2233   /* If this isn't really an insn, we can't do anything.
2234      This can occur when flow deletes an insn that it has merged into an
2235      auto-increment address.  */
2236   if (! INSN_P (insn))
2237     return 1;
2238
2239   /* Never combine loads and stores involving hard regs that are likely
2240      to be spilled.  The register allocator can usually handle such
2241      reg-reg moves by tying.  If we allow the combiner to make
2242      substitutions of likely-spilled regs, reload might die.
2243      As an exception, we allow combinations involving fixed regs; these are
2244      not available to the register allocator so there's no risk involved.  */
2245
2246   set = single_set (insn);
2247   if (! set)
2248     return 0;
2249   src = SET_SRC (set);
2250   dest = SET_DEST (set);
2251   if (GET_CODE (src) == SUBREG)
2252     src = SUBREG_REG (src);
2253   if (GET_CODE (dest) == SUBREG)
2254     dest = SUBREG_REG (dest);
2255   if (REG_P (src) && REG_P (dest)
2256       && ((HARD_REGISTER_P (src)
2257            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2258            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2259           || (HARD_REGISTER_P (dest)
2260               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2261               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2262     return 1;
2263
2264   return 0;
2265 }
2266
2267 struct likely_spilled_retval_info
2268 {
2269   unsigned regno, nregs;
2270   unsigned mask;
2271 };
2272
2273 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2274    hard registers that are known to be written to / clobbered in full.  */
2275 static void
2276 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2277 {
2278   struct likely_spilled_retval_info *const info =
2279     (struct likely_spilled_retval_info *) data;
2280   unsigned regno, nregs;
2281   unsigned new_mask;
2282
2283   if (!REG_P (XEXP (set, 0)))
2284     return;
2285   regno = REGNO (x);
2286   if (regno >= info->regno + info->nregs)
2287     return;
2288   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2289   if (regno + nregs <= info->regno)
2290     return;
2291   new_mask = (2U << (nregs - 1)) - 1;
2292   if (regno < info->regno)
2293     new_mask >>= info->regno - regno;
2294   else
2295     new_mask <<= regno - info->regno;
2296   info->mask &= ~new_mask;
2297 }
2298
2299 /* Return nonzero iff part of the return value is live during INSN, and
2300    it is likely spilled.  This can happen when more than one insn is needed
2301    to copy the return value, e.g. when we consider to combine into the
2302    second copy insn for a complex value.  */
2303
2304 static int
2305 likely_spilled_retval_p (rtx_insn *insn)
2306 {
2307   rtx_insn *use = BB_END (this_basic_block);
2308   rtx reg;
2309   rtx_insn *p;
2310   unsigned regno, nregs;
2311   /* We assume here that no machine mode needs more than
2312      32 hard registers when the value overlaps with a register
2313      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2314   unsigned mask;
2315   struct likely_spilled_retval_info info;
2316
2317   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2318     return 0;
2319   reg = XEXP (PATTERN (use), 0);
2320   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2321     return 0;
2322   regno = REGNO (reg);
2323   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2324   if (nregs == 1)
2325     return 0;
2326   mask = (2U << (nregs - 1)) - 1;
2327
2328   /* Disregard parts of the return value that are set later.  */
2329   info.regno = regno;
2330   info.nregs = nregs;
2331   info.mask = mask;
2332   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2333     if (INSN_P (p))
2334       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2335   mask = info.mask;
2336
2337   /* Check if any of the (probably) live return value registers is
2338      likely spilled.  */
2339   nregs --;
2340   do
2341     {
2342       if ((mask & 1 << nregs)
2343           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2344         return 1;
2345     } while (nregs--);
2346   return 0;
2347 }
2348
2349 /* Adjust INSN after we made a change to its destination.
2350
2351    Changing the destination can invalidate notes that say something about
2352    the results of the insn and a LOG_LINK pointing to the insn.  */
2353
2354 static void
2355 adjust_for_new_dest (rtx_insn *insn)
2356 {
2357   /* For notes, be conservative and simply remove them.  */
2358   remove_reg_equal_equiv_notes (insn);
2359
2360   /* The new insn will have a destination that was previously the destination
2361      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2362      the next use of that destination.  */
2363   distribute_links (alloc_insn_link (insn, NULL));
2364
2365   df_insn_rescan (insn);
2366 }
2367
2368 /* Return TRUE if combine can reuse reg X in mode MODE.
2369    ADDED_SETS is nonzero if the original set is still required.  */
2370 static bool
2371 can_change_dest_mode (rtx x, int added_sets, machine_mode mode)
2372 {
2373   unsigned int regno;
2374
2375   if (!REG_P (x))
2376     return false;
2377
2378   regno = REGNO (x);
2379   /* Allow hard registers if the new mode is legal, and occupies no more
2380      registers than the old mode.  */
2381   if (regno < FIRST_PSEUDO_REGISTER)
2382     return (HARD_REGNO_MODE_OK (regno, mode)
2383             && (hard_regno_nregs[regno][GET_MODE (x)]
2384                 >= hard_regno_nregs[regno][mode]));
2385
2386   /* Or a pseudo that is only used once.  */
2387   return (REG_N_SETS (regno) == 1 && !added_sets
2388           && !REG_USERVAR_P (x));
2389 }
2390
2391
2392 /* Check whether X, the destination of a set, refers to part of
2393    the register specified by REG.  */
2394
2395 static bool
2396 reg_subword_p (rtx x, rtx reg)
2397 {
2398   /* Check that reg is an integer mode register.  */
2399   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2400     return false;
2401
2402   if (GET_CODE (x) == STRICT_LOW_PART
2403       || GET_CODE (x) == ZERO_EXTRACT)
2404     x = XEXP (x, 0);
2405
2406   return GET_CODE (x) == SUBREG
2407          && SUBREG_REG (x) == reg
2408          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2409 }
2410
2411 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2412    Note that the INSN should be deleted *after* removing dead edges, so
2413    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2414    but not for a (set (pc) (label_ref FOO)).  */
2415
2416 static void
2417 update_cfg_for_uncondjump (rtx_insn *insn)
2418 {
2419   basic_block bb = BLOCK_FOR_INSN (insn);
2420   gcc_assert (BB_END (bb) == insn);
2421
2422   purge_dead_edges (bb);
2423
2424   delete_insn (insn);
2425   if (EDGE_COUNT (bb->succs) == 1)
2426     {
2427       rtx_insn *insn;
2428
2429       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2430
2431       /* Remove barriers from the footer if there are any.  */
2432       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2433         if (BARRIER_P (insn))
2434           {
2435             if (PREV_INSN (insn))
2436               SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2437             else
2438               BB_FOOTER (bb) = NEXT_INSN (insn);
2439             if (NEXT_INSN (insn))
2440               SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2441           }
2442         else if (LABEL_P (insn))
2443           break;
2444     }
2445 }
2446
2447 /* Try to combine the insns I0, I1 and I2 into I3.
2448    Here I0, I1 and I2 appear earlier than I3.
2449    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2450    I3.
2451
2452    If we are combining more than two insns and the resulting insn is not
2453    recognized, try splitting it into two insns.  If that happens, I2 and I3
2454    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2455    Otherwise, I0, I1 and I2 are pseudo-deleted.
2456
2457    Return 0 if the combination does not work.  Then nothing is changed.
2458    If we did the combination, return the insn at which combine should
2459    resume scanning.
2460
2461    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2462    new direct jump instruction.
2463
2464    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2465    been I3 passed to an earlier try_combine within the same basic
2466    block.  */
2467
2468 static rtx_insn *
2469 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2470              int *new_direct_jump_p, rtx_insn *last_combined_insn)
2471 {
2472   /* New patterns for I3 and I2, respectively.  */
2473   rtx newpat, newi2pat = 0;
2474   rtvec newpat_vec_with_clobbers = 0;
2475   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2476   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2477      dead.  */
2478   int added_sets_0, added_sets_1, added_sets_2;
2479   /* Total number of SETs to put into I3.  */
2480   int total_sets;
2481   /* Nonzero if I2's or I1's body now appears in I3.  */
2482   int i2_is_used = 0, i1_is_used = 0;
2483   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2484   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2485   /* Contains I3 if the destination of I3 is used in its source, which means
2486      that the old life of I3 is being killed.  If that usage is placed into
2487      I2 and not in I3, a REG_DEAD note must be made.  */
2488   rtx i3dest_killed = 0;
2489   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2490   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2491   /* Copy of SET_SRC of I1 and I0, if needed.  */
2492   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2493   /* Set if I2DEST was reused as a scratch register.  */
2494   bool i2scratch = false;
2495   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2496   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2497   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2498   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2499   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2500   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2501   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2502   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2503   rtx new_i3_notes, new_i2_notes;
2504   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2505   int i3_subst_into_i2 = 0;
2506   /* Notes that I1, I2 or I3 is a MULT operation.  */
2507   int have_mult = 0;
2508   int swap_i2i3 = 0;
2509   int changed_i3_dest = 0;
2510
2511   int maxreg;
2512   rtx_insn *temp_insn;
2513   rtx temp_expr;
2514   struct insn_link *link;
2515   rtx other_pat = 0;
2516   rtx new_other_notes;
2517   int i;
2518
2519   /* Only try four-insn combinations when there's high likelihood of
2520      success.  Look for simple insns, such as loads of constants or
2521      binary operations involving a constant.  */
2522   if (i0)
2523     {
2524       int i;
2525       int ngood = 0;
2526       int nshift = 0;
2527
2528       if (!flag_expensive_optimizations)
2529         return 0;
2530
2531       for (i = 0; i < 4; i++)
2532         {
2533           rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2534           rtx set = single_set (insn);
2535           rtx src;
2536           if (!set)
2537             continue;
2538           src = SET_SRC (set);
2539           if (CONSTANT_P (src))
2540             {
2541               ngood += 2;
2542               break;
2543             }
2544           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2545             ngood++;
2546           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2547                    || GET_CODE (src) == LSHIFTRT)
2548             nshift++;
2549         }
2550       if (ngood < 2 && nshift < 2)
2551         return 0;
2552     }
2553
2554   /* Exit early if one of the insns involved can't be used for
2555      combinations.  */
2556   if (cant_combine_insn_p (i3)
2557       || cant_combine_insn_p (i2)
2558       || (i1 && cant_combine_insn_p (i1))
2559       || (i0 && cant_combine_insn_p (i0))
2560       || likely_spilled_retval_p (i3))
2561     return 0;
2562
2563   combine_attempts++;
2564   undobuf.other_insn = 0;
2565
2566   /* Reset the hard register usage information.  */
2567   CLEAR_HARD_REG_SET (newpat_used_regs);
2568
2569   if (dump_file && (dump_flags & TDF_DETAILS))
2570     {
2571       if (i0)
2572         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2573                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2574       else if (i1)
2575         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2576                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2577       else
2578         fprintf (dump_file, "\nTrying %d -> %d:\n",
2579                  INSN_UID (i2), INSN_UID (i3));
2580     }
2581
2582   /* If multiple insns feed into one of I2 or I3, they can be in any
2583      order.  To simplify the code below, reorder them in sequence.  */
2584   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2585     temp_insn = i2, i2 = i0, i0 = temp_insn;
2586   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2587     temp_insn = i1, i1 = i0, i0 = temp_insn;
2588   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2589     temp_insn = i1, i1 = i2, i2 = temp_insn;
2590
2591   added_links_insn = 0;
2592
2593   /* First check for one important special case that the code below will
2594      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2595      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2596      we may be able to replace that destination with the destination of I3.
2597      This occurs in the common code where we compute both a quotient and
2598      remainder into a structure, in which case we want to do the computation
2599      directly into the structure to avoid register-register copies.
2600
2601      Note that this case handles both multiple sets in I2 and also cases
2602      where I2 has a number of CLOBBERs inside the PARALLEL.
2603
2604      We make very conservative checks below and only try to handle the
2605      most common cases of this.  For example, we only handle the case
2606      where I2 and I3 are adjacent to avoid making difficult register
2607      usage tests.  */
2608
2609   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2610       && REG_P (SET_SRC (PATTERN (i3)))
2611       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2612       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2613       && GET_CODE (PATTERN (i2)) == PARALLEL
2614       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2615       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2616          below would need to check what is inside (and reg_overlap_mentioned_p
2617          doesn't support those codes anyway).  Don't allow those destinations;
2618          the resulting insn isn't likely to be recognized anyway.  */
2619       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2620       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2621       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2622                                     SET_DEST (PATTERN (i3)))
2623       && next_active_insn (i2) == i3)
2624     {
2625       rtx p2 = PATTERN (i2);
2626
2627       /* Make sure that the destination of I3,
2628          which we are going to substitute into one output of I2,
2629          is not used within another output of I2.  We must avoid making this:
2630          (parallel [(set (mem (reg 69)) ...)
2631                     (set (reg 69) ...)])
2632          which is not well-defined as to order of actions.
2633          (Besides, reload can't handle output reloads for this.)
2634
2635          The problem can also happen if the dest of I3 is a memory ref,
2636          if another dest in I2 is an indirect memory ref.  */
2637       for (i = 0; i < XVECLEN (p2, 0); i++)
2638         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2639              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2640             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2641                                         SET_DEST (XVECEXP (p2, 0, i))))
2642           break;
2643
2644       if (i == XVECLEN (p2, 0))
2645         for (i = 0; i < XVECLEN (p2, 0); i++)
2646           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2647               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2648             {
2649               combine_merges++;
2650
2651               subst_insn = i3;
2652               subst_low_luid = DF_INSN_LUID (i2);
2653
2654               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2655               i2src = SET_SRC (XVECEXP (p2, 0, i));
2656               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2657               i2dest_killed = dead_or_set_p (i2, i2dest);
2658
2659               /* Replace the dest in I2 with our dest and make the resulting
2660                  insn the new pattern for I3.  Then skip to where we validate
2661                  the pattern.  Everything was set up above.  */
2662               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2663               newpat = p2;
2664               i3_subst_into_i2 = 1;
2665               goto validate_replacement;
2666             }
2667     }
2668
2669   /* If I2 is setting a pseudo to a constant and I3 is setting some
2670      sub-part of it to another constant, merge them by making a new
2671      constant.  */
2672   if (i1 == 0
2673       && (temp_expr = single_set (i2)) != 0
2674       && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2675       && GET_CODE (PATTERN (i3)) == SET
2676       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2677       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2678     {
2679       rtx dest = SET_DEST (PATTERN (i3));
2680       int offset = -1;
2681       int width = 0;
2682
2683       if (GET_CODE (dest) == ZERO_EXTRACT)
2684         {
2685           if (CONST_INT_P (XEXP (dest, 1))
2686               && CONST_INT_P (XEXP (dest, 2)))
2687             {
2688               width = INTVAL (XEXP (dest, 1));
2689               offset = INTVAL (XEXP (dest, 2));
2690               dest = XEXP (dest, 0);
2691               if (BITS_BIG_ENDIAN)
2692                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2693             }
2694         }
2695       else
2696         {
2697           if (GET_CODE (dest) == STRICT_LOW_PART)
2698             dest = XEXP (dest, 0);
2699           width = GET_MODE_PRECISION (GET_MODE (dest));
2700           offset = 0;
2701         }
2702
2703       if (offset >= 0)
2704         {
2705           /* If this is the low part, we're done.  */
2706           if (subreg_lowpart_p (dest))
2707             ;
2708           /* Handle the case where inner is twice the size of outer.  */
2709           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr)))
2710                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2711             offset += GET_MODE_PRECISION (GET_MODE (dest));
2712           /* Otherwise give up for now.  */
2713           else
2714             offset = -1;
2715         }
2716
2717       if (offset >= 0)
2718         {
2719           rtx inner = SET_SRC (PATTERN (i3));
2720           rtx outer = SET_SRC (temp_expr);
2721
2722           wide_int o
2723             = wi::insert (std::make_pair (outer, GET_MODE (SET_DEST (temp_expr))),
2724                           std::make_pair (inner, GET_MODE (dest)),
2725                           offset, width);
2726
2727           combine_merges++;
2728           subst_insn = i3;
2729           subst_low_luid = DF_INSN_LUID (i2);
2730           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2731           i2dest = SET_DEST (temp_expr);
2732           i2dest_killed = dead_or_set_p (i2, i2dest);
2733
2734           /* Replace the source in I2 with the new constant and make the
2735              resulting insn the new pattern for I3.  Then skip to where we
2736              validate the pattern.  Everything was set up above.  */
2737           SUBST (SET_SRC (temp_expr),
2738                  immed_wide_int_const (o, GET_MODE (SET_DEST (temp_expr))));
2739
2740           newpat = PATTERN (i2);
2741
2742           /* The dest of I3 has been replaced with the dest of I2.  */
2743           changed_i3_dest = 1;
2744           goto validate_replacement;
2745         }
2746     }
2747
2748 #ifndef HAVE_cc0
2749   /* If we have no I1 and I2 looks like:
2750         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2751                    (set Y OP)])
2752      make up a dummy I1 that is
2753         (set Y OP)
2754      and change I2 to be
2755         (set (reg:CC X) (compare:CC Y (const_int 0)))
2756
2757      (We can ignore any trailing CLOBBERs.)
2758
2759      This undoes a previous combination and allows us to match a branch-and-
2760      decrement insn.  */
2761
2762   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2763       && XVECLEN (PATTERN (i2), 0) >= 2
2764       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2765       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2766           == MODE_CC)
2767       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2768       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2769       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2770       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2771       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2772                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2773     {
2774       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2775         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2776           break;
2777
2778       if (i == 1)
2779         {
2780           /* We make I1 with the same INSN_UID as I2.  This gives it
2781              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2782              never appear in the insn stream so giving it the same INSN_UID
2783              as I2 will not cause a problem.  */
2784
2785           i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2786                              XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2787                              -1, NULL_RTX);
2788           INSN_UID (i1) = INSN_UID (i2);
2789
2790           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2791           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2792                  SET_DEST (PATTERN (i1)));
2793           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2794         }
2795     }
2796 #endif
2797
2798   /* Verify that I2 and I1 are valid for combining.  */
2799   if (! can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src)
2800       || (i1 && ! can_combine_p (i1, i3, i0, NULL, i2, NULL,
2801                                  &i1dest, &i1src))
2802       || (i0 && ! can_combine_p (i0, i3, NULL, NULL, i1, i2,
2803                                  &i0dest, &i0src)))
2804     {
2805       undo_all ();
2806       return 0;
2807     }
2808
2809   /* Record whether I2DEST is used in I2SRC and similarly for the other
2810      cases.  Knowing this will help in register status updating below.  */
2811   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2812   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2813   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2814   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2815   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2816   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2817   i2dest_killed = dead_or_set_p (i2, i2dest);
2818   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2819   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2820
2821   /* For the earlier insns, determine which of the subsequent ones they
2822      feed.  */
2823   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2824   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2825   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2826                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2827                              && reg_overlap_mentioned_p (i0dest, i2src))));
2828
2829   /* Ensure that I3's pattern can be the destination of combines.  */
2830   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2831                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2832                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2833                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2834                           &i3dest_killed))
2835     {
2836       undo_all ();
2837       return 0;
2838     }
2839
2840   /* See if any of the insns is a MULT operation.  Unless one is, we will
2841      reject a combination that is, since it must be slower.  Be conservative
2842      here.  */
2843   if (GET_CODE (i2src) == MULT
2844       || (i1 != 0 && GET_CODE (i1src) == MULT)
2845       || (i0 != 0 && GET_CODE (i0src) == MULT)
2846       || (GET_CODE (PATTERN (i3)) == SET
2847           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2848     have_mult = 1;
2849
2850   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2851      We used to do this EXCEPT in one case: I3 has a post-inc in an
2852      output operand.  However, that exception can give rise to insns like
2853         mov r3,(r3)+
2854      which is a famous insn on the PDP-11 where the value of r3 used as the
2855      source was model-dependent.  Avoid this sort of thing.  */
2856
2857 #if 0
2858   if (!(GET_CODE (PATTERN (i3)) == SET
2859         && REG_P (SET_SRC (PATTERN (i3)))
2860         && MEM_P (SET_DEST (PATTERN (i3)))
2861         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2862             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2863     /* It's not the exception.  */
2864 #endif
2865 #ifdef AUTO_INC_DEC
2866     {
2867       rtx link;
2868       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2869         if (REG_NOTE_KIND (link) == REG_INC
2870             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2871                 || (i1 != 0
2872                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2873           {
2874             undo_all ();
2875             return 0;
2876           }
2877     }
2878 #endif
2879
2880   /* See if the SETs in I1 or I2 need to be kept around in the merged
2881      instruction: whenever the value set there is still needed past I3.
2882      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2883
2884      For the SET in I1, we have two cases: if I1 and I2 independently feed
2885      into I3, the set in I1 needs to be kept around unless I1DEST dies
2886      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2887      in I1 needs to be kept around unless I1DEST dies or is set in either
2888      I2 or I3.  The same considerations apply to I0.  */
2889
2890   added_sets_2 = !dead_or_set_p (i3, i2dest);
2891
2892   if (i1)
2893     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2894                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2895   else
2896     added_sets_1 = 0;
2897
2898   if (i0)
2899     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2900                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2901                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2902                           && dead_or_set_p (i2, i0dest)));
2903   else
2904     added_sets_0 = 0;
2905
2906   /* We are about to copy insns for the case where they need to be kept
2907      around.  Check that they can be copied in the merged instruction.  */
2908
2909   if (targetm.cannot_copy_insn_p
2910       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2911           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2912           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2913     {
2914       undo_all ();
2915       return 0;
2916     }
2917
2918   /* If the set in I2 needs to be kept around, we must make a copy of
2919      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2920      PATTERN (I2), we are only substituting for the original I1DEST, not into
2921      an already-substituted copy.  This also prevents making self-referential
2922      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2923      I2DEST.  */
2924
2925   if (added_sets_2)
2926     {
2927       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2928         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2929       else
2930         i2pat = copy_rtx (PATTERN (i2));
2931     }
2932
2933   if (added_sets_1)
2934     {
2935       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2936         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2937       else
2938         i1pat = copy_rtx (PATTERN (i1));
2939     }
2940
2941   if (added_sets_0)
2942     {
2943       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2944         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2945       else
2946         i0pat = copy_rtx (PATTERN (i0));
2947     }
2948
2949   combine_merges++;
2950
2951   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2952
2953   maxreg = max_reg_num ();
2954
2955   subst_insn = i3;
2956
2957 #ifndef HAVE_cc0
2958   /* Many machines that don't use CC0 have insns that can both perform an
2959      arithmetic operation and set the condition code.  These operations will
2960      be represented as a PARALLEL with the first element of the vector
2961      being a COMPARE of an arithmetic operation with the constant zero.
2962      The second element of the vector will set some pseudo to the result
2963      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2964      match such a pattern and so will generate an extra insn.   Here we test
2965      for this case, where both the comparison and the operation result are
2966      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2967      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2968
2969   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2970       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2971       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2972       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2973     {
2974       rtx newpat_dest;
2975       rtx *cc_use_loc = NULL;
2976       rtx_insn *cc_use_insn = NULL;
2977       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2978       machine_mode compare_mode, orig_compare_mode;
2979       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2980
2981       newpat = PATTERN (i3);
2982       newpat_dest = SET_DEST (newpat);
2983       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2984
2985       if (undobuf.other_insn == 0
2986           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2987                                             &cc_use_insn)))
2988         {
2989           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2990           compare_code = simplify_compare_const (compare_code,
2991                                                  GET_MODE (i2dest), op0, &op1);
2992           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2993         }
2994
2995       /* Do the rest only if op1 is const0_rtx, which may be the
2996          result of simplification.  */
2997       if (op1 == const0_rtx)
2998         {
2999           /* If a single use of the CC is found, prepare to modify it
3000              when SELECT_CC_MODE returns a new CC-class mode, or when
3001              the above simplify_compare_const() returned a new comparison
3002              operator.  undobuf.other_insn is assigned the CC use insn
3003              when modifying it.  */
3004           if (cc_use_loc)
3005             {
3006 #ifdef SELECT_CC_MODE
3007               machine_mode new_mode
3008                 = SELECT_CC_MODE (compare_code, op0, op1);
3009               if (new_mode != orig_compare_mode
3010                   && can_change_dest_mode (SET_DEST (newpat),
3011                                            added_sets_2, new_mode))
3012                 {
3013                   unsigned int regno = REGNO (newpat_dest);
3014                   compare_mode = new_mode;
3015                   if (regno < FIRST_PSEUDO_REGISTER)
3016                     newpat_dest = gen_rtx_REG (compare_mode, regno);
3017                   else
3018                     {
3019                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3020                       newpat_dest = regno_reg_rtx[regno];
3021                     }
3022                 }
3023 #endif
3024               /* Cases for modifying the CC-using comparison.  */
3025               if (compare_code != orig_compare_code
3026                   /* ??? Do we need to verify the zero rtx?  */
3027                   && XEXP (*cc_use_loc, 1) == const0_rtx)
3028                 {
3029                   /* Replace cc_use_loc with entire new RTX.  */
3030                   SUBST (*cc_use_loc,
3031                          gen_rtx_fmt_ee (compare_code, compare_mode,
3032                                          newpat_dest, const0_rtx));
3033                   undobuf.other_insn = cc_use_insn;
3034                 }
3035               else if (compare_mode != orig_compare_mode)
3036                 {
3037                   /* Just replace the CC reg with a new mode.  */
3038                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3039                   undobuf.other_insn = cc_use_insn;
3040                 }
3041             }
3042
3043           /* Now we modify the current newpat:
3044              First, SET_DEST(newpat) is updated if the CC mode has been
3045              altered. For targets without SELECT_CC_MODE, this should be
3046              optimized away.  */
3047           if (compare_mode != orig_compare_mode)
3048             SUBST (SET_DEST (newpat), newpat_dest);
3049           /* This is always done to propagate i2src into newpat.  */
3050           SUBST (SET_SRC (newpat),
3051                  gen_rtx_COMPARE (compare_mode, op0, op1));
3052           /* Create new version of i2pat if needed; the below PARALLEL
3053              creation needs this to work correctly.  */
3054           if (! rtx_equal_p (i2src, op0))
3055             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3056           i2_is_used = 1;
3057         }
3058     }
3059 #endif
3060
3061   if (i2_is_used == 0)
3062     {
3063       /* It is possible that the source of I2 or I1 may be performing
3064          an unneeded operation, such as a ZERO_EXTEND of something
3065          that is known to have the high part zero.  Handle that case
3066          by letting subst look at the inner insns.
3067
3068          Another way to do this would be to have a function that tries
3069          to simplify a single insn instead of merging two or more
3070          insns.  We don't do this because of the potential of infinite
3071          loops and because of the potential extra memory required.
3072          However, doing it the way we are is a bit of a kludge and
3073          doesn't catch all cases.
3074
3075          But only do this if -fexpensive-optimizations since it slows
3076          things down and doesn't usually win.
3077
3078          This is not done in the COMPARE case above because the
3079          unmodified I2PAT is used in the PARALLEL and so a pattern
3080          with a modified I2SRC would not match.  */
3081
3082       if (flag_expensive_optimizations)
3083         {
3084           /* Pass pc_rtx so no substitutions are done, just
3085              simplifications.  */
3086           if (i1)
3087             {
3088               subst_low_luid = DF_INSN_LUID (i1);
3089               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3090             }
3091
3092           subst_low_luid = DF_INSN_LUID (i2);
3093           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3094         }
3095
3096       n_occurrences = 0;                /* `subst' counts here */
3097       subst_low_luid = DF_INSN_LUID (i2);
3098
3099       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3100          copy of I2SRC each time we substitute it, in order to avoid creating
3101          self-referential RTL when we will be substituting I1SRC for I1DEST
3102          later.  Likewise if I0 feeds into I2, either directly or indirectly
3103          through I1, and I0DEST is in I0SRC.  */
3104       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3105                       (i1_feeds_i2_n && i1dest_in_i1src)
3106                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3107                           && i0dest_in_i0src));
3108       substed_i2 = 1;
3109
3110       /* Record whether I2's body now appears within I3's body.  */
3111       i2_is_used = n_occurrences;
3112     }
3113
3114   /* If we already got a failure, don't try to do more.  Otherwise, try to
3115      substitute I1 if we have it.  */
3116
3117   if (i1 && GET_CODE (newpat) != CLOBBER)
3118     {
3119       /* Check that an autoincrement side-effect on I1 has not been lost.
3120          This happens if I1DEST is mentioned in I2 and dies there, and
3121          has disappeared from the new pattern.  */
3122       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3123            && i1_feeds_i2_n
3124            && dead_or_set_p (i2, i1dest)
3125            && !reg_overlap_mentioned_p (i1dest, newpat))
3126            /* Before we can do this substitution, we must redo the test done
3127               above (see detailed comments there) that ensures I1DEST isn't
3128               mentioned in any SETs in NEWPAT that are field assignments.  */
3129           || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3130                                 0, 0, 0))
3131         {
3132           undo_all ();
3133           return 0;
3134         }
3135
3136       n_occurrences = 0;
3137       subst_low_luid = DF_INSN_LUID (i1);
3138
3139       /* If the following substitution will modify I1SRC, make a copy of it
3140          for the case where it is substituted for I1DEST in I2PAT later.  */
3141       if (added_sets_2 && i1_feeds_i2_n)
3142         i1src_copy = copy_rtx (i1src);
3143
3144       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3145          copy of I1SRC each time we substitute it, in order to avoid creating
3146          self-referential RTL when we will be substituting I0SRC for I0DEST
3147          later.  */
3148       newpat = subst (newpat, i1dest, i1src, 0, 0,
3149                       i0_feeds_i1_n && i0dest_in_i0src);
3150       substed_i1 = 1;
3151
3152       /* Record whether I1's body now appears within I3's body.  */
3153       i1_is_used = n_occurrences;
3154     }
3155
3156   /* Likewise for I0 if we have it.  */
3157
3158   if (i0 && GET_CODE (newpat) != CLOBBER)
3159     {
3160       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3161            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3162                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3163            && !reg_overlap_mentioned_p (i0dest, newpat))
3164           || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3165                                 0, 0, 0))
3166         {
3167           undo_all ();
3168           return 0;
3169         }
3170
3171       /* If the following substitution will modify I0SRC, make a copy of it
3172          for the case where it is substituted for I0DEST in I1PAT later.  */
3173       if (added_sets_1 && i0_feeds_i1_n)
3174         i0src_copy = copy_rtx (i0src);
3175       /* And a copy for I0DEST in I2PAT substitution.  */
3176       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3177                            || (i0_feeds_i2_n)))
3178         i0src_copy2 = copy_rtx (i0src);
3179
3180       n_occurrences = 0;
3181       subst_low_luid = DF_INSN_LUID (i0);
3182       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3183       substed_i0 = 1;
3184     }
3185
3186   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3187      to count all the ways that I2SRC and I1SRC can be used.  */
3188   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3189        && i2_is_used + added_sets_2 > 1)
3190       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3191           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3192               > 1))
3193       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3194           && (n_occurrences + added_sets_0
3195               + (added_sets_1 && i0_feeds_i1_n)
3196               + (added_sets_2 && i0_feeds_i2_n)
3197               > 1))
3198       /* Fail if we tried to make a new register.  */
3199       || max_reg_num () != maxreg
3200       /* Fail if we couldn't do something and have a CLOBBER.  */
3201       || GET_CODE (newpat) == CLOBBER
3202       /* Fail if this new pattern is a MULT and we didn't have one before
3203          at the outer level.  */
3204       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3205           && ! have_mult))
3206     {
3207       undo_all ();
3208       return 0;
3209     }
3210
3211   /* If the actions of the earlier insns must be kept
3212      in addition to substituting them into the latest one,
3213      we must make a new PARALLEL for the latest insn
3214      to hold additional the SETs.  */
3215
3216   if (added_sets_0 || added_sets_1 || added_sets_2)
3217     {
3218       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3219       combine_extras++;
3220
3221       if (GET_CODE (newpat) == PARALLEL)
3222         {
3223           rtvec old = XVEC (newpat, 0);
3224           total_sets = XVECLEN (newpat, 0) + extra_sets;
3225           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3226           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3227                   sizeof (old->elem[0]) * old->num_elem);
3228         }
3229       else
3230         {
3231           rtx old = newpat;
3232           total_sets = 1 + extra_sets;
3233           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3234           XVECEXP (newpat, 0, 0) = old;
3235         }
3236
3237       if (added_sets_0)
3238         XVECEXP (newpat, 0, --total_sets) = i0pat;
3239
3240       if (added_sets_1)
3241         {
3242           rtx t = i1pat;
3243           if (i0_feeds_i1_n)
3244             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3245
3246           XVECEXP (newpat, 0, --total_sets) = t;
3247         }
3248       if (added_sets_2)
3249         {
3250           rtx t = i2pat;
3251           if (i1_feeds_i2_n)
3252             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3253                        i0_feeds_i1_n && i0dest_in_i0src);
3254           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3255             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3256
3257           XVECEXP (newpat, 0, --total_sets) = t;
3258         }
3259     }
3260
3261  validate_replacement:
3262
3263   /* Note which hard regs this insn has as inputs.  */
3264   mark_used_regs_combine (newpat);
3265
3266   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3267      consider splitting this pattern, we might need these clobbers.  */
3268   if (i1 && GET_CODE (newpat) == PARALLEL
3269       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3270     {
3271       int len = XVECLEN (newpat, 0);
3272
3273       newpat_vec_with_clobbers = rtvec_alloc (len);
3274       for (i = 0; i < len; i++)
3275         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3276     }
3277
3278   /* Is the result of combination a valid instruction?  */
3279   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3280
3281   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3282      the second SET's destination is a register that is unused and isn't
3283      marked as an instruction that might trap in an EH region.  In that case,
3284      we just need the first SET.   This can occur when simplifying a divmod
3285      insn.  We *must* test for this case here because the code below that
3286      splits two independent SETs doesn't handle this case correctly when it
3287      updates the register status.
3288
3289      It's pointless doing this if we originally had two sets, one from
3290      i3, and one from i2.  Combining then splitting the parallel results
3291      in the original i2 again plus an invalid insn (which we delete).
3292      The net effect is only to move instructions around, which makes
3293      debug info less accurate.
3294
3295      Also check the case where the first SET's destination is unused.
3296      That would not cause incorrect code, but does cause an unneeded
3297      insn to remain.  */
3298
3299   if (insn_code_number < 0
3300       && !(added_sets_2 && i1 == 0)
3301       && GET_CODE (newpat) == PARALLEL
3302       && XVECLEN (newpat, 0) == 2
3303       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3304       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3305       && asm_noperands (newpat) < 0)
3306     {
3307       rtx set0 = XVECEXP (newpat, 0, 0);
3308       rtx set1 = XVECEXP (newpat, 0, 1);
3309
3310       if (((REG_P (SET_DEST (set1))
3311             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3312            || (GET_CODE (SET_DEST (set1)) == SUBREG
3313                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3314           && insn_nothrow_p (i3)
3315           && !side_effects_p (SET_SRC (set1)))
3316         {
3317           newpat = set0;
3318           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3319         }
3320
3321       else if (((REG_P (SET_DEST (set0))
3322                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3323                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3324                     && find_reg_note (i3, REG_UNUSED,
3325                                       SUBREG_REG (SET_DEST (set0)))))
3326                && insn_nothrow_p (i3)
3327                && !side_effects_p (SET_SRC (set0)))
3328         {
3329           newpat = set1;
3330           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3331
3332           if (insn_code_number >= 0)
3333             changed_i3_dest = 1;
3334         }
3335     }
3336
3337   /* If we were combining three insns and the result is a simple SET
3338      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3339      insns.  There are two ways to do this.  It can be split using a
3340      machine-specific method (like when you have an addition of a large
3341      constant) or by combine in the function find_split_point.  */
3342
3343   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3344       && asm_noperands (newpat) < 0)
3345     {
3346       rtx parallel, *split;
3347       rtx_insn *m_split_insn;
3348
3349       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3350          use I2DEST as a scratch register will help.  In the latter case,
3351          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3352
3353       m_split_insn = combine_split_insns (newpat, i3);
3354
3355       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3356          inputs of NEWPAT.  */
3357
3358       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3359          possible to try that as a scratch reg.  This would require adding
3360          more code to make it work though.  */
3361
3362       if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3363         {
3364           machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3365
3366           /* First try to split using the original register as a
3367              scratch register.  */
3368           parallel = gen_rtx_PARALLEL (VOIDmode,
3369                                        gen_rtvec (2, newpat,
3370                                                   gen_rtx_CLOBBER (VOIDmode,
3371                                                                    i2dest)));
3372           m_split_insn = combine_split_insns (parallel, i3);
3373
3374           /* If that didn't work, try changing the mode of I2DEST if
3375              we can.  */
3376           if (m_split_insn == 0
3377               && new_mode != GET_MODE (i2dest)
3378               && new_mode != VOIDmode
3379               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3380             {
3381               machine_mode old_mode = GET_MODE (i2dest);
3382               rtx ni2dest;
3383
3384               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3385                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3386               else
3387                 {
3388                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3389                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3390                 }
3391
3392               parallel = (gen_rtx_PARALLEL
3393                           (VOIDmode,
3394                            gen_rtvec (2, newpat,
3395                                       gen_rtx_CLOBBER (VOIDmode,
3396                                                        ni2dest))));
3397               m_split_insn = combine_split_insns (parallel, i3);
3398
3399               if (m_split_insn == 0
3400                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3401                 {
3402                   struct undo *buf;
3403
3404                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3405                   buf = undobuf.undos;
3406                   undobuf.undos = buf->next;
3407                   buf->next = undobuf.frees;
3408                   undobuf.frees = buf;
3409                 }
3410             }
3411
3412           i2scratch = m_split_insn != 0;
3413         }
3414
3415       /* If recog_for_combine has discarded clobbers, try to use them
3416          again for the split.  */
3417       if (m_split_insn == 0 && newpat_vec_with_clobbers)
3418         {
3419           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3420           m_split_insn = combine_split_insns (parallel, i3);
3421         }
3422
3423       if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3424         {
3425           rtx m_split_pat = PATTERN (m_split_insn);
3426           insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3427           if (insn_code_number >= 0)
3428             newpat = m_split_pat;
3429         }
3430       else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3431                && (next_nonnote_nondebug_insn (i2) == i3
3432                    || ! use_crosses_set_p (PATTERN (m_split_insn), DF_INSN_LUID (i2))))
3433         {
3434           rtx i2set, i3set;
3435           rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3436           newi2pat = PATTERN (m_split_insn);
3437
3438           i3set = single_set (NEXT_INSN (m_split_insn));
3439           i2set = single_set (m_split_insn);
3440
3441           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3442
3443           /* If I2 or I3 has multiple SETs, we won't know how to track
3444              register status, so don't use these insns.  If I2's destination
3445              is used between I2 and I3, we also can't use these insns.  */
3446
3447           if (i2_code_number >= 0 && i2set && i3set
3448               && (next_nonnote_nondebug_insn (i2) == i3
3449                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3450             insn_code_number = recog_for_combine (&newi3pat, i3,
3451                                                   &new_i3_notes);
3452           if (insn_code_number >= 0)
3453             newpat = newi3pat;
3454
3455           /* It is possible that both insns now set the destination of I3.
3456              If so, we must show an extra use of it.  */
3457
3458           if (insn_code_number >= 0)
3459             {
3460               rtx new_i3_dest = SET_DEST (i3set);
3461               rtx new_i2_dest = SET_DEST (i2set);
3462
3463               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3464                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3465                      || GET_CODE (new_i3_dest) == SUBREG)
3466                 new_i3_dest = XEXP (new_i3_dest, 0);
3467
3468               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3469                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3470                      || GET_CODE (new_i2_dest) == SUBREG)
3471                 new_i2_dest = XEXP (new_i2_dest, 0);
3472
3473               if (REG_P (new_i3_dest)
3474                   && REG_P (new_i2_dest)
3475                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3476                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3477             }
3478         }
3479
3480       /* If we can split it and use I2DEST, go ahead and see if that
3481          helps things be recognized.  Verify that none of the registers
3482          are set between I2 and I3.  */
3483       if (insn_code_number < 0
3484           && (split = find_split_point (&newpat, i3, false)) != 0
3485 #ifdef HAVE_cc0
3486           && REG_P (i2dest)
3487 #endif
3488           /* We need I2DEST in the proper mode.  If it is a hard register
3489              or the only use of a pseudo, we can change its mode.
3490              Make sure we don't change a hard register to have a mode that
3491              isn't valid for it, or change the number of registers.  */
3492           && (GET_MODE (*split) == GET_MODE (i2dest)
3493               || GET_MODE (*split) == VOIDmode
3494               || can_change_dest_mode (i2dest, added_sets_2,
3495                                        GET_MODE (*split)))
3496           && (next_nonnote_nondebug_insn (i2) == i3
3497               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3498           /* We can't overwrite I2DEST if its value is still used by
3499              NEWPAT.  */
3500           && ! reg_referenced_p (i2dest, newpat))
3501         {
3502           rtx newdest = i2dest;
3503           enum rtx_code split_code = GET_CODE (*split);
3504           machine_mode split_mode = GET_MODE (*split);
3505           bool subst_done = false;
3506           newi2pat = NULL_RTX;
3507
3508           i2scratch = true;
3509
3510           /* *SPLIT may be part of I2SRC, so make sure we have the
3511              original expression around for later debug processing.
3512              We should not need I2SRC any more in other cases.  */
3513           if (MAY_HAVE_DEBUG_INSNS)
3514             i2src = copy_rtx (i2src);
3515           else
3516             i2src = NULL;
3517
3518           /* Get NEWDEST as a register in the proper mode.  We have already
3519              validated that we can do this.  */
3520           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3521             {
3522               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3523                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3524               else
3525                 {
3526                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3527                   newdest = regno_reg_rtx[REGNO (i2dest)];
3528                 }
3529             }
3530
3531           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3532              an ASHIFT.  This can occur if it was inside a PLUS and hence
3533              appeared to be a memory address.  This is a kludge.  */
3534           if (split_code == MULT
3535               && CONST_INT_P (XEXP (*split, 1))
3536               && INTVAL (XEXP (*split, 1)) > 0
3537               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3538             {
3539               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3540                                              XEXP (*split, 0), GEN_INT (i)));
3541               /* Update split_code because we may not have a multiply
3542                  anymore.  */
3543               split_code = GET_CODE (*split);
3544             }
3545
3546 #ifdef INSN_SCHEDULING
3547           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3548              be written as a ZERO_EXTEND.  */
3549           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3550             {
3551 #ifdef LOAD_EXTEND_OP
3552               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3553                  what it really is.  */
3554               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3555                   == SIGN_EXTEND)
3556                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3557                                                     SUBREG_REG (*split)));
3558               else
3559 #endif
3560                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3561                                                     SUBREG_REG (*split)));
3562             }
3563 #endif
3564
3565           /* Attempt to split binary operators using arithmetic identities.  */
3566           if (BINARY_P (SET_SRC (newpat))
3567               && split_mode == GET_MODE (SET_SRC (newpat))
3568               && ! side_effects_p (SET_SRC (newpat)))
3569             {
3570               rtx setsrc = SET_SRC (newpat);
3571               machine_mode mode = GET_MODE (setsrc);
3572               enum rtx_code code = GET_CODE (setsrc);
3573               rtx src_op0 = XEXP (setsrc, 0);
3574               rtx src_op1 = XEXP (setsrc, 1);
3575
3576               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3577               if (rtx_equal_p (src_op0, src_op1))
3578                 {
3579                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3580                   SUBST (XEXP (setsrc, 0), newdest);
3581                   SUBST (XEXP (setsrc, 1), newdest);
3582                   subst_done = true;
3583                 }
3584               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3585               else if ((code == PLUS || code == MULT)
3586                        && GET_CODE (src_op0) == code
3587                        && GET_CODE (XEXP (src_op0, 0)) == code
3588                        && (INTEGRAL_MODE_P (mode)
3589                            || (FLOAT_MODE_P (mode)
3590                                && flag_unsafe_math_optimizations)))
3591                 {
3592                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3593                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3594                   rtx r = XEXP (src_op0, 1);
3595                   rtx s = src_op1;
3596
3597                   /* Split both "((X op Y) op X) op Y" and
3598                      "((X op Y) op Y) op X" as "T op T" where T is
3599                      "X op Y".  */
3600                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3601                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3602                     {
3603                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3604                                               XEXP (src_op0, 0));
3605                       SUBST (XEXP (setsrc, 0), newdest);
3606                       SUBST (XEXP (setsrc, 1), newdest);
3607                       subst_done = true;
3608                     }
3609                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3610                      T is "X op Y".  */
3611                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3612                     {
3613                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3614                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3615                       SUBST (XEXP (setsrc, 0), newdest);
3616                       SUBST (XEXP (setsrc, 1), newdest);
3617                       subst_done = true;
3618                     }
3619                 }
3620             }
3621
3622           if (!subst_done)
3623             {
3624               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3625               SUBST (*split, newdest);
3626             }
3627
3628           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3629
3630           /* recog_for_combine might have added CLOBBERs to newi2pat.
3631              Make sure NEWPAT does not depend on the clobbered regs.  */
3632           if (GET_CODE (newi2pat) == PARALLEL)
3633             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3634               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3635                 {
3636                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3637                   if (reg_overlap_mentioned_p (reg, newpat))
3638                     {
3639                       undo_all ();
3640                       return 0;
3641                     }
3642                 }
3643
3644           /* If the split point was a MULT and we didn't have one before,
3645              don't use one now.  */
3646           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3647             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3648         }
3649     }
3650
3651   /* Check for a case where we loaded from memory in a narrow mode and
3652      then sign extended it, but we need both registers.  In that case,
3653      we have a PARALLEL with both loads from the same memory location.
3654      We can split this into a load from memory followed by a register-register
3655      copy.  This saves at least one insn, more if register allocation can
3656      eliminate the copy.
3657
3658      We cannot do this if the destination of the first assignment is a
3659      condition code register or cc0.  We eliminate this case by making sure
3660      the SET_DEST and SET_SRC have the same mode.
3661
3662      We cannot do this if the destination of the second assignment is
3663      a register that we have already assumed is zero-extended.  Similarly
3664      for a SUBREG of such a register.  */
3665
3666   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3667            && GET_CODE (newpat) == PARALLEL
3668            && XVECLEN (newpat, 0) == 2
3669            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3670            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3671            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3672                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3673            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3674            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3675                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3676            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3677                                    DF_INSN_LUID (i2))
3678            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3679            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3680            && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3681                  (REG_P (temp_expr)
3682                   && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3683                   && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
3684                   && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
3685                   && (reg_stat[REGNO (temp_expr)].nonzero_bits
3686                       != GET_MODE_MASK (word_mode))))
3687            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3688                  && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3689                      (REG_P (temp_expr)
3690                       && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3691                       && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
3692                       && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
3693                       && (reg_stat[REGNO (temp_expr)].nonzero_bits
3694                           != GET_MODE_MASK (word_mode)))))
3695            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3696                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3697            && ! find_reg_note (i3, REG_UNUSED,
3698                                SET_DEST (XVECEXP (newpat, 0, 0))))
3699     {
3700       rtx ni2dest;
3701
3702       newi2pat = XVECEXP (newpat, 0, 0);
3703       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3704       newpat = XVECEXP (newpat, 0, 1);
3705       SUBST (SET_SRC (newpat),
3706              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3707       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3708
3709       if (i2_code_number >= 0)
3710         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3711
3712       if (insn_code_number >= 0)
3713         swap_i2i3 = 1;
3714     }
3715
3716   /* Similarly, check for a case where we have a PARALLEL of two independent
3717      SETs but we started with three insns.  In this case, we can do the sets
3718      as two separate insns.  This case occurs when some SET allows two
3719      other insns to combine, but the destination of that SET is still live.  */
3720
3721   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3722            && GET_CODE (newpat) == PARALLEL
3723            && XVECLEN (newpat, 0) == 2
3724            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3725            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3726            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3727            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3728            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3729            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3730            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3731                                   XVECEXP (newpat, 0, 0))
3732            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3733                                   XVECEXP (newpat, 0, 1))
3734            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3735                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3736     {
3737       rtx set0 = XVECEXP (newpat, 0, 0);
3738       rtx set1 = XVECEXP (newpat, 0, 1);
3739
3740       /* Normally, it doesn't matter which of the two is done first,
3741          but the one that references cc0 can't be the second, and
3742          one which uses any regs/memory set in between i2 and i3 can't
3743          be first.  The PARALLEL might also have been pre-existing in i3,
3744          so we need to make sure that we won't wrongly hoist a SET to i2
3745          that would conflict with a death note present in there.  */
3746       if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3747           && !(REG_P (SET_DEST (set1))
3748                && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3749           && !(GET_CODE (SET_DEST (set1)) == SUBREG
3750                && find_reg_note (i2, REG_DEAD,
3751                                  SUBREG_REG (SET_DEST (set1))))
3752 #ifdef HAVE_cc0
3753           && !reg_referenced_p (cc0_rtx, set0)
3754 #endif
3755           /* If I3 is a jump, ensure that set0 is a jump so that
3756              we do not create invalid RTL.  */
3757           && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
3758          )
3759         {
3760           newi2pat = set1;
3761           newpat = set0;
3762         }
3763       else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3764                && !(REG_P (SET_DEST (set0))
3765                     && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3766                && !(GET_CODE (SET_DEST (set0)) == SUBREG
3767                     && find_reg_note (i2, REG_DEAD,
3768                                       SUBREG_REG (SET_DEST (set0))))
3769 #ifdef HAVE_cc0
3770                && !reg_referenced_p (cc0_rtx, set1)
3771 #endif
3772                /* If I3 is a jump, ensure that set1 is a jump so that
3773                   we do not create invalid RTL.  */
3774                && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
3775               )
3776         {
3777           newi2pat = set0;
3778           newpat = set1;
3779         }
3780       else
3781         {
3782           undo_all ();
3783           return 0;
3784         }
3785
3786       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3787
3788       if (i2_code_number >= 0)
3789         {
3790           /* recog_for_combine might have added CLOBBERs to newi2pat.
3791              Make sure NEWPAT does not depend on the clobbered regs.  */
3792           if (GET_CODE (newi2pat) == PARALLEL)
3793             {
3794               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3795                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3796                   {
3797                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3798                     if (reg_overlap_mentioned_p (reg, newpat))
3799                       {
3800                         undo_all ();
3801                         return 0;
3802                       }
3803                   }
3804             }
3805
3806           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3807         }
3808     }
3809
3810   /* If it still isn't recognized, fail and change things back the way they
3811      were.  */
3812   if ((insn_code_number < 0
3813        /* Is the result a reasonable ASM_OPERANDS?  */
3814        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3815     {
3816       undo_all ();
3817       return 0;
3818     }
3819
3820   /* If we had to change another insn, make sure it is valid also.  */
3821   if (undobuf.other_insn)
3822     {
3823       CLEAR_HARD_REG_SET (newpat_used_regs);
3824
3825       other_pat = PATTERN (undobuf.other_insn);
3826       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3827                                              &new_other_notes);
3828
3829       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3830         {
3831           undo_all ();
3832           return 0;
3833         }
3834     }
3835
3836 #ifdef HAVE_cc0
3837   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3838      they are adjacent to each other or not.  */
3839   {
3840     rtx_insn *p = prev_nonnote_insn (i3);
3841     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3842         && sets_cc0_p (newi2pat))
3843       {
3844         undo_all ();
3845         return 0;
3846       }
3847   }
3848 #endif
3849
3850   /* Only allow this combination if insn_rtx_costs reports that the
3851      replacement instructions are cheaper than the originals.  */
3852   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3853     {
3854       undo_all ();
3855       return 0;
3856     }
3857
3858   if (MAY_HAVE_DEBUG_INSNS)
3859     {
3860       struct undo *undo;
3861
3862       for (undo = undobuf.undos; undo; undo = undo->next)
3863         if (undo->kind == UNDO_MODE)
3864           {
3865             rtx reg = *undo->where.r;
3866             machine_mode new_mode = GET_MODE (reg);
3867             machine_mode old_mode = undo->old_contents.m;
3868
3869             /* Temporarily revert mode back.  */
3870             adjust_reg_mode (reg, old_mode);
3871
3872             if (reg == i2dest && i2scratch)
3873               {
3874                 /* If we used i2dest as a scratch register with a
3875                    different mode, substitute it for the original
3876                    i2src while its original mode is temporarily
3877                    restored, and then clear i2scratch so that we don't
3878                    do it again later.  */
3879                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3880                                      this_basic_block);
3881                 i2scratch = false;
3882                 /* Put back the new mode.  */
3883                 adjust_reg_mode (reg, new_mode);
3884               }
3885             else
3886               {
3887                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3888                 rtx_insn *first, *last;
3889
3890                 if (reg == i2dest)
3891                   {
3892                     first = i2;
3893                     last = last_combined_insn;
3894                   }
3895                 else
3896                   {
3897                     first = i3;
3898                     last = undobuf.other_insn;
3899                     gcc_assert (last);
3900                     if (DF_INSN_LUID (last)
3901                         < DF_INSN_LUID (last_combined_insn))
3902                       last = last_combined_insn;
3903                   }
3904
3905                 /* We're dealing with a reg that changed mode but not
3906                    meaning, so we want to turn it into a subreg for
3907                    the new mode.  However, because of REG sharing and
3908                    because its mode had already changed, we have to do
3909                    it in two steps.  First, replace any debug uses of
3910                    reg, with its original mode temporarily restored,
3911                    with this copy we have created; then, replace the
3912                    copy with the SUBREG of the original shared reg,
3913                    once again changed to the new mode.  */
3914                 propagate_for_debug (first, last, reg, tempreg,
3915                                      this_basic_block);
3916                 adjust_reg_mode (reg, new_mode);
3917                 propagate_for_debug (first, last, tempreg,
3918                                      lowpart_subreg (old_mode, reg, new_mode),
3919                                      this_basic_block);
3920               }
3921           }
3922     }
3923
3924   /* If we will be able to accept this, we have made a
3925      change to the destination of I3.  This requires us to
3926      do a few adjustments.  */
3927
3928   if (changed_i3_dest)
3929     {
3930       PATTERN (i3) = newpat;
3931       adjust_for_new_dest (i3);
3932     }
3933
3934   /* We now know that we can do this combination.  Merge the insns and
3935      update the status of registers and LOG_LINKS.  */
3936
3937   if (undobuf.other_insn)
3938     {
3939       rtx note, next;
3940
3941       PATTERN (undobuf.other_insn) = other_pat;
3942
3943       /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3944          ensure that they are still valid.  Then add any non-duplicate
3945          notes added by recog_for_combine.  */
3946       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3947         {
3948           next = XEXP (note, 1);
3949
3950           if ((REG_NOTE_KIND (note) == REG_DEAD
3951                && !reg_referenced_p (XEXP (note, 0),
3952                                      PATTERN (undobuf.other_insn)))
3953               ||(REG_NOTE_KIND (note) == REG_UNUSED
3954                  && !reg_set_p (XEXP (note, 0),
3955                                 PATTERN (undobuf.other_insn))))
3956             remove_note (undobuf.other_insn, note);
3957         }
3958
3959       distribute_notes  (new_other_notes, undobuf.other_insn,
3960                         undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
3961                         NULL_RTX);
3962     }
3963
3964   if (swap_i2i3)
3965     {
3966       rtx_insn *insn;
3967       struct insn_link *link;
3968       rtx ni2dest;
3969
3970       /* I3 now uses what used to be its destination and which is now
3971          I2's destination.  This requires us to do a few adjustments.  */
3972       PATTERN (i3) = newpat;
3973       adjust_for_new_dest (i3);
3974
3975       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3976          so we still will.
3977
3978          However, some later insn might be using I2's dest and have
3979          a LOG_LINK pointing at I3.  We must remove this link.
3980          The simplest way to remove the link is to point it at I1,
3981          which we know will be a NOTE.  */
3982
3983       /* newi2pat is usually a SET here; however, recog_for_combine might
3984          have added some clobbers.  */
3985       if (GET_CODE (newi2pat) == PARALLEL)
3986         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3987       else
3988         ni2dest = SET_DEST (newi2pat);
3989
3990       for (insn = NEXT_INSN (i3);
3991            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
3992                     || insn != BB_HEAD (this_basic_block->next_bb));
3993            insn = NEXT_INSN (insn))
3994         {
3995           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3996             {
3997               FOR_EACH_LOG_LINK (link, insn)
3998                 if (link->insn == i3)
3999                   link->insn = i1;
4000
4001               break;
4002             }
4003         }
4004     }
4005
4006   {
4007     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4008     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4009     rtx midnotes = 0;
4010     int from_luid;
4011     /* Compute which registers we expect to eliminate.  newi2pat may be setting
4012        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
4013        same as i3dest, in which case newi2pat may be setting i1dest.  */
4014     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4015                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4016                    || !i2dest_killed
4017                    ? 0 : i2dest);
4018     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4019                    || (newi2pat && reg_set_p (i1dest, newi2pat))
4020                    || !i1dest_killed
4021                    ? 0 : i1dest);
4022     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4023                    || (newi2pat && reg_set_p (i0dest, newi2pat))
4024                    || !i0dest_killed
4025                    ? 0 : i0dest);
4026
4027     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4028        clear them.  */
4029     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4030     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4031     if (i1)
4032       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4033     if (i0)
4034       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4035
4036     /* Ensure that we do not have something that should not be shared but
4037        occurs multiple times in the new insns.  Check this by first
4038        resetting all the `used' flags and then copying anything is shared.  */
4039
4040     reset_used_flags (i3notes);
4041     reset_used_flags (i2notes);
4042     reset_used_flags (i1notes);
4043     reset_used_flags (i0notes);
4044     reset_used_flags (newpat);
4045     reset_used_flags (newi2pat);
4046     if (undobuf.other_insn)
4047       reset_used_flags (PATTERN (undobuf.other_insn));
4048
4049     i3notes = copy_rtx_if_shared (i3notes);
4050     i2notes = copy_rtx_if_shared (i2notes);
4051     i1notes = copy_rtx_if_shared (i1notes);
4052     i0notes = copy_rtx_if_shared (i0notes);
4053     newpat = copy_rtx_if_shared (newpat);
4054     newi2pat = copy_rtx_if_shared (newi2pat);
4055     if (undobuf.other_insn)
4056       reset_used_flags (PATTERN (undobuf.other_insn));
4057
4058     INSN_CODE (i3) = insn_code_number;
4059     PATTERN (i3) = newpat;
4060
4061     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4062       {
4063         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4064
4065         reset_used_flags (call_usage);
4066         call_usage = copy_rtx (call_usage);
4067
4068         if (substed_i2)
4069           {
4070             /* I2SRC must still be meaningful at this point.  Some splitting
4071                operations can invalidate I2SRC, but those operations do not
4072                apply to calls.  */
4073             gcc_assert (i2src);
4074             replace_rtx (call_usage, i2dest, i2src);
4075           }
4076
4077         if (substed_i1)
4078           replace_rtx (call_usage, i1dest, i1src);
4079         if (substed_i0)
4080           replace_rtx (call_usage, i0dest, i0src);
4081
4082         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4083       }
4084
4085     if (undobuf.other_insn)
4086       INSN_CODE (undobuf.other_insn) = other_code_number;
4087
4088     /* We had one special case above where I2 had more than one set and
4089        we replaced a destination of one of those sets with the destination
4090        of I3.  In that case, we have to update LOG_LINKS of insns later
4091        in this basic block.  Note that this (expensive) case is rare.
4092
4093        Also, in this case, we must pretend that all REG_NOTEs for I2
4094        actually came from I3, so that REG_UNUSED notes from I2 will be
4095        properly handled.  */
4096
4097     if (i3_subst_into_i2)
4098       {
4099         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4100           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4101                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4102               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4103               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4104               && ! find_reg_note (i2, REG_UNUSED,
4105                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4106             for (temp_insn = NEXT_INSN (i2);
4107                  temp_insn
4108                  && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4109                           || BB_HEAD (this_basic_block) != temp_insn);
4110                  temp_insn = NEXT_INSN (temp_insn))
4111               if (temp_insn != i3 && INSN_P (temp_insn))
4112                 FOR_EACH_LOG_LINK (link, temp_insn)
4113                   if (link->insn == i2)
4114                     link->insn = i3;
4115
4116         if (i3notes)
4117           {
4118             rtx link = i3notes;
4119             while (XEXP (link, 1))
4120               link = XEXP (link, 1);
4121             XEXP (link, 1) = i2notes;
4122           }
4123         else
4124           i3notes = i2notes;
4125         i2notes = 0;
4126       }
4127
4128     LOG_LINKS (i3) = NULL;
4129     REG_NOTES (i3) = 0;
4130     LOG_LINKS (i2) = NULL;
4131     REG_NOTES (i2) = 0;
4132
4133     if (newi2pat)
4134       {
4135         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4136           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4137                                this_basic_block);
4138         INSN_CODE (i2) = i2_code_number;
4139         PATTERN (i2) = newi2pat;
4140       }
4141     else
4142       {
4143         if (MAY_HAVE_DEBUG_INSNS && i2src)
4144           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4145                                this_basic_block);
4146         SET_INSN_DELETED (i2);
4147       }
4148
4149     if (i1)
4150       {
4151         LOG_LINKS (i1) = NULL;
4152         REG_NOTES (i1) = 0;
4153         if (MAY_HAVE_DEBUG_INSNS)
4154           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4155                                this_basic_block);
4156         SET_INSN_DELETED (i1);
4157       }
4158
4159     if (i0)
4160       {
4161         LOG_LINKS (i0) = NULL;
4162         REG_NOTES (i0) = 0;
4163         if (MAY_HAVE_DEBUG_INSNS)
4164           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4165                                this_basic_block);
4166         SET_INSN_DELETED (i0);
4167       }
4168
4169     /* Get death notes for everything that is now used in either I3 or
4170        I2 and used to die in a previous insn.  If we built two new
4171        patterns, move from I1 to I2 then I2 to I3 so that we get the
4172        proper movement on registers that I2 modifies.  */
4173
4174     if (i0)
4175       from_luid = DF_INSN_LUID (i0);
4176     else if (i1)
4177       from_luid = DF_INSN_LUID (i1);
4178     else
4179       from_luid = DF_INSN_LUID (i2);
4180     if (newi2pat)
4181       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4182     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4183
4184     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4185     if (i3notes)
4186       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4187                         elim_i2, elim_i1, elim_i0);
4188     if (i2notes)
4189       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4190                         elim_i2, elim_i1, elim_i0);
4191     if (i1notes)
4192       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4193                         elim_i2, elim_i1, elim_i0);
4194     if (i0notes)
4195       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4196                         elim_i2, elim_i1, elim_i0);
4197     if (midnotes)
4198       distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4199                         elim_i2, elim_i1, elim_i0);
4200
4201     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4202        know these are REG_UNUSED and want them to go to the desired insn,
4203        so we always pass it as i3.  */
4204
4205     if (newi2pat && new_i2_notes)
4206       distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4207                         NULL_RTX);
4208
4209     if (new_i3_notes)
4210       distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4211                         NULL_RTX);
4212
4213     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4214        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4215        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4216        in that case, it might delete I2.  Similarly for I2 and I1.
4217        Show an additional death due to the REG_DEAD note we make here.  If
4218        we discard it in distribute_notes, we will decrement it again.  */
4219
4220     if (i3dest_killed)
4221       {
4222         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4223         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4224           distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4225                             elim_i1, elim_i0);
4226         else
4227           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4228                             elim_i2, elim_i1, elim_i0);
4229       }
4230
4231     if (i2dest_in_i2src)
4232       {
4233         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4234         if (newi2pat && reg_set_p (i2dest, newi2pat))
4235           distribute_notes (new_note,  NULL, i2, NULL, NULL_RTX,
4236                             NULL_RTX, NULL_RTX);
4237         else
4238           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4239                             NULL_RTX, NULL_RTX, NULL_RTX);
4240       }
4241
4242     if (i1dest_in_i1src)
4243       {
4244         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4245         if (newi2pat && reg_set_p (i1dest, newi2pat))
4246           distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4247                             NULL_RTX, NULL_RTX);
4248         else
4249           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4250                             NULL_RTX, NULL_RTX, NULL_RTX);
4251       }
4252
4253     if (i0dest_in_i0src)
4254       {
4255         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4256         if (newi2pat && reg_set_p (i0dest, newi2pat))
4257           distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4258                             NULL_RTX, NULL_RTX);
4259         else
4260           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4261                             NULL_RTX, NULL_RTX, NULL_RTX);
4262       }
4263
4264     distribute_links (i3links);
4265     distribute_links (i2links);
4266     distribute_links (i1links);
4267     distribute_links (i0links);
4268
4269     if (REG_P (i2dest))
4270       {
4271         struct insn_link *link;
4272         rtx_insn *i2_insn = 0;
4273         rtx i2_val = 0, set;
4274
4275         /* The insn that used to set this register doesn't exist, and
4276            this life of the register may not exist either.  See if one of
4277            I3's links points to an insn that sets I2DEST.  If it does,
4278            that is now the last known value for I2DEST. If we don't update
4279            this and I2 set the register to a value that depended on its old
4280            contents, we will get confused.  If this insn is used, thing
4281            will be set correctly in combine_instructions.  */
4282         FOR_EACH_LOG_LINK (link, i3)
4283           if ((set = single_set (link->insn)) != 0
4284               && rtx_equal_p (i2dest, SET_DEST (set)))
4285             i2_insn = link->insn, i2_val = SET_SRC (set);
4286
4287         record_value_for_reg (i2dest, i2_insn, i2_val);
4288
4289         /* If the reg formerly set in I2 died only once and that was in I3,
4290            zero its use count so it won't make `reload' do any work.  */
4291         if (! added_sets_2
4292             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4293             && ! i2dest_in_i2src)
4294           INC_REG_N_SETS (REGNO (i2dest), -1);
4295       }
4296
4297     if (i1 && REG_P (i1dest))
4298       {
4299         struct insn_link *link;
4300         rtx_insn *i1_insn = 0;
4301         rtx i1_val = 0, set;
4302
4303         FOR_EACH_LOG_LINK (link, i3)
4304           if ((set = single_set (link->insn)) != 0
4305               && rtx_equal_p (i1dest, SET_DEST (set)))
4306             i1_insn = link->insn, i1_val = SET_SRC (set);
4307
4308         record_value_for_reg (i1dest, i1_insn, i1_val);
4309
4310         if (! added_sets_1 && ! i1dest_in_i1src)
4311           INC_REG_N_SETS (REGNO (i1dest), -1);
4312       }
4313
4314     if (i0 && REG_P (i0dest))
4315       {
4316         struct insn_link *link;
4317         rtx_insn *i0_insn = 0;
4318         rtx i0_val = 0, set;
4319
4320         FOR_EACH_LOG_LINK (link, i3)
4321           if ((set = single_set (link->insn)) != 0
4322               && rtx_equal_p (i0dest, SET_DEST (set)))
4323             i0_insn = link->insn, i0_val = SET_SRC (set);
4324
4325         record_value_for_reg (i0dest, i0_insn, i0_val);
4326
4327         if (! added_sets_0 && ! i0dest_in_i0src)
4328           INC_REG_N_SETS (REGNO (i0dest), -1);
4329       }
4330
4331     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4332        been made to this insn.  The order is important, because newi2pat
4333        can affect nonzero_bits of newpat.  */
4334     if (newi2pat)
4335       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4336     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4337   }
4338
4339   if (undobuf.other_insn != NULL_RTX)
4340     {
4341       if (dump_file)
4342         {
4343           fprintf (dump_file, "modifying other_insn ");
4344           dump_insn_slim (dump_file, undobuf.other_insn);
4345         }
4346       df_insn_rescan (undobuf.other_insn);
4347     }
4348
4349   if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4350     {
4351       if (dump_file)
4352         {
4353           fprintf (dump_file, "modifying insn i0 ");
4354           dump_insn_slim (dump_file, i0);
4355         }
4356       df_insn_rescan (i0);
4357     }
4358
4359   if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4360     {
4361       if (dump_file)
4362         {
4363           fprintf (dump_file, "modifying insn i1 ");
4364           dump_insn_slim (dump_file, i1);
4365         }
4366       df_insn_rescan (i1);
4367     }
4368
4369   if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4370     {
4371       if (dump_file)
4372         {
4373           fprintf (dump_file, "modifying insn i2 ");
4374           dump_insn_slim (dump_file, i2);
4375         }
4376       df_insn_rescan (i2);
4377     }
4378
4379   if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4380     {
4381       if (dump_file)
4382         {
4383           fprintf (dump_file, "modifying insn i3 ");
4384           dump_insn_slim (dump_file, i3);
4385         }
4386       df_insn_rescan (i3);
4387     }
4388
4389   /* Set new_direct_jump_p if a new return or simple jump instruction
4390      has been created.  Adjust the CFG accordingly.  */
4391   if (returnjump_p (i3) || any_uncondjump_p (i3))
4392     {
4393       *new_direct_jump_p = 1;
4394       mark_jump_label (PATTERN (i3), i3, 0);
4395       update_cfg_for_uncondjump (i3);
4396     }
4397
4398   if (undobuf.other_insn != NULL_RTX
4399       && (returnjump_p (undobuf.other_insn)
4400           || any_uncondjump_p (undobuf.other_insn)))
4401     {
4402       *new_direct_jump_p = 1;
4403       update_cfg_for_uncondjump (undobuf.other_insn);
4404     }
4405
4406   /* A noop might also need cleaning up of CFG, if it comes from the
4407      simplification of a jump.  */
4408   if (JUMP_P (i3)
4409       && GET_CODE (newpat) == SET
4410       && SET_SRC (newpat) == pc_rtx
4411       && SET_DEST (newpat) == pc_rtx)
4412     {
4413       *new_direct_jump_p = 1;
4414       update_cfg_for_uncondjump (i3);
4415     }
4416
4417   if (undobuf.other_insn != NULL_RTX
4418       && JUMP_P (undobuf.other_insn)
4419       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4420       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4421       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4422     {
4423       *new_direct_jump_p = 1;
4424       update_cfg_for_uncondjump (undobuf.other_insn);
4425     }
4426
4427   combine_successes++;
4428   undo_commit ();
4429
4430   if (added_links_insn
4431       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4432       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4433     return added_links_insn;
4434   else
4435     return newi2pat ? i2 : i3;
4436 }
4437 \f
4438 /* Undo all the modifications recorded in undobuf.  */
4439
4440 static void
4441 undo_all (void)
4442 {
4443   struct undo *undo, *next;
4444
4445   for (undo = undobuf.undos; undo; undo = next)
4446     {
4447       next = undo->next;
4448       switch (undo->kind)
4449         {
4450         case UNDO_RTX:
4451           *undo->where.r = undo->old_contents.r;
4452           break;
4453         case UNDO_INT:
4454           *undo->where.i = undo->old_contents.i;
4455           break;
4456         case UNDO_MODE:
4457           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4458           break;
4459         case UNDO_LINKS:
4460           *undo->where.l = undo->old_contents.l;
4461           break;
4462         default:
4463           gcc_unreachable ();
4464         }
4465
4466       undo->next = undobuf.frees;
4467       undobuf.frees = undo;
4468     }
4469
4470   undobuf.undos = 0;
4471 }
4472
4473 /* We've committed to accepting the changes we made.  Move all
4474    of the undos to the free list.  */
4475
4476 static void
4477 undo_commit (void)
4478 {
4479   struct undo *undo, *next;
4480
4481   for (undo = undobuf.undos; undo; undo = next)
4482     {
4483       next = undo->next;
4484       undo->next = undobuf.frees;
4485       undobuf.frees = undo;
4486     }
4487   undobuf.undos = 0;
4488 }
4489 \f
4490 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4491    where we have an arithmetic expression and return that point.  LOC will
4492    be inside INSN.
4493
4494    try_combine will call this function to see if an insn can be split into
4495    two insns.  */
4496
4497 static rtx *
4498 find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4499 {
4500   rtx x = *loc;
4501   enum rtx_code code = GET_CODE (x);
4502   rtx *split;
4503   unsigned HOST_WIDE_INT len = 0;
4504   HOST_WIDE_INT pos = 0;
4505   int unsignedp = 0;
4506   rtx inner = NULL_RTX;
4507
4508   /* First special-case some codes.  */
4509   switch (code)
4510     {
4511     case SUBREG:
4512 #ifdef INSN_SCHEDULING
4513       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4514          point.  */
4515       if (MEM_P (SUBREG_REG (x)))
4516         return loc;
4517 #endif
4518       return find_split_point (&SUBREG_REG (x), insn, false);
4519
4520     case MEM:
4521 #ifdef HAVE_lo_sum
4522       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4523          using LO_SUM and HIGH.  */
4524       if (GET_CODE (XEXP (x, 0)) == CONST
4525           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4526         {
4527           machine_mode address_mode = get_address_mode (x);
4528
4529           SUBST (XEXP (x, 0),
4530                  gen_rtx_LO_SUM (address_mode,
4531                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4532                                  XEXP (x, 0)));
4533           return &XEXP (XEXP (x, 0), 0);
4534         }
4535 #endif
4536
4537       /* If we have a PLUS whose second operand is a constant and the
4538          address is not valid, perhaps will can split it up using
4539          the machine-specific way to split large constants.  We use
4540          the first pseudo-reg (one of the virtual regs) as a placeholder;
4541          it will not remain in the result.  */
4542       if (GET_CODE (XEXP (x, 0)) == PLUS
4543           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4544           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4545                                             MEM_ADDR_SPACE (x)))
4546         {
4547           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4548           rtx_insn *seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4549                                                             XEXP (x, 0)),
4550                                                subst_insn);
4551
4552           /* This should have produced two insns, each of which sets our
4553              placeholder.  If the source of the second is a valid address,
4554              we can make put both sources together and make a split point
4555              in the middle.  */
4556
4557           if (seq
4558               && NEXT_INSN (seq) != NULL_RTX
4559               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4560               && NONJUMP_INSN_P (seq)
4561               && GET_CODE (PATTERN (seq)) == SET
4562               && SET_DEST (PATTERN (seq)) == reg
4563               && ! reg_mentioned_p (reg,
4564                                     SET_SRC (PATTERN (seq)))
4565               && NONJUMP_INSN_P (NEXT_INSN (seq))
4566               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4567               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4568               && memory_address_addr_space_p
4569                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4570                     MEM_ADDR_SPACE (x)))
4571             {
4572               rtx src1 = SET_SRC (PATTERN (seq));
4573               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4574
4575               /* Replace the placeholder in SRC2 with SRC1.  If we can
4576                  find where in SRC2 it was placed, that can become our
4577                  split point and we can replace this address with SRC2.
4578                  Just try two obvious places.  */
4579
4580               src2 = replace_rtx (src2, reg, src1);
4581               split = 0;
4582               if (XEXP (src2, 0) == src1)
4583                 split = &XEXP (src2, 0);
4584               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4585                        && XEXP (XEXP (src2, 0), 0) == src1)
4586                 split = &XEXP (XEXP (src2, 0), 0);
4587
4588               if (split)
4589                 {
4590                   SUBST (XEXP (x, 0), src2);
4591                   return split;
4592                 }
4593             }
4594
4595           /* If that didn't work, perhaps the first operand is complex and
4596              needs to be computed separately, so make a split point there.
4597              This will occur on machines that just support REG + CONST
4598              and have a constant moved through some previous computation.  */
4599
4600           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4601                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4602                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4603             return &XEXP (XEXP (x, 0), 0);
4604         }
4605
4606       /* If we have a PLUS whose first operand is complex, try computing it
4607          separately by making a split there.  */
4608       if (GET_CODE (XEXP (x, 0)) == PLUS
4609           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4610                                             MEM_ADDR_SPACE (x))
4611           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4612           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4613                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4614         return &XEXP (XEXP (x, 0), 0);
4615       break;
4616
4617     case SET:
4618 #ifdef HAVE_cc0
4619       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4620          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4621          we need to put the operand into a register.  So split at that
4622          point.  */
4623
4624       if (SET_DEST (x) == cc0_rtx
4625           && GET_CODE (SET_SRC (x)) != COMPARE
4626           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4627           && !OBJECT_P (SET_SRC (x))
4628           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4629                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4630         return &SET_SRC (x);
4631 #endif
4632
4633       /* See if we can split SET_SRC as it stands.  */
4634       split = find_split_point (&SET_SRC (x), insn, true);
4635       if (split && split != &SET_SRC (x))
4636         return split;
4637
4638       /* See if we can split SET_DEST as it stands.  */
4639       split = find_split_point (&SET_DEST (x), insn, false);
4640       if (split && split != &SET_DEST (x))
4641         return split;
4642
4643       /* See if this is a bitfield assignment with everything constant.  If
4644          so, this is an IOR of an AND, so split it into that.  */
4645       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4646           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4647           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4648           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4649           && CONST_INT_P (SET_SRC (x))
4650           && ((INTVAL (XEXP (SET_DEST (x), 1))
4651                + INTVAL (XEXP (SET_DEST (x), 2)))
4652               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4653           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4654         {
4655           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4656           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4657           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4658           rtx dest = XEXP (SET_DEST (x), 0);
4659           machine_mode mode = GET_MODE (dest);
4660           unsigned HOST_WIDE_INT mask
4661             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4662           rtx or_mask;
4663
4664           if (BITS_BIG_ENDIAN)
4665             pos = GET_MODE_PRECISION (mode) - len - pos;
4666
4667           or_mask = gen_int_mode (src << pos, mode);
4668           if (src == mask)
4669             SUBST (SET_SRC (x),
4670                    simplify_gen_binary (IOR, mode, dest, or_mask));
4671           else
4672             {
4673               rtx negmask = gen_int_mode (~(mask << pos), mode);
4674               SUBST (SET_SRC (x),
4675                      simplify_gen_binary (IOR, mode,
4676                                           simplify_gen_binary (AND, mode,
4677                                                                dest, negmask),
4678                                           or_mask));
4679             }
4680
4681           SUBST (SET_DEST (x), dest);
4682
4683           split = find_split_point (&SET_SRC (x), insn, true);
4684           if (split && split != &SET_SRC (x))
4685             return split;
4686         }
4687
4688       /* Otherwise, see if this is an operation that we can split into two.
4689          If so, try to split that.  */
4690       code = GET_CODE (SET_SRC (x));
4691
4692       switch (code)
4693         {
4694         case AND:
4695           /* If we are AND'ing with a large constant that is only a single
4696              bit and the result is only being used in a context where we
4697              need to know if it is zero or nonzero, replace it with a bit
4698              extraction.  This will avoid the large constant, which might
4699              have taken more than one insn to make.  If the constant were
4700              not a valid argument to the AND but took only one insn to make,
4701              this is no worse, but if it took more than one insn, it will
4702              be better.  */
4703
4704           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4705               && REG_P (XEXP (SET_SRC (x), 0))
4706               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4707               && REG_P (SET_DEST (x))
4708               && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
4709               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4710               && XEXP (*split, 0) == SET_DEST (x)
4711               && XEXP (*split, 1) == const0_rtx)
4712             {
4713               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4714                                                 XEXP (SET_SRC (x), 0),
4715                                                 pos, NULL_RTX, 1, 1, 0, 0);
4716               if (extraction != 0)
4717                 {
4718                   SUBST (SET_SRC (x), extraction);
4719                   return find_split_point (loc, insn, false);
4720                 }
4721             }
4722           break;
4723
4724         case NE:
4725           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4726              is known to be on, this can be converted into a NEG of a shift.  */
4727           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4728               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4729               && 1 <= (pos = exact_log2
4730                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4731                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4732             {
4733               machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4734
4735               SUBST (SET_SRC (x),
4736                      gen_rtx_NEG (mode,
4737                                   gen_rtx_LSHIFTRT (mode,
4738                                                     XEXP (SET_SRC (x), 0),
4739                                                     GEN_INT (pos))));
4740
4741               split = find_split_point (&SET_SRC (x), insn, true);
4742               if (split && split != &SET_SRC (x))
4743                 return split;
4744             }
4745           break;
4746
4747         case SIGN_EXTEND:
4748           inner = XEXP (SET_SRC (x), 0);
4749
4750           /* We can't optimize if either mode is a partial integer
4751              mode as we don't know how many bits are significant
4752              in those modes.  */
4753           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4754               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4755             break;
4756
4757           pos = 0;
4758           len = GET_MODE_PRECISION (GET_MODE (inner));
4759           unsignedp = 0;
4760           break;
4761
4762         case SIGN_EXTRACT:
4763         case ZERO_EXTRACT:
4764           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4765               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4766             {
4767               inner = XEXP (SET_SRC (x), 0);
4768               len = INTVAL (XEXP (SET_SRC (x), 1));
4769               pos = INTVAL (XEXP (SET_SRC (x), 2));
4770
4771               if (BITS_BIG_ENDIAN)
4772                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4773               unsignedp = (code == ZERO_EXTRACT);
4774             }
4775           break;
4776
4777         default:
4778           break;
4779         }
4780
4781       if (len && pos >= 0
4782           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4783         {
4784           machine_mode mode = GET_MODE (SET_SRC (x));
4785
4786           /* For unsigned, we have a choice of a shift followed by an
4787              AND or two shifts.  Use two shifts for field sizes where the
4788              constant might be too large.  We assume here that we can
4789              always at least get 8-bit constants in an AND insn, which is
4790              true for every current RISC.  */
4791
4792           if (unsignedp && len <= 8)
4793             {
4794               unsigned HOST_WIDE_INT mask
4795                 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4796               SUBST (SET_SRC (x),
4797                      gen_rtx_AND (mode,
4798                                   gen_rtx_LSHIFTRT
4799                                   (mode, gen_lowpart (mode, inner),
4800                                    GEN_INT (pos)),
4801                                   gen_int_mode (mask, mode)));
4802
4803               split = find_split_point (&SET_SRC (x), insn, true);
4804               if (split && split != &SET_SRC (x))
4805                 return split;
4806             }
4807           else
4808             {
4809               SUBST (SET_SRC (x),
4810                      gen_rtx_fmt_ee
4811                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4812                       gen_rtx_ASHIFT (mode,
4813                                       gen_lowpart (mode, inner),
4814                                       GEN_INT (GET_MODE_PRECISION (mode)
4815                                                - len - pos)),
4816                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4817
4818               split = find_split_point (&SET_SRC (x), insn, true);
4819               if (split && split != &SET_SRC (x))
4820                 return split;
4821             }
4822         }
4823
4824       /* See if this is a simple operation with a constant as the second
4825          operand.  It might be that this constant is out of range and hence
4826          could be used as a split point.  */
4827       if (BINARY_P (SET_SRC (x))
4828           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4829           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4830               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4831                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4832         return &XEXP (SET_SRC (x), 1);
4833
4834       /* Finally, see if this is a simple operation with its first operand
4835          not in a register.  The operation might require this operand in a
4836          register, so return it as a split point.  We can always do this
4837          because if the first operand were another operation, we would have
4838          already found it as a split point.  */
4839       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4840           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4841         return &XEXP (SET_SRC (x), 0);
4842
4843       return 0;
4844
4845     case AND:
4846     case IOR:
4847       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4848          it is better to write this as (not (ior A B)) so we can split it.
4849          Similarly for IOR.  */
4850       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4851         {
4852           SUBST (*loc,
4853                  gen_rtx_NOT (GET_MODE (x),
4854                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4855                                               GET_MODE (x),
4856                                               XEXP (XEXP (x, 0), 0),
4857                                               XEXP (XEXP (x, 1), 0))));
4858           return find_split_point (loc, insn, set_src);
4859         }
4860
4861       /* Many RISC machines have a large set of logical insns.  If the
4862          second operand is a NOT, put it first so we will try to split the
4863          other operand first.  */
4864       if (GET_CODE (XEXP (x, 1)) == NOT)
4865         {
4866           rtx tem = XEXP (x, 0);
4867           SUBST (XEXP (x, 0), XEXP (x, 1));
4868           SUBST (XEXP (x, 1), tem);
4869         }
4870       break;
4871
4872     case PLUS:
4873     case MINUS:
4874       /* Canonicalization can produce (minus A (mult B C)), where C is a
4875          constant.  It may be better to try splitting (plus (mult B -C) A)
4876          instead if this isn't a multiply by a power of two.  */
4877       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4878           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4879           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4880         {
4881           machine_mode mode = GET_MODE (x);
4882           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4883           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4884           SUBST (*loc, gen_rtx_PLUS (mode,
4885                                      gen_rtx_MULT (mode,
4886                                                    XEXP (XEXP (x, 1), 0),
4887                                                    gen_int_mode (other_int,
4888                                                                  mode)),
4889                                      XEXP (x, 0)));
4890           return find_split_point (loc, insn, set_src);
4891         }
4892
4893       /* Split at a multiply-accumulate instruction.  However if this is
4894          the SET_SRC, we likely do not have such an instruction and it's
4895          worthless to try this split.  */
4896       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4897         return loc;
4898
4899     default:
4900       break;
4901     }
4902
4903   /* Otherwise, select our actions depending on our rtx class.  */
4904   switch (GET_RTX_CLASS (code))
4905     {
4906     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4907     case RTX_TERNARY:
4908       split = find_split_point (&XEXP (x, 2), insn, false);
4909       if (split)
4910         return split;
4911       /* ... fall through ...  */
4912     case RTX_BIN_ARITH:
4913     case RTX_COMM_ARITH:
4914     case RTX_COMPARE:
4915     case RTX_COMM_COMPARE:
4916       split = find_split_point (&XEXP (x, 1), insn, false);
4917       if (split)
4918         return split;
4919       /* ... fall through ...  */
4920     case RTX_UNARY:
4921       /* Some machines have (and (shift ...) ...) insns.  If X is not
4922          an AND, but XEXP (X, 0) is, use it as our split point.  */
4923       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4924         return &XEXP (x, 0);
4925
4926       split = find_split_point (&XEXP (x, 0), insn, false);
4927       if (split)
4928         return split;
4929       return loc;
4930
4931     default:
4932       /* Otherwise, we don't have a split point.  */
4933       return 0;
4934     }
4935 }
4936 \f
4937 /* Throughout X, replace FROM with TO, and return the result.
4938    The result is TO if X is FROM;
4939    otherwise the result is X, but its contents may have been modified.
4940    If they were modified, a record was made in undobuf so that
4941    undo_all will (among other things) return X to its original state.
4942
4943    If the number of changes necessary is too much to record to undo,
4944    the excess changes are not made, so the result is invalid.
4945    The changes already made can still be undone.
4946    undobuf.num_undo is incremented for such changes, so by testing that
4947    the caller can tell whether the result is valid.
4948
4949    `n_occurrences' is incremented each time FROM is replaced.
4950
4951    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4952
4953    IN_COND is nonzero if we are at the top level of a condition.
4954
4955    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4956    by copying if `n_occurrences' is nonzero.  */
4957
4958 static rtx
4959 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4960 {
4961   enum rtx_code code = GET_CODE (x);
4962   machine_mode op0_mode = VOIDmode;
4963   const char *fmt;
4964   int len, i;
4965   rtx new_rtx;
4966
4967 /* Two expressions are equal if they are identical copies of a shared
4968    RTX or if they are both registers with the same register number
4969    and mode.  */
4970
4971 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4972   ((X) == (Y)                                           \
4973    || (REG_P (X) && REG_P (Y)   \
4974        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4975
4976   /* Do not substitute into clobbers of regs -- this will never result in
4977      valid RTL.  */
4978   if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
4979     return x;
4980
4981   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4982     {
4983       n_occurrences++;
4984       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4985     }
4986
4987   /* If X and FROM are the same register but different modes, they
4988      will not have been seen as equal above.  However, the log links code
4989      will make a LOG_LINKS entry for that case.  If we do nothing, we
4990      will try to rerecognize our original insn and, when it succeeds,
4991      we will delete the feeding insn, which is incorrect.
4992
4993      So force this insn not to match in this (rare) case.  */
4994   if (! in_dest && code == REG && REG_P (from)
4995       && reg_overlap_mentioned_p (x, from))
4996     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4997
4998   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4999      of which may contain things that can be combined.  */
5000   if (code != MEM && code != LO_SUM && OBJECT_P (x))
5001     return x;
5002
5003   /* It is possible to have a subexpression appear twice in the insn.
5004      Suppose that FROM is a register that appears within TO.
5005      Then, after that subexpression has been scanned once by `subst',
5006      the second time it is scanned, TO may be found.  If we were
5007      to scan TO here, we would find FROM within it and create a
5008      self-referent rtl structure which is completely wrong.  */
5009   if (COMBINE_RTX_EQUAL_P (x, to))
5010     return to;
5011
5012   /* Parallel asm_operands need special attention because all of the
5013      inputs are shared across the arms.  Furthermore, unsharing the
5014      rtl results in recognition failures.  Failure to handle this case
5015      specially can result in circular rtl.
5016
5017      Solve this by doing a normal pass across the first entry of the
5018      parallel, and only processing the SET_DESTs of the subsequent
5019      entries.  Ug.  */
5020
5021   if (code == PARALLEL
5022       && GET_CODE (XVECEXP (x, 0, 0)) == SET
5023       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5024     {
5025       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5026
5027       /* If this substitution failed, this whole thing fails.  */
5028       if (GET_CODE (new_rtx) == CLOBBER
5029           && XEXP (new_rtx, 0) == const0_rtx)
5030         return new_rtx;
5031
5032       SUBST (XVECEXP (x, 0, 0), new_rtx);
5033
5034       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5035         {
5036           rtx dest = SET_DEST (XVECEXP (x, 0, i));
5037
5038           if (!REG_P (dest)
5039               && GET_CODE (dest) != CC0
5040               && GET_CODE (dest) != PC)
5041             {
5042               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5043
5044               /* If this substitution failed, this whole thing fails.  */
5045               if (GET_CODE (new_rtx) == CLOBBER
5046                   && XEXP (new_rtx, 0) == const0_rtx)
5047                 return new_rtx;
5048
5049               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5050             }
5051         }
5052     }
5053   else
5054     {
5055       len = GET_RTX_LENGTH (code);
5056       fmt = GET_RTX_FORMAT (code);
5057
5058       /* We don't need to process a SET_DEST that is a register, CC0,
5059          or PC, so set up to skip this common case.  All other cases
5060          where we want to suppress replacing something inside a
5061          SET_SRC are handled via the IN_DEST operand.  */
5062       if (code == SET
5063           && (REG_P (SET_DEST (x))
5064               || GET_CODE (SET_DEST (x)) == CC0
5065               || GET_CODE (SET_DEST (x)) == PC))
5066         fmt = "ie";
5067
5068       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5069          constant.  */
5070       if (fmt[0] == 'e')
5071         op0_mode = GET_MODE (XEXP (x, 0));
5072
5073       for (i = 0; i < len; i++)
5074         {
5075           if (fmt[i] == 'E')
5076             {
5077               int j;
5078               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5079                 {
5080                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5081                     {
5082                       new_rtx = (unique_copy && n_occurrences
5083                              ? copy_rtx (to) : to);
5084                       n_occurrences++;
5085                     }
5086                   else
5087                     {
5088                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5089                                        unique_copy);
5090
5091                       /* If this substitution failed, this whole thing
5092                          fails.  */
5093                       if (GET_CODE (new_rtx) == CLOBBER
5094                           && XEXP (new_rtx, 0) == const0_rtx)
5095                         return new_rtx;
5096                     }
5097
5098                   SUBST (XVECEXP (x, i, j), new_rtx);
5099                 }
5100             }
5101           else if (fmt[i] == 'e')
5102             {
5103               /* If this is a register being set, ignore it.  */
5104               new_rtx = XEXP (x, i);
5105               if (in_dest
5106                   && i == 0
5107                   && (((code == SUBREG || code == ZERO_EXTRACT)
5108                        && REG_P (new_rtx))
5109                       || code == STRICT_LOW_PART))
5110                 ;
5111
5112               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5113                 {
5114                   /* In general, don't install a subreg involving two
5115                      modes not tieable.  It can worsen register
5116                      allocation, and can even make invalid reload
5117                      insns, since the reg inside may need to be copied
5118                      from in the outside mode, and that may be invalid
5119                      if it is an fp reg copied in integer mode.
5120
5121                      We allow two exceptions to this: It is valid if
5122                      it is inside another SUBREG and the mode of that
5123                      SUBREG and the mode of the inside of TO is
5124                      tieable and it is valid if X is a SET that copies
5125                      FROM to CC0.  */
5126
5127                   if (GET_CODE (to) == SUBREG
5128                       && ! MODES_TIEABLE_P (GET_MODE (to),
5129                                             GET_MODE (SUBREG_REG (to)))
5130                       && ! (code == SUBREG
5131                             && MODES_TIEABLE_P (GET_MODE (x),
5132                                                 GET_MODE (SUBREG_REG (to))))
5133 #ifdef HAVE_cc0
5134                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5135 #endif
5136                       )
5137                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5138
5139                   if (code == SUBREG
5140                       && REG_P (to)
5141                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5142                       && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5143                                                 SUBREG_BYTE (x),
5144                                                 GET_MODE (x)) < 0)
5145                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5146
5147                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5148                   n_occurrences++;
5149                 }
5150               else
5151                 /* If we are in a SET_DEST, suppress most cases unless we
5152                    have gone inside a MEM, in which case we want to
5153                    simplify the address.  We assume here that things that
5154                    are actually part of the destination have their inner
5155                    parts in the first expression.  This is true for SUBREG,
5156                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5157                    things aside from REG and MEM that should appear in a
5158                    SET_DEST.  */
5159                 new_rtx = subst (XEXP (x, i), from, to,
5160                              (((in_dest
5161                                 && (code == SUBREG || code == STRICT_LOW_PART
5162                                     || code == ZERO_EXTRACT))
5163                                || code == SET)
5164                               && i == 0),
5165                                  code == IF_THEN_ELSE && i == 0,
5166                                  unique_copy);
5167
5168               /* If we found that we will have to reject this combination,
5169                  indicate that by returning the CLOBBER ourselves, rather than
5170                  an expression containing it.  This will speed things up as
5171                  well as prevent accidents where two CLOBBERs are considered
5172                  to be equal, thus producing an incorrect simplification.  */
5173
5174               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5175                 return new_rtx;
5176
5177               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5178                 {
5179                   machine_mode mode = GET_MODE (x);
5180
5181                   x = simplify_subreg (GET_MODE (x), new_rtx,
5182                                        GET_MODE (SUBREG_REG (x)),
5183                                        SUBREG_BYTE (x));
5184                   if (! x)
5185                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5186                 }
5187               else if (CONST_SCALAR_INT_P (new_rtx)
5188                        && GET_CODE (x) == ZERO_EXTEND)
5189                 {
5190                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5191                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5192                   gcc_assert (x);
5193                 }
5194               else
5195                 SUBST (XEXP (x, i), new_rtx);
5196             }
5197         }
5198     }
5199
5200   /* Check if we are loading something from the constant pool via float
5201      extension; in this case we would undo compress_float_constant
5202      optimization and degenerate constant load to an immediate value.  */
5203   if (GET_CODE (x) == FLOAT_EXTEND
5204       && MEM_P (XEXP (x, 0))
5205       && MEM_READONLY_P (XEXP (x, 0)))
5206     {
5207       rtx tmp = avoid_constant_pool_reference (x);
5208       if (x != tmp)
5209         return x;
5210     }
5211
5212   /* Try to simplify X.  If the simplification changed the code, it is likely
5213      that further simplification will help, so loop, but limit the number
5214      of repetitions that will be performed.  */
5215
5216   for (i = 0; i < 4; i++)
5217     {
5218       /* If X is sufficiently simple, don't bother trying to do anything
5219          with it.  */
5220       if (code != CONST_INT && code != REG && code != CLOBBER)
5221         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5222
5223       if (GET_CODE (x) == code)
5224         break;
5225
5226       code = GET_CODE (x);
5227
5228       /* We no longer know the original mode of operand 0 since we
5229          have changed the form of X)  */
5230       op0_mode = VOIDmode;
5231     }
5232
5233   return x;
5234 }
5235 \f
5236 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5237    outer level; call `subst' to simplify recursively.  Return the new
5238    expression.
5239
5240    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5241    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5242    of a condition.  */
5243
5244 static rtx
5245 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
5246                       int in_cond)
5247 {
5248   enum rtx_code code = GET_CODE (x);
5249   machine_mode mode = GET_MODE (x);
5250   rtx temp;
5251   int i;
5252
5253   /* If this is a commutative operation, put a constant last and a complex
5254      expression first.  We don't need to do this for comparisons here.  */
5255   if (COMMUTATIVE_ARITH_P (x)
5256       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5257     {
5258       temp = XEXP (x, 0);
5259       SUBST (XEXP (x, 0), XEXP (x, 1));
5260       SUBST (XEXP (x, 1), temp);
5261     }
5262
5263   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5264      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5265      things.  Check for cases where both arms are testing the same
5266      condition.
5267
5268      Don't do anything if all operands are very simple.  */
5269
5270   if ((BINARY_P (x)
5271        && ((!OBJECT_P (XEXP (x, 0))
5272             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5273                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5274            || (!OBJECT_P (XEXP (x, 1))
5275                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5276                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5277       || (UNARY_P (x)
5278           && (!OBJECT_P (XEXP (x, 0))
5279                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5280                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5281     {
5282       rtx cond, true_rtx, false_rtx;
5283
5284       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5285       if (cond != 0
5286           /* If everything is a comparison, what we have is highly unlikely
5287              to be simpler, so don't use it.  */
5288           && ! (COMPARISON_P (x)
5289                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5290         {
5291           rtx cop1 = const0_rtx;
5292           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5293
5294           if (cond_code == NE && COMPARISON_P (cond))
5295             return x;
5296
5297           /* Simplify the alternative arms; this may collapse the true and
5298              false arms to store-flag values.  Be careful to use copy_rtx
5299              here since true_rtx or false_rtx might share RTL with x as a
5300              result of the if_then_else_cond call above.  */
5301           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5302           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5303
5304           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5305              is unlikely to be simpler.  */
5306           if (general_operand (true_rtx, VOIDmode)
5307               && general_operand (false_rtx, VOIDmode))
5308             {
5309               enum rtx_code reversed;
5310
5311               /* Restarting if we generate a store-flag expression will cause
5312                  us to loop.  Just drop through in this case.  */
5313
5314               /* If the result values are STORE_FLAG_VALUE and zero, we can
5315                  just make the comparison operation.  */
5316               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5317                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5318                                              cond, cop1);
5319               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5320                        && ((reversed = reversed_comparison_code_parts
5321                                         (cond_code, cond, cop1, NULL))
5322                            != UNKNOWN))
5323                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5324                                              cond, cop1);
5325
5326               /* Likewise, we can make the negate of a comparison operation
5327                  if the result values are - STORE_FLAG_VALUE and zero.  */
5328               else if (CONST_INT_P (true_rtx)
5329                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5330                        && false_rtx == const0_rtx)
5331                 x = simplify_gen_unary (NEG, mode,
5332                                         simplify_gen_relational (cond_code,
5333                                                                  mode, VOIDmode,
5334                                                                  cond, cop1),
5335                                         mode);
5336               else if (CONST_INT_P (false_rtx)
5337                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5338                        && true_rtx == const0_rtx
5339                        && ((reversed = reversed_comparison_code_parts
5340                                         (cond_code, cond, cop1, NULL))
5341                            != UNKNOWN))
5342                 x = simplify_gen_unary (NEG, mode,
5343                                         simplify_gen_relational (reversed,
5344                                                                  mode, VOIDmode,
5345                                                                  cond, cop1),
5346                                         mode);
5347               else
5348                 return gen_rtx_IF_THEN_ELSE (mode,
5349                                              simplify_gen_relational (cond_code,
5350                                                                       mode,
5351                                                                       VOIDmode,
5352                                                                       cond,
5353                                                                       cop1),
5354                                              true_rtx, false_rtx);
5355
5356               code = GET_CODE (x);
5357               op0_mode = VOIDmode;
5358             }
5359         }
5360     }
5361
5362   /* Try to fold this expression in case we have constants that weren't
5363      present before.  */
5364   temp = 0;
5365   switch (GET_RTX_CLASS (code))
5366     {
5367     case RTX_UNARY:
5368       if (op0_mode == VOIDmode)
5369         op0_mode = GET_MODE (XEXP (x, 0));
5370       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5371       break;
5372     case RTX_COMPARE:
5373     case RTX_COMM_COMPARE:
5374       {
5375         machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5376         if (cmp_mode == VOIDmode)
5377           {
5378             cmp_mode = GET_MODE (XEXP (x, 1));
5379             if (cmp_mode == VOIDmode)
5380               cmp_mode = op0_mode;
5381           }
5382         temp = simplify_relational_operation (code, mode, cmp_mode,
5383                                               XEXP (x, 0), XEXP (x, 1));
5384       }
5385       break;
5386     case RTX_COMM_ARITH:
5387     case RTX_BIN_ARITH:
5388       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5389       break;
5390     case RTX_BITFIELD_OPS:
5391     case RTX_TERNARY:
5392       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5393                                          XEXP (x, 1), XEXP (x, 2));
5394       break;
5395     default:
5396       break;
5397     }
5398
5399   if (temp)
5400     {
5401       x = temp;
5402       code = GET_CODE (temp);
5403       op0_mode = VOIDmode;
5404       mode = GET_MODE (temp);
5405     }
5406
5407   /* First see if we can apply the inverse distributive law.  */
5408   if (code == PLUS || code == MINUS
5409       || code == AND || code == IOR || code == XOR)
5410     {
5411       x = apply_distributive_law (x);
5412       code = GET_CODE (x);
5413       op0_mode = VOIDmode;
5414     }
5415
5416   /* If CODE is an associative operation not otherwise handled, see if we
5417      can associate some operands.  This can win if they are constants or
5418      if they are logically related (i.e. (a & b) & a).  */
5419   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5420        || code == AND || code == IOR || code == XOR
5421        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5422       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5423           || (flag_associative_math && FLOAT_MODE_P (mode))))
5424     {
5425       if (GET_CODE (XEXP (x, 0)) == code)
5426         {
5427           rtx other = XEXP (XEXP (x, 0), 0);
5428           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5429           rtx inner_op1 = XEXP (x, 1);
5430           rtx inner;
5431
5432           /* Make sure we pass the constant operand if any as the second
5433              one if this is a commutative operation.  */
5434           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5435             {
5436               rtx tem = inner_op0;
5437               inner_op0 = inner_op1;
5438               inner_op1 = tem;
5439             }
5440           inner = simplify_binary_operation (code == MINUS ? PLUS
5441                                              : code == DIV ? MULT
5442                                              : code,
5443                                              mode, inner_op0, inner_op1);
5444
5445           /* For commutative operations, try the other pair if that one
5446              didn't simplify.  */
5447           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5448             {
5449               other = XEXP (XEXP (x, 0), 1);
5450               inner = simplify_binary_operation (code, mode,
5451                                                  XEXP (XEXP (x, 0), 0),
5452                                                  XEXP (x, 1));
5453             }
5454
5455           if (inner)
5456             return simplify_gen_binary (code, mode, other, inner);
5457         }
5458     }
5459
5460   /* A little bit of algebraic simplification here.  */
5461   switch (code)
5462     {
5463     case MEM:
5464       /* Ensure that our address has any ASHIFTs converted to MULT in case
5465          address-recognizing predicates are called later.  */
5466       temp = make_compound_operation (XEXP (x, 0), MEM);
5467       SUBST (XEXP (x, 0), temp);
5468       break;
5469
5470     case SUBREG:
5471       if (op0_mode == VOIDmode)
5472         op0_mode = GET_MODE (SUBREG_REG (x));
5473
5474       /* See if this can be moved to simplify_subreg.  */
5475       if (CONSTANT_P (SUBREG_REG (x))
5476           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5477              /* Don't call gen_lowpart if the inner mode
5478                 is VOIDmode and we cannot simplify it, as SUBREG without
5479                 inner mode is invalid.  */
5480           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5481               || gen_lowpart_common (mode, SUBREG_REG (x))))
5482         return gen_lowpart (mode, SUBREG_REG (x));
5483
5484       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5485         break;
5486       {
5487         rtx temp;
5488         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5489                                 SUBREG_BYTE (x));
5490         if (temp)
5491           return temp;
5492
5493         /* If op is known to have all lower bits zero, the result is zero.  */
5494         if (!in_dest
5495             && SCALAR_INT_MODE_P (mode)
5496             && SCALAR_INT_MODE_P (op0_mode)
5497             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5498             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5499             && HWI_COMPUTABLE_MODE_P (op0_mode)
5500             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5501                 & GET_MODE_MASK (mode)) == 0)
5502           return CONST0_RTX (mode);
5503       }
5504
5505       /* Don't change the mode of the MEM if that would change the meaning
5506          of the address.  */
5507       if (MEM_P (SUBREG_REG (x))
5508           && (MEM_VOLATILE_P (SUBREG_REG (x))
5509               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5510                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5511         return gen_rtx_CLOBBER (mode, const0_rtx);
5512
5513       /* Note that we cannot do any narrowing for non-constants since
5514          we might have been counting on using the fact that some bits were
5515          zero.  We now do this in the SET.  */
5516
5517       break;
5518
5519     case NEG:
5520       temp = expand_compound_operation (XEXP (x, 0));
5521
5522       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5523          replaced by (lshiftrt X C).  This will convert
5524          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5525
5526       if (GET_CODE (temp) == ASHIFTRT
5527           && CONST_INT_P (XEXP (temp, 1))
5528           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5529         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5530                                      INTVAL (XEXP (temp, 1)));
5531
5532       /* If X has only a single bit that might be nonzero, say, bit I, convert
5533          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5534          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5535          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5536          or a SUBREG of one since we'd be making the expression more
5537          complex if it was just a register.  */
5538
5539       if (!REG_P (temp)
5540           && ! (GET_CODE (temp) == SUBREG
5541                 && REG_P (SUBREG_REG (temp)))
5542           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5543         {
5544           rtx temp1 = simplify_shift_const
5545             (NULL_RTX, ASHIFTRT, mode,
5546              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5547                                    GET_MODE_PRECISION (mode) - 1 - i),
5548              GET_MODE_PRECISION (mode) - 1 - i);
5549
5550           /* If all we did was surround TEMP with the two shifts, we
5551              haven't improved anything, so don't use it.  Otherwise,
5552              we are better off with TEMP1.  */
5553           if (GET_CODE (temp1) != ASHIFTRT
5554               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5555               || XEXP (XEXP (temp1, 0), 0) != temp)
5556             return temp1;
5557         }
5558       break;
5559
5560     case TRUNCATE:
5561       /* We can't handle truncation to a partial integer mode here
5562          because we don't know the real bitsize of the partial
5563          integer mode.  */
5564       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5565         break;
5566
5567       if (HWI_COMPUTABLE_MODE_P (mode))
5568         SUBST (XEXP (x, 0),
5569                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5570                               GET_MODE_MASK (mode), 0));
5571
5572       /* We can truncate a constant value and return it.  */
5573       if (CONST_INT_P (XEXP (x, 0)))
5574         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5575
5576       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5577          whose value is a comparison can be replaced with a subreg if
5578          STORE_FLAG_VALUE permits.  */
5579       if (HWI_COMPUTABLE_MODE_P (mode)
5580           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5581           && (temp = get_last_value (XEXP (x, 0)))
5582           && COMPARISON_P (temp))
5583         return gen_lowpart (mode, XEXP (x, 0));
5584       break;
5585
5586     case CONST:
5587       /* (const (const X)) can become (const X).  Do it this way rather than
5588          returning the inner CONST since CONST can be shared with a
5589          REG_EQUAL note.  */
5590       if (GET_CODE (XEXP (x, 0)) == CONST)
5591         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5592       break;
5593
5594 #ifdef HAVE_lo_sum
5595     case LO_SUM:
5596       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5597          can add in an offset.  find_split_point will split this address up
5598          again if it doesn't match.  */
5599       if (GET_CODE (XEXP (x, 0)) == HIGH
5600           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5601         return XEXP (x, 1);
5602       break;
5603 #endif
5604
5605     case PLUS:
5606       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5607          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5608          bit-field and can be replaced by either a sign_extend or a
5609          sign_extract.  The `and' may be a zero_extend and the two
5610          <c>, -<c> constants may be reversed.  */
5611       if (GET_CODE (XEXP (x, 0)) == XOR
5612           && CONST_INT_P (XEXP (x, 1))
5613           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5614           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5615           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5616               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5617           && HWI_COMPUTABLE_MODE_P (mode)
5618           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5619                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5620                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5621                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5622               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5623                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5624                       == (unsigned int) i + 1))))
5625         return simplify_shift_const
5626           (NULL_RTX, ASHIFTRT, mode,
5627            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5628                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5629                                  GET_MODE_PRECISION (mode) - (i + 1)),
5630            GET_MODE_PRECISION (mode) - (i + 1));
5631
5632       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5633          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5634          the bitsize of the mode - 1.  This allows simplification of
5635          "a = (b & 8) == 0;"  */
5636       if (XEXP (x, 1) == constm1_rtx
5637           && !REG_P (XEXP (x, 0))
5638           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5639                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5640           && nonzero_bits (XEXP (x, 0), mode) == 1)
5641         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5642            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5643                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5644                                  GET_MODE_PRECISION (mode) - 1),
5645            GET_MODE_PRECISION (mode) - 1);
5646
5647       /* If we are adding two things that have no bits in common, convert
5648          the addition into an IOR.  This will often be further simplified,
5649          for example in cases like ((a & 1) + (a & 2)), which can
5650          become a & 3.  */
5651
5652       if (HWI_COMPUTABLE_MODE_P (mode)
5653           && (nonzero_bits (XEXP (x, 0), mode)
5654               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5655         {
5656           /* Try to simplify the expression further.  */
5657           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5658           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5659
5660           /* If we could, great.  If not, do not go ahead with the IOR
5661              replacement, since PLUS appears in many special purpose
5662              address arithmetic instructions.  */
5663           if (GET_CODE (temp) != CLOBBER
5664               && (GET_CODE (temp) != IOR
5665                   || ((XEXP (temp, 0) != XEXP (x, 0)
5666                        || XEXP (temp, 1) != XEXP (x, 1))
5667                       && (XEXP (temp, 0) != XEXP (x, 1)
5668                           || XEXP (temp, 1) != XEXP (x, 0)))))
5669             return temp;
5670         }
5671       break;
5672
5673     case MINUS:
5674       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5675          (and <foo> (const_int pow2-1))  */
5676       if (GET_CODE (XEXP (x, 1)) == AND
5677           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5678           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5679           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5680         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5681                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5682       break;
5683
5684     case MULT:
5685       /* If we have (mult (plus A B) C), apply the distributive law and then
5686          the inverse distributive law to see if things simplify.  This
5687          occurs mostly in addresses, often when unrolling loops.  */
5688
5689       if (GET_CODE (XEXP (x, 0)) == PLUS)
5690         {
5691           rtx result = distribute_and_simplify_rtx (x, 0);
5692           if (result)
5693             return result;
5694         }
5695
5696       /* Try simplify a*(b/c) as (a*b)/c.  */
5697       if (FLOAT_MODE_P (mode) && flag_associative_math
5698           && GET_CODE (XEXP (x, 0)) == DIV)
5699         {
5700           rtx tem = simplify_binary_operation (MULT, mode,
5701                                                XEXP (XEXP (x, 0), 0),
5702                                                XEXP (x, 1));
5703           if (tem)
5704             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5705         }
5706       break;
5707
5708     case UDIV:
5709       /* If this is a divide by a power of two, treat it as a shift if
5710          its first operand is a shift.  */
5711       if (CONST_INT_P (XEXP (x, 1))
5712           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5713           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5714               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5715               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5716               || GET_CODE (XEXP (x, 0)) == ROTATE
5717               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5718         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5719       break;
5720
5721     case EQ:  case NE:
5722     case GT:  case GTU:  case GE:  case GEU:
5723     case LT:  case LTU:  case LE:  case LEU:
5724     case UNEQ:  case LTGT:
5725     case UNGT:  case UNGE:
5726     case UNLT:  case UNLE:
5727     case UNORDERED: case ORDERED:
5728       /* If the first operand is a condition code, we can't do anything
5729          with it.  */
5730       if (GET_CODE (XEXP (x, 0)) == COMPARE
5731           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5732               && ! CC0_P (XEXP (x, 0))))
5733         {
5734           rtx op0 = XEXP (x, 0);
5735           rtx op1 = XEXP (x, 1);
5736           enum rtx_code new_code;
5737
5738           if (GET_CODE (op0) == COMPARE)
5739             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5740
5741           /* Simplify our comparison, if possible.  */
5742           new_code = simplify_comparison (code, &op0, &op1);
5743
5744           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5745              if only the low-order bit is possibly nonzero in X (such as when
5746              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5747              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5748              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5749              (plus X 1).
5750
5751              Remove any ZERO_EXTRACT we made when thinking this was a
5752              comparison.  It may now be simpler to use, e.g., an AND.  If a
5753              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5754              the call to make_compound_operation in the SET case.
5755
5756              Don't apply these optimizations if the caller would
5757              prefer a comparison rather than a value.
5758              E.g., for the condition in an IF_THEN_ELSE most targets need
5759              an explicit comparison.  */
5760
5761           if (in_cond)
5762             ;
5763
5764           else if (STORE_FLAG_VALUE == 1
5765               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5766               && op1 == const0_rtx
5767               && mode == GET_MODE (op0)
5768               && nonzero_bits (op0, mode) == 1)
5769             return gen_lowpart (mode,
5770                                 expand_compound_operation (op0));
5771
5772           else if (STORE_FLAG_VALUE == 1
5773                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5774                    && op1 == const0_rtx
5775                    && mode == GET_MODE (op0)
5776                    && (num_sign_bit_copies (op0, mode)
5777                        == GET_MODE_PRECISION (mode)))
5778             {
5779               op0 = expand_compound_operation (op0);
5780               return simplify_gen_unary (NEG, mode,
5781                                          gen_lowpart (mode, op0),
5782                                          mode);
5783             }
5784
5785           else if (STORE_FLAG_VALUE == 1
5786                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5787                    && op1 == const0_rtx
5788                    && mode == GET_MODE (op0)
5789                    && nonzero_bits (op0, mode) == 1)
5790             {
5791               op0 = expand_compound_operation (op0);
5792               return simplify_gen_binary (XOR, mode,
5793                                           gen_lowpart (mode, op0),
5794                                           const1_rtx);
5795             }
5796
5797           else if (STORE_FLAG_VALUE == 1
5798                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5799                    && op1 == const0_rtx
5800                    && mode == GET_MODE (op0)
5801                    && (num_sign_bit_copies (op0, mode)
5802                        == GET_MODE_PRECISION (mode)))
5803             {
5804               op0 = expand_compound_operation (op0);
5805               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5806             }
5807
5808           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5809              those above.  */
5810           if (in_cond)
5811             ;
5812
5813           else if (STORE_FLAG_VALUE == -1
5814               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5815               && op1 == const0_rtx
5816               && (num_sign_bit_copies (op0, mode)
5817                   == GET_MODE_PRECISION (mode)))
5818             return gen_lowpart (mode,
5819                                 expand_compound_operation (op0));
5820
5821           else if (STORE_FLAG_VALUE == -1
5822                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5823                    && op1 == const0_rtx
5824                    && mode == GET_MODE (op0)
5825                    && nonzero_bits (op0, mode) == 1)
5826             {
5827               op0 = expand_compound_operation (op0);
5828               return simplify_gen_unary (NEG, mode,
5829                                          gen_lowpart (mode, op0),
5830                                          mode);
5831             }
5832
5833           else if (STORE_FLAG_VALUE == -1
5834                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5835                    && op1 == const0_rtx
5836                    && mode == GET_MODE (op0)
5837                    && (num_sign_bit_copies (op0, mode)
5838                        == GET_MODE_PRECISION (mode)))
5839             {
5840               op0 = expand_compound_operation (op0);
5841               return simplify_gen_unary (NOT, mode,
5842                                          gen_lowpart (mode, op0),
5843                                          mode);
5844             }
5845
5846           /* If X is 0/1, (eq X 0) is X-1.  */
5847           else if (STORE_FLAG_VALUE == -1
5848                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5849                    && op1 == const0_rtx
5850                    && mode == GET_MODE (op0)
5851                    && nonzero_bits (op0, mode) == 1)
5852             {
5853               op0 = expand_compound_operation (op0);
5854               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5855             }
5856
5857           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5858              one bit that might be nonzero, we can convert (ne x 0) to
5859              (ashift x c) where C puts the bit in the sign bit.  Remove any
5860              AND with STORE_FLAG_VALUE when we are done, since we are only
5861              going to test the sign bit.  */
5862           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5863               && HWI_COMPUTABLE_MODE_P (mode)
5864               && val_signbit_p (mode, STORE_FLAG_VALUE)
5865               && op1 == const0_rtx
5866               && mode == GET_MODE (op0)
5867               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5868             {
5869               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5870                                         expand_compound_operation (op0),
5871                                         GET_MODE_PRECISION (mode) - 1 - i);
5872               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5873                 return XEXP (x, 0);
5874               else
5875                 return x;
5876             }
5877
5878           /* If the code changed, return a whole new comparison.
5879              We also need to avoid using SUBST in cases where
5880              simplify_comparison has widened a comparison with a CONST_INT,
5881              since in that case the wider CONST_INT may fail the sanity
5882              checks in do_SUBST.  */
5883           if (new_code != code
5884               || (CONST_INT_P (op1)
5885                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5886                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5887             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5888
5889           /* Otherwise, keep this operation, but maybe change its operands.
5890              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5891           SUBST (XEXP (x, 0), op0);
5892           SUBST (XEXP (x, 1), op1);
5893         }
5894       break;
5895
5896     case IF_THEN_ELSE:
5897       return simplify_if_then_else (x);
5898
5899     case ZERO_EXTRACT:
5900     case SIGN_EXTRACT:
5901     case ZERO_EXTEND:
5902     case SIGN_EXTEND:
5903       /* If we are processing SET_DEST, we are done.  */
5904       if (in_dest)
5905         return x;
5906
5907       return expand_compound_operation (x);
5908
5909     case SET:
5910       return simplify_set (x);
5911
5912     case AND:
5913     case IOR:
5914       return simplify_logical (x);
5915
5916     case ASHIFT:
5917     case LSHIFTRT:
5918     case ASHIFTRT:
5919     case ROTATE:
5920     case ROTATERT:
5921       /* If this is a shift by a constant amount, simplify it.  */
5922       if (CONST_INT_P (XEXP (x, 1)))
5923         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5924                                      INTVAL (XEXP (x, 1)));
5925
5926       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5927         SUBST (XEXP (x, 1),
5928                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5929                               ((unsigned HOST_WIDE_INT) 1
5930                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5931                               - 1,
5932                               0));
5933       break;
5934
5935     default:
5936       break;
5937     }
5938
5939   return x;
5940 }
5941 \f
5942 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5943
5944 static rtx
5945 simplify_if_then_else (rtx x)
5946 {
5947   machine_mode mode = GET_MODE (x);
5948   rtx cond = XEXP (x, 0);
5949   rtx true_rtx = XEXP (x, 1);
5950   rtx false_rtx = XEXP (x, 2);
5951   enum rtx_code true_code = GET_CODE (cond);
5952   int comparison_p = COMPARISON_P (cond);
5953   rtx temp;
5954   int i;
5955   enum rtx_code false_code;
5956   rtx reversed;
5957
5958   /* Simplify storing of the truth value.  */
5959   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5960     return simplify_gen_relational (true_code, mode, VOIDmode,
5961                                     XEXP (cond, 0), XEXP (cond, 1));
5962
5963   /* Also when the truth value has to be reversed.  */
5964   if (comparison_p
5965       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5966       && (reversed = reversed_comparison (cond, mode)))
5967     return reversed;
5968
5969   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5970      in it is being compared against certain values.  Get the true and false
5971      comparisons and see if that says anything about the value of each arm.  */
5972
5973   if (comparison_p
5974       && ((false_code = reversed_comparison_code (cond, NULL))
5975           != UNKNOWN)
5976       && REG_P (XEXP (cond, 0)))
5977     {
5978       HOST_WIDE_INT nzb;
5979       rtx from = XEXP (cond, 0);
5980       rtx true_val = XEXP (cond, 1);
5981       rtx false_val = true_val;
5982       int swapped = 0;
5983
5984       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5985
5986       if (false_code == EQ)
5987         {
5988           swapped = 1, true_code = EQ, false_code = NE;
5989           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5990         }
5991
5992       /* If we are comparing against zero and the expression being tested has
5993          only a single bit that might be nonzero, that is its value when it is
5994          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5995
5996       if (true_code == EQ && true_val == const0_rtx
5997           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5998         {
5999           false_code = EQ;
6000           false_val = gen_int_mode (nzb, GET_MODE (from));
6001         }
6002       else if (true_code == EQ && true_val == const0_rtx
6003                && (num_sign_bit_copies (from, GET_MODE (from))
6004                    == GET_MODE_PRECISION (GET_MODE (from))))
6005         {
6006           false_code = EQ;
6007           false_val = constm1_rtx;
6008         }
6009
6010       /* Now simplify an arm if we know the value of the register in the
6011          branch and it is used in the arm.  Be careful due to the potential
6012          of locally-shared RTL.  */
6013
6014       if (reg_mentioned_p (from, true_rtx))
6015         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6016                                       from, true_val),
6017                           pc_rtx, pc_rtx, 0, 0, 0);
6018       if (reg_mentioned_p (from, false_rtx))
6019         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6020                                    from, false_val),
6021                            pc_rtx, pc_rtx, 0, 0, 0);
6022
6023       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6024       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6025
6026       true_rtx = XEXP (x, 1);
6027       false_rtx = XEXP (x, 2);
6028       true_code = GET_CODE (cond);
6029     }
6030
6031   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6032      reversed, do so to avoid needing two sets of patterns for
6033      subtract-and-branch insns.  Similarly if we have a constant in the true
6034      arm, the false arm is the same as the first operand of the comparison, or
6035      the false arm is more complicated than the true arm.  */
6036
6037   if (comparison_p
6038       && reversed_comparison_code (cond, NULL) != UNKNOWN
6039       && (true_rtx == pc_rtx
6040           || (CONSTANT_P (true_rtx)
6041               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6042           || true_rtx == const0_rtx
6043           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6044           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6045               && !OBJECT_P (false_rtx))
6046           || reg_mentioned_p (true_rtx, false_rtx)
6047           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6048     {
6049       true_code = reversed_comparison_code (cond, NULL);
6050       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6051       SUBST (XEXP (x, 1), false_rtx);
6052       SUBST (XEXP (x, 2), true_rtx);
6053
6054       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6055       cond = XEXP (x, 0);
6056
6057       /* It is possible that the conditional has been simplified out.  */
6058       true_code = GET_CODE (cond);
6059       comparison_p = COMPARISON_P (cond);
6060     }
6061
6062   /* If the two arms are identical, we don't need the comparison.  */
6063
6064   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6065     return true_rtx;
6066
6067   /* Convert a == b ? b : a to "a".  */
6068   if (true_code == EQ && ! side_effects_p (cond)
6069       && !HONOR_NANS (mode)
6070       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6071       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6072     return false_rtx;
6073   else if (true_code == NE && ! side_effects_p (cond)
6074            && !HONOR_NANS (mode)
6075            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6076            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6077     return true_rtx;
6078
6079   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6080
6081   if (GET_MODE_CLASS (mode) == MODE_INT
6082       && comparison_p
6083       && XEXP (cond, 1) == const0_rtx
6084       && GET_CODE (false_rtx) == NEG
6085       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6086       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6087       && ! side_effects_p (true_rtx))
6088     switch (true_code)
6089       {
6090       case GT:
6091       case GE:
6092         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6093       case LT:
6094       case LE:
6095         return
6096           simplify_gen_unary (NEG, mode,
6097                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6098                               mode);
6099       default:
6100         break;
6101       }
6102
6103   /* Look for MIN or MAX.  */
6104
6105   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6106       && comparison_p
6107       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6108       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6109       && ! side_effects_p (cond))
6110     switch (true_code)
6111       {
6112       case GE:
6113       case GT:
6114         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6115       case LE:
6116       case LT:
6117         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6118       case GEU:
6119       case GTU:
6120         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6121       case LEU:
6122       case LTU:
6123         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6124       default:
6125         break;
6126       }
6127
6128   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6129      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6130      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6131      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6132      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6133      neither 1 or -1, but it isn't worth checking for.  */
6134
6135   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6136       && comparison_p
6137       && GET_MODE_CLASS (mode) == MODE_INT
6138       && ! side_effects_p (x))
6139     {
6140       rtx t = make_compound_operation (true_rtx, SET);
6141       rtx f = make_compound_operation (false_rtx, SET);
6142       rtx cond_op0 = XEXP (cond, 0);
6143       rtx cond_op1 = XEXP (cond, 1);
6144       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6145       machine_mode m = mode;
6146       rtx z = 0, c1 = NULL_RTX;
6147
6148       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6149            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6150            || GET_CODE (t) == ASHIFT
6151            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6152           && rtx_equal_p (XEXP (t, 0), f))
6153         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6154
6155       /* If an identity-zero op is commutative, check whether there
6156          would be a match if we swapped the operands.  */
6157       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6158                 || GET_CODE (t) == XOR)
6159                && rtx_equal_p (XEXP (t, 1), f))
6160         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6161       else if (GET_CODE (t) == SIGN_EXTEND
6162                && (GET_CODE (XEXP (t, 0)) == PLUS
6163                    || GET_CODE (XEXP (t, 0)) == MINUS
6164                    || GET_CODE (XEXP (t, 0)) == IOR
6165                    || GET_CODE (XEXP (t, 0)) == XOR
6166                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6167                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6168                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6169                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6170                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6171                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6172                && (num_sign_bit_copies (f, GET_MODE (f))
6173                    > (unsigned int)
6174                      (GET_MODE_PRECISION (mode)
6175                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6176         {
6177           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6178           extend_op = SIGN_EXTEND;
6179           m = GET_MODE (XEXP (t, 0));
6180         }
6181       else if (GET_CODE (t) == SIGN_EXTEND
6182                && (GET_CODE (XEXP (t, 0)) == PLUS
6183                    || GET_CODE (XEXP (t, 0)) == IOR
6184                    || GET_CODE (XEXP (t, 0)) == XOR)
6185                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6186                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6187                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6188                && (num_sign_bit_copies (f, GET_MODE (f))
6189                    > (unsigned int)
6190                      (GET_MODE_PRECISION (mode)
6191                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6192         {
6193           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6194           extend_op = SIGN_EXTEND;
6195           m = GET_MODE (XEXP (t, 0));
6196         }
6197       else if (GET_CODE (t) == ZERO_EXTEND
6198                && (GET_CODE (XEXP (t, 0)) == PLUS
6199                    || GET_CODE (XEXP (t, 0)) == MINUS
6200                    || GET_CODE (XEXP (t, 0)) == IOR
6201                    || GET_CODE (XEXP (t, 0)) == XOR
6202                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6203                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6204                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6205                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6206                && HWI_COMPUTABLE_MODE_P (mode)
6207                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6208                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6209                && ((nonzero_bits (f, GET_MODE (f))
6210                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6211                    == 0))
6212         {
6213           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6214           extend_op = ZERO_EXTEND;
6215           m = GET_MODE (XEXP (t, 0));
6216         }
6217       else if (GET_CODE (t) == ZERO_EXTEND
6218                && (GET_CODE (XEXP (t, 0)) == PLUS
6219                    || GET_CODE (XEXP (t, 0)) == IOR
6220                    || GET_CODE (XEXP (t, 0)) == XOR)
6221                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6222                && HWI_COMPUTABLE_MODE_P (mode)
6223                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6224                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6225                && ((nonzero_bits (f, GET_MODE (f))
6226                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6227                    == 0))
6228         {
6229           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6230           extend_op = ZERO_EXTEND;
6231           m = GET_MODE (XEXP (t, 0));
6232         }
6233
6234       if (z)
6235         {
6236           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6237                                                  cond_op0, cond_op1),
6238                         pc_rtx, pc_rtx, 0, 0, 0);
6239           temp = simplify_gen_binary (MULT, m, temp,
6240                                       simplify_gen_binary (MULT, m, c1,
6241                                                            const_true_rtx));
6242           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6243           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6244
6245           if (extend_op != UNKNOWN)
6246             temp = simplify_gen_unary (extend_op, mode, temp, m);
6247
6248           return temp;
6249         }
6250     }
6251
6252   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6253      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6254      negation of a single bit, we can convert this operation to a shift.  We
6255      can actually do this more generally, but it doesn't seem worth it.  */
6256
6257   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6258       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6259       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6260            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6261           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6262                == GET_MODE_PRECISION (mode))
6263               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6264     return
6265       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6266                             gen_lowpart (mode, XEXP (cond, 0)), i);
6267
6268   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6269   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6270       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6271       && GET_MODE (XEXP (cond, 0)) == mode
6272       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6273           == nonzero_bits (XEXP (cond, 0), mode)
6274       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6275     return XEXP (cond, 0);
6276
6277   return x;
6278 }
6279 \f
6280 /* Simplify X, a SET expression.  Return the new expression.  */
6281
6282 static rtx
6283 simplify_set (rtx x)
6284 {
6285   rtx src = SET_SRC (x);
6286   rtx dest = SET_DEST (x);
6287   machine_mode mode
6288     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6289   rtx_insn *other_insn;
6290   rtx *cc_use;
6291
6292   /* (set (pc) (return)) gets written as (return).  */
6293   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6294     return src;
6295
6296   /* Now that we know for sure which bits of SRC we are using, see if we can
6297      simplify the expression for the object knowing that we only need the
6298      low-order bits.  */
6299
6300   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6301     {
6302       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6303       SUBST (SET_SRC (x), src);
6304     }
6305
6306   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6307      the comparison result and try to simplify it unless we already have used
6308      undobuf.other_insn.  */
6309   if ((GET_MODE_CLASS (mode) == MODE_CC
6310        || GET_CODE (src) == COMPARE
6311        || CC0_P (dest))
6312       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6313       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6314       && COMPARISON_P (*cc_use)
6315       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6316     {
6317       enum rtx_code old_code = GET_CODE (*cc_use);
6318       enum rtx_code new_code;
6319       rtx op0, op1, tmp;
6320       int other_changed = 0;
6321       rtx inner_compare = NULL_RTX;
6322       machine_mode compare_mode = GET_MODE (dest);
6323
6324       if (GET_CODE (src) == COMPARE)
6325         {
6326           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6327           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6328             {
6329               inner_compare = op0;
6330               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6331             }
6332         }
6333       else
6334         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6335
6336       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6337                                            op0, op1);
6338       if (!tmp)
6339         new_code = old_code;
6340       else if (!CONSTANT_P (tmp))
6341         {
6342           new_code = GET_CODE (tmp);
6343           op0 = XEXP (tmp, 0);
6344           op1 = XEXP (tmp, 1);
6345         }
6346       else
6347         {
6348           rtx pat = PATTERN (other_insn);
6349           undobuf.other_insn = other_insn;
6350           SUBST (*cc_use, tmp);
6351
6352           /* Attempt to simplify CC user.  */
6353           if (GET_CODE (pat) == SET)
6354             {
6355               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6356               if (new_rtx != NULL_RTX)
6357                 SUBST (SET_SRC (pat), new_rtx);
6358             }
6359
6360           /* Convert X into a no-op move.  */
6361           SUBST (SET_DEST (x), pc_rtx);
6362           SUBST (SET_SRC (x), pc_rtx);
6363           return x;
6364         }
6365
6366       /* Simplify our comparison, if possible.  */
6367       new_code = simplify_comparison (new_code, &op0, &op1);
6368
6369 #ifdef SELECT_CC_MODE
6370       /* If this machine has CC modes other than CCmode, check to see if we
6371          need to use a different CC mode here.  */
6372       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6373         compare_mode = GET_MODE (op0);
6374       else if (inner_compare
6375                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6376                && new_code == old_code
6377                && op0 == XEXP (inner_compare, 0)
6378                && op1 == XEXP (inner_compare, 1))
6379         compare_mode = GET_MODE (inner_compare);
6380       else
6381         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6382
6383 #ifndef HAVE_cc0
6384       /* If the mode changed, we have to change SET_DEST, the mode in the
6385          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6386          a hard register, just build new versions with the proper mode.  If it
6387          is a pseudo, we lose unless it is only time we set the pseudo, in
6388          which case we can safely change its mode.  */
6389       if (compare_mode != GET_MODE (dest))
6390         {
6391           if (can_change_dest_mode (dest, 0, compare_mode))
6392             {
6393               unsigned int regno = REGNO (dest);
6394               rtx new_dest;
6395
6396               if (regno < FIRST_PSEUDO_REGISTER)
6397                 new_dest = gen_rtx_REG (compare_mode, regno);
6398               else
6399                 {
6400                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6401                   new_dest = regno_reg_rtx[regno];
6402                 }
6403
6404               SUBST (SET_DEST (x), new_dest);
6405               SUBST (XEXP (*cc_use, 0), new_dest);
6406               other_changed = 1;
6407
6408               dest = new_dest;
6409             }
6410         }
6411 #endif  /* cc0 */
6412 #endif  /* SELECT_CC_MODE */
6413
6414       /* If the code changed, we have to build a new comparison in
6415          undobuf.other_insn.  */
6416       if (new_code != old_code)
6417         {
6418           int other_changed_previously = other_changed;
6419           unsigned HOST_WIDE_INT mask;
6420           rtx old_cc_use = *cc_use;
6421
6422           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6423                                           dest, const0_rtx));
6424           other_changed = 1;
6425
6426           /* If the only change we made was to change an EQ into an NE or
6427              vice versa, OP0 has only one bit that might be nonzero, and OP1
6428              is zero, check if changing the user of the condition code will
6429              produce a valid insn.  If it won't, we can keep the original code
6430              in that insn by surrounding our operation with an XOR.  */
6431
6432           if (((old_code == NE && new_code == EQ)
6433                || (old_code == EQ && new_code == NE))
6434               && ! other_changed_previously && op1 == const0_rtx
6435               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6436               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6437             {
6438               rtx pat = PATTERN (other_insn), note = 0;
6439
6440               if ((recog_for_combine (&pat, other_insn, &note) < 0
6441                    && ! check_asm_operands (pat)))
6442                 {
6443                   *cc_use = old_cc_use;
6444                   other_changed = 0;
6445
6446                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6447                                              gen_int_mode (mask,
6448                                                            GET_MODE (op0)));
6449                 }
6450             }
6451         }
6452
6453       if (other_changed)
6454         undobuf.other_insn = other_insn;
6455
6456       /* Otherwise, if we didn't previously have a COMPARE in the
6457          correct mode, we need one.  */
6458       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6459         {
6460           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6461           src = SET_SRC (x);
6462         }
6463       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6464         {
6465           SUBST (SET_SRC (x), op0);
6466           src = SET_SRC (x);
6467         }
6468       /* Otherwise, update the COMPARE if needed.  */
6469       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6470         {
6471           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6472           src = SET_SRC (x);
6473         }
6474     }
6475   else
6476     {
6477       /* Get SET_SRC in a form where we have placed back any
6478          compound expressions.  Then do the checks below.  */
6479       src = make_compound_operation (src, SET);
6480       SUBST (SET_SRC (x), src);
6481     }
6482
6483   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6484      and X being a REG or (subreg (reg)), we may be able to convert this to
6485      (set (subreg:m2 x) (op)).
6486
6487      We can always do this if M1 is narrower than M2 because that means that
6488      we only care about the low bits of the result.
6489
6490      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6491      perform a narrower operation than requested since the high-order bits will
6492      be undefined.  On machine where it is defined, this transformation is safe
6493      as long as M1 and M2 have the same number of words.  */
6494
6495   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6496       && !OBJECT_P (SUBREG_REG (src))
6497       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6498            / UNITS_PER_WORD)
6499           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6500                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6501 #ifndef WORD_REGISTER_OPERATIONS
6502       && (GET_MODE_SIZE (GET_MODE (src))
6503         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6504 #endif
6505 #ifdef CANNOT_CHANGE_MODE_CLASS
6506       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6507             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6508                                          GET_MODE (SUBREG_REG (src)),
6509                                          GET_MODE (src)))
6510 #endif
6511       && (REG_P (dest)
6512           || (GET_CODE (dest) == SUBREG
6513               && REG_P (SUBREG_REG (dest)))))
6514     {
6515       SUBST (SET_DEST (x),
6516              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6517                                       dest));
6518       SUBST (SET_SRC (x), SUBREG_REG (src));
6519
6520       src = SET_SRC (x), dest = SET_DEST (x);
6521     }
6522
6523 #ifdef HAVE_cc0
6524   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6525      in SRC.  */
6526   if (dest == cc0_rtx
6527       && GET_CODE (src) == SUBREG
6528       && subreg_lowpart_p (src)
6529       && (GET_MODE_PRECISION (GET_MODE (src))
6530           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6531     {
6532       rtx inner = SUBREG_REG (src);
6533       machine_mode inner_mode = GET_MODE (inner);
6534
6535       /* Here we make sure that we don't have a sign bit on.  */
6536       if (val_signbit_known_clear_p (GET_MODE (src),
6537                                      nonzero_bits (inner, inner_mode)))
6538         {
6539           SUBST (SET_SRC (x), inner);
6540           src = SET_SRC (x);
6541         }
6542     }
6543 #endif
6544
6545 #ifdef LOAD_EXTEND_OP
6546   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6547      would require a paradoxical subreg.  Replace the subreg with a
6548      zero_extend to avoid the reload that would otherwise be required.  */
6549
6550   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6551       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6552       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6553       && SUBREG_BYTE (src) == 0
6554       && paradoxical_subreg_p (src)
6555       && MEM_P (SUBREG_REG (src)))
6556     {
6557       SUBST (SET_SRC (x),
6558              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6559                             GET_MODE (src), SUBREG_REG (src)));
6560
6561       src = SET_SRC (x);
6562     }
6563 #endif
6564
6565   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6566      are comparing an item known to be 0 or -1 against 0, use a logical
6567      operation instead. Check for one of the arms being an IOR of the other
6568      arm with some value.  We compute three terms to be IOR'ed together.  In
6569      practice, at most two will be nonzero.  Then we do the IOR's.  */
6570
6571   if (GET_CODE (dest) != PC
6572       && GET_CODE (src) == IF_THEN_ELSE
6573       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6574       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6575       && XEXP (XEXP (src, 0), 1) == const0_rtx
6576       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6577 #ifdef HAVE_conditional_move
6578       && ! can_conditionally_move_p (GET_MODE (src))
6579 #endif
6580       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6581                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6582           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6583       && ! side_effects_p (src))
6584     {
6585       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6586                       ? XEXP (src, 1) : XEXP (src, 2));
6587       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6588                    ? XEXP (src, 2) : XEXP (src, 1));
6589       rtx term1 = const0_rtx, term2, term3;
6590
6591       if (GET_CODE (true_rtx) == IOR
6592           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6593         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6594       else if (GET_CODE (true_rtx) == IOR
6595                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6596         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6597       else if (GET_CODE (false_rtx) == IOR
6598                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6599         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6600       else if (GET_CODE (false_rtx) == IOR
6601                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6602         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6603
6604       term2 = simplify_gen_binary (AND, GET_MODE (src),
6605                                    XEXP (XEXP (src, 0), 0), true_rtx);
6606       term3 = simplify_gen_binary (AND, GET_MODE (src),
6607                                    simplify_gen_unary (NOT, GET_MODE (src),
6608                                                        XEXP (XEXP (src, 0), 0),
6609                                                        GET_MODE (src)),
6610                                    false_rtx);
6611
6612       SUBST (SET_SRC (x),
6613              simplify_gen_binary (IOR, GET_MODE (src),
6614                                   simplify_gen_binary (IOR, GET_MODE (src),
6615                                                        term1, term2),
6616                                   term3));
6617
6618       src = SET_SRC (x);
6619     }
6620
6621   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6622      whole thing fail.  */
6623   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6624     return src;
6625   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6626     return dest;
6627   else
6628     /* Convert this into a field assignment operation, if possible.  */
6629     return make_field_assignment (x);
6630 }
6631 \f
6632 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6633    result.  */
6634
6635 static rtx
6636 simplify_logical (rtx x)
6637 {
6638   machine_mode mode = GET_MODE (x);
6639   rtx op0 = XEXP (x, 0);
6640   rtx op1 = XEXP (x, 1);
6641
6642   switch (GET_CODE (x))
6643     {
6644     case AND:
6645       /* We can call simplify_and_const_int only if we don't lose
6646          any (sign) bits when converting INTVAL (op1) to
6647          "unsigned HOST_WIDE_INT".  */
6648       if (CONST_INT_P (op1)
6649           && (HWI_COMPUTABLE_MODE_P (mode)
6650               || INTVAL (op1) > 0))
6651         {
6652           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6653           if (GET_CODE (x) != AND)
6654             return x;
6655
6656           op0 = XEXP (x, 0);
6657           op1 = XEXP (x, 1);
6658         }
6659
6660       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6661          apply the distributive law and then the inverse distributive
6662          law to see if things simplify.  */
6663       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6664         {
6665           rtx result = distribute_and_simplify_rtx (x, 0);
6666           if (result)
6667             return result;
6668         }
6669       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6670         {
6671           rtx result = distribute_and_simplify_rtx (x, 1);
6672           if (result)
6673             return result;
6674         }
6675       break;
6676
6677     case IOR:
6678       /* If we have (ior (and A B) C), apply the distributive law and then
6679          the inverse distributive law to see if things simplify.  */
6680
6681       if (GET_CODE (op0) == AND)
6682         {
6683           rtx result = distribute_and_simplify_rtx (x, 0);
6684           if (result)
6685             return result;
6686         }
6687
6688       if (GET_CODE (op1) == AND)
6689         {
6690           rtx result = distribute_and_simplify_rtx (x, 1);
6691           if (result)
6692             return result;
6693         }
6694       break;
6695
6696     default:
6697       gcc_unreachable ();
6698     }
6699
6700   return x;
6701 }
6702 \f
6703 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6704    operations" because they can be replaced with two more basic operations.
6705    ZERO_EXTEND is also considered "compound" because it can be replaced with
6706    an AND operation, which is simpler, though only one operation.
6707
6708    The function expand_compound_operation is called with an rtx expression
6709    and will convert it to the appropriate shifts and AND operations,
6710    simplifying at each stage.
6711
6712    The function make_compound_operation is called to convert an expression
6713    consisting of shifts and ANDs into the equivalent compound expression.
6714    It is the inverse of this function, loosely speaking.  */
6715
6716 static rtx
6717 expand_compound_operation (rtx x)
6718 {
6719   unsigned HOST_WIDE_INT pos = 0, len;
6720   int unsignedp = 0;
6721   unsigned int modewidth;
6722   rtx tem;
6723
6724   switch (GET_CODE (x))
6725     {
6726     case ZERO_EXTEND:
6727       unsignedp = 1;
6728     case SIGN_EXTEND:
6729       /* We can't necessarily use a const_int for a multiword mode;
6730          it depends on implicitly extending the value.
6731          Since we don't know the right way to extend it,
6732          we can't tell whether the implicit way is right.
6733
6734          Even for a mode that is no wider than a const_int,
6735          we can't win, because we need to sign extend one of its bits through
6736          the rest of it, and we don't know which bit.  */
6737       if (CONST_INT_P (XEXP (x, 0)))
6738         return x;
6739
6740       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6741          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6742          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6743          reloaded. If not for that, MEM's would very rarely be safe.
6744
6745          Reject MODEs bigger than a word, because we might not be able
6746          to reference a two-register group starting with an arbitrary register
6747          (and currently gen_lowpart might crash for a SUBREG).  */
6748
6749       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6750         return x;
6751
6752       /* Reject MODEs that aren't scalar integers because turning vector
6753          or complex modes into shifts causes problems.  */
6754
6755       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6756         return x;
6757
6758       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6759       /* If the inner object has VOIDmode (the only way this can happen
6760          is if it is an ASM_OPERANDS), we can't do anything since we don't
6761          know how much masking to do.  */
6762       if (len == 0)
6763         return x;
6764
6765       break;
6766
6767     case ZERO_EXTRACT:
6768       unsignedp = 1;
6769
6770       /* ... fall through ...  */
6771
6772     case SIGN_EXTRACT:
6773       /* If the operand is a CLOBBER, just return it.  */
6774       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6775         return XEXP (x, 0);
6776
6777       if (!CONST_INT_P (XEXP (x, 1))
6778           || !CONST_INT_P (XEXP (x, 2))
6779           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6780         return x;
6781
6782       /* Reject MODEs that aren't scalar integers because turning vector
6783          or complex modes into shifts causes problems.  */
6784
6785       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6786         return x;
6787
6788       len = INTVAL (XEXP (x, 1));
6789       pos = INTVAL (XEXP (x, 2));
6790
6791       /* This should stay within the object being extracted, fail otherwise.  */
6792       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6793         return x;
6794
6795       if (BITS_BIG_ENDIAN)
6796         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6797
6798       break;
6799
6800     default:
6801       return x;
6802     }
6803   /* Convert sign extension to zero extension, if we know that the high
6804      bit is not set, as this is easier to optimize.  It will be converted
6805      back to cheaper alternative in make_extraction.  */
6806   if (GET_CODE (x) == SIGN_EXTEND
6807       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6808           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6809                 & ~(((unsigned HOST_WIDE_INT)
6810                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6811                      >> 1))
6812                == 0)))
6813     {
6814       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6815       rtx temp2 = expand_compound_operation (temp);
6816
6817       /* Make sure this is a profitable operation.  */
6818       if (set_src_cost (x, optimize_this_for_speed_p)
6819           > set_src_cost (temp2, optimize_this_for_speed_p))
6820        return temp2;
6821       else if (set_src_cost (x, optimize_this_for_speed_p)
6822                > set_src_cost (temp, optimize_this_for_speed_p))
6823        return temp;
6824       else
6825        return x;
6826     }
6827
6828   /* We can optimize some special cases of ZERO_EXTEND.  */
6829   if (GET_CODE (x) == ZERO_EXTEND)
6830     {
6831       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6832          know that the last value didn't have any inappropriate bits
6833          set.  */
6834       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6835           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6836           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6837           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6838               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6839         return XEXP (XEXP (x, 0), 0);
6840
6841       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6842       if (GET_CODE (XEXP (x, 0)) == SUBREG
6843           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6844           && subreg_lowpart_p (XEXP (x, 0))
6845           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6846           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6847               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6848         return SUBREG_REG (XEXP (x, 0));
6849
6850       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6851          is a comparison and STORE_FLAG_VALUE permits.  This is like
6852          the first case, but it works even when GET_MODE (x) is larger
6853          than HOST_WIDE_INT.  */
6854       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6855           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6856           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6857           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6858               <= HOST_BITS_PER_WIDE_INT)
6859           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6860         return XEXP (XEXP (x, 0), 0);
6861
6862       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6863       if (GET_CODE (XEXP (x, 0)) == SUBREG
6864           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6865           && subreg_lowpart_p (XEXP (x, 0))
6866           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6867           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6868               <= HOST_BITS_PER_WIDE_INT)
6869           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6870         return SUBREG_REG (XEXP (x, 0));
6871
6872     }
6873
6874   /* If we reach here, we want to return a pair of shifts.  The inner
6875      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6876      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6877      logical depending on the value of UNSIGNEDP.
6878
6879      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6880      converted into an AND of a shift.
6881
6882      We must check for the case where the left shift would have a negative
6883      count.  This can happen in a case like (x >> 31) & 255 on machines
6884      that can't shift by a constant.  On those machines, we would first
6885      combine the shift with the AND to produce a variable-position
6886      extraction.  Then the constant of 31 would be substituted in
6887      to produce such a position.  */
6888
6889   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6890   if (modewidth >= pos + len)
6891     {
6892       machine_mode mode = GET_MODE (x);
6893       tem = gen_lowpart (mode, XEXP (x, 0));
6894       if (!tem || GET_CODE (tem) == CLOBBER)
6895         return x;
6896       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6897                                   tem, modewidth - pos - len);
6898       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6899                                   mode, tem, modewidth - len);
6900     }
6901   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6902     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6903                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6904                                                         GET_MODE (x),
6905                                                         XEXP (x, 0), pos),
6906                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6907   else
6908     /* Any other cases we can't handle.  */
6909     return x;
6910
6911   /* If we couldn't do this for some reason, return the original
6912      expression.  */
6913   if (GET_CODE (tem) == CLOBBER)
6914     return x;
6915
6916   return tem;
6917 }
6918 \f
6919 /* X is a SET which contains an assignment of one object into
6920    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6921    or certain SUBREGS). If possible, convert it into a series of
6922    logical operations.
6923
6924    We half-heartedly support variable positions, but do not at all
6925    support variable lengths.  */
6926
6927 static const_rtx
6928 expand_field_assignment (const_rtx x)
6929 {
6930   rtx inner;
6931   rtx pos;                      /* Always counts from low bit.  */
6932   int len;
6933   rtx mask, cleared, masked;
6934   machine_mode compute_mode;
6935
6936   /* Loop until we find something we can't simplify.  */
6937   while (1)
6938     {
6939       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6940           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6941         {
6942           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6943           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6944           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6945         }
6946       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6947                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6948         {
6949           inner = XEXP (SET_DEST (x), 0);
6950           len = INTVAL (XEXP (SET_DEST (x), 1));
6951           pos = XEXP (SET_DEST (x), 2);
6952
6953           /* A constant position should stay within the width of INNER.  */
6954           if (CONST_INT_P (pos)
6955               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6956             break;
6957
6958           if (BITS_BIG_ENDIAN)
6959             {
6960               if (CONST_INT_P (pos))
6961                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6962                                - INTVAL (pos));
6963               else if (GET_CODE (pos) == MINUS
6964                        && CONST_INT_P (XEXP (pos, 1))
6965                        && (INTVAL (XEXP (pos, 1))
6966                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6967                 /* If position is ADJUST - X, new position is X.  */
6968                 pos = XEXP (pos, 0);
6969               else
6970                 {
6971                   HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6972                   pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6973                                              gen_int_mode (prec - len,
6974                                                            GET_MODE (pos)),
6975                                              pos);
6976                 }
6977             }
6978         }
6979
6980       /* A SUBREG between two modes that occupy the same numbers of words
6981          can be done by moving the SUBREG to the source.  */
6982       else if (GET_CODE (SET_DEST (x)) == SUBREG
6983                /* We need SUBREGs to compute nonzero_bits properly.  */
6984                && nonzero_sign_valid
6985                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6986                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6987                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6988                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6989         {
6990           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6991                            gen_lowpart
6992                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6993                             SET_SRC (x)));
6994           continue;
6995         }
6996       else
6997         break;
6998
6999       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7000         inner = SUBREG_REG (inner);
7001
7002       compute_mode = GET_MODE (inner);
7003
7004       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
7005       if (! SCALAR_INT_MODE_P (compute_mode))
7006         {
7007           machine_mode imode;
7008
7009           /* Don't do anything for vector or complex integral types.  */
7010           if (! FLOAT_MODE_P (compute_mode))
7011             break;
7012
7013           /* Try to find an integral mode to pun with.  */
7014           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7015           if (imode == BLKmode)
7016             break;
7017
7018           compute_mode = imode;
7019           inner = gen_lowpart (imode, inner);
7020         }
7021
7022       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
7023       if (len >= HOST_BITS_PER_WIDE_INT)
7024         break;
7025
7026       /* Now compute the equivalent expression.  Make a copy of INNER
7027          for the SET_DEST in case it is a MEM into which we will substitute;
7028          we don't want shared RTL in that case.  */
7029       mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
7030                            compute_mode);
7031       cleared = simplify_gen_binary (AND, compute_mode,
7032                                      simplify_gen_unary (NOT, compute_mode,
7033                                        simplify_gen_binary (ASHIFT,
7034                                                             compute_mode,
7035                                                             mask, pos),
7036                                        compute_mode),
7037                                      inner);
7038       masked = simplify_gen_binary (ASHIFT, compute_mode,
7039                                     simplify_gen_binary (
7040                                       AND, compute_mode,
7041                                       gen_lowpart (compute_mode, SET_SRC (x)),
7042                                       mask),
7043                                     pos);
7044
7045       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7046                        simplify_gen_binary (IOR, compute_mode,
7047                                             cleared, masked));
7048     }
7049
7050   return x;
7051 }
7052 \f
7053 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
7054    it is an RTX that represents the (variable) starting position; otherwise,
7055    POS is the (constant) starting bit position.  Both are counted from the LSB.
7056
7057    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7058
7059    IN_DEST is nonzero if this is a reference in the destination of a SET.
7060    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7061    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7062    be used.
7063
7064    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7065    ZERO_EXTRACT should be built even for bits starting at bit 0.
7066
7067    MODE is the desired mode of the result (if IN_DEST == 0).
7068
7069    The result is an RTX for the extraction or NULL_RTX if the target
7070    can't handle it.  */
7071
7072 static rtx
7073 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7074                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7075                  int in_dest, int in_compare)
7076 {
7077   /* This mode describes the size of the storage area
7078      to fetch the overall value from.  Within that, we
7079      ignore the POS lowest bits, etc.  */
7080   machine_mode is_mode = GET_MODE (inner);
7081   machine_mode inner_mode;
7082   machine_mode wanted_inner_mode;
7083   machine_mode wanted_inner_reg_mode = word_mode;
7084   machine_mode pos_mode = word_mode;
7085   machine_mode extraction_mode = word_mode;
7086   machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7087   rtx new_rtx = 0;
7088   rtx orig_pos_rtx = pos_rtx;
7089   HOST_WIDE_INT orig_pos;
7090
7091   if (pos_rtx && CONST_INT_P (pos_rtx))
7092     pos = INTVAL (pos_rtx), pos_rtx = 0;
7093
7094   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7095     {
7096       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7097          consider just the QI as the memory to extract from.
7098          The subreg adds or removes high bits; its mode is
7099          irrelevant to the meaning of this extraction,
7100          since POS and LEN count from the lsb.  */
7101       if (MEM_P (SUBREG_REG (inner)))
7102         is_mode = GET_MODE (SUBREG_REG (inner));
7103       inner = SUBREG_REG (inner);
7104     }
7105   else if (GET_CODE (inner) == ASHIFT
7106            && CONST_INT_P (XEXP (inner, 1))
7107            && pos_rtx == 0 && pos == 0
7108            && len > UINTVAL (XEXP (inner, 1)))
7109     {
7110       /* We're extracting the least significant bits of an rtx
7111          (ashift X (const_int C)), where LEN > C.  Extract the
7112          least significant (LEN - C) bits of X, giving an rtx
7113          whose mode is MODE, then shift it left C times.  */
7114       new_rtx = make_extraction (mode, XEXP (inner, 0),
7115                              0, 0, len - INTVAL (XEXP (inner, 1)),
7116                              unsignedp, in_dest, in_compare);
7117       if (new_rtx != 0)
7118         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7119     }
7120   else if (GET_CODE (inner) == TRUNCATE)
7121     inner = XEXP (inner, 0);
7122
7123   inner_mode = GET_MODE (inner);
7124
7125   /* See if this can be done without an extraction.  We never can if the
7126      width of the field is not the same as that of some integer mode. For
7127      registers, we can only avoid the extraction if the position is at the
7128      low-order bit and this is either not in the destination or we have the
7129      appropriate STRICT_LOW_PART operation available.
7130
7131      For MEM, we can avoid an extract if the field starts on an appropriate
7132      boundary and we can change the mode of the memory reference.  */
7133
7134   if (tmode != BLKmode
7135       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7136            && !MEM_P (inner)
7137            && (inner_mode == tmode
7138                || !REG_P (inner)
7139                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7140                || reg_truncated_to_mode (tmode, inner))
7141            && (! in_dest
7142                || (REG_P (inner)
7143                    && have_insn_for (STRICT_LOW_PART, tmode))))
7144           || (MEM_P (inner) && pos_rtx == 0
7145               && (pos
7146                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7147                      : BITS_PER_UNIT)) == 0
7148               /* We can't do this if we are widening INNER_MODE (it
7149                  may not be aligned, for one thing).  */
7150               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7151               && (inner_mode == tmode
7152                   || (! mode_dependent_address_p (XEXP (inner, 0),
7153                                                   MEM_ADDR_SPACE (inner))
7154                       && ! MEM_VOLATILE_P (inner))))))
7155     {
7156       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7157          field.  If the original and current mode are the same, we need not
7158          adjust the offset.  Otherwise, we do if bytes big endian.
7159
7160          If INNER is not a MEM, get a piece consisting of just the field
7161          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7162
7163       if (MEM_P (inner))
7164         {
7165           HOST_WIDE_INT offset;
7166
7167           /* POS counts from lsb, but make OFFSET count in memory order.  */
7168           if (BYTES_BIG_ENDIAN)
7169             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7170           else
7171             offset = pos / BITS_PER_UNIT;
7172
7173           new_rtx = adjust_address_nv (inner, tmode, offset);
7174         }
7175       else if (REG_P (inner))
7176         {
7177           if (tmode != inner_mode)
7178             {
7179               /* We can't call gen_lowpart in a DEST since we
7180                  always want a SUBREG (see below) and it would sometimes
7181                  return a new hard register.  */
7182               if (pos || in_dest)
7183                 {
7184                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7185
7186                   if (WORDS_BIG_ENDIAN
7187                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7188                     final_word = ((GET_MODE_SIZE (inner_mode)
7189                                    - GET_MODE_SIZE (tmode))
7190                                   / UNITS_PER_WORD) - final_word;
7191
7192                   final_word *= UNITS_PER_WORD;
7193                   if (BYTES_BIG_ENDIAN &&
7194                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7195                     final_word += (GET_MODE_SIZE (inner_mode)
7196                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7197
7198                   /* Avoid creating invalid subregs, for example when
7199                      simplifying (x>>32)&255.  */
7200                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7201                     return NULL_RTX;
7202
7203                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7204                 }
7205               else
7206                 new_rtx = gen_lowpart (tmode, inner);
7207             }
7208           else
7209             new_rtx = inner;
7210         }
7211       else
7212         new_rtx = force_to_mode (inner, tmode,
7213                              len >= HOST_BITS_PER_WIDE_INT
7214                              ? ~(unsigned HOST_WIDE_INT) 0
7215                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7216                              0);
7217
7218       /* If this extraction is going into the destination of a SET,
7219          make a STRICT_LOW_PART unless we made a MEM.  */
7220
7221       if (in_dest)
7222         return (MEM_P (new_rtx) ? new_rtx
7223                 : (GET_CODE (new_rtx) != SUBREG
7224                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7225                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7226
7227       if (mode == tmode)
7228         return new_rtx;
7229
7230       if (CONST_SCALAR_INT_P (new_rtx))
7231         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7232                                          mode, new_rtx, tmode);
7233
7234       /* If we know that no extraneous bits are set, and that the high
7235          bit is not set, convert the extraction to the cheaper of
7236          sign and zero extension, that are equivalent in these cases.  */
7237       if (flag_expensive_optimizations
7238           && (HWI_COMPUTABLE_MODE_P (tmode)
7239               && ((nonzero_bits (new_rtx, tmode)
7240                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7241                   == 0)))
7242         {
7243           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7244           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7245
7246           /* Prefer ZERO_EXTENSION, since it gives more information to
7247              backends.  */
7248           if (set_src_cost (temp, optimize_this_for_speed_p)
7249               <= set_src_cost (temp1, optimize_this_for_speed_p))
7250             return temp;
7251           return temp1;
7252         }
7253
7254       /* Otherwise, sign- or zero-extend unless we already are in the
7255          proper mode.  */
7256
7257       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7258                              mode, new_rtx));
7259     }
7260
7261   /* Unless this is a COMPARE or we have a funny memory reference,
7262      don't do anything with zero-extending field extracts starting at
7263      the low-order bit since they are simple AND operations.  */
7264   if (pos_rtx == 0 && pos == 0 && ! in_dest
7265       && ! in_compare && unsignedp)
7266     return 0;
7267
7268   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7269      if the position is not a constant and the length is not 1.  In all
7270      other cases, we would only be going outside our object in cases when
7271      an original shift would have been undefined.  */
7272   if (MEM_P (inner)
7273       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7274           || (pos_rtx != 0 && len != 1)))
7275     return 0;
7276
7277   enum extraction_pattern pattern = (in_dest ? EP_insv
7278                                      : unsignedp ? EP_extzv : EP_extv);
7279
7280   /* If INNER is not from memory, we want it to have the mode of a register
7281      extraction pattern's structure operand, or word_mode if there is no
7282      such pattern.  The same applies to extraction_mode and pos_mode
7283      and their respective operands.
7284
7285      For memory, assume that the desired extraction_mode and pos_mode
7286      are the same as for a register operation, since at present we don't
7287      have named patterns for aligned memory structures.  */
7288   struct extraction_insn insn;
7289   if (get_best_reg_extraction_insn (&insn, pattern,
7290                                     GET_MODE_BITSIZE (inner_mode), mode))
7291     {
7292       wanted_inner_reg_mode = insn.struct_mode;
7293       pos_mode = insn.pos_mode;
7294       extraction_mode = insn.field_mode;
7295     }
7296
7297   /* Never narrow an object, since that might not be safe.  */
7298
7299   if (mode != VOIDmode
7300       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7301     extraction_mode = mode;
7302
7303   if (!MEM_P (inner))
7304     wanted_inner_mode = wanted_inner_reg_mode;
7305   else
7306     {
7307       /* Be careful not to go beyond the extracted object and maintain the
7308          natural alignment of the memory.  */
7309       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7310       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7311              > GET_MODE_BITSIZE (wanted_inner_mode))
7312         {
7313           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7314           gcc_assert (wanted_inner_mode != VOIDmode);
7315         }
7316     }
7317
7318   orig_pos = pos;
7319
7320   if (BITS_BIG_ENDIAN)
7321     {
7322       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7323          BITS_BIG_ENDIAN style.  If position is constant, compute new
7324          position.  Otherwise, build subtraction.
7325          Note that POS is relative to the mode of the original argument.
7326          If it's a MEM we need to recompute POS relative to that.
7327          However, if we're extracting from (or inserting into) a register,
7328          we want to recompute POS relative to wanted_inner_mode.  */
7329       int width = (MEM_P (inner)
7330                    ? GET_MODE_BITSIZE (is_mode)
7331                    : GET_MODE_BITSIZE (wanted_inner_mode));
7332
7333       if (pos_rtx == 0)
7334         pos = width - len - pos;
7335       else
7336         pos_rtx
7337           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7338                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7339                            pos_rtx);
7340       /* POS may be less than 0 now, but we check for that below.
7341          Note that it can only be less than 0 if !MEM_P (inner).  */
7342     }
7343
7344   /* If INNER has a wider mode, and this is a constant extraction, try to
7345      make it smaller and adjust the byte to point to the byte containing
7346      the value.  */
7347   if (wanted_inner_mode != VOIDmode
7348       && inner_mode != wanted_inner_mode
7349       && ! pos_rtx
7350       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7351       && MEM_P (inner)
7352       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7353       && ! MEM_VOLATILE_P (inner))
7354     {
7355       int offset = 0;
7356
7357       /* The computations below will be correct if the machine is big
7358          endian in both bits and bytes or little endian in bits and bytes.
7359          If it is mixed, we must adjust.  */
7360
7361       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7362          adjust OFFSET to compensate.  */
7363       if (BYTES_BIG_ENDIAN
7364           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7365         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7366
7367       /* We can now move to the desired byte.  */
7368       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7369                 * GET_MODE_SIZE (wanted_inner_mode);
7370       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7371
7372       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7373           && is_mode != wanted_inner_mode)
7374         offset = (GET_MODE_SIZE (is_mode)
7375                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7376
7377       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7378     }
7379
7380   /* If INNER is not memory, get it into the proper mode.  If we are changing
7381      its mode, POS must be a constant and smaller than the size of the new
7382      mode.  */
7383   else if (!MEM_P (inner))
7384     {
7385       /* On the LHS, don't create paradoxical subregs implicitely truncating
7386          the register unless TRULY_NOOP_TRUNCATION.  */
7387       if (in_dest
7388           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7389                                              wanted_inner_mode))
7390         return NULL_RTX;
7391
7392       if (GET_MODE (inner) != wanted_inner_mode
7393           && (pos_rtx != 0
7394               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7395         return NULL_RTX;
7396
7397       if (orig_pos < 0)
7398         return NULL_RTX;
7399
7400       inner = force_to_mode (inner, wanted_inner_mode,
7401                              pos_rtx
7402                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7403                              ? ~(unsigned HOST_WIDE_INT) 0
7404                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7405                                 << orig_pos),
7406                              0);
7407     }
7408
7409   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7410      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7411   if (pos_rtx != 0
7412       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7413     {
7414       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7415                                      GET_MODE (pos_rtx));
7416
7417       /* If we know that no extraneous bits are set, and that the high
7418          bit is not set, convert extraction to cheaper one - either
7419          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7420          cases.  */
7421       if (flag_expensive_optimizations
7422           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7423               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7424                    & ~(((unsigned HOST_WIDE_INT)
7425                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7426                        >> 1))
7427                   == 0)))
7428         {
7429           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7430                                           GET_MODE (pos_rtx));
7431
7432           /* Prefer ZERO_EXTENSION, since it gives more information to
7433              backends.  */
7434           if (set_src_cost (temp1, optimize_this_for_speed_p)
7435               < set_src_cost (temp, optimize_this_for_speed_p))
7436             temp = temp1;
7437         }
7438       pos_rtx = temp;
7439     }
7440
7441   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7442      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7443      be a CONST_INT.  */
7444   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7445     pos_rtx = orig_pos_rtx;
7446
7447   else if (pos_rtx == 0)
7448     pos_rtx = GEN_INT (pos);
7449
7450   /* Make the required operation.  See if we can use existing rtx.  */
7451   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7452                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7453   if (! in_dest)
7454     new_rtx = gen_lowpart (mode, new_rtx);
7455
7456   return new_rtx;
7457 }
7458 \f
7459 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7460    with any other operations in X.  Return X without that shift if so.  */
7461
7462 static rtx
7463 extract_left_shift (rtx x, int count)
7464 {
7465   enum rtx_code code = GET_CODE (x);
7466   machine_mode mode = GET_MODE (x);
7467   rtx tem;
7468
7469   switch (code)
7470     {
7471     case ASHIFT:
7472       /* This is the shift itself.  If it is wide enough, we will return
7473          either the value being shifted if the shift count is equal to
7474          COUNT or a shift for the difference.  */
7475       if (CONST_INT_P (XEXP (x, 1))
7476           && INTVAL (XEXP (x, 1)) >= count)
7477         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7478                                      INTVAL (XEXP (x, 1)) - count);
7479       break;
7480
7481     case NEG:  case NOT:
7482       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7483         return simplify_gen_unary (code, mode, tem, mode);
7484
7485       break;
7486
7487     case PLUS:  case IOR:  case XOR:  case AND:
7488       /* If we can safely shift this constant and we find the inner shift,
7489          make a new operation.  */
7490       if (CONST_INT_P (XEXP (x, 1))
7491           && (UINTVAL (XEXP (x, 1))
7492               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7493           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7494         {
7495           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7496           return simplify_gen_binary (code, mode, tem,
7497                                       gen_int_mode (val, mode));
7498         }
7499       break;
7500
7501     default:
7502       break;
7503     }
7504
7505   return 0;
7506 }
7507 \f
7508 /* Look at the expression rooted at X.  Look for expressions
7509    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7510    Form these expressions.
7511
7512    Return the new rtx, usually just X.
7513
7514    Also, for machines like the VAX that don't have logical shift insns,
7515    try to convert logical to arithmetic shift operations in cases where
7516    they are equivalent.  This undoes the canonicalizations to logical
7517    shifts done elsewhere.
7518
7519    We try, as much as possible, to re-use rtl expressions to save memory.
7520
7521    IN_CODE says what kind of expression we are processing.  Normally, it is
7522    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7523    being kludges), it is MEM.  When processing the arguments of a comparison
7524    or a COMPARE against zero, it is COMPARE.  */
7525
7526 rtx
7527 make_compound_operation (rtx x, enum rtx_code in_code)
7528 {
7529   enum rtx_code code = GET_CODE (x);
7530   machine_mode mode = GET_MODE (x);
7531   int mode_width = GET_MODE_PRECISION (mode);
7532   rtx rhs, lhs;
7533   enum rtx_code next_code;
7534   int i, j;
7535   rtx new_rtx = 0;
7536   rtx tem;
7537   const char *fmt;
7538
7539   /* Select the code to be used in recursive calls.  Once we are inside an
7540      address, we stay there.  If we have a comparison, set to COMPARE,
7541      but once inside, go back to our default of SET.  */
7542
7543   next_code = (code == MEM ? MEM
7544                : ((code == PLUS || code == MINUS)
7545                   && SCALAR_INT_MODE_P (mode)) ? MEM
7546                : ((code == COMPARE || COMPARISON_P (x))
7547                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7548                : in_code == COMPARE ? SET : in_code);
7549
7550   /* Process depending on the code of this operation.  If NEW is set
7551      nonzero, it will be returned.  */
7552
7553   switch (code)
7554     {
7555     case ASHIFT:
7556       /* Convert shifts by constants into multiplications if inside
7557          an address.  */
7558       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7559           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7560           && INTVAL (XEXP (x, 1)) >= 0
7561           && SCALAR_INT_MODE_P (mode))
7562         {
7563           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7564           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7565
7566           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7567           if (GET_CODE (new_rtx) == NEG)
7568             {
7569               new_rtx = XEXP (new_rtx, 0);
7570               multval = -multval;
7571             }
7572           multval = trunc_int_for_mode (multval, mode);
7573           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7574         }
7575       break;
7576
7577     case PLUS:
7578       lhs = XEXP (x, 0);
7579       rhs = XEXP (x, 1);
7580       lhs = make_compound_operation (lhs, next_code);
7581       rhs = make_compound_operation (rhs, next_code);
7582       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7583           && SCALAR_INT_MODE_P (mode))
7584         {
7585           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7586                                      XEXP (lhs, 1));
7587           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7588         }
7589       else if (GET_CODE (lhs) == MULT
7590                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7591         {
7592           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7593                                      simplify_gen_unary (NEG, mode,
7594                                                          XEXP (lhs, 1),
7595                                                          mode));
7596           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7597         }
7598       else
7599         {
7600           SUBST (XEXP (x, 0), lhs);
7601           SUBST (XEXP (x, 1), rhs);
7602           goto maybe_swap;
7603         }
7604       x = gen_lowpart (mode, new_rtx);
7605       goto maybe_swap;
7606
7607     case MINUS:
7608       lhs = XEXP (x, 0);
7609       rhs = XEXP (x, 1);
7610       lhs = make_compound_operation (lhs, next_code);
7611       rhs = make_compound_operation (rhs, next_code);
7612       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7613           && SCALAR_INT_MODE_P (mode))
7614         {
7615           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7616                                      XEXP (rhs, 1));
7617           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7618         }
7619       else if (GET_CODE (rhs) == MULT
7620                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7621         {
7622           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7623                                      simplify_gen_unary (NEG, mode,
7624                                                          XEXP (rhs, 1),
7625                                                          mode));
7626           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7627         }
7628       else
7629         {
7630           SUBST (XEXP (x, 0), lhs);
7631           SUBST (XEXP (x, 1), rhs);
7632           return x;
7633         }
7634       return gen_lowpart (mode, new_rtx);
7635
7636     case AND:
7637       /* If the second operand is not a constant, we can't do anything
7638          with it.  */
7639       if (!CONST_INT_P (XEXP (x, 1)))
7640         break;
7641
7642       /* If the constant is a power of two minus one and the first operand
7643          is a logical right shift, make an extraction.  */
7644       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7645           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7646         {
7647           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7648           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7649                                  0, in_code == COMPARE);
7650         }
7651
7652       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7653       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7654                && subreg_lowpart_p (XEXP (x, 0))
7655                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7656                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7657         {
7658           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7659                                          next_code);
7660           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7661                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7662                                  0, in_code == COMPARE);
7663         }
7664       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7665       else if ((GET_CODE (XEXP (x, 0)) == XOR
7666                 || GET_CODE (XEXP (x, 0)) == IOR)
7667                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7668                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7669                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7670         {
7671           /* Apply the distributive law, and then try to make extractions.  */
7672           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7673                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7674                                              XEXP (x, 1)),
7675                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7676                                              XEXP (x, 1)));
7677           new_rtx = make_compound_operation (new_rtx, in_code);
7678         }
7679
7680       /* If we are have (and (rotate X C) M) and C is larger than the number
7681          of bits in M, this is an extraction.  */
7682
7683       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7684                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7685                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7686                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7687         {
7688           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7689           new_rtx = make_extraction (mode, new_rtx,
7690                                  (GET_MODE_PRECISION (mode)
7691                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7692                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7693         }
7694
7695       /* On machines without logical shifts, if the operand of the AND is
7696          a logical shift and our mask turns off all the propagated sign
7697          bits, we can replace the logical shift with an arithmetic shift.  */
7698       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7699                && !have_insn_for (LSHIFTRT, mode)
7700                && have_insn_for (ASHIFTRT, mode)
7701                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7702                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7703                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7704                && mode_width <= HOST_BITS_PER_WIDE_INT)
7705         {
7706           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7707
7708           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7709           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7710             SUBST (XEXP (x, 0),
7711                    gen_rtx_ASHIFTRT (mode,
7712                                      make_compound_operation
7713                                      (XEXP (XEXP (x, 0), 0), next_code),
7714                                      XEXP (XEXP (x, 0), 1)));
7715         }
7716
7717       /* If the constant is one less than a power of two, this might be
7718          representable by an extraction even if no shift is present.
7719          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7720          we are in a COMPARE.  */
7721       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7722         new_rtx = make_extraction (mode,
7723                                make_compound_operation (XEXP (x, 0),
7724                                                         next_code),
7725                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7726
7727       /* If we are in a comparison and this is an AND with a power of two,
7728          convert this into the appropriate bit extract.  */
7729       else if (in_code == COMPARE
7730                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7731         new_rtx = make_extraction (mode,
7732                                make_compound_operation (XEXP (x, 0),
7733                                                         next_code),
7734                                i, NULL_RTX, 1, 1, 0, 1);
7735
7736       break;
7737
7738     case LSHIFTRT:
7739       /* If the sign bit is known to be zero, replace this with an
7740          arithmetic shift.  */
7741       if (have_insn_for (ASHIFTRT, mode)
7742           && ! have_insn_for (LSHIFTRT, mode)
7743           && mode_width <= HOST_BITS_PER_WIDE_INT
7744           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7745         {
7746           new_rtx = gen_rtx_ASHIFTRT (mode,
7747                                   make_compound_operation (XEXP (x, 0),
7748                                                            next_code),
7749                                   XEXP (x, 1));
7750           break;
7751         }
7752
7753       /* ... fall through ...  */
7754
7755     case ASHIFTRT:
7756       lhs = XEXP (x, 0);
7757       rhs = XEXP (x, 1);
7758
7759       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7760          this is a SIGN_EXTRACT.  */
7761       if (CONST_INT_P (rhs)
7762           && GET_CODE (lhs) == ASHIFT
7763           && CONST_INT_P (XEXP (lhs, 1))
7764           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7765           && INTVAL (XEXP (lhs, 1)) >= 0
7766           && INTVAL (rhs) < mode_width)
7767         {
7768           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7769           new_rtx = make_extraction (mode, new_rtx,
7770                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7771                                  NULL_RTX, mode_width - INTVAL (rhs),
7772                                  code == LSHIFTRT, 0, in_code == COMPARE);
7773           break;
7774         }
7775
7776       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7777          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7778          also do this for some cases of SIGN_EXTRACT, but it doesn't
7779          seem worth the effort; the case checked for occurs on Alpha.  */
7780
7781       if (!OBJECT_P (lhs)
7782           && ! (GET_CODE (lhs) == SUBREG
7783                 && (OBJECT_P (SUBREG_REG (lhs))))
7784           && CONST_INT_P (rhs)
7785           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7786           && INTVAL (rhs) < mode_width
7787           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7788         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7789                                0, NULL_RTX, mode_width - INTVAL (rhs),
7790                                code == LSHIFTRT, 0, in_code == COMPARE);
7791
7792       break;
7793
7794     case SUBREG:
7795       /* Call ourselves recursively on the inner expression.  If we are
7796          narrowing the object and it has a different RTL code from
7797          what it originally did, do this SUBREG as a force_to_mode.  */
7798       {
7799         rtx inner = SUBREG_REG (x), simplified;
7800         enum rtx_code subreg_code = in_code;
7801
7802         /* If in_code is COMPARE, it isn't always safe to pass it through
7803            to the recursive make_compound_operation call.  */
7804         if (subreg_code == COMPARE
7805             && (!subreg_lowpart_p (x)
7806                 || GET_CODE (inner) == SUBREG
7807                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7808                    is (const_int 0), rather than
7809                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7810                 || (GET_CODE (inner) == AND
7811                     && CONST_INT_P (XEXP (inner, 1))
7812                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7813                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7814                        >= GET_MODE_BITSIZE (mode))))
7815           subreg_code = SET;
7816
7817         tem = make_compound_operation (inner, subreg_code);
7818
7819         simplified
7820           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7821         if (simplified)
7822           tem = simplified;
7823
7824         if (GET_CODE (tem) != GET_CODE (inner)
7825             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7826             && subreg_lowpart_p (x))
7827           {
7828             rtx newer
7829               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7830
7831             /* If we have something other than a SUBREG, we might have
7832                done an expansion, so rerun ourselves.  */
7833             if (GET_CODE (newer) != SUBREG)
7834               newer = make_compound_operation (newer, in_code);
7835
7836             /* force_to_mode can expand compounds.  If it just re-expanded the
7837                compound, use gen_lowpart to convert to the desired mode.  */
7838             if (rtx_equal_p (newer, x)
7839                 /* Likewise if it re-expanded the compound only partially.
7840                    This happens for SUBREG of ZERO_EXTRACT if they extract
7841                    the same number of bits.  */
7842                 || (GET_CODE (newer) == SUBREG
7843                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7844                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7845                     && GET_CODE (inner) == AND
7846                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7847               return gen_lowpart (GET_MODE (x), tem);
7848
7849             return newer;
7850           }
7851
7852         if (simplified)
7853           return tem;
7854       }
7855       break;
7856
7857     default:
7858       break;
7859     }
7860
7861   if (new_rtx)
7862     {
7863       x = gen_lowpart (mode, new_rtx);
7864       code = GET_CODE (x);
7865     }
7866
7867   /* Now recursively process each operand of this operation.  We need to
7868      handle ZERO_EXTEND specially so that we don't lose track of the
7869      inner mode.  */
7870   if (GET_CODE (x) == ZERO_EXTEND)
7871     {
7872       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7873       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7874                                             new_rtx, GET_MODE (XEXP (x, 0)));
7875       if (tem)
7876         return tem;
7877       SUBST (XEXP (x, 0), new_rtx);
7878       return x;
7879     }
7880
7881   fmt = GET_RTX_FORMAT (code);
7882   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7883     if (fmt[i] == 'e')
7884       {
7885         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7886         SUBST (XEXP (x, i), new_rtx);
7887       }
7888     else if (fmt[i] == 'E')
7889       for (j = 0; j < XVECLEN (x, i); j++)
7890         {
7891           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7892           SUBST (XVECEXP (x, i, j), new_rtx);
7893         }
7894
7895  maybe_swap:
7896   /* If this is a commutative operation, the changes to the operands
7897      may have made it noncanonical.  */
7898   if (COMMUTATIVE_ARITH_P (x)
7899       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7900     {
7901       tem = XEXP (x, 0);
7902       SUBST (XEXP (x, 0), XEXP (x, 1));
7903       SUBST (XEXP (x, 1), tem);
7904     }
7905
7906   return x;
7907 }
7908 \f
7909 /* Given M see if it is a value that would select a field of bits
7910    within an item, but not the entire word.  Return -1 if not.
7911    Otherwise, return the starting position of the field, where 0 is the
7912    low-order bit.
7913
7914    *PLEN is set to the length of the field.  */
7915
7916 static int
7917 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7918 {
7919   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7920   int pos = m ? ctz_hwi (m) : -1;
7921   int len = 0;
7922
7923   if (pos >= 0)
7924     /* Now shift off the low-order zero bits and see if we have a
7925        power of two minus 1.  */
7926     len = exact_log2 ((m >> pos) + 1);
7927
7928   if (len <= 0)
7929     pos = -1;
7930
7931   *plen = len;
7932   return pos;
7933 }
7934 \f
7935 /* If X refers to a register that equals REG in value, replace these
7936    references with REG.  */
7937 static rtx
7938 canon_reg_for_combine (rtx x, rtx reg)
7939 {
7940   rtx op0, op1, op2;
7941   const char *fmt;
7942   int i;
7943   bool copied;
7944
7945   enum rtx_code code = GET_CODE (x);
7946   switch (GET_RTX_CLASS (code))
7947     {
7948     case RTX_UNARY:
7949       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7950       if (op0 != XEXP (x, 0))
7951         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7952                                    GET_MODE (reg));
7953       break;
7954
7955     case RTX_BIN_ARITH:
7956     case RTX_COMM_ARITH:
7957       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7958       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7959       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7960         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7961       break;
7962
7963     case RTX_COMPARE:
7964     case RTX_COMM_COMPARE:
7965       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7966       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7967       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7968         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7969                                         GET_MODE (op0), op0, op1);
7970       break;
7971
7972     case RTX_TERNARY:
7973     case RTX_BITFIELD_OPS:
7974       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7975       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7976       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7977       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7978         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7979                                      GET_MODE (op0), op0, op1, op2);
7980
7981     case RTX_OBJ:
7982       if (REG_P (x))
7983         {
7984           if (rtx_equal_p (get_last_value (reg), x)
7985               || rtx_equal_p (reg, get_last_value (x)))
7986             return reg;
7987           else
7988             break;
7989         }
7990
7991       /* fall through */
7992
7993     default:
7994       fmt = GET_RTX_FORMAT (code);
7995       copied = false;
7996       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7997         if (fmt[i] == 'e')
7998           {
7999             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8000             if (op != XEXP (x, i))
8001               {
8002                 if (!copied)
8003                   {
8004                     copied = true;
8005                     x = copy_rtx (x);
8006                   }
8007                 XEXP (x, i) = op;
8008               }
8009           }
8010         else if (fmt[i] == 'E')
8011           {
8012             int j;
8013             for (j = 0; j < XVECLEN (x, i); j++)
8014               {
8015                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8016                 if (op != XVECEXP (x, i, j))
8017                   {
8018                     if (!copied)
8019                       {
8020                         copied = true;
8021                         x = copy_rtx (x);
8022                       }
8023                     XVECEXP (x, i, j) = op;
8024                   }
8025               }
8026           }
8027
8028       break;
8029     }
8030
8031   return x;
8032 }
8033
8034 /* Return X converted to MODE.  If the value is already truncated to
8035    MODE we can just return a subreg even though in the general case we
8036    would need an explicit truncation.  */
8037
8038 static rtx
8039 gen_lowpart_or_truncate (machine_mode mode, rtx x)
8040 {
8041   if (!CONST_INT_P (x)
8042       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8043       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8044       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8045     {
8046       /* Bit-cast X into an integer mode.  */
8047       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8048         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8049       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8050                               x, GET_MODE (x));
8051     }
8052
8053   return gen_lowpart (mode, x);
8054 }
8055
8056 /* See if X can be simplified knowing that we will only refer to it in
8057    MODE and will only refer to those bits that are nonzero in MASK.
8058    If other bits are being computed or if masking operations are done
8059    that select a superset of the bits in MASK, they can sometimes be
8060    ignored.
8061
8062    Return a possibly simplified expression, but always convert X to
8063    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8064
8065    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8066    are all off in X.  This is used when X will be complemented, by either
8067    NOT, NEG, or XOR.  */
8068
8069 static rtx
8070 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8071                int just_select)
8072 {
8073   enum rtx_code code = GET_CODE (x);
8074   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8075   machine_mode op_mode;
8076   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8077   rtx op0, op1, temp;
8078
8079   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8080      code below will do the wrong thing since the mode of such an
8081      expression is VOIDmode.
8082
8083      Also do nothing if X is a CLOBBER; this can happen if X was
8084      the return value from a call to gen_lowpart.  */
8085   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8086     return x;
8087
8088   /* We want to perform the operation in its present mode unless we know
8089      that the operation is valid in MODE, in which case we do the operation
8090      in MODE.  */
8091   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8092               && have_insn_for (code, mode))
8093              ? mode : GET_MODE (x));
8094
8095   /* It is not valid to do a right-shift in a narrower mode
8096      than the one it came in with.  */
8097   if ((code == LSHIFTRT || code == ASHIFTRT)
8098       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8099     op_mode = GET_MODE (x);
8100
8101   /* Truncate MASK to fit OP_MODE.  */
8102   if (op_mode)
8103     mask &= GET_MODE_MASK (op_mode);
8104
8105   /* When we have an arithmetic operation, or a shift whose count we
8106      do not know, we need to assume that all bits up to the highest-order
8107      bit in MASK will be needed.  This is how we form such a mask.  */
8108   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8109     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8110   else
8111     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8112                    - 1);
8113
8114   /* Determine what bits of X are guaranteed to be (non)zero.  */
8115   nonzero = nonzero_bits (x, mode);
8116
8117   /* If none of the bits in X are needed, return a zero.  */
8118   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8119     x = const0_rtx;
8120
8121   /* If X is a CONST_INT, return a new one.  Do this here since the
8122      test below will fail.  */
8123   if (CONST_INT_P (x))
8124     {
8125       if (SCALAR_INT_MODE_P (mode))
8126         return gen_int_mode (INTVAL (x) & mask, mode);
8127       else
8128         {
8129           x = GEN_INT (INTVAL (x) & mask);
8130           return gen_lowpart_common (mode, x);
8131         }
8132     }
8133
8134   /* If X is narrower than MODE and we want all the bits in X's mode, just
8135      get X in the proper mode.  */
8136   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8137       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8138     return gen_lowpart (mode, x);
8139
8140   /* We can ignore the effect of a SUBREG if it narrows the mode or
8141      if the constant masks to zero all the bits the mode doesn't have.  */
8142   if (GET_CODE (x) == SUBREG
8143       && subreg_lowpart_p (x)
8144       && ((GET_MODE_SIZE (GET_MODE (x))
8145            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8146           || (0 == (mask
8147                     & GET_MODE_MASK (GET_MODE (x))
8148                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8149     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8150
8151   /* The arithmetic simplifications here only work for scalar integer modes.  */
8152   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8153     return gen_lowpart_or_truncate (mode, x);
8154
8155   switch (code)
8156     {
8157     case CLOBBER:
8158       /* If X is a (clobber (const_int)), return it since we know we are
8159          generating something that won't match.  */
8160       return x;
8161
8162     case SIGN_EXTEND:
8163     case ZERO_EXTEND:
8164     case ZERO_EXTRACT:
8165     case SIGN_EXTRACT:
8166       x = expand_compound_operation (x);
8167       if (GET_CODE (x) != code)
8168         return force_to_mode (x, mode, mask, next_select);
8169       break;
8170
8171     case TRUNCATE:
8172       /* Similarly for a truncate.  */
8173       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8174
8175     case AND:
8176       /* If this is an AND with a constant, convert it into an AND
8177          whose constant is the AND of that constant with MASK.  If it
8178          remains an AND of MASK, delete it since it is redundant.  */
8179
8180       if (CONST_INT_P (XEXP (x, 1)))
8181         {
8182           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8183                                       mask & INTVAL (XEXP (x, 1)));
8184
8185           /* If X is still an AND, see if it is an AND with a mask that
8186              is just some low-order bits.  If so, and it is MASK, we don't
8187              need it.  */
8188
8189           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8190               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8191                   == mask))
8192             x = XEXP (x, 0);
8193
8194           /* If it remains an AND, try making another AND with the bits
8195              in the mode mask that aren't in MASK turned on.  If the
8196              constant in the AND is wide enough, this might make a
8197              cheaper constant.  */
8198
8199           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8200               && GET_MODE_MASK (GET_MODE (x)) != mask
8201               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8202             {
8203               unsigned HOST_WIDE_INT cval
8204                 = UINTVAL (XEXP (x, 1))
8205                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8206               rtx y;
8207
8208               y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8209                                        gen_int_mode (cval, GET_MODE (x)));
8210               if (set_src_cost (y, optimize_this_for_speed_p)
8211                   < set_src_cost (x, optimize_this_for_speed_p))
8212                 x = y;
8213             }
8214
8215           break;
8216         }
8217
8218       goto binop;
8219
8220     case PLUS:
8221       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8222          low-order bits (as in an alignment operation) and FOO is already
8223          aligned to that boundary, mask C1 to that boundary as well.
8224          This may eliminate that PLUS and, later, the AND.  */
8225
8226       {
8227         unsigned int width = GET_MODE_PRECISION (mode);
8228         unsigned HOST_WIDE_INT smask = mask;
8229
8230         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8231            number, sign extend it.  */
8232
8233         if (width < HOST_BITS_PER_WIDE_INT
8234             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8235           smask |= HOST_WIDE_INT_M1U << width;
8236
8237         if (CONST_INT_P (XEXP (x, 1))
8238             && exact_log2 (- smask) >= 0
8239             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8240             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8241           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8242                                                (INTVAL (XEXP (x, 1)) & smask)),
8243                                 mode, smask, next_select);
8244       }
8245
8246       /* ... fall through ...  */
8247
8248     case MULT:
8249       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8250          most significant bit in MASK since carries from those bits will
8251          affect the bits we are interested in.  */
8252       mask = fuller_mask;
8253       goto binop;
8254
8255     case MINUS:
8256       /* If X is (minus C Y) where C's least set bit is larger than any bit
8257          in the mask, then we may replace with (neg Y).  */
8258       if (CONST_INT_P (XEXP (x, 0))
8259           && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask))
8260         {
8261           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8262                                   GET_MODE (x));
8263           return force_to_mode (x, mode, mask, next_select);
8264         }
8265
8266       /* Similarly, if C contains every bit in the fuller_mask, then we may
8267          replace with (not Y).  */
8268       if (CONST_INT_P (XEXP (x, 0))
8269           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8270         {
8271           x = simplify_gen_unary (NOT, GET_MODE (x),
8272                                   XEXP (x, 1), GET_MODE (x));
8273           return force_to_mode (x, mode, mask, next_select);
8274         }
8275
8276       mask = fuller_mask;
8277       goto binop;
8278
8279     case IOR:
8280     case XOR:
8281       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8282          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8283          operation which may be a bitfield extraction.  Ensure that the
8284          constant we form is not wider than the mode of X.  */
8285
8286       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8287           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8288           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8289           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8290           && CONST_INT_P (XEXP (x, 1))
8291           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8292                + floor_log2 (INTVAL (XEXP (x, 1))))
8293               < GET_MODE_PRECISION (GET_MODE (x)))
8294           && (UINTVAL (XEXP (x, 1))
8295               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8296         {
8297           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8298                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8299                                GET_MODE (x));
8300           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8301                                       XEXP (XEXP (x, 0), 0), temp);
8302           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8303                                    XEXP (XEXP (x, 0), 1));
8304           return force_to_mode (x, mode, mask, next_select);
8305         }
8306
8307     binop:
8308       /* For most binary operations, just propagate into the operation and
8309          change the mode if we have an operation of that mode.  */
8310
8311       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8312       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8313
8314       /* If we ended up truncating both operands, truncate the result of the
8315          operation instead.  */
8316       if (GET_CODE (op0) == TRUNCATE
8317           && GET_CODE (op1) == TRUNCATE)
8318         {
8319           op0 = XEXP (op0, 0);
8320           op1 = XEXP (op1, 0);
8321         }
8322
8323       op0 = gen_lowpart_or_truncate (op_mode, op0);
8324       op1 = gen_lowpart_or_truncate (op_mode, op1);
8325
8326       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8327         x = simplify_gen_binary (code, op_mode, op0, op1);
8328       break;
8329
8330     case ASHIFT:
8331       /* For left shifts, do the same, but just for the first operand.
8332          However, we cannot do anything with shifts where we cannot
8333          guarantee that the counts are smaller than the size of the mode
8334          because such a count will have a different meaning in a
8335          wider mode.  */
8336
8337       if (! (CONST_INT_P (XEXP (x, 1))
8338              && INTVAL (XEXP (x, 1)) >= 0
8339              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8340           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8341                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8342                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8343         break;
8344
8345       /* If the shift count is a constant and we can do arithmetic in
8346          the mode of the shift, refine which bits we need.  Otherwise, use the
8347          conservative form of the mask.  */
8348       if (CONST_INT_P (XEXP (x, 1))
8349           && INTVAL (XEXP (x, 1)) >= 0
8350           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8351           && HWI_COMPUTABLE_MODE_P (op_mode))
8352         mask >>= INTVAL (XEXP (x, 1));
8353       else
8354         mask = fuller_mask;
8355
8356       op0 = gen_lowpart_or_truncate (op_mode,
8357                                      force_to_mode (XEXP (x, 0), op_mode,
8358                                                     mask, next_select));
8359
8360       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8361         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8362       break;
8363
8364     case LSHIFTRT:
8365       /* Here we can only do something if the shift count is a constant,
8366          this shift constant is valid for the host, and we can do arithmetic
8367          in OP_MODE.  */
8368
8369       if (CONST_INT_P (XEXP (x, 1))
8370           && INTVAL (XEXP (x, 1)) >= 0
8371           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8372           && HWI_COMPUTABLE_MODE_P (op_mode))
8373         {
8374           rtx inner = XEXP (x, 0);
8375           unsigned HOST_WIDE_INT inner_mask;
8376
8377           /* Select the mask of the bits we need for the shift operand.  */
8378           inner_mask = mask << INTVAL (XEXP (x, 1));
8379
8380           /* We can only change the mode of the shift if we can do arithmetic
8381              in the mode of the shift and INNER_MASK is no wider than the
8382              width of X's mode.  */
8383           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8384             op_mode = GET_MODE (x);
8385
8386           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8387
8388           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8389             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8390         }
8391
8392       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8393          shift and AND produces only copies of the sign bit (C2 is one less
8394          than a power of two), we can do this with just a shift.  */
8395
8396       if (GET_CODE (x) == LSHIFTRT
8397           && CONST_INT_P (XEXP (x, 1))
8398           /* The shift puts one of the sign bit copies in the least significant
8399              bit.  */
8400           && ((INTVAL (XEXP (x, 1))
8401                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8402               >= GET_MODE_PRECISION (GET_MODE (x)))
8403           && exact_log2 (mask + 1) >= 0
8404           /* Number of bits left after the shift must be more than the mask
8405              needs.  */
8406           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8407               <= GET_MODE_PRECISION (GET_MODE (x)))
8408           /* Must be more sign bit copies than the mask needs.  */
8409           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8410               >= exact_log2 (mask + 1)))
8411         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8412                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8413                                           - exact_log2 (mask + 1)));
8414
8415       goto shiftrt;
8416
8417     case ASHIFTRT:
8418       /* If we are just looking for the sign bit, we don't need this shift at
8419          all, even if it has a variable count.  */
8420       if (val_signbit_p (GET_MODE (x), mask))
8421         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8422
8423       /* If this is a shift by a constant, get a mask that contains those bits
8424          that are not copies of the sign bit.  We then have two cases:  If
8425          MASK only includes those bits, this can be a logical shift, which may
8426          allow simplifications.  If MASK is a single-bit field not within
8427          those bits, we are requesting a copy of the sign bit and hence can
8428          shift the sign bit to the appropriate location.  */
8429
8430       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8431           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8432         {
8433           int i;
8434
8435           /* If the considered data is wider than HOST_WIDE_INT, we can't
8436              represent a mask for all its bits in a single scalar.
8437              But we only care about the lower bits, so calculate these.  */
8438
8439           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8440             {
8441               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8442
8443               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8444                  is the number of bits a full-width mask would have set.
8445                  We need only shift if these are fewer than nonzero can
8446                  hold.  If not, we must keep all bits set in nonzero.  */
8447
8448               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8449                   < HOST_BITS_PER_WIDE_INT)
8450                 nonzero >>= INTVAL (XEXP (x, 1))
8451                             + HOST_BITS_PER_WIDE_INT
8452                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8453             }
8454           else
8455             {
8456               nonzero = GET_MODE_MASK (GET_MODE (x));
8457               nonzero >>= INTVAL (XEXP (x, 1));
8458             }
8459
8460           if ((mask & ~nonzero) == 0)
8461             {
8462               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8463                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8464               if (GET_CODE (x) != ASHIFTRT)
8465                 return force_to_mode (x, mode, mask, next_select);
8466             }
8467
8468           else if ((i = exact_log2 (mask)) >= 0)
8469             {
8470               x = simplify_shift_const
8471                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8472                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8473
8474               if (GET_CODE (x) != ASHIFTRT)
8475                 return force_to_mode (x, mode, mask, next_select);
8476             }
8477         }
8478
8479       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8480          even if the shift count isn't a constant.  */
8481       if (mask == 1)
8482         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8483                                  XEXP (x, 0), XEXP (x, 1));
8484
8485     shiftrt:
8486
8487       /* If this is a zero- or sign-extension operation that just affects bits
8488          we don't care about, remove it.  Be sure the call above returned
8489          something that is still a shift.  */
8490
8491       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8492           && CONST_INT_P (XEXP (x, 1))
8493           && INTVAL (XEXP (x, 1)) >= 0
8494           && (INTVAL (XEXP (x, 1))
8495               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8496           && GET_CODE (XEXP (x, 0)) == ASHIFT
8497           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8498         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8499                               next_select);
8500
8501       break;
8502
8503     case ROTATE:
8504     case ROTATERT:
8505       /* If the shift count is constant and we can do computations
8506          in the mode of X, compute where the bits we care about are.
8507          Otherwise, we can't do anything.  Don't change the mode of
8508          the shift or propagate MODE into the shift, though.  */
8509       if (CONST_INT_P (XEXP (x, 1))
8510           && INTVAL (XEXP (x, 1)) >= 0)
8511         {
8512           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8513                                             GET_MODE (x),
8514                                             gen_int_mode (mask, GET_MODE (x)),
8515                                             XEXP (x, 1));
8516           if (temp && CONST_INT_P (temp))
8517             x = simplify_gen_binary (code, GET_MODE (x),
8518                                      force_to_mode (XEXP (x, 0), GET_MODE (x),
8519                                                     INTVAL (temp), next_select),
8520                                      XEXP (x, 1));
8521         }
8522       break;
8523
8524     case NEG:
8525       /* If we just want the low-order bit, the NEG isn't needed since it
8526          won't change the low-order bit.  */
8527       if (mask == 1)
8528         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8529
8530       /* We need any bits less significant than the most significant bit in
8531          MASK since carries from those bits will affect the bits we are
8532          interested in.  */
8533       mask = fuller_mask;
8534       goto unop;
8535
8536     case NOT:
8537       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8538          same as the XOR case above.  Ensure that the constant we form is not
8539          wider than the mode of X.  */
8540
8541       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8542           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8543           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8544           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8545               < GET_MODE_PRECISION (GET_MODE (x)))
8546           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8547         {
8548           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8549                                GET_MODE (x));
8550           temp = simplify_gen_binary (XOR, GET_MODE (x),
8551                                       XEXP (XEXP (x, 0), 0), temp);
8552           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8553                                    temp, XEXP (XEXP (x, 0), 1));
8554
8555           return force_to_mode (x, mode, mask, next_select);
8556         }
8557
8558       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8559          use the full mask inside the NOT.  */
8560       mask = fuller_mask;
8561
8562     unop:
8563       op0 = gen_lowpart_or_truncate (op_mode,
8564                                      force_to_mode (XEXP (x, 0), mode, mask,
8565                                                     next_select));
8566       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8567         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8568       break;
8569
8570     case NE:
8571       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8572          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8573          which is equal to STORE_FLAG_VALUE.  */
8574       if ((mask & ~STORE_FLAG_VALUE) == 0
8575           && XEXP (x, 1) == const0_rtx
8576           && GET_MODE (XEXP (x, 0)) == mode
8577           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8578           && (nonzero_bits (XEXP (x, 0), mode)
8579               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8580         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8581
8582       break;
8583
8584     case IF_THEN_ELSE:
8585       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8586          written in a narrower mode.  We play it safe and do not do so.  */
8587
8588       op0 = gen_lowpart_or_truncate (GET_MODE (x),
8589                                      force_to_mode (XEXP (x, 1), mode,
8590                                                     mask, next_select));
8591       op1 = gen_lowpart_or_truncate (GET_MODE (x),
8592                                      force_to_mode (XEXP (x, 2), mode,
8593                                                     mask, next_select));
8594       if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
8595         x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),
8596                                   GET_MODE (XEXP (x, 0)), XEXP (x, 0),
8597                                   op0, op1);
8598       break;
8599
8600     default:
8601       break;
8602     }
8603
8604   /* Ensure we return a value of the proper mode.  */
8605   return gen_lowpart_or_truncate (mode, x);
8606 }
8607 \f
8608 /* Return nonzero if X is an expression that has one of two values depending on
8609    whether some other value is zero or nonzero.  In that case, we return the
8610    value that is being tested, *PTRUE is set to the value if the rtx being
8611    returned has a nonzero value, and *PFALSE is set to the other alternative.
8612
8613    If we return zero, we set *PTRUE and *PFALSE to X.  */
8614
8615 static rtx
8616 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8617 {
8618   machine_mode mode = GET_MODE (x);
8619   enum rtx_code code = GET_CODE (x);
8620   rtx cond0, cond1, true0, true1, false0, false1;
8621   unsigned HOST_WIDE_INT nz;
8622
8623   /* If we are comparing a value against zero, we are done.  */
8624   if ((code == NE || code == EQ)
8625       && XEXP (x, 1) == const0_rtx)
8626     {
8627       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8628       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8629       return XEXP (x, 0);
8630     }
8631
8632   /* If this is a unary operation whose operand has one of two values, apply
8633      our opcode to compute those values.  */
8634   else if (UNARY_P (x)
8635            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8636     {
8637       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8638       *pfalse = simplify_gen_unary (code, mode, false0,
8639                                     GET_MODE (XEXP (x, 0)));
8640       return cond0;
8641     }
8642
8643   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8644      make can't possibly match and would suppress other optimizations.  */
8645   else if (code == COMPARE)
8646     ;
8647
8648   /* If this is a binary operation, see if either side has only one of two
8649      values.  If either one does or if both do and they are conditional on
8650      the same value, compute the new true and false values.  */
8651   else if (BINARY_P (x))
8652     {
8653       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8654       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8655
8656       if ((cond0 != 0 || cond1 != 0)
8657           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8658         {
8659           /* If if_then_else_cond returned zero, then true/false are the
8660              same rtl.  We must copy one of them to prevent invalid rtl
8661              sharing.  */
8662           if (cond0 == 0)
8663             true0 = copy_rtx (true0);
8664           else if (cond1 == 0)
8665             true1 = copy_rtx (true1);
8666
8667           if (COMPARISON_P (x))
8668             {
8669               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8670                                                 true0, true1);
8671               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8672                                                  false0, false1);
8673              }
8674           else
8675             {
8676               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8677               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8678             }
8679
8680           return cond0 ? cond0 : cond1;
8681         }
8682
8683       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8684          operands is zero when the other is nonzero, and vice-versa,
8685          and STORE_FLAG_VALUE is 1 or -1.  */
8686
8687       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8688           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8689               || code == UMAX)
8690           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8691         {
8692           rtx op0 = XEXP (XEXP (x, 0), 1);
8693           rtx op1 = XEXP (XEXP (x, 1), 1);
8694
8695           cond0 = XEXP (XEXP (x, 0), 0);
8696           cond1 = XEXP (XEXP (x, 1), 0);
8697
8698           if (COMPARISON_P (cond0)
8699               && COMPARISON_P (cond1)
8700               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8701                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8702                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8703                   || ((swap_condition (GET_CODE (cond0))
8704                        == reversed_comparison_code (cond1, NULL))
8705                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8706                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8707               && ! side_effects_p (x))
8708             {
8709               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8710               *pfalse = simplify_gen_binary (MULT, mode,
8711                                              (code == MINUS
8712                                               ? simplify_gen_unary (NEG, mode,
8713                                                                     op1, mode)
8714                                               : op1),
8715                                               const_true_rtx);
8716               return cond0;
8717             }
8718         }
8719
8720       /* Similarly for MULT, AND and UMIN, except that for these the result
8721          is always zero.  */
8722       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8723           && (code == MULT || code == AND || code == UMIN)
8724           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8725         {
8726           cond0 = XEXP (XEXP (x, 0), 0);
8727           cond1 = XEXP (XEXP (x, 1), 0);
8728
8729           if (COMPARISON_P (cond0)
8730               && COMPARISON_P (cond1)
8731               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8732                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8733                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8734                   || ((swap_condition (GET_CODE (cond0))
8735                        == reversed_comparison_code (cond1, NULL))
8736                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8737                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8738               && ! side_effects_p (x))
8739             {
8740               *ptrue = *pfalse = const0_rtx;
8741               return cond0;
8742             }
8743         }
8744     }
8745
8746   else if (code == IF_THEN_ELSE)
8747     {
8748       /* If we have IF_THEN_ELSE already, extract the condition and
8749          canonicalize it if it is NE or EQ.  */
8750       cond0 = XEXP (x, 0);
8751       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8752       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8753         return XEXP (cond0, 0);
8754       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8755         {
8756           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8757           return XEXP (cond0, 0);
8758         }
8759       else
8760         return cond0;
8761     }
8762
8763   /* If X is a SUBREG, we can narrow both the true and false values
8764      if the inner expression, if there is a condition.  */
8765   else if (code == SUBREG
8766            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8767                                                &true0, &false0)))
8768     {
8769       true0 = simplify_gen_subreg (mode, true0,
8770                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8771       false0 = simplify_gen_subreg (mode, false0,
8772                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8773       if (true0 && false0)
8774         {
8775           *ptrue = true0;
8776           *pfalse = false0;
8777           return cond0;
8778         }
8779     }
8780
8781   /* If X is a constant, this isn't special and will cause confusions
8782      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8783   else if (CONSTANT_P (x)
8784            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8785     ;
8786
8787   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8788      will be least confusing to the rest of the compiler.  */
8789   else if (mode == BImode)
8790     {
8791       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8792       return x;
8793     }
8794
8795   /* If X is known to be either 0 or -1, those are the true and
8796      false values when testing X.  */
8797   else if (x == constm1_rtx || x == const0_rtx
8798            || (mode != VOIDmode
8799                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8800     {
8801       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8802       return x;
8803     }
8804
8805   /* Likewise for 0 or a single bit.  */
8806   else if (HWI_COMPUTABLE_MODE_P (mode)
8807            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8808     {
8809       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8810       return x;
8811     }
8812
8813   /* Otherwise fail; show no condition with true and false values the same.  */
8814   *ptrue = *pfalse = x;
8815   return 0;
8816 }
8817 \f
8818 /* Return the value of expression X given the fact that condition COND
8819    is known to be true when applied to REG as its first operand and VAL
8820    as its second.  X is known to not be shared and so can be modified in
8821    place.
8822
8823    We only handle the simplest cases, and specifically those cases that
8824    arise with IF_THEN_ELSE expressions.  */
8825
8826 static rtx
8827 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8828 {
8829   enum rtx_code code = GET_CODE (x);
8830   rtx temp;
8831   const char *fmt;
8832   int i, j;
8833
8834   if (side_effects_p (x))
8835     return x;
8836
8837   /* If either operand of the condition is a floating point value,
8838      then we have to avoid collapsing an EQ comparison.  */
8839   if (cond == EQ
8840       && rtx_equal_p (x, reg)
8841       && ! FLOAT_MODE_P (GET_MODE (x))
8842       && ! FLOAT_MODE_P (GET_MODE (val)))
8843     return val;
8844
8845   if (cond == UNEQ && rtx_equal_p (x, reg))
8846     return val;
8847
8848   /* If X is (abs REG) and we know something about REG's relationship
8849      with zero, we may be able to simplify this.  */
8850
8851   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8852     switch (cond)
8853       {
8854       case GE:  case GT:  case EQ:
8855         return XEXP (x, 0);
8856       case LT:  case LE:
8857         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8858                                    XEXP (x, 0),
8859                                    GET_MODE (XEXP (x, 0)));
8860       default:
8861         break;
8862       }
8863
8864   /* The only other cases we handle are MIN, MAX, and comparisons if the
8865      operands are the same as REG and VAL.  */
8866
8867   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8868     {
8869       if (rtx_equal_p (XEXP (x, 0), val))
8870         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8871
8872       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8873         {
8874           if (COMPARISON_P (x))
8875             {
8876               if (comparison_dominates_p (cond, code))
8877                 return const_true_rtx;
8878
8879               code = reversed_comparison_code (x, NULL);
8880               if (code != UNKNOWN
8881                   && comparison_dominates_p (cond, code))
8882                 return const0_rtx;
8883               else
8884                 return x;
8885             }
8886           else if (code == SMAX || code == SMIN
8887                    || code == UMIN || code == UMAX)
8888             {
8889               int unsignedp = (code == UMIN || code == UMAX);
8890
8891               /* Do not reverse the condition when it is NE or EQ.
8892                  This is because we cannot conclude anything about
8893                  the value of 'SMAX (x, y)' when x is not equal to y,
8894                  but we can when x equals y.  */
8895               if ((code == SMAX || code == UMAX)
8896                   && ! (cond == EQ || cond == NE))
8897                 cond = reverse_condition (cond);
8898
8899               switch (cond)
8900                 {
8901                 case GE:   case GT:
8902                   return unsignedp ? x : XEXP (x, 1);
8903                 case LE:   case LT:
8904                   return unsignedp ? x : XEXP (x, 0);
8905                 case GEU:  case GTU:
8906                   return unsignedp ? XEXP (x, 1) : x;
8907                 case LEU:  case LTU:
8908                   return unsignedp ? XEXP (x, 0) : x;
8909                 default:
8910                   break;
8911                 }
8912             }
8913         }
8914     }
8915   else if (code == SUBREG)
8916     {
8917       machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8918       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8919
8920       if (SUBREG_REG (x) != r)
8921         {
8922           /* We must simplify subreg here, before we lose track of the
8923              original inner_mode.  */
8924           new_rtx = simplify_subreg (GET_MODE (x), r,
8925                                  inner_mode, SUBREG_BYTE (x));
8926           if (new_rtx)
8927             return new_rtx;
8928           else
8929             SUBST (SUBREG_REG (x), r);
8930         }
8931
8932       return x;
8933     }
8934   /* We don't have to handle SIGN_EXTEND here, because even in the
8935      case of replacing something with a modeless CONST_INT, a
8936      CONST_INT is already (supposed to be) a valid sign extension for
8937      its narrower mode, which implies it's already properly
8938      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8939      story is different.  */
8940   else if (code == ZERO_EXTEND)
8941     {
8942       machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8943       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8944
8945       if (XEXP (x, 0) != r)
8946         {
8947           /* We must simplify the zero_extend here, before we lose
8948              track of the original inner_mode.  */
8949           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8950                                           r, inner_mode);
8951           if (new_rtx)
8952             return new_rtx;
8953           else
8954             SUBST (XEXP (x, 0), r);
8955         }
8956
8957       return x;
8958     }
8959
8960   fmt = GET_RTX_FORMAT (code);
8961   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8962     {
8963       if (fmt[i] == 'e')
8964         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8965       else if (fmt[i] == 'E')
8966         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8967           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8968                                                 cond, reg, val));
8969     }
8970
8971   return x;
8972 }
8973 \f
8974 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8975    assignment as a field assignment.  */
8976
8977 static int
8978 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8979 {
8980   if (x == y || rtx_equal_p (x, y))
8981     return 1;
8982
8983   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8984     return 0;
8985
8986   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8987      Note that all SUBREGs of MEM are paradoxical; otherwise they
8988      would have been rewritten.  */
8989   if (MEM_P (x) && GET_CODE (y) == SUBREG
8990       && MEM_P (SUBREG_REG (y))
8991       && rtx_equal_p (SUBREG_REG (y),
8992                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8993     return 1;
8994
8995   if (MEM_P (y) && GET_CODE (x) == SUBREG
8996       && MEM_P (SUBREG_REG (x))
8997       && rtx_equal_p (SUBREG_REG (x),
8998                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8999     return 1;
9000
9001   /* We used to see if get_last_value of X and Y were the same but that's
9002      not correct.  In one direction, we'll cause the assignment to have
9003      the wrong destination and in the case, we'll import a register into this
9004      insn that might have already have been dead.   So fail if none of the
9005      above cases are true.  */
9006   return 0;
9007 }
9008 \f
9009 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9010    Return that assignment if so.
9011
9012    We only handle the most common cases.  */
9013
9014 static rtx
9015 make_field_assignment (rtx x)
9016 {
9017   rtx dest = SET_DEST (x);
9018   rtx src = SET_SRC (x);
9019   rtx assign;
9020   rtx rhs, lhs;
9021   HOST_WIDE_INT c1;
9022   HOST_WIDE_INT pos;
9023   unsigned HOST_WIDE_INT len;
9024   rtx other;
9025   machine_mode mode;
9026
9027   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9028      a clear of a one-bit field.  We will have changed it to
9029      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
9030      for a SUBREG.  */
9031
9032   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9033       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9034       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9035       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9036     {
9037       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9038                                 1, 1, 1, 0);
9039       if (assign != 0)
9040         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9041       return x;
9042     }
9043
9044   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9045       && subreg_lowpart_p (XEXP (src, 0))
9046       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9047           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9048       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9049       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9050       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9051       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9052     {
9053       assign = make_extraction (VOIDmode, dest, 0,
9054                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9055                                 1, 1, 1, 0);
9056       if (assign != 0)
9057         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9058       return x;
9059     }
9060
9061   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9062      one-bit field.  */
9063   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9064       && XEXP (XEXP (src, 0), 0) == const1_rtx
9065       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9066     {
9067       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9068                                 1, 1, 1, 0);
9069       if (assign != 0)
9070         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9071       return x;
9072     }
9073
9074   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9075      SRC is an AND with all bits of that field set, then we can discard
9076      the AND.  */
9077   if (GET_CODE (dest) == ZERO_EXTRACT
9078       && CONST_INT_P (XEXP (dest, 1))
9079       && GET_CODE (src) == AND
9080       && CONST_INT_P (XEXP (src, 1)))
9081     {
9082       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9083       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9084       unsigned HOST_WIDE_INT ze_mask;
9085
9086       if (width >= HOST_BITS_PER_WIDE_INT)
9087         ze_mask = -1;
9088       else
9089         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9090
9091       /* Complete overlap.  We can remove the source AND.  */
9092       if ((and_mask & ze_mask) == ze_mask)
9093         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9094
9095       /* Partial overlap.  We can reduce the source AND.  */
9096       if ((and_mask & ze_mask) != and_mask)
9097         {
9098           mode = GET_MODE (src);
9099           src = gen_rtx_AND (mode, XEXP (src, 0),
9100                              gen_int_mode (and_mask & ze_mask, mode));
9101           return gen_rtx_SET (VOIDmode, dest, src);
9102         }
9103     }
9104
9105   /* The other case we handle is assignments into a constant-position
9106      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9107      a mask that has all one bits except for a group of zero bits and
9108      OTHER is known to have zeros where C1 has ones, this is such an
9109      assignment.  Compute the position and length from C1.  Shift OTHER
9110      to the appropriate position, force it to the required mode, and
9111      make the extraction.  Check for the AND in both operands.  */
9112
9113   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9114     return x;
9115
9116   rhs = expand_compound_operation (XEXP (src, 0));
9117   lhs = expand_compound_operation (XEXP (src, 1));
9118
9119   if (GET_CODE (rhs) == AND
9120       && CONST_INT_P (XEXP (rhs, 1))
9121       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9122     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9123   else if (GET_CODE (lhs) == AND
9124            && CONST_INT_P (XEXP (lhs, 1))
9125            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9126     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9127   else
9128     return x;
9129
9130   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9131   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9132       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9133       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9134     return x;
9135
9136   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9137   if (assign == 0)
9138     return x;
9139
9140   /* The mode to use for the source is the mode of the assignment, or of
9141      what is inside a possible STRICT_LOW_PART.  */
9142   mode = (GET_CODE (assign) == STRICT_LOW_PART
9143           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9144
9145   /* Shift OTHER right POS places and make it the source, restricting it
9146      to the proper length and mode.  */
9147
9148   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9149                                                      GET_MODE (src),
9150                                                      other, pos),
9151                                dest);
9152   src = force_to_mode (src, mode,
9153                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9154                        ? ~(unsigned HOST_WIDE_INT) 0
9155                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9156                        0);
9157
9158   /* If SRC is masked by an AND that does not make a difference in
9159      the value being stored, strip it.  */
9160   if (GET_CODE (assign) == ZERO_EXTRACT
9161       && CONST_INT_P (XEXP (assign, 1))
9162       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9163       && GET_CODE (src) == AND
9164       && CONST_INT_P (XEXP (src, 1))
9165       && UINTVAL (XEXP (src, 1))
9166          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9167     src = XEXP (src, 0);
9168
9169   return gen_rtx_SET (VOIDmode, assign, src);
9170 }
9171 \f
9172 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9173    if so.  */
9174
9175 static rtx
9176 apply_distributive_law (rtx x)
9177 {
9178   enum rtx_code code = GET_CODE (x);
9179   enum rtx_code inner_code;
9180   rtx lhs, rhs, other;
9181   rtx tem;
9182
9183   /* Distributivity is not true for floating point as it can change the
9184      value.  So we don't do it unless -funsafe-math-optimizations.  */
9185   if (FLOAT_MODE_P (GET_MODE (x))
9186       && ! flag_unsafe_math_optimizations)
9187     return x;
9188
9189   /* The outer operation can only be one of the following:  */
9190   if (code != IOR && code != AND && code != XOR
9191       && code != PLUS && code != MINUS)
9192     return x;
9193
9194   lhs = XEXP (x, 0);
9195   rhs = XEXP (x, 1);
9196
9197   /* If either operand is a primitive we can't do anything, so get out
9198      fast.  */
9199   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9200     return x;
9201
9202   lhs = expand_compound_operation (lhs);
9203   rhs = expand_compound_operation (rhs);
9204   inner_code = GET_CODE (lhs);
9205   if (inner_code != GET_CODE (rhs))
9206     return x;
9207
9208   /* See if the inner and outer operations distribute.  */
9209   switch (inner_code)
9210     {
9211     case LSHIFTRT:
9212     case ASHIFTRT:
9213     case AND:
9214     case IOR:
9215       /* These all distribute except over PLUS.  */
9216       if (code == PLUS || code == MINUS)
9217         return x;
9218       break;
9219
9220     case MULT:
9221       if (code != PLUS && code != MINUS)
9222         return x;
9223       break;
9224
9225     case ASHIFT:
9226       /* This is also a multiply, so it distributes over everything.  */
9227       break;
9228
9229     /* This used to handle SUBREG, but this turned out to be counter-
9230        productive, since (subreg (op ...)) usually is not handled by
9231        insn patterns, and this "optimization" therefore transformed
9232        recognizable patterns into unrecognizable ones.  Therefore the
9233        SUBREG case was removed from here.
9234
9235        It is possible that distributing SUBREG over arithmetic operations
9236        leads to an intermediate result than can then be optimized further,
9237        e.g. by moving the outer SUBREG to the other side of a SET as done
9238        in simplify_set.  This seems to have been the original intent of
9239        handling SUBREGs here.
9240
9241        However, with current GCC this does not appear to actually happen,
9242        at least on major platforms.  If some case is found where removing
9243        the SUBREG case here prevents follow-on optimizations, distributing
9244        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9245
9246     default:
9247       return x;
9248     }
9249
9250   /* Set LHS and RHS to the inner operands (A and B in the example
9251      above) and set OTHER to the common operand (C in the example).
9252      There is only one way to do this unless the inner operation is
9253      commutative.  */
9254   if (COMMUTATIVE_ARITH_P (lhs)
9255       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9256     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9257   else if (COMMUTATIVE_ARITH_P (lhs)
9258            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9259     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9260   else if (COMMUTATIVE_ARITH_P (lhs)
9261            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9262     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9263   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9264     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9265   else
9266     return x;
9267
9268   /* Form the new inner operation, seeing if it simplifies first.  */
9269   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9270
9271   /* There is one exception to the general way of distributing:
9272      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9273   if (code == XOR && inner_code == IOR)
9274     {
9275       inner_code = AND;
9276       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9277     }
9278
9279   /* We may be able to continuing distributing the result, so call
9280      ourselves recursively on the inner operation before forming the
9281      outer operation, which we return.  */
9282   return simplify_gen_binary (inner_code, GET_MODE (x),
9283                               apply_distributive_law (tem), other);
9284 }
9285
9286 /* See if X is of the form (* (+ A B) C), and if so convert to
9287    (+ (* A C) (* B C)) and try to simplify.
9288
9289    Most of the time, this results in no change.  However, if some of
9290    the operands are the same or inverses of each other, simplifications
9291    will result.
9292
9293    For example, (and (ior A B) (not B)) can occur as the result of
9294    expanding a bit field assignment.  When we apply the distributive
9295    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9296    which then simplifies to (and (A (not B))).
9297
9298    Note that no checks happen on the validity of applying the inverse
9299    distributive law.  This is pointless since we can do it in the
9300    few places where this routine is called.
9301
9302    N is the index of the term that is decomposed (the arithmetic operation,
9303    i.e. (+ A B) in the first example above).  !N is the index of the term that
9304    is distributed, i.e. of C in the first example above.  */
9305 static rtx
9306 distribute_and_simplify_rtx (rtx x, int n)
9307 {
9308   machine_mode mode;
9309   enum rtx_code outer_code, inner_code;
9310   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9311
9312   /* Distributivity is not true for floating point as it can change the
9313      value.  So we don't do it unless -funsafe-math-optimizations.  */
9314   if (FLOAT_MODE_P (GET_MODE (x))
9315       && ! flag_unsafe_math_optimizations)
9316     return NULL_RTX;
9317
9318   decomposed = XEXP (x, n);
9319   if (!ARITHMETIC_P (decomposed))
9320     return NULL_RTX;
9321
9322   mode = GET_MODE (x);
9323   outer_code = GET_CODE (x);
9324   distributed = XEXP (x, !n);
9325
9326   inner_code = GET_CODE (decomposed);
9327   inner_op0 = XEXP (decomposed, 0);
9328   inner_op1 = XEXP (decomposed, 1);
9329
9330   /* Special case (and (xor B C) (not A)), which is equivalent to
9331      (xor (ior A B) (ior A C))  */
9332   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9333     {
9334       distributed = XEXP (distributed, 0);
9335       outer_code = IOR;
9336     }
9337
9338   if (n == 0)
9339     {
9340       /* Distribute the second term.  */
9341       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9342       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9343     }
9344   else
9345     {
9346       /* Distribute the first term.  */
9347       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9348       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9349     }
9350
9351   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9352                                                      new_op0, new_op1));
9353   if (GET_CODE (tmp) != outer_code
9354       && (set_src_cost (tmp, optimize_this_for_speed_p)
9355           < set_src_cost (x, optimize_this_for_speed_p)))
9356     return tmp;
9357
9358   return NULL_RTX;
9359 }
9360 \f
9361 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9362    in MODE.  Return an equivalent form, if different from (and VAROP
9363    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9364
9365 static rtx
9366 simplify_and_const_int_1 (machine_mode mode, rtx varop,
9367                           unsigned HOST_WIDE_INT constop)
9368 {
9369   unsigned HOST_WIDE_INT nonzero;
9370   unsigned HOST_WIDE_INT orig_constop;
9371   rtx orig_varop;
9372   int i;
9373
9374   orig_varop = varop;
9375   orig_constop = constop;
9376   if (GET_CODE (varop) == CLOBBER)
9377     return NULL_RTX;
9378
9379   /* Simplify VAROP knowing that we will be only looking at some of the
9380      bits in it.
9381
9382      Note by passing in CONSTOP, we guarantee that the bits not set in
9383      CONSTOP are not significant and will never be examined.  We must
9384      ensure that is the case by explicitly masking out those bits
9385      before returning.  */
9386   varop = force_to_mode (varop, mode, constop, 0);
9387
9388   /* If VAROP is a CLOBBER, we will fail so return it.  */
9389   if (GET_CODE (varop) == CLOBBER)
9390     return varop;
9391
9392   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9393      to VAROP and return the new constant.  */
9394   if (CONST_INT_P (varop))
9395     return gen_int_mode (INTVAL (varop) & constop, mode);
9396
9397   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9398      a call to nonzero_bits, here we don't care about bits outside
9399      MODE.  */
9400
9401   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9402
9403   /* Turn off all bits in the constant that are known to already be zero.
9404      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9405      which is tested below.  */
9406
9407   constop &= nonzero;
9408
9409   /* If we don't have any bits left, return zero.  */
9410   if (constop == 0)
9411     return const0_rtx;
9412
9413   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9414      a power of two, we can replace this with an ASHIFT.  */
9415   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9416       && (i = exact_log2 (constop)) >= 0)
9417     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9418
9419   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9420      or XOR, then try to apply the distributive law.  This may eliminate
9421      operations if either branch can be simplified because of the AND.
9422      It may also make some cases more complex, but those cases probably
9423      won't match a pattern either with or without this.  */
9424
9425   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9426     return
9427       gen_lowpart
9428         (mode,
9429          apply_distributive_law
9430          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9431                                simplify_and_const_int (NULL_RTX,
9432                                                        GET_MODE (varop),
9433                                                        XEXP (varop, 0),
9434                                                        constop),
9435                                simplify_and_const_int (NULL_RTX,
9436                                                        GET_MODE (varop),
9437                                                        XEXP (varop, 1),
9438                                                        constop))));
9439
9440   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9441      the AND and see if one of the operands simplifies to zero.  If so, we
9442      may eliminate it.  */
9443
9444   if (GET_CODE (varop) == PLUS
9445       && exact_log2 (constop + 1) >= 0)
9446     {
9447       rtx o0, o1;
9448
9449       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9450       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9451       if (o0 == const0_rtx)
9452         return o1;
9453       if (o1 == const0_rtx)
9454         return o0;
9455     }
9456
9457   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9458   varop = gen_lowpart (mode, varop);
9459   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9460     return NULL_RTX;
9461
9462   /* If we are only masking insignificant bits, return VAROP.  */
9463   if (constop == nonzero)
9464     return varop;
9465
9466   if (varop == orig_varop && constop == orig_constop)
9467     return NULL_RTX;
9468
9469   /* Otherwise, return an AND.  */
9470   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9471 }
9472
9473
9474 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9475    in MODE.
9476
9477    Return an equivalent form, if different from X.  Otherwise, return X.  If
9478    X is zero, we are to always construct the equivalent form.  */
9479
9480 static rtx
9481 simplify_and_const_int (rtx x, machine_mode mode, rtx varop,
9482                         unsigned HOST_WIDE_INT constop)
9483 {
9484   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9485   if (tem)
9486     return tem;
9487
9488   if (!x)
9489     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9490                              gen_int_mode (constop, mode));
9491   if (GET_MODE (x) != mode)
9492     x = gen_lowpart (mode, x);
9493   return x;
9494 }
9495 \f
9496 /* Given a REG, X, compute which bits in X can be nonzero.
9497    We don't care about bits outside of those defined in MODE.
9498
9499    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9500    a shift, AND, or zero_extract, we can do better.  */
9501
9502 static rtx
9503 reg_nonzero_bits_for_combine (const_rtx x, machine_mode mode,
9504                               const_rtx known_x ATTRIBUTE_UNUSED,
9505                               machine_mode known_mode ATTRIBUTE_UNUSED,
9506                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9507                               unsigned HOST_WIDE_INT *nonzero)
9508 {
9509   rtx tem;
9510   reg_stat_type *rsp;
9511
9512   /* If X is a register whose nonzero bits value is current, use it.
9513      Otherwise, if X is a register whose value we can find, use that
9514      value.  Otherwise, use the previously-computed global nonzero bits
9515      for this register.  */
9516
9517   rsp = &reg_stat[REGNO (x)];
9518   if (rsp->last_set_value != 0
9519       && (rsp->last_set_mode == mode
9520           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9521               && GET_MODE_CLASS (mode) == MODE_INT))
9522       && ((rsp->last_set_label >= label_tick_ebb_start
9523            && rsp->last_set_label < label_tick)
9524           || (rsp->last_set_label == label_tick
9525               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9526           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9527               && REG_N_SETS (REGNO (x)) == 1
9528               && !REGNO_REG_SET_P
9529                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9530                    REGNO (x)))))
9531     {
9532       unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits;
9533
9534       if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode))
9535         /* We don't know anything about the upper bits.  */
9536         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode);
9537
9538       *nonzero &= mask;
9539       return NULL;
9540     }
9541
9542   tem = get_last_value (x);
9543
9544   if (tem)
9545     {
9546 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9547       /* If X is narrower than MODE and TEM is a non-negative
9548          constant that would appear negative in the mode of X,
9549          sign-extend it for use in reg_nonzero_bits because some
9550          machines (maybe most) will actually do the sign-extension
9551          and this is the conservative approach.
9552
9553          ??? For 2.5, try to tighten up the MD files in this regard
9554          instead of this kludge.  */
9555
9556       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9557           && CONST_INT_P (tem)
9558           && INTVAL (tem) > 0
9559           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9560         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9561 #endif
9562       return tem;
9563     }
9564   else if (nonzero_sign_valid && rsp->nonzero_bits)
9565     {
9566       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9567
9568       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9569         /* We don't know anything about the upper bits.  */
9570         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9571
9572       *nonzero &= mask;
9573     }
9574
9575   return NULL;
9576 }
9577
9578 /* Return the number of bits at the high-order end of X that are known to
9579    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9580    VOIDmode, X will be used in its own mode.  The returned value  will always
9581    be between 1 and the number of bits in MODE.  */
9582
9583 static rtx
9584 reg_num_sign_bit_copies_for_combine (const_rtx x, machine_mode mode,
9585                                      const_rtx known_x ATTRIBUTE_UNUSED,
9586                                      machine_mode known_mode
9587                                      ATTRIBUTE_UNUSED,
9588                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9589                                      unsigned int *result)
9590 {
9591   rtx tem;
9592   reg_stat_type *rsp;
9593
9594   rsp = &reg_stat[REGNO (x)];
9595   if (rsp->last_set_value != 0
9596       && rsp->last_set_mode == mode
9597       && ((rsp->last_set_label >= label_tick_ebb_start
9598            && rsp->last_set_label < label_tick)
9599           || (rsp->last_set_label == label_tick
9600               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9601           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9602               && REG_N_SETS (REGNO (x)) == 1
9603               && !REGNO_REG_SET_P
9604                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9605                    REGNO (x)))))
9606     {
9607       *result = rsp->last_set_sign_bit_copies;
9608       return NULL;
9609     }
9610
9611   tem = get_last_value (x);
9612   if (tem != 0)
9613     return tem;
9614
9615   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9616       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9617     *result = rsp->sign_bit_copies;
9618
9619   return NULL;
9620 }
9621 \f
9622 /* Return the number of "extended" bits there are in X, when interpreted
9623    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9624    unsigned quantities, this is the number of high-order zero bits.
9625    For signed quantities, this is the number of copies of the sign bit
9626    minus 1.  In both case, this function returns the number of "spare"
9627    bits.  For example, if two quantities for which this function returns
9628    at least 1 are added, the addition is known not to overflow.
9629
9630    This function will always return 0 unless called during combine, which
9631    implies that it must be called from a define_split.  */
9632
9633 unsigned int
9634 extended_count (const_rtx x, machine_mode mode, int unsignedp)
9635 {
9636   if (nonzero_sign_valid == 0)
9637     return 0;
9638
9639   return (unsignedp
9640           ? (HWI_COMPUTABLE_MODE_P (mode)
9641              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9642                                - floor_log2 (nonzero_bits (x, mode)))
9643              : 0)
9644           : num_sign_bit_copies (x, mode) - 1);
9645 }
9646
9647 /* This function is called from `simplify_shift_const' to merge two
9648    outer operations.  Specifically, we have already found that we need
9649    to perform operation *POP0 with constant *PCONST0 at the outermost
9650    position.  We would now like to also perform OP1 with constant CONST1
9651    (with *POP0 being done last).
9652
9653    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9654    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9655    complement the innermost operand, otherwise it is unchanged.
9656
9657    MODE is the mode in which the operation will be done.  No bits outside
9658    the width of this mode matter.  It is assumed that the width of this mode
9659    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9660
9661    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9662    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9663    result is simply *PCONST0.
9664
9665    If the resulting operation cannot be expressed as one operation, we
9666    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9667
9668 static int
9669 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9670 {
9671   enum rtx_code op0 = *pop0;
9672   HOST_WIDE_INT const0 = *pconst0;
9673
9674   const0 &= GET_MODE_MASK (mode);
9675   const1 &= GET_MODE_MASK (mode);
9676
9677   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9678   if (op0 == AND)
9679     const1 &= const0;
9680
9681   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9682      if OP0 is SET.  */
9683
9684   if (op1 == UNKNOWN || op0 == SET)
9685     return 1;
9686
9687   else if (op0 == UNKNOWN)
9688     op0 = op1, const0 = const1;
9689
9690   else if (op0 == op1)
9691     {
9692       switch (op0)
9693         {
9694         case AND:
9695           const0 &= const1;
9696           break;
9697         case IOR:
9698           const0 |= const1;
9699           break;
9700         case XOR:
9701           const0 ^= const1;
9702           break;
9703         case PLUS:
9704           const0 += const1;
9705           break;
9706         case NEG:
9707           op0 = UNKNOWN;
9708           break;
9709         default:
9710           break;
9711         }
9712     }
9713
9714   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9715   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9716     return 0;
9717
9718   /* If the two constants aren't the same, we can't do anything.  The
9719      remaining six cases can all be done.  */
9720   else if (const0 != const1)
9721     return 0;
9722
9723   else
9724     switch (op0)
9725       {
9726       case IOR:
9727         if (op1 == AND)
9728           /* (a & b) | b == b */
9729           op0 = SET;
9730         else /* op1 == XOR */
9731           /* (a ^ b) | b == a | b */
9732           {;}
9733         break;
9734
9735       case XOR:
9736         if (op1 == AND)
9737           /* (a & b) ^ b == (~a) & b */
9738           op0 = AND, *pcomp_p = 1;
9739         else /* op1 == IOR */
9740           /* (a | b) ^ b == a & ~b */
9741           op0 = AND, const0 = ~const0;
9742         break;
9743
9744       case AND:
9745         if (op1 == IOR)
9746           /* (a | b) & b == b */
9747         op0 = SET;
9748         else /* op1 == XOR */
9749           /* (a ^ b) & b) == (~a) & b */
9750           *pcomp_p = 1;
9751         break;
9752       default:
9753         break;
9754       }
9755
9756   /* Check for NO-OP cases.  */
9757   const0 &= GET_MODE_MASK (mode);
9758   if (const0 == 0
9759       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9760     op0 = UNKNOWN;
9761   else if (const0 == 0 && op0 == AND)
9762     op0 = SET;
9763   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9764            && op0 == AND)
9765     op0 = UNKNOWN;
9766
9767   *pop0 = op0;
9768
9769   /* ??? Slightly redundant with the above mask, but not entirely.
9770      Moving this above means we'd have to sign-extend the mode mask
9771      for the final test.  */
9772   if (op0 != UNKNOWN && op0 != NEG)
9773     *pconst0 = trunc_int_for_mode (const0, mode);
9774
9775   return 1;
9776 }
9777 \f
9778 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9779    the shift in.  The original shift operation CODE is performed on OP in
9780    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9781    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9782    result of the shift is subject to operation OUTER_CODE with operand
9783    OUTER_CONST.  */
9784
9785 static machine_mode
9786 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9787                       machine_mode orig_mode, machine_mode mode,
9788                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9789 {
9790   if (orig_mode == mode)
9791     return mode;
9792   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9793
9794   /* In general we can't perform in wider mode for right shift and rotate.  */
9795   switch (code)
9796     {
9797     case ASHIFTRT:
9798       /* We can still widen if the bits brought in from the left are identical
9799          to the sign bit of ORIG_MODE.  */
9800       if (num_sign_bit_copies (op, mode)
9801           > (unsigned) (GET_MODE_PRECISION (mode)
9802                         - GET_MODE_PRECISION (orig_mode)))
9803         return mode;
9804       return orig_mode;
9805
9806     case LSHIFTRT:
9807       /* Similarly here but with zero bits.  */
9808       if (HWI_COMPUTABLE_MODE_P (mode)
9809           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9810         return mode;
9811
9812       /* We can also widen if the bits brought in will be masked off.  This
9813          operation is performed in ORIG_MODE.  */
9814       if (outer_code == AND)
9815         {
9816           int care_bits = low_bitmask_len (orig_mode, outer_const);
9817
9818           if (care_bits >= 0
9819               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9820             return mode;
9821         }
9822       /* fall through */
9823
9824     case ROTATE:
9825       return orig_mode;
9826
9827     case ROTATERT:
9828       gcc_unreachable ();
9829
9830     default:
9831       return mode;
9832     }
9833 }
9834
9835 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9836    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9837    if we cannot simplify it.  Otherwise, return a simplified value.
9838
9839    The shift is normally computed in the widest mode we find in VAROP, as
9840    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9841    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9842
9843 static rtx
9844 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
9845                         rtx varop, int orig_count)
9846 {
9847   enum rtx_code orig_code = code;
9848   rtx orig_varop = varop;
9849   int count;
9850   machine_mode mode = result_mode;
9851   machine_mode shift_mode, tmode;
9852   unsigned int mode_words
9853     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9854   /* We form (outer_op (code varop count) (outer_const)).  */
9855   enum rtx_code outer_op = UNKNOWN;
9856   HOST_WIDE_INT outer_const = 0;
9857   int complement_p = 0;
9858   rtx new_rtx, x;
9859
9860   /* Make sure and truncate the "natural" shift on the way in.  We don't
9861      want to do this inside the loop as it makes it more difficult to
9862      combine shifts.  */
9863   if (SHIFT_COUNT_TRUNCATED)
9864     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9865
9866   /* If we were given an invalid count, don't do anything except exactly
9867      what was requested.  */
9868
9869   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9870     return NULL_RTX;
9871
9872   count = orig_count;
9873
9874   /* Unless one of the branches of the `if' in this loop does a `continue',
9875      we will `break' the loop after the `if'.  */
9876
9877   while (count != 0)
9878     {
9879       /* If we have an operand of (clobber (const_int 0)), fail.  */
9880       if (GET_CODE (varop) == CLOBBER)
9881         return NULL_RTX;
9882
9883       /* Convert ROTATERT to ROTATE.  */
9884       if (code == ROTATERT)
9885         {
9886           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9887           code = ROTATE;
9888           if (VECTOR_MODE_P (result_mode))
9889             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9890           else
9891             count = bitsize - count;
9892         }
9893
9894       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9895                                          mode, outer_op, outer_const);
9896
9897       /* Handle cases where the count is greater than the size of the mode
9898          minus 1.  For ASHIFT, use the size minus one as the count (this can
9899          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9900          take the count modulo the size.  For other shifts, the result is
9901          zero.
9902
9903          Since these shifts are being produced by the compiler by combining
9904          multiple operations, each of which are defined, we know what the
9905          result is supposed to be.  */
9906
9907       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9908         {
9909           if (code == ASHIFTRT)
9910             count = GET_MODE_PRECISION (shift_mode) - 1;
9911           else if (code == ROTATE || code == ROTATERT)
9912             count %= GET_MODE_PRECISION (shift_mode);
9913           else
9914             {
9915               /* We can't simply return zero because there may be an
9916                  outer op.  */
9917               varop = const0_rtx;
9918               count = 0;
9919               break;
9920             }
9921         }
9922
9923       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9924          here would cause an infinite loop.  */
9925       if (complement_p)
9926         break;
9927
9928       /* An arithmetic right shift of a quantity known to be -1 or 0
9929          is a no-op.  */
9930       if (code == ASHIFTRT
9931           && (num_sign_bit_copies (varop, shift_mode)
9932               == GET_MODE_PRECISION (shift_mode)))
9933         {
9934           count = 0;
9935           break;
9936         }
9937
9938       /* If we are doing an arithmetic right shift and discarding all but
9939          the sign bit copies, this is equivalent to doing a shift by the
9940          bitsize minus one.  Convert it into that shift because it will often
9941          allow other simplifications.  */
9942
9943       if (code == ASHIFTRT
9944           && (count + num_sign_bit_copies (varop, shift_mode)
9945               >= GET_MODE_PRECISION (shift_mode)))
9946         count = GET_MODE_PRECISION (shift_mode) - 1;
9947
9948       /* We simplify the tests below and elsewhere by converting
9949          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9950          `make_compound_operation' will convert it to an ASHIFTRT for
9951          those machines (such as VAX) that don't have an LSHIFTRT.  */
9952       if (code == ASHIFTRT
9953           && val_signbit_known_clear_p (shift_mode,
9954                                         nonzero_bits (varop, shift_mode)))
9955         code = LSHIFTRT;
9956
9957       if (((code == LSHIFTRT
9958             && HWI_COMPUTABLE_MODE_P (shift_mode)
9959             && !(nonzero_bits (varop, shift_mode) >> count))
9960            || (code == ASHIFT
9961                && HWI_COMPUTABLE_MODE_P (shift_mode)
9962                && !((nonzero_bits (varop, shift_mode) << count)
9963                     & GET_MODE_MASK (shift_mode))))
9964           && !side_effects_p (varop))
9965         varop = const0_rtx;
9966
9967       switch (GET_CODE (varop))
9968         {
9969         case SIGN_EXTEND:
9970         case ZERO_EXTEND:
9971         case SIGN_EXTRACT:
9972         case ZERO_EXTRACT:
9973           new_rtx = expand_compound_operation (varop);
9974           if (new_rtx != varop)
9975             {
9976               varop = new_rtx;
9977               continue;
9978             }
9979           break;
9980
9981         case MEM:
9982           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9983              minus the width of a smaller mode, we can do this with a
9984              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9985           if ((code == ASHIFTRT || code == LSHIFTRT)
9986               && ! mode_dependent_address_p (XEXP (varop, 0),
9987                                              MEM_ADDR_SPACE (varop))
9988               && ! MEM_VOLATILE_P (varop)
9989               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9990                                          MODE_INT, 1)) != BLKmode)
9991             {
9992               new_rtx = adjust_address_nv (varop, tmode,
9993                                        BYTES_BIG_ENDIAN ? 0
9994                                        : count / BITS_PER_UNIT);
9995
9996               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9997                                      : ZERO_EXTEND, mode, new_rtx);
9998               count = 0;
9999               continue;
10000             }
10001           break;
10002
10003         case SUBREG:
10004           /* If VAROP is a SUBREG, strip it as long as the inner operand has
10005              the same number of words as what we've seen so far.  Then store
10006              the widest mode in MODE.  */
10007           if (subreg_lowpart_p (varop)
10008               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10009                   > GET_MODE_SIZE (GET_MODE (varop)))
10010               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10011                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10012                  == mode_words
10013               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10014               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10015             {
10016               varop = SUBREG_REG (varop);
10017               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10018                 mode = GET_MODE (varop);
10019               continue;
10020             }
10021           break;
10022
10023         case MULT:
10024           /* Some machines use MULT instead of ASHIFT because MULT
10025              is cheaper.  But it is still better on those machines to
10026              merge two shifts into one.  */
10027           if (CONST_INT_P (XEXP (varop, 1))
10028               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10029             {
10030               varop
10031                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10032                                        XEXP (varop, 0),
10033                                        GEN_INT (exact_log2 (
10034                                                 UINTVAL (XEXP (varop, 1)))));
10035               continue;
10036             }
10037           break;
10038
10039         case UDIV:
10040           /* Similar, for when divides are cheaper.  */
10041           if (CONST_INT_P (XEXP (varop, 1))
10042               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10043             {
10044               varop
10045                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10046                                        XEXP (varop, 0),
10047                                        GEN_INT (exact_log2 (
10048                                                 UINTVAL (XEXP (varop, 1)))));
10049               continue;
10050             }
10051           break;
10052
10053         case ASHIFTRT:
10054           /* If we are extracting just the sign bit of an arithmetic
10055              right shift, that shift is not needed.  However, the sign
10056              bit of a wider mode may be different from what would be
10057              interpreted as the sign bit in a narrower mode, so, if
10058              the result is narrower, don't discard the shift.  */
10059           if (code == LSHIFTRT
10060               && count == (GET_MODE_BITSIZE (result_mode) - 1)
10061               && (GET_MODE_BITSIZE (result_mode)
10062                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
10063             {
10064               varop = XEXP (varop, 0);
10065               continue;
10066             }
10067
10068           /* ... fall through ...  */
10069
10070         case LSHIFTRT:
10071         case ASHIFT:
10072         case ROTATE:
10073           /* Here we have two nested shifts.  The result is usually the
10074              AND of a new shift with a mask.  We compute the result below.  */
10075           if (CONST_INT_P (XEXP (varop, 1))
10076               && INTVAL (XEXP (varop, 1)) >= 0
10077               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10078               && HWI_COMPUTABLE_MODE_P (result_mode)
10079               && HWI_COMPUTABLE_MODE_P (mode)
10080               && !VECTOR_MODE_P (result_mode))
10081             {
10082               enum rtx_code first_code = GET_CODE (varop);
10083               unsigned int first_count = INTVAL (XEXP (varop, 1));
10084               unsigned HOST_WIDE_INT mask;
10085               rtx mask_rtx;
10086
10087               /* We have one common special case.  We can't do any merging if
10088                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10089                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10090                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10091                  we can convert it to
10092                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10093                  This simplifies certain SIGN_EXTEND operations.  */
10094               if (code == ASHIFT && first_code == ASHIFTRT
10095                   && count == (GET_MODE_PRECISION (result_mode)
10096                                - GET_MODE_PRECISION (GET_MODE (varop))))
10097                 {
10098                   /* C3 has the low-order C1 bits zero.  */
10099
10100                   mask = GET_MODE_MASK (mode)
10101                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10102
10103                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10104                                                   XEXP (varop, 0), mask);
10105                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10106                                                 varop, count);
10107                   count = first_count;
10108                   code = ASHIFTRT;
10109                   continue;
10110                 }
10111
10112               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10113                  than C1 high-order bits equal to the sign bit, we can convert
10114                  this to either an ASHIFT or an ASHIFTRT depending on the
10115                  two counts.
10116
10117                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10118
10119               if (code == ASHIFTRT && first_code == ASHIFT
10120                   && GET_MODE (varop) == shift_mode
10121                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10122                       > first_count))
10123                 {
10124                   varop = XEXP (varop, 0);
10125                   count -= first_count;
10126                   if (count < 0)
10127                     {
10128                       count = -count;
10129                       code = ASHIFT;
10130                     }
10131
10132                   continue;
10133                 }
10134
10135               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10136                  we can only do this if FIRST_CODE is also ASHIFTRT.
10137
10138                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10139                  ASHIFTRT.
10140
10141                  If the mode of this shift is not the mode of the outer shift,
10142                  we can't do this if either shift is a right shift or ROTATE.
10143
10144                  Finally, we can't do any of these if the mode is too wide
10145                  unless the codes are the same.
10146
10147                  Handle the case where the shift codes are the same
10148                  first.  */
10149
10150               if (code == first_code)
10151                 {
10152                   if (GET_MODE (varop) != result_mode
10153                       && (code == ASHIFTRT || code == LSHIFTRT
10154                           || code == ROTATE))
10155                     break;
10156
10157                   count += first_count;
10158                   varop = XEXP (varop, 0);
10159                   continue;
10160                 }
10161
10162               if (code == ASHIFTRT
10163                   || (code == ROTATE && first_code == ASHIFTRT)
10164                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10165                   || (GET_MODE (varop) != result_mode
10166                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10167                           || first_code == ROTATE
10168                           || code == ROTATE)))
10169                 break;
10170
10171               /* To compute the mask to apply after the shift, shift the
10172                  nonzero bits of the inner shift the same way the
10173                  outer shift will.  */
10174
10175               mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10176                                        result_mode);
10177
10178               mask_rtx
10179                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10180                                                    GEN_INT (count));
10181
10182               /* Give up if we can't compute an outer operation to use.  */
10183               if (mask_rtx == 0
10184                   || !CONST_INT_P (mask_rtx)
10185                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10186                                         INTVAL (mask_rtx),
10187                                         result_mode, &complement_p))
10188                 break;
10189
10190               /* If the shifts are in the same direction, we add the
10191                  counts.  Otherwise, we subtract them.  */
10192               if ((code == ASHIFTRT || code == LSHIFTRT)
10193                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10194                 count += first_count;
10195               else
10196                 count -= first_count;
10197
10198               /* If COUNT is positive, the new shift is usually CODE,
10199                  except for the two exceptions below, in which case it is
10200                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10201                  always be used  */
10202               if (count > 0
10203                   && ((first_code == ROTATE && code == ASHIFT)
10204                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10205                 code = first_code;
10206               else if (count < 0)
10207                 code = first_code, count = -count;
10208
10209               varop = XEXP (varop, 0);
10210               continue;
10211             }
10212
10213           /* If we have (A << B << C) for any shift, we can convert this to
10214              (A << C << B).  This wins if A is a constant.  Only try this if
10215              B is not a constant.  */
10216
10217           else if (GET_CODE (varop) == code
10218                    && CONST_INT_P (XEXP (varop, 0))
10219                    && !CONST_INT_P (XEXP (varop, 1)))
10220             {
10221               rtx new_rtx = simplify_const_binary_operation (code, mode,
10222                                                          XEXP (varop, 0),
10223                                                          GEN_INT (count));
10224               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10225               count = 0;
10226               continue;
10227             }
10228           break;
10229
10230         case NOT:
10231           if (VECTOR_MODE_P (mode))
10232             break;
10233
10234           /* Make this fit the case below.  */
10235           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10236           continue;
10237
10238         case IOR:
10239         case AND:
10240         case XOR:
10241           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10242              with C the size of VAROP - 1 and the shift is logical if
10243              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10244              we have an (le X 0) operation.   If we have an arithmetic shift
10245              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10246              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10247
10248           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10249               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10250               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10251               && (code == LSHIFTRT || code == ASHIFTRT)
10252               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10253               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10254             {
10255               count = 0;
10256               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10257                                   const0_rtx);
10258
10259               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10260                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10261
10262               continue;
10263             }
10264
10265           /* If we have (shift (logical)), move the logical to the outside
10266              to allow it to possibly combine with another logical and the
10267              shift to combine with another shift.  This also canonicalizes to
10268              what a ZERO_EXTRACT looks like.  Also, some machines have
10269              (and (shift)) insns.  */
10270
10271           if (CONST_INT_P (XEXP (varop, 1))
10272               /* We can't do this if we have (ashiftrt (xor))  and the
10273                  constant has its sign bit set in shift_mode with shift_mode
10274                  wider than result_mode.  */
10275               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10276                    && result_mode != shift_mode
10277                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10278                                               shift_mode))
10279               && (new_rtx = simplify_const_binary_operation
10280                   (code, result_mode,
10281                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10282                    GEN_INT (count))) != 0
10283               && CONST_INT_P (new_rtx)
10284               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10285                                   INTVAL (new_rtx), result_mode, &complement_p))
10286             {
10287               varop = XEXP (varop, 0);
10288               continue;
10289             }
10290
10291           /* If we can't do that, try to simplify the shift in each arm of the
10292              logical expression, make a new logical expression, and apply
10293              the inverse distributive law.  This also can't be done for
10294              (ashiftrt (xor)) where we've widened the shift and the constant
10295              changes the sign bit.  */
10296           if (CONST_INT_P (XEXP (varop, 1))
10297              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10298                   && result_mode != shift_mode
10299                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10300                                              shift_mode)))
10301             {
10302               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10303                                               XEXP (varop, 0), count);
10304               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10305                                               XEXP (varop, 1), count);
10306
10307               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10308                                            lhs, rhs);
10309               varop = apply_distributive_law (varop);
10310
10311               count = 0;
10312               continue;
10313             }
10314           break;
10315
10316         case EQ:
10317           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10318              says that the sign bit can be tested, FOO has mode MODE, C is
10319              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10320              that may be nonzero.  */
10321           if (code == LSHIFTRT
10322               && XEXP (varop, 1) == const0_rtx
10323               && GET_MODE (XEXP (varop, 0)) == result_mode
10324               && count == (GET_MODE_PRECISION (result_mode) - 1)
10325               && HWI_COMPUTABLE_MODE_P (result_mode)
10326               && STORE_FLAG_VALUE == -1
10327               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10328               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10329                                   &complement_p))
10330             {
10331               varop = XEXP (varop, 0);
10332               count = 0;
10333               continue;
10334             }
10335           break;
10336
10337         case NEG:
10338           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10339              than the number of bits in the mode is equivalent to A.  */
10340           if (code == LSHIFTRT
10341               && count == (GET_MODE_PRECISION (result_mode) - 1)
10342               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10343             {
10344               varop = XEXP (varop, 0);
10345               count = 0;
10346               continue;
10347             }
10348
10349           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10350              NEG outside to allow shifts to combine.  */
10351           if (code == ASHIFT
10352               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10353                                   &complement_p))
10354             {
10355               varop = XEXP (varop, 0);
10356               continue;
10357             }
10358           break;
10359
10360         case PLUS:
10361           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10362              is one less than the number of bits in the mode is
10363              equivalent to (xor A 1).  */
10364           if (code == LSHIFTRT
10365               && count == (GET_MODE_PRECISION (result_mode) - 1)
10366               && XEXP (varop, 1) == constm1_rtx
10367               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10368               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10369                                   &complement_p))
10370             {
10371               count = 0;
10372               varop = XEXP (varop, 0);
10373               continue;
10374             }
10375
10376           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10377              that might be nonzero in BAR are those being shifted out and those
10378              bits are known zero in FOO, we can replace the PLUS with FOO.
10379              Similarly in the other operand order.  This code occurs when
10380              we are computing the size of a variable-size array.  */
10381
10382           if ((code == ASHIFTRT || code == LSHIFTRT)
10383               && count < HOST_BITS_PER_WIDE_INT
10384               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10385               && (nonzero_bits (XEXP (varop, 1), result_mode)
10386                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10387             {
10388               varop = XEXP (varop, 0);
10389               continue;
10390             }
10391           else if ((code == ASHIFTRT || code == LSHIFTRT)
10392                    && count < HOST_BITS_PER_WIDE_INT
10393                    && HWI_COMPUTABLE_MODE_P (result_mode)
10394                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10395                             >> count)
10396                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10397                             & nonzero_bits (XEXP (varop, 1),
10398                                                  result_mode)))
10399             {
10400               varop = XEXP (varop, 1);
10401               continue;
10402             }
10403
10404           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10405           if (code == ASHIFT
10406               && CONST_INT_P (XEXP (varop, 1))
10407               && (new_rtx = simplify_const_binary_operation
10408                   (ASHIFT, result_mode,
10409                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10410                    GEN_INT (count))) != 0
10411               && CONST_INT_P (new_rtx)
10412               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10413                                   INTVAL (new_rtx), result_mode, &complement_p))
10414             {
10415               varop = XEXP (varop, 0);
10416               continue;
10417             }
10418
10419           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10420              signbit', and attempt to change the PLUS to an XOR and move it to
10421              the outer operation as is done above in the AND/IOR/XOR case
10422              leg for shift(logical). See details in logical handling above
10423              for reasoning in doing so.  */
10424           if (code == LSHIFTRT
10425               && CONST_INT_P (XEXP (varop, 1))
10426               && mode_signbit_p (result_mode, XEXP (varop, 1))
10427               && (new_rtx = simplify_const_binary_operation
10428                   (code, result_mode,
10429                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10430                    GEN_INT (count))) != 0
10431               && CONST_INT_P (new_rtx)
10432               && merge_outer_ops (&outer_op, &outer_const, XOR,
10433                                   INTVAL (new_rtx), result_mode, &complement_p))
10434             {
10435               varop = XEXP (varop, 0);
10436               continue;
10437             }
10438
10439           break;
10440
10441         case MINUS:
10442           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10443              with C the size of VAROP - 1 and the shift is logical if
10444              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10445              we have a (gt X 0) operation.  If the shift is arithmetic with
10446              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10447              we have a (neg (gt X 0)) operation.  */
10448
10449           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10450               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10451               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10452               && (code == LSHIFTRT || code == ASHIFTRT)
10453               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10454               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10455               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10456             {
10457               count = 0;
10458               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10459                                   const0_rtx);
10460
10461               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10462                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10463
10464               continue;
10465             }
10466           break;
10467
10468         case TRUNCATE:
10469           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10470              if the truncate does not affect the value.  */
10471           if (code == LSHIFTRT
10472               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10473               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10474               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10475                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10476                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10477             {
10478               rtx varop_inner = XEXP (varop, 0);
10479
10480               varop_inner
10481                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10482                                     XEXP (varop_inner, 0),
10483                                     GEN_INT
10484                                     (count + INTVAL (XEXP (varop_inner, 1))));
10485               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10486               count = 0;
10487               continue;
10488             }
10489           break;
10490
10491         default:
10492           break;
10493         }
10494
10495       break;
10496     }
10497
10498   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10499                                      outer_op, outer_const);
10500
10501   /* We have now finished analyzing the shift.  The result should be
10502      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10503      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10504      to the result of the shift.  OUTER_CONST is the relevant constant,
10505      but we must turn off all bits turned off in the shift.  */
10506
10507   if (outer_op == UNKNOWN
10508       && orig_code == code && orig_count == count
10509       && varop == orig_varop
10510       && shift_mode == GET_MODE (varop))
10511     return NULL_RTX;
10512
10513   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10514   varop = gen_lowpart (shift_mode, varop);
10515   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10516     return NULL_RTX;
10517
10518   /* If we have an outer operation and we just made a shift, it is
10519      possible that we could have simplified the shift were it not
10520      for the outer operation.  So try to do the simplification
10521      recursively.  */
10522
10523   if (outer_op != UNKNOWN)
10524     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10525   else
10526     x = NULL_RTX;
10527
10528   if (x == NULL_RTX)
10529     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10530
10531   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10532      turn off all the bits that the shift would have turned off.  */
10533   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10534     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10535                                 GET_MODE_MASK (result_mode) >> orig_count);
10536
10537   /* Do the remainder of the processing in RESULT_MODE.  */
10538   x = gen_lowpart_or_truncate (result_mode, x);
10539
10540   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10541      operation.  */
10542   if (complement_p)
10543     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10544
10545   if (outer_op != UNKNOWN)
10546     {
10547       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10548           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10549         outer_const = trunc_int_for_mode (outer_const, result_mode);
10550
10551       if (outer_op == AND)
10552         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10553       else if (outer_op == SET)
10554         {
10555           /* This means that we have determined that the result is
10556              equivalent to a constant.  This should be rare.  */
10557           if (!side_effects_p (x))
10558             x = GEN_INT (outer_const);
10559         }
10560       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10561         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10562       else
10563         x = simplify_gen_binary (outer_op, result_mode, x,
10564                                  GEN_INT (outer_const));
10565     }
10566
10567   return x;
10568 }
10569
10570 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10571    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10572    return X or, if it is NULL, synthesize the expression with
10573    simplify_gen_binary.  Otherwise, return a simplified value.
10574
10575    The shift is normally computed in the widest mode we find in VAROP, as
10576    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10577    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10578
10579 static rtx
10580 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
10581                       rtx varop, int count)
10582 {
10583   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10584   if (tem)
10585     return tem;
10586
10587   if (!x)
10588     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10589   if (GET_MODE (x) != result_mode)
10590     x = gen_lowpart (result_mode, x);
10591   return x;
10592 }
10593
10594 \f
10595 /* Like recog, but we receive the address of a pointer to a new pattern.
10596    We try to match the rtx that the pointer points to.
10597    If that fails, we may try to modify or replace the pattern,
10598    storing the replacement into the same pointer object.
10599
10600    Modifications include deletion or addition of CLOBBERs.
10601
10602    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10603    the CLOBBERs are placed.
10604
10605    The value is the final insn code from the pattern ultimately matched,
10606    or -1.  */
10607
10608 static int
10609 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
10610 {
10611   rtx pat = *pnewpat;
10612   rtx pat_without_clobbers;
10613   int insn_code_number;
10614   int num_clobbers_to_add = 0;
10615   int i;
10616   rtx notes = NULL_RTX;
10617   rtx old_notes, old_pat;
10618   int old_icode;
10619
10620   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10621      we use to indicate that something didn't match.  If we find such a
10622      thing, force rejection.  */
10623   if (GET_CODE (pat) == PARALLEL)
10624     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10625       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10626           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10627         return -1;
10628
10629   old_pat = PATTERN (insn);
10630   old_notes = REG_NOTES (insn);
10631   PATTERN (insn) = pat;
10632   REG_NOTES (insn) = NULL_RTX;
10633
10634   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10635   if (dump_file && (dump_flags & TDF_DETAILS))
10636     {
10637       if (insn_code_number < 0)
10638         fputs ("Failed to match this instruction:\n", dump_file);
10639       else
10640         fputs ("Successfully matched this instruction:\n", dump_file);
10641       print_rtl_single (dump_file, pat);
10642     }
10643
10644   /* If it isn't, there is the possibility that we previously had an insn
10645      that clobbered some register as a side effect, but the combined
10646      insn doesn't need to do that.  So try once more without the clobbers
10647      unless this represents an ASM insn.  */
10648
10649   if (insn_code_number < 0 && ! check_asm_operands (pat)
10650       && GET_CODE (pat) == PARALLEL)
10651     {
10652       int pos;
10653
10654       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10655         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10656           {
10657             if (i != pos)
10658               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10659             pos++;
10660           }
10661
10662       SUBST_INT (XVECLEN (pat, 0), pos);
10663
10664       if (pos == 1)
10665         pat = XVECEXP (pat, 0, 0);
10666
10667       PATTERN (insn) = pat;
10668       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10669       if (dump_file && (dump_flags & TDF_DETAILS))
10670         {
10671           if (insn_code_number < 0)
10672             fputs ("Failed to match this instruction:\n", dump_file);
10673           else
10674             fputs ("Successfully matched this instruction:\n", dump_file);
10675           print_rtl_single (dump_file, pat);
10676         }
10677     }
10678
10679   pat_without_clobbers = pat;
10680
10681   PATTERN (insn) = old_pat;
10682   REG_NOTES (insn) = old_notes;
10683
10684   /* Recognize all noop sets, these will be killed by followup pass.  */
10685   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10686     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10687
10688   /* If we had any clobbers to add, make a new pattern than contains
10689      them.  Then check to make sure that all of them are dead.  */
10690   if (num_clobbers_to_add)
10691     {
10692       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10693                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10694                                                   ? (XVECLEN (pat, 0)
10695                                                      + num_clobbers_to_add)
10696                                                   : num_clobbers_to_add + 1));
10697
10698       if (GET_CODE (pat) == PARALLEL)
10699         for (i = 0; i < XVECLEN (pat, 0); i++)
10700           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10701       else
10702         XVECEXP (newpat, 0, 0) = pat;
10703
10704       add_clobbers (newpat, insn_code_number);
10705
10706       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10707            i < XVECLEN (newpat, 0); i++)
10708         {
10709           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10710               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10711             return -1;
10712           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10713             {
10714               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10715               notes = alloc_reg_note (REG_UNUSED,
10716                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10717             }
10718         }
10719       pat = newpat;
10720     }
10721
10722   if (insn_code_number >= 0
10723       && insn_code_number != NOOP_MOVE_INSN_CODE)
10724     {
10725       old_pat = PATTERN (insn);
10726       old_notes = REG_NOTES (insn);
10727       old_icode = INSN_CODE (insn);
10728       PATTERN (insn) = pat;
10729       REG_NOTES (insn) = notes;
10730
10731       /* Allow targets to reject combined insn.  */
10732       if (!targetm.legitimate_combined_insn (insn))
10733         {
10734           if (dump_file && (dump_flags & TDF_DETAILS))
10735             fputs ("Instruction not appropriate for target.",
10736                    dump_file);
10737
10738           /* Callers expect recog_for_combine to strip
10739              clobbers from the pattern on failure.  */
10740           pat = pat_without_clobbers;
10741           notes = NULL_RTX;
10742
10743           insn_code_number = -1;
10744         }
10745
10746       PATTERN (insn) = old_pat;
10747       REG_NOTES (insn) = old_notes;
10748       INSN_CODE (insn) = old_icode;
10749     }
10750
10751   *pnewpat = pat;
10752   *pnotes = notes;
10753
10754   return insn_code_number;
10755 }
10756 \f
10757 /* Like gen_lowpart_general but for use by combine.  In combine it
10758    is not possible to create any new pseudoregs.  However, it is
10759    safe to create invalid memory addresses, because combine will
10760    try to recognize them and all they will do is make the combine
10761    attempt fail.
10762
10763    If for some reason this cannot do its job, an rtx
10764    (clobber (const_int 0)) is returned.
10765    An insn containing that will not be recognized.  */
10766
10767 static rtx
10768 gen_lowpart_for_combine (machine_mode omode, rtx x)
10769 {
10770   machine_mode imode = GET_MODE (x);
10771   unsigned int osize = GET_MODE_SIZE (omode);
10772   unsigned int isize = GET_MODE_SIZE (imode);
10773   rtx result;
10774
10775   if (omode == imode)
10776     return x;
10777
10778   /* We can only support MODE being wider than a word if X is a
10779      constant integer or has a mode the same size.  */
10780   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10781       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10782     goto fail;
10783
10784   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10785      won't know what to do.  So we will strip off the SUBREG here and
10786      process normally.  */
10787   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10788     {
10789       x = SUBREG_REG (x);
10790
10791       /* For use in case we fall down into the address adjustments
10792          further below, we need to adjust the known mode and size of
10793          x; imode and isize, since we just adjusted x.  */
10794       imode = GET_MODE (x);
10795
10796       if (imode == omode)
10797         return x;
10798
10799       isize = GET_MODE_SIZE (imode);
10800     }
10801
10802   result = gen_lowpart_common (omode, x);
10803
10804   if (result)
10805     return result;
10806
10807   if (MEM_P (x))
10808     {
10809       int offset = 0;
10810
10811       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10812          address.  */
10813       if (MEM_VOLATILE_P (x)
10814           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10815         goto fail;
10816
10817       /* If we want to refer to something bigger than the original memref,
10818          generate a paradoxical subreg instead.  That will force a reload
10819          of the original memref X.  */
10820       if (isize < osize)
10821         return gen_rtx_SUBREG (omode, x, 0);
10822
10823       if (WORDS_BIG_ENDIAN)
10824         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10825
10826       /* Adjust the address so that the address-after-the-data is
10827          unchanged.  */
10828       if (BYTES_BIG_ENDIAN)
10829         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10830
10831       return adjust_address_nv (x, omode, offset);
10832     }
10833
10834   /* If X is a comparison operator, rewrite it in a new mode.  This
10835      probably won't match, but may allow further simplifications.  */
10836   else if (COMPARISON_P (x))
10837     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10838
10839   /* If we couldn't simplify X any other way, just enclose it in a
10840      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10841      include an explicit SUBREG or we may simplify it further in combine.  */
10842   else
10843     {
10844       int offset = 0;
10845       rtx res;
10846
10847       offset = subreg_lowpart_offset (omode, imode);
10848       if (imode == VOIDmode)
10849         {
10850           imode = int_mode_for_mode (omode);
10851           x = gen_lowpart_common (imode, x);
10852           if (x == NULL)
10853             goto fail;
10854         }
10855       res = simplify_gen_subreg (omode, x, imode, offset);
10856       if (res)
10857         return res;
10858     }
10859
10860  fail:
10861   return gen_rtx_CLOBBER (omode, const0_rtx);
10862 }
10863 \f
10864 /* Try to simplify a comparison between OP0 and a constant OP1,
10865    where CODE is the comparison code that will be tested, into a
10866    (CODE OP0 const0_rtx) form.
10867
10868    The result is a possibly different comparison code to use.
10869    *POP1 may be updated.  */
10870
10871 static enum rtx_code
10872 simplify_compare_const (enum rtx_code code, machine_mode mode,
10873                         rtx op0, rtx *pop1)
10874 {
10875   unsigned int mode_width = GET_MODE_PRECISION (mode);
10876   HOST_WIDE_INT const_op = INTVAL (*pop1);
10877
10878   /* Get the constant we are comparing against and turn off all bits
10879      not on in our mode.  */
10880   if (mode != VOIDmode)
10881     const_op = trunc_int_for_mode (const_op, mode);
10882
10883   /* If we are comparing against a constant power of two and the value
10884      being compared can only have that single bit nonzero (e.g., it was
10885      `and'ed with that bit), we can replace this with a comparison
10886      with zero.  */
10887   if (const_op
10888       && (code == EQ || code == NE || code == GE || code == GEU
10889           || code == LT || code == LTU)
10890       && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10891       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10892       && (nonzero_bits (op0, mode)
10893           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10894     {
10895       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10896       const_op = 0;
10897     }
10898
10899   /* Similarly, if we are comparing a value known to be either -1 or
10900      0 with -1, change it to the opposite comparison against zero.  */
10901   if (const_op == -1
10902       && (code == EQ || code == NE || code == GT || code == LE
10903           || code == GEU || code == LTU)
10904       && num_sign_bit_copies (op0, mode) == mode_width)
10905     {
10906       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10907       const_op = 0;
10908     }
10909
10910   /* Do some canonicalizations based on the comparison code.  We prefer
10911      comparisons against zero and then prefer equality comparisons.
10912      If we can reduce the size of a constant, we will do that too.  */
10913   switch (code)
10914     {
10915     case LT:
10916       /* < C is equivalent to <= (C - 1) */
10917       if (const_op > 0)
10918         {
10919           const_op -= 1;
10920           code = LE;
10921           /* ... fall through to LE case below.  */
10922         }
10923       else
10924         break;
10925
10926     case LE:
10927       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10928       if (const_op < 0)
10929         {
10930           const_op += 1;
10931           code = LT;
10932         }
10933
10934       /* If we are doing a <= 0 comparison on a value known to have
10935          a zero sign bit, we can replace this with == 0.  */
10936       else if (const_op == 0
10937                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10938                && (nonzero_bits (op0, mode)
10939                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10940                == 0)
10941         code = EQ;
10942       break;
10943
10944     case GE:
10945       /* >= C is equivalent to > (C - 1).  */
10946       if (const_op > 0)
10947         {
10948           const_op -= 1;
10949           code = GT;
10950           /* ... fall through to GT below.  */
10951         }
10952       else
10953         break;
10954
10955     case GT:
10956       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10957       if (const_op < 0)
10958         {
10959           const_op += 1;
10960           code = GE;
10961         }
10962
10963       /* If we are doing a > 0 comparison on a value known to have
10964          a zero sign bit, we can replace this with != 0.  */
10965       else if (const_op == 0
10966                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10967                && (nonzero_bits (op0, mode)
10968                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10969                == 0)
10970         code = NE;
10971       break;
10972
10973     case LTU:
10974       /* < C is equivalent to <= (C - 1).  */
10975       if (const_op > 0)
10976         {
10977           const_op -= 1;
10978           code = LEU;
10979           /* ... fall through ...  */
10980         }
10981       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10982       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10983                && (unsigned HOST_WIDE_INT) const_op
10984                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10985         {
10986           const_op = 0;
10987           code = GE;
10988           break;
10989         }
10990       else
10991         break;
10992
10993     case LEU:
10994       /* unsigned <= 0 is equivalent to == 0 */
10995       if (const_op == 0)
10996         code = EQ;
10997       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10998       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10999                && (unsigned HOST_WIDE_INT) const_op
11000                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11001         {
11002           const_op = 0;
11003           code = GE;
11004         }
11005       break;
11006
11007     case GEU:
11008       /* >= C is equivalent to > (C - 1).  */
11009       if (const_op > 1)
11010         {
11011           const_op -= 1;
11012           code = GTU;
11013           /* ... fall through ...  */
11014         }
11015
11016       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
11017       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11018                && (unsigned HOST_WIDE_INT) const_op
11019                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11020         {
11021           const_op = 0;
11022           code = LT;
11023           break;
11024         }
11025       else
11026         break;
11027
11028     case GTU:
11029       /* unsigned > 0 is equivalent to != 0 */
11030       if (const_op == 0)
11031         code = NE;
11032       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
11033       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11034                && (unsigned HOST_WIDE_INT) const_op
11035                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11036         {
11037           const_op = 0;
11038           code = LT;
11039         }
11040       break;
11041
11042     default:
11043       break;
11044     }
11045
11046   *pop1 = GEN_INT (const_op);
11047   return code;
11048 }
11049 \f
11050 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11051    comparison code that will be tested.
11052
11053    The result is a possibly different comparison code to use.  *POP0 and
11054    *POP1 may be updated.
11055
11056    It is possible that we might detect that a comparison is either always
11057    true or always false.  However, we do not perform general constant
11058    folding in combine, so this knowledge isn't useful.  Such tautologies
11059    should have been detected earlier.  Hence we ignore all such cases.  */
11060
11061 static enum rtx_code
11062 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11063 {
11064   rtx op0 = *pop0;
11065   rtx op1 = *pop1;
11066   rtx tem, tem1;
11067   int i;
11068   machine_mode mode, tmode;
11069
11070   /* Try a few ways of applying the same transformation to both operands.  */
11071   while (1)
11072     {
11073 #ifndef WORD_REGISTER_OPERATIONS
11074       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11075          so check specially.  */
11076       if (code != GTU && code != GEU && code != LTU && code != LEU
11077           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11078           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11079           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11080           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11081           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11082           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11083               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11084           && CONST_INT_P (XEXP (op0, 1))
11085           && XEXP (op0, 1) == XEXP (op1, 1)
11086           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11087           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11088           && (INTVAL (XEXP (op0, 1))
11089               == (GET_MODE_PRECISION (GET_MODE (op0))
11090                   - (GET_MODE_PRECISION
11091                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11092         {
11093           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11094           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11095         }
11096 #endif
11097
11098       /* If both operands are the same constant shift, see if we can ignore the
11099          shift.  We can if the shift is a rotate or if the bits shifted out of
11100          this shift are known to be zero for both inputs and if the type of
11101          comparison is compatible with the shift.  */
11102       if (GET_CODE (op0) == GET_CODE (op1)
11103           && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11104           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11105               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11106                   && (code != GT && code != LT && code != GE && code != LE))
11107               || (GET_CODE (op0) == ASHIFTRT
11108                   && (code != GTU && code != LTU
11109                       && code != GEU && code != LEU)))
11110           && CONST_INT_P (XEXP (op0, 1))
11111           && INTVAL (XEXP (op0, 1)) >= 0
11112           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11113           && XEXP (op0, 1) == XEXP (op1, 1))
11114         {
11115           machine_mode mode = GET_MODE (op0);
11116           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11117           int shift_count = INTVAL (XEXP (op0, 1));
11118
11119           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11120             mask &= (mask >> shift_count) << shift_count;
11121           else if (GET_CODE (op0) == ASHIFT)
11122             mask = (mask & (mask << shift_count)) >> shift_count;
11123
11124           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11125               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11126             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11127           else
11128             break;
11129         }
11130
11131       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11132          SUBREGs are of the same mode, and, in both cases, the AND would
11133          be redundant if the comparison was done in the narrower mode,
11134          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11135          and the operand's possibly nonzero bits are 0xffffff01; in that case
11136          if we only care about QImode, we don't need the AND).  This case
11137          occurs if the output mode of an scc insn is not SImode and
11138          STORE_FLAG_VALUE == 1 (e.g., the 386).
11139
11140          Similarly, check for a case where the AND's are ZERO_EXTEND
11141          operations from some narrower mode even though a SUBREG is not
11142          present.  */
11143
11144       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11145                && CONST_INT_P (XEXP (op0, 1))
11146                && CONST_INT_P (XEXP (op1, 1)))
11147         {
11148           rtx inner_op0 = XEXP (op0, 0);
11149           rtx inner_op1 = XEXP (op1, 0);
11150           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11151           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11152           int changed = 0;
11153
11154           if (paradoxical_subreg_p (inner_op0)
11155               && GET_CODE (inner_op1) == SUBREG
11156               && (GET_MODE (SUBREG_REG (inner_op0))
11157                   == GET_MODE (SUBREG_REG (inner_op1)))
11158               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11159                   <= HOST_BITS_PER_WIDE_INT)
11160               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11161                                              GET_MODE (SUBREG_REG (inner_op0)))))
11162               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11163                                              GET_MODE (SUBREG_REG (inner_op1))))))
11164             {
11165               op0 = SUBREG_REG (inner_op0);
11166               op1 = SUBREG_REG (inner_op1);
11167
11168               /* The resulting comparison is always unsigned since we masked
11169                  off the original sign bit.  */
11170               code = unsigned_condition (code);
11171
11172               changed = 1;
11173             }
11174
11175           else if (c0 == c1)
11176             for (tmode = GET_CLASS_NARROWEST_MODE
11177                  (GET_MODE_CLASS (GET_MODE (op0)));
11178                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11179               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11180                 {
11181                   op0 = gen_lowpart (tmode, inner_op0);
11182                   op1 = gen_lowpart (tmode, inner_op1);
11183                   code = unsigned_condition (code);
11184                   changed = 1;
11185                   break;
11186                 }
11187
11188           if (! changed)
11189             break;
11190         }
11191
11192       /* If both operands are NOT, we can strip off the outer operation
11193          and adjust the comparison code for swapped operands; similarly for
11194          NEG, except that this must be an equality comparison.  */
11195       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11196                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11197                    && (code == EQ || code == NE)))
11198         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11199
11200       else
11201         break;
11202     }
11203
11204   /* If the first operand is a constant, swap the operands and adjust the
11205      comparison code appropriately, but don't do this if the second operand
11206      is already a constant integer.  */
11207   if (swap_commutative_operands_p (op0, op1))
11208     {
11209       tem = op0, op0 = op1, op1 = tem;
11210       code = swap_condition (code);
11211     }
11212
11213   /* We now enter a loop during which we will try to simplify the comparison.
11214      For the most part, we only are concerned with comparisons with zero,
11215      but some things may really be comparisons with zero but not start
11216      out looking that way.  */
11217
11218   while (CONST_INT_P (op1))
11219     {
11220       machine_mode mode = GET_MODE (op0);
11221       unsigned int mode_width = GET_MODE_PRECISION (mode);
11222       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11223       int equality_comparison_p;
11224       int sign_bit_comparison_p;
11225       int unsigned_comparison_p;
11226       HOST_WIDE_INT const_op;
11227
11228       /* We only want to handle integral modes.  This catches VOIDmode,
11229          CCmode, and the floating-point modes.  An exception is that we
11230          can handle VOIDmode if OP0 is a COMPARE or a comparison
11231          operation.  */
11232
11233       if (GET_MODE_CLASS (mode) != MODE_INT
11234           && ! (mode == VOIDmode
11235                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11236         break;
11237
11238       /* Try to simplify the compare to constant, possibly changing the
11239          comparison op, and/or changing op1 to zero.  */
11240       code = simplify_compare_const (code, mode, op0, &op1);
11241       const_op = INTVAL (op1);
11242
11243       /* Compute some predicates to simplify code below.  */
11244
11245       equality_comparison_p = (code == EQ || code == NE);
11246       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11247       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11248                                || code == GEU);
11249
11250       /* If this is a sign bit comparison and we can do arithmetic in
11251          MODE, say that we will only be needing the sign bit of OP0.  */
11252       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11253         op0 = force_to_mode (op0, mode,
11254                              (unsigned HOST_WIDE_INT) 1
11255                              << (GET_MODE_PRECISION (mode) - 1),
11256                              0);
11257
11258       /* Now try cases based on the opcode of OP0.  If none of the cases
11259          does a "continue", we exit this loop immediately after the
11260          switch.  */
11261
11262       switch (GET_CODE (op0))
11263         {
11264         case ZERO_EXTRACT:
11265           /* If we are extracting a single bit from a variable position in
11266              a constant that has only a single bit set and are comparing it
11267              with zero, we can convert this into an equality comparison
11268              between the position and the location of the single bit.  */
11269           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11270              have already reduced the shift count modulo the word size.  */
11271           if (!SHIFT_COUNT_TRUNCATED
11272               && CONST_INT_P (XEXP (op0, 0))
11273               && XEXP (op0, 1) == const1_rtx
11274               && equality_comparison_p && const_op == 0
11275               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11276             {
11277               if (BITS_BIG_ENDIAN)
11278                 i = BITS_PER_WORD - 1 - i;
11279
11280               op0 = XEXP (op0, 2);
11281               op1 = GEN_INT (i);
11282               const_op = i;
11283
11284               /* Result is nonzero iff shift count is equal to I.  */
11285               code = reverse_condition (code);
11286               continue;
11287             }
11288
11289           /* ... fall through ...  */
11290
11291         case SIGN_EXTRACT:
11292           tem = expand_compound_operation (op0);
11293           if (tem != op0)
11294             {
11295               op0 = tem;
11296               continue;
11297             }
11298           break;
11299
11300         case NOT:
11301           /* If testing for equality, we can take the NOT of the constant.  */
11302           if (equality_comparison_p
11303               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11304             {
11305               op0 = XEXP (op0, 0);
11306               op1 = tem;
11307               continue;
11308             }
11309
11310           /* If just looking at the sign bit, reverse the sense of the
11311              comparison.  */
11312           if (sign_bit_comparison_p)
11313             {
11314               op0 = XEXP (op0, 0);
11315               code = (code == GE ? LT : GE);
11316               continue;
11317             }
11318           break;
11319
11320         case NEG:
11321           /* If testing for equality, we can take the NEG of the constant.  */
11322           if (equality_comparison_p
11323               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11324             {
11325               op0 = XEXP (op0, 0);
11326               op1 = tem;
11327               continue;
11328             }
11329
11330           /* The remaining cases only apply to comparisons with zero.  */
11331           if (const_op != 0)
11332             break;
11333
11334           /* When X is ABS or is known positive,
11335              (neg X) is < 0 if and only if X != 0.  */
11336
11337           if (sign_bit_comparison_p
11338               && (GET_CODE (XEXP (op0, 0)) == ABS
11339                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11340                       && (nonzero_bits (XEXP (op0, 0), mode)
11341                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11342                          == 0)))
11343             {
11344               op0 = XEXP (op0, 0);
11345               code = (code == LT ? NE : EQ);
11346               continue;
11347             }
11348
11349           /* If we have NEG of something whose two high-order bits are the
11350              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11351           if (num_sign_bit_copies (op0, mode) >= 2)
11352             {
11353               op0 = XEXP (op0, 0);
11354               code = swap_condition (code);
11355               continue;
11356             }
11357           break;
11358
11359         case ROTATE:
11360           /* If we are testing equality and our count is a constant, we
11361              can perform the inverse operation on our RHS.  */
11362           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11363               && (tem = simplify_binary_operation (ROTATERT, mode,
11364                                                    op1, XEXP (op0, 1))) != 0)
11365             {
11366               op0 = XEXP (op0, 0);
11367               op1 = tem;
11368               continue;
11369             }
11370
11371           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11372              a particular bit.  Convert it to an AND of a constant of that
11373              bit.  This will be converted into a ZERO_EXTRACT.  */
11374           if (const_op == 0 && sign_bit_comparison_p
11375               && CONST_INT_P (XEXP (op0, 1))
11376               && mode_width <= HOST_BITS_PER_WIDE_INT)
11377             {
11378               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11379                                             ((unsigned HOST_WIDE_INT) 1
11380                                              << (mode_width - 1
11381                                                  - INTVAL (XEXP (op0, 1)))));
11382               code = (code == LT ? NE : EQ);
11383               continue;
11384             }
11385
11386           /* Fall through.  */
11387
11388         case ABS:
11389           /* ABS is ignorable inside an equality comparison with zero.  */
11390           if (const_op == 0 && equality_comparison_p)
11391             {
11392               op0 = XEXP (op0, 0);
11393               continue;
11394             }
11395           break;
11396
11397         case SIGN_EXTEND:
11398           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11399              (compare FOO CONST) if CONST fits in FOO's mode and we
11400              are either testing inequality or have an unsigned
11401              comparison with ZERO_EXTEND or a signed comparison with
11402              SIGN_EXTEND.  But don't do it if we don't have a compare
11403              insn of the given mode, since we'd have to revert it
11404              later on, and then we wouldn't know whether to sign- or
11405              zero-extend.  */
11406           mode = GET_MODE (XEXP (op0, 0));
11407           if (GET_MODE_CLASS (mode) == MODE_INT
11408               && ! unsigned_comparison_p
11409               && HWI_COMPUTABLE_MODE_P (mode)
11410               && trunc_int_for_mode (const_op, mode) == const_op
11411               && have_insn_for (COMPARE, mode))
11412             {
11413               op0 = XEXP (op0, 0);
11414               continue;
11415             }
11416           break;
11417
11418         case SUBREG:
11419           /* Check for the case where we are comparing A - C1 with C2, that is
11420
11421                (subreg:MODE (plus (A) (-C1))) op (C2)
11422
11423              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11424              comparison in the wider mode.  One of the following two conditions
11425              must be true in order for this to be valid:
11426
11427                1. The mode extension results in the same bit pattern being added
11428                   on both sides and the comparison is equality or unsigned.  As
11429                   C2 has been truncated to fit in MODE, the pattern can only be
11430                   all 0s or all 1s.
11431
11432                2. The mode extension results in the sign bit being copied on
11433                   each side.
11434
11435              The difficulty here is that we have predicates for A but not for
11436              (A - C1) so we need to check that C1 is within proper bounds so
11437              as to perturbate A as little as possible.  */
11438
11439           if (mode_width <= HOST_BITS_PER_WIDE_INT
11440               && subreg_lowpart_p (op0)
11441               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11442               && GET_CODE (SUBREG_REG (op0)) == PLUS
11443               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11444             {
11445               machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11446               rtx a = XEXP (SUBREG_REG (op0), 0);
11447               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11448
11449               if ((c1 > 0
11450                    && (unsigned HOST_WIDE_INT) c1
11451                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11452                    && (equality_comparison_p || unsigned_comparison_p)
11453                    /* (A - C1) zero-extends if it is positive and sign-extends
11454                       if it is negative, C2 both zero- and sign-extends.  */
11455                    && ((0 == (nonzero_bits (a, inner_mode)
11456                               & ~GET_MODE_MASK (mode))
11457                         && const_op >= 0)
11458                        /* (A - C1) sign-extends if it is positive and 1-extends
11459                           if it is negative, C2 both sign- and 1-extends.  */
11460                        || (num_sign_bit_copies (a, inner_mode)
11461                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11462                                              - mode_width)
11463                            && const_op < 0)))
11464                   || ((unsigned HOST_WIDE_INT) c1
11465                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11466                       /* (A - C1) always sign-extends, like C2.  */
11467                       && num_sign_bit_copies (a, inner_mode)
11468                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11469                                            - (mode_width - 1))))
11470                 {
11471                   op0 = SUBREG_REG (op0);
11472                   continue;
11473                 }
11474             }
11475
11476           /* If the inner mode is narrower and we are extracting the low part,
11477              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11478           if (subreg_lowpart_p (op0)
11479               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11480             /* Fall through */ ;
11481           else
11482             break;
11483
11484           /* ... fall through ...  */
11485
11486         case ZERO_EXTEND:
11487           mode = GET_MODE (XEXP (op0, 0));
11488           if (GET_MODE_CLASS (mode) == MODE_INT
11489               && (unsigned_comparison_p || equality_comparison_p)
11490               && HWI_COMPUTABLE_MODE_P (mode)
11491               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11492               && const_op >= 0
11493               && have_insn_for (COMPARE, mode))
11494             {
11495               op0 = XEXP (op0, 0);
11496               continue;
11497             }
11498           break;
11499
11500         case PLUS:
11501           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11502              this for equality comparisons due to pathological cases involving
11503              overflows.  */
11504           if (equality_comparison_p
11505               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11506                                                         op1, XEXP (op0, 1))))
11507             {
11508               op0 = XEXP (op0, 0);
11509               op1 = tem;
11510               continue;
11511             }
11512
11513           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11514           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11515               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11516             {
11517               op0 = XEXP (XEXP (op0, 0), 0);
11518               code = (code == LT ? EQ : NE);
11519               continue;
11520             }
11521           break;
11522
11523         case MINUS:
11524           /* We used to optimize signed comparisons against zero, but that
11525              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11526              arrive here as equality comparisons, or (GEU, LTU) are
11527              optimized away.  No need to special-case them.  */
11528
11529           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11530              (eq B (minus A C)), whichever simplifies.  We can only do
11531              this for equality comparisons due to pathological cases involving
11532              overflows.  */
11533           if (equality_comparison_p
11534               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11535                                                         XEXP (op0, 1), op1)))
11536             {
11537               op0 = XEXP (op0, 0);
11538               op1 = tem;
11539               continue;
11540             }
11541
11542           if (equality_comparison_p
11543               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11544                                                         XEXP (op0, 0), op1)))
11545             {
11546               op0 = XEXP (op0, 1);
11547               op1 = tem;
11548               continue;
11549             }
11550
11551           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11552              of bits in X minus 1, is one iff X > 0.  */
11553           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11554               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11555               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11556               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11557             {
11558               op0 = XEXP (op0, 1);
11559               code = (code == GE ? LE : GT);
11560               continue;
11561             }
11562           break;
11563
11564         case XOR:
11565           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11566              if C is zero or B is a constant.  */
11567           if (equality_comparison_p
11568               && 0 != (tem = simplify_binary_operation (XOR, mode,
11569                                                         XEXP (op0, 1), op1)))
11570             {
11571               op0 = XEXP (op0, 0);
11572               op1 = tem;
11573               continue;
11574             }
11575           break;
11576
11577         case EQ:  case NE:
11578         case UNEQ:  case LTGT:
11579         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11580         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11581         case UNORDERED: case ORDERED:
11582           /* We can't do anything if OP0 is a condition code value, rather
11583              than an actual data value.  */
11584           if (const_op != 0
11585               || CC0_P (XEXP (op0, 0))
11586               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11587             break;
11588
11589           /* Get the two operands being compared.  */
11590           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11591             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11592           else
11593             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11594
11595           /* Check for the cases where we simply want the result of the
11596              earlier test or the opposite of that result.  */
11597           if (code == NE || code == EQ
11598               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11599                   && (code == LT || code == GE)))
11600             {
11601               enum rtx_code new_code;
11602               if (code == LT || code == NE)
11603                 new_code = GET_CODE (op0);
11604               else
11605                 new_code = reversed_comparison_code (op0, NULL);
11606
11607               if (new_code != UNKNOWN)
11608                 {
11609                   code = new_code;
11610                   op0 = tem;
11611                   op1 = tem1;
11612                   continue;
11613                 }
11614             }
11615           break;
11616
11617         case IOR:
11618           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11619              iff X <= 0.  */
11620           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11621               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11622               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11623             {
11624               op0 = XEXP (op0, 1);
11625               code = (code == GE ? GT : LE);
11626               continue;
11627             }
11628           break;
11629
11630         case AND:
11631           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11632              will be converted to a ZERO_EXTRACT later.  */
11633           if (const_op == 0 && equality_comparison_p
11634               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11635               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11636             {
11637               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11638                                       XEXP (XEXP (op0, 0), 1));
11639               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11640               continue;
11641             }
11642
11643           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11644              zero and X is a comparison and C1 and C2 describe only bits set
11645              in STORE_FLAG_VALUE, we can compare with X.  */
11646           if (const_op == 0 && equality_comparison_p
11647               && mode_width <= HOST_BITS_PER_WIDE_INT
11648               && CONST_INT_P (XEXP (op0, 1))
11649               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11650               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11651               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11652               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11653             {
11654               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11655                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11656               if ((~STORE_FLAG_VALUE & mask) == 0
11657                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11658                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11659                           && COMPARISON_P (tem))))
11660                 {
11661                   op0 = XEXP (XEXP (op0, 0), 0);
11662                   continue;
11663                 }
11664             }
11665
11666           /* If we are doing an equality comparison of an AND of a bit equal
11667              to the sign bit, replace this with a LT or GE comparison of
11668              the underlying value.  */
11669           if (equality_comparison_p
11670               && const_op == 0
11671               && CONST_INT_P (XEXP (op0, 1))
11672               && mode_width <= HOST_BITS_PER_WIDE_INT
11673               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11674                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11675             {
11676               op0 = XEXP (op0, 0);
11677               code = (code == EQ ? GE : LT);
11678               continue;
11679             }
11680
11681           /* If this AND operation is really a ZERO_EXTEND from a narrower
11682              mode, the constant fits within that mode, and this is either an
11683              equality or unsigned comparison, try to do this comparison in
11684              the narrower mode.
11685
11686              Note that in:
11687
11688              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11689              -> (ne:DI (reg:SI 4) (const_int 0))
11690
11691              unless TRULY_NOOP_TRUNCATION allows it or the register is
11692              known to hold a value of the required mode the
11693              transformation is invalid.  */
11694           if ((equality_comparison_p || unsigned_comparison_p)
11695               && CONST_INT_P (XEXP (op0, 1))
11696               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11697                                    & GET_MODE_MASK (mode))
11698                                   + 1)) >= 0
11699               && const_op >> i == 0
11700               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11701               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11702                   || (REG_P (XEXP (op0, 0))
11703                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11704             {
11705               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11706               continue;
11707             }
11708
11709           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11710              fits in both M1 and M2 and the SUBREG is either paradoxical
11711              or represents the low part, permute the SUBREG and the AND
11712              and try again.  */
11713           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11714             {
11715               unsigned HOST_WIDE_INT c1;
11716               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11717               /* Require an integral mode, to avoid creating something like
11718                  (AND:SF ...).  */
11719               if (SCALAR_INT_MODE_P (tmode)
11720                   /* It is unsafe to commute the AND into the SUBREG if the
11721                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11722                      not defined.  As originally written the upper bits
11723                      have a defined value due to the AND operation.
11724                      However, if we commute the AND inside the SUBREG then
11725                      they no longer have defined values and the meaning of
11726                      the code has been changed.  */
11727                   && (0
11728 #ifdef WORD_REGISTER_OPERATIONS
11729                       || (mode_width > GET_MODE_PRECISION (tmode)
11730                           && mode_width <= BITS_PER_WORD)
11731 #endif
11732                       || (mode_width <= GET_MODE_PRECISION (tmode)
11733                           && subreg_lowpart_p (XEXP (op0, 0))))
11734                   && CONST_INT_P (XEXP (op0, 1))
11735                   && mode_width <= HOST_BITS_PER_WIDE_INT
11736                   && HWI_COMPUTABLE_MODE_P (tmode)
11737                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11738                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11739                   && c1 != mask
11740                   && c1 != GET_MODE_MASK (tmode))
11741                 {
11742                   op0 = simplify_gen_binary (AND, tmode,
11743                                              SUBREG_REG (XEXP (op0, 0)),
11744                                              gen_int_mode (c1, tmode));
11745                   op0 = gen_lowpart (mode, op0);
11746                   continue;
11747                 }
11748             }
11749
11750           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11751           if (const_op == 0 && equality_comparison_p
11752               && XEXP (op0, 1) == const1_rtx
11753               && GET_CODE (XEXP (op0, 0)) == NOT)
11754             {
11755               op0 = simplify_and_const_int (NULL_RTX, mode,
11756                                             XEXP (XEXP (op0, 0), 0), 1);
11757               code = (code == NE ? EQ : NE);
11758               continue;
11759             }
11760
11761           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11762              (eq (and (lshiftrt X) 1) 0).
11763              Also handle the case where (not X) is expressed using xor.  */
11764           if (const_op == 0 && equality_comparison_p
11765               && XEXP (op0, 1) == const1_rtx
11766               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11767             {
11768               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11769               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11770
11771               if (GET_CODE (shift_op) == NOT
11772                   || (GET_CODE (shift_op) == XOR
11773                       && CONST_INT_P (XEXP (shift_op, 1))
11774                       && CONST_INT_P (shift_count)
11775                       && HWI_COMPUTABLE_MODE_P (mode)
11776                       && (UINTVAL (XEXP (shift_op, 1))
11777                           == (unsigned HOST_WIDE_INT) 1
11778                                << INTVAL (shift_count))))
11779                 {
11780                   op0
11781                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11782                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11783                   code = (code == NE ? EQ : NE);
11784                   continue;
11785                 }
11786             }
11787           break;
11788
11789         case ASHIFT:
11790           /* If we have (compare (ashift FOO N) (const_int C)) and
11791              the high order N bits of FOO (N+1 if an inequality comparison)
11792              are known to be zero, we can do this by comparing FOO with C
11793              shifted right N bits so long as the low-order N bits of C are
11794              zero.  */
11795           if (CONST_INT_P (XEXP (op0, 1))
11796               && INTVAL (XEXP (op0, 1)) >= 0
11797               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11798                   < HOST_BITS_PER_WIDE_INT)
11799               && (((unsigned HOST_WIDE_INT) const_op
11800                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11801                       - 1)) == 0)
11802               && mode_width <= HOST_BITS_PER_WIDE_INT
11803               && (nonzero_bits (XEXP (op0, 0), mode)
11804                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11805                                + ! equality_comparison_p))) == 0)
11806             {
11807               /* We must perform a logical shift, not an arithmetic one,
11808                  as we want the top N bits of C to be zero.  */
11809               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11810
11811               temp >>= INTVAL (XEXP (op0, 1));
11812               op1 = gen_int_mode (temp, mode);
11813               op0 = XEXP (op0, 0);
11814               continue;
11815             }
11816
11817           /* If we are doing a sign bit comparison, it means we are testing
11818              a particular bit.  Convert it to the appropriate AND.  */
11819           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11820               && mode_width <= HOST_BITS_PER_WIDE_INT)
11821             {
11822               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11823                                             ((unsigned HOST_WIDE_INT) 1
11824                                              << (mode_width - 1
11825                                                  - INTVAL (XEXP (op0, 1)))));
11826               code = (code == LT ? NE : EQ);
11827               continue;
11828             }
11829
11830           /* If this an equality comparison with zero and we are shifting
11831              the low bit to the sign bit, we can convert this to an AND of the
11832              low-order bit.  */
11833           if (const_op == 0 && equality_comparison_p
11834               && CONST_INT_P (XEXP (op0, 1))
11835               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11836             {
11837               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11838               continue;
11839             }
11840           break;
11841
11842         case ASHIFTRT:
11843           /* If this is an equality comparison with zero, we can do this
11844              as a logical shift, which might be much simpler.  */
11845           if (equality_comparison_p && const_op == 0
11846               && CONST_INT_P (XEXP (op0, 1)))
11847             {
11848               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11849                                           XEXP (op0, 0),
11850                                           INTVAL (XEXP (op0, 1)));
11851               continue;
11852             }
11853
11854           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11855              do the comparison in a narrower mode.  */
11856           if (! unsigned_comparison_p
11857               && CONST_INT_P (XEXP (op0, 1))
11858               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11859               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11860               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11861                                          MODE_INT, 1)) != BLKmode
11862               && (((unsigned HOST_WIDE_INT) const_op
11863                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11864                   <= GET_MODE_MASK (tmode)))
11865             {
11866               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11867               continue;
11868             }
11869
11870           /* Likewise if OP0 is a PLUS of a sign extension with a
11871              constant, which is usually represented with the PLUS
11872              between the shifts.  */
11873           if (! unsigned_comparison_p
11874               && CONST_INT_P (XEXP (op0, 1))
11875               && GET_CODE (XEXP (op0, 0)) == PLUS
11876               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11877               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11878               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11879               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11880                                          MODE_INT, 1)) != BLKmode
11881               && (((unsigned HOST_WIDE_INT) const_op
11882                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11883                   <= GET_MODE_MASK (tmode)))
11884             {
11885               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11886               rtx add_const = XEXP (XEXP (op0, 0), 1);
11887               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11888                                                    add_const, XEXP (op0, 1));
11889
11890               op0 = simplify_gen_binary (PLUS, tmode,
11891                                          gen_lowpart (tmode, inner),
11892                                          new_const);
11893               continue;
11894             }
11895
11896           /* ... fall through ...  */
11897         case LSHIFTRT:
11898           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11899              the low order N bits of FOO are known to be zero, we can do this
11900              by comparing FOO with C shifted left N bits so long as no
11901              overflow occurs.  Even if the low order N bits of FOO aren't known
11902              to be zero, if the comparison is >= or < we can use the same
11903              optimization and for > or <= by setting all the low
11904              order N bits in the comparison constant.  */
11905           if (CONST_INT_P (XEXP (op0, 1))
11906               && INTVAL (XEXP (op0, 1)) > 0
11907               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11908               && mode_width <= HOST_BITS_PER_WIDE_INT
11909               && (((unsigned HOST_WIDE_INT) const_op
11910                    + (GET_CODE (op0) != LSHIFTRT
11911                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11912                          + 1)
11913                       : 0))
11914                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11915             {
11916               unsigned HOST_WIDE_INT low_bits
11917                 = (nonzero_bits (XEXP (op0, 0), mode)
11918                    & (((unsigned HOST_WIDE_INT) 1
11919                        << INTVAL (XEXP (op0, 1))) - 1));
11920               if (low_bits == 0 || !equality_comparison_p)
11921                 {
11922                   /* If the shift was logical, then we must make the condition
11923                      unsigned.  */
11924                   if (GET_CODE (op0) == LSHIFTRT)
11925                     code = unsigned_condition (code);
11926
11927                   const_op <<= INTVAL (XEXP (op0, 1));
11928                   if (low_bits != 0
11929                       && (code == GT || code == GTU
11930                           || code == LE || code == LEU))
11931                     const_op
11932                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11933                   op1 = GEN_INT (const_op);
11934                   op0 = XEXP (op0, 0);
11935                   continue;
11936                 }
11937             }
11938
11939           /* If we are using this shift to extract just the sign bit, we
11940              can replace this with an LT or GE comparison.  */
11941           if (const_op == 0
11942               && (equality_comparison_p || sign_bit_comparison_p)
11943               && CONST_INT_P (XEXP (op0, 1))
11944               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11945             {
11946               op0 = XEXP (op0, 0);
11947               code = (code == NE || code == GT ? LT : GE);
11948               continue;
11949             }
11950           break;
11951
11952         default:
11953           break;
11954         }
11955
11956       break;
11957     }
11958
11959   /* Now make any compound operations involved in this comparison.  Then,
11960      check for an outmost SUBREG on OP0 that is not doing anything or is
11961      paradoxical.  The latter transformation must only be performed when
11962      it is known that the "extra" bits will be the same in op0 and op1 or
11963      that they don't matter.  There are three cases to consider:
11964
11965      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11966      care bits and we can assume they have any convenient value.  So
11967      making the transformation is safe.
11968
11969      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11970      In this case the upper bits of op0 are undefined.  We should not make
11971      the simplification in that case as we do not know the contents of
11972      those bits.
11973
11974      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11975      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11976      also be sure that they are the same as the upper bits of op1.
11977
11978      We can never remove a SUBREG for a non-equality comparison because
11979      the sign bit is in a different place in the underlying object.  */
11980
11981   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11982   op1 = make_compound_operation (op1, SET);
11983
11984   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11985       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11986       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11987       && (code == NE || code == EQ))
11988     {
11989       if (paradoxical_subreg_p (op0))
11990         {
11991           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11992              implemented.  */
11993           if (REG_P (SUBREG_REG (op0)))
11994             {
11995               op0 = SUBREG_REG (op0);
11996               op1 = gen_lowpart (GET_MODE (op0), op1);
11997             }
11998         }
11999       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
12000                 <= HOST_BITS_PER_WIDE_INT)
12001                && (nonzero_bits (SUBREG_REG (op0),
12002                                  GET_MODE (SUBREG_REG (op0)))
12003                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12004         {
12005           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12006
12007           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12008                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12009             op0 = SUBREG_REG (op0), op1 = tem;
12010         }
12011     }
12012
12013   /* We now do the opposite procedure: Some machines don't have compare
12014      insns in all modes.  If OP0's mode is an integer mode smaller than a
12015      word and we can't do a compare in that mode, see if there is a larger
12016      mode for which we can do the compare.  There are a number of cases in
12017      which we can use the wider mode.  */
12018
12019   mode = GET_MODE (op0);
12020   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12021       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12022       && ! have_insn_for (COMPARE, mode))
12023     for (tmode = GET_MODE_WIDER_MODE (mode);
12024          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12025          tmode = GET_MODE_WIDER_MODE (tmode))
12026       if (have_insn_for (COMPARE, tmode))
12027         {
12028           int zero_extended;
12029
12030           /* If this is a test for negative, we can make an explicit
12031              test of the sign bit.  Test this first so we can use
12032              a paradoxical subreg to extend OP0.  */
12033
12034           if (op1 == const0_rtx && (code == LT || code == GE)
12035               && HWI_COMPUTABLE_MODE_P (mode))
12036             {
12037               unsigned HOST_WIDE_INT sign
12038                 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
12039               op0 = simplify_gen_binary (AND, tmode,
12040                                          gen_lowpart (tmode, op0),
12041                                          gen_int_mode (sign, tmode));
12042               code = (code == LT) ? NE : EQ;
12043               break;
12044             }
12045
12046           /* If the only nonzero bits in OP0 and OP1 are those in the
12047              narrower mode and this is an equality or unsigned comparison,
12048              we can use the wider mode.  Similarly for sign-extended
12049              values, in which case it is true for all comparisons.  */
12050           zero_extended = ((code == EQ || code == NE
12051                             || code == GEU || code == GTU
12052                             || code == LEU || code == LTU)
12053                            && (nonzero_bits (op0, tmode)
12054                                & ~GET_MODE_MASK (mode)) == 0
12055                            && ((CONST_INT_P (op1)
12056                                 || (nonzero_bits (op1, tmode)
12057                                     & ~GET_MODE_MASK (mode)) == 0)));
12058
12059           if (zero_extended
12060               || ((num_sign_bit_copies (op0, tmode)
12061                    > (unsigned int) (GET_MODE_PRECISION (tmode)
12062                                      - GET_MODE_PRECISION (mode)))
12063                   && (num_sign_bit_copies (op1, tmode)
12064                       > (unsigned int) (GET_MODE_PRECISION (tmode)
12065                                         - GET_MODE_PRECISION (mode)))))
12066             {
12067               /* If OP0 is an AND and we don't have an AND in MODE either,
12068                  make a new AND in the proper mode.  */
12069               if (GET_CODE (op0) == AND
12070                   && !have_insn_for (AND, mode))
12071                 op0 = simplify_gen_binary (AND, tmode,
12072                                            gen_lowpart (tmode,
12073                                                         XEXP (op0, 0)),
12074                                            gen_lowpart (tmode,
12075                                                         XEXP (op0, 1)));
12076               else
12077                 {
12078                   if (zero_extended)
12079                     {
12080                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12081                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12082                     }
12083                   else
12084                     {
12085                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12086                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12087                     }
12088                   break;
12089                 }
12090             }
12091         }
12092
12093   /* We may have changed the comparison operands.  Re-canonicalize.  */
12094   if (swap_commutative_operands_p (op0, op1))
12095     {
12096       tem = op0, op0 = op1, op1 = tem;
12097       code = swap_condition (code);
12098     }
12099
12100   /* If this machine only supports a subset of valid comparisons, see if we
12101      can convert an unsupported one into a supported one.  */
12102   target_canonicalize_comparison (&code, &op0, &op1, 0);
12103
12104   *pop0 = op0;
12105   *pop1 = op1;
12106
12107   return code;
12108 }
12109 \f
12110 /* Utility function for record_value_for_reg.  Count number of
12111    rtxs in X.  */
12112 static int
12113 count_rtxs (rtx x)
12114 {
12115   enum rtx_code code = GET_CODE (x);
12116   const char *fmt;
12117   int i, j, ret = 1;
12118
12119   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12120       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12121     {
12122       rtx x0 = XEXP (x, 0);
12123       rtx x1 = XEXP (x, 1);
12124
12125       if (x0 == x1)
12126         return 1 + 2 * count_rtxs (x0);
12127
12128       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12129            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12130           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12131         return 2 + 2 * count_rtxs (x0)
12132                + count_rtxs (x == XEXP (x1, 0)
12133                              ? XEXP (x1, 1) : XEXP (x1, 0));
12134
12135       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12136            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12137           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12138         return 2 + 2 * count_rtxs (x1)
12139                + count_rtxs (x == XEXP (x0, 0)
12140                              ? XEXP (x0, 1) : XEXP (x0, 0));
12141     }
12142
12143   fmt = GET_RTX_FORMAT (code);
12144   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12145     if (fmt[i] == 'e')
12146       ret += count_rtxs (XEXP (x, i));
12147     else if (fmt[i] == 'E')
12148       for (j = 0; j < XVECLEN (x, i); j++)
12149         ret += count_rtxs (XVECEXP (x, i, j));
12150
12151   return ret;
12152 }
12153 \f
12154 /* Utility function for following routine.  Called when X is part of a value
12155    being stored into last_set_value.  Sets last_set_table_tick
12156    for each register mentioned.  Similar to mention_regs in cse.c  */
12157
12158 static void
12159 update_table_tick (rtx x)
12160 {
12161   enum rtx_code code = GET_CODE (x);
12162   const char *fmt = GET_RTX_FORMAT (code);
12163   int i, j;
12164
12165   if (code == REG)
12166     {
12167       unsigned int regno = REGNO (x);
12168       unsigned int endregno = END_REGNO (x);
12169       unsigned int r;
12170
12171       for (r = regno; r < endregno; r++)
12172         {
12173           reg_stat_type *rsp = &reg_stat[r];
12174           rsp->last_set_table_tick = label_tick;
12175         }
12176
12177       return;
12178     }
12179
12180   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12181     if (fmt[i] == 'e')
12182       {
12183         /* Check for identical subexpressions.  If x contains
12184            identical subexpression we only have to traverse one of
12185            them.  */
12186         if (i == 0 && ARITHMETIC_P (x))
12187           {
12188             /* Note that at this point x1 has already been
12189                processed.  */
12190             rtx x0 = XEXP (x, 0);
12191             rtx x1 = XEXP (x, 1);
12192
12193             /* If x0 and x1 are identical then there is no need to
12194                process x0.  */
12195             if (x0 == x1)
12196               break;
12197
12198             /* If x0 is identical to a subexpression of x1 then while
12199                processing x1, x0 has already been processed.  Thus we
12200                are done with x.  */
12201             if (ARITHMETIC_P (x1)
12202                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12203               break;
12204
12205             /* If x1 is identical to a subexpression of x0 then we
12206                still have to process the rest of x0.  */
12207             if (ARITHMETIC_P (x0)
12208                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12209               {
12210                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12211                 break;
12212               }
12213           }
12214
12215         update_table_tick (XEXP (x, i));
12216       }
12217     else if (fmt[i] == 'E')
12218       for (j = 0; j < XVECLEN (x, i); j++)
12219         update_table_tick (XVECEXP (x, i, j));
12220 }
12221
12222 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12223    are saying that the register is clobbered and we no longer know its
12224    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12225    only permitted with VALUE also zero and is used to invalidate the
12226    register.  */
12227
12228 static void
12229 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
12230 {
12231   unsigned int regno = REGNO (reg);
12232   unsigned int endregno = END_REGNO (reg);
12233   unsigned int i;
12234   reg_stat_type *rsp;
12235
12236   /* If VALUE contains REG and we have a previous value for REG, substitute
12237      the previous value.  */
12238   if (value && insn && reg_overlap_mentioned_p (reg, value))
12239     {
12240       rtx tem;
12241
12242       /* Set things up so get_last_value is allowed to see anything set up to
12243          our insn.  */
12244       subst_low_luid = DF_INSN_LUID (insn);
12245       tem = get_last_value (reg);
12246
12247       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12248          it isn't going to be useful and will take a lot of time to process,
12249          so just use the CLOBBER.  */
12250
12251       if (tem)
12252         {
12253           if (ARITHMETIC_P (tem)
12254               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12255               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12256             tem = XEXP (tem, 0);
12257           else if (count_occurrences (value, reg, 1) >= 2)
12258             {
12259               /* If there are two or more occurrences of REG in VALUE,
12260                  prevent the value from growing too much.  */
12261               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12262                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12263             }
12264
12265           value = replace_rtx (copy_rtx (value), reg, tem);
12266         }
12267     }
12268
12269   /* For each register modified, show we don't know its value, that
12270      we don't know about its bitwise content, that its value has been
12271      updated, and that we don't know the location of the death of the
12272      register.  */
12273   for (i = regno; i < endregno; i++)
12274     {
12275       rsp = &reg_stat[i];
12276
12277       if (insn)
12278         rsp->last_set = insn;
12279
12280       rsp->last_set_value = 0;
12281       rsp->last_set_mode = VOIDmode;
12282       rsp->last_set_nonzero_bits = 0;
12283       rsp->last_set_sign_bit_copies = 0;
12284       rsp->last_death = 0;
12285       rsp->truncated_to_mode = VOIDmode;
12286     }
12287
12288   /* Mark registers that are being referenced in this value.  */
12289   if (value)
12290     update_table_tick (value);
12291
12292   /* Now update the status of each register being set.
12293      If someone is using this register in this block, set this register
12294      to invalid since we will get confused between the two lives in this
12295      basic block.  This makes using this register always invalid.  In cse, we
12296      scan the table to invalidate all entries using this register, but this
12297      is too much work for us.  */
12298
12299   for (i = regno; i < endregno; i++)
12300     {
12301       rsp = &reg_stat[i];
12302       rsp->last_set_label = label_tick;
12303       if (!insn
12304           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12305         rsp->last_set_invalid = 1;
12306       else
12307         rsp->last_set_invalid = 0;
12308     }
12309
12310   /* The value being assigned might refer to X (like in "x++;").  In that
12311      case, we must replace it with (clobber (const_int 0)) to prevent
12312      infinite loops.  */
12313   rsp = &reg_stat[regno];
12314   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12315     {
12316       value = copy_rtx (value);
12317       if (!get_last_value_validate (&value, insn, label_tick, 1))
12318         value = 0;
12319     }
12320
12321   /* For the main register being modified, update the value, the mode, the
12322      nonzero bits, and the number of sign bit copies.  */
12323
12324   rsp->last_set_value = value;
12325
12326   if (value)
12327     {
12328       machine_mode mode = GET_MODE (reg);
12329       subst_low_luid = DF_INSN_LUID (insn);
12330       rsp->last_set_mode = mode;
12331       if (GET_MODE_CLASS (mode) == MODE_INT
12332           && HWI_COMPUTABLE_MODE_P (mode))
12333         mode = nonzero_bits_mode;
12334       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12335       rsp->last_set_sign_bit_copies
12336         = num_sign_bit_copies (value, GET_MODE (reg));
12337     }
12338 }
12339
12340 /* Called via note_stores from record_dead_and_set_regs to handle one
12341    SET or CLOBBER in an insn.  DATA is the instruction in which the
12342    set is occurring.  */
12343
12344 static void
12345 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12346 {
12347   rtx_insn *record_dead_insn = (rtx_insn *) data;
12348
12349   if (GET_CODE (dest) == SUBREG)
12350     dest = SUBREG_REG (dest);
12351
12352   if (!record_dead_insn)
12353     {
12354       if (REG_P (dest))
12355         record_value_for_reg (dest, NULL, NULL_RTX);
12356       return;
12357     }
12358
12359   if (REG_P (dest))
12360     {
12361       /* If we are setting the whole register, we know its value.  Otherwise
12362          show that we don't know the value.  We can handle SUBREG in
12363          some cases.  */
12364       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12365         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12366       else if (GET_CODE (setter) == SET
12367                && GET_CODE (SET_DEST (setter)) == SUBREG
12368                && SUBREG_REG (SET_DEST (setter)) == dest
12369                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12370                && subreg_lowpart_p (SET_DEST (setter)))
12371         record_value_for_reg (dest, record_dead_insn,
12372                               gen_lowpart (GET_MODE (dest),
12373                                                        SET_SRC (setter)));
12374       else
12375         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12376     }
12377   else if (MEM_P (dest)
12378            /* Ignore pushes, they clobber nothing.  */
12379            && ! push_operand (dest, GET_MODE (dest)))
12380     mem_last_set = DF_INSN_LUID (record_dead_insn);
12381 }
12382
12383 /* Update the records of when each REG was most recently set or killed
12384    for the things done by INSN.  This is the last thing done in processing
12385    INSN in the combiner loop.
12386
12387    We update reg_stat[], in particular fields last_set, last_set_value,
12388    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12389    last_death, and also the similar information mem_last_set (which insn
12390    most recently modified memory) and last_call_luid (which insn was the
12391    most recent subroutine call).  */
12392
12393 static void
12394 record_dead_and_set_regs (rtx_insn *insn)
12395 {
12396   rtx link;
12397   unsigned int i;
12398
12399   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12400     {
12401       if (REG_NOTE_KIND (link) == REG_DEAD
12402           && REG_P (XEXP (link, 0)))
12403         {
12404           unsigned int regno = REGNO (XEXP (link, 0));
12405           unsigned int endregno = END_REGNO (XEXP (link, 0));
12406
12407           for (i = regno; i < endregno; i++)
12408             {
12409               reg_stat_type *rsp;
12410
12411               rsp = &reg_stat[i];
12412               rsp->last_death = insn;
12413             }
12414         }
12415       else if (REG_NOTE_KIND (link) == REG_INC)
12416         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12417     }
12418
12419   if (CALL_P (insn))
12420     {
12421       hard_reg_set_iterator hrsi;
12422       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12423         {
12424           reg_stat_type *rsp;
12425
12426           rsp = &reg_stat[i];
12427           rsp->last_set_invalid = 1;
12428           rsp->last_set = insn;
12429           rsp->last_set_value = 0;
12430           rsp->last_set_mode = VOIDmode;
12431           rsp->last_set_nonzero_bits = 0;
12432           rsp->last_set_sign_bit_copies = 0;
12433           rsp->last_death = 0;
12434           rsp->truncated_to_mode = VOIDmode;
12435         }
12436
12437       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12438
12439       /* We can't combine into a call pattern.  Remember, though, that
12440          the return value register is set at this LUID.  We could
12441          still replace a register with the return value from the
12442          wrong subroutine call!  */
12443       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12444     }
12445   else
12446     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12447 }
12448
12449 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12450    register present in the SUBREG, so for each such SUBREG go back and
12451    adjust nonzero and sign bit information of the registers that are
12452    known to have some zero/sign bits set.
12453
12454    This is needed because when combine blows the SUBREGs away, the
12455    information on zero/sign bits is lost and further combines can be
12456    missed because of that.  */
12457
12458 static void
12459 record_promoted_value (rtx_insn *insn, rtx subreg)
12460 {
12461   struct insn_link *links;
12462   rtx set;
12463   unsigned int regno = REGNO (SUBREG_REG (subreg));
12464   machine_mode mode = GET_MODE (subreg);
12465
12466   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12467     return;
12468
12469   for (links = LOG_LINKS (insn); links;)
12470     {
12471       reg_stat_type *rsp;
12472
12473       insn = links->insn;
12474       set = single_set (insn);
12475
12476       if (! set || !REG_P (SET_DEST (set))
12477           || REGNO (SET_DEST (set)) != regno
12478           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12479         {
12480           links = links->next;
12481           continue;
12482         }
12483
12484       rsp = &reg_stat[regno];
12485       if (rsp->last_set == insn)
12486         {
12487           if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
12488             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12489         }
12490
12491       if (REG_P (SET_SRC (set)))
12492         {
12493           regno = REGNO (SET_SRC (set));
12494           links = LOG_LINKS (insn);
12495         }
12496       else
12497         break;
12498     }
12499 }
12500
12501 /* Check if X, a register, is known to contain a value already
12502    truncated to MODE.  In this case we can use a subreg to refer to
12503    the truncated value even though in the generic case we would need
12504    an explicit truncation.  */
12505
12506 static bool
12507 reg_truncated_to_mode (machine_mode mode, const_rtx x)
12508 {
12509   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12510   machine_mode truncated = rsp->truncated_to_mode;
12511
12512   if (truncated == 0
12513       || rsp->truncation_label < label_tick_ebb_start)
12514     return false;
12515   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12516     return true;
12517   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12518     return true;
12519   return false;
12520 }
12521
12522 /* If X is a hard reg or a subreg record the mode that the register is
12523    accessed in.  For non-TRULY_NOOP_TRUNCATION targets we might be able
12524    to turn a truncate into a subreg using this information.  Return true
12525    if traversing X is complete.  */
12526
12527 static bool
12528 record_truncated_value (rtx x)
12529 {
12530   machine_mode truncated_mode;
12531   reg_stat_type *rsp;
12532
12533   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12534     {
12535       machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12536       truncated_mode = GET_MODE (x);
12537
12538       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12539         return true;
12540
12541       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12542         return true;
12543
12544       x = SUBREG_REG (x);
12545     }
12546   /* ??? For hard-regs we now record everything.  We might be able to
12547      optimize this using last_set_mode.  */
12548   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12549     truncated_mode = GET_MODE (x);
12550   else
12551     return false;
12552
12553   rsp = &reg_stat[REGNO (x)];
12554   if (rsp->truncated_to_mode == 0
12555       || rsp->truncation_label < label_tick_ebb_start
12556       || (GET_MODE_SIZE (truncated_mode)
12557           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12558     {
12559       rsp->truncated_to_mode = truncated_mode;
12560       rsp->truncation_label = label_tick;
12561     }
12562
12563   return true;
12564 }
12565
12566 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12567    the modes they are used in.  This can help truning TRUNCATEs into
12568    SUBREGs.  */
12569
12570 static void
12571 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
12572 {
12573   subrtx_var_iterator::array_type array;
12574   FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
12575     if (record_truncated_value (*iter))
12576       iter.skip_subrtxes ();
12577 }
12578
12579 /* Scan X for promoted SUBREGs.  For each one found,
12580    note what it implies to the registers used in it.  */
12581
12582 static void
12583 check_promoted_subreg (rtx_insn *insn, rtx x)
12584 {
12585   if (GET_CODE (x) == SUBREG
12586       && SUBREG_PROMOTED_VAR_P (x)
12587       && REG_P (SUBREG_REG (x)))
12588     record_promoted_value (insn, x);
12589   else
12590     {
12591       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12592       int i, j;
12593
12594       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12595         switch (format[i])
12596           {
12597           case 'e':
12598             check_promoted_subreg (insn, XEXP (x, i));
12599             break;
12600           case 'V':
12601           case 'E':
12602             if (XVEC (x, i) != 0)
12603               for (j = 0; j < XVECLEN (x, i); j++)
12604                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12605             break;
12606           }
12607     }
12608 }
12609 \f
12610 /* Verify that all the registers and memory references mentioned in *LOC are
12611    still valid.  *LOC was part of a value set in INSN when label_tick was
12612    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12613    the invalid references with (clobber (const_int 0)) and return 1.  This
12614    replacement is useful because we often can get useful information about
12615    the form of a value (e.g., if it was produced by a shift that always
12616    produces -1 or 0) even though we don't know exactly what registers it
12617    was produced from.  */
12618
12619 static int
12620 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace)
12621 {
12622   rtx x = *loc;
12623   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12624   int len = GET_RTX_LENGTH (GET_CODE (x));
12625   int i, j;
12626
12627   if (REG_P (x))
12628     {
12629       unsigned int regno = REGNO (x);
12630       unsigned int endregno = END_REGNO (x);
12631       unsigned int j;
12632
12633       for (j = regno; j < endregno; j++)
12634         {
12635           reg_stat_type *rsp = &reg_stat[j];
12636           if (rsp->last_set_invalid
12637               /* If this is a pseudo-register that was only set once and not
12638                  live at the beginning of the function, it is always valid.  */
12639               || (! (regno >= FIRST_PSEUDO_REGISTER
12640                      && REG_N_SETS (regno) == 1
12641                      && (!REGNO_REG_SET_P
12642                          (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
12643                           regno)))
12644                   && rsp->last_set_label > tick))
12645           {
12646             if (replace)
12647               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12648             return replace;
12649           }
12650         }
12651
12652       return 1;
12653     }
12654   /* If this is a memory reference, make sure that there were no stores after
12655      it that might have clobbered the value.  We don't have alias info, so we
12656      assume any store invalidates it.  Moreover, we only have local UIDs, so
12657      we also assume that there were stores in the intervening basic blocks.  */
12658   else if (MEM_P (x) && !MEM_READONLY_P (x)
12659            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12660     {
12661       if (replace)
12662         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12663       return replace;
12664     }
12665
12666   for (i = 0; i < len; i++)
12667     {
12668       if (fmt[i] == 'e')
12669         {
12670           /* Check for identical subexpressions.  If x contains
12671              identical subexpression we only have to traverse one of
12672              them.  */
12673           if (i == 1 && ARITHMETIC_P (x))
12674             {
12675               /* Note that at this point x0 has already been checked
12676                  and found valid.  */
12677               rtx x0 = XEXP (x, 0);
12678               rtx x1 = XEXP (x, 1);
12679
12680               /* If x0 and x1 are identical then x is also valid.  */
12681               if (x0 == x1)
12682                 return 1;
12683
12684               /* If x1 is identical to a subexpression of x0 then
12685                  while checking x0, x1 has already been checked.  Thus
12686                  it is valid and so as x.  */
12687               if (ARITHMETIC_P (x0)
12688                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12689                 return 1;
12690
12691               /* If x0 is identical to a subexpression of x1 then x is
12692                  valid iff the rest of x1 is valid.  */
12693               if (ARITHMETIC_P (x1)
12694                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12695                 return
12696                   get_last_value_validate (&XEXP (x1,
12697                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12698                                            insn, tick, replace);
12699             }
12700
12701           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12702                                        replace) == 0)
12703             return 0;
12704         }
12705       else if (fmt[i] == 'E')
12706         for (j = 0; j < XVECLEN (x, i); j++)
12707           if (get_last_value_validate (&XVECEXP (x, i, j),
12708                                        insn, tick, replace) == 0)
12709             return 0;
12710     }
12711
12712   /* If we haven't found a reason for it to be invalid, it is valid.  */
12713   return 1;
12714 }
12715
12716 /* Get the last value assigned to X, if known.  Some registers
12717    in the value may be replaced with (clobber (const_int 0)) if their value
12718    is known longer known reliably.  */
12719
12720 static rtx
12721 get_last_value (const_rtx x)
12722 {
12723   unsigned int regno;
12724   rtx value;
12725   reg_stat_type *rsp;
12726
12727   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12728      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12729      we cannot predict what values the "extra" bits might have.  */
12730   if (GET_CODE (x) == SUBREG
12731       && subreg_lowpart_p (x)
12732       && !paradoxical_subreg_p (x)
12733       && (value = get_last_value (SUBREG_REG (x))) != 0)
12734     return gen_lowpart (GET_MODE (x), value);
12735
12736   if (!REG_P (x))
12737     return 0;
12738
12739   regno = REGNO (x);
12740   rsp = &reg_stat[regno];
12741   value = rsp->last_set_value;
12742
12743   /* If we don't have a value, or if it isn't for this basic block and
12744      it's either a hard register, set more than once, or it's a live
12745      at the beginning of the function, return 0.
12746
12747      Because if it's not live at the beginning of the function then the reg
12748      is always set before being used (is never used without being set).
12749      And, if it's set only once, and it's always set before use, then all
12750      uses must have the same last value, even if it's not from this basic
12751      block.  */
12752
12753   if (value == 0
12754       || (rsp->last_set_label < label_tick_ebb_start
12755           && (regno < FIRST_PSEUDO_REGISTER
12756               || REG_N_SETS (regno) != 1
12757               || REGNO_REG_SET_P
12758                  (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
12759     return 0;
12760
12761   /* If the value was set in a later insn than the ones we are processing,
12762      we can't use it even if the register was only set once.  */
12763   if (rsp->last_set_label == label_tick
12764       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12765     return 0;
12766
12767   /* If the value has all its registers valid, return it.  */
12768   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12769     return value;
12770
12771   /* Otherwise, make a copy and replace any invalid register with
12772      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12773
12774   value = copy_rtx (value);
12775   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12776     return value;
12777
12778   return 0;
12779 }
12780 \f
12781 /* Return nonzero if expression X refers to a REG or to memory
12782    that is set in an instruction more recent than FROM_LUID.  */
12783
12784 static int
12785 use_crosses_set_p (const_rtx x, int from_luid)
12786 {
12787   const char *fmt;
12788   int i;
12789   enum rtx_code code = GET_CODE (x);
12790
12791   if (code == REG)
12792     {
12793       unsigned int regno = REGNO (x);
12794       unsigned endreg = END_REGNO (x);
12795
12796 #ifdef PUSH_ROUNDING
12797       /* Don't allow uses of the stack pointer to be moved,
12798          because we don't know whether the move crosses a push insn.  */
12799       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12800         return 1;
12801 #endif
12802       for (; regno < endreg; regno++)
12803         {
12804           reg_stat_type *rsp = &reg_stat[regno];
12805           if (rsp->last_set
12806               && rsp->last_set_label == label_tick
12807               && DF_INSN_LUID (rsp->last_set) > from_luid)
12808             return 1;
12809         }
12810       return 0;
12811     }
12812
12813   if (code == MEM && mem_last_set > from_luid)
12814     return 1;
12815
12816   fmt = GET_RTX_FORMAT (code);
12817
12818   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12819     {
12820       if (fmt[i] == 'E')
12821         {
12822           int j;
12823           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12824             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12825               return 1;
12826         }
12827       else if (fmt[i] == 'e'
12828                && use_crosses_set_p (XEXP (x, i), from_luid))
12829         return 1;
12830     }
12831   return 0;
12832 }
12833 \f
12834 /* Define three variables used for communication between the following
12835    routines.  */
12836
12837 static unsigned int reg_dead_regno, reg_dead_endregno;
12838 static int reg_dead_flag;
12839
12840 /* Function called via note_stores from reg_dead_at_p.
12841
12842    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12843    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12844
12845 static void
12846 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12847 {
12848   unsigned int regno, endregno;
12849
12850   if (!REG_P (dest))
12851     return;
12852
12853   regno = REGNO (dest);
12854   endregno = END_REGNO (dest);
12855   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12856     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12857 }
12858
12859 /* Return nonzero if REG is known to be dead at INSN.
12860
12861    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12862    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12863    live.  Otherwise, see if it is live or dead at the start of the basic
12864    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12865    must be assumed to be always live.  */
12866
12867 static int
12868 reg_dead_at_p (rtx reg, rtx_insn *insn)
12869 {
12870   basic_block block;
12871   unsigned int i;
12872
12873   /* Set variables for reg_dead_at_p_1.  */
12874   reg_dead_regno = REGNO (reg);
12875   reg_dead_endregno = END_REGNO (reg);
12876
12877   reg_dead_flag = 0;
12878
12879   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12880      we allow the machine description to decide whether use-and-clobber
12881      patterns are OK.  */
12882   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12883     {
12884       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12885         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12886           return 0;
12887     }
12888
12889   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12890      beginning of basic block.  */
12891   block = BLOCK_FOR_INSN (insn);
12892   for (;;)
12893     {
12894       if (INSN_P (insn))
12895         {
12896           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12897           if (reg_dead_flag)
12898             return reg_dead_flag == 1 ? 1 : 0;
12899
12900           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12901             return 1;
12902         }
12903
12904       if (insn == BB_HEAD (block))
12905         break;
12906
12907       insn = PREV_INSN (insn);
12908     }
12909
12910   /* Look at live-in sets for the basic block that we were in.  */
12911   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12912     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12913       return 0;
12914
12915   return 1;
12916 }
12917 \f
12918 /* Note hard registers in X that are used.  */
12919
12920 static void
12921 mark_used_regs_combine (rtx x)
12922 {
12923   RTX_CODE code = GET_CODE (x);
12924   unsigned int regno;
12925   int i;
12926
12927   switch (code)
12928     {
12929     case LABEL_REF:
12930     case SYMBOL_REF:
12931     case CONST:
12932     CASE_CONST_ANY:
12933     case PC:
12934     case ADDR_VEC:
12935     case ADDR_DIFF_VEC:
12936     case ASM_INPUT:
12937 #ifdef HAVE_cc0
12938     /* CC0 must die in the insn after it is set, so we don't need to take
12939        special note of it here.  */
12940     case CC0:
12941 #endif
12942       return;
12943
12944     case CLOBBER:
12945       /* If we are clobbering a MEM, mark any hard registers inside the
12946          address as used.  */
12947       if (MEM_P (XEXP (x, 0)))
12948         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12949       return;
12950
12951     case REG:
12952       regno = REGNO (x);
12953       /* A hard reg in a wide mode may really be multiple registers.
12954          If so, mark all of them just like the first.  */
12955       if (regno < FIRST_PSEUDO_REGISTER)
12956         {
12957           /* None of this applies to the stack, frame or arg pointers.  */
12958           if (regno == STACK_POINTER_REGNUM
12959 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12960               || regno == HARD_FRAME_POINTER_REGNUM
12961 #endif
12962 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12963               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12964 #endif
12965               || regno == FRAME_POINTER_REGNUM)
12966             return;
12967
12968           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12969         }
12970       return;
12971
12972     case SET:
12973       {
12974         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12975            the address.  */
12976         rtx testreg = SET_DEST (x);
12977
12978         while (GET_CODE (testreg) == SUBREG
12979                || GET_CODE (testreg) == ZERO_EXTRACT
12980                || GET_CODE (testreg) == STRICT_LOW_PART)
12981           testreg = XEXP (testreg, 0);
12982
12983         if (MEM_P (testreg))
12984           mark_used_regs_combine (XEXP (testreg, 0));
12985
12986         mark_used_regs_combine (SET_SRC (x));
12987       }
12988       return;
12989
12990     default:
12991       break;
12992     }
12993
12994   /* Recursively scan the operands of this expression.  */
12995
12996   {
12997     const char *fmt = GET_RTX_FORMAT (code);
12998
12999     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13000       {
13001         if (fmt[i] == 'e')
13002           mark_used_regs_combine (XEXP (x, i));
13003         else if (fmt[i] == 'E')
13004           {
13005             int j;
13006
13007             for (j = 0; j < XVECLEN (x, i); j++)
13008               mark_used_regs_combine (XVECEXP (x, i, j));
13009           }
13010       }
13011   }
13012 }
13013 \f
13014 /* Remove register number REGNO from the dead registers list of INSN.
13015
13016    Return the note used to record the death, if there was one.  */
13017
13018 rtx
13019 remove_death (unsigned int regno, rtx_insn *insn)
13020 {
13021   rtx note = find_regno_note (insn, REG_DEAD, regno);
13022
13023   if (note)
13024     remove_note (insn, note);
13025
13026   return note;
13027 }
13028
13029 /* For each register (hardware or pseudo) used within expression X, if its
13030    death is in an instruction with luid between FROM_LUID (inclusive) and
13031    TO_INSN (exclusive), put a REG_DEAD note for that register in the
13032    list headed by PNOTES.
13033
13034    That said, don't move registers killed by maybe_kill_insn.
13035
13036    This is done when X is being merged by combination into TO_INSN.  These
13037    notes will then be distributed as needed.  */
13038
13039 static void
13040 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
13041              rtx *pnotes)
13042 {
13043   const char *fmt;
13044   int len, i;
13045   enum rtx_code code = GET_CODE (x);
13046
13047   if (code == REG)
13048     {
13049       unsigned int regno = REGNO (x);
13050       rtx_insn *where_dead = reg_stat[regno].last_death;
13051
13052       /* Don't move the register if it gets killed in between from and to.  */
13053       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13054           && ! reg_referenced_p (x, maybe_kill_insn))
13055         return;
13056
13057       if (where_dead
13058           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13059           && DF_INSN_LUID (where_dead) >= from_luid
13060           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13061         {
13062           rtx note = remove_death (regno, where_dead);
13063
13064           /* It is possible for the call above to return 0.  This can occur
13065              when last_death points to I2 or I1 that we combined with.
13066              In that case make a new note.
13067
13068              We must also check for the case where X is a hard register
13069              and NOTE is a death note for a range of hard registers
13070              including X.  In that case, we must put REG_DEAD notes for
13071              the remaining registers in place of NOTE.  */
13072
13073           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13074               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13075                   > GET_MODE_SIZE (GET_MODE (x))))
13076             {
13077               unsigned int deadregno = REGNO (XEXP (note, 0));
13078               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13079               unsigned int ourend = END_HARD_REGNO (x);
13080               unsigned int i;
13081
13082               for (i = deadregno; i < deadend; i++)
13083                 if (i < regno || i >= ourend)
13084                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13085             }
13086
13087           /* If we didn't find any note, or if we found a REG_DEAD note that
13088              covers only part of the given reg, and we have a multi-reg hard
13089              register, then to be safe we must check for REG_DEAD notes
13090              for each register other than the first.  They could have
13091              their own REG_DEAD notes lying around.  */
13092           else if ((note == 0
13093                     || (note != 0
13094                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13095                             < GET_MODE_SIZE (GET_MODE (x)))))
13096                    && regno < FIRST_PSEUDO_REGISTER
13097                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13098             {
13099               unsigned int ourend = END_HARD_REGNO (x);
13100               unsigned int i, offset;
13101               rtx oldnotes = 0;
13102
13103               if (note)
13104                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13105               else
13106                 offset = 1;
13107
13108               for (i = regno + offset; i < ourend; i++)
13109                 move_deaths (regno_reg_rtx[i],
13110                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13111             }
13112
13113           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13114             {
13115               XEXP (note, 1) = *pnotes;
13116               *pnotes = note;
13117             }
13118           else
13119             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13120         }
13121
13122       return;
13123     }
13124
13125   else if (GET_CODE (x) == SET)
13126     {
13127       rtx dest = SET_DEST (x);
13128
13129       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13130
13131       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13132          that accesses one word of a multi-word item, some
13133          piece of everything register in the expression is used by
13134          this insn, so remove any old death.  */
13135       /* ??? So why do we test for equality of the sizes?  */
13136
13137       if (GET_CODE (dest) == ZERO_EXTRACT
13138           || GET_CODE (dest) == STRICT_LOW_PART
13139           || (GET_CODE (dest) == SUBREG
13140               && (((GET_MODE_SIZE (GET_MODE (dest))
13141                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13142                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13143                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13144         {
13145           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13146           return;
13147         }
13148
13149       /* If this is some other SUBREG, we know it replaces the entire
13150          value, so use that as the destination.  */
13151       if (GET_CODE (dest) == SUBREG)
13152         dest = SUBREG_REG (dest);
13153
13154       /* If this is a MEM, adjust deaths of anything used in the address.
13155          For a REG (the only other possibility), the entire value is
13156          being replaced so the old value is not used in this insn.  */
13157
13158       if (MEM_P (dest))
13159         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13160                      to_insn, pnotes);
13161       return;
13162     }
13163
13164   else if (GET_CODE (x) == CLOBBER)
13165     return;
13166
13167   len = GET_RTX_LENGTH (code);
13168   fmt = GET_RTX_FORMAT (code);
13169
13170   for (i = 0; i < len; i++)
13171     {
13172       if (fmt[i] == 'E')
13173         {
13174           int j;
13175           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13176             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13177                          to_insn, pnotes);
13178         }
13179       else if (fmt[i] == 'e')
13180         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13181     }
13182 }
13183 \f
13184 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13185    pattern of an insn.  X must be a REG.  */
13186
13187 static int
13188 reg_bitfield_target_p (rtx x, rtx body)
13189 {
13190   int i;
13191
13192   if (GET_CODE (body) == SET)
13193     {
13194       rtx dest = SET_DEST (body);
13195       rtx target;
13196       unsigned int regno, tregno, endregno, endtregno;
13197
13198       if (GET_CODE (dest) == ZERO_EXTRACT)
13199         target = XEXP (dest, 0);
13200       else if (GET_CODE (dest) == STRICT_LOW_PART)
13201         target = SUBREG_REG (XEXP (dest, 0));
13202       else
13203         return 0;
13204
13205       if (GET_CODE (target) == SUBREG)
13206         target = SUBREG_REG (target);
13207
13208       if (!REG_P (target))
13209         return 0;
13210
13211       tregno = REGNO (target), regno = REGNO (x);
13212       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13213         return target == x;
13214
13215       endtregno = end_hard_regno (GET_MODE (target), tregno);
13216       endregno = end_hard_regno (GET_MODE (x), regno);
13217
13218       return endregno > tregno && regno < endtregno;
13219     }
13220
13221   else if (GET_CODE (body) == PARALLEL)
13222     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13223       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13224         return 1;
13225
13226   return 0;
13227 }
13228 \f
13229 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13230    as appropriate.  I3 and I2 are the insns resulting from the combination
13231    insns including FROM (I2 may be zero).
13232
13233    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13234    not need REG_DEAD notes because they are being substituted for.  This
13235    saves searching in the most common cases.
13236
13237    Each note in the list is either ignored or placed on some insns, depending
13238    on the type of note.  */
13239
13240 static void
13241 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
13242                   rtx elim_i2, rtx elim_i1, rtx elim_i0)
13243 {
13244   rtx note, next_note;
13245   rtx tem_note;
13246   rtx_insn *tem_insn;
13247
13248   for (note = notes; note; note = next_note)
13249     {
13250       rtx_insn *place = 0, *place2 = 0;
13251
13252       next_note = XEXP (note, 1);
13253       switch (REG_NOTE_KIND (note))
13254         {
13255         case REG_BR_PROB:
13256         case REG_BR_PRED:
13257           /* Doesn't matter much where we put this, as long as it's somewhere.
13258              It is preferable to keep these notes on branches, which is most
13259              likely to be i3.  */
13260           place = i3;
13261           break;
13262
13263         case REG_NON_LOCAL_GOTO:
13264           if (JUMP_P (i3))
13265             place = i3;
13266           else
13267             {
13268               gcc_assert (i2 && JUMP_P (i2));
13269               place = i2;
13270             }
13271           break;
13272
13273         case REG_EH_REGION:
13274           /* These notes must remain with the call or trapping instruction.  */
13275           if (CALL_P (i3))
13276             place = i3;
13277           else if (i2 && CALL_P (i2))
13278             place = i2;
13279           else
13280             {
13281               gcc_assert (cfun->can_throw_non_call_exceptions);
13282               if (may_trap_p (i3))
13283                 place = i3;
13284               else if (i2 && may_trap_p (i2))
13285                 place = i2;
13286               /* ??? Otherwise assume we've combined things such that we
13287                  can now prove that the instructions can't trap.  Drop the
13288                  note in this case.  */
13289             }
13290           break;
13291
13292         case REG_ARGS_SIZE:
13293           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13294              entire adjustment.  Assert i3 contains at least some adjust.  */
13295           if (!noop_move_p (i3))
13296             {
13297               int old_size, args_size = INTVAL (XEXP (note, 0));
13298               /* fixup_args_size_notes looks at REG_NORETURN note,
13299                  so ensure the note is placed there first.  */
13300               if (CALL_P (i3))
13301                 {
13302                   rtx *np;
13303                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13304                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13305                       {
13306                         rtx n = *np;
13307                         *np = XEXP (n, 1);
13308                         XEXP (n, 1) = REG_NOTES (i3);
13309                         REG_NOTES (i3) = n;
13310                         break;
13311                       }
13312                 }
13313               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13314               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13315                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13316               gcc_assert (old_size != args_size
13317                           || (CALL_P (i3)
13318                               && !ACCUMULATE_OUTGOING_ARGS
13319                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13320             }
13321           break;
13322
13323         case REG_NORETURN:
13324         case REG_SETJMP:
13325         case REG_TM:
13326         case REG_CALL_DECL:
13327           /* These notes must remain with the call.  It should not be
13328              possible for both I2 and I3 to be a call.  */
13329           if (CALL_P (i3))
13330             place = i3;
13331           else
13332             {
13333               gcc_assert (i2 && CALL_P (i2));
13334               place = i2;
13335             }
13336           break;
13337
13338         case REG_UNUSED:
13339           /* Any clobbers for i3 may still exist, and so we must process
13340              REG_UNUSED notes from that insn.
13341
13342              Any clobbers from i2 or i1 can only exist if they were added by
13343              recog_for_combine.  In that case, recog_for_combine created the
13344              necessary REG_UNUSED notes.  Trying to keep any original
13345              REG_UNUSED notes from these insns can cause incorrect output
13346              if it is for the same register as the original i3 dest.
13347              In that case, we will notice that the register is set in i3,
13348              and then add a REG_UNUSED note for the destination of i3, which
13349              is wrong.  However, it is possible to have REG_UNUSED notes from
13350              i2 or i1 for register which were both used and clobbered, so
13351              we keep notes from i2 or i1 if they will turn into REG_DEAD
13352              notes.  */
13353
13354           /* If this register is set or clobbered in I3, put the note there
13355              unless there is one already.  */
13356           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13357             {
13358               if (from_insn != i3)
13359                 break;
13360
13361               if (! (REG_P (XEXP (note, 0))
13362                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13363                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13364                 place = i3;
13365             }
13366           /* Otherwise, if this register is used by I3, then this register
13367              now dies here, so we must put a REG_DEAD note here unless there
13368              is one already.  */
13369           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13370                    && ! (REG_P (XEXP (note, 0))
13371                          ? find_regno_note (i3, REG_DEAD,
13372                                             REGNO (XEXP (note, 0)))
13373                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13374             {
13375               PUT_REG_NOTE_KIND (note, REG_DEAD);
13376               place = i3;
13377             }
13378           break;
13379
13380         case REG_EQUAL:
13381         case REG_EQUIV:
13382         case REG_NOALIAS:
13383           /* These notes say something about results of an insn.  We can
13384              only support them if they used to be on I3 in which case they
13385              remain on I3.  Otherwise they are ignored.
13386
13387              If the note refers to an expression that is not a constant, we
13388              must also ignore the note since we cannot tell whether the
13389              equivalence is still true.  It might be possible to do
13390              slightly better than this (we only have a problem if I2DEST
13391              or I1DEST is present in the expression), but it doesn't
13392              seem worth the trouble.  */
13393
13394           if (from_insn == i3
13395               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13396             place = i3;
13397           break;
13398
13399         case REG_INC:
13400           /* These notes say something about how a register is used.  They must
13401              be present on any use of the register in I2 or I3.  */
13402           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13403             place = i3;
13404
13405           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13406             {
13407               if (place)
13408                 place2 = i2;
13409               else
13410                 place = i2;
13411             }
13412           break;
13413
13414         case REG_LABEL_TARGET:
13415         case REG_LABEL_OPERAND:
13416           /* This can show up in several ways -- either directly in the
13417              pattern, or hidden off in the constant pool with (or without?)
13418              a REG_EQUAL note.  */
13419           /* ??? Ignore the without-reg_equal-note problem for now.  */
13420           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13421               || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13422                   && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
13423                   && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0)))
13424             place = i3;
13425
13426           if (i2
13427               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13428                   || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13429                       && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
13430                       && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0))))
13431             {
13432               if (place)
13433                 place2 = i2;
13434               else
13435                 place = i2;
13436             }
13437
13438           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13439              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13440              there.  */
13441           if (place && JUMP_P (place)
13442               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13443               && (JUMP_LABEL (place) == NULL
13444                   || JUMP_LABEL (place) == XEXP (note, 0)))
13445             {
13446               rtx label = JUMP_LABEL (place);
13447
13448               if (!label)
13449                 JUMP_LABEL (place) = XEXP (note, 0);
13450               else if (LABEL_P (label))
13451                 LABEL_NUSES (label)--;
13452             }
13453
13454           if (place2 && JUMP_P (place2)
13455               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13456               && (JUMP_LABEL (place2) == NULL
13457                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13458             {
13459               rtx label = JUMP_LABEL (place2);
13460
13461               if (!label)
13462                 JUMP_LABEL (place2) = XEXP (note, 0);
13463               else if (LABEL_P (label))
13464                 LABEL_NUSES (label)--;
13465               place2 = 0;
13466             }
13467           break;
13468
13469         case REG_NONNEG:
13470           /* This note says something about the value of a register prior
13471              to the execution of an insn.  It is too much trouble to see
13472              if the note is still correct in all situations.  It is better
13473              to simply delete it.  */
13474           break;
13475
13476         case REG_DEAD:
13477           /* If we replaced the right hand side of FROM_INSN with a
13478              REG_EQUAL note, the original use of the dying register
13479              will not have been combined into I3 and I2.  In such cases,
13480              FROM_INSN is guaranteed to be the first of the combined
13481              instructions, so we simply need to search back before
13482              FROM_INSN for the previous use or set of this register,
13483              then alter the notes there appropriately.
13484
13485              If the register is used as an input in I3, it dies there.
13486              Similarly for I2, if it is nonzero and adjacent to I3.
13487
13488              If the register is not used as an input in either I3 or I2
13489              and it is not one of the registers we were supposed to eliminate,
13490              there are two possibilities.  We might have a non-adjacent I2
13491              or we might have somehow eliminated an additional register
13492              from a computation.  For example, we might have had A & B where
13493              we discover that B will always be zero.  In this case we will
13494              eliminate the reference to A.
13495
13496              In both cases, we must search to see if we can find a previous
13497              use of A and put the death note there.  */
13498
13499           if (from_insn
13500               && from_insn == i2mod
13501               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13502             tem_insn = from_insn;
13503           else
13504             {
13505               if (from_insn
13506                   && CALL_P (from_insn)
13507                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13508                 place = from_insn;
13509               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13510                 place = i3;
13511               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13512                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13513                 place = i2;
13514               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13515                         && !(i2mod
13516                              && reg_overlap_mentioned_p (XEXP (note, 0),
13517                                                          i2mod_old_rhs)))
13518                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13519                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13520                 break;
13521               tem_insn = i3;
13522             }
13523
13524           if (place == 0)
13525             {
13526               basic_block bb = this_basic_block;
13527
13528               for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
13529                 {
13530                   if (!NONDEBUG_INSN_P (tem_insn))
13531                     {
13532                       if (tem_insn == BB_HEAD (bb))
13533                         break;
13534                       continue;
13535                     }
13536
13537                   /* If the register is being set at TEM_INSN, see if that is all
13538                      TEM_INSN is doing.  If so, delete TEM_INSN.  Otherwise, make this
13539                      into a REG_UNUSED note instead. Don't delete sets to
13540                      global register vars.  */
13541                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13542                        || !global_regs[REGNO (XEXP (note, 0))])
13543                       && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
13544                     {
13545                       rtx set = single_set (tem_insn);
13546                       rtx inner_dest = 0;
13547 #ifdef HAVE_cc0
13548                       rtx_insn *cc0_setter = NULL;
13549 #endif
13550
13551                       if (set != 0)
13552                         for (inner_dest = SET_DEST (set);
13553                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13554                               || GET_CODE (inner_dest) == SUBREG
13555                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13556                              inner_dest = XEXP (inner_dest, 0))
13557                           ;
13558
13559                       /* Verify that it was the set, and not a clobber that
13560                          modified the register.
13561
13562                          CC0 targets must be careful to maintain setter/user
13563                          pairs.  If we cannot delete the setter due to side
13564                          effects, mark the user with an UNUSED note instead
13565                          of deleting it.  */
13566
13567                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13568                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13569 #ifdef HAVE_cc0
13570                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13571                               || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
13572                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13573 #endif
13574                           )
13575                         {
13576                           /* Move the notes and links of TEM_INSN elsewhere.
13577                              This might delete other dead insns recursively.
13578                              First set the pattern to something that won't use
13579                              any register.  */
13580                           rtx old_notes = REG_NOTES (tem_insn);
13581
13582                           PATTERN (tem_insn) = pc_rtx;
13583                           REG_NOTES (tem_insn) = NULL;
13584
13585                           distribute_notes (old_notes, tem_insn, tem_insn, NULL,
13586                                             NULL_RTX, NULL_RTX, NULL_RTX);
13587                           distribute_links (LOG_LINKS (tem_insn));
13588
13589                           SET_INSN_DELETED (tem_insn);
13590                           if (tem_insn == i2)
13591                             i2 = NULL;
13592
13593 #ifdef HAVE_cc0
13594                           /* Delete the setter too.  */
13595                           if (cc0_setter)
13596                             {
13597                               PATTERN (cc0_setter) = pc_rtx;
13598                               old_notes = REG_NOTES (cc0_setter);
13599                               REG_NOTES (cc0_setter) = NULL;
13600
13601                               distribute_notes (old_notes, cc0_setter,
13602                                                 cc0_setter, NULL,
13603                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13604                               distribute_links (LOG_LINKS (cc0_setter));
13605
13606                               SET_INSN_DELETED (cc0_setter);
13607                               if (cc0_setter == i2)
13608                                 i2 = NULL;
13609                             }
13610 #endif
13611                         }
13612                       else
13613                         {
13614                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13615
13616                           /*  If there isn't already a REG_UNUSED note, put one
13617                               here.  Do not place a REG_DEAD note, even if
13618                               the register is also used here; that would not
13619                               match the algorithm used in lifetime analysis
13620                               and can cause the consistency check in the
13621                               scheduler to fail.  */
13622                           if (! find_regno_note (tem_insn, REG_UNUSED,
13623                                                  REGNO (XEXP (note, 0))))
13624                             place = tem_insn;
13625                           break;
13626                         }
13627                     }
13628                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
13629                            || (CALL_P (tem_insn)
13630                                && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
13631                     {
13632                       place = tem_insn;
13633
13634                       /* If we are doing a 3->2 combination, and we have a
13635                          register which formerly died in i3 and was not used
13636                          by i2, which now no longer dies in i3 and is used in
13637                          i2 but does not die in i2, and place is between i2
13638                          and i3, then we may need to move a link from place to
13639                          i2.  */
13640                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13641                           && from_insn
13642                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13643                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13644                         {
13645                           struct insn_link *links = LOG_LINKS (place);
13646                           LOG_LINKS (place) = NULL;
13647                           distribute_links (links);
13648                         }
13649                       break;
13650                     }
13651
13652                   if (tem_insn == BB_HEAD (bb))
13653                     break;
13654                 }
13655
13656             }
13657
13658           /* If the register is set or already dead at PLACE, we needn't do
13659              anything with this note if it is still a REG_DEAD note.
13660              We check here if it is set at all, not if is it totally replaced,
13661              which is what `dead_or_set_p' checks, so also check for it being
13662              set partially.  */
13663
13664           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13665             {
13666               unsigned int regno = REGNO (XEXP (note, 0));
13667               reg_stat_type *rsp = &reg_stat[regno];
13668
13669               if (dead_or_set_p (place, XEXP (note, 0))
13670                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13671                 {
13672                   /* Unless the register previously died in PLACE, clear
13673                      last_death.  [I no longer understand why this is
13674                      being done.] */
13675                   if (rsp->last_death != place)
13676                     rsp->last_death = 0;
13677                   place = 0;
13678                 }
13679               else
13680                 rsp->last_death = place;
13681
13682               /* If this is a death note for a hard reg that is occupying
13683                  multiple registers, ensure that we are still using all
13684                  parts of the object.  If we find a piece of the object
13685                  that is unused, we must arrange for an appropriate REG_DEAD
13686                  note to be added for it.  However, we can't just emit a USE
13687                  and tag the note to it, since the register might actually
13688                  be dead; so we recourse, and the recursive call then finds
13689                  the previous insn that used this register.  */
13690
13691               if (place && regno < FIRST_PSEUDO_REGISTER
13692                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13693                 {
13694                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13695                   bool all_used = true;
13696                   unsigned int i;
13697
13698                   for (i = regno; i < endregno; i++)
13699                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13700                          && ! find_regno_fusage (place, USE, i))
13701                         || dead_or_set_regno_p (place, i))
13702                       {
13703                         all_used = false;
13704                         break;
13705                       }
13706
13707                   if (! all_used)
13708                     {
13709                       /* Put only REG_DEAD notes for pieces that are
13710                          not already dead or set.  */
13711
13712                       for (i = regno; i < endregno;
13713                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13714                         {
13715                           rtx piece = regno_reg_rtx[i];
13716                           basic_block bb = this_basic_block;
13717
13718                           if (! dead_or_set_p (place, piece)
13719                               && ! reg_bitfield_target_p (piece,
13720                                                           PATTERN (place)))
13721                             {
13722                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13723                                                              NULL_RTX);
13724
13725                               distribute_notes (new_note, place, place,
13726                                                 NULL, NULL_RTX, NULL_RTX,
13727                                                 NULL_RTX);
13728                             }
13729                           else if (! refers_to_regno_p (i, i + 1,
13730                                                         PATTERN (place), 0)
13731                                    && ! find_regno_fusage (place, USE, i))
13732                             for (tem_insn = PREV_INSN (place); ;
13733                                  tem_insn = PREV_INSN (tem_insn))
13734                               {
13735                                 if (!NONDEBUG_INSN_P (tem_insn))
13736                                   {
13737                                     if (tem_insn == BB_HEAD (bb))
13738                                       break;
13739                                     continue;
13740                                   }
13741                                 if (dead_or_set_p (tem_insn, piece)
13742                                     || reg_bitfield_target_p (piece,
13743                                                               PATTERN (tem_insn)))
13744                                   {
13745                                     add_reg_note (tem_insn, REG_UNUSED, piece);
13746                                     break;
13747                                   }
13748                               }
13749                         }
13750
13751                       place = 0;
13752                     }
13753                 }
13754             }
13755           break;
13756
13757         default:
13758           /* Any other notes should not be present at this point in the
13759              compilation.  */
13760           gcc_unreachable ();
13761         }
13762
13763       if (place)
13764         {
13765           XEXP (note, 1) = REG_NOTES (place);
13766           REG_NOTES (place) = note;
13767         }
13768
13769       if (place2)
13770         add_shallow_copy_of_reg_note (place2, note);
13771     }
13772 }
13773 \f
13774 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13775    I3, I2, and I1 to new locations.  This is also called to add a link
13776    pointing at I3 when I3's destination is changed.  */
13777
13778 static void
13779 distribute_links (struct insn_link *links)
13780 {
13781   struct insn_link *link, *next_link;
13782
13783   for (link = links; link; link = next_link)
13784     {
13785       rtx_insn *place = 0;
13786       rtx_insn *insn;
13787       rtx set, reg;
13788
13789       next_link = link->next;
13790
13791       /* If the insn that this link points to is a NOTE or isn't a single
13792          set, ignore it.  In the latter case, it isn't clear what we
13793          can do other than ignore the link, since we can't tell which
13794          register it was for.  Such links wouldn't be used by combine
13795          anyway.
13796
13797          It is not possible for the destination of the target of the link to
13798          have been changed by combine.  The only potential of this is if we
13799          replace I3, I2, and I1 by I3 and I2.  But in that case the
13800          destination of I2 also remains unchanged.  */
13801
13802       if (NOTE_P (link->insn)
13803           || (set = single_set (link->insn)) == 0)
13804         continue;
13805
13806       reg = SET_DEST (set);
13807       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13808              || GET_CODE (reg) == STRICT_LOW_PART)
13809         reg = XEXP (reg, 0);
13810
13811       /* A LOG_LINK is defined as being placed on the first insn that uses
13812          a register and points to the insn that sets the register.  Start
13813          searching at the next insn after the target of the link and stop
13814          when we reach a set of the register or the end of the basic block.
13815
13816          Note that this correctly handles the link that used to point from
13817          I3 to I2.  Also note that not much searching is typically done here
13818          since most links don't point very far away.  */
13819
13820       for (insn = NEXT_INSN (link->insn);
13821            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
13822                      || BB_HEAD (this_basic_block->next_bb) != insn));
13823            insn = NEXT_INSN (insn))
13824         if (DEBUG_INSN_P (insn))
13825           continue;
13826         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13827           {
13828             if (reg_referenced_p (reg, PATTERN (insn)))
13829               place = insn;
13830             break;
13831           }
13832         else if (CALL_P (insn)
13833                  && find_reg_fusage (insn, USE, reg))
13834           {
13835             place = insn;
13836             break;
13837           }
13838         else if (INSN_P (insn) && reg_set_p (reg, insn))
13839           break;
13840
13841       /* If we found a place to put the link, place it there unless there
13842          is already a link to the same insn as LINK at that point.  */
13843
13844       if (place)
13845         {
13846           struct insn_link *link2;
13847
13848           FOR_EACH_LOG_LINK (link2, place)
13849             if (link2->insn == link->insn)
13850               break;
13851
13852           if (link2 == NULL)
13853             {
13854               link->next = LOG_LINKS (place);
13855               LOG_LINKS (place) = link;
13856
13857               /* Set added_links_insn to the earliest insn we added a
13858                  link to.  */
13859               if (added_links_insn == 0
13860                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13861                 added_links_insn = place;
13862             }
13863         }
13864     }
13865 }
13866 \f
13867 /* Check for any register or memory mentioned in EQUIV that is not
13868    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13869    of EXPR where some registers may have been replaced by constants.  */
13870
13871 static bool
13872 unmentioned_reg_p (rtx equiv, rtx expr)
13873 {
13874   subrtx_iterator::array_type array;
13875   FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
13876     {
13877       const_rtx x = *iter;
13878       if ((REG_P (x) || MEM_P (x))
13879           && !reg_mentioned_p (x, expr))
13880         return true;
13881     }
13882   return false;
13883 }
13884 \f
13885 DEBUG_FUNCTION void
13886 dump_combine_stats (FILE *file)
13887 {
13888   fprintf
13889     (file,
13890      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13891      combine_attempts, combine_merges, combine_extras, combine_successes);
13892 }
13893
13894 void
13895 dump_combine_total_stats (FILE *file)
13896 {
13897   fprintf
13898     (file,
13899      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13900      total_attempts, total_merges, total_extras, total_successes);
13901 }
13902 \f
13903 /* Try combining insns through substitution.  */
13904 static unsigned int
13905 rest_of_handle_combine (void)
13906 {
13907   int rebuild_jump_labels_after_combine;
13908
13909   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13910   df_note_add_problem ();
13911   df_analyze ();
13912
13913   regstat_init_n_sets_and_refs ();
13914
13915   rebuild_jump_labels_after_combine
13916     = combine_instructions (get_insns (), max_reg_num ());
13917
13918   /* Combining insns may have turned an indirect jump into a
13919      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13920      instructions.  */
13921   if (rebuild_jump_labels_after_combine)
13922     {
13923       timevar_push (TV_JUMP);
13924       rebuild_jump_labels (get_insns ());
13925       cleanup_cfg (0);
13926       timevar_pop (TV_JUMP);
13927     }
13928
13929   regstat_free_n_sets_and_refs ();
13930   return 0;
13931 }
13932
13933 namespace {
13934
13935 const pass_data pass_data_combine =
13936 {
13937   RTL_PASS, /* type */
13938   "combine", /* name */
13939   OPTGROUP_NONE, /* optinfo_flags */
13940   TV_COMBINE, /* tv_id */
13941   PROP_cfglayout, /* properties_required */
13942   0, /* properties_provided */
13943   0, /* properties_destroyed */
13944   0, /* todo_flags_start */
13945   TODO_df_finish, /* todo_flags_finish */
13946 };
13947
13948 class pass_combine : public rtl_opt_pass
13949 {
13950 public:
13951   pass_combine (gcc::context *ctxt)
13952     : rtl_opt_pass (pass_data_combine, ctxt)
13953   {}
13954
13955   /* opt_pass methods: */
13956   virtual bool gate (function *) { return (optimize > 0); }
13957   virtual unsigned int execute (function *)
13958     {
13959       return rest_of_handle_combine ();
13960     }
13961
13962 }; // class pass_combine
13963
13964 } // anon namespace
13965
13966 rtl_opt_pass *
13967 make_pass_combine (gcc::context *ctxt)
13968 {
13969   return new pass_combine (ctxt);
13970 }