gcc/config/nds32/nds32-memory-manipulation.c

   1 /* Auxiliary functions for expand movmem, setmem, cmpmem, load_multiple
   2    and store_multiple pattern of Andes NDS32 cpu for GNU compiler
   3    Copyright (C) 2012-2015 Free Software Foundation, Inc.
   4    Contributed by Andes Technology Corporation.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 #include "config.h"
  25 #include "system.h"
  26 #include "coretypes.h"
  27 #include "tm.h"
  28 #include "alias.h"
  29 #include "symtab.h"
  30 #include "tree.h"
  31 #include "stor-layout.h"
  32 #include "varasm.h"
  33 #include "calls.h"
  34 #include "rtl.h"
  35 #include "regs.h"
  36 #include "hard-reg-set.h"
  37 #include "insn-config.h"        /* Required by recog.h.  */
  38 #include "conditions.h"
  39 #include "output.h"
  40 #include "insn-attr.h"          /* For DFA state_t.  */
  41 #include "insn-codes.h"         /* For CODE_FOR_xxx.  */
  42 #include "reload.h"             /* For push_reload().  */
  43 #include "flags.h"
  44 #include "function.h"
  45 #include "insn-config.h"
  46 #include "expmed.h"
  47 #include "dojump.h"
  48 #include "explow.h"
  49 #include "emit-rtl.h"
  50 #include "stmt.h"
  51 #include "expr.h"
  52 #include "recog.h"
  53 #include "diagnostic-core.h"
  54 #include "dominance.h"
  55 #include "cfg.h"
  56 #include "cfgrtl.h"
  57 #include "cfganal.h"
  58 #include "lcm.h"
  59 #include "cfgbuild.h"
  60 #include "cfgcleanup.h"
  61 #include "predict.h"
  62 #include "basic-block.h"
  63 #include "df.h"
  64 #include "tm_p.h"
  65 #include "tm-constrs.h"
  66 #include "optabs.h"             /* For GEN_FCN.  */
  67 #include "target.h"
  68 #include "langhooks.h"          /* For add_builtin_function().  */
  69 #include "builtins.h"
  70
  71 /* ------------------------------------------------------------------------ */
  72
  73 /* Functions to expand load_multiple and store_multiple.
  74    They are auxiliary extern functions to help create rtx template.
  75    Check nds32-multiple.md file for the patterns.  */
  76 rtx
  77 nds32_expand_load_multiple (int base_regno, int count,
  78                             rtx base_addr, rtx basemem)
  79 {
  80   int par_index;
  81   int offset;
  82   rtx result;
  83   rtx new_addr, mem, reg;
  84
  85   /* Create the pattern that is presented in nds32-multiple.md.  */
  86
  87   result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
  88
  89   for (par_index = 0; par_index < count; par_index++)
  90     {
  91       offset   = par_index * 4;
  92       /* 4-byte for loading data to each register.  */
  93       new_addr = plus_constant (Pmode, base_addr, offset);
  94       mem      = adjust_automodify_address_nv (basemem, SImode,
  95                                                new_addr, offset);
  96       reg      = gen_rtx_REG (SImode, base_regno + par_index);
  97
  98       XVECEXP (result, 0, par_index) = gen_rtx_SET (reg, mem);
  99     }
 100
 101   return result;
 102 }
 103
 104 rtx
 105 nds32_expand_store_multiple (int base_regno, int count,
 106                              rtx base_addr, rtx basemem)
 107 {
 108   int par_index;
 109   int offset;
 110   rtx result;
 111   rtx new_addr, mem, reg;
 112
 113   /* Create the pattern that is presented in nds32-multiple.md.  */
 114
 115   result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
 116
 117   for (par_index = 0; par_index < count; par_index++)
 118     {
 119       offset   = par_index * 4;
 120       /* 4-byte for storing data to memory.  */
 121       new_addr = plus_constant (Pmode, base_addr, offset);
 122       mem      = adjust_automodify_address_nv (basemem, SImode,
 123                                                new_addr, offset);
 124       reg      = gen_rtx_REG (SImode, base_regno + par_index);
 125
 126       XVECEXP (result, 0, par_index) = gen_rtx_SET (mem, reg);
 127     }
 128
 129   return result;
 130 }
 131
 132 /* Function to move block memory content by
 133    using load_multiple and store_multiple.
 134    This is auxiliary extern function to help create rtx template.
 135    Check nds32-multiple.md file for the patterns.  */
 136 int
 137 nds32_expand_movmemqi (rtx dstmem, rtx srcmem, rtx total_bytes, rtx alignment)
 138 {
 139   HOST_WIDE_INT in_words, out_words;
 140   rtx dst_base_reg, src_base_reg;
 141   int maximum_bytes;
 142
 143   /* Because reduced-set regsiters has few registers
 144      (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31'
 145       cannot be used for register allocation),
 146      using 8 registers (32 bytes) for moving memory block
 147      may easily consume all of them.
 148      It makes register allocation/spilling hard to work.
 149      So we only allow maximum=4 registers (16 bytes) for
 150      moving memory block under reduced-set registers.  */
 151   if (TARGET_REDUCED_REGS)
 152     maximum_bytes = 16;
 153   else
 154     maximum_bytes = 32;
 155
 156   /* 1. Total_bytes is integer for sure.
 157      2. Alignment is integer for sure.
 158      3. Maximum 4 or 8 registers, 4 * 4 = 16 bytes, 8 * 4 = 32 bytes.
 159      4. Requires (n * 4) block size.
 160      5. Requires 4-byte alignment.  */
 161   if (GET_CODE (total_bytes) != CONST_INT
 162       || GET_CODE (alignment) != CONST_INT
 163       || INTVAL (total_bytes) > maximum_bytes
 164       || INTVAL (total_bytes) & 3
 165       || INTVAL (alignment) & 3)
 166     return 0;
 167
 168   dst_base_reg = copy_to_mode_reg (SImode, XEXP (dstmem, 0));
 169   src_base_reg = copy_to_mode_reg (SImode, XEXP (srcmem, 0));
 170
 171   out_words = in_words = INTVAL (total_bytes) / UNITS_PER_WORD;
 172
 173   emit_insn (nds32_expand_load_multiple (0, in_words, src_base_reg, srcmem));
 174   emit_insn (nds32_expand_store_multiple (0, out_words, dst_base_reg, dstmem));
 175
 176   /* Successfully create patterns, return 1.  */
 177   return 1;
 178 }
 179
 180 /* ------------------------------------------------------------------------ */