| blob | 3558b4e93daa96c04bff89ea76b5dd98bd17fb57 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
92 #ifndef CHECK_STACK_LIMIT
93 #define CHECK_STACK_LIMIT (-1)
94 #endif
96 /* Return index of given mode in mult and division cost tables. */
97 #define MODE_INDEX(mode) \
98 ((mode) == QImode ? 0 \
99 : (mode) == HImode ? 1 \
100 : (mode) == SImode ? 2 \
101 : (mode) == DImode ? 3 \
102 : 4)
104 /* Processor costs (relative to an add) */
105 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
106 #define COSTS_N_BYTES(N) ((N) * 2)
108 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
117 const
140 in QImode, HImode and SImode.
141 Relative to reg-reg move (2). */
145 in SFmode, DFmode and XFmode */
147 in SFmode, DFmode and XFmode */
150 in SImode and DImode */
152 in SImode and DImode */
155 in SImode, DImode and TImode */
157 in SImode, DImode and TImode */
170 ix86_size_memcpy,
171 ix86_size_memset,
183 };
185 /* Processor costs (relative to an add) */
188 DUMMY_STRINGOP_ALGS};
191 DUMMY_STRINGOP_ALGS};
193 static const
216 in QImode, HImode and SImode.
217 Relative to reg-reg move (2). */
221 in SFmode, DFmode and XFmode */
223 in SFmode, DFmode and XFmode */
226 in SImode and DImode */
228 in SImode and DImode */
231 in SImode, DImode and TImode */
233 in SImode, DImode and TImode */
246 i386_memcpy,
247 i386_memset,
259 };
263 DUMMY_STRINGOP_ALGS};
266 DUMMY_STRINGOP_ALGS};
268 static const
291 in QImode, HImode and SImode.
292 Relative to reg-reg move (2). */
296 in SFmode, DFmode and XFmode */
298 in SFmode, DFmode and XFmode */
301 in SImode and DImode */
303 in SImode and DImode */
306 in SImode, DImode and TImode */
308 in SImode, DImode and TImode */
311 shared for code and data, so 4kB is
312 not really precise. */
323 i486_memcpy,
324 i486_memset,
336 };
340 DUMMY_STRINGOP_ALGS};
343 DUMMY_STRINGOP_ALGS};
345 static const
368 in QImode, HImode and SImode.
369 Relative to reg-reg move (2). */
373 in SFmode, DFmode and XFmode */
375 in SFmode, DFmode and XFmode */
378 in SImode and DImode */
380 in SImode and DImode */
383 in SImode, DImode and TImode */
385 in SImode, DImode and TImode */
398 pentium_memcpy,
399 pentium_memset,
411 };
413 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
414 (we ensure the alignment). For small blocks inline loop is still a
415 noticeable win, for bigger blocks either rep movsl or rep movsb is
416 way to go. Rep movsb has apparently more expensive startup time in CPU,
417 but after 4K the difference is down in the noise. */
422 DUMMY_STRINGOP_ALGS};
427 DUMMY_STRINGOP_ALGS};
428 static const
451 in QImode, HImode and SImode.
452 Relative to reg-reg move (2). */
456 in SFmode, DFmode and XFmode */
458 in SFmode, DFmode and XFmode */
461 in SImode and DImode */
463 in SImode and DImode */
466 in SImode, DImode and TImode */
468 in SImode, DImode and TImode */
481 pentiumpro_memcpy,
482 pentiumpro_memset,
494 };
498 DUMMY_STRINGOP_ALGS};
501 DUMMY_STRINGOP_ALGS};
502 static const
525 in QImode, HImode and SImode.
526 Relative to reg-reg move (2). */
530 in SFmode, DFmode and XFmode */
532 in SFmode, DFmode and XFmode */
536 in SImode and DImode */
538 in SImode and DImode */
541 in SImode, DImode and TImode */
543 in SImode, DImode and TImode */
556 geode_memcpy,
557 geode_memset,
569 };
573 DUMMY_STRINGOP_ALGS};
576 DUMMY_STRINGOP_ALGS};
577 static const
600 in QImode, HImode and SImode.
601 Relative to reg-reg move (2). */
605 in SFmode, DFmode and XFmode */
607 in SFmode, DFmode and XFmode */
610 in SImode and DImode */
612 in SImode and DImode */
615 in SImode, DImode and TImode */
617 in SImode, DImode and TImode */
621 have integrated l2 cache, but
622 optimizing for k6 is not important
623 enough to worry about that. */
633 k6_memcpy,
634 k6_memset,
646 };
648 /* For some reason, Athlon deals better with REP prefix (relative to loops)
649 compared to K8. Alignment becomes important after 8 bytes for memcpy and
650 128 bytes for memset. */
653 DUMMY_STRINGOP_ALGS};
656 DUMMY_STRINGOP_ALGS};
657 static const
680 in QImode, HImode and SImode.
681 Relative to reg-reg move (2). */
685 in SFmode, DFmode and XFmode */
687 in SFmode, DFmode and XFmode */
690 in SImode and DImode */
692 in SImode and DImode */
695 in SImode, DImode and TImode */
697 in SImode, DImode and TImode */
710 athlon_memcpy,
711 athlon_memset,
723 };
725 /* K8 has optimized REP instruction for medium sized blocks, but for very
726 small blocks it is better to use loop. For large blocks, libcall can
727 do nontemporary accesses and beat inline considerably. */
738 static const
761 in QImode, HImode and SImode.
762 Relative to reg-reg move (2). */
766 in SFmode, DFmode and XFmode */
768 in SFmode, DFmode and XFmode */
771 in SImode and DImode */
773 in SImode and DImode */
776 in SImode, DImode and TImode */
778 in SImode, DImode and TImode */
783 /* New AMD processors never drop prefetches; if they cannot be performed
784 immediately, they are queued. We set number of simultaneous prefetches
785 to a large constant to reflect this (it probably is not a good idea not
786 to limit number of prefetches at all, as their execution also takes some
787 time). */
797 k8_memcpy,
798 k8_memset,
810 };
812 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
813 very small blocks it is better to use loop. For large blocks, libcall can
814 do nontemporary accesses and beat inline considerably. */
847 in QImode, HImode and SImode.
848 Relative to reg-reg move (2). */
852 in SFmode, DFmode and XFmode */
854 in SFmode, DFmode and XFmode */
857 in SImode and DImode */
859 in SImode and DImode */
862 in SImode, DImode and TImode */
864 in SImode, DImode and TImode */
866 /* On K8:
867 MOVD reg64, xmmreg Double FSTORE 4
868 MOVD reg32, xmmreg Double FSTORE 4
869 On AMDFAM10:
870 MOVD reg64, xmmreg Double FADD 3
871 1/1 1/1
872 MOVD reg32, xmmreg Double FADD 3
873 1/1 1/1 */
877 /* New AMD processors never drop prefetches; if they cannot be performed
878 immediately, they are queued. We set number of simultaneous prefetches
879 to a large constant to reflect this (it probably is not a good idea not
880 to limit number of prefetches at all, as their execution also takes some
881 time). */
891 amdfam10_memcpy,
892 amdfam10_memset,
904 };
906 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
907 very small blocks it is better to use loop. For large blocks, libcall
908 can do nontemporary accesses and beat inline considerably. */
942 in QImode, HImode and SImode.
943 Relative to reg-reg move (2). */
947 in SFmode, DFmode and XFmode */
949 in SFmode, DFmode and XFmode */
952 in SImode and DImode */
954 in SImode and DImode */
957 in SImode, DImode and TImode */
959 in SImode, DImode and TImode */
961 /* On K8:
962 MOVD reg64, xmmreg Double FSTORE 4
963 MOVD reg32, xmmreg Double FSTORE 4
964 On AMDFAM10:
965 MOVD reg64, xmmreg Double FADD 3
966 1/1 1/1
967 MOVD reg32, xmmreg Double FADD 3
968 1/1 1/1 */
972 /* New AMD processors never drop prefetches; if they cannot be performed
973 immediately, they are queued. We set number of simultaneous prefetches
974 to a large constant to reflect this (it probably is not a good idea not
975 to limit number of prefetches at all, as their execution also takes some
976 time). */
986 bdver1_memcpy,
987 bdver1_memset,
999 };
1001 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1002 very small blocks it is better to use loop. For large blocks, libcall
1003 can do nontemporary accesses and beat inline considerably. */
1038 in QImode, HImode and SImode.
1039 Relative to reg-reg move (2). */
1043 in SFmode, DFmode and XFmode */
1045 in SFmode, DFmode and XFmode */
1048 in SImode and DImode */
1050 in SImode and DImode */
1053 in SImode, DImode and TImode */
1055 in SImode, DImode and TImode */
1057 /* On K8:
1058 MOVD reg64, xmmreg Double FSTORE 4
1059 MOVD reg32, xmmreg Double FSTORE 4
1060 On AMDFAM10:
1061 MOVD reg64, xmmreg Double FADD 3
1062 1/1 1/1
1063 MOVD reg32, xmmreg Double FADD 3
1064 1/1 1/1 */
1068 /* New AMD processors never drop prefetches; if they cannot be performed
1069 immediately, they are queued. We set number of simultaneous prefetches
1070 to a large constant to reflect this (it probably is not a good idea not
1071 to limit number of prefetches at all, as their execution also takes some
1072 time). */
1082 bdver2_memcpy,
1083 bdver2_memset,
1095 };
1098 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1099 very small blocks it is better to use loop. For large blocks, libcall
1100 can do nontemporary accesses and beat inline considerably. */
1133 in QImode, HImode and SImode.
1134 Relative to reg-reg move (2). */
1138 in SFmode, DFmode and XFmode */
1140 in SFmode, DFmode and XFmode */
1143 in SImode and DImode */
1145 in SImode and DImode */
1148 in SImode, DImode and TImode */
1150 in SImode, DImode and TImode */
1155 /* New AMD processors never drop prefetches; if they cannot be performed
1156 immediately, they are queued. We set number of simultaneous prefetches
1157 to a large constant to reflect this (it probably is not a good idea not
1158 to limit number of prefetches at all, as their execution also takes some
1159 time). */
1169 bdver3_memcpy,
1170 bdver3_memset,
1182 };
1184 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1185 very small blocks it is better to use loop. For large blocks, libcall
1186 can do nontemporary accesses and beat inline considerably. */
1219 in QImode, HImode and SImode.
1220 Relative to reg-reg move (2). */
1224 in SFmode, DFmode and XFmode */
1226 in SFmode, DFmode and XFmode */
1229 in SImode and DImode */
1231 in SImode and DImode */
1234 in SImode, DImode and TImode */
1236 in SImode, DImode and TImode */
1241 /* New AMD processors never drop prefetches; if they cannot be performed
1242 immediately, they are queued. We set number of simultaneous prefetches
1243 to a large constant to reflect this (it probably is not a good idea not
1244 to limit number of prefetches at all, as their execution also takes some
1245 time). */
1255 bdver4_memcpy,
1256 bdver4_memset,
1268 };
1270 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1271 very small blocks it is better to use loop. For large blocks, libcall can
1272 do nontemporary accesses and beat inline considerably. */
1305 in QImode, HImode and SImode.
1306 Relative to reg-reg move (2). */
1310 in SFmode, DFmode and XFmode */
1312 in SFmode, DFmode and XFmode */
1315 in SImode and DImode */
1317 in SImode and DImode */
1320 in SImode, DImode and TImode */
1322 in SImode, DImode and TImode */
1324 /* On K8:
1325 MOVD reg64, xmmreg Double FSTORE 4
1326 MOVD reg32, xmmreg Double FSTORE 4
1327 On AMDFAM10:
1328 MOVD reg64, xmmreg Double FADD 3
1329 1/1 1/1
1330 MOVD reg32, xmmreg Double FADD 3
1331 1/1 1/1 */
1344 btver1_memcpy,
1345 btver1_memset,
1357 };
1391 in QImode, HImode and SImode.
1392 Relative to reg-reg move (2). */
1396 in SFmode, DFmode and XFmode */
1398 in SFmode, DFmode and XFmode */
1401 in SImode and DImode */
1403 in SImode and DImode */
1406 in SImode, DImode and TImode */
1408 in SImode, DImode and TImode */
1410 /* On K8:
1411 MOVD reg64, xmmreg Double FSTORE 4
1412 MOVD reg32, xmmreg Double FSTORE 4
1413 On AMDFAM10:
1414 MOVD reg64, xmmreg Double FADD 3
1415 1/1 1/1
1416 MOVD reg32, xmmreg Double FADD 3
1417 1/1 1/1 */
1429 btver2_memcpy,
1430 btver2_memset,
1442 };
1446 DUMMY_STRINGOP_ALGS};
1450 DUMMY_STRINGOP_ALGS};
1452 static const
1475 in QImode, HImode and SImode.
1476 Relative to reg-reg move (2). */
1480 in SFmode, DFmode and XFmode */
1482 in SFmode, DFmode and XFmode */
1485 in SImode and DImode */
1487 in SImode and DImode */
1490 in SImode, DImode and TImode */
1492 in SImode, DImode and TImode */
1505 pentium4_memcpy,
1506 pentium4_memset,
1518 };
1531 static const
1554 in QImode, HImode and SImode.
1555 Relative to reg-reg move (2). */
1559 in SFmode, DFmode and XFmode */
1561 in SFmode, DFmode and XFmode */
1564 in SImode and DImode */
1566 in SImode and DImode */
1569 in SImode, DImode and TImode */
1571 in SImode, DImode and TImode */
1584 nocona_memcpy,
1585 nocona_memset,
1597 };
1608 static const
1631 in QImode, HImode and SImode.
1632 Relative to reg-reg move (2). */
1636 in SFmode, DFmode and XFmode */
1638 in SFmode, DFmode and XFmode */
1641 in SImode and DImode */
1643 in SImode and DImode */
1646 in SImode, DImode and TImode */
1648 in SImode, DImode and TImode */
1661 atom_memcpy,
1662 atom_memset,
1674 };
1685 static const
1708 in QImode, HImode and SImode.
1709 Relative to reg-reg move (2). */
1713 in SFmode, DFmode and XFmode */
1715 in SFmode, DFmode and XFmode */
1718 in SImode and DImode */
1720 in SImode and DImode */
1723 in SImode, DImode and TImode */
1725 in SImode, DImode and TImode */
1738 slm_memcpy,
1739 slm_memset,
1751 };
1762 static const
1785 in QImode, HImode and SImode.
1786 Relative to reg-reg move (2). */
1790 in SFmode, DFmode and XFmode */
1792 in SFmode, DFmode and XFmode */
1795 in SImode and DImode */
1797 in SImode and DImode */
1800 in SImode, DImode and TImode */
1802 in SImode, DImode and TImode */
1815 intel_memcpy,
1816 intel_memset,
1828 };
1830 /* Generic should produce code tuned for Core-i7 (and newer chips)
1831 and btver1 (and newer chips). */
1843 static const
1846 /* On all chips taken into consideration lea is 2 cycles and more. With
1847 this cost however our current implementation of synth_mult results in
1848 use of unnecessary temporary registers causing regression on several
1849 SPECfp benchmarks. */
1870 in QImode, HImode and SImode.
1871 Relative to reg-reg move (2). */
1875 in SFmode, DFmode and XFmode */
1877 in SFmode, DFmode and XFmode */
1880 in SImode and DImode */
1882 in SImode and DImode */
1885 in SImode, DImode and TImode */
1887 in SImode, DImode and TImode */
1893 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1894 value is increased to perhaps more appropriate value of 5. */
1902 generic_memcpy,
1903 generic_memset,
1915 };
1917 /* core_cost should produce code tuned for Core familly of CPUs. */
1930 static const
1933 /* On all chips taken into consideration lea is 2 cycles and more. With
1934 this cost however our current implementation of synth_mult results in
1935 use of unnecessary temporary registers causing regression on several
1936 SPECfp benchmarks. */
1957 in QImode, HImode and SImode.
1958 Relative to reg-reg move (2). */
1962 in SFmode, DFmode and XFmode */
1964 in SFmode, DFmode and XFmode */
1967 in SImode and DImode */
1969 in SImode and DImode */
1972 in SImode, DImode and TImode */
1974 in SImode, DImode and TImode */
1980 /* FIXME perhaps more appropriate value is 5. */
1988 core_memcpy,
1989 core_memset,
2001 };
2004 /* Set by -mtune. */
2007 /* Set by -mtune or -Os. */
2010 /* Processor feature/optimization bitmasks. */
2011 #define m_386 (1<<PROCESSOR_I386)
2012 #define m_486 (1<<PROCESSOR_I486)
2013 #define m_PENT (1<<PROCESSOR_PENTIUM)
2014 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2015 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2016 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2017 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2018 #define m_CORE2 (1<<PROCESSOR_CORE2)
2019 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2020 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2021 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2022 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2023 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2024 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2025 #define m_INTEL (1<<PROCESSOR_INTEL)
2027 #define m_GEODE (1<<PROCESSOR_GEODE)
2028 #define m_K6 (1<<PROCESSOR_K6)
2029 #define m_K6_GEODE (m_K6 | m_GEODE)
2030 #define m_K8 (1<<PROCESSOR_K8)
2031 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2032 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2033 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2034 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2035 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2036 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2037 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2038 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2039 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2040 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2041 #define m_BTVER (m_BTVER1 | m_BTVER2)
2042 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2044 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2047 #undef DEF_TUNE
2048 #define DEF_TUNE(tune, name, selector) name,
2050 #undef DEF_TUNE
2051 };
2053 /* Feature tests against the various tunings. */
2056 /* Feature tests against the various tunings used to create ix86_tune_features
2057 based on the processor mask. */
2059 #undef DEF_TUNE
2060 #define DEF_TUNE(tune, name, selector) selector,
2062 #undef DEF_TUNE
2063 };
2065 /* Feature tests against the various architecture variations. */
2068 /* Feature tests against the various architecture variations, used to create
2069 ix86_arch_features based on the processor mask. */
2071 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2074 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2077 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2080 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2083 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2085 };
2087 /* In case the average insn count for single function invocation is
2088 lower than this constant, emit fast (but longer) prologue and
2089 epilogue code. */
2090 #define FAST_PROLOGUE_INSN_COUNT 20
2092 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2097 /* Array of the smallest class containing reg number REGNO, indexed by
2098 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2101 {
2102 /* ax, dx, cx, bx */
2104 /* si, di, bp, sp */
2106 /* FP registers */
2109 /* arg pointer */
2110 NON_Q_REGS,
2111 /* flags, fpsr, fpcr, frame */
2113 /* SSE registers */
2116 /* MMX registers */
2119 /* REX registers */
2122 /* SSE REX registers */
2125 /* AVX-512 SSE registers */
2130 /* Mask registers. */
2133 };
2135 /* The "default" register map used in 32bit mode. */
2138 {
2149 };
2151 /* The "default" register map used in 64bit mode. */
2154 {
2165 };
2167 /* Define the register numbers to be used in Dwarf debugging information.
2168 The SVR4 reference port C compiler uses the following register numbers
2169 in its Dwarf output code:
2170 0 for %eax (gcc regno = 0)
2171 1 for %ecx (gcc regno = 2)
2172 2 for %edx (gcc regno = 1)
2173 3 for %ebx (gcc regno = 3)
2174 4 for %esp (gcc regno = 7)
2175 5 for %ebp (gcc regno = 6)
2176 6 for %esi (gcc regno = 4)
2177 7 for %edi (gcc regno = 5)
2178 The following three DWARF register numbers are never generated by
2179 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2180 believes these numbers have these meanings.
2181 8 for %eip (no gcc equivalent)
2182 9 for %eflags (gcc regno = 17)
2183 10 for %trapno (no gcc equivalent)
2184 It is not at all clear how we should number the FP stack registers
2185 for the x86 architecture. If the version of SDB on x86/svr4 were
2186 a bit less brain dead with respect to floating-point then we would
2187 have a precedent to follow with respect to DWARF register numbers
2188 for x86 FP registers, but the SDB on x86/svr4 is so completely
2189 broken with respect to FP registers that it is hardly worth thinking
2190 of it as something to strive for compatibility with.
2191 The version of x86/svr4 SDB I have at the moment does (partially)
2192 seem to believe that DWARF register number 11 is associated with
2193 the x86 register %st(0), but that's about all. Higher DWARF
2194 register numbers don't seem to be associated with anything in
2195 particular, and even for DWARF regno 11, SDB only seems to under-
2196 stand that it should say that a variable lives in %st(0) (when
2197 asked via an `=' command) if we said it was in DWARF regno 11,
2198 but SDB still prints garbage when asked for the value of the
2199 variable in question (via a `/' command).
2200 (Also note that the labels SDB prints for various FP stack regs
2201 when doing an `x' command are all wrong.)
2202 Note that these problems generally don't affect the native SVR4
2203 C compiler because it doesn't allow the use of -O with -g and
2204 because when it is *not* optimizing, it allocates a memory
2205 location for each floating-point variable, and the memory
2206 location is what gets described in the DWARF AT_location
2207 attribute for the variable in question.
2208 Regardless of the severe mental illness of the x86/svr4 SDB, we
2209 do something sensible here and we use the following DWARF
2210 register numbers. Note that these are all stack-top-relative
2211 numbers.
2212 11 for %st(0) (gcc regno = 8)
2213 12 for %st(1) (gcc regno = 9)
2214 13 for %st(2) (gcc regno = 10)
2215 14 for %st(3) (gcc regno = 11)
2216 15 for %st(4) (gcc regno = 12)
2217 16 for %st(5) (gcc regno = 13)
2218 17 for %st(6) (gcc regno = 14)
2219 18 for %st(7) (gcc regno = 15)
2220 */
2222 {
2233 };
2235 /* Define parameter passing and return registers. */
2238 {
2240 };
2243 {
2245 };
2248 {
2250 };
2252 /* Additional registers that are clobbered by SYSV calls. */
2255 {
2260 };
2262 /* Define the structure for the machine field in struct function. */
2267 rtx rtl;
2269 };
2271 /* Structure describing stack frame layout.
2272 Stack grows downward:
2274 [arguments]
2275 <- ARG_POINTER
2276 saved pc
2278 saved static chain if ix86_static_chain_on_stack
2280 saved frame pointer if frame_pointer_needed
2281 <- HARD_FRAME_POINTER
2282 [saved regs]
2283 <- regs_save_offset
2284 [padding0]
2286 [saved SSE regs]
2287 <- sse_regs_save_offset
2288 [padding1] |
2289 | <- FRAME_POINTER
2290 [va_arg registers] |
2291 |
2292 [frame] |
2293 |
2294 [padding2] | = to_allocate
2295 <- STACK_POINTER
2296 */
2297 struct ix86_frame
2298 {
2305 /* The offsets relative to ARG_POINTER. */
2306 HOST_WIDE_INT frame_pointer_offset;
2307 HOST_WIDE_INT hard_frame_pointer_offset;
2308 HOST_WIDE_INT stack_pointer_offset;
2309 HOST_WIDE_INT hfp_save_offset;
2310 HOST_WIDE_INT reg_save_offset;
2311 HOST_WIDE_INT sse_reg_save_offset;
2313 /* When save_regs_using_mov is set, emit prologue using
2314 move instead of push instructions. */
2316 };
2318 /* Which cpu are we scheduling for. */
2321 /* Which cpu are we optimizing for. */
2324 /* Which instruction set architecture to use. */
2327 /* True if processor has SSE prefetch instruction. */
2330 /* -mstackrealign option */
2347 /* Preferred alignment for stack boundary in bits. */
2350 /* Alignment for incoming stack boundary in bits specified at
2351 command line. */
2354 /* Default alignment for incoming stack boundary in bits. */
2357 /* Alignment for incoming stack boundary in bits. */
2360 /* Calling abi specific va_list type nodes. */
2364 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2368 /* Fence to use after loop using movnt. */
2369 tree x86_mfence;
2371 /* Register class used for passing given 64bit part of the argument.
2372 These represent classes as documented by the PS ABI, with the exception
2373 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2374 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2376 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2377 whenever possible (upper half does contain padding). */
2378 enum x86_64_reg_class
2379 {
2380 X86_64_NO_CLASS,
2381 X86_64_INTEGER_CLASS,
2382 X86_64_INTEGERSI_CLASS,
2383 X86_64_SSE_CLASS,
2384 X86_64_SSESF_CLASS,
2385 X86_64_SSEDF_CLASS,
2386 X86_64_SSEUP_CLASS,
2387 X86_64_X87_CLASS,
2388 X86_64_X87UP_CLASS,
2389 X86_64_COMPLEX_X87_CLASS,
2390 X86_64_MEMORY_CLASS
2391 };
2393 #define MAX_CLASSES 8
2395 /* Table of constants used by fldpi, fldln2, etc.... */
2399 \f
2404 const_tree);
2416 enum ix86_function_specific_strings
2417 {
2418 IX86_FUNCTION_SPECIFIC_ARCH,
2419 IX86_FUNCTION_SPECIFIC_TUNE,
2420 IX86_FUNCTION_SPECIFIC_MAX
2421 };
2442 \f
2443 #ifndef SUBTARGET32_DEFAULT_CPU
2445 #endif
2447 /* Whether -mtune= or -march= were specified */
2451 /* Vectorization library interface and handlers. */
2457 /* Processor target table, indexed by processor number */
2458 struct ptt
2459 {
2467 };
2469 /* This table must be in sync with enum processor_type in i386.h. */
2471 {
2497 };
2498 \f
2499 static unsigned int
2501 {
2504 /* vzeroupper instructions are inserted immediately after reload to
2505 account for possible spills from 256bit registers. The pass
2506 reuses mode switching infrastructure by re-running mode insertion
2507 pass, so disable entities that have already been processed. */
2513 /* Call optimize_mode_switching. */
2516 }
2521 {
2531 };
2534 {
2538 {}
2540 /* opt_pass methods: */
2542 {
2544 }
2547 {
2549 }
2555 rtl_opt_pass *
2557 {
2559 }
2561 /* Return true if a red-zone is in use. */
2565 {
2567 }
2568 \f
2569 /* Return a string that documents the current -m options. The caller is
2570 responsible for freeing the string. */
2576 {
2577 struct ix86_target_opts
2578 {
2581 };
2583 /* This table is ordered so that options like -msse4.2 that imply
2584 preceding options while match those first. */
2586 {
2634 };
2636 /* Flag options. */
2638 {
2667 };
2684 /* Add -march= option. */
2686 {
2689 }
2691 /* Add -mtune= option. */
2693 {
2696 }
2698 /* Add -m32/-m64/-mx32. */
2700 {
2703 else
2705 isa &= ~ (OPTION_MASK_ISA_64BIT
2706 | OPTION_MASK_ABI_64
2708 }
2709 else
2713 /* Pick out the options in isa options. */
2715 {
2717 {
2720 }
2721 }
2724 {
2727 isa);
2728 }
2730 /* Add flag options. */
2732 {
2734 {
2737 }
2738 }
2741 {
2744 }
2746 /* Add -fpmath= option. */
2748 {
2751 {
2766 }
2767 }
2769 /* Any options? */
2775 /* Size the string. */
2779 {
2784 }
2786 /* Build the string. */
2791 {
2798 {
2800 line_len++;
2803 {
2807 }
2808 }
2812 {
2816 }
2817 }
2823 }
2825 /* Return true, if profiling code should be emitted before
2826 prologue. Otherwise it returns false.
2827 Note: For x86 with "hotfix" it is sorried. */
2828 static bool
2830 {
2832 }
2834 /* Function that is callable from the debugger to print the current
2835 options. */
2836 void ATTRIBUTE_UNUSED
2838 {
2844 {
2847 }
2848 else
2852 }
2855 #define DEF_ENUM
2856 #define DEF_ALG(alg, name) #name,
2858 #undef DEF_ENUM
2859 #undef DEF_ALG
2860 };
2862 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2863 The string is of the following form (or comma separated list of it):
2865 strategy_alg:max_size:[align|noalign]
2867 where the full size range for the strategy is either [0, max_size] or
2868 [min_size, max_size], in which min_size is the max_size + 1 of the
2869 preceding range. The last size range must have max_size == -1.
2871 Examples:
2873 1.
2874 -mmemcpy-strategy=libcall:-1:noalign
2876 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2879 2.
2880 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2882 This is to tell the compiler to use the following strategy for memset
2883 1) when the expected size is between [1, 16], use rep_8byte strategy;
2884 2) when the size is between [17, 2048], use vector_loop;
2885 3) when the size is > 2048, use libcall. */
2887 struct stringop_size_range
2888 {
2890 stringop_alg alg;
2892 };
2894 static void
2896 {
2904 else
2909 do
2910 {
2920 {
2924 }
2927 {
2931 }
2938 {
2940 alg_name,
2943 }
2951 else
2952 {
2956 }
2957 n++;
2959 }
2963 {
2968 }
2971 {
2975 }
2977 /* Now override the default algs array. */
2979 {
2985 }
2986 }
2988 \f
2989 /* parse -mtune-ctrl= option. When DUMP is true,
2990 print the features that are explicitly set. */
2992 static void
2994 {
3002 do
3003 {
3010 {
3011 curr_feature_string++;
3013 }
3015 {
3017 {
3023 }
3024 }
3029 }
3032 }
3034 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3035 processor type. */
3037 static void
3039 {
3044 {
3047 else
3049 }
3052 {
3057 }
3060 }
3063 /* Override various settings based on options. If MAIN_ARGS_P, the
3064 options are from the command line, otherwise they are from
3065 attributes. */
3067 static void
3071 {
3079 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3080 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3081 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3082 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3083 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3084 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3085 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3086 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3087 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3088 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3089 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3090 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3091 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3092 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3093 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3094 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3095 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3096 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3097 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3098 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3099 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3100 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3101 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3102 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3103 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3104 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3105 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3106 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3107 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3108 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3109 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3110 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3111 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3112 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3113 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3114 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3115 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3116 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3117 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3118 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3119 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3120 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3121 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3122 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3123 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3124 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3125 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3126 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3127 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3128 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3129 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3130 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3132 #define PTA_CORE2 \
3133 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3134 | PTA_CX16 | PTA_FXSR)
3135 #define PTA_NEHALEM \
3136 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3137 #define PTA_WESTMERE \
3138 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3139 #define PTA_SANDYBRIDGE \
3140 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3141 #define PTA_IVYBRIDGE \
3142 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3143 #define PTA_HASWELL \
3144 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3145 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3146 #define PTA_BROADWELL \
3147 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3148 #define PTA_BONNELL \
3149 (PTA_CORE2 | PTA_MOVBE)
3150 #define PTA_SILVERMONT \
3151 (PTA_WESTMERE | PTA_MOVBE)
3153 /* if this reaches 64, need to widen struct pta flags below */
3155 static struct pta
3156 {
3161 }
3163 {
3197 PTA_SANDYBRIDGE},
3199 PTA_SANDYBRIDGE},
3201 PTA_IVYBRIDGE},
3203 PTA_IVYBRIDGE},
3294 PTA_64BIT
3296 };
3298 /* -mrecip options. */
3299 static struct
3300 {
3303 }
3305 {
3312 };
3316 /* Set up prefix/suffix so the error messages refer to either the command
3317 line argument, or the attribute(target). */
3319 {
3323 }
3324 else
3325 {
3329 }
3331 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3332 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3335 #ifdef TARGET_BI_ARCH
3336 else
3337 {
3338 #if TARGET_BI_ARCH == 1
3339 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3340 is on and OPTION_MASK_ABI_X32 is off. We turn off
3341 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3342 -mx32. */
3345 #else
3346 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3347 on and OPTION_MASK_ABI_64 is off. We turn off
3348 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3349 -m64. */
3352 #endif
3353 }
3354 #endif
3357 {
3358 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3359 OPTION_MASK_ABI_64 for TARGET_X32. */
3362 }
3365 | OPTION_MASK_ABI_X32
3368 {
3369 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3370 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3373 }
3375 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3376 SUBTARGET_OVERRIDE_OPTIONS;
3377 #endif
3379 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3380 SUBSUBTARGET_OVERRIDE_OPTIONS;
3381 #endif
3383 /* -fPIC is the default for x86_64. */
3387 /* Need to check -mtune=generic first. */
3389 {
3390 /* As special support for cross compilers we read -mtune=native
3391 as -mtune=generic. With native compilers we won't see the
3392 -mtune=native, as it was changed by the driver. */
3394 {
3396 }
3401 }
3402 else
3403 {
3407 {
3408 opts->x_ix86_tune_string
3411 }
3413 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3414 or defaulted. We need to use a sensible tune option. */
3416 {
3418 }
3419 }
3423 {
3424 /* rep; movq isn't available in 32-bit code. */
3427 }
3430 opts->x_ix86_arch_string
3433 else
3437 {
3445 }
3446 else
3453 /* For targets using ms ABI enable ms-extensions, if not
3454 explicit turned off. For non-ms ABI we turn off this
3455 option. */
3460 {
3462 {
3506 {
3509 }
3517 }
3518 }
3519 else
3520 {
3521 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3522 use of rip-relative addressing. This eliminates fixups that
3523 would otherwise be needed if this object is to be placed in a
3524 DLL, and is essentially just as efficient as direct addressing. */
3530 else
3532 }
3534 {
3537 }
3545 {
3548 /* Default cpu tuning to the architecture. */
3711 }
3729 {
3733 {
3735 {
3737 {
3745 }
3746 else
3749 }
3750 }
3751 /* Intel CPUs have always interpreted SSE prefetch instructions as
3752 NOPs; so, we can enable SSE prefetch instructions even when
3753 -mtune (rather than -march) points us to a processor that has them.
3754 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3755 higher processors. */
3760 }
3768 #ifndef USE_IX86_FRAME_POINTER
3769 #define USE_IX86_FRAME_POINTER 0
3770 #endif
3772 #ifndef USE_X86_64_FRAME_POINTER
3773 #define USE_X86_64_FRAME_POINTER 0
3774 #endif
3776 /* Set the default values for switches whose default depends on TARGET_64BIT
3777 in case they weren't overwritten by command line options. */
3779 {
3787 opts->x_flag_unwind_tables
3791 }
3792 else
3793 {
3795 opts->x_flag_omit_frame_pointer
3801 }
3806 else
3809 /* Arrange to set up i386_stack_locals for all functions. */
3812 /* Validate -mregparm= value. */
3814 {
3818 {
3822 }
3823 }
3827 /* Default align_* from the processor table. */
3829 {
3832 }
3834 {
3837 }
3839 {
3841 }
3843 /* Provide default for -mbranch-cost= value. */
3848 {
3849 opts->x_target_flags
3852 /* Enable by default the SSE and MMX builtins. Do allow the user to
3853 explicitly disable any of these. In particular, disabling SSE and
3854 MMX for kernel code is extremely useful. */
3856 opts->x_ix86_isa_flags
3863 }
3864 else
3865 {
3866 opts->x_target_flags
3870 opts->x_ix86_isa_flags
3873 /* i386 ABI does not specify red zone. It still makes sense to use it
3874 when programmer takes care to stack from being destroyed. */
3877 }
3879 /* Keep nonleaf frame pointers. */
3885 /* If we're doing fast math, we don't care about comparison order
3886 wrt NaNs. This lets us use a shorter comparison sequence. */
3890 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3891 since the insns won't need emulation. */
3895 /* Likewise, if the target doesn't have a 387, or we've specified
3896 software floating point, don't use 387 inline intrinsics. */
3900 /* Turn on MMX builtins for -msse. */
3902 opts->x_ix86_isa_flags
3905 /* Enable SSE prefetch. */
3910 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3913 opts->x_ix86_isa_flags
3916 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3919 opts->x_ix86_isa_flags
3922 /* Enable lzcnt instruction for -mabm. */
3924 opts->x_ix86_isa_flags
3927 /* Validate -mpreferred-stack-boundary= value or default it to
3928 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3931 {
3938 {
3942 else
3945 }
3946 else
3947 ix86_preferred_stack_boundary
3949 }
3951 /* Set the default value for -mstackrealign. */
3957 /* Validate -mincoming-stack-boundary= value or default it to
3958 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3961 {
3968 else
3969 {
3970 ix86_user_incoming_stack_boundary
3972 ix86_incoming_stack_boundary
3974 }
3975 }
3977 /* Accept -msseregparm only if at least SSE support is enabled. */
3983 {
3985 {
3987 {
3990 }
3993 {
3996 }
3997 }
3998 }
3999 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4000 fpmath=387. The second is however default at many targets since the
4001 extra 80bit precision of temporaries is considered to be part of ABI.
4002 Overwrite the default at least for -ffast-math.
4003 TODO: -mfpmath=both seems to produce same performing code with bit
4004 smaller binaries. It is however not clear if register allocation is
4005 ready for this setting.
4006 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4007 codegen. We may switch to 387 with -ffast-math for size optimized
4008 functions. */
4012 else
4015 /* If the i387 is disabled, then do not return values in it. */
4019 /* Use external vectorized library in vectorizing intrinsics. */
4022 {
4033 }
4040 /* If stack probes are required, the space used for large function
4041 arguments on the stack must also be probed, so enable
4042 -maccumulate-outgoing-args so this happens in the prologue. */
4045 {
4050 }
4052 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4053 {
4059 }
4061 /* When scheduling description is not available, disable scheduler pass
4062 so it won't slow down the compilation and make x87 code slower. */
4083 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4085 && HAVE_prefetch
4090 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4091 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4096 {
4099 {
4101 ix86_gen_tls_local_dynamic_base_64
4103 }
4104 else
4105 {
4107 ix86_gen_tls_local_dynamic_base_64
4109 }
4110 }
4111 else
4115 {
4125 }
4126 else
4127 {
4137 }
4139 #ifdef USE_IX86_CLD
4140 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4143 #endif
4146 {
4151 }
4153 {
4157 }
4159 {
4160 #if defined(PROFILE_BEFORE_PROLOGUE)
4162 #else
4164 #endif
4165 }
4167 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4168 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4169 AVX unaligned load/store. */
4171 {
4181 /* Enable 128-bit AVX instruction generation
4182 for the auto-vectorizer. */
4186 }
4189 {
4196 {
4199 {
4201 q++;
4202 }
4203 else
4208 else
4209 {
4212 {
4215 }
4218 {
4222 }
4223 }
4228 else
4230 }
4231 }
4238 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4239 for 64-bit Bionic. */
4244 ? MASK_LONG_DOUBLE_128
4247 /* Only one of them can be active. */
4251 /* Save the initial options in case the user does function specific
4252 options. */
4254 target_option_default_node = target_option_current_node
4257 /* Handle stack protector */
4259 opts->x_ix86_stack_protector_guard
4262 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4264 {
4268 }
4271 {
4275 }
4276 }
4278 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4280 static void
4282 {
4284 static struct register_pass_info insert_vzeroupper_info
4287 };
4292 /* This needs to be done at start up. It's convenient to do it here. */
4294 }
4296 /* Update register usage after having seen the compiler flags. */
4298 static void
4300 {
4304 /* The PIC register, if it exists, is fixed. */
4309 /* For 32-bit targets, squash the REX registers. */
4311 {
4318 }
4320 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4328 {
4329 /* Set/reset conditionally defined registers from
4330 CALL_USED_REGISTERS initializer. */
4334 /* Calculate registers of CLOBBERED_REGS register set
4335 as call used registers from GENERAL_REGS register set. */
4339 }
4341 /* If MMX is disabled, squash the registers. */
4347 /* If SSE is disabled, squash the registers. */
4353 /* If the FPU is disabled, squash the registers. */
4359 /* If AVX512F is disabled, squash the registers. */
4361 {
4367 }
4368 }
4370 \f
4371 /* Save the current options */
4373 static void
4376 {
4411 /* The fields are char but the variables are not; make sure the
4412 values fit in the fields. */
4417 }
4419 /* Restore the current options */
4421 static void
4424 {
4430 /* We don't change -fPIC. */
4467 /* Recreate the arch feature tests if the arch changed */
4469 {
4474 }
4476 /* Recreate the tune optimization tests */
4479 }
4481 /* Print the current options */
4483 static void
4486 {
4504 {
4507 }
4508 }
4510 \f
4511 /* Inner function to process the attribute((target(...))), take an argument and
4512 set the current options from the argument. If we have a list, recursively go
4513 over the list. */
4515 static bool
4520 {
4524 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4525 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4526 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4527 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4528 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4530 enum ix86_opt_type
4531 {
4532 ix86_opt_unknown,
4533 ix86_opt_yes,
4534 ix86_opt_no,
4535 ix86_opt_str,
4536 ix86_opt_enum,
4537 ix86_opt_isa
4538 };
4540 static const struct
4541 {
4548 /* isa options */
4597 /* enum options */
4600 /* string options */
4604 /* flag options */
4606 OPT_mcld,
4607 MASK_CLD),
4610 OPT_mfancy_math_387,
4611 MASK_NO_FANCY_MATH_387),
4614 OPT_mieee_fp,
4615 MASK_IEEE_FP),
4618 OPT_minline_all_stringops,
4619 MASK_INLINE_ALL_STRINGOPS),
4622 OPT_minline_stringops_dynamically,
4623 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4626 OPT_mno_align_stringops,
4627 MASK_NO_ALIGN_STRINGOPS),
4630 OPT_mrecip,
4631 MASK_RECIP),
4633 };
4635 /* If this is a list, recurse to get the options. */
4637 {
4644 enum_opts_set))
4648 }
4651 {
4654 }
4656 /* Handle multiple arguments separated by commas. */
4660 {
4674 {
4678 }
4679 else
4680 {
4683 }
4685 /* Recognize no-xxx. */
4687 {
4691 }
4692 else
4695 /* Find the option. */
4699 {
4707 {
4712 }
4713 }
4715 /* Process the option. */
4717 {
4720 }
4723 {
4729 }
4732 {
4738 else
4740 }
4743 {
4745 {
4748 }
4749 else
4751 }
4754 {
4762 global_dc);
4763 else
4764 {
4767 }
4768 }
4770 else
4772 }
4775 }
4777 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4779 tree
4783 {
4798 /* Process each of the options on the chain. */
4803 /* If the changed options are different from the default, rerun
4804 ix86_option_override_internal, and then save the options away.
4805 The string options are are attribute options, and will be undone
4806 when we copy the save structure. */
4812 {
4813 /* If we are using the default tune= or arch=, undo the string assigned,
4814 and use the default. */
4825 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4830 {
4833 }
4835 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4838 /* Add any builtin functions with the new isa if any. */
4841 /* Save the current options unless we are validating options for
4842 #pragma. */
4849 /* Free up memory allocated to hold the strings */
4852 }
4855 }
4857 /* Hook to validate attribute((target("string"))). */
4859 static bool
4862 tree args,
4864 {
4869 /* attribute((target("default"))) does nothing, beyond
4870 affecting multi-versioning. */
4879 /* Get the optimization options of the current function. */
4885 /* Init func_options. */
4893 /* Initialize func_options to the default before its target options can
4894 be set. */
4907 {
4912 }
4915 }
4917 \f
4918 /* Hook to determine if one function can safely inline another. */
4920 static bool
4922 {
4927 /* If callee has no option attributes, then it is ok to inline. */
4931 /* If caller has no option attributes, but callee does then it is not ok to
4932 inline. */
4936 else
4937 {
4941 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4942 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4943 function. */
4948 /* See if we have the same non-isa options. */
4952 /* See if arch, tune, etc. are the same. */
4965 else
4967 }
4970 }
4972 \f
4973 /* Remember the last target of ix86_set_current_function. */
4976 /* Invalidate ix86_previous_fndecl cache. */
4977 void
4979 {
4981 }
4983 /* Establish appropriate back-end context for processing the function
4984 FNDECL. The argument might be NULL to indicate processing at top
4985 level, outside of any function scope. */
4986 static void
4988 {
4989 /* Only change the context if the function changes. This hook is called
4990 several times in the course of compiling a function, and we don't want to
4991 slow things down too much or call target_reinit when it isn't safe. */
4993 {
4994 tree old_tree = (ix86_previous_fndecl
4998 tree new_tree = (fndecl
5004 ;
5007 {
5012 else
5015 }
5018 {
5026 else
5029 }
5030 }
5031 }
5033 \f
5034 /* Return true if this goes in large data/bss. */
5036 static bool
5038 {
5042 /* Functions are never large data. */
5047 {
5053 }
5054 else
5055 {
5058 /* If this is an incomplete type with size 0, then we can't put it
5059 in data because it might be too big when completed. Also,
5060 int_size_in_bytes returns -1 if size can vary or is larger than
5061 an integer in which case also it is safer to assume that it goes in
5062 large data. */
5065 }
5068 }
5070 /* Switch to the appropriate section for output of DECL.
5071 DECL is either a `VAR_DECL' node or a constant of some sort.
5072 RELOC indicates whether forming the initial value of DECL requires
5073 link-time relocations. */
5078 {
5081 {
5085 {
5119 /* We don't split these for medium model. Place them into
5120 default sections and hope for best. */
5122 }
5124 {
5125 /* We might get called with string constants, but get_named_section
5126 doesn't like them as they are not DECLs. Also, we need to set
5127 flags in that case. */
5131 }
5132 }
5134 }
5136 /* Select a set of attributes for section NAME based on the properties
5137 of DECL and whether or not RELOC indicates that DECL's initializer
5138 might contain runtime relocations. */
5140 static unsigned int ATTRIBUTE_UNUSED
5142 {
5156 }
5158 /* Build up a unique section name, expressed as a
5159 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5160 RELOC indicates whether the initial value of EXP requires
5161 link-time relocations. */
5163 static void ATTRIBUTE_UNUSED
5165 {
5168 {
5170 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5174 {
5198 /* We don't split these for medium model. Place them into
5199 default sections and hope for best. */
5201 }
5203 {
5210 /* If we're using one_only, then there needs to be a .gnu.linkonce
5211 prefix to the section name. */
5218 }
5219 }
5221 }
5223 #ifdef COMMON_ASM_OP
5224 /* This says how to output assembler code to declare an
5225 uninitialized external linkage data object.
5227 For medium model x86-64 we need to use .largecomm opcode for
5228 large objects. */
5229 void
5233 {
5237 else
5242 }
5243 #endif
5245 /* Utility function for targets to use in implementing
5246 ASM_OUTPUT_ALIGNED_BSS. */
5248 void
5251 {
5255 else
5258 #ifdef ASM_DECLARE_OBJECT_NAME
5261 #else
5262 /* Standard thing is just output label for the object. */
5266 }
5267 \f
5268 /* Decide whether we must probe the stack before any space allocation
5269 on this target. It's essentially TARGET_STACK_PROBE except when
5270 -fstack-check causes the stack to be already probed differently. */
5272 bool
5274 {
5275 /* Do not probe the stack twice if static stack checking is enabled. */
5280 }
5281 \f
5282 /* Decide whether we can make a sibling call to a function. DECL is the
5283 declaration of the function being targeted by the call and EXP is the
5284 CALL_EXPR representing the call. */
5286 static bool
5288 {
5292 /* If we are generating position-independent code, we cannot sibcall
5293 optimize any indirect call, or a direct call to a global function,
5294 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5296 && !TARGET_64BIT
5297 && flag_pic
5301 /* If we need to align the outgoing stack, then sibcalling would
5302 unalign the stack, which may break the called function. */
5308 {
5311 }
5312 else
5313 {
5314 /* We're looking at the CALL_EXPR, we need the type of the function. */
5319 }
5321 /* Check that the return value locations are the same. Like
5322 if we are returning floats on the 80387 register stack, we cannot
5323 make a sibcall from a function that doesn't return a float to a
5324 function that does or, conversely, from a function that does return
5325 a float to a function that doesn't; the necessary stack adjustment
5326 would not be executed. This is also the place we notice
5327 differences in the return value ABI. Note that it is ok for one
5328 of the functions to have void return type as long as the return
5329 value of the other is passed in a register. */
5334 {
5337 }
5339 ;
5344 {
5345 /* The SYSV ABI has more call-clobbered registers;
5346 disallow sibcalls from MS to SYSV. */
5350 }
5351 else
5352 {
5353 /* If this call is indirect, we'll need to be able to use a
5354 call-clobbered register for the address of the target function.
5355 Make sure that all such registers are not used for passing
5356 parameters. Note that DLLIMPORT functions are indirect. */
5359 {
5361 {
5362 /* ??? Need to count the actual number of registers to be used,
5363 not the possible number of registers. Fix later. */
5365 }
5366 }
5367 }
5369 /* Otherwise okay. That also includes certain types of indirect calls. */
5371 }
5373 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5374 and "sseregparm" calling convention attributes;
5375 arguments as in struct attribute_spec.handler. */
5377 static tree
5379 tree args,
5382 {
5387 {
5389 name);
5392 }
5394 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5396 {
5397 tree cst;
5400 {
5402 }
5405 {
5407 }
5411 {
5414 name);
5416 }
5418 {
5422 }
5425 }
5428 {
5429 /* Do not warn when emulating the MS ABI. */
5434 name);
5437 }
5439 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5441 {
5443 {
5445 }
5447 {
5449 }
5451 {
5453 }
5455 {
5457 }
5458 }
5460 /* Can combine stdcall with fastcall (redundant), regparm and
5461 sseregparm. */
5463 {
5465 {
5467 }
5469 {
5471 }
5473 {
5475 }
5476 }
5478 /* Can combine cdecl with regparm and sseregparm. */
5480 {
5482 {
5484 }
5486 {
5488 }
5490 {
5492 }
5493 }
5495 {
5498 name);
5500 {
5502 }
5504 {
5506 }
5508 {
5510 }
5511 }
5513 /* Can combine sseregparm with all attributes. */
5516 }
5518 /* The transactional memory builtins are implicitly regparm or fastcall
5519 depending on the ABI. Override the generic do-nothing attribute that
5520 these builtins were declared with, and replace it with one of the two
5521 attributes that we expect elsewhere. */
5523 static tree
5526 {
5527 tree alt;
5529 /* In no case do we want to add the placeholder attribute. */
5532 /* The 64-bit ABI is unchanged for transactional memory. */
5536 /* ??? Is there a better way to validate 32-bit windows? We have
5537 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5540 else
5541 {
5544 }
5548 }
5550 /* This function determines from TYPE the calling-convention. */
5552 unsigned int
5554 {
5557 tree attrs;
5564 {
5574 /* Regparam isn't allowed for thiscall and fastcall. */
5576 {
5581 }
5585 }
5592 || is_stdarg
5598 }
5600 /* Return 0 if the attributes for two types are incompatible, 1 if they
5601 are compatible, and 2 if they are nearly compatible (which causes a
5602 warning to be generated). */
5604 static int
5606 {
5622 }
5623 \f
5624 /* Return the regparm value for a function with the indicated TYPE and DECL.
5625 DECL may be NULL when calling function indirectly
5626 or considering a libcall. */
5628 static int
5630 {
5631 tree attr;
5642 {
5645 {
5648 }
5649 }
5655 /* Use register calling convention for local functions when possible. */
5658 /* Caller and callee must agree on the calling convention, so
5659 checking here just optimize means that with
5660 __attribute__((optimize (...))) caller could use regparm convention
5661 and callee not, or vice versa. Instead look at whether the callee
5662 is optimized or not. */
5665 {
5666 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5669 {
5672 /* Make sure no regparm register is taken by a
5673 fixed register variable. */
5678 /* We don't want to use regparm(3) for nested functions as
5679 these use a static chain pointer in the third argument. */
5683 /* In 32-bit mode save a register for the split stack. */
5687 /* Each fixed register usage increases register pressure,
5688 so less registers should be used for argument passing.
5689 This functionality can be overriden by an explicit
5690 regparm value. */
5693 globals++;
5695 local_regparm
5700 }
5701 }
5704 }
5706 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5707 DFmode (2) arguments in SSE registers for a function with the
5708 indicated TYPE and DECL. DECL may be NULL when calling function
5709 indirectly or considering a libcall. Otherwise return 0. */
5711 static int
5713 {
5716 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5717 by the sseregparm attribute. */
5720 {
5722 {
5724 {
5728 else
5731 }
5733 }
5736 }
5738 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5739 (and DFmode for SSE2) arguments in SSE registers. */
5742 {
5743 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5747 }
5750 }
5752 /* Return true if EAX is live at the start of the function. Used by
5753 ix86_expand_prologue to determine if we need special help before
5754 calling allocate_stack_worker. */
5756 static bool
5758 {
5759 /* Cheat. Don't bother working forward from ix86_function_regparm
5760 to the function type to whether an actual argument is located in
5761 eax. Instead just look at cfg info, which is still close enough
5762 to correct at this point. This gives false positives for broken
5763 functions that might use uninitialized data that happens to be
5764 allocated in eax, but who cares? */
5766 }
5768 static bool
5770 {
5771 tree attr;
5774 {
5780 /* For 32-bit MS-ABI the default is to keep aggregate
5781 return pointer. */
5784 }
5786 }
5788 /* Value is the number of bytes of arguments automatically
5789 popped when returning from a subroutine call.
5790 FUNDECL is the declaration node of the function (as a tree),
5791 FUNTYPE is the data type of the function (as a tree),
5792 or for a library call it is an identifier node for the subroutine name.
5793 SIZE is the number of bytes of arguments passed on the stack.
5795 On the 80386, the RTD insn may be used to pop them if the number
5796 of args is fixed, but if the number is variable then the caller
5797 must pop them all. RTD can't be used for library calls now
5798 because the library is compiled with the Unix compiler.
5799 Use of RTD is a selectable option, since it is incompatible with
5800 standard Unix calling sequences. If the option is not selected,
5801 the caller must always pop the args.
5803 The attribute stdcall is equivalent to RTD on a per module basis. */
5805 static int
5807 {
5810 /* None of the 64-bit ABIs pop arguments. */
5821 /* Lose any fake structure return argument if it is passed on the stack. */
5824 {
5828 }
5831 }
5833 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5835 static bool
5837 {
5838 /* Check operand constraints in case hard registers were propagated
5839 into insn pattern. This check prevents combine pass from
5840 generating insn patterns with invalid hard register operands.
5841 These invalid insns can eventually confuse reload to error out
5842 with a spill failure. See also PRs 46829 and 46843. */
5844 {
5853 {
5861 /* For pre-AVX disallow unaligned loads/stores where the
5862 instructions don't support it. */
5866 {
5870 }
5872 /* A unary operator may be accepted by the predicate, but it
5873 is irrelevant for matching constraints. */
5878 {
5886 }
5893 /* Operand has no constraints, anything is OK. */
5898 {
5903 && operands_match_p
5907 {
5910 }
5911 }
5915 }
5916 }
5919 }
5920 \f
5921 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5923 static unsigned HOST_WIDE_INT
5925 {
5929 }
5930 \f
5931 /* Argument support functions. */
5933 /* Return true when register may be used to pass function parameters. */
5934 bool
5936 {
5941 {
5945 else
5951 }
5957 /* TODO: The function should depend on current function ABI but
5958 builtins.c would need updating then. Therefore we use the
5959 default ABI. */
5961 /* RAX is used as hidden argument to va_arg functions. */
5967 else
5974 }
5976 /* Return if we do not know how to pass TYPE solely in registers. */
5978 static bool
5980 {
5984 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5985 The layout_type routine is crafty and tries to trick us into passing
5986 currently unsupported vector types on the stack by using TImode. */
5989 }
5991 /* It returns the size, in bytes, of the area reserved for arguments passed
5992 in registers for the function represented by fndecl dependent to the used
5993 abi format. */
5994 int
5996 {
6000 else
6005 }
6007 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6008 call abi used. */
6009 enum calling_abi
6011 {
6013 {
6016 {
6019 }
6023 }
6025 }
6027 /* We add this as a workaround in order to use libc_has_function
6028 hook in i386.md. */
6029 bool
6031 {
6033 }
6035 static bool
6037 {
6039 {
6043 else
6045 }
6047 }
6049 static enum calling_abi
6051 {
6055 }
6057 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6058 call abi used. */
6059 enum calling_abi
6061 {
6065 }
6067 /* Write the extra assembler code needed to declare a function properly. */
6069 void
6071 tree decl)
6072 {
6076 {
6082 }
6084 #ifdef SUBTARGET_ASM_UNWIND_INIT
6086 #endif
6090 /* Output magic byte marker, if hot-patch attribute is set. */
6092 {
6094 {
6095 /* leaq [%rsp + 0], %rsp */
6098 }
6099 else
6100 {
6101 /* movl.s %edi, %edi
6102 push %ebp
6103 movl.s %esp, %ebp */
6106 }
6107 }
6108 }
6110 /* regclass.c */
6113 /* Implementation of call abi switching target hook. Specific to FNDECL
6114 the specific call register sets are set. See also
6115 ix86_conditional_register_usage for more details. */
6116 void
6118 {
6121 else
6123 }
6125 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6126 expensive re-initialization of init_regs each time we switch function context
6127 since this is needed only during RTL expansion. */
6128 static void
6130 {
6134 }
6136 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6137 for a call to a function whose data type is FNTYPE.
6138 For a library call, FNTYPE is 0. */
6140 void
6144 tree fndecl,
6146 {
6152 {
6155 }
6156 else
6157 {
6160 }
6164 /* Set up the number of registers to use for passing arguments. */
6167 {
6169 ? X86_64_REGPARM_MAX
6171 }
6173 {
6176 {
6178 ? X86_64_SSE_REGPARM_MAX
6180 }
6181 }
6189 /* Because type might mismatch in between caller and callee, we need to
6190 use actual type of function for local calls.
6191 FIXME: cgraph_analyze can be told to actually record if function uses
6192 va_start so for local functions maybe_vaarg can be made aggressive
6193 helping K&R code.
6194 FIXME: once typesytem is fixed, we won't need this code anymore. */
6202 {
6203 /* If there are variable arguments, then we won't pass anything
6204 in registers in 32-bit mode. */
6206 {
6215 }
6217 /* Use ecx and edx registers if function has fastcall attribute,
6218 else look for regparm information. */
6220 {
6223 {
6226 }
6228 {
6231 }
6232 else
6234 }
6236 /* Set up the number of SSE registers used for passing SFmode
6237 and DFmode arguments. Warn for mismatching ABI. */
6239 }
6240 }
6242 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6243 But in the case of vector types, it is some vector mode.
6245 When we have only some of our vector isa extensions enabled, then there
6246 are some modes for which vector_mode_supported_p is false. For these
6247 modes, the generic vector support in gcc will choose some non-vector mode
6248 in order to implement the type. By computing the natural mode, we'll
6249 select the proper ABI location for the operand and not depend on whatever
6250 the middle-end decides to do with these vector types.
6252 The midde-end can't deal with the vector types > 16 bytes. In this
6253 case, we return the original mode and warn ABI change if CUM isn't
6254 NULL.
6256 If INT_RETURN is true, warn ABI change if the vector mode isn't
6257 available for function return value. */
6259 static enum machine_mode
6262 {
6266 {
6269 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6271 {
6276 else
6279 /* Get the mode which has this inner mode and number of units. */
6283 {
6285 {
6290 {
6294 }
6296 {
6300 }
6303 }
6305 {
6310 {
6314 }
6316 {
6320 }
6323 }
6326 {
6331 {
6335 }
6337 {
6341 }
6342 }
6344 {
6349 {
6353 }
6355 {
6359 }
6360 }
6362 }
6365 }
6366 }
6369 }
6371 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6372 this may not agree with the mode that the type system has chosen for the
6373 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6374 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6376 static rtx
6379 {
6380 rtx tmp;
6384 else
6385 {
6389 }
6392 }
6394 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6395 of this code is to classify each 8bytes of incoming argument by the register
6396 class and assign registers accordingly. */
6398 /* Return the union class of CLASS1 and CLASS2.
6399 See the x86-64 PS ABI for details. */
6401 static enum x86_64_reg_class
6403 {
6404 /* Rule #1: If both classes are equal, this is the resulting class. */
6408 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6409 the other class. */
6415 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6419 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6427 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6428 MEMORY is used. */
6437 /* Rule #6: Otherwise class SSE is used. */
6439 }
6441 /* Classify the argument of type TYPE and mode MODE.
6442 CLASSES will be filled by the register class used to pass each word
6443 of the operand. The number of words is returned. In case the parameter
6444 should be passed in memory, 0 is returned. As a special case for zero
6445 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6447 BIT_OFFSET is used internally for handling records and specifies offset
6448 of the offset in bits modulo 512 to avoid overflow cases.
6450 See the x86-64 PS ABI for details.
6451 */
6453 static int
6456 {
6457 HOST_WIDE_INT bytes =
6459 int words
6462 /* Variable sized entities are always passed/returned in memory. */
6470 /* Special case check for pointer to shared, on 64-bit target. */
6474 {
6477 }
6480 {
6482 tree field;
6485 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6492 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6493 signalize memory class, so handle it as special case. */
6495 {
6498 }
6500 /* Classify each field of record and merge classes. */
6502 {
6504 /* And now merge the fields of structure. */
6506 {
6508 {
6514 /* Bitfields are always classified as integer. Handle them
6515 early, since later code would consider them to be
6516 misaligned integers. */
6518 {
6527 }
6528 else
6529 {
6534 /* Flexible array member is ignored. */
6541 {
6545 {
6548 "the ABI of passing struct with"
6549 " a flexible array member has"
6551 }
6553 }
6555 subclasses,
6565 }
6566 }
6567 }
6571 /* Arrays are handled as small records. */
6572 {
6579 /* The partial classes are now full classes. */
6590 }
6593 /* Unions are similar to RECORD_TYPE but offset is always 0.
6594 */
6596 {
6598 {
6606 bit_offset);
6611 }
6612 }
6617 }
6620 {
6621 /* When size > 16 bytes, if the first one isn't
6622 X86_64_SSE_CLASS or any other ones aren't
6623 X86_64_SSEUP_CLASS, everything should be passed in
6624 memory. */
6631 }
6633 /* Final merger cleanup. */
6635 {
6636 /* If one class is MEMORY, everything should be passed in
6637 memory. */
6641 /* The X86_64_SSEUP_CLASS should be always preceded by
6642 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6646 {
6647 /* The first one should never be X86_64_SSEUP_CLASS. */
6650 }
6652 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6653 everything should be passed in memory. */
6656 {
6659 /* The first one should never be X86_64_X87UP_CLASS. */
6662 {
6665 "the ABI of passing union with long double"
6667 }
6669 }
6670 }
6672 }
6674 /* Compute alignment needed. We align all types to natural boundaries with
6675 exception of XFmode that is aligned to 64bits. */
6677 {
6686 /* Misaligned fields are always returned in memory. */
6689 }
6691 /* for V1xx modes, just use the base mode */
6696 /* Classification of atomic types. */
6698 {
6714 {
6717 /* Analyze last 128 bits only. */
6721 {
6724 }
6726 {
6729 }
6731 {
6735 }
6737 {
6740 }
6741 else
6743 }
6750 /* OImode shouldn't be used directly. */
6757 else
6775 else
6776 {
6780 {
6783 "the ABI of passing structure with complex float"
6785 }
6788 }
6797 /* This modes is larger than 16 bytes. */
6855 else
6859 }
6860 }
6862 /* Examine the argument and return set number of register required in each
6863 class. Return true iff parameter should be passed in memory. */
6865 static bool
6868 {
6879 {
6900 }
6903 }
6905 /* Construct container for the argument used by GCC interface. See
6906 FUNCTION_ARG for the detailed description. */
6908 static rtx
6912 {
6913 /* The following variables hold the static issued_error state. */
6927 rtx ret;
6938 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6939 some less clueful developer tries to use floating-point anyway. */
6941 {
6943 {
6945 {
6948 }
6949 }
6951 {
6954 }
6956 }
6958 /* Likewise, error if the ABI requires us to return values in the
6959 x87 registers and the user specified -mno-80387. */
6965 {
6967 {
6970 }
6972 }
6974 /* First construct simple cases. Avoid SCmode, since we want to use
6975 single register to pass this type. */
6978 {
6993 /* Zero sized array, struct or class. */
6997 }
7036 /* Otherwise figure out the entries of the PARALLEL. */
7038 {
7042 {
7047 /* Merge TImodes on aligned occasions here too. */
7049 tmpmode
7053 else
7055 /* We've requested 24 bytes we
7056 don't have mode for. Use DImode. */
7063 intreg++;
7071 sse_regno++;
7079 sse_regno++;
7084 {
7090 {
7092 i++;
7093 }
7094 else
7119 }
7125 sse_regno++;
7129 }
7130 }
7132 /* Empty aligned struct, union or class. */
7140 }
7142 /* Update the data in CUM to advance over an argument of mode MODE
7143 and data type TYPE. (TYPE is null for libcalls where that information
7144 may not be available.) */
7146 static void
7149 HOST_WIDE_INT words)
7150 {
7152 {
7159 /* FALLTHRU */
7170 {
7173 }
7177 /* OImode shouldn't be used directly. */
7186 /* FALLTHRU */
7208 {
7213 {
7216 }
7217 }
7227 {
7232 {
7235 }
7236 }
7238 }
7239 }
7241 static void
7244 {
7247 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7254 {
7259 }
7260 else
7261 {
7265 }
7266 }
7268 static void
7270 HOST_WIDE_INT words)
7271 {
7272 /* Otherwise, this should be passed indirect. */
7277 {
7280 }
7281 }
7283 /* Update the data in CUM to advance over an argument of mode MODE and
7284 data type TYPE. (TYPE is null for libcalls where that information
7285 may not be available.) */
7287 static void
7290 {
7296 else
7307 else
7309 }
7311 /* Define where to put the arguments to a function.
7312 Value is zero to push the argument on the stack,
7313 or a hard register in which to store the argument.
7315 MODE is the argument's machine mode.
7316 TYPE is the data type of the argument (as a tree).
7317 This is null for libcalls where that information may
7318 not be available.
7319 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7320 the preceding args and about the function being called.
7321 NAMED is nonzero if this argument is a named parameter
7322 (otherwise it is an extra parameter matching an ellipsis). */
7324 static rtx
7328 {
7329 /* Avoid the AL settings for the Unix64 ABI. */
7334 {
7341 /* FALLTHRU */
7347 {
7350 /* Fastcall allocates the first two DWORD (SImode) or
7351 smaller arguments to ECX and EDX if it isn't an
7352 aggregate type . */
7354 {
7360 /* ECX not EAX is the first allocated register. */
7363 }
7365 }
7374 /* FALLTHRU */
7376 /* In 32bit, we pass TImode in xmm registers. */
7384 {
7388 }
7393 /* OImode and XImode shouldn't be used directly. */
7409 {
7413 }
7423 {
7427 }
7429 }
7432 }
7434 static rtx
7437 {
7438 /* Handle a hidden AL argument containing number of registers
7439 for varargs x86-64 functions. */
7443 ? X86_64_SSE_REGPARM_MAX
7448 {
7464 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7468 }
7474 }
7476 static rtx
7479 HOST_WIDE_INT bytes)
7480 {
7483 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7484 We use value of -2 to specify that current function call is MSABI. */
7488 /* If we've run out of registers, it goes on the stack. */
7494 /* Only floating point modes are passed in anything but integer regs. */
7496 {
7499 else
7500 {
7503 /* Unnamed floating parameters are passed in both the
7504 SSE and integer registers. */
7510 }
7511 }
7512 /* Handle aggregated types passed in register. */
7514 {
7519 }
7522 }
7524 /* Return where to put the arguments to a function.
7525 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7527 MODE is the argument's machine mode. TYPE is the data type of the
7528 argument. It is null for libcalls where that information may not be
7529 available. CUM gives information about the preceding args and about
7530 the function being called. NAMED is nonzero if this argument is a
7531 named parameter (otherwise it is an extra parameter matching an
7532 ellipsis). */
7534 static rtx
7537 {
7541 rtx arg;
7545 else
7549 /* To simplify the code below, represent vector types with a vector mode
7550 even if MMX/SSE are not active. */
7558 else
7562 }
7564 /* A C expression that indicates when an argument must be passed by
7565 reference. If nonzero for an argument, a copy of that argument is
7566 made in memory and a pointer to the argument is passed instead of
7567 the argument itself. The pointer is passed in whatever way is
7568 appropriate for passing a pointer to that type. */
7570 static bool
7573 {
7576 /* See Windows x64 Software Convention. */
7578 {
7581 {
7582 /* Arrays are passed by reference. */
7587 {
7588 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7589 are passed by reference. */
7591 }
7592 }
7594 /* __m128 is passed by reference. */
7600 }
7601 }
7606 }
7608 /* Return true when TYPE should be 128bit aligned for 32bit argument
7609 passing ABI. XXX: This function is obsolete and is only used for
7610 checking psABI compatibility with previous versions of GCC. */
7612 static bool
7614 {
7626 {
7627 /* Walk the aggregates recursively. */
7629 {
7633 {
7634 tree field;
7636 /* Walk all the structure fields. */
7638 {
7642 }
7644 }
7647 /* Just for use if some languages passes arrays by value. */
7654 }
7655 }
7657 }
7659 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7660 XXX: This function is obsolete and is only used for checking psABI
7661 compatibility with previous versions of GCC. */
7663 static unsigned int
7666 {
7667 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7668 natural boundaries. */
7670 {
7671 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7672 make an exception for SSE modes since these require 128bit
7673 alignment.
7675 The handling here differs from field_alignment. ICC aligns MMX
7676 arguments to 4 byte boundaries, while structure fields are aligned
7677 to 8 byte boundaries. */
7679 {
7682 }
7683 else
7684 {
7687 }
7688 }
7692 }
7694 /* Return true when TYPE should be 128bit aligned for 32bit argument
7695 passing ABI. */
7697 static bool
7699 {
7709 {
7710 /* Walk the aggregates recursively. */
7712 {
7716 {
7717 tree field;
7719 /* Walk all the structure fields. */
7721 field;
7723 {
7727 }
7729 }
7732 /* Just for use if some languages passes arrays by value. */
7739 }
7740 }
7741 else
7745 }
7747 /* Gives the alignment boundary, in bits, of an argument with the
7748 specified mode and type. */
7750 static unsigned int
7752 {
7755 {
7756 /* Since the main variant type is used for call, we convert it to
7757 the main variant type. */
7760 }
7761 else
7765 else
7766 {
7771 {
7772 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7774 {
7777 }
7783 }
7786 && !warned
7788 saved_align))
7789 {
7792 "The ABI for passing parameters with %d-byte"
7795 }
7796 }
7799 }
7801 /* Return true if N is a possible register number of function value. */
7803 static bool
7805 {
7807 {
7816 /* Complex values are returned in %st(0)/%st(1) pair. */
7819 /* TODO: The function should depend on current function ABI but
7820 builtins.c would need updating then. Therefore we use the
7821 default ABI. */
7826 /* Complex values are returned in %xmm0/%xmm1 pair. */
7835 }
7838 }
7840 /* Define how to find the value returned by a function.
7841 VALTYPE is the data type of the value (as a tree).
7842 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7843 otherwise, FUNC is 0. */
7845 static rtx
7848 {
7851 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7852 we normally prevent this case when mmx is not available. However
7853 some ABIs may require the result to be returned like DImode. */
7857 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7858 we prevent this case when sse is not available. However some ABIs
7859 may require the result to be returned like integer TImode. */
7864 /* 32-byte vector modes in %ymm0. */
7868 /* 64-byte vector modes in %zmm0. */
7872 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7875 else
7876 /* Most things go in %eax. */
7879 /* Override FP return register with %xmm0 for local functions when
7880 SSE math is enabled or for functions with sseregparm attribute. */
7882 {
7887 }
7889 /* OImode shouldn't be used directly. */
7893 }
7895 static rtx
7897 const_tree valtype)
7898 {
7899 rtx ret;
7901 /* Handle libcalls, which don't provide a type node. */
7903 {
7907 {
7926 }
7929 }
7932 {
7933 /* Pointers are always returned in word_mode. */
7935 }
7941 /* For zero sized structures, construct_container returns NULL, but we
7942 need to keep rest of compiler happy by returning meaningful value. */
7947 }
7949 static rtx
7951 const_tree valtype)
7952 {
7956 {
7958 {
7977 }
7978 }
7980 }
7982 static rtx
7985 {
7997 else
7999 }
8001 static rtx
8003 {
8009 }
8011 /* Pointer function arguments and return values are promoted to
8012 word_mode. */
8014 static enum machine_mode
8018 {
8020 {
8022 {
8025 }
8028 }
8030 for_return);
8031 }
8033 /* Return true if a structure, union or array with MODE containing FIELD
8034 should be accessed using BLKmode. */
8036 static bool
8038 {
8039 /* Union with XFmode must be in BLKmode. */
8043 }
8045 rtx
8047 {
8049 }
8051 /* Return true iff type is returned in memory. */
8053 static bool
8055 {
8056 #ifdef SUBTARGET_RETURN_IN_MEMORY
8058 #else
8060 HOST_WIDE_INT size;
8063 {
8065 {
8068 /* __m128 is returned in xmm0. */
8077 /* Otherwise, the size must be exactly in [1248]. */
8079 }
8080 else
8081 {
8086 }
8087 }
8088 else
8089 {
8099 {
8100 /* User-created vectors small enough to fit in EAX. */
8104 /* Unless ABI prescibes otherwise,
8105 MMX/3dNow values are returned in MM0 if available. */
8110 /* SSE values are returned in XMM0 if available. */
8114 /* AVX values are returned in YMM0 if available. */
8118 /* AVX512F values are returned in ZMM0 if available. */
8121 }
8129 /* OImode shouldn't be used directly. */
8133 }
8134 #endif
8135 }
8137 \f
8138 /* Create the va_list data type. */
8140 /* Returns the calling convention specific va_list date type.
8141 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8143 static tree
8145 {
8148 /* For i386 we use plain pointer to argument area. */
8158 unsigned_type_node);
8161 unsigned_type_node);
8164 ptr_type_node);
8167 ptr_type_node);
8186 /* The correct type is an array type of one element. */
8188 }
8190 /* Setup the builtin va_list data type and for 64-bit the additional
8191 calling convention specific va_list data types. */
8193 static tree
8195 {
8198 /* Initialize abi specific va_list builtin types. */
8200 {
8201 tree t;
8203 {
8208 }
8209 else
8210 {
8215 }
8217 {
8222 }
8223 else
8224 {
8229 }
8230 }
8233 }
8235 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8237 static void
8239 {
8241 alias_set_type set;
8244 /* GPR size of varargs save area. */
8247 else
8250 /* FPR size of varargs save area. We don't need it if we don't pass
8251 anything in SSE registers. */
8254 else
8268 {
8276 }
8279 {
8282 rtx test;
8284 /* Now emit code to save SSE registers. The AX parameter contains number
8285 of SSE parameter registers used to call this function, though all we
8286 actually check here is the zero/non-zero status. */
8291 label));
8293 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8294 we used movdqa (i.e. TImode) instead? Perhaps even better would
8295 be if we could determine the real mode of the data, via a hook
8296 into pass_stdarg. Ignore all that for now. */
8306 {
8315 }
8318 }
8319 }
8321 static void
8323 {
8327 /* Reset to zero, as there might be a sysv vaarg used
8328 before. */
8333 {
8344 }
8345 }
8347 static void
8350 {
8352 CUMULATIVE_ARGS next_cum;
8353 tree fntype;
8355 /* This argument doesn't appear to be used anymore. Which is good,
8356 because the old code here didn't suppress rtl generation. */
8364 /* For varargs, we do not want to skip the dummy va_dcl argument.
8365 For stdargs, we do want to skip the last named argument. */
8373 else
8375 }
8377 /* Checks if TYPE is of kind va_list char *. */
8379 static bool
8381 {
8382 tree canonic;
8384 /* For 32-bit it is always true. */
8390 }
8392 /* Implement va_start. */
8394 static void
8396 {
8400 tree type;
8401 rtx ovf_rtx;
8405 {
8408 /* When we are splitting the stack, we can't refer to the stack
8409 arguments using internal_arg_pointer, because they may be on
8410 the old stack. The split stack prologue will arrange to
8411 leave a pointer to the old stack arguments in a scratch
8412 register, which we here copy to a pseudo-register. The split
8413 stack prologue can't set the pseudo-register directly because
8414 it (the prologue) runs before any registers have been saved. */
8418 {
8419 rtx reg;
8433 }
8434 }
8436 /* Only 64bit target needs something special. */
8438 {
8441 else
8442 {
8451 }
8453 }
8462 /* The following should be folded into the MEM_REF offset. */
8472 /* Count number of gp and fp argument registers used. */
8478 {
8484 }
8487 {
8493 }
8495 /* Find the overflow area. */
8499 else
8509 {
8510 /* Find the register save area.
8511 Prologue of the function save it right above stack frame. */
8519 }
8520 }
8522 /* Implement va_arg. */
8524 static tree
8527 {
8534 rtx container;
8536 tree ptrtype;
8540 /* Only 64bit target needs something special. */
8564 {
8577 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8579 {
8582 }
8590 }
8592 /* Pull the value out of the saved registers. */
8597 {
8611 /* In case we are passing structure, verify that it is consecutive block
8612 on the register save area. If not we need to do moves. */
8614 {
8615 /* Verify that all registers are strictly consecutive */
8617 {
8621 {
8626 }
8627 }
8628 else
8629 {
8633 {
8638 }
8639 }
8640 }
8642 {
8645 }
8646 else
8647 {
8650 }
8652 /* First ensure that we fit completely in registers. */
8654 {
8661 }
8663 {
8671 }
8673 /* Compute index to start of area used for integer regs. */
8675 {
8676 /* int_addr = gpr + sav; */
8679 }
8681 {
8682 /* sse_addr = fpr + sav; */
8685 }
8687 {
8691 /* addr = &temp; */
8696 {
8700 tree piece_type;
8701 tree addr_type;
8702 tree daddr_type;
8711 {
8716 }
8720 else
8727 {
8730 }
8731 else
8732 {
8735 }
8742 {
8747 }
8748 else
8749 {
8750 tree copy
8755 }
8757 }
8758 }
8761 {
8765 }
8768 {
8772 }
8777 }
8779 /* ... otherwise out of the overflow area. */
8781 /* When we align parameter on stack for caller, if the parameter
8782 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8783 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8784 here with caller. */
8789 /* Care for on-stack alignment if needed. */
8792 else
8793 {
8798 }
8815 }
8816 \f
8817 /* Return true if OPNUM's MEM should be matched
8818 in movabs* patterns. */
8820 bool
8822 {
8834 }
8835 \f
8836 /* Initialize the table of extra 80387 mathematical constants. */
8838 static void
8840 {
8842 {
8848 };
8852 {
8854 /* Ensure each constant is rounded to XFmode precision. */
8857 }
8860 }
8862 /* Return non-zero if the constant is something that
8863 can be loaded with a special instruction. */
8865 int
8867 {
8870 REAL_VALUE_TYPE r;
8882 /* For XFmode constants, try to find a special 80387 instruction when
8883 optimizing for size or on those CPUs that benefit from them. */
8886 {
8895 }
8897 /* Load of the constant -0.0 or -1.0 will be split as
8898 fldz;fchs or fld1;fchs sequence. */
8905 }
8907 /* Return the opcode of the special instruction to be used to load
8908 the constant X. */
8912 {
8914 {
8934 }
8935 }
8937 /* Return the CONST_DOUBLE representing the 80387 constant that is
8938 loaded by the specified special instruction. The argument IDX
8939 matches the return value from standard_80387_constant_p. */
8941 rtx
8943 {
8950 {
8961 }
8964 XFmode);
8965 }
8967 /* Return 1 if X is all 0s and 2 if x is all 1s
8968 in supported SSE/AVX vector mode. */
8970 int
8972 {
8979 {
9000 }
9003 }
9005 /* Return the opcode of the special instruction to be used to load
9006 the constant X. */
9010 {
9012 {
9015 {
9042 }
9052 else
9057 }
9059 }
9061 /* Returns true if OP contains a symbol reference */
9063 bool
9065 {
9074 {
9076 {
9082 }
9086 }
9089 }
9091 /* Return true if it is appropriate to emit `ret' instructions in the
9092 body of a function. Do this only if the epilogue is simple, needing a
9093 couple of insns. Prior to reloading, we can't tell how many registers
9094 must be saved, so return false then. Return false if there is no frame
9095 marker to de-allocate. */
9097 bool
9099 {
9105 /* Don't allow more than 32k pop, since that's all we can do
9106 with one instruction. */
9113 }
9114 \f
9115 /* Value should be nonzero if functions must have frame pointers.
9116 Zero means the frame pointer need not be set up (and parms may
9117 be accessed via the stack pointer) in functions that seem suitable. */
9119 static bool
9121 {
9122 /* If we accessed previous frames, then the generated code expects
9123 to be able to access the saved ebp value in our frame. */
9127 /* Several x86 os'es need a frame pointer for other reasons,
9128 usually pertaining to setjmp. */
9132 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9136 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9137 allocation is 4GB. */
9141 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9142 turns off the frame pointer by default. Turn it back on now if
9143 we've not got a leaf function. */
9153 }
9155 /* Record that the current function accesses previous call frames. */
9157 void
9159 {
9161 }
9162 \f
9163 #ifndef USE_HIDDEN_LINKONCE
9164 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9165 # define USE_HIDDEN_LINKONCE 1
9166 # else
9167 # define USE_HIDDEN_LINKONCE 0
9168 # endif
9169 #endif
9173 /* Fills in the label name that should be used for a pc thunk for
9174 the given register. */
9176 static void
9178 {
9183 else
9185 }
9188 /* This function generates code for -fpic that loads %ebx with
9189 the return address of the caller and then returns. */
9191 static void
9193 {
9198 {
9200 tree decl;
9216 #if TARGET_MACHO
9218 {
9227 }
9228 else
9229 #endif
9231 {
9242 }
9243 else
9244 {
9247 }
9253 /* Make sure unwind info is emitted for the thunk if needed. */
9256 /* Pad stack IP move with 4 instructions (two NOPs count
9257 as one instruction). */
9259 {
9264 }
9275 }
9279 }
9281 /* Emit code for the SET_GOT patterns. */
9285 {
9291 {
9292 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9297 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9298 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9299 an unadorned address. */
9304 }
9309 {
9311 /* We don't need a pic base, we're not producing pic. */
9318 }
9319 else
9320 {
9329 #if TARGET_MACHO
9330 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9331 This is what will be referenced by the Mach-O PIC subsystem. */
9335 /* When we are restoring the pic base at the site of a nonlocal label,
9336 and we decided to emit the pic base above, we will still output a
9337 local label used for calculating the correction offset (even though
9338 the offset will be 0 in that case). */
9342 #endif
9343 }
9349 }
9351 /* Generate an "push" pattern for input ARG. */
9353 static rtx
9355 {
9368 stack_pointer_rtx)),
9369 arg);
9370 }
9372 /* Generate an "pop" pattern for input ARG. */
9374 static rtx
9376 {
9381 arg,
9384 stack_pointer_rtx)));
9385 }
9387 /* Return >= 0 if there is an unused call-clobbered register available
9388 for the entire function. */
9390 static unsigned int
9392 {
9396 {
9398 /* Can't use the same register for both PIC and DRAP. */
9401 else
9406 }
9409 }
9411 /* Return TRUE if we need to save REGNO. */
9413 static bool
9415 {
9426 {
9429 {
9435 }
9436 }
9447 }
9449 /* Return number of saved general prupose registers. */
9451 static int
9453 {
9459 nregs ++;
9461 }
9463 /* Return number of saved SSE registrers. */
9465 static int
9467 {
9475 nregs ++;
9477 }
9479 /* Given FROM and TO register numbers, say whether this elimination is
9480 allowed. If stack alignment is needed, we can only replace argument
9481 pointer with hard frame pointer, or replace frame pointer with stack
9482 pointer. Otherwise, frame pointer elimination is automatically
9483 handled and all other eliminations are valid. */
9485 static bool
9487 {
9493 else
9495 }
9497 /* Return the offset between two registers, one to be eliminated, and the other
9498 its replacement, at the start of a routine. */
9500 HOST_WIDE_INT
9502 {
9511 else
9512 {
9520 }
9521 }
9523 /* In a dynamically-aligned function, we can't know the offset from
9524 stack pointer to frame pointer, so we must ensure that setjmp
9525 eliminates fp against the hard fp (%ebp) rather than trying to
9526 index from %esp up to the top of the frame across a gap that is
9527 of unknown (at compile-time) size. */
9528 static rtx
9530 {
9532 }
9534 /* When using -fsplit-stack, the allocation routines set a field in
9535 the TCB to the bottom of the stack plus this much space, measured
9536 in bytes. */
9538 #define SPLIT_STACK_AVAILABLE 256
9540 /* Fill structure ix86_frame about frame of currently computed function. */
9542 static void
9544 {
9546 HOST_WIDE_INT offset;
9549 HOST_WIDE_INT to_allocate;
9554 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9555 function prologues and leaf. */
9559 {
9562 }
9563 /* preferred_stack_boundary is never updated for call
9564 expanded from tls descriptor. Update it here. We don't update it in
9565 expand stage because according to the comments before
9566 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9567 away. */
9570 {
9574 }
9583 /* For SEH we have to limit the amount of code movement into the prologue.
9584 At present we do this via a BLOCKAGE, at which point there's very little
9585 scheduling that can be done, which means that there's very little point
9586 in doing anything except PUSHs. */
9590 /* During reload iteration the amount of registers saved can change.
9591 Recompute the value as needed. Do not recompute when amount of registers
9592 didn't change as reload does multiple calls to the function and does not
9593 expect the decision to change within single iteration. */
9596 {
9602 /* The fast prologue uses move instead of push to save registers. This
9603 is significantly longer, but also executes faster as modern hardware
9604 can execute the moves in parallel, but can't do that for push/pop.
9606 Be careful about choosing what prologue to emit: When function takes
9607 many instructions to execute we may use slow version as well as in
9608 case function is known to be outside hot spot (this is known with
9609 feedback only). Weight the size of function by number of registers
9610 to save as it is cheap to use one or two push instructions but very
9611 slow to use many of them. */
9615 || (flag_branch_probabilities
9618 else
9621 }
9623 frame->save_regs_using_mov
9625 /* If static stack checking is enabled and done with probes,
9626 the registers need to be saved before allocating the frame. */
9629 /* Skip return address. */
9632 /* Skip pushed static chain. */
9636 /* Skip saved base pointer. */
9641 /* The traditional frame pointer location is at the top of the frame. */
9644 /* Register save area */
9648 /* On SEH target, registers are pushed just before the frame pointer
9649 location. */
9653 /* Align and set SSE register save area. */
9655 {
9656 /* The only ABI that has saved SSE registers (Win64) also has a
9657 16-byte aligned default stack, and thus we don't need to be
9658 within the re-aligned local stack frame to save them. */
9662 }
9665 /* The re-aligned stack starts here. Values before this point are not
9666 directly comparable with values below this point. In order to make
9667 sure that no value happens to be the same before and after, force
9668 the alignment computation below to add a non-zero value. */
9672 /* Va-arg area */
9676 /* Align start of frame for local function. */
9685 /* Frame pointer points here. */
9690 /* Add outgoing arguments area. Can be skipped if we eliminated
9691 all the function calls as dead code.
9692 Skipping is however impossible when function calls alloca. Alloca
9693 expander assumes that last crtl->outgoing_args_size
9694 of stack frame are unused. */
9698 {
9701 }
9702 else
9705 /* Align stack boundary. Only needed if we're calling another function
9706 or using alloca. */
9711 /* We've reached end of stack frame. */
9714 /* Size prologue needs to allocate. */
9725 {
9731 }
9732 else
9736 /* The SEH frame pointer location is near the bottom of the frame.
9737 This is enforced by the fact that the difference between the
9738 stack pointer and the frame pointer is limited to 240 bytes in
9739 the unwind data structure. */
9741 {
9742 HOST_WIDE_INT diff;
9744 /* If we can leave the frame pointer where it is, do so. Also, returns
9745 the establisher frame for __builtin_frame_address (0). */
9750 {
9751 /* Ideally we'd determine what portion of the local stack frame
9752 (within the constraint of the lowest 240) is most heavily used.
9753 But without that complication, simply bias the frame pointer
9754 by 128 bytes so as to maximize the amount of the local stack
9755 frame that is addressable with 8-bit offsets. */
9757 }
9758 }
9759 }
9761 /* This is semi-inlined memory_address_length, but simplified
9762 since we know that we're always dealing with reg+offset, and
9763 to avoid having to create and discard all that rtl. */
9767 {
9771 {
9772 /* EBP and R13 cannot be encoded without an offset. */
9774 }
9778 /* ESP and R12 must be encoded with a SIB byte. */
9780 len++;
9783 }
9785 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9786 The valid base registers are taken from CFUN->MACHINE->FS. */
9788 static rtx
9790 {
9796 {
9797 /* Choose the base register most likely to allow the most scheduling
9798 opportunities. Generally FP is valid throughout the function,
9799 while DRAP must be reloaded within the epilogue. But choose either
9800 over the SP due to increased encoding size. */
9803 {
9806 }
9808 {
9811 }
9813 {
9816 }
9817 }
9818 else
9819 {
9820 HOST_WIDE_INT toffset;
9823 /* Choose the base register with the smallest address encoding.
9824 With a tie, choose FP > DRAP > SP. */
9826 {
9830 }
9832 {
9836 {
9840 }
9841 }
9843 {
9847 {
9851 }
9852 }
9853 }
9857 }
9859 /* Emit code to save registers in the prologue. */
9861 static void
9863 {
9865 rtx insn;
9869 {
9872 }
9873 }
9875 /* Emit a single register save at CFA - CFA_OFFSET. */
9877 static void
9879 HOST_WIDE_INT cfa_offset)
9880 {
9888 /* For SSE saves, we need to indicate the 128-bit alignment. */
9899 /* When saving registers into a re-aligned local stack frame, avoid
9900 any tricky guessing by dwarf2out. */
9902 {
9906 {
9907 /* A bit of a hack. We force the DRAP register to be saved in
9908 the re-aligned stack frame, which provides us with a copy
9909 of the CFA that will last past the prologue. Install it. */
9915 }
9916 else
9917 {
9918 /* The frame pointer is a stable reference within the
9919 aligned frame. Use it. */
9926 }
9927 }
9929 /* The memory may not be relative to the current CFA register,
9930 which means that we may need to generate a new pattern for
9931 use by the unwind info. */
9933 {
9938 }
9939 }
9941 /* Emit code to save registers using MOV insns.
9942 First register is stored at CFA - CFA_OFFSET. */
9943 static void
9945 {
9950 {
9953 }
9954 }
9956 /* Emit code to save SSE registers using MOV insns.
9957 First register is stored at CFA - CFA_OFFSET. */
9958 static void
9960 {
9965 {
9968 }
9969 }
9973 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9974 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9975 Don't add the note if the previously saved value will be left untouched
9976 within stack red-zone till return, as unwinders can find the same value
9977 in the register and on the stack. */
9979 static void
9981 {
9987 {
9990 }
9991 else
9992 queued_cfa_restores
9994 }
9996 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9998 static void
10000 {
10001 rtx last;
10005 ;
10010 }
10012 /* Expand prologue or epilogue stack adjustment.
10013 The pattern exist to put a dependency on all ebp-based memory accesses.
10014 STYLE should be negative if instructions should be marked as frame related,
10015 zero if %r11 register is live and cannot be freely used and positive
10016 otherwise. */
10018 static void
10021 {
10023 rtx insn;
10030 else
10031 {
10032 rtx tmp;
10033 /* r11 is used by indirect sibcall return as well, set before the
10034 epilogue and used after the epilogue. */
10037 else
10038 {
10042 }
10048 }
10055 {
10056 rtx r;
10066 }
10068 {
10071 {
10075 }
10076 }
10079 {
10084 {
10087 }
10089 {
10092 }
10093 else
10094 {
10095 /* Else there are two possibilities: SP itself, which we set
10096 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10097 taken care of this by hand along the eh_return path. */
10100 }
10104 }
10105 }
10107 /* Find an available register to be used as dynamic realign argument
10108 pointer regsiter. Such a register will be written in prologue and
10109 used in begin of body, so it must not be
10110 1. parameter passing register.
10111 2. GOT pointer.
10112 We reuse static-chain register if it is available. Otherwise, we
10113 use DI for i386 and R13 for x86-64. We chose R13 since it has
10114 shorter encoding.
10116 Return: the regno of chosen register. */
10118 static unsigned int
10120 {
10124 {
10125 /* Use R13 for nested function or function need static chain.
10126 Since function with tail call may use any caller-saved
10127 registers in epilogue, DRAP must not use caller-saved
10128 register in such case. */
10133 }
10134 else
10135 {
10136 /* Use DI for nested function or function need static chain.
10137 Since function with tail call may use any caller-saved
10138 registers in epilogue, DRAP must not use caller-saved
10139 register in such case. */
10143 /* Reuse static chain register if it isn't used for parameter
10144 passing. */
10146 {
10150 }
10152 }
10153 }
10155 /* Return minimum incoming stack alignment. */
10157 static unsigned int
10159 {
10162 /* Prefer the one specified at command line. */
10165 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10166 if -mstackrealign is used, it isn't used for sibcall check and
10167 estimated stack alignment is 128bit. */
10169 && !TARGET_64BIT
10170 && ix86_force_align_arg_pointer
10173 else
10176 /* Incoming stack alignment can be changed on individual functions
10177 via force_align_arg_pointer attribute. We use the smallest
10178 incoming stack boundary. */
10184 /* The incoming stack frame has to be aligned at least at
10185 parm_stack_boundary. */
10189 /* Stack at entrance of main is aligned by runtime. We use the
10190 smallest incoming stack boundary. */
10198 }
10200 /* Update incoming stack boundary and estimated stack alignment. */
10202 static void
10204 {
10205 ix86_incoming_stack_boundary
10208 /* x86_64 vararg needs 16byte stack alignment for register save
10209 area. */
10214 }
10216 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10217 needed or an rtx for DRAP otherwise. */
10219 static rtx
10221 {
10226 {
10227 /* Assign DRAP to vDRAP and returns vDRAP */
10229 rtx drap_vreg;
10230 rtx arg_ptr;
10243 {
10246 }
10248 }
10249 else
10251 }
10253 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10255 static rtx
10257 {
10259 }
10262 rtx reg;
10264 };
10266 /* Return a short-lived scratch register for use on function entry.
10267 In 32-bit mode, it is valid only after the registers are saved
10268 in the prologue. This register must be released by means of
10269 release_scratch_register_on_entry once it is dead. */
10271 static void
10273 {
10279 {
10280 /* We always use R11 in 64-bit mode. */
10282 }
10283 else
10284 {
10286 bool fastcall_p
10288 bool thiscall_p
10292 int drap_regno
10295 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10296 for the static chain register. */
10300 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10301 for the static chain register. */
10306 /* ecx is the static chain register. */
10308 && !static_chain_p
10313 /* esi is the static chain register. */
10319 else
10320 {
10323 }
10324 }
10328 {
10331 }
10332 }
10334 /* Release a scratch register obtained from the preceding function. */
10336 static void
10338 {
10340 {
10344 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10350 }
10351 }
10353 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10355 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10357 static void
10359 {
10360 /* We skip the probe for the first interval + a small dope of 4 words and
10361 probe that many bytes past the specified size to maintain a protection
10362 area at the botton of the stack. */
10366 /* See if we have a constant small number of probes to generate. If so,
10367 that's the easy case. The run-time loop is made up of 11 insns in the
10368 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10369 for n # of intervals. */
10371 {
10375 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10376 values of N from 1 until it exceeds SIZE. If only one probe is
10377 needed, this will not generate any code. Then adjust and probe
10378 to PROBE_INTERVAL + SIZE. */
10380 {
10382 {
10385 }
10386 else
10393 }
10397 else
10405 /* Adjust back to account for the additional first interval. */
10409 }
10411 /* Otherwise, do the same as above, but in a loop. Note that we must be
10412 extra careful with variables wrapping around because we might be at
10413 the very top (or the very bottom) of the address space and we have
10414 to be able to handle this case properly; in particular, we use an
10415 equality test for the loop condition. */
10416 else
10417 {
10418 HOST_WIDE_INT rounded_size;
10424 /* Step 1: round SIZE to the previous multiple of the interval. */
10429 /* Step 2: compute initial and final value of the loop counter. */
10431 /* SP = SP_0 + PROBE_INTERVAL. */
10436 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10440 stack_pointer_rtx)));
10443 /* Step 3: the loop
10445 while (SP != LAST_ADDR)
10446 {
10447 SP = SP + PROBE_INTERVAL
10448 probe at SP
10449 }
10451 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10452 values of N from 1 until it is equal to ROUNDED_SIZE. */
10457 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10458 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10461 {
10466 }
10468 /* Adjust back to account for the additional first interval. */
10474 }
10478 /* Even if the stack pointer isn't the CFA register, we need to correctly
10479 describe the adjustments made to it, in particular differentiate the
10480 frame-related ones from the frame-unrelated ones. */
10482 {
10495 }
10497 /* Make sure nothing is scheduled before we are done. */
10499 }
10501 /* Adjust the stack pointer up to REG while probing it. */
10505 {
10515 /* Jump to END_LAB if SP == LAST_ADDR. */
10523 /* SP = SP + PROBE_INTERVAL. */
10527 /* Probe at SP. */
10538 }
10540 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10541 inclusive. These are offsets from the current stack pointer. */
10543 static void
10545 {
10546 /* See if we have a constant small number of probes to generate. If so,
10547 that's the easy case. The run-time loop is made up of 7 insns in the
10548 generic case while the compile-time loop is made up of n insns for n #
10549 of intervals. */
10551 {
10552 HOST_WIDE_INT i;
10554 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10555 it exceeds SIZE. If only one probe is needed, this will not
10556 generate any code. Then probe at FIRST + SIZE. */
10563 }
10565 /* Otherwise, do the same as above, but in a loop. Note that we must be
10566 extra careful with variables wrapping around because we might be at
10567 the very top (or the very bottom) of the address space and we have
10568 to be able to handle this case properly; in particular, we use an
10569 equality test for the loop condition. */
10570 else
10571 {
10578 /* Step 1: round SIZE to the previous multiple of the interval. */
10583 /* Step 2: compute initial and final value of the loop counter. */
10585 /* TEST_OFFSET = FIRST. */
10588 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10592 /* Step 3: the loop
10594 while (TEST_ADDR != LAST_ADDR)
10595 {
10596 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10597 probe at TEST_ADDR
10598 }
10600 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10601 until it is equal to ROUNDED_SIZE. */
10606 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10607 that SIZE is equal to ROUNDED_SIZE. */
10612 stack_pointer_rtx,
10617 }
10619 /* Make sure nothing is scheduled before we are done. */
10621 }
10623 /* Probe a range of stack addresses from REG to END, inclusive. These are
10624 offsets from the current stack pointer. */
10628 {
10638 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10646 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10650 /* Probe at TEST_ADDR. */
10663 }
10665 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10666 to be generated in correct form. */
10667 static void
10669 {
10670 /* Check if stack realign is really needed after reload, and
10671 stores result in cfun */
10672 unsigned int incoming_stack_boundary
10681 {
10682 /* After stack_realign_needed is finalized, we can't no longer
10683 change it. */
10686 }
10688 /* If the only reason for frame_pointer_needed is that we conservatively
10689 assumed stack realignment might be needed, but in the end nothing that
10690 needed the stack alignment had been spilled, clear frame_pointer_needed
10691 and say we don't need stack realignment. */
10693 && frame_pointer_needed
10695 && flag_omit_frame_pointer
10697 && !ix86_current_function_calls_tls_descriptor
10706 {
10708 basic_block bb;
10715 HARD_FRAME_POINTER_REGNUM);
10717 {
10722 set_up_by_prologue))
10723 {
10727 }
10728 }
10730 /* If drap has been set, but it actually isn't live at the start
10731 of the function, there is no reason to set it up. */
10733 {
10736 {
10739 }
10740 }
10741 else
10756 }
10760 }
10762 /* Expand the prologue into a bunch of separate insns. */
10764 void
10766 {
10771 HOST_WIDE_INT allocate;
10777 /* DRAP should not coexist with stack_realign_fp */
10782 /* Initialize CFA state for before the prologue. */
10786 /* Track SP offset to the CFA. We continue tracking this after we've
10787 swapped the CFA register away from SP. In the case of re-alignment
10788 this is fudged; we're interested to offsets within the local frame. */
10795 {
10796 /* We should have already generated an error for any use of
10797 ms_hook on a nested function. */
10800 /* Check if profiling is active and we shall use profiling before
10801 prologue variant. If so sorry. */
10806 /* In ix86_asm_output_function_label we emitted:
10807 8b ff movl.s %edi,%edi
10808 55 push %ebp
10809 8b ec movl.s %esp,%ebp
10811 This matches the hookable function prologue in Win32 API
10812 functions in Microsoft Windows XP Service Pack 2 and newer.
10813 Wine uses this to enable Windows apps to hook the Win32 API
10814 functions provided by Wine.
10816 What that means is that we've already set up the frame pointer. */
10820 {
10823 /* We've decided to use the frame pointer already set up.
10824 Describe this to the unwinder by pretending that both
10825 push and mov insns happen right here.
10827 Putting the unwind info here at the end of the ms_hook
10828 is done so that we can make absolutely certain we get
10829 the required byte sequence at the start of the function,
10830 rather than relying on an assembler that can produce
10831 the exact encoding required.
10833 However it does mean (in the unpatched case) that we have
10834 a 1 insn window where the asynchronous unwind info is
10835 incorrect. However, if we placed the unwind info at
10836 its correct location we would have incorrect unwind info
10837 in the patched case. Which is probably all moot since
10838 I don't expect Wine generates dwarf2 unwind info for the
10839 system libraries that use this feature. */
10845 stack_pointer_rtx);
10853 /* Note that gen_push incremented m->fs.cfa_offset, even
10854 though we didn't emit the push insn here. */
10858 }
10859 else
10860 {
10861 /* The frame pointer is not needed so pop %ebp again.
10862 This leaves us with a pristine state. */
10864 }
10865 }
10867 /* The first insn of a function that accepts its static chain on the
10868 stack is to push the register that would be filled in by a direct
10869 call. This insn will be skipped by the trampoline. */
10871 {
10875 /* We don't want to interpret this push insn as a register save,
10876 only as a stack adjustment. The real copy of the register as
10877 a save will be done later, if needed. */
10882 }
10884 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10885 of DRAP is needed and stack realignment is really needed after reload */
10887 {
10890 /* Only need to push parameter pointer reg if it is caller saved. */
10892 {
10893 /* Push arg pointer reg */
10896 }
10898 /* Grab the argument pointer. */
10905 /* Align the stack. */
10907 stack_pointer_rtx,
10911 /* Replicate the return address on the stack so that return
10912 address can be reached via (argp - 1) slot. This is needed
10913 to implement macro RETURN_ADDR_RTX and intrinsic function
10914 expand_builtin_return_addr etc. */
10920 /* For the purposes of frame and register save area addressing,
10921 we've started over with a new frame. */
10924 }
10930 {
10931 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10932 slower on all targets. Also sdb doesn't like it. */
10936 /* Push registers now, before setting the frame pointer
10937 on SEH target. */
10939 && TARGET_SEH
10941 {
10945 }
10948 {
10956 }
10957 }
10960 {
10961 /* If saving registers via PUSH, do so now. */
10963 {
10967 }
10969 /* When using red zone we may start register saving before allocating
10970 the stack frame saving one cycle of the prologue. However, avoid
10971 doing this if we have to probe the stack; at least on x86_64 the
10972 stack probe can turn into a call that clobbers a red zone location. */
10974 && (! TARGET_STACK_PROBE
10976 {
10979 }
10980 }
10983 {
10987 /* The computation of the size of the re-aligned stack frame means
10988 that we must allocate the size of the register save area before
10989 performing the actual alignment. Otherwise we cannot guarantee
10990 that there's enough storage above the realignment point. */
10997 /* Align the stack. */
10999 stack_pointer_rtx,
11002 /* For the purposes of register save area addressing, the stack
11003 pointer is no longer valid. As for the value of sp_offset,
11004 see ix86_compute_frame_layout, which we need to match in order
11005 to pass verification of stack_pointer_offset at the end. */
11008 }
11013 {
11014 /* We start to count from ARG_POINTER. */
11017 /* If it was realigned, take into account the fake frame. */
11019 {
11026 /* This over-estimates by 1 minimal-stack-alignment-unit but
11027 mitigates that by counting in the new return address slot. */
11028 current_function_dynamic_stack_size
11030 }
11033 }
11035 /* On SEH target with very large frame size, allocate an area to save
11036 SSE registers (as the very large allocation won't be described). */
11040 {
11041 HOST_WIDE_INT sse_size =
11046 /* No need to do stack checking as the area will be immediately
11047 written. */
11054 }
11056 /* The stack has already been decremented by the instruction calling us
11057 so probe if the size is non-negative to preserve the protection area. */
11059 {
11060 /* We expect the registers to be saved when probes are used. */
11064 {
11067 {
11070 }
11071 }
11072 else
11073 {
11080 {
11082 {
11085 }
11086 else
11088 }
11089 else
11090 {
11092 {
11096 }
11097 else
11099 }
11100 }
11101 }
11104 ;
11107 {
11111 }
11112 else
11113 {
11125 {
11128 /* Note that SEH directives need to continue tracking the stack
11129 pointer even after the frame pointer has been set up. */
11131 {
11135 }
11136 }
11139 {
11144 {
11148 }
11149 }
11154 /* Use the fact that AX still contains ALLOCATE. */
11156 ? gen_pro_epilogue_adjust_stack_di_sub
11163 {
11171 }
11174 /* Use stack_pointer_rtx for relative addressing so that code
11175 works for realigned stack, too. */
11177 {
11184 }
11186 {
11191 }
11192 }
11195 /* If we havn't already set up the frame pointer, do so now. */
11197 {
11209 }
11217 /* We don't use pic-register for pe-coff target. */
11219 && !TARGET_PECOFF
11222 {
11229 }
11232 {
11234 {
11236 {
11238 rtx tmp_reg;
11247 label));
11251 }
11252 else
11254 }
11255 else
11256 {
11260 }
11261 }
11263 /* In the pic_reg_used case, make sure that the got load isn't deleted
11264 when mcount needs it. Blockage to avoid call movement across mcount
11265 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11266 note. */
11271 {
11272 /* vDRAP is setup but after reload it turns out stack realign
11273 isn't necessary, here we will emit prologue to setup DRAP
11274 without stack realign adjustment */
11277 }
11279 /* Prevent instructions from being scheduled into register save push
11280 sequence when access to the redzone area is done through frame pointer.
11281 The offset between the frame pointer and the stack pointer is calculated
11282 relative to the value of the stack pointer at the end of the function
11283 prologue, and moving instructions that access redzone area via frame
11284 pointer inside push sequence violates this assumption. */
11288 /* Emit cld instruction if stringops are used in the function. */
11292 /* SEH requires that the prologue end within 256 bytes of the start of
11293 the function. Prevent instruction schedules that would extend that.
11294 Further, prevent alloca modifications to the stack pointer from being
11295 combined with prologue modifications. */
11298 }
11300 /* Emit code to restore REG using a POP insn. */
11302 static void
11304 {
11313 {
11314 /* Previously we'd represented the CFA as an expression
11315 like *(%ebp - 8). We've just popped that value from
11316 the stack, which means we need to reset the CFA to
11317 the drap register. This will remain until we restore
11318 the stack pointer. */
11322 /* This means that the DRAP register is valid for addressing too. */
11325 }
11328 {
11335 }
11337 /* When the frame pointer is the CFA, and we pop it, we are
11338 swapping back to the stack pointer as the CFA. This happens
11339 for stack frames that don't allocate other data, so we assume
11340 the stack pointer is now pointing at the return address, i.e.
11341 the function entry state, which makes the offset be 1 word. */
11343 {
11346 {
11354 }
11355 }
11356 }
11358 /* Emit code to restore saved registers using POP insns. */
11360 static void
11362 {
11368 }
11370 /* Emit code and notes for the LEAVE instruction. */
11372 static void
11374 {
11386 {
11394 }
11397 }
11399 /* Emit code to restore saved registers using MOV insns.
11400 First register is restored from CFA - CFA_OFFSET. */
11401 static void
11404 {
11410 {
11419 {
11420 /* Previously we'd represented the CFA as an expression
11421 like *(%ebp - 8). We've just popped that value from
11422 the stack, which means we need to reset the CFA to
11423 the drap register. This will remain until we restore
11424 the stack pointer. */
11428 /* This means that the DRAP register is valid for addressing. */
11430 }
11431 else
11435 }
11436 }
11438 /* Emit code to restore saved registers using MOV insns.
11439 First register is restored from CFA - CFA_OFFSET. */
11440 static void
11443 {
11448 {
11450 rtx mem;
11460 }
11461 }
11463 /* Restore function stack, frame, and registers. */
11465 void
11467 {
11483 /* The FP must be valid if the frame pointer is present. */
11488 /* We must have *some* valid pointer to the stack frame. */
11491 /* The DRAP is never valid at this point. */
11494 /* See the comment about red zone and frame
11495 pointer usage in ix86_expand_prologue. */
11502 /* Determine the CFA offset of the end of the red-zone. */
11505 {
11506 /* The red-zone begins below the return address. */
11509 /* When the register save area is in the aligned portion of
11510 the stack, determine the maximum runtime displacement that
11511 matches up with the aligned frame. */
11515 }
11517 /* Special care must be taken for the normal return case of a function
11518 using eh_return: the eax and edx registers are marked as saved, but
11519 not restored along this path. Adjust the save location to match. */
11523 /* EH_RETURN requires the use of moves to function properly. */
11526 /* SEH requires the use of pops to identify the epilogue. */
11529 /* If we're only restoring one register and sp is not valid then
11530 using a move instruction to restore the register since it's
11531 less work than reloading sp and popping the register. */
11544 && TARGET_USE_LEAVE
11548 else
11552 {
11553 /* Ensure that the entire register save area is addressable via
11554 the stack pointer, if we will restore via sp. */
11559 {
11563 style,
11565 }
11566 }
11568 /* If there are any SSE registers to restore, then we have to do it
11569 via moves, since there's obviously no pop for SSE regs. */
11575 {
11576 rtx t;
11581 /* eh_return epilogues need %ecx added to the stack pointer. */
11583 {
11586 /* Stack align doesn't work with eh_return. */
11588 /* Neither does regparm nested functions. */
11592 {
11600 /* Note that we use SA as a temporary CFA, as the return
11601 address is at the proper place relative to it. We
11602 pretend this happens at the FP restore insn because
11603 prior to this insn the FP would be stored at the wrong
11604 offset relative to SA, and after this insn we have no
11605 other reasonable register to use for the CFA. We don't
11606 bother resetting the CFA to the SP for the duration of
11607 the return insn. */
11620 }
11621 else
11622 {
11630 {
11634 UNITS_PER_WORD));
11636 }
11637 }
11640 }
11641 }
11642 else
11643 {
11644 /* SEH requires that the function end with (1) a stack adjustment
11645 if necessary, (2) a sequence of pops, and (3) a return or
11646 jump instruction. Prevent insns from the function body from
11647 being scheduled into this sequence. */
11649 {
11650 /* Prevent a catch region from being adjacent to the standard
11651 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11652 several other flags that would be interesting to test are
11653 not yet set up. */
11656 else
11658 }
11660 /* First step is to deallocate the stack frame so that we can
11661 pop the registers. Also do it on SEH target for very large
11662 frame as the emitted instructions aren't allowed by the ABI in
11663 epilogues. */
11665 || (TARGET_SEH
11668 {
11673 }
11675 {
11679 style,
11681 }
11684 }
11686 /* If we used a stack pointer and haven't already got rid of it,
11687 then do so now. */
11689 {
11690 /* If the stack pointer is valid and pointing at the frame
11691 pointer store address, then we only need a pop. */
11694 /* Leave results in shorter dependency chains on CPUs that are
11695 able to grok it fast. */
11700 else
11701 {
11703 hard_frame_pointer_rtx,
11706 }
11707 }
11710 {
11712 rtx insn;
11738 }
11740 /* At this point the stack pointer must be valid, and we must have
11741 restored all of the registers. We may not have deallocated the
11742 entire stack frame. We've delayed this until now because it may
11743 be possible to merge the local stack deallocation with the
11744 deallocation forced by ix86_static_chain_on_stack. */
11749 {
11753 }
11754 else
11757 /* Sibcall epilogues don't want a return instruction. */
11759 {
11762 }
11765 {
11768 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11769 address, do explicit add, and jump indirectly to the caller. */
11772 {
11774 rtx insn;
11776 /* There is no "pascal" calling convention in any 64bit ABI. */
11793 }
11794 else
11796 }
11797 else
11800 /* Restore the state back to the state from the prologue,
11801 so that it's correct for the next epilogue. */
11803 }
11805 /* Reset from the function's potential modifications. */
11807 static void
11809 {
11812 #if TARGET_MACHO
11813 /* Mach-O doesn't support labels at the end of objects, so if
11814 it looks like we might want one, insert a NOP. */
11815 {
11821 {
11822 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11823 notes only, instead set their CODE_LABEL_NUMBER to -1,
11824 otherwise there would be code generation differences
11825 in between -g and -g0. */
11829 }
11839 }
11840 #endif
11842 }
11844 /* Return a scratch register to use in the split stack prologue. The
11845 split stack prologue is used for -fsplit-stack. It is the first
11846 instructions in the function, even before the regular prologue.
11847 The scratch register can be any caller-saved register which is not
11848 used for parameters or for the static chain. */
11850 static unsigned int
11852 {
11855 else
11856 {
11869 {
11871 {
11875 }
11877 }
11879 {
11883 }
11885 {
11888 else
11889 {
11891 {
11895 }
11897 }
11898 }
11899 else
11900 {
11901 /* FIXME: We could make this work by pushing a register
11902 around the addition and comparison. */
11905 }
11906 }
11907 }
11909 /* A SYMBOL_REF for the function which allocates new stackspace for
11910 -fsplit-stack. */
11914 /* A SYMBOL_REF for the more stack function when using the large
11915 model. */
11919 /* Handle -fsplit-stack. These are the first instructions in the
11920 function, even before the regular prologue. */
11922 void
11924 {
11926 HOST_WIDE_INT allocate;
11932 rtx fn;
11940 /* This is the label we will branch to if we have enough stack
11941 space. We expect the basic block reordering pass to reverse this
11942 branch if optimizing, so that we branch in the unlikely case. */
11945 /* We need to compare the stack pointer minus the frame size with
11946 the stack boundary in the TCB. The stack boundary always gives
11947 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11948 can compare directly. Otherwise we need to do an addition. */
11951 UNSPEC_STACK_CHECK);
11956 else
11957 {
11959 rtx offset;
11961 /* We need a scratch register to hold the stack pointer minus
11962 the required frame size. Since this is the very start of the
11963 function, the scratch register can be any caller-saved
11964 register which is not used for parameters. */
11971 {
11972 /* We don't use ix86_gen_add3 in this case because it will
11973 want to split to lea, but when not optimizing the insn
11974 will not be split after this point. */
11977 offset)));
11978 }
11979 else
11980 {
11983 stack_pointer_rtx));
11984 }
11986 }
11992 /* Mark the jump as very likely to be taken. */
12000 /* Get more stack space. We pass in the desired stack space and the
12001 size of the arguments to copy to the new stack. In 32-bit mode
12002 we push the parameters; __morestack will return on a new stack
12003 anyhow. In 64-bit mode we pass the parameters in r10 and
12004 r11. */
12009 {
12015 /* If this function uses a static chain, it will be in %r10.
12016 Preserve it across the call to __morestack. */
12018 {
12019 rtx rax;
12024 }
12028 {
12029 HOST_WIDE_INT argval;
12032 /* When using the large model we need to load the address
12033 into a register, and we've run out of registers. So we
12034 switch to a different calling convention, and we call a
12035 different function: __morestack_large. We pass the
12036 argument size in the upper 32 bits of r10 and pass the
12037 frame size in the lower 32 bits. */
12042 split_stack_fn_large =
12046 {
12048 rtx x;
12057 UNSPEC_GOT);
12063 }
12064 else
12071 }
12072 else
12073 {
12077 }
12080 }
12081 else
12082 {
12085 }
12091 /* In order to make call/return prediction work right, we now need
12092 to execute a return instruction. See
12093 libgcc/config/i386/morestack.S for the details on how this works.
12095 For flow purposes gcc must not see this as a return
12096 instruction--we need control flow to continue at the subsequent
12097 label. Therefore, we use an unspec. */
12101 /* If we are in 64-bit mode and this function uses a static chain,
12102 we saved %r10 in %rax before calling _morestack. */
12107 /* If this function calls va_start, we need to store a pointer to
12108 the arguments on the old stack, because they may not have been
12109 all copied to the new stack. At this point the old stack can be
12110 found at the frame pointer value used by __morestack, because
12111 __morestack has set that up before calling back to us. Here we
12112 store that pointer in a scratch register, and in
12113 ix86_expand_prologue we store the scratch register in a stack
12114 slot. */
12116 {
12118 rtx frame_reg;
12125 /* 64-bit:
12126 fp -> old fp value
12127 return address within this function
12128 return address of caller of this function
12129 stack arguments
12130 So we add three words to get to the stack arguments.
12132 32-bit:
12133 fp -> old fp value
12134 return address within this function
12135 first argument to __morestack
12136 second argument to __morestack
12137 return address of caller of this function
12138 stack arguments
12139 So we add five words to get to the stack arguments.
12140 */
12151 }
12156 /* If this function calls va_start, we now have to set the scratch
12157 register for the case where we do not call __morestack. In this
12158 case we need to set it based on the stack pointer. */
12160 {
12167 }
12168 }
12170 /* We may have to tell the dataflow pass that the split stack prologue
12171 is initializing a scratch register. */
12173 static void
12175 {
12177 {
12180 }
12181 }
12182 \f
12183 /* Extract the parts of an RTL expression that is a valid memory address
12184 for an instruction. Return 0 if the structure of the address is
12185 grossly off. Return -1 if the address contains ASHIFT, so it is not
12186 strictly valid, but still used for computing length of lea instruction. */
12188 int
12190 {
12195 rtx tmp;
12199 /* Allow zero-extended SImode addresses,
12200 they will be emitted with addr32 prefix. */
12202 {
12205 {
12209 }
12212 {
12219 }
12220 }
12222 /* Allow SImode subregs of DImode addresses,
12223 they will be emitted with addr32 prefix. */
12225 {
12228 {
12232 }
12233 }
12238 {
12241 else
12243 }
12245 {
12250 do
12251 {
12256 }
12263 {
12266 {
12291 /* FALLTHRU */
12295 && TARGET_TLS_DIRECT_SEG_REFS
12298 else
12305 /* FALLTHRU */
12312 else
12327 }
12328 }
12329 }
12331 {
12334 }
12336 {
12337 /* We're called for lea too, which implements ashift on occasion. */
12347 }
12348 else
12352 {
12354 ;
12357 ;
12358 else
12360 }
12362 /* Extract the integral value of scale. */
12364 {
12368 }
12373 /* Avoid useless 0 displacement. */
12377 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12382 {
12383 rtx tmp;
12386 }
12388 /* Special case: %ebp cannot be encoded as a base without a displacement.
12389 Similarly %r13. */
12391 && base_reg
12400 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12401 Avoid this by transforming to [%esi+0].
12402 Reload calls address legitimization without cfun defined, so we need
12403 to test cfun for being non-NULL. */
12409 /* Special case: encode reg+reg instead of reg*2. */
12413 /* Special case: scaling cannot be encoded without base or displacement. */
12424 }
12425 \f
12426 /* Return cost of the memory address x.
12427 For i386, it is better to use a complex address than let gcc copy
12428 the address into a reg and make a new pseudo. But not if the address
12429 requires to two regs - that would mean more pseudos with longer
12430 lifetimes. */
12431 static int
12433 {
12445 /* Attempt to minimize number of registers in the address. */
12451 cost++;
12458 cost++;
12460 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12461 since it's predecode logic can't detect the length of instructions
12462 and it degenerates to vector decoded. Increase cost of such
12463 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12464 to split such addresses or even refuse such addresses at all.
12466 Following addressing modes are affected:
12467 [base+scale*index]
12468 [scale*index+disp]
12469 [base+index]
12471 The first and last case may be avoidable by explicitly coding the zero in
12472 memory address, but I don't have AMD-K6 machine handy to check this
12473 theory. */
12482 }
12483 \f
12484 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12485 this is used for to form addresses to local data when -fPIC is in
12486 use. */
12488 static bool
12490 {
12493 }
12495 /* Determine if a given RTX is a valid constant. We already know this
12496 satisfies CONSTANT_P. */
12498 static bool
12500 {
12502 {
12507 {
12511 }
12516 /* Only some unspecs are valid as "constants". */
12519 {
12535 }
12537 /* We must have drilled down to a symbol. */
12542 /* FALLTHRU */
12545 /* TLS symbols are never valid. */
12549 /* DLLIMPORT symbols are never valid. */
12554 #if TARGET_MACHO
12555 /* mdynamic-no-pic */
12558 #endif
12574 }
12576 /* Otherwise we handle everything else in the move patterns. */
12578 }
12580 /* Determine if it's legal to put X into the constant pool. This
12581 is not possible for the address of thread-local symbols, which
12582 is checked above. */
12584 static bool
12586 {
12587 /* We can always put integral constants and vectors in memory. */
12589 {
12597 }
12599 }
12601 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12602 otherwise zero. */
12604 static bool
12606 {
12612 }
12615 /* Nonzero if the constant value X is a legitimate general operand
12616 when generating PIC code. It is given that flag_pic is on and
12617 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12619 bool
12621 {
12622 rtx inner;
12625 {
12632 /* Only some unspecs are valid as "constants". */
12635 {
12648 }
12649 /* FALLTHRU */
12657 }
12658 }
12660 /* Determine if a given CONST RTX is a valid memory displacement
12661 in PIC mode. */
12663 bool
12665 {
12668 /* In 64bit mode we can allow direct addresses of symbols and labels
12669 when they are not dynamic symbols. */
12671 {
12675 {
12699 /* FALLTHRU */
12702 /* TLS references should always be enclosed in UNSPEC.
12703 The dllimported symbol needs always to be resolved. */
12709 {
12717 /* Function-symbols need to be resolved only for
12718 large-model.
12719 For the small-model we don't need to resolve anything
12720 here. */
12725 /* Non-external symbols don't need to be resolved for
12726 large, and medium-model. */
12731 }
12740 }
12741 }
12747 {
12748 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12749 of GOT tables. We should not need these anyway. */
12761 }
12765 {
12770 }
12779 {
12783 /* We need to check for both symbols and labels because VxWorks loads
12784 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12785 details. */
12789 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12790 While ABI specify also 32bit relocation but we don't produce it in
12791 small PIC model at all. */
12813 }
12816 }
12818 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12819 replace the input X, or the original X if no replacement is called for.
12820 The output parameter *WIN is 1 if the calling macro should goto WIN,
12821 0 if it should not. */
12823 bool
12826 {
12827 /* Reload can generate:
12829 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12830 (reg:DI 97))
12831 (reg:DI 2 cx))
12833 This RTX is rejected from ix86_legitimate_address_p due to
12834 non-strictness of base register 97. Following this rejection,
12835 reload pushes all three components into separate registers,
12836 creating invalid memory address RTX.
12838 Following code reloads only the invalid part of the
12839 memory address RTX. */
12845 {
12851 {
12856 }
12860 {
12865 }
12869 }
12872 }
12874 /* Determine if op is suitable RTX for an address register.
12875 Return naked register if a register or a register subreg is
12876 found, otherwise return NULL_RTX. */
12878 static rtx
12880 {
12883 /* Only SImode or DImode registers can form the address. */
12890 {
12898 /* Don't allow SUBREGs that span more than a word. It can
12899 lead to spill failures when the register is one word out
12900 of a two word structure. */
12904 /* Allow only SUBREGs of non-eliminable hard registers. */
12907 }
12909 /* Op is not a register. */
12911 }
12913 /* Recognizes RTL expressions that are valid memory addresses for an
12914 instruction. The MODE argument is the machine mode for the MEM
12915 expression that wants to use this address.
12917 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12918 convert common non-canonical forms to canonical form so that they will
12919 be recognized. */
12921 static bool
12923 {
12926 HOST_WIDE_INT scale;
12930 /* Decomposition failed. */
12939 /* Validate base register. */
12941 {
12949 /* Base is not valid. */
12951 }
12953 /* Validate index register. */
12955 {
12963 /* Index is not valid. */
12965 }
12967 /* Index and base should have the same mode. */
12972 /* Address override works only on the (%reg) part of %fs:(%reg). */
12978 /* Validate scale factor. */
12980 {
12982 /* Scale without index. */
12986 /* Scale is not a valid multiplier. */
12988 }
12990 /* Validate displacement. */
12992 {
12997 {
12998 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12999 used. While ABI specify also 32bit relocations, we don't produce
13000 them at all and use IP relative instead. */
13007 /* 64bit address unspec. */
13027 /* Invalid address unspec. */
13029 }
13032 && (flag_pic
13033 || (TARGET_MACHO
13034 #if TARGET_MACHO
13035 && MACHOPIC_INDIRECT
13037 #endif
13038 )))
13039 {
13041 is_legitimate_pic:
13043 {
13044 /* foo@dtpoff(%rX) is ok. */
13051 /* Non-constant pic memory reference. */
13053 }
13056 /* Displacement is an invalid pic construct. */
13058 #if TARGET_MACHO
13061 /* displacment must be referenced via non_lazy_pointer */
13063 #endif
13065 /* This code used to verify that a symbolic pic displacement
13066 includes the pic_offset_table_rtx register.
13068 While this is good idea, unfortunately these constructs may
13069 be created by "adds using lea" optimization for incorrect
13070 code like:
13072 int a;
13073 int foo(int i)
13074 {
13075 return *(&a+i);
13076 }
13078 This code is nonsensical, but results in addressing
13079 GOT table with pic_offset_table_rtx base. We can't
13080 just refuse it easily, since it gets matched by
13081 "addsi3" pattern, that later gets split to lea in the
13082 case output register differs from input. While this
13083 can be handled by separate addsi pattern for this case
13084 that never results in lea, this seems to be easier and
13085 correct fix for crash to disable this test. */
13086 }
13093 /* Displacement is not constant. */
13097 /* Displacement is out of range. */
13099 /* In x32 mode, constant addresses are sign extended to 64bit, so
13100 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13105 }
13107 /* Everything looks valid. */
13109 }
13111 /* Determine if a given RTX is a valid constant address. */
13113 bool
13115 {
13117 }
13118 \f
13119 /* Return a unique alias set for the GOT. */
13121 static alias_set_type
13123 {
13128 }
13130 /* Return a legitimate reference for ORIG (an address) using the
13131 register REG. If REG is 0, a new pseudo is generated.
13133 There are two types of references that must be handled:
13135 1. Global data references must load the address from the GOT, via
13136 the PIC reg. An insn is emitted to do this load, and the reg is
13137 returned.
13139 2. Static data references, constant pool addresses, and code labels
13140 compute the address as an offset from the GOT, whose base is in
13141 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13142 differentiate them from global data objects. The returned
13143 address is the PIC reg + an unspec constant.
13145 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13146 reg also appears in the address. */
13148 static rtx
13150 {
13154 #if TARGET_MACHO
13156 {
13159 /* Use the generic Mach-O PIC machinery. */
13161 }
13162 #endif
13165 {
13169 }
13175 {
13176 rtx tmpreg;
13177 /* This symbol may be referenced via a displacement from the PIC
13178 base address (@GOTOFF). */
13185 {
13187 UNSPEC_GOTOFF);
13189 }
13190 else
13195 else
13200 {
13204 }
13205 else
13207 }
13209 {
13210 /* This symbol may be referenced via a displacement from the PIC
13211 base address (@GOTOFF). */
13218 {
13220 UNSPEC_GOTOFF);
13222 }
13223 else
13229 {
13232 }
13233 }
13235 /* We can't use @GOTOFF for text labels on VxWorks;
13236 see gotoff_operand. */
13238 {
13243 /* For x64 PE-COFF there is no GOT table. So we use address
13244 directly. */
13246 {
13254 }
13256 {
13264 /* Use directly gen_movsi, otherwise the address is loaded
13265 into register for CSE. We don't want to CSE this addresses,
13266 instead we CSE addresses from the GOT table, so skip this. */
13269 }
13270 else
13271 {
13272 /* This symbol must be referenced via a load from the
13273 Global Offset Table (@GOT). */
13289 }
13290 }
13291 else
13292 {
13295 {
13297 {
13300 }
13301 else
13303 }
13305 {
13308 /* We must match stuff we generate before. Assume the only
13309 unspecs that can get here are ours. Not that we could do
13310 anything with them anyway.... */
13316 }
13318 {
13321 /* Check first to see if this is a constant offset from a @GOTOFF
13322 symbol reference. */
13325 {
13327 {
13331 UNSPEC_GOTOFF);
13337 {
13340 }
13341 }
13342 else
13343 {
13346 {
13350 }
13351 }
13352 }
13353 else
13354 {
13357 new_rtx
13361 {
13364 {
13367 new_rtx
13369 }
13370 else
13372 }
13373 else
13374 {
13377 {
13380 }
13382 }
13383 }
13384 }
13385 }
13387 }
13388 \f
13389 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13391 static rtx
13393 {
13397 {
13402 }
13408 }
13410 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13414 static rtx
13416 {
13418 {
13424 }
13427 {
13429 UNSPEC_PLTOFF);
13432 }
13435 }
13437 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13441 rtx
13443 {
13445 {
13446 ix86_tls_module_base_symbol
13451 }
13454 }
13456 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13457 false if we expect this to be used for a memory address and true if
13458 we expect to load the address into a register. */
13460 static rtx
13462 {
13468 /* Fall back to global dynamic model if tool chain cannot support local
13469 dynamic. */
13476 {
13481 {
13484 else
13485 {
13488 }
13489 }
13492 {
13495 else
13505 }
13506 else
13507 {
13511 {
13516 emit_call_insn
13526 }
13527 else
13529 }
13536 {
13539 else
13540 {
13543 }
13544 }
13547 {
13552 else
13558 }
13559 else
13560 {
13564 {
13567 rtx eqv;
13570 emit_call_insn
13575 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13576 share the LD_BASE result with other LD model accesses. */
13578 UNSPEC_TLS_LD_BASE);
13582 }
13583 else
13585 }
13593 {
13600 }
13605 {
13607 {
13608 /* The Sun linker took the AMD64 TLS spec literally
13609 and can only handle %rax as destination of the
13610 initial executable code sequence. */
13615 }
13617 /* Generate DImode references to avoid %fs:(%reg32)
13618 problems and linker IE->LE relaxation bug. */
13622 }
13624 {
13629 }
13631 {
13635 }
13636 else
13637 {
13640 }
13650 {
13655 }
13656 else
13657 {
13661 }
13671 {
13675 }
13676 else
13677 {
13681 }
13686 }
13689 }
13691 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13692 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13693 unique refptr-DECL symbol corresponding to symbol DECL. */
13696 htab_t dllimport_map;
13698 static tree
13700 {
13707 tree to;
13708 rtx rtl;
13735 else
13748 {
13750 #ifdef SUB_TARGET_RECORD_STUB
13752 #endif
13753 }
13762 }
13764 /* Expand SYMBOL into its corresponding far-addresse symbol.
13765 WANT_REG is true if we require the result be a register. */
13767 static rtx
13769 {
13770 tree imp_decl;
13771 rtx x;
13780 }
13782 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13783 true if we require the result be a register. */
13785 static rtx
13787 {
13788 tree imp_decl;
13789 rtx x;
13798 }
13800 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13801 is true if we require the result be a register. */
13803 static rtx
13805 {
13810 {
13817 {
13820 }
13821 }
13837 {
13840 }
13842 }
13844 /* Try machine-dependent ways of modifying an illegitimate address
13845 to be legitimate. If we find one, return the new, valid address.
13846 This macro is used in only one place: `memory_address' in explow.c.
13848 OLDX is the address as it was before break_out_memory_refs was called.
13849 In some cases it is useful to look at this to decide what needs to be done.
13851 It is always safe for this macro to do nothing. It exists to recognize
13852 opportunities to optimize the output.
13854 For the 80386, we handle X+REG by loading X into a register R and
13855 using R+REG. R will go in a general reg and indexing will be used.
13856 However, if REG is a broken-out memory address or multiplication,
13857 nothing needs to be done because REG can certainly go in a general reg.
13859 When -fpic is used, special handling is needed for symbolic references.
13860 See comments by legitimize_pic_address in i386.c for details. */
13862 static rtx
13864 {
13875 {
13879 }
13882 {
13886 }
13891 #if TARGET_MACHO
13894 #endif
13896 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13900 {
13905 }
13908 {
13909 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13914 {
13920 }
13925 {
13931 }
13933 /* Put multiply first if it isn't already. */
13935 {
13940 }
13942 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13943 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13944 created by virtual register instantiation, register elimination, and
13945 similar optimizations. */
13947 {
13953 }
13955 /* Canonicalize
13956 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13957 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13962 {
13963 rtx constant;
13967 {
13970 }
13972 {
13975 }
13976 else
13980 {
13987 }
13988 }
13994 {
13997 }
14000 {
14003 }
14011 {
14014 }
14020 {
14024 {
14027 }
14031 }
14034 {
14038 {
14041 }
14045 }
14046 }
14049 }
14050 \f
14051 /* Print an integer constant expression in assembler syntax. Addition
14052 and subtraction are the only arithmetic that may appear in these
14053 expressions. FILE is the stdio stream to write to, X is the rtx, and
14054 CODE is the operand print code from the output string. */
14056 static void
14058 {
14062 {
14071 else
14072 {
14075 /* Mark the decl as referenced so that cgraph will
14076 output the function. */
14080 #if TARGET_MACHO
14084 #endif
14086 }
14094 /* FALLTHRU */
14105 /* This used to output parentheses around the expression,
14106 but that does not work on the 386 (either ATT or BSD assembler). */
14112 {
14113 /* We can use %d if the number is <32 bits and positive. */
14118 else
14120 }
14121 else
14122 /* We can't handle floating point constants;
14123 TARGET_PRINT_OPERAND must handle them. */
14128 /* Some assemblers need integer constants to appear first. */
14130 {
14134 }
14135 else
14136 {
14141 }
14156 {
14160 }
14165 {
14184 /* FIXME: This might be @TPOFF in Sun ld too. */
14193 else
14203 else
14209 #if TARGET_MACHO
14214 #endif
14218 }
14223 }
14224 }
14226 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14227 We need to emit DTP-relative relocations. */
14229 static void ATTRIBUTE_UNUSED
14231 {
14236 {
14244 }
14245 }
14247 /* Return true if X is a representation of the PIC register. This copes
14248 with calls from ix86_find_base_term, where the register might have
14249 been replaced by a cselib value. */
14251 static bool
14253 {
14257 else
14259 }
14261 /* Helper function for ix86_delegitimize_address.
14262 Attempt to delegitimize TLS local-exec accesses. */
14264 static rtx
14266 {
14291 {
14296 }
14302 }
14304 /* In the name of slightly smaller debug output, and to cater to
14305 general assembler lossage, recognize PIC+GOTOFF and turn it back
14306 into a direct symbol reference.
14308 On Darwin, this is necessary to avoid a crash, because Darwin
14309 has a different PIC label for each routine but the DWARF debugging
14310 information is not associated with any particular routine, so it's
14311 necessary to remove references to the PIC label from RTL stored by
14312 the DWARF output code. */
14314 static rtx
14316 {
14318 /* addend is NULL or some rtx if x is something+GOTOFF where
14319 something doesn't include the PIC register. */
14321 /* reg_addend is NULL or a multiple of some register. */
14323 /* const_addend is NULL or a const_int. */
14325 /* This is the result, or NULL. */
14334 {
14341 {
14347 }
14354 {
14357 {
14362 }
14364 }
14369 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14370 and -mcmodel=medium -fpic. */
14371 }
14378 /* %ebx + GOT/GOTOFF */
14379 ;
14381 {
14382 /* %ebx + %reg * scale + GOT/GOTOFF */
14388 else
14389 {
14392 }
14393 }
14394 else
14400 {
14403 }
14424 {
14425 /* If the rest of original X doesn't involve the PIC register, add
14426 addend and subtract pic_offset_table_rtx. This can happen e.g.
14427 for code like:
14428 leal (%ebx, %ecx, 4), %ecx
14429 ...
14430 movl foo@GOTOFF(%ecx), %edx
14431 in which case we return (%ecx - %ebx) + foo. */
14434 pic_offset_table_rtx),
14435 result);
14436 else
14438 }
14440 {
14444 }
14446 }
14448 /* If X is a machine specific address (i.e. a symbol or label being
14449 referenced as a displacement from the GOT implemented using an
14450 UNSPEC), then return the base term. Otherwise return X. */
14452 rtx
14454 {
14455 rtx term;
14458 {
14472 }
14475 }
14476 \f
14477 static void
14480 {
14484 {
14487 }
14492 {
14495 {
14514 }
14518 {
14537 }
14544 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14545 Those same assemblers have the same but opposite lossage on cmov. */
14548 else
14553 {
14566 }
14573 else
14578 {
14591 }
14598 else
14608 else
14619 }
14621 }
14623 /* Print the name of register X to FILE based on its machine mode and number.
14624 If CODE is 'w', pretend the mode is HImode.
14625 If CODE is 'b', pretend the mode is QImode.
14626 If CODE is 'k', pretend the mode is SImode.
14627 If CODE is 'q', pretend the mode is DImode.
14628 If CODE is 'x', pretend the mode is V4SFmode.
14629 If CODE is 't', pretend the mode is V8SFmode.
14630 If CODE is 'g', pretend the mode is V16SFmode.
14631 If CODE is 'h', pretend the reg is the 'high' byte register.
14632 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14633 If CODE is 'd', duplicate the operand for AVX instruction.
14634 */
14636 void
14638 {
14647 {
14651 }
14678 else
14681 /* Irritatingly, AMD extended registers use different naming convention
14682 from the normal registers: "r%d[bwd]" */
14684 {
14689 {
14703 /* no suffix */
14708 }
14710 }
14714 {
14717 {
14720 }
14721 /* FALLTHRU */
14727 /* FALLTHRU */
14730 normal:
14745 {
14750 }
14753 {
14758 }
14762 }
14766 {
14769 else
14771 }
14772 }
14774 /* Locate some local-dynamic symbol still in use by this function
14775 so that we can print its name in some tls_local_dynamic_base
14776 pattern. */
14778 static int
14780 {
14785 {
14788 }
14791 }
14795 {
14807 }
14809 /* Meaning of CODE:
14810 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14811 C -- print opcode suffix for set/cmov insn.
14812 c -- like C, but print reversed condition
14813 F,f -- likewise, but for floating-point.
14814 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14815 otherwise nothing
14816 R -- print embeded rounding and sae.
14817 r -- print only sae.
14818 z -- print the opcode suffix for the size of the current operand.
14819 Z -- likewise, with special suffixes for x87 instructions.
14820 * -- print a star (in certain assembler syntax)
14821 A -- print an absolute memory reference.
14822 E -- print address with DImode register names if TARGET_64BIT.
14823 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14824 s -- print a shift double count, followed by the assemblers argument
14825 delimiter.
14826 b -- print the QImode name of the register for the indicated operand.
14827 %b0 would print %al if operands[0] is reg 0.
14828 w -- likewise, print the HImode name of the register.
14829 k -- likewise, print the SImode name of the register.
14830 q -- likewise, print the DImode name of the register.
14831 x -- likewise, print the V4SFmode name of the register.
14832 t -- likewise, print the V8SFmode name of the register.
14833 g -- likewise, print the V16SFmode name of the register.
14834 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14835 y -- print "st(0)" instead of "st" as a register.
14836 d -- print duplicated register operand for AVX instruction.
14837 D -- print condition for SSE cmp instruction.
14838 P -- if PIC, print an @PLT suffix.
14839 p -- print raw symbol name.
14840 X -- don't print any sort of PIC '@' suffix for a symbol.
14841 & -- print some in-use local-dynamic symbol name.
14842 H -- print a memory address offset by 8; used for sse high-parts
14843 Y -- print condition for XOP pcom* instruction.
14844 + -- print a branch hint as 'cs' or 'ds' prefix
14845 ; -- print a semicolon (after prefixes due to bug in older gas).
14846 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14847 @ -- print a segment register of thread base pointer load
14848 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14849 */
14851 void
14853 {
14855 {
14857 {
14860 {
14866 /* Intel syntax. For absolute addresses, registers should not
14867 be surrounded by braces. */
14869 {
14874 }
14879 }
14885 /* Wrap address in an UNSPEC to declare special handling. */
14923 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14928 {
14942 output_operand_lossage
14945 }
14948 #endif
14953 {
14954 /* Opcodes don't get size suffixes if using Intel opcodes. */
14959 {
14977 output_operand_lossage
14980 }
14981 }
14984 warning
14986 /* FALLTHRU */
14989 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14994 {
14996 {
14998 #ifdef HAVE_AS_IX86_FILDS
15000 #endif
15008 #ifdef HAVE_AS_IX86_FILDQ
15010 #else
15012 #endif
15017 }
15018 }
15020 {
15021 /* 387 opcodes don't get size suffixes
15022 if the operands are registers. */
15027 {
15043 }
15044 }
15045 else
15046 {
15047 output_operand_lossage
15050 }
15052 output_operand_lossage
15073 {
15076 }
15081 {
15132 }
15136 /* Little bit of braindamage here. The SSE compare instructions
15137 does use completely different names for the comparisons that the
15138 fp conditional moves. */
15140 {
15143 {
15146 }
15152 {
15155 }
15161 {
15164 }
15173 {
15176 }
15182 {
15185 }
15191 {
15194 }
15205 }
15210 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15213 #endif
15218 {
15222 }
15226 file);
15231 {
15235 }
15236 /* It doesn't actually matter what mode we use here, as we're
15237 only going to use this for printing. */
15239 /* Output 'qword ptr' for intel assembler dialect. */
15248 #ifdef HAVE_AS_IX86_HLE
15250 #else
15252 #endif
15254 #ifdef HAVE_AS_IX86_HLE
15256 #else
15258 #endif
15259 /* We do not want to print value of the operand. */
15288 {
15303 }
15316 {
15321 else
15324 }
15327 {
15328 rtx x;
15337 {
15342 {
15344 bool cputaken
15347 /* Emit hints only in the case default branch prediction
15348 heuristics would fail. */
15350 {
15351 /* We use 3e (DS) prefix for taken branches and
15352 2e (CS) prefix for not taken branches. */
15355 else
15357 }
15358 }
15359 }
15361 }
15364 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15366 #endif
15373 /* The kernel uses a different segment register for performance
15374 reasons; a system call would not have to trash the userspace
15375 segment register, which would be expensive. */
15378 else
15393 }
15394 }
15400 {
15401 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15404 {
15407 {
15416 else
15423 }
15425 /* Check for explicit size override (codes 'b', 'w', 'k',
15426 'q' and 'x') */
15440 }
15443 /* Avoid (%rip) for call operands. */
15449 else
15451 }
15454 {
15455 REAL_VALUE_TYPE r;
15463 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15467 else
15469 }
15472 {
15473 REAL_VALUE_TYPE r;
15482 }
15484 /* These float cases don't actually occur as immediate operands. */
15486 {
15491 }
15493 else
15494 {
15495 /* We have patterns that allow zero sets of memory, for instance.
15496 In 64-bit mode, we should probably support all 8-byte vectors,
15497 since we can in fact encode that into an immediate. */
15499 {
15502 }
15505 {
15507 {
15510 }
15513 {
15516 else
15518 }
15519 }
15524 else
15526 }
15527 }
15529 static bool
15531 {
15534 }
15535 \f
15536 /* Print a memory operand whose address is ADDR. */
15538 static void
15540 {
15549 {
15556 }
15558 {
15562 }
15563 else
15574 {
15585 }
15587 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15589 {
15601 }
15603 {
15604 /* Displacement only requires special attention. */
15607 {
15611 }
15614 else
15616 }
15617 else
15618 {
15619 /* Print SImode register names to force addr32 prefix. */
15621 {
15622 #ifdef ENABLE_CHECKING
15625 {
15636 }
15637 #endif
15640 }
15642 && TARGET_X32
15643 && disp
15646 {
15647 /* X32 runs in 64-bit mode, where displacement, DISP, in
15648 address DISP(%r64), is encoded as 32-bit immediate sign-
15649 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15650 address is %r64 + 0xffffffffbffffd00. When %r64 <
15651 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15652 which is invalid for x32. The correct address is %r64
15653 - 0x40000300 == 0xf7ffdd64. To properly encode
15654 -0x40000300(%r64) for x32, we zero-extend negative
15655 displacement by forcing addr32 prefix which truncates
15656 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15657 zero-extend all negative displacements, including -1(%rsp).
15658 However, for small negative displacements, sign-extension
15659 won't cause overflow. We only zero-extend negative
15660 displacements if they < -16*1024*1024, which is also used
15661 to check legitimate address displacements for PIC. */
15663 }
15666 {
15668 {
15673 else
15675 }
15681 {
15686 }
15688 }
15689 else
15690 {
15694 {
15695 /* Pull out the offset of a symbol; print any symbol itself. */
15699 {
15703 }
15711 else
15713 }
15717 {
15720 {
15724 }
15725 }
15728 else
15732 {
15737 }
15739 }
15740 }
15741 }
15743 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15745 static bool
15747 {
15748 rtx op;
15755 {
15758 /* FIXME: This might be @TPOFF in Sun ld. */
15769 else
15781 else
15788 #if TARGET_MACHO
15794 #endif
15797 {
15802 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15804 #else
15806 #endif
15809 }
15814 }
15817 }
15818 \f
15819 /* Split one or more double-mode RTL references into pairs of half-mode
15820 references. The RTL can be REG, offsettable MEM, integer constant, or
15821 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15822 split and "num" is its length. lo_half and hi_half are output arrays
15823 that parallel "operands". */
15825 void
15828 {
15833 {
15842 }
15847 {
15850 /* simplify_subreg refuse to split volatile memory addresses,
15851 but we still have to handle it. */
15853 {
15856 }
15857 else
15858 {
15865 }
15866 }
15867 }
15868 \f
15869 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15870 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15871 is the expression of the binary operation. The output may either be
15872 emitted here, or returned to the caller, like all output_* functions.
15874 There is no guarantee that the operands are the same mode, as they
15875 might be within FLOAT or FLOAT_EXTEND expressions. */
15877 #ifndef SYSV386_COMPAT
15878 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15879 wants to fix the assemblers because that causes incompatibility
15880 with gcc. No-one wants to fix gcc because that causes
15881 incompatibility with assemblers... You can use the option of
15882 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15883 #define SYSV386_COMPAT 1
15884 #endif
15888 {
15894 #ifdef ENABLE_CHECKING
15895 /* Even if we do not want to check the inputs, this documents input
15896 constraints. Which helps in understanding the following code. */
15906 else
15908 #endif
15911 {
15916 else
15925 else
15934 else
15943 else
15950 }
15953 {
15955 {
15959 else
15961 }
15962 else
15963 {
15967 else
15969 }
15971 }
15975 {
15979 {
15983 }
15985 /* know operands[0] == operands[1]. */
15988 {
15991 }
15994 {
15996 /* How is it that we are storing to a dead operand[2]?
15997 Well, presumably operands[1] is dead too. We can't
15998 store the result to st(0) as st(0) gets popped on this
15999 instruction. Instead store to operands[2] (which I
16000 think has to be st(1)). st(1) will be popped later.
16001 gcc <= 2.8.1 didn't have this check and generated
16002 assembly code that the Unixware assembler rejected. */
16004 else
16007 }
16011 else
16018 {
16021 }
16024 {
16027 }
16030 {
16031 #if SYSV386_COMPAT
16032 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16033 derived assemblers, confusingly reverse the direction of
16034 the operation for fsub{r} and fdiv{r} when the
16035 destination register is not st(0). The Intel assembler
16036 doesn't have this brain damage. Read !SYSV386_COMPAT to
16037 figure out what the hardware really does. */
16040 else
16042 #else
16044 /* As above for fmul/fadd, we can't store to st(0). */
16046 else
16048 #endif
16050 }
16053 {
16054 #if SYSV386_COMPAT
16057 else
16059 #else
16062 else
16064 #endif
16066 }
16069 {
16072 else
16075 }
16077 {
16078 #if SYSV386_COMPAT
16080 #else
16082 #endif
16083 }
16084 else
16085 {
16086 #if SYSV386_COMPAT
16088 #else
16090 #endif
16091 }
16096 }
16100 }
16102 /* Check if a 256bit AVX register is referenced inside of EXP. */
16104 static int
16106 {
16117 }
16119 /* Return needed mode for entity in optimize_mode_switching pass. */
16121 static int
16123 {
16125 {
16126 rtx link;
16128 /* Needed mode is set to AVX_U128_CLEAN if there are
16129 no 256bit modes used in function arguments. */
16131 link;
16133 {
16135 {
16140 }
16141 }
16144 }
16146 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16147 changes state only when a 256bit register is written to, but we need
16148 to prevent the compiler from moving optimal insertion point above
16149 eventual read from 256bit register. */
16154 }
16156 /* Return mode that i387 must be switched into
16157 prior to the execution of insn. */
16159 static int
16161 {
16164 /* The mode UNINITIALIZED is used to store control word after a
16165 function call or ASM pattern. The mode ANY specify that function
16166 has no requirements on the control word and make no changes in the
16167 bits we are interested in. */
16181 {
16204 }
16207 }
16209 /* Return mode that entity must be switched into
16210 prior to the execution of insn. */
16212 static int
16214 {
16216 {
16226 }
16228 }
16230 /* Check if a 256bit AVX register is referenced in stores. */
16232 static void
16234 {
16236 {
16239 }
16240 }
16242 /* Calculate mode of upper 128bit AVX registers after the insn. */
16244 static int
16246 {
16253 /* We know that state is clean after CALL insn if there are no
16254 256bit registers used in the function return register. */
16256 {
16261 }
16263 /* Otherwise, return current mode. Remember that if insn
16264 references AVX 256bit registers, the mode was already changed
16265 to DIRTY from MODE_NEEDED. */
16267 }
16269 /* Return the mode that an insn results in. */
16271 int
16273 {
16275 {
16285 }
16286 }
16288 static int
16290 {
16291 tree arg;
16293 /* Entry mode is set to AVX_U128_DIRTY if there are
16294 256bit modes used in function arguments. */
16297 {
16302 }
16305 }
16307 /* Return a mode that ENTITY is assumed to be
16308 switched to at function entry. */
16310 static int
16312 {
16314 {
16324 }
16325 }
16327 static int
16329 {
16332 /* Exit mode is set to AVX_U128_DIRTY if there are
16333 256bit modes used in the function return register. */
16338 }
16340 /* Return a mode that ENTITY is assumed to be
16341 switched to at function exit. */
16343 static int
16345 {
16347 {
16357 }
16358 }
16360 static int
16362 {
16364 }
16366 /* Output code to initialize control word copies used by trunc?f?i and
16367 rounding patterns. CURRENT_MODE is set to current control word,
16368 while NEW_MODE is set to new control word. */
16370 static void
16372 {
16374 rtx new_mode;
16385 {
16387 {
16389 /* round toward zero (truncate) */
16395 /* round down toward -oo */
16402 /* round up toward +oo */
16409 /* mask precision exception for nearbyint() */
16416 }
16417 }
16418 else
16419 {
16421 {
16423 /* round toward zero (truncate) */
16429 /* round down toward -oo */
16435 /* round up toward +oo */
16441 /* mask precision exception for nearbyint() */
16448 }
16449 }
16455 }
16457 /* Emit vzeroupper. */
16459 void
16461 {
16464 /* Cancel automatic vzeroupper insertion if there are
16465 live call-saved SSE registers at the insertion point. */
16477 }
16479 /* Generate one or more insns to set ENTITY to MODE. */
16481 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16482 is the set of hard registers live at the point where the insn(s)
16483 are to be inserted. */
16485 static void
16487 HARD_REG_SET regs_live)
16488 {
16490 {
16505 }
16506 }
16508 /* Output code for INSN to convert a float to a signed int. OPERANDS
16509 are the insn operands. The output may be [HSD]Imode and the input
16510 operand may be [SDX]Fmode. */
16514 {
16519 /* Jump through a hoop or two for DImode, since the hardware has no
16520 non-popping instruction. We used to do this a different way, but
16521 that was somewhat fragile and broke with post-reload splitters. */
16531 else
16532 {
16537 else
16541 }
16544 }
16546 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16547 have the values zero or one, indicates the ffreep insn's operand
16548 from the OPERANDS array. */
16552 {
16554 #ifdef HAVE_AS_IX86_FFREEP
16556 #else
16557 {
16567 }
16568 #endif
16571 }
16574 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16575 should be used. UNORDERED_P is true when fucom should be used. */
16579 {
16585 {
16588 }
16589 else
16590 {
16593 }
16596 {
16600 else
16602 else
16605 else
16607 }
16614 {
16616 {
16619 }
16620 else
16622 }
16625 && stack_top_dies
16628 {
16629 /* If both the top of the 387 stack dies, and the other operand
16630 is also a stack register that dies, then this must be a
16631 `fcompp' float compare */
16634 {
16635 /* There is no double popping fcomi variant. Fortunately,
16636 eflags is immune from the fstp's cc clobbering. */
16639 else
16642 }
16643 else
16644 {
16647 else
16649 }
16650 }
16651 else
16652 {
16653 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16656 {
16664 NULL,
16665 NULL,
16672 NULL,
16673 NULL,
16674 NULL,
16675 NULL
16676 };
16691 }
16692 }
16694 void
16696 {
16699 #ifdef ASM_QUAD
16702 #else
16704 #endif
16707 }
16709 void
16711 {
16714 #ifdef ASM_QUAD
16717 #else
16719 #endif
16720 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16726 #if TARGET_MACHO
16728 {
16732 }
16733 #endif
16734 else
16737 }
16738 \f
16739 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16740 for the target. */
16742 void
16744 {
16745 rtx tmp;
16747 /* We play register width games, which are only valid after reload. */
16750 /* Avoid HImode and its attendant prefix byte. */
16756 {
16759 }
16762 }
16764 /* X is an unchanging MEM. If it is a constant pool reference, return
16765 the constant pool rtx, else NULL. */
16767 rtx
16769 {
16776 }
16778 void
16780 {
16788 {
16789 rtx tmp;
16793 {
16799 }
16802 }
16806 {
16809 rtx tmp;
16814 else
16818 {
16825 }
16826 }
16830 {
16832 {
16833 #if TARGET_MACHO
16834 /* dynamic-no-pic */
16836 {
16837 rtx temp = ((reload_in_progress
16845 }
16847 {
16851 }
16854 else
16855 {
16863 }
16864 /* dynamic-no-pic */
16865 #endif
16866 }
16867 else
16868 {
16872 {
16878 }
16879 }
16880 }
16881 else
16882 {
16893 /* Force large constants in 64bit compilation into register
16894 to get them CSEed. */
16906 {
16907 /* If we are loading a floating point constant to a register,
16908 force the value to memory now, since we'll get better code
16909 out the back end. */
16913 {
16918 }
16919 }
16920 }
16923 }
16925 void
16927 {
16934 /* Force constants other than zero into memory. We do not know how
16935 the instructions used to build constants modify the upper 64 bits
16936 of the register, once we have that information we may be able
16937 to handle some of them more efficiently. */
16946 /* We need to check memory alignment for SSE mode since attribute
16947 can make operands unaligned. */
16952 {
16955 /* ix86_expand_vector_move_misalign() does not like constants ... */
16961 /* ... nor both arguments in memory. */
16969 }
16971 /* Make operand1 a register if it isn't already. */
16975 {
16978 }
16981 }
16983 /* Split 32-byte AVX unaligned load and store if needed. */
16985 static void
16987 {
16988 rtx m;
16995 {
17016 }
17019 {
17021 {
17028 }
17029 /* Normal *mov<mode>_internal pattern will handle
17030 unaligned loads just fine if misaligned_operand
17031 is true, and without the UNSPEC it can be combined
17032 with arithmetic instructions. */
17035 else
17037 }
17039 {
17041 {
17046 }
17047 else
17049 }
17050 else
17052 }
17054 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17055 straight to ix86_expand_vector_move. */
17056 /* Code generation for scalar reg-reg moves of single and double precision data:
17057 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17058 movaps reg, reg
17059 else
17060 movss reg, reg
17061 if (x86_sse_partial_reg_dependency == true)
17062 movapd reg, reg
17063 else
17064 movsd reg, reg
17066 Code generation for scalar loads of double precision data:
17067 if (x86_sse_split_regs == true)
17068 movlpd mem, reg (gas syntax)
17069 else
17070 movsd mem, reg
17072 Code generation for unaligned packed loads of single precision data
17073 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17074 if (x86_sse_unaligned_move_optimal)
17075 movups mem, reg
17077 if (x86_sse_partial_reg_dependency == true)
17078 {
17079 xorps reg, reg
17080 movlps mem, reg
17081 movhps mem+8, reg
17082 }
17083 else
17084 {
17085 movlps mem, reg
17086 movhps mem+8, reg
17087 }
17089 Code generation for unaligned packed loads of double precision data
17090 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17091 if (x86_sse_unaligned_move_optimal)
17092 movupd mem, reg
17094 if (x86_sse_split_regs == true)
17095 {
17096 movlpd mem, reg
17097 movhpd mem+8, reg
17098 }
17099 else
17100 {
17101 movsd mem, reg
17102 movhpd mem+8, reg
17103 }
17104 */
17106 void
17108 {
17117 {
17119 {
17123 {
17125 {
17128 }
17129 else
17131 }
17133 /* FALLTHRU */
17137 {
17152 }
17158 else
17166 }
17169 }
17173 {
17175 {
17179 {
17181 {
17184 }
17185 else
17187 }
17189 /* FALLTHRU */
17199 }
17202 }
17205 {
17206 /* Normal *mov<mode>_internal pattern will handle
17207 unaligned loads just fine if misaligned_operand
17208 is true, and without the UNSPEC it can be combined
17209 with arithmetic instructions. */
17215 /* ??? If we have typed data, then it would appear that using
17216 movdqu is the only way to get unaligned data loaded with
17217 integer type. */
17219 {
17221 {
17224 }
17226 /* We will eventually emit movups based on insn attributes. */
17230 }
17232 {
17233 rtx zero;
17236 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17237 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17239 {
17240 /* We will eventually emit movups based on insn attributes. */
17243 }
17245 /* When SSE registers are split into halves, we can avoid
17246 writing to the top half twice. */
17248 {
17251 }
17252 else
17253 {
17254 /* ??? Not sure about the best option for the Intel chips.
17255 The following would seem to satisfy; the register is
17256 entirely cleared, breaking the dependency chain. We
17257 then store to the upper half, with a dependency depth
17258 of one. A rumor has it that Intel recommends two movsd
17259 followed by an unpacklpd, but this is unconfirmed. And
17260 given that the dependency depth of the unpacklpd would
17261 still be one, I'm not sure why this would be better. */
17263 }
17269 }
17270 else
17271 {
17272 rtx t;
17275 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17276 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17278 {
17280 {
17283 }
17290 }
17294 else
17299 else
17308 }
17309 }
17311 {
17313 {
17316 /* We will eventually emit movups based on insn attributes. */
17318 }
17320 {
17322 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17323 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17325 /* We will eventually emit movups based on insn attributes. */
17327 else
17328 {
17333 }
17334 }
17335 else
17336 {
17341 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17342 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17344 {
17347 }
17348 else
17349 {
17354 }
17355 }
17356 }
17357 else
17359 }
17361 /* Helper function of ix86_fixup_binary_operands to canonicalize
17362 operand order. Returns true if the operands should be swapped. */
17364 static bool
17366 rtx operands[])
17367 {
17372 /* If the operation is not commutative, we can't do anything. */
17376 /* Highest priority is that src1 should match dst. */
17382 /* Next highest priority is that immediate constants come second. */
17388 /* Lowest priority is that memory references should come second. */
17395 }
17398 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17399 destination to use for the operation. If different from the true
17400 destination in operands[0], a copy operation will be required. */
17402 rtx
17404 rtx operands[])
17405 {
17410 /* Canonicalize operand order. */
17412 {
17413 rtx temp;
17415 /* It is invalid to swap operands of different modes. */
17421 }
17423 /* Both source operands cannot be in memory. */
17425 {
17426 /* Optimization: Only read from memory once. */
17428 {
17431 }
17434 else
17436 }
17438 /* If the destination is memory, and we do not have matching source
17439 operands, do things in registers. */
17443 /* Source 1 cannot be a constant. */
17447 /* Source 1 cannot be a non-matching memory. */
17451 /* Improve address combine. */
17460 }
17462 /* Similarly, but assume that the destination has already been
17463 set up properly. */
17465 void
17468 {
17471 }
17473 /* Attempt to expand a binary operator. Make the expansion closer to the
17474 actual machine, then just general_operand, which will allow 3 separate
17475 memory references (one output, two input) in a single insn. */
17477 void
17479 rtx operands[])
17480 {
17487 /* Emit the instruction. */
17491 {
17492 /* Reload doesn't know about the flags register, and doesn't know that
17493 it doesn't want to clobber it. We can only do this with PLUS. */
17496 }
17500 {
17501 /* This is going to be an LEA; avoid splitting it later. */
17503 }
17504 else
17505 {
17508 }
17510 /* Fix up the destination if needed. */
17513 }
17515 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17516 the given OPERANDS. */
17518 void
17520 rtx operands[])
17521 {
17524 {
17527 }
17529 {
17532 }
17533 /* Optimize (__m128i) d | (__m128i) e and similar code
17534 when d and e are float vectors into float vector logical
17535 insn. In C/C++ without using intrinsics there is no other way
17536 to express vector logical operation on float vectors than
17537 to cast them temporarily to integer vectors. */
17539 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17548 {
17549 rtx dst;
17551 {
17558 {
17561 }
17562 else
17563 {
17568 }
17579 }
17580 }
17589 }
17591 /* Return TRUE or FALSE depending on whether the binary operator meets the
17592 appropriate constraints. */
17594 bool
17597 {
17602 /* Both source operands cannot be in memory. */
17606 /* Canonicalize operand order for commutative operators. */
17608 {
17612 }
17614 /* If the destination is memory, we must have a matching source operand. */
17618 /* Source 1 cannot be a constant. */
17622 /* Source 1 cannot be a non-matching memory. */
17624 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17632 }
17634 /* Attempt to expand a unary operator. Make the expansion closer to the
17635 actual machine, then just general_operand, which will allow 2 separate
17636 memory references (one output, one input) in a single insn. */
17638 void
17640 rtx operands[])
17641 {
17648 /* If the destination is memory, and we do not have matching source
17649 operands, do things in registers. */
17652 {
17655 else
17657 }
17659 /* When source operand is memory, destination must match. */
17663 /* Emit the instruction. */
17667 {
17668 /* Reload doesn't know about the flags register, and doesn't know that
17669 it doesn't want to clobber it. */
17672 }
17673 else
17674 {
17677 }
17679 /* Fix up the destination if needed. */
17682 }
17684 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17685 divisor are within the range [0-255]. */
17687 void
17690 {
17699 {
17712 }
17719 /* Use 8bit unsigned divimod if dividend and divisor are within
17720 the range [0-255]. */
17729 pc_rtx);
17734 /* Generate original signed/unsigned divimod. */
17739 /* Branch to the end. */
17743 /* Generate 8bit unsigned divide. */
17745 /* Don't use operands[0] for result of 8bit divide since not all
17746 registers support QImode ZERO_EXTRACT. */
17753 {
17756 }
17757 else
17758 {
17761 }
17763 /* Extract remainder from AH. */
17767 else
17768 {
17769 /* Need a new scratch register since the old one has result
17770 of 8bit divide. */
17774 }
17777 /* Zero extend quotient from AL. */
17783 }
17785 /* Whether it is OK to emit CFI directives when emitting asm code. */
17787 bool
17789 {
17791 }
17793 #define LEA_MAX_STALL (3)
17794 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17796 /* Increase given DISTANCE in half-cycles according to
17797 dependencies between PREV and NEXT instructions.
17798 Add 1 half-cycle if there is no dependency and
17799 go to next cycle if there is some dependecy. */
17801 static unsigned int
17803 {
17819 }
17821 /* Function checks if instruction INSN defines register number
17822 REGNO1 or REGNO2. */
17824 static bool
17826 rtx insn)
17827 {
17828 df_ref def;
17838 }
17840 /* Function checks if instruction INSN uses register number
17841 REGNO as a part of address expression. */
17843 static bool
17845 {
17846 df_ref use;
17853 }
17855 /* Search backward for non-agu definition of register number REGNO1
17856 or register number REGNO2 in basic block starting from instruction
17857 START up to head of basic block or instruction INSN.
17859 Function puts true value into *FOUND var if definition was found
17860 and false otherwise.
17862 Distance in half-cycles between START and found instruction or head
17863 of BB is added to DISTANCE and returned. */
17865 static int
17869 {
17879 {
17881 {
17884 {
17887 {
17890 }
17891 }
17894 }
17899 }
17902 }
17904 /* Search backward for non-agu definition of register number REGNO1
17905 or register number REGNO2 in INSN's basic block until
17906 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17907 2. Reach neighbour BBs boundary, or
17908 3. Reach agu definition.
17909 Returns the distance between the non-agu definition point and INSN.
17910 If no definition point, returns -1. */
17912 static int
17915 {
17926 {
17927 edge e;
17928 edge_iterator ei;
17933 {
17936 }
17942 else
17943 {
17948 {
17949 int bb_dist
17955 {
17962 }
17963 }
17966 }
17967 }
17969 /* get_attr_type may modify recog data. We want to make sure
17970 that recog data is valid for instruction INSN, on which
17971 distance_non_agu_define is called. INSN is unchanged here. */
17978 }
17980 /* Return the distance in half-cycles between INSN and the next
17981 insn that uses register number REGNO in memory address added
17982 to DISTANCE. Return -1 if REGNO0 is set.
17984 Put true value into *FOUND if register usage was found and
17985 false otherwise.
17986 Put true value into *REDEFINED if register redefinition was
17987 found and false otherwise. */
17989 static int
17993 {
18002 {
18005 /* If insn and start belong to the same bb, set prev to insn,
18006 so the call to increase_distance will increase the distance
18007 between insns by 1. */
18009 }
18014 {
18016 {
18019 {
18020 /* Return DISTANCE if OP0 is used in memory
18021 address in NEXT. */
18024 }
18027 {
18028 /* Return -1 if OP0 is set in NEXT. */
18031 }
18034 }
18040 }
18043 }
18045 /* Return the distance between INSN and the next insn that uses
18046 register number REGNO0 in memory address. Return -1 if no such
18047 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18049 static int
18051 {
18063 {
18064 edge e;
18065 edge_iterator ei;
18070 {
18073 }
18079 else
18080 {
18086 {
18087 int bb_dist
18092 {
18099 }
18100 }
18103 }
18104 }
18110 }
18112 /* Define this macro to tune LEA priority vs ADD, it take effect when
18113 there is a dilemma of choicing LEA or ADD
18114 Negative value: ADD is more preferred than LEA
18115 Zero: Netrual
18116 Positive value: LEA is more preferred than ADD*/
18117 #define IX86_LEA_PRIORITY 0
18119 /* Return true if usage of lea INSN has performance advantage
18120 over a sequence of instructions. Instructions sequence has
18121 SPLIT_COST cycles higher latency than lea latency. */
18123 static bool
18126 {
18129 /* For Silvermont if using a 2-source or 3-source LEA for
18130 non-destructive destination purposes, or due to wanting
18131 ability to use SCALE, the use of LEA is justified. */
18133 {
18141 }
18147 {
18148 /* If there is no non AGU operand definition, no AGU
18149 operand usage and split cost is 0 then both lea
18150 and non lea variants have same priority. Currently
18151 we prefer lea for 64 bit code and non lea on 32 bit
18152 code. */
18155 else
18157 }
18159 /* With longer definitions distance lea is more preferable.
18160 Here we change it to take into account splitting cost and
18161 lea priority. */
18164 /* If there is no use in memory addess then we just check
18165 that split cost exceeds AGU stall. */
18169 /* If this insn has both backward non-agu dependence and forward
18170 agu dependence, the one with short distance takes effect. */
18172 }
18174 /* Return true if it is legal to clobber flags by INSN and
18175 false otherwise. */
18177 static bool
18179 {
18181 df_ref use;
18182 bitmap live;
18185 {
18187 {
18194 }
18200 }
18204 }
18206 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18207 move and add to avoid AGU stalls. */
18209 bool
18211 {
18214 /* Check if we need to optimize. */
18218 /* Check it is correct to split here. */
18226 /* We need to split only adds with non destructive
18227 destination operand. */
18230 else
18232 }
18234 /* Return true if we should emit lea instruction instead of mov
18235 instruction. */
18237 bool
18239 {
18242 /* Check if we need to optimize. */
18246 /* Use lea for reg to reg moves only. */
18254 }
18256 /* Return true if we need to split lea into a sequence of
18257 instructions to avoid AGU stalls. */
18259 bool
18261 {
18267 /* Check we need to optimize. */
18271 /* The "at least two components" test below might not catch simple
18272 move or zero extension insns if parts.base is non-NULL and parts.disp
18273 is const0_rtx as the only components in the address, e.g. if the
18274 register is %rbp or %r13. As this test is much cheaper and moves or
18275 zero extensions are the common case, do this check first. */
18281 /* Check if it is OK to split here. */
18288 /* There should be at least two components in the address. */
18293 /* We should not split into add if non legitimate pic
18294 operand is used as displacement. */
18309 /* Compute how many cycles we will add to execution time
18310 if split lea into a sequence of instructions. */
18312 {
18313 /* Have to use mov instruction if non desctructive
18314 destination form is used. */
18318 /* Have to add index to base if both exist. */
18322 /* Have to use shift and adds if scale is 2 or greater. */
18324 {
18329 else
18331 }
18333 /* Have to use add instruction with immediate if
18334 disp is non zero. */
18338 /* Subtract the price of lea. */
18340 }
18344 }
18346 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18347 matches destination. RTX includes clobber of FLAGS_REG. */
18349 static void
18352 {
18359 }
18361 /* Return true if regno1 def is nearest to the insn. */
18363 static bool
18365 {
18372 {
18374 {
18377 }
18383 }
18385 /* None of the regs is defined in the bb. */
18387 }
18389 /* Split lea instructions into a sequence of instructions
18390 which are executed on ALU to avoid AGU stalls.
18391 It is assumed that it is allowed to clobber flags register
18392 at lea position. */
18394 void
18396 {
18412 {
18415 }
18418 {
18421 }
18427 {
18428 /* Case r1 = r1 + ... */
18430 {
18431 /* If we have a case r1 = r1 + C * r2 then we
18432 should use multiplication which is very
18433 expensive. Assume cost model is wrong if we
18434 have such case here. */
18439 }
18440 else
18441 {
18442 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18446 /* Use shift for scaling. */
18455 }
18456 }
18458 {
18461 }
18462 else
18463 {
18465 {
18468 }
18470 {
18473 }
18474 else
18475 {
18480 else
18481 {
18482 rtx tmp1;
18484 /* Find better operand for SET instruction, depending
18485 on which definition is farther from the insn. */
18488 else
18498 }
18501 }
18505 }
18506 }
18508 /* Return true if it is ok to optimize an ADD operation to LEA
18509 operation to avoid flag register consumation. For most processors,
18510 ADD is faster than LEA. For the processors like BONNELL, if the
18511 destination register of LEA holds an actual address which will be
18512 used soon, LEA is better and otherwise ADD is better. */
18514 bool
18516 {
18521 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18529 }
18531 /* Return true if destination reg of SET_BODY is shift count of
18532 USE_BODY. */
18534 static bool
18536 {
18537 rtx set_dest;
18538 rtx shift_rtx;
18541 /* Retrieve destination of SET_BODY. */
18543 {
18552 use_body))
18557 }
18559 /* Retrieve shift count of USE_BODY. */
18561 {
18573 }
18581 {
18584 /* Return true if shift count is dest of SET_BODY. */
18586 {
18587 /* Add check since it can be invoked before register
18588 allocation in pre-reload schedule. */
18594 }
18595 }
18598 }
18600 /* Return true if destination reg of SET_INSN is shift count of
18601 USE_INSN. */
18603 bool
18605 {
18608 }
18610 /* Return TRUE or FALSE depending on whether the unary operator meets the
18611 appropriate constraints. */
18613 bool
18617 {
18618 /* If one of operands is memory, source and destination must match. */
18624 }
18626 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18627 are ok, keeping in mind the possible movddup alternative. */
18629 bool
18631 {
18637 }
18639 /* Post-reload splitter for converting an SF or DFmode value in an
18640 SSE register into an unsigned SImode. */
18642 void
18644 {
18655 /* Load up the value into the low element. We must ensure that the other
18656 elements are valid floats -- zero is the easiest such value. */
18658 {
18661 else
18663 }
18664 else
18665 {
18670 else
18672 }
18692 else
18697 }
18699 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18700 Expects the 64-bit DImode to be supplied in a pair of integral
18701 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18702 -mfpmath=sse, !optimize_size only. */
18704 void
18706 {
18710 rtx x;
18716 {
18719 }
18720 else
18721 {
18725 }
18733 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18736 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18737 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18738 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18739 (0x1.0p84 + double(fp_value_hi_xmm)).
18740 Note these exponents differ by 32. */
18744 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18745 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18754 /* Add the upper and lower DFmode values together. */
18757 else
18758 {
18762 }
18765 }
18767 /* Not used, but eases macroization of patterns. */
18768 void
18770 {
18772 }
18774 /* Convert an unsigned SImode value into a DFmode. Only currently used
18775 for SSE, but applicable anywhere. */
18777 void
18779 {
18780 REAL_VALUE_TYPE TWO31r;
18795 }
18797 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18798 32-bit mode; otherwise we have a direct convert instruction. */
18800 void
18802 {
18803 REAL_VALUE_TYPE TWO32r;
18821 }
18823 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18824 For x86_32, -mfpmath=sse, !optimize_size only. */
18825 void
18827 {
18828 REAL_VALUE_TYPE ONE16r;
18847 }
18849 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18850 a vector of unsigned ints VAL to vector of floats TARGET. */
18852 void
18854 {
18856 REAL_VALUE_TYPE TWO16r;
18863 else
18868 OPTAB_DIRECT);
18879 OPTAB_DIRECT);
18881 OPTAB_DIRECT);
18884 }
18886 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18887 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18888 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18889 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18891 rtx
18893 {
18894 REAL_VALUE_TYPE TWO31r;
18909 {
18915 }
18924 OPTAB_DIRECT);
18925 else
18926 {
18932 OPTAB_DIRECT);
18933 }
18936 }
18938 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18939 then replicate the value for all elements of the vector
18940 register. */
18942 rtx
18944 {
18946 rtvec v;
18950 {
18983 }
18984 }
18986 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18987 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18988 for an SSE register. If VECT is true, then replicate the mask for
18989 all elements of the vector register. If INVERT is true, then create
18990 a mask excluding the sign bit. */
18992 rtx
18994 {
18998 rtx v;
18999 rtx mask;
19001 /* Find the sign bit, sign extended to 2*HWI. */
19003 {
19027 else
19035 {
19038 }
19039 else
19040 {
19041 rtvec vec;
19047 {
19050 }
19051 else
19061 }
19066 }
19071 /* Force this value into the low part of a fp vector constant. */
19080 }
19082 /* Generate code for floating point ABS or NEG. */
19084 void
19086 rtx operands[])
19087 {
19098 {
19104 }
19106 /* NEG and ABS performed with SSE use bitwise mask operations.
19107 Create the appropriate mask now. */
19110 else
19120 {
19122 rtvec par;
19127 else
19128 {
19131 }
19133 }
19134 else
19136 }
19138 /* Expand a copysign operation. Special case operand 0 being a constant. */
19140 void
19142 {
19156 else
19160 {
19167 {
19170 else
19171 {
19175 }
19176 }
19186 else
19190 }
19191 else
19192 {
19202 else
19206 }
19207 }
19209 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19210 be a constant, and so has already been expanded into a vector constant. */
19212 void
19214 {
19230 {
19233 }
19234 }
19236 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19237 so we have to do two masks. */
19239 void
19241 {
19256 {
19257 /* Shouldn't happen often (it's useless, obviously), but when it does
19258 we'd generate incorrect code if we continue below. */
19261 }
19264 {
19275 }
19276 else
19277 {
19279 {
19281 }
19283 {
19287 }
19291 {
19294 }
19296 {
19301 }
19303 }
19307 }
19309 /* Return TRUE or FALSE depending on whether the first SET in INSN
19310 has source and destination with matching CC modes, and that the
19311 CC mode is at least as constrained as REQ_MODE. */
19313 bool
19315 {
19316 rtx set;
19327 {
19337 /* FALLTHRU */
19341 /* FALLTHRU */
19345 /* FALLTHRU */
19359 }
19362 }
19364 /* Generate insn patterns to do an integer compare of OPERANDS. */
19366 static rtx
19368 {
19375 /* This is very simple, but making the interface the same as in the
19376 FP case makes the rest of the code easier. */
19380 /* Return the test that should be put into the flags user, i.e.
19381 the bcc, scc, or cmov instruction. */
19383 }
19385 /* Figure out whether to use ordered or unordered fp comparisons.
19386 Return the appropriate mode to use. */
19388 enum machine_mode
19390 {
19391 /* ??? In order to make all comparisons reversible, we do all comparisons
19392 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19393 all forms trapping and nontrapping comparisons, we can make inequality
19394 comparisons trapping again, since it results in better code when using
19395 FCOM based compares. */
19397 }
19399 enum machine_mode
19401 {
19405 {
19408 }
19411 {
19412 /* Only zero flag is needed. */
19416 /* Codes needing carry flag. */
19419 /* Detect overflow checks. They need just the carry flag. */
19423 else
19428 /* Codes possibly doable only with sign flag when
19429 comparing against zero. */
19434 else
19435 /* For other cases Carry flag is not required. */
19437 /* Codes doable only with sign flag when comparing
19438 against zero, but we miss jump instruction for it
19439 so we need to use relational tests against overflow
19440 that thus needs to be zero. */
19445 else
19447 /* strcmp pattern do (use flags) and combine may ask us for proper
19448 mode. */
19453 }
19454 }
19456 /* Return the fixed registers used for condition codes. */
19458 static bool
19460 {
19464 }
19466 /* If two condition code modes are compatible, return a condition code
19467 mode which is compatible with both. Otherwise, return
19468 VOIDmode. */
19470 static enum machine_mode
19472 {
19489 {
19503 {
19517 }
19521 /* These are only compatible with themselves, which we already
19522 checked above. */
19524 }
19525 }
19528 /* Return a comparison we can do and that it is equivalent to
19529 swap_condition (code) apart possibly from orderedness.
19530 But, never change orderedness if TARGET_IEEE_FP, returning
19531 UNKNOWN in that case if necessary. */
19533 static enum rtx_code
19535 {
19537 {
19548 }
19549 }
19551 /* Return cost of comparison CODE using the best strategy for performance.
19552 All following functions do use number of instructions as a cost metrics.
19553 In future this should be tweaked to compute bytes for optimize_size and
19554 take into account performance of various instructions on various CPUs. */
19556 static int
19558 {
19561 /* The cost of code using bit-twiddling on %ah. */
19563 {
19586 }
19589 {
19596 }
19597 }
19599 /* Return strategy to use for floating-point. We assume that fcomi is always
19600 preferrable where available, since that is also true when looking at size
19601 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19603 enum ix86_fpcmp_strategy
19605 {
19606 /* Do fcomi/sahf based test when profitable. */
19615 }
19617 /* Swap, force into registers, or otherwise massage the two operands
19618 to a fp comparison. The operands are updated in place; the new
19619 comparison code is returned. */
19621 static enum rtx_code
19623 {
19629 /* All of the unordered compare instructions only work on registers.
19630 The same is true of the fcomi compare instructions. The XFmode
19631 compare instructions require registers except when comparing
19632 against zero or when converting operand 1 from fixed point to
19633 floating point. */
19642 {
19645 }
19646 else
19647 {
19648 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19649 things around if they appear profitable, otherwise force op0
19650 into a register. */
19656 {
19659 {
19660 rtx tmp;
19663 }
19664 }
19670 {
19675 {
19678 }
19679 else
19681 }
19682 }
19684 /* Try to rearrange the comparison to make it cheaper. */
19688 {
19689 rtx tmp;
19694 }
19699 }
19701 /* Convert comparison codes we use to represent FP comparison to integer
19702 code that will result in proper branch. Return UNKNOWN if no such code
19703 is available. */
19705 enum rtx_code
19707 {
19709 {
19732 }
19733 }
19735 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19737 static rtx
19739 {
19746 /* Do fcomi/sahf based test when profitable. */
19748 {
19753 tmp);
19761 tmp);
19770 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19777 /* In the unordered case, we have to check C2 for NaN's, which
19778 doesn't happen to work out to anything nice combination-wise.
19779 So do some bit twiddling on the value we've got in AH to come
19780 up with an appropriate set of condition codes. */
19784 {
19788 {
19791 }
19792 else
19793 {
19799 }
19804 {
19809 }
19810 else
19811 {
19814 }
19819 {
19822 }
19823 else
19824 {
19828 }
19833 {
19839 }
19840 else
19841 {
19844 }
19849 {
19854 }
19855 else
19856 {
19859 }
19864 {
19869 }
19870 else
19871 {
19874 }
19888 }
19893 }
19895 /* Return the test that should be put into the flags user, i.e.
19896 the bcc, scc, or cmov instruction. */
19899 const0_rtx);
19900 }
19902 static rtx
19904 {
19905 rtx ret;
19911 {
19914 }
19915 else
19919 }
19921 void
19923 {
19925 rtx tmp;
19928 {
19935 simple:
19939 pc_rtx);
19947 /* Expand DImode branch into multiple compare+branch. */
19948 {
19955 {
19958 }
19965 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19966 avoid two branches. This costs one extra insn, so disable when
19967 optimizing for size. */
19972 {
19990 }
19992 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19993 op1 is a constant and the low word is zero, then we can just
19994 examine the high word. Similarly for low word -1 and
19995 less-or-equal-than or greater-than. */
19999 {
20002 {
20005 }
20009 {
20012 }
20016 }
20018 /* Otherwise, we need two or three jumps. */
20027 {
20041 }
20043 /*
20044 * a < b =>
20045 * if (hi(a) < hi(b)) goto true;
20046 * if (hi(a) > hi(b)) goto false;
20047 * if (lo(a) < lo(b)) goto true;
20048 * false:
20049 */
20061 }
20066 }
20067 }
20069 /* Split branch based on floating point condition. */
20070 void
20073 {
20074 rtx condition;
20075 rtx i;
20078 {
20083 }
20086 tmp);
20094 }
20096 void
20098 {
20099 rtx ret;
20106 }
20108 /* Expand comparison setting or clearing carry flag. Return true when
20109 successful and set pop for the operation. */
20110 static bool
20112 {
20116 /* Do not handle double-mode compares that go through special path. */
20121 {
20122 rtx compare_op;
20127 /* Shortcut: following common codes never translate
20128 into carry flag compares. */
20133 /* These comparisons require zero flag; swap operands so they won't. */
20136 {
20141 }
20143 /* Try to expand the comparison and verify that we end up with
20144 carry flag based comparison. This fails to be true only when
20145 we decide to expand comparison using arithmetic that is not
20146 too common scenario. */
20155 else
20164 }
20170 {
20175 /* Convert a==0 into (unsigned)a<1. */
20184 /* Convert a>b into b<a or a>=b-1. */
20188 {
20190 /* Bail out on overflow. We still can swap operands but that
20191 would force loading of the constant into register. */
20196 }
20197 else
20198 {
20203 }
20206 /* Convert a>=0 into (unsigned)a<0x80000000. */
20224 }
20225 /* Swapping operands may cause constant to appear as first operand. */
20227 {
20231 }
20235 }
20237 bool
20239 {
20242 rtx compare_op;
20264 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20265 HImode insns, we'd be swallowed in word prefix ops. */
20271 {
20275 HOST_WIDE_INT diff;
20278 /* Sign bit compares are better done using shifts than we do by using
20279 sbb. */
20282 {
20283 /* Detect overlap between destination and compare sources. */
20287 {
20288 rtx flags;
20297 {
20299 compare_code
20301 }
20303 /* To simplify rest of code, restrict to the GEU case. */
20305 {
20311 }
20312 else
20313 {
20316 reverse_condition_maybe_unordered
20318 else
20321 }
20330 else
20333 }
20334 else
20335 {
20338 else
20339 {
20344 }
20346 }
20349 {
20350 /*
20351 * cmpl op0,op1
20352 * sbbl dest,dest
20353 * [addl dest, ct]
20354 *
20355 * Size 5 - 8.
20356 */
20361 }
20363 {
20364 /*
20365 * cmpl op0,op1
20366 * sbbl dest,dest
20367 * orl $ct, dest
20368 *
20369 * Size 8.
20370 */
20374 }
20376 {
20377 /*
20378 * cmpl op0,op1
20379 * sbbl dest,dest
20380 * notl dest
20381 * [addl dest, cf]
20382 *
20383 * Size 8 - 11.
20384 */
20390 }
20391 else
20392 {
20393 /*
20394 * cmpl op0,op1
20395 * sbbl dest,dest
20396 * [notl dest]
20397 * andl cf - ct, dest
20398 * [addl dest, ct]
20399 *
20400 * Size 8 - 11.
20401 */
20404 {
20408 }
20418 }
20424 }
20427 {
20430 HOST_WIDE_INT tmp;
20435 {
20438 /* We may be reversing unordered compare to normal compare, that
20439 is not valid in general (we may convert non-trapping condition
20440 to trapping one), however on i386 we currently emit all
20441 comparisons unordered. */
20444 }
20445 else
20446 {
20449 }
20450 }
20455 {
20460 {
20465 }
20466 }
20468 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20472 {
20473 /* If lea code below could be used, only optimize
20474 if it results in a 2 insn sequence. */
20480 {
20481 /*
20482 * notl op1 (if necessary)
20483 * sarl $31, op1
20484 * orl cf, op1
20485 */
20487 {
20491 }
20502 }
20503 }
20511 {
20512 /*
20513 * xorl dest,dest
20514 * cmpl op1,op2
20515 * setcc dest
20516 * lea cf(dest*(ct-cf)),dest
20517 *
20518 * Size 14.
20519 *
20520 * This also catches the degenerate setcc-only case.
20521 */
20523 rtx tmp;
20529 /* On x86_64 the lea instruction operates on Pmode, so we need
20530 to get arithmetics done in proper mode to match. */
20533 else
20534 {
20535 rtx out1;
20538 nops++;
20540 {
20542 nops++;
20543 }
20544 }
20546 {
20548 nops++;
20549 }
20551 {
20554 else
20556 }
20561 }
20563 /*
20564 * General case: Jumpful:
20565 * xorl dest,dest cmpl op1, op2
20566 * cmpl op1, op2 movl ct, dest
20567 * setcc dest jcc 1f
20568 * decl dest movl cf, dest
20569 * andl (cf-ct),dest 1:
20570 * addl ct,dest
20571 *
20572 * Size 20. Size 14.
20573 *
20574 * This is reasonably steep, but branch mispredict costs are
20575 * high on modern cpus, so consider failing only if optimizing
20576 * for space.
20577 */
20582 {
20584 {
20591 {
20594 /* We may be reversing unordered compare to normal compare,
20595 that is not valid in general (we may convert non-trapping
20596 condition to trapping one), however on i386 we currently
20597 emit all comparisons unordered. */
20599 }
20600 else
20601 {
20605 }
20606 }
20609 {
20610 /* notl op1 (if needed)
20611 sarl $31, op1
20612 andl (cf-ct), op1
20613 addl ct, op1
20615 For x < 0 (resp. x <= -1) there will be no notl,
20616 so if possible swap the constants to get rid of the
20617 complement.
20618 True/false will be -1/0 while code below (store flag
20619 followed by decrement) is 0/-1, so the constants need
20620 to be exchanged once more. */
20623 {
20626 }
20627 else
20628 {
20632 }
20635 }
20636 else
20637 {
20641 constm1_rtx,
20643 }
20655 }
20656 }
20659 {
20660 /* Try a few things more with specific constants and a variable. */
20662 optab op;
20668 /* If one of the two operands is an interesting constant, load a
20669 constant with the above and mask it in with a logical operation. */
20672 {
20678 else
20680 }
20682 {
20688 else
20690 }
20691 else
20698 /* Recurse to get the constant loaded. */
20702 /* Mask in the interesting variable. */
20704 OPTAB_WIDEN);
20709 }
20711 /*
20712 * For comparison with above,
20713 *
20714 * movl cf,dest
20715 * movl ct,tmp
20716 * cmpl op1,op2
20717 * cmovcc tmp,dest
20718 *
20719 * Size 15.
20720 */
20742 }
20744 /* Swap, force into registers, or otherwise massage the two operands
20745 to an sse comparison with a mask result. Thus we differ a bit from
20746 ix86_prepare_fp_compare_args which expects to produce a flags result.
20748 The DEST operand exists to help determine whether to commute commutative
20749 operators. The POP0/POP1 operands are updated in place. The new
20750 comparison code is returned, or UNKNOWN if not implementable. */
20752 static enum rtx_code
20755 {
20756 rtx tmp;
20759 {
20762 /* AVX supports all the needed comparisons. */
20765 /* We have no LTGT as an operator. We could implement it with
20766 NE & ORDERED, but this requires an extra temporary. It's
20767 not clear that it's worth it. */
20774 /* These are supported directly. */
20781 /* AVX has 3 operand comparisons, no need to swap anything. */
20784 /* For commutative operators, try to canonicalize the destination
20785 operand to be first in the comparison - this helps reload to
20786 avoid extra moves. */
20789 /* FALLTHRU */
20795 /* These are not supported directly before AVX, and furthermore
20796 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20797 comparison operands to transform into something that is
20798 supported. */
20807 }
20810 }
20812 /* Detect conditional moves that exactly match min/max operational
20813 semantics. Note that this is IEEE safe, as long as we don't
20814 interchange the operands.
20816 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20817 and TRUE if the operation is successful and instructions are emitted. */
20819 static bool
20822 {
20825 rtx tmp;
20828 ;
20830 {
20834 }
20835 else
20842 else
20847 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20848 but MODE may be a vector mode and thus not appropriate. */
20850 {
20852 rtvec v;
20857 }
20858 else
20859 {
20862 }
20866 }
20868 /* Expand an sse vector comparison. Return the register with the result. */
20870 static rtx
20873 {
20877 /* In general case result of comparison can differ from operands' type. */
20880 /* In AVX512F the result of comparison is an integer mask. */
20882 rtx x;
20885 {
20890 }
20891 else
20904 /* Compare patterns for int modes are unspec in AVX512F only. */
20906 {
20910 {
20919 }
20922 {
20925 }
20926 }
20930 {
20933 }
20934 else
20938 }
20940 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20941 operations. This is used for both scalar and vector conditional moves. */
20943 static void
20945 {
20949 /* In AVX512F the result of comparison is an integer mask. */
20957 {
20959 }
20962 {
20966 }
20969 {
20974 }
20977 {
20981 }
20984 {
20992 op_true,
20993 op_false)));
20994 }
20995 else
20996 {
21006 {
21020 {
21027 }
21042 {
21049 }
21067 }
21070 {
21074 }
21075 else
21076 {
21082 else
21094 }
21095 }
21096 }
21098 /* Expand a floating-point conditional move. Return true if successful. */
21100 bool
21102 {
21110 {
21113 /* Since we've no cmove for sse registers, don't force bad register
21114 allocation just to gain access to it. Deny movcc when the
21115 comparison mode doesn't match the move mode. */
21134 }
21141 /* The floating point conditional move instructions don't directly
21142 support conditions resulting from a signed integer comparison. */
21146 {
21151 }
21158 }
21160 /* Expand a floating-point vector conditional move; a vcond operation
21161 rather than a movcc operation. */
21163 bool
21165 {
21167 rtx cmp;
21172 {
21173 rtx temp;
21175 {
21192 }
21194 OPTAB_DIRECT);
21197 }
21207 }
21209 /* Expand a signed/unsigned integral vector conditional move. */
21211 bool
21213 {
21223 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21224 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21233 {
21237 {
21243 }
21246 {
21252 }
21253 }
21262 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21266 ;
21267 else
21268 {
21269 /* Canonicalize the comparison to EQ, GT, GTU. */
21271 {
21288 /* FALLTHRU */
21298 }
21300 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21302 {
21304 {
21306 /* SSE4.1 supports EQ. */
21313 /* SSE4.2 supports GT/GTU. */
21320 }
21321 }
21323 /* Unsigned parallel compare is not supported by the hardware.
21324 Play some tricks to turn this into a signed comparison
21325 against 0. */
21327 {
21331 {
21338 {
21343 {
21352 }
21353 /* Subtract (-(INT MAX) - 1) from both operands to make
21354 them signed. */
21365 }
21372 /* Perform a parallel unsigned saturating subtraction. */
21385 }
21386 }
21387 }
21389 /* Allow the comparison to be done in one mode, but the movcc to
21390 happen in another mode. */
21392 {
21395 }
21396 else
21397 {
21403 }
21408 }
21410 static bool
21412 {
21415 {
21419 op1));
21424 op1));
21436 }
21437 }
21439 /* Expand a variable vector permutation. */
21441 void
21443 {
21454 /* Number of elements in the vector. */
21463 {
21465 {
21466 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21467 an constant shuffle operand. With a tiny bit of effort we can
21468 use VPERMD instead. A re-interpretation stall for V4DFmode is
21469 unfortunate but there's no avoiding it.
21470 Similarly for V16HImode we don't have instructions for variable
21471 shuffling, while for V32QImode we can use after preparing suitable
21472 masks vpshufb; vpshufb; vpermq; vpor. */
21475 {
21479 }
21480 else
21481 {
21485 }
21488 /* Replicate the low bits of the V4DImode mask into V8SImode:
21489 mask = { A B C D }
21490 t1 = { A A B B C C D D }. */
21498 else
21501 /* Multiply the shuffle indicies by two. */
21503 OPTAB_DIRECT);
21505 /* Add one to the odd shuffle indicies:
21506 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21508 {
21511 }
21515 OPTAB_DIRECT);
21517 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21522 }
21525 {
21527 /* The VPERMD and VPERMPS instructions already properly ignore
21528 the high bits of the shuffle elements. No need for us to
21529 perform an AND ourselves. */
21531 {
21536 }
21537 else
21538 {
21544 }
21551 else
21552 {
21558 }
21562 /* By combining the two 128-bit input vectors into one 256-bit
21563 input vector, we can use VPERMD and VPERMPS for the full
21564 two-operand shuffle. */
21596 /* From mask create two adjusted masks, which contain the same
21597 bits as mask in the low 7 bits of each vector element.
21598 The first mask will have the most significant bit clear
21599 if it requests element from the same 128-bit lane
21600 and MSB set if it requests element from the other 128-bit lane.
21601 The second mask will have the opposite values of the MSB,
21602 and additionally will have its 128-bit lanes swapped.
21603 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21604 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21605 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21606 stands for other 12 bytes. */
21607 /* The bit whether element is from the same lane or the other
21608 lane is bit 4, so shift it up by 3 to the MSB position. */
21612 /* Clear MSB bits from the mask just in case it had them set. */
21614 /* After this t1 will have MSB set for elements from other lane. */
21616 /* Clear bits other than MSB. */
21618 /* Or in the lower bits from mask into t3. */
21620 /* And invert MSB bits in t1, so MSB is set for elements from the same
21621 lane. */
21623 /* Swap 128-bit lanes in t3. */
21628 /* And or in the lower bits from mask into t1. */
21631 {
21632 /* Each of these shuffles will put 0s in places where
21633 element from the other 128-bit lane is needed, otherwise
21634 will shuffle in the requested value. */
21638 /* For t3 the 128-bit lanes are swapped again. */
21643 /* And oring both together leads to the result. */
21650 }
21653 /* Similarly to the above one_operand_shuffle code,
21654 just for repeated twice for each operand. merge_two:
21655 code will merge the two results together. */
21679 }
21680 }
21683 {
21684 /* The XOP VPPERM insn supports three inputs. By ignoring the
21685 one_operand_shuffle special case, we avoid creating another
21686 set of constant vectors in memory. */
21689 /* mask = mask & {2*w-1, ...} */
21691 }
21692 else
21693 {
21694 /* mask = mask & {w-1, ...} */
21696 }
21704 /* For non-QImode operations, convert the word permutation control
21705 into a byte permutation control. */
21707 {
21712 /* Convert mask to vector of chars. */
21715 /* Replicate each of the input bytes into byte positions:
21716 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21717 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21718 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21725 else
21728 /* Convert it into the byte positions by doing
21729 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21735 }
21737 /* The actual shuffle operations all operate on V16QImode. */
21742 {
21749 }
21751 {
21758 }
21759 else
21760 {
21764 /* Shuffle the two input vectors independently. */
21770 merge_two:
21771 /* Then merge them together. The key is whether any given control
21772 element contained a bit set that indicates the second word. */
21776 {
21777 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21778 more shuffle to convert the V2DI input mask into a V4SI
21779 input mask. At which point the masking that expand_int_vcond
21780 will work as desired. */
21788 }
21810 }
21811 }
21813 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21814 true if we should do zero extension, else sign extension. HIGH_P is
21815 true if we want the N/2 high elements, else the low elements. */
21817 void
21819 {
21821 rtx tmp;
21824 {
21830 {
21834 else
21837 extract
21843 else
21846 extract
21852 else
21855 extract
21861 else
21864 extract
21870 else
21873 extract
21879 else
21885 else
21891 else
21896 }
21899 {
21902 }
21904 {
21905 /* Shift higher 8 bytes to lower 8 bytes. */
21910 }
21911 else
21915 }
21916 else
21917 {
21921 {
21925 else
21931 else
21937 else
21942 }
21946 else
21953 }
21954 }
21956 /* Expand conditional increment or decrement using adb/sbb instructions.
21957 The default case using setcc followed by the conditional move can be
21958 done by generic code. */
21959 bool
21961 {
21963 rtx flags;
21965 rtx compare_op;
21983 {
21986 }
21989 {
21993 reverse_condition_maybe_unordered
21995 else
21997 }
22001 /* Construct either adc or sbb insn. */
22003 {
22005 {
22020 }
22021 }
22022 else
22023 {
22025 {
22040 }
22041 }
22045 }
22048 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22049 but works for floating pointer parameters and nonoffsetable memories.
22050 For pushes, it returns just stack offsets; the values will be saved
22051 in the right order. Maximally three parts are generated. */
22053 static int
22055 {
22060 else
22066 /* Optimize constant pool reference to immediates. This is used by fp
22067 moves, that force all constants to memory to allow combining. */
22069 {
22073 }
22076 {
22077 /* The only non-offsetable memories we handle are pushes. */
22086 }
22089 {
22091 /* Caution: if we looked through a constant pool memory above,
22092 the operand may actually have a different mode now. That's
22093 ok, since we want to pun this all the way back to an integer. */
22097 }
22100 {
22103 else
22104 {
22108 {
22112 }
22114 {
22119 }
22121 {
22122 REAL_VALUE_TYPE r;
22127 {
22134 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22135 long double may not be 80-bit. */
22144 }
22147 }
22148 else
22150 }
22151 }
22152 else
22153 {
22157 {
22160 {
22164 }
22166 {
22170 }
22172 {
22173 REAL_VALUE_TYPE r;
22179 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22182 = gen_int_mode
22185 DImode);
22186 else
22193 = gen_int_mode
22196 DImode);
22197 else
22199 }
22200 else
22202 }
22203 }
22206 }
22208 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22209 Return false when normal moves are needed; true when all required
22210 insns have been emitted. Operands 2-4 contain the input values
22211 int the correct order; operands 5-7 contain the output values. */
22213 void
22215 {
22223 /* The DFmode expanders may ask us to move double.
22224 For 64bit target this is single move. By hiding the fact
22225 here we simplify i386.md splitters. */
22227 {
22228 /* Optimize constant pool reference to immediates. This is used by
22229 fp moves, that force all constants to memory to allow combining. */
22236 {
22239 }
22240 else
22245 }
22247 /* The only non-offsettable memory we handle is push. */
22250 else
22257 /* When emitting push, take care for source operands on the stack. */
22260 {
22263 /* Compensate for the stack decrement by 4. */
22268 /* src_base refers to the stack pointer and is
22269 automatically decreased by emitted push. */
22273 }
22275 /* We need to do copy in the right order in case an address register
22276 of the source overlaps the destination. */
22278 {
22279 rtx tmp;
22282 {
22286 collisions++;
22287 }
22289 /* Collision in the middle part can be handled by reordering. */
22291 {
22294 }
22298 {
22300 {
22303 }
22304 else
22305 {
22308 }
22309 }
22311 /* If there are more collisions, we can't handle it by reordering.
22312 Do an lea to the last part and use only one colliding move. */
22314 {
22315 rtx base;
22321 /* Handle the case when the last part isn't valid for lea.
22322 Happens in 64-bit mode storing the 12-byte XFmode. */
22329 {
22332 }
22333 }
22334 }
22337 {
22339 {
22341 {
22346 }
22348 {
22351 }
22352 }
22353 else
22354 {
22355 /* In 64bit mode we don't have 32bit push available. In case this is
22356 register, it is OK - we will just use larger counterpart. We also
22357 retype memory - these comes from attempt to avoid REX prefix on
22358 moving of second half of TFmode value. */
22360 {
22362 {
22373 }
22377 }
22378 }
22382 }
22384 /* Choose correct order to not overwrite the source before it is copied. */
22394 {
22396 {
22399 }
22400 }
22401 else
22402 {
22404 {
22407 }
22408 }
22410 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22412 {
22421 }
22427 }
22429 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22430 left shift by a constant, either using a single shift or
22431 a sequence of add instructions. */
22433 static void
22435 {
22441 {
22445 }
22446 else
22447 {
22450 }
22451 }
22453 void
22455 {
22464 {
22469 {
22475 }
22476 else
22477 {
22485 }
22487 }
22494 {
22495 /* Assuming we've chosen a QImode capable registers, then 1 << N
22496 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22498 {
22514 }
22516 /* Otherwise, we can get the same results by manually performing
22517 a bit extract operation on bit 5/6, and then performing the two
22518 shifts. The two methods of getting 0/1 into low/high are exactly
22519 the same size. Avoiding the shift in the bit extract case helps
22520 pentium4 a bit; no one else seems to care much either way. */
22521 else
22522 {
22527 HOST_WIDE_INT bits;
22528 rtx x;
22531 {
22537 }
22538 else
22539 {
22545 }
22549 else
22557 }
22562 }
22565 {
22566 /* For -1 << N, we can avoid the shld instruction, because we
22567 know that we're shifting 0...31/63 ones into a -1. */
22571 else
22573 }
22574 else
22575 {
22583 }
22588 {
22594 }
22595 else
22596 {
22601 }
22602 }
22604 void
22606 {
22616 {
22621 {
22627 }
22629 {
22638 }
22639 else
22640 {
22648 }
22649 }
22650 else
22651 {
22663 {
22671 scratch));
22672 }
22673 else
22674 {
22679 }
22680 }
22681 }
22683 void
22685 {
22695 {
22700 {
22707 }
22708 else
22709 {
22717 }
22718 }
22719 else
22720 {
22732 {
22738 scratch));
22739 }
22740 else
22741 {
22746 }
22747 }
22748 }
22750 /* Predict just emitted jump instruction to be taken with probability PROB. */
22751 static void
22753 {
22757 }
22759 /* Helper function for the string operations below. Dest VARIABLE whether
22760 it is aligned to VALUE bytes. If true, jump to the label. */
22763 {
22768 else
22774 else
22777 }
22779 /* Adjust COUNTER by the VALUE. */
22780 static void
22782 {
22787 }
22789 /* Zero extend possibly SImode EXP to Pmode register. */
22790 rtx
22792 {
22794 }
22796 /* Divide COUNTREG by SCALE. */
22797 static rtx
22799 {
22800 rtx sc;
22812 }
22814 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22815 DImode for constant loop counts. */
22817 static enum machine_mode
22819 {
22827 }
22829 /* Copy the address to a Pmode register. This is used for x32 to
22830 truncate DImode TLS address to a SImode register. */
22832 static rtx
22834 {
22837 else
22838 {
22841 }
22842 }
22844 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22845 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22846 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22847 memory by VALUE (supposed to be in MODE).
22849 The size is rounded down to whole number of chunk size moved at once.
22850 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22853 static void
22858 {
22865 rtx size;
22874 /* Those two should combine. */
22876 {
22880 }
22887 /* This assert could be relaxed - in this case we'll need to compute
22888 smallest power of two, containing in PIECE_SIZE_N and pass it to
22889 offset_address. */
22895 {
22899 /* When unrolling for chips that reorder memory reads and writes,
22900 we can save registers by using single temporary.
22901 Also using 4 temporaries is overkill in 32bit mode. */
22903 {
22905 {
22907 {
22908 destmem =
22910 srcmem =
22912 }
22914 }
22915 }
22916 else
22917 {
22921 {
22924 {
22925 srcmem =
22927 }
22929 }
22931 {
22933 {
22934 destmem =
22936 }
22938 }
22939 }
22940 }
22941 else
22943 {
22945 destmem =
22948 }
22958 {
22964 else
22966 }
22967 else
22975 {
22980 }
22982 }
22984 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22985 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22986 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22987 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22988 ORIG_VALUE is the original value passed to memset to fill the memory with.
22989 Other arguments have same meaning as for previous function. */
22991 static void
22994 rtx count,
22996 {
22997 rtx destexp;
22998 rtx srcexp;
22999 rtx countreg;
23000 HOST_WIDE_INT rounded_count;
23002 /* If possible, it is shorter to use rep movs.
23003 TODO: Maybe it is better to move this logic to decide_alg. */
23014 {
23018 }
23019 else
23022 {
23027 }
23032 {
23035 }
23036 else
23037 {
23041 {
23045 }
23046 else
23049 {
23054 }
23055 else
23056 {
23059 }
23062 }
23063 }
23065 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23066 DESTMEM.
23067 SRC is passed by pointer to be updated on return.
23068 Return value is updated DST. */
23069 static rtx
23071 HOST_WIDE_INT size_to_move)
23072 {
23078 /* Find the widest mode in which we could perform moves.
23079 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23080 it until move of such size is supported. */
23085 {
23089 }
23091 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23092 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23094 {
23099 {
23103 }
23104 }
23110 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23114 {
23115 /* We move from memory to memory, so we'll need to do it via
23116 a temporary register. */
23127 piece_size);
23129 piece_size);
23130 }
23132 /* Update DST and SRC rtx. */
23135 }
23137 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23138 static void
23141 {
23144 {
23149 /* For now MAX_SIZE should be a power of 2. This assert could be
23150 relaxed, but it'll require a bit more complicated epilogue
23151 expanding. */
23154 {
23157 }
23159 }
23161 {
23167 }
23169 /* When there are stringops, we can cheaply increase dest and src pointers.
23170 Otherwise we save code size by maintaining offset (zero is readily
23171 available from preceding rep operation) and using x86 addressing modes.
23172 */
23174 {
23176 {
23183 }
23185 {
23192 }
23194 {
23201 }
23202 }
23203 else
23204 {
23206 rtx tmp;
23209 {
23220 }
23222 {
23235 }
23237 {
23246 }
23247 }
23248 }
23250 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23251 with value PROMOTED_VAL.
23252 SRC is passed by pointer to be updated on return.
23253 Return value is updated DST. */
23254 static rtx
23256 HOST_WIDE_INT size_to_move)
23257 {
23263 /* Find the widest mode in which we could perform moves.
23264 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23265 it until move of such size is supported. */
23270 {
23273 }
23280 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23284 {
23286 {
23289 piece_size);
23291 }
23299 piece_size);
23300 }
23302 /* Update DST rtx. */
23304 }
23305 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23306 static void
23309 {
23310 count =
23316 }
23318 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23319 static void
23322 {
23323 rtx dest;
23326 {
23331 /* For now MAX_SIZE should be a power of 2. This assert could be
23332 relaxed, but it'll require a bit more complicated epilogue
23333 expanding. */
23336 {
23338 {
23341 else
23343 }
23344 }
23346 }
23348 {
23351 }
23353 {
23356 {
23361 }
23362 else
23363 {
23372 }
23375 }
23377 {
23380 {
23383 }
23384 else
23385 {
23390 }
23393 }
23395 {
23401 }
23403 {
23409 }
23411 {
23417 }
23418 }
23420 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23421 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23422 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23423 ignored.
23424 Return value is updated DESTMEM. */
23425 static rtx
23430 {
23433 {
23435 {
23438 {
23441 else
23443 }
23444 else
23450 }
23451 }
23453 }
23455 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23456 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23457 and jump to DONE_LABEL. */
23458 static void
23464 {
23467 rtx modesize;
23470 /* If we do not have vector value to copy, we must reduce size. */
23472 {
23474 {
23479 }
23480 else
23482 }
23483 else
23484 {
23485 /* Choose appropriate vector mode. */
23491 }
23496 {
23499 else
23500 {
23503 }
23505 }
23511 {
23515 }
23517 {
23520 else
23521 {
23524 }
23526 }
23532 }
23534 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23535 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23536 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23537 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23538 DONE_LABEL is a label after the whole copying sequence. The label is created
23539 on demand if *DONE_LABEL is NULL.
23540 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23541 bounds after the initial copies.
23543 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23544 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23545 we will dispatch to a library call for large blocks.
23547 In pseudocode we do:
23549 if (COUNT < SIZE)
23550 {
23551 Assume that SIZE is 4. Bigger sizes are handled analogously
23552 if (COUNT & 4)
23553 {
23554 copy 4 bytes from SRCPTR to DESTPTR
23555 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23556 goto done_label
23557 }
23558 if (!COUNT)
23559 goto done_label;
23560 copy 1 byte from SRCPTR to DESTPTR
23561 if (COUNT & 2)
23562 {
23563 copy 2 bytes from SRCPTR to DESTPTR
23564 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23565 }
23566 }
23567 else
23568 {
23569 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23570 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23572 OLD_DESPTR = DESTPTR;
23573 Align DESTPTR up to DESIRED_ALIGN
23574 SRCPTR += DESTPTR - OLD_DESTPTR
23575 COUNT -= DEST_PTR - OLD_DESTPTR
23576 if (DYNAMIC_CHECK)
23577 Round COUNT down to multiple of SIZE
23578 << optional caller supplied zero size guard is here >>
23579 << optional caller suppplied dynamic check is here >>
23580 << caller supplied main copy loop is here >>
23581 }
23582 done_label:
23583 */
23584 static void
23597 {
23600 rtx modesize;
23602 rtx mode_value;
23604 /* Chose proper value to copy. */
23607 else
23611 /* See if block is big or small, handle small blocks. */
23613 {
23624 /* Handle sizes > 3. */
23631 /* Nothing to copy? Jump to DONE_LABEL if so */
23635 /* Do a byte copy. */
23639 else
23640 {
23643 }
23645 /* Handle sizes 2 and 3. */
23652 else
23653 {
23658 }
23664 }
23665 else
23669 /* Start memcpy for COUNT >= SIZE. */
23671 {
23674 }
23676 /* Copy first desired_align bytes. */
23682 {
23685 else
23686 {
23689 }
23692 }
23695 /* Copy last SIZE bytes. */
23702 else
23703 {
23709 }
23711 {
23715 else
23716 {
23719 }
23720 }
23722 /* Align destination. */
23724 {
23728 /* Align destptr up, place it to new register. */
23735 /* See how many bytes we skipped. */
23739 /* Adjust srcptr and count. */
23745 /* We copied at most size + prolog_size. */
23748 else
23751 /* Our loops always round down the bock size, but for dispatch to library
23752 we need precise value. */
23756 }
23757 else
23758 {
23760 /* Decrease count, so we won't end up copying last word twice. */
23764 else
23768 }
23769 }
23772 /* This function is like the previous one, except here we know how many bytes
23773 need to be copied. That allows us to update alignment not only of DST, which
23774 is returned, but also of SRC, which is passed as a pointer for that
23775 reason. */
23776 static rtx
23781 {
23789 {
23793 }
23798 {
23800 {
23802 {
23805 else
23807 }
23808 else
23811 }
23812 }
23819 {
23825 {
23828 {
23832 }
23837 }
23841 }
23844 }
23846 /* Return true if ALG can be used in current context.
23847 Assume we expand memset if MEMSET is true. */
23848 static bool
23850 {
23855 /* Algorithms using the rep prefix want at least edi and ecx;
23856 additionally, memset wants eax and memcpy wants esi. Don't
23857 consider such algorithms if the user has appropriated those
23858 registers for their own purposes. */
23865 }
23867 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23868 static enum stringop_alg
23872 {
23883 /* Even if the string operation call is cold, we still might spend a lot
23884 of time processing large blocks. */
23890 else
23896 else
23899 /* See maximal size for user defined algorithm. */
23901 {
23908 }
23910 /* If expected size is not known but max size is small enough
23911 so inline version is a win, set expected size into
23912 the range. */
23917 /* If user specified the algorithm, honnor it if possible. */
23921 /* rep; movq or rep; movl is the smallest variant. */
23923 {
23928 else
23931 }
23932 /* Very tiny blocks are best handled via the loop, REP is expensive to
23933 setup. */
23937 {
23941 {
23942 /* We get here if the algorithms that were not libcall-based
23943 were rep-prefix based and we are unable to use rep prefixes
23944 based on global register usage. Break out of the loop and
23945 use the heuristic below. */
23949 {
23953 {
23956 }
23957 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23958 last non-libcall inline algorithm. */
23960 {
23961 /* When the current size is best to be copied by a libcall,
23962 but we are still forced to inline, run the heuristic below
23963 that will pick code for medium sized blocks. */
23965 {
23968 }
23970 }
23972 {
23975 }
23976 }
23977 }
23978 }
23979 /* When asked to inline the call anyway, try to pick meaningful choice.
23980 We look for maximal size of block that is faster to copy by hand and
23981 take blocks of at most of that size guessing that average size will
23982 be roughly half of the block.
23984 If this turns out to be bad, we might simply specify the preferred
23985 choice in ix86_costs. */
23989 {
23992 /* If there aren't any usable algorithms, then recursing on
23993 smaller sizes isn't going to find anything. Just return the
23994 simple byte-at-a-time copy loop. */
23996 {
23997 /* Pick something reasonable. */
24001 }
24011 }
24014 }
24016 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24017 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24018 static int
24023 {
24034 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24035 copying whole cacheline at once. */
24048 }
24051 /* Helper function for memcpy. For QImode value 0xXY produce
24052 0xXYXYXYXY of wide specified by MODE. This is essentially
24053 a * 0x10101010, but we can do slightly better than
24054 synth_mult by unwinding the sequence by hand on CPUs with
24055 slow multiply. */
24056 static rtx
24058 {
24060 rtx tmp;
24067 {
24075 }
24084 nops--;
24089 {
24093 OPTAB_DIRECT);
24094 }
24095 else
24096 {
24102 else
24104 else
24105 {
24108 reg =
24110 }
24120 }
24121 }
24123 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24124 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24125 alignment from ALIGN to DESIRED_ALIGN. */
24126 static rtx
24129 {
24130 rtx promoted_val;
24139 else
24143 }
24145 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24146 operations when profitable. The code depends upon architecture, block size
24147 and alignment, but always has one of the following overall structures:
24149 Aligned move sequence:
24151 1) Prologue guard: Conditional that jumps up to epilogues for small
24152 blocks that can be handled by epilogue alone. This is faster
24153 but also needed for correctness, since prologue assume the block
24154 is larger than the desired alignment.
24156 Optional dynamic check for size and libcall for large
24157 blocks is emitted here too, with -minline-stringops-dynamically.
24159 2) Prologue: copy first few bytes in order to get destination
24160 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24161 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24162 copied. We emit either a jump tree on power of two sized
24163 blocks, or a byte loop.
24165 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24166 with specified algorithm.
24168 4) Epilogue: code copying tail of the block that is too small to be
24169 handled by main body (or up to size guarded by prologue guard).
24171 Misaligned move sequence
24173 1) missaligned move prologue/epilogue containing:
24174 a) Prologue handling small memory blocks and jumping to done_label
24175 (skipped if blocks are known to be large enough)
24176 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24177 needed by single possibly misaligned move
24178 (skipped if alignment is not needed)
24179 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24181 2) Zero size guard dispatching to done_label, if needed
24183 3) dispatch to library call, if needed,
24185 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24186 with specified algorithm. */
24187 bool
24193 {
24194 rtx destreg;
24197 rtx tmp;
24213 /* TODO: Once value ranges are available, fill in proper data. */
24221 /* i386 can do misaligned access on reasonably increased cost. */
24225 /* ALIGN is the minimum of destination and source alignment, but we care here
24226 just about destination alignment. */
24232 {
24235 /* When COUNT is 0, there is nothing to do. */
24238 }
24239 else
24240 {
24249 }
24251 /* Make sure we don't need to care about overflow later on. */
24255 /* Step 0: Decide on preferred algorithm, desired alignment and
24256 size of chunks to be copied by main loop. */
24258 issetmem,
24265 /* For now vector-version of memset is generated only for memory zeroing, as
24266 creating of promoted vector value is very cheap in this case. */
24279 {
24298 /* Find the widest supported mode. */
24304 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24305 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24307 {
24312 }
24324 }
24332 /* Step 1: Prologue guard. */
24334 /* Alignment code needs count to be in register. */
24336 {
24339 {
24340 align_bytes
24344 else
24346 }
24349 }
24352 /* Misaligned move sequences handle both prologue and epilogue at once.
24353 Default code generation results in a smaller code for large alignments
24354 and also avoids redundant job when sizes are known precisely. */
24355 misaligned_prologue_used
24356 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24362 /* Do the cheap promotion to allow better CSE across the
24363 main loop and epilogue (ie one load of the big constant in the
24364 front of all code.
24365 For now the misaligned move sequences do not have fast path
24366 without broadcasting. */
24368 {
24370 {
24376 }
24377 else
24378 {
24381 }
24382 }
24383 /* Misaligned move sequences handles both prologues and epilogues at once.
24384 Default code generation results in smaller code for large alignments and
24385 also avoids redundant job when sizes are known precisely. */
24387 {
24388 /* Misaligned move prologue handled small blocks by itself. */
24389 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24394 desired_align < align
24403 {
24404 /* It is possible that we copied enough so the main loop will not
24405 execute. */
24415 else
24417 }
24418 }
24419 /* Ensure that alignment prologue won't copy past end of block. */
24421 {
24423 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24424 Make sure it is power of 2. */
24427 /* To improve performance of small blocks, we jump around the VAL
24428 promoting mode. This mean that if the promoted VAL is not constant,
24429 we might not use it in the epilogue and have to use byte
24430 loop variant. */
24435 {
24436 /* If main algorithm works on QImode, no epilogue is needed.
24437 For small sizes just don't align anything. */
24440 else
24442 }
24445 {
24452 else
24454 }
24455 }
24457 /* Emit code to decide on runtime whether library call or inline should be
24458 used. */
24460 {
24462 {
24464 {
24468 }
24469 }
24470 else
24471 {
24481 else
24485 }
24486 }
24488 /* Step 2: Alignment prologue. */
24489 /* Do the expensive promotion once we branched off the small blocks. */
24495 {
24497 {
24498 /* Except for the first move in prologue, we no longer know
24499 constant offset in aliasing info. It don't seems to worth
24500 the pain to maintain it for the first move, so throw away
24501 the info early. */
24508 issetmem);
24509 /* At most desired_align - align bytes are copied. */
24512 else
24514 }
24515 else
24516 {
24517 /* If we know how many bytes need to be stored before dst is
24518 sufficiently aligned, maintain aliasing info accurately. */
24520 srcreg,
24521 promoted_val,
24522 vec_promoted_val,
24523 desired_align,
24524 align_bytes,
24525 issetmem);
24532 }
24534 && !min_size
24539 {
24540 /* It is possible that we copied enough so the main loop will not
24541 execute. */
24551 else
24553 }
24554 }
24556 {
24563 }
24567 /* Step 3: Main loop. */
24570 {
24593 }
24594 /* Adjust properly the offset of src and dest memory for aliasing. */
24596 {
24602 }
24603 else
24604 {
24608 }
24610 /* Step 4: Epilogue to copy the remaining bytes. */
24611 epilogue:
24613 {
24614 /* When the main loop is done, COUNT_EXP might hold original count,
24615 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24616 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24617 bytes. Compensate if needed. */
24620 {
24621 tmp =
24624 OPTAB_DIRECT);
24627 }
24630 }
24633 {
24636 epilogue_size_needed);
24637 else
24638 {
24642 epilogue_size_needed);
24643 else
24645 epilogue_size_needed);
24646 }
24647 }
24651 }
24654 /* Expand the appropriate insns for doing strlen if not just doing
24655 repnz; scasb
24657 out = result, initialized with the start address
24658 align_rtx = alignment of the address.
24659 scratch = scratch register, initialized with the startaddress when
24660 not aligned, otherwise undefined
24662 This is just the body. It needs the initializations mentioned above and
24663 some address computing at the end. These things are done in i386.md. */
24665 static void
24667 {
24669 rtx tmp;
24674 rtx mem;
24677 rtx cmp;
24683 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24685 /* Is there a known alignment and is it less than 4? */
24687 {
24690 /* Is there a known alignment and is it not 2? */
24692 {
24696 /* Leave just the 3 lower bits. */
24706 }
24707 else
24708 {
24709 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24710 check if is aligned to 4 - byte. */
24717 }
24721 /* Now compare the bytes. */
24723 /* Compare the first n unaligned byte on a byte per byte basis. */
24727 /* Increment the address. */
24730 /* Not needed with an alignment of 2 */
24732 {
24736 end_0_label);
24741 }
24744 end_0_label);
24747 }
24749 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24750 align this loop. It gives only huge programs, but does not help to
24751 speed up. */
24758 /* This formula yields a nonzero result iff one of the bytes is zero.
24759 This saves three branches inside loop and many cycles. */
24767 align_4_label);
24770 {
24776 /* If zero is not in the first two bytes, move two bytes forward. */
24782 reg,
24783 tmpreg)));
24784 /* Emit lea manually to avoid clobbering of flags. */
24792 reg2,
24793 out)));
24794 }
24795 else
24796 {
24798 /* Is zero in the first two bytes? */
24805 pc_rtx);
24809 /* Not in the first two. Move two bytes forward. */
24815 }
24817 /* Avoid branch in fixing the byte. */
24825 }
24827 /* Expand strlen. */
24829 bool
24831 {
24834 /* The generic case of strlen expander is long. Avoid it's
24835 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24838 && !TARGET_INLINE_ALL_STRINGOPS
24848 {
24849 /* Well it seems that some optimizer does not combine a call like
24850 foo(strlen(bar), strlen(bar));
24851 when the move and the subtraction is done here. It does calculate
24852 the length just once when these instructions are done inside of
24853 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24854 often used and I use one fewer register for the lifetime of
24855 output_strlen_unroll() this is better. */
24861 /* strlensi_unroll_1 returns the address of the zero at the end of
24862 the string, like memchr(), so compute the length by subtracting
24863 the start address. */
24865 }
24866 else
24867 {
24868 rtx unspec;
24870 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24883 /* If .md starts supporting :P, this can be done in .md. */
24889 }
24891 }
24893 /* For given symbol (function) construct code to compute address of it's PLT
24894 entry in large x86-64 PIC model. */
24895 static rtx
24897 {
24910 }
24912 rtx
24914 rtx callarg2,
24916 {
24917 unsigned int const cregs_size
24928 {
24929 #if TARGET_MACHO
24932 #endif
24933 }
24934 else
24935 {
24936 /* Static functions and indirect calls don't need the pic register. */
24938 && (!TARGET_64BIT
24944 }
24947 {
24951 }
24954 && !TARGET_PECOFF
24962 {
24965 }
24973 {
24977 }
24981 {
24985 UNSPEC_MS_TO_SYSV_CALL);
24988 {
24994 }
24995 }
25004 }
25006 /* Output the assembly for a call instruction. */
25010 {
25016 {
25019 /* SEH epilogue detection requires the indirect branch case
25020 to include REX.W. */
25023 else
25028 }
25030 /* SEH unwinding can require an extra nop to be emitted in several
25031 circumstances. Determine if we have one of those. */
25033 {
25037 {
25038 /* If we get to another real insn, we don't need the nop. */
25042 /* If we get to the epilogue note, prevent a catch region from
25043 being adjacent to the standard epilogue sequence. If non-
25044 call-exceptions, we'll have done this during epilogue emission. */
25046 && !flag_non_call_exceptions
25048 {
25051 }
25052 }
25054 /* If we didn't find a real insn following the call, prevent the
25055 unwinder from looking into the next function. */
25058 }
25062 else
25071 }
25072 \f
25073 /* Clear stack slot assignments remembered from previous functions.
25074 This is called from INIT_EXPANDERS once before RTL is emitted for each
25075 function. */
25079 {
25087 }
25089 /* Return a MEM corresponding to a stack slot with mode MODE.
25090 Allocate a new slot if necessary.
25092 The RTL for a function can have several slots available: N is
25093 which slot to use. */
25095 rtx
25097 {
25114 }
25116 static void
25118 {
25124 }
25125 \f
25126 /* Check whether x86 address PARTS is a pc-relative address. */
25128 static bool
25130 {
25138 {
25140 {
25157 }
25158 }
25160 }
25162 /* Calculate the length of the memory address in the instruction encoding.
25163 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25164 or other prefixes. We never generate addr32 prefix for LEA insn. */
25166 int
25168 {
25185 /* If this is not LEA instruction, add the length of addr32 prefix. */
25190 len++;
25204 /* Rule of thumb:
25205 - esp as the base always wants an index,
25206 - ebp as the base always wants a displacement,
25207 - r12 as the base always wants an index,
25208 - r13 as the base always wants a displacement. */
25210 /* Register Indirect. */
25212 {
25213 /* esp (for its index) and ebp (for its displacement) need
25214 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25215 code. */
25222 len++;
25223 }
25225 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25226 is not disp32, but disp32(%rip), so for disp32
25227 SIB byte is needed, unless print_operand_address
25228 optimizes it into disp32(%rip) or (%rip) is implied
25229 by UNSPEC. */
25231 {
25234 len++;
25235 }
25236 else
25237 {
25238 /* Find the length of the displacement constant. */
25240 {
25243 else
25245 }
25246 /* ebp always wants a displacement. Similarly r13. */
25248 len++;
25250 /* An index requires the two-byte modrm form.... */
25252 /* ...like esp (or r12), which always wants an index. */
25256 len++;
25257 }
25260 }
25262 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25263 is set, expect that insn have 8bit immediate alternative. */
25264 int
25266 {
25272 {
25277 {
25280 {
25292 }
25294 {
25297 }
25298 }
25300 {
25310 /* Immediates for DImode instructions are encoded
25311 as 32bit sign extended values. */
25317 }
25318 }
25320 }
25322 /* Compute default value for "length_address" attribute. */
25323 int
25325 {
25329 {
25340 }
25345 {
25348 {
25353 constraints++;
25356 ;
25357 /* Skip ignored operands. */
25360 }
25362 }
25364 }
25366 /* Compute default value for "length_vex" attribute. It includes
25367 2 or 3 byte VEX prefix and 1 opcode byte. */
25369 int
25371 {
25374 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25375 byte VEX prefix. */
25379 /* We can always use 2 byte VEX prefix in 32bit. */
25387 {
25388 /* REX.W bit uses 3 byte VEX prefix. */
25392 }
25393 else
25394 {
25395 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25399 }
25402 }
25403 \f
25404 /* Return the maximum number of instructions a cpu can issue. */
25406 static int
25408 {
25410 {
25441 }
25442 }
25444 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25445 by DEP_INSN and nothing set by DEP_INSN. */
25447 static bool
25449 {
25452 /* Simplify the test for uninteresting insns. */
25460 {
25463 }
25468 {
25471 }
25472 else
25478 /* This test is true if the dependent insn reads the flags but
25479 not any other potentially set register. */
25487 }
25489 /* Return true iff USE_INSN has a memory address with operands set by
25490 SET_INSN. */
25492 bool
25494 {
25499 {
25502 }
25504 }
25506 /* Helper function for exact_store_load_dependency.
25507 Return true if addr is found in insn. */
25508 static bool
25510 {
25517 {
25523 CASE_CONST_ANY:
25532 }
25536 {
25538 {
25548 }
25549 }
25551 }
25553 /* Return true if there exists exact dependency for store & load, i.e.
25554 the same memory address is used in them. */
25555 static bool
25557 {
25571 }
25573 static int
25575 {
25581 /* Anti and output dependencies have zero cost on all CPUs. */
25587 /* If we can't recognize the insns, we can't really do anything. */
25595 {
25597 /* Address Generation Interlock adds a cycle of latency. */
25599 {
25610 }
25614 /* ??? Compares pair with jump/setcc. */
25618 /* Floating point stores require value to be ready one cycle earlier. */
25626 /* INT->FP conversion is expensive. */
25630 /* There is one cycle extra latency between an FP op and a store. */
25640 /* Show ability of reorder buffer to hide latency of load by executing
25641 in parallel with previous instruction in case
25642 previous instruction is not needed to compute the address. */
25645 {
25646 /* Claim moves to take one cycle, as core can issue one load
25647 at time and the next load can start cycle later. */
25652 cost--;
25653 }
25657 /* The esp dependency is resolved before
25658 the instruction is really finished. */
25663 /* INT->FP conversion is expensive. */
25669 /* Show ability of reorder buffer to hide latency of load by executing
25670 in parallel with previous instruction in case
25671 previous instruction is not needed to compute the address. */
25674 {
25675 /* Claim moves to take one cycle, as core can issue one load
25676 at time and the next load can start cycle later. */
25682 else
25684 }
25695 /* Stack engine allows to execute push&pop instructions in parall. */
25699 /* FALLTHRU */
25705 /* Show ability of reorder buffer to hide latency of load by executing
25706 in parallel with previous instruction in case
25707 previous instruction is not needed to compute the address. */
25710 {
25714 /* Because of the difference between the length of integer and
25715 floating unit pipeline preparation stages, the memory operands
25716 for floating point are cheaper.
25718 ??? For Athlon it the difference is most probably 2. */
25721 else
25726 else
25728 }
25735 /* Stack engine allows to execute push&pop instructions in parall. */
25742 /* Show ability of reorder buffer to hide latency of load by executing
25743 in parallel with previous instruction in case
25744 previous instruction is not needed to compute the address. */
25747 {
25750 else
25752 }
25760 /* Increase cost of integer loads. */
25763 {
25766 {
25769 else
25770 {
25771 /* Increase cost of ld/st for short int types only
25772 because of store forwarding issue. */
25776 {
25777 /* Increase cost of store/load insn if exact
25778 dependence exists and it is load insn. */
25783 }
25784 }
25785 }
25786 }
25790 }
25793 }
25795 /* How many alternative schedules to try. This should be as wide as the
25796 scheduling freedom in the DFA, but no wider. Making this value too
25797 large results extra work for the scheduler. */
25799 static int
25801 {
25803 {
25815 /* We use lookahead value 4 for BD both before and after reload
25816 schedules. Plan is to have value 8 included for O3. */
25826 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25827 as many instructions can be executed on a cycle, i.e.,
25828 issue_rate. I wonder why tuning for many CPUs does not do this. */
25831 /* Don't use lookahead for pre-reload schedule to save compile time. */
25836 }
25837 }
25839 /* Return true if target platform supports macro-fusion. */
25841 static bool
25843 {
25845 }
25847 /* Check whether current microarchitecture support macro fusion
25848 for insn pair "CONDGEN + CONDJMP". Refer to
25849 "Intel Architectures Optimization Reference Manual". */
25851 static bool
25853 {
25875 else
25876 {
25881 {
25885 else
25887 }
25888 }
25895 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25896 supported. */
25903 /* No fusion for RIP-relative address. */
25910 ix86_address parts;
25916 }
25921 /* Check whether conditional jump use Sign or Overflow Flags. */
25929 /* Return true for TYPE_TEST and TYPE_ICMP. */
25934 /* The following is the case that macro-fusion for alu + jmp. */
25938 /* No fusion for alu op with memory destination operand. */
25943 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25944 supported. */
25953 }
25955 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25956 execution. It is applied if
25957 (1) IMUL instruction is on the top of list;
25958 (2) There exists the only producer of independent IMUL instruction in
25959 ready list.
25960 Return index of IMUL producer if it was found and -1 otherwise. */
25961 static int
25963 {
25966 sd_iterator_def sd_it;
25967 dep_t dep;
25974 /* Check that IMUL instruction is on the top of ready list. */
25983 /* Search for producer of independent IMUL instruction. */
25985 {
25989 /* Skip IMUL instruction. */
25999 {
26000 rtx con;
26011 {
26012 sd_iterator_def sd_it1;
26013 dep_t dep1;
26014 /* Check if there is no other dependee for IMUL. */
26017 {
26018 rtx pro;
26024 }
26027 }
26028 }
26031 }
26033 }
26035 /* Try to find the best candidate on the top of ready list if two insns
26036 have the same priority - candidate is best if its dependees were
26037 scheduled earlier. Applied for Silvermont only.
26038 Return true if top 2 insns must be interchanged. */
26039 static bool
26041 {
26044 rtx set;
26045 sd_iterator_def sd_it;
26046 dep_t dep;
26049 #define INSN_TICK(INSN) (HID (INSN)->tick)
26070 {
26073 /* Determine winner more precise. */
26075 {
26076 rtx pro;
26082 }
26084 {
26085 rtx pro;
26091 }
26094 {
26095 /* Determine winner - load must win. */
26101 }
26103 }
26105 #undef INSN_TICK
26106 }
26108 /* Perform possible reodering of ready list for Atom/Silvermont only.
26109 Return issue rate. */
26110 static int
26113 {
26120 /* Set up issue rate. */
26123 /* Do reodering for BONNELL/SILVERMONT only. */
26127 /* Nothing to do if ready list contains only 1 instruction. */
26131 /* Do reodering for post-reload scheduler only. */
26136 {
26141 /* Put IMUL producer (ready[index]) at the top of ready list. */
26147 }
26149 {
26153 /* Swap 2 top elements of ready list. */
26157 }
26159 }
26161 static bool
26164 /* Returns true if lhs of insn is HW function argument register and set up
26165 is_spilled to true if it is likely spilled HW register. */
26166 static bool
26168 {
26169 rtx dst;
26173 /* Call instructions are not movable, ignore it. */
26184 {
26185 /* Is it likely spilled HW register? */
26190 }
26192 }
26194 /* Add output dependencies for chain of function adjacent arguments if only
26195 there is a move to likely spilled HW register. Return first argument
26196 if at least one dependence was added or NULL otherwise. */
26199 {
26207 /* Find nearest to call argument passing instruction. */
26209 {
26218 }
26222 {
26229 {
26232 }
26234 {
26235 /* Add output depdendence between two function arguments if chain
26236 of output arguments contains likely spilled HW registers. */
26240 }
26241 else
26243 }
26247 }
26249 /* Add output or anti dependency from insn to first_arg to restrict its code
26250 motion. */
26251 static void
26253 {
26254 rtx set;
26255 rtx tmp;
26262 {
26263 /* Add output dependency to the first function argument. */
26266 }
26267 /* Add anti dependency. */
26269 }
26271 /* Avoid cross block motion of function argument through adding dependency
26272 from the first non-jump instruction in bb. */
26273 static void
26275 {
26279 {
26281 {
26284 {
26287 }
26288 }
26292 }
26293 }
26295 /* Hook for pre-reload schedule - avoid motion of function arguments
26296 passed in likely spilled HW registers. */
26297 static void
26299 {
26308 {
26311 {
26312 /* Add dependee for first argument to predecessors if only
26313 region contains more than one block. */
26317 /* Skip trivial regions and region head blocks that can have
26318 predecessors outside of region. */
26320 {
26321 edge e;
26322 edge_iterator ei;
26324 /* Regions are SCCs with the exception of selective
26325 scheduling with pipelining of outer blocks enabled.
26326 So also check that immediate predecessors of a non-head
26327 block are in the same region. */
26329 {
26330 /* Avoid creating of loop-carried dependencies through
26331 using topological ordering in the region. */
26335 }
26336 }
26340 }
26341 }
26344 }
26346 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26347 HW registers to maximum, to schedule them at soon as possible. These are
26348 moves from function argument registers at the top of the function entry
26349 and moves from function return value registers after call. */
26350 static int
26352 {
26353 rtx set;
26363 {
26370 }
26373 }
26375 /* Model decoder of Core 2/i7.
26376 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26377 track the instruction fetch block boundaries and make sure that long
26378 (9+ bytes) instructions are assigned to D0. */
26380 /* Maximum length of an insn that can be handled by
26381 a secondary decoder unit. '8' for Core 2/i7. */
26384 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26385 '16' for Core 2/i7. */
26388 /* Maximum number of instructions decoder can handle per cycle.
26389 '6' for Core 2/i7. */
26393 ix86_first_cycle_multipass_data_t;
26395 const_ix86_first_cycle_multipass_data_t;
26397 /* A variable to store target state across calls to max_issue within
26398 one cycle. */
26402 /* Initialize DATA. */
26403 static void
26405 {
26406 ix86_first_cycle_multipass_data_t data
26413 }
26415 /* Advancing the cycle; reset ifetch block counts. */
26416 static void
26418 {
26425 }
26429 /* Filter out insns from ready_try that the core will not be able to issue
26430 on current cycle due to decoder. */
26431 static void
26432 core2i7_first_cycle_multipass_filter_ready_try
26435 {
26437 {
26438 rtx insn;
26448 (!first_cycle_insn_p
26450 /* ... or it would not fit into the ifetch block ... */
26452 /* ... or the decoder is full already ... */
26454 /* ... mask the insn out. */
26455 {
26460 }
26461 }
26462 }
26464 /* Prepare for a new round of multipass lookahead scheduling. */
26465 static void
26469 {
26470 ix86_first_cycle_multipass_data_t data
26472 const_ix86_first_cycle_multipass_data_t prev_data
26475 /* Restore the state from the end of the previous round. */
26479 /* Filter instructions that cannot be issued on current cycle due to
26480 decoder restrictions. */
26482 first_cycle_insn_p);
26483 }
26485 /* INSN is being issued in current solution. Account for its impact on
26486 the decoder model. */
26487 static void
26491 {
26492 ix86_first_cycle_multipass_data_t data
26494 const_ix86_first_cycle_multipass_data_t prev_data
26504 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26506 {
26509 }
26511 {
26515 }
26518 /* Filter out insns from ready_try that the core will not be able to issue
26519 on current cycle due to decoder. */
26522 }
26524 /* Revert the effect on ready_try. */
26525 static void
26529 {
26530 const_ix86_first_cycle_multipass_data_t data
26533 sbitmap_iterator sbi;
26537 {
26539 }
26540 }
26542 /* Save the result of multipass lookahead scheduling for the next round. */
26543 static void
26545 {
26546 const_ix86_first_cycle_multipass_data_t data
26548 ix86_first_cycle_multipass_data_t next_data
26552 {
26555 }
26556 }
26558 /* Deallocate target data. */
26559 static void
26561 {
26562 ix86_first_cycle_multipass_data_t data
26566 {
26570 }
26571 }
26573 /* Prepare for scheduling pass. */
26574 static void
26576 {
26577 /* Install scheduling hooks for current CPU. Some of these hooks are used
26578 in time-critical parts of the scheduler, so we only set them up when
26579 they are actually used. */
26581 {
26586 /* Do not perform multipass scheduling for pre-reload schedule
26587 to save compile time. */
26589 {
26605 /* Set decoder parameters. */
26610 }
26611 /* ... Fall through ... */
26621 }
26622 }
26624 \f
26625 /* Compute the alignment given to a constant that is being placed in memory.
26626 EXP is the constant and ALIGN is the alignment that the object would
26627 ordinarily have.
26628 The value of this function is used instead of that alignment to align
26629 the object. */
26631 int
26633 {
26636 {
26641 }
26647 }
26649 /* Compute the alignment for a static variable.
26650 TYPE is the data type, and ALIGN is the alignment that
26651 the object would ordinarily have. The value of this function is used
26652 instead of that alignment to align the object. */
26654 int
26656 {
26657 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26658 for symbols from other compilation units or symbols that don't need
26659 to bind locally. In order to preserve some ABI compatibility with
26660 those compilers, ensure we don't decrease alignment from what we
26661 used to assume. */
26663 int max_align_compat
26666 /* A data structure, equal or greater than the size of a cache line
26667 (64 bytes in the Pentium 4 and other recent Intel processors, including
26668 processors based on Intel Core microarchitecture) should be aligned
26669 so that its base address is a multiple of a cache line size. */
26671 int max_align
26681 {
26688 }
26690 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26691 to 16byte boundary. */
26693 {
26700 }
26706 {
26711 }
26713 {
26720 }
26725 {
26730 }
26733 {
26738 }
26741 }
26743 /* Compute the alignment for a local variable or a stack slot. EXP is
26744 the data type or decl itself, MODE is the widest mode available and
26745 ALIGN is the alignment that the object would ordinarily have. The
26746 value of this macro is used instead of that alignment to align the
26747 object. */
26749 unsigned int
26752 {
26756 {
26759 }
26760 else
26761 {
26764 }
26766 /* Don't do dynamic stack realignment for long long objects with
26767 -mpreferred-stack-boundary=2. */
26776 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26777 register in MODE. We will return the largest alignment of XF
26778 and DF. */
26780 {
26784 }
26786 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26787 to 16byte boundary. Exact wording is:
26789 An array uses the same alignment as its elements, except that a local or
26790 global array variable of length at least 16 bytes or
26791 a C99 variable-length array variable always has alignment of at least 16 bytes.
26793 This was added to allow use of aligned SSE instructions at arrays. This
26794 rule is meant for static storage (where compiler can not do the analysis
26795 by itself). We follow it for automatic variables only when convenient.
26796 We fully control everything in the function compiled and functions from
26797 other unit can not rely on the alignment.
26799 Exclude va_list type. It is the common case of local array where
26800 we can not benefit from the alignment.
26802 TODO: Probably one should optimize for size only when var is not escaping. */
26805 {
26815 }
26817 {
26822 }
26824 {
26830 }
26835 {
26840 }
26843 {
26849 }
26851 }
26853 /* Compute the minimum required alignment for dynamic stack realignment
26854 purposes for a local variable, parameter or a stack slot. EXP is
26855 the data type or decl itself, MODE is its mode and ALIGN is the
26856 alignment that the object would ordinarily have. */
26858 unsigned int
26861 {
26865 {
26868 }
26869 else
26870 {
26873 }
26878 /* Don't do dynamic stack realignment for long long objects with
26879 -mpreferred-stack-boundary=2. */
26886 }
26887 \f
26888 /* Find a location for the static chain incoming to a nested function.
26889 This is a register, unless all free registers are used by arguments. */
26891 static rtx
26893 {
26900 {
26901 /* We always use R10 in 64-bit mode. */
26903 }
26904 else
26905 {
26906 tree fntype;
26909 /* By default in 32-bit mode we use ECX to pass the static chain. */
26915 {
26916 /* Fastcall functions use ecx/edx for arguments, which leaves
26917 us with EAX for the static chain.
26918 Thiscall functions use ecx for arguments, which also
26919 leaves us with EAX for the static chain. */
26921 }
26923 {
26924 /* Thiscall functions use ecx for arguments, which leaves
26925 us with EAX and EDX for the static chain.
26926 We are using for abi-compatibility EAX. */
26928 }
26930 {
26931 /* For regparm 3, we have no free call-clobbered registers in
26932 which to store the static chain. In order to implement this,
26933 we have the trampoline push the static chain to the stack.
26934 However, we can't push a value below the return address when
26935 we call the nested function directly, so we have to use an
26936 alternate entry point. For this we use ESI, and have the
26937 alternate entry point push ESI, so that things appear the
26938 same once we're executing the nested function. */
26940 {
26946 }
26948 }
26949 }
26952 }
26954 /* Emit RTL insns to initialize the variable parts of a trampoline.
26955 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26956 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26957 to be passed to the target function. */
26959 static void
26961 {
26969 {
26972 /* Load the function address to r11. Try to load address using
26973 the shorter movl instead of movabs. We may want to support
26974 movq for kernel mode, but kernel does not use trampolines at
26975 the moment. FNADDR is a 32bit address and may not be in
26976 DImode when ptr_mode == SImode. Always use movl in this
26977 case. */
26980 {
26989 }
26990 else
26991 {
26998 }
27000 /* Load static chain using movabs to r10. Use the shorter movl
27001 instead of movabs when ptr_mode == SImode. */
27003 {
27006 }
27007 else
27008 {
27011 }
27020 /* Jump to r11; the last (unused) byte is a nop, only there to
27021 pad the write out to a single 32-bit store. */
27025 }
27026 else
27027 {
27030 /* Depending on the static chain location, either load a register
27031 with a constant, or push the constant to the stack. All of the
27032 instructions are the same size. */
27035 {
27037 {
27044 }
27045 }
27046 else
27061 /* Compute offset from the end of the jmp to the target function.
27062 In the case in which the trampoline stores the static chain on
27063 the stack, we need to skip the first insn which pushes the
27064 (call-saved) register static chain; this push is 1 byte. */
27071 }
27075 #ifdef HAVE_ENABLE_EXECUTE_STACK
27076 #ifdef CHECK_EXECUTE_STACK_ENABLED
27078 #endif
27081 #endif
27082 }
27083 \f
27084 /* The following file contains several enumerations and data structures
27085 built from the definitions in i386-builtin-types.def. */
27089 /* Table for the ix86 builtin non-function types. */
27092 /* Retrieve an element from the above table, building some of
27093 the types lazily. */
27095 static tree
27097 {
27109 {
27117 }
27118 else
27119 {
27125 else
27133 }
27137 }
27139 /* Table for the ix86 builtin function types. */
27142 /* Retrieve an element from the above table, building some of
27143 the types lazily. */
27145 static tree
27147 {
27148 tree type;
27157 {
27165 {
27168 }
27171 }
27172 else
27173 {
27179 }
27183 }
27186 /* Codes for all the SSE/MMX builtins. */
27187 enum ix86_builtins
27188 {
27189 IX86_BUILTIN_ADDPS,
27190 IX86_BUILTIN_ADDSS,
27191 IX86_BUILTIN_DIVPS,
27192 IX86_BUILTIN_DIVSS,
27193 IX86_BUILTIN_MULPS,
27194 IX86_BUILTIN_MULSS,
27195 IX86_BUILTIN_SUBPS,
27196 IX86_BUILTIN_SUBSS,
27198 IX86_BUILTIN_CMPEQPS,
27199 IX86_BUILTIN_CMPLTPS,
27200 IX86_BUILTIN_CMPLEPS,
27201 IX86_BUILTIN_CMPGTPS,
27202 IX86_BUILTIN_CMPGEPS,
27203 IX86_BUILTIN_CMPNEQPS,
27204 IX86_BUILTIN_CMPNLTPS,
27205 IX86_BUILTIN_CMPNLEPS,
27206 IX86_BUILTIN_CMPNGTPS,
27207 IX86_BUILTIN_CMPNGEPS,
27208 IX86_BUILTIN_CMPORDPS,
27209 IX86_BUILTIN_CMPUNORDPS,
27210 IX86_BUILTIN_CMPEQSS,
27211 IX86_BUILTIN_CMPLTSS,
27212 IX86_BUILTIN_CMPLESS,
27213 IX86_BUILTIN_CMPNEQSS,
27214 IX86_BUILTIN_CMPNLTSS,
27215 IX86_BUILTIN_CMPNLESS,
27216 IX86_BUILTIN_CMPORDSS,
27217 IX86_BUILTIN_CMPUNORDSS,
27219 IX86_BUILTIN_COMIEQSS,
27220 IX86_BUILTIN_COMILTSS,
27221 IX86_BUILTIN_COMILESS,
27222 IX86_BUILTIN_COMIGTSS,
27223 IX86_BUILTIN_COMIGESS,
27224 IX86_BUILTIN_COMINEQSS,
27225 IX86_BUILTIN_UCOMIEQSS,
27226 IX86_BUILTIN_UCOMILTSS,
27227 IX86_BUILTIN_UCOMILESS,
27228 IX86_BUILTIN_UCOMIGTSS,
27229 IX86_BUILTIN_UCOMIGESS,
27230 IX86_BUILTIN_UCOMINEQSS,
27232 IX86_BUILTIN_CVTPI2PS,
27233 IX86_BUILTIN_CVTPS2PI,
27234 IX86_BUILTIN_CVTSI2SS,
27235 IX86_BUILTIN_CVTSI642SS,
27236 IX86_BUILTIN_CVTSS2SI,
27237 IX86_BUILTIN_CVTSS2SI64,
27238 IX86_BUILTIN_CVTTPS2PI,
27239 IX86_BUILTIN_CVTTSS2SI,
27240 IX86_BUILTIN_CVTTSS2SI64,
27242 IX86_BUILTIN_MAXPS,
27243 IX86_BUILTIN_MAXSS,
27244 IX86_BUILTIN_MINPS,
27245 IX86_BUILTIN_MINSS,
27247 IX86_BUILTIN_LOADUPS,
27248 IX86_BUILTIN_STOREUPS,
27249 IX86_BUILTIN_MOVSS,
27251 IX86_BUILTIN_MOVHLPS,
27252 IX86_BUILTIN_MOVLHPS,
27253 IX86_BUILTIN_LOADHPS,
27254 IX86_BUILTIN_LOADLPS,
27255 IX86_BUILTIN_STOREHPS,
27256 IX86_BUILTIN_STORELPS,
27258 IX86_BUILTIN_MASKMOVQ,
27259 IX86_BUILTIN_MOVMSKPS,
27260 IX86_BUILTIN_PMOVMSKB,
27262 IX86_BUILTIN_MOVNTPS,
27263 IX86_BUILTIN_MOVNTQ,
27265 IX86_BUILTIN_LOADDQU,
27266 IX86_BUILTIN_STOREDQU,
27268 IX86_BUILTIN_PACKSSWB,
27269 IX86_BUILTIN_PACKSSDW,
27270 IX86_BUILTIN_PACKUSWB,
27272 IX86_BUILTIN_PADDB,
27273 IX86_BUILTIN_PADDW,
27274 IX86_BUILTIN_PADDD,
27275 IX86_BUILTIN_PADDQ,
27276 IX86_BUILTIN_PADDSB,
27277 IX86_BUILTIN_PADDSW,
27278 IX86_BUILTIN_PADDUSB,
27279 IX86_BUILTIN_PADDUSW,
27280 IX86_BUILTIN_PSUBB,
27281 IX86_BUILTIN_PSUBW,
27282 IX86_BUILTIN_PSUBD,
27283 IX86_BUILTIN_PSUBQ,
27284 IX86_BUILTIN_PSUBSB,
27285 IX86_BUILTIN_PSUBSW,
27286 IX86_BUILTIN_PSUBUSB,
27287 IX86_BUILTIN_PSUBUSW,
27289 IX86_BUILTIN_PAND,
27290 IX86_BUILTIN_PANDN,
27291 IX86_BUILTIN_POR,
27292 IX86_BUILTIN_PXOR,
27294 IX86_BUILTIN_PAVGB,
27295 IX86_BUILTIN_PAVGW,
27297 IX86_BUILTIN_PCMPEQB,
27298 IX86_BUILTIN_PCMPEQW,
27299 IX86_BUILTIN_PCMPEQD,
27300 IX86_BUILTIN_PCMPGTB,
27301 IX86_BUILTIN_PCMPGTW,
27302 IX86_BUILTIN_PCMPGTD,
27304 IX86_BUILTIN_PMADDWD,
27306 IX86_BUILTIN_PMAXSW,
27307 IX86_BUILTIN_PMAXUB,
27308 IX86_BUILTIN_PMINSW,
27309 IX86_BUILTIN_PMINUB,
27311 IX86_BUILTIN_PMULHUW,
27312 IX86_BUILTIN_PMULHW,
27313 IX86_BUILTIN_PMULLW,
27315 IX86_BUILTIN_PSADBW,
27316 IX86_BUILTIN_PSHUFW,
27318 IX86_BUILTIN_PSLLW,
27319 IX86_BUILTIN_PSLLD,
27320 IX86_BUILTIN_PSLLQ,
27321 IX86_BUILTIN_PSRAW,
27322 IX86_BUILTIN_PSRAD,
27323 IX86_BUILTIN_PSRLW,
27324 IX86_BUILTIN_PSRLD,
27325 IX86_BUILTIN_PSRLQ,
27326 IX86_BUILTIN_PSLLWI,
27327 IX86_BUILTIN_PSLLDI,
27328 IX86_BUILTIN_PSLLQI,
27329 IX86_BUILTIN_PSRAWI,
27330 IX86_BUILTIN_PSRADI,
27331 IX86_BUILTIN_PSRLWI,
27332 IX86_BUILTIN_PSRLDI,
27333 IX86_BUILTIN_PSRLQI,
27335 IX86_BUILTIN_PUNPCKHBW,
27336 IX86_BUILTIN_PUNPCKHWD,
27337 IX86_BUILTIN_PUNPCKHDQ,
27338 IX86_BUILTIN_PUNPCKLBW,
27339 IX86_BUILTIN_PUNPCKLWD,
27340 IX86_BUILTIN_PUNPCKLDQ,
27342 IX86_BUILTIN_SHUFPS,
27344 IX86_BUILTIN_RCPPS,
27345 IX86_BUILTIN_RCPSS,
27346 IX86_BUILTIN_RSQRTPS,
27347 IX86_BUILTIN_RSQRTPS_NR,
27348 IX86_BUILTIN_RSQRTSS,
27349 IX86_BUILTIN_RSQRTF,
27350 IX86_BUILTIN_SQRTPS,
27351 IX86_BUILTIN_SQRTPS_NR,
27352 IX86_BUILTIN_SQRTSS,
27354 IX86_BUILTIN_UNPCKHPS,
27355 IX86_BUILTIN_UNPCKLPS,
27357 IX86_BUILTIN_ANDPS,
27358 IX86_BUILTIN_ANDNPS,
27359 IX86_BUILTIN_ORPS,
27360 IX86_BUILTIN_XORPS,
27362 IX86_BUILTIN_EMMS,
27363 IX86_BUILTIN_LDMXCSR,
27364 IX86_BUILTIN_STMXCSR,
27365 IX86_BUILTIN_SFENCE,
27367 IX86_BUILTIN_FXSAVE,
27368 IX86_BUILTIN_FXRSTOR,
27369 IX86_BUILTIN_FXSAVE64,
27370 IX86_BUILTIN_FXRSTOR64,
27372 IX86_BUILTIN_XSAVE,
27373 IX86_BUILTIN_XRSTOR,
27374 IX86_BUILTIN_XSAVE64,
27375 IX86_BUILTIN_XRSTOR64,
27377 IX86_BUILTIN_XSAVEOPT,
27378 IX86_BUILTIN_XSAVEOPT64,
27380 IX86_BUILTIN_XSAVEC,
27381 IX86_BUILTIN_XSAVEC64,
27383 IX86_BUILTIN_XSAVES,
27384 IX86_BUILTIN_XRSTORS,
27385 IX86_BUILTIN_XSAVES64,
27386 IX86_BUILTIN_XRSTORS64,
27388 /* 3DNow! Original */
27389 IX86_BUILTIN_FEMMS,
27390 IX86_BUILTIN_PAVGUSB,
27391 IX86_BUILTIN_PF2ID,
27392 IX86_BUILTIN_PFACC,
27393 IX86_BUILTIN_PFADD,
27394 IX86_BUILTIN_PFCMPEQ,
27395 IX86_BUILTIN_PFCMPGE,
27396 IX86_BUILTIN_PFCMPGT,
27397 IX86_BUILTIN_PFMAX,
27398 IX86_BUILTIN_PFMIN,
27399 IX86_BUILTIN_PFMUL,
27400 IX86_BUILTIN_PFRCP,
27401 IX86_BUILTIN_PFRCPIT1,
27402 IX86_BUILTIN_PFRCPIT2,
27403 IX86_BUILTIN_PFRSQIT1,
27404 IX86_BUILTIN_PFRSQRT,
27405 IX86_BUILTIN_PFSUB,
27406 IX86_BUILTIN_PFSUBR,
27407 IX86_BUILTIN_PI2FD,
27408 IX86_BUILTIN_PMULHRW,
27410 /* 3DNow! Athlon Extensions */
27411 IX86_BUILTIN_PF2IW,
27412 IX86_BUILTIN_PFNACC,
27413 IX86_BUILTIN_PFPNACC,
27414 IX86_BUILTIN_PI2FW,
27415 IX86_BUILTIN_PSWAPDSI,
27416 IX86_BUILTIN_PSWAPDSF,
27418 /* SSE2 */
27419 IX86_BUILTIN_ADDPD,
27420 IX86_BUILTIN_ADDSD,
27421 IX86_BUILTIN_DIVPD,
27422 IX86_BUILTIN_DIVSD,
27423 IX86_BUILTIN_MULPD,
27424 IX86_BUILTIN_MULSD,
27425 IX86_BUILTIN_SUBPD,
27426 IX86_BUILTIN_SUBSD,
27428 IX86_BUILTIN_CMPEQPD,
27429 IX86_BUILTIN_CMPLTPD,
27430 IX86_BUILTIN_CMPLEPD,
27431 IX86_BUILTIN_CMPGTPD,
27432 IX86_BUILTIN_CMPGEPD,
27433 IX86_BUILTIN_CMPNEQPD,
27434 IX86_BUILTIN_CMPNLTPD,
27435 IX86_BUILTIN_CMPNLEPD,
27436 IX86_BUILTIN_CMPNGTPD,
27437 IX86_BUILTIN_CMPNGEPD,
27438 IX86_BUILTIN_CMPORDPD,
27439 IX86_BUILTIN_CMPUNORDPD,
27440 IX86_BUILTIN_CMPEQSD,
27441 IX86_BUILTIN_CMPLTSD,
27442 IX86_BUILTIN_CMPLESD,
27443 IX86_BUILTIN_CMPNEQSD,
27444 IX86_BUILTIN_CMPNLTSD,
27445 IX86_BUILTIN_CMPNLESD,
27446 IX86_BUILTIN_CMPORDSD,
27447 IX86_BUILTIN_CMPUNORDSD,
27449 IX86_BUILTIN_COMIEQSD,
27450 IX86_BUILTIN_COMILTSD,
27451 IX86_BUILTIN_COMILESD,
27452 IX86_BUILTIN_COMIGTSD,
27453 IX86_BUILTIN_COMIGESD,
27454 IX86_BUILTIN_COMINEQSD,
27455 IX86_BUILTIN_UCOMIEQSD,
27456 IX86_BUILTIN_UCOMILTSD,
27457 IX86_BUILTIN_UCOMILESD,
27458 IX86_BUILTIN_UCOMIGTSD,
27459 IX86_BUILTIN_UCOMIGESD,
27460 IX86_BUILTIN_UCOMINEQSD,
27462 IX86_BUILTIN_MAXPD,
27463 IX86_BUILTIN_MAXSD,
27464 IX86_BUILTIN_MINPD,
27465 IX86_BUILTIN_MINSD,
27467 IX86_BUILTIN_ANDPD,
27468 IX86_BUILTIN_ANDNPD,
27469 IX86_BUILTIN_ORPD,
27470 IX86_BUILTIN_XORPD,
27472 IX86_BUILTIN_SQRTPD,
27473 IX86_BUILTIN_SQRTSD,
27475 IX86_BUILTIN_UNPCKHPD,
27476 IX86_BUILTIN_UNPCKLPD,
27478 IX86_BUILTIN_SHUFPD,
27480 IX86_BUILTIN_LOADUPD,
27481 IX86_BUILTIN_STOREUPD,
27482 IX86_BUILTIN_MOVSD,
27484 IX86_BUILTIN_LOADHPD,
27485 IX86_BUILTIN_LOADLPD,
27487 IX86_BUILTIN_CVTDQ2PD,
27488 IX86_BUILTIN_CVTDQ2PS,
27490 IX86_BUILTIN_CVTPD2DQ,
27491 IX86_BUILTIN_CVTPD2PI,
27492 IX86_BUILTIN_CVTPD2PS,
27493 IX86_BUILTIN_CVTTPD2DQ,
27494 IX86_BUILTIN_CVTTPD2PI,
27496 IX86_BUILTIN_CVTPI2PD,
27497 IX86_BUILTIN_CVTSI2SD,
27498 IX86_BUILTIN_CVTSI642SD,
27500 IX86_BUILTIN_CVTSD2SI,
27501 IX86_BUILTIN_CVTSD2SI64,
27502 IX86_BUILTIN_CVTSD2SS,
27503 IX86_BUILTIN_CVTSS2SD,
27504 IX86_BUILTIN_CVTTSD2SI,
27505 IX86_BUILTIN_CVTTSD2SI64,
27507 IX86_BUILTIN_CVTPS2DQ,
27508 IX86_BUILTIN_CVTPS2PD,
27509 IX86_BUILTIN_CVTTPS2DQ,
27511 IX86_BUILTIN_MOVNTI,
27512 IX86_BUILTIN_MOVNTI64,
27513 IX86_BUILTIN_MOVNTPD,
27514 IX86_BUILTIN_MOVNTDQ,
27516 IX86_BUILTIN_MOVQ128,
27518 /* SSE2 MMX */
27519 IX86_BUILTIN_MASKMOVDQU,
27520 IX86_BUILTIN_MOVMSKPD,
27521 IX86_BUILTIN_PMOVMSKB128,
27523 IX86_BUILTIN_PACKSSWB128,
27524 IX86_BUILTIN_PACKSSDW128,
27525 IX86_BUILTIN_PACKUSWB128,
27527 IX86_BUILTIN_PADDB128,
27528 IX86_BUILTIN_PADDW128,
27529 IX86_BUILTIN_PADDD128,
27530 IX86_BUILTIN_PADDQ128,
27531 IX86_BUILTIN_PADDSB128,
27532 IX86_BUILTIN_PADDSW128,
27533 IX86_BUILTIN_PADDUSB128,
27534 IX86_BUILTIN_PADDUSW128,
27535 IX86_BUILTIN_PSUBB128,
27536 IX86_BUILTIN_PSUBW128,
27537 IX86_BUILTIN_PSUBD128,
27538 IX86_BUILTIN_PSUBQ128,
27539 IX86_BUILTIN_PSUBSB128,
27540 IX86_BUILTIN_PSUBSW128,
27541 IX86_BUILTIN_PSUBUSB128,
27542 IX86_BUILTIN_PSUBUSW128,
27544 IX86_BUILTIN_PAND128,
27545 IX86_BUILTIN_PANDN128,
27546 IX86_BUILTIN_POR128,
27547 IX86_BUILTIN_PXOR128,
27549 IX86_BUILTIN_PAVGB128,
27550 IX86_BUILTIN_PAVGW128,
27552 IX86_BUILTIN_PCMPEQB128,
27553 IX86_BUILTIN_PCMPEQW128,
27554 IX86_BUILTIN_PCMPEQD128,
27555 IX86_BUILTIN_PCMPGTB128,
27556 IX86_BUILTIN_PCMPGTW128,
27557 IX86_BUILTIN_PCMPGTD128,
27559 IX86_BUILTIN_PMADDWD128,
27561 IX86_BUILTIN_PMAXSW128,
27562 IX86_BUILTIN_PMAXUB128,
27563 IX86_BUILTIN_PMINSW128,
27564 IX86_BUILTIN_PMINUB128,
27566 IX86_BUILTIN_PMULUDQ,
27567 IX86_BUILTIN_PMULUDQ128,
27568 IX86_BUILTIN_PMULHUW128,
27569 IX86_BUILTIN_PMULHW128,
27570 IX86_BUILTIN_PMULLW128,
27572 IX86_BUILTIN_PSADBW128,
27573 IX86_BUILTIN_PSHUFHW,
27574 IX86_BUILTIN_PSHUFLW,
27575 IX86_BUILTIN_PSHUFD,
27577 IX86_BUILTIN_PSLLDQI128,
27578 IX86_BUILTIN_PSLLWI128,
27579 IX86_BUILTIN_PSLLDI128,
27580 IX86_BUILTIN_PSLLQI128,
27581 IX86_BUILTIN_PSRAWI128,
27582 IX86_BUILTIN_PSRADI128,
27583 IX86_BUILTIN_PSRLDQI128,
27584 IX86_BUILTIN_PSRLWI128,
27585 IX86_BUILTIN_PSRLDI128,
27586 IX86_BUILTIN_PSRLQI128,
27588 IX86_BUILTIN_PSLLDQ128,
27589 IX86_BUILTIN_PSLLW128,
27590 IX86_BUILTIN_PSLLD128,
27591 IX86_BUILTIN_PSLLQ128,
27592 IX86_BUILTIN_PSRAW128,
27593 IX86_BUILTIN_PSRAD128,
27594 IX86_BUILTIN_PSRLW128,
27595 IX86_BUILTIN_PSRLD128,
27596 IX86_BUILTIN_PSRLQ128,
27598 IX86_BUILTIN_PUNPCKHBW128,
27599 IX86_BUILTIN_PUNPCKHWD128,
27600 IX86_BUILTIN_PUNPCKHDQ128,
27601 IX86_BUILTIN_PUNPCKHQDQ128,
27602 IX86_BUILTIN_PUNPCKLBW128,
27603 IX86_BUILTIN_PUNPCKLWD128,
27604 IX86_BUILTIN_PUNPCKLDQ128,
27605 IX86_BUILTIN_PUNPCKLQDQ128,
27607 IX86_BUILTIN_CLFLUSH,
27608 IX86_BUILTIN_MFENCE,
27609 IX86_BUILTIN_LFENCE,
27610 IX86_BUILTIN_PAUSE,
27612 IX86_BUILTIN_FNSTENV,
27613 IX86_BUILTIN_FLDENV,
27614 IX86_BUILTIN_FNSTSW,
27615 IX86_BUILTIN_FNCLEX,
27617 IX86_BUILTIN_BSRSI,
27618 IX86_BUILTIN_BSRDI,
27619 IX86_BUILTIN_RDPMC,
27620 IX86_BUILTIN_RDTSC,
27621 IX86_BUILTIN_RDTSCP,
27622 IX86_BUILTIN_ROLQI,
27623 IX86_BUILTIN_ROLHI,
27624 IX86_BUILTIN_RORQI,
27625 IX86_BUILTIN_RORHI,
27627 /* SSE3. */
27628 IX86_BUILTIN_ADDSUBPS,
27629 IX86_BUILTIN_HADDPS,
27630 IX86_BUILTIN_HSUBPS,
27631 IX86_BUILTIN_MOVSHDUP,
27632 IX86_BUILTIN_MOVSLDUP,
27633 IX86_BUILTIN_ADDSUBPD,
27634 IX86_BUILTIN_HADDPD,
27635 IX86_BUILTIN_HSUBPD,
27636 IX86_BUILTIN_LDDQU,
27638 IX86_BUILTIN_MONITOR,
27639 IX86_BUILTIN_MWAIT,
27641 /* SSSE3. */
27642 IX86_BUILTIN_PHADDW,
27643 IX86_BUILTIN_PHADDD,
27644 IX86_BUILTIN_PHADDSW,
27645 IX86_BUILTIN_PHSUBW,
27646 IX86_BUILTIN_PHSUBD,
27647 IX86_BUILTIN_PHSUBSW,
27648 IX86_BUILTIN_PMADDUBSW,
27649 IX86_BUILTIN_PMULHRSW,
27650 IX86_BUILTIN_PSHUFB,
27651 IX86_BUILTIN_PSIGNB,
27652 IX86_BUILTIN_PSIGNW,
27653 IX86_BUILTIN_PSIGND,
27654 IX86_BUILTIN_PALIGNR,
27655 IX86_BUILTIN_PABSB,
27656 IX86_BUILTIN_PABSW,
27657 IX86_BUILTIN_PABSD,
27659 IX86_BUILTIN_PHADDW128,
27660 IX86_BUILTIN_PHADDD128,
27661 IX86_BUILTIN_PHADDSW128,
27662 IX86_BUILTIN_PHSUBW128,
27663 IX86_BUILTIN_PHSUBD128,
27664 IX86_BUILTIN_PHSUBSW128,
27665 IX86_BUILTIN_PMADDUBSW128,
27666 IX86_BUILTIN_PMULHRSW128,
27667 IX86_BUILTIN_PSHUFB128,
27668 IX86_BUILTIN_PSIGNB128,
27669 IX86_BUILTIN_PSIGNW128,
27670 IX86_BUILTIN_PSIGND128,
27671 IX86_BUILTIN_PALIGNR128,
27672 IX86_BUILTIN_PABSB128,
27673 IX86_BUILTIN_PABSW128,
27674 IX86_BUILTIN_PABSD128,
27676 /* AMDFAM10 - SSE4A New Instructions. */
27677 IX86_BUILTIN_MOVNTSD,
27678 IX86_BUILTIN_MOVNTSS,
27679 IX86_BUILTIN_EXTRQI,
27680 IX86_BUILTIN_EXTRQ,
27681 IX86_BUILTIN_INSERTQI,
27682 IX86_BUILTIN_INSERTQ,
27684 /* SSE4.1. */
27685 IX86_BUILTIN_BLENDPD,
27686 IX86_BUILTIN_BLENDPS,
27687 IX86_BUILTIN_BLENDVPD,
27688 IX86_BUILTIN_BLENDVPS,
27689 IX86_BUILTIN_PBLENDVB128,
27690 IX86_BUILTIN_PBLENDW128,
27692 IX86_BUILTIN_DPPD,
27693 IX86_BUILTIN_DPPS,
27695 IX86_BUILTIN_INSERTPS128,
27697 IX86_BUILTIN_MOVNTDQA,
27698 IX86_BUILTIN_MPSADBW128,
27699 IX86_BUILTIN_PACKUSDW128,
27700 IX86_BUILTIN_PCMPEQQ,
27701 IX86_BUILTIN_PHMINPOSUW128,
27703 IX86_BUILTIN_PMAXSB128,
27704 IX86_BUILTIN_PMAXSD128,
27705 IX86_BUILTIN_PMAXUD128,
27706 IX86_BUILTIN_PMAXUW128,
27708 IX86_BUILTIN_PMINSB128,
27709 IX86_BUILTIN_PMINSD128,
27710 IX86_BUILTIN_PMINUD128,
27711 IX86_BUILTIN_PMINUW128,
27713 IX86_BUILTIN_PMOVSXBW128,
27714 IX86_BUILTIN_PMOVSXBD128,
27715 IX86_BUILTIN_PMOVSXBQ128,
27716 IX86_BUILTIN_PMOVSXWD128,
27717 IX86_BUILTIN_PMOVSXWQ128,
27718 IX86_BUILTIN_PMOVSXDQ128,
27720 IX86_BUILTIN_PMOVZXBW128,
27721 IX86_BUILTIN_PMOVZXBD128,
27722 IX86_BUILTIN_PMOVZXBQ128,
27723 IX86_BUILTIN_PMOVZXWD128,
27724 IX86_BUILTIN_PMOVZXWQ128,
27725 IX86_BUILTIN_PMOVZXDQ128,
27727 IX86_BUILTIN_PMULDQ128,
27728 IX86_BUILTIN_PMULLD128,
27730 IX86_BUILTIN_ROUNDSD,
27731 IX86_BUILTIN_ROUNDSS,
27733 IX86_BUILTIN_ROUNDPD,
27734 IX86_BUILTIN_ROUNDPS,
27736 IX86_BUILTIN_FLOORPD,
27737 IX86_BUILTIN_CEILPD,
27738 IX86_BUILTIN_TRUNCPD,
27739 IX86_BUILTIN_RINTPD,
27740 IX86_BUILTIN_ROUNDPD_AZ,
27742 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27743 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27744 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27746 IX86_BUILTIN_FLOORPS,
27747 IX86_BUILTIN_CEILPS,
27748 IX86_BUILTIN_TRUNCPS,
27749 IX86_BUILTIN_RINTPS,
27750 IX86_BUILTIN_ROUNDPS_AZ,
27752 IX86_BUILTIN_FLOORPS_SFIX,
27753 IX86_BUILTIN_CEILPS_SFIX,
27754 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27756 IX86_BUILTIN_PTESTZ,
27757 IX86_BUILTIN_PTESTC,
27758 IX86_BUILTIN_PTESTNZC,
27760 IX86_BUILTIN_VEC_INIT_V2SI,
27761 IX86_BUILTIN_VEC_INIT_V4HI,
27762 IX86_BUILTIN_VEC_INIT_V8QI,
27763 IX86_BUILTIN_VEC_EXT_V2DF,
27764 IX86_BUILTIN_VEC_EXT_V2DI,
27765 IX86_BUILTIN_VEC_EXT_V4SF,
27766 IX86_BUILTIN_VEC_EXT_V4SI,
27767 IX86_BUILTIN_VEC_EXT_V8HI,
27768 IX86_BUILTIN_VEC_EXT_V2SI,
27769 IX86_BUILTIN_VEC_EXT_V4HI,
27770 IX86_BUILTIN_VEC_EXT_V16QI,
27771 IX86_BUILTIN_VEC_SET_V2DI,
27772 IX86_BUILTIN_VEC_SET_V4SF,
27773 IX86_BUILTIN_VEC_SET_V4SI,
27774 IX86_BUILTIN_VEC_SET_V8HI,
27775 IX86_BUILTIN_VEC_SET_V4HI,
27776 IX86_BUILTIN_VEC_SET_V16QI,
27778 IX86_BUILTIN_VEC_PACK_SFIX,
27779 IX86_BUILTIN_VEC_PACK_SFIX256,
27781 /* SSE4.2. */
27782 IX86_BUILTIN_CRC32QI,
27783 IX86_BUILTIN_CRC32HI,
27784 IX86_BUILTIN_CRC32SI,
27785 IX86_BUILTIN_CRC32DI,
27787 IX86_BUILTIN_PCMPESTRI128,
27788 IX86_BUILTIN_PCMPESTRM128,
27789 IX86_BUILTIN_PCMPESTRA128,
27790 IX86_BUILTIN_PCMPESTRC128,
27791 IX86_BUILTIN_PCMPESTRO128,
27792 IX86_BUILTIN_PCMPESTRS128,
27793 IX86_BUILTIN_PCMPESTRZ128,
27794 IX86_BUILTIN_PCMPISTRI128,
27795 IX86_BUILTIN_PCMPISTRM128,
27796 IX86_BUILTIN_PCMPISTRA128,
27797 IX86_BUILTIN_PCMPISTRC128,
27798 IX86_BUILTIN_PCMPISTRO128,
27799 IX86_BUILTIN_PCMPISTRS128,
27800 IX86_BUILTIN_PCMPISTRZ128,
27802 IX86_BUILTIN_PCMPGTQ,
27804 /* AES instructions */
27805 IX86_BUILTIN_AESENC128,
27806 IX86_BUILTIN_AESENCLAST128,
27807 IX86_BUILTIN_AESDEC128,
27808 IX86_BUILTIN_AESDECLAST128,
27809 IX86_BUILTIN_AESIMC128,
27810 IX86_BUILTIN_AESKEYGENASSIST128,
27812 /* PCLMUL instruction */
27813 IX86_BUILTIN_PCLMULQDQ128,
27815 /* AVX */
27816 IX86_BUILTIN_ADDPD256,
27817 IX86_BUILTIN_ADDPS256,
27818 IX86_BUILTIN_ADDSUBPD256,
27819 IX86_BUILTIN_ADDSUBPS256,
27820 IX86_BUILTIN_ANDPD256,
27821 IX86_BUILTIN_ANDPS256,
27822 IX86_BUILTIN_ANDNPD256,
27823 IX86_BUILTIN_ANDNPS256,
27824 IX86_BUILTIN_BLENDPD256,
27825 IX86_BUILTIN_BLENDPS256,
27826 IX86_BUILTIN_BLENDVPD256,
27827 IX86_BUILTIN_BLENDVPS256,
27828 IX86_BUILTIN_DIVPD256,
27829 IX86_BUILTIN_DIVPS256,
27830 IX86_BUILTIN_DPPS256,
27831 IX86_BUILTIN_HADDPD256,
27832 IX86_BUILTIN_HADDPS256,
27833 IX86_BUILTIN_HSUBPD256,
27834 IX86_BUILTIN_HSUBPS256,
27835 IX86_BUILTIN_MAXPD256,
27836 IX86_BUILTIN_MAXPS256,
27837 IX86_BUILTIN_MINPD256,
27838 IX86_BUILTIN_MINPS256,
27839 IX86_BUILTIN_MULPD256,
27840 IX86_BUILTIN_MULPS256,
27841 IX86_BUILTIN_ORPD256,
27842 IX86_BUILTIN_ORPS256,
27843 IX86_BUILTIN_SHUFPD256,
27844 IX86_BUILTIN_SHUFPS256,
27845 IX86_BUILTIN_SUBPD256,
27846 IX86_BUILTIN_SUBPS256,
27847 IX86_BUILTIN_XORPD256,
27848 IX86_BUILTIN_XORPS256,
27849 IX86_BUILTIN_CMPSD,
27850 IX86_BUILTIN_CMPSS,
27851 IX86_BUILTIN_CMPPD,
27852 IX86_BUILTIN_CMPPS,
27853 IX86_BUILTIN_CMPPD256,
27854 IX86_BUILTIN_CMPPS256,
27855 IX86_BUILTIN_CVTDQ2PD256,
27856 IX86_BUILTIN_CVTDQ2PS256,
27857 IX86_BUILTIN_CVTPD2PS256,
27858 IX86_BUILTIN_CVTPS2DQ256,
27859 IX86_BUILTIN_CVTPS2PD256,
27860 IX86_BUILTIN_CVTTPD2DQ256,
27861 IX86_BUILTIN_CVTPD2DQ256,
27862 IX86_BUILTIN_CVTTPS2DQ256,
27863 IX86_BUILTIN_EXTRACTF128PD256,
27864 IX86_BUILTIN_EXTRACTF128PS256,
27865 IX86_BUILTIN_EXTRACTF128SI256,
27866 IX86_BUILTIN_VZEROALL,
27867 IX86_BUILTIN_VZEROUPPER,
27868 IX86_BUILTIN_VPERMILVARPD,
27869 IX86_BUILTIN_VPERMILVARPS,
27870 IX86_BUILTIN_VPERMILVARPD256,
27871 IX86_BUILTIN_VPERMILVARPS256,
27872 IX86_BUILTIN_VPERMILPD,
27873 IX86_BUILTIN_VPERMILPS,
27874 IX86_BUILTIN_VPERMILPD256,
27875 IX86_BUILTIN_VPERMILPS256,
27876 IX86_BUILTIN_VPERMIL2PD,
27877 IX86_BUILTIN_VPERMIL2PS,
27878 IX86_BUILTIN_VPERMIL2PD256,
27879 IX86_BUILTIN_VPERMIL2PS256,
27880 IX86_BUILTIN_VPERM2F128PD256,
27881 IX86_BUILTIN_VPERM2F128PS256,
27882 IX86_BUILTIN_VPERM2F128SI256,
27883 IX86_BUILTIN_VBROADCASTSS,
27884 IX86_BUILTIN_VBROADCASTSD256,
27885 IX86_BUILTIN_VBROADCASTSS256,
27886 IX86_BUILTIN_VBROADCASTPD256,
27887 IX86_BUILTIN_VBROADCASTPS256,
27888 IX86_BUILTIN_VINSERTF128PD256,
27889 IX86_BUILTIN_VINSERTF128PS256,
27890 IX86_BUILTIN_VINSERTF128SI256,
27891 IX86_BUILTIN_LOADUPD256,
27892 IX86_BUILTIN_LOADUPS256,
27893 IX86_BUILTIN_STOREUPD256,
27894 IX86_BUILTIN_STOREUPS256,
27895 IX86_BUILTIN_LDDQU256,
27896 IX86_BUILTIN_MOVNTDQ256,
27897 IX86_BUILTIN_MOVNTPD256,
27898 IX86_BUILTIN_MOVNTPS256,
27899 IX86_BUILTIN_LOADDQU256,
27900 IX86_BUILTIN_STOREDQU256,
27901 IX86_BUILTIN_MASKLOADPD,
27902 IX86_BUILTIN_MASKLOADPS,
27903 IX86_BUILTIN_MASKSTOREPD,
27904 IX86_BUILTIN_MASKSTOREPS,
27905 IX86_BUILTIN_MASKLOADPD256,
27906 IX86_BUILTIN_MASKLOADPS256,
27907 IX86_BUILTIN_MASKSTOREPD256,
27908 IX86_BUILTIN_MASKSTOREPS256,
27909 IX86_BUILTIN_MOVSHDUP256,
27910 IX86_BUILTIN_MOVSLDUP256,
27911 IX86_BUILTIN_MOVDDUP256,
27913 IX86_BUILTIN_SQRTPD256,
27914 IX86_BUILTIN_SQRTPS256,
27915 IX86_BUILTIN_SQRTPS_NR256,
27916 IX86_BUILTIN_RSQRTPS256,
27917 IX86_BUILTIN_RSQRTPS_NR256,
27919 IX86_BUILTIN_RCPPS256,
27921 IX86_BUILTIN_ROUNDPD256,
27922 IX86_BUILTIN_ROUNDPS256,
27924 IX86_BUILTIN_FLOORPD256,
27925 IX86_BUILTIN_CEILPD256,
27926 IX86_BUILTIN_TRUNCPD256,
27927 IX86_BUILTIN_RINTPD256,
27928 IX86_BUILTIN_ROUNDPD_AZ256,
27930 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27931 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27932 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27934 IX86_BUILTIN_FLOORPS256,
27935 IX86_BUILTIN_CEILPS256,
27936 IX86_BUILTIN_TRUNCPS256,
27937 IX86_BUILTIN_RINTPS256,
27938 IX86_BUILTIN_ROUNDPS_AZ256,
27940 IX86_BUILTIN_FLOORPS_SFIX256,
27941 IX86_BUILTIN_CEILPS_SFIX256,
27942 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27944 IX86_BUILTIN_UNPCKHPD256,
27945 IX86_BUILTIN_UNPCKLPD256,
27946 IX86_BUILTIN_UNPCKHPS256,
27947 IX86_BUILTIN_UNPCKLPS256,
27949 IX86_BUILTIN_SI256_SI,
27950 IX86_BUILTIN_PS256_PS,
27951 IX86_BUILTIN_PD256_PD,
27952 IX86_BUILTIN_SI_SI256,
27953 IX86_BUILTIN_PS_PS256,
27954 IX86_BUILTIN_PD_PD256,
27956 IX86_BUILTIN_VTESTZPD,
27957 IX86_BUILTIN_VTESTCPD,
27958 IX86_BUILTIN_VTESTNZCPD,
27959 IX86_BUILTIN_VTESTZPS,
27960 IX86_BUILTIN_VTESTCPS,
27961 IX86_BUILTIN_VTESTNZCPS,
27962 IX86_BUILTIN_VTESTZPD256,
27963 IX86_BUILTIN_VTESTCPD256,
27964 IX86_BUILTIN_VTESTNZCPD256,
27965 IX86_BUILTIN_VTESTZPS256,
27966 IX86_BUILTIN_VTESTCPS256,
27967 IX86_BUILTIN_VTESTNZCPS256,
27968 IX86_BUILTIN_PTESTZ256,
27969 IX86_BUILTIN_PTESTC256,
27970 IX86_BUILTIN_PTESTNZC256,
27972 IX86_BUILTIN_MOVMSKPD256,
27973 IX86_BUILTIN_MOVMSKPS256,
27975 /* AVX2 */
27976 IX86_BUILTIN_MPSADBW256,
27977 IX86_BUILTIN_PABSB256,
27978 IX86_BUILTIN_PABSW256,
27979 IX86_BUILTIN_PABSD256,
27980 IX86_BUILTIN_PACKSSDW256,
27981 IX86_BUILTIN_PACKSSWB256,
27982 IX86_BUILTIN_PACKUSDW256,
27983 IX86_BUILTIN_PACKUSWB256,
27984 IX86_BUILTIN_PADDB256,
27985 IX86_BUILTIN_PADDW256,
27986 IX86_BUILTIN_PADDD256,
27987 IX86_BUILTIN_PADDQ256,
27988 IX86_BUILTIN_PADDSB256,
27989 IX86_BUILTIN_PADDSW256,
27990 IX86_BUILTIN_PADDUSB256,
27991 IX86_BUILTIN_PADDUSW256,
27992 IX86_BUILTIN_PALIGNR256,
27993 IX86_BUILTIN_AND256I,
27994 IX86_BUILTIN_ANDNOT256I,
27995 IX86_BUILTIN_PAVGB256,
27996 IX86_BUILTIN_PAVGW256,
27997 IX86_BUILTIN_PBLENDVB256,
27998 IX86_BUILTIN_PBLENDVW256,
27999 IX86_BUILTIN_PCMPEQB256,
28000 IX86_BUILTIN_PCMPEQW256,
28001 IX86_BUILTIN_PCMPEQD256,
28002 IX86_BUILTIN_PCMPEQQ256,
28003 IX86_BUILTIN_PCMPGTB256,
28004 IX86_BUILTIN_PCMPGTW256,
28005 IX86_BUILTIN_PCMPGTD256,
28006 IX86_BUILTIN_PCMPGTQ256,
28007 IX86_BUILTIN_PHADDW256,
28008 IX86_BUILTIN_PHADDD256,
28009 IX86_BUILTIN_PHADDSW256,
28010 IX86_BUILTIN_PHSUBW256,
28011 IX86_BUILTIN_PHSUBD256,
28012 IX86_BUILTIN_PHSUBSW256,
28013 IX86_BUILTIN_PMADDUBSW256,
28014 IX86_BUILTIN_PMADDWD256,
28015 IX86_BUILTIN_PMAXSB256,
28016 IX86_BUILTIN_PMAXSW256,
28017 IX86_BUILTIN_PMAXSD256,
28018 IX86_BUILTIN_PMAXUB256,
28019 IX86_BUILTIN_PMAXUW256,
28020 IX86_BUILTIN_PMAXUD256,
28021 IX86_BUILTIN_PMINSB256,
28022 IX86_BUILTIN_PMINSW256,
28023 IX86_BUILTIN_PMINSD256,
28024 IX86_BUILTIN_PMINUB256,
28025 IX86_BUILTIN_PMINUW256,
28026 IX86_BUILTIN_PMINUD256,
28027 IX86_BUILTIN_PMOVMSKB256,
28028 IX86_BUILTIN_PMOVSXBW256,
28029 IX86_BUILTIN_PMOVSXBD256,
28030 IX86_BUILTIN_PMOVSXBQ256,
28031 IX86_BUILTIN_PMOVSXWD256,
28032 IX86_BUILTIN_PMOVSXWQ256,
28033 IX86_BUILTIN_PMOVSXDQ256,
28034 IX86_BUILTIN_PMOVZXBW256,
28035 IX86_BUILTIN_PMOVZXBD256,
28036 IX86_BUILTIN_PMOVZXBQ256,
28037 IX86_BUILTIN_PMOVZXWD256,
28038 IX86_BUILTIN_PMOVZXWQ256,
28039 IX86_BUILTIN_PMOVZXDQ256,
28040 IX86_BUILTIN_PMULDQ256,
28041 IX86_BUILTIN_PMULHRSW256,
28042 IX86_BUILTIN_PMULHUW256,
28043 IX86_BUILTIN_PMULHW256,
28044 IX86_BUILTIN_PMULLW256,
28045 IX86_BUILTIN_PMULLD256,
28046 IX86_BUILTIN_PMULUDQ256,
28047 IX86_BUILTIN_POR256,
28048 IX86_BUILTIN_PSADBW256,
28049 IX86_BUILTIN_PSHUFB256,
28050 IX86_BUILTIN_PSHUFD256,
28051 IX86_BUILTIN_PSHUFHW256,
28052 IX86_BUILTIN_PSHUFLW256,
28053 IX86_BUILTIN_PSIGNB256,
28054 IX86_BUILTIN_PSIGNW256,
28055 IX86_BUILTIN_PSIGND256,
28056 IX86_BUILTIN_PSLLDQI256,
28057 IX86_BUILTIN_PSLLWI256,
28058 IX86_BUILTIN_PSLLW256,
28059 IX86_BUILTIN_PSLLDI256,
28060 IX86_BUILTIN_PSLLD256,
28061 IX86_BUILTIN_PSLLQI256,
28062 IX86_BUILTIN_PSLLQ256,
28063 IX86_BUILTIN_PSRAWI256,
28064 IX86_BUILTIN_PSRAW256,
28065 IX86_BUILTIN_PSRADI256,
28066 IX86_BUILTIN_PSRAD256,
28067 IX86_BUILTIN_PSRLDQI256,
28068 IX86_BUILTIN_PSRLWI256,
28069 IX86_BUILTIN_PSRLW256,
28070 IX86_BUILTIN_PSRLDI256,
28071 IX86_BUILTIN_PSRLD256,
28072 IX86_BUILTIN_PSRLQI256,
28073 IX86_BUILTIN_PSRLQ256,
28074 IX86_BUILTIN_PSUBB256,
28075 IX86_BUILTIN_PSUBW256,
28076 IX86_BUILTIN_PSUBD256,
28077 IX86_BUILTIN_PSUBQ256,
28078 IX86_BUILTIN_PSUBSB256,
28079 IX86_BUILTIN_PSUBSW256,
28080 IX86_BUILTIN_PSUBUSB256,
28081 IX86_BUILTIN_PSUBUSW256,
28082 IX86_BUILTIN_PUNPCKHBW256,
28083 IX86_BUILTIN_PUNPCKHWD256,
28084 IX86_BUILTIN_PUNPCKHDQ256,
28085 IX86_BUILTIN_PUNPCKHQDQ256,
28086 IX86_BUILTIN_PUNPCKLBW256,
28087 IX86_BUILTIN_PUNPCKLWD256,
28088 IX86_BUILTIN_PUNPCKLDQ256,
28089 IX86_BUILTIN_PUNPCKLQDQ256,
28090 IX86_BUILTIN_PXOR256,
28091 IX86_BUILTIN_MOVNTDQA256,
28092 IX86_BUILTIN_VBROADCASTSS_PS,
28093 IX86_BUILTIN_VBROADCASTSS_PS256,
28094 IX86_BUILTIN_VBROADCASTSD_PD256,
28095 IX86_BUILTIN_VBROADCASTSI256,
28096 IX86_BUILTIN_PBLENDD256,
28097 IX86_BUILTIN_PBLENDD128,
28098 IX86_BUILTIN_PBROADCASTB256,
28099 IX86_BUILTIN_PBROADCASTW256,
28100 IX86_BUILTIN_PBROADCASTD256,
28101 IX86_BUILTIN_PBROADCASTQ256,
28102 IX86_BUILTIN_PBROADCASTB128,
28103 IX86_BUILTIN_PBROADCASTW128,
28104 IX86_BUILTIN_PBROADCASTD128,
28105 IX86_BUILTIN_PBROADCASTQ128,
28106 IX86_BUILTIN_VPERMVARSI256,
28107 IX86_BUILTIN_VPERMDF256,
28108 IX86_BUILTIN_VPERMVARSF256,
28109 IX86_BUILTIN_VPERMDI256,
28110 IX86_BUILTIN_VPERMTI256,
28111 IX86_BUILTIN_VEXTRACT128I256,
28112 IX86_BUILTIN_VINSERT128I256,
28113 IX86_BUILTIN_MASKLOADD,
28114 IX86_BUILTIN_MASKLOADQ,
28115 IX86_BUILTIN_MASKLOADD256,
28116 IX86_BUILTIN_MASKLOADQ256,
28117 IX86_BUILTIN_MASKSTORED,
28118 IX86_BUILTIN_MASKSTOREQ,
28119 IX86_BUILTIN_MASKSTORED256,
28120 IX86_BUILTIN_MASKSTOREQ256,
28121 IX86_BUILTIN_PSLLVV4DI,
28122 IX86_BUILTIN_PSLLVV2DI,
28123 IX86_BUILTIN_PSLLVV8SI,
28124 IX86_BUILTIN_PSLLVV4SI,
28125 IX86_BUILTIN_PSRAVV8SI,
28126 IX86_BUILTIN_PSRAVV4SI,
28127 IX86_BUILTIN_PSRLVV4DI,
28128 IX86_BUILTIN_PSRLVV2DI,
28129 IX86_BUILTIN_PSRLVV8SI,
28130 IX86_BUILTIN_PSRLVV4SI,
28132 IX86_BUILTIN_GATHERSIV2DF,
28133 IX86_BUILTIN_GATHERSIV4DF,
28134 IX86_BUILTIN_GATHERDIV2DF,
28135 IX86_BUILTIN_GATHERDIV4DF,
28136 IX86_BUILTIN_GATHERSIV4SF,
28137 IX86_BUILTIN_GATHERSIV8SF,
28138 IX86_BUILTIN_GATHERDIV4SF,
28139 IX86_BUILTIN_GATHERDIV8SF,
28140 IX86_BUILTIN_GATHERSIV2DI,
28141 IX86_BUILTIN_GATHERSIV4DI,
28142 IX86_BUILTIN_GATHERDIV2DI,
28143 IX86_BUILTIN_GATHERDIV4DI,
28144 IX86_BUILTIN_GATHERSIV4SI,
28145 IX86_BUILTIN_GATHERSIV8SI,
28146 IX86_BUILTIN_GATHERDIV4SI,
28147 IX86_BUILTIN_GATHERDIV8SI,
28149 /* AVX512F */
28150 IX86_BUILTIN_SI512_SI256,
28151 IX86_BUILTIN_PD512_PD256,
28152 IX86_BUILTIN_PS512_PS256,
28153 IX86_BUILTIN_SI512_SI,
28154 IX86_BUILTIN_PD512_PD,
28155 IX86_BUILTIN_PS512_PS,
28156 IX86_BUILTIN_ADDPD512,
28157 IX86_BUILTIN_ADDPS512,
28158 IX86_BUILTIN_ADDSD_ROUND,
28159 IX86_BUILTIN_ADDSS_ROUND,
28160 IX86_BUILTIN_ALIGND512,
28161 IX86_BUILTIN_ALIGNQ512,
28162 IX86_BUILTIN_BLENDMD512,
28163 IX86_BUILTIN_BLENDMPD512,
28164 IX86_BUILTIN_BLENDMPS512,
28165 IX86_BUILTIN_BLENDMQ512,
28166 IX86_BUILTIN_BROADCASTF32X4_512,
28167 IX86_BUILTIN_BROADCASTF64X4_512,
28168 IX86_BUILTIN_BROADCASTI32X4_512,
28169 IX86_BUILTIN_BROADCASTI64X4_512,
28170 IX86_BUILTIN_BROADCASTSD512,
28171 IX86_BUILTIN_BROADCASTSS512,
28172 IX86_BUILTIN_CMPD512,
28173 IX86_BUILTIN_CMPPD512,
28174 IX86_BUILTIN_CMPPS512,
28175 IX86_BUILTIN_CMPQ512,
28176 IX86_BUILTIN_CMPSD_MASK,
28177 IX86_BUILTIN_CMPSS_MASK,
28178 IX86_BUILTIN_COMIDF,
28179 IX86_BUILTIN_COMISF,
28180 IX86_BUILTIN_COMPRESSPD512,
28181 IX86_BUILTIN_COMPRESSPDSTORE512,
28182 IX86_BUILTIN_COMPRESSPS512,
28183 IX86_BUILTIN_COMPRESSPSSTORE512,
28184 IX86_BUILTIN_CVTDQ2PD512,
28185 IX86_BUILTIN_CVTDQ2PS512,
28186 IX86_BUILTIN_CVTPD2DQ512,
28187 IX86_BUILTIN_CVTPD2PS512,
28188 IX86_BUILTIN_CVTPD2UDQ512,
28189 IX86_BUILTIN_CVTPH2PS512,
28190 IX86_BUILTIN_CVTPS2DQ512,
28191 IX86_BUILTIN_CVTPS2PD512,
28192 IX86_BUILTIN_CVTPS2PH512,
28193 IX86_BUILTIN_CVTPS2UDQ512,
28194 IX86_BUILTIN_CVTSD2SS_ROUND,
28195 IX86_BUILTIN_CVTSI2SD64,
28196 IX86_BUILTIN_CVTSI2SS32,
28197 IX86_BUILTIN_CVTSI2SS64,
28198 IX86_BUILTIN_CVTSS2SD_ROUND,
28199 IX86_BUILTIN_CVTTPD2DQ512,
28200 IX86_BUILTIN_CVTTPD2UDQ512,
28201 IX86_BUILTIN_CVTTPS2DQ512,
28202 IX86_BUILTIN_CVTTPS2UDQ512,
28203 IX86_BUILTIN_CVTUDQ2PD512,
28204 IX86_BUILTIN_CVTUDQ2PS512,
28205 IX86_BUILTIN_CVTUSI2SD32,
28206 IX86_BUILTIN_CVTUSI2SD64,
28207 IX86_BUILTIN_CVTUSI2SS32,
28208 IX86_BUILTIN_CVTUSI2SS64,
28209 IX86_BUILTIN_DIVPD512,
28210 IX86_BUILTIN_DIVPS512,
28211 IX86_BUILTIN_DIVSD_ROUND,
28212 IX86_BUILTIN_DIVSS_ROUND,
28213 IX86_BUILTIN_EXPANDPD512,
28214 IX86_BUILTIN_EXPANDPD512Z,
28215 IX86_BUILTIN_EXPANDPDLOAD512,
28216 IX86_BUILTIN_EXPANDPDLOAD512Z,
28217 IX86_BUILTIN_EXPANDPS512,
28218 IX86_BUILTIN_EXPANDPS512Z,
28219 IX86_BUILTIN_EXPANDPSLOAD512,
28220 IX86_BUILTIN_EXPANDPSLOAD512Z,
28221 IX86_BUILTIN_EXTRACTF32X4,
28222 IX86_BUILTIN_EXTRACTF64X4,
28223 IX86_BUILTIN_EXTRACTI32X4,
28224 IX86_BUILTIN_EXTRACTI64X4,
28225 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28226 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28227 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28228 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28229 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28230 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28231 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28232 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28233 IX86_BUILTIN_GETEXPPD512,
28234 IX86_BUILTIN_GETEXPPS512,
28235 IX86_BUILTIN_GETEXPSD128,
28236 IX86_BUILTIN_GETEXPSS128,
28237 IX86_BUILTIN_GETMANTPD512,
28238 IX86_BUILTIN_GETMANTPS512,
28239 IX86_BUILTIN_GETMANTSD128,
28240 IX86_BUILTIN_GETMANTSS128,
28241 IX86_BUILTIN_INSERTF32X4,
28242 IX86_BUILTIN_INSERTF64X4,
28243 IX86_BUILTIN_INSERTI32X4,
28244 IX86_BUILTIN_INSERTI64X4,
28245 IX86_BUILTIN_LOADAPD512,
28246 IX86_BUILTIN_LOADAPS512,
28247 IX86_BUILTIN_LOADDQUDI512,
28248 IX86_BUILTIN_LOADDQUSI512,
28249 IX86_BUILTIN_LOADUPD512,
28250 IX86_BUILTIN_LOADUPS512,
28251 IX86_BUILTIN_MAXPD512,
28252 IX86_BUILTIN_MAXPS512,
28253 IX86_BUILTIN_MAXSD_ROUND,
28254 IX86_BUILTIN_MAXSS_ROUND,
28255 IX86_BUILTIN_MINPD512,
28256 IX86_BUILTIN_MINPS512,
28257 IX86_BUILTIN_MINSD_ROUND,
28258 IX86_BUILTIN_MINSS_ROUND,
28259 IX86_BUILTIN_MOVAPD512,
28260 IX86_BUILTIN_MOVAPS512,
28261 IX86_BUILTIN_MOVDDUP512,
28262 IX86_BUILTIN_MOVDQA32LOAD512,
28263 IX86_BUILTIN_MOVDQA32STORE512,
28264 IX86_BUILTIN_MOVDQA32_512,
28265 IX86_BUILTIN_MOVDQA64LOAD512,
28266 IX86_BUILTIN_MOVDQA64STORE512,
28267 IX86_BUILTIN_MOVDQA64_512,
28268 IX86_BUILTIN_MOVNTDQ512,
28269 IX86_BUILTIN_MOVNTDQA512,
28270 IX86_BUILTIN_MOVNTPD512,
28271 IX86_BUILTIN_MOVNTPS512,
28272 IX86_BUILTIN_MOVSHDUP512,
28273 IX86_BUILTIN_MOVSLDUP512,
28274 IX86_BUILTIN_MULPD512,
28275 IX86_BUILTIN_MULPS512,
28276 IX86_BUILTIN_MULSD_ROUND,
28277 IX86_BUILTIN_MULSS_ROUND,
28278 IX86_BUILTIN_PABSD512,
28279 IX86_BUILTIN_PABSQ512,
28280 IX86_BUILTIN_PADDD512,
28281 IX86_BUILTIN_PADDQ512,
28282 IX86_BUILTIN_PANDD512,
28283 IX86_BUILTIN_PANDND512,
28284 IX86_BUILTIN_PANDNQ512,
28285 IX86_BUILTIN_PANDQ512,
28286 IX86_BUILTIN_PBROADCASTD512,
28287 IX86_BUILTIN_PBROADCASTD512_GPR,
28288 IX86_BUILTIN_PBROADCASTMB512,
28289 IX86_BUILTIN_PBROADCASTMW512,
28290 IX86_BUILTIN_PBROADCASTQ512,
28291 IX86_BUILTIN_PBROADCASTQ512_GPR,
28292 IX86_BUILTIN_PBROADCASTQ512_MEM,
28293 IX86_BUILTIN_PCMPEQD512_MASK,
28294 IX86_BUILTIN_PCMPEQQ512_MASK,
28295 IX86_BUILTIN_PCMPGTD512_MASK,
28296 IX86_BUILTIN_PCMPGTQ512_MASK,
28297 IX86_BUILTIN_PCOMPRESSD512,
28298 IX86_BUILTIN_PCOMPRESSDSTORE512,
28299 IX86_BUILTIN_PCOMPRESSQ512,
28300 IX86_BUILTIN_PCOMPRESSQSTORE512,
28301 IX86_BUILTIN_PEXPANDD512,
28302 IX86_BUILTIN_PEXPANDD512Z,
28303 IX86_BUILTIN_PEXPANDDLOAD512,
28304 IX86_BUILTIN_PEXPANDDLOAD512Z,
28305 IX86_BUILTIN_PEXPANDQ512,
28306 IX86_BUILTIN_PEXPANDQ512Z,
28307 IX86_BUILTIN_PEXPANDQLOAD512,
28308 IX86_BUILTIN_PEXPANDQLOAD512Z,
28309 IX86_BUILTIN_PMAXSD512,
28310 IX86_BUILTIN_PMAXSQ512,
28311 IX86_BUILTIN_PMAXUD512,
28312 IX86_BUILTIN_PMAXUQ512,
28313 IX86_BUILTIN_PMINSD512,
28314 IX86_BUILTIN_PMINSQ512,
28315 IX86_BUILTIN_PMINUD512,
28316 IX86_BUILTIN_PMINUQ512,
28317 IX86_BUILTIN_PMOVDB512,
28318 IX86_BUILTIN_PMOVDB512_MEM,
28319 IX86_BUILTIN_PMOVDW512,
28320 IX86_BUILTIN_PMOVDW512_MEM,
28321 IX86_BUILTIN_PMOVQB512,
28322 IX86_BUILTIN_PMOVQB512_MEM,
28323 IX86_BUILTIN_PMOVQD512,
28324 IX86_BUILTIN_PMOVQD512_MEM,
28325 IX86_BUILTIN_PMOVQW512,
28326 IX86_BUILTIN_PMOVQW512_MEM,
28327 IX86_BUILTIN_PMOVSDB512,
28328 IX86_BUILTIN_PMOVSDB512_MEM,
28329 IX86_BUILTIN_PMOVSDW512,
28330 IX86_BUILTIN_PMOVSDW512_MEM,
28331 IX86_BUILTIN_PMOVSQB512,
28332 IX86_BUILTIN_PMOVSQB512_MEM,
28333 IX86_BUILTIN_PMOVSQD512,
28334 IX86_BUILTIN_PMOVSQD512_MEM,
28335 IX86_BUILTIN_PMOVSQW512,
28336 IX86_BUILTIN_PMOVSQW512_MEM,
28337 IX86_BUILTIN_PMOVSXBD512,
28338 IX86_BUILTIN_PMOVSXBQ512,
28339 IX86_BUILTIN_PMOVSXDQ512,
28340 IX86_BUILTIN_PMOVSXWD512,
28341 IX86_BUILTIN_PMOVSXWQ512,
28342 IX86_BUILTIN_PMOVUSDB512,
28343 IX86_BUILTIN_PMOVUSDB512_MEM,
28344 IX86_BUILTIN_PMOVUSDW512,
28345 IX86_BUILTIN_PMOVUSDW512_MEM,
28346 IX86_BUILTIN_PMOVUSQB512,
28347 IX86_BUILTIN_PMOVUSQB512_MEM,
28348 IX86_BUILTIN_PMOVUSQD512,
28349 IX86_BUILTIN_PMOVUSQD512_MEM,
28350 IX86_BUILTIN_PMOVUSQW512,
28351 IX86_BUILTIN_PMOVUSQW512_MEM,
28352 IX86_BUILTIN_PMOVZXBD512,
28353 IX86_BUILTIN_PMOVZXBQ512,
28354 IX86_BUILTIN_PMOVZXDQ512,
28355 IX86_BUILTIN_PMOVZXWD512,
28356 IX86_BUILTIN_PMOVZXWQ512,
28357 IX86_BUILTIN_PMULDQ512,
28358 IX86_BUILTIN_PMULLD512,
28359 IX86_BUILTIN_PMULUDQ512,
28360 IX86_BUILTIN_PORD512,
28361 IX86_BUILTIN_PORQ512,
28362 IX86_BUILTIN_PROLD512,
28363 IX86_BUILTIN_PROLQ512,
28364 IX86_BUILTIN_PROLVD512,
28365 IX86_BUILTIN_PROLVQ512,
28366 IX86_BUILTIN_PRORD512,
28367 IX86_BUILTIN_PRORQ512,
28368 IX86_BUILTIN_PRORVD512,
28369 IX86_BUILTIN_PRORVQ512,
28370 IX86_BUILTIN_PSHUFD512,
28371 IX86_BUILTIN_PSLLD512,
28372 IX86_BUILTIN_PSLLDI512,
28373 IX86_BUILTIN_PSLLQ512,
28374 IX86_BUILTIN_PSLLQI512,
28375 IX86_BUILTIN_PSLLVV16SI,
28376 IX86_BUILTIN_PSLLVV8DI,
28377 IX86_BUILTIN_PSRAD512,
28378 IX86_BUILTIN_PSRADI512,
28379 IX86_BUILTIN_PSRAQ512,
28380 IX86_BUILTIN_PSRAQI512,
28381 IX86_BUILTIN_PSRAVV16SI,
28382 IX86_BUILTIN_PSRAVV8DI,
28383 IX86_BUILTIN_PSRLD512,
28384 IX86_BUILTIN_PSRLDI512,
28385 IX86_BUILTIN_PSRLQ512,
28386 IX86_BUILTIN_PSRLQI512,
28387 IX86_BUILTIN_PSRLVV16SI,
28388 IX86_BUILTIN_PSRLVV8DI,
28389 IX86_BUILTIN_PSUBD512,
28390 IX86_BUILTIN_PSUBQ512,
28391 IX86_BUILTIN_PTESTMD512,
28392 IX86_BUILTIN_PTESTMQ512,
28393 IX86_BUILTIN_PTESTNMD512,
28394 IX86_BUILTIN_PTESTNMQ512,
28395 IX86_BUILTIN_PUNPCKHDQ512,
28396 IX86_BUILTIN_PUNPCKHQDQ512,
28397 IX86_BUILTIN_PUNPCKLDQ512,
28398 IX86_BUILTIN_PUNPCKLQDQ512,
28399 IX86_BUILTIN_PXORD512,
28400 IX86_BUILTIN_PXORQ512,
28401 IX86_BUILTIN_RCP14PD512,
28402 IX86_BUILTIN_RCP14PS512,
28403 IX86_BUILTIN_RCP14SD,
28404 IX86_BUILTIN_RCP14SS,
28405 IX86_BUILTIN_RNDSCALEPD,
28406 IX86_BUILTIN_RNDSCALEPS,
28407 IX86_BUILTIN_RNDSCALESD,
28408 IX86_BUILTIN_RNDSCALESS,
28409 IX86_BUILTIN_RSQRT14PD512,
28410 IX86_BUILTIN_RSQRT14PS512,
28411 IX86_BUILTIN_RSQRT14SD,
28412 IX86_BUILTIN_RSQRT14SS,
28413 IX86_BUILTIN_SCALEFPD512,
28414 IX86_BUILTIN_SCALEFPS512,
28415 IX86_BUILTIN_SCALEFSD,
28416 IX86_BUILTIN_SCALEFSS,
28417 IX86_BUILTIN_SHUFPD512,
28418 IX86_BUILTIN_SHUFPS512,
28419 IX86_BUILTIN_SHUF_F32x4,
28420 IX86_BUILTIN_SHUF_F64x2,
28421 IX86_BUILTIN_SHUF_I32x4,
28422 IX86_BUILTIN_SHUF_I64x2,
28423 IX86_BUILTIN_SQRTPD512,
28424 IX86_BUILTIN_SQRTPD512_MASK,
28425 IX86_BUILTIN_SQRTPS512_MASK,
28426 IX86_BUILTIN_SQRTPS_NR512,
28427 IX86_BUILTIN_SQRTSD_ROUND,
28428 IX86_BUILTIN_SQRTSS_ROUND,
28429 IX86_BUILTIN_STOREAPD512,
28430 IX86_BUILTIN_STOREAPS512,
28431 IX86_BUILTIN_STOREDQUDI512,
28432 IX86_BUILTIN_STOREDQUSI512,
28433 IX86_BUILTIN_STOREUPD512,
28434 IX86_BUILTIN_STOREUPS512,
28435 IX86_BUILTIN_SUBPD512,
28436 IX86_BUILTIN_SUBPS512,
28437 IX86_BUILTIN_SUBSD_ROUND,
28438 IX86_BUILTIN_SUBSS_ROUND,
28439 IX86_BUILTIN_UCMPD512,
28440 IX86_BUILTIN_UCMPQ512,
28441 IX86_BUILTIN_UNPCKHPD512,
28442 IX86_BUILTIN_UNPCKHPS512,
28443 IX86_BUILTIN_UNPCKLPD512,
28444 IX86_BUILTIN_UNPCKLPS512,
28445 IX86_BUILTIN_VCVTSD2SI32,
28446 IX86_BUILTIN_VCVTSD2SI64,
28447 IX86_BUILTIN_VCVTSD2USI32,
28448 IX86_BUILTIN_VCVTSD2USI64,
28449 IX86_BUILTIN_VCVTSS2SI32,
28450 IX86_BUILTIN_VCVTSS2SI64,
28451 IX86_BUILTIN_VCVTSS2USI32,
28452 IX86_BUILTIN_VCVTSS2USI64,
28453 IX86_BUILTIN_VCVTTSD2SI32,
28454 IX86_BUILTIN_VCVTTSD2SI64,
28455 IX86_BUILTIN_VCVTTSD2USI32,
28456 IX86_BUILTIN_VCVTTSD2USI64,
28457 IX86_BUILTIN_VCVTTSS2SI32,
28458 IX86_BUILTIN_VCVTTSS2SI64,
28459 IX86_BUILTIN_VCVTTSS2USI32,
28460 IX86_BUILTIN_VCVTTSS2USI64,
28461 IX86_BUILTIN_VFMADDPD512_MASK,
28462 IX86_BUILTIN_VFMADDPD512_MASK3,
28463 IX86_BUILTIN_VFMADDPD512_MASKZ,
28464 IX86_BUILTIN_VFMADDPS512_MASK,
28465 IX86_BUILTIN_VFMADDPS512_MASK3,
28466 IX86_BUILTIN_VFMADDPS512_MASKZ,
28467 IX86_BUILTIN_VFMADDSD3_ROUND,
28468 IX86_BUILTIN_VFMADDSS3_ROUND,
28469 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28470 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28471 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28472 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28473 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28474 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28475 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28476 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28477 IX86_BUILTIN_VFMSUBPD512_MASK3,
28478 IX86_BUILTIN_VFMSUBPS512_MASK3,
28479 IX86_BUILTIN_VFMSUBSD3_MASK3,
28480 IX86_BUILTIN_VFMSUBSS3_MASK3,
28481 IX86_BUILTIN_VFNMADDPD512_MASK,
28482 IX86_BUILTIN_VFNMADDPS512_MASK,
28483 IX86_BUILTIN_VFNMSUBPD512_MASK,
28484 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28485 IX86_BUILTIN_VFNMSUBPS512_MASK,
28486 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28487 IX86_BUILTIN_VPCLZCNTD512,
28488 IX86_BUILTIN_VPCLZCNTQ512,
28489 IX86_BUILTIN_VPCONFLICTD512,
28490 IX86_BUILTIN_VPCONFLICTQ512,
28491 IX86_BUILTIN_VPERMDF512,
28492 IX86_BUILTIN_VPERMDI512,
28493 IX86_BUILTIN_VPERMI2VARD512,
28494 IX86_BUILTIN_VPERMI2VARPD512,
28495 IX86_BUILTIN_VPERMI2VARPS512,
28496 IX86_BUILTIN_VPERMI2VARQ512,
28497 IX86_BUILTIN_VPERMILPD512,
28498 IX86_BUILTIN_VPERMILPS512,
28499 IX86_BUILTIN_VPERMILVARPD512,
28500 IX86_BUILTIN_VPERMILVARPS512,
28501 IX86_BUILTIN_VPERMT2VARD512,
28502 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28503 IX86_BUILTIN_VPERMT2VARPD512,
28504 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28505 IX86_BUILTIN_VPERMT2VARPS512,
28506 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28507 IX86_BUILTIN_VPERMT2VARQ512,
28508 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28509 IX86_BUILTIN_VPERMVARDF512,
28510 IX86_BUILTIN_VPERMVARDI512,
28511 IX86_BUILTIN_VPERMVARSF512,
28512 IX86_BUILTIN_VPERMVARSI512,
28513 IX86_BUILTIN_VTERNLOGD512_MASK,
28514 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28515 IX86_BUILTIN_VTERNLOGQ512_MASK,
28516 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28518 /* Mask arithmetic operations */
28519 IX86_BUILTIN_KAND16,
28520 IX86_BUILTIN_KANDN16,
28521 IX86_BUILTIN_KNOT16,
28522 IX86_BUILTIN_KOR16,
28523 IX86_BUILTIN_KORTESTC16,
28524 IX86_BUILTIN_KORTESTZ16,
28525 IX86_BUILTIN_KUNPCKBW,
28526 IX86_BUILTIN_KXNOR16,
28527 IX86_BUILTIN_KXOR16,
28528 IX86_BUILTIN_KMOV16,
28530 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28531 where all operands are 32-byte or 64-byte wide respectively. */
28532 IX86_BUILTIN_GATHERALTSIV4DF,
28533 IX86_BUILTIN_GATHERALTDIV8SF,
28534 IX86_BUILTIN_GATHERALTSIV4DI,
28535 IX86_BUILTIN_GATHERALTDIV8SI,
28536 IX86_BUILTIN_GATHER3ALTDIV16SF,
28537 IX86_BUILTIN_GATHER3ALTDIV16SI,
28538 IX86_BUILTIN_GATHER3ALTSIV8DF,
28539 IX86_BUILTIN_GATHER3ALTSIV8DI,
28540 IX86_BUILTIN_GATHER3DIV16SF,
28541 IX86_BUILTIN_GATHER3DIV16SI,
28542 IX86_BUILTIN_GATHER3DIV8DF,
28543 IX86_BUILTIN_GATHER3DIV8DI,
28544 IX86_BUILTIN_GATHER3SIV16SF,
28545 IX86_BUILTIN_GATHER3SIV16SI,
28546 IX86_BUILTIN_GATHER3SIV8DF,
28547 IX86_BUILTIN_GATHER3SIV8DI,
28548 IX86_BUILTIN_SCATTERDIV16SF,
28549 IX86_BUILTIN_SCATTERDIV16SI,
28550 IX86_BUILTIN_SCATTERDIV8DF,
28551 IX86_BUILTIN_SCATTERDIV8DI,
28552 IX86_BUILTIN_SCATTERSIV16SF,
28553 IX86_BUILTIN_SCATTERSIV16SI,
28554 IX86_BUILTIN_SCATTERSIV8DF,
28555 IX86_BUILTIN_SCATTERSIV8DI,
28557 /* AVX512PF */
28558 IX86_BUILTIN_GATHERPFQPD,
28559 IX86_BUILTIN_GATHERPFDPS,
28560 IX86_BUILTIN_GATHERPFDPD,
28561 IX86_BUILTIN_GATHERPFQPS,
28562 IX86_BUILTIN_SCATTERPFDPD,
28563 IX86_BUILTIN_SCATTERPFDPS,
28564 IX86_BUILTIN_SCATTERPFQPD,
28565 IX86_BUILTIN_SCATTERPFQPS,
28567 /* AVX-512ER */
28568 IX86_BUILTIN_EXP2PD_MASK,
28569 IX86_BUILTIN_EXP2PS_MASK,
28570 IX86_BUILTIN_EXP2PS,
28571 IX86_BUILTIN_RCP28PD,
28572 IX86_BUILTIN_RCP28PS,
28573 IX86_BUILTIN_RCP28SD,
28574 IX86_BUILTIN_RCP28SS,
28575 IX86_BUILTIN_RSQRT28PD,
28576 IX86_BUILTIN_RSQRT28PS,
28577 IX86_BUILTIN_RSQRT28SD,
28578 IX86_BUILTIN_RSQRT28SS,
28580 /* SHA builtins. */
28581 IX86_BUILTIN_SHA1MSG1,
28582 IX86_BUILTIN_SHA1MSG2,
28583 IX86_BUILTIN_SHA1NEXTE,
28584 IX86_BUILTIN_SHA1RNDS4,
28585 IX86_BUILTIN_SHA256MSG1,
28586 IX86_BUILTIN_SHA256MSG2,
28587 IX86_BUILTIN_SHA256RNDS2,
28589 /* CLFLUSHOPT instructions. */
28590 IX86_BUILTIN_CLFLUSHOPT,
28592 /* TFmode support builtins. */
28593 IX86_BUILTIN_INFQ,
28594 IX86_BUILTIN_HUGE_VALQ,
28595 IX86_BUILTIN_FABSQ,
28596 IX86_BUILTIN_COPYSIGNQ,
28598 /* Vectorizer support builtins. */
28599 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28600 IX86_BUILTIN_CPYSGNPS,
28601 IX86_BUILTIN_CPYSGNPD,
28602 IX86_BUILTIN_CPYSGNPS256,
28603 IX86_BUILTIN_CPYSGNPS512,
28604 IX86_BUILTIN_CPYSGNPD256,
28605 IX86_BUILTIN_CPYSGNPD512,
28606 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28607 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28610 /* FMA4 instructions. */
28611 IX86_BUILTIN_VFMADDSS,
28612 IX86_BUILTIN_VFMADDSD,
28613 IX86_BUILTIN_VFMADDPS,
28614 IX86_BUILTIN_VFMADDPD,
28615 IX86_BUILTIN_VFMADDPS256,
28616 IX86_BUILTIN_VFMADDPD256,
28617 IX86_BUILTIN_VFMADDSUBPS,
28618 IX86_BUILTIN_VFMADDSUBPD,
28619 IX86_BUILTIN_VFMADDSUBPS256,
28620 IX86_BUILTIN_VFMADDSUBPD256,
28622 /* FMA3 instructions. */
28623 IX86_BUILTIN_VFMADDSS3,
28624 IX86_BUILTIN_VFMADDSD3,
28626 /* XOP instructions. */
28627 IX86_BUILTIN_VPCMOV,
28628 IX86_BUILTIN_VPCMOV_V2DI,
28629 IX86_BUILTIN_VPCMOV_V4SI,
28630 IX86_BUILTIN_VPCMOV_V8HI,
28631 IX86_BUILTIN_VPCMOV_V16QI,
28632 IX86_BUILTIN_VPCMOV_V4SF,
28633 IX86_BUILTIN_VPCMOV_V2DF,
28634 IX86_BUILTIN_VPCMOV256,
28635 IX86_BUILTIN_VPCMOV_V4DI256,
28636 IX86_BUILTIN_VPCMOV_V8SI256,
28637 IX86_BUILTIN_VPCMOV_V16HI256,
28638 IX86_BUILTIN_VPCMOV_V32QI256,
28639 IX86_BUILTIN_VPCMOV_V8SF256,
28640 IX86_BUILTIN_VPCMOV_V4DF256,
28642 IX86_BUILTIN_VPPERM,
28644 IX86_BUILTIN_VPMACSSWW,
28645 IX86_BUILTIN_VPMACSWW,
28646 IX86_BUILTIN_VPMACSSWD,
28647 IX86_BUILTIN_VPMACSWD,
28648 IX86_BUILTIN_VPMACSSDD,
28649 IX86_BUILTIN_VPMACSDD,
28650 IX86_BUILTIN_VPMACSSDQL,
28651 IX86_BUILTIN_VPMACSSDQH,
28652 IX86_BUILTIN_VPMACSDQL,
28653 IX86_BUILTIN_VPMACSDQH,
28654 IX86_BUILTIN_VPMADCSSWD,
28655 IX86_BUILTIN_VPMADCSWD,
28657 IX86_BUILTIN_VPHADDBW,
28658 IX86_BUILTIN_VPHADDBD,
28659 IX86_BUILTIN_VPHADDBQ,
28660 IX86_BUILTIN_VPHADDWD,
28661 IX86_BUILTIN_VPHADDWQ,
28662 IX86_BUILTIN_VPHADDDQ,
28663 IX86_BUILTIN_VPHADDUBW,
28664 IX86_BUILTIN_VPHADDUBD,
28665 IX86_BUILTIN_VPHADDUBQ,
28666 IX86_BUILTIN_VPHADDUWD,
28667 IX86_BUILTIN_VPHADDUWQ,
28668 IX86_BUILTIN_VPHADDUDQ,
28669 IX86_BUILTIN_VPHSUBBW,
28670 IX86_BUILTIN_VPHSUBWD,
28671 IX86_BUILTIN_VPHSUBDQ,
28673 IX86_BUILTIN_VPROTB,
28674 IX86_BUILTIN_VPROTW,
28675 IX86_BUILTIN_VPROTD,
28676 IX86_BUILTIN_VPROTQ,
28677 IX86_BUILTIN_VPROTB_IMM,
28678 IX86_BUILTIN_VPROTW_IMM,
28679 IX86_BUILTIN_VPROTD_IMM,
28680 IX86_BUILTIN_VPROTQ_IMM,
28682 IX86_BUILTIN_VPSHLB,
28683 IX86_BUILTIN_VPSHLW,
28684 IX86_BUILTIN_VPSHLD,
28685 IX86_BUILTIN_VPSHLQ,
28686 IX86_BUILTIN_VPSHAB,
28687 IX86_BUILTIN_VPSHAW,
28688 IX86_BUILTIN_VPSHAD,
28689 IX86_BUILTIN_VPSHAQ,
28691 IX86_BUILTIN_VFRCZSS,
28692 IX86_BUILTIN_VFRCZSD,
28693 IX86_BUILTIN_VFRCZPS,
28694 IX86_BUILTIN_VFRCZPD,
28695 IX86_BUILTIN_VFRCZPS256,
28696 IX86_BUILTIN_VFRCZPD256,
28698 IX86_BUILTIN_VPCOMEQUB,
28699 IX86_BUILTIN_VPCOMNEUB,
28700 IX86_BUILTIN_VPCOMLTUB,
28701 IX86_BUILTIN_VPCOMLEUB,
28702 IX86_BUILTIN_VPCOMGTUB,
28703 IX86_BUILTIN_VPCOMGEUB,
28704 IX86_BUILTIN_VPCOMFALSEUB,
28705 IX86_BUILTIN_VPCOMTRUEUB,
28707 IX86_BUILTIN_VPCOMEQUW,
28708 IX86_BUILTIN_VPCOMNEUW,
28709 IX86_BUILTIN_VPCOMLTUW,
28710 IX86_BUILTIN_VPCOMLEUW,
28711 IX86_BUILTIN_VPCOMGTUW,
28712 IX86_BUILTIN_VPCOMGEUW,
28713 IX86_BUILTIN_VPCOMFALSEUW,
28714 IX86_BUILTIN_VPCOMTRUEUW,
28716 IX86_BUILTIN_VPCOMEQUD,
28717 IX86_BUILTIN_VPCOMNEUD,
28718 IX86_BUILTIN_VPCOMLTUD,
28719 IX86_BUILTIN_VPCOMLEUD,
28720 IX86_BUILTIN_VPCOMGTUD,
28721 IX86_BUILTIN_VPCOMGEUD,
28722 IX86_BUILTIN_VPCOMFALSEUD,
28723 IX86_BUILTIN_VPCOMTRUEUD,
28725 IX86_BUILTIN_VPCOMEQUQ,
28726 IX86_BUILTIN_VPCOMNEUQ,
28727 IX86_BUILTIN_VPCOMLTUQ,
28728 IX86_BUILTIN_VPCOMLEUQ,
28729 IX86_BUILTIN_VPCOMGTUQ,
28730 IX86_BUILTIN_VPCOMGEUQ,
28731 IX86_BUILTIN_VPCOMFALSEUQ,
28732 IX86_BUILTIN_VPCOMTRUEUQ,
28734 IX86_BUILTIN_VPCOMEQB,
28735 IX86_BUILTIN_VPCOMNEB,
28736 IX86_BUILTIN_VPCOMLTB,
28737 IX86_BUILTIN_VPCOMLEB,
28738 IX86_BUILTIN_VPCOMGTB,
28739 IX86_BUILTIN_VPCOMGEB,
28740 IX86_BUILTIN_VPCOMFALSEB,
28741 IX86_BUILTIN_VPCOMTRUEB,
28743 IX86_BUILTIN_VPCOMEQW,
28744 IX86_BUILTIN_VPCOMNEW,
28745 IX86_BUILTIN_VPCOMLTW,
28746 IX86_BUILTIN_VPCOMLEW,
28747 IX86_BUILTIN_VPCOMGTW,
28748 IX86_BUILTIN_VPCOMGEW,
28749 IX86_BUILTIN_VPCOMFALSEW,
28750 IX86_BUILTIN_VPCOMTRUEW,
28752 IX86_BUILTIN_VPCOMEQD,
28753 IX86_BUILTIN_VPCOMNED,
28754 IX86_BUILTIN_VPCOMLTD,
28755 IX86_BUILTIN_VPCOMLED,
28756 IX86_BUILTIN_VPCOMGTD,
28757 IX86_BUILTIN_VPCOMGED,
28758 IX86_BUILTIN_VPCOMFALSED,
28759 IX86_BUILTIN_VPCOMTRUED,
28761 IX86_BUILTIN_VPCOMEQQ,
28762 IX86_BUILTIN_VPCOMNEQ,
28763 IX86_BUILTIN_VPCOMLTQ,
28764 IX86_BUILTIN_VPCOMLEQ,
28765 IX86_BUILTIN_VPCOMGTQ,
28766 IX86_BUILTIN_VPCOMGEQ,
28767 IX86_BUILTIN_VPCOMFALSEQ,
28768 IX86_BUILTIN_VPCOMTRUEQ,
28770 /* LWP instructions. */
28771 IX86_BUILTIN_LLWPCB,
28772 IX86_BUILTIN_SLWPCB,
28773 IX86_BUILTIN_LWPVAL32,
28774 IX86_BUILTIN_LWPVAL64,
28775 IX86_BUILTIN_LWPINS32,
28776 IX86_BUILTIN_LWPINS64,
28778 IX86_BUILTIN_CLZS,
28780 /* RTM */
28781 IX86_BUILTIN_XBEGIN,
28782 IX86_BUILTIN_XEND,
28783 IX86_BUILTIN_XABORT,
28784 IX86_BUILTIN_XTEST,
28786 /* BMI instructions. */
28787 IX86_BUILTIN_BEXTR32,
28788 IX86_BUILTIN_BEXTR64,
28789 IX86_BUILTIN_CTZS,
28791 /* TBM instructions. */
28792 IX86_BUILTIN_BEXTRI32,
28793 IX86_BUILTIN_BEXTRI64,
28795 /* BMI2 instructions. */
28796 IX86_BUILTIN_BZHI32,
28797 IX86_BUILTIN_BZHI64,
28798 IX86_BUILTIN_PDEP32,
28799 IX86_BUILTIN_PDEP64,
28800 IX86_BUILTIN_PEXT32,
28801 IX86_BUILTIN_PEXT64,
28803 /* ADX instructions. */
28804 IX86_BUILTIN_ADDCARRYX32,
28805 IX86_BUILTIN_ADDCARRYX64,
28807 /* FSGSBASE instructions. */
28808 IX86_BUILTIN_RDFSBASE32,
28809 IX86_BUILTIN_RDFSBASE64,
28810 IX86_BUILTIN_RDGSBASE32,
28811 IX86_BUILTIN_RDGSBASE64,
28812 IX86_BUILTIN_WRFSBASE32,
28813 IX86_BUILTIN_WRFSBASE64,
28814 IX86_BUILTIN_WRGSBASE32,
28815 IX86_BUILTIN_WRGSBASE64,
28817 /* RDRND instructions. */
28818 IX86_BUILTIN_RDRAND16_STEP,
28819 IX86_BUILTIN_RDRAND32_STEP,
28820 IX86_BUILTIN_RDRAND64_STEP,
28822 /* RDSEED instructions. */
28823 IX86_BUILTIN_RDSEED16_STEP,
28824 IX86_BUILTIN_RDSEED32_STEP,
28825 IX86_BUILTIN_RDSEED64_STEP,
28827 /* F16C instructions. */
28828 IX86_BUILTIN_CVTPH2PS,
28829 IX86_BUILTIN_CVTPH2PS256,
28830 IX86_BUILTIN_CVTPS2PH,
28831 IX86_BUILTIN_CVTPS2PH256,
28833 /* CFString built-in for darwin */
28834 IX86_BUILTIN_CFSTRING,
28836 /* Builtins to get CPU type and supported features. */
28837 IX86_BUILTIN_CPU_INIT,
28838 IX86_BUILTIN_CPU_IS,
28839 IX86_BUILTIN_CPU_SUPPORTS,
28841 /* Read/write FLAGS register built-ins. */
28842 IX86_BUILTIN_READ_FLAGS,
28843 IX86_BUILTIN_WRITE_FLAGS,
28845 IX86_BUILTIN_MAX
28846 };
28848 /* Table for the ix86 builtin decls. */
28851 /* Table of all of the builtin functions that are possible with different ISA's
28852 but are waiting to be built until a function is declared to use that
28853 ISA. */
28860 };
28865 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28866 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28867 function decl in the ix86_builtins array. Returns the function decl or
28868 NULL_TREE, if the builtin was not added.
28870 If the front end has a special hook for builtin functions, delay adding
28871 builtin functions that aren't in the current ISA until the ISA is changed
28872 with function specific optimization. Doing so, can save about 300K for the
28873 default compiler. When the builtin is expanded, check at that time whether
28874 it is valid.
28876 If the front end doesn't have a special hook, record all builtins, even if
28877 it isn't an instruction set in the current ISA in case the user uses
28878 function specific options for a different ISA, so that we don't get scope
28879 errors if a builtin is added in the middle of a function scope. */
28885 {
28889 {
28898 {
28904 }
28905 else
28906 {
28912 }
28913 }
28916 }
28918 /* Like def_builtin, but also marks the function decl "const". */
28923 {
28927 else
28931 }
28933 /* Add any new builtin functions for a given ISA that may not have been
28934 declared. This saves a bit of space compared to adding all of the
28935 declarations to the tree, even if we didn't use them. */
28937 static void
28939 {
28943 {
28946 {
28949 /* Don't define the builtin again. */
28955 NULL_TREE);
28960 }
28961 }
28962 }
28964 /* Bits for builtin_description.flag. */
28966 /* Set when we don't support the comparison natively, and should
28967 swap_comparison in order to support it. */
28968 #define BUILTIN_DESC_SWAP_OPERANDS 1
28970 struct builtin_description
28971 {
28978 };
28981 {
28982 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28984 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28985 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28986 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28987 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28988 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28989 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28990 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28992 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28993 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28994 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28995 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28997 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28999 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
29000 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
29001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
29002 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
29003 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
29004 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
29005 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
29006 };
29009 {
29010 /* SSE4.2 */
29011 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
29012 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
29013 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
29014 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
29015 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
29016 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
29017 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
29018 };
29021 {
29022 /* SSE4.2 */
29023 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
29024 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
29025 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
29026 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
29027 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
29028 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
29029 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
29030 };
29032 /* Special builtins with variable number of arguments. */
29034 {
29035 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
29036 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
29037 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
29039 /* 80387 (for use internally for atomic compound assignment). */
29040 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
29041 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
29042 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
29043 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
29045 /* MMX */
29046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29048 /* 3DNow! */
29049 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29051 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
29052 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
29053 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
29054 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29055 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29056 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29057 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29058 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29059 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29061 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29062 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29063 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29064 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29065 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29066 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29067 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29068 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29070 /* SSE */
29071 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29072 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29075 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29076 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29077 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29078 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29080 /* SSE or 3DNow!A */
29081 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29082 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
29084 /* SSE2 */
29085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
29089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
29091 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
29092 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
29093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
29094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29099 /* SSE3 */
29100 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29102 /* SSE4.1 */
29103 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
29105 /* SSE4A */
29106 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29107 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29109 /* AVX */
29110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
29111 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
29113 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29114 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29115 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29116 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29117 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29119 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29120 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29121 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29122 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29123 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29124 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29125 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29127 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29134 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29140 /* AVX2 */
29141 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29142 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29143 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29144 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29145 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29146 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29147 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29148 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29149 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29151 /* AVX512F */
29152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29200 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29201 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29202 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29203 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29204 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29205 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29207 /* FSGSBASE */
29208 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29209 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29210 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29211 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29212 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29213 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29214 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29215 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29217 /* RTM */
29218 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29219 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29220 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29221 };
29223 /* Builtins with variable number of arguments. */
29225 {
29226 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29227 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29228 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29229 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29230 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29231 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29232 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29234 /* MMX */
29235 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29240 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29242 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29243 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29244 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29246 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29247 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29248 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29249 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29251 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29252 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29254 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29255 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29256 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29257 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29259 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29260 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29261 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29262 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29263 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29264 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29266 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29267 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29268 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29269 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29270 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29273 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29274 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29275 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29277 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29279 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29282 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29284 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29286 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29287 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29289 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29294 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29295 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29298 /* 3DNow! */
29299 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29300 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29301 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29302 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29304 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29305 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29306 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29307 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29308 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29309 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29310 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29311 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29312 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29313 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29314 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29315 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29316 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29317 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29318 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29320 /* 3DNow!A */
29321 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29322 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29323 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29324 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29325 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29326 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29328 /* SSE */
29329 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29330 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29331 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29332 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29333 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29334 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29335 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29336 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29337 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29338 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29339 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29340 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29342 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29344 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29345 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29346 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29347 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29348 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29349 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29350 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29353 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29354 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29355 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29356 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29357 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29358 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29359 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29360 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29361 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29362 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29363 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29364 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29365 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29366 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29367 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29368 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29369 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29370 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29371 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29372 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29374 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29375 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29376 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29377 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29379 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29380 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29381 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29382 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29384 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29386 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29388 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29389 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29390 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29393 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29394 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29396 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29402 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29403 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29405 /* SSE MMX or 3Dnow!A */
29406 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29407 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29408 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29410 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29411 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29412 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29413 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29415 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29416 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29418 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29420 /* SSE2 */
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29424 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29427 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29438 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29439 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29440 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29444 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29448 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29449 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29477 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29481 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29483 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29484 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29486 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29489 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29490 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29492 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29494 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29495 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29496 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29497 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29498 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29499 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29500 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29501 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29512 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29513 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29515 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29517 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29518 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29525 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29526 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29530 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29531 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29532 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29535 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29536 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29537 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29538 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29539 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29540 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29541 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29542 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29548 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29552 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29557 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29561 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29562 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29563 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29564 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29565 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29566 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29567 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29569 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29570 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29571 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29572 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29573 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29574 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29575 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29577 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29578 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29579 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29580 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29586 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29588 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29590 /* SSE2 MMX */
29591 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29592 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29594 /* SSE3 */
29595 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29596 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29598 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29599 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29600 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29601 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29602 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29603 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29605 /* SSSE3 */
29606 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29607 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29608 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29609 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29610 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29611 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29613 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29614 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29615 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29616 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29617 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29618 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29619 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29620 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29621 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29622 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29623 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29624 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29625 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29626 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29627 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29628 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29629 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29630 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29631 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29632 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29633 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29634 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29635 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29636 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29638 /* SSSE3. */
29639 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29640 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29642 /* SSE4.1 */
29643 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29644 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29645 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29646 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29647 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29648 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29649 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29650 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29651 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29652 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29654 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29655 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29656 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29657 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29658 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29659 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29660 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29661 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29662 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29663 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29664 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29665 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29666 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29668 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29669 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29670 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29671 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29672 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29673 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29674 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29675 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29676 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29677 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29678 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29679 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29681 /* SSE4.1 */
29682 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29683 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29684 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29685 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29687 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29688 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29689 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29690 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29692 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29693 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29695 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29696 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29698 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29699 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29700 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29701 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29703 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29704 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29706 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29707 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29709 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29710 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29711 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29713 /* SSE4.2 */
29714 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29715 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29716 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29717 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29718 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29720 /* SSE4A */
29721 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29722 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29723 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29724 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29726 /* AES */
29727 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29728 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29730 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29731 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29732 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29733 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29735 /* PCLMUL */
29736 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29738 /* AVX */
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29744 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29747 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29753 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29754 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29755 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29756 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29757 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29758 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29759 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29760 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29761 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29762 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29763 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29764 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29768 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29787 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29788 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29792 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29794 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29810 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29812 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29814 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29826 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29827 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29840 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29841 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29851 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29852 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29853 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29860 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29865 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29874 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29875 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29877 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29879 /* AVX2 */
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29909 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29910 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29911 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29912 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29913 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29914 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29915 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29916 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29917 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29918 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29919 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29920 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29921 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29922 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29923 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29924 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29925 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29926 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29927 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29928 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29929 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29930 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29931 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29933 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29934 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29936 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29937 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29938 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29939 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29940 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29944 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29946 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29947 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29948 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29949 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29950 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29951 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29952 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29953 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29954 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29955 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29956 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29957 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29958 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29959 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29961 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29962 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29963 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29964 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29965 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29966 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29967 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29968 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29969 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29970 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29971 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29972 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29973 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29974 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29975 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29976 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29977 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29978 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29979 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29980 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29981 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29982 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29983 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29984 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29985 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29986 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29987 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29988 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29989 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29990 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29991 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29992 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29993 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29994 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29995 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29996 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29997 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29998 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29999 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30000 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
30001 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
30002 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
30003 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
30004 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
30005 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
30006 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
30007 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
30008 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
30009 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30010 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
30011 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
30012 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
30013 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
30014 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
30015 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
30016 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30017 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30018 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30019 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30020 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30021 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30022 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30023 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30024 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30025 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30027 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30029 /* BMI */
30030 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30031 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30032 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30034 /* TBM */
30035 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30036 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30038 /* F16C */
30039 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
30040 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
30041 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
30042 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
30044 /* BMI2 */
30045 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30046 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30047 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30048 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30049 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30050 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30052 /* AVX512F */
30053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
30054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
30055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
30057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
30058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
30090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
30091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
30108 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
30109 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
30111 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30112 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30220 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30221 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30222 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30223 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30255 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30260 /* Mask arithmetic operations */
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30272 /* SHA */
30273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30280 };
30282 /* Builtins with rounding support. */
30284 {
30285 /* AVX512F */
30286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30305 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30307 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30314 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30316 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30318 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30320 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30321 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30322 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30323 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30324 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30325 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30326 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30327 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30328 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30329 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30330 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30347 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30348 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30349 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30350 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30351 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30352 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30353 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30354 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30355 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30356 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30357 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30358 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30359 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30360 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30361 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30362 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30363 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30364 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30365 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30366 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30367 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30368 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30369 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30370 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30371 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30372 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30373 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30374 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30375 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30376 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30377 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30378 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30379 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30380 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30381 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30382 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30383 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30384 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30385 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30386 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30387 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30388 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30389 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30390 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30391 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30392 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30393 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30394 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30395 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30396 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30397 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30398 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30399 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30400 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30401 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30402 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30403 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30404 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30406 /* AVX512ER */
30407 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30408 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30409 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30410 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30411 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30412 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30413 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30414 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30415 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30416 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30417 };
30419 /* FMA4 and XOP. */
30420 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30421 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30422 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30423 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30424 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30425 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30426 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30427 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30428 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30429 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30430 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30431 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30432 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30433 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30434 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30435 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30436 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30437 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30438 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30439 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30440 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30441 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30442 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30443 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30444 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30445 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30446 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30447 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30448 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30449 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30450 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30451 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30452 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30453 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30454 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30455 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30456 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30457 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30458 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30459 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30460 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30461 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30462 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30463 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30464 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30465 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30466 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30467 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30468 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30469 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30470 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30471 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30474 {
30515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30621 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30629 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30630 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30636 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30637 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30638 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30639 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30642 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30644 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30645 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30646 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30651 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30652 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30654 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30656 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30657 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30659 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30660 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30661 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30662 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30663 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30664 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30665 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30666 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30668 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30669 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30670 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30671 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30673 };
30674 \f
30675 /* TM vector builtins. */
30677 /* Reuse the existing x86-specific `struct builtin_description' cause
30678 we're lazy. Add casts to make them fit. */
30680 {
30681 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30682 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30683 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30684 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30685 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30686 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30687 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30689 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30690 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30691 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30692 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30693 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30694 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30695 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30697 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30698 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30699 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30700 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30701 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30702 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30703 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30705 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30706 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30707 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30708 };
30710 /* TM callbacks. */
30712 /* Return the builtin decl needed to load a vector of TYPE. */
30714 static tree
30716 {
30718 {
30720 {
30727 }
30728 }
30730 }
30732 /* Return the builtin decl needed to store a vector of TYPE. */
30734 static tree
30736 {
30738 {
30740 {
30747 }
30748 }
30750 }
30751 \f
30752 /* Initialize the transactional memory vector load/store builtins. */
30754 static void
30756 {
30760 tree decl;
30767 /* If there are no builtins defined, we must be compiling in a
30768 language without trans-mem support. */
30772 /* Use whatever attributes a normal TM load has. */
30776 /* Use whatever attributes a normal TM store has. */
30780 /* Use whatever attributes a normal TM log has. */
30788 {
30792 {
30800 {
30803 }
30805 {
30808 }
30809 else
30810 {
30813 }
30815 /* The builtin without the prefix for
30816 calling it directly. */
30818 attrs);
30819 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30820 set the TYPE_ATTRIBUTES. */
30824 }
30825 }
30826 }
30828 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30829 in the current target ISA to allow the user to compile particular modules
30830 with different target specific options that differ from the command line
30831 options. */
30832 static void
30834 {
30839 /* Add all special builtins with variable number of operands. */
30843 {
30849 }
30851 /* Add all builtins with variable number of operands. */
30855 {
30861 }
30863 /* Add all builtins with rounding. */
30867 {
30873 }
30875 /* pcmpestr[im] insns. */
30879 {
30882 else
30885 }
30887 /* pcmpistr[im] insns. */
30891 {
30894 else
30897 }
30899 /* comi/ucomi insns. */
30901 {
30904 else
30907 }
30909 /* SSE */
30915 /* SSE or 3DNow!A */
30918 IX86_BUILTIN_MASKMOVQ);
30920 /* SSE2 */
30929 /* SSE3. */
30935 /* AES */
30949 /* PCLMUL */
30953 /* RDRND */
30960 IX86_BUILTIN_RDRAND64_STEP);
30962 /* AVX2 */
30964 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30965 IX86_BUILTIN_GATHERSIV2DF);
30968 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30969 IX86_BUILTIN_GATHERSIV4DF);
30972 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30973 IX86_BUILTIN_GATHERDIV2DF);
30976 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30977 IX86_BUILTIN_GATHERDIV4DF);
30980 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30981 IX86_BUILTIN_GATHERSIV4SF);
30984 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30985 IX86_BUILTIN_GATHERSIV8SF);
30988 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30989 IX86_BUILTIN_GATHERDIV4SF);
30992 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30993 IX86_BUILTIN_GATHERDIV8SF);
30996 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30997 IX86_BUILTIN_GATHERSIV2DI);
31000 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
31001 IX86_BUILTIN_GATHERSIV4DI);
31004 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
31005 IX86_BUILTIN_GATHERDIV2DI);
31008 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
31009 IX86_BUILTIN_GATHERDIV4DI);
31012 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
31013 IX86_BUILTIN_GATHERSIV4SI);
31016 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
31017 IX86_BUILTIN_GATHERSIV8SI);
31020 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
31021 IX86_BUILTIN_GATHERDIV4SI);
31024 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
31025 IX86_BUILTIN_GATHERDIV8SI);
31028 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
31029 IX86_BUILTIN_GATHERALTSIV4DF);
31032 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
31033 IX86_BUILTIN_GATHERALTDIV8SF);
31036 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
31037 IX86_BUILTIN_GATHERALTSIV4DI);
31040 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
31041 IX86_BUILTIN_GATHERALTDIV8SI);
31043 /* AVX512F */
31045 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
31046 IX86_BUILTIN_GATHER3SIV16SF);
31049 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
31050 IX86_BUILTIN_GATHER3SIV8DF);
31053 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
31054 IX86_BUILTIN_GATHER3DIV16SF);
31057 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
31058 IX86_BUILTIN_GATHER3DIV8DF);
31061 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
31062 IX86_BUILTIN_GATHER3SIV16SI);
31065 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
31066 IX86_BUILTIN_GATHER3SIV8DI);
31069 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
31070 IX86_BUILTIN_GATHER3DIV16SI);
31073 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
31074 IX86_BUILTIN_GATHER3DIV8DI);
31077 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
31078 IX86_BUILTIN_GATHER3ALTSIV8DF);
31081 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
31082 IX86_BUILTIN_GATHER3ALTDIV16SF);
31085 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
31086 IX86_BUILTIN_GATHER3ALTSIV8DI);
31089 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
31090 IX86_BUILTIN_GATHER3ALTDIV16SI);
31093 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
31094 IX86_BUILTIN_SCATTERSIV16SF);
31097 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
31098 IX86_BUILTIN_SCATTERSIV8DF);
31101 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
31102 IX86_BUILTIN_SCATTERDIV16SF);
31105 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
31106 IX86_BUILTIN_SCATTERDIV8DF);
31109 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
31110 IX86_BUILTIN_SCATTERSIV16SI);
31113 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
31114 IX86_BUILTIN_SCATTERSIV8DI);
31117 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
31118 IX86_BUILTIN_SCATTERDIV16SI);
31121 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
31122 IX86_BUILTIN_SCATTERDIV8DI);
31124 /* AVX512PF */
31126 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31127 IX86_BUILTIN_GATHERPFDPD);
31129 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31130 IX86_BUILTIN_GATHERPFDPS);
31132 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31133 IX86_BUILTIN_GATHERPFQPD);
31135 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31136 IX86_BUILTIN_GATHERPFQPS);
31138 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31139 IX86_BUILTIN_SCATTERPFDPD);
31141 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31142 IX86_BUILTIN_SCATTERPFDPS);
31144 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31145 IX86_BUILTIN_SCATTERPFQPD);
31147 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31148 IX86_BUILTIN_SCATTERPFQPS);
31150 /* SHA */
31166 /* RTM. */
31170 /* MMX access to the vec_init patterns. */
31175 V4HI_FTYPE_HI_HI_HI_HI,
31176 IX86_BUILTIN_VEC_INIT_V4HI);
31179 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31180 IX86_BUILTIN_VEC_INIT_V8QI);
31182 /* Access to the vec_extract patterns. */
31204 /* Access to the vec_set patterns. */
31225 /* RDSEED */
31234 /* ADCX */
31239 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31240 IX86_BUILTIN_ADDCARRYX64);
31242 /* Read/write FLAGS. */
31252 /* CLFLUSHOPT. */
31256 /* Add FMA4 multi-arg argument instructions */
31258 {
31264 }
31265 }
31267 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31268 to return a pointer to VERSION_DECL if the outcome of the expression
31269 formed by PREDICATE_CHAIN is true. This function will be called during
31270 version dispatch to decide which function version to execute. It returns
31271 the basic block at the end, to which more conditions can be added. */
31273 static basic_block
31276 {
31277 gimple return_stmt;
31279 gimple convert_stmt;
31280 gimple call_cond_stmt;
31281 gimple if_else_stmt;
31287 gimple_seq gseq;
31304 {
31312 }
31315 {
31330 else
31331 {
31332 gimple assign_stmt;
31333 /* Use MIN_EXPR to check if any integer is zero?.
31334 and_expr_var = min_expr <cond_var, and_expr_var> */
31342 }
31343 }
31346 integer_zero_node,
31376 }
31378 /* This parses the attribute arguments to target in DECL and determines
31379 the right builtin to use to match the platform specification.
31380 It returns the priority value for this version decl. If PREDICATE_LIST
31381 is not NULL, it stores the list of cpu features that need to be checked
31382 before dispatching this function. */
31384 static unsigned int
31386 {
31387 tree attrs;
31389 tree target_node;
31396 /* Priority of i386 features, greater value is higher priority. This is
31397 used to decide the order in which function dispatch must happen. For
31398 instance, a version specialized for SSE4.2 should be checked for dispatch
31399 before a version for SSE3, as SSE4.2 implies SSE3. */
31400 enum feature_priority
31401 {
31403 P_MMX,
31404 P_SSE,
31405 P_SSE2,
31406 P_SSE3,
31407 P_SSSE3,
31408 P_PROC_SSSE3,
31409 P_SSE4_A,
31410 P_PROC_SSE4_A,
31411 P_SSE4_1,
31412 P_SSE4_2,
31413 P_PROC_SSE4_2,
31414 P_POPCNT,
31415 P_AVX,
31416 P_PROC_AVX,
31417 P_FMA4,
31418 P_XOP,
31419 P_PROC_XOP,
31420 P_FMA,
31421 P_PROC_FMA,
31422 P_AVX2,
31423 P_PROC_AVX2
31424 };
31428 /* These are the target attribute strings for which a dispatcher is
31429 available, from fold_builtin_cpu. */
31431 static struct _feature_list
31432 {
31435 }
31437 {
31452 };
31455 static unsigned int NUM_FEATURES
31471 /* Return priority zero for default function. */
31475 /* Handle arch= if specified. For priority, set it to be 1 more than
31476 the best instruction set the processor can handle. For instance, if
31477 there is a version for atom and a version for ssse3 (the highest ISA
31478 priority for atom), the atom version must be checked for dispatch
31479 before the ssse3 version. */
31481 {
31491 {
31493 {
31501 else
31502 /* We translate "arch=corei7" and "arch=nehalem" to
31503 "corei7" so that it will be mapped to M_INTEL_COREI7
31504 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31511 else
31518 else
31558 }
31559 }
31564 {
31568 }
31571 {
31573 /* For a C string literal the length includes the trailing NULL. */
31576 predicate_chain);
31577 }
31578 }
31580 /* Process feature name. */
31587 {
31588 /* Do not process "arch=" */
31590 {
31593 }
31595 {
31597 {
31599 {
31604 predicate_chain);
31605 }
31606 /* Find the maximum priority feature. */
31611 }
31612 }
31614 {
31618 }
31620 }
31624 {
31627 attrs_str);
31629 }
31631 {
31634 }
31637 }
31639 /* This compares the priority of target features in function DECL1
31640 and DECL2. It returns positive value if DECL1 is higher priority,
31641 negative value if DECL2 is higher priority and 0 if they are the
31642 same. */
31644 static int
31646 {
31651 }
31653 /* V1 and V2 point to function versions with different priorities
31654 based on the target ISA. This function compares their priorities. */
31656 static int
31658 {
31660 {
31661 tree version_decl;
31662 tree predicate_chain;
31669 }
31671 /* This function generates the dispatch function for
31672 multi-versioned functions. DISPATCH_DECL is the function which will
31673 contain the dispatch logic. FNDECLS are the function choices for
31674 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31675 in DISPATCH_DECL in which the dispatch code is generated. */
31677 static int
31681 {
31682 tree default_decl;
31683 gimple ifunc_cpu_init_stmt;
31684 gimple_seq gseq;
31686 tree ele;
31692 struct _function_version_info
31693 {
31694 tree version_decl;
31695 tree predicate_chain;
31703 /*fndecls_p is actually a vector. */
31706 /* At least one more version other than the default. */
31713 /* The first version in the vector is the default decl. */
31719 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31720 constructors, so explicity call __builtin_cpu_init here. */
31731 {
31735 /* Get attribute string, parse it and find the right predicate decl.
31736 The predicate function could be a lengthy combination of many
31737 features, like arch-type and various isa-variants. */
31748 actual_versions++;
31749 }
31751 /* Sort the versions according to descending order of dispatch priority. The
31752 priority is based on the ISA. This is not a perfect solution. There
31753 could still be ambiguity. If more than one function version is suitable
31754 to execute, which one should be dispatched? In future, allow the user
31755 to specify a dispatch priority next to the version. */
31765 /* dispatch default version at the end. */
31771 }
31773 /* Comparator function to be used in qsort routine to sort attribute
31774 specification strings to "target". */
31776 static int
31778 {
31782 }
31784 /* ARGLIST is the argument to target attribute. This function tokenizes
31785 the comma separated arguments, sorts them and returns a string which
31786 is a unique identifier for the comma separated arguments. It also
31787 replaces non-identifier characters "=,-" with "_". */
31791 {
31792 tree arg;
31801 {
31806 argnum++;
31809 argnum++;
31810 }
31815 {
31821 }
31823 /* Replace "=,-" with "_". */
31836 {
31838 i++;
31840 }
31847 {
31852 }
31857 }
31859 /* This function changes the assembler name for functions that are
31860 versions. If DECL is a function version and has a "target"
31861 attribute, it appends the attribute string to its assembler name. */
31863 static tree
31865 {
31866 tree version_attr;
31874 "Function versions cannot be marked as gnu_inline,"
31883 /* target attribute string cannot be NULL. */
31887 version_string
31898 /* Allow assembler name to be modified if already set. */
31906 }
31908 /* This function returns true if FN1 and FN2 are versions of the same function,
31909 that is, the target strings of the function decls are different. This assumes
31910 that FN1 and FN2 have the same signature. */
31912 static bool
31914 {
31926 /* At least one function decl should have the target attribute specified. */
31930 /* Diagnose missing target attribute if one of the decls is already
31931 multi-versioned. */
31933 {
31935 {
31937 {
31942 }
31945 fn2);
31948 /* Prevent diagnosing of the same error multiple times. */
31953 }
31955 }
31960 /* The sorted target strings must be different for fn1 and fn2
31961 to be versions. */
31964 else
31971 }
31973 static tree
31975 {
31976 /* For function version, add the target suffix to the assembler name. */
31980 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31982 #endif
31985 }
31987 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31988 is true, append the full path name of the source file. */
31992 {
32000 /* Get a unique name that can be used globally without any chances
32001 of collision at link time. */
32011 /* Use '.' to concatenate names as it is demangler friendly. */
32014 suffix);
32015 else
32019 }
32021 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32023 /* Make a dispatcher declaration for the multi-versioned function DECL.
32024 Calls to DECL function will be replaced with calls to the dispatcher
32025 by the front-end. Return the decl created. */
32027 static tree
32029 {
32030 tree func_decl;
32050 /* Mark this func as external, the resolver will flip it again if
32051 it gets generated. */
32053 /* This will be of type IFUNCs have to be externally visible. */
32057 }
32059 #endif
32061 /* Returns true if decl is multi-versioned and DECL is the default function,
32062 that is it is not tagged with target specific optimization. */
32064 static bool
32066 {
32075 }
32077 /* Make a dispatcher declaration for the multi-versioned function DECL.
32078 Calls to DECL function will be replaced with calls to the dispatcher
32079 by the front-end. Returns the decl of the dispatcher function. */
32081 static tree
32083 {
32105 /* Find the default version and make it the first node. */
32107 /* Go to the beginning of the chain. */
32112 {
32117 }
32119 /* If there is no default node, just return NULL. */
32123 /* Make default info the first node. */
32125 {
32132 }
32136 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32138 {
32143 /* Right now, the dispatching is done via ifunc. */
32149 dispatcher_version_info
32154 /* Set the dispatcher for all the versions. */
32157 {
32160 }
32161 }
32162 else
32163 #endif
32164 {
32166 "multiversioning needs ifunc which is not supported "
32168 }
32171 }
32173 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32174 it to CHAIN. */
32176 static tree
32178 {
32179 tree attr_name;
32180 tree attr_arg_name;
32181 tree attr_args;
32182 tree attr;
32189 }
32191 /* Make the resolver function decl to dispatch the versions of
32192 a multi-versioned function, DEFAULT_DECL. Create an
32193 empty basic block in the resolver and store the pointer in
32194 EMPTY_BB. Return the decl of the resolver function. */
32196 static tree
32200 {
32205 /* IFUNC's have to be globally visible. So, if the default_decl is
32206 not, then the name of the IFUNC should be made unique. */
32210 /* Append the filename to the resolver function if the versions are
32211 not externally visible. This is because the resolver function has
32212 to be externally visible for the loader to find it. So, appending
32213 the filename will prevent conflicts with a resolver function from
32214 another module which is based on the same version name. */
32217 /* The resolver function should return a (void *). */
32228 /* IFUNC resolvers have to be externally visible. */
32232 /* Resolver is not external, body is generated. */
32242 {
32243 /* In this case, each translation unit with a call to this
32244 versioned function will put out a resolver. Ensure it
32245 is comdat to keep just one copy. */
32248 }
32249 /* Build result decl and add to function_decl. */
32265 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32269 /* Create the alias for dispatch to resolver here. */
32270 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32274 }
32276 /* Generate the dispatching code body to dispatch multi-versioned function
32277 DECL. The target hook is called to process the "target" attributes and
32278 provide the code to dispatch the right function at run-time. NODE points
32279 to the dispatcher decl whose body will be created. */
32281 static tree
32283 {
32284 tree resolver_decl;
32285 basic_block empty_bb;
32286 tree default_ver_decl;
32302 /* The first version in the chain corresponds to the default version. */
32305 /* node is going to be an alias, so remove the finalized bit. */
32319 {
32321 /* Check for virtual functions here again, as by this time it should
32322 have been determined if this function needs a vtable index or
32323 not. This happens for methods in derived classes that override
32324 virtual methods in base classes but are not explicitly marked as
32325 virtual. */
32330 }
32336 }
32337 /* This builds the processor_model struct type defined in
32338 libgcc/config/i386/cpuinfo.c */
32340 static tree
32342 {
32349 /* The first 3 fields are unsigned int. */
32351 {
32357 }
32359 /* The last field is an array of unsigned integers of size one. */
32370 }
32372 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32374 static tree
32376 {
32377 tree new_decl;
32380 VAR_DECL,
32382 type);
32395 }
32397 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32398 into an integer defined in libgcc/config/i386/cpuinfo.c */
32400 static tree
32402 {
32408 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32409 enum processor_features
32410 {
32412 F_MMX,
32413 F_POPCNT,
32414 F_SSE,
32415 F_SSE2,
32416 F_SSE3,
32417 F_SSSE3,
32418 F_SSE4_1,
32419 F_SSE4_2,
32420 F_AVX,
32421 F_AVX2,
32422 F_SSE4_A,
32423 F_FMA4,
32424 F_XOP,
32425 F_FMA,
32426 F_MAX
32427 };
32429 /* These are the values for vendor types and cpu types and subtypes
32430 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32431 the corresponding start value. */
32432 enum processor_model
32433 {
32435 M_AMD,
32436 M_CPU_TYPE_START,
32437 M_INTEL_BONNELL,
32438 M_INTEL_CORE2,
32439 M_INTEL_COREI7,
32440 M_AMDFAM10H,
32441 M_AMDFAM15H,
32442 M_INTEL_SILVERMONT,
32443 M_AMD_BTVER1,
32444 M_AMD_BTVER2,
32445 M_CPU_SUBTYPE_START,
32446 M_INTEL_COREI7_NEHALEM,
32447 M_INTEL_COREI7_WESTMERE,
32448 M_INTEL_COREI7_SANDYBRIDGE,
32449 M_AMDFAM10H_BARCELONA,
32450 M_AMDFAM10H_SHANGHAI,
32451 M_AMDFAM10H_ISTANBUL,
32452 M_AMDFAM15H_BDVER1,
32453 M_AMDFAM15H_BDVER2,
32454 M_AMDFAM15H_BDVER3,
32455 M_AMDFAM15H_BDVER4,
32456 M_INTEL_COREI7_IVYBRIDGE,
32457 M_INTEL_COREI7_HASWELL
32458 };
32460 static struct _arch_names_table
32461 {
32464 }
32466 {
32491 };
32493 static struct _isa_names_table
32494 {
32497 }
32499 {
32515 };
32529 {
32530 /* *args must be a expr that can contain other EXPRS leading to a
32531 STRING_CST. */
32533 {
32536 }
32538 }
32543 {
32544 tree ref;
32545 tree field;
32546 tree final;
32549 unsigned int NUM_ARCH_NAMES
32558 {
32562 }
32567 /* CPU types are stored in the next field. */
32570 {
32573 }
32575 /* CPU subtypes are stored in the next field. */
32577 {
32580 }
32582 /* Get the appropriate field in __cpu_model. */
32586 /* Check the value. */
32590 }
32592 {
32593 tree ref;
32594 tree array_elt;
32595 tree field;
32596 tree final;
32599 unsigned int NUM_ISA_NAMES
32608 {
32612 }
32615 /* Get the last field, which is __cpu_features. */
32619 /* Get the appropriate field: __cpu_model.__cpu_features */
32623 /* Access the 0th element of __cpu_features array. */
32628 /* Return __cpu_model.__cpu_features[0] & field_val */
32632 }
32634 }
32636 static tree
32639 {
32641 {
32646 {
32649 }
32650 }
32652 #ifdef SUBTARGET_FOLD_BUILTIN
32654 #endif
32657 }
32659 /* Make builtins to detect cpu type and features supported. NAME is
32660 the builtin name, CODE is the builtin code, and FTYPE is the function
32661 type of the builtin. */
32663 static void
32666 {
32667 tree decl;
32668 tree type;
32676 }
32678 /* Make builtins to get CPU type and features supported. The created
32679 builtins are :
32681 __builtin_cpu_init (), to detect cpu type and features,
32682 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32683 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32684 */
32686 static void
32688 {
32695 }
32697 /* Internal method for ix86_init_builtins. */
32699 static void
32701 {
32713 sysv_va_ref =
32716 fnvoid_va_end_ms =
32718 fnvoid_va_start_ms =
32720 fnvoid_va_end_sysv =
32722 fnvoid_va_start_sysv =
32724 NULL_TREE);
32725 fnvoid_va_copy_ms =
32727 NULL_TREE);
32728 fnvoid_va_copy_sysv =
32744 }
32746 static void
32748 {
32751 /* The __float80 type. */
32754 {
32755 /* The __float80 type. */
32760 }
32763 /* The __float128 type. */
32769 /* This macro is built by i386-builtin-types.awk. */
32770 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32771 }
32773 static void
32775 {
32776 tree t;
32780 /* Builtins to get CPU type and features. */
32783 /* TFmode support builtins. */
32789 /* We will expand them to normal call if SSE isn't available since
32790 they are used by libgcc. */
32809 #ifdef SUBTARGET_INIT_BUILTINS
32810 SUBTARGET_INIT_BUILTINS;
32811 #endif
32812 }
32814 /* Return the ix86 builtin for CODE. */
32816 static tree
32818 {
32823 }
32825 /* Errors in the source file can cause expand_expr to return const0_rtx
32826 where we expect a vector. To avoid crashing, use one of the vector
32827 clear instructions. */
32828 static rtx
32830 {
32834 }
32836 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32838 static rtx
32840 {
32841 rtx pat;
32861 {
32865 }
32879 }
32881 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32883 static rtx
32887 {
32888 rtx pat;
32896 rtx op;
32903 {
32983 }
32993 {
33000 {
33002 {
33005 {
33023 xop_rotl:
33025 {
33028 gcc_checking_assert
33030 }
33031 else
33032 {
33033 gcc_checking_assert
33044 }
33048 }
33049 }
33050 }
33051 else
33052 {
33053 non_constant:
33057 /* If we aren't optimizing, only allow one memory operand to be
33058 generated. */
33060 num_memory++;
33068 }
33072 }
33075 {
33086 else
33087 {
33093 }
33106 }
33113 }
33115 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
33116 insns with vec_merge. */
33118 static rtx
33120 rtx target)
33121 {
33122 rtx pat;
33149 }
33151 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33153 static rtx
33156 {
33157 rtx pat;
33162 rtx op2;
33173 /* Swap operands if we have a comparison that isn't available in
33174 hardware. */
33176 {
33181 }
33201 }
33203 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33205 static rtx
33207 rtx target)
33208 {
33209 rtx pat;
33223 /* Swap operands if we have a comparison that isn't available in
33224 hardware. */
33226 {
33230 }
33251 const0_rtx)));
33254 }
33256 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33258 static rtx
33260 rtx target)
33261 {
33262 rtx pat;
33287 }
33289 static rtx
33292 {
33293 rtx pat;
33298 rtx op2;
33325 }
33327 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33329 static rtx
33331 rtx target)
33332 {
33333 rtx pat;
33366 const0_rtx)));
33369 }
33371 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33373 static rtx
33376 {
33377 rtx pat;
33415 {
33418 }
33421 {
33430 }
33432 {
33441 }
33442 else
33443 {
33450 }
33458 {
33463 emit_insn
33467 FLAGS_REG),
33468 const0_rtx)));
33470 }
33471 else
33473 }
33476 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33478 static rtx
33481 {
33482 rtx pat;
33510 {
33513 }
33516 {
33525 }
33527 {
33536 }
33537 else
33538 {
33545 }
33553 {
33558 emit_insn
33562 FLAGS_REG),
33563 const0_rtx)));
33565 }
33566 else
33568 }
33570 /* Subroutine of ix86_expand_builtin to take care of insns with
33571 variable number of operands. */
33573 static rtx
33576 {
33582 struct
33583 {
33584 rtx op;
33596 {
34048 }
34053 {
34056 }
34059 {
34066 }
34067 else
34068 {
34071 }
34074 {
34081 {
34082 /* SIMD shift insns take either an 8-bit immediate or
34083 register as count. But builtin functions take int as
34084 count. If count doesn't match, we put it in register. */
34086 {
34090 }
34091 }
34094 {
34097 {
34173 {
34177 {
34180 }
34186 }
34188 }
34189 }
34190 else
34191 {
34195 /* If we aren't optimizing, only allow one memory operand to
34196 be generated. */
34198 num_memory++;
34201 {
34204 }
34205 else
34206 {
34209 }
34210 }
34214 }
34217 {
34242 }
34249 }
34251 /* Transform pattern of following layout:
34252 (parallel [
34253 set (A B)
34254 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34255 ])
34256 into:
34257 (set (A B))
34259 Or:
34260 (parallel [ A B
34261 ...
34262 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34263 ...
34264 ])
34265 into:
34266 (parallel [ A B ... ]) */
34268 static rtx
34270 {
34277 {
34286 }
34287 else
34288 {
34294 {
34299 }
34301 /* No more than 1 occurence was removed. */
34305 }
34306 }
34308 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34309 with rounding. */
34310 static rtx
34313 {
34330 /* See avxintrin.h for values. */
34332 {
34336 };
34338 {
34343 };
34346 {
34349 }
34351 {
34354 }
34357 {
34360 }
34383 ? CODE_FOR_sse_ucomi_round
34390 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34392 {
34398 }
34399 else
34400 {
34403 }
34409 set_dst,
34410 const0_rtx)));
34413 }
34415 static rtx
34418 {
34419 rtx pat;
34421 struct
34422 {
34423 rtx op;
34433 {
34510 }
34520 {
34527 {
34529 {
34531 {
34547 }
34548 }
34549 }
34551 {
34553 {
34556 }
34558 /* If there is no rounding use normal version of the pattern. */
34561 }
34562 else
34563 {
34568 {
34571 }
34572 else
34573 {
34576 }
34577 }
34581 }
34584 {
34609 }
34619 }
34621 /* Subroutine of ix86_expand_builtin to take care of special insns
34622 with variable number of operands. */
34624 static rtx
34627 {
34628 tree arg;
34632 struct
34633 {
34634 rtx op;
34644 {
34684 {
34692 }
34711 /* Reserve memory operand for target. */
34714 {
34715 /* These builtins and instructions require the memory
34716 to be properly aligned. */
34735 }
34760 {
34761 /* These builtins and instructions require the memory
34762 to be properly aligned. */
34779 }
34780 /* FALLTHRU */
34798 /* Reserve memory operand for target. */
34811 {
34812 /* These builtins and instructions require the memory
34813 to be properly aligned. */
34836 }
34849 }
34854 {
34859 {
34862 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34863 on it. Try to improve it using get_pointer_alignment,
34864 and if the special builtin is one that requires strict
34865 mode alignment, also from it's GET_MODE_ALIGNMENT.
34866 Failure to do so could lead to ix86_legitimate_combined_insn
34867 rejecting all changes to such insns. */
34873 }
34874 else
34877 }
34878 else
34879 {
34886 }
34889 {
34898 {
34900 {
34906 else
34909 }
34910 }
34911 else
34912 {
34914 {
34915 /* This must be the memory operand. */
34918 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34919 on it. Try to improve it using get_pointer_alignment,
34920 and if the special builtin is one that requires strict
34921 mode alignment, also from it's GET_MODE_ALIGNMENT.
34922 Failure to do so could lead to ix86_legitimate_combined_insn
34923 rejecting all changes to such insns. */
34929 }
34930 else
34931 {
34932 /* This must be register. */
34938 else
34939 {
34942 }
34943 }
34944 }
34948 }
34951 {
34966 }
34972 }
34974 /* Return the integer constant in ARG. Constrain it to be in the range
34975 of the subparts of VEC_TYPE; issue an error if not. */
34977 static int
34979 {
34984 {
34987 }
34990 }
34992 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34993 ix86_expand_vector_init. We DO have language-level syntax for this, in
34994 the form of (type){ init-list }. Except that since we can't place emms
34995 instructions from inside the compiler, we can't allow the use of MMX
34996 registers unless the user explicitly asks for it. So we do *not* define
34997 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34998 we have builtins invoked by mmintrin.h that gives us license to emit
34999 these sorts of instructions. */
35001 static rtx
35003 {
35013 {
35016 }
35023 }
35025 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35026 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
35027 had a language-level syntax for referencing vector elements. */
35029 static rtx
35031 {
35035 rtx op0;
35055 }
35057 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35058 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
35059 a language-level syntax for referencing vector elements. */
35061 static rtx
35063 {
35087 /* OP0 is the source of these builtin functions and shouldn't be
35088 modified. Create a copy, use it and return it as target. */
35094 }
35096 /* Expand an expression EXP that calls a built-in function,
35097 with result going to TARGET if that's convenient
35098 (and in mode MODE if that's convenient).
35099 SUBTARGET may be used as the target for computing one of EXP's operands.
35100 IGNORE is nonzero if the value is to be ignored. */
35102 static rtx
35105 {
35115 /* For CPU builtins that can be folded, fold first and expand the fold. */
35117 {
35119 {
35120 /* Make it call __cpu_indicator_init in libgcc. */
35126 }
35129 {
35134 }
35135 }
35137 /* Determine whether the builtin function is available under the current ISA.
35138 Originally the builtin was not created if it wasn't applicable to the
35139 current ISA based on the command line switches. With function specific
35140 options, we need to check in the context of the function making the call
35141 whether it is supported. */
35144 {
35150 else
35151 {
35155 }
35157 }
35160 {
35164 ? CODE_FOR_mmx_maskmovq
35166 /* Note the arg order is different from the operand order. */
35277 {
35278 REAL_VALUE_TYPE inf;
35279 rtx tmp;
35291 }
35301 {
35307 insn = (TARGET_64BIT
35311 }
35313 {
35314 insn = (TARGET_64BIT
35318 }
35319 else
35320 {
35323 insn = (TARGET_64BIT
35331 {
35334 }
35336 }
35339 {
35340 /* mode is VOIDmode if __builtin_rd* has been called
35341 without lhs. */
35345 }
35348 {
35353 }
35366 {
35387 }
35393 {
35396 }
35422 {
35425 }
35431 {
35435 {
35474 }
35479 }
35480 else
35481 {
35483 {
35504 }
35506 }
35536 ? CODE_FOR_tbm_bextri_si
35539 {
35542 }
35543 else
35544 {
35553 }
35569 rdrand_step:
35576 {
35579 }
35585 /* Emit SImode conditional move. */
35587 {
35590 }
35593 else
35601 const0_rtx);
35620 rdseed_step:
35627 {
35630 }
35636 const0_rtx);
35655 addcarryx:
35663 /* Generate CF from input operand. */
35668 /* Gen ADCX instruction to compute X+Y+CF. */
35683 /* Store the result. */
35686 {
35689 }
35692 /* Return current CF value. */
35734 kortest:
35748 /* Emit kortest. */
35750 /* And use setcc to return result from flags. */
35901 gather_gen:
35902 rtx half;
35915 /* Note the arg order is different from the operand order. */
35926 else
35930 {
35952 else
35959 {
35964 }
35971 else
35978 {
35983 }
35987 }
35989 /* Force memory operand only with base register here. But we
35990 don't want to do it on memory operand for other builtin
35991 functions. */
36001 {
36004 }
36005 else
36006 {
36009 }
36011 {
36014 }
36016 /* Optimize. If mask is known to have all high bits set,
36017 replace op0 with pc_rtx to signal that the instruction
36018 overwrites the whole destination and doesn't use its
36019 previous contents. */
36021 {
36023 {
36026 }
36028 {
36031 {
36035 negative++;
36038 negative++;
36039 }
36042 }
36045 {
36046 /* Recognize also when mask is like:
36047 __v2df src = _mm_setzero_pd ();
36048 __v2df mask = _mm_cmpeq_pd (src, src);
36049 or
36050 __v8sf src = _mm256_setzero_ps ();
36051 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
36052 as that is a cheaper way to load all ones into
36053 a register than having to load a constant from
36054 memory. */
36057 {
36062 {
36069 /* FALLTHRU */
36079 }
36080 }
36081 }
36082 }
36090 {
36114 }
36117 scatter_gen:
36133 /* Force memory operand only with base register here. But we
36134 don't want to do it on memory operand for other builtin
36135 functions. */
36142 {
36145 }
36146 else
36147 {
36150 }
36159 {
36162 }
36171 vec_prefetch_gen:
36189 {
36192 }
36194 {
36197 }
36202 /* Force memory operand only with base register here. But we
36203 don't want to do it on memory operand for other builtin
36204 functions. */
36211 {
36214 }
36217 {
36220 }
36236 {
36239 }
36245 }
36258 {
36262 /* Emit a normal call if SSE isn't available. */
36266 }
36295 }
36297 /* This returns the target-specific builtin with code CODE if
36298 current_function_decl has visibility on this builtin, which is checked
36299 using isa flags. Returns NULL_TREE otherwise. */
36302 {
36306 /* Determine the isa flags of current_function_decl. */
36318 else
36320 }
36322 /* Returns a function decl for a vectorized version of the builtin function
36323 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36324 if it is not available. */
36326 static tree
36328 tree type_in)
36329 {
36345 {
36348 {
36355 }
36360 {
36363 }
36368 {
36375 }
36381 /* The round insn does not trap on denormals. */
36386 {
36393 }
36399 /* The round insn does not trap on denormals. */
36404 {
36409 }
36415 /* The round insn does not trap on denormals. */
36420 {
36427 }
36433 /* The round insn does not trap on denormals. */
36438 {
36443 }
36450 {
36455 }
36462 {
36467 }
36473 /* The round insn does not trap on denormals. */
36478 {
36485 }
36491 /* The round insn does not trap on denormals. */
36496 {
36501 }
36506 {
36513 }
36518 {
36525 }
36529 /* The round insn does not trap on denormals. */
36534 {
36539 }
36543 /* The round insn does not trap on denormals. */
36548 {
36553 }
36557 /* The round insn does not trap on denormals. */
36562 {
36567 }
36571 /* The round insn does not trap on denormals. */
36576 {
36581 }
36585 /* The round insn does not trap on denormals. */
36590 {
36595 }
36599 /* The round insn does not trap on denormals. */
36604 {
36609 }
36613 /* The round insn does not trap on denormals. */
36618 {
36623 }
36627 /* The round insn does not trap on denormals. */
36632 {
36637 }
36641 /* The round insn does not trap on denormals. */
36646 {
36651 }
36655 /* The round insn does not trap on denormals. */
36660 {
36665 }
36670 {
36675 }
36680 {
36685 }
36690 }
36692 /* Dispatch to a handler for a vectorization library. */
36695 type_in);
36698 }
36700 /* Handler for an SVML-style interface to
36701 a library with vectorized intrinsics. */
36703 static tree
36705 {
36713 /* The SVML is suitable for unsafe math only. */
36726 {
36773 }
36782 {
36785 }
36786 else
36789 /* Convert to uppercase. */
36794 args;
36796 arity++;
36800 else
36803 /* Build a function declaration for the vectorized function. */
36812 }
36814 /* Handler for an ACML-style interface to
36815 a library with vectorized intrinsics. */
36817 static tree
36819 {
36827 /* The ACML is 64bits only and suitable for unsafe math only as
36828 it does not correctly support parts of IEEE with the required
36829 precision such as denormals. */
36843 {
36873 }
36880 args;
36882 arity++;
36886 else
36889 /* Build a function declaration for the vectorized function. */
36898 }
36900 /* Returns a decl of a function that implements gather load with
36901 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36902 Return NULL_TREE if it is not available. */
36904 static tree
36907 {
36923 /* v*gather* insn sign extends index to pointer mode. */
36935 {
36963 else
36969 else
36975 else
36981 else
36986 }
36989 }
36991 /* Returns a code for a target-specific builtin that implements
36992 reciprocal of the function, or NULL_TREE if not available. */
36994 static tree
36996 {
37003 /* Machine dependent builtins. */
37005 {
37006 /* Vectorized version of sqrt to rsqrt conversion. */
37015 }
37016 else
37017 /* Normal builtins. */
37019 {
37020 /* Sqrt to rsqrt conversion. */
37026 }
37027 }
37028 \f
37029 /* Helper for avx_vpermilps256_operand et al. This is also used by
37030 the expansion functions to turn the parallel back into a mask.
37031 The return value is 0 for no match and the imm8+1 for a match. */
37033 int
37035 {
37043 /* Validate that all of the elements are constants, and not totally
37044 out of range. Copy the data into an integral array to make the
37045 subsequent checks easier. */
37047 {
37057 }
37060 {
37062 /* In the 512-bit DFmode case, we can only move elements within
37063 a 128-bit lane. First fill the second part of the mask,
37064 then fallthru. */
37066 {
37070 }
37072 {
37076 }
37077 /* FALLTHRU */
37080 /* In the 256-bit DFmode case, we can only move elements within
37081 a 128-bit lane. */
37083 {
37087 }
37089 {
37093 }
37097 /* In 512 bit SFmode case, permutation in the upper 256 bits
37098 must mirror the permutation in the lower 256-bits. */
37102 /* FALLTHRU */
37105 /* In 256 bit SFmode case, we have full freedom of
37106 movement within the low 128-bit lane, but the high 128-bit
37107 lane must mirror the exact same pattern. */
37112 /* FALLTHRU */
37116 /* In the 128-bit case, we've full freedom in the placement of
37117 the elements from the source operand. */
37124 }
37126 /* Make sure success has a non-zero value by adding one. */
37128 }
37130 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
37131 the expansion functions to turn the parallel back into a mask.
37132 The return value is 0 for no match and the imm8+1 for a match. */
37134 int
37136 {
37144 /* Validate that all of the elements are constants, and not totally
37145 out of range. Copy the data into an integral array to make the
37146 subsequent checks easier. */
37148 {
37158 }
37160 /* Validate that the halves of the permute are halves. */
37168 /* Reconstruct the mask. */
37170 {
37176 }
37178 /* Make sure success has a non-zero value by adding one. */
37180 }
37181 \f
37182 /* Return a register priority for hard reg REGNO. */
37183 static int
37185 {
37186 /* ebp and r13 as the base always wants a displacement, r12 as the
37187 base always wants an index. So discourage their usage in an
37188 address. */
37193 /* New x86-64 int registers result in bigger code size. Discourage
37194 them. */
37197 /* New x86-64 SSE registers result in bigger code size. Discourage
37198 them. */
37201 /* Usage of AX register results in smaller code. Prefer it. */
37205 }
37207 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37209 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37210 QImode must go into class Q_REGS.
37211 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37212 movdf to do mem-to-mem moves through integer regs. */
37214 static reg_class_t
37216 {
37219 /* We're only allowed to return a subclass of CLASS. Many of the
37220 following checks fail for NO_REGS, so eliminate that early. */
37224 /* All classes can load zeros. */
37228 /* Force constants into memory if we are loading a (nonzero) constant into
37229 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37230 instructions to load from a constant. */
37237 /* Prefer SSE regs only, if we can use them for math. */
37241 /* Floating-point constants need more complex checks. */
37243 {
37244 /* General regs can load everything. */
37248 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37249 zero above. We only want to wind up preferring 80387 registers if
37250 we plan on doing computation with them. */
37253 {
37254 /* Limit class to non-sse. */
37263 }
37266 }
37268 /* Generally when we see PLUS here, it's the function invariant
37269 (plus soft-fp const_int). Which can only be computed into general
37270 regs. */
37274 /* QImode constants are easy to load, but non-constant QImode data
37275 must go into Q_REGS. */
37277 {
37283 }
37286 }
37288 /* Discourage putting floating-point values in SSE registers unless
37289 SSE math is being used, and likewise for the 387 registers. */
37290 static reg_class_t
37292 {
37295 /* Restrict the output reload class to the register bank that we are doing
37296 math on. If we would like not to return a subset of CLASS, reject this
37297 alternative: if reload cannot do this, it will still use its choice. */
37303 {
37308 else
37310 }
37313 }
37315 static reg_class_t
37318 {
37319 /* Double-word spills from general registers to non-offsettable memory
37320 references (zero-extended addresses) require special handling. */
37326 {
37328 ? CODE_FOR_reload_noff_load
37330 /* Add the cost of moving address to a temporary. */
37334 }
37336 /* QImode spills from non-QI registers require
37337 intermediate register on 32bit targets. */
37343 {
37348 else
37354 /* Return Q_REGS if the operand is in memory. */
37357 }
37359 /* This condition handles corner case where an expression involving
37360 pointers gets vectorized. We're trying to use the address of a
37361 stack slot as a vector initializer.
37363 (set (reg:V2DI 74 [ vect_cst_.2 ])
37364 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37366 Eventually frame gets turned into sp+offset like this:
37368 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37369 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37370 (const_int 392 [0x188]))))
37372 That later gets turned into:
37374 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37375 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37376 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37378 We'll have the following reload recorded:
37380 Reload 0: reload_in (DI) =
37381 (plus:DI (reg/f:DI 7 sp)
37382 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37383 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37384 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37385 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37386 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37387 reload_reg_rtx: (reg:V2DI 22 xmm1)
37389 Which isn't going to work since SSE instructions can't handle scalar
37390 additions. Returning GENERAL_REGS forces the addition into integer
37391 register and reload can handle subsequent reloads without problems. */
37399 }
37401 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37403 static bool
37405 {
37407 {
37422 }
37425 }
37427 /* If we are copying between general and FP registers, we need a memory
37428 location. The same is true for SSE and MMX registers.
37430 To optimize register_move_cost performance, allow inline variant.
37432 The macro can't work reliably when one of the CLASSES is class containing
37433 registers from multiple units (SSE, MMX, integer). We avoid this by never
37434 combining those units in single alternative in the machine description.
37435 Ensure that this constraint holds to avoid unexpected surprises.
37437 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37438 enforce these sanity checks. */
37443 {
37452 {
37455 }
37460 /* Between mask and general, we have moves no larger than word size. */
37465 /* ??? This is a lie. We do have moves between mmx/general, and for
37466 mmx/sse2. But by saying we need secondary memory we discourage the
37467 register allocator from using the mmx registers unless needed. */
37472 {
37473 /* SSE1 doesn't have any direct moves from other classes. */
37477 /* If the target says that inter-unit moves are more expensive
37478 than moving through memory, then don't generate them. */
37483 /* Between SSE and general, we have moves no larger than word size. */
37486 }
37489 }
37491 bool
37494 {
37496 }
37498 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37500 On the 80386, this is the size of MODE in words,
37501 except in the FP regs, where a single reg is always enough. */
37503 static unsigned char
37505 {
37507 {
37512 else
37514 }
37515 else
37516 {
37519 else
37521 }
37522 }
37524 /* Return true if the registers in CLASS cannot represent the change from
37525 modes FROM to TO. */
37527 bool
37530 {
37534 /* x87 registers can't do subreg at all, as all values are reformatted
37535 to extended precision. */
37540 {
37541 /* Vector registers do not support QI or HImode loads. If we don't
37542 disallow a change to these modes, reload will assume it's ok to
37543 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37544 the vec_dupv4hi pattern. */
37548 /* Vector registers do not support subreg with nonzero offsets, which
37549 are otherwise valid for integer registers. Since we can't see
37550 whether we have a nonzero offset from here, prohibit all
37551 nonparadoxical subregs changing size. */
37554 }
37557 }
37559 /* Return the cost of moving data of mode M between a
37560 register and memory. A value of 2 is the default; this cost is
37561 relative to those in `REGISTER_MOVE_COST'.
37563 This function is used extensively by register_move_cost that is used to
37564 build tables at startup. Make it inline in this case.
37565 When IN is 2, return maximum of in and out move cost.
37567 If moving between registers and memory is more expensive than
37568 between two registers, you should define this macro to express the
37569 relative cost.
37571 Model also increased moving costs of QImode registers in non
37572 Q_REGS classes.
37573 */
37577 {
37580 {
37583 {
37595 }
37599 }
37601 {
37604 {
37616 }
37620 }
37622 {
37625 {
37634 }
37638 }
37640 {
37643 {
37649 else
37654 }
37655 else
37656 {
37661 else
37663 }
37670 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37677 else
37681 }
37682 }
37684 static int
37687 {
37689 }
37692 /* Return the cost of moving data from a register in class CLASS1 to
37693 one in class CLASS2.
37695 It is not required that the cost always equal 2 when FROM is the same as TO;
37696 on some machines it is expensive to move between registers if they are not
37697 general registers. */
37699 static int
37701 reg_class_t class2_i)
37702 {
37706 /* In case we require secondary memory, compute cost of the store followed
37707 by load. In order to avoid bad register allocation choices, we need
37708 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37711 {
37717 /* In case of copying from general_purpose_register we may emit multiple
37718 stores followed by single load causing memory size mismatch stall.
37719 Count this as arbitrarily high cost of 20. */
37724 /* In the case of FP/MMX moves, the registers actually overlap, and we
37725 have to switch modes in order to treat them differently. */
37731 }
37733 /* Moves between SSE/MMX and integer unit are expensive. */
37737 /* ??? By keeping returned value relatively high, we limit the number
37738 of moves between integer and MMX/SSE registers for all targets.
37739 Additionally, high value prevents problem with x86_modes_tieable_p(),
37740 where integer modes in MMX/SSE registers are not tieable
37741 because of missing QImode and HImode moves to, from or between
37742 MMX/SSE registers. */
37752 }
37754 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37755 MODE. */
37757 bool
37759 {
37760 /* Flags and only flags can only hold CCmode values. */
37773 {
37774 /* We implement the move patterns for all vector modes into and
37775 out of SSE registers, even when no operation instructions
37776 are available. */
37778 /* For AVX-512 we allow, regardless of regno:
37779 - XI mode
37780 - any of 512-bit wide vector mode
37781 - any scalar mode. */
37788 /* TODO check for QI/HI scalars. */
37789 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
37797 /* xmm16-xmm31 are only available for AVX-512. */
37801 /* OImode and AVX modes are available only when AVX is enabled. */
37808 }
37810 {
37811 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37812 so if the register is available at all, then we can move data of
37813 the given mode into or out of it. */
37816 }
37819 {
37820 /* Take care for QImode values - they can be in non-QI regs,
37821 but then they do cause partial register stalls. */
37826 /* LRA checks if the hard register is OK for the given mode.
37827 QImode values can live in non-QI regs, so we allow all
37828 registers here. */
37832 }
37833 /* We handle both integer and floats in the general purpose registers. */
37840 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37841 on to use that value in smaller contexts, this can easily force a
37842 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37843 supporting DImode, allow it. */
37848 }
37850 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37851 tieable integer mode. */
37853 static bool
37855 {
37857 {
37870 }
37871 }
37873 /* Return true if MODE1 is accessible in a register that can hold MODE2
37874 without copying. That is, all register classes that can hold MODE2
37875 can also hold MODE1. */
37877 bool
37879 {
37887 /* MODE2 being XFmode implies fp stack or general regs, which means we
37888 can tie any smaller floating point modes to it. Note that we do not
37889 tie this with TFmode. */
37893 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37894 that we can tie it with SFmode. */
37898 /* If MODE2 is only appropriate for an SSE register, then tie with
37899 any other mode acceptable to SSE registers. */
37909 /* If MODE2 is appropriate for an MMX register, then tie
37910 with any other mode acceptable to MMX registers. */
37917 }
37919 /* Return the cost of moving between two registers of mode MODE. */
37921 static int
37923 {
37927 {
37959 }
37961 /* Return the cost of moving between two registers of mode MODE,
37962 assuming that the move will be in pieces of at most UNITS bytes. */
37964 }
37966 /* Compute a (partial) cost for rtx X. Return true if the complete
37967 cost has been computed, and false if subexpressions should be
37968 scanned. In either case, *TOTAL contains the cost result. */
37970 static bool
37973 {
37974 rtx mask;
37981 {
37985 {
37988 }
38000 && !(TARGET_64BIT
38005 else
38011 {
38014 }
38016 {
38026 }
38028 {
38031 {
38040 }
38041 }
38042 /* Fall back to (MEM (SYMBOL_REF)), since that's where
38043 it'll probably end up. Add a penalty for size. */
38050 /* The zero extensions is often completely free on x86_64, so make
38051 it as cheap as possible. */
38057 else
38069 {
38072 {
38075 }
38078 {
38081 }
38082 }
38083 /* FALLTHRU */
38090 {
38091 /* ??? Should be SSE vector operation cost. */
38092 /* At least for published AMD latencies, this really is the same
38093 as the latency for a simple fpu operation like fabs. */
38094 /* V*QImode is emulated with 1-11 insns. */
38096 {
38099 {
38100 /* For XOP we use vpshab, which requires a broadcast of the
38101 value to the variable shift insn. For constants this
38102 means a V16Q const in mem; even when we can perform the
38103 shift with one insn set the cost to prefer paddb. */
38105 {
38110 }
38112 }
38116 }
38117 else
38119 }
38121 {
38123 {
38126 else
38128 }
38129 else
38130 {
38133 else
38135 }
38136 }
38137 else
38138 {
38143 {
38144 /* Return the cost after shift-and truncation. */
38147 }
38148 else
38150 }
38154 {
38155 rtx sub;
38160 /* ??? SSE scalar/vector cost should be used here. */
38161 /* ??? Bald assumption that fma has the same cost as fmul. */
38165 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38176 }
38180 {
38181 /* ??? SSE scalar cost should be used here. */
38184 }
38186 {
38189 }
38191 {
38192 /* ??? SSE vector cost should be used here. */
38195 }
38197 {
38198 /* V*QImode is emulated with 7-13 insns. */
38200 {
38207 }
38208 /* V*DImode is emulated with 5-8 insns. */
38210 {
38213 else
38215 }
38216 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38217 insns, including two PMULUDQ. */
38220 else
38223 }
38224 else
38225 {
38230 {
38233 nbits++;
38234 }
38235 else
38236 /* This is arbitrary. */
38239 /* Compute costs correctly for widening multiplication. */
38243 {
38250 {
38254 else
38256 }
38260 }
38268 }
38275 /* ??? SSE cost should be used here. */
38280 /* ??? SSE vector cost should be used here. */
38282 else
38289 {
38294 {
38297 {
38305 }
38306 }
38309 {
38312 {
38318 }
38319 }
38321 {
38329 }
38330 }
38331 /* FALLTHRU */
38335 {
38336 /* ??? SSE cost should be used here. */
38339 }
38341 {
38344 }
38346 {
38347 /* ??? SSE vector cost should be used here. */
38350 }
38351 /* FALLTHRU */
38358 {
38365 }
38366 /* FALLTHRU */
38370 {
38371 /* ??? SSE cost should be used here. */
38374 }
38376 {
38379 }
38381 {
38382 /* ??? SSE vector cost should be used here. */
38385 }
38386 /* FALLTHRU */
38390 {
38391 /* ??? Should be SSE vector operation cost. */
38392 /* At least for published AMD latencies, this really is the same
38393 as the latency for a simple fpu operation like fabs. */
38395 }
38398 else
38407 {
38408 /* This kind of construct is implemented using test[bwl].
38409 Treat it as if we had an AND. */
38414 }
38424 /* ??? SSE cost should be used here. */
38429 /* ??? SSE vector cost should be used here. */
38435 /* ??? SSE cost should be used here. */
38440 /* ??? SSE vector cost should be used here. */
38452 /* ??? Assume all of these vector manipulation patterns are
38453 recognizable. In which case they all pretty much have the
38454 same cost. */
38459 /* This is masked instruction, assume the same cost,
38460 as nonmasked variant. */
38463 else
38469 }
38470 }
38472 #if TARGET_MACHO
38476 /* Given a symbol name and its associated stub, write out the
38477 definition of the stub. */
38479 void
38481 {
38486 /* For 64-bit we shouldn't get here. */
38489 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38506 else
38513 {
38515 }
38517 {
38518 /* PIC stub. */
38519 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38525 }
38526 else
38529 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38530 it needs no stub-binding-helper. */
38537 {
38540 }
38541 else
38546 /* N.B. Keep the correspondence of these
38547 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38548 old-pic/new-pic/non-pic stubs; altering this will break
38549 compatibility with existing dylibs. */
38551 {
38552 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38554 }
38555 else
38556 /* 16-byte -mdynamic-no-pic stub. */
38562 }
38565 /* Order the registers for register allocator. */
38567 void
38569 {
38573 /* First allocate the local general purpose registers. */
38578 /* Global general purpose registers. */
38583 /* x87 registers come first in case we are doing FP math
38584 using them. */
38589 /* SSE registers. */
38595 /* Extended REX SSE registers. */
38599 /* Mask register. */
38603 /* x87 registers. */
38611 /* Initialize the rest of array as we do not allocate some registers
38612 at all. */
38615 }
38617 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38618 in struct attribute_spec handler. */
38619 static tree
38621 tree args,
38624 {
38629 {
38631 name);
38634 }
38636 {
38638 name);
38641 }
38643 {
38644 tree cst;
38648 {
38651 name);
38653 }
38656 {
38659 name);
38661 }
38664 }
38667 }
38669 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38670 struct attribute_spec.handler. */
38671 static tree
38674 {
38679 {
38681 name);
38684 }
38686 /* Can combine regparm with all attributes but fastcall. */
38688 {
38690 {
38692 }
38695 }
38697 {
38699 {
38701 }
38704 }
38707 }
38709 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38710 struct attribute_spec.handler. */
38711 static tree
38714 {
38717 {
38720 }
38721 else
38725 {
38727 name);
38729 }
38735 {
38737 name);
38739 }
38742 }
38744 static tree
38747 {
38749 {
38751 name);
38753 }
38755 }
38757 static bool
38759 {
38763 }
38765 /* Returns an expression indicating where the this parameter is
38766 located on entry to the FUNCTION. */
38768 static rtx
38770 {
38776 {
38781 else
38784 }
38789 {
38796 {
38801 }
38802 else
38803 {
38806 {
38812 }
38813 }
38815 }
38819 }
38821 /* Determine whether x86_output_mi_thunk can succeed. */
38823 static bool
38825 const_tree function)
38826 {
38827 /* 64-bit can handle anything. */
38831 /* For 32-bit, everything's fine if we have one free register. */
38835 /* Need a free register for vcall_offset. */
38839 /* Need a free register for GOT references. */
38843 /* Otherwise ok. */
38845 }
38847 /* Output the assembler code for a thunk function. THUNK_DECL is the
38848 declaration for the thunk function itself, FUNCTION is the decl for
38849 the target function. DELTA is an immediate constant offset to be
38850 added to THIS. If VCALL_OFFSET is nonzero, the word at
38851 *(*this + vcall_offset) should be added to THIS. */
38853 static void
38856 {
38864 else
38865 {
38871 else
38873 }
38877 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38878 pull it in now and let DELTA benefit. */
38882 {
38883 /* Put the this parameter into %eax. */
38886 }
38887 else
38890 /* Adjust the this parameter by a fixed constant. */
38892 {
38897 {
38899 {
38903 }
38904 }
38907 }
38909 /* Adjust the this parameter by a value stored in the vtable. */
38911 {
38921 /* Adjust the this parameter. */
38925 {
38929 }
38936 vcall_mem));
38937 else
38939 }
38941 /* If necessary, drop THIS back to its stack slot. */
38947 {
38950 ;
38951 else
38952 {
38956 }
38957 }
38958 else
38959 {
38961 ;
38962 #if TARGET_MACHO
38964 {
38967 }
38969 else
38970 {
38978 }
38979 }
38981 /* Our sibling call patterns do not allow memories, because we have no
38982 predicate that can distinguish between frame and non-frame memory.
38983 For our purposes here, we can get away with (ab)using a jump pattern,
38984 because we're going to do no optimization. */
38986 {
38988 {
38992 }
38993 else
38995 }
38996 else
38997 {
39003 {
39009 }
39015 }
39018 /* Emit just enough of rest_of_compilation to get the insns emitted.
39019 Note that use_thunk calls assemble_start_function et al. */
39025 }
39027 static void
39029 {
39033 #if TARGET_MACHO
39035 #endif
39042 }
39044 int
39046 {
39058 }
39060 /* Output assembler code to FILE to increment profiler label # LABELNO
39061 for profiling a function entry. */
39062 void
39064 {
39069 {
39070 #ifndef NO_PROFILE_COUNTERS
39072 #endif
39076 else
39078 }
39080 {
39081 #ifndef NO_PROFILE_COUNTERS
39084 #endif
39086 }
39087 else
39088 {
39089 #ifndef NO_PROFILE_COUNTERS
39092 #endif
39094 }
39095 }
39097 /* We don't have exact information about the insn sizes, but we may assume
39098 quite safely that we are informed about all 1 byte insns and memory
39099 address sizes. This is enough to eliminate unnecessary padding in
39100 99% of cases. */
39102 static int
39104 {
39110 /* Discard alignments we've emit and jump instructions. */
39115 /* Important case - calls are always 5 bytes.
39116 It is common to have many calls in the row. */
39125 /* For normal instructions we rely on get_attr_length being exact,
39126 with a few exceptions. */
39128 {
39132 {
39142 /* Otherwise trust get_attr_length. */
39144 }
39149 }
39152 else
39154 }
39156 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39158 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39159 window. */
39161 static void
39163 {
39168 /* Look for all minimal intervals of instructions containing 4 jumps.
39169 The intervals are bounded by START and INSN. NBYTES is the total
39170 size of instructions in the interval including INSN and not including
39171 START. When the NBYTES is smaller than 16 bytes, it is possible
39172 that the end of START and INSN ends up in the same 16byte page.
39174 The smallest offset in the page INSN can start is the case where START
39175 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39176 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39178 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39179 have to, control transfer to label(s) can be performed through other
39180 means, and also we estimate minimum length of all asm stmts as 0. */
39182 {
39186 {
39192 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39193 already in the current 16 byte page, because otherwise
39194 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39195 bytes to reach 16 byte boundary. */
39203 {
39205 {
39210 else
39213 }
39214 }
39216 }
39225 njumps++;
39226 else
39230 {
39235 else
39238 }
39245 {
39252 }
39253 }
39254 }
39255 #endif
39257 /* AMD Athlon works faster
39258 when RET is not destination of conditional jump or directly preceded
39259 by other jump instruction. We avoid the penalty by inserting NOP just
39260 before the RET instructions in such cases. */
39261 static void
39263 {
39264 edge e;
39265 edge_iterator ei;
39268 {
39281 {
39282 edge e;
39283 edge_iterator ei;
39288 {
39291 }
39292 }
39294 {
39300 /* Empty functions get branch mispredict even when
39301 the jump destination is not visible to us. */
39304 }
39306 {
39309 }
39310 }
39311 }
39313 /* Count the minimum number of instructions in BB. Return 4 if the
39314 number of instructions >= 4. */
39316 static int
39318 {
39322 /* Count number of instructions in this block. Return 4 if the number
39323 of instructions >= 4. */
39325 {
39326 /* Only happen in exit blocks. */
39334 {
39335 insn_count++;
39338 }
39339 }
39342 }
39345 /* Count the minimum number of instructions in code path in BB.
39346 Return 4 if the number of instructions >= 4. */
39348 static int
39350 {
39351 edge e;
39352 edge_iterator ei;
39355 /* Only bother counting instructions along paths with no
39356 more than 2 basic blocks between entry and exit. Given
39357 that BB has an edge to exit, determine if a predecessor
39358 of BB has an edge from entry. If so, compute the number
39359 of instructions in the predecessor block. If there
39360 happen to be multiple such blocks, compute the minimum. */
39363 {
39364 edge prev_e;
39365 edge_iterator prev_ei;
39368 {
39371 }
39373 {
39375 {
39380 }
39381 }
39382 }
39388 }
39390 /* Pad short function to 4 instructions. */
39392 static void
39394 {
39395 edge e;
39396 edge_iterator ei;
39399 {
39402 {
39405 /* Pad short function. */
39407 {
39410 /* Find epilogue. */
39419 /* Two NOPs count as one instruction. */
39422 }
39423 }
39424 }
39425 }
39427 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39428 the epilogue, the Windows system unwinder will apply epilogue logic and
39429 produce incorrect offsets. This can be avoided by adding a nop between
39430 the last insn that can throw and the first insn of the epilogue. */
39432 static void
39434 {
39435 edge e;
39436 edge_iterator ei;
39439 {
39442 /* Find the beginning of the epilogue. */
39449 /* We only care about preceding insns that can throw. */
39454 /* Do not separate calls from their debug information. */
39460 else
39464 }
39465 }
39467 /* Implement machine specific optimizations. We implement padding of returns
39468 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39469 static void
39471 {
39472 /* We are freeing block_for_insn in the toplev to keep compatibility
39473 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39480 {
39485 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39488 #endif
39489 }
39490 }
39492 /* Return nonzero when QImode register that must be represented via REX prefix
39493 is used. */
39494 bool
39496 {
39504 }
39506 /* Return nonzero when P points to register encoded via REX prefix.
39507 Called via for_each_rtx. */
39508 static int
39510 {
39516 }
39518 /* Return true when INSN mentions register that must be encoded using REX
39519 prefix. */
39520 bool
39522 {
39525 }
39527 /* If profitable, negate (without causing overflow) integer constant
39528 of mode MODE at location LOC. Return true in this case. */
39529 bool
39531 {
39532 HOST_WIDE_INT val;
39538 {
39540 /* DImode x86_64 constants must fit in 32 bits. */
39553 }
39555 /* Avoid overflows. */
39561 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39562 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39565 {
39568 }
39571 }
39573 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39574 optabs would emit if we didn't have TFmode patterns. */
39576 void
39578 {
39613 }
39614 \f
39615 /* AVX512F does support 64-byte integer vector operations,
39616 thus the longest vector we are faced with is V64QImode. */
39617 #define MAX_VECT_LEN 64
39619 struct expand_vec_perm_d
39620 {
39627 };
39633 /* Get a vector mode of the same size as the original but with elements
39634 twice as wide. This is only guaranteed to apply to integral vectors. */
39638 {
39639 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39644 }
39646 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39647 fill target with val via vec_duplicate. */
39649 static bool
39651 {
39654 rtx dup;
39656 /* First attempt to recognize VAL as-is. */
39660 {
39662 /* If that fails, force VAL into a register. */
39673 }
39675 }
39677 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39678 with all elements equal to VAR. Return true if successful. */
39680 static bool
39683 {
39687 {
39692 /* FALLTHRU */
39712 {
39713 rtx x;
39720 }
39730 {
39734 permute:
39742 /* Extend to SImode using a paradoxical SUBREG. */
39746 /* Insert the SImode value as low element of a V4SImode vector. */
39755 }
39763 widen:
39764 /* Replicate the value once into the next wider mode and recurse. */
39765 {
39767 rtx x;
39784 }
39788 {
39797 }
39802 }
39803 }
39805 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39806 whose ONE_VAR element is VAR, and other elements are zero. Return true
39807 if successful. */
39809 static bool
39812 {
39814 rtx new_target;
39819 {
39821 /* For SSE4.1, we normally use vector set. But if the second
39822 element is zero and inter-unit moves are OK, we use movq
39823 instead. */
39825 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39847 /* Use ix86_expand_vector_set in 64bit mode only. */
39852 }
39855 {
39860 }
39863 {
39868 /* FALLTHRU */
39883 else
39890 {
39891 /* We need to shuffle the value to the correct position, so
39892 create a new pseudo to store the intermediate result. */
39894 /* With SSE2, we can use the integer shuffle insns. */
39896 {
39898 const1_rtx,
39905 }
39907 /* Otherwise convert the intermediate result to V4SFmode and
39908 use the SSE1 shuffle instructions. */
39910 {
39913 }
39914 else
39918 const1_rtx,
39927 }
39942 widen:
39946 /* Zero extend the variable element to SImode and recurse. */
39959 }
39960 }
39962 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39963 consisting of the values in VALS. It is known that all elements
39964 except ONE_VAR are constants. Return true if successful. */
39966 static bool
39969 {
39979 {
39984 /* For the two element vectors, it's just as easy to use
39985 the general case. */
39989 /* Use ix86_expand_vector_set in 64bit mode only. */
40011 widen:
40012 /* There's no way to set one QImode entry easily. Combine
40013 the variable value with its adjacent constant value, and
40014 promote to an HImode set. */
40017 {
40022 }
40023 else
40024 {
40027 }
40041 }
40046 }
40048 /* A subroutine of ix86_expand_vector_init_general. Use vector
40049 concatenate to handle the most general case: all values variable,
40050 and none identical. */
40052 static void
40055 {
40058 rtvec v;
40062 {
40065 {
40110 }
40123 {
40138 }
40143 {
40162 }
40167 {
40180 }
40183 half:
40184 /* FIXME: We process inputs backward to help RA. PR 36222. */
40188 {
40193 }
40197 {
40201 {
40205 }
40208 {
40212 }
40215 }
40217 {
40220 {
40224 }
40227 }
40228 else
40234 }
40235 }
40237 /* A subroutine of ix86_expand_vector_init_general. Use vector
40238 interleave to handle the most general case: all values variable,
40239 and none identical. */
40241 static void
40244 {
40253 {
40274 }
40277 {
40278 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40282 /* Insert the SImode value as low element of V4SImode vector. */
40286 op0),
40288 const1_rtx);
40291 /* Cast the V4SImode vector back to a vector in orignal mode. */
40295 /* Load even elements into the second position. */
40299 const1_rtx));
40301 /* Cast vector to FIRST_IMODE vector. */
40304 }
40306 /* Interleave low FIRST_IMODE vectors. */
40308 {
40312 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40315 }
40317 /* Interleave low SECOND_IMODE vectors. */
40319 {
40322 {
40327 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40328 vector. */
40331 }
40334 /* FALLTHRU */
40341 /* Cast the SECOND_IMODE vector back to a vector on original
40342 mode. */
40349 }
40350 }
40352 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40353 all values variable, and none identical. */
40355 static void
40358 {
40364 {
40369 /* FALLTHRU */
40397 half:
40414 /* FALLTHRU */
40420 /* Don't use ix86_expand_vector_init_interleave if we can't
40421 move from GPR to SSE register directly. */
40437 }
40439 {
40451 {
40455 {
40461 else
40462 {
40467 }
40468 }
40471 }
40476 {
40482 }
40484 {
40490 }
40491 else
40493 }
40494 }
40496 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40497 instructions unless MMX_OK is true. */
40499 void
40501 {
40508 rtx x;
40511 {
40521 }
40523 /* Constants are best loaded from the constant pool. */
40525 {
40528 }
40530 /* If all values are identical, broadcast the value. */
40536 /* Values where only one field is non-constant are best loaded from
40537 the pool and overwritten via move later. */
40539 {
40543 one_var))
40548 }
40551 }
40553 void
40555 {
40560 rtx tmp;
40562 = {
40569 };
40571 = {
40578 };
40582 {
40586 {
40591 else
40595 }
40607 else
40613 {
40616 /* For the two element vectors, we implement a VEC_CONCAT with
40617 the extraction of the other element. */
40624 else
40629 }
40638 {
40644 /* tmp = target = A B C D */
40646 /* target = A A B B */
40648 /* target = X A B B */
40650 /* target = A X C D */
40657 /* tmp = target = A B C D */
40659 /* tmp = X B C D */
40661 /* target = A B X D */
40668 /* tmp = target = A B C D */
40670 /* tmp = X B C D */
40672 /* target = A B X D */
40680 }
40688 /* Element 0 handled by vec_merge below. */
40690 {
40693 }
40696 {
40697 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40698 store into element 0, then shuffle them back. */
40715 }
40716 else
40717 {
40718 /* For SSE1, we have to reuse the V4SF code. */
40722 }
40775 half:
40776 /* Compute offset. */
40782 /* Extract the half. */
40786 /* Put val in tmp at elt. */
40789 /* Put it back. */
40795 }
40798 {
40802 }
40803 else
40804 {
40813 }
40814 }
40816 void
40818 {
40822 rtx tmp;
40825 {
40830 /* FALLTHRU */
40843 {
40863 }
40875 {
40877 {
40897 }
40901 }
40902 else
40903 {
40904 /* For SSE1, we have to reuse the V4SF code. */
40908 }
40924 {
40928 else
40932 }
40937 {
40941 else
40945 }
40950 {
40954 else
40958 }
40963 {
40967 else
40971 }
40976 {
40980 else
40984 }
40989 {
40993 else
40997 }
41004 else
41013 else
41022 else
41031 else
41037 /* ??? Could extract the appropriate HImode element and shift. */
41040 }
41043 {
41047 /* Let the rtl optimizers know about the zero extension performed. */
41049 {
41052 }
41055 }
41056 else
41057 {
41064 }
41065 }
41067 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
41068 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
41069 The upper bits of DEST are undefined, though they shouldn't cause
41070 exceptions (some bits from src or all zeros are ok). */
41072 static void
41074 {
41077 {
41081 else
41099 else
41106 else
41114 {
41119 const1_rtx);
41120 }
41121 else
41122 {
41126 }
41146 else
41168 }
41172 }
41174 /* Expand a vector reduction. FN is the binary pattern to reduce;
41175 DEST is the destination; IN is the input vector. */
41177 void
41179 {
41184 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41188 {
41191 }
41196 {
41201 else
41205 }
41206 }
41207 \f
41208 /* Target hook for scalar_mode_supported_p. */
41209 static bool
41211 {
41216 else
41218 }
41220 /* Implements target hook vector_mode_supported_p. */
41221 static bool
41223 {
41237 }
41239 /* Target hook for c_mode_for_suffix. */
41240 static enum machine_mode
41242 {
41249 }
41251 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41253 We do this in the new i386 backend to maintain source compatibility
41254 with the old cc0-based compiler. */
41256 static tree
41258 {
41260 clobbers);
41262 clobbers);
41264 }
41266 /* Implements target vector targetm.asm.encode_section_info. */
41268 static void ATTRIBUTE_UNUSED
41270 {
41277 }
41279 /* Worker function for REVERSE_CONDITION. */
41281 enum rtx_code
41283 {
41287 }
41289 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41290 to OPERANDS[0]. */
41294 {
41296 {
41299 {
41303 }
41307 }
41309 {
41313 else
41314 {
41315 /* There is no non-popping store to memory for XFmode.
41316 So if we need one, follow the store with a load. */
41319 else
41321 }
41322 }
41323 else
41325 }
41327 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41328 FP status register is set. */
41330 void
41332 {
41334 rtx temp;
41339 {
41344 }
41345 else
41346 {
41351 }
41355 pc_rtx);
41360 }
41362 /* Output code to perform a log1p XFmode calculation. */
41365 {
41371 rtx test;
41377 XFmode));
41391 }
41393 /* Emit code for round calculation. */
41395 {
41402 rtx insn;
41407 {
41419 }
41422 {
41443 }
41451 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41453 /* scratch = fxam(op1) */
41456 UNSPEC_FXAM)));
41457 /* e1 = fabs(op1) */
41460 /* e2 = e1 + 0.5 */
41465 /* res = floor(e2) */
41467 {
41472 }
41473 else
41477 {
41480 {
41487 UNSPEC_TRUNC_NOOP)));
41488 }
41504 }
41506 /* flags = signbit(a) */
41509 /* if (flags) then res = -res */
41513 pc_rtx);
41524 }
41526 /* Output code to perform a Newton-Rhapson approximation of a single precision
41527 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41530 {
41538 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41542 /* x0 = rcp(b) estimate */
41546 UNSPEC_RCP14)));
41547 else
41550 UNSPEC_RCP)));
41552 /* e0 = x0 * b */
41556 /* e0 = x0 * e0 */
41560 /* e1 = x0 + x0 */
41564 /* x1 = e1 - e0 */
41568 /* res = a * x1 */
41571 }
41573 /* Output code to perform a Newton-Rhapson approximation of a
41574 single precision floating point [reciprocal] square root. */
41578 {
41580 REAL_VALUE_TYPE r;
41597 {
41600 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41603 }
41605 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41606 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41610 /* x0 = rsqrt(a) estimate */
41613 unspec)));
41615 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41617 {
41625 /* Handle masked compare. */
41627 {
41629 /* Imm value 0x4 corresponds to not-equal comparison. */
41632 }
41633 else
41634 {
41640 }
41641 }
41643 /* e0 = x0 * a */
41646 /* e1 = e0 * x0 */
41650 /* e2 = e1 - 3. */
41657 /* e3 = -.5 * x0 */
41660 else
41661 /* e3 = -.5 * e0 */
41664 /* ret = e2 * e3 */
41667 }
41669 #ifdef TARGET_SOLARIS
41670 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41672 static void
41674 tree decl)
41675 {
41676 /* With Binutils 2.15, the "@unwind" marker must be specified on
41677 every occurrence of the ".eh_frame" section, not just the first
41678 one. */
41681 {
41685 }
41687 #ifndef USE_GAS
41689 {
41692 }
41693 #endif
41696 }
41699 /* Return the mangling of TYPE if it is an extended fundamental type. */
41703 {
41711 {
41713 /* __float128 is "g". */
41716 /* "long double" or __float80 is "e". */
41720 }
41721 }
41723 /* For 32-bit code we can save PIC register setup by using
41724 __stack_chk_fail_local hidden function instead of calling
41725 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41726 register, so it is better to call __stack_chk_fail directly. */
41728 static tree ATTRIBUTE_UNUSED
41730 {
41731 return TARGET_64BIT
41734 }
41736 /* Select a format to encode pointers in exception handling data. CODE
41737 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41738 true if the symbol may be affected by dynamic relocations.
41740 ??? All x86 object file formats are capable of representing this.
41741 After all, the relocation needed is the same as for the call insn.
41742 Whether or not a particular assembler allows us to enter such, I
41743 guess we'll have to see. */
41744 int
41746 {
41748 {
41755 }
41760 }
41761 \f
41762 /* Expand copysign from SIGN to the positive value ABS_VALUE
41763 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41764 the sign-bit. */
41765 static void
41767 {
41771 {
41778 else
41783 {
41784 /* We need to generate a scalar mode mask in this case. */
41789 }
41790 }
41791 else
41797 }
41799 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41800 mask for masking out the sign-bit is stored in *SMASK, if that is
41801 non-null. */
41802 static rtx
41804 {
41813 else
41817 {
41818 /* We need to generate a scalar mode mask in this case. */
41823 }
41831 }
41833 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41834 swapping the operands if SWAP_OPERANDS is true. The expanded
41835 code is a forward jump to a newly created label in case the
41836 comparison is true. The generated label rtx is returned. */
41840 {
41843 rtx tmp;
41846 {
41850 }
41863 }
41865 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41866 using comparison code CODE. Operands are swapped for the comparison if
41867 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41868 static rtx
41871 {
41877 {
41881 }
41888 }
41890 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41891 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41892 static rtx
41894 {
41895 REAL_VALUE_TYPE TWO52r;
41896 rtx TWO52;
41903 }
41905 /* Expand SSE sequence for computing lround from OP1 storing
41906 into OP0. */
41907 void
41909 {
41910 /* C code for the stuff we're doing below:
41911 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41912 return (long)tmp;
41913 */
41917 rtx adj;
41919 /* load nextafter (0.5, 0.0) */
41924 /* adj = copysign (0.5, op1) */
41928 /* adj = op1 + adj */
41931 /* op0 = (imode)adj */
41933 }
41935 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41936 into OPERAND0. */
41937 void
41939 {
41940 /* C code for the stuff we're doing below (for do_floor):
41941 xi = (long)op1;
41942 xi -= (double)xi > op1 ? 1 : 0;
41943 return xi;
41944 */
41950 /* reg = (long)op1 */
41954 /* freg = (double)reg */
41958 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41969 }
41971 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41972 result in OPERAND0. */
41973 void
41975 {
41976 /* C code for the stuff we're doing below:
41977 xa = fabs (operand1);
41978 if (!isless (xa, 2**52))
41979 return operand1;
41980 xa = xa + 2**52 - 2**52;
41981 return copysign (xa, operand1);
41982 */
41990 /* xa = abs (operand1) */
41993 /* if (!isless (xa, TWO52)) goto label; */
42006 }
42008 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
42009 into OPERAND0. */
42010 void
42012 {
42013 /* C code for the stuff we expand below.
42014 double xa = fabs (x), x2;
42015 if (!isless (xa, TWO52))
42016 return x;
42017 xa = xa + TWO52 - TWO52;
42018 x2 = copysign (xa, x);
42019 Compensate. Floor:
42020 if (x2 > x)
42021 x2 -= 1;
42022 Compensate. Ceil:
42023 if (x2 < x)
42024 x2 -= -1;
42025 return x2;
42026 */
42033 /* Temporary for holding the result, initialized to the input
42034 operand to ease control flow. */
42038 /* xa = abs (operand1) */
42041 /* if (!isless (xa, TWO52)) goto label; */
42044 /* xa = xa + TWO52 - TWO52; */
42048 /* xa = copysign (xa, operand1) */
42051 /* generate 1.0 or -1.0 */
42056 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42060 /* We always need to subtract here to preserve signed zero. */
42069 }
42071 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
42072 into OPERAND0. */
42073 void
42075 {
42076 /* C code for the stuff we expand below.
42077 double xa = fabs (x), x2;
42078 if (!isless (xa, TWO52))
42079 return x;
42080 x2 = (double)(long)x;
42081 Compensate. Floor:
42082 if (x2 > x)
42083 x2 -= 1;
42084 Compensate. Ceil:
42085 if (x2 < x)
42086 x2 += 1;
42087 if (HONOR_SIGNED_ZEROS (mode))
42088 return copysign (x2, x);
42089 return x2;
42090 */
42097 /* Temporary for holding the result, initialized to the input
42098 operand to ease control flow. */
42102 /* xa = abs (operand1) */
42105 /* if (!isless (xa, TWO52)) goto label; */
42108 /* xa = (double)(long)x */
42113 /* generate 1.0 */
42116 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42131 }
42133 /* Expand SSE sequence for computing round from OPERAND1 storing
42134 into OPERAND0. Sequence that works without relying on DImode truncation
42135 via cvttsd2siq that is only available on 64bit targets. */
42136 void
42138 {
42139 /* C code for the stuff we expand below.
42140 double xa = fabs (x), xa2, x2;
42141 if (!isless (xa, TWO52))
42142 return x;
42143 Using the absolute value and copying back sign makes
42144 -0.0 -> -0.0 correct.
42145 xa2 = xa + TWO52 - TWO52;
42146 Compensate.
42147 dxa = xa2 - xa;
42148 if (dxa <= -0.5)
42149 xa2 += 1;
42150 else if (dxa > 0.5)
42151 xa2 -= 1;
42152 x2 = copysign (xa2, x);
42153 return x2;
42154 */
42161 /* Temporary for holding the result, initialized to the input
42162 operand to ease control flow. */
42166 /* xa = abs (operand1) */
42169 /* if (!isless (xa, TWO52)) goto label; */
42172 /* xa2 = xa + TWO52 - TWO52; */
42176 /* dxa = xa2 - xa; */
42179 /* generate 0.5, 1.0 and -0.5 */
42185 /* Compensate. */
42187 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42192 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42198 /* res = copysign (xa2, operand1) */
42205 }
42207 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42208 into OPERAND0. */
42209 void
42211 {
42212 /* C code for SSE variant we expand below.
42213 double xa = fabs (x), x2;
42214 if (!isless (xa, TWO52))
42215 return x;
42216 x2 = (double)(long)x;
42217 if (HONOR_SIGNED_ZEROS (mode))
42218 return copysign (x2, x);
42219 return x2;
42220 */
42227 /* Temporary for holding the result, initialized to the input
42228 operand to ease control flow. */
42232 /* xa = abs (operand1) */
42235 /* if (!isless (xa, TWO52)) goto label; */
42238 /* x = (double)(long)x */
42250 }
42252 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42253 into OPERAND0. */
42254 void
42256 {
42261 /* C code for SSE variant we expand below.
42262 double xa = fabs (x), x2;
42263 if (!isless (xa, TWO52))
42264 return x;
42265 xa2 = xa + TWO52 - TWO52;
42266 Compensate:
42267 if (xa2 > xa)
42268 xa2 -= 1.0;
42269 x2 = copysign (xa2, x);
42270 return x2;
42271 */
42275 /* Temporary for holding the result, initialized to the input
42276 operand to ease control flow. */
42280 /* xa = abs (operand1) */
42283 /* if (!isless (xa, TWO52)) goto label; */
42286 /* res = xa + TWO52 - TWO52; */
42291 /* generate 1.0 */
42294 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42302 /* res = copysign (res, operand1) */
42309 }
42311 /* Expand SSE sequence for computing round from OPERAND1 storing
42312 into OPERAND0. */
42313 void
42315 {
42316 /* C code for the stuff we're doing below:
42317 double xa = fabs (x);
42318 if (!isless (xa, TWO52))
42319 return x;
42320 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42321 return copysign (xa, x);
42322 */
42329 /* Temporary for holding the result, initialized to the input
42330 operand to ease control flow. */
42338 /* load nextafter (0.5, 0.0) */
42343 /* xa = xa + 0.5 */
42347 /* xa = (double)(int64_t)xa */
42352 /* res = copysign (xa, operand1) */
42359 }
42361 /* Expand SSE sequence for computing round
42362 from OP1 storing into OP0 using sse4 round insn. */
42363 void
42365 {
42374 {
42385 }
42387 /* round (a) = trunc (a + copysign (0.5, a)) */
42389 /* load nextafter (0.5, 0.0) */
42395 /* e1 = copysign (0.5, op1) */
42399 /* e2 = op1 + e1 */
42402 /* res = trunc (e2) */
42407 }
42408 \f
42410 /* Table of valid machine attributes. */
42412 {
42413 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42414 affects_type_identity } */
42415 /* Stdcall attribute says callee is responsible for popping arguments
42416 if they are not variable. */
42419 /* Fastcall attribute says callee is responsible for popping arguments
42420 if they are not variable. */
42423 /* Thiscall attribute says callee is responsible for popping arguments
42424 if they are not variable. */
42427 /* Cdecl attribute says the callee is a normal C declaration */
42430 /* Regparm attribute specifies how many integer arguments are to be
42431 passed in registers. */
42434 /* Sseregparm attribute says we are using x86_64 calling conventions
42435 for FP arguments. */
42438 /* The transactional memory builtins are implicitly regparm or fastcall
42439 depending on the ABI. Override the generic do-nothing attribute that
42440 these builtins were declared with. */
42443 /* force_align_arg_pointer says this function realigns the stack at entry. */
42446 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42451 #endif
42456 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42457 SUBTARGET_ATTRIBUTE_TABLE,
42458 #endif
42459 /* ms_abi and sysv_abi calling convention function attributes. */
42466 /* End element. */
42468 };
42470 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42471 static int
42474 {
42478 {
42523 }
42524 }
42526 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42527 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42528 insn every time. */
42532 /* Initialize vselect_insn. */
42534 static void
42536 {
42538 rtx x;
42549 }
42551 /* Construct (set target (vec_select op0 (parallel perm))) and
42552 return true if that's a valid instruction in the active ISA. */
42554 static bool
42557 {
42583 }
42585 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42587 static bool
42591 {
42593 rtx x;
42608 }
42610 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42611 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42613 static bool
42615 {
42624 ;
42626 ;
42628 ;
42629 else
42632 /* This is a blend, not a permute. Elements must stay in their
42633 respective lanes. */
42635 {
42639 }
42644 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42645 decision should be extracted elsewhere, so that we only try that
42646 sequence once all budget==3 options have been tried. */
42653 {
42677 /* See if bytes move in pairs so we can use pblendw with
42678 an immediate argument, rather than pblendvb with a vector
42679 argument. */
42682 {
42683 use_pblendvb:
42687 finish_pblendvb:
42693 else
42698 }
42703 /* FALLTHRU */
42705 do_subreg:
42712 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42716 /* See if bytes move in quadruplets. If yes, vpblendd
42717 with immediate can be used. */
42722 {
42723 /* See if bytes move the same in both lanes. If yes,
42724 vpblendw with immediate can be used. */
42729 /* Use vpblendw. */
42734 }
42736 /* Use vpblendd. */
42743 /* See if words move in pairs. If yes, vpblendd can be used. */
42748 {
42749 /* See if words move the same in both lanes. If not,
42750 vpblendvb must be used. */
42753 {
42754 /* Use vpblendvb. */
42764 }
42766 /* Use vpblendw. */
42770 }
42772 /* Use vpblendd. */
42779 /* Use vpblendd. */
42787 }
42789 /* This matches five different patterns with the different modes. */
42797 }
42799 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42800 in terms of the variable form of vpermilps.
42802 Note that we will have already failed the immediate input vpermilps,
42803 which requires that the high and low part shuffle be identical; the
42804 variable form doesn't require that. */
42806 static bool
42808 {
42815 /* We can only permute within the 128-bit lane. */
42817 {
42821 }
42827 {
42830 /* Within each 128-bit lane, the elements of op0 are numbered
42831 from 0 and the elements of op1 are numbered from 4. */
42838 }
42845 }
42847 /* Return true if permutation D can be performed as VMODE permutation
42848 instead. */
42850 static bool
42852 {
42867 else
42873 }
42875 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42876 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42878 static bool
42880 {
42889 {
42891 {
42894 {
42898 /* Use vperm2i128 insn. The pattern uses
42899 V4DImode instead of V2TImode. */
42912 }
42914 }
42915 }
42916 else
42917 {
42919 {
42922 }
42924 {
42928 /* V4DImode should be already handled through
42929 expand_vselect by vpermq instruction. */
42936 {
42937 /* First see if vpermq can be used for
42938 V8SImode/V16HImode/V32QImode. */
42940 {
42948 {
42952 }
42954 }
42956 /* Next see if vpermd can be used. */
42959 }
42960 /* Or if vpermps can be used. */
42965 {
42966 /* vpshufb only works intra lanes, it is not
42967 possible to shuffle bytes in between the lanes. */
42971 }
42972 }
42973 else
42975 }
42983 else
42984 {
42990 else
42994 {
42998 }
42999 }
43010 {
43017 else
43019 }
43020 else
43021 {
43024 }
43029 }
43031 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
43032 in a single instruction. */
43034 static bool
43036 {
43040 /* Check plain VEC_SELECT first, because AVX has instructions that could
43041 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
43042 input where SEL+CONCAT may not. */
43044 {
43050 {
43056 }
43059 {
43063 }
43065 {
43066 /* Use vpbroadcast{b,w,d}. */
43069 {
43088 /* For other modes prefer other shuffles this function creates. */
43090 }
43092 {
43096 }
43097 }
43102 /* There are plenty of patterns in sse.md that are written for
43103 SEL+CONCAT and are not replicated for a single op. Perhaps
43104 that should be changed, to avoid the nastiness here. */
43106 /* Recognize interleave style patterns, which means incrementing
43107 every other permutation operand. */
43109 {
43112 }
43117 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
43119 {
43121 {
43126 }
43131 }
43132 }
43134 /* Finally, try the fully general two operand permute. */
43139 /* Recognize interleave style patterns with reversed operands. */
43141 {
43143 {
43147 else
43150 }
43155 }
43157 /* Try the SSE4.1 blend variable merge instructions. */
43161 /* Try one of the AVX vpermil variable permutations. */
43165 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43166 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43170 /* Try the AVX512F vpermi2 instructions. */
43184 }
43186 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43187 in terms of a pair of pshuflw + pshufhw instructions. */
43189 static bool
43191 {
43199 /* The two permutations only operate in 64-bit lanes. */
43210 /* Emit the pshuflw. */
43217 /* Emit the pshufhw. */
43225 }
43227 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43228 the permutation using the SSSE3 palignr instruction. This succeeds
43229 when all of the elements in PERM fit within one vector and we merely
43230 need to shift them down so that a single vector permutation has a
43231 chance to succeed. */
43233 static bool
43235 {
43242 /* Even with AVX, palignr only operates on 128-bit vectors. */
43248 {
43254 }
43258 /* Given that we have SSSE3, we know we'll be able to implement the
43259 single operand permutation after the palignr with pshufb. */
43274 {
43279 }
43281 /* Test for the degenerate case where the alignment by itself
43282 produces the desired permutation. */
43284 {
43287 }
43293 }
43295 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
43296 the permutation using the SSE4_1 pblendv instruction. Potentially
43297 reduces permutaion from 2 pshufb and or to 1 pshufb and pblendv. */
43299 static bool
43301 {
43307 /* Use the same checks as in expand_vec_perm_blend, but skipping
43308 AVX and AVX2 as they require more than 2 instructions. */
43312 ;
43313 else
43316 /* Figure out where permutation elements stay not in their
43317 respective lanes. */
43319 {
43323 }
43324 /* We can pblend the part where elements stay not in their
43325 respective lanes only when these elements are all in one
43326 half of a permutation.
43327 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
43328 lanes, but both 8 and 9 >= 8
43329 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
43330 respective lanes and 8 >= 8, but 2 not. */
43336 /* First we apply one operand permutation to the part where
43337 elements stay not in their respective lanes. */
43341 else
43351 /* Next we put permuted elements into their positions. */
43355 else
43365 }
43369 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43370 a two vector permutation into a single vector permutation by using
43371 an interleave operation to merge the vectors. */
43373 static bool
43375 {
43384 {
43387 }
43389 {
43392 /* For 32-byte modes allow even d->one_operand_p.
43393 The lack of cross-lane shuffling in some instructions
43394 might prevent a single insn shuffle. */
43397 /* If expand_vec_perm_interleave3 can expand this into
43398 a 3 insn sequence, give up and let it be expanded as
43399 3 insn sequence. While that is one insn longer,
43400 it doesn't need a memory operand and in the common
43401 case that both interleave low and high permutations
43402 with the same operands are adjacent needs 4 insns
43403 for both after CSE. */
43406 }
43407 else
43410 /* Examine from whence the elements come. */
43419 {
43422 /* Split the two input vectors into 4 halves. */
43428 /* If the elements from the low halves use interleave low, and similarly
43429 for interleave high. If the elements are from mis-matched halves, we
43430 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43432 {
43433 /* punpckl* */
43435 {
43440 }
43443 }
43445 {
43446 /* punpckh* */
43448 {
43453 }
43456 }
43458 {
43459 /* shufps */
43461 {
43466 }
43468 {
43469 /* shufpd */
43474 }
43475 }
43477 {
43478 /* shufps */
43480 {
43485 }
43487 {
43488 /* shufpd */
43493 }
43494 }
43495 else
43497 }
43498 else
43499 {
43504 /* Split the two input vectors into 8 quarters. */
43510 {
43513 }
43516 {
43520 }
43522 {
43525 }
43528 {
43530 {
43531 /* Attempt to increase the likelihood that dfinal
43532 shuffle will be intra-lane. */
43536 }
43538 /* vperm2f128 or vperm2i128. */
43540 {
43545 }
43550 {
43554 {
43557 }
43558 }
43559 }
43564 {
43565 /* vpunpckl* */
43567 {
43576 }
43577 }
43580 {
43581 /* vpunpckh* */
43583 {
43592 }
43593 }
43594 else
43596 }
43598 /* Use the remapping array set up above to move the elements from their
43599 swizzled locations into their final destinations. */
43602 {
43605 /* If same_halves is true, both halves of the remapped vector are the
43606 same. Avoid cross-lane accesses if possible. */
43608 {
43611 }
43612 else
43614 }
43616 {
43619 }
43623 /* Test if the final remap can be done with a single insn. For V4SFmode or
43624 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43637 {
43640 }
43647 }
43649 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43650 a single vector cross-lane permutation into vpermq followed
43651 by any of the single insn permutations. */
43653 static bool
43655 {
43669 {
43672 }
43675 {
43680 }
43693 {
43700 }
43707 {
43712 ;
43715 else
43717 }
43726 }
43728 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43729 a vector permutation using two instructions, vperm2f128 resp.
43730 vperm2i128 followed by any single in-lane permutation. */
43732 static bool
43734 {
43748 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43749 immediate. For perm < 16 the second permutation uses
43750 d->op0 as first operand, for perm >= 16 it uses d->op1
43751 as first operand. The second operand is the result of
43752 vperm2[fi]128. */
43754 {
43755 /* Ignore permutations which do not move anything cross-lane. */
43757 {
43758 /* The second shuffle for e.g. V4DFmode has
43759 0123 and ABCD operands.
43760 Ignore AB23, as 23 is already in the second lane
43761 of the first operand. */
43763 /* And 01CD, as 01 is in the first lane of the first
43764 operand. */
43766 /* And 4567, as then the vperm2[fi]128 doesn't change
43767 anything on the original 4567 second operand. */
43769 }
43770 else
43771 {
43772 /* The second shuffle for e.g. V4DFmode has
43773 4567 and ABCD operands.
43774 Ignore AB67, as 67 is already in the second lane
43775 of the first operand. */
43777 /* And 45CD, as 45 is in the first lane of the first
43778 operand. */
43780 /* And 0123, as then the vperm2[fi]128 doesn't change
43781 anything on the original 0123 first operand. */
43783 }
43786 {
43792 else
43794 }
43797 {
43801 }
43802 else
43806 {
43810 /* Found a usable second shuffle. dfirst will be
43811 vperm2f128 on d->op0 and d->op1. */
43822 /* And dsecond is some single insn shuffle, taking
43823 d->op0 and result of vperm2f128 (if perm < 16) or
43824 d->op1 and result of vperm2f128 (otherwise). */
43833 }
43835 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43838 }
43841 }
43843 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43844 a two vector permutation using 2 intra-lane interleave insns
43845 and cross-lane shuffle for 32-byte vectors. */
43847 static bool
43849 {
43856 ;
43858 ;
43859 else
43874 {
43878 else
43884 else
43890 else
43896 else
43902 else
43908 else
43913 }
43917 }
43919 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43920 a single vector permutation using a single intra-lane vector
43921 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43922 the non-swapped and swapped vectors together. */
43924 static bool
43926 {
43934 || TARGET_AVX2
43943 {
43950 }
43985 }
43987 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43988 permutation using two vperm2f128, followed by a vshufpd insn blending
43989 the two vectors together. */
43991 static bool
43993 {
44036 }
44038 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
44039 permutation with two pshufb insns and an ior. We should have already
44040 failed all two instruction sequences. */
44042 static bool
44044 {
44058 /* Generate two permutation masks. If the required element is within
44059 the given vector it is shuffled into the proper lane. If the required
44060 element is in the other vector, force a zero into the lane by setting
44061 bit 7 in the permutation mask. */
44064 {
44071 {
44074 }
44075 }
44099 }
44101 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
44102 with two vpshufb insns, vpermq and vpor. We should have already failed
44103 all two or three instruction sequences. */
44105 static bool
44107 {
44122 /* Generate two permutation masks. If the required element is within
44123 the same lane, it is shuffled in. If the required element from the
44124 other lane, force a zero by setting bit 7 in the permutation mask.
44125 In the other mask the mask has non-negative elements if element
44126 is requested from the other lane, but also moved to the other lane,
44127 so that the result of vpshufb can have the two V2TImode halves
44128 swapped. */
44131 {
44136 {
44139 }
44140 }
44149 /* Swap the 128-byte lanes of h into hp. */
44153 const1_rtx));
44170 }
44172 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
44173 and extract-odd permutations of two V32QImode and V16QImode operand
44174 with two vpshufb insns, vpor and vpermq. We should have already
44175 failed all two or three instruction sequences. */
44177 static bool
44179 {
44198 /* Generate two permutation masks. In the first permutation mask
44199 the first quarter will contain indexes for the first half
44200 of the op0, the second quarter will contain bit 7 set, third quarter
44201 will contain indexes for the second half of the op0 and the
44202 last quarter bit 7 set. In the second permutation mask
44203 the first quarter will contain bit 7 set, the second quarter
44204 indexes for the first half of the op1, the third quarter bit 7 set
44205 and last quarter indexes for the second half of the op1.
44206 I.e. the first mask e.g. for V32QImode extract even will be:
44207 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44208 (all values masked with 0xf except for -128) and second mask
44209 for extract even will be
44210 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44213 {
44219 {
44222 }
44223 }
44242 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44250 }
44252 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44253 and extract-odd permutations. */
44255 static bool
44257 {
44261 {
44268 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44272 /* Now an unpck[lh]pd will produce the result required. */
44275 else
44281 {
44290 /* Shuffle within the 128-bit lanes to produce:
44291 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44295 /* Shuffle the lanes around to produce:
44296 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44300 /* Shuffle within the 128-bit lanes to produce:
44301 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44304 /* Shuffle within the 128-bit lanes to produce:
44305 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44308 /* Shuffle the lanes around to produce:
44309 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44312 }
44319 /* These are always directly implementable by expand_vec_perm_1. */
44325 else
44326 {
44329 /* We need 2*log2(N)-1 operations to achieve odd/even
44330 with interleave. */
44339 else
44342 }
44348 else
44349 {
44363 else
44366 }
44375 {
44380 else
44385 {
44390 }
44392 }
44400 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44404 /* Now an vpunpck[lh]qdq will produce the result required. */
44407 else
44414 {
44419 else
44424 {
44429 }
44431 }
44442 /* Shuffle the lanes around into
44443 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44451 /* Swap the 2nd and 3rd position in each lane into
44452 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44458 /* Now an vpunpck[lh]qdq will produce
44459 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44463 else
44472 }
44475 }
44477 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44478 extract-even and extract-odd permutations. */
44480 static bool
44482 {
44494 }
44496 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44497 permutations. We assume that expand_vec_perm_1 has already failed. */
44499 static bool
44501 {
44509 {
44512 /* These are special-cased in sse.md so that we can optionally
44513 use the vbroadcast instruction. They expand to two insns
44514 if the input happens to be in a register. */
44521 /* These are always implementable using standard shuffle patterns. */
44526 /* These can be implemented via interleave. We save one insn by
44527 stopping once we have promoted to V4SImode and then use pshufd. */
44530 do
44531 {
44532 rtx dest;
44538 {
44542 }
44549 }
44564 /* For AVX2 broadcasts of the first element vpbroadcast* or
44565 vpermq should be used by expand_vec_perm_1. */
44571 }
44572 }
44574 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44575 broadcast permutations. */
44577 static bool
44579 {
44591 }
44593 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44594 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44595 all the shorter instruction sequences. */
44597 static bool
44599 {
44615 /* Generate 4 permutation masks. If the required element is within
44616 the same lane, it is shuffled in. If the required element from the
44617 other lane, force a zero by setting bit 7 in the permutation mask.
44618 In the other mask the mask has non-negative elements if element
44619 is requested from the other lane, but also moved to the other lane,
44620 so that the result of vpshufb can have the two V2TImode halves
44621 swapped. */
44624 {
44629 }
44635 {
44643 }
44646 {
44648 {
44651 }
44658 }
44660 /* Swap the 128-byte lanes of h[X]. */
44662 {
44668 const1_rtx));
44670 }
44673 {
44675 {
44678 }
44684 }
44687 {
44689 {
44693 }
44696 }
44706 }
44708 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44709 With all of the interface bits taken care of, perform the expansion
44710 in D and return true on success. */
44712 static bool
44714 {
44715 /* Try a single instruction expansion. */
44719 /* Try sequences of two instructions. */
44742 /* Try sequences of three instructions. */
44756 /* Try sequences of four instructions. */
44764 /* ??? Look for narrow permutations whose element orderings would
44765 allow the promotion to a wider mode. */
44767 /* ??? Look for sequences of interleave or a wider permute that place
44768 the data into the correct lanes for a half-vector shuffle like
44769 pshuf[lh]w or vpermilps. */
44771 /* ??? Look for sequences of interleave that produce the desired results.
44772 The combinatorics of punpck[lh] get pretty ugly... */
44777 /* Even longer sequences. */
44782 }
44784 /* If a permutation only uses one operand, make it clear. Returns true
44785 if the permutation references both operands. */
44787 static bool
44789 {
44797 {
44803 {
44806 }
44807 /* The elements of PERM do not suggest that only the first operand
44808 is used, but both operands are identical. Allow easier matching
44809 of the permutation by folding the permutation into the single
44810 input vector. */
44811 /* FALLTHRU */
44822 }
44825 }
44827 bool
44829 {
44834 rtx sel;
44851 {
44856 }
44863 /* If the selector says both arguments are needed, but the operands are the
44864 same, the above tried to expand with one_operand_p and flattened selector.
44865 If that didn't work, retry without one_operand_p; we succeeded with that
44866 during testing. */
44868 {
44872 }
44875 }
44877 /* Implement targetm.vectorize.vec_perm_const_ok. */
44879 static bool
44882 {
44891 /* Given sufficient ISA support we can just return true here
44892 for selected vector modes. */
44895 /* All implementable with a single vpermi2 insn. */
44898 {
44899 /* All implementable with a single vpperm insn. */
44902 /* All implementable with 2 pshufb + 1 ior. */
44905 /* All implementable with shufpd or unpck[lh]pd. */
44908 }
44910 /* Extract the values from the vector CST into the permutation
44911 array in D. */
44914 {
44918 }
44920 /* For all elements from second vector, fold the elements to first. */
44925 /* Check whether the mask can be applied to the vector type. */
44928 /* Implementable with shufps or pshufd. */
44932 /* Otherwise we have to go through the motions and see if we can
44933 figure out how to generate the requested permutation. */
44944 }
44946 void
44948 {
44963 /* We'll either be able to implement the permutation directly... */
44967 /* ... or we use the special-case patterns. */
44969 }
44971 static void
44973 {
44988 {
44991 }
44993 /* Note that for AVX this isn't one instruction. */
44996 }
44999 /* Expand a vector operation CODE for a V*QImode in terms of the
45000 same operation on V*HImode. */
45002 void
45004 {
45016 {
45029 }
45033 {
45035 /* Unpack data such that we've got a source byte in each low byte of
45036 each word. We don't care what goes into the high byte of each word.
45037 Rather than trying to get zero in there, most convenient is to let
45038 it be a copy of the low byte. */
45043 /* FALLTHRU */
45055 /* FALLTHRU */
45065 }
45067 /* Perform the operation. */
45074 /* Merge the data back into the right place. */
45084 {
45085 /* For SSE2, we used an full interleave, so the desired
45086 results are in the even elements. */
45089 }
45090 else
45091 {
45092 /* For AVX, the interleave used above was not cross-lane. So the
45093 extraction is evens but with the second and third quarter swapped.
45094 Happily, that is even one insn shorter than even extraction. */
45097 }
45104 }
45106 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
45107 if op is CONST_VECTOR with all odd elements equal to their
45108 preceding element. */
45110 static bool
45112 {
45122 }
45124 void
45127 {
45130 rtx x;
45138 /* We only play even/odd games with vectors of SImode. */
45141 /* If we're looking for the odd results, shift those members down to
45142 the even slots. For some cpus this is faster than a PSHUFD. */
45144 {
45145 /* For XOP use vpmacsdqh, but only for smult, as it is only
45146 signed. */
45148 {
45152 }
45163 }
45166 {
45169 else
45171 }
45173 {
45176 else
45178 }
45183 else
45184 {
45187 /* The easiest way to implement this without PMULDQ is to go through
45188 the motions as if we are performing a full 64-bit multiply. With
45189 the exception that we need to do less shuffling of the elements. */
45191 /* Compute the sign-extension, aka highparts, of the two operands. */
45197 /* Multiply LO(A) * HI(B), and vice-versa. */
45203 /* Multiply LO(A) * LO(B). */
45207 /* Combine and shift the highparts into place. */
45212 /* Combine high and low parts. */
45215 }
45217 }
45219 void
45222 {
45228 {
45233 {
45234 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45235 shuffle the elements once so that all elements are in the right
45236 place for immediate use: { A C B D }. */
45241 }
45242 else
45243 {
45244 /* Put the elements into place for the multiply. */
45248 }
45253 /* Shuffle the elements between the lanes. After this we
45254 have { A B E F | C D G H } for each operand. */
45264 /* Shuffle the elements within the lanes. After this we
45265 have { A A B B | C C D D } or { E E F F | G G H H }. */
45303 }
45304 }
45306 void
45308 {
45318 /* Move the results in element 2 down to element 1; we don't care
45319 what goes in elements 2 and 3. Then we can merge the parts
45320 back together with an interleave.
45322 Note that two other sequences were tried:
45323 (1) Use interleaves at the start instead of psrldq, which allows
45324 us to use a single shufps to merge things back at the end.
45325 (2) Use shufps here to combine the two vectors, then pshufd to
45326 put the elements in the correct order.
45327 In both cases the cost of the reformatting stall was too high
45328 and the overall sequence slower. */
45339 }
45341 void
45343 {
45348 {
45349 /* op1: A,B,C,D, op2: E,F,G,H */
45358 /* t1: B,A,D,C */
45365 /* t2: (B*E),(A*F),(D*G),(C*H) */
45368 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45371 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45374 /* Multiply lower parts and add all */
45381 }
45382 else
45383 {
45388 {
45391 }
45393 {
45396 }
45398 {
45401 }
45402 else
45406 /* Multiply low parts. */
45410 /* Shift input vectors right 32 bits so we can multiply high parts. */
45415 /* Multiply high parts by low parts. */
45421 /* Combine and shift the highparts back. */
45425 /* Combine high and low parts. */
45427 }
45431 }
45433 /* Calculate integer abs() using only SSE2 instructions. */
45435 void
45437 {
45442 {
45443 /* For 32-bit signed integer X, the best way to calculate the absolute
45444 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45456 /* For 16-bit signed integer X, the best way to calculate the absolute
45457 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45465 /* For 8-bit signed integer X, the best way to calculate the absolute
45466 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45467 as SSE2 provides the PMINUB insn. */
45477 }
45481 }
45483 /* Expand an insert into a vector register through pinsr insn.
45484 Return true if successful. */
45486 bool
45488 {
45496 {
45499 }
45505 {
45510 {
45517 {
45549 }
45563 }
45567 }
45568 }
45569 \f
45570 /* This function returns the calling abi specific va_list type node.
45571 It returns the FNDECL specific va_list type. */
45573 static tree
45575 {
45582 else
45584 }
45586 /* Returns the canonical va_list type specified by TYPE. If there
45587 is no valid TYPE provided, it return NULL_TREE. */
45589 static tree
45591 {
45594 /* Resolve references and pointers to va_list type. */
45603 {
45608 {
45609 /* If va_list is an array type, the argument may have decayed
45610 to a pointer type, e.g. by being passed to another function.
45611 In that case, unwrap both types so that we can compare the
45612 underlying records. */
45615 {
45618 }
45619 }
45626 {
45627 /* If va_list is an array type, the argument may have decayed
45628 to a pointer type, e.g. by being passed to another function.
45629 In that case, unwrap both types so that we can compare the
45630 underlying records. */
45633 {
45636 }
45637 }
45644 {
45645 /* If va_list is an array type, the argument may have decayed
45646 to a pointer type, e.g. by being passed to another function.
45647 In that case, unwrap both types so that we can compare the
45648 underlying records. */
45651 {
45654 }
45655 }
45659 }
45661 }
45663 /* Iterate through the target-specific builtin types for va_list.
45664 IDX denotes the iterator, *PTREE is set to the result type of
45665 the va_list builtin, and *PNAME to its internal type.
45666 Returns zero if there is no element for this index, otherwise
45667 IDX should be increased upon the next call.
45668 Note, do not iterate a base builtin's name like __builtin_va_list.
45669 Used from c_common_nodes_and_builtins. */
45671 static int
45673 {
45675 {
45677 {
45690 }
45691 }
45694 }
45696 #undef TARGET_SCHED_DISPATCH
45697 #define TARGET_SCHED_DISPATCH has_dispatch
45698 #undef TARGET_SCHED_DISPATCH_DO
45699 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45700 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45701 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45702 #undef TARGET_SCHED_REORDER
45703 #define TARGET_SCHED_REORDER ix86_sched_reorder
45704 #undef TARGET_SCHED_ADJUST_PRIORITY
45705 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45706 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45707 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45708 ix86_dependencies_evaluation_hook
45710 /* The size of the dispatch window is the total number of bytes of
45711 object code allowed in a window. */
45712 #define DISPATCH_WINDOW_SIZE 16
45714 /* Number of dispatch windows considered for scheduling. */
45715 #define MAX_DISPATCH_WINDOWS 3
45717 /* Maximum number of instructions in a window. */
45718 #define MAX_INSN 4
45720 /* Maximum number of immediate operands in a window. */
45721 #define MAX_IMM 4
45723 /* Maximum number of immediate bits allowed in a window. */
45724 #define MAX_IMM_SIZE 128
45726 /* Maximum number of 32 bit immediates allowed in a window. */
45727 #define MAX_IMM_32 4
45729 /* Maximum number of 64 bit immediates allowed in a window. */
45730 #define MAX_IMM_64 2
45732 /* Maximum total of loads or prefetches allowed in a window. */
45733 #define MAX_LOAD 2
45735 /* Maximum total of stores allowed in a window. */
45736 #define MAX_STORE 1
45738 #undef BIG
45739 #define BIG 100
45742 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45745 disp_load,
45746 disp_store,
45747 disp_load_store,
45748 disp_prefetch,
45749 disp_imm,
45750 disp_imm_32,
45751 disp_imm_64,
45752 disp_branch,
45753 disp_cmp,
45754 disp_jcc,
45755 disp_last
45756 };
45758 /* Number of allowable groups in a dispatch window. It is an array
45759 indexed by dispatch_group enum. 100 is used as a big number,
45760 because the number of these kind of operations does not have any
45761 effect in dispatch window, but we need them for other reasons in
45762 the table. */
45765 };
45771 };
45773 /* Instruction path. */
45779 last_path
45780 };
45782 /* sched_insn_info defines a window to the instructions scheduled in
45783 the basic block. It contains a pointer to the insn_info table and
45784 the instruction scheduled.
45786 Windows are allocated for each basic block and are linked
45787 together. */
45789 rtx insn;
45796 /* Linked list of dispatch windows. This is a two way list of
45797 dispatch windows of a basic block. It contains information about
45798 the number of uops in the window and the total number of
45799 instructions and of bytes in the object code for this dispatch
45800 window. */
45818 /* Immediate valuse used in an insn. */
45820 {
45829 /* Get dispatch group of insn. */
45831 static enum dispatch_group
45833 {
45849 }
45851 /* Return true if insn is a compare instruction. */
45853 static bool
45855 {
45863 }
45865 /* Return true if a dispatch violation encountered. */
45867 static bool
45869 {
45873 }
45875 /* Return true if insn is a branch instruction. */
45877 static bool
45879 {
45881 }
45883 /* Return true if insn is a prefetch instruction. */
45885 static bool
45887 {
45889 }
45891 /* This function initializes a dispatch window and the list container holding a
45892 pointer to the window. */
45894 static void
45896 {
45902 else
45920 {
45926 }
45928 }
45930 /* This function allocates and initializes a dispatch window and the
45931 list container holding a pointer to the window. */
45935 {
45940 }
45942 /* This routine initializes the dispatch scheduling information. It
45943 initiates building dispatch scheduler tables and constructs the
45944 first dispatch window. */
45946 static void
45948 {
45949 /* Allocate a dispatch list and a window. */
45954 }
45956 /* This function returns true if a branch is detected. End of a basic block
45957 does not have to be a branch, but here we assume only branches end a
45958 window. */
45960 static bool
45962 {
45964 }
45966 /* This function is called when the end of a window processing is reached. */
45968 static void
45970 {
45973 {
45978 }
45980 }
45982 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45983 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45984 for 48 bytes of instructions. Note that these windows are not dispatch
45985 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45989 {
45991 {
45996 }
46002 }
46004 /* Increment the number of immediate operands of an instruction. */
46006 static int
46008 {
46013 {
46020 else
46031 {
46034 }
46039 }
46042 }
46044 /* Compute number of immediate operands of an instruction. */
46046 static void
46048 {
46051 }
46053 /* Return total size of immediate operands of an instruction along with number
46054 of corresponding immediate-operands. It initializes its parameters to zero
46055 befor calling FIND_CONSTANT.
46056 INSN is the input instruction. IMM is the total of immediates.
46057 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
46058 bit immediates. */
46060 static int
46062 {
46070 }
46072 /* This function indicates if an operand of an instruction is an
46073 immediate. */
46075 static bool
46077 {
46086 }
46088 /* Return single or double path for instructions. */
46090 static enum insn_path
46092 {
46102 }
46104 /* Return insn dispatch group. */
46106 static enum dispatch_group
46108 {
46126 }
46128 /* Count number of GROUP restricted instructions in a dispatch
46129 window WINDOW_LIST. */
46131 static int
46133 {
46144 {
46163 }
46176 }
46178 /* This function returns true if insn satisfies dispatch rules on the
46179 last window scheduled. */
46181 static bool
46183 {
46191 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
46192 instructions should be given the lowest priority in the
46193 scheduling process in Haifa scheduler to make sure they will be
46194 scheduled in the same dispatch window as the reference to them. */
46198 /* Check nonrestricted. */
46202 /* Get last dispatch window. */
46207 {
46212 /* Window 1 is full. Go for next window. */
46214 }
46221 /* See if it fits in the first window. */
46223 {
46224 /* The first widow should have only single and double path
46225 uops. */
46231 }
46233 }
46235 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46236 dispatch window WINDOW_LIST. */
46238 static void
46240 {
46258 /* Initialize window with new instruction. */
46279 {
46282 }
46283 }
46285 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46286 If the total bytes of instructions or the number of instructions in
46287 the window exceed allowable, it allocates a new window. */
46289 static void
46291 {
46314 /* Get the last dispatch window. */
46322 else
46325 /* If current window is full, get a new window.
46326 Window number zero is full, if MAX_INSN uops are scheduled in it.
46327 Window number one is full, if window zero's bytes plus window
46328 one's bytes is 32, or if the bytes of the new instruction added
46329 to the total makes it greater than 48, or it has already MAX_INSN
46330 instructions in it. */
46339 {
46342 }
46345 {
46349 {
46352 }
46353 }
46355 {
46360 {
46363 }
46366 }
46367 else
46371 {
46372 /* End of basic block is reached do end-basic-block process. */
46375 }
46376 }
46378 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46380 DEBUG_FUNCTION static void
46382 {
46388 else
46402 {
46405 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46411 }
46412 }
46414 /* Print to stdout a dispatch window. */
46416 DEBUG_FUNCTION void
46418 {
46420 }
46422 /* Print INSN dispatch information to FILE. */
46424 DEBUG_FUNCTION static void
46426 {
46449 }
46451 /* Print to STDERR the status of the ready list with respect to
46452 dispatch windows. */
46454 DEBUG_FUNCTION void
46456 {
46464 }
46466 /* This routine is the driver of the dispatch scheduler. */
46468 static void
46470 {
46475 }
46477 /* Return TRUE if Dispatch Scheduling is supported. */
46479 static bool
46481 {
46485 {
46501 }
46504 }
46506 /* Implementation of reassociation_width target hook used by
46507 reassoc phase to identify parallelism level in reassociated
46508 tree. Statements tree_code is passed in OPC. Arguments type
46509 is passed in MODE.
46511 Currently parallel reassociation is enabled for Atom
46512 processors only and we set reassociation width to be 2
46513 because Atom may issue up to 2 instructions per cycle.
46515 Return value should be fixed if parallel reassociation is
46516 enabled for other processors. */
46518 static int
46520 {
46523 /* Vector part. */
46525 {
46528 else
46530 }
46532 /* Scalar part. */
46539 }
46541 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46542 place emms and femms instructions. */
46544 static enum machine_mode
46546 {
46551 {
46570 else
46582 /* FALLTHRU */
46586 }
46587 }
46589 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46590 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46591 256bit and 128bit vectors. */
46593 static unsigned int
46595 {
46598 }
46600 \f
46602 /* Return class of registers which could be used for pseudo of MODE
46603 and of class RCLASS for spilling instead of memory. Return NO_REGS
46604 if it is not possible or non-profitable. */
46605 static reg_class_t
46607 {
46613 }
46615 /* Implement targetm.vectorize.init_cost. */
46619 {
46623 }
46625 /* Implement targetm.vectorize.add_stmt_cost. */
46627 static unsigned
46631 {
46638 /* Statements in an inner loop relative to the loop being
46639 vectorized are weighted more heavily. The value here is
46640 arbitrary and could potentially be improved with analysis. */
46646 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
46647 for Silvermont as it has out of order integer pipeline and can execute
46648 2 scalar instruction per tick, but has in order SIMD pipeline. */
46651 {
46655 }
46660 }
46662 /* Implement targetm.vectorize.finish_cost. */
46664 static void
46667 {
46672 }
46674 /* Implement targetm.vectorize.destroy_cost_data. */
46676 static void
46678 {
46680 }
46682 /* Validate target specific memory model bits in VAL. */
46684 static unsigned HOST_WIDE_INT
46686 {
46693 {
46697 }
46700 {
46704 }
46706 {
46710 }
46712 }
46714 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46715 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46716 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46717 or number of vecsize_mangle variants that should be emitted. */
46719 static int
46723 {
46730 {
46734 }
46739 {
46746 /* case SCmode: */
46747 /* case DCmode: */
46753 }
46755 tree t;
46759 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46761 {
46768 /* case SCmode: */
46769 /* case DCmode: */
46775 }
46778 {
46779 /* Parse here processor clause. If not present, default to 'b'. */
46781 }
46783 {
46784 /* If the function isn't exported, we can pick up just one ISA
46785 for the clones. */
46790 else
46793 }
46794 else
46795 {
46798 }
46800 {
46813 }
46815 {
46818 else
46823 }
46825 }
46827 /* Add target attribute to SIMD clone NODE if needed. */
46829 static void
46831 {
46835 {
46850 }
46860 }
46862 /* If SIMD clone NODE can't be used in a vectorized loop
46863 in current function, return -1, otherwise return a badness of using it
46864 (0 if it is most desirable from vecsize_mangle point of view, 1
46865 slightly less desirable, etc.). */
46867 static int
46869 {
46871 {
46889 }
46890 }
46892 /* This function gives out the number of memory references.
46893 This value determines the unrolling factor for
46894 bdver3 and bdver4 architectures. */
46896 static int
46898 {
46900 {
46909 else
46911 }
46913 }
46915 /* This function adjusts the unroll factor based on
46916 the hardware capabilities. For ex, bdver3 has
46917 a loop buffer which makes unrolling of smaller
46918 loops less important. This function decides the
46919 unroll factor using number of memory references
46920 (value 32 is used) as a heuristic. */
46922 static unsigned
46924 {
46933 /* Count the number of memory references within the loop body. */
46936 {
46941 }
46948 }
46951 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46953 static bool
46955 {
46956 /* For x87 floating point with standard excess precision handling,
46957 there is no adddf3 pattern (since x87 floating point only has
46958 XFmode operations) so the default hook implementation gets this
46959 wrong. */
46961 }
46963 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46965 static void
46967 {
46972 {
46987 hold_fnclex);
47000 }
47002 {
47011 mxcsr_orig_var,
47021 ldmxcsr_hold_call);
47024 else
47029 ldmxcsr_clear_call);
47030 else
47034 stxmcsr_update_call);
47036 {
47042 exceptions_assign);
47043 }
47044 else
47049 ldmxcsr_update_call);
47050 }
47051 tree atomic_feraiseexcept
47056 atomic_feraiseexcept_call);
47057 }
47059 /* Initialize the GCC target structure. */
47060 #undef TARGET_RETURN_IN_MEMORY
47061 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
47063 #undef TARGET_LEGITIMIZE_ADDRESS
47064 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
47066 #undef TARGET_ATTRIBUTE_TABLE
47067 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
47068 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
47069 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
47070 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47071 # undef TARGET_MERGE_DECL_ATTRIBUTES
47072 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
47073 #endif
47075 #undef TARGET_COMP_TYPE_ATTRIBUTES
47076 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
47078 #undef TARGET_INIT_BUILTINS
47079 #define TARGET_INIT_BUILTINS ix86_init_builtins
47080 #undef TARGET_BUILTIN_DECL
47081 #define TARGET_BUILTIN_DECL ix86_builtin_decl
47082 #undef TARGET_EXPAND_BUILTIN
47083 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
47085 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
47086 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
47087 ix86_builtin_vectorized_function
47089 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
47090 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
47092 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
47093 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
47095 #undef TARGET_VECTORIZE_BUILTIN_GATHER
47096 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
47098 #undef TARGET_BUILTIN_RECIPROCAL
47099 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
47101 #undef TARGET_ASM_FUNCTION_EPILOGUE
47102 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
47104 #undef TARGET_ENCODE_SECTION_INFO
47105 #ifndef SUBTARGET_ENCODE_SECTION_INFO
47106 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
47107 #else
47108 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
47109 #endif
47111 #undef TARGET_ASM_OPEN_PAREN
47113 #undef TARGET_ASM_CLOSE_PAREN
47116 #undef TARGET_ASM_BYTE_OP
47117 #define TARGET_ASM_BYTE_OP ASM_BYTE
47119 #undef TARGET_ASM_ALIGNED_HI_OP
47120 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
47121 #undef TARGET_ASM_ALIGNED_SI_OP
47122 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
47123 #ifdef ASM_QUAD
47124 #undef TARGET_ASM_ALIGNED_DI_OP
47125 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
47126 #endif
47128 #undef TARGET_PROFILE_BEFORE_PROLOGUE
47129 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
47131 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
47132 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
47134 #undef TARGET_ASM_UNALIGNED_HI_OP
47135 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
47136 #undef TARGET_ASM_UNALIGNED_SI_OP
47137 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
47138 #undef TARGET_ASM_UNALIGNED_DI_OP
47139 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
47141 #undef TARGET_PRINT_OPERAND
47142 #define TARGET_PRINT_OPERAND ix86_print_operand
47143 #undef TARGET_PRINT_OPERAND_ADDRESS
47144 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
47145 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
47146 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
47147 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
47148 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
47150 #undef TARGET_SCHED_INIT_GLOBAL
47151 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
47152 #undef TARGET_SCHED_ADJUST_COST
47153 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
47154 #undef TARGET_SCHED_ISSUE_RATE
47155 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
47156 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
47157 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
47158 ia32_multipass_dfa_lookahead
47159 #undef TARGET_SCHED_MACRO_FUSION_P
47160 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
47161 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
47162 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
47164 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
47165 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
47167 #undef TARGET_MEMMODEL_CHECK
47168 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
47170 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
47171 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
47173 #ifdef HAVE_AS_TLS
47174 #undef TARGET_HAVE_TLS
47175 #define TARGET_HAVE_TLS true
47176 #endif
47177 #undef TARGET_CANNOT_FORCE_CONST_MEM
47178 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
47179 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
47180 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
47182 #undef TARGET_DELEGITIMIZE_ADDRESS
47183 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
47185 #undef TARGET_MS_BITFIELD_LAYOUT_P
47186 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
47188 #if TARGET_MACHO
47189 #undef TARGET_BINDS_LOCAL_P
47190 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
47191 #endif
47192 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47193 #undef TARGET_BINDS_LOCAL_P
47194 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
47195 #endif
47197 #undef TARGET_ASM_OUTPUT_MI_THUNK
47198 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
47199 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
47200 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
47202 #undef TARGET_ASM_FILE_START
47203 #define TARGET_ASM_FILE_START x86_file_start
47205 #undef TARGET_OPTION_OVERRIDE
47206 #define TARGET_OPTION_OVERRIDE ix86_option_override
47208 #undef TARGET_REGISTER_MOVE_COST
47209 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
47210 #undef TARGET_MEMORY_MOVE_COST
47211 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
47212 #undef TARGET_RTX_COSTS
47213 #define TARGET_RTX_COSTS ix86_rtx_costs
47214 #undef TARGET_ADDRESS_COST
47215 #define TARGET_ADDRESS_COST ix86_address_cost
47217 #undef TARGET_FIXED_CONDITION_CODE_REGS
47218 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
47219 #undef TARGET_CC_MODES_COMPATIBLE
47220 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
47222 #undef TARGET_MACHINE_DEPENDENT_REORG
47223 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47225 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47226 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47228 #undef TARGET_BUILD_BUILTIN_VA_LIST
47229 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47231 #undef TARGET_FOLD_BUILTIN
47232 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47234 #undef TARGET_COMPARE_VERSION_PRIORITY
47235 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47237 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47238 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47239 ix86_generate_version_dispatcher_body
47241 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47242 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47243 ix86_get_function_versions_dispatcher
47245 #undef TARGET_ENUM_VA_LIST_P
47246 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47248 #undef TARGET_FN_ABI_VA_LIST
47249 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47251 #undef TARGET_CANONICAL_VA_LIST_TYPE
47252 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47254 #undef TARGET_EXPAND_BUILTIN_VA_START
47255 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47257 #undef TARGET_MD_ASM_CLOBBERS
47258 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47260 #undef TARGET_PROMOTE_PROTOTYPES
47261 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47262 #undef TARGET_SETUP_INCOMING_VARARGS
47263 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47264 #undef TARGET_MUST_PASS_IN_STACK
47265 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47266 #undef TARGET_FUNCTION_ARG_ADVANCE
47267 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47268 #undef TARGET_FUNCTION_ARG
47269 #define TARGET_FUNCTION_ARG ix86_function_arg
47270 #undef TARGET_FUNCTION_ARG_BOUNDARY
47271 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47272 #undef TARGET_PASS_BY_REFERENCE
47273 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47274 #undef TARGET_INTERNAL_ARG_POINTER
47275 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47276 #undef TARGET_UPDATE_STACK_BOUNDARY
47277 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47278 #undef TARGET_GET_DRAP_RTX
47279 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47280 #undef TARGET_STRICT_ARGUMENT_NAMING
47281 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47282 #undef TARGET_STATIC_CHAIN
47283 #define TARGET_STATIC_CHAIN ix86_static_chain
47284 #undef TARGET_TRAMPOLINE_INIT
47285 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47286 #undef TARGET_RETURN_POPS_ARGS
47287 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47289 #undef TARGET_LEGITIMATE_COMBINED_INSN
47290 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47292 #undef TARGET_ASAN_SHADOW_OFFSET
47293 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47295 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47296 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47298 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47299 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47301 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47302 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47304 #undef TARGET_C_MODE_FOR_SUFFIX
47305 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47307 #ifdef HAVE_AS_TLS
47308 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47309 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47310 #endif
47312 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47313 #undef TARGET_INSERT_ATTRIBUTES
47314 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47315 #endif
47317 #undef TARGET_MANGLE_TYPE
47318 #define TARGET_MANGLE_TYPE ix86_mangle_type
47320 #if !TARGET_MACHO
47321 #undef TARGET_STACK_PROTECT_FAIL
47322 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47323 #endif
47325 #undef TARGET_FUNCTION_VALUE
47326 #define TARGET_FUNCTION_VALUE ix86_function_value
47328 #undef TARGET_FUNCTION_VALUE_REGNO_P
47329 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47331 #undef TARGET_PROMOTE_FUNCTION_MODE
47332 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47334 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47335 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47337 #undef TARGET_INSTANTIATE_DECLS
47338 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47340 #undef TARGET_SECONDARY_RELOAD
47341 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47343 #undef TARGET_CLASS_MAX_NREGS
47344 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47346 #undef TARGET_PREFERRED_RELOAD_CLASS
47347 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47348 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47349 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47350 #undef TARGET_CLASS_LIKELY_SPILLED_P
47351 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47353 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47354 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47355 ix86_builtin_vectorization_cost
47356 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47357 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47358 ix86_vectorize_vec_perm_const_ok
47359 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47360 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47361 ix86_preferred_simd_mode
47362 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47363 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47364 ix86_autovectorize_vector_sizes
47365 #undef TARGET_VECTORIZE_INIT_COST
47366 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47367 #undef TARGET_VECTORIZE_ADD_STMT_COST
47368 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47369 #undef TARGET_VECTORIZE_FINISH_COST
47370 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47371 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47372 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47374 #undef TARGET_SET_CURRENT_FUNCTION
47375 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47377 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47378 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47380 #undef TARGET_OPTION_SAVE
47381 #define TARGET_OPTION_SAVE ix86_function_specific_save
47383 #undef TARGET_OPTION_RESTORE
47384 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47386 #undef TARGET_OPTION_PRINT
47387 #define TARGET_OPTION_PRINT ix86_function_specific_print
47389 #undef TARGET_OPTION_FUNCTION_VERSIONS
47390 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47392 #undef TARGET_CAN_INLINE_P
47393 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47395 #undef TARGET_EXPAND_TO_RTL_HOOK
47396 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47398 #undef TARGET_LEGITIMATE_ADDRESS_P
47399 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47401 #undef TARGET_LRA_P
47402 #define TARGET_LRA_P hook_bool_void_true
47404 #undef TARGET_REGISTER_PRIORITY
47405 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47407 #undef TARGET_REGISTER_USAGE_LEVELING_P
47408 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47410 #undef TARGET_LEGITIMATE_CONSTANT_P
47411 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47413 #undef TARGET_FRAME_POINTER_REQUIRED
47414 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47416 #undef TARGET_CAN_ELIMINATE
47417 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47419 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47420 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47422 #undef TARGET_ASM_CODE_END
47423 #define TARGET_ASM_CODE_END ix86_code_end
47425 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47426 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47428 #if TARGET_MACHO
47429 #undef TARGET_INIT_LIBFUNCS
47430 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47431 #endif
47433 #undef TARGET_LOOP_UNROLL_ADJUST
47434 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47436 #undef TARGET_SPILL_CLASS
47437 #define TARGET_SPILL_CLASS ix86_spill_class
47439 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47440 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47441 ix86_simd_clone_compute_vecsize_and_simdlen
47443 #undef TARGET_SIMD_CLONE_ADJUST
47444 #define TARGET_SIMD_CLONE_ADJUST \
47445 ix86_simd_clone_adjust
47447 #undef TARGET_SIMD_CLONE_USABLE
47448 #define TARGET_SIMD_CLONE_USABLE \
47449 ix86_simd_clone_usable
47451 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47452 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47453 ix86_float_exceptions_rounding_supported_p
47455 #undef TARGET_MODE_EMIT
47456 #define TARGET_MODE_EMIT ix86_emit_mode_set
47458 #undef TARGET_MODE_NEEDED
47459 #define TARGET_MODE_NEEDED ix86_mode_needed
47461 #undef TARGET_MODE_AFTER
47462 #define TARGET_MODE_AFTER ix86_mode_after
47464 #undef TARGET_MODE_ENTRY
47465 #define TARGET_MODE_ENTRY ix86_mode_entry
47467 #undef TARGET_MODE_EXIT
47468 #define TARGET_MODE_EXIT ix86_mode_exit
47470 #undef TARGET_MODE_PRIORITY
47471 #define TARGET_MODE_PRIORITY ix86_mode_priority
47473 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
47474 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
47477 \f