[AArch64] Fix ICEs in aarch64_print_operand
[official-gcc.git] / gcc / config / i386 / i386.h
blob3477aa9eba789baee24fb97cba8e4fea692bda2c
1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 Under Section 7 of GPL version 3, you are granted additional
17 permissions described in the GCC Runtime Library Exception, version
18 3.1, as published by the Free Software Foundation.
20 You should have received a copy of the GNU General Public License and
21 a copy of the GCC Runtime Library Exception along with this program;
22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23 <http://www.gnu.org/licenses/>. */
25 /* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
40 /* Redefines for option macros. */
42 #define TARGET_64BIT TARGET_ISA_64BIT
43 #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x)
44 #define TARGET_MMX TARGET_ISA_MMX
45 #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x)
46 #define TARGET_3DNOW TARGET_ISA_3DNOW
47 #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x)
48 #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A
49 #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x)
50 #define TARGET_SSE TARGET_ISA_SSE
51 #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x)
52 #define TARGET_SSE2 TARGET_ISA_SSE2
53 #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x)
54 #define TARGET_SSE3 TARGET_ISA_SSE3
55 #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x)
56 #define TARGET_SSSE3 TARGET_ISA_SSSE3
57 #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x)
58 #define TARGET_SSE4_1 TARGET_ISA_SSE4_1
59 #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x)
60 #define TARGET_SSE4_2 TARGET_ISA_SSE4_2
61 #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x)
62 #define TARGET_AVX TARGET_ISA_AVX
63 #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x)
64 #define TARGET_AVX2 TARGET_ISA_AVX2
65 #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x)
66 #define TARGET_AVX512F TARGET_ISA_AVX512F
67 #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x)
68 #define TARGET_AVX512PF TARGET_ISA_AVX512PF
69 #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x)
70 #define TARGET_AVX512ER TARGET_ISA_AVX512ER
71 #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x)
72 #define TARGET_AVX512CD TARGET_ISA_AVX512CD
73 #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x)
74 #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ
75 #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x)
76 #define TARGET_AVX512BW TARGET_ISA_AVX512BW
77 #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x)
78 #define TARGET_AVX512VL TARGET_ISA_AVX512VL
79 #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x)
80 #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI
81 #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x)
82 #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA
83 #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x)
84 #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS
85 #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x)
86 #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW
87 #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x)
88 #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2
89 #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x)
90 #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ
91 #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x)
92 #define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI
93 #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x)
94 #define TARGET_FMA TARGET_ISA_FMA
95 #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
96 #define TARGET_SSE4A TARGET_ISA_SSE4A
97 #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x)
98 #define TARGET_FMA4 TARGET_ISA_FMA4
99 #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x)
100 #define TARGET_XOP TARGET_ISA_XOP
101 #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x)
102 #define TARGET_LWP TARGET_ISA_LWP
103 #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x)
104 #define TARGET_ABM TARGET_ISA_ABM
105 #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x)
106 #define TARGET_SGX TARGET_ISA_SGX
107 #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x)
108 #define TARGET_RDPID TARGET_ISA_RDPID
109 #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x)
110 #define TARGET_GFNI TARGET_ISA_GFNI
111 #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x)
112 #define TARGET_BMI TARGET_ISA_BMI
113 #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x)
114 #define TARGET_BMI2 TARGET_ISA_BMI2
115 #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x)
116 #define TARGET_LZCNT TARGET_ISA_LZCNT
117 #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x)
118 #define TARGET_TBM TARGET_ISA_TBM
119 #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x)
120 #define TARGET_POPCNT TARGET_ISA_POPCNT
121 #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x)
122 #define TARGET_SAHF TARGET_ISA_SAHF
123 #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x)
124 #define TARGET_MOVBE TARGET_ISA_MOVBE
125 #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x)
126 #define TARGET_CRC32 TARGET_ISA_CRC32
127 #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x)
128 #define TARGET_AES TARGET_ISA_AES
129 #define TARGET_AES_P(x) TARGET_ISA_AES_P(x)
130 #define TARGET_SHA TARGET_ISA_SHA
131 #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x)
132 #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT
133 #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x)
134 #define TARGET_CLZERO TARGET_ISA_CLZERO
135 #define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x)
136 #define TARGET_XSAVEC TARGET_ISA_XSAVEC
137 #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x)
138 #define TARGET_XSAVES TARGET_ISA_XSAVES
139 #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x)
140 #define TARGET_PCLMUL TARGET_ISA_PCLMUL
141 #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x)
142 #define TARGET_CMPXCHG16B TARGET_ISA_CX16
143 #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x)
144 #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE
145 #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x)
146 #define TARGET_RDRND TARGET_ISA_RDRND
147 #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x)
148 #define TARGET_F16C TARGET_ISA_F16C
149 #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x)
150 #define TARGET_RTM TARGET_ISA_RTM
151 #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x)
152 #define TARGET_HLE TARGET_ISA_HLE
153 #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x)
154 #define TARGET_RDSEED TARGET_ISA_RDSEED
155 #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x)
156 #define TARGET_PRFCHW TARGET_ISA_PRFCHW
157 #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x)
158 #define TARGET_ADX TARGET_ISA_ADX
159 #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x)
160 #define TARGET_FXSR TARGET_ISA_FXSR
161 #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x)
162 #define TARGET_XSAVE TARGET_ISA_XSAVE
163 #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x)
164 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT
165 #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x)
166 #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1
167 #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x)
168 #define TARGET_MPX TARGET_ISA_MPX
169 #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x)
170 #define TARGET_CLWB TARGET_ISA_CLWB
171 #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x)
172 #define TARGET_MWAITX TARGET_ISA_MWAITX
173 #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x)
174 #define TARGET_PKU TARGET_ISA_PKU
175 #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x)
176 #define TARGET_IBT TARGET_ISA_IBT
177 #define TARGET_IBT_P(x) TARGET_ISA_IBT_P(x)
178 #define TARGET_SHSTK TARGET_ISA_SHSTK
179 #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x)
181 #define TARGET_LP64 TARGET_ABI_64
182 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
183 #define TARGET_X32 TARGET_ABI_X32
184 #define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
185 #define TARGET_16BIT TARGET_CODE16
186 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
188 #include "config/vxworks-dummy.h"
190 #include "config/i386/i386-opts.h"
192 #define MAX_STRINGOP_ALGS 4
194 /* Specify what algorithm to use for stringops on known size.
195 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
196 known at compile time or estimated via feedback, the SIZE array
197 is walked in order until MAX is greater then the estimate (or -1
198 means infinity). Corresponding ALG is used then.
199 When NOALIGN is true the code guaranting the alignment of the memory
200 block is skipped.
202 For example initializer:
203 {{256, loop}, {-1, rep_prefix_4_byte}}
204 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
205 be used otherwise. */
206 struct stringop_algs
208 const enum stringop_alg unknown_size;
209 const struct stringop_strategy {
210 const int max;
211 const enum stringop_alg alg;
212 int noalign;
213 } size [MAX_STRINGOP_ALGS];
216 /* Define the specific costs for a given cpu */
218 struct processor_costs {
219 const int add; /* cost of an add instruction */
220 const int lea; /* cost of a lea instruction */
221 const int shift_var; /* variable shift costs */
222 const int shift_const; /* constant shift costs */
223 const int mult_init[5]; /* cost of starting a multiply
224 in QImode, HImode, SImode, DImode, TImode*/
225 const int mult_bit; /* cost of multiply per each bit set */
226 const int divide[5]; /* cost of a divide/mod
227 in QImode, HImode, SImode, DImode, TImode*/
228 int movsx; /* The cost of movsx operation. */
229 int movzx; /* The cost of movzx operation. */
230 const int large_insn; /* insns larger than this cost more */
231 const int move_ratio; /* The threshold of number of scalar
232 memory-to-memory move insns. */
233 const int movzbl_load; /* cost of loading using movzbl */
234 const int int_load[3]; /* cost of loading integer registers
235 in QImode, HImode and SImode relative
236 to reg-reg move (2). */
237 const int int_store[3]; /* cost of storing integer register
238 in QImode, HImode and SImode */
239 const int fp_move; /* cost of reg,reg fld/fst */
240 const int fp_load[3]; /* cost of loading FP register
241 in SFmode, DFmode and XFmode */
242 const int fp_store[3]; /* cost of storing FP register
243 in SFmode, DFmode and XFmode */
244 const int mmx_move; /* cost of moving MMX register. */
245 const int mmx_load[2]; /* cost of loading MMX register
246 in SImode and DImode */
247 const int mmx_store[2]; /* cost of storing MMX register
248 in SImode and DImode */
249 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */
250 zmm_move;
251 const int sse_load[5]; /* cost of loading SSE register
252 in 32bit, 64bit, 128bit, 256bit and 512bit */
253 const int sse_unaligned_load[5];/* cost of unaligned load. */
254 const int sse_store[5]; /* cost of storing SSE register
255 in SImode, DImode and TImode. */
256 const int sse_unaligned_store[5];/* cost of unaligned store. */
257 const int mmxsse_to_integer; /* cost of moving mmxsse register to
258 integer. */
259 const int ssemmx_to_integer; /* cost of moving integer to mmxsse register. */
260 const int gather_static, gather_per_elt; /* Cost of gather load is computed
261 as static + per_item * nelts. */
262 const int scatter_static, scatter_per_elt; /* Cost of gather store is
263 computed as static + per_item * nelts. */
264 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
265 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
266 const int prefetch_block; /* bytes moved to cache for prefetch. */
267 const int simultaneous_prefetches; /* number of parallel prefetch
268 operations. */
269 const int branch_cost; /* Default value for BRANCH_COST. */
270 const int fadd; /* cost of FADD and FSUB instructions. */
271 const int fmul; /* cost of FMUL instruction. */
272 const int fdiv; /* cost of FDIV instruction. */
273 const int fabs; /* cost of FABS instruction. */
274 const int fchs; /* cost of FCHS instruction. */
275 const int fsqrt; /* cost of FSQRT instruction. */
276 /* Specify what algorithm
277 to use for stringops on unknown size. */
278 const int sse_op; /* cost of cheap SSE instruction. */
279 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */
280 const int mulss; /* cost of MULSS instructions. */
281 const int mulsd; /* cost of MULSD instructions. */
282 const int fmass; /* cost of FMASS instructions. */
283 const int fmasd; /* cost of FMASD instructions. */
284 const int divss; /* cost of DIVSS instructions. */
285 const int divsd; /* cost of DIVSD instructions. */
286 const int sqrtss; /* cost of SQRTSS instructions. */
287 const int sqrtsd; /* cost of SQRTSD instructions. */
288 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp;
289 /* Specify reassociation width for integer,
290 fp, vector integer and vector fp
291 operations. Generally should correspond
292 to number of instructions executed in
293 parallel. See also
294 ix86_reassociation_width. */
295 struct stringop_algs *memcpy, *memset;
296 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
297 cost model. */
298 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
299 vectorizer cost model. */
302 extern const struct processor_costs *ix86_cost;
303 extern const struct processor_costs ix86_size_cost;
305 #define ix86_cur_cost() \
306 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
308 /* Macros used in the machine description to test the flags. */
310 /* configure can arrange to change it. */
312 #ifndef TARGET_CPU_DEFAULT
313 #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
314 #endif
316 #ifndef TARGET_FPMATH_DEFAULT
317 #define TARGET_FPMATH_DEFAULT \
318 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
319 #endif
321 #ifndef TARGET_FPMATH_DEFAULT_P
322 #define TARGET_FPMATH_DEFAULT_P(x) \
323 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
324 #endif
326 /* If the i387 is disabled or -miamcu is used , then do not return
327 values in it. */
328 #define TARGET_FLOAT_RETURNS_IN_80387 \
329 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU)
330 #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \
331 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x))
333 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
334 compile-time constant. */
335 #ifdef IN_LIBGCC2
336 #undef TARGET_64BIT
337 #ifdef __x86_64__
338 #define TARGET_64BIT 1
339 #else
340 #define TARGET_64BIT 0
341 #endif
342 #else
343 #ifndef TARGET_BI_ARCH
344 #undef TARGET_64BIT
345 #undef TARGET_64BIT_P
346 #if TARGET_64BIT_DEFAULT
347 #define TARGET_64BIT 1
348 #define TARGET_64BIT_P(x) 1
349 #else
350 #define TARGET_64BIT 0
351 #define TARGET_64BIT_P(x) 0
352 #endif
353 #endif
354 #endif
356 #define HAS_LONG_COND_BRANCH 1
357 #define HAS_LONG_UNCOND_BRANCH 1
359 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
360 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
361 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
362 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
363 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
364 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
365 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
366 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
367 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
368 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
369 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
370 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
371 #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
372 #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
373 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
374 #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
375 #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
376 #define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
377 #define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
378 #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
379 #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
380 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
381 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
382 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
383 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
384 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
385 #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3)
386 #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)
387 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
388 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
389 #define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1)
391 /* Feature tests against the various tunings. */
392 enum ix86_tune_indices {
393 #undef DEF_TUNE
394 #define DEF_TUNE(tune, name, selector) tune,
395 #include "x86-tune.def"
396 #undef DEF_TUNE
397 X86_TUNE_LAST
400 extern unsigned char ix86_tune_features[X86_TUNE_LAST];
402 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
403 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
404 #define TARGET_ZERO_EXTEND_WITH_AND \
405 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
406 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
407 #define TARGET_BRANCH_PREDICTION_HINTS \
408 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
409 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
410 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
411 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
412 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
413 #define TARGET_PARTIAL_FLAG_REG_STALL \
414 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
415 #define TARGET_LCP_STALL \
416 ix86_tune_features[X86_TUNE_LCP_STALL]
417 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
418 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
419 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
420 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
421 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
422 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
423 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
424 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
425 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
426 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
427 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
428 #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
429 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
430 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
431 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
432 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
433 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
434 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
435 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
436 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
437 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
438 #define TARGET_INTEGER_DFMODE_MOVES \
439 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
440 #define TARGET_PARTIAL_REG_DEPENDENCY \
441 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
442 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
443 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
444 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
445 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
446 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
447 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
448 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
449 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
450 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
451 #define TARGET_SSE_TYPELESS_STORES \
452 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
453 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
454 #define TARGET_MEMORY_MISMATCH_STALL \
455 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
456 #define TARGET_PROLOGUE_USING_MOVE \
457 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
458 #define TARGET_EPILOGUE_USING_MOVE \
459 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
460 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
461 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
462 #define TARGET_INTER_UNIT_MOVES_TO_VEC \
463 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
464 #define TARGET_INTER_UNIT_MOVES_FROM_VEC \
465 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
466 #define TARGET_INTER_UNIT_CONVERSIONS \
467 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
468 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
469 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
470 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
471 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
472 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
473 #define TARGET_PAD_SHORT_FUNCTION \
474 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
475 #define TARGET_EXT_80387_CONSTANTS \
476 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
477 #define TARGET_AVOID_VECTOR_DECODE \
478 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
479 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
480 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
481 #define TARGET_SLOW_IMUL_IMM32_MEM \
482 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
483 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
484 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
485 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
486 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
487 #define TARGET_USE_VECTOR_FP_CONVERTS \
488 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
489 #define TARGET_USE_VECTOR_CONVERTS \
490 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
491 #define TARGET_SLOW_PSHUFB \
492 ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
493 #define TARGET_AVOID_4BYTE_PREFIXES \
494 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]
495 #define TARGET_FUSE_CMP_AND_BRANCH_32 \
496 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
497 #define TARGET_FUSE_CMP_AND_BRANCH_64 \
498 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
499 #define TARGET_FUSE_CMP_AND_BRANCH \
500 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
501 : TARGET_FUSE_CMP_AND_BRANCH_32)
502 #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
503 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
504 #define TARGET_FUSE_ALU_AND_BRANCH \
505 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
506 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
507 #define TARGET_AVOID_LEA_FOR_ADDR \
508 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]
509 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
510 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
511 #define TARGET_AVX128_OPTIMAL \
512 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
513 #define TARGET_GENERAL_REGS_SSE_SPILL \
514 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
515 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
516 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
517 #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
518 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
519 #define TARGET_ADJUST_UNROLL \
520 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
521 #define TARGET_AVOID_FALSE_DEP_FOR_BMI \
522 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
523 #define TARGET_ONE_IF_CONV_INSN \
524 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
525 #define TARGET_EMIT_VZEROUPPER \
526 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
528 /* Feature tests against the various architecture variations. */
529 enum ix86_arch_indices {
530 X86_ARCH_CMOV,
531 X86_ARCH_CMPXCHG,
532 X86_ARCH_CMPXCHG8B,
533 X86_ARCH_XADD,
534 X86_ARCH_BSWAP,
536 X86_ARCH_LAST
539 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
541 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
542 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
543 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
544 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
545 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
547 /* For sane SSE instruction set generation we need fcomi instruction.
548 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
549 expands to a sequence that includes conditional move. */
550 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
552 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
554 extern unsigned char x86_prefetch_sse;
555 #define TARGET_PREFETCH_SSE x86_prefetch_sse
557 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
559 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
560 #define TARGET_MIX_SSE_I387 \
561 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
563 #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
564 #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE)
565 #define TARGET_HARD_XF_REGS (TARGET_80387)
567 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
568 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
569 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
570 #define TARGET_SUN_TLS 0
572 #ifndef TARGET_64BIT_DEFAULT
573 #define TARGET_64BIT_DEFAULT 0
574 #endif
575 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
576 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
577 #endif
579 #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
580 #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
582 /* Fence to use after loop using storent. */
584 extern tree x86_mfence;
585 #define FENCE_FOLLOWING_MOVNT x86_mfence
587 /* Once GDB has been enhanced to deal with functions without frame
588 pointers, we can change this to allow for elimination of
589 the frame pointer in leaf functions. */
590 #define TARGET_DEFAULT 0
592 /* Extra bits to force. */
593 #define TARGET_SUBTARGET_DEFAULT 0
594 #define TARGET_SUBTARGET_ISA_DEFAULT 0
596 /* Extra bits to force on w/ 32-bit mode. */
597 #define TARGET_SUBTARGET32_DEFAULT 0
598 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
600 /* Extra bits to force on w/ 64-bit mode. */
601 #define TARGET_SUBTARGET64_DEFAULT 0
602 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
604 /* Replace MACH-O, ifdefs by in-line tests, where possible.
605 (a) Macros defined in config/i386/darwin.h */
606 #define TARGET_MACHO 0
607 #define TARGET_MACHO_BRANCH_ISLANDS 0
608 #define MACHOPIC_ATT_STUB 0
609 /* (b) Macros defined in config/darwin.h */
610 #define MACHO_DYNAMIC_NO_PIC_P 0
611 #define MACHOPIC_INDIRECT 0
612 #define MACHOPIC_PURE 0
614 /* For the RDOS */
615 #define TARGET_RDOS 0
617 /* For the Windows 64-bit ABI. */
618 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
620 /* For the Windows 32-bit ABI. */
621 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
623 /* This is re-defined by cygming.h. */
624 #define TARGET_SEH 0
626 /* The default abi used by target. */
627 #define DEFAULT_ABI SYSV_ABI
629 /* The default TLS segment register used by target. */
630 #define DEFAULT_TLS_SEG_REG \
631 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS)
633 /* Subtargets may reset this to 1 in order to enable 96-bit long double
634 with the rounding mode forced to 53 bits. */
635 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
637 /* -march=native handling only makes sense with compiler running on
638 an x86 or x86_64 chip. If changing this condition, also change
639 the condition in driver-i386.c. */
640 #if defined(__i386__) || defined(__x86_64__)
641 /* In driver-i386.c. */
642 extern const char *host_detect_local_cpu (int argc, const char **argv);
643 #define EXTRA_SPEC_FUNCTIONS \
644 { "local_cpu_detect", host_detect_local_cpu },
645 #define HAVE_LOCAL_CPU_DETECT
646 #endif
648 #if TARGET_64BIT_DEFAULT
649 #define OPT_ARCH64 "!m32"
650 #define OPT_ARCH32 "m32"
651 #else
652 #define OPT_ARCH64 "m64|mx32"
653 #define OPT_ARCH32 "m64|mx32:;"
654 #endif
656 /* Support for configure-time defaults of some command line options.
657 The order here is important so that -march doesn't squash the
658 tune or cpu values. */
659 #define OPTION_DEFAULT_SPECS \
660 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
661 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
662 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
663 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
664 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
665 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
666 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
667 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
668 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
670 /* Specs for the compiler proper */
672 #ifndef CC1_CPU_SPEC
673 #define CC1_CPU_SPEC_1 ""
675 #ifndef HAVE_LOCAL_CPU_DETECT
676 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
677 #else
678 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
679 "%{march=native:%>march=native %:local_cpu_detect(arch) \
680 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
681 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
682 #endif
683 #endif
685 /* Target CPU builtins. */
686 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
688 /* Target Pragmas. */
689 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
691 #ifndef CC1_SPEC
692 #define CC1_SPEC "%(cc1_cpu) "
693 #endif
695 /* This macro defines names of additional specifications to put in the
696 specs that can be used in various specifications like CC1_SPEC. Its
697 definition is an initializer with a subgrouping for each command option.
699 Each subgrouping contains a string constant, that defines the
700 specification name, and a string constant that used by the GCC driver
701 program.
703 Do not define this macro if it does not need to do anything. */
705 #ifndef SUBTARGET_EXTRA_SPECS
706 #define SUBTARGET_EXTRA_SPECS
707 #endif
709 #define EXTRA_SPECS \
710 { "cc1_cpu", CC1_CPU_SPEC }, \
711 SUBTARGET_EXTRA_SPECS
714 /* Whether to allow x87 floating-point arithmetic on MODE (one of
715 SFmode, DFmode and XFmode) in the current excess precision
716 configuration. */
717 #define X87_ENABLE_ARITH(MODE) \
718 (flag_unsafe_math_optimizations \
719 || flag_excess_precision == EXCESS_PRECISION_FAST \
720 || (MODE) == XFmode)
722 /* Likewise, whether to allow direct conversions from integer mode
723 IMODE (HImode, SImode or DImode) to MODE. */
724 #define X87_ENABLE_FLOAT(MODE, IMODE) \
725 (flag_unsafe_math_optimizations \
726 || flag_excess_precision == EXCESS_PRECISION_FAST \
727 || (MODE) == XFmode \
728 || ((MODE) == DFmode && (IMODE) == SImode) \
729 || (IMODE) == HImode)
731 /* target machine storage layout */
733 #define SHORT_TYPE_SIZE 16
734 #define INT_TYPE_SIZE 32
735 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
736 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
737 #define LONG_LONG_TYPE_SIZE 64
738 #define FLOAT_TYPE_SIZE 32
739 #define DOUBLE_TYPE_SIZE 64
740 #define LONG_DOUBLE_TYPE_SIZE \
741 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80))
743 #define WIDEST_HARDWARE_FP_SIZE 80
745 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
746 #define MAX_BITS_PER_WORD 64
747 #else
748 #define MAX_BITS_PER_WORD 32
749 #endif
751 /* Define this if most significant byte of a word is the lowest numbered. */
752 /* That is true on the 80386. */
754 #define BITS_BIG_ENDIAN 0
756 /* Define this if most significant byte of a word is the lowest numbered. */
757 /* That is not true on the 80386. */
758 #define BYTES_BIG_ENDIAN 0
760 /* Define this if most significant word of a multiword number is the lowest
761 numbered. */
762 /* Not true for 80386 */
763 #define WORDS_BIG_ENDIAN 0
765 /* Width of a word, in units (bytes). */
766 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
768 #ifndef IN_LIBGCC2
769 #define MIN_UNITS_PER_WORD 4
770 #endif
772 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
773 #define PARM_BOUNDARY BITS_PER_WORD
775 /* Boundary (in *bits*) on which stack pointer should be aligned. */
776 #define STACK_BOUNDARY \
777 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
779 /* Stack boundary of the main function guaranteed by OS. */
780 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
782 /* Minimum stack boundary. */
783 #define MIN_STACK_BOUNDARY BITS_PER_WORD
785 /* Boundary (in *bits*) on which the stack pointer prefers to be
786 aligned; the compiler cannot rely on having this alignment. */
787 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
789 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
790 both 32bit and 64bit, to support codes that need 128 bit stack
791 alignment for SSE instructions, but can't realign the stack. */
792 #define PREFERRED_STACK_BOUNDARY_DEFAULT \
793 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128)
795 /* 1 if -mstackrealign should be turned on by default. It will
796 generate an alternate prologue and epilogue that realigns the
797 runtime stack if nessary. This supports mixing codes that keep a
798 4-byte aligned stack, as specified by i386 psABI, with codes that
799 need a 16-byte aligned stack, as required by SSE instructions. */
800 #define STACK_REALIGN_DEFAULT 0
802 /* Boundary (in *bits*) on which the incoming stack is aligned. */
803 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
805 /* According to Windows x64 software convention, the maximum stack allocatable
806 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
807 instructions allowed to adjust the stack pointer in the epilog, forcing the
808 use of frame pointer for frames larger than 2 GB. This theorical limit
809 is reduced by 256, an over-estimated upper bound for the stack use by the
810 prologue.
811 We define only one threshold for both the prolog and the epilog. When the
812 frame size is larger than this threshold, we allocate the area to save SSE
813 regs, then save them, and then allocate the remaining. There is no SEH
814 unwind info for this later allocation. */
815 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
817 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
818 mandatory for the 64-bit ABI, and may or may not be true for other
819 operating systems. */
820 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
822 /* Minimum allocation boundary for the code of a function. */
823 #define FUNCTION_BOUNDARY 8
825 /* C++ stores the virtual bit in the lowest bit of function pointers. */
826 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
828 /* Minimum size in bits of the largest boundary to which any
829 and all fundamental data types supported by the hardware
830 might need to be aligned. No data type wants to be aligned
831 rounder than this.
833 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
834 and Pentium Pro XFmode values at 128 bit boundaries.
836 When increasing the maximum, also update
837 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
839 #define BIGGEST_ALIGNMENT \
840 (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128)))
842 /* Maximum stack alignment. */
843 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
845 /* Alignment value for attribute ((aligned)). It is a constant since
846 it is the part of the ABI. We shouldn't change it with -mavx. */
847 #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128)
849 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
850 #define ALIGN_MODE_128(MODE) \
851 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
853 /* The published ABIs say that doubles should be aligned on word
854 boundaries, so lower the alignment for structure fields unless
855 -malign-double is set. */
857 /* ??? Blah -- this macro is used directly by libobjc. Since it
858 supports no vector modes, cut out the complexity and fall back
859 on BIGGEST_FIELD_ALIGNMENT. */
860 #ifdef IN_TARGET_LIBS
861 #ifdef __x86_64__
862 #define BIGGEST_FIELD_ALIGNMENT 128
863 #else
864 #define BIGGEST_FIELD_ALIGNMENT 32
865 #endif
866 #else
867 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
868 x86_field_alignment ((TYPE), (COMPUTED))
869 #endif
871 /* If defined, a C expression to compute the alignment for a static
872 variable. TYPE is the data type, and ALIGN is the alignment that
873 the object would ordinarily have. The value of this macro is used
874 instead of that alignment to align the object.
876 If this macro is not defined, then ALIGN is used.
878 One use of this macro is to increase alignment of medium-size
879 data to make it all fit in fewer cache lines. Another is to
880 cause character arrays to be word-aligned so that `strcpy' calls
881 that copy constants to character arrays can be done inline. */
883 #define DATA_ALIGNMENT(TYPE, ALIGN) \
884 ix86_data_alignment ((TYPE), (ALIGN), true)
886 /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
887 some alignment increase, instead of optimization only purposes. E.g.
888 AMD x86-64 psABI says that variables with array type larger than 15 bytes
889 must be aligned to 16 byte boundaries.
891 If this macro is not defined, then ALIGN is used. */
893 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
894 ix86_data_alignment ((TYPE), (ALIGN), false)
896 /* If defined, a C expression to compute the alignment for a local
897 variable. TYPE is the data type, and ALIGN is the alignment that
898 the object would ordinarily have. The value of this macro is used
899 instead of that alignment to align the object.
901 If this macro is not defined, then ALIGN is used.
903 One use of this macro is to increase alignment of medium-size
904 data to make it all fit in fewer cache lines. */
906 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
907 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
909 /* If defined, a C expression to compute the alignment for stack slot.
910 TYPE is the data type, MODE is the widest mode available, and ALIGN
911 is the alignment that the slot would ordinarily have. The value of
912 this macro is used instead of that alignment to align the slot.
914 If this macro is not defined, then ALIGN is used when TYPE is NULL,
915 Otherwise, LOCAL_ALIGNMENT will be used.
917 One use of this macro is to set alignment of stack slot to the
918 maximum alignment of all possible modes which the slot may have. */
920 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
921 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
923 /* If defined, a C expression to compute the alignment for a local
924 variable DECL.
926 If this macro is not defined, then
927 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
929 One use of this macro is to increase alignment of medium-size
930 data to make it all fit in fewer cache lines. */
932 #define LOCAL_DECL_ALIGNMENT(DECL) \
933 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
935 /* If defined, a C expression to compute the minimum required alignment
936 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
937 MODE, assuming normal alignment ALIGN.
939 If this macro is not defined, then (ALIGN) will be used. */
941 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
942 ix86_minimum_alignment ((EXP), (MODE), (ALIGN))
945 /* Set this nonzero if move instructions will actually fail to work
946 when given unaligned data. */
947 #define STRICT_ALIGNMENT 0
949 /* If bit field type is int, don't let it cross an int,
950 and give entire struct the alignment of an int. */
951 /* Required on the 386 since it doesn't have bit-field insns. */
952 #define PCC_BITFIELD_TYPE_MATTERS 1
954 /* Standard register usage. */
956 /* This processor has special stack-like registers. See reg-stack.c
957 for details. */
959 #define STACK_REGS
961 #define IS_STACK_MODE(MODE) \
962 (X87_FLOAT_MODE_P (MODE) \
963 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
964 || TARGET_MIX_SSE_I387))
966 /* Number of actual hardware registers.
967 The hardware registers are assigned numbers for the compiler
968 from 0 to just below FIRST_PSEUDO_REGISTER.
969 All registers that the compiler knows about must be given numbers,
970 even those that are not normally considered general registers.
972 In the 80386 we give the 8 general purpose registers the numbers 0-7.
973 We number the floating point registers 8-15.
974 Note that registers 0-7 can be accessed as a short or int,
975 while only 0-3 may be used with byte `mov' instructions.
977 Reg 16 does not correspond to any hardware register, but instead
978 appears in the RTL as an argument pointer prior to reload, and is
979 eliminated during reloading in favor of either the stack or frame
980 pointer. */
982 #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG
984 /* Number of hardware registers that go into the DWARF-2 unwind info.
985 If not defined, equals FIRST_PSEUDO_REGISTER. */
987 #define DWARF_FRAME_REGISTERS 17
989 /* 1 for registers that have pervasive standard uses
990 and are not available for the register allocator.
991 On the 80386, the stack pointer is such, as is the arg pointer.
993 REX registers are disabled for 32bit targets in
994 TARGET_CONDITIONAL_REGISTER_USAGE. */
996 #define FIXED_REGISTERS \
997 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
998 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
999 /*arg,flags,fpsr,fpcr,frame*/ \
1000 1, 1, 1, 1, 1, \
1001 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1002 0, 0, 0, 0, 0, 0, 0, 0, \
1003 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1004 0, 0, 0, 0, 0, 0, 0, 0, \
1005 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1006 0, 0, 0, 0, 0, 0, 0, 0, \
1007 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1008 0, 0, 0, 0, 0, 0, 0, 0, \
1009 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1010 0, 0, 0, 0, 0, 0, 0, 0, \
1011 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1012 0, 0, 0, 0, 0, 0, 0, 0, \
1013 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1014 0, 0, 0, 0, 0, 0, 0, 0, \
1015 /* b0, b1, b2, b3*/ \
1016 0, 0, 0, 0 }
1018 /* 1 for registers not available across function calls.
1019 These must include the FIXED_REGISTERS and also any
1020 registers that can be used without being saved.
1021 The latter must include the registers where values are returned
1022 and the register where structure-value addresses are passed.
1023 Aside from that, you can include as many other registers as you like.
1025 Value is set to 1 if the register is call used unconditionally.
1026 Bit one is set if the register is call used on TARGET_32BIT ABI.
1027 Bit two is set if the register is call used on TARGET_64BIT ABI.
1028 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
1030 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
1032 #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \
1033 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1))
1035 #define CALL_USED_REGISTERS \
1036 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
1037 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1038 /*arg,flags,fpsr,fpcr,frame*/ \
1039 1, 1, 1, 1, 1, \
1040 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1041 1, 1, 1, 1, 1, 1, 6, 6, \
1042 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1043 1, 1, 1, 1, 1, 1, 1, 1, \
1044 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1045 1, 1, 1, 1, 2, 2, 2, 2, \
1046 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1047 6, 6, 6, 6, 6, 6, 6, 6, \
1048 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1049 6, 6, 6, 6, 6, 6, 6, 6, \
1050 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1051 6, 6, 6, 6, 6, 6, 6, 6, \
1052 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1053 1, 1, 1, 1, 1, 1, 1, 1, \
1054 /* b0, b1, b2, b3*/ \
1055 1, 1, 1, 1 }
1057 /* Order in which to allocate registers. Each register must be
1058 listed once, even those in FIXED_REGISTERS. List frame pointer
1059 late and fixed registers last. Note that, in general, we prefer
1060 registers listed in CALL_USED_REGISTERS, keeping the others
1061 available for storage of persistent values.
1063 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
1064 so this is just empty initializer for array. */
1066 #define REG_ALLOC_ORDER \
1067 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
1068 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
1069 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1070 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
1071 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \
1072 78, 79, 80 }
1074 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1075 to be rearranged based on a particular function. When using sse math,
1076 we want to allocate SSE before x87 registers and vice versa. */
1078 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
1081 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1083 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1084 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \
1085 && GENERAL_REGNO_P (REGNO) \
1086 && ((MODE) == XFmode || (MODE) == XCmode))
1088 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1090 #define VALID_AVX256_REG_MODE(MODE) \
1091 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1092 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1093 || (MODE) == V4DFmode)
1095 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1096 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1098 #define VALID_AVX512F_SCALAR_MODE(MODE) \
1099 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \
1100 || (MODE) == SFmode)
1102 #define VALID_AVX512F_REG_MODE(MODE) \
1103 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1104 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
1105 || (MODE) == V4TImode)
1107 #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \
1108 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
1110 #define VALID_AVX512VL_128_REG_MODE(MODE) \
1111 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
1112 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
1113 || (MODE) == TFmode || (MODE) == V1TImode)
1115 #define VALID_SSE2_REG_MODE(MODE) \
1116 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1117 || (MODE) == V2DImode || (MODE) == DFmode)
1119 #define VALID_SSE_REG_MODE(MODE) \
1120 ((MODE) == V1TImode || (MODE) == TImode \
1121 || (MODE) == V4SFmode || (MODE) == V4SImode \
1122 || (MODE) == SFmode || (MODE) == TFmode)
1124 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1125 ((MODE) == V2SFmode || (MODE) == SFmode)
1127 #define VALID_MMX_REG_MODE(MODE) \
1128 ((MODE == V1DImode) || (MODE) == DImode \
1129 || (MODE) == V2SImode || (MODE) == SImode \
1130 || (MODE) == V4HImode || (MODE) == V8QImode)
1132 #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1134 #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
1136 #define VALID_BND_REG_MODE(MODE) \
1137 (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode)
1139 #define VALID_DFP_MODE_P(MODE) \
1140 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1142 #define VALID_FP_MODE_P(MODE) \
1143 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1144 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1146 #define VALID_INT_MODE_P(MODE) \
1147 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1148 || (MODE) == DImode \
1149 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1150 || (MODE) == CDImode \
1151 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1152 || (MODE) == TFmode || (MODE) == TCmode)))
1154 /* Return true for modes passed in SSE registers. */
1155 #define SSE_REG_MODE_P(MODE) \
1156 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1157 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1158 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1159 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1160 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1161 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
1162 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
1163 || (MODE) == V16SFmode)
1165 #define X87_FLOAT_MODE_P(MODE) \
1166 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1168 #define SSE_FLOAT_MODE_P(MODE) \
1169 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1171 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
1172 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1173 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1175 /* It is possible to write patterns to move flags; but until someone
1176 does it, */
1177 #define AVOID_CCMODE_COPIES
1179 /* Specify the modes required to caller save a given hard regno.
1180 We do this on i386 to prevent flags from being saved at all.
1182 Kill any attempts to combine saving of modes. */
1184 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1185 (CC_REGNO_P (REGNO) ? VOIDmode \
1186 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1187 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1188 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \
1189 && TARGET_PARTIAL_REG_STALL) \
1190 || MASK_REGNO_P (REGNO)) ? SImode \
1191 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \
1192 || MASK_REGNO_P (REGNO)) ? SImode \
1193 : (MODE))
1195 /* Specify the registers used for certain standard purposes.
1196 The values of these macros are register numbers. */
1198 /* on the 386 the pc register is %eip, and is not usable as a general
1199 register. The ordinary mov instructions won't work */
1200 /* #define PC_REGNUM */
1202 /* Base register for access to arguments of the function. */
1203 #define ARG_POINTER_REGNUM ARGP_REG
1205 /* Register to use for pushing function arguments. */
1206 #define STACK_POINTER_REGNUM SP_REG
1208 /* Base register for access to local variables of the function. */
1209 #define FRAME_POINTER_REGNUM FRAME_REG
1210 #define HARD_FRAME_POINTER_REGNUM BP_REG
1212 #define FIRST_INT_REG AX_REG
1213 #define LAST_INT_REG SP_REG
1215 #define FIRST_QI_REG AX_REG
1216 #define LAST_QI_REG BX_REG
1218 /* First & last stack-like regs */
1219 #define FIRST_STACK_REG ST0_REG
1220 #define LAST_STACK_REG ST7_REG
1222 #define FIRST_SSE_REG XMM0_REG
1223 #define LAST_SSE_REG XMM7_REG
1225 #define FIRST_MMX_REG MM0_REG
1226 #define LAST_MMX_REG MM7_REG
1228 #define FIRST_REX_INT_REG R8_REG
1229 #define LAST_REX_INT_REG R15_REG
1231 #define FIRST_REX_SSE_REG XMM8_REG
1232 #define LAST_REX_SSE_REG XMM15_REG
1234 #define FIRST_EXT_REX_SSE_REG XMM16_REG
1235 #define LAST_EXT_REX_SSE_REG XMM31_REG
1237 #define FIRST_MASK_REG MASK0_REG
1238 #define LAST_MASK_REG MASK7_REG
1240 #define FIRST_BND_REG BND0_REG
1241 #define LAST_BND_REG BND3_REG
1243 /* Override this in other tm.h files to cope with various OS lossage
1244 requiring a frame pointer. */
1245 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1246 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1247 #endif
1249 /* Make sure we can access arbitrary call frames. */
1250 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1252 /* Register to hold the addressing base for position independent
1253 code access to data items. We don't use PIC pointer for 64bit
1254 mode. Define the regnum to dummy value to prevent gcc from
1255 pessimizing code dealing with EBX.
1257 To avoid clobbering a call-saved register unnecessarily, we renumber
1258 the pic register when possible. The change is visible after the
1259 prologue has been emitted. */
1261 #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG)
1263 #define PIC_OFFSET_TABLE_REGNUM \
1264 (ix86_use_pseudo_pic_reg () \
1265 ? (pic_offset_table_rtx \
1266 ? INVALID_REGNUM \
1267 : REAL_PIC_OFFSET_TABLE_REGNUM) \
1268 : INVALID_REGNUM)
1270 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1272 /* This is overridden by <cygwin.h>. */
1273 #define MS_AGGREGATE_RETURN 0
1275 #define KEEP_AGGREGATE_RETURN_POINTER 0
1277 /* Define the classes of registers for register constraints in the
1278 machine description. Also define ranges of constants.
1280 One of the classes must always be named ALL_REGS and include all hard regs.
1281 If there is more than one class, another class must be named NO_REGS
1282 and contain no registers.
1284 The name GENERAL_REGS must be the name of a class (or an alias for
1285 another name such as ALL_REGS). This is the class of registers
1286 that is allowed by "g" or "r" in a register constraint.
1287 Also, registers outside this class are allocated only when
1288 instructions express preferences for them.
1290 The classes must be numbered in nondecreasing order; that is,
1291 a larger-numbered class must never be contained completely
1292 in a smaller-numbered class. This is why CLOBBERED_REGS class
1293 is listed early, even though in 64-bit mode it contains more
1294 registers than just %eax, %ecx, %edx.
1296 For any two classes, it is very desirable that there be another
1297 class that represents their union.
1299 It might seem that class BREG is unnecessary, since no useful 386
1300 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1301 and the "b" register constraint is useful in asms for syscalls.
1303 The flags, fpsr and fpcr registers are in no class. */
1305 enum reg_class
1307 NO_REGS,
1308 AREG, DREG, CREG, BREG, SIREG, DIREG,
1309 AD_REGS, /* %eax/%edx for DImode */
1310 CLOBBERED_REGS, /* call-clobbered integer registers */
1311 Q_REGS, /* %eax %ebx %ecx %edx */
1312 NON_Q_REGS, /* %esi %edi %ebp %esp */
1313 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */
1314 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1315 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1316 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1317 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1318 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1319 FLOAT_REGS,
1320 SSE_FIRST_REG,
1321 NO_REX_SSE_REGS,
1322 SSE_REGS,
1323 EVEX_SSE_REGS,
1324 BND_REGS,
1325 ALL_SSE_REGS,
1326 MMX_REGS,
1327 FP_TOP_SSE_REGS,
1328 FP_SECOND_SSE_REGS,
1329 FLOAT_SSE_REGS,
1330 FLOAT_INT_REGS,
1331 INT_SSE_REGS,
1332 FLOAT_INT_SSE_REGS,
1333 MASK_EVEX_REGS,
1334 MASK_REGS,
1335 MOD4_SSE_REGS,
1336 ALL_REGS, LIM_REG_CLASSES
1339 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1341 #define INTEGER_CLASS_P(CLASS) \
1342 reg_class_subset_p ((CLASS), GENERAL_REGS)
1343 #define FLOAT_CLASS_P(CLASS) \
1344 reg_class_subset_p ((CLASS), FLOAT_REGS)
1345 #define SSE_CLASS_P(CLASS) \
1346 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1347 #define MMX_CLASS_P(CLASS) \
1348 ((CLASS) == MMX_REGS)
1349 #define MASK_CLASS_P(CLASS) \
1350 reg_class_subset_p ((CLASS), MASK_REGS)
1351 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1352 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1353 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1354 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1355 #define MAYBE_SSE_CLASS_P(CLASS) \
1356 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1357 #define MAYBE_MMX_CLASS_P(CLASS) \
1358 reg_classes_intersect_p ((CLASS), MMX_REGS)
1359 #define MAYBE_MASK_CLASS_P(CLASS) \
1360 reg_classes_intersect_p ((CLASS), MASK_REGS)
1362 #define Q_CLASS_P(CLASS) \
1363 reg_class_subset_p ((CLASS), Q_REGS)
1365 #define MAYBE_NON_Q_CLASS_P(CLASS) \
1366 reg_classes_intersect_p ((CLASS), NON_Q_REGS)
1368 /* Give names of register classes as strings for dump file. */
1370 #define REG_CLASS_NAMES \
1371 { "NO_REGS", \
1372 "AREG", "DREG", "CREG", "BREG", \
1373 "SIREG", "DIREG", \
1374 "AD_REGS", \
1375 "CLOBBERED_REGS", \
1376 "Q_REGS", "NON_Q_REGS", \
1377 "TLS_GOTBASE_REGS", \
1378 "INDEX_REGS", \
1379 "LEGACY_REGS", \
1380 "GENERAL_REGS", \
1381 "FP_TOP_REG", "FP_SECOND_REG", \
1382 "FLOAT_REGS", \
1383 "SSE_FIRST_REG", \
1384 "NO_REX_SSE_REGS", \
1385 "SSE_REGS", \
1386 "EVEX_SSE_REGS", \
1387 "BND_REGS", \
1388 "ALL_SSE_REGS", \
1389 "MMX_REGS", \
1390 "FP_TOP_SSE_REGS", \
1391 "FP_SECOND_SSE_REGS", \
1392 "FLOAT_SSE_REGS", \
1393 "FLOAT_INT_REGS", \
1394 "INT_SSE_REGS", \
1395 "FLOAT_INT_SSE_REGS", \
1396 "MASK_EVEX_REGS", \
1397 "MASK_REGS", \
1398 "MOD4_SSE_REGS", \
1399 "ALL_REGS" }
1401 /* Define which registers fit in which classes. This is an initializer
1402 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1404 Note that CLOBBERED_REGS are calculated by
1405 TARGET_CONDITIONAL_REGISTER_USAGE. */
1407 #define REG_CLASS_CONTENTS \
1408 { { 0x00, 0x0, 0x0 }, \
1409 { 0x01, 0x0, 0x0 }, /* AREG */ \
1410 { 0x02, 0x0, 0x0 }, /* DREG */ \
1411 { 0x04, 0x0, 0x0 }, /* CREG */ \
1412 { 0x08, 0x0, 0x0 }, /* BREG */ \
1413 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1414 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1415 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1416 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1417 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1418 { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \
1419 { 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \
1420 { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
1421 { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
1422 { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
1423 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1424 { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1425 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1426 { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1427 { 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \
1428 { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
1429 { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \
1430 { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \
1431 { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
1432 { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
1433 { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
1434 { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
1435 { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
1436 { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
1437 { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
1438 { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
1439 { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \
1440 { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \
1441 { 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \
1442 { 0xffffffff,0xffffffff,0x1ffff } \
1445 /* The same information, inverted:
1446 Return the class number of the smallest class containing
1447 reg number REGNO. This could be a conditional expression
1448 or could index an array. */
1450 #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)])
1452 /* When this hook returns true for MODE, the compiler allows
1453 registers explicitly used in the rtl to be used as spill registers
1454 but prevents the compiler from extending the lifetime of these
1455 registers. */
1456 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1458 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1459 #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG)
1461 #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
1462 #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG))
1464 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1465 #define REX_INT_REGNO_P(N) \
1466 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1468 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1469 #define GENERAL_REGNO_P(N) \
1470 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
1472 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1473 #define ANY_QI_REGNO_P(N) \
1474 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1476 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1477 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1479 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1480 #define SSE_REGNO_P(N) \
1481 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1482 || REX_SSE_REGNO_P (N) \
1483 || EXT_REX_SSE_REGNO_P (N))
1485 #define REX_SSE_REGNO_P(N) \
1486 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1488 #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
1490 #define EXT_REX_SSE_REGNO_P(N) \
1491 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
1493 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1494 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1496 #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
1497 #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
1499 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1500 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1502 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1503 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1505 #define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X)))
1506 #define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG)
1508 #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X)))
1509 #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \
1510 || (N) == XMM4_REG \
1511 || (N) == XMM8_REG \
1512 || (N) == XMM12_REG \
1513 || (N) == XMM16_REG \
1514 || (N) == XMM20_REG \
1515 || (N) == XMM24_REG \
1516 || (N) == XMM28_REG)
1518 /* First floating point reg */
1519 #define FIRST_FLOAT_REG FIRST_STACK_REG
1520 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
1522 #define SSE_REGNO(N) \
1523 ((N) < 8 ? FIRST_SSE_REG + (N) \
1524 : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
1525 : (FIRST_EXT_REX_SSE_REG + (N) - 16))
1527 /* The class value for index registers, and the one for base regs. */
1529 #define INDEX_REG_CLASS INDEX_REGS
1530 #define BASE_REG_CLASS GENERAL_REGS
1532 /* Stack layout; function entry, exit and calling. */
1534 /* Define this if pushing a word on the stack
1535 makes the stack pointer a smaller address. */
1536 #define STACK_GROWS_DOWNWARD 1
1538 /* Define this to nonzero if the nominal address of the stack frame
1539 is at the high-address end of the local variables;
1540 that is, each additional local variable allocated
1541 goes at a more negative offset in the frame. */
1542 #define FRAME_GROWS_DOWNWARD 1
1544 /* If we generate an insn to push BYTES bytes, this says how many the stack
1545 pointer really advances by. On 386, we have pushw instruction that
1546 decrements by exactly 2 no matter what the position was, there is no pushb.
1548 But as CIE data alignment factor on this arch is -4 for 32bit targets
1549 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1550 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1552 #define PUSH_ROUNDING(BYTES) ROUND_UP ((BYTES), UNITS_PER_WORD)
1554 /* If defined, the maximum amount of space required for outgoing arguments
1555 will be computed and placed into the variable `crtl->outgoing_args_size'.
1556 No space will be pushed onto the stack for each call; instead, the
1557 function prologue should increase the stack frame size by this amount.
1559 In 32bit mode enabling argument accumulation results in about 5% code size
1560 growth because move instructions are less compact than push. In 64bit
1561 mode the difference is less drastic but visible.
1563 FIXME: Unlike earlier implementations, the size of unwind info seems to
1564 actually grow with accumulation. Is that because accumulated args
1565 unwind info became unnecesarily bloated?
1567 With the 64-bit MS ABI, we can generate correct code with or without
1568 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code
1569 generated without accumulated args is terrible.
1571 If stack probes are required, the space used for large function
1572 arguments on the stack must also be probed, so enable
1573 -maccumulate-outgoing-args so this happens in the prologue.
1575 We must use argument accumulation in interrupt function if stack
1576 may be realigned to avoid DRAP. */
1578 #define ACCUMULATE_OUTGOING_ARGS \
1579 ((TARGET_ACCUMULATE_OUTGOING_ARGS \
1580 && optimize_function_for_speed_p (cfun)) \
1581 || (cfun->machine->func_type != TYPE_NORMAL \
1582 && crtl->stack_realign_needed) \
1583 || TARGET_STACK_PROBE \
1584 || TARGET_64BIT_MS_ABI \
1585 || (TARGET_MACHO && crtl->profile))
1587 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1588 instructions to pass outgoing arguments. */
1590 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1592 /* We want the stack and args grow in opposite directions, even if
1593 PUSH_ARGS is 0. */
1594 #define PUSH_ARGS_REVERSED 1
1596 /* Offset of first parameter from the argument pointer register value. */
1597 #define FIRST_PARM_OFFSET(FNDECL) 0
1599 /* Define this macro if functions should assume that stack space has been
1600 allocated for arguments even when their values are passed in registers.
1602 The value of this macro is the size, in bytes, of the area reserved for
1603 arguments passed in registers for the function represented by FNDECL.
1605 This space can be allocated by the caller, or be a part of the
1606 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1607 which. */
1608 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1610 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1611 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1613 /* Define how to find the value returned by a library function
1614 assuming the value has mode MODE. */
1616 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1618 /* Define the size of the result block used for communication between
1619 untyped_call and untyped_return. The block contains a DImode value
1620 followed by the block used by fnsave and frstor. */
1622 #define APPLY_RESULT_SIZE (8+108)
1624 /* 1 if N is a possible register number for function argument passing. */
1625 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1627 /* Define a data type for recording info about an argument list
1628 during the scan of that argument list. This data type should
1629 hold all necessary information about the function itself
1630 and about the args processed so far, enough to enable macros
1631 such as FUNCTION_ARG to determine where the next arg should go. */
1633 typedef struct ix86_args {
1634 int words; /* # words passed so far */
1635 int nregs; /* # registers available for passing */
1636 int regno; /* next available register number */
1637 int fastcall; /* fastcall or thiscall calling convention
1638 is used */
1639 int sse_words; /* # sse words passed so far */
1640 int sse_nregs; /* # sse registers available for passing */
1641 int warn_avx512f; /* True when we want to warn
1642 about AVX512F ABI. */
1643 int warn_avx; /* True when we want to warn about AVX ABI. */
1644 int warn_sse; /* True when we want to warn about SSE ABI. */
1645 int warn_mmx; /* True when we want to warn about MMX ABI. */
1646 int warn_empty; /* True when we want to warn about empty classes
1647 passing ABI change. */
1648 int sse_regno; /* next available sse register number */
1649 int mmx_words; /* # mmx words passed so far */
1650 int mmx_nregs; /* # mmx registers available for passing */
1651 int mmx_regno; /* next available mmx register number */
1652 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1653 int caller; /* true if it is caller. */
1654 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1655 SFmode/DFmode arguments should be passed
1656 in SSE registers. Otherwise 0. */
1657 int bnd_regno; /* next available bnd register number */
1658 int bnds_in_bt; /* number of bounds expected in BT. */
1659 int force_bnd_pass; /* number of bounds expected for stdarg arg. */
1660 int stdarg; /* Set to 1 if function is stdarg. */
1661 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1662 MS_ABI for ms abi. */
1663 tree decl; /* Callee decl. */
1664 } CUMULATIVE_ARGS;
1666 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1667 for a call to a function whose data type is FNTYPE.
1668 For a library call, FNTYPE is 0. */
1670 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1671 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1672 (N_NAMED_ARGS) != -1)
1674 /* Output assembler code to FILE to increment profiler label # LABELNO
1675 for profiling a function entry. */
1677 #define FUNCTION_PROFILER(FILE, LABELNO) \
1678 x86_function_profiler ((FILE), (LABELNO))
1680 #define MCOUNT_NAME "_mcount"
1682 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1684 #define PROFILE_COUNT_REGISTER "edx"
1686 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1687 the stack pointer does not matter. The value is tested only in
1688 functions that have frame pointers.
1689 No definition is equivalent to always zero. */
1690 /* Note on the 386 it might be more efficient not to define this since
1691 we have to restore it ourselves from the frame pointer, in order to
1692 use pop */
1694 #define EXIT_IGNORE_STACK 1
1696 /* Define this macro as a C expression that is nonzero for registers
1697 used by the epilogue or the `return' pattern. */
1699 #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO)
1701 /* Output assembler code for a block containing the constant parts
1702 of a trampoline, leaving space for the variable parts. */
1704 /* On the 386, the trampoline contains two instructions:
1705 mov #STATIC,ecx
1706 jmp FUNCTION
1707 The trampoline is generated entirely at runtime. The operand of JMP
1708 is the address of FUNCTION relative to the instruction following the
1709 JMP (which is 5 bytes long). */
1711 /* Length in units of the trampoline for entering a nested function. */
1713 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1715 /* Definitions for register eliminations.
1717 This is an array of structures. Each structure initializes one pair
1718 of eliminable registers. The "from" register number is given first,
1719 followed by "to". Eliminations of the same "from" register are listed
1720 in order of preference.
1722 There are two registers that can always be eliminated on the i386.
1723 The frame pointer and the arg pointer can be replaced by either the
1724 hard frame pointer or to the stack pointer, depending upon the
1725 circumstances. The hard frame pointer is not used before reload and
1726 so it is not eligible for elimination. */
1728 #define ELIMINABLE_REGS \
1729 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1730 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1731 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1732 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1734 /* Define the offset between two registers, one to be eliminated, and the other
1735 its replacement, at the start of a routine. */
1737 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1738 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1740 /* Addressing modes, and classification of registers for them. */
1742 /* Macros to check register numbers against specific register classes. */
1744 /* These assume that REGNO is a hard or pseudo reg number.
1745 They give nonzero only if REGNO is a hard reg of the suitable class
1746 or a pseudo reg currently allocated to a suitable hard reg.
1747 Since they use reg_renumber, they are safe only once reg_renumber
1748 has been allocated, which happens in reginfo.c during register
1749 allocation. */
1751 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1752 ((REGNO) < STACK_POINTER_REGNUM \
1753 || REX_INT_REGNO_P (REGNO) \
1754 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1755 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1757 #define REGNO_OK_FOR_BASE_P(REGNO) \
1758 (GENERAL_REGNO_P (REGNO) \
1759 || (REGNO) == ARG_POINTER_REGNUM \
1760 || (REGNO) == FRAME_POINTER_REGNUM \
1761 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1763 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1764 and check its validity for a certain class.
1765 We have two alternate definitions for each of them.
1766 The usual definition accepts all pseudo regs; the other rejects
1767 them unless they have been allocated suitable hard regs.
1768 The symbol REG_OK_STRICT causes the latter definition to be used.
1770 Most source files want to accept pseudo regs in the hope that
1771 they will get allocated to the class that the insn wants them to be in.
1772 Source files for reload pass need to be strict.
1773 After reload, it makes no difference, since pseudo regs have
1774 been eliminated by then. */
1777 /* Non strict versions, pseudos are ok. */
1778 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1779 (REGNO (X) < STACK_POINTER_REGNUM \
1780 || REX_INT_REGNO_P (REGNO (X)) \
1781 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1783 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1784 (GENERAL_REGNO_P (REGNO (X)) \
1785 || REGNO (X) == ARG_POINTER_REGNUM \
1786 || REGNO (X) == FRAME_POINTER_REGNUM \
1787 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1789 /* Strict versions, hard registers only */
1790 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1791 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1793 #ifndef REG_OK_STRICT
1794 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1795 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1797 #else
1798 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1799 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1800 #endif
1802 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1803 that is a valid memory address for an instruction.
1804 The MODE argument is the machine mode for the MEM expression
1805 that wants to use this address.
1807 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1808 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1810 See legitimize_pic_address in i386.c for details as to what
1811 constitutes a legitimate address when -fpic is used. */
1813 #define MAX_REGS_PER_ADDRESS 2
1815 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1817 /* If defined, a C expression to determine the base term of address X.
1818 This macro is used in only one place: `find_base_term' in alias.c.
1820 It is always safe for this macro to not be defined. It exists so
1821 that alias analysis can understand machine-dependent addresses.
1823 The typical use of this macro is to handle addresses containing
1824 a label_ref or symbol_ref within an UNSPEC. */
1826 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1828 /* Nonzero if the constant value X is a legitimate general operand
1829 when generating PIC code. It is given that flag_pic is on and
1830 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1832 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1834 #define SYMBOLIC_CONST(X) \
1835 (GET_CODE (X) == SYMBOL_REF \
1836 || GET_CODE (X) == LABEL_REF \
1837 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1839 /* Max number of args passed in registers. If this is more than 3, we will
1840 have problems with ebx (register #4), since it is a caller save register and
1841 is also used as the pic register in ELF. So for now, don't allow more than
1842 3 registers to be passed in registers. */
1844 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1845 #define X86_64_REGPARM_MAX 6
1846 #define X86_64_MS_REGPARM_MAX 4
1848 #define X86_32_REGPARM_MAX 3
1850 #define REGPARM_MAX \
1851 (TARGET_64BIT \
1852 ? (TARGET_64BIT_MS_ABI \
1853 ? X86_64_MS_REGPARM_MAX \
1854 : X86_64_REGPARM_MAX) \
1855 : X86_32_REGPARM_MAX)
1857 #define X86_64_SSE_REGPARM_MAX 8
1858 #define X86_64_MS_SSE_REGPARM_MAX 4
1860 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1862 #define SSE_REGPARM_MAX \
1863 (TARGET_64BIT \
1864 ? (TARGET_64BIT_MS_ABI \
1865 ? X86_64_MS_SSE_REGPARM_MAX \
1866 : X86_64_SSE_REGPARM_MAX) \
1867 : X86_32_SSE_REGPARM_MAX)
1869 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1871 /* Specify the machine mode that this machine uses
1872 for the index in the tablejump instruction. */
1873 #define CASE_VECTOR_MODE \
1874 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1876 /* Define this as 1 if `char' should by default be signed; else as 0. */
1877 #define DEFAULT_SIGNED_CHAR 1
1879 /* Max number of bytes we can move from memory to memory
1880 in one reasonably fast instruction. */
1881 #define MOVE_MAX 16
1883 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1884 move efficiently, as opposed to MOVE_MAX which is the maximum
1885 number of bytes we can move with a single instruction.
1887 ??? We should use TImode in 32-bit mode and use OImode or XImode
1888 if they are available. But since by_pieces_ninsns determines the
1889 widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in
1890 64-bit mode. */
1891 #define MOVE_MAX_PIECES \
1892 ((TARGET_64BIT \
1893 && TARGET_SSE2 \
1894 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
1895 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1896 ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD)
1898 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1899 move-instruction pairs, we will do a movmem or libcall instead.
1900 Increasing the value will always make code faster, but eventually
1901 incurs high cost in increased code size.
1903 If you don't define this, a reasonable default is used. */
1905 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1907 /* If a clear memory operation would take CLEAR_RATIO or more simple
1908 move-instruction sequences, we will do a clrmem or libcall instead. */
1910 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1912 /* Define if shifts truncate the shift count which implies one can
1913 omit a sign-extension or zero-extension of a shift count.
1915 On i386, shifts do truncate the count. But bit test instructions
1916 take the modulo of the bit offset operand. */
1918 /* #define SHIFT_COUNT_TRUNCATED */
1920 /* A macro to update M and UNSIGNEDP when an object whose type is
1921 TYPE and which has the specified mode and signedness is to be
1922 stored in a register. This macro is only called when TYPE is a
1923 scalar type.
1925 On i386 it is sometimes useful to promote HImode and QImode
1926 quantities to SImode. The choice depends on target type. */
1928 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1929 do { \
1930 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1931 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1932 (MODE) = SImode; \
1933 } while (0)
1935 /* Specify the machine mode that pointers have.
1936 After generation of rtl, the compiler makes no further distinction
1937 between pointers and any other objects of this machine mode. */
1938 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1940 /* Specify the machine mode that bounds have. */
1941 #define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode)
1943 /* A C expression whose value is zero if pointers that need to be extended
1944 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1945 greater then zero if they are zero-extended and less then zero if the
1946 ptr_extend instruction should be used. */
1948 #define POINTERS_EXTEND_UNSIGNED 1
1950 /* A function address in a call instruction
1951 is a byte address (for indexing purposes)
1952 so give the MEM rtx a byte's mode. */
1953 #define FUNCTION_MODE QImode
1956 /* A C expression for the cost of a branch instruction. A value of 1
1957 is the default; other values are interpreted relative to that. */
1959 #define BRANCH_COST(speed_p, predictable_p) \
1960 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1962 /* An integer expression for the size in bits of the largest integer machine
1963 mode that should actually be used. We allow pairs of registers. */
1964 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
1966 /* Define this macro as a C expression which is nonzero if accessing
1967 less than a word of memory (i.e. a `char' or a `short') is no
1968 faster than accessing a word of memory, i.e., if such access
1969 require more than one instruction or if there is no difference in
1970 cost between byte and (aligned) word loads.
1972 When this macro is not defined, the compiler will access a field by
1973 finding the smallest containing object; when it is defined, a
1974 fullword load will be used if alignment permits. Unless bytes
1975 accesses are faster than word accesses, using word accesses is
1976 preferable since it may eliminate subsequent memory access if
1977 subsequent accesses occur to other fields in the same word of the
1978 structure, but to different bytes. */
1980 #define SLOW_BYTE_ACCESS 0
1982 /* Nonzero if access to memory by shorts is slow and undesirable. */
1983 #define SLOW_SHORT_ACCESS 0
1985 /* Define this macro if it is as good or better to call a constant
1986 function address than to call an address kept in a register.
1988 Desirable on the 386 because a CALL with a constant address is
1989 faster than one with a register address. */
1991 #define NO_FUNCTION_CSE 1
1993 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1994 return the mode to be used for the comparison.
1996 For floating-point equality comparisons, CCFPEQmode should be used.
1997 VOIDmode should be used in all other cases.
1999 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2000 possible, to allow for more combinations. */
2002 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2004 /* Return nonzero if MODE implies a floating point inequality can be
2005 reversed. */
2007 #define REVERSIBLE_CC_MODE(MODE) 1
2009 /* A C expression whose value is reversed condition code of the CODE for
2010 comparison done in CC_MODE mode. */
2011 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2014 /* Control the assembler format that we output, to the extent
2015 this does not vary between assemblers. */
2017 /* How to refer to registers in assembler output.
2018 This sequence is indexed by compiler's hard-register-number (see above). */
2020 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2021 For non floating point regs, the following are the HImode names.
2023 For float regs, the stack top is sometimes referred to as "%st(0)"
2024 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
2025 "y" code. */
2027 #define HI_REGISTER_NAMES \
2028 {"ax","dx","cx","bx","si","di","bp","sp", \
2029 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2030 "argp", "flags", "fpsr", "fpcr", "frame", \
2031 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2032 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2033 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2034 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
2035 "xmm16", "xmm17", "xmm18", "xmm19", \
2036 "xmm20", "xmm21", "xmm22", "xmm23", \
2037 "xmm24", "xmm25", "xmm26", "xmm27", \
2038 "xmm28", "xmm29", "xmm30", "xmm31", \
2039 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \
2040 "bnd0", "bnd1", "bnd2", "bnd3" }
2042 #define REGISTER_NAMES HI_REGISTER_NAMES
2044 /* Table of additional register names to use in user input. */
2046 #define ADDITIONAL_REGISTER_NAMES \
2047 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2048 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2049 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2050 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2051 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2052 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2053 { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \
2054 { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \
2055 { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \
2056 { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \
2057 { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \
2058 { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \
2059 { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \
2060 { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \
2061 { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \
2062 { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \
2063 { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \
2064 { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \
2065 { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \
2066 { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \
2067 { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \
2068 { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} }
2070 /* Note we are omitting these since currently I don't know how
2071 to get gcc to use these, since they want the same but different
2072 number as al, and ax.
2075 #define QI_REGISTER_NAMES \
2076 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2078 /* These parallel the array above, and can be used to access bits 8:15
2079 of regs 0 through 3. */
2081 #define QI_HIGH_REGISTER_NAMES \
2082 {"ah", "dh", "ch", "bh", }
2084 /* How to renumber registers for dbx and gdb. */
2086 #define DBX_REGISTER_NUMBER(N) \
2087 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2089 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2090 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2091 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2093 /* Before the prologue, RA is at 0(%esp). */
2094 #define INCOMING_RETURN_ADDR_RTX \
2095 gen_rtx_MEM (Pmode, stack_pointer_rtx)
2097 /* After the prologue, RA is at -4(AP) in the current frame. */
2098 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2099 ((COUNT) == 0 \
2100 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
2101 -UNITS_PER_WORD)) \
2102 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD)))
2104 /* PC is dbx register 8; let's use that column for RA. */
2105 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2107 /* Before the prologue, there are return address and error code for
2108 exception handler on the top of the frame. */
2109 #define INCOMING_FRAME_SP_OFFSET \
2110 (cfun->machine->func_type == TYPE_EXCEPTION \
2111 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD)
2113 /* Describe how we implement __builtin_eh_return. */
2114 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2115 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2118 /* Select a format to encode pointers in exception handling data. CODE
2119 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2120 true if the symbol may be affected by dynamic relocations.
2122 ??? All x86 object file formats are capable of representing this.
2123 After all, the relocation needed is the same as for the call insn.
2124 Whether or not a particular assembler allows us to enter such, I
2125 guess we'll have to see. */
2126 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2127 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2129 /* These are a couple of extensions to the formats accepted
2130 by asm_fprintf:
2131 %z prints out opcode suffix for word-mode instruction
2132 %r prints out word-mode name for reg_names[arg] */
2133 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
2134 case 'z': \
2135 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \
2136 break; \
2138 case 'r': \
2140 unsigned int regno = va_arg ((ARGS), int); \
2141 if (LEGACY_INT_REGNO_P (regno)) \
2142 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \
2143 fputs (reg_names[regno], (FILE)); \
2144 break; \
2147 /* This is how to output an insn to push a register on the stack. */
2149 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2150 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO))
2152 /* This is how to output an insn to pop a register from the stack. */
2154 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2155 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO))
2157 /* This is how to output an element of a case-vector that is absolute. */
2159 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2160 ix86_output_addr_vec_elt ((FILE), (VALUE))
2162 /* This is how to output an element of a case-vector that is relative. */
2164 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2165 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2167 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2169 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2171 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2172 (PTR) += TARGET_AVX ? 1 : 2; \
2175 /* A C statement or statements which output an assembler instruction
2176 opcode to the stdio stream STREAM. The macro-operand PTR is a
2177 variable of type `char *' which points to the opcode name in
2178 its "internal" form--the form that is written in the machine
2179 description. */
2181 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2182 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2184 /* A C statement to output to the stdio stream FILE an assembler
2185 command to pad the location counter to a multiple of 1<<LOG
2186 bytes if it is within MAX_SKIP bytes. */
2188 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2189 #undef ASM_OUTPUT_MAX_SKIP_PAD
2190 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2191 if ((LOG) != 0) \
2193 if ((MAX_SKIP) == 0) \
2194 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2195 else \
2196 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2198 #endif
2200 /* Write the extra assembler code needed to declare a function
2201 properly. */
2203 #undef ASM_OUTPUT_FUNCTION_LABEL
2204 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2205 ix86_asm_output_function_label ((FILE), (NAME), (DECL))
2207 /* Under some conditions we need jump tables in the text section,
2208 because the assembler cannot handle label differences between
2209 sections. This is the case for x86_64 on Mach-O for example. */
2211 #define JUMP_TABLES_IN_TEXT_SECTION \
2212 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2213 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2215 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2216 and switch back. For x86 we do this only to save a few bytes that
2217 would otherwise be unused in the text section. */
2218 #define CRT_MKSTR2(VAL) #VAL
2219 #define CRT_MKSTR(x) CRT_MKSTR2(x)
2221 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2222 asm (SECTION_OP "\n\t" \
2223 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2224 TEXT_SECTION_ASM_OP);
2226 /* Default threshold for putting data in large sections
2227 with x86-64 medium memory model */
2228 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2230 /* Adjust the length of the insn with the length of BND prefix. */
2232 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2233 do { \
2234 if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \
2235 && get_attr_maybe_prefix_bnd (INSN)) \
2236 LENGTH += ix86_bnd_prefixed_insn_p (INSN); \
2237 } while (0)
2239 /* Which processor to tune code generation for. These must be in sync
2240 with processor_target_table in i386.c. */
2242 enum processor_type
2244 PROCESSOR_GENERIC = 0,
2245 PROCESSOR_I386, /* 80386 */
2246 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2247 PROCESSOR_PENTIUM,
2248 PROCESSOR_LAKEMONT,
2249 PROCESSOR_PENTIUMPRO,
2250 PROCESSOR_PENTIUM4,
2251 PROCESSOR_NOCONA,
2252 PROCESSOR_CORE2,
2253 PROCESSOR_NEHALEM,
2254 PROCESSOR_SANDYBRIDGE,
2255 PROCESSOR_HASWELL,
2256 PROCESSOR_BONNELL,
2257 PROCESSOR_SILVERMONT,
2258 PROCESSOR_KNL,
2259 PROCESSOR_KNM,
2260 PROCESSOR_SKYLAKE_AVX512,
2261 PROCESSOR_CANNONLAKE,
2262 PROCESSOR_INTEL,
2263 PROCESSOR_GEODE,
2264 PROCESSOR_K6,
2265 PROCESSOR_ATHLON,
2266 PROCESSOR_K8,
2267 PROCESSOR_AMDFAM10,
2268 PROCESSOR_BDVER1,
2269 PROCESSOR_BDVER2,
2270 PROCESSOR_BDVER3,
2271 PROCESSOR_BDVER4,
2272 PROCESSOR_BTVER1,
2273 PROCESSOR_BTVER2,
2274 PROCESSOR_ZNVER1,
2275 PROCESSOR_max
2278 extern enum processor_type ix86_tune;
2279 extern enum processor_type ix86_arch;
2281 /* Size of the RED_ZONE area. */
2282 #define RED_ZONE_SIZE 128
2283 /* Reserved area of the red zone for temporaries. */
2284 #define RED_ZONE_RESERVE 8
2286 extern unsigned int ix86_preferred_stack_boundary;
2287 extern unsigned int ix86_incoming_stack_boundary;
2289 /* Smallest class containing REGNO. */
2290 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2292 enum ix86_fpcmp_strategy {
2293 IX86_FPCMP_SAHF,
2294 IX86_FPCMP_COMI,
2295 IX86_FPCMP_ARITH
2298 /* To properly truncate FP values into integers, we need to set i387 control
2299 word. We can't emit proper mode switching code before reload, as spills
2300 generated by reload may truncate values incorrectly, but we still can avoid
2301 redundant computation of new control word by the mode switching pass.
2302 The fldcw instructions are still emitted redundantly, but this is probably
2303 not going to be noticeable problem, as most CPUs do have fast path for
2304 the sequence.
2306 The machinery is to emit simple truncation instructions and split them
2307 before reload to instructions having USEs of two memory locations that
2308 are filled by this code to old and new control word.
2310 Post-reload pass may be later used to eliminate the redundant fildcw if
2311 needed. */
2313 enum ix86_stack_slot
2315 SLOT_TEMP = 0,
2316 SLOT_CW_STORED,
2317 SLOT_CW_TRUNC,
2318 SLOT_CW_FLOOR,
2319 SLOT_CW_CEIL,
2320 SLOT_CW_MASK_PM,
2321 SLOT_STV_TEMP,
2322 MAX_386_STACK_LOCALS
2325 enum ix86_entity
2327 X86_DIRFLAG = 0,
2328 AVX_U128,
2329 I387_TRUNC,
2330 I387_FLOOR,
2331 I387_CEIL,
2332 I387_MASK_PM,
2333 MAX_386_ENTITIES
2336 enum x86_dirflag_state
2338 X86_DIRFLAG_RESET,
2339 X86_DIRFLAG_ANY
2342 enum avx_u128_state
2344 AVX_U128_CLEAN,
2345 AVX_U128_DIRTY,
2346 AVX_U128_ANY
2349 /* Define this macro if the port needs extra instructions inserted
2350 for mode switching in an optimizing compilation. */
2352 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2353 ix86_optimize_mode_switching[(ENTITY)]
2355 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2356 initializer for an array of integers. Each initializer element N
2357 refers to an entity that needs mode switching, and specifies the
2358 number of different modes that might need to be set for this
2359 entity. The position of the initializer in the initializer -
2360 starting counting at zero - determines the integer that is used to
2361 refer to the mode-switched entity in question. */
2363 #define NUM_MODES_FOR_MODE_SWITCHING \
2364 { X86_DIRFLAG_ANY, AVX_U128_ANY, \
2365 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2368 /* Avoid renaming of stack registers, as doing so in combination with
2369 scheduling just increases amount of live registers at time and in
2370 the turn amount of fxch instructions needed.
2372 ??? Maybe Pentium chips benefits from renaming, someone can try....
2374 Don't rename evex to non-evex sse registers. */
2376 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2377 (!STACK_REGNO_P (SRC) \
2378 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET))
2381 #define FASTCALL_PREFIX '@'
2383 #ifndef USED_FOR_TARGET
2384 /* Structure describing stack frame layout.
2385 Stack grows downward:
2387 [arguments]
2388 <- ARG_POINTER
2389 saved pc
2391 saved static chain if ix86_static_chain_on_stack
2393 saved frame pointer if frame_pointer_needed
2394 <- HARD_FRAME_POINTER
2395 [saved regs]
2396 <- reg_save_offset
2397 [padding0]
2398 <- stack_realign_offset
2399 [saved SSE regs]
2401 [stub-saved registers for ms x64 --> sysv clobbers
2402 <- Start of out-of-line, stub-saved/restored regs
2403 (see libgcc/config/i386/(sav|res)ms64*.S)
2404 [XMM6-15]
2405 [RSI]
2406 [RDI]
2407 [?RBX] only if RBX is clobbered
2408 [?RBP] only if RBP and RBX are clobbered
2409 [?R12] only if R12 and all previous regs are clobbered
2410 [?R13] only if R13 and all previous regs are clobbered
2411 [?R14] only if R14 and all previous regs are clobbered
2412 [?R15] only if R15 and all previous regs are clobbered
2413 <- end of stub-saved/restored regs
2414 [padding1]
2416 <- sse_reg_save_offset
2417 [padding2]
2418 | <- FRAME_POINTER
2419 [va_arg registers] |
2421 [frame] |
2423 [padding2] | = to_allocate
2424 <- STACK_POINTER
2426 struct GTY(()) ix86_frame
2428 int nsseregs;
2429 int nregs;
2430 int va_arg_size;
2431 int red_zone_size;
2432 int outgoing_arguments_size;
2434 /* The offsets relative to ARG_POINTER. */
2435 HOST_WIDE_INT frame_pointer_offset;
2436 HOST_WIDE_INT hard_frame_pointer_offset;
2437 HOST_WIDE_INT stack_pointer_offset;
2438 HOST_WIDE_INT hfp_save_offset;
2439 HOST_WIDE_INT reg_save_offset;
2440 HOST_WIDE_INT stack_realign_allocate;
2441 HOST_WIDE_INT stack_realign_offset;
2442 HOST_WIDE_INT sse_reg_save_offset;
2444 /* When save_regs_using_mov is set, emit prologue using
2445 move instead of push instructions. */
2446 bool save_regs_using_mov;
2449 /* Machine specific frame tracking during prologue/epilogue generation. All
2450 values are positive, but since the x86 stack grows downward, are subtratced
2451 from the CFA to produce a valid address. */
2453 struct GTY(()) machine_frame_state
2455 /* This pair tracks the currently active CFA as reg+offset. When reg
2456 is drap_reg, we don't bother trying to record here the real CFA when
2457 it might really be a DW_CFA_def_cfa_expression. */
2458 rtx cfa_reg;
2459 HOST_WIDE_INT cfa_offset;
2461 /* The current offset (canonically from the CFA) of ESP and EBP.
2462 When stack frame re-alignment is active, these may not be relative
2463 to the CFA. However, in all cases they are relative to the offsets
2464 of the saved registers stored in ix86_frame. */
2465 HOST_WIDE_INT sp_offset;
2466 HOST_WIDE_INT fp_offset;
2468 /* The size of the red-zone that may be assumed for the purposes of
2469 eliding register restore notes in the epilogue. This may be zero
2470 if no red-zone is in effect, or may be reduced from the real
2471 red-zone value by a maximum runtime stack re-alignment value. */
2472 int red_zone_offset;
2474 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2475 value within the frame. If false then the offset above should be
2476 ignored. Note that DRAP, if valid, *always* points to the CFA and
2477 thus has an offset of zero. */
2478 BOOL_BITFIELD sp_valid : 1;
2479 BOOL_BITFIELD fp_valid : 1;
2480 BOOL_BITFIELD drap_valid : 1;
2482 /* Indicate whether the local stack frame has been re-aligned. When
2483 set, the SP/FP offsets above are relative to the aligned frame
2484 and not the CFA. */
2485 BOOL_BITFIELD realigned : 1;
2487 /* Indicates whether the stack pointer has been re-aligned. When set,
2488 SP/FP continue to be relative to the CFA, but the stack pointer
2489 should only be used for offsets > sp_realigned_offset, while
2490 the frame pointer should be used for offsets <= sp_realigned_fp_last.
2491 The flags realigned and sp_realigned are mutually exclusive. */
2492 BOOL_BITFIELD sp_realigned : 1;
2494 /* If sp_realigned is set, this is the last valid offset from the CFA
2495 that can be used for access with the frame pointer. */
2496 HOST_WIDE_INT sp_realigned_fp_last;
2498 /* If sp_realigned is set, this is the offset from the CFA that the stack
2499 pointer was realigned, and may or may not be equal to sp_realigned_fp_last.
2500 Access via the stack pointer is only valid for offsets that are greater than
2501 this value. */
2502 HOST_WIDE_INT sp_realigned_offset;
2505 /* Private to winnt.c. */
2506 struct seh_frame_state;
2508 enum function_type
2510 TYPE_UNKNOWN = 0,
2511 TYPE_NORMAL,
2512 /* The current function is an interrupt service routine with a
2513 pointer argument as specified by the "interrupt" attribute. */
2514 TYPE_INTERRUPT,
2515 /* The current function is an interrupt service routine with a
2516 pointer argument and an integer argument as specified by the
2517 "interrupt" attribute. */
2518 TYPE_EXCEPTION
2521 struct GTY(()) machine_function {
2522 struct stack_local_entry *stack_locals;
2523 int varargs_gpr_size;
2524 int varargs_fpr_size;
2525 int optimize_mode_switching[MAX_386_ENTITIES];
2527 /* Cached initial frame layout for the current function. */
2528 struct ix86_frame frame;
2530 /* For -fsplit-stack support: A stack local which holds a pointer to
2531 the stack arguments for a function with a variable number of
2532 arguments. This is set at the start of the function and is used
2533 to initialize the overflow_arg_area field of the va_list
2534 structure. */
2535 rtx split_stack_varargs_pointer;
2537 /* This value is used for amd64 targets and specifies the current abi
2538 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2539 ENUM_BITFIELD(calling_abi) call_abi : 8;
2541 /* Nonzero if the function accesses a previous frame. */
2542 BOOL_BITFIELD accesses_prev_frame : 1;
2544 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2545 expander to determine the style used. */
2546 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2548 /* Nonzero if the current function calls pc thunk and
2549 must not use the red zone. */
2550 BOOL_BITFIELD pc_thunk_call_expanded : 1;
2552 /* If true, the current function needs the default PIC register, not
2553 an alternate register (on x86) and must not use the red zone (on
2554 x86_64), even if it's a leaf function. We don't want the
2555 function to be regarded as non-leaf because TLS calls need not
2556 affect register allocation. This flag is set when a TLS call
2557 instruction is expanded within a function, and never reset, even
2558 if all such instructions are optimized away. Use the
2559 ix86_current_function_calls_tls_descriptor macro for a better
2560 approximation. */
2561 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2563 /* If true, the current function has a STATIC_CHAIN is placed on the
2564 stack below the return address. */
2565 BOOL_BITFIELD static_chain_on_stack : 1;
2567 /* If true, it is safe to not save/restore DRAP register. */
2568 BOOL_BITFIELD no_drap_save_restore : 1;
2570 /* Function type. */
2571 ENUM_BITFIELD(function_type) func_type : 2;
2573 /* If true, the current function is a function specified with
2574 the "interrupt" or "no_caller_saved_registers" attribute. */
2575 BOOL_BITFIELD no_caller_saved_registers : 1;
2577 /* If true, there is register available for argument passing. This
2578 is used only in ix86_function_ok_for_sibcall by 32-bit to determine
2579 if there is scratch register available for indirect sibcall. In
2580 64-bit, rax, r10 and r11 are scratch registers which aren't used to
2581 pass arguments and can be used for indirect sibcall. */
2582 BOOL_BITFIELD arg_reg_available : 1;
2584 /* If true, we're out-of-lining reg save/restore for regs clobbered
2585 by 64-bit ms_abi functions calling a sysv_abi function. */
2586 BOOL_BITFIELD call_ms2sysv : 1;
2588 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and
2589 needs padding prior to out-of-line stub save/restore area. */
2590 BOOL_BITFIELD call_ms2sysv_pad_in : 1;
2592 /* This is the number of extra registers saved by stub (valid range is
2593 0-6). Each additional register is only saved/restored by the stubs
2594 if all successive ones are. (Will always be zero when using a hard
2595 frame pointer.) */
2596 unsigned int call_ms2sysv_extra_regs:3;
2598 /* Nonzero if the function places outgoing arguments on stack. */
2599 BOOL_BITFIELD outgoing_args_on_stack : 1;
2601 /* During prologue/epilogue generation, the current frame state.
2602 Otherwise, the frame state at the end of the prologue. */
2603 struct machine_frame_state fs;
2605 /* During SEH output, this is non-null. */
2606 struct seh_frame_state * GTY((skip(""))) seh;
2608 #endif
2610 #define ix86_stack_locals (cfun->machine->stack_locals)
2611 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2612 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2613 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2614 #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded)
2615 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2616 (cfun->machine->tls_descriptor_call_expanded_p)
2617 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2618 calls are optimized away, we try to detect cases in which it was
2619 optimized away. Since such instructions (use (reg REG_SP)), we can
2620 verify whether there's any such instruction live by testing that
2621 REG_SP is live. */
2622 #define ix86_current_function_calls_tls_descriptor \
2623 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2624 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2625 #define ix86_red_zone_size (cfun->machine->frame.red_zone_size)
2627 /* Control behavior of x86_file_start. */
2628 #define X86_FILE_START_VERSION_DIRECTIVE false
2629 #define X86_FILE_START_FLTUSED false
2631 /* Flag to mark data that is in the large address area. */
2632 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2633 #define SYMBOL_REF_FAR_ADDR_P(X) \
2634 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2636 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2637 have defined always, to avoid ifdefing. */
2638 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2639 #define SYMBOL_REF_DLLIMPORT_P(X) \
2640 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2642 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2643 #define SYMBOL_REF_DLLEXPORT_P(X) \
2644 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2646 #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
2647 #define SYMBOL_REF_STUBVAR_P(X) \
2648 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
2650 extern void debug_ready_dispatch (void);
2651 extern void debug_dispatch_window (int);
2653 /* The value at zero is only defined for the BMI instructions
2654 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2655 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2656 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0)
2657 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2658 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0)
2661 /* Flags returned by ix86_get_callcvt (). */
2662 #define IX86_CALLCVT_CDECL 0x1
2663 #define IX86_CALLCVT_STDCALL 0x2
2664 #define IX86_CALLCVT_FASTCALL 0x4
2665 #define IX86_CALLCVT_THISCALL 0x8
2666 #define IX86_CALLCVT_REGPARM 0x10
2667 #define IX86_CALLCVT_SSEREGPARM 0x20
2669 #define IX86_BASE_CALLCVT(FLAGS) \
2670 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2671 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2673 #define RECIP_MASK_NONE 0x00
2674 #define RECIP_MASK_DIV 0x01
2675 #define RECIP_MASK_SQRT 0x02
2676 #define RECIP_MASK_VEC_DIV 0x04
2677 #define RECIP_MASK_VEC_SQRT 0x08
2678 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2679 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2680 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2682 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2683 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2684 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2685 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2687 /* Use 128-bit AVX instructions in the auto-vectorizer. */
2688 #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
2689 /* Use 256-bit AVX instructions in the auto-vectorizer. */
2690 #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \
2691 || prefer_vector_width_type == PVW_AVX256)
2693 #define IX86_HLE_ACQUIRE (1 << 16)
2694 #define IX86_HLE_RELEASE (1 << 17)
2696 /* For switching between functions with different target attributes. */
2697 #define SWITCHABLE_TARGET 1
2699 #define TARGET_SUPPORTS_WIDE_INT 1
2702 Local variables:
2703 version-control: t
2704 End: