1 /* { dg-do compile { target { powerpc*-*-* } } } */
2 /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
3 /* { dg-require-effective-target powerpc_p8vector_ok } */
4 /* { dg-options "-O2 -mcpu=power8" } */
5 /* { dg-final { scan-assembler-not "\[ \t\]and " } } */
6 /* { dg-final { scan-assembler-not "\[ \t\]or " } } */
7 /* { dg-final { scan-assembler-not "\[ \t\]xor " } } */
8 /* { dg-final { scan-assembler-not "\[ \t\]nor " } } */
9 /* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */
10 /* { dg-final { scan-assembler-not "\[ \t\]andc " } } */
11 /* { dg-final { scan-assembler-not "\[ \t\]orc " } } */
12 /* { dg-final { scan-assembler-not "\[ \t\]nand " } } */
13 /* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
14 /* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
15 /* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
16 /* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
17 /* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
18 /* { dg-final { scan-assembler "\[ \t\]xxland " } } */
19 /* { dg-final { scan-assembler "\[ \t\]xxlor " } } */
20 /* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */
21 /* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */
22 /* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */
23 /* { dg-final { scan-assembler "\[ \t\]xxleqv " } } */
24 /* { dg-final { scan-assembler "\[ \t\]xxlorc " } } */
25 /* { dg-final { scan-assembler "\[ \t\]xxlnand " } } */
28 typedef int v4si
__attribute__ ((vector_size (16)));