1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
52 (UNSPEC_CLEAR_HAZARD 33)
56 (UNSPEC_COMPARE_AND_SWAP 37)
57 (UNSPEC_SYNC_OLD_OP 38)
58 (UNSPEC_SYNC_NEW_OP 39)
59 (UNSPEC_SYNC_EXCHANGE 40)
60 (UNSPEC_MEMORY_BARRIER 41)
61 (UNSPEC_SET_GOT_VERSION 42)
62 (UNSPEC_UPDATE_GOT_VERSION 43)
64 (UNSPEC_ADDRESS_FIRST 100)
66 (GOT_VERSION_REGNUM 79)
68 ;; For MIPS Paired-Singled Floating Point Instructions.
70 (UNSPEC_MOVE_TF_PS 200)
73 ;; MIPS64/MIPS32R2 alnv.ps
76 ;; MIPS-3D instructions
80 (UNSPEC_CVT_PW_PS 205)
81 (UNSPEC_CVT_PS_PW 206)
89 (UNSPEC_SINGLE_CC 213)
92 ;; MIPS DSP ASE Revision 0.98 3/24/2005
100 (UNSPEC_RADDU_W_QB 307)
102 (UNSPEC_PRECRQ_QB_PH 309)
103 (UNSPEC_PRECRQ_PH_W 310)
104 (UNSPEC_PRECRQ_RS_PH_W 311)
105 (UNSPEC_PRECRQU_S_QB_PH 312)
106 (UNSPEC_PRECEQ_W_PHL 313)
107 (UNSPEC_PRECEQ_W_PHR 314)
108 (UNSPEC_PRECEQU_PH_QBL 315)
109 (UNSPEC_PRECEQU_PH_QBR 316)
110 (UNSPEC_PRECEQU_PH_QBLA 317)
111 (UNSPEC_PRECEQU_PH_QBRA 318)
112 (UNSPEC_PRECEU_PH_QBL 319)
113 (UNSPEC_PRECEU_PH_QBR 320)
114 (UNSPEC_PRECEU_PH_QBLA 321)
115 (UNSPEC_PRECEU_PH_QBRA 322)
121 (UNSPEC_MULEU_S_PH_QBL 328)
122 (UNSPEC_MULEU_S_PH_QBR 329)
123 (UNSPEC_MULQ_RS_PH 330)
124 (UNSPEC_MULEQ_S_W_PHL 331)
125 (UNSPEC_MULEQ_S_W_PHR 332)
126 (UNSPEC_DPAU_H_QBL 333)
127 (UNSPEC_DPAU_H_QBR 334)
128 (UNSPEC_DPSU_H_QBL 335)
129 (UNSPEC_DPSU_H_QBR 336)
130 (UNSPEC_DPAQ_S_W_PH 337)
131 (UNSPEC_DPSQ_S_W_PH 338)
132 (UNSPEC_MULSAQ_S_W_PH 339)
133 (UNSPEC_DPAQ_SA_L_W 340)
134 (UNSPEC_DPSQ_SA_L_W 341)
135 (UNSPEC_MAQ_S_W_PHL 342)
136 (UNSPEC_MAQ_S_W_PHR 343)
137 (UNSPEC_MAQ_SA_W_PHL 344)
138 (UNSPEC_MAQ_SA_W_PHR 345)
146 (UNSPEC_CMPGU_EQ_QB 353)
147 (UNSPEC_CMPGU_LT_QB 354)
148 (UNSPEC_CMPGU_LE_QB 355)
150 (UNSPEC_PACKRL_PH 357)
152 (UNSPEC_EXTR_R_W 359)
153 (UNSPEC_EXTR_RS_W 360)
154 (UNSPEC_EXTR_S_H 361)
162 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
163 (UNSPEC_ABSQ_S_QB 400)
165 (UNSPEC_ADDU_S_PH 402)
166 (UNSPEC_ADDUH_QB 403)
167 (UNSPEC_ADDUH_R_QB 404)
170 (UNSPEC_CMPGDU_EQ_QB 407)
171 (UNSPEC_CMPGDU_LT_QB 408)
172 (UNSPEC_CMPGDU_LE_QB 409)
173 (UNSPEC_DPA_W_PH 410)
174 (UNSPEC_DPS_W_PH 411)
180 (UNSPEC_MUL_S_PH 417)
181 (UNSPEC_MULQ_RS_W 418)
182 (UNSPEC_MULQ_S_PH 419)
183 (UNSPEC_MULQ_S_W 420)
184 (UNSPEC_MULSA_W_PH 421)
187 (UNSPEC_PRECR_QB_PH 424)
188 (UNSPEC_PRECR_SRA_PH_W 425)
189 (UNSPEC_PRECR_SRA_R_PH_W 426)
192 (UNSPEC_SHRA_R_QB 429)
195 (UNSPEC_SUBU_S_PH 432)
196 (UNSPEC_SUBUH_QB 433)
197 (UNSPEC_SUBUH_R_QB 434)
198 (UNSPEC_ADDQH_PH 435)
199 (UNSPEC_ADDQH_R_PH 436)
201 (UNSPEC_ADDQH_R_W 438)
202 (UNSPEC_SUBQH_PH 439)
203 (UNSPEC_SUBQH_R_PH 440)
205 (UNSPEC_SUBQH_R_W 442)
206 (UNSPEC_DPAX_W_PH 443)
207 (UNSPEC_DPSX_W_PH 444)
208 (UNSPEC_DPAQX_S_W_PH 445)
209 (UNSPEC_DPAQX_SA_W_PH 446)
210 (UNSPEC_DPSQX_S_W_PH 447)
211 (UNSPEC_DPSQX_SA_W_PH 448)
215 (include "predicates.md")
216 (include "constraints.md")
218 ;; ....................
222 ;; ....................
224 (define_attr "got" "unset,xgot_high,load"
225 (const_string "unset"))
227 ;; For jal instructions, this attribute is DIRECT when the target address
228 ;; is symbolic and INDIRECT when it is a register.
229 (define_attr "jal" "unset,direct,indirect"
230 (const_string "unset"))
232 ;; This attribute is YES if the instruction is a jal macro (not a
233 ;; real jal instruction).
235 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
236 ;; an instruction to restore $gp. Direct jals are also macros for
237 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
238 ;; the target address into a register.
239 (define_attr "jal_macro" "no,yes"
240 (cond [(eq_attr "jal" "direct")
241 (symbol_ref "TARGET_CALL_CLOBBERED_GP
242 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
243 (eq_attr "jal" "indirect")
244 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
245 (const_string "no")))
247 ;; Classification of each insn.
248 ;; branch conditional branch
249 ;; jump unconditional jump
250 ;; call unconditional call
251 ;; load load instruction(s)
252 ;; fpload floating point load
253 ;; fpidxload floating point indexed load
254 ;; store store instruction(s)
255 ;; fpstore floating point store
256 ;; fpidxstore floating point indexed store
257 ;; prefetch memory prefetch (register + offset)
258 ;; prefetchx memory indexed prefetch (register + register)
259 ;; condmove conditional moves
260 ;; mfc transfer from coprocessor
261 ;; mtc transfer to coprocessor
262 ;; mthilo transfer to hi/lo registers
263 ;; mfhilo transfer from hi/lo registers
264 ;; const load constant
265 ;; arith integer arithmetic instructions
266 ;; logical integer logical instructions
267 ;; shift integer shift instructions
268 ;; slt set less than instructions
269 ;; signext sign extend instructions
270 ;; clz the clz and clo instructions
271 ;; trap trap if instructions
272 ;; imul integer multiply 2 operands
273 ;; imul3 integer multiply 3 operands
274 ;; imadd integer multiply-add
275 ;; idiv integer divide
276 ;; move integer register move ({,D}ADD{,U} with rt = 0)
277 ;; fmove floating point register move
278 ;; fadd floating point add/subtract
279 ;; fmul floating point multiply
280 ;; fmadd floating point multiply-add
281 ;; fdiv floating point divide
282 ;; frdiv floating point reciprocal divide
283 ;; frdiv1 floating point reciprocal divide step 1
284 ;; frdiv2 floating point reciprocal divide step 2
285 ;; fabs floating point absolute value
286 ;; fneg floating point negation
287 ;; fcmp floating point compare
288 ;; fcvt floating point convert
289 ;; fsqrt floating point square root
290 ;; frsqrt floating point reciprocal square root
291 ;; frsqrt1 floating point reciprocal square root step1
292 ;; frsqrt2 floating point reciprocal square root step2
293 ;; multi multiword sequence (or user asm statements)
295 ;; ghost an instruction that produces no real code
297 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
298 (cond [(eq_attr "jal" "!unset") (const_string "call")
299 (eq_attr "got" "load") (const_string "load")]
300 (const_string "unknown")))
302 ;; Main data type used by the insn
303 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
304 (const_string "unknown"))
306 ;; Mode for conversion types (fcvt)
307 ;; I2S integer to float single (SI/DI to SF)
308 ;; I2D integer to float double (SI/DI to DF)
309 ;; S2I float to integer (SF to SI/DI)
310 ;; D2I float to integer (DF to SI/DI)
311 ;; D2S double to float single
312 ;; S2D float single to double
314 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
315 (const_string "unknown"))
317 ;; Is this an extended instruction in mips16 mode?
318 (define_attr "extended_mips16" "no,yes"
321 ;; Length of instruction in bytes.
322 (define_attr "length" ""
323 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
324 ;; If a branch is outside this range, we have a choice of two
325 ;; sequences. For PIC, an out-of-range branch like:
330 ;; becomes the equivalent of:
339 ;; where the load address can be up to three instructions long
342 ;; The non-PIC case is similar except that we use a direct
343 ;; jump instead of an la/jr pair. Since the target of this
344 ;; jump is an absolute 28-bit bit address (the other bits
345 ;; coming from the address of the delay slot) this form cannot
346 ;; cross a 256MB boundary. We could provide the option of
347 ;; using la/jr in this case too, but we do not do so at
350 ;; Note that this value does not account for the delay slot
351 ;; instruction, whose length is added separately. If the RTL
352 ;; pattern has no explicit delay slot, mips_adjust_insn_length
353 ;; will add the length of the implicit nop. The values for
354 ;; forward and backward branches will be different as well.
355 (eq_attr "type" "branch")
356 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
357 (le (minus (pc) (match_dup 1)) (const_int 131068)))
359 (ne (symbol_ref "flag_pic") (const_int 0))
363 (eq_attr "got" "load")
365 (eq_attr "got" "xgot_high")
368 (eq_attr "type" "const")
369 (symbol_ref "mips_const_insns (operands[1]) * 4")
370 (eq_attr "type" "load,fpload")
371 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
372 (eq_attr "type" "store,fpstore")
373 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
375 ;; In the worst case, a call macro will take 8 instructions:
377 ;; lui $25,%call_hi(FOO)
379 ;; lw $25,%call_lo(FOO)($25)
385 (eq_attr "jal_macro" "yes")
388 (and (eq_attr "extended_mips16" "yes")
389 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
392 ;; Various VR4120 errata require a nop to be inserted after a macc
393 ;; instruction. The assembler does this for us, so account for
394 ;; the worst-case length here.
395 (and (eq_attr "type" "imadd")
396 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
399 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
400 ;; the result of the second one is missed. The assembler should work
401 ;; around this by inserting a nop after the first dmult.
402 (and (eq_attr "type" "imul,imul3")
403 (and (eq_attr "mode" "DI")
404 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
407 (eq_attr "type" "idiv")
408 (symbol_ref "mips_idiv_insns () * 4")
411 ;; Attribute describing the processor. This attribute must match exactly
412 ;; with the processor_type enumeration in mips.h.
414 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
415 (const (symbol_ref "mips_tune")))
417 ;; The type of hardware hazard associated with this instruction.
418 ;; DELAY means that the next instruction cannot read the result
419 ;; of this one. HILO means that the next two instructions cannot
420 ;; write to HI or LO.
421 (define_attr "hazard" "none,delay,hilo"
422 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
423 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
424 (const_string "delay")
426 (and (eq_attr "type" "mfc,mtc")
427 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
428 (const_string "delay")
430 (and (eq_attr "type" "fcmp")
431 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
432 (const_string "delay")
434 ;; The r4000 multiplication patterns include an mflo instruction.
435 (and (eq_attr "type" "imul")
436 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
437 (const_string "hilo")
439 (and (eq_attr "type" "mfhilo")
440 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
441 (const_string "hilo")]
442 (const_string "none")))
444 ;; Is it a single instruction?
445 (define_attr "single_insn" "no,yes"
446 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
448 ;; Can the instruction be put into a delay slot?
449 (define_attr "can_delay" "no,yes"
450 (if_then_else (and (eq_attr "type" "!branch,call,jump")
451 (and (eq_attr "hazard" "none")
452 (eq_attr "single_insn" "yes")))
454 (const_string "no")))
456 ;; Attribute defining whether or not we can use the branch-likely instructions
457 (define_attr "branch_likely" "no,yes"
459 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
461 (const_string "no"))))
463 ;; True if an instruction might assign to hi or lo when reloaded.
464 ;; This is used by the TUNE_MACC_CHAINS code.
465 (define_attr "may_clobber_hilo" "no,yes"
466 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
468 (const_string "no")))
470 ;; Describe a user's asm statement.
471 (define_asm_attributes
472 [(set_attr "type" "multi")
473 (set_attr "can_delay" "no")])
475 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
476 ;; from the same template.
477 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
479 ;; This mode iterator allows :P to be used for patterns that operate on
480 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
481 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
483 ;; This mode iterator allows :MOVECC to be used anywhere that a
484 ;; conditional-move-type condition is needed.
485 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
487 ;; 64-bit modes for which we provide move patterns.
488 (define_mode_iterator MOVE64
489 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
491 ;; This mode iterator allows the QI and HI extension patterns to be
492 ;; defined from the same template.
493 (define_mode_iterator SHORT [QI HI])
495 ;; Likewise the 64-bit truncate-and-shift patterns.
496 (define_mode_iterator SUBDI [QI HI SI])
498 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
499 ;; floating-point mode is allowed.
500 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
501 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
502 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
504 ;; Like ANYF, but only applies to scalar modes.
505 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
506 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
508 ;; A floating-point mode for which moves involving FPRs may need to be split.
509 (define_mode_iterator SPLITF
510 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
511 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
512 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
513 (TF "TARGET_64BIT && TARGET_FLOAT64")])
515 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
516 ;; 32-bit version and "dsubu" in the 64-bit version.
517 (define_mode_attr d [(SI "") (DI "d")
518 (QQ "") (HQ "") (SQ "") (DQ "d")
519 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
520 (HA "") (SA "") (DA "d")
521 (UHA "") (USA "") (UDA "d")])
523 ;; This attribute gives the length suffix for a sign- or zero-extension
525 (define_mode_attr size [(QI "b") (HI "h")])
527 ;; This attributes gives the mode mask of a SHORT.
528 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
530 ;; Mode attributes for GPR loads and stores.
531 (define_mode_attr load [(SI "lw") (DI "ld")])
532 (define_mode_attr store [(SI "sw") (DI "sd")])
534 ;; Similarly for MIPS IV indexed FPR loads and stores.
535 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
536 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
538 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
539 ;; are different. Some forms of unextended addiu have an 8-bit immediate
540 ;; field but the equivalent daddiu has only a 5-bit field.
541 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
543 ;; This attribute gives the best constraint to use for registers of
545 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
547 ;; This attribute gives the format suffix for floating-point operations.
548 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
550 ;; This attribute gives the upper-case mode name for one unit of a
551 ;; floating-point mode.
552 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
554 ;; This attribute gives the integer mode that has the same size as a
556 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
557 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
558 (HA "HI") (SA "SI") (DA "DI")
559 (UHA "HI") (USA "SI") (UDA "DI")
560 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
561 (V2HQ "SI") (V2HA "SI")])
563 ;; This attribute gives the integer mode that has half the size of
564 ;; the controlling mode.
565 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI") (TF "DI")])
567 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
569 ;; In certain cases, div.s and div.ps may have a rounding error
570 ;; and/or wrong inexact flag.
572 ;; Therefore, we only allow div.s if not working around SB-1 rev2
573 ;; errata or if a slight loss of precision is OK.
574 (define_mode_attr divide_condition
575 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
576 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
578 ;; This attribute gives the conditions under which SQRT.fmt instructions
580 (define_mode_attr sqrt_condition
581 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
583 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
584 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
585 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
586 ;; so for safety's sake, we apply this restriction to all targets.
587 (define_mode_attr recip_condition
589 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
590 (V2SF "TARGET_SB1")])
592 ;; This code iterator allows all branch instructions to be generated from
593 ;; a single define_expand template.
594 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
595 eq ne gt ge lt le gtu geu ltu leu])
597 ;; This code iterator allows signed and unsigned widening multiplications
598 ;; to use the same template.
599 (define_code_iterator any_extend [sign_extend zero_extend])
601 ;; This code iterator allows the three shift instructions to be generated
602 ;; from the same template.
603 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
605 ;; This code iterator allows all native floating-point comparisons to be
606 ;; generated from the same template.
607 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
609 ;; This code iterator is used for comparisons that can be implemented
610 ;; by swapping the operands.
611 (define_code_iterator swapped_fcond [ge gt unge ungt])
613 ;; <u> expands to an empty string when doing a signed operation and
614 ;; "u" when doing an unsigned operation.
615 (define_code_attr u [(sign_extend "") (zero_extend "u")])
617 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
618 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
620 ;; <optab> expands to the name of the optab for a particular code.
621 (define_code_attr optab [(ashift "ashl")
628 ;; <insn> expands to the name of the insn that implements a particular code.
629 (define_code_attr insn [(ashift "sll")
636 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
637 (define_code_attr fcond [(unordered "un")
645 ;; Similar, but for swapped conditions.
646 (define_code_attr swapped_fcond [(ge "le")
651 ;; Atomic fetch bitwise operations.
652 (define_code_iterator fetchop_bit [ior xor and])
654 ;; <immediate_insn> expands to the name of the insn that implements
655 ;; a particular code to operate in immediate values.
656 (define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
659 ;; .........................
661 ;; Branch, call and jump delay slots
663 ;; .........................
665 (define_delay (and (eq_attr "type" "branch")
666 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
667 [(eq_attr "can_delay" "yes")
669 (and (eq_attr "branch_likely" "yes")
670 (eq_attr "can_delay" "yes"))])
672 (define_delay (eq_attr "type" "jump")
673 [(eq_attr "can_delay" "yes")
677 (define_delay (and (eq_attr "type" "call")
678 (eq_attr "jal_macro" "no"))
679 [(eq_attr "can_delay" "yes")
683 ;; Pipeline descriptions.
685 ;; generic.md provides a fallback for processors without a specific
686 ;; pipeline description. It is derived from the old define_function_unit
687 ;; version and uses the "alu" and "imuldiv" units declared below.
689 ;; Some of the processor-specific files are also derived from old
690 ;; define_function_unit descriptions and simply override the parts of
691 ;; generic.md that don't apply. The other processor-specific files
692 ;; are self-contained.
693 (define_automaton "alu,imuldiv")
695 (define_cpu_unit "alu" "alu")
696 (define_cpu_unit "imuldiv" "imuldiv")
698 ;; Ghost instructions produce no real code and introduce no hazards.
699 ;; They exist purely to express an effect on dataflow.
700 (define_insn_reservation "ghost" 0
701 (eq_attr "type" "ghost")
723 (include "generic.md")
726 ;; ....................
730 ;; ....................
734 [(trap_if (const_int 1) (const_int 0))]
737 if (ISA_HAS_COND_TRAP)
739 else if (TARGET_MIPS16)
744 [(set_attr "type" "trap")])
746 (define_expand "conditional_trap"
747 [(trap_if (match_operator 0 "comparison_operator"
748 [(match_dup 2) (match_dup 3)])
749 (match_operand 1 "const_int_operand"))]
752 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
753 && operands[1] == const0_rtx)
755 mips_expand_conditional_trap (GET_CODE (operands[0]));
761 (define_insn "*conditional_trap<mode>"
762 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
763 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
764 (match_operand:GPR 2 "arith_operand" "dI")])
768 [(set_attr "type" "trap")])
771 ;; ....................
775 ;; ....................
778 (define_insn "add<mode>3"
779 [(set (match_operand:ANYF 0 "register_operand" "=f")
780 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
781 (match_operand:ANYF 2 "register_operand" "f")))]
783 "add.<fmt>\t%0,%1,%2"
784 [(set_attr "type" "fadd")
785 (set_attr "mode" "<UNITMODE>")])
787 (define_expand "add<mode>3"
788 [(set (match_operand:GPR 0 "register_operand")
789 (plus:GPR (match_operand:GPR 1 "register_operand")
790 (match_operand:GPR 2 "arith_operand")))]
793 (define_insn "*add<mode>3"
794 [(set (match_operand:GPR 0 "register_operand" "=d,d")
795 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
796 (match_operand:GPR 2 "arith_operand" "d,Q")))]
801 [(set_attr "type" "arith")
802 (set_attr "mode" "<MODE>")])
804 (define_insn "*add<mode>3_mips16"
805 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
806 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
807 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
815 [(set_attr "type" "arith")
816 (set_attr "mode" "<MODE>")
817 (set_attr_alternative "length"
818 [(if_then_else (match_operand 2 "m16_simm8_8")
821 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
824 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
827 (if_then_else (match_operand 2 "m16_simm4_1")
832 ;; On the mips16, we can sometimes split an add of a constant which is
833 ;; a 4 byte instruction into two adds which are both 2 byte
834 ;; instructions. There are two cases: one where we are adding a
835 ;; constant plus a register to another register, and one where we are
836 ;; simply adding a constant to a register.
839 [(set (match_operand:SI 0 "register_operand")
840 (plus:SI (match_dup 0)
841 (match_operand:SI 1 "const_int_operand")))]
842 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
843 && REG_P (operands[0])
844 && M16_REG_P (REGNO (operands[0]))
845 && GET_CODE (operands[1]) == CONST_INT
846 && ((INTVAL (operands[1]) > 0x7f
847 && INTVAL (operands[1]) <= 0x7f + 0x7f)
848 || (INTVAL (operands[1]) < - 0x80
849 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
850 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
851 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
853 HOST_WIDE_INT val = INTVAL (operands[1]);
857 operands[1] = GEN_INT (0x7f);
858 operands[2] = GEN_INT (val - 0x7f);
862 operands[1] = GEN_INT (- 0x80);
863 operands[2] = GEN_INT (val + 0x80);
868 [(set (match_operand:SI 0 "register_operand")
869 (plus:SI (match_operand:SI 1 "register_operand")
870 (match_operand:SI 2 "const_int_operand")))]
871 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
872 && REG_P (operands[0])
873 && M16_REG_P (REGNO (operands[0]))
874 && REG_P (operands[1])
875 && M16_REG_P (REGNO (operands[1]))
876 && REGNO (operands[0]) != REGNO (operands[1])
877 && GET_CODE (operands[2]) == CONST_INT
878 && ((INTVAL (operands[2]) > 0x7
879 && INTVAL (operands[2]) <= 0x7 + 0x7f)
880 || (INTVAL (operands[2]) < - 0x8
881 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
882 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
883 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
885 HOST_WIDE_INT val = INTVAL (operands[2]);
889 operands[2] = GEN_INT (0x7);
890 operands[3] = GEN_INT (val - 0x7);
894 operands[2] = GEN_INT (- 0x8);
895 operands[3] = GEN_INT (val + 0x8);
900 [(set (match_operand:DI 0 "register_operand")
901 (plus:DI (match_dup 0)
902 (match_operand:DI 1 "const_int_operand")))]
903 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
904 && REG_P (operands[0])
905 && M16_REG_P (REGNO (operands[0]))
906 && GET_CODE (operands[1]) == CONST_INT
907 && ((INTVAL (operands[1]) > 0xf
908 && INTVAL (operands[1]) <= 0xf + 0xf)
909 || (INTVAL (operands[1]) < - 0x10
910 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
911 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
912 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
914 HOST_WIDE_INT val = INTVAL (operands[1]);
918 operands[1] = GEN_INT (0xf);
919 operands[2] = GEN_INT (val - 0xf);
923 operands[1] = GEN_INT (- 0x10);
924 operands[2] = GEN_INT (val + 0x10);
929 [(set (match_operand:DI 0 "register_operand")
930 (plus:DI (match_operand:DI 1 "register_operand")
931 (match_operand:DI 2 "const_int_operand")))]
932 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
933 && REG_P (operands[0])
934 && M16_REG_P (REGNO (operands[0]))
935 && REG_P (operands[1])
936 && M16_REG_P (REGNO (operands[1]))
937 && REGNO (operands[0]) != REGNO (operands[1])
938 && GET_CODE (operands[2]) == CONST_INT
939 && ((INTVAL (operands[2]) > 0x7
940 && INTVAL (operands[2]) <= 0x7 + 0xf)
941 || (INTVAL (operands[2]) < - 0x8
942 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
943 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
944 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
946 HOST_WIDE_INT val = INTVAL (operands[2]);
950 operands[2] = GEN_INT (0x7);
951 operands[3] = GEN_INT (val - 0x7);
955 operands[2] = GEN_INT (- 0x8);
956 operands[3] = GEN_INT (val + 0x8);
960 (define_insn "*addsi3_extended"
961 [(set (match_operand:DI 0 "register_operand" "=d,d")
963 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
964 (match_operand:SI 2 "arith_operand" "d,Q"))))]
965 "TARGET_64BIT && !TARGET_MIPS16"
969 [(set_attr "type" "arith")
970 (set_attr "mode" "SI")])
972 ;; Split this insn so that the addiu splitters can have a crack at it.
973 ;; Use a conservative length estimate until the split.
974 (define_insn_and_split "*addsi3_extended_mips16"
975 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
977 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
978 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
979 "TARGET_64BIT && TARGET_MIPS16"
981 "&& reload_completed"
982 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
983 { operands[3] = gen_lowpart (SImode, operands[0]); }
984 [(set_attr "type" "arith")
985 (set_attr "mode" "SI")
986 (set_attr "extended_mips16" "yes")])
989 ;; ....................
993 ;; ....................
996 (define_insn "sub<mode>3"
997 [(set (match_operand:ANYF 0 "register_operand" "=f")
998 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
999 (match_operand:ANYF 2 "register_operand" "f")))]
1001 "sub.<fmt>\t%0,%1,%2"
1002 [(set_attr "type" "fadd")
1003 (set_attr "mode" "<UNITMODE>")])
1005 (define_insn "sub<mode>3"
1006 [(set (match_operand:GPR 0 "register_operand" "=d")
1007 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1008 (match_operand:GPR 2 "register_operand" "d")))]
1011 [(set_attr "type" "arith")
1012 (set_attr "mode" "<MODE>")])
1014 (define_insn "*subsi3_extended"
1015 [(set (match_operand:DI 0 "register_operand" "=d")
1017 (minus:SI (match_operand:SI 1 "register_operand" "d")
1018 (match_operand:SI 2 "register_operand" "d"))))]
1021 [(set_attr "type" "arith")
1022 (set_attr "mode" "DI")])
1025 ;; ....................
1029 ;; ....................
1032 (define_expand "mul<mode>3"
1033 [(set (match_operand:SCALARF 0 "register_operand")
1034 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1035 (match_operand:SCALARF 2 "register_operand")))]
1039 (define_insn "*mul<mode>3"
1040 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1041 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1042 (match_operand:SCALARF 2 "register_operand" "f")))]
1043 "!TARGET_4300_MUL_FIX"
1044 "mul.<fmt>\t%0,%1,%2"
1045 [(set_attr "type" "fmul")
1046 (set_attr "mode" "<MODE>")])
1048 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1049 ;; operands may corrupt immediately following multiplies. This is a
1050 ;; simple fix to insert NOPs.
1052 (define_insn "*mul<mode>3_r4300"
1053 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1054 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1055 (match_operand:SCALARF 2 "register_operand" "f")))]
1056 "TARGET_4300_MUL_FIX"
1057 "mul.<fmt>\t%0,%1,%2\;nop"
1058 [(set_attr "type" "fmul")
1059 (set_attr "mode" "<MODE>")
1060 (set_attr "length" "8")])
1062 (define_insn "mulv2sf3"
1063 [(set (match_operand:V2SF 0 "register_operand" "=f")
1064 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1065 (match_operand:V2SF 2 "register_operand" "f")))]
1066 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1068 [(set_attr "type" "fmul")
1069 (set_attr "mode" "SF")])
1071 ;; The original R4000 has a cpu bug. If a double-word or a variable
1072 ;; shift executes while an integer multiplication is in progress, the
1073 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1074 ;; with the mult on the R4000.
1076 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1077 ;; (also valid for MIPS R4000MC processors):
1079 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1080 ;; this errata description.
1081 ;; The following code sequence causes the R4000 to incorrectly
1082 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1083 ;; instruction. If the dsra32 instruction is executed during an
1084 ;; integer multiply, the dsra32 will only shift by the amount in
1085 ;; specified in the instruction rather than the amount plus 32
1087 ;; instruction 1: mult rs,rt integer multiply
1088 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1089 ;; right arithmetic + 32
1090 ;; Workaround: A dsra32 instruction placed after an integer
1091 ;; multiply should not be one of the 11 instructions after the
1092 ;; multiply instruction."
1096 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1097 ;; the following description.
1098 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1099 ;; 64-bit versions) may produce incorrect results under the
1100 ;; following conditions:
1101 ;; 1) An integer multiply is currently executing
1102 ;; 2) These types of shift instructions are executed immediately
1103 ;; following an integer divide instruction.
1105 ;; 1) Make sure no integer multiply is running wihen these
1106 ;; instruction are executed. If this cannot be predicted at
1107 ;; compile time, then insert a "mfhi" to R0 instruction
1108 ;; immediately after the integer multiply instruction. This
1109 ;; will cause the integer multiply to complete before the shift
1111 ;; 2) Separate integer divide and these two classes of shift
1112 ;; instructions by another instruction or a noop."
1114 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1117 (define_expand "mulsi3"
1118 [(set (match_operand:SI 0 "register_operand")
1119 (mult:SI (match_operand:SI 1 "register_operand")
1120 (match_operand:SI 2 "register_operand")))]
1124 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1125 else if (TARGET_FIX_R4000)
1126 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1128 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1132 (define_expand "muldi3"
1133 [(set (match_operand:DI 0 "register_operand")
1134 (mult:DI (match_operand:DI 1 "register_operand")
1135 (match_operand:DI 2 "register_operand")))]
1138 if (TARGET_FIX_R4000)
1139 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1141 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1145 (define_insn "mulsi3_mult3"
1146 [(set (match_operand:SI 0 "register_operand" "=d,l")
1147 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1148 (match_operand:SI 2 "register_operand" "d,d")))
1149 (clobber (match_scratch:SI 3 "=h,h"))
1150 (clobber (match_scratch:SI 4 "=l,X"))]
1153 if (which_alternative == 1)
1154 return "mult\t%1,%2";
1155 if (TARGET_MIPS3900)
1156 return "mult\t%0,%1,%2";
1157 return "mul\t%0,%1,%2";
1159 [(set_attr "type" "imul3,imul")
1160 (set_attr "mode" "SI")])
1162 ;; If a register gets allocated to LO, and we spill to memory, the reload
1163 ;; will include a move from LO to a GPR. Merge it into the multiplication
1164 ;; if it can set the GPR directly.
1167 ;; Operand 1: GPR (1st multiplication operand)
1168 ;; Operand 2: GPR (2nd multiplication operand)
1170 ;; Operand 4: GPR (destination)
1173 [(set (match_operand:SI 0 "register_operand")
1174 (mult:SI (match_operand:SI 1 "register_operand")
1175 (match_operand:SI 2 "register_operand")))
1176 (clobber (match_operand:SI 3 "register_operand"))
1177 (clobber (scratch:SI))])
1178 (set (match_operand:SI 4 "register_operand")
1179 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1180 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1183 (mult:SI (match_dup 1)
1185 (clobber (match_dup 3))
1186 (clobber (match_dup 0))])])
1188 (define_insn "mul<mode>3_internal"
1189 [(set (match_operand:GPR 0 "register_operand" "=l")
1190 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1191 (match_operand:GPR 2 "register_operand" "d")))
1192 (clobber (match_scratch:GPR 3 "=h"))]
1195 [(set_attr "type" "imul")
1196 (set_attr "mode" "<MODE>")])
1198 (define_insn "mul<mode>3_r4000"
1199 [(set (match_operand:GPR 0 "register_operand" "=d")
1200 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1201 (match_operand:GPR 2 "register_operand" "d")))
1202 (clobber (match_scratch:GPR 3 "=h"))
1203 (clobber (match_scratch:GPR 4 "=l"))]
1205 "<d>mult\t%1,%2\;mflo\t%0"
1206 [(set_attr "type" "imul")
1207 (set_attr "mode" "<MODE>")
1208 (set_attr "length" "8")])
1210 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1211 ;; of "mult; mflo". They have the same latency, but the first form gives
1212 ;; us an extra cycle to compute the operands.
1215 ;; Operand 1: GPR (1st multiplication operand)
1216 ;; Operand 2: GPR (2nd multiplication operand)
1218 ;; Operand 4: GPR (destination)
1221 [(set (match_operand:SI 0 "register_operand")
1222 (mult:SI (match_operand:SI 1 "register_operand")
1223 (match_operand:SI 2 "register_operand")))
1224 (clobber (match_operand:SI 3 "register_operand"))])
1225 (set (match_operand:SI 4 "register_operand")
1226 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1227 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1232 (plus:SI (mult:SI (match_dup 1)
1236 (plus:SI (mult:SI (match_dup 1)
1239 (clobber (match_dup 3))])])
1241 ;; Multiply-accumulate patterns
1243 ;; For processors that can copy the output to a general register:
1245 ;; The all-d alternative is needed because the combiner will find this
1246 ;; pattern and then register alloc/reload will move registers around to
1247 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1249 ;; The last alternative should be made slightly less desirable, but adding
1250 ;; "?" to the constraint is too strong, and causes values to be loaded into
1251 ;; LO even when that's more costly. For now, using "*d" mostly does the
1253 (define_insn "*mul_acc_si"
1254 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1255 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1256 (match_operand:SI 2 "register_operand" "d,d,d"))
1257 (match_operand:SI 3 "register_operand" "0,l,*d")))
1258 (clobber (match_scratch:SI 4 "=h,h,h"))
1259 (clobber (match_scratch:SI 5 "=X,3,l"))
1260 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1262 || GENERATE_MADD_MSUB)
1265 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1266 if (which_alternative == 2)
1268 if (GENERATE_MADD_MSUB && which_alternative != 0)
1270 return madd[which_alternative];
1272 [(set_attr "type" "imadd")
1273 (set_attr "mode" "SI")
1274 (set_attr "length" "4,4,8")])
1276 ;; Split the above insn if we failed to get LO allocated.
1278 [(set (match_operand:SI 0 "register_operand")
1279 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1280 (match_operand:SI 2 "register_operand"))
1281 (match_operand:SI 3 "register_operand")))
1282 (clobber (match_scratch:SI 4))
1283 (clobber (match_scratch:SI 5))
1284 (clobber (match_scratch:SI 6))]
1285 "reload_completed && !TARGET_DEBUG_D_MODE
1286 && GP_REG_P (true_regnum (operands[0]))
1287 && GP_REG_P (true_regnum (operands[3]))"
1288 [(parallel [(set (match_dup 6)
1289 (mult:SI (match_dup 1) (match_dup 2)))
1290 (clobber (match_dup 4))
1291 (clobber (match_dup 5))])
1292 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1295 ;; Splitter to copy result of MADD to a general register
1297 [(set (match_operand:SI 0 "register_operand")
1298 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1299 (match_operand:SI 2 "register_operand"))
1300 (match_operand:SI 3 "register_operand")))
1301 (clobber (match_scratch:SI 4))
1302 (clobber (match_scratch:SI 5))
1303 (clobber (match_scratch:SI 6))]
1304 "reload_completed && !TARGET_DEBUG_D_MODE
1305 && GP_REG_P (true_regnum (operands[0]))
1306 && true_regnum (operands[3]) == LO_REGNUM"
1307 [(parallel [(set (match_dup 3)
1308 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1310 (clobber (match_dup 4))
1311 (clobber (match_dup 5))
1312 (clobber (match_dup 6))])
1313 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1316 (define_insn "*macc"
1317 [(set (match_operand:SI 0 "register_operand" "=l,d")
1318 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1319 (match_operand:SI 2 "register_operand" "d,d"))
1320 (match_operand:SI 3 "register_operand" "0,l")))
1321 (clobber (match_scratch:SI 4 "=h,h"))
1322 (clobber (match_scratch:SI 5 "=X,3"))]
1325 if (which_alternative == 1)
1326 return "macc\t%0,%1,%2";
1327 else if (TARGET_MIPS5500)
1328 return "madd\t%1,%2";
1330 /* The VR4130 assumes that there is a two-cycle latency between a macc
1331 that "writes" to $0 and an instruction that reads from it. We avoid
1332 this by assigning to $1 instead. */
1333 return "%[macc\t%@,%1,%2%]";
1335 [(set_attr "type" "imadd")
1336 (set_attr "mode" "SI")])
1338 (define_insn "*msac"
1339 [(set (match_operand:SI 0 "register_operand" "=l,d")
1340 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1341 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1342 (match_operand:SI 3 "register_operand" "d,d"))))
1343 (clobber (match_scratch:SI 4 "=h,h"))
1344 (clobber (match_scratch:SI 5 "=X,1"))]
1347 if (which_alternative == 1)
1348 return "msac\t%0,%2,%3";
1349 else if (TARGET_MIPS5500)
1350 return "msub\t%2,%3";
1352 return "msac\t$0,%2,%3";
1354 [(set_attr "type" "imadd")
1355 (set_attr "mode" "SI")])
1357 ;; An msac-like instruction implemented using negation and a macc.
1358 (define_insn_and_split "*msac_using_macc"
1359 [(set (match_operand:SI 0 "register_operand" "=l,d")
1360 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1361 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1362 (match_operand:SI 3 "register_operand" "d,d"))))
1363 (clobber (match_scratch:SI 4 "=h,h"))
1364 (clobber (match_scratch:SI 5 "=X,1"))
1365 (clobber (match_scratch:SI 6 "=d,d"))]
1366 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1368 "&& reload_completed"
1370 (neg:SI (match_dup 3)))
1373 (plus:SI (mult:SI (match_dup 2)
1376 (clobber (match_dup 4))
1377 (clobber (match_dup 5))])]
1379 [(set_attr "type" "imadd")
1380 (set_attr "length" "8")])
1382 ;; Patterns generated by the define_peephole2 below.
1384 (define_insn "*macc2"
1385 [(set (match_operand:SI 0 "register_operand" "=l")
1386 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1387 (match_operand:SI 2 "register_operand" "d"))
1389 (set (match_operand:SI 3 "register_operand" "=d")
1390 (plus:SI (mult:SI (match_dup 1)
1393 (clobber (match_scratch:SI 4 "=h"))]
1394 "ISA_HAS_MACC && reload_completed"
1396 [(set_attr "type" "imadd")
1397 (set_attr "mode" "SI")])
1399 (define_insn "*msac2"
1400 [(set (match_operand:SI 0 "register_operand" "=l")
1401 (minus:SI (match_dup 0)
1402 (mult:SI (match_operand:SI 1 "register_operand" "d")
1403 (match_operand:SI 2 "register_operand" "d"))))
1404 (set (match_operand:SI 3 "register_operand" "=d")
1405 (minus:SI (match_dup 0)
1406 (mult:SI (match_dup 1)
1408 (clobber (match_scratch:SI 4 "=h"))]
1409 "ISA_HAS_MSAC && reload_completed"
1411 [(set_attr "type" "imadd")
1412 (set_attr "mode" "SI")])
1414 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1418 ;; Operand 1: macc/msac
1420 ;; Operand 3: GPR (destination)
1423 [(set (match_operand:SI 0 "register_operand")
1424 (match_operand:SI 1 "macc_msac_operand"))
1425 (clobber (match_operand:SI 2 "register_operand"))
1426 (clobber (scratch:SI))])
1427 (set (match_operand:SI 3 "register_operand")
1428 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1430 [(parallel [(set (match_dup 0)
1434 (clobber (match_dup 2))])]
1437 ;; When we have a three-address multiplication instruction, it should
1438 ;; be faster to do a separate multiply and add, rather than moving
1439 ;; something into LO in order to use a macc instruction.
1441 ;; This peephole needs a scratch register to cater for the case when one
1442 ;; of the multiplication operands is the same as the destination.
1444 ;; Operand 0: GPR (scratch)
1446 ;; Operand 2: GPR (addend)
1447 ;; Operand 3: GPR (destination)
1448 ;; Operand 4: macc/msac
1450 ;; Operand 6: new multiplication
1451 ;; Operand 7: new addition/subtraction
1453 [(match_scratch:SI 0 "d")
1454 (set (match_operand:SI 1 "register_operand")
1455 (match_operand:SI 2 "register_operand"))
1458 [(set (match_operand:SI 3 "register_operand")
1459 (match_operand:SI 4 "macc_msac_operand"))
1460 (clobber (match_operand:SI 5 "register_operand"))
1461 (clobber (match_dup 1))])]
1463 && true_regnum (operands[1]) == LO_REGNUM
1464 && peep2_reg_dead_p (2, operands[1])
1465 && GP_REG_P (true_regnum (operands[3]))"
1466 [(parallel [(set (match_dup 0)
1468 (clobber (match_dup 5))
1469 (clobber (match_dup 1))])
1473 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1474 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1475 operands[2], operands[0]);
1478 ;; Same as above, except LO is the initial target of the macc.
1480 ;; Operand 0: GPR (scratch)
1482 ;; Operand 2: GPR (addend)
1483 ;; Operand 3: macc/msac
1485 ;; Operand 5: GPR (destination)
1486 ;; Operand 6: new multiplication
1487 ;; Operand 7: new addition/subtraction
1489 [(match_scratch:SI 0 "d")
1490 (set (match_operand:SI 1 "register_operand")
1491 (match_operand:SI 2 "register_operand"))
1495 (match_operand:SI 3 "macc_msac_operand"))
1496 (clobber (match_operand:SI 4 "register_operand"))
1497 (clobber (scratch:SI))])
1499 (set (match_operand:SI 5 "register_operand")
1500 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1501 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1502 [(parallel [(set (match_dup 0)
1504 (clobber (match_dup 4))
1505 (clobber (match_dup 1))])
1509 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1510 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1511 operands[2], operands[0]);
1514 (define_insn "*mul_sub_si"
1515 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1516 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1517 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1518 (match_operand:SI 3 "register_operand" "d,d,d"))))
1519 (clobber (match_scratch:SI 4 "=h,h,h"))
1520 (clobber (match_scratch:SI 5 "=X,1,l"))
1521 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1522 "GENERATE_MADD_MSUB"
1527 [(set_attr "type" "imadd")
1528 (set_attr "mode" "SI")
1529 (set_attr "length" "4,8,8")])
1531 ;; Split the above insn if we failed to get LO allocated.
1533 [(set (match_operand:SI 0 "register_operand")
1534 (minus:SI (match_operand:SI 1 "register_operand")
1535 (mult:SI (match_operand:SI 2 "register_operand")
1536 (match_operand:SI 3 "register_operand"))))
1537 (clobber (match_scratch:SI 4))
1538 (clobber (match_scratch:SI 5))
1539 (clobber (match_scratch:SI 6))]
1540 "reload_completed && !TARGET_DEBUG_D_MODE
1541 && GP_REG_P (true_regnum (operands[0]))
1542 && GP_REG_P (true_regnum (operands[1]))"
1543 [(parallel [(set (match_dup 6)
1544 (mult:SI (match_dup 2) (match_dup 3)))
1545 (clobber (match_dup 4))
1546 (clobber (match_dup 5))])
1547 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1550 ;; Splitter to copy result of MSUB to a general register
1552 [(set (match_operand:SI 0 "register_operand")
1553 (minus:SI (match_operand:SI 1 "register_operand")
1554 (mult:SI (match_operand:SI 2 "register_operand")
1555 (match_operand:SI 3 "register_operand"))))
1556 (clobber (match_scratch:SI 4))
1557 (clobber (match_scratch:SI 5))
1558 (clobber (match_scratch:SI 6))]
1559 "reload_completed && !TARGET_DEBUG_D_MODE
1560 && GP_REG_P (true_regnum (operands[0]))
1561 && true_regnum (operands[1]) == LO_REGNUM"
1562 [(parallel [(set (match_dup 1)
1563 (minus:SI (match_dup 1)
1564 (mult:SI (match_dup 2) (match_dup 3))))
1565 (clobber (match_dup 4))
1566 (clobber (match_dup 5))
1567 (clobber (match_dup 6))])
1568 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1571 (define_insn "*muls"
1572 [(set (match_operand:SI 0 "register_operand" "=l,d")
1573 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1574 (match_operand:SI 2 "register_operand" "d,d"))))
1575 (clobber (match_scratch:SI 3 "=h,h"))
1576 (clobber (match_scratch:SI 4 "=X,l"))]
1581 [(set_attr "type" "imul,imul3")
1582 (set_attr "mode" "SI")])
1584 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1586 (define_expand "<u>mulsidi3"
1588 [(set (match_operand:DI 0 "register_operand")
1589 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1590 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1591 (clobber (scratch:DI))
1592 (clobber (scratch:DI))
1593 (clobber (scratch:DI))])]
1594 "!TARGET_64BIT || !TARGET_FIX_R4000"
1598 if (!TARGET_FIX_R4000)
1599 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1602 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1608 (define_insn "<u>mulsidi3_32bit_internal"
1609 [(set (match_operand:DI 0 "register_operand" "=x")
1610 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1611 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1612 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1614 [(set_attr "type" "imul")
1615 (set_attr "mode" "SI")])
1617 (define_insn "<u>mulsidi3_32bit_r4000"
1618 [(set (match_operand:DI 0 "register_operand" "=d")
1619 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1620 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1621 (clobber (match_scratch:DI 3 "=x"))]
1622 "!TARGET_64BIT && TARGET_FIX_R4000"
1623 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1624 [(set_attr "type" "imul")
1625 (set_attr "mode" "SI")
1626 (set_attr "length" "12")])
1628 (define_insn_and_split "*<u>mulsidi3_64bit"
1629 [(set (match_operand:DI 0 "register_operand" "=d")
1630 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1631 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1632 (clobber (match_scratch:DI 3 "=l"))
1633 (clobber (match_scratch:DI 4 "=h"))
1634 (clobber (match_scratch:DI 5 "=d"))]
1635 "TARGET_64BIT && !TARGET_FIX_R4000"
1637 "&& reload_completed"
1641 (mult:SI (match_dup 1)
1645 (mult:DI (any_extend:DI (match_dup 1))
1646 (any_extend:DI (match_dup 2)))
1649 ;; OP5 <- LO, OP0 <- HI
1650 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1651 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1655 (ashift:DI (match_dup 5)
1658 (lshiftrt:DI (match_dup 5)
1661 ;; Shift OP0 into place.
1663 (ashift:DI (match_dup 0)
1666 ;; OR the two halves together
1668 (ior:DI (match_dup 0)
1671 [(set_attr "type" "imul")
1672 (set_attr "mode" "SI")
1673 (set_attr "length" "24")])
1675 (define_insn "*<u>mulsidi3_64bit_parts"
1676 [(set (match_operand:DI 0 "register_operand" "=l")
1678 (mult:SI (match_operand:SI 2 "register_operand" "d")
1679 (match_operand:SI 3 "register_operand" "d"))))
1680 (set (match_operand:DI 1 "register_operand" "=h")
1682 (mult:DI (any_extend:DI (match_dup 2))
1683 (any_extend:DI (match_dup 3)))
1685 "TARGET_64BIT && !TARGET_FIX_R4000"
1687 [(set_attr "type" "imul")
1688 (set_attr "mode" "SI")])
1690 ;; Widening multiply with negation.
1691 (define_insn "*muls<u>_di"
1692 [(set (match_operand:DI 0 "register_operand" "=x")
1695 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1696 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1697 "!TARGET_64BIT && ISA_HAS_MULS"
1699 [(set_attr "type" "imul")
1700 (set_attr "mode" "SI")])
1702 (define_insn "<u>msubsidi4"
1703 [(set (match_operand:DI 0 "register_operand" "=ka")
1705 (match_operand:DI 3 "register_operand" "0")
1707 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1708 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1709 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1712 return "msub<u>\t%q0,%1,%2";
1713 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1714 return "msub<u>\t%1,%2";
1716 return "msac<u>\t$0,%1,%2";
1718 [(set_attr "type" "imadd")
1719 (set_attr "mode" "SI")])
1721 ;; _highpart patterns
1723 (define_expand "<su>mulsi3_highpart"
1724 [(set (match_operand:SI 0 "register_operand")
1727 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1728 (any_extend:DI (match_operand:SI 2 "register_operand")))
1730 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1733 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1737 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1742 (define_insn "<su>mulsi3_highpart_internal"
1743 [(set (match_operand:SI 0 "register_operand" "=h")
1746 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1747 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1749 (clobber (match_scratch:SI 3 "=l"))]
1750 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1752 [(set_attr "type" "imul")
1753 (set_attr "mode" "SI")])
1755 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1756 [(set (match_operand:SI 0 "register_operand" "=h,d")
1760 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1761 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1763 (clobber (match_scratch:SI 3 "=l,l"))
1764 (clobber (match_scratch:SI 4 "=X,h"))]
1769 [(set_attr "type" "imul,imul3")
1770 (set_attr "mode" "SI")])
1772 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1773 [(set (match_operand:SI 0 "register_operand" "=h,d")
1778 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1779 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1781 (clobber (match_scratch:SI 3 "=l,l"))
1782 (clobber (match_scratch:SI 4 "=X,h"))]
1786 mulshi<u>\t%0,%1,%2"
1787 [(set_attr "type" "imul,imul3")
1788 (set_attr "mode" "SI")])
1790 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1791 ;; errata MD(0), which says that dmultu does not always produce the
1793 (define_insn "<su>muldi3_highpart"
1794 [(set (match_operand:DI 0 "register_operand" "=h")
1798 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1799 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1801 (clobber (match_scratch:DI 3 "=l"))]
1802 "TARGET_64BIT && !TARGET_FIX_R4000
1803 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1805 [(set_attr "type" "imul")
1806 (set_attr "mode" "DI")])
1808 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1809 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1811 (define_insn "madsi"
1812 [(set (match_operand:SI 0 "register_operand" "+l")
1813 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1814 (match_operand:SI 2 "register_operand" "d"))
1816 (clobber (match_scratch:SI 3 "=h"))]
1819 [(set_attr "type" "imadd")
1820 (set_attr "mode" "SI")])
1822 (define_insn "<u>maddsidi4"
1823 [(set (match_operand:DI 0 "register_operand" "=ka")
1825 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1826 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1827 (match_operand:DI 3 "register_operand" "0")))]
1828 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
1832 return "mad<u>\t%1,%2";
1833 else if (ISA_HAS_DSPR2)
1834 return "madd<u>\t%q0,%1,%2";
1835 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1836 return "madd<u>\t%1,%2";
1838 /* See comment in *macc. */
1839 return "%[macc<u>\t%@,%1,%2%]";
1841 [(set_attr "type" "imadd")
1842 (set_attr "mode" "SI")])
1844 ;; Floating point multiply accumulate instructions.
1846 (define_insn "*madd<mode>"
1847 [(set (match_operand:ANYF 0 "register_operand" "=f")
1848 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1849 (match_operand:ANYF 2 "register_operand" "f"))
1850 (match_operand:ANYF 3 "register_operand" "f")))]
1851 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1852 "madd.<fmt>\t%0,%3,%1,%2"
1853 [(set_attr "type" "fmadd")
1854 (set_attr "mode" "<UNITMODE>")])
1856 (define_insn "*msub<mode>"
1857 [(set (match_operand:ANYF 0 "register_operand" "=f")
1858 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1859 (match_operand:ANYF 2 "register_operand" "f"))
1860 (match_operand:ANYF 3 "register_operand" "f")))]
1861 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1862 "msub.<fmt>\t%0,%3,%1,%2"
1863 [(set_attr "type" "fmadd")
1864 (set_attr "mode" "<UNITMODE>")])
1866 (define_insn "*nmadd<mode>"
1867 [(set (match_operand:ANYF 0 "register_operand" "=f")
1868 (neg:ANYF (plus:ANYF
1869 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1870 (match_operand:ANYF 2 "register_operand" "f"))
1871 (match_operand:ANYF 3 "register_operand" "f"))))]
1872 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1873 && TARGET_FUSED_MADD
1874 && HONOR_SIGNED_ZEROS (<MODE>mode)
1875 && !HONOR_NANS (<MODE>mode)"
1876 "nmadd.<fmt>\t%0,%3,%1,%2"
1877 [(set_attr "type" "fmadd")
1878 (set_attr "mode" "<UNITMODE>")])
1880 (define_insn "*nmadd<mode>_fastmath"
1881 [(set (match_operand:ANYF 0 "register_operand" "=f")
1883 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1884 (match_operand:ANYF 2 "register_operand" "f"))
1885 (match_operand:ANYF 3 "register_operand" "f")))]
1886 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1887 && TARGET_FUSED_MADD
1888 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1889 && !HONOR_NANS (<MODE>mode)"
1890 "nmadd.<fmt>\t%0,%3,%1,%2"
1891 [(set_attr "type" "fmadd")
1892 (set_attr "mode" "<UNITMODE>")])
1894 (define_insn "*nmsub<mode>"
1895 [(set (match_operand:ANYF 0 "register_operand" "=f")
1896 (neg:ANYF (minus:ANYF
1897 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1898 (match_operand:ANYF 3 "register_operand" "f"))
1899 (match_operand:ANYF 1 "register_operand" "f"))))]
1900 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1901 && TARGET_FUSED_MADD
1902 && HONOR_SIGNED_ZEROS (<MODE>mode)
1903 && !HONOR_NANS (<MODE>mode)"
1904 "nmsub.<fmt>\t%0,%1,%2,%3"
1905 [(set_attr "type" "fmadd")
1906 (set_attr "mode" "<UNITMODE>")])
1908 (define_insn "*nmsub<mode>_fastmath"
1909 [(set (match_operand:ANYF 0 "register_operand" "=f")
1911 (match_operand:ANYF 1 "register_operand" "f")
1912 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1913 (match_operand:ANYF 3 "register_operand" "f"))))]
1914 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1915 && TARGET_FUSED_MADD
1916 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1917 && !HONOR_NANS (<MODE>mode)"
1918 "nmsub.<fmt>\t%0,%1,%2,%3"
1919 [(set_attr "type" "fmadd")
1920 (set_attr "mode" "<UNITMODE>")])
1923 ;; ....................
1925 ;; DIVISION and REMAINDER
1927 ;; ....................
1930 (define_expand "div<mode>3"
1931 [(set (match_operand:ANYF 0 "register_operand")
1932 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1933 (match_operand:ANYF 2 "register_operand")))]
1934 "<divide_condition>"
1936 if (const_1_operand (operands[1], <MODE>mode))
1937 if (!(<recip_condition> && flag_unsafe_math_optimizations))
1938 operands[1] = force_reg (<MODE>mode, operands[1]);
1941 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1943 ;; If an mfc1 or dmfc1 happens to access the floating point register
1944 ;; file at the same time a long latency operation (div, sqrt, recip,
1945 ;; sqrt) iterates an intermediate result back through the floating
1946 ;; point register file bypass, then instead returning the correct
1947 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1948 ;; result of the long latency operation.
1950 ;; The workaround is to insert an unconditional 'mov' from/to the
1951 ;; long latency op destination register.
1953 (define_insn "*div<mode>3"
1954 [(set (match_operand:ANYF 0 "register_operand" "=f")
1955 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1956 (match_operand:ANYF 2 "register_operand" "f")))]
1957 "<divide_condition>"
1960 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1962 return "div.<fmt>\t%0,%1,%2";
1964 [(set_attr "type" "fdiv")
1965 (set_attr "mode" "<UNITMODE>")
1966 (set (attr "length")
1967 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1971 (define_insn "*recip<mode>3"
1972 [(set (match_operand:ANYF 0 "register_operand" "=f")
1973 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1974 (match_operand:ANYF 2 "register_operand" "f")))]
1975 "<recip_condition> && flag_unsafe_math_optimizations"
1978 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1980 return "recip.<fmt>\t%0,%2";
1982 [(set_attr "type" "frdiv")
1983 (set_attr "mode" "<UNITMODE>")
1984 (set (attr "length")
1985 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1989 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1990 ;; with negative operands. We use special libgcc functions instead.
1991 (define_insn "divmod<mode>4"
1992 [(set (match_operand:GPR 0 "register_operand" "=l")
1993 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1994 (match_operand:GPR 2 "register_operand" "d")))
1995 (set (match_operand:GPR 3 "register_operand" "=h")
1996 (mod:GPR (match_dup 1)
1998 "!TARGET_FIX_VR4120"
1999 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
2000 [(set_attr "type" "idiv")
2001 (set_attr "mode" "<MODE>")])
2003 (define_insn "udivmod<mode>4"
2004 [(set (match_operand:GPR 0 "register_operand" "=l")
2005 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2006 (match_operand:GPR 2 "register_operand" "d")))
2007 (set (match_operand:GPR 3 "register_operand" "=h")
2008 (umod:GPR (match_dup 1)
2011 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
2012 [(set_attr "type" "idiv")
2013 (set_attr "mode" "<MODE>")])
2016 ;; ....................
2020 ;; ....................
2022 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2023 ;; "*div[sd]f3" comment for details).
2025 (define_insn "sqrt<mode>2"
2026 [(set (match_operand:ANYF 0 "register_operand" "=f")
2027 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2031 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2033 return "sqrt.<fmt>\t%0,%1";
2035 [(set_attr "type" "fsqrt")
2036 (set_attr "mode" "<UNITMODE>")
2037 (set (attr "length")
2038 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2042 (define_insn "*rsqrt<mode>a"
2043 [(set (match_operand:ANYF 0 "register_operand" "=f")
2044 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2045 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2046 "<recip_condition> && flag_unsafe_math_optimizations"
2049 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2051 return "rsqrt.<fmt>\t%0,%2";
2053 [(set_attr "type" "frsqrt")
2054 (set_attr "mode" "<UNITMODE>")
2055 (set (attr "length")
2056 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2060 (define_insn "*rsqrt<mode>b"
2061 [(set (match_operand:ANYF 0 "register_operand" "=f")
2062 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2063 (match_operand:ANYF 2 "register_operand" "f"))))]
2064 "<recip_condition> && flag_unsafe_math_optimizations"
2067 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2069 return "rsqrt.<fmt>\t%0,%2";
2071 [(set_attr "type" "frsqrt")
2072 (set_attr "mode" "<UNITMODE>")
2073 (set (attr "length")
2074 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2079 ;; ....................
2083 ;; ....................
2085 ;; Do not use the integer abs macro instruction, since that signals an
2086 ;; exception on -2147483648 (sigh).
2088 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2089 ;; invalid; it does not clear their sign bits. We therefore can't use
2090 ;; abs.fmt if the signs of NaNs matter.
2092 (define_insn "abs<mode>2"
2093 [(set (match_operand:ANYF 0 "register_operand" "=f")
2094 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2095 "!HONOR_NANS (<MODE>mode)"
2097 [(set_attr "type" "fabs")
2098 (set_attr "mode" "<UNITMODE>")])
2101 ;; ...................
2103 ;; Count leading zeroes.
2105 ;; ...................
2108 (define_insn "clz<mode>2"
2109 [(set (match_operand:GPR 0 "register_operand" "=d")
2110 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2113 [(set_attr "type" "clz")
2114 (set_attr "mode" "<MODE>")])
2117 ;; ....................
2119 ;; NEGATION and ONE'S COMPLEMENT
2121 ;; ....................
2123 (define_insn "negsi2"
2124 [(set (match_operand:SI 0 "register_operand" "=d")
2125 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2129 return "neg\t%0,%1";
2131 return "subu\t%0,%.,%1";
2133 [(set_attr "type" "arith")
2134 (set_attr "mode" "SI")])
2136 (define_insn "negdi2"
2137 [(set (match_operand:DI 0 "register_operand" "=d")
2138 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2139 "TARGET_64BIT && !TARGET_MIPS16"
2141 [(set_attr "type" "arith")
2142 (set_attr "mode" "DI")])
2144 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2145 ;; invalid; it does not flip their sign bit. We therefore can't use
2146 ;; neg.fmt if the signs of NaNs matter.
2148 (define_insn "neg<mode>2"
2149 [(set (match_operand:ANYF 0 "register_operand" "=f")
2150 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2151 "!HONOR_NANS (<MODE>mode)"
2153 [(set_attr "type" "fneg")
2154 (set_attr "mode" "<UNITMODE>")])
2156 (define_insn "one_cmpl<mode>2"
2157 [(set (match_operand:GPR 0 "register_operand" "=d")
2158 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2162 return "not\t%0,%1";
2164 return "nor\t%0,%.,%1";
2166 [(set_attr "type" "logical")
2167 (set_attr "mode" "<MODE>")])
2170 ;; ....................
2174 ;; ....................
2177 ;; Many of these instructions use trivial define_expands, because we
2178 ;; want to use a different set of constraints when TARGET_MIPS16.
2180 (define_expand "and<mode>3"
2181 [(set (match_operand:GPR 0 "register_operand")
2182 (and:GPR (match_operand:GPR 1 "register_operand")
2183 (match_operand:GPR 2 "uns_arith_operand")))]
2187 operands[2] = force_reg (<MODE>mode, operands[2]);
2190 (define_insn "*and<mode>3"
2191 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2192 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2193 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2198 [(set_attr "type" "logical")
2199 (set_attr "mode" "<MODE>")])
2201 (define_insn "*and<mode>3_mips16"
2202 [(set (match_operand:GPR 0 "register_operand" "=d")
2203 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2204 (match_operand:GPR 2 "register_operand" "d")))]
2207 [(set_attr "type" "logical")
2208 (set_attr "mode" "<MODE>")])
2210 (define_expand "ior<mode>3"
2211 [(set (match_operand:GPR 0 "register_operand")
2212 (ior:GPR (match_operand:GPR 1 "register_operand")
2213 (match_operand:GPR 2 "uns_arith_operand")))]
2217 operands[2] = force_reg (<MODE>mode, operands[2]);
2220 (define_insn "*ior<mode>3"
2221 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2222 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2223 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2228 [(set_attr "type" "logical")
2229 (set_attr "mode" "<MODE>")])
2231 (define_insn "*ior<mode>3_mips16"
2232 [(set (match_operand:GPR 0 "register_operand" "=d")
2233 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2234 (match_operand:GPR 2 "register_operand" "d")))]
2237 [(set_attr "type" "logical")
2238 (set_attr "mode" "<MODE>")])
2240 (define_expand "xor<mode>3"
2241 [(set (match_operand:GPR 0 "register_operand")
2242 (xor:GPR (match_operand:GPR 1 "register_operand")
2243 (match_operand:GPR 2 "uns_arith_operand")))]
2248 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2249 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2250 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2255 [(set_attr "type" "logical")
2256 (set_attr "mode" "<MODE>")])
2259 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2260 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2261 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2267 [(set_attr "type" "logical,arith,arith")
2268 (set_attr "mode" "<MODE>")
2269 (set_attr_alternative "length"
2271 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2276 (define_insn "*nor<mode>3"
2277 [(set (match_operand:GPR 0 "register_operand" "=d")
2278 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2279 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2282 [(set_attr "type" "logical")
2283 (set_attr "mode" "<MODE>")])
2286 ;; ....................
2290 ;; ....................
2294 (define_insn "truncdfsf2"
2295 [(set (match_operand:SF 0 "register_operand" "=f")
2296 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2297 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2299 [(set_attr "type" "fcvt")
2300 (set_attr "cnv_mode" "D2S")
2301 (set_attr "mode" "SF")])
2303 ;; Integer truncation patterns. Truncating SImode values to smaller
2304 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2305 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2306 ;; need to make sure that the lower 32 bits are properly sign-extended
2307 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2308 ;; smaller than SImode is equivalent to two separate truncations:
2311 ;; DI ---> HI == DI ---> SI ---> HI
2312 ;; DI ---> QI == DI ---> SI ---> QI
2314 ;; Step A needs a real instruction but step B does not.
2316 (define_insn "truncdisi2"
2317 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2318 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2323 [(set_attr "type" "shift,store")
2324 (set_attr "mode" "SI")
2325 (set_attr "extended_mips16" "yes,*")])
2327 (define_insn "truncdihi2"
2328 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2329 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2334 [(set_attr "type" "shift,store")
2335 (set_attr "mode" "SI")
2336 (set_attr "extended_mips16" "yes,*")])
2338 (define_insn "truncdiqi2"
2339 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2340 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2345 [(set_attr "type" "shift,store")
2346 (set_attr "mode" "SI")
2347 (set_attr "extended_mips16" "yes,*")])
2349 ;; Combiner patterns to optimize shift/truncate combinations.
2352 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2354 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2355 (match_operand:DI 2 "const_arith_operand" ""))))]
2356 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2358 [(set_attr "type" "shift")
2359 (set_attr "mode" "SI")])
2362 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2364 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2366 "TARGET_64BIT && !TARGET_MIPS16"
2368 [(set_attr "type" "shift")
2369 (set_attr "mode" "SI")])
2372 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
2373 ;; use the shift/truncate patterns above.
2375 (define_insn_and_split "*extenddi_truncate<mode>"
2376 [(set (match_operand:DI 0 "register_operand" "=d")
2378 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2379 "TARGET_64BIT && !TARGET_MIPS16"
2381 "&& reload_completed"
2383 (ashift:DI (match_dup 1)
2386 (ashiftrt:DI (match_dup 2)
2389 operands[2] = gen_lowpart (DImode, operands[0]);
2390 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2393 (define_insn_and_split "*extendsi_truncate<mode>"
2394 [(set (match_operand:SI 0 "register_operand" "=d")
2396 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2397 "TARGET_64BIT && !TARGET_MIPS16"
2399 "&& reload_completed"
2401 (ashift:DI (match_dup 1)
2404 (truncate:SI (ashiftrt:DI (match_dup 2)
2407 operands[2] = gen_lowpart (DImode, operands[0]);
2408 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2411 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2413 (define_insn "*zero_extend<mode>_trunchi"
2414 [(set (match_operand:GPR 0 "register_operand" "=d")
2416 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2417 "TARGET_64BIT && !TARGET_MIPS16"
2418 "andi\t%0,%1,0xffff"
2419 [(set_attr "type" "logical")
2420 (set_attr "mode" "<MODE>")])
2422 (define_insn "*zero_extend<mode>_truncqi"
2423 [(set (match_operand:GPR 0 "register_operand" "=d")
2425 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2426 "TARGET_64BIT && !TARGET_MIPS16"
2428 [(set_attr "type" "logical")
2429 (set_attr "mode" "<MODE>")])
2432 [(set (match_operand:HI 0 "register_operand" "=d")
2434 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2435 "TARGET_64BIT && !TARGET_MIPS16"
2437 [(set_attr "type" "logical")
2438 (set_attr "mode" "HI")])
2441 ;; ....................
2445 ;; ....................
2449 (define_insn_and_split "zero_extendsidi2"
2450 [(set (match_operand:DI 0 "register_operand" "=d,d")
2451 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2456 "&& reload_completed && REG_P (operands[1])"
2458 (ashift:DI (match_dup 1) (const_int 32)))
2460 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2461 { operands[1] = gen_lowpart (DImode, operands[1]); }
2462 [(set_attr "type" "multi,load")
2463 (set_attr "mode" "DI")
2464 (set_attr "length" "8,*")])
2466 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2467 ;; because of TRULY_NOOP_TRUNCATION.
2469 (define_insn_and_split "*clear_upper32"
2470 [(set (match_operand:DI 0 "register_operand" "=d,d")
2471 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2472 (const_int 4294967295)))]
2475 if (which_alternative == 0)
2478 operands[1] = gen_lowpart (SImode, operands[1]);
2479 return "lwu\t%0,%1";
2481 "&& reload_completed && REG_P (operands[1])"
2483 (ashift:DI (match_dup 1) (const_int 32)))
2485 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2487 [(set_attr "type" "multi,load")
2488 (set_attr "mode" "DI")
2489 (set_attr "length" "8,*")])
2491 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2492 [(set (match_operand:GPR 0 "register_operand")
2493 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2496 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2497 && !memory_operand (operands[1], <SHORT:MODE>mode))
2499 emit_insn (gen_and<GPR:mode>3 (operands[0],
2500 gen_lowpart (<GPR:MODE>mode, operands[1]),
2501 force_reg (<GPR:MODE>mode,
2502 GEN_INT (<SHORT:mask>))));
2507 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2508 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2510 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2513 andi\t%0,%1,<SHORT:mask>
2514 l<SHORT:size>u\t%0,%1"
2515 [(set_attr "type" "logical,load")
2516 (set_attr "mode" "<GPR:MODE>")])
2518 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2519 [(set (match_operand:GPR 0 "register_operand" "=d")
2520 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2522 "ze<SHORT:size>\t%0"
2523 [(set_attr "type" "arith")
2524 (set_attr "mode" "<GPR:MODE>")])
2526 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2527 [(set (match_operand:GPR 0 "register_operand" "=d")
2528 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2530 "l<SHORT:size>u\t%0,%1"
2531 [(set_attr "type" "load")
2532 (set_attr "mode" "<GPR:MODE>")])
2534 (define_expand "zero_extendqihi2"
2535 [(set (match_operand:HI 0 "register_operand")
2536 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2539 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2541 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2547 (define_insn "*zero_extendqihi2"
2548 [(set (match_operand:HI 0 "register_operand" "=d,d")
2549 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2554 [(set_attr "type" "logical,load")
2555 (set_attr "mode" "HI")])
2557 (define_insn "*zero_extendqihi2_mips16"
2558 [(set (match_operand:HI 0 "register_operand" "=d")
2559 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2562 [(set_attr "type" "load")
2563 (set_attr "mode" "HI")])
2566 ;; ....................
2570 ;; ....................
2573 ;; Those for integer source operand are ordered widest source type first.
2575 ;; When TARGET_64BIT, all SImode integer registers should already be in
2576 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2577 ;; therefore get rid of register->register instructions if we constrain
2578 ;; the source to be in the same register as the destination.
2580 ;; The register alternative has type "arith" so that the pre-reload
2581 ;; scheduler will treat it as a move. This reflects what happens if
2582 ;; the register alternative needs a reload.
2583 (define_insn_and_split "extendsidi2"
2584 [(set (match_operand:DI 0 "register_operand" "=d,d")
2585 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2590 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2593 emit_note (NOTE_INSN_DELETED);
2596 [(set_attr "type" "arith,load")
2597 (set_attr "mode" "DI")])
2599 (define_expand "extend<SHORT:mode><GPR:mode>2"
2600 [(set (match_operand:GPR 0 "register_operand")
2601 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2604 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2605 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2606 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2610 l<SHORT:size>\t%0,%1"
2611 [(set_attr "type" "signext,load")
2612 (set_attr "mode" "<GPR:MODE>")])
2614 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2615 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2617 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2618 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2621 l<SHORT:size>\t%0,%1"
2622 "&& reload_completed && REG_P (operands[1])"
2623 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2624 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2626 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2627 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2628 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2630 [(set_attr "type" "arith,load")
2631 (set_attr "mode" "<GPR:MODE>")
2632 (set_attr "length" "8,*")])
2634 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2635 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2637 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2640 se<SHORT:size>\t%0,%1
2641 l<SHORT:size>\t%0,%1"
2642 [(set_attr "type" "signext,load")
2643 (set_attr "mode" "<GPR:MODE>")])
2645 (define_expand "extendqihi2"
2646 [(set (match_operand:HI 0 "register_operand")
2647 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2650 (define_insn "*extendqihi2_mips16e"
2651 [(set (match_operand:HI 0 "register_operand" "=d,d")
2652 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2657 [(set_attr "type" "signext,load")
2658 (set_attr "mode" "SI")])
2660 (define_insn_and_split "*extendqihi2"
2661 [(set (match_operand:HI 0 "register_operand" "=d,d")
2663 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2664 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2668 "&& reload_completed && REG_P (operands[1])"
2669 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2670 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2672 operands[0] = gen_lowpart (SImode, operands[0]);
2673 operands[1] = gen_lowpart (SImode, operands[1]);
2674 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2675 - GET_MODE_BITSIZE (QImode));
2677 [(set_attr "type" "multi,load")
2678 (set_attr "mode" "SI")
2679 (set_attr "length" "8,*")])
2681 (define_insn "*extendqihi2_seb"
2682 [(set (match_operand:HI 0 "register_operand" "=d,d")
2684 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2689 [(set_attr "type" "signext,load")
2690 (set_attr "mode" "SI")])
2692 (define_insn "extendsfdf2"
2693 [(set (match_operand:DF 0 "register_operand" "=f")
2694 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2695 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2697 [(set_attr "type" "fcvt")
2698 (set_attr "cnv_mode" "S2D")
2699 (set_attr "mode" "DF")])
2702 ;; ....................
2706 ;; ....................
2708 (define_expand "fix_truncdfsi2"
2709 [(set (match_operand:SI 0 "register_operand")
2710 (fix:SI (match_operand:DF 1 "register_operand")))]
2711 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2713 if (!ISA_HAS_TRUNC_W)
2715 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2720 (define_insn "fix_truncdfsi2_insn"
2721 [(set (match_operand:SI 0 "register_operand" "=f")
2722 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2723 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2725 [(set_attr "type" "fcvt")
2726 (set_attr "mode" "DF")
2727 (set_attr "cnv_mode" "D2I")
2728 (set_attr "length" "4")])
2730 (define_insn "fix_truncdfsi2_macro"
2731 [(set (match_operand:SI 0 "register_operand" "=f")
2732 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2733 (clobber (match_scratch:DF 2 "=d"))]
2734 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2737 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2739 return "trunc.w.d %0,%1,%2";
2741 [(set_attr "type" "fcvt")
2742 (set_attr "mode" "DF")
2743 (set_attr "cnv_mode" "D2I")
2744 (set_attr "length" "36")])
2746 (define_expand "fix_truncsfsi2"
2747 [(set (match_operand:SI 0 "register_operand")
2748 (fix:SI (match_operand:SF 1 "register_operand")))]
2751 if (!ISA_HAS_TRUNC_W)
2753 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2758 (define_insn "fix_truncsfsi2_insn"
2759 [(set (match_operand:SI 0 "register_operand" "=f")
2760 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2761 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2763 [(set_attr "type" "fcvt")
2764 (set_attr "mode" "SF")
2765 (set_attr "cnv_mode" "S2I")
2766 (set_attr "length" "4")])
2768 (define_insn "fix_truncsfsi2_macro"
2769 [(set (match_operand:SI 0 "register_operand" "=f")
2770 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2771 (clobber (match_scratch:SF 2 "=d"))]
2772 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2775 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2777 return "trunc.w.s %0,%1,%2";
2779 [(set_attr "type" "fcvt")
2780 (set_attr "mode" "SF")
2781 (set_attr "cnv_mode" "S2I")
2782 (set_attr "length" "36")])
2785 (define_insn "fix_truncdfdi2"
2786 [(set (match_operand:DI 0 "register_operand" "=f")
2787 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2788 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2790 [(set_attr "type" "fcvt")
2791 (set_attr "mode" "DF")
2792 (set_attr "cnv_mode" "D2I")
2793 (set_attr "length" "4")])
2796 (define_insn "fix_truncsfdi2"
2797 [(set (match_operand:DI 0 "register_operand" "=f")
2798 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2799 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2801 [(set_attr "type" "fcvt")
2802 (set_attr "mode" "SF")
2803 (set_attr "cnv_mode" "S2I")
2804 (set_attr "length" "4")])
2807 (define_insn "floatsidf2"
2808 [(set (match_operand:DF 0 "register_operand" "=f")
2809 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2810 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2812 [(set_attr "type" "fcvt")
2813 (set_attr "mode" "DF")
2814 (set_attr "cnv_mode" "I2D")
2815 (set_attr "length" "4")])
2818 (define_insn "floatdidf2"
2819 [(set (match_operand:DF 0 "register_operand" "=f")
2820 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2821 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2823 [(set_attr "type" "fcvt")
2824 (set_attr "mode" "DF")
2825 (set_attr "cnv_mode" "I2D")
2826 (set_attr "length" "4")])
2829 (define_insn "floatsisf2"
2830 [(set (match_operand:SF 0 "register_operand" "=f")
2831 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2834 [(set_attr "type" "fcvt")
2835 (set_attr "mode" "SF")
2836 (set_attr "cnv_mode" "I2S")
2837 (set_attr "length" "4")])
2840 (define_insn "floatdisf2"
2841 [(set (match_operand:SF 0 "register_operand" "=f")
2842 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2843 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2845 [(set_attr "type" "fcvt")
2846 (set_attr "mode" "SF")
2847 (set_attr "cnv_mode" "I2S")
2848 (set_attr "length" "4")])
2851 (define_expand "fixuns_truncdfsi2"
2852 [(set (match_operand:SI 0 "register_operand")
2853 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2854 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2856 rtx reg1 = gen_reg_rtx (DFmode);
2857 rtx reg2 = gen_reg_rtx (DFmode);
2858 rtx reg3 = gen_reg_rtx (SImode);
2859 rtx label1 = gen_label_rtx ();
2860 rtx label2 = gen_label_rtx ();
2861 REAL_VALUE_TYPE offset;
2863 real_2expN (&offset, 31, DFmode);
2865 if (reg1) /* Turn off complaints about unreached code. */
2867 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2868 do_pending_stack_adjust ();
2870 emit_insn (gen_cmpdf (operands[1], reg1));
2871 emit_jump_insn (gen_bge (label1));
2873 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2874 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2875 gen_rtx_LABEL_REF (VOIDmode, label2)));
2878 emit_label (label1);
2879 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2880 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2881 (BITMASK_HIGH, SImode)));
2883 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2884 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2886 emit_label (label2);
2888 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2889 fields, and can't be used for REG_NOTES anyway). */
2890 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2896 (define_expand "fixuns_truncdfdi2"
2897 [(set (match_operand:DI 0 "register_operand")
2898 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2899 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2901 rtx reg1 = gen_reg_rtx (DFmode);
2902 rtx reg2 = gen_reg_rtx (DFmode);
2903 rtx reg3 = gen_reg_rtx (DImode);
2904 rtx label1 = gen_label_rtx ();
2905 rtx label2 = gen_label_rtx ();
2906 REAL_VALUE_TYPE offset;
2908 real_2expN (&offset, 63, DFmode);
2910 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2911 do_pending_stack_adjust ();
2913 emit_insn (gen_cmpdf (operands[1], reg1));
2914 emit_jump_insn (gen_bge (label1));
2916 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2917 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2918 gen_rtx_LABEL_REF (VOIDmode, label2)));
2921 emit_label (label1);
2922 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2923 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2924 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2926 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2927 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2929 emit_label (label2);
2931 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2932 fields, and can't be used for REG_NOTES anyway). */
2933 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2938 (define_expand "fixuns_truncsfsi2"
2939 [(set (match_operand:SI 0 "register_operand")
2940 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2943 rtx reg1 = gen_reg_rtx (SFmode);
2944 rtx reg2 = gen_reg_rtx (SFmode);
2945 rtx reg3 = gen_reg_rtx (SImode);
2946 rtx label1 = gen_label_rtx ();
2947 rtx label2 = gen_label_rtx ();
2948 REAL_VALUE_TYPE offset;
2950 real_2expN (&offset, 31, SFmode);
2952 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2953 do_pending_stack_adjust ();
2955 emit_insn (gen_cmpsf (operands[1], reg1));
2956 emit_jump_insn (gen_bge (label1));
2958 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2959 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2960 gen_rtx_LABEL_REF (VOIDmode, label2)));
2963 emit_label (label1);
2964 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2965 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2966 (BITMASK_HIGH, SImode)));
2968 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2969 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2971 emit_label (label2);
2973 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2974 fields, and can't be used for REG_NOTES anyway). */
2975 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2980 (define_expand "fixuns_truncsfdi2"
2981 [(set (match_operand:DI 0 "register_operand")
2982 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2983 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2985 rtx reg1 = gen_reg_rtx (SFmode);
2986 rtx reg2 = gen_reg_rtx (SFmode);
2987 rtx reg3 = gen_reg_rtx (DImode);
2988 rtx label1 = gen_label_rtx ();
2989 rtx label2 = gen_label_rtx ();
2990 REAL_VALUE_TYPE offset;
2992 real_2expN (&offset, 63, SFmode);
2994 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2995 do_pending_stack_adjust ();
2997 emit_insn (gen_cmpsf (operands[1], reg1));
2998 emit_jump_insn (gen_bge (label1));
3000 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3001 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3002 gen_rtx_LABEL_REF (VOIDmode, label2)));
3005 emit_label (label1);
3006 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3007 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3008 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3010 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3011 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3013 emit_label (label2);
3015 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3016 fields, and can't be used for REG_NOTES anyway). */
3017 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
3022 ;; ....................
3026 ;; ....................
3028 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3030 (define_expand "extv"
3031 [(set (match_operand 0 "register_operand")
3032 (sign_extract (match_operand:QI 1 "memory_operand")
3033 (match_operand 2 "immediate_operand")
3034 (match_operand 3 "immediate_operand")))]
3037 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3038 INTVAL (operands[2]),
3039 INTVAL (operands[3])))
3045 (define_expand "extzv"
3046 [(set (match_operand 0 "register_operand")
3047 (zero_extract (match_operand 1 "nonimmediate_operand")
3048 (match_operand 2 "immediate_operand")
3049 (match_operand 3 "immediate_operand")))]
3052 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3053 INTVAL (operands[2]),
3054 INTVAL (operands[3])))
3056 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3057 INTVAL (operands[3])))
3059 if (GET_MODE (operands[0]) == DImode)
3060 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3063 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3071 (define_insn "extzv<mode>"
3072 [(set (match_operand:GPR 0 "register_operand" "=d")
3073 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3074 (match_operand:SI 2 "immediate_operand" "I")
3075 (match_operand:SI 3 "immediate_operand" "I")))]
3076 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3077 INTVAL (operands[3]))"
3078 "<d>ext\t%0,%1,%3,%2"
3079 [(set_attr "type" "arith")
3080 (set_attr "mode" "<MODE>")])
3083 (define_expand "insv"
3084 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3085 (match_operand 1 "immediate_operand")
3086 (match_operand 2 "immediate_operand"))
3087 (match_operand 3 "reg_or_0_operand"))]
3090 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3091 INTVAL (operands[1]),
3092 INTVAL (operands[2])))
3094 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3095 INTVAL (operands[2])))
3097 if (GET_MODE (operands[0]) == DImode)
3098 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3101 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3109 (define_insn "insv<mode>"
3110 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3111 (match_operand:SI 1 "immediate_operand" "I")
3112 (match_operand:SI 2 "immediate_operand" "I"))
3113 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3114 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3115 INTVAL (operands[2]))"
3116 "<d>ins\t%0,%z3,%2,%1"
3117 [(set_attr "type" "arith")
3118 (set_attr "mode" "<MODE>")])
3120 ;; Unaligned word moves generated by the bit field patterns.
3122 ;; As far as the rtl is concerned, both the left-part and right-part
3123 ;; instructions can access the whole field. However, the real operand
3124 ;; refers to just the first or the last byte (depending on endianness).
3125 ;; We therefore use two memory operands to each instruction, one to
3126 ;; describe the rtl effect and one to use in the assembly output.
3128 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3129 ;; This allows us to use the standard length calculations for the "load"
3130 ;; and "store" type attributes.
3132 (define_insn "mov_<load>l"
3133 [(set (match_operand:GPR 0 "register_operand" "=d")
3134 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3135 (match_operand:QI 2 "memory_operand" "m")]
3137 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3139 [(set_attr "type" "load")
3140 (set_attr "mode" "<MODE>")])
3142 (define_insn "mov_<load>r"
3143 [(set (match_operand:GPR 0 "register_operand" "=d")
3144 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3145 (match_operand:QI 2 "memory_operand" "m")
3146 (match_operand:GPR 3 "register_operand" "0")]
3147 UNSPEC_LOAD_RIGHT))]
3148 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3150 [(set_attr "type" "load")
3151 (set_attr "mode" "<MODE>")])
3153 (define_insn "mov_<store>l"
3154 [(set (match_operand:BLK 0 "memory_operand" "=m")
3155 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3156 (match_operand:QI 2 "memory_operand" "m")]
3157 UNSPEC_STORE_LEFT))]
3158 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3160 [(set_attr "type" "store")
3161 (set_attr "mode" "<MODE>")])
3163 (define_insn "mov_<store>r"
3164 [(set (match_operand:BLK 0 "memory_operand" "+m")
3165 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3166 (match_operand:QI 2 "memory_operand" "m")
3168 UNSPEC_STORE_RIGHT))]
3169 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3171 [(set_attr "type" "store")
3172 (set_attr "mode" "<MODE>")])
3174 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3175 ;; The required value is:
3177 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3179 ;; which translates to:
3181 ;; lui op0,%highest(op1)
3182 ;; daddiu op0,op0,%higher(op1)
3184 ;; daddiu op0,op0,%hi(op1)
3187 ;; The split is deferred until after flow2 to allow the peephole2 below
3189 (define_insn_and_split "*lea_high64"
3190 [(set (match_operand:DI 0 "register_operand" "=d")
3191 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3192 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3194 "&& epilogue_completed"
3195 [(set (match_dup 0) (high:DI (match_dup 2)))
3196 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3197 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3198 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3199 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3201 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3202 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3204 [(set_attr "length" "20")])
3206 ;; Use a scratch register to reduce the latency of the above pattern
3207 ;; on superscalar machines. The optimized sequence is:
3209 ;; lui op1,%highest(op2)
3211 ;; daddiu op1,op1,%higher(op2)
3213 ;; daddu op1,op1,op0
3215 [(set (match_operand:DI 1 "register_operand")
3216 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3217 (match_scratch:DI 0 "d")]
3218 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3219 [(set (match_dup 1) (high:DI (match_dup 3)))
3220 (set (match_dup 0) (high:DI (match_dup 4)))
3221 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3222 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3223 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3225 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3226 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3229 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3230 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3231 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3232 ;; used once. We can then use the sequence:
3234 ;; lui op0,%highest(op1)
3236 ;; daddiu op0,op0,%higher(op1)
3237 ;; daddiu op2,op2,%lo(op1)
3239 ;; daddu op0,op0,op2
3241 ;; which takes 4 cycles on most superscalar targets.
3242 (define_insn_and_split "*lea64"
3243 [(set (match_operand:DI 0 "register_operand" "=d")
3244 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3245 (clobber (match_scratch:DI 2 "=&d"))]
3246 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3248 "&& reload_completed"
3249 [(set (match_dup 0) (high:DI (match_dup 3)))
3250 (set (match_dup 2) (high:DI (match_dup 4)))
3251 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3252 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3253 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3254 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3256 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3257 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3259 [(set_attr "length" "24")])
3261 ;; Split HIGHs into:
3266 ;; on MIPS16 targets.
3268 [(set (match_operand:SI 0 "register_operand" "=d")
3269 (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
3270 "TARGET_MIPS16 && reload_completed"
3271 [(set (match_dup 0) (match_dup 2))
3272 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3274 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3277 ;; Insns to fetch a symbol from a big GOT.
3279 (define_insn_and_split "*xgot_hi<mode>"
3280 [(set (match_operand:P 0 "register_operand" "=d")
3281 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3282 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3284 "&& reload_completed"
3285 [(set (match_dup 0) (high:P (match_dup 2)))
3286 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3288 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3289 operands[3] = pic_offset_table_rtx;
3291 [(set_attr "got" "xgot_high")
3292 (set_attr "mode" "<MODE>")])
3294 (define_insn_and_split "*xgot_lo<mode>"
3295 [(set (match_operand:P 0 "register_operand" "=d")
3296 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3297 (match_operand:P 2 "got_disp_operand" "")))]
3298 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3300 "&& reload_completed"
3302 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3303 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3304 [(set_attr "got" "load")
3305 (set_attr "mode" "<MODE>")])
3307 ;; Insns to fetch a symbol from a normal GOT.
3309 (define_insn_and_split "*got_disp<mode>"
3310 [(set (match_operand:P 0 "register_operand" "=d")
3311 (match_operand:P 1 "got_disp_operand" ""))]
3312 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3314 "&& reload_completed"
3316 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3318 operands[2] = pic_offset_table_rtx;
3319 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3321 [(set_attr "got" "load")
3322 (set_attr "mode" "<MODE>")])
3324 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3326 (define_insn_and_split "*got_page<mode>"
3327 [(set (match_operand:P 0 "register_operand" "=d")
3328 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3329 "TARGET_EXPLICIT_RELOCS"
3331 "&& reload_completed"
3333 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3335 operands[2] = pic_offset_table_rtx;
3336 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3338 [(set_attr "got" "load")
3339 (set_attr "mode" "<MODE>")])
3341 ;; Lower-level instructions for loading an address from the GOT.
3342 ;; We could use MEMs, but an unspec gives more optimization
3345 (define_insn "load_got<mode>"
3346 [(set (match_operand:P 0 "register_operand" "=d")
3347 (unspec:P [(match_operand:P 1 "register_operand" "d")
3348 (match_operand:P 2 "immediate_operand" "")]
3351 "<load>\t%0,%R2(%1)"
3352 [(set_attr "type" "load")
3353 (set_attr "mode" "<MODE>")
3354 (set_attr "length" "4")])
3356 ;; Instructions for adding the low 16 bits of an address to a register.
3357 ;; Operand 2 is the address: mips_print_operand works out which relocation
3358 ;; should be applied.
3360 (define_insn "*low<mode>"
3361 [(set (match_operand:P 0 "register_operand" "=d")
3362 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3363 (match_operand:P 2 "immediate_operand" "")))]
3365 "<d>addiu\t%0,%1,%R2"
3366 [(set_attr "type" "arith")
3367 (set_attr "mode" "<MODE>")])
3369 (define_insn "*low<mode>_mips16"
3370 [(set (match_operand:P 0 "register_operand" "=d")
3371 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3372 (match_operand:P 2 "immediate_operand" "")))]
3375 [(set_attr "type" "arith")
3376 (set_attr "mode" "<MODE>")
3377 (set_attr "length" "8")])
3379 ;; Allow combine to split complex const_int load sequences, using operand 2
3380 ;; to store the intermediate results. See move_operand for details.
3382 [(set (match_operand:GPR 0 "register_operand")
3383 (match_operand:GPR 1 "splittable_const_int_operand"))
3384 (clobber (match_operand:GPR 2 "register_operand"))]
3388 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3392 ;; Likewise, for symbolic operands.
3394 [(set (match_operand:P 0 "register_operand")
3395 (match_operand:P 1))
3396 (clobber (match_operand:P 2 "register_operand"))]
3397 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3398 [(set (match_dup 0) (match_dup 3))]
3400 mips_split_symbol (operands[2], operands[1],
3401 MAX_MACHINE_MODE, &operands[3]);
3404 ;; 64-bit integer moves
3406 ;; Unlike most other insns, the move insns can't be split with
3407 ;; different predicates, because register spilling and other parts of
3408 ;; the compiler, have memoized the insn number already.
3410 (define_expand "movdi"
3411 [(set (match_operand:DI 0 "")
3412 (match_operand:DI 1 ""))]
3415 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3419 ;; For mips16, we need a special case to handle storing $31 into
3420 ;; memory, since we don't have a constraint to match $31. This
3421 ;; instruction can be generated by save_restore_insns.
3423 (define_insn "*mov<mode>_ra"
3424 [(set (match_operand:GPR 0 "stack_operand" "=m")
3428 [(set_attr "type" "store")
3429 (set_attr "mode" "<MODE>")])
3431 (define_insn "*movdi_32bit"
3432 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3433 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3434 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3435 && (register_operand (operands[0], DImode)
3436 || reg_or_0_operand (operands[1], DImode))"
3437 { return mips_output_move (operands[0], operands[1]); }
3438 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3439 (set_attr "mode" "DI")
3440 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3442 (define_insn "*movdi_gp32_fp64"
3443 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m")
3444 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f"))]
3445 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3446 && (register_operand (operands[0], DImode)
3447 || reg_or_0_operand (operands[1], DImode))"
3448 { return mips_output_move (operands[0], operands[1]); }
3449 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3450 (set_attr "mode" "DI")
3451 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3453 (define_insn "*movdi_32bit_mips16"
3454 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3455 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3456 "!TARGET_64BIT && TARGET_MIPS16
3457 && (register_operand (operands[0], DImode)
3458 || register_operand (operands[1], DImode))"
3459 { return mips_output_move (operands[0], operands[1]); }
3460 [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
3461 (set_attr "mode" "DI")
3462 (set_attr "length" "8,8,8,8,12,*,*,8")])
3464 (define_insn "*movdi_64bit"
3465 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3466 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3467 "TARGET_64BIT && !TARGET_MIPS16
3468 && (register_operand (operands[0], DImode)
3469 || reg_or_0_operand (operands[1], DImode))"
3470 { return mips_output_move (operands[0], operands[1]); }
3471 [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3472 (set_attr "mode" "DI")
3473 (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")])
3475 (define_insn "*movdi_64bit_mips16"
3476 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3477 (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3478 "TARGET_64BIT && TARGET_MIPS16
3479 && (register_operand (operands[0], DImode)
3480 || register_operand (operands[1], DImode))"
3481 { return mips_output_move (operands[0], operands[1]); }
3482 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3483 (set_attr "mode" "DI")
3484 (set_attr_alternative "length"
3488 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3491 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3497 (const_string "*")])])
3500 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3501 ;; when the original load is a 4 byte instruction but the add and the
3502 ;; load are 2 2 byte instructions.
3505 [(set (match_operand:DI 0 "register_operand")
3506 (mem:DI (plus:DI (match_dup 0)
3507 (match_operand:DI 1 "const_int_operand"))))]
3508 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3509 && !TARGET_DEBUG_D_MODE
3510 && REG_P (operands[0])
3511 && M16_REG_P (REGNO (operands[0]))
3512 && GET_CODE (operands[1]) == CONST_INT
3513 && ((INTVAL (operands[1]) < 0
3514 && INTVAL (operands[1]) >= -0x10)
3515 || (INTVAL (operands[1]) >= 32 * 8
3516 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3517 || (INTVAL (operands[1]) >= 0
3518 && INTVAL (operands[1]) < 32 * 8
3519 && (INTVAL (operands[1]) & 7) != 0))"
3520 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3521 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3523 HOST_WIDE_INT val = INTVAL (operands[1]);
3526 operands[2] = const0_rtx;
3527 else if (val >= 32 * 8)
3531 operands[1] = GEN_INT (0x8 + off);
3532 operands[2] = GEN_INT (val - off - 0x8);
3538 operands[1] = GEN_INT (off);
3539 operands[2] = GEN_INT (val - off);
3543 ;; 32-bit Integer moves
3545 ;; Unlike most other insns, the move insns can't be split with
3546 ;; different predicates, because register spilling and other parts of
3547 ;; the compiler, have memoized the insn number already.
3549 (define_expand "movsi"
3550 [(set (match_operand:SI 0 "")
3551 (match_operand:SI 1 ""))]
3554 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3558 ;; The difference between these two is whether or not ints are allowed
3559 ;; in FP registers (off by default, use -mdebugh to enable).
3561 (define_insn "*movsi_internal"
3562 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3563 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3565 && (register_operand (operands[0], SImode)
3566 || reg_or_0_operand (operands[1], SImode))"
3567 { return mips_output_move (operands[0], operands[1]); }
3568 [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3569 (set_attr "mode" "SI")
3570 (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")])
3572 (define_insn "*movsi_mips16"
3573 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3574 (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3576 && (register_operand (operands[0], SImode)
3577 || register_operand (operands[1], SImode))"
3578 { return mips_output_move (operands[0], operands[1]); }
3579 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3580 (set_attr "mode" "SI")
3581 (set_attr_alternative "length"
3585 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3588 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3594 (const_string "*")])])
3596 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3597 ;; when the original load is a 4 byte instruction but the add and the
3598 ;; load are 2 2 byte instructions.
3601 [(set (match_operand:SI 0 "register_operand")
3602 (mem:SI (plus:SI (match_dup 0)
3603 (match_operand:SI 1 "const_int_operand"))))]
3604 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3605 && REG_P (operands[0])
3606 && M16_REG_P (REGNO (operands[0]))
3607 && GET_CODE (operands[1]) == CONST_INT
3608 && ((INTVAL (operands[1]) < 0
3609 && INTVAL (operands[1]) >= -0x80)
3610 || (INTVAL (operands[1]) >= 32 * 4
3611 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3612 || (INTVAL (operands[1]) >= 0
3613 && INTVAL (operands[1]) < 32 * 4
3614 && (INTVAL (operands[1]) & 3) != 0))"
3615 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3616 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3618 HOST_WIDE_INT val = INTVAL (operands[1]);
3621 operands[2] = const0_rtx;
3622 else if (val >= 32 * 4)
3626 operands[1] = GEN_INT (0x7c + off);
3627 operands[2] = GEN_INT (val - off - 0x7c);
3633 operands[1] = GEN_INT (off);
3634 operands[2] = GEN_INT (val - off);
3638 ;; On the mips16, we can split a load of certain constants into a load
3639 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3643 [(set (match_operand:SI 0 "register_operand")
3644 (match_operand:SI 1 "const_int_operand"))]
3645 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3646 && REG_P (operands[0])
3647 && M16_REG_P (REGNO (operands[0]))
3648 && GET_CODE (operands[1]) == CONST_INT
3649 && INTVAL (operands[1]) >= 0x100
3650 && INTVAL (operands[1]) <= 0xff + 0x7f"
3651 [(set (match_dup 0) (match_dup 1))
3652 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3654 int val = INTVAL (operands[1]);
3656 operands[1] = GEN_INT (0xff);
3657 operands[2] = GEN_INT (val - 0xff);
3660 ;; This insn handles moving CCmode values. It's really just a
3661 ;; slightly simplified copy of movsi_internal2, with additional cases
3662 ;; to move a condition register to a general register and to move
3663 ;; between the general registers and the floating point registers.
3665 (define_insn "movcc"
3666 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3667 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3668 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3669 { return mips_output_move (operands[0], operands[1]); }
3670 [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3671 (set_attr "mode" "SI")
3672 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3674 ;; Reload condition code registers. reload_incc and reload_outcc
3675 ;; both handle moves from arbitrary operands into condition code
3676 ;; registers. reload_incc handles the more common case in which
3677 ;; a source operand is constrained to be in a condition-code
3678 ;; register, but has not been allocated to one.
3680 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3681 ;; constraints do not include 'z'. reload_outcc handles the case
3682 ;; when such an operand is allocated to a condition-code register.
3684 ;; Note that reloads from a condition code register to some
3685 ;; other location can be done using ordinary moves. Moving
3686 ;; into a GPR takes a single movcc, moving elsewhere takes
3687 ;; two. We can leave these cases to the generic reload code.
3688 (define_expand "reload_incc"
3689 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3690 (match_operand:CC 1 "general_operand" ""))
3691 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3692 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3694 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
3698 (define_expand "reload_outcc"
3699 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3700 (match_operand:CC 1 "register_operand" ""))
3701 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3702 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3704 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
3708 ;; MIPS4 supports loading and storing a floating point register from
3709 ;; the sum of two general registers. We use two versions for each of
3710 ;; these four instructions: one where the two general registers are
3711 ;; SImode, and one where they are DImode. This is because general
3712 ;; registers will be in SImode when they hold 32-bit values, but,
3713 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3714 ;; instructions will still work correctly.
3716 ;; ??? Perhaps it would be better to support these instructions by
3717 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3718 ;; these instructions can only be used to load and store floating
3719 ;; point registers, that would probably cause trouble in reload.
3721 (define_insn "*<ANYF:loadx>_<P:mode>"
3722 [(set (match_operand:ANYF 0 "register_operand" "=f")
3723 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3724 (match_operand:P 2 "register_operand" "d"))))]
3726 "<ANYF:loadx>\t%0,%1(%2)"
3727 [(set_attr "type" "fpidxload")
3728 (set_attr "mode" "<ANYF:UNITMODE>")])
3730 (define_insn "*<ANYF:storex>_<P:mode>"
3731 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3732 (match_operand:P 2 "register_operand" "d")))
3733 (match_operand:ANYF 0 "register_operand" "f"))]
3735 "<ANYF:storex>\t%0,%1(%2)"
3736 [(set_attr "type" "fpidxstore")
3737 (set_attr "mode" "<ANYF:UNITMODE>")])
3739 ;; Scaled indexed address load.
3740 ;; Per md.texi, we only need to look for a pattern with multiply in the
3741 ;; address expression, not shift.
3743 (define_insn "*lwxs"
3744 [(set (match_operand:SI 0 "register_operand" "=d")
3745 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
3747 (match_operand:SI 2 "register_operand" "d"))))]
3750 [(set_attr "type" "load")
3751 (set_attr "mode" "SI")
3752 (set_attr "length" "4")])
3754 ;; 16-bit Integer moves
3756 ;; Unlike most other insns, the move insns can't be split with
3757 ;; different predicates, because register spilling and other parts of
3758 ;; the compiler, have memoized the insn number already.
3759 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3761 (define_expand "movhi"
3762 [(set (match_operand:HI 0 "")
3763 (match_operand:HI 1 ""))]
3766 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3770 (define_insn "*movhi_internal"
3771 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x")
3772 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))]
3774 && (register_operand (operands[0], HImode)
3775 || reg_or_0_operand (operands[1], HImode))"
3782 [(set_attr "type" "move,arith,load,store,mthilo")
3783 (set_attr "mode" "HI")
3784 (set_attr "length" "4,4,*,*,4")])
3786 (define_insn "*movhi_mips16"
3787 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3788 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3790 && (register_operand (operands[0], HImode)
3791 || register_operand (operands[1], HImode))"
3800 [(set_attr "type" "move,move,move,arith,arith,load,store")
3801 (set_attr "mode" "HI")
3802 (set_attr_alternative "length"
3806 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3809 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3813 (const_string "*")])])
3816 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3817 ;; when the original load is a 4 byte instruction but the add and the
3818 ;; load are 2 2 byte instructions.
3821 [(set (match_operand:HI 0 "register_operand")
3822 (mem:HI (plus:SI (match_dup 0)
3823 (match_operand:SI 1 "const_int_operand"))))]
3824 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3825 && REG_P (operands[0])
3826 && M16_REG_P (REGNO (operands[0]))
3827 && GET_CODE (operands[1]) == CONST_INT
3828 && ((INTVAL (operands[1]) < 0
3829 && INTVAL (operands[1]) >= -0x80)
3830 || (INTVAL (operands[1]) >= 32 * 2
3831 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3832 || (INTVAL (operands[1]) >= 0
3833 && INTVAL (operands[1]) < 32 * 2
3834 && (INTVAL (operands[1]) & 1) != 0))"
3835 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3836 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3838 HOST_WIDE_INT val = INTVAL (operands[1]);
3841 operands[2] = const0_rtx;
3842 else if (val >= 32 * 2)
3846 operands[1] = GEN_INT (0x7e + off);
3847 operands[2] = GEN_INT (val - off - 0x7e);
3853 operands[1] = GEN_INT (off);
3854 operands[2] = GEN_INT (val - off);
3858 ;; 8-bit Integer moves
3860 ;; Unlike most other insns, the move insns can't be split with
3861 ;; different predicates, because register spilling and other parts of
3862 ;; the compiler, have memoized the insn number already.
3863 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3865 (define_expand "movqi"
3866 [(set (match_operand:QI 0 "")
3867 (match_operand:QI 1 ""))]
3870 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3874 (define_insn "*movqi_internal"
3875 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x")
3876 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))]
3878 && (register_operand (operands[0], QImode)
3879 || reg_or_0_operand (operands[1], QImode))"
3886 [(set_attr "type" "move,arith,load,store,mthilo")
3887 (set_attr "mode" "QI")
3888 (set_attr "length" "4,4,*,*,4")])
3890 (define_insn "*movqi_mips16"
3891 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3892 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3894 && (register_operand (operands[0], QImode)
3895 || register_operand (operands[1], QImode))"
3904 [(set_attr "type" "move,move,move,arith,arith,load,store")
3905 (set_attr "mode" "QI")
3906 (set_attr "length" "4,4,4,4,8,*,*")])
3908 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3909 ;; when the original load is a 4 byte instruction but the add and the
3910 ;; load are 2 2 byte instructions.
3913 [(set (match_operand:QI 0 "register_operand")
3914 (mem:QI (plus:SI (match_dup 0)
3915 (match_operand:SI 1 "const_int_operand"))))]
3916 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3917 && REG_P (operands[0])
3918 && M16_REG_P (REGNO (operands[0]))
3919 && GET_CODE (operands[1]) == CONST_INT
3920 && ((INTVAL (operands[1]) < 0
3921 && INTVAL (operands[1]) >= -0x80)
3922 || (INTVAL (operands[1]) >= 32
3923 && INTVAL (operands[1]) <= 31 + 0x7f))"
3924 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3925 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3927 HOST_WIDE_INT val = INTVAL (operands[1]);
3930 operands[2] = const0_rtx;
3933 operands[1] = GEN_INT (0x7f);
3934 operands[2] = GEN_INT (val - 0x7f);
3938 ;; 32-bit floating point moves
3940 (define_expand "movsf"
3941 [(set (match_operand:SF 0 "")
3942 (match_operand:SF 1 ""))]
3945 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3949 (define_insn "*movsf_hardfloat"
3950 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3951 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3953 && (register_operand (operands[0], SFmode)
3954 || reg_or_0_operand (operands[1], SFmode))"
3955 { return mips_output_move (operands[0], operands[1]); }
3956 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3957 (set_attr "mode" "SF")
3958 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3960 (define_insn "*movsf_softfloat"
3961 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3962 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3963 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3964 && (register_operand (operands[0], SFmode)
3965 || reg_or_0_operand (operands[1], SFmode))"
3966 { return mips_output_move (operands[0], operands[1]); }
3967 [(set_attr "type" "move,load,store")
3968 (set_attr "mode" "SF")
3969 (set_attr "length" "4,*,*")])
3971 (define_insn "*movsf_mips16"
3972 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3973 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3975 && (register_operand (operands[0], SFmode)
3976 || register_operand (operands[1], SFmode))"
3977 { return mips_output_move (operands[0], operands[1]); }
3978 [(set_attr "type" "move,move,move,load,store")
3979 (set_attr "mode" "SF")
3980 (set_attr "length" "4,4,4,*,*")])
3983 ;; 64-bit floating point moves
3985 (define_expand "movdf"
3986 [(set (match_operand:DF 0 "")
3987 (match_operand:DF 1 ""))]
3990 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3994 (define_insn "*movdf_hardfloat_64bit"
3995 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3996 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3997 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3998 && (register_operand (operands[0], DFmode)
3999 || reg_or_0_operand (operands[1], DFmode))"
4000 { return mips_output_move (operands[0], operands[1]); }
4001 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4002 (set_attr "mode" "DF")
4003 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4005 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
4006 (define_insn "*movdf_hardfloat_32bit"
4007 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4008 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4009 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
4010 && (register_operand (operands[0], DFmode)
4011 || reg_or_0_operand (operands[1], DFmode))"
4012 { return mips_output_move (operands[0], operands[1]); }
4013 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4014 (set_attr "mode" "DF")
4015 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
4017 (define_insn "*movdf_softfloat"
4018 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
4019 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
4020 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4021 && (register_operand (operands[0], DFmode)
4022 || reg_or_0_operand (operands[1], DFmode))"
4023 { return mips_output_move (operands[0], operands[1]); }
4024 [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
4025 (set_attr "mode" "DF")
4026 (set_attr "length" "8,*,*,4,4,4")])
4028 (define_insn "*movdf_mips16"
4029 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4030 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4032 && (register_operand (operands[0], DFmode)
4033 || register_operand (operands[1], DFmode))"
4034 { return mips_output_move (operands[0], operands[1]); }
4035 [(set_attr "type" "multi,multi,multi,load,store")
4036 (set_attr "mode" "DF")
4037 (set_attr "length" "8,8,8,*,*")])
4039 ;; 128-bit floating point moves
4041 (define_expand "movtf"
4042 [(set (match_operand:TF 0 "")
4043 (match_operand:TF 1 ""))]
4046 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4050 ;; This pattern handles both hard- and soft-float cases.
4051 (define_insn_and_split "*movtf_internal"
4052 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,R,f,dR")
4053 (match_operand:TF 1 "move_operand" "dGR,dG,dGR,f"))]
4056 "&& reload_completed"
4059 mips_split_doubleword_move (operands[0], operands[1]);
4062 [(set_attr "type" "multi")
4063 (set_attr "length" "16")])
4066 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4067 (match_operand:MOVE64 1 "move_operand"))]
4068 "reload_completed && !TARGET_64BIT
4069 && mips_split_64bit_move_p (operands[0], operands[1])"
4072 mips_split_doubleword_move (operands[0], operands[1]);
4076 ;; When generating mips16 code, split moves of negative constants into
4077 ;; a positive "li" followed by a negation.
4079 [(set (match_operand 0 "register_operand")
4080 (match_operand 1 "const_int_operand"))]
4081 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4085 (neg:SI (match_dup 2)))]
4087 operands[2] = gen_lowpart (SImode, operands[0]);
4088 operands[3] = GEN_INT (-INTVAL (operands[1]));
4091 ;; 64-bit paired-single floating point moves
4093 (define_expand "movv2sf"
4094 [(set (match_operand:V2SF 0)
4095 (match_operand:V2SF 1))]
4096 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4098 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4102 (define_insn "movv2sf_hardfloat_64bit"
4103 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4104 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4106 && TARGET_PAIRED_SINGLE_FLOAT
4108 && (register_operand (operands[0], V2SFmode)
4109 || reg_or_0_operand (operands[1], V2SFmode))"
4110 { return mips_output_move (operands[0], operands[1]); }
4111 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4112 (set_attr "mode" "SF")
4113 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4115 (define_insn "movv2sf_hardfloat_32bit"
4116 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4117 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4119 && TARGET_PAIRED_SINGLE_FLOAT
4121 && (register_operand (operands[0], V2SFmode)
4122 || reg_or_0_operand (operands[1], V2SFmode))"
4123 { return mips_output_move (operands[0], operands[1]); }
4124 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4125 (set_attr "mode" "SF")
4126 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
4128 ;; The HI and LO registers are not truly independent. If we move an mthi
4129 ;; instruction before an mflo instruction, it will make the result of the
4130 ;; mflo unpredictable. The same goes for mtlo and mfhi.
4132 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
4133 ;; Operand 1 is the register we want, operand 2 is the other one.
4135 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
4136 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
4137 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
4139 (define_expand "mfhilo_<mode>"
4140 [(set (match_operand:GPR 0 "register_operand")
4141 (unspec:GPR [(match_operand:GPR 1 "register_operand")
4142 (match_operand:GPR 2 "register_operand")]
4145 (define_insn "*mfhilo_<mode>"
4146 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4147 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4148 (match_operand:GPR 2 "register_operand" "l,h")]
4152 [(set_attr "type" "mfhilo")
4153 (set_attr "mode" "<MODE>")])
4155 (define_insn "*mfhilo_<mode>_macc"
4156 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4157 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4158 (match_operand:GPR 2 "register_operand" "l,h")]
4164 [(set_attr "type" "mfhilo")
4165 (set_attr "mode" "<MODE>")])
4167 ;; Emit a doubleword move in which exactly one of the operands is
4168 ;; a floating-point register. We can't just emit two normal moves
4169 ;; because of the constraints imposed by the FPU register model;
4170 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4171 ;; the FPR whole and use special patterns to refer to each word of
4172 ;; the other operand.
4174 (define_expand "move_doubleword_fpr<mode>"
4175 [(set (match_operand:SPLITF 0)
4176 (match_operand:SPLITF 1))]
4179 if (FP_REG_RTX_P (operands[0]))
4181 rtx low = mips_subword (operands[1], 0);
4182 rtx high = mips_subword (operands[1], 1);
4183 emit_insn (gen_load_low<mode> (operands[0], low));
4185 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4187 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4191 rtx low = mips_subword (operands[0], 0);
4192 rtx high = mips_subword (operands[0], 1);
4193 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4195 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4197 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4202 ;; Load the low word of operand 0 with operand 1.
4203 (define_insn "load_low<mode>"
4204 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4205 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4209 operands[0] = mips_subword (operands[0], 0);
4210 return mips_output_move (operands[0], operands[1]);
4212 [(set_attr "type" "mtc,fpload")
4213 (set_attr "mode" "<HALFMODE>")])
4215 ;; Load the high word of operand 0 from operand 1, preserving the value
4217 (define_insn "load_high<mode>"
4218 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4219 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4220 (match_operand:SPLITF 2 "register_operand" "0,0")]
4224 operands[0] = mips_subword (operands[0], 1);
4225 return mips_output_move (operands[0], operands[1]);
4227 [(set_attr "type" "mtc,fpload")
4228 (set_attr "mode" "<HALFMODE>")])
4230 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4231 ;; high word and 0 to store the low word.
4232 (define_insn "store_word<mode>"
4233 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4234 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4235 (match_operand 2 "const_int_operand")]
4236 UNSPEC_STORE_WORD))]
4239 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4240 return mips_output_move (operands[0], operands[1]);
4242 [(set_attr "type" "mfc,fpstore")
4243 (set_attr "mode" "<HALFMODE>")])
4245 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4246 ;; value in the low word.
4247 (define_insn "mthc1<mode>"
4248 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4249 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ")
4250 (match_operand:SPLITF 2 "register_operand" "0")]
4252 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4254 [(set_attr "type" "mtc")
4255 (set_attr "mode" "<HALFMODE>")])
4257 ;; Move high word of operand 1 to operand 0 using mfhc1.
4258 (define_insn "mfhc1<mode>"
4259 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4260 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4262 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4264 [(set_attr "type" "mfc")
4265 (set_attr "mode" "<HALFMODE>")])
4267 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4268 (define_expand "load_const_gp"
4269 [(set (match_operand 0 "register_operand" "=d")
4270 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4272 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4273 ;; of _gp from the start of this function. Operand 1 is the incoming
4274 ;; function address.
4275 (define_insn_and_split "loadgp_newabi_<mode>"
4276 [(set (match_operand:P 0 "register_operand" "=d")
4277 (unspec_volatile:P [(match_operand:P 1)
4278 (match_operand:P 2 "register_operand" "d")]
4280 "mips_current_loadgp_style () == LOADGP_NEWABI"
4283 [(set (match_dup 0) (match_dup 3))
4284 (set (match_dup 0) (match_dup 4))
4285 (set (match_dup 0) (match_dup 5))]
4287 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4288 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4289 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4291 [(set_attr "length" "12")])
4293 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4294 (define_insn_and_split "loadgp_absolute_<mode>"
4295 [(set (match_operand:P 0 "register_operand" "=d")
4296 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4297 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4302 mips_emit_move (operands[0], operands[1]);
4305 [(set_attr "length" "8")])
4307 ;; The use of gp is hidden when not using explicit relocations.
4308 ;; This blockage instruction prevents the gp load from being
4309 ;; scheduled after an implicit use of gp. It also prevents
4310 ;; the load from being deleted as dead.
4311 (define_insn "loadgp_blockage"
4312 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4315 [(set_attr "type" "unknown")
4316 (set_attr "mode" "none")
4317 (set_attr "length" "0")])
4319 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4320 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4321 (define_insn_and_split "loadgp_rtp_<mode>"
4322 [(set (match_operand:P 0 "register_operand" "=d")
4323 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4324 (match_operand:P 2 "symbol_ref_operand")]
4326 "mips_current_loadgp_style () == LOADGP_RTP"
4329 [(set (match_dup 0) (high:P (match_dup 3)))
4330 (set (match_dup 0) (unspec:P [(match_dup 0)
4331 (match_dup 3)] UNSPEC_LOAD_GOT))
4332 (set (match_dup 0) (unspec:P [(match_dup 0)
4333 (match_dup 4)] UNSPEC_LOAD_GOT))]
4335 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4336 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4338 [(set_attr "length" "12")])
4340 ;; Emit a .cprestore directive, which normally expands to a single store
4341 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4342 ;; code so that jals inside inline asms will work correctly.
4343 (define_insn "cprestore"
4344 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4349 if (set_nomacro && which_alternative == 1)
4350 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4352 return ".cprestore\t%0";
4354 [(set_attr "type" "store")
4355 (set_attr "length" "4,12")])
4357 ;; Expand in-line code to clear the instruction cache between operand[0] and
4359 (define_expand "clear_cache"
4360 [(match_operand 0 "pmode_register_operand")
4361 (match_operand 1 "pmode_register_operand")]
4367 mips_expand_synci_loop (operands[0], operands[1]);
4368 emit_insn (gen_sync ());
4369 emit_insn (gen_clear_hazard ());
4371 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4373 rtx len = gen_reg_rtx (Pmode);
4374 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4375 MIPS_ICACHE_SYNC (operands[0], len);
4381 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4385 (define_insn "synci"
4386 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4391 (define_insn "rdhwr"
4392 [(set (match_operand:SI 0 "register_operand" "=d")
4393 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4398 (define_insn "clear_hazard"
4399 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4400 (clobber (reg:SI 31))]
4403 return "%(%<bal\t1f\n"
4405 "1:\taddiu\t$31,$31,12\n"
4409 [(set_attr "length" "20")])
4411 ;; Atomic memory operations.
4413 (define_insn "memory_barrier"
4414 [(set (mem:BLK (scratch))
4415 (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))]
4419 (define_insn "sync_compare_and_swap<mode>"
4420 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4421 (match_operand:GPR 1 "memory_operand" "+R,R"))
4423 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
4424 (match_operand:GPR 3 "arith_operand" "I,d")]
4425 UNSPEC_COMPARE_AND_SWAP))]
4428 if (which_alternative == 0)
4429 return MIPS_COMPARE_AND_SWAP ("<d>", "li");
4431 return MIPS_COMPARE_AND_SWAP ("<d>", "move");
4433 [(set_attr "length" "32")])
4435 (define_insn "sync_add<mode>"
4436 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4437 (unspec_volatile:GPR
4438 [(plus:GPR (match_dup 0)
4439 (match_operand:GPR 1 "arith_operand" "I,d"))]
4440 UNSPEC_SYNC_OLD_OP))]
4443 if (which_alternative == 0)
4444 return MIPS_SYNC_OP ("<d>", "<d>addiu");
4446 return MIPS_SYNC_OP ("<d>", "<d>addu");
4448 [(set_attr "length" "28")])
4450 (define_insn "sync_sub<mode>"
4451 [(set (match_operand:GPR 0 "memory_operand" "+R")
4452 (unspec_volatile:GPR
4453 [(minus:GPR (match_dup 0)
4454 (match_operand:GPR 1 "register_operand" "d"))]
4455 UNSPEC_SYNC_OLD_OP))]
4458 return MIPS_SYNC_OP ("<d>", "<d>subu");
4460 [(set_attr "length" "28")])
4462 (define_insn "sync_old_add<mode>"
4463 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4464 (match_operand:GPR 1 "memory_operand" "+R,R"))
4466 (unspec_volatile:GPR
4467 [(plus:GPR (match_dup 1)
4468 (match_operand:GPR 2 "arith_operand" "I,d"))]
4469 UNSPEC_SYNC_OLD_OP))]
4472 if (which_alternative == 0)
4473 return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
4475 return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
4477 [(set_attr "length" "28")])
4479 (define_insn "sync_old_sub<mode>"
4480 [(set (match_operand:GPR 0 "register_operand" "=&d")
4481 (match_operand:GPR 1 "memory_operand" "+R"))
4483 (unspec_volatile:GPR
4484 [(minus:GPR (match_dup 1)
4485 (match_operand:GPR 2 "register_operand" "d"))]
4486 UNSPEC_SYNC_OLD_OP))]
4489 return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
4491 [(set_attr "length" "28")])
4493 (define_insn "sync_new_add<mode>"
4494 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4495 (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
4496 (match_operand:GPR 2 "arith_operand" "I,d")))
4498 (unspec_volatile:GPR
4499 [(plus:GPR (match_dup 1) (match_dup 2))]
4500 UNSPEC_SYNC_NEW_OP))]
4503 if (which_alternative == 0)
4504 return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
4506 return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
4508 [(set_attr "length" "28")])
4510 (define_insn "sync_new_sub<mode>"
4511 [(set (match_operand:GPR 0 "register_operand" "=&d")
4512 (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
4513 (match_operand:GPR 2 "register_operand" "d")))
4515 (unspec_volatile:GPR
4516 [(minus:GPR (match_dup 1) (match_dup 2))]
4517 UNSPEC_SYNC_NEW_OP))]
4520 return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
4522 [(set_attr "length" "28")])
4524 (define_insn "sync_<optab><mode>"
4525 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4526 (unspec_volatile:GPR
4527 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
4529 UNSPEC_SYNC_OLD_OP))]
4532 if (which_alternative == 0)
4533 return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
4535 return MIPS_SYNC_OP ("<d>", "<insn>");
4537 [(set_attr "length" "28")])
4539 (define_insn "sync_old_<optab><mode>"
4540 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4541 (match_operand:GPR 1 "memory_operand" "+R,R"))
4543 (unspec_volatile:GPR
4544 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4546 UNSPEC_SYNC_OLD_OP))]
4549 if (which_alternative == 0)
4550 return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
4552 return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
4554 [(set_attr "length" "28")])
4556 (define_insn "sync_new_<optab><mode>"
4557 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4558 (match_operand:GPR 1 "memory_operand" "+R,R"))
4560 (unspec_volatile:GPR
4561 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4563 UNSPEC_SYNC_NEW_OP))]
4566 if (which_alternative == 0)
4567 return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
4569 return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
4571 [(set_attr "length" "28")])
4573 (define_insn "sync_nand<mode>"
4574 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4575 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
4576 UNSPEC_SYNC_OLD_OP))]
4579 if (which_alternative == 0)
4580 return MIPS_SYNC_NAND ("<d>", "andi");
4582 return MIPS_SYNC_NAND ("<d>", "and");
4584 [(set_attr "length" "32")])
4586 (define_insn "sync_old_nand<mode>"
4587 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4588 (match_operand:GPR 1 "memory_operand" "+R,R"))
4590 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4591 UNSPEC_SYNC_OLD_OP))]
4594 if (which_alternative == 0)
4595 return MIPS_SYNC_OLD_NAND ("<d>", "andi");
4597 return MIPS_SYNC_OLD_NAND ("<d>", "and");
4599 [(set_attr "length" "32")])
4601 (define_insn "sync_new_nand<mode>"
4602 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4603 (match_operand:GPR 1 "memory_operand" "+R,R"))
4605 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4606 UNSPEC_SYNC_NEW_OP))]
4609 if (which_alternative == 0)
4610 return MIPS_SYNC_NEW_NAND ("<d>", "andi");
4612 return MIPS_SYNC_NEW_NAND ("<d>", "and");
4614 [(set_attr "length" "32")])
4616 (define_insn "sync_lock_test_and_set<mode>"
4617 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4618 (match_operand:GPR 1 "memory_operand" "+R,R"))
4620 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
4621 UNSPEC_SYNC_EXCHANGE))]
4624 if (which_alternative == 0)
4625 return MIPS_SYNC_EXCHANGE ("<d>", "li");
4627 return MIPS_SYNC_EXCHANGE ("<d>", "move");
4629 [(set_attr "length" "24")])
4631 ;; Block moves, see mips.c for more details.
4632 ;; Argument 0 is the destination
4633 ;; Argument 1 is the source
4634 ;; Argument 2 is the length
4635 ;; Argument 3 is the alignment
4637 (define_expand "movmemsi"
4638 [(parallel [(set (match_operand:BLK 0 "general_operand")
4639 (match_operand:BLK 1 "general_operand"))
4640 (use (match_operand:SI 2 ""))
4641 (use (match_operand:SI 3 "const_int_operand"))])]
4642 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4644 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4651 ;; ....................
4655 ;; ....................
4657 (define_expand "<optab><mode>3"
4658 [(set (match_operand:GPR 0 "register_operand")
4659 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4660 (match_operand:SI 2 "arith_operand")))]
4663 /* On the mips16, a shift of more than 8 is a four byte instruction,
4664 so, for a shift between 8 and 16, it is just as fast to do two
4665 shifts of 8 or less. If there is a lot of shifting going on, we
4666 may win in CSE. Otherwise combine will put the shifts back
4667 together again. This can be called by mips_function_arg, so we must
4668 be careful not to allocate a new register if we've reached the
4672 && GET_CODE (operands[2]) == CONST_INT
4673 && INTVAL (operands[2]) > 8
4674 && INTVAL (operands[2]) <= 16
4675 && !reload_in_progress
4676 && !reload_completed)
4678 rtx temp = gen_reg_rtx (<MODE>mode);
4680 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4681 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4682 GEN_INT (INTVAL (operands[2]) - 8)));
4687 (define_insn "*<optab><mode>3"
4688 [(set (match_operand:GPR 0 "register_operand" "=d")
4689 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4690 (match_operand:SI 2 "arith_operand" "dI")))]
4693 if (GET_CODE (operands[2]) == CONST_INT)
4694 operands[2] = GEN_INT (INTVAL (operands[2])
4695 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4697 return "<d><insn>\t%0,%1,%2";
4699 [(set_attr "type" "shift")
4700 (set_attr "mode" "<MODE>")])
4702 (define_insn "*<optab>si3_extend"
4703 [(set (match_operand:DI 0 "register_operand" "=d")
4705 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4706 (match_operand:SI 2 "arith_operand" "dI"))))]
4707 "TARGET_64BIT && !TARGET_MIPS16"
4709 if (GET_CODE (operands[2]) == CONST_INT)
4710 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4712 return "<insn>\t%0,%1,%2";
4714 [(set_attr "type" "shift")
4715 (set_attr "mode" "SI")])
4717 (define_insn "*<optab>si3_mips16"
4718 [(set (match_operand:SI 0 "register_operand" "=d,d")
4719 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4720 (match_operand:SI 2 "arith_operand" "d,I")))]
4723 if (which_alternative == 0)
4724 return "<insn>\t%0,%2";
4726 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4727 return "<insn>\t%0,%1,%2";
4729 [(set_attr "type" "shift")
4730 (set_attr "mode" "SI")
4731 (set_attr_alternative "length"
4733 (if_then_else (match_operand 2 "m16_uimm3_b")
4737 ;; We need separate DImode MIPS16 patterns because of the irregularity
4739 (define_insn "*ashldi3_mips16"
4740 [(set (match_operand:DI 0 "register_operand" "=d,d")
4741 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4742 (match_operand:SI 2 "arith_operand" "d,I")))]
4743 "TARGET_64BIT && TARGET_MIPS16"
4745 if (which_alternative == 0)
4746 return "dsll\t%0,%2";
4748 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4749 return "dsll\t%0,%1,%2";
4751 [(set_attr "type" "shift")
4752 (set_attr "mode" "DI")
4753 (set_attr_alternative "length"
4755 (if_then_else (match_operand 2 "m16_uimm3_b")
4759 (define_insn "*ashrdi3_mips16"
4760 [(set (match_operand:DI 0 "register_operand" "=d,d")
4761 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4762 (match_operand:SI 2 "arith_operand" "d,I")))]
4763 "TARGET_64BIT && TARGET_MIPS16"
4765 if (GET_CODE (operands[2]) == CONST_INT)
4766 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4768 return "dsra\t%0,%2";
4770 [(set_attr "type" "shift")
4771 (set_attr "mode" "DI")
4772 (set_attr_alternative "length"
4774 (if_then_else (match_operand 2 "m16_uimm3_b")
4778 (define_insn "*lshrdi3_mips16"
4779 [(set (match_operand:DI 0 "register_operand" "=d,d")
4780 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4781 (match_operand:SI 2 "arith_operand" "d,I")))]
4782 "TARGET_64BIT && TARGET_MIPS16"
4784 if (GET_CODE (operands[2]) == CONST_INT)
4785 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4787 return "dsrl\t%0,%2";
4789 [(set_attr "type" "shift")
4790 (set_attr "mode" "DI")
4791 (set_attr_alternative "length"
4793 (if_then_else (match_operand 2 "m16_uimm3_b")
4797 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4800 [(set (match_operand:GPR 0 "register_operand")
4801 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4802 (match_operand:GPR 2 "const_int_operand")))]
4803 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4804 && GET_CODE (operands[2]) == CONST_INT
4805 && INTVAL (operands[2]) > 8
4806 && INTVAL (operands[2]) <= 16"
4807 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4808 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4809 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4811 ;; If we load a byte on the mips16 as a bitfield, the resulting
4812 ;; sequence of instructions is too complicated for combine, because it
4813 ;; involves four instructions: a load, a shift, a constant load into a
4814 ;; register, and an and (the key problem here is that the mips16 does
4815 ;; not have and immediate). We recognize a shift of a load in order
4816 ;; to make it simple enough for combine to understand.
4818 ;; The length here is the worst case: the length of the split version
4819 ;; will be more accurate.
4820 (define_insn_and_split ""
4821 [(set (match_operand:SI 0 "register_operand" "=d")
4822 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4823 (match_operand:SI 2 "immediate_operand" "I")))]
4827 [(set (match_dup 0) (match_dup 1))
4828 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4830 [(set_attr "type" "load")
4831 (set_attr "mode" "SI")
4832 (set_attr "length" "16")])
4834 (define_insn "rotr<mode>3"
4835 [(set (match_operand:GPR 0 "register_operand" "=d")
4836 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4837 (match_operand:SI 2 "arith_operand" "dI")))]
4840 if (GET_CODE (operands[2]) == CONST_INT)
4841 gcc_assert (INTVAL (operands[2]) >= 0
4842 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4844 return "<d>ror\t%0,%1,%2";
4846 [(set_attr "type" "shift")
4847 (set_attr "mode" "<MODE>")])
4850 ;; ....................
4854 ;; ....................
4856 ;; Flow here is rather complex:
4858 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4859 ;; into cmp_operands[] but generates no RTL.
4861 ;; 2) The appropriate branch define_expand is called, which then
4862 ;; creates the appropriate RTL for the comparison and branch.
4863 ;; Different CC modes are used, based on what type of branch is
4864 ;; done, so that we can constrain things appropriately. There
4865 ;; are assumptions in the rest of GCC that break if we fold the
4866 ;; operands into the branches for integer operations, and use cc0
4867 ;; for floating point, so we use the fp status register instead.
4868 ;; If needed, an appropriate temporary is created to hold the
4869 ;; of the integer compare.
4871 (define_expand "cmp<mode>"
4873 (compare:CC (match_operand:GPR 0 "register_operand")
4874 (match_operand:GPR 1 "nonmemory_operand")))]
4877 cmp_operands[0] = operands[0];
4878 cmp_operands[1] = operands[1];
4882 (define_expand "cmp<mode>"
4884 (compare:CC (match_operand:SCALARF 0 "register_operand")
4885 (match_operand:SCALARF 1 "register_operand")))]
4888 cmp_operands[0] = operands[0];
4889 cmp_operands[1] = operands[1];
4894 ;; ....................
4896 ;; CONDITIONAL BRANCHES
4898 ;; ....................
4900 ;; Conditional branches on floating-point equality tests.
4902 (define_insn "*branch_fp"
4905 (match_operator 0 "equality_operator"
4906 [(match_operand:CC 2 "register_operand" "z")
4908 (label_ref (match_operand 1 "" ""))
4912 return mips_output_conditional_branch (insn, operands,
4913 MIPS_BRANCH ("b%F0", "%Z2%1"),
4914 MIPS_BRANCH ("b%W0", "%Z2%1"));
4916 [(set_attr "type" "branch")
4917 (set_attr "mode" "none")])
4919 (define_insn "*branch_fp_inverted"
4922 (match_operator 0 "equality_operator"
4923 [(match_operand:CC 2 "register_operand" "z")
4926 (label_ref (match_operand 1 "" ""))))]
4929 return mips_output_conditional_branch (insn, operands,
4930 MIPS_BRANCH ("b%W0", "%Z2%1"),
4931 MIPS_BRANCH ("b%F0", "%Z2%1"));
4933 [(set_attr "type" "branch")
4934 (set_attr "mode" "none")])
4936 ;; Conditional branches on ordered comparisons with zero.
4938 (define_insn "*branch_order<mode>"
4941 (match_operator 0 "order_operator"
4942 [(match_operand:GPR 2 "register_operand" "d")
4944 (label_ref (match_operand 1 "" ""))
4947 { return mips_output_order_conditional_branch (insn, operands, false); }
4948 [(set_attr "type" "branch")
4949 (set_attr "mode" "none")])
4951 (define_insn "*branch_order<mode>_inverted"
4954 (match_operator 0 "order_operator"
4955 [(match_operand:GPR 2 "register_operand" "d")
4958 (label_ref (match_operand 1 "" ""))))]
4960 { return mips_output_order_conditional_branch (insn, operands, true); }
4961 [(set_attr "type" "branch")
4962 (set_attr "mode" "none")])
4964 ;; Conditional branch on equality comparison.
4966 (define_insn "*branch_equality<mode>"
4969 (match_operator 0 "equality_operator"
4970 [(match_operand:GPR 2 "register_operand" "d")
4971 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4972 (label_ref (match_operand 1 "" ""))
4976 return mips_output_conditional_branch (insn, operands,
4977 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4978 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4980 [(set_attr "type" "branch")
4981 (set_attr "mode" "none")])
4983 (define_insn "*branch_equality<mode>_inverted"
4986 (match_operator 0 "equality_operator"
4987 [(match_operand:GPR 2 "register_operand" "d")
4988 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4990 (label_ref (match_operand 1 "" ""))))]
4993 return mips_output_conditional_branch (insn, operands,
4994 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4995 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4997 [(set_attr "type" "branch")
4998 (set_attr "mode" "none")])
5002 (define_insn "*branch_equality<mode>_mips16"
5005 (match_operator 0 "equality_operator"
5006 [(match_operand:GPR 1 "register_operand" "d,t")
5008 (match_operand 2 "pc_or_label_operand" "")
5009 (match_operand 3 "pc_or_label_operand" "")))]
5012 if (operands[2] != pc_rtx)
5014 if (which_alternative == 0)
5015 return "b%C0z\t%1,%2";
5017 return "bt%C0z\t%2";
5021 if (which_alternative == 0)
5022 return "b%N0z\t%1,%3";
5024 return "bt%N0z\t%3";
5027 [(set_attr "type" "branch")
5028 (set_attr "mode" "none")
5029 (set_attr "length" "8")])
5031 (define_expand "b<code>"
5033 (if_then_else (any_cond:CC (cc0)
5035 (label_ref (match_operand 0 ""))
5039 mips_expand_conditional_branch (operands, <CODE>);
5043 ;; Used to implement built-in functions.
5044 (define_expand "condjump"
5046 (if_then_else (match_operand 0)
5047 (label_ref (match_operand 1))
5051 ;; ....................
5053 ;; SETTING A REGISTER FROM A COMPARISON
5055 ;; ....................
5057 (define_expand "seq"
5058 [(set (match_operand:SI 0 "register_operand")
5059 (eq:SI (match_dup 1)
5062 { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
5064 (define_insn "*seq_<mode>"
5065 [(set (match_operand:GPR 0 "register_operand" "=d")
5066 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
5070 [(set_attr "type" "slt")
5071 (set_attr "mode" "<MODE>")])
5073 (define_insn "*seq_<mode>_mips16"
5074 [(set (match_operand:GPR 0 "register_operand" "=t")
5075 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
5079 [(set_attr "type" "slt")
5080 (set_attr "mode" "<MODE>")])
5082 ;; "sne" uses sltu instructions in which the first operand is $0.
5083 ;; This isn't possible in mips16 code.
5085 (define_expand "sne"
5086 [(set (match_operand:SI 0 "register_operand")
5087 (ne:SI (match_dup 1)
5090 { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
5092 (define_insn "*sne_<mode>"
5093 [(set (match_operand:GPR 0 "register_operand" "=d")
5094 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
5098 [(set_attr "type" "slt")
5099 (set_attr "mode" "<MODE>")])
5101 (define_expand "sgt"
5102 [(set (match_operand:SI 0 "register_operand")
5103 (gt:SI (match_dup 1)
5106 { if (mips_expand_scc (GT, operands[0])) DONE; else FAIL; })
5108 (define_insn "*sgt_<mode>"
5109 [(set (match_operand:GPR 0 "register_operand" "=d")
5110 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5111 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5114 [(set_attr "type" "slt")
5115 (set_attr "mode" "<MODE>")])
5117 (define_insn "*sgt_<mode>_mips16"
5118 [(set (match_operand:GPR 0 "register_operand" "=t")
5119 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5120 (match_operand:GPR 2 "register_operand" "d")))]
5123 [(set_attr "type" "slt")
5124 (set_attr "mode" "<MODE>")])
5126 (define_expand "sge"
5127 [(set (match_operand:SI 0 "register_operand")
5128 (ge:SI (match_dup 1)
5131 { if (mips_expand_scc (GE, operands[0])) DONE; else FAIL; })
5133 (define_insn "*sge_<mode>"
5134 [(set (match_operand:GPR 0 "register_operand" "=d")
5135 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
5139 [(set_attr "type" "slt")
5140 (set_attr "mode" "<MODE>")])
5142 (define_expand "slt"
5143 [(set (match_operand:SI 0 "register_operand")
5144 (lt:SI (match_dup 1)
5147 { if (mips_expand_scc (LT, operands[0])) DONE; else FAIL; })
5149 (define_insn "*slt_<mode>"
5150 [(set (match_operand:GPR 0 "register_operand" "=d")
5151 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
5152 (match_operand:GPR 2 "arith_operand" "dI")))]
5155 [(set_attr "type" "slt")
5156 (set_attr "mode" "<MODE>")])
5158 (define_insn "*slt_<mode>_mips16"
5159 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5160 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
5161 (match_operand:GPR 2 "arith_operand" "d,I")))]
5164 [(set_attr "type" "slt")
5165 (set_attr "mode" "<MODE>")
5166 (set_attr_alternative "length"
5168 (if_then_else (match_operand 2 "m16_uimm8_1")
5172 (define_expand "sle"
5173 [(set (match_operand:SI 0 "register_operand")
5174 (le:SI (match_dup 1)
5177 { if (mips_expand_scc (LE, operands[0])) DONE; else FAIL; })
5179 (define_insn "*sle_<mode>"
5180 [(set (match_operand:GPR 0 "register_operand" "=d")
5181 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5182 (match_operand:GPR 2 "sle_operand" "")))]
5185 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5186 return "slt\t%0,%1,%2";
5188 [(set_attr "type" "slt")
5189 (set_attr "mode" "<MODE>")])
5191 (define_insn "*sle_<mode>_mips16"
5192 [(set (match_operand:GPR 0 "register_operand" "=t")
5193 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5194 (match_operand:GPR 2 "sle_operand" "")))]
5197 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5198 return "slt\t%1,%2";
5200 [(set_attr "type" "slt")
5201 (set_attr "mode" "<MODE>")
5202 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5206 (define_expand "sgtu"
5207 [(set (match_operand:SI 0 "register_operand")
5208 (gtu:SI (match_dup 1)
5211 { if (mips_expand_scc (GTU, operands[0])) DONE; else FAIL; })
5213 (define_insn "*sgtu_<mode>"
5214 [(set (match_operand:GPR 0 "register_operand" "=d")
5215 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5216 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5219 [(set_attr "type" "slt")
5220 (set_attr "mode" "<MODE>")])
5222 (define_insn "*sgtu_<mode>_mips16"
5223 [(set (match_operand:GPR 0 "register_operand" "=t")
5224 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5225 (match_operand:GPR 2 "register_operand" "d")))]
5228 [(set_attr "type" "slt")
5229 (set_attr "mode" "<MODE>")])
5231 (define_expand "sgeu"
5232 [(set (match_operand:SI 0 "register_operand")
5233 (geu:SI (match_dup 1)
5236 { if (mips_expand_scc (GEU, operands[0])) DONE; else FAIL; })
5238 (define_insn "*sge_<mode>"
5239 [(set (match_operand:GPR 0 "register_operand" "=d")
5240 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
5244 [(set_attr "type" "slt")
5245 (set_attr "mode" "<MODE>")])
5247 (define_expand "sltu"
5248 [(set (match_operand:SI 0 "register_operand")
5249 (ltu:SI (match_dup 1)
5252 { if (mips_expand_scc (LTU, operands[0])) DONE; else FAIL; })
5254 (define_insn "*sltu_<mode>"
5255 [(set (match_operand:GPR 0 "register_operand" "=d")
5256 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
5257 (match_operand:GPR 2 "arith_operand" "dI")))]
5260 [(set_attr "type" "slt")
5261 (set_attr "mode" "<MODE>")])
5263 (define_insn "*sltu_<mode>_mips16"
5264 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5265 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
5266 (match_operand:GPR 2 "arith_operand" "d,I")))]
5269 [(set_attr "type" "slt")
5270 (set_attr "mode" "<MODE>")
5271 (set_attr_alternative "length"
5273 (if_then_else (match_operand 2 "m16_uimm8_1")
5277 (define_expand "sleu"
5278 [(set (match_operand:SI 0 "register_operand")
5279 (leu:SI (match_dup 1)
5282 { if (mips_expand_scc (LEU, operands[0])) DONE; else FAIL; })
5284 (define_insn "*sleu_<mode>"
5285 [(set (match_operand:GPR 0 "register_operand" "=d")
5286 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5287 (match_operand:GPR 2 "sleu_operand" "")))]
5290 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5291 return "sltu\t%0,%1,%2";
5293 [(set_attr "type" "slt")
5294 (set_attr "mode" "<MODE>")])
5296 (define_insn "*sleu_<mode>_mips16"
5297 [(set (match_operand:GPR 0 "register_operand" "=t")
5298 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5299 (match_operand:GPR 2 "sleu_operand" "")))]
5302 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5303 return "sltu\t%1,%2";
5305 [(set_attr "type" "slt")
5306 (set_attr "mode" "<MODE>")
5307 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5312 ;; ....................
5314 ;; FLOATING POINT COMPARISONS
5316 ;; ....................
5318 (define_insn "s<code>_<mode>"
5319 [(set (match_operand:CC 0 "register_operand" "=z")
5320 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5321 (match_operand:SCALARF 2 "register_operand" "f")))]
5323 "c.<fcond>.<fmt>\t%Z0%1,%2"
5324 [(set_attr "type" "fcmp")
5325 (set_attr "mode" "FPSW")])
5327 (define_insn "s<code>_<mode>"
5328 [(set (match_operand:CC 0 "register_operand" "=z")
5329 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5330 (match_operand:SCALARF 2 "register_operand" "f")))]
5332 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5333 [(set_attr "type" "fcmp")
5334 (set_attr "mode" "FPSW")])
5337 ;; ....................
5339 ;; UNCONDITIONAL BRANCHES
5341 ;; ....................
5343 ;; Unconditional branches.
5347 (label_ref (match_operand 0 "" "")))]
5352 if (get_attr_length (insn) <= 8)
5353 return "%*b\t%l0%/";
5356 output_asm_insn (mips_output_load_label (), operands);
5357 return "%*jr\t%@%/%]";
5361 return "%*j\t%l0%/";
5363 [(set_attr "type" "jump")
5364 (set_attr "mode" "none")
5365 (set (attr "length")
5366 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5367 ;; in range, otherwise load the address of the branch target into
5368 ;; $at and then jump to it.
5370 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5371 (lt (abs (minus (match_dup 0)
5372 (plus (pc) (const_int 4))))
5373 (const_int 131072)))
5374 (const_int 4) (const_int 16)))])
5376 ;; We need a different insn for the mips16, because a mips16 branch
5377 ;; does not have a delay slot.
5381 (label_ref (match_operand 0 "" "")))]
5384 [(set_attr "type" "branch")
5385 (set_attr "mode" "none")
5386 (set_attr "length" "8")])
5388 (define_expand "indirect_jump"
5389 [(set (pc) (match_operand 0 "register_operand"))]
5392 operands[0] = force_reg (Pmode, operands[0]);
5393 if (Pmode == SImode)
5394 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5396 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5400 (define_insn "indirect_jump<mode>"
5401 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5404 [(set_attr "type" "jump")
5405 (set_attr "mode" "none")])
5407 (define_expand "tablejump"
5409 (match_operand 0 "register_operand"))
5410 (use (label_ref (match_operand 1 "")))]
5413 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5414 operands[0] = expand_binop (Pmode, add_optab,
5415 convert_to_mode (Pmode, operands[0], false),
5416 gen_rtx_LABEL_REF (Pmode, operands[1]),
5418 else if (TARGET_GPWORD)
5419 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5420 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5421 else if (TARGET_RTP_PIC)
5423 /* When generating RTP PIC, we use case table entries that are relative
5424 to the start of the function. Add the function's address to the
5426 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5427 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5428 start, 0, 0, OPTAB_WIDEN);
5431 if (Pmode == SImode)
5432 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5434 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5438 (define_insn "tablejump<mode>"
5440 (match_operand:P 0 "register_operand" "d"))
5441 (use (label_ref (match_operand 1 "" "")))]
5444 [(set_attr "type" "jump")
5445 (set_attr "mode" "none")])
5447 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5448 ;; While it is possible to either pull it off the stack (in the
5449 ;; o32 case) or recalculate it given t9 and our target label,
5450 ;; it takes 3 or 4 insns to do so.
5452 (define_expand "builtin_setjmp_setup"
5453 [(use (match_operand 0 "register_operand"))]
5458 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5459 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5463 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5464 ;; that older code did recalculate the gp from $25. Continue to jump through
5465 ;; $25 for compatibility (we lose nothing by doing so).
5467 (define_expand "builtin_longjmp"
5468 [(use (match_operand 0 "register_operand"))]
5471 /* The elements of the buffer are, in order: */
5472 int W = GET_MODE_SIZE (Pmode);
5473 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5474 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5475 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5476 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5477 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5478 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5479 The target is bound to be using $28 as the global pointer
5480 but the current function might not be. */
5481 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5483 /* This bit is similar to expand_builtin_longjmp except that it
5484 restores $gp as well. */
5485 mips_emit_move (hard_frame_pointer_rtx, fp);
5486 mips_emit_move (pv, lab);
5487 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5488 mips_emit_move (gp, gpv);
5489 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5490 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5491 emit_insn (gen_rtx_USE (VOIDmode, gp));
5492 emit_indirect_jump (pv);
5497 ;; ....................
5499 ;; Function prologue/epilogue
5501 ;; ....................
5504 (define_expand "prologue"
5508 mips_expand_prologue ();
5512 ;; Block any insns from being moved before this point, since the
5513 ;; profiling call to mcount can use various registers that aren't
5514 ;; saved or used to pass arguments.
5516 (define_insn "blockage"
5517 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5520 [(set_attr "type" "unknown")
5521 (set_attr "mode" "none")
5522 (set_attr "length" "0")])
5524 (define_expand "epilogue"
5528 mips_expand_epilogue (false);
5532 (define_expand "sibcall_epilogue"
5536 mips_expand_epilogue (true);
5540 ;; Trivial return. Make it look like a normal return insn as that
5541 ;; allows jump optimizations to work better.
5543 (define_insn "return"
5545 "mips_can_use_return_insn ()"
5547 [(set_attr "type" "jump")
5548 (set_attr "mode" "none")])
5552 (define_insn "return_internal"
5554 (use (match_operand 0 "pmode_register_operand" ""))]
5557 [(set_attr "type" "jump")
5558 (set_attr "mode" "none")])
5560 ;; This is used in compiling the unwind routines.
5561 (define_expand "eh_return"
5562 [(use (match_operand 0 "general_operand"))]
5565 if (GET_MODE (operands[0]) != word_mode)
5566 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5568 emit_insn (gen_eh_set_lr_di (operands[0]));
5570 emit_insn (gen_eh_set_lr_si (operands[0]));
5574 ;; Clobber the return address on the stack. We can't expand this
5575 ;; until we know where it will be put in the stack frame.
5577 (define_insn "eh_set_lr_si"
5578 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5579 (clobber (match_scratch:SI 1 "=&d"))]
5583 (define_insn "eh_set_lr_di"
5584 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5585 (clobber (match_scratch:DI 1 "=&d"))]
5590 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5591 (clobber (match_scratch 1))]
5592 "reload_completed && !TARGET_DEBUG_D_MODE"
5595 mips_set_return_address (operands[0], operands[1]);
5599 (define_expand "exception_receiver"
5603 /* See the comment above load_call<mode> for details. */
5604 emit_insn (gen_set_got_version ());
5606 /* If we have a call-clobbered $gp, restore it from its save slot. */
5607 if (HAVE_restore_gp)
5608 emit_insn (gen_restore_gp ());
5612 (define_expand "nonlocal_goto_receiver"
5616 /* See the comment above load_call<mode> for details. */
5617 emit_insn (gen_set_got_version ());
5621 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5622 ;; volatile until all uses of $28 are exposed.
5623 (define_insn_and_split "restore_gp"
5625 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))]
5626 "TARGET_CALL_CLOBBERED_GP"
5628 "&& reload_completed"
5634 [(set_attr "type" "load")
5635 (set_attr "length" "12")])
5638 ;; ....................
5642 ;; ....................
5644 ;; Instructions to load a call address from the GOT. The address might
5645 ;; point to a function or to a lazy binding stub. In the latter case,
5646 ;; the stub will use the dynamic linker to resolve the function, which
5647 ;; in turn will change the GOT entry to point to the function's real
5650 ;; This means that every call, even pure and constant ones, can
5651 ;; potentially modify the GOT entry. And once a stub has been called,
5652 ;; we must not call it again.
5654 ;; We represent this restriction using an imaginary, fixed, call-saved
5655 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5656 ;; live throughout the function and to change its value after every
5657 ;; potential call site. This stops any rtx value that uses the register
5658 ;; from being computed before an earlier call. To do this, we:
5660 ;; - Ensure that the register is live on entry to the function,
5661 ;; so that it is never thought to be used uninitalized.
5663 ;; - Ensure that the register is live on exit from the function,
5664 ;; so that it is live throughout.
5666 ;; - Make each call (lazily-bound or not) use the current value
5667 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5668 ;; not moved across call boundaries.
5670 ;; - Add "ghost" definitions of the register to the beginning of
5671 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5672 ;; edges may involve calls that normal paths don't. (E.g. the
5673 ;; unwinding code that handles a non-call exception may change
5674 ;; lazily-bound GOT entries.) We do this by making the
5675 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5676 ;; a set_got_version instruction.
5678 ;; - After each call (lazily-bound or not), use a "ghost"
5679 ;; update_got_version instruction to change the register's value.
5680 ;; This instruction mimics the _possible_ effect of the dynamic
5681 ;; resolver during the call and it remains live even if the call
5682 ;; itself becomes dead.
5684 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5685 ;; The register is therefore not a valid register_operand
5686 ;; and cannot be moved to or from other registers.
5687 (define_insn "load_call<mode>"
5688 [(set (match_operand:P 0 "register_operand" "=d")
5689 (unspec:P [(match_operand:P 1 "register_operand" "r")
5690 (match_operand:P 2 "immediate_operand" "")
5691 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5693 "<load>\t%0,%R2(%1)"
5694 [(set_attr "type" "load")
5695 (set_attr "mode" "<MODE>")
5696 (set_attr "length" "4")])
5698 (define_insn "set_got_version"
5699 [(set (reg:SI GOT_VERSION_REGNUM)
5700 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5703 [(set_attr "length" "0")
5704 (set_attr "type" "ghost")])
5706 (define_insn "update_got_version"
5707 [(set (reg:SI GOT_VERSION_REGNUM)
5708 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5711 [(set_attr "length" "0")
5712 (set_attr "type" "ghost")])
5714 ;; Sibling calls. All these patterns use jump instructions.
5716 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5717 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5718 ;; is defined in terms of call_insn_operand, the same is true of the
5721 ;; When we use an indirect jump, we need a register that will be
5722 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5723 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5724 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5727 (define_expand "sibcall"
5728 [(parallel [(call (match_operand 0 "")
5729 (match_operand 1 ""))
5730 (use (match_operand 2 "")) ;; next_arg_reg
5731 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5734 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5738 (define_insn "sibcall_internal"
5739 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5740 (match_operand 1 "" ""))]
5741 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5742 { return MIPS_CALL ("j", operands, 0); }
5743 [(set_attr "type" "call")])
5745 (define_expand "sibcall_value"
5746 [(parallel [(set (match_operand 0 "")
5747 (call (match_operand 1 "")
5748 (match_operand 2 "")))
5749 (use (match_operand 3 ""))])] ;; next_arg_reg
5752 mips_expand_call (operands[0], XEXP (operands[1], 0),
5753 operands[2], operands[3], true);
5757 (define_insn "sibcall_value_internal"
5758 [(set (match_operand 0 "register_operand" "")
5759 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5760 (match_operand 2 "" "")))]
5761 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5762 { return MIPS_CALL ("j", operands, 1); }
5763 [(set_attr "type" "call")])
5765 (define_insn "sibcall_value_multiple_internal"
5766 [(set (match_operand 0 "register_operand" "")
5767 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5768 (match_operand 2 "" "")))
5769 (set (match_operand 3 "register_operand" "")
5770 (call (mem:SI (match_dup 1))
5772 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5773 { return MIPS_CALL ("j", operands, 1); }
5774 [(set_attr "type" "call")])
5776 (define_expand "call"
5777 [(parallel [(call (match_operand 0 "")
5778 (match_operand 1 ""))
5779 (use (match_operand 2 "")) ;; next_arg_reg
5780 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5783 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5787 ;; This instruction directly corresponds to an assembly-language "jal".
5788 ;; There are four cases:
5791 ;; Both symbolic and register destinations are OK. The pattern
5792 ;; always expands to a single mips instruction.
5794 ;; - -mabicalls/-mno-explicit-relocs:
5795 ;; Again, both symbolic and register destinations are OK.
5796 ;; The call is treated as a multi-instruction black box.
5798 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5799 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5802 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5803 ;; Only "jal $25" is allowed. The call is actually two instructions:
5804 ;; "jalr $25" followed by an insn to reload $gp.
5806 ;; In the last case, we can generate the individual instructions with
5807 ;; a define_split. There are several things to be wary of:
5809 ;; - We can't expose the load of $gp before reload. If we did,
5810 ;; it might get removed as dead, but reload can introduce new
5811 ;; uses of $gp by rematerializing constants.
5813 ;; - We shouldn't restore $gp after calls that never return.
5814 ;; It isn't valid to insert instructions between a noreturn
5815 ;; call and the following barrier.
5817 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5818 ;; instruction preserves $gp and so have no effect on its liveness.
5819 ;; But once we generate the separate insns, it becomes obvious that
5820 ;; $gp is not live on entry to the call.
5822 ;; ??? The operands[2] = insn check is a hack to make the original insn
5823 ;; available to the splitter.
5824 (define_insn_and_split "call_internal"
5825 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5826 (match_operand 1 "" ""))
5827 (clobber (reg:SI 31))]
5829 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5830 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5833 emit_call_insn (gen_call_split (operands[0], operands[1]));
5834 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5838 [(set_attr "jal" "indirect,direct")
5839 (set_attr "extended_mips16" "no,yes")])
5841 ;; A pattern for calls that must be made directly. It is used for
5842 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5843 ;; stub; the linker relies on the call relocation type to detect when
5844 ;; such redirection is needed.
5845 (define_insn "call_internal_direct"
5846 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5849 (clobber (reg:SI 31))]
5851 { return MIPS_CALL ("jal", operands, 0); })
5853 (define_insn "call_split"
5854 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5855 (match_operand 1 "" ""))
5856 (clobber (reg:SI 31))
5857 (clobber (reg:SI 28))]
5858 "TARGET_SPLIT_CALLS"
5859 { return MIPS_CALL ("jal", operands, 0); }
5860 [(set_attr "type" "call")])
5862 (define_expand "call_value"
5863 [(parallel [(set (match_operand 0 "")
5864 (call (match_operand 1 "")
5865 (match_operand 2 "")))
5866 (use (match_operand 3 ""))])] ;; next_arg_reg
5869 mips_expand_call (operands[0], XEXP (operands[1], 0),
5870 operands[2], operands[3], false);
5874 ;; See comment for call_internal.
5875 (define_insn_and_split "call_value_internal"
5876 [(set (match_operand 0 "register_operand" "")
5877 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5878 (match_operand 2 "" "")))
5879 (clobber (reg:SI 31))]
5881 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5882 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5885 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5887 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5891 [(set_attr "jal" "indirect,direct")
5892 (set_attr "extended_mips16" "no,yes")])
5894 (define_insn "call_value_split"
5895 [(set (match_operand 0 "register_operand" "")
5896 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5897 (match_operand 2 "" "")))
5898 (clobber (reg:SI 31))
5899 (clobber (reg:SI 28))]
5900 "TARGET_SPLIT_CALLS"
5901 { return MIPS_CALL ("jal", operands, 1); }
5902 [(set_attr "type" "call")])
5904 ;; See call_internal_direct.
5905 (define_insn "call_value_internal_direct"
5906 [(set (match_operand 0 "register_operand")
5907 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
5910 (clobber (reg:SI 31))]
5912 { return MIPS_CALL ("jal", operands, 1); })
5914 ;; See comment for call_internal.
5915 (define_insn_and_split "call_value_multiple_internal"
5916 [(set (match_operand 0 "register_operand" "")
5917 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5918 (match_operand 2 "" "")))
5919 (set (match_operand 3 "register_operand" "")
5920 (call (mem:SI (match_dup 1))
5922 (clobber (reg:SI 31))]
5924 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5925 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5928 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5929 operands[2], operands[3]));
5930 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5934 [(set_attr "jal" "indirect,direct")
5935 (set_attr "extended_mips16" "no,yes")])
5937 (define_insn "call_value_multiple_split"
5938 [(set (match_operand 0 "register_operand" "")
5939 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5940 (match_operand 2 "" "")))
5941 (set (match_operand 3 "register_operand" "")
5942 (call (mem:SI (match_dup 1))
5944 (clobber (reg:SI 31))
5945 (clobber (reg:SI 28))]
5946 "TARGET_SPLIT_CALLS"
5947 { return MIPS_CALL ("jal", operands, 1); }
5948 [(set_attr "type" "call")])
5950 ;; Call subroutine returning any type.
5952 (define_expand "untyped_call"
5953 [(parallel [(call (match_operand 0 "")
5955 (match_operand 1 "")
5956 (match_operand 2 "")])]
5961 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5963 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5965 rtx set = XVECEXP (operands[2], 0, i);
5966 mips_emit_move (SET_DEST (set), SET_SRC (set));
5969 emit_insn (gen_blockage ());
5974 ;; ....................
5978 ;; ....................
5982 (define_insn "prefetch"
5983 [(prefetch (match_operand:QI 0 "address_operand" "p")
5984 (match_operand 1 "const_int_operand" "n")
5985 (match_operand 2 "const_int_operand" "n"))]
5986 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5988 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5989 return "pref\t%1,%a0";
5991 [(set_attr "type" "prefetch")])
5993 (define_insn "*prefetch_indexed_<mode>"
5994 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5995 (match_operand:P 1 "register_operand" "d"))
5996 (match_operand 2 "const_int_operand" "n")
5997 (match_operand 3 "const_int_operand" "n"))]
5998 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6000 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6001 return "prefx\t%2,%1(%0)";
6003 [(set_attr "type" "prefetchx")])
6009 [(set_attr "type" "nop")
6010 (set_attr "mode" "none")])
6012 ;; Like nop, but commented out when outside a .set noreorder block.
6013 (define_insn "hazard_nop"
6022 [(set_attr "type" "nop")])
6024 ;; MIPS4 Conditional move instructions.
6026 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6027 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6029 (match_operator:MOVECC 4 "equality_operator"
6030 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6032 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6033 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6038 [(set_attr "type" "condmove")
6039 (set_attr "mode" "<GPR:MODE>")])
6041 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6042 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6043 (if_then_else:SCALARF
6044 (match_operator:MOVECC 4 "equality_operator"
6045 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6047 (match_operand:SCALARF 2 "register_operand" "f,0")
6048 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6051 mov%T4.<fmt>\t%0,%2,%1
6052 mov%t4.<fmt>\t%0,%3,%1"
6053 [(set_attr "type" "condmove")
6054 (set_attr "mode" "<SCALARF:MODE>")])
6056 ;; These are the main define_expand's used to make conditional moves.
6058 (define_expand "mov<mode>cc"
6059 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6060 (set (match_operand:GPR 0 "register_operand")
6061 (if_then_else:GPR (match_dup 5)
6062 (match_operand:GPR 2 "reg_or_0_operand")
6063 (match_operand:GPR 3 "reg_or_0_operand")))]
6066 mips_expand_conditional_move (operands);
6070 (define_expand "mov<mode>cc"
6071 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6072 (set (match_operand:SCALARF 0 "register_operand")
6073 (if_then_else:SCALARF (match_dup 5)
6074 (match_operand:SCALARF 2 "register_operand")
6075 (match_operand:SCALARF 3 "register_operand")))]
6078 mips_expand_conditional_move (operands);
6083 ;; ....................
6085 ;; mips16 inline constant tables
6087 ;; ....................
6090 (define_insn "consttable_int"
6091 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6092 (match_operand 1 "const_int_operand" "")]
6093 UNSPEC_CONSTTABLE_INT)]
6096 assemble_integer (operands[0], INTVAL (operands[1]),
6097 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6100 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6102 (define_insn "consttable_float"
6103 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6104 UNSPEC_CONSTTABLE_FLOAT)]
6109 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6110 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6111 assemble_real (d, GET_MODE (operands[0]),
6112 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6115 [(set (attr "length")
6116 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6118 (define_insn "align"
6119 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6122 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6125 [(match_operand 0 "small_data_pattern")]
6128 { operands[0] = mips_rewrite_small_data (operands[0]); })
6131 ;; ....................
6133 ;; MIPS16e Save/Restore
6135 ;; ....................
6138 (define_insn "*mips16e_save_restore"
6139 [(match_parallel 0 ""
6140 [(set (match_operand:SI 1 "register_operand")
6141 (plus:SI (match_dup 1)
6142 (match_operand:SI 2 "const_int_operand")))])]
6143 "operands[1] == stack_pointer_rtx
6144 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6145 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6146 [(set_attr "type" "arith")
6147 (set_attr "extended_mips16" "yes")])
6149 ; Thread-Local Storage
6151 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
6152 ; MIPS architecture defines this register, and no current
6153 ; implementation provides it; instead, any OS which supports TLS is
6154 ; expected to trap and emulate this instruction. rdhwr is part of the
6155 ; MIPS 32r2 specification, but we use it on any architecture because
6156 ; we expect it to be emulated. Use .set to force the assembler to
6159 (define_insn "tls_get_tp_<mode>"
6160 [(set (match_operand:P 0 "register_operand" "=v")
6161 (unspec:P [(const_int 0)]
6162 UNSPEC_TLS_GET_TP))]
6163 "HAVE_AS_TLS && !TARGET_MIPS16"
6164 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
6165 [(set_attr "type" "unknown")
6166 ; Since rdhwr always generates a trap for now, putting it in a delay
6167 ; slot would make the kernel's emulation of it much slower.
6168 (set_attr "can_delay" "no")
6169 (set_attr "mode" "<MODE>")])
6171 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6173 (include "mips-ps-3d.md")
6175 ; The MIPS DSP Instructions.
6177 (include "mips-dsp.md")
6179 ; The MIPS DSP REV 2 Instructions.
6181 (include "mips-dspr2.md")
6183 ; MIPS fixed-point instructions.
6184 (include "mips-fixed.md")