1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 #include "diagnostic.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address. */
143 enum mips_address_type
{
150 /* Macros to create an enumeration identifier for a function prototype. */
151 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
152 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
153 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
154 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
156 /* Classifies the prototype of a built-in function. */
157 enum mips_function_type
{
158 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
159 #include "config/mips/mips-ftypes.def"
160 #undef DEF_MIPS_FTYPE
164 /* Specifies how a built-in function should be converted into rtl. */
165 enum mips_builtin_type
{
166 /* The function corresponds directly to an .md pattern. The return
167 value is mapped to operand 0 and the arguments are mapped to
168 operands 1 and above. */
171 /* The function corresponds directly to an .md pattern. There is no return
172 value and the arguments are mapped to operands 0 and above. */
173 MIPS_BUILTIN_DIRECT_NO_TARGET
,
175 /* The function corresponds to a comparison instruction followed by
176 a mips_cond_move_tf_ps pattern. The first two arguments are the
177 values to compare and the second two arguments are the vector
178 operands for the movt.ps or movf.ps instruction (in assembly order). */
182 /* The function corresponds to a V2SF comparison instruction. Operand 0
183 of this instruction is the result of the comparison, which has mode
184 CCV2 or CCV4. The function arguments are mapped to operands 1 and
185 above. The function's return value is an SImode boolean that is
186 true under the following conditions:
188 MIPS_BUILTIN_CMP_ANY: one of the registers is true
189 MIPS_BUILTIN_CMP_ALL: all of the registers are true
190 MIPS_BUILTIN_CMP_LOWER: the first register is true
191 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
192 MIPS_BUILTIN_CMP_ANY
,
193 MIPS_BUILTIN_CMP_ALL
,
194 MIPS_BUILTIN_CMP_UPPER
,
195 MIPS_BUILTIN_CMP_LOWER
,
197 /* As above, but the instruction only sets a single $fcc register. */
198 MIPS_BUILTIN_CMP_SINGLE
,
200 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
201 MIPS_BUILTIN_BPOSGE32
204 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
205 #define MIPS_FP_CONDITIONS(MACRO) \
223 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
224 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
225 enum mips_fp_condition
{
226 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
229 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
230 #define STRINGIFY(X) #X
231 static const char *const mips_fp_conditions
[] = {
232 MIPS_FP_CONDITIONS (STRINGIFY
)
235 /* Information about a function's frame layout. */
236 struct mips_frame_info
GTY(()) {
237 /* The size of the frame in bytes. */
238 HOST_WIDE_INT total_size
;
240 /* The number of bytes allocated to variables. */
241 HOST_WIDE_INT var_size
;
243 /* The number of bytes allocated to outgoing function arguments. */
244 HOST_WIDE_INT args_size
;
246 /* The number of bytes allocated to the .cprestore slot, or 0 if there
248 HOST_WIDE_INT cprestore_size
;
250 /* Bit X is set if the function saves or restores GPR X. */
253 /* Likewise FPR X. */
256 /* The number of GPRs and FPRs saved. */
260 /* The offset of the topmost GPR and FPR save slots from the top of
261 the frame, or zero if no such slots are needed. */
262 HOST_WIDE_INT gp_save_offset
;
263 HOST_WIDE_INT fp_save_offset
;
265 /* Likewise, but giving offsets from the bottom of the frame. */
266 HOST_WIDE_INT gp_sp_offset
;
267 HOST_WIDE_INT fp_sp_offset
;
269 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
270 HOST_WIDE_INT arg_pointer_offset
;
272 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
273 HOST_WIDE_INT hard_frame_pointer_offset
;
276 struct machine_function
GTY(()) {
277 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
278 rtx mips16_gp_pseudo_rtx
;
280 /* The number of extra stack bytes taken up by register varargs.
281 This area is allocated by the callee at the very top of the frame. */
284 /* The current frame information, calculated by mips_compute_frame_info. */
285 struct mips_frame_info frame
;
287 /* The register to use as the function's global pointer. */
288 unsigned int global_pointer
;
290 /* True if mips_adjust_insn_length should ignore an instruction's
292 bool ignore_hazard_length_p
;
294 /* True if the whole function is suitable for .set noreorder and
296 bool all_noreorder_p
;
298 /* True if the function is known to have an instruction that needs $gp. */
301 /* True if we have emitted an instruction to initialize
302 mips16_gp_pseudo_rtx. */
303 bool initialized_mips16_gp_pseudo_p
;
306 /* Information about a single argument. */
307 struct mips_arg_info
{
308 /* True if the argument is passed in a floating-point register, or
309 would have been if we hadn't run out of registers. */
312 /* The number of words passed in registers, rounded up. */
313 unsigned int reg_words
;
315 /* For EABI, the offset of the first register from GP_ARG_FIRST or
316 FP_ARG_FIRST. For other ABIs, the offset of the first register from
317 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
318 comment for details).
320 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
322 unsigned int reg_offset
;
324 /* The number of words that must be passed on the stack, rounded up. */
325 unsigned int stack_words
;
327 /* The offset from the start of the stack overflow area of the argument's
328 first stack word. Only meaningful when STACK_WORDS is nonzero. */
329 unsigned int stack_offset
;
332 /* Information about an address described by mips_address_type.
338 REG is the base register and OFFSET is the constant offset.
341 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
342 is the type of symbol it references.
345 SYMBOL_TYPE is the type of symbol that the address references. */
346 struct mips_address_info
{
347 enum mips_address_type type
;
350 enum mips_symbol_type symbol_type
;
353 /* One stage in a constant building sequence. These sequences have
357 A = A CODE[1] VALUE[1]
358 A = A CODE[2] VALUE[2]
361 where A is an accumulator, each CODE[i] is a binary rtl operation
362 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
363 struct mips_integer_op
{
365 unsigned HOST_WIDE_INT value
;
368 /* The largest number of operations needed to load an integer constant.
369 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
370 When the lowest bit is clear, we can try, but reject a sequence with
371 an extra SLL at the end. */
372 #define MIPS_MAX_INTEGER_OPS 7
374 /* Information about a MIPS16e SAVE or RESTORE instruction. */
375 struct mips16e_save_restore_info
{
376 /* The number of argument registers saved by a SAVE instruction.
377 0 for RESTORE instructions. */
380 /* Bit X is set if the instruction saves or restores GPR X. */
383 /* The total number of bytes to allocate. */
387 /* Global variables for machine-dependent things. */
389 /* The -G setting, or the configuration's default small-data limit if
390 no -G option is given. */
391 static unsigned int mips_small_data_threshold
;
393 /* The number of file directives written by mips_output_filename. */
394 int num_source_filenames
;
396 /* The name that appeared in the last .file directive written by
397 mips_output_filename, or "" if mips_output_filename hasn't
398 written anything yet. */
399 const char *current_function_file
= "";
401 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
404 /* Arrays that map GCC register numbers to debugger register numbers. */
405 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
406 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
408 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
413 /* True if we're writing out a branch-likely instruction rather than a
415 static bool mips_branch_likely
;
417 /* The operands passed to the last cmpMM expander. */
420 /* The current instruction-set architecture. */
421 enum processor_type mips_arch
;
422 const struct mips_cpu_info
*mips_arch_info
;
424 /* The processor that we should tune the code for. */
425 enum processor_type mips_tune
;
426 const struct mips_cpu_info
*mips_tune_info
;
428 /* The ISA level associated with mips_arch. */
431 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
432 static const struct mips_cpu_info
*mips_isa_option_info
;
434 /* Which ABI to use. */
435 int mips_abi
= MIPS_ABI_DEFAULT
;
437 /* Which cost information to use. */
438 const struct mips_rtx_cost_data
*mips_cost
;
440 /* The ambient target flags, excluding MASK_MIPS16. */
441 static int mips_base_target_flags
;
443 /* True if MIPS16 is the default mode. */
444 static bool mips_base_mips16
;
446 /* The ambient values of other global variables. */
447 static int mips_base_delayed_branch
; /* flag_delayed_branch */
448 static int mips_base_schedule_insns
; /* flag_schedule_insns */
449 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
450 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
451 static int mips_base_align_loops
; /* align_loops */
452 static int mips_base_align_jumps
; /* align_jumps */
453 static int mips_base_align_functions
; /* align_functions */
455 /* The -mcode-readable setting. */
456 enum mips_code_readable_setting mips_code_readable
= CODE_READABLE_YES
;
458 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
459 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
461 /* Index C is true if character C is a valid PRINT_OPERAND punctation
463 bool mips_print_operand_punct
[256];
465 static GTY (()) int mips_output_filename_first_time
= 1;
467 /* mips_split_p[X] is true if symbols of type X can be split by
468 mips_split_symbol. */
469 bool mips_split_p
[NUM_SYMBOL_TYPES
];
471 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
472 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
473 if they are matched by a special .md file pattern. */
474 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
476 /* Likewise for HIGHs. */
477 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
479 /* Index R is the smallest register class that contains register R. */
480 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
481 LEA_REGS
, LEA_REGS
, M16_NA_REGS
, V1_REG
,
482 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
483 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
484 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
485 M16_NA_REGS
, M16_NA_REGS
, LEA_REGS
, LEA_REGS
,
486 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
487 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
488 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
489 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
490 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
491 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
492 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
493 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
494 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
495 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
496 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
497 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
498 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
499 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
500 NO_REGS
, ALL_REGS
, ALL_REGS
, NO_REGS
,
501 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
502 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
503 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
504 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
505 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
506 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
507 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
508 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
509 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
510 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
511 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
512 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
513 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
514 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
515 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
516 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
517 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
518 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
519 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
520 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
521 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
522 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
523 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
524 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
525 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
526 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
527 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
530 /* The value of TARGET_ATTRIBUTE_TABLE. */
531 const struct attribute_spec mips_attribute_table
[] = {
532 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
533 { "long_call", 0, 0, false, true, true, NULL
},
534 { "far", 0, 0, false, true, true, NULL
},
535 { "near", 0, 0, false, true, true, NULL
},
536 /* We would really like to treat "mips16" and "nomips16" as type
537 attributes, but GCC doesn't provide the hooks we need to support
538 the right conversion rules. As declaration attributes, they affect
539 code generation but don't carry other semantics. */
540 { "mips16", 0, 0, true, false, false, NULL
},
541 { "nomips16", 0, 0, true, false, false, NULL
},
542 { NULL
, 0, 0, false, false, false, NULL
}
545 /* A table describing all the processors GCC knows about. Names are
546 matched in the order listed. The first mention of an ISA level is
547 taken as the canonical name for that ISA.
549 To ease comparison, please keep this table in the same order
550 as GAS's mips_cpu_info_table. Please also make sure that
551 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
552 options correctly. */
553 static const struct mips_cpu_info mips_cpu_info_table
[] = {
554 /* Entries for generic ISAs. */
555 { "mips1", PROCESSOR_R3000
, 1, 0 },
556 { "mips2", PROCESSOR_R6000
, 2, 0 },
557 { "mips3", PROCESSOR_R4000
, 3, 0 },
558 { "mips4", PROCESSOR_R8000
, 4, 0 },
559 /* Prefer not to use branch-likely instructions for generic MIPS32rX
560 and MIPS64rX code. The instructions were officially deprecated
561 in revisions 2 and earlier, but revision 3 is likely to downgrade
562 that to a recommendation to avoid the instructions in code that
563 isn't tuned to a specific processor. */
564 { "mips32", PROCESSOR_4KC
, 32, PTF_AVOID_BRANCHLIKELY
},
565 { "mips32r2", PROCESSOR_M4K
, 33, PTF_AVOID_BRANCHLIKELY
},
566 { "mips64", PROCESSOR_5KC
, 64, PTF_AVOID_BRANCHLIKELY
},
568 /* MIPS I processors. */
569 { "r3000", PROCESSOR_R3000
, 1, 0 },
570 { "r2000", PROCESSOR_R3000
, 1, 0 },
571 { "r3900", PROCESSOR_R3900
, 1, 0 },
573 /* MIPS II processors. */
574 { "r6000", PROCESSOR_R6000
, 2, 0 },
576 /* MIPS III processors. */
577 { "r4000", PROCESSOR_R4000
, 3, 0 },
578 { "vr4100", PROCESSOR_R4100
, 3, 0 },
579 { "vr4111", PROCESSOR_R4111
, 3, 0 },
580 { "vr4120", PROCESSOR_R4120
, 3, 0 },
581 { "vr4130", PROCESSOR_R4130
, 3, 0 },
582 { "vr4300", PROCESSOR_R4300
, 3, 0 },
583 { "r4400", PROCESSOR_R4000
, 3, 0 },
584 { "r4600", PROCESSOR_R4600
, 3, 0 },
585 { "orion", PROCESSOR_R4600
, 3, 0 },
586 { "r4650", PROCESSOR_R4650
, 3, 0 },
588 /* MIPS IV processors. */
589 { "r8000", PROCESSOR_R8000
, 4, 0 },
590 { "vr5000", PROCESSOR_R5000
, 4, 0 },
591 { "vr5400", PROCESSOR_R5400
, 4, 0 },
592 { "vr5500", PROCESSOR_R5500
, 4, PTF_AVOID_BRANCHLIKELY
},
593 { "rm7000", PROCESSOR_R7000
, 4, 0 },
594 { "rm9000", PROCESSOR_R9000
, 4, 0 },
596 /* MIPS32 processors. */
597 { "4kc", PROCESSOR_4KC
, 32, 0 },
598 { "4km", PROCESSOR_4KC
, 32, 0 },
599 { "4kp", PROCESSOR_4KP
, 32, 0 },
600 { "4ksc", PROCESSOR_4KC
, 32, 0 },
602 /* MIPS32 Release 2 processors. */
603 { "m4k", PROCESSOR_M4K
, 33, 0 },
604 { "4kec", PROCESSOR_4KC
, 33, 0 },
605 { "4kem", PROCESSOR_4KC
, 33, 0 },
606 { "4kep", PROCESSOR_4KP
, 33, 0 },
607 { "4ksd", PROCESSOR_4KC
, 33, 0 },
609 { "24kc", PROCESSOR_24KC
, 33, 0 },
610 { "24kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
611 { "24kf", PROCESSOR_24KF2_1
, 33, 0 },
612 { "24kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
613 { "24kfx", PROCESSOR_24KF1_1
, 33, 0 },
614 { "24kx", PROCESSOR_24KF1_1
, 33, 0 },
616 { "24kec", PROCESSOR_24KC
, 33, 0 }, /* 24K with DSP. */
617 { "24kef2_1", PROCESSOR_24KF2_1
, 33, 0 },
618 { "24kef", PROCESSOR_24KF2_1
, 33, 0 },
619 { "24kef1_1", PROCESSOR_24KF1_1
, 33, 0 },
620 { "24kefx", PROCESSOR_24KF1_1
, 33, 0 },
621 { "24kex", PROCESSOR_24KF1_1
, 33, 0 },
623 { "34kc", PROCESSOR_24KC
, 33, 0 }, /* 34K with MT/DSP. */
624 { "34kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
625 { "34kf", PROCESSOR_24KF2_1
, 33, 0 },
626 { "34kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
627 { "34kfx", PROCESSOR_24KF1_1
, 33, 0 },
628 { "34kx", PROCESSOR_24KF1_1
, 33, 0 },
630 { "74kc", PROCESSOR_74KC
, 33, 0 }, /* 74K with DSPr2. */
631 { "74kf2_1", PROCESSOR_74KF2_1
, 33, 0 },
632 { "74kf", PROCESSOR_74KF2_1
, 33, 0 },
633 { "74kf1_1", PROCESSOR_74KF1_1
, 33, 0 },
634 { "74kfx", PROCESSOR_74KF1_1
, 33, 0 },
635 { "74kx", PROCESSOR_74KF1_1
, 33, 0 },
636 { "74kf3_2", PROCESSOR_74KF3_2
, 33, 0 },
638 /* MIPS64 processors. */
639 { "5kc", PROCESSOR_5KC
, 64, 0 },
640 { "5kf", PROCESSOR_5KF
, 64, 0 },
641 { "20kc", PROCESSOR_20KC
, 64, PTF_AVOID_BRANCHLIKELY
},
642 { "sb1", PROCESSOR_SB1
, 64, PTF_AVOID_BRANCHLIKELY
},
643 { "sb1a", PROCESSOR_SB1A
, 64, PTF_AVOID_BRANCHLIKELY
},
644 { "sr71000", PROCESSOR_SR71000
, 64, PTF_AVOID_BRANCHLIKELY
},
647 /* Default costs. If these are used for a processor we should look
648 up the actual costs. */
649 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
650 COSTS_N_INSNS (7), /* fp_mult_sf */ \
651 COSTS_N_INSNS (8), /* fp_mult_df */ \
652 COSTS_N_INSNS (23), /* fp_div_sf */ \
653 COSTS_N_INSNS (36), /* fp_div_df */ \
654 COSTS_N_INSNS (10), /* int_mult_si */ \
655 COSTS_N_INSNS (10), /* int_mult_di */ \
656 COSTS_N_INSNS (69), /* int_div_si */ \
657 COSTS_N_INSNS (69), /* int_div_di */ \
658 2, /* branch_cost */ \
659 4 /* memory_latency */
661 /* Floating-point costs for processors without an FPU. Just assume that
662 all floating-point libcalls are very expensive. */
663 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
664 COSTS_N_INSNS (256), /* fp_mult_sf */ \
665 COSTS_N_INSNS (256), /* fp_mult_df */ \
666 COSTS_N_INSNS (256), /* fp_div_sf */ \
667 COSTS_N_INSNS (256) /* fp_div_df */
669 /* Costs to use when optimizing for size. */
670 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
671 COSTS_N_INSNS (1), /* fp_add */
672 COSTS_N_INSNS (1), /* fp_mult_sf */
673 COSTS_N_INSNS (1), /* fp_mult_df */
674 COSTS_N_INSNS (1), /* fp_div_sf */
675 COSTS_N_INSNS (1), /* fp_div_df */
676 COSTS_N_INSNS (1), /* int_mult_si */
677 COSTS_N_INSNS (1), /* int_mult_di */
678 COSTS_N_INSNS (1), /* int_div_si */
679 COSTS_N_INSNS (1), /* int_div_di */
681 4 /* memory_latency */
684 /* Costs to use when optimizing for speed, indexed by processor. */
685 static const struct mips_rtx_cost_data mips_rtx_cost_data
[PROCESSOR_MAX
] = {
687 COSTS_N_INSNS (2), /* fp_add */
688 COSTS_N_INSNS (4), /* fp_mult_sf */
689 COSTS_N_INSNS (5), /* fp_mult_df */
690 COSTS_N_INSNS (12), /* fp_div_sf */
691 COSTS_N_INSNS (19), /* fp_div_df */
692 COSTS_N_INSNS (12), /* int_mult_si */
693 COSTS_N_INSNS (12), /* int_mult_di */
694 COSTS_N_INSNS (35), /* int_div_si */
695 COSTS_N_INSNS (35), /* int_div_di */
697 4 /* memory_latency */
701 COSTS_N_INSNS (6), /* int_mult_si */
702 COSTS_N_INSNS (6), /* int_mult_di */
703 COSTS_N_INSNS (36), /* int_div_si */
704 COSTS_N_INSNS (36), /* int_div_di */
706 4 /* memory_latency */
710 COSTS_N_INSNS (36), /* int_mult_si */
711 COSTS_N_INSNS (36), /* int_mult_di */
712 COSTS_N_INSNS (37), /* int_div_si */
713 COSTS_N_INSNS (37), /* int_div_di */
715 4 /* memory_latency */
719 COSTS_N_INSNS (4), /* int_mult_si */
720 COSTS_N_INSNS (11), /* int_mult_di */
721 COSTS_N_INSNS (36), /* int_div_si */
722 COSTS_N_INSNS (68), /* int_div_di */
724 4 /* memory_latency */
727 COSTS_N_INSNS (4), /* fp_add */
728 COSTS_N_INSNS (4), /* fp_mult_sf */
729 COSTS_N_INSNS (5), /* fp_mult_df */
730 COSTS_N_INSNS (17), /* fp_div_sf */
731 COSTS_N_INSNS (32), /* fp_div_df */
732 COSTS_N_INSNS (4), /* int_mult_si */
733 COSTS_N_INSNS (11), /* int_mult_di */
734 COSTS_N_INSNS (36), /* int_div_si */
735 COSTS_N_INSNS (68), /* int_div_di */
737 4 /* memory_latency */
740 COSTS_N_INSNS (4), /* fp_add */
741 COSTS_N_INSNS (4), /* fp_mult_sf */
742 COSTS_N_INSNS (5), /* fp_mult_df */
743 COSTS_N_INSNS (17), /* fp_div_sf */
744 COSTS_N_INSNS (32), /* fp_div_df */
745 COSTS_N_INSNS (4), /* int_mult_si */
746 COSTS_N_INSNS (7), /* int_mult_di */
747 COSTS_N_INSNS (42), /* int_div_si */
748 COSTS_N_INSNS (72), /* int_div_di */
750 4 /* memory_latency */
754 COSTS_N_INSNS (5), /* int_mult_si */
755 COSTS_N_INSNS (5), /* int_mult_di */
756 COSTS_N_INSNS (41), /* int_div_si */
757 COSTS_N_INSNS (41), /* int_div_di */
759 4 /* memory_latency */
762 COSTS_N_INSNS (8), /* fp_add */
763 COSTS_N_INSNS (8), /* fp_mult_sf */
764 COSTS_N_INSNS (10), /* fp_mult_df */
765 COSTS_N_INSNS (34), /* fp_div_sf */
766 COSTS_N_INSNS (64), /* fp_div_df */
767 COSTS_N_INSNS (5), /* int_mult_si */
768 COSTS_N_INSNS (5), /* int_mult_di */
769 COSTS_N_INSNS (41), /* int_div_si */
770 COSTS_N_INSNS (41), /* int_div_di */
772 4 /* memory_latency */
775 COSTS_N_INSNS (4), /* fp_add */
776 COSTS_N_INSNS (4), /* fp_mult_sf */
777 COSTS_N_INSNS (5), /* fp_mult_df */
778 COSTS_N_INSNS (17), /* fp_div_sf */
779 COSTS_N_INSNS (32), /* fp_div_df */
780 COSTS_N_INSNS (5), /* int_mult_si */
781 COSTS_N_INSNS (5), /* int_mult_di */
782 COSTS_N_INSNS (41), /* int_div_si */
783 COSTS_N_INSNS (41), /* int_div_di */
785 4 /* memory_latency */
789 COSTS_N_INSNS (5), /* int_mult_si */
790 COSTS_N_INSNS (5), /* int_mult_di */
791 COSTS_N_INSNS (41), /* int_div_si */
792 COSTS_N_INSNS (41), /* int_div_di */
794 4 /* memory_latency */
797 COSTS_N_INSNS (8), /* fp_add */
798 COSTS_N_INSNS (8), /* fp_mult_sf */
799 COSTS_N_INSNS (10), /* fp_mult_df */
800 COSTS_N_INSNS (34), /* fp_div_sf */
801 COSTS_N_INSNS (64), /* fp_div_df */
802 COSTS_N_INSNS (5), /* int_mult_si */
803 COSTS_N_INSNS (5), /* int_mult_di */
804 COSTS_N_INSNS (41), /* int_div_si */
805 COSTS_N_INSNS (41), /* int_div_di */
807 4 /* memory_latency */
810 COSTS_N_INSNS (4), /* fp_add */
811 COSTS_N_INSNS (4), /* fp_mult_sf */
812 COSTS_N_INSNS (5), /* fp_mult_df */
813 COSTS_N_INSNS (17), /* fp_div_sf */
814 COSTS_N_INSNS (32), /* fp_div_df */
815 COSTS_N_INSNS (5), /* int_mult_si */
816 COSTS_N_INSNS (5), /* int_mult_di */
817 COSTS_N_INSNS (41), /* int_div_si */
818 COSTS_N_INSNS (41), /* int_div_di */
820 4 /* memory_latency */
823 COSTS_N_INSNS (6), /* fp_add */
824 COSTS_N_INSNS (6), /* fp_mult_sf */
825 COSTS_N_INSNS (7), /* fp_mult_df */
826 COSTS_N_INSNS (25), /* fp_div_sf */
827 COSTS_N_INSNS (48), /* fp_div_df */
828 COSTS_N_INSNS (5), /* int_mult_si */
829 COSTS_N_INSNS (5), /* int_mult_di */
830 COSTS_N_INSNS (41), /* int_div_si */
831 COSTS_N_INSNS (41), /* int_div_di */
833 4 /* memory_latency */
839 COSTS_N_INSNS (2), /* fp_add */
840 COSTS_N_INSNS (4), /* fp_mult_sf */
841 COSTS_N_INSNS (5), /* fp_mult_df */
842 COSTS_N_INSNS (12), /* fp_div_sf */
843 COSTS_N_INSNS (19), /* fp_div_df */
844 COSTS_N_INSNS (2), /* int_mult_si */
845 COSTS_N_INSNS (2), /* int_mult_di */
846 COSTS_N_INSNS (35), /* int_div_si */
847 COSTS_N_INSNS (35), /* int_div_di */
849 4 /* memory_latency */
852 COSTS_N_INSNS (3), /* fp_add */
853 COSTS_N_INSNS (5), /* fp_mult_sf */
854 COSTS_N_INSNS (6), /* fp_mult_df */
855 COSTS_N_INSNS (15), /* fp_div_sf */
856 COSTS_N_INSNS (16), /* fp_div_df */
857 COSTS_N_INSNS (17), /* int_mult_si */
858 COSTS_N_INSNS (17), /* int_mult_di */
859 COSTS_N_INSNS (38), /* int_div_si */
860 COSTS_N_INSNS (38), /* int_div_di */
862 6 /* memory_latency */
865 COSTS_N_INSNS (6), /* fp_add */
866 COSTS_N_INSNS (7), /* fp_mult_sf */
867 COSTS_N_INSNS (8), /* fp_mult_df */
868 COSTS_N_INSNS (23), /* fp_div_sf */
869 COSTS_N_INSNS (36), /* fp_div_df */
870 COSTS_N_INSNS (10), /* int_mult_si */
871 COSTS_N_INSNS (10), /* int_mult_di */
872 COSTS_N_INSNS (69), /* int_div_si */
873 COSTS_N_INSNS (69), /* int_div_di */
875 6 /* memory_latency */
887 /* The only costs that appear to be updated here are
888 integer multiplication. */
890 COSTS_N_INSNS (4), /* int_mult_si */
891 COSTS_N_INSNS (6), /* int_mult_di */
892 COSTS_N_INSNS (69), /* int_div_si */
893 COSTS_N_INSNS (69), /* int_div_di */
895 4 /* memory_latency */
907 COSTS_N_INSNS (6), /* fp_add */
908 COSTS_N_INSNS (4), /* fp_mult_sf */
909 COSTS_N_INSNS (5), /* fp_mult_df */
910 COSTS_N_INSNS (23), /* fp_div_sf */
911 COSTS_N_INSNS (36), /* fp_div_df */
912 COSTS_N_INSNS (5), /* int_mult_si */
913 COSTS_N_INSNS (5), /* int_mult_di */
914 COSTS_N_INSNS (36), /* int_div_si */
915 COSTS_N_INSNS (36), /* int_div_di */
917 4 /* memory_latency */
920 COSTS_N_INSNS (6), /* fp_add */
921 COSTS_N_INSNS (5), /* fp_mult_sf */
922 COSTS_N_INSNS (6), /* fp_mult_df */
923 COSTS_N_INSNS (30), /* fp_div_sf */
924 COSTS_N_INSNS (59), /* fp_div_df */
925 COSTS_N_INSNS (3), /* int_mult_si */
926 COSTS_N_INSNS (4), /* int_mult_di */
927 COSTS_N_INSNS (42), /* int_div_si */
928 COSTS_N_INSNS (74), /* int_div_di */
930 4 /* memory_latency */
933 COSTS_N_INSNS (6), /* fp_add */
934 COSTS_N_INSNS (5), /* fp_mult_sf */
935 COSTS_N_INSNS (6), /* fp_mult_df */
936 COSTS_N_INSNS (30), /* fp_div_sf */
937 COSTS_N_INSNS (59), /* fp_div_df */
938 COSTS_N_INSNS (5), /* int_mult_si */
939 COSTS_N_INSNS (9), /* int_mult_di */
940 COSTS_N_INSNS (42), /* int_div_si */
941 COSTS_N_INSNS (74), /* int_div_di */
943 4 /* memory_latency */
946 /* The only costs that are changed here are
947 integer multiplication. */
948 COSTS_N_INSNS (6), /* fp_add */
949 COSTS_N_INSNS (7), /* fp_mult_sf */
950 COSTS_N_INSNS (8), /* fp_mult_df */
951 COSTS_N_INSNS (23), /* fp_div_sf */
952 COSTS_N_INSNS (36), /* fp_div_df */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (9), /* int_mult_di */
955 COSTS_N_INSNS (69), /* int_div_si */
956 COSTS_N_INSNS (69), /* int_div_di */
958 4 /* memory_latency */
964 /* The only costs that are changed here are
965 integer multiplication. */
966 COSTS_N_INSNS (6), /* fp_add */
967 COSTS_N_INSNS (7), /* fp_mult_sf */
968 COSTS_N_INSNS (8), /* fp_mult_df */
969 COSTS_N_INSNS (23), /* fp_div_sf */
970 COSTS_N_INSNS (36), /* fp_div_df */
971 COSTS_N_INSNS (3), /* int_mult_si */
972 COSTS_N_INSNS (8), /* int_mult_di */
973 COSTS_N_INSNS (69), /* int_div_si */
974 COSTS_N_INSNS (69), /* int_div_di */
976 4 /* memory_latency */
979 /* These costs are the same as the SB-1A below. */
980 COSTS_N_INSNS (4), /* fp_add */
981 COSTS_N_INSNS (4), /* fp_mult_sf */
982 COSTS_N_INSNS (4), /* fp_mult_df */
983 COSTS_N_INSNS (24), /* fp_div_sf */
984 COSTS_N_INSNS (32), /* fp_div_df */
985 COSTS_N_INSNS (3), /* int_mult_si */
986 COSTS_N_INSNS (4), /* int_mult_di */
987 COSTS_N_INSNS (36), /* int_div_si */
988 COSTS_N_INSNS (68), /* int_div_di */
990 4 /* memory_latency */
993 /* These costs are the same as the SB-1 above. */
994 COSTS_N_INSNS (4), /* fp_add */
995 COSTS_N_INSNS (4), /* fp_mult_sf */
996 COSTS_N_INSNS (4), /* fp_mult_df */
997 COSTS_N_INSNS (24), /* fp_div_sf */
998 COSTS_N_INSNS (32), /* fp_div_df */
999 COSTS_N_INSNS (3), /* int_mult_si */
1000 COSTS_N_INSNS (4), /* int_mult_di */
1001 COSTS_N_INSNS (36), /* int_div_si */
1002 COSTS_N_INSNS (68), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1011 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1012 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1013 struct mflip_mips16_entry
GTY (()) {
1017 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1019 /* Hash table callbacks for mflip_mips16_htab. */
1022 mflip_mips16_htab_hash (const void *entry
)
1024 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1028 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1030 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1031 (const char *) name
) == 0;
1034 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1035 mode, false if it should next add an attribute for the opposite mode. */
1036 static GTY(()) bool mips16_flipper
;
1038 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1039 for -mflip-mips16. Return true if it should use "mips16" and false if
1040 it should use "nomips16". */
1043 mflip_mips16_use_mips16_p (tree decl
)
1045 struct mflip_mips16_entry
*entry
;
1050 /* Use the opposite of the command-line setting for anonymous decls. */
1051 if (!DECL_NAME (decl
))
1052 return !mips_base_mips16
;
1054 if (!mflip_mips16_htab
)
1055 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1056 mflip_mips16_htab_eq
, NULL
);
1058 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1059 hash
= htab_hash_string (name
);
1060 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1061 entry
= (struct mflip_mips16_entry
*) *slot
;
1064 mips16_flipper
= !mips16_flipper
;
1065 entry
= GGC_NEW (struct mflip_mips16_entry
);
1067 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1070 return entry
->mips16_p
;
1073 /* Predicates to test for presence of "near" and "far"/"long_call"
1074 attributes on the given TYPE. */
1077 mips_near_type_p (const_tree type
)
1079 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1083 mips_far_type_p (const_tree type
)
1085 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1086 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1089 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1092 mips_mips16_decl_p (const_tree decl
)
1094 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1098 mips_nomips16_decl_p (const_tree decl
)
1100 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1103 /* Return true if function DECL is a MIPS16 function. Return the ambient
1104 setting if DECL is null. */
1107 mips_use_mips16_mode_p (tree decl
)
1111 /* Nested functions must use the same frame pointer as their
1112 parent and must therefore use the same ISA mode. */
1113 tree parent
= decl_function_context (decl
);
1116 if (mips_mips16_decl_p (decl
))
1118 if (mips_nomips16_decl_p (decl
))
1121 return mips_base_mips16
;
1124 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1127 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1129 /* Disallow mixed near/far attributes. */
1130 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1132 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1137 /* Implement TARGET_INSERT_ATTRIBUTES. */
1140 mips_insert_attributes (tree decl
, tree
*attributes
)
1143 bool mips16_p
, nomips16_p
;
1145 /* Check for "mips16" and "nomips16" attributes. */
1146 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1147 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1148 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1151 error ("%qs attribute only applies to functions", "mips16");
1153 error ("%qs attribute only applies to functions", "nomips16");
1157 mips16_p
|= mips_mips16_decl_p (decl
);
1158 nomips16_p
|= mips_nomips16_decl_p (decl
);
1159 if (mips16_p
|| nomips16_p
)
1161 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1162 if (mips16_p
&& nomips16_p
)
1163 error ("%qs cannot have both %<mips16%> and "
1164 "%<nomips16%> attributes",
1165 IDENTIFIER_POINTER (DECL_NAME (decl
)));
1167 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1169 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1170 "mips16" attribute, arbitrarily pick one. We must pick the same
1171 setting for duplicate declarations of a function. */
1172 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1173 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1178 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1181 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1183 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1184 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1185 error ("%qs redeclared with conflicting %qs attributes",
1186 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "mips16");
1187 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1188 error ("%qs redeclared with conflicting %qs attributes",
1189 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "nomips16");
1191 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1192 DECL_ATTRIBUTES (newdecl
));
1195 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1196 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1199 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1201 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1203 *base_ptr
= XEXP (x
, 0);
1204 *offset_ptr
= INTVAL (XEXP (x
, 1));
1213 static unsigned int mips_build_integer (struct mips_integer_op
*,
1214 unsigned HOST_WIDE_INT
);
1216 /* A subroutine of mips_build_integer, with the same interface.
1217 Assume that the final action in the sequence should be a left shift. */
1220 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1222 unsigned int i
, shift
;
1224 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1225 since signed numbers are easier to load than unsigned ones. */
1227 while ((value
& 1) == 0)
1228 value
/= 2, shift
++;
1230 i
= mips_build_integer (codes
, value
);
1231 codes
[i
].code
= ASHIFT
;
1232 codes
[i
].value
= shift
;
1236 /* As for mips_build_shift, but assume that the final action will be
1237 an IOR or PLUS operation. */
1240 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1242 unsigned HOST_WIDE_INT high
;
1245 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1246 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1248 /* The constant is too complex to load with a simple LUI/ORI pair,
1249 so we want to give the recursive call as many trailing zeros as
1250 possible. In this case, we know bit 16 is set and that the
1251 low 16 bits form a negative number. If we subtract that number
1252 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1253 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1254 codes
[i
].code
= PLUS
;
1255 codes
[i
].value
= CONST_LOW_PART (value
);
1259 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1260 bits gives a value with at least 17 trailing zeros. */
1261 i
= mips_build_integer (codes
, high
);
1262 codes
[i
].code
= IOR
;
1263 codes
[i
].value
= value
& 0xffff;
1268 /* Fill CODES with a sequence of rtl operations to load VALUE.
1269 Return the number of operations needed. */
1272 mips_build_integer (struct mips_integer_op
*codes
,
1273 unsigned HOST_WIDE_INT value
)
1275 if (SMALL_OPERAND (value
)
1276 || SMALL_OPERAND_UNSIGNED (value
)
1277 || LUI_OPERAND (value
))
1279 /* The value can be loaded with a single instruction. */
1280 codes
[0].code
= UNKNOWN
;
1281 codes
[0].value
= value
;
1284 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1286 /* Either the constant is a simple LUI/ORI combination or its
1287 lowest bit is set. We don't want to shift in this case. */
1288 return mips_build_lower (codes
, value
);
1290 else if ((value
& 0xffff) == 0)
1292 /* The constant will need at least three actions. The lowest
1293 16 bits are clear, so the final action will be a shift. */
1294 return mips_build_shift (codes
, value
);
1298 /* The final action could be a shift, add or inclusive OR.
1299 Rather than use a complex condition to select the best
1300 approach, try both mips_build_shift and mips_build_lower
1301 and pick the one that gives the shortest sequence.
1302 Note that this case is only used once per constant. */
1303 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1304 unsigned int cost
, alt_cost
;
1306 cost
= mips_build_shift (codes
, value
);
1307 alt_cost
= mips_build_lower (alt_codes
, value
);
1308 if (alt_cost
< cost
)
1310 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1317 /* Return true if X is a thread-local symbol. */
1320 mips_tls_symbol_p (rtx x
)
1322 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1325 /* Return true if SYMBOL_REF X is associated with a global symbol
1326 (in the STB_GLOBAL sense). */
1329 mips_global_symbol_p (const_rtx x
)
1331 const_tree decl
= SYMBOL_REF_DECL (x
);
1334 return !SYMBOL_REF_LOCAL_P (x
);
1336 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1337 or weak symbols. Relocations in the object file will be against
1338 the target symbol, so it's that symbol's binding that matters here. */
1339 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1342 /* Return true if SYMBOL_REF X binds locally. */
1345 mips_symbol_binds_local_p (const_rtx x
)
1347 return (SYMBOL_REF_DECL (x
)
1348 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1349 : SYMBOL_REF_LOCAL_P (x
));
1352 /* Return true if rtx constants of mode MODE should be put into a small
1356 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1358 return (!TARGET_EMBEDDED_DATA
1359 && TARGET_LOCAL_SDATA
1360 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1363 /* Return true if X should not be moved directly into register $25.
1364 We need this because many versions of GAS will treat "la $25,foo" as
1365 part of a call sequence and so allow a global "foo" to be lazily bound. */
1368 mips_dangerous_for_la25_p (rtx x
)
1370 return (!TARGET_EXPLICIT_RELOCS
1372 && GET_CODE (x
) == SYMBOL_REF
1373 && mips_global_symbol_p (x
));
1376 /* Return the method that should be used to access SYMBOL_REF or
1377 LABEL_REF X in context CONTEXT. */
1379 static enum mips_symbol_type
1380 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1383 return SYMBOL_GOT_DISP
;
1385 if (GET_CODE (x
) == LABEL_REF
)
1387 /* LABEL_REFs are used for jump tables as well as text labels.
1388 Only return SYMBOL_PC_RELATIVE if we know the label is in
1389 the text section. */
1390 if (TARGET_MIPS16_SHORT_JUMP_TABLES
)
1391 return SYMBOL_PC_RELATIVE
;
1393 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1394 return SYMBOL_GOT_PAGE_OFST
;
1396 return SYMBOL_ABSOLUTE
;
1399 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1401 if (SYMBOL_REF_TLS_MODEL (x
))
1404 if (CONSTANT_POOL_ADDRESS_P (x
))
1406 if (TARGET_MIPS16_TEXT_LOADS
)
1407 return SYMBOL_PC_RELATIVE
;
1409 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1410 return SYMBOL_PC_RELATIVE
;
1412 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1413 return SYMBOL_GP_RELATIVE
;
1416 /* Do not use small-data accesses for weak symbols; they may end up
1418 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1419 return SYMBOL_GP_RELATIVE
;
1421 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1424 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1426 /* There are three cases to consider:
1428 - o32 PIC (either with or without explicit relocs)
1429 - n32/n64 PIC without explicit relocs
1430 - n32/n64 PIC with explicit relocs
1432 In the first case, both local and global accesses will use an
1433 R_MIPS_GOT16 relocation. We must correctly predict which of
1434 the two semantics (local or global) the assembler and linker
1435 will apply. The choice depends on the symbol's binding rather
1436 than its visibility.
1438 In the second case, the assembler will not use R_MIPS_GOT16
1439 relocations, but it chooses between local and global accesses
1440 in the same way as for o32 PIC.
1442 In the third case we have more freedom since both forms of
1443 access will work for any kind of symbol. However, there seems
1444 little point in doing things differently. */
1445 if (mips_global_symbol_p (x
))
1446 return SYMBOL_GOT_DISP
;
1448 return SYMBOL_GOT_PAGE_OFST
;
1451 if (TARGET_MIPS16_PCREL_LOADS
&& context
!= SYMBOL_CONTEXT_CALL
)
1452 return SYMBOL_FORCE_TO_MEM
;
1454 return SYMBOL_ABSOLUTE
;
1457 /* Classify the base of symbolic expression X, given that X appears in
1460 static enum mips_symbol_type
1461 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1465 split_const (x
, &x
, &offset
);
1466 if (UNSPEC_ADDRESS_P (x
))
1467 return UNSPEC_ADDRESS_TYPE (x
);
1469 return mips_classify_symbol (x
, context
);
1472 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1473 is the alignment in bytes of SYMBOL_REF X. */
1476 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1478 HOST_WIDE_INT align
;
1480 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1481 return IN_RANGE (offset
, 0, align
- 1);
1484 /* Return true if X is a symbolic constant that can be used in context
1485 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1488 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1489 enum mips_symbol_type
*symbol_type
)
1493 split_const (x
, &x
, &offset
);
1494 if (UNSPEC_ADDRESS_P (x
))
1496 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1497 x
= UNSPEC_ADDRESS (x
);
1499 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1501 *symbol_type
= mips_classify_symbol (x
, context
);
1502 if (*symbol_type
== SYMBOL_TLS
)
1508 if (offset
== const0_rtx
)
1511 /* Check whether a nonzero offset is valid for the underlying
1513 switch (*symbol_type
)
1515 case SYMBOL_ABSOLUTE
:
1516 case SYMBOL_FORCE_TO_MEM
:
1517 case SYMBOL_32_HIGH
:
1518 case SYMBOL_64_HIGH
:
1521 /* If the target has 64-bit pointers and the object file only
1522 supports 32-bit symbols, the values of those symbols will be
1523 sign-extended. In this case we can't allow an arbitrary offset
1524 in case the 32-bit value X + OFFSET has a different sign from X. */
1525 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1526 return offset_within_block_p (x
, INTVAL (offset
));
1528 /* In other cases the relocations can handle any offset. */
1531 case SYMBOL_PC_RELATIVE
:
1532 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1533 In this case, we no longer have access to the underlying constant,
1534 but the original symbol-based access was known to be valid. */
1535 if (GET_CODE (x
) == LABEL_REF
)
1540 case SYMBOL_GP_RELATIVE
:
1541 /* Make sure that the offset refers to something within the
1542 same object block. This should guarantee that the final
1543 PC- or GP-relative offset is within the 16-bit limit. */
1544 return offset_within_block_p (x
, INTVAL (offset
));
1546 case SYMBOL_GOT_PAGE_OFST
:
1547 case SYMBOL_GOTOFF_PAGE
:
1548 /* If the symbol is global, the GOT entry will contain the symbol's
1549 address, and we will apply a 16-bit offset after loading it.
1550 If the symbol is local, the linker should provide enough local
1551 GOT entries for a 16-bit offset, but larger offsets may lead
1553 return SMALL_INT (offset
);
1557 /* There is no carry between the HI and LO REL relocations, so the
1558 offset is only valid if we know it won't lead to such a carry. */
1559 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1561 case SYMBOL_GOT_DISP
:
1562 case SYMBOL_GOTOFF_DISP
:
1563 case SYMBOL_GOTOFF_CALL
:
1564 case SYMBOL_GOTOFF_LOADGP
:
1567 case SYMBOL_GOTTPREL
:
1575 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1576 single instruction. We rely on the fact that, in the worst case,
1577 all instructions involved in a MIPS16 address calculation are usually
1581 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1585 case SYMBOL_ABSOLUTE
:
1586 /* When using 64-bit symbols, we need 5 preparatory instructions,
1589 lui $at,%highest(symbol)
1590 daddiu $at,$at,%higher(symbol)
1592 daddiu $at,$at,%hi(symbol)
1595 The final address is then $at + %lo(symbol). With 32-bit
1596 symbols we just need a preparatory LUI for normal mode and
1597 a preparatory LI and SLL for MIPS16. */
1598 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1600 case SYMBOL_GP_RELATIVE
:
1601 /* Treat GP-relative accesses as taking a single instruction on
1602 MIPS16 too; the copy of $gp can often be shared. */
1605 case SYMBOL_PC_RELATIVE
:
1606 /* PC-relative constants can be only be used with ADDIUPC,
1607 DADDIUPC, LWPC and LDPC. */
1608 if (mode
== MAX_MACHINE_MODE
1609 || GET_MODE_SIZE (mode
) == 4
1610 || GET_MODE_SIZE (mode
) == 8)
1613 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1616 case SYMBOL_FORCE_TO_MEM
:
1617 /* LEAs will be converted into constant-pool references by
1619 if (mode
== MAX_MACHINE_MODE
)
1622 /* The constant must be loaded and then dereferenced. */
1625 case SYMBOL_GOT_DISP
:
1626 /* The constant will have to be loaded from the GOT before it
1627 is used in an address. */
1628 if (mode
!= MAX_MACHINE_MODE
)
1633 case SYMBOL_GOT_PAGE_OFST
:
1634 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1635 local/global classification is accurate. The worst cases are:
1637 (1) For local symbols when generating o32 or o64 code. The assembler
1643 ...and the final address will be $at + %lo(symbol).
1645 (2) For global symbols when -mxgot. The assembler will use:
1647 lui $at,%got_hi(symbol)
1650 ...and the final address will be $at + %got_lo(symbol). */
1653 case SYMBOL_GOTOFF_PAGE
:
1654 case SYMBOL_GOTOFF_DISP
:
1655 case SYMBOL_GOTOFF_CALL
:
1656 case SYMBOL_GOTOFF_LOADGP
:
1657 case SYMBOL_32_HIGH
:
1658 case SYMBOL_64_HIGH
:
1664 case SYMBOL_GOTTPREL
:
1667 /* A 16-bit constant formed by a single relocation, or a 32-bit
1668 constant formed from a high 16-bit relocation and a low 16-bit
1669 relocation. Use mips_split_p to determine which. 32-bit
1670 constants need an "lui; addiu" sequence for normal mode and
1671 an "li; sll; addiu" sequence for MIPS16 mode. */
1672 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1675 /* We don't treat a bare TLS symbol as a constant. */
1681 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1682 to load symbols of type TYPE into a register. Return 0 if the given
1683 type of symbol cannot be used as an immediate operand.
1685 Otherwise, return the number of instructions needed to load or store
1686 values of mode MODE to or from addresses of type TYPE. Return 0 if
1687 the given type of symbol is not valid in addresses.
1689 In both cases, treat extended MIPS16 instructions as two instructions. */
1692 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1694 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1697 /* A for_each_rtx callback. Stop the search if *X references a
1698 thread-local symbol. */
1701 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1703 return mips_tls_symbol_p (*x
);
1706 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1709 mips_cannot_force_const_mem (rtx x
)
1715 /* As an optimization, reject constants that mips_legitimize_move
1718 Suppose we have a multi-instruction sequence that loads constant C
1719 into register R. If R does not get allocated a hard register, and
1720 R is used in an operand that allows both registers and memory
1721 references, reload will consider forcing C into memory and using
1722 one of the instruction's memory alternatives. Returning false
1723 here will force it to use an input reload instead. */
1724 if (GET_CODE (x
) == CONST_INT
)
1727 split_const (x
, &base
, &offset
);
1728 if (symbolic_operand (base
, VOIDmode
) && SMALL_INT (offset
))
1732 /* TLS symbols must be computed by mips_legitimize_move. */
1733 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
1739 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1740 constants when we're using a per-function constant pool. */
1743 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1744 const_rtx x ATTRIBUTE_UNUSED
)
1746 return !TARGET_MIPS16_PCREL_LOADS
;
1749 /* Return true if register REGNO is a valid base register for mode MODE.
1750 STRICT_P is true if REG_OK_STRICT is in effect. */
1753 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
1756 if (!HARD_REGISTER_NUM_P (regno
))
1760 regno
= reg_renumber
[regno
];
1763 /* These fake registers will be eliminated to either the stack or
1764 hard frame pointer, both of which are usually valid base registers.
1765 Reload deals with the cases where the eliminated form isn't valid. */
1766 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
1769 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1770 values, nothing smaller. There are two problems here:
1772 (a) Instantiating virtual registers can introduce new uses of the
1773 stack pointer. If these virtual registers are valid addresses,
1774 the stack pointer should be too.
1776 (b) Most uses of the stack pointer are not made explicit until
1777 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1778 We don't know until that stage whether we'll be eliminating to the
1779 stack pointer (which needs the restriction) or the hard frame
1780 pointer (which doesn't).
1782 All in all, it seems more consistent to only enforce this restriction
1783 during and after reload. */
1784 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
1785 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1787 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
1790 /* Return true if X is a valid base register for mode MODE.
1791 STRICT_P is true if REG_OK_STRICT is in effect. */
1794 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
1796 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1800 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
1803 /* Return true if X is a valid address for machine mode MODE. If it is,
1804 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1808 mips_classify_address (struct mips_address_info
*info
, rtx x
,
1809 enum machine_mode mode
, bool strict_p
)
1811 switch (GET_CODE (x
))
1815 info
->type
= ADDRESS_REG
;
1817 info
->offset
= const0_rtx
;
1818 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
1821 info
->type
= ADDRESS_REG
;
1822 info
->reg
= XEXP (x
, 0);
1823 info
->offset
= XEXP (x
, 1);
1824 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
1825 && const_arith_operand (info
->offset
, VOIDmode
));
1828 info
->type
= ADDRESS_LO_SUM
;
1829 info
->reg
= XEXP (x
, 0);
1830 info
->offset
= XEXP (x
, 1);
1831 /* We have to trust the creator of the LO_SUM to do something vaguely
1832 sane. Target-independent code that creates a LO_SUM should also
1833 create and verify the matching HIGH. Target-independent code that
1834 adds an offset to a LO_SUM must prove that the offset will not
1835 induce a carry. Failure to do either of these things would be
1836 a bug, and we are not required to check for it here. The MIPS
1837 backend itself should only create LO_SUMs for valid symbolic
1838 constants, with the high part being either a HIGH or a copy
1841 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
1842 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
1843 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
1844 && mips_lo_relocs
[info
->symbol_type
] != 0);
1847 /* Small-integer addresses don't occur very often, but they
1848 are legitimate if $0 is a valid base register. */
1849 info
->type
= ADDRESS_CONST_INT
;
1850 return !TARGET_MIPS16
&& SMALL_INT (x
);
1855 info
->type
= ADDRESS_SYMBOLIC
;
1856 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
1858 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
1859 && !mips_split_p
[info
->symbol_type
]);
1866 /* Return true if X is a legitimate address for a memory operand of mode
1867 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
1870 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1872 struct mips_address_info addr
;
1874 return mips_classify_address (&addr
, x
, mode
, strict_p
);
1877 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1880 mips_stack_address_p (rtx x
, enum machine_mode mode
)
1882 struct mips_address_info addr
;
1884 return (mips_classify_address (&addr
, x
, mode
, false)
1885 && addr
.type
== ADDRESS_REG
1886 && addr
.reg
== stack_pointer_rtx
);
1889 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
1890 address instruction. Note that such addresses are not considered
1891 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
1892 is so restricted. */
1895 mips_lwxs_address_p (rtx addr
)
1898 && GET_CODE (addr
) == PLUS
1899 && REG_P (XEXP (addr
, 1)))
1901 rtx offset
= XEXP (addr
, 0);
1902 if (GET_CODE (offset
) == MULT
1903 && REG_P (XEXP (offset
, 0))
1904 && GET_CODE (XEXP (offset
, 1)) == CONST_INT
1905 && INTVAL (XEXP (offset
, 1)) == 4)
1911 /* Return true if a value at OFFSET bytes from base register BASE can be
1912 accessed using an unextended MIPS16 instruction. MODE is the mode of
1915 Usually the offset in an unextended instruction is a 5-bit field.
1916 The offset is unsigned and shifted left once for LH and SH, twice
1917 for LW and SW, and so on. An exception is LWSP and SWSP, which have
1918 an 8-bit immediate field that's shifted left twice. */
1921 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
1922 unsigned HOST_WIDE_INT offset
)
1924 if (offset
% GET_MODE_SIZE (mode
) == 0)
1926 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
1927 return offset
< 256U * GET_MODE_SIZE (mode
);
1928 return offset
< 32U * GET_MODE_SIZE (mode
);
1933 /* Return the number of instructions needed to load or store a value
1934 of mode MODE at address X. Return 0 if X isn't valid for MODE.
1935 Assume that multiword moves may need to be split into word moves
1936 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
1939 For MIPS16 code, count extended instructions as two instructions. */
1942 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
1944 struct mips_address_info addr
;
1947 /* BLKmode is used for single unaligned loads and stores and should
1948 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
1949 meaningless, so we have to single it out as a special case one way
1951 if (mode
!= BLKmode
&& might_split_p
)
1952 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1956 if (mips_classify_address (&addr
, x
, mode
, false))
1961 && !mips16_unextended_reference_p (mode
, addr
.reg
,
1962 UINTVAL (addr
.offset
)))
1966 case ADDRESS_LO_SUM
:
1967 return TARGET_MIPS16
? factor
* 2 : factor
;
1969 case ADDRESS_CONST_INT
:
1972 case ADDRESS_SYMBOLIC
:
1973 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
1978 /* Return the number of instructions needed to load constant X.
1979 Return 0 if X isn't a valid constant. */
1982 mips_const_insns (rtx x
)
1984 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
1985 enum mips_symbol_type symbol_type
;
1988 switch (GET_CODE (x
))
1991 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
1993 || !mips_split_p
[symbol_type
])
1996 /* This is simply an LUI for normal mode. It is an extended
1997 LI followed by an extended SLL for MIPS16. */
1998 return TARGET_MIPS16
? 4 : 1;
2002 /* Unsigned 8-bit constants can be loaded using an unextended
2003 LI instruction. Unsigned 16-bit constants can be loaded
2004 using an extended LI. Negative constants must be loaded
2005 using LI and then negated. */
2006 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2007 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2008 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2009 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2012 return mips_build_integer (codes
, INTVAL (x
));
2016 /* Allow zeros for normal mode, where we can use $0. */
2017 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2023 /* See if we can refer to X directly. */
2024 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2025 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2027 /* Otherwise try splitting the constant into a base and offset.
2028 16-bit offsets can be added using an extra ADDIU. Larger offsets
2029 must be calculated separately and then added to the base. */
2030 split_const (x
, &x
, &offset
);
2033 int n
= mips_const_insns (x
);
2036 if (SMALL_INT (offset
))
2039 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2046 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2054 /* Return the number of instructions needed to implement INSN,
2055 given that it loads from or stores to MEM. Count extended
2056 MIPS16 instructions as two instructions. */
2059 mips_load_store_insns (rtx mem
, rtx insn
)
2061 enum machine_mode mode
;
2065 gcc_assert (MEM_P (mem
));
2066 mode
= GET_MODE (mem
);
2068 /* Try to prove that INSN does not need to be split. */
2069 might_split_p
= true;
2070 if (GET_MODE_BITSIZE (mode
) == 64)
2072 set
= single_set (insn
);
2073 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2074 might_split_p
= false;
2077 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2080 /* Return the number of instructions needed for an integer division. */
2083 mips_idiv_insns (void)
2088 if (TARGET_CHECK_ZERO_DIV
)
2090 if (GENERATE_DIVIDE_TRAPS
)
2096 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2101 /* Emit a move from SRC to DEST. Assume that the move expanders can
2102 handle all moves if !can_create_pseudo_p (). The distinction is
2103 important because, unlike emit_move_insn, the move expanders know
2104 how to force Pmode objects into the constant pool even when the
2105 constant pool address is not itself legitimate. */
2108 mips_emit_move (rtx dest
, rtx src
)
2110 return (can_create_pseudo_p ()
2111 ? emit_move_insn (dest
, src
)
2112 : emit_move_insn_1 (dest
, src
));
2115 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2118 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2120 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2121 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2124 /* Copy VALUE to a register and return that register. If new pseudos
2125 are allowed, copy it into a new register, otherwise use DEST. */
2128 mips_force_temporary (rtx dest
, rtx value
)
2130 if (can_create_pseudo_p ())
2131 return force_reg (Pmode
, value
);
2134 mips_emit_move (dest
, value
);
2139 /* Emit a call sequence with call pattern PATTERN and return the call
2140 instruction itself (which is not necessarily the last instruction
2141 emitted). LAZY_P is true if the call address is lazily-bound. */
2144 mips_emit_call_insn (rtx pattern
, bool lazy_p
)
2148 insn
= emit_call_insn (pattern
);
2150 /* Lazy-binding stubs require $gp to be valid on entry. */
2152 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2156 /* See the comment above load_call<mode> for details. */
2157 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2158 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2159 emit_insn (gen_update_got_version ());
2164 /* Return a pseudo register that contains the value of $gp throughout
2165 the current function. Such registers are needed by MIPS16 functions,
2166 for which $gp itself is not a valid base register or addition operand. */
2169 mips16_gp_pseudo_reg (void)
2171 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2172 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2174 /* Don't emit an instruction to initialize the pseudo register if
2175 we are being called from the tree optimizers' cost-calculation
2177 if (!cfun
->machine
->initialized_mips16_gp_pseudo_p
2178 && (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
))
2180 rtx insn
, scan
, after
;
2182 /* We want GCC to treat the register's value as constant, so that
2183 it can be rematerialized on demand. */
2184 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2186 push_topmost_sequence ();
2187 /* We need to emit the initialization after the FUNCTION_BEG
2188 note, so that it will be integrated. */
2189 after
= get_insns ();
2190 for (scan
= after
; scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
2191 if (NOTE_P (scan
) && NOTE_KIND (scan
) == NOTE_INSN_FUNCTION_BEG
)
2196 insn
= emit_insn_after (insn
, after
);
2197 pop_topmost_sequence ();
2199 cfun
->machine
->initialized_mips16_gp_pseudo_p
= true;
2202 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2205 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2206 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2207 constant in that context and can be split into a high part and a LO_SUM.
2208 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2209 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2211 TEMP is as for mips_force_temporary and is used to load the high
2212 part into a register. */
2215 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*lo_sum_out
)
2217 enum mips_symbol_context context
;
2218 enum mips_symbol_type symbol_type
;
2221 context
= (mode
== MAX_MACHINE_MODE
2222 ? SYMBOL_CONTEXT_LEA
2223 : SYMBOL_CONTEXT_MEM
);
2224 if (!mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2225 || mips_symbol_insns (symbol_type
, mode
) == 0
2226 || !mips_split_p
[symbol_type
])
2231 if (symbol_type
== SYMBOL_GP_RELATIVE
)
2233 if (!can_create_pseudo_p ())
2235 emit_insn (gen_load_const_gp (temp
));
2239 high
= mips16_gp_pseudo_reg ();
2243 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2244 high
= mips_force_temporary (temp
, high
);
2246 *lo_sum_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2251 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2252 then add CONST_INT OFFSET to the result. */
2255 mips_unspec_address_offset (rtx base
, rtx offset
,
2256 enum mips_symbol_type symbol_type
)
2258 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2259 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2260 if (offset
!= const0_rtx
)
2261 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2262 return gen_rtx_CONST (Pmode
, base
);
2265 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2266 type SYMBOL_TYPE. */
2269 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2273 split_const (address
, &base
, &offset
);
2274 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2277 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2278 high part to BASE and return the result. Just return BASE otherwise.
2279 TEMP is as for mips_force_temporary.
2281 The returned expression can be used as the first operand to a LO_SUM. */
2284 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2285 enum mips_symbol_type symbol_type
)
2287 if (mips_split_p
[symbol_type
])
2289 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2290 addr
= mips_force_temporary (temp
, addr
);
2291 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2296 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2297 mips_force_temporary; it is only needed when OFFSET is not a
2301 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2303 if (!SMALL_OPERAND (offset
))
2309 /* Load the full offset into a register so that we can use
2310 an unextended instruction for the address itself. */
2311 high
= GEN_INT (offset
);
2316 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2317 high
= GEN_INT (CONST_HIGH_PART (offset
));
2318 offset
= CONST_LOW_PART (offset
);
2320 high
= mips_force_temporary (temp
, high
);
2321 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2323 return plus_constant (reg
, offset
);
2326 /* The __tls_get_attr symbol. */
2327 static GTY(()) rtx mips_tls_symbol
;
2329 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2330 the TLS symbol we are referencing and TYPE is the symbol type to use
2331 (either global dynamic or local dynamic). V0 is an RTX for the
2332 return value location. */
2335 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2339 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2341 if (!mips_tls_symbol
)
2342 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2344 loc
= mips_unspec_address (sym
, type
);
2348 emit_insn (gen_rtx_SET (Pmode
, a0
,
2349 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2350 insn
= mips_expand_call (v0
, mips_tls_symbol
, const0_rtx
, const0_rtx
, false);
2351 CONST_OR_PURE_CALL_P (insn
) = 1;
2352 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2353 insn
= get_insns ();
2360 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2361 its address. The return value will be both a valid address and a valid
2362 SET_SRC (either a REG or a LO_SUM). */
2365 mips_legitimize_tls_address (rtx loc
)
2367 rtx dest
, insn
, v0
, v1
, tmp1
, tmp2
, eqv
;
2368 enum tls_model model
;
2372 sorry ("MIPS16 TLS");
2373 return gen_reg_rtx (Pmode
);
2376 model
= SYMBOL_REF_TLS_MODEL (loc
);
2377 /* Only TARGET_ABICALLS code can have more than one module; other
2378 code must be be static and should not use a GOT. All TLS models
2379 reduce to local exec in this situation. */
2380 if (!TARGET_ABICALLS
)
2381 model
= TLS_MODEL_LOCAL_EXEC
;
2385 case TLS_MODEL_GLOBAL_DYNAMIC
:
2386 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2387 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2388 dest
= gen_reg_rtx (Pmode
);
2389 emit_libcall_block (insn
, dest
, v0
, loc
);
2392 case TLS_MODEL_LOCAL_DYNAMIC
:
2393 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2394 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2395 tmp1
= gen_reg_rtx (Pmode
);
2397 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2398 share the LDM result with other LD model accesses. */
2399 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2401 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2403 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2404 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2405 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2408 case TLS_MODEL_INITIAL_EXEC
:
2409 v1
= gen_rtx_REG (Pmode
, GP_RETURN
+ 1);
2410 tmp1
= gen_reg_rtx (Pmode
);
2411 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2412 if (Pmode
== DImode
)
2414 emit_insn (gen_tls_get_tp_di (v1
));
2415 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2419 emit_insn (gen_tls_get_tp_si (v1
));
2420 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2422 dest
= gen_reg_rtx (Pmode
);
2423 emit_insn (gen_add3_insn (dest
, tmp1
, v1
));
2426 case TLS_MODEL_LOCAL_EXEC
:
2427 v1
= gen_rtx_REG (Pmode
, GP_RETURN
+ 1);
2428 if (Pmode
== DImode
)
2429 emit_insn (gen_tls_get_tp_di (v1
));
2431 emit_insn (gen_tls_get_tp_si (v1
));
2433 tmp1
= mips_unspec_offset_high (NULL
, v1
, loc
, SYMBOL_TPREL
);
2434 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2435 mips_unspec_address (loc
, SYMBOL_TPREL
));
2444 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2445 be legitimized in a way that the generic machinery might not expect,
2446 put the new address in *XLOC and return true. MODE is the mode of
2447 the memory being accessed. */
2450 mips_legitimize_address (rtx
*xloc
, enum machine_mode mode
)
2453 HOST_WIDE_INT offset
;
2455 if (mips_tls_symbol_p (*xloc
))
2457 *xloc
= mips_legitimize_tls_address (*xloc
);
2461 /* See if the address can split into a high part and a LO_SUM. */
2462 if (mips_split_symbol (NULL
, *xloc
, mode
, xloc
))
2465 /* Handle BASE + OFFSET using mips_add_offset. */
2466 mips_split_plus (*xloc
, &base
, &offset
);
2469 if (!mips_valid_base_register_p (base
, mode
, false))
2470 base
= copy_to_mode_reg (Pmode
, base
);
2471 *xloc
= mips_add_offset (NULL
, base
, offset
);
2477 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2480 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
2482 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2483 enum machine_mode mode
;
2484 unsigned int i
, num_ops
;
2487 mode
= GET_MODE (dest
);
2488 num_ops
= mips_build_integer (codes
, value
);
2490 /* Apply each binary operation to X. Invariant: X is a legitimate
2491 source operand for a SET pattern. */
2492 x
= GEN_INT (codes
[0].value
);
2493 for (i
= 1; i
< num_ops
; i
++)
2495 if (!can_create_pseudo_p ())
2497 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
2501 x
= force_reg (mode
, x
);
2502 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
2505 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
2508 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2509 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2513 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
2517 /* Split moves of big integers into smaller pieces. */
2518 if (splittable_const_int_operand (src
, mode
))
2520 mips_move_integer (dest
, dest
, INTVAL (src
));
2524 /* Split moves of symbolic constants into high/low pairs. */
2525 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
2527 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
2531 /* Generate the appropriate access sequences for TLS symbols. */
2532 if (mips_tls_symbol_p (src
))
2534 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
2538 /* If we have (const (plus symbol offset)), and that expression cannot
2539 be forced into memory, load the symbol first and add in the offset.
2540 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2541 forced into memory, as it usually produces better code. */
2542 split_const (src
, &base
, &offset
);
2543 if (offset
!= const0_rtx
2544 && (targetm
.cannot_force_const_mem (src
)
2545 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
2547 base
= mips_force_temporary (dest
, base
);
2548 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
2552 src
= force_const_mem (mode
, src
);
2554 /* When using explicit relocs, constant pool references are sometimes
2555 not legitimate addresses. */
2556 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
2557 mips_emit_move (dest
, src
);
2560 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2561 sequence that is valid. */
2564 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
2566 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
2568 mips_emit_move (dest
, force_reg (mode
, src
));
2572 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2573 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
2574 && REG_P (src
) && MD_REG_P (REGNO (src
))
2575 && REG_P (dest
) && GP_REG_P (REGNO (dest
)))
2577 int other_regno
= REGNO (src
) == HI_REGNUM
? LO_REGNUM
: HI_REGNUM
;
2578 if (GET_MODE_SIZE (mode
) <= 4)
2579 emit_insn (gen_mfhilo_si (gen_lowpart (SImode
, dest
),
2580 gen_lowpart (SImode
, src
),
2581 gen_rtx_REG (SImode
, other_regno
)));
2583 emit_insn (gen_mfhilo_di (gen_lowpart (DImode
, dest
),
2584 gen_lowpart (DImode
, src
),
2585 gen_rtx_REG (DImode
, other_regno
)));
2589 /* We need to deal with constants that would be legitimate
2590 immediate_operands but aren't legitimate move_operands. */
2591 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
2593 mips_legitimize_const_move (mode
, dest
, src
);
2594 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
2600 /* Return true if value X in context CONTEXT is a small-data address
2601 that can be rewritten as a LO_SUM. */
2604 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
2606 enum mips_symbol_type symbol_type
;
2608 return (TARGET_EXPLICIT_RELOCS
2609 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
2610 && symbol_type
== SYMBOL_GP_RELATIVE
);
2613 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2614 containing MEM, or null if none. */
2617 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
2619 enum mips_symbol_context context
;
2621 if (GET_CODE (*loc
) == LO_SUM
)
2626 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
2631 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
2632 return mips_rewrite_small_data_p (*loc
, context
);
2635 /* Return true if OP refers to small data symbols directly, not through
2639 mips_small_data_pattern_p (rtx op
)
2641 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
2644 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2645 DATA is the containing MEM, or null if none. */
2648 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
2650 enum mips_symbol_context context
;
2654 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
2658 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
2659 if (mips_rewrite_small_data_p (*loc
, context
))
2660 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
2662 if (GET_CODE (*loc
) == LO_SUM
)
2668 /* Rewrite instruction pattern PATTERN so that it refers to small data
2669 using explicit relocations. */
2672 mips_rewrite_small_data (rtx pattern
)
2674 pattern
= copy_insn (pattern
);
2675 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
2679 /* We need a lot of little routines to check the range of MIPS16 immediate
2683 m16_check_op (rtx op
, int low
, int high
, int mask
)
2685 return (GET_CODE (op
) == CONST_INT
2686 && IN_RANGE (INTVAL (op
), low
, high
)
2687 && (INTVAL (op
) & mask
) == 0);
2691 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2693 return m16_check_op (op
, 0x1, 0x8, 0);
2697 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2699 return m16_check_op (op
, -0x8, 0x7, 0);
2703 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2705 return m16_check_op (op
, -0x7, 0x8, 0);
2709 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2711 return m16_check_op (op
, -0x10, 0xf, 0);
2715 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2717 return m16_check_op (op
, -0xf, 0x10, 0);
2721 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2723 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
2727 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2729 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
2733 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2735 return m16_check_op (op
, -0x80, 0x7f, 0);
2739 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2741 return m16_check_op (op
, -0x7f, 0x80, 0);
2745 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2747 return m16_check_op (op
, 0x0, 0xff, 0);
2751 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2753 return m16_check_op (op
, -0xff, 0x0, 0);
2757 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2759 return m16_check_op (op
, -0x1, 0xfe, 0);
2763 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2765 return m16_check_op (op
, 0x0, 0xff << 2, 3);
2769 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2771 return m16_check_op (op
, -0xff << 2, 0x0, 3);
2775 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2777 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
2781 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2783 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
2786 /* The cost of loading values from the constant pool. It should be
2787 larger than the cost of any constant we want to synthesize inline. */
2788 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2790 /* Return the cost of X when used as an operand to the MIPS16 instruction
2791 that implements CODE. Return -1 if there is no such instruction, or if
2792 X is not a valid immediate operand for it. */
2795 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
2802 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2803 other shifts are extended. The shift patterns truncate the shift
2804 count to the right size, so there are no out-of-range values. */
2805 if (IN_RANGE (x
, 1, 8))
2807 return COSTS_N_INSNS (1);
2810 if (IN_RANGE (x
, -128, 127))
2812 if (SMALL_OPERAND (x
))
2813 return COSTS_N_INSNS (1);
2817 /* Like LE, but reject the always-true case. */
2821 /* We add 1 to the immediate and use SLT. */
2824 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2827 if (IN_RANGE (x
, 0, 255))
2829 if (SMALL_OPERAND_UNSIGNED (x
))
2830 return COSTS_N_INSNS (1);
2835 /* Equality comparisons with 0 are cheap. */
2845 /* Return true if there is a non-MIPS16 instruction that implements CODE
2846 and if that instruction accepts X as an immediate operand. */
2849 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
2856 /* All shift counts are truncated to a valid constant. */
2861 /* Likewise rotates, if the target supports rotates at all. */
2867 /* These instructions take 16-bit unsigned immediates. */
2868 return SMALL_OPERAND_UNSIGNED (x
);
2873 /* These instructions take 16-bit signed immediates. */
2874 return SMALL_OPERAND (x
);
2880 /* The "immediate" forms of these instructions are really
2881 implemented as comparisons with register 0. */
2886 /* Likewise, meaning that the only valid immediate operand is 1. */
2890 /* We add 1 to the immediate and use SLT. */
2891 return SMALL_OPERAND (x
+ 1);
2894 /* Likewise SLTU, but reject the always-true case. */
2895 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
2899 /* The bit position and size are immediate operands. */
2900 return ISA_HAS_EXT_INS
;
2903 /* By default assume that $0 can be used for 0. */
2908 /* Return the cost of binary operation X, given that the instruction
2909 sequence for a word-sized or smaller operation has cost SINGLE_COST
2910 and that the sequence of a double-word operation has cost DOUBLE_COST. */
2913 mips_binary_cost (rtx x
, int single_cost
, int double_cost
)
2917 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
2922 + rtx_cost (XEXP (x
, 0), 0)
2923 + rtx_cost (XEXP (x
, 1), GET_CODE (x
)));
2926 /* Return the cost of floating-point multiplications of mode MODE. */
2929 mips_fp_mult_cost (enum machine_mode mode
)
2931 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
2934 /* Return the cost of floating-point divisions of mode MODE. */
2937 mips_fp_div_cost (enum machine_mode mode
)
2939 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
2942 /* Return the cost of sign-extending OP to mode MODE, not including the
2943 cost of OP itself. */
2946 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
2949 /* Extended loads are as cheap as unextended ones. */
2952 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
2953 /* A sign extension from SImode to DImode in 64-bit mode is free. */
2956 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
2957 /* We can use SEB or SEH. */
2958 return COSTS_N_INSNS (1);
2960 /* We need to use a shift left and a shift right. */
2961 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
2964 /* Return the cost of zero-extending OP to mode MODE, not including the
2965 cost of OP itself. */
2968 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
2971 /* Extended loads are as cheap as unextended ones. */
2974 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
2975 /* We need a shift left by 32 bits and a shift right by 32 bits. */
2976 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
2978 if (GENERATE_MIPS16E
)
2979 /* We can use ZEB or ZEH. */
2980 return COSTS_N_INSNS (1);
2983 /* We need to load 0xff or 0xffff into a register and use AND. */
2984 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
2986 /* We can use ANDI. */
2987 return COSTS_N_INSNS (1);
2990 /* Implement TARGET_RTX_COSTS. */
2993 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2995 enum machine_mode mode
= GET_MODE (x
);
2996 bool float_mode_p
= FLOAT_MODE_P (mode
);
3000 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3001 appear in the instruction stream, and the cost of a comparison is
3002 really the cost of the branch or scc condition. At the time of
3003 writing, GCC only uses an explicit outer COMPARE code when optabs
3004 is testing whether a constant is expensive enough to force into a
3005 register. We want optabs to pass such constants through the MIPS
3006 expanders instead, so make all constants very cheap here. */
3007 if (outer_code
== COMPARE
)
3009 gcc_assert (CONSTANT_P (x
));
3017 /* Treat *clear_upper32-style ANDs as having zero cost in the
3018 second operand. The cost is entirely in the first operand.
3020 ??? This is needed because we would otherwise try to CSE
3021 the constant operand. Although that's the right thing for
3022 instructions that continue to be a register operation throughout
3023 compilation, it is disastrous for instructions that could
3024 later be converted into a memory operation. */
3026 && outer_code
== AND
3027 && UINTVAL (x
) == 0xffffffff)
3035 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3044 /* When not optimizing for size, we care more about the cost
3045 of hot code, and hot code is often in a loop. If a constant
3046 operand needs to be forced into a register, we will often be
3047 able to hoist the constant load out of the loop, so the load
3048 should not contribute to the cost. */
3050 || mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3062 if (force_to_mem_operand (x
, VOIDmode
))
3064 *total
= COSTS_N_INSNS (1);
3067 cost
= mips_const_insns (x
);
3070 /* If the constant is likely to be stored in a GPR, SETs of
3071 single-insn constants are as cheap as register sets; we
3072 never want to CSE them.
3074 Don't reduce the cost of storing a floating-point zero in
3075 FPRs. If we have a zero in an FPR for other reasons, we
3076 can get better cfg-cleanup and delayed-branch results by
3077 using it consistently, rather than using $0 sometimes and
3078 an FPR at other times. Also, moves between floating-point
3079 registers are sometimes cheaper than (D)MTC1 $0. */
3081 && outer_code
== SET
3082 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3084 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3085 want to CSE the constant itself. It is usually better to
3086 have N copies of the last operation in the sequence and one
3087 shared copy of the other operations. (Note that this is
3088 not true for MIPS16 code, where the final operation in the
3089 sequence is often an extended instruction.)
3091 Also, if we have a CONST_INT, we don't know whether it is
3092 for a word or doubleword operation, so we cannot rely on
3093 the result of mips_build_integer. */
3094 else if (!TARGET_MIPS16
3095 && (outer_code
== SET
|| mode
== VOIDmode
))
3097 *total
= COSTS_N_INSNS (cost
);
3100 /* The value will need to be fetched from the constant pool. */
3101 *total
= CONSTANT_POOL_COST
;
3105 /* If the address is legitimate, return the number of
3106 instructions it needs. */
3108 cost
= mips_address_insns (addr
, mode
, true);
3111 *total
= COSTS_N_INSNS (cost
+ 1);
3114 /* Check for a scaled indexed address. */
3115 if (mips_lwxs_address_p (addr
))
3117 *total
= COSTS_N_INSNS (2);
3120 /* Otherwise use the default handling. */
3124 *total
= COSTS_N_INSNS (6);
3128 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3132 /* Check for a *clear_upper32 pattern and treat it like a zero
3133 extension. See the pattern's comment for details. */
3136 && CONST_INT_P (XEXP (x
, 1))
3137 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3139 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3140 + rtx_cost (XEXP (x
, 0), 0));
3147 /* Double-word operations use two single-word operations. */
3148 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3156 if (CONSTANT_P (XEXP (x
, 1)))
3157 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3159 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3164 *total
= mips_cost
->fp_add
;
3166 *total
= COSTS_N_INSNS (4);
3170 /* Low-part immediates need an extended MIPS16 instruction. */
3171 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3172 + rtx_cost (XEXP (x
, 0), 0));
3187 /* Branch comparisons have VOIDmode, so use the first operand's
3189 mode
= GET_MODE (XEXP (x
, 0));
3190 if (FLOAT_MODE_P (mode
))
3192 *total
= mips_cost
->fp_add
;
3195 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3200 && ISA_HAS_NMADD_NMSUB (mode
)
3201 && TARGET_FUSED_MADD
3202 && !HONOR_NANS (mode
)
3203 && !HONOR_SIGNED_ZEROS (mode
))
3205 /* See if we can use NMADD or NMSUB. See mips.md for the
3206 associated patterns. */
3207 rtx op0
= XEXP (x
, 0);
3208 rtx op1
= XEXP (x
, 1);
3209 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3211 *total
= (mips_fp_mult_cost (mode
)
3212 + rtx_cost (XEXP (XEXP (op0
, 0), 0), 0)
3213 + rtx_cost (XEXP (op0
, 1), 0)
3214 + rtx_cost (op1
, 0));
3217 if (GET_CODE (op1
) == MULT
)
3219 *total
= (mips_fp_mult_cost (mode
)
3221 + rtx_cost (XEXP (op1
, 0), 0)
3222 + rtx_cost (XEXP (op1
, 1), 0));
3231 /* If this is part of a MADD or MSUB, treat the PLUS as
3234 && TARGET_FUSED_MADD
3235 && GET_CODE (XEXP (x
, 0)) == MULT
)
3238 *total
= mips_cost
->fp_add
;
3242 /* Double-word operations require three single-word operations and
3243 an SLTU. The MIPS16 version then needs to move the result of
3244 the SLTU from $24 to a MIPS16 register. */
3245 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3246 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4));
3251 && ISA_HAS_NMADD_NMSUB (mode
)
3252 && TARGET_FUSED_MADD
3253 && !HONOR_NANS (mode
)
3254 && HONOR_SIGNED_ZEROS (mode
))
3256 /* See if we can use NMADD or NMSUB. See mips.md for the
3257 associated patterns. */
3258 rtx op
= XEXP (x
, 0);
3259 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3260 && GET_CODE (XEXP (op
, 0)) == MULT
)
3262 *total
= (mips_fp_mult_cost (mode
)
3263 + rtx_cost (XEXP (XEXP (op
, 0), 0), 0)
3264 + rtx_cost (XEXP (XEXP (op
, 0), 1), 0)
3265 + rtx_cost (XEXP (op
, 1), 0));
3271 *total
= mips_cost
->fp_add
;
3273 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3278 *total
= mips_fp_mult_cost (mode
);
3279 else if (mode
== DImode
&& !TARGET_64BIT
)
3280 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3281 where the mulsidi3 always includes an MFHI and an MFLO. */
3282 *total
= (optimize_size
3283 ? COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9)
3284 : mips_cost
->int_mult_si
* 3 + 6);
3285 else if (optimize_size
)
3286 *total
= (ISA_HAS_MUL3
? 1 : 2);
3287 else if (mode
== DImode
)
3288 *total
= mips_cost
->int_mult_di
;
3290 *total
= mips_cost
->int_mult_si
;
3294 /* Check for a reciprocal. */
3297 && flag_unsafe_math_optimizations
3298 && XEXP (x
, 0) == CONST1_RTX (mode
))
3300 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3301 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3302 division as being free. */
3303 *total
= rtx_cost (XEXP (x
, 1), 0);
3305 *total
= mips_fp_div_cost (mode
) + rtx_cost (XEXP (x
, 1), 0);
3314 *total
= mips_fp_div_cost (mode
);
3323 /* It is our responsibility to make division by a power of 2
3324 as cheap as 2 register additions if we want the division
3325 expanders to be used for such operations; see the setting
3326 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3327 should always produce shorter code than using
3328 expand_sdiv2_pow2. */
3330 && CONST_INT_P (XEXP (x
, 1))
3331 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3333 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), 0);
3336 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3338 else if (mode
== DImode
)
3339 *total
= mips_cost
->int_div_di
;
3341 *total
= mips_cost
->int_div_si
;
3345 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3349 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3353 case UNSIGNED_FLOAT
:
3356 case FLOAT_TRUNCATE
:
3357 *total
= mips_cost
->fp_add
;
3365 /* Implement TARGET_ADDRESS_COST. */
3368 mips_address_cost (rtx addr
)
3370 return mips_address_insns (addr
, SImode
, false);
3373 /* Return one word of double-word value OP, taking into account the fixed
3374 endianness of certain registers. HIGH_P is true to select the high part,
3375 false to select the low part. */
3378 mips_subword (rtx op
, bool high_p
)
3380 unsigned int byte
, offset
;
3381 enum machine_mode mode
;
3383 mode
= GET_MODE (op
);
3384 if (mode
== VOIDmode
)
3387 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
3388 byte
= UNITS_PER_WORD
;
3392 if (FP_REG_RTX_P (op
))
3394 /* Paired FPRs are always ordered little-endian. */
3395 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
3396 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
3400 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
3402 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
3405 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3408 mips_split_64bit_move_p (rtx dest
, rtx src
)
3413 /* FPR-to-FPR moves can be done in a single instruction, if they're
3415 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
3418 /* Check for floating-point loads and stores. */
3419 if (ISA_HAS_LDC1_SDC1
)
3421 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
3423 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
3429 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3430 this function handles 64-bit moves for which mips_split_64bit_move_p
3431 holds. For 64-bit targets, this function handles 128-bit moves. */
3434 mips_split_doubleword_move (rtx dest
, rtx src
)
3436 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
3438 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
3439 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
3440 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
3441 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
3442 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
3443 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
3444 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
3445 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
3451 /* The operation can be split into two normal moves. Decide in
3452 which order to do them. */
3455 low_dest
= mips_subword (dest
, false);
3456 if (REG_P (low_dest
)
3457 && reg_overlap_mentioned_p (low_dest
, src
))
3459 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
3460 mips_emit_move (low_dest
, mips_subword (src
, false));
3464 mips_emit_move (low_dest
, mips_subword (src
, false));
3465 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
3470 /* Return the appropriate instructions to move SRC into DEST. Assume
3471 that SRC is operand 1 and DEST is operand 0. */
3474 mips_output_move (rtx dest
, rtx src
)
3476 enum rtx_code dest_code
, src_code
;
3477 enum machine_mode mode
;
3478 enum mips_symbol_type symbol_type
;
3481 dest_code
= GET_CODE (dest
);
3482 src_code
= GET_CODE (src
);
3483 mode
= GET_MODE (dest
);
3484 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
3486 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
3489 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
3490 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
3492 if (dest_code
== REG
)
3494 if (GP_REG_P (REGNO (dest
)))
3495 return "move\t%0,%z1";
3497 if (MD_REG_P (REGNO (dest
)))
3500 if (DSP_ACC_REG_P (REGNO (dest
)))
3502 static char retval
[] = "mt__\t%z1,%q0";
3504 retval
[2] = reg_names
[REGNO (dest
)][4];
3505 retval
[3] = reg_names
[REGNO (dest
)][5];
3509 if (FP_REG_P (REGNO (dest
)))
3510 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3512 if (ALL_COP_REG_P (REGNO (dest
)))
3514 static char retval
[] = "dmtc_\t%z1,%0";
3516 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
3517 return dbl_p
? retval
: retval
+ 1;
3520 if (dest_code
== MEM
)
3521 return dbl_p
? "sd\t%z1,%0" : "sw\t%z1,%0";
3523 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
3525 if (src_code
== REG
)
3527 /* Handled by separate patterns. */
3528 gcc_assert (!MD_REG_P (REGNO (src
)));
3530 if (DSP_ACC_REG_P (REGNO (src
)))
3532 static char retval
[] = "mf__\t%0,%q1";
3534 retval
[2] = reg_names
[REGNO (src
)][4];
3535 retval
[3] = reg_names
[REGNO (src
)][5];
3539 if (FP_REG_P (REGNO (src
)))
3540 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3542 if (ALL_COP_REG_P (REGNO (src
)))
3544 static char retval
[] = "dmfc_\t%0,%1";
3546 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
3547 return dbl_p
? retval
: retval
+ 1;
3550 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
3551 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3554 if (src_code
== MEM
)
3555 return dbl_p
? "ld\t%0,%1" : "lw\t%0,%1";
3557 if (src_code
== CONST_INT
)
3559 /* Don't use the X format for the operand itself, because that
3560 will give out-of-range numbers for 64-bit hosts and 32-bit
3563 return "li\t%0,%1\t\t\t# %X1";
3565 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
3568 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
3572 if (src_code
== HIGH
)
3573 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
3575 if (CONST_GP_P (src
))
3576 return "move\t%0,%1";
3578 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
3579 && mips_lo_relocs
[symbol_type
] != 0)
3581 /* A signed 16-bit constant formed by applying a relocation
3582 operator to a symbolic address. */
3583 gcc_assert (!mips_split_p
[symbol_type
]);
3584 return "li\t%0,%R1";
3587 if (symbolic_operand (src
, VOIDmode
))
3589 gcc_assert (TARGET_MIPS16
3590 ? TARGET_MIPS16_TEXT_LOADS
3591 : !TARGET_EXPLICIT_RELOCS
);
3592 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
3595 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
3597 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
3599 if (GET_MODE (dest
) == V2SFmode
)
3600 return "mov.ps\t%0,%1";
3602 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3605 if (dest_code
== MEM
)
3606 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
3608 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
3610 if (src_code
== MEM
)
3611 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3613 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
3615 static char retval
[] = "l_c_\t%0,%1";
3617 retval
[1] = (dbl_p
? 'd' : 'w');
3618 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
3621 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
3623 static char retval
[] = "s_c_\t%1,%0";
3625 retval
[1] = (dbl_p
? 'd' : 'w');
3626 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
3632 /* Return true if CMP1 is a suitable second operand for integer ordering
3633 test CODE. See also the *sCC patterns in mips.md. */
3636 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
3642 return reg_or_0_operand (cmp1
, VOIDmode
);
3646 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
3650 return arith_operand (cmp1
, VOIDmode
);
3653 return sle_operand (cmp1
, VOIDmode
);
3656 return sleu_operand (cmp1
, VOIDmode
);
3663 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
3664 integer ordering test *CODE, or if an equivalent combination can
3665 be formed by adjusting *CODE and *CMP1. When returning true, update
3666 *CODE and *CMP1 with the chosen code and operand, otherwise leave
3670 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
3671 enum machine_mode mode
)
3673 HOST_WIDE_INT plus_one
;
3675 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
3678 if (GET_CODE (*cmp1
) == CONST_INT
)
3682 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
3683 if (INTVAL (*cmp1
) < plus_one
)
3686 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3692 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
3696 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3707 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
3708 in TARGET. CMP0 and TARGET are register_operands that have the same
3709 integer mode. If INVERT_PTR is nonnull, it's OK to set TARGET to the
3710 inverse of the result and flip *INVERT_PTR instead. */
3713 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
3714 rtx target
, rtx cmp0
, rtx cmp1
)
3716 enum machine_mode mode
;
3718 /* First see if there is a MIPS instruction that can do this operation.
3719 If not, try doing the same for the inverse operation. If that also
3720 fails, force CMP1 into a register and try again. */
3721 mode
= GET_MODE (target
);
3722 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
3723 mips_emit_binary (code
, target
, cmp0
, cmp1
);
3726 enum rtx_code inv_code
= reverse_condition (code
);
3727 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
3729 cmp1
= force_reg (mode
, cmp1
);
3730 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
3732 else if (invert_ptr
== 0)
3734 rtx inv_target
= gen_reg_rtx (mode
);
3735 mips_emit_binary (inv_code
, inv_target
, cmp0
, cmp1
);
3736 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
3740 *invert_ptr
= !*invert_ptr
;
3741 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
3746 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3747 The register will have the same mode as CMP0. */
3750 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
3752 if (cmp1
== const0_rtx
)
3755 if (uns_arith_operand (cmp1
, VOIDmode
))
3756 return expand_binop (GET_MODE (cmp0
), xor_optab
,
3757 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3759 return expand_binop (GET_MODE (cmp0
), sub_optab
,
3760 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3763 /* Convert *CODE into a code that can be used in a floating-point
3764 scc instruction (C.cond.fmt). Return true if the values of
3765 the condition code registers will be inverted, with 0 indicating
3766 that the condition holds. */
3769 mips_reversed_fp_cond (enum rtx_code
*code
)
3776 *code
= reverse_condition_maybe_unordered (*code
);
3784 /* Convert a comparison into something that can be used in a branch or
3785 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3786 being compared and *CODE is the code used to compare them.
3788 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3789 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
3790 otherwise any standard branch condition can be used. The standard branch
3793 - EQ or NE between two registers.
3794 - any comparison between a register and zero. */
3797 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
3799 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) == MODE_INT
)
3801 if (!need_eq_ne_p
&& cmp_operands
[1] == const0_rtx
)
3803 *op0
= cmp_operands
[0];
3804 *op1
= cmp_operands
[1];
3806 else if (*code
== EQ
|| *code
== NE
)
3810 *op0
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3815 *op0
= cmp_operands
[0];
3816 *op1
= force_reg (GET_MODE (*op0
), cmp_operands
[1]);
3821 /* The comparison needs a separate scc instruction. Store the
3822 result of the scc in *OP0 and compare it against zero. */
3823 bool invert
= false;
3824 *op0
= gen_reg_rtx (GET_MODE (cmp_operands
[0]));
3825 mips_emit_int_order_test (*code
, &invert
, *op0
,
3826 cmp_operands
[0], cmp_operands
[1]);
3827 *code
= (invert
? EQ
: NE
);
3831 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands
[0])))
3833 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
3834 mips_emit_binary (*code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3840 enum rtx_code cmp_code
;
3842 /* Floating-point tests use a separate C.cond.fmt comparison to
3843 set a condition code register. The branch or conditional move
3844 will then compare that register against zero.
3846 Set CMP_CODE to the code of the comparison instruction and
3847 *CODE to the code that the branch or move should use. */
3849 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
3851 ? gen_reg_rtx (CCmode
)
3852 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
3854 mips_emit_binary (cmp_code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3858 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3859 Store the result in TARGET and return true if successful.
3861 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3864 mips_expand_scc (enum rtx_code code
, rtx target
)
3866 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) != MODE_INT
)
3869 target
= gen_lowpart (GET_MODE (cmp_operands
[0]), target
);
3870 if (code
== EQ
|| code
== NE
)
3872 rtx zie
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3873 mips_emit_binary (code
, target
, zie
, const0_rtx
);
3876 mips_emit_int_order_test (code
, 0, target
,
3877 cmp_operands
[0], cmp_operands
[1]);
3881 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
3882 CODE and jump to OPERANDS[0] if the condition holds. */
3885 mips_expand_conditional_branch (rtx
*operands
, enum rtx_code code
)
3887 rtx op0
, op1
, condition
;
3889 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
3890 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3891 emit_jump_insn (gen_condjump (condition
, operands
[0]));
3896 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3897 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3900 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
3901 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
3906 reversed_p
= mips_reversed_fp_cond (&cond
);
3907 cmp_result
= gen_reg_rtx (CCV2mode
);
3908 emit_insn (gen_scc_ps (cmp_result
,
3909 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
3911 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
3914 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
3918 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
3919 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
3920 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
3923 mips_expand_conditional_move (rtx
*operands
)
3928 code
= GET_CODE (operands
[1]);
3929 mips_emit_compare (&code
, &op0
, &op1
, true);
3930 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
),
3931 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
3932 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
3933 operands
[2], operands
[3])));
3936 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
3937 then trap if the condition holds. */
3940 mips_expand_conditional_trap (enum rtx_code code
)
3943 enum machine_mode mode
;
3945 /* MIPS conditional trap instructions don't have GT or LE flavors,
3946 so we must swap the operands and convert to LT and GE respectively. */
3953 code
= swap_condition (code
);
3954 op0
= cmp_operands
[1];
3955 op1
= cmp_operands
[0];
3959 op0
= cmp_operands
[0];
3960 op1
= cmp_operands
[1];
3964 mode
= GET_MODE (cmp_operands
[0]);
3965 op0
= force_reg (mode
, op0
);
3966 if (!arith_operand (op1
, mode
))
3967 op1
= force_reg (mode
, op1
);
3969 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3970 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
3974 /* Initialize *CUM for a call to a function of type FNTYPE. */
3977 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
3979 memset (cum
, 0, sizeof (*cum
));
3980 cum
->prototype
= (fntype
&& prototype_p (fntype
));
3981 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
3984 /* Fill INFO with information about a single argument. CUM is the
3985 cumulative state for earlier arguments. MODE is the mode of this
3986 argument and TYPE is its type (if known). NAMED is true if this
3987 is a named (fixed) argument rather than a variable one. */
3990 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
3991 enum machine_mode mode
, tree type
, int named
)
3993 bool doubleword_aligned_p
;
3994 unsigned int num_bytes
, num_words
, max_regs
;
3996 /* Work out the size of the argument. */
3997 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
3998 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4000 /* Decide whether it should go in a floating-point register, assuming
4001 one is free. Later code checks for availability.
4003 The checks against UNITS_PER_FPVALUE handle the soft-float and
4004 single-float cases. */
4008 /* The EABI conventions have traditionally been defined in terms
4009 of TYPE_MODE, regardless of the actual type. */
4010 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4011 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4012 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4017 /* Only leading floating-point scalars are passed in
4018 floating-point registers. We also handle vector floats the same
4019 say, which is OK because they are not covered by the standard ABI. */
4020 info
->fpr_p
= (!cum
->gp_reg_found
4021 && cum
->arg_number
< 2
4023 || SCALAR_FLOAT_TYPE_P (type
)
4024 || VECTOR_FLOAT_TYPE_P (type
))
4025 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4026 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4027 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4032 /* Scalar, complex and vector floating-point types are passed in
4033 floating-point registers, as long as this is a named rather
4034 than a variable argument. */
4035 info
->fpr_p
= (named
4036 && (type
== 0 || FLOAT_TYPE_P (type
))
4037 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4038 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4039 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4040 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4042 /* ??? According to the ABI documentation, the real and imaginary
4043 parts of complex floats should be passed in individual registers.
4044 The real and imaginary parts of stack arguments are supposed
4045 to be contiguous and there should be an extra word of padding
4048 This has two problems. First, it makes it impossible to use a
4049 single "void *" va_list type, since register and stack arguments
4050 are passed differently. (At the time of writing, MIPSpro cannot
4051 handle complex float varargs correctly.) Second, it's unclear
4052 what should happen when there is only one register free.
4054 For now, we assume that named complex floats should go into FPRs
4055 if there are two FPRs free, otherwise they should be passed in the
4056 same way as a struct containing two floats. */
4058 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4059 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4061 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4062 info
->fpr_p
= false;
4072 /* See whether the argument has doubleword alignment. */
4073 doubleword_aligned_p
= FUNCTION_ARG_BOUNDARY (mode
, type
) > BITS_PER_WORD
;
4075 /* Set REG_OFFSET to the register count we're interested in.
4076 The EABI allocates the floating-point registers separately,
4077 but the other ABIs allocate them like integer registers. */
4078 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4082 /* Advance to an even register if the argument is doubleword-aligned. */
4083 if (doubleword_aligned_p
)
4084 info
->reg_offset
+= info
->reg_offset
& 1;
4086 /* Work out the offset of a stack argument. */
4087 info
->stack_offset
= cum
->stack_words
;
4088 if (doubleword_aligned_p
)
4089 info
->stack_offset
+= info
->stack_offset
& 1;
4091 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4093 /* Partition the argument between registers and stack. */
4094 info
->reg_words
= MIN (num_words
, max_regs
);
4095 info
->stack_words
= num_words
- info
->reg_words
;
4098 /* INFO describes a register argument that has the normal format for the
4099 argument's mode. Return the register it uses, assuming that FPRs are
4100 available if HARD_FLOAT_P. */
4103 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4105 if (!info
->fpr_p
|| !hard_float_p
)
4106 return GP_ARG_FIRST
+ info
->reg_offset
;
4107 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4108 /* In o32, the second argument is always passed in $f14
4109 for TARGET_DOUBLE_FLOAT, regardless of whether the
4110 first argument was a word or doubleword. */
4111 return FP_ARG_FIRST
+ 2;
4113 return FP_ARG_FIRST
+ info
->reg_offset
;
4116 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4119 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4121 return !TARGET_OLDABI
;
4124 /* Implement FUNCTION_ARG. */
4127 mips_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4128 tree type
, int named
)
4130 struct mips_arg_info info
;
4132 /* We will be called with a mode of VOIDmode after the last argument
4133 has been seen. Whatever we return will be passed to the call expander.
4134 If we need a MIPS16 fp_code, return a REG with the code stored as
4136 if (mode
== VOIDmode
)
4138 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4139 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4144 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4146 /* Return straight away if the whole argument is passed on the stack. */
4147 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4150 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4151 contains a double in its entirety, then that 64-bit chunk is passed
4152 in a floating-point register. */
4154 && TARGET_HARD_FLOAT
4157 && TREE_CODE (type
) == RECORD_TYPE
4158 && TYPE_SIZE_UNIT (type
)
4159 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4163 /* First check to see if there is any such field. */
4164 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4165 if (TREE_CODE (field
) == FIELD_DECL
4166 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4167 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4168 && host_integerp (bit_position (field
), 0)
4169 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4174 /* Now handle the special case by returning a PARALLEL
4175 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4176 chunks are passed in registers. */
4178 HOST_WIDE_INT bitpos
;
4181 /* assign_parms checks the mode of ENTRY_PARM, so we must
4182 use the actual mode here. */
4183 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4186 field
= TYPE_FIELDS (type
);
4187 for (i
= 0; i
< info
.reg_words
; i
++)
4191 for (; field
; field
= TREE_CHAIN (field
))
4192 if (TREE_CODE (field
) == FIELD_DECL
4193 && int_bit_position (field
) >= bitpos
)
4197 && int_bit_position (field
) == bitpos
4198 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4199 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4200 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4202 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4205 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4206 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4208 bitpos
+= BITS_PER_WORD
;
4214 /* Handle the n32/n64 conventions for passing complex floating-point
4215 arguments in FPR pairs. The real part goes in the lower register
4216 and the imaginary part goes in the upper register. */
4219 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4222 enum machine_mode inner
;
4225 inner
= GET_MODE_INNER (mode
);
4226 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4227 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4229 /* Real part in registers, imaginary part on stack. */
4230 gcc_assert (info
.stack_words
== info
.reg_words
);
4231 return gen_rtx_REG (inner
, regno
);
4235 gcc_assert (info
.stack_words
== 0);
4236 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4237 gen_rtx_REG (inner
, regno
),
4239 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4241 regno
+ info
.reg_words
/ 2),
4242 GEN_INT (GET_MODE_SIZE (inner
)));
4243 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4247 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4250 /* Implement FUNCTION_ARG_ADVANCE. */
4253 mips_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4254 tree type
, int named
)
4256 struct mips_arg_info info
;
4258 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4261 cum
->gp_reg_found
= true;
4263 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4264 an explanation of what this code does. It assumes that we're using
4265 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4267 if (cum
->arg_number
< 2 && info
.fpr_p
)
4268 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
4270 /* Advance the register count. This has the effect of setting
4271 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4272 argument required us to skip the final GPR and pass the whole
4273 argument on the stack. */
4274 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4275 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4276 else if (info
.reg_words
> 0)
4277 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
4279 /* Advance the stack word count. */
4280 if (info
.stack_words
> 0)
4281 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4286 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4289 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
4290 enum machine_mode mode
, tree type
, bool named
)
4292 struct mips_arg_info info
;
4294 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4295 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
4298 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4299 PARM_BOUNDARY bits of alignment, but will be given anything up
4300 to STACK_BOUNDARY bits if the type requires it. */
4303 mips_function_arg_boundary (enum machine_mode mode
, tree type
)
4305 unsigned int alignment
;
4307 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
4308 if (alignment
< PARM_BOUNDARY
)
4309 alignment
= PARM_BOUNDARY
;
4310 if (alignment
> STACK_BOUNDARY
)
4311 alignment
= STACK_BOUNDARY
;
4315 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4316 upward rather than downward. In other words, return true if the
4317 first byte of the stack slot has useful data, false if the last
4321 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
4323 /* On little-endian targets, the first byte of every stack argument
4324 is passed in the first byte of the stack slot. */
4325 if (!BYTES_BIG_ENDIAN
)
4328 /* Otherwise, integral types are padded downward: the last byte of a
4329 stack argument is passed in the last byte of the stack slot. */
4331 ? (INTEGRAL_TYPE_P (type
)
4332 || POINTER_TYPE_P (type
)
4333 || FIXED_POINT_TYPE_P (type
))
4334 : (SCALAR_INT_MODE_P (mode
)
4335 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
4338 /* Big-endian o64 pads floating-point arguments downward. */
4339 if (mips_abi
== ABI_O64
)
4340 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4343 /* Other types are padded upward for o32, o64, n32 and n64. */
4344 if (mips_abi
!= ABI_EABI
)
4347 /* Arguments smaller than a stack slot are padded downward. */
4348 if (mode
!= BLKmode
)
4349 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
4351 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
4354 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4355 if the least significant byte of the register has useful data. Return
4356 the opposite if the most significant byte does. */
4359 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
4361 /* No shifting is required for floating-point arguments. */
4362 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4363 return !BYTES_BIG_ENDIAN
;
4365 /* Otherwise, apply the same padding to register arguments as we do
4366 to stack arguments. */
4367 return mips_pad_arg_upward (mode
, type
);
4370 /* Return nonzero when an argument must be passed by reference. */
4373 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4374 enum machine_mode mode
, const_tree type
,
4375 bool named ATTRIBUTE_UNUSED
)
4377 if (mips_abi
== ABI_EABI
)
4381 /* ??? How should SCmode be handled? */
4382 if (mode
== DImode
|| mode
== DFmode
4383 || mode
== DQmode
|| mode
== UDQmode
4384 || mode
== DAmode
|| mode
== UDAmode
)
4387 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4388 return size
== -1 || size
> UNITS_PER_WORD
;
4392 /* If we have a variable-sized parameter, we have no choice. */
4393 return targetm
.calls
.must_pass_in_stack (mode
, type
);
4397 /* Implement TARGET_CALLEE_COPIES. */
4400 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4401 enum machine_mode mode ATTRIBUTE_UNUSED
,
4402 const_tree type ATTRIBUTE_UNUSED
, bool named
)
4404 return mips_abi
== ABI_EABI
&& named
;
4407 /* See whether VALTYPE is a record whose fields should be returned in
4408 floating-point registers. If so, return the number of fields and
4409 list them in FIELDS (which should have two elements). Return 0
4412 For n32 & n64, a structure with one or two fields is returned in
4413 floating-point registers as long as every field has a floating-point
4417 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
4425 if (TREE_CODE (valtype
) != RECORD_TYPE
)
4429 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= TREE_CHAIN (field
))
4431 if (TREE_CODE (field
) != FIELD_DECL
)
4434 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
4440 fields
[i
++] = field
;
4445 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4446 a value in the most significant part of $2/$3 if:
4448 - the target is big-endian;
4450 - the value has a structure or union type (we generalize this to
4451 cover aggregates from other languages too); and
4453 - the structure is not returned in floating-point registers. */
4456 mips_return_in_msb (const_tree valtype
)
4460 return (TARGET_NEWABI
4461 && TARGET_BIG_ENDIAN
4462 && AGGREGATE_TYPE_P (valtype
)
4463 && mips_fpr_return_fields (valtype
, fields
) == 0);
4466 /* Return true if the function return value MODE will get returned in a
4467 floating-point register. */
4470 mips_return_mode_in_fpr_p (enum machine_mode mode
)
4472 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4473 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
4474 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4475 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
4478 /* Return the representation of an FPR return register when the
4479 value being returned in FP_RETURN has mode VALUE_MODE and the
4480 return type itself has mode TYPE_MODE. On NewABI targets,
4481 the two modes may be different for structures like:
4483 struct __attribute__((packed)) foo { float f; }
4485 where we return the SFmode value of "f" in FP_RETURN, but where
4486 the structure itself has mode BLKmode. */
4489 mips_return_fpr_single (enum machine_mode type_mode
,
4490 enum machine_mode value_mode
)
4494 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
4495 if (type_mode
!= value_mode
)
4497 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
4498 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
4503 /* Return a composite value in a pair of floating-point registers.
4504 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4505 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4508 For n32 & n64, $f0 always holds the first value and $f2 the second.
4509 Otherwise the values are packed together as closely as possible. */
4512 mips_return_fpr_pair (enum machine_mode mode
,
4513 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
4514 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
4518 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
4519 return gen_rtx_PARALLEL
4522 gen_rtx_EXPR_LIST (VOIDmode
,
4523 gen_rtx_REG (mode1
, FP_RETURN
),
4525 gen_rtx_EXPR_LIST (VOIDmode
,
4526 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
4527 GEN_INT (offset2
))));
4531 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4532 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4533 VALTYPE is null and MODE is the mode of the return value. */
4536 mips_function_value (const_tree valtype
, enum machine_mode mode
)
4543 mode
= TYPE_MODE (valtype
);
4544 unsigned_p
= TYPE_UNSIGNED (valtype
);
4546 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4547 we must promote the mode just as PROMOTE_MODE does. */
4548 mode
= promote_mode (valtype
, mode
, &unsigned_p
, 1);
4550 /* Handle structures whose fields are returned in $f0/$f2. */
4551 switch (mips_fpr_return_fields (valtype
, fields
))
4554 return mips_return_fpr_single (mode
,
4555 TYPE_MODE (TREE_TYPE (fields
[0])));
4558 return mips_return_fpr_pair (mode
,
4559 TYPE_MODE (TREE_TYPE (fields
[0])),
4560 int_byte_position (fields
[0]),
4561 TYPE_MODE (TREE_TYPE (fields
[1])),
4562 int_byte_position (fields
[1]));
4565 /* If a value is passed in the most significant part of a register, see
4566 whether we have to round the mode up to a whole number of words. */
4567 if (mips_return_in_msb (valtype
))
4569 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
4570 if (size
% UNITS_PER_WORD
!= 0)
4572 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
4573 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
4577 /* For EABI, the class of return register depends entirely on MODE.
4578 For example, "struct { some_type x; }" and "union { some_type x; }"
4579 are returned in the same way as a bare "some_type" would be.
4580 Other ABIs only use FPRs for scalar, complex or vector types. */
4581 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
4582 return gen_rtx_REG (mode
, GP_RETURN
);
4587 /* Handle long doubles for n32 & n64. */
4589 return mips_return_fpr_pair (mode
,
4591 DImode
, GET_MODE_SIZE (mode
) / 2);
4593 if (mips_return_mode_in_fpr_p (mode
))
4595 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4596 return mips_return_fpr_pair (mode
,
4597 GET_MODE_INNER (mode
), 0,
4598 GET_MODE_INNER (mode
),
4599 GET_MODE_SIZE (mode
) / 2);
4601 return gen_rtx_REG (mode
, FP_RETURN
);
4605 return gen_rtx_REG (mode
, GP_RETURN
);
4608 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4609 all BLKmode objects are returned in memory. Under the n32, n64
4610 and embedded ABIs, small structures are returned in a register.
4611 Objects with varying size must still be returned in memory, of
4615 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
4617 return (TARGET_OLDABI
4618 ? TYPE_MODE (type
) == BLKmode
4619 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
4622 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
4625 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4626 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
4629 CUMULATIVE_ARGS local_cum
;
4630 int gp_saved
, fp_saved
;
4632 /* The caller has advanced CUM up to, but not beyond, the last named
4633 argument. Advance a local copy of CUM past the last "real" named
4634 argument, to find out how many registers are left over. */
4636 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, true);
4638 /* Found out how many registers we need to save. */
4639 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4640 fp_saved
= (EABI_FLOAT_VARARGS_P
4641 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4650 ptr
= plus_constant (virtual_incoming_args_rtx
,
4651 REG_PARM_STACK_SPACE (cfun
->decl
)
4652 - gp_saved
* UNITS_PER_WORD
);
4653 mem
= gen_frame_mem (BLKmode
, ptr
);
4654 set_mem_alias_set (mem
, get_varargs_alias_set ());
4656 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
4661 /* We can't use move_block_from_reg, because it will use
4663 enum machine_mode mode
;
4666 /* Set OFF to the offset from virtual_incoming_args_rtx of
4667 the first float register. The FP save area lies below
4668 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4669 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
4670 off
-= fp_saved
* UNITS_PER_FPREG
;
4672 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4674 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
4675 i
+= MAX_FPRS_PER_FMT
)
4679 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4680 mem
= gen_frame_mem (mode
, ptr
);
4681 set_mem_alias_set (mem
, get_varargs_alias_set ());
4682 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4683 off
+= UNITS_PER_HWFPVALUE
;
4687 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
4688 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
4689 + fp_saved
* UNITS_PER_FPREG
);
4692 /* Implement TARGET_BUILTIN_VA_LIST. */
4695 mips_build_builtin_va_list (void)
4697 if (EABI_FLOAT_VARARGS_P
)
4699 /* We keep 3 pointers, and two offsets.
4701 Two pointers are to the overflow area, which starts at the CFA.
4702 One of these is constant, for addressing into the GPR save area
4703 below it. The other is advanced up the stack through the
4706 The third pointer is to the bottom of the GPR save area.
4707 Since the FPR save area is just below it, we can address
4708 FPR slots off this pointer.
4710 We also keep two one-byte offsets, which are to be subtracted
4711 from the constant pointers to yield addresses in the GPR and
4712 FPR save areas. These are downcounted as float or non-float
4713 arguments are used, and when they get to zero, the argument
4714 must be obtained from the overflow region. */
4715 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
4718 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
4720 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4722 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4724 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4726 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4727 unsigned_char_type_node
);
4728 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4729 unsigned_char_type_node
);
4730 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4731 warn on every user file. */
4732 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
4733 array
= build_array_type (unsigned_char_type_node
,
4734 build_index_type (index
));
4735 f_res
= build_decl (FIELD_DECL
, get_identifier ("__reserved"), array
);
4737 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4738 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4739 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4740 DECL_FIELD_CONTEXT (f_goff
) = record
;
4741 DECL_FIELD_CONTEXT (f_foff
) = record
;
4742 DECL_FIELD_CONTEXT (f_res
) = record
;
4744 TYPE_FIELDS (record
) = f_ovfl
;
4745 TREE_CHAIN (f_ovfl
) = f_gtop
;
4746 TREE_CHAIN (f_gtop
) = f_ftop
;
4747 TREE_CHAIN (f_ftop
) = f_goff
;
4748 TREE_CHAIN (f_goff
) = f_foff
;
4749 TREE_CHAIN (f_foff
) = f_res
;
4751 layout_type (record
);
4754 else if (TARGET_IRIX
&& TARGET_IRIX6
)
4755 /* On IRIX 6, this type is 'char *'. */
4756 return build_pointer_type (char_type_node
);
4758 /* Otherwise, we use 'void *'. */
4759 return ptr_type_node
;
4762 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
4765 mips_va_start (tree valist
, rtx nextarg
)
4767 if (EABI_FLOAT_VARARGS_P
)
4769 const CUMULATIVE_ARGS
*cum
;
4770 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4771 tree ovfl
, gtop
, ftop
, goff
, foff
;
4773 int gpr_save_area_size
;
4774 int fpr_save_area_size
;
4777 cum
= ¤t_function_args_info
;
4779 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4781 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4783 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4784 f_gtop
= TREE_CHAIN (f_ovfl
);
4785 f_ftop
= TREE_CHAIN (f_gtop
);
4786 f_goff
= TREE_CHAIN (f_ftop
);
4787 f_foff
= TREE_CHAIN (f_goff
);
4789 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4791 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4793 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4795 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4797 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4800 /* Emit code to initialize OVFL, which points to the next varargs
4801 stack argument. CUM->STACK_WORDS gives the number of stack
4802 words used by named arguments. */
4803 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4804 if (cum
->stack_words
> 0)
4805 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4806 size_int (cum
->stack_words
* UNITS_PER_WORD
));
4807 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
4808 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4810 /* Emit code to initialize GTOP, the top of the GPR save area. */
4811 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4812 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gtop
), gtop
, t
);
4813 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4815 /* Emit code to initialize FTOP, the top of the FPR save area.
4816 This address is gpr_save_area_bytes below GTOP, rounded
4817 down to the next fp-aligned boundary. */
4818 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4819 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4820 fpr_offset
&= -UNITS_PER_FPVALUE
;
4822 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4823 size_int (-fpr_offset
));
4824 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ftop
), ftop
, t
);
4825 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4827 /* Emit code to initialize GOFF, the offset from GTOP of the
4828 next GPR argument. */
4829 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (goff
), goff
,
4830 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
4831 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4833 /* Likewise emit code to initialize FOFF, the offset from FTOP
4834 of the next FPR argument. */
4835 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (foff
), foff
,
4836 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
4837 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4841 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
4842 std_expand_builtin_va_start (valist
, nextarg
);
4846 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
4849 mips_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
4854 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4856 type
= build_pointer_type (type
);
4858 if (!EABI_FLOAT_VARARGS_P
)
4859 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
4862 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4863 tree ovfl
, top
, off
, align
;
4864 HOST_WIDE_INT size
, rsize
, osize
;
4867 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4868 f_gtop
= TREE_CHAIN (f_ovfl
);
4869 f_ftop
= TREE_CHAIN (f_gtop
);
4870 f_goff
= TREE_CHAIN (f_ftop
);
4871 f_foff
= TREE_CHAIN (f_goff
);
4875 TOP be the top of the GPR or FPR save area;
4876 OFF be the offset from TOP of the next register;
4877 ADDR_RTX be the address of the argument;
4878 SIZE be the number of bytes in the argument type;
4879 RSIZE be the number of bytes used to store the argument
4880 when it's in the register save area; and
4881 OSIZE be the number of bytes used to store it when it's
4882 in the stack overflow area.
4884 The code we want is:
4886 1: off &= -rsize; // round down
4889 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
4894 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
4895 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
4899 [1] and [9] can sometimes be optimized away. */
4901 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4903 size
= int_size_in_bytes (type
);
4905 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
4906 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
4908 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4910 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4913 /* When va_start saves FPR arguments to the stack, each slot
4914 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
4915 argument's precision. */
4916 rsize
= UNITS_PER_HWFPVALUE
;
4918 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4919 (= PARM_BOUNDARY bits). This can be different from RSIZE
4922 (1) On 32-bit targets when TYPE is a structure such as:
4924 struct s { float f; };
4926 Such structures are passed in paired FPRs, so RSIZE
4927 will be 8 bytes. However, the structure only takes
4928 up 4 bytes of memory, so OSIZE will only be 4.
4930 (2) In combinations such as -mgp64 -msingle-float
4931 -fshort-double. Doubles passed in registers will then take
4932 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
4933 stack take up UNITS_PER_WORD bytes. */
4934 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
4938 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4940 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4942 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4943 if (rsize
> UNITS_PER_WORD
)
4945 /* [1] Emit code for: off &= -rsize. */
4946 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
4947 build_int_cst (NULL_TREE
, -rsize
));
4948 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (off
), off
, t
);
4949 gimplify_and_add (t
, pre_p
);
4954 /* [2] Emit code to branch if off == 0. */
4955 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
4956 build_int_cst (TREE_TYPE (off
), 0));
4957 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
4959 /* [5] Emit code for: off -= rsize. We do this as a form of
4960 post-decrement not available to C. */
4961 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
4962 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
4964 /* [4] Emit code for:
4965 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
4966 t
= fold_convert (sizetype
, t
);
4967 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
4968 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (top
), top
, t
);
4969 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
4971 u
= size_int (rsize
- size
);
4972 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
4974 COND_EXPR_THEN (addr
) = t
;
4976 if (osize
> UNITS_PER_WORD
)
4978 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
4979 u
= size_int (osize
- 1);
4980 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
4981 t
= fold_convert (sizetype
, t
);
4982 u
= size_int (-osize
);
4983 t
= build2 (BIT_AND_EXPR
, sizetype
, t
, u
);
4984 t
= fold_convert (TREE_TYPE (ovfl
), t
);
4985 align
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
4990 /* [10, 11] Emit code for:
4991 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
4993 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
4994 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
4995 if (BYTES_BIG_ENDIAN
&& osize
> size
)
4997 u
= size_int (osize
- size
);
4998 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5001 /* String [9] and [10, 11] together. */
5003 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5004 COND_EXPR_ELSE (addr
) = t
;
5006 addr
= fold_convert (build_pointer_type (type
), addr
);
5007 addr
= build_va_arg_indirect_ref (addr
);
5011 addr
= build_va_arg_indirect_ref (addr
);
5016 /* A chained list of functions for which mips16_build_call_stub has already
5017 generated a stub. NAME is the name of the function and FP_RET_P is true
5018 if the function returns a value in floating-point registers. */
5019 struct mips16_stub
{
5020 struct mips16_stub
*next
;
5024 static struct mips16_stub
*mips16_stubs
;
5026 /* Return the two-character string that identifies floating-point
5027 return mode MODE in the name of a MIPS16 function stub. */
5030 mips16_call_stub_mode_suffix (enum machine_mode mode
)
5034 else if (mode
== DFmode
)
5036 else if (mode
== SCmode
)
5038 else if (mode
== DCmode
)
5040 else if (mode
== V2SFmode
)
5046 /* Write instructions to move a 32-bit value between general register
5047 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5048 from GPREG to FPREG and 'f' to move in the opposite direction. */
5051 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5053 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5054 reg_names
[gpreg
], reg_names
[fpreg
]);
5057 /* Likewise for 64-bit values. */
5060 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5063 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
5064 reg_names
[gpreg
], reg_names
[fpreg
]);
5065 else if (TARGET_FLOAT64
)
5067 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5068 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5069 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
5070 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
5074 /* Move the least-significant word. */
5075 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5076 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5077 /* ...then the most significant word. */
5078 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5079 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
5083 /* Write out code to move floating-point arguments into or out of
5084 general registers. FP_CODE is the code describing which arguments
5085 are present (see the comment above the definition of CUMULATIVE_ARGS
5086 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5089 mips_output_args_xfer (int fp_code
, char direction
)
5091 unsigned int gparg
, fparg
, f
;
5092 CUMULATIVE_ARGS cum
;
5094 /* This code only works for o32 and o64. */
5095 gcc_assert (TARGET_OLDABI
);
5097 mips_init_cumulative_args (&cum
, NULL
);
5099 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5101 enum machine_mode mode
;
5102 struct mips_arg_info info
;
5106 else if ((f
& 3) == 2)
5111 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
5112 gparg
= mips_arg_regno (&info
, false);
5113 fparg
= mips_arg_regno (&info
, true);
5116 mips_output_32bit_xfer (direction
, gparg
, fparg
);
5118 mips_output_64bit_xfer (direction
, gparg
, fparg
);
5120 mips_function_arg_advance (&cum
, mode
, NULL
, true);
5124 /* Write a MIPS16 stub for the current function. This stub is used
5125 for functions which take arguments in the floating-point registers.
5126 It is normal-mode code that moves the floating-point arguments
5127 into the general registers and then jumps to the MIPS16 code. */
5130 mips16_build_function_stub (void)
5132 const char *fnname
, *separator
;
5133 char *secname
, *stubname
;
5137 /* Create the name of the stub, and its unique section. */
5138 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5139 fnname
= targetm
.strip_name_encoding (fnname
);
5140 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
5141 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
5143 /* Build a decl for the stub. */
5144 stubdecl
= build_decl (FUNCTION_DECL
, get_identifier (stubname
),
5145 build_function_type (void_type_node
, NULL_TREE
));
5146 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5147 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
, void_type_node
);
5149 /* Output a comment. */
5150 fprintf (asm_out_file
, "\t# Stub function for %s (",
5151 current_function_name ());
5153 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
5155 fprintf (asm_out_file
, "%s%s", separator
,
5156 (f
& 3) == 1 ? "float" : "double");
5159 fprintf (asm_out_file
, ")\n");
5161 /* Write the preamble leading up to the function declaration. */
5162 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5163 switch_to_section (function_section (stubdecl
));
5164 ASM_OUTPUT_ALIGN (asm_out_file
,
5165 floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
5167 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5168 within a .ent, and we cannot emit another .ent. */
5169 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5171 fputs ("\t.ent\t", asm_out_file
);
5172 assemble_name (asm_out_file
, stubname
);
5173 fputs ("\n", asm_out_file
);
5176 /* Start the definition proper. */
5177 assemble_name (asm_out_file
, stubname
);
5178 fputs (":\n", asm_out_file
);
5180 /* Load the address of the MIPS16 function into $at. Do this first so
5181 that targets with coprocessor interlocks can use an MFC1 to fill the
5183 fprintf (asm_out_file
, "\t.set\tnoat\n");
5184 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
5185 assemble_name (asm_out_file
, fnname
);
5186 fprintf (asm_out_file
, "\n");
5188 /* Move the arguments from floating-point registers to general registers. */
5189 mips_output_args_xfer (current_function_args_info
.fp_code
, 'f');
5191 /* Jump to the MIPS16 function. */
5192 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
5193 fprintf (asm_out_file
, "\t.set\tat\n");
5195 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5197 fputs ("\t.end\t", asm_out_file
);
5198 assemble_name (asm_out_file
, stubname
);
5199 fputs ("\n", asm_out_file
);
5202 switch_to_section (function_section (current_function_decl
));
5205 /* The current function is a MIPS16 function that returns a value in an FPR.
5206 Copy the return value from its soft-float to its hard-float location.
5207 libgcc2 has special non-MIPS16 helper functions for each case. */
5210 mips16_copy_fpr_return_value (void)
5212 rtx fn
, insn
, arg
, call
;
5213 tree id
, return_type
;
5214 enum machine_mode return_mode
;
5216 return_type
= DECL_RESULT (current_function_decl
);
5217 return_mode
= DECL_MODE (return_type
);
5219 id
= get_identifier (ACONCAT (("__mips16_ret_",
5220 mips16_call_stub_mode_suffix (return_mode
),
5222 fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
5223 arg
= gen_rtx_REG (return_mode
, GP_RETURN
);
5224 call
= gen_call_value_internal (arg
, fn
, const0_rtx
);
5225 insn
= mips_emit_call_insn (call
, false);
5226 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), arg
);
5229 /* Consider building a stub for a MIPS16 call to function FN.
5230 RETVAL is the location of the return value, or null if this is
5231 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5232 arguments and FP_CODE is the code built by mips_function_arg;
5233 see the comment above CUMULATIVE_ARGS for details.
5235 If a stub was needed, emit the call and return the call insn itself.
5236 Return null otherwise.
5238 A stub is needed for calls to functions that, in normal mode,
5239 receive arguments in FPRs or return values in FPRs. The stub
5240 copies the arguments from their soft-float positions to their
5241 hard-float positions, calls the real function, then copies the
5242 return value from its hard-float position to its soft-float
5245 We emit a JAL to FN even when FN might need a stub. If FN turns out
5246 to be to a non-MIPS16 function, the linker automatically redirects
5247 the JAL to the stub, otherwise the JAL continues to call FN directly. */
5250 mips16_build_call_stub (rtx retval
, rtx fn
, rtx args_size
, int fp_code
)
5254 struct mips16_stub
*l
;
5257 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5258 we were invoked with the -msoft-float option. */
5259 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
5262 /* Figure out whether the value might come back in a floating-point
5264 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
5266 /* We don't need to do anything if there were no floating-point
5267 arguments and the value will not be returned in a floating-point
5269 if (fp_code
== 0 && !fp_ret_p
)
5272 /* We don't need to do anything if this is a call to a special
5273 MIPS16 support function. */
5274 if (GET_CODE (fn
) == SYMBOL_REF
5275 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
5278 /* This code will only work for o32 and o64 abis. The other ABI's
5279 require more sophisticated support. */
5280 gcc_assert (TARGET_OLDABI
);
5282 /* If we're calling via a function pointer, use one of the magic
5283 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5284 Each stub expects the function address to arrive in register $2. */
5285 if (GET_CODE (fn
) != SYMBOL_REF
)
5291 /* Create a SYMBOL_REF for the libgcc.a function. */
5293 sprintf (buf
, "__mips16_call_stub_%s_%d",
5294 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
5297 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
5298 id
= get_identifier (buf
);
5299 stub_fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
5301 /* Load the target function into $2. */
5302 mips_emit_move (gen_rtx_REG (Pmode
, 2), fn
);
5304 /* Emit the call. */
5305 if (retval
== NULL_RTX
)
5306 insn
= gen_call_internal (stub_fn
, args_size
);
5308 insn
= gen_call_value_internal (retval
, stub_fn
, args_size
);
5309 insn
= mips_emit_call_insn (insn
, false);
5311 /* Tell GCC that this call does indeed use the value of $2. */
5312 CALL_INSN_FUNCTION_USAGE (insn
) =
5313 gen_rtx_EXPR_LIST (VOIDmode
,
5314 gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 2)),
5315 CALL_INSN_FUNCTION_USAGE (insn
));
5317 /* If we are handling a floating-point return value, we need to
5318 save $18 in the function prologue. Putting a note on the
5319 call will mean that df_regs_ever_live_p ($18) will be true if the
5320 call is not eliminated, and we can check that in the prologue
5323 CALL_INSN_FUNCTION_USAGE (insn
) =
5324 gen_rtx_EXPR_LIST (VOIDmode
,
5325 gen_rtx_USE (VOIDmode
,
5326 gen_rtx_REG (word_mode
, 18)),
5327 CALL_INSN_FUNCTION_USAGE (insn
));
5332 /* We know the function we are going to call. If we have already
5333 built a stub, we don't need to do anything further. */
5334 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
5335 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
5336 if (strcmp (l
->name
, fnname
) == 0)
5341 const char *separator
;
5342 char *secname
, *stubname
;
5343 tree stubid
, stubdecl
;
5346 /* If the function does not return in FPRs, the special stub
5350 If the function does return in FPRs, the stub section is named
5351 .mips16.call.fp.FNNAME
5353 Build a decl for the stub. */
5354 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
5356 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
5358 stubid
= get_identifier (stubname
);
5359 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
5360 build_function_type (void_type_node
, NULL_TREE
));
5361 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5362 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
,
5365 /* Output a comment. */
5366 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
5368 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
5372 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5374 fprintf (asm_out_file
, "%s%s", separator
,
5375 (f
& 3) == 1 ? "float" : "double");
5378 fprintf (asm_out_file
, ")\n");
5380 /* Write the preamble leading up to the function declaration. */
5381 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5382 assemble_start_function (stubdecl
, stubname
);
5384 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5386 fputs ("\t.ent\t", asm_out_file
);
5387 assemble_name (asm_out_file
, stubname
);
5388 fputs ("\n", asm_out_file
);
5390 assemble_name (asm_out_file
, stubname
);
5391 fputs (":\n", asm_out_file
);
5396 /* Load the address of the MIPS16 function into $at. Do this
5397 first so that targets with coprocessor interlocks can use
5398 an MFC1 to fill the delay slot. */
5399 fprintf (asm_out_file
, "\t.set\tnoat\n");
5400 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
5404 /* Move the arguments from general registers to floating-point
5406 mips_output_args_xfer (fp_code
, 't');
5410 /* Jump to the previously-loaded address. */
5411 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
5412 fprintf (asm_out_file
, "\t.set\tat\n");
5416 /* Save the return address in $18 and call the non-MIPS16 function.
5417 The stub's caller knows that $18 might be clobbered, even though
5418 $18 is usually a call-saved register. */
5419 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
5420 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
5421 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
5423 /* Move the result from floating-point registers to
5424 general registers. */
5425 switch (GET_MODE (retval
))
5428 mips_output_32bit_xfer ('f', GP_RETURN
+ 1,
5429 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
5432 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
5433 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
5435 /* On 64-bit targets, complex floats are returned in
5436 a single GPR, such that "sd" on a suitably-aligned
5437 target would store the value correctly. */
5438 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
5439 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
5440 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
5441 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
5442 reg_names
[GP_RETURN
],
5443 reg_names
[GP_RETURN
],
5444 reg_names
[GP_RETURN
+ 1]);
5449 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
5450 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
5454 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
5460 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
5463 #ifdef ASM_DECLARE_FUNCTION_SIZE
5464 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
5467 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5469 fputs ("\t.end\t", asm_out_file
);
5470 assemble_name (asm_out_file
, stubname
);
5471 fputs ("\n", asm_out_file
);
5474 /* Record this stub. */
5475 l
= XNEW (struct mips16_stub
);
5476 l
->name
= xstrdup (fnname
);
5477 l
->fp_ret_p
= fp_ret_p
;
5478 l
->next
= mips16_stubs
;
5482 /* If we expect a floating-point return value, but we've built a
5483 stub which does not expect one, then we're in trouble. We can't
5484 use the existing stub, because it won't handle the floating-point
5485 value. We can't build a new stub, because the linker won't know
5486 which stub to use for the various calls in this object file.
5487 Fortunately, this case is illegal, since it means that a function
5488 was declared in two different ways in a single compilation. */
5489 if (fp_ret_p
&& !l
->fp_ret_p
)
5490 error ("cannot handle inconsistent calls to %qs", fnname
);
5492 if (retval
== NULL_RTX
)
5493 insn
= gen_call_internal_direct (fn
, args_size
);
5495 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
5496 insn
= mips_emit_call_insn (insn
, false);
5498 /* If we are calling a stub which handles a floating-point return
5499 value, we need to arrange to save $18 in the prologue. We do this
5500 by marking the function call as using the register. The prologue
5501 will later see that it is used, and emit code to save it. */
5503 CALL_INSN_FUNCTION_USAGE (insn
) =
5504 gen_rtx_EXPR_LIST (VOIDmode
,
5505 gen_rtx_USE (VOIDmode
, gen_rtx_REG (word_mode
, 18)),
5506 CALL_INSN_FUNCTION_USAGE (insn
));
5511 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5514 mips_ok_for_lazy_binding_p (rtx x
)
5516 return (TARGET_USE_GOT
5517 && GET_CODE (x
) == SYMBOL_REF
5518 && !mips_symbol_binds_local_p (x
));
5521 /* Load function address ADDR into register DEST. SIBCALL_P is true
5522 if the address is needed for a sibling call. Return true if we
5523 used an explicit lazy-binding sequence. */
5526 mips_load_call_address (rtx dest
, rtx addr
, bool sibcall_p
)
5528 /* If we're generating PIC, and this call is to a global function,
5529 try to allow its address to be resolved lazily. This isn't
5530 possible for sibcalls when $gp is call-saved because the value
5531 of $gp on entry to the stub would be our caller's gp, not ours. */
5532 if (TARGET_EXPLICIT_RELOCS
5533 && !(sibcall_p
&& TARGET_CALL_SAVED_GP
)
5534 && mips_ok_for_lazy_binding_p (addr
))
5536 rtx high
, lo_sum_symbol
;
5538 high
= mips_unspec_offset_high (dest
, pic_offset_table_rtx
,
5539 addr
, SYMBOL_GOTOFF_CALL
);
5540 lo_sum_symbol
= mips_unspec_address (addr
, SYMBOL_GOTOFF_CALL
);
5541 if (Pmode
== SImode
)
5542 emit_insn (gen_load_callsi (dest
, high
, lo_sum_symbol
));
5544 emit_insn (gen_load_calldi (dest
, high
, lo_sum_symbol
));
5549 mips_emit_move (dest
, addr
);
5554 /* Expand a "call", "sibcall", "call_value" or "sibcall_value" instruction.
5555 RESULT is where the result will go (null for "call"s and "sibcall"s),
5556 ADDR is the address of the function, ARGS_SIZE is the size of the
5557 arguments and AUX is the value passed to us by mips_function_arg.
5558 SIBCALL_P is true if we are expanding a sibling call, false if we're
5559 expanding a normal call.
5561 Return the call itself. */
5564 mips_expand_call (rtx result
, rtx addr
, rtx args_size
, rtx aux
, bool sibcall_p
)
5566 rtx orig_addr
, pattern
, insn
;
5571 if (!call_insn_operand (addr
, VOIDmode
))
5573 addr
= gen_reg_rtx (Pmode
);
5574 lazy_p
= mips_load_call_address (addr
, orig_addr
, sibcall_p
);
5577 insn
= mips16_build_call_stub (result
, addr
, args_size
,
5578 aux
== 0 ? 0 : (int) GET_MODE (aux
));
5581 gcc_assert (!sibcall_p
&& !lazy_p
);
5586 pattern
= (sibcall_p
5587 ? gen_sibcall_internal (addr
, args_size
)
5588 : gen_call_internal (addr
, args_size
));
5589 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
5591 /* Handle return values created by mips_return_fpr_pair. */
5594 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
5595 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
5598 ? gen_sibcall_value_multiple_internal (reg1
, addr
, args_size
, reg2
)
5599 : gen_call_value_multiple_internal (reg1
, addr
, args_size
, reg2
));
5603 /* Handle return values created by mips_return_fpr_single. */
5604 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
5605 result
= XEXP (XVECEXP (result
, 0, 0), 0);
5606 pattern
= (sibcall_p
5607 ? gen_sibcall_value_internal (result
, addr
, args_size
)
5608 : gen_call_value_internal (result
, addr
, args_size
));
5611 return mips_emit_call_insn (pattern
, lazy_p
);
5614 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5617 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
5619 if (!TARGET_SIBCALLS
)
5622 /* We can't do a sibcall if the called function is a MIPS16 function
5623 because there is no direct "jx" instruction equivalent to "jalx" to
5624 switch the ISA mode. We only care about cases where the sibling
5625 and normal calls would both be direct. */
5626 if (mips_use_mips16_mode_p (decl
)
5627 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
5630 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
5631 functions could be MIPS16 ones unless an attribute explicitly tells
5633 if (TARGET_INTERLINK_MIPS16
5635 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
5636 && !mips_nomips16_decl_p (decl
)
5637 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
5644 /* Emit code to move general operand SRC into condition-code
5645 register DEST given that SCRATCH is a scratch TFmode FPR.
5652 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
5655 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
5659 /* Change the source to SFmode. */
5661 src
= adjust_address (src
, SFmode
, 0);
5662 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
5663 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
5665 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
5666 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
5668 mips_emit_move (copy_rtx (fp1
), src
);
5669 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
5670 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
5673 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5674 Assume that the areas do not overlap. */
5677 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
5679 HOST_WIDE_INT offset
, delta
;
5680 unsigned HOST_WIDE_INT bits
;
5682 enum machine_mode mode
;
5685 /* Work out how many bits to move at a time. If both operands have
5686 half-word alignment, it is usually better to move in half words.
5687 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5688 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5689 Otherwise move word-sized chunks. */
5690 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
5691 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
5692 bits
= BITS_PER_WORD
/ 2;
5694 bits
= BITS_PER_WORD
;
5696 mode
= mode_for_size (bits
, MODE_INT
, 0);
5697 delta
= bits
/ BITS_PER_UNIT
;
5699 /* Allocate a buffer for the temporary registers. */
5700 regs
= alloca (sizeof (rtx
) * length
/ delta
);
5702 /* Load as many BITS-sized chunks as possible. Use a normal load if
5703 the source has enough alignment, otherwise use left/right pairs. */
5704 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
5706 regs
[i
] = gen_reg_rtx (mode
);
5707 if (MEM_ALIGN (src
) >= bits
)
5708 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
5711 rtx part
= adjust_address (src
, BLKmode
, offset
);
5712 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0))
5717 /* Copy the chunks to the destination. */
5718 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
5719 if (MEM_ALIGN (dest
) >= bits
)
5720 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
5723 rtx part
= adjust_address (dest
, BLKmode
, offset
);
5724 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
5728 /* Mop up any left-over bytes. */
5729 if (offset
< length
)
5731 src
= adjust_address (src
, BLKmode
, offset
);
5732 dest
= adjust_address (dest
, BLKmode
, offset
);
5733 move_by_pieces (dest
, src
, length
- offset
,
5734 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
5738 /* Helper function for doing a loop-based block operation on memory
5739 reference MEM. Each iteration of the loop will operate on LENGTH
5742 Create a new base register for use within the loop and point it to
5743 the start of MEM. Create a new memory reference that uses this
5744 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5747 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
5748 rtx
*loop_reg
, rtx
*loop_mem
)
5750 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
5752 /* Although the new mem does not refer to a known location,
5753 it does keep up to LENGTH bytes of alignment. */
5754 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
5755 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
5758 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
5759 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
5760 the memory regions do not overlap. */
5763 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
5764 HOST_WIDE_INT bytes_per_iter
)
5766 rtx label
, src_reg
, dest_reg
, final_src
;
5767 HOST_WIDE_INT leftover
;
5769 leftover
= length
% bytes_per_iter
;
5772 /* Create registers and memory references for use within the loop. */
5773 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
5774 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
5776 /* Calculate the value that SRC_REG should have after the last iteration
5778 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
5781 /* Emit the start of the loop. */
5782 label
= gen_label_rtx ();
5785 /* Emit the loop body. */
5786 mips_block_move_straight (dest
, src
, bytes_per_iter
);
5788 /* Move on to the next block. */
5789 mips_emit_move (src_reg
, plus_constant (src_reg
, bytes_per_iter
));
5790 mips_emit_move (dest_reg
, plus_constant (dest_reg
, bytes_per_iter
));
5792 /* Emit the loop condition. */
5793 if (Pmode
== DImode
)
5794 emit_insn (gen_cmpdi (src_reg
, final_src
));
5796 emit_insn (gen_cmpsi (src_reg
, final_src
));
5797 emit_jump_insn (gen_bne (label
));
5799 /* Mop up any left-over bytes. */
5801 mips_block_move_straight (dest
, src
, leftover
);
5804 /* Expand a movmemsi instruction, which copies LENGTH bytes from
5805 memory reference SRC to memory reference DEST. */
5808 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
5810 if (GET_CODE (length
) == CONST_INT
)
5812 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
5814 mips_block_move_straight (dest
, src
, INTVAL (length
));
5819 mips_block_move_loop (dest
, src
, INTVAL (length
),
5820 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
5827 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5830 mips_expand_synci_loop (rtx begin
, rtx end
)
5832 rtx inc
, label
, cmp
, cmp_result
;
5834 /* Load INC with the cache line size (rdhwr INC,$1). */
5835 inc
= gen_reg_rtx (SImode
);
5836 emit_insn (gen_rdhwr (inc
, const1_rtx
));
5838 /* Loop back to here. */
5839 label
= gen_label_rtx ();
5842 emit_insn (gen_synci (begin
));
5844 cmp
= gen_reg_rtx (Pmode
);
5845 mips_emit_binary (GTU
, cmp
, begin
, end
);
5847 mips_emit_binary (PLUS
, begin
, begin
, inc
);
5849 cmp_result
= gen_rtx_EQ (VOIDmode
, cmp
, const0_rtx
);
5850 emit_jump_insn (gen_condjump (cmp_result
, label
));
5853 /* Return true if it is possible to use left/right accesses for a
5854 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5855 returning true, update *OP, *LEFT and *RIGHT as follows:
5857 *OP is a BLKmode reference to the whole field.
5859 *LEFT is a QImode reference to the first byte if big endian or
5860 the last byte if little endian. This address can be used in the
5861 left-side instructions (LWL, SWL, LDL, SDL).
5863 *RIGHT is a QImode reference to the opposite end of the field and
5864 can be used in the patterning right-side instruction. */
5867 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
5868 rtx
*left
, rtx
*right
)
5872 /* Check that the operand really is a MEM. Not all the extv and
5873 extzv predicates are checked. */
5877 /* Check that the size is valid. */
5878 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
5881 /* We can only access byte-aligned values. Since we are always passed
5882 a reference to the first byte of the field, it is not necessary to
5883 do anything with BITPOS after this check. */
5884 if (bitpos
% BITS_PER_UNIT
!= 0)
5887 /* Reject aligned bitfields: we want to use a normal load or store
5888 instead of a left/right pair. */
5889 if (MEM_ALIGN (*op
) >= width
)
5892 /* Adjust *OP to refer to the whole field. This also has the effect
5893 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
5894 *op
= adjust_address (*op
, BLKmode
, 0);
5895 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
5897 /* Get references to both ends of the field. We deliberately don't
5898 use the original QImode *OP for FIRST since the new BLKmode one
5899 might have a simpler address. */
5900 first
= adjust_address (*op
, QImode
, 0);
5901 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
5903 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
5904 correspond to the MSB and RIGHT to the LSB. */
5905 if (TARGET_BIG_ENDIAN
)
5906 *left
= first
, *right
= last
;
5908 *left
= last
, *right
= first
;
5913 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
5914 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
5915 the operation is the equivalent of:
5917 (set DEST (*_extract SRC WIDTH BITPOS))
5919 Return true on success. */
5922 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
5923 HOST_WIDE_INT bitpos
)
5925 rtx left
, right
, temp
;
5927 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
5928 be a paradoxical word_mode subreg. This is the only case in which
5929 we allow the destination to be larger than the source. */
5930 if (GET_CODE (dest
) == SUBREG
5931 && GET_MODE (dest
) == DImode
5932 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
5933 dest
= SUBREG_REG (dest
);
5935 /* After the above adjustment, the destination must be the same
5936 width as the source. */
5937 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
5940 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
5943 temp
= gen_reg_rtx (GET_MODE (dest
));
5944 if (GET_MODE (dest
) == DImode
)
5946 emit_insn (gen_mov_ldl (temp
, src
, left
));
5947 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
5951 emit_insn (gen_mov_lwl (temp
, src
, left
));
5952 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
5957 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
5958 BITPOS and SRC are the operands passed to the expander; the operation
5959 is the equivalent of:
5961 (set (zero_extract DEST WIDTH BITPOS) SRC)
5963 Return true on success. */
5966 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
5967 HOST_WIDE_INT bitpos
)
5970 enum machine_mode mode
;
5972 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
5975 mode
= mode_for_size (width
, MODE_INT
, 0);
5976 src
= gen_lowpart (mode
, src
);
5979 emit_insn (gen_mov_sdl (dest
, src
, left
));
5980 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
5984 emit_insn (gen_mov_swl (dest
, src
, left
));
5985 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
5990 /* Return true if X is a MEM with the same size as MODE. */
5993 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
6000 size
= MEM_SIZE (x
);
6001 return size
&& INTVAL (size
) == GET_MODE_SIZE (mode
);
6004 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6005 source of an "ext" instruction or the destination of an "ins"
6006 instruction. OP must be a register operand and the following
6007 conditions must hold:
6009 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6010 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6011 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6013 Also reject lengths equal to a word as they are better handled
6014 by the move patterns. */
6017 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
6019 if (!ISA_HAS_EXT_INS
6020 || !register_operand (op
, VOIDmode
)
6021 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
6024 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
6027 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
6033 /* Return true if -msplit-addresses is selected and should be honored.
6035 -msplit-addresses is a half-way house between explicit relocations
6036 and the traditional assembler macros. It can split absolute 32-bit
6037 symbolic constants into a high/lo_sum pair but uses macros for other
6040 Like explicit relocation support for REL targets, it relies
6041 on GNU extensions in the assembler and the linker.
6043 Although this code should work for -O0, it has traditionally
6044 been treated as an optimization. */
6047 mips_split_addresses_p (void)
6049 return (TARGET_SPLIT_ADDRESSES
6053 && !ABI_HAS_64BIT_SYMBOLS
);
6056 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6059 mips_init_relocs (void)
6061 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
6062 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
6063 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
6065 if (ABI_HAS_64BIT_SYMBOLS
)
6067 if (TARGET_EXPLICIT_RELOCS
)
6069 mips_split_p
[SYMBOL_64_HIGH
] = true;
6070 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
6071 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
6073 mips_split_p
[SYMBOL_64_MID
] = true;
6074 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
6075 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
6077 mips_split_p
[SYMBOL_64_LOW
] = true;
6078 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
6079 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
6081 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6082 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6087 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses_p () || TARGET_MIPS16
)
6089 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6090 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
6091 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6093 mips_lo_relocs
[SYMBOL_32_HIGH
] = "%hi(";
6099 /* The high part is provided by a pseudo copy of $gp. */
6100 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
6101 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
6104 if (TARGET_EXPLICIT_RELOCS
)
6106 /* Small data constants are kept whole until after reload,
6107 then lowered by mips_rewrite_small_data. */
6108 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
6110 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
6113 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
6114 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
6118 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
6119 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
6124 /* The HIGH and LO_SUM are matched by special .md patterns. */
6125 mips_split_p
[SYMBOL_GOT_DISP
] = true;
6127 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
6128 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
6129 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
6131 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
6132 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
6133 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
6138 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
6140 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
6141 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
6147 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
6148 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
6149 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
6152 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
6153 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
6155 mips_split_p
[SYMBOL_DTPREL
] = true;
6156 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
6157 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
6159 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
6161 mips_split_p
[SYMBOL_TPREL
] = true;
6162 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
6163 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
6165 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
6168 /* If OP is an UNSPEC address, return the address to which it refers,
6169 otherwise return OP itself. */
6172 mips_strip_unspec_address (rtx op
)
6176 split_const (op
, &base
, &offset
);
6177 if (UNSPEC_ADDRESS_P (base
))
6178 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
6182 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6183 in context CONTEXT. RELOCS is the array of relocations to use. */
6186 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
6187 const char **relocs
)
6189 enum mips_symbol_type symbol_type
;
6192 symbol_type
= mips_classify_symbolic_expression (op
, context
);
6193 gcc_assert (relocs
[symbol_type
]);
6195 fputs (relocs
[symbol_type
], file
);
6196 output_addr_const (file
, mips_strip_unspec_address (op
));
6197 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
6202 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6203 The punctuation characters are:
6205 '(' Start a nested ".set noreorder" block.
6206 ')' End a nested ".set noreorder" block.
6207 '[' Start a nested ".set noat" block.
6208 ']' End a nested ".set noat" block.
6209 '<' Start a nested ".set nomacro" block.
6210 '>' End a nested ".set nomacro" block.
6211 '*' Behave like %(%< if generating a delayed-branch sequence.
6212 '#' Print a nop if in a ".set noreorder" block.
6213 '/' Like '#', but do nothing within a delayed-branch sequence.
6214 '?' Print "l" if mips_branch_likely is true
6215 '.' Print the name of the register with a hard-wired zero (zero or $0).
6216 '@' Print the name of the assembler temporary register (at or $1).
6217 '^' Print the name of the pic call-through register (t9 or $25).
6218 '+' Print the name of the gp register (usually gp or $28).
6219 '$' Print the name of the stack pointer register (sp or $29).
6220 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6221 '-' Print ".set pop" under the same conditions for '|'.
6223 See also mips_init_print_operand_pucnt. */
6226 mips_print_operand_punctuation (FILE *file
, int ch
)
6231 if (set_noreorder
++ == 0)
6232 fputs (".set\tnoreorder\n\t", file
);
6236 gcc_assert (set_noreorder
> 0);
6237 if (--set_noreorder
== 0)
6238 fputs ("\n\t.set\treorder", file
);
6242 if (set_noat
++ == 0)
6243 fputs (".set\tnoat\n\t", file
);
6247 gcc_assert (set_noat
> 0);
6248 if (--set_noat
== 0)
6249 fputs ("\n\t.set\tat", file
);
6253 if (set_nomacro
++ == 0)
6254 fputs (".set\tnomacro\n\t", file
);
6258 gcc_assert (set_nomacro
> 0);
6259 if (--set_nomacro
== 0)
6260 fputs ("\n\t.set\tmacro", file
);
6264 if (final_sequence
!= 0)
6266 mips_print_operand_punctuation (file
, '(');
6267 mips_print_operand_punctuation (file
, '<');
6272 if (set_noreorder
!= 0)
6273 fputs ("\n\tnop", file
);
6277 /* Print an extra newline so that the delayed insn is separated
6278 from the following ones. This looks neater and is consistent
6279 with non-nop delayed sequences. */
6280 if (set_noreorder
!= 0 && final_sequence
== 0)
6281 fputs ("\n\tnop\n", file
);
6285 if (mips_branch_likely
)
6290 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
6294 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
6298 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
6302 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
6306 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
6311 fputs (".set\tpush\n\t.set\tmips2\n\t", file
);
6316 fputs ("\n\t.set\tpop", file
);
6325 /* Initialize mips_print_operand_punct. */
6328 mips_init_print_operand_punct (void)
6332 for (p
= "()[]<>*#/?.@^+$|-"; *p
; p
++)
6333 mips_print_operand_punct
[(unsigned char) *p
] = true;
6336 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6337 associated with condition CODE. Print the condition part of the
6341 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
6355 /* Conveniently, the MIPS names for these conditions are the same
6356 as their RTL equivalents. */
6357 fputs (GET_RTX_NAME (code
), file
);
6361 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
6366 /* Likewise floating-point branches. */
6369 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
6374 fputs ("c1f", file
);
6378 fputs ("c1t", file
);
6382 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
6387 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6389 'X' Print CONST_INT OP in hexadecimal format.
6390 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6391 'd' Print CONST_INT OP in decimal.
6392 'h' Print the high-part relocation associated with OP, after stripping
6394 'R' Print the low-part relocation associated with OP.
6395 'C' Print the integer branch condition for comparison OP.
6396 'N' Print the inverse of the integer branch condition for comparison OP.
6397 'F' Print the FPU branch condition for comparison OP.
6398 'W' Print the inverse of the FPU branch condition for comparison OP.
6399 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6400 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6401 't' Like 'T', but with the EQ/NE cases reversed
6402 'Y' Print mips_fp_conditions[INTVAL (OP)]
6403 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6404 'q' Print a DSP accumulator register.
6405 'D' Print the second part of a double-word register or memory operand.
6406 'L' Print the low-order register in a double-word register operand.
6407 'M' Print high-order register in a double-word register operand.
6408 'z' Print $0 if OP is zero, otherwise print OP normally. */
6411 mips_print_operand (FILE *file
, rtx op
, int letter
)
6415 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
6417 mips_print_operand_punctuation (file
, letter
);
6422 code
= GET_CODE (op
);
6427 if (GET_CODE (op
) == CONST_INT
)
6428 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
6430 output_operand_lossage ("invalid use of '%%%c'", letter
);
6434 if (GET_CODE (op
) == CONST_INT
)
6435 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
6437 output_operand_lossage ("invalid use of '%%%c'", letter
);
6441 if (GET_CODE (op
) == CONST_INT
)
6442 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
6444 output_operand_lossage ("invalid use of '%%%c'", letter
);
6450 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
6454 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
6458 mips_print_int_branch_condition (file
, code
, letter
);
6462 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
6466 mips_print_float_branch_condition (file
, code
, letter
);
6470 mips_print_float_branch_condition (file
, reverse_condition (code
),
6477 int truth
= (code
== NE
) == (letter
== 'T');
6478 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
6483 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
6484 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
6486 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6493 mips_print_operand (file
, op
, 0);
6499 if (code
== REG
&& MD_REG_P (REGNO (op
)))
6500 fprintf (file
, "$ac0");
6501 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
6502 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
6504 output_operand_lossage ("invalid use of '%%%c'", letter
);
6512 unsigned int regno
= REGNO (op
);
6513 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
6514 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
6517 fprintf (file
, "%s", reg_names
[regno
]);
6523 output_address (plus_constant (XEXP (op
, 0), 4));
6525 output_address (XEXP (op
, 0));
6529 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
6530 fputs (reg_names
[GP_REG_FIRST
], file
);
6531 else if (CONST_GP_P (op
))
6532 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
6534 output_addr_const (file
, mips_strip_unspec_address (op
));
6540 /* Output address operand X to FILE. */
6543 mips_print_operand_address (FILE *file
, rtx x
)
6545 struct mips_address_info addr
;
6547 if (mips_classify_address (&addr
, x
, word_mode
, true))
6551 mips_print_operand (file
, addr
.offset
, 0);
6552 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
6555 case ADDRESS_LO_SUM
:
6556 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
6558 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
6561 case ADDRESS_CONST_INT
:
6562 output_addr_const (file
, x
);
6563 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
6566 case ADDRESS_SYMBOLIC
:
6567 output_addr_const (file
, mips_strip_unspec_address (x
));
6573 /* Implement TARGET_ENCODE_SECTION_INFO. */
6576 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
6578 default_encode_section_info (decl
, rtl
, first
);
6580 if (TREE_CODE (decl
) == FUNCTION_DECL
)
6582 rtx symbol
= XEXP (rtl
, 0);
6583 tree type
= TREE_TYPE (decl
);
6585 /* Encode whether the symbol is short or long. */
6586 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
6587 || mips_far_type_p (type
))
6588 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
6592 /* Implement TARGET_SELECT_RTX_SECTION. */
6595 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
6596 unsigned HOST_WIDE_INT align
)
6598 /* ??? Consider using mergeable small data sections. */
6599 if (mips_rtx_constant_in_small_data_p (mode
))
6600 return get_named_section (NULL
, ".sdata", 0);
6602 return default_elf_select_rtx_section (mode
, x
, align
);
6605 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6607 The complication here is that, with the combination TARGET_ABICALLS
6608 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6609 therefore not be included in the read-only part of a DSO. Handle such
6610 cases by selecting a normal data section instead of a read-only one.
6611 The logic apes that in default_function_rodata_section. */
6614 mips_function_rodata_section (tree decl
)
6616 if (!TARGET_ABICALLS
|| TARGET_GPWORD
)
6617 return default_function_rodata_section (decl
);
6619 if (decl
&& DECL_SECTION_NAME (decl
))
6621 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
6622 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
6624 char *rname
= ASTRDUP (name
);
6626 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
6628 else if (flag_function_sections
6629 && flag_data_sections
6630 && strncmp (name
, ".text.", 6) == 0)
6632 char *rname
= ASTRDUP (name
);
6633 memcpy (rname
+ 1, "data", 4);
6634 return get_section (rname
, SECTION_WRITE
, decl
);
6637 return data_section
;
6640 /* Implement TARGET_IN_SMALL_DATA_P. */
6643 mips_in_small_data_p (const_tree decl
)
6645 unsigned HOST_WIDE_INT size
;
6647 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
6650 /* We don't yet generate small-data references for -mabicalls
6651 or VxWorks RTP code. See the related -G handling in
6652 mips_override_options. */
6653 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
6656 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
6660 /* Reject anything that isn't in a known small-data section. */
6661 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
6662 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
6665 /* If a symbol is defined externally, the assembler will use the
6666 usual -G rules when deciding how to implement macros. */
6667 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
6670 else if (TARGET_EMBEDDED_DATA
)
6672 /* Don't put constants into the small data section: we want them
6673 to be in ROM rather than RAM. */
6674 if (TREE_CODE (decl
) != VAR_DECL
)
6677 if (TREE_READONLY (decl
)
6678 && !TREE_SIDE_EFFECTS (decl
)
6679 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
6683 /* Enforce -mlocal-sdata. */
6684 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
6687 /* Enforce -mextern-sdata. */
6688 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
6690 if (DECL_EXTERNAL (decl
))
6692 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
6696 /* We have traditionally not treated zero-sized objects as small data,
6697 so this is now effectively part of the ABI. */
6698 size
= int_size_in_bytes (TREE_TYPE (decl
));
6699 return size
> 0 && size
<= mips_small_data_threshold
;
6702 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6703 anchors for small data: the GP register acts as an anchor in that
6704 case. We also don't want to use them for PC-relative accesses,
6705 where the PC acts as an anchor. */
6708 mips_use_anchors_for_symbol_p (const_rtx symbol
)
6710 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
6712 case SYMBOL_PC_RELATIVE
:
6713 case SYMBOL_GP_RELATIVE
:
6717 return default_use_anchors_for_symbol_p (symbol
);
6721 /* The MIPS debug format wants all automatic variables and arguments
6722 to be in terms of the virtual frame pointer (stack pointer before
6723 any adjustment in the function), while the MIPS 3.0 linker wants
6724 the frame pointer to be the stack pointer after the initial
6725 adjustment. So, we do the adjustment here. The arg pointer (which
6726 is eliminated) points to the virtual frame pointer, while the frame
6727 pointer (which may be eliminated) points to the stack pointer after
6728 the initial adjustments. */
6731 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
6733 rtx offset2
= const0_rtx
;
6734 rtx reg
= eliminate_constant_term (addr
, &offset2
);
6737 offset
= INTVAL (offset2
);
6739 if (reg
== stack_pointer_rtx
6740 || reg
== frame_pointer_rtx
6741 || reg
== hard_frame_pointer_rtx
)
6743 offset
-= cfun
->machine
->frame
.total_size
;
6744 if (reg
== hard_frame_pointer_rtx
)
6745 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
6748 /* sdbout_parms does not want this to crash for unrecognized cases. */
6750 else if (reg
!= arg_pointer_rtx
)
6751 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6758 /* Implement ASM_OUTPUT_EXTERNAL. */
6761 mips_output_external (FILE *file
, tree decl
, const char *name
)
6763 default_elf_asm_output_external (file
, decl
, name
);
6765 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6766 set in order to avoid putting out names that are never really
6768 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
6770 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
6772 /* When using assembler macros, emit .extern directives for
6773 all small-data externs so that the assembler knows how
6776 In most cases it would be safe (though pointless) to emit
6777 .externs for other symbols too. One exception is when an
6778 object is within the -G limit but declared by the user to
6779 be in a section other than .sbss or .sdata. */
6780 fputs ("\t.extern\t", file
);
6781 assemble_name (file
, name
);
6782 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
6783 int_size_in_bytes (TREE_TYPE (decl
)));
6785 else if (TARGET_IRIX
6786 && mips_abi
== ABI_32
6787 && TREE_CODE (decl
) == FUNCTION_DECL
)
6789 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6790 `.global name .text' directive for every used but
6791 undefined function. If we don't, the linker may perform
6792 an optimization (skipping over the insns that set $gp)
6793 when it is unsafe. */
6794 fputs ("\t.globl ", file
);
6795 assemble_name (file
, name
);
6796 fputs (" .text\n", file
);
6801 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
6804 mips_output_filename (FILE *stream
, const char *name
)
6806 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6808 if (write_symbols
== DWARF2_DEBUG
)
6810 else if (mips_output_filename_first_time
)
6812 mips_output_filename_first_time
= 0;
6813 num_source_filenames
+= 1;
6814 current_function_file
= name
;
6815 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
6816 output_quoted_string (stream
, name
);
6817 putc ('\n', stream
);
6819 /* If we are emitting stabs, let dbxout.c handle this (except for
6820 the mips_output_filename_first_time case). */
6821 else if (write_symbols
== DBX_DEBUG
)
6823 else if (name
!= current_function_file
6824 && strcmp (name
, current_function_file
) != 0)
6826 num_source_filenames
+= 1;
6827 current_function_file
= name
;
6828 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
6829 output_quoted_string (stream
, name
);
6830 putc ('\n', stream
);
6834 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
6836 static void ATTRIBUTE_UNUSED
6837 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6842 fputs ("\t.dtprelword\t", file
);
6846 fputs ("\t.dtpreldword\t", file
);
6852 output_addr_const (file
, x
);
6853 fputs ("+0x8000", file
);
6856 /* Implement TARGET_DWARF_REGISTER_SPAN. */
6859 mips_dwarf_register_span (rtx reg
)
6862 enum machine_mode mode
;
6864 /* By default, GCC maps increasing register numbers to increasing
6865 memory locations, but paired FPRs are always little-endian,
6866 regardless of the prevailing endianness. */
6867 mode
= GET_MODE (reg
);
6868 if (FP_REG_P (REGNO (reg
))
6869 && TARGET_BIG_ENDIAN
6870 && MAX_FPRS_PER_FMT
> 1
6871 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
6873 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
6874 high
= mips_subword (reg
, true);
6875 low
= mips_subword (reg
, false);
6876 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
6882 /* Implement ASM_OUTPUT_ASCII. */
6885 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
6891 fprintf (stream
, "\t.ascii\t\"");
6892 for (i
= 0; i
< len
; i
++)
6896 c
= (unsigned char) string
[i
];
6899 if (c
== '\\' || c
== '\"')
6901 putc ('\\', stream
);
6909 fprintf (stream
, "\\%03o", c
);
6913 if (cur_pos
> 72 && i
+1 < len
)
6916 fprintf (stream
, "\"\n\t.ascii\t\"");
6919 fprintf (stream
, "\"\n");
6922 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6923 macros, mark the symbol as written so that mips_asm_output_external
6924 won't emit an .extern for it. STREAM is the output file, NAME is the
6925 name of the symbol, INIT_STRING is the string that should be written
6926 before the symbol and FINAL_STRING is the string that should be
6927 written after it. FINAL_STRING is a printf format that consumes the
6928 remaining arguments. */
6931 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
6932 const char *final_string
, ...)
6936 fputs (init_string
, stream
);
6937 assemble_name (stream
, name
);
6938 va_start (ap
, final_string
);
6939 vfprintf (stream
, final_string
, ap
);
6942 if (!TARGET_EXPLICIT_RELOCS
)
6944 tree name_tree
= get_identifier (name
);
6945 TREE_ASM_WRITTEN (name_tree
) = 1;
6949 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6950 NAME is the name of the object and ALIGN is the required alignment
6951 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6952 alignment argument. */
6955 mips_declare_common_object (FILE *stream
, const char *name
,
6956 const char *init_string
,
6957 unsigned HOST_WIDE_INT size
,
6958 unsigned int align
, bool takes_alignment_p
)
6960 if (!takes_alignment_p
)
6962 size
+= (align
/ BITS_PER_UNIT
) - 1;
6963 size
-= size
% (align
/ BITS_PER_UNIT
);
6964 mips_declare_object (stream
, name
, init_string
,
6965 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
6968 mips_declare_object (stream
, name
, init_string
,
6969 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
6970 size
, align
/ BITS_PER_UNIT
);
6973 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
6974 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6977 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
6978 unsigned HOST_WIDE_INT size
,
6981 /* If the target wants uninitialized const declarations in
6982 .rdata then don't put them in .comm. */
6983 if (TARGET_EMBEDDED_DATA
6984 && TARGET_UNINIT_CONST_IN_RODATA
6985 && TREE_CODE (decl
) == VAR_DECL
6986 && TREE_READONLY (decl
)
6987 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
6989 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
6990 targetm
.asm_out
.globalize_label (stream
, name
);
6992 switch_to_section (readonly_data_section
);
6993 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
6994 mips_declare_object (stream
, name
, "",
6995 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
6999 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
7003 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7004 extern int size_directive_output
;
7006 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7007 definitions except that it uses mips_declare_object to emit the label. */
7010 mips_declare_object_name (FILE *stream
, const char *name
,
7011 tree decl ATTRIBUTE_UNUSED
)
7013 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7014 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
7017 size_directive_output
= 0;
7018 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
7022 size_directive_output
= 1;
7023 size
= int_size_in_bytes (TREE_TYPE (decl
));
7024 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7027 mips_declare_object (stream
, name
, "", ":\n");
7030 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7033 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
7037 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
7038 if (!flag_inhibit_size_directive
7039 && DECL_SIZE (decl
) != 0
7042 && DECL_INITIAL (decl
) == error_mark_node
7043 && !size_directive_output
)
7047 size_directive_output
= 1;
7048 size
= int_size_in_bytes (TREE_TYPE (decl
));
7049 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7054 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7055 with the current ABI. */
7058 mips_mdebug_abi_name (void)
7071 return TARGET_64BIT
? "eabi64" : "eabi32";
7077 /* Implement TARGET_ASM_FILE_START. */
7080 mips_file_start (void)
7082 default_file_start ();
7084 /* Generate a special section to describe the ABI switches used to
7085 produce the resultant binary. This is unnecessary on IRIX and
7086 causes unwanted warnings from the native linker. */
7089 /* Record the ABI itself. Modern versions of binutils encode
7090 this information in the ELF header flags, but GDB needs the
7091 information in order to correctly debug binaries produced by
7092 older binutils. See the function mips_gdbarch_init in
7094 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
7095 mips_mdebug_abi_name ());
7097 /* There is no ELF header flag to distinguish long32 forms of the
7098 EABI from long64 forms. Emit a special section to help tools
7099 such as GDB. Do the same for o64, which is sometimes used with
7101 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
7102 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
7103 "\t.previous\n", TARGET_LONG64
? 64 : 32);
7105 #ifdef HAVE_AS_GNU_ATTRIBUTE
7106 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
7107 (TARGET_HARD_FLOAT_ABI
7108 ? (TARGET_DOUBLE_FLOAT
7109 ? ((!TARGET_64BIT
&& TARGET_FLOAT64
) ? 4 : 1) : 2) : 3));
7113 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7114 if (TARGET_ABICALLS
)
7115 fprintf (asm_out_file
, "\t.abicalls\n");
7117 if (flag_verbose_asm
)
7118 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7120 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
7123 /* Make the last instruction frame-related and note that it performs
7124 the operation described by FRAME_PATTERN. */
7127 mips_set_frame_expr (rtx frame_pattern
)
7131 insn
= get_last_insn ();
7132 RTX_FRAME_RELATED_P (insn
) = 1;
7133 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7138 /* Return a frame-related rtx that stores REG at MEM.
7139 REG must be a single register. */
7142 mips_frame_set (rtx mem
, rtx reg
)
7146 /* If we're saving the return address register and the DWARF return
7147 address column differs from the hard register number, adjust the
7148 note reg to refer to the former. */
7149 if (REGNO (reg
) == GP_REG_FIRST
+ 31
7150 && DWARF_FRAME_RETURN_COLUMN
!= GP_REG_FIRST
+ 31)
7151 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
7153 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
7154 RTX_FRAME_RELATED_P (set
) = 1;
7159 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7160 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7161 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7162 static const unsigned char mips16e_s2_s8_regs
[] = {
7163 30, 23, 22, 21, 20, 19, 18
7165 static const unsigned char mips16e_a0_a3_regs
[] = {
7169 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7170 ordered from the uppermost in memory to the lowest in memory. */
7171 static const unsigned char mips16e_save_restore_regs
[] = {
7172 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7175 /* Return the index of the lowest X in the range [0, SIZE) for which
7176 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7179 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
7184 for (i
= 0; i
< size
; i
++)
7185 if (BITSET_P (mask
, regs
[i
]))
7191 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7192 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7193 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7194 is true for all indexes (X, SIZE). */
7197 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
7198 unsigned int size
, unsigned int *num_regs_ptr
)
7202 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
7203 for (i
++; i
< size
; i
++)
7204 if (!BITSET_P (*mask_ptr
, regs
[i
]))
7207 *mask_ptr
|= 1 << regs
[i
];
7211 /* Return a simplified form of X using the register values in REG_VALUES.
7212 REG_VALUES[R] is the last value assigned to hard register R, or null
7213 if R has not been modified.
7215 This function is rather limited, but is good enough for our purposes. */
7218 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
7220 x
= avoid_constant_pool_reference (x
);
7224 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
7225 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
7226 x0
, GET_MODE (XEXP (x
, 0)));
7229 if (ARITHMETIC_P (x
))
7231 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
7232 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
7233 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
7237 && reg_values
[REGNO (x
)]
7238 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
7239 return reg_values
[REGNO (x
)];
7244 /* Return true if (set DEST SRC) stores an argument register into its
7245 caller-allocated save slot, storing the number of that argument
7246 register in *REGNO_PTR if so. REG_VALUES is as for
7247 mips16e_collect_propagate_value. */
7250 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
7251 unsigned int *regno_ptr
)
7253 unsigned int argno
, regno
;
7254 HOST_WIDE_INT offset
, required_offset
;
7257 /* Check that this is a word-mode store. */
7258 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
7261 /* Check that the register being saved is an unmodified argument
7263 regno
= REGNO (src
);
7264 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
7266 argno
= regno
- GP_ARG_FIRST
;
7268 /* Check whether the address is an appropriate stack-pointer or
7269 frame-pointer access. */
7270 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
7271 mips_split_plus (addr
, &base
, &offset
);
7272 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
7273 if (base
== hard_frame_pointer_rtx
)
7274 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7275 else if (base
!= stack_pointer_rtx
)
7277 if (offset
!= required_offset
)
7284 /* A subroutine of mips_expand_prologue, called only when generating
7285 MIPS16e SAVE instructions. Search the start of the function for any
7286 instructions that save argument registers into their caller-allocated
7287 save slots. Delete such instructions and return a value N such that
7288 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7289 instructions redundant. */
7292 mips16e_collect_argument_saves (void)
7294 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
7295 rtx insn
, next
, set
, dest
, src
;
7296 unsigned int nargs
, regno
;
7298 push_topmost_sequence ();
7300 memset (reg_values
, 0, sizeof (reg_values
));
7301 for (insn
= get_insns (); insn
; insn
= next
)
7303 next
= NEXT_INSN (insn
);
7310 set
= PATTERN (insn
);
7311 if (GET_CODE (set
) != SET
)
7314 dest
= SET_DEST (set
);
7315 src
= SET_SRC (set
);
7316 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
7318 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
7321 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
7324 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
7325 reg_values
[REGNO (dest
)]
7326 = mips16e_collect_propagate_value (src
, reg_values
);
7330 pop_topmost_sequence ();
7335 /* Return a move between register REGNO and memory location SP + OFFSET.
7336 Make the move a load if RESTORE_P, otherwise make it a frame-related
7340 mips16e_save_restore_reg (bool restore_p
, HOST_WIDE_INT offset
,
7345 mem
= gen_frame_mem (SImode
, plus_constant (stack_pointer_rtx
, offset
));
7346 reg
= gen_rtx_REG (SImode
, regno
);
7348 ? gen_rtx_SET (VOIDmode
, reg
, mem
)
7349 : mips_frame_set (mem
, reg
));
7352 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7353 The instruction must:
7355 - Allocate or deallocate SIZE bytes in total; SIZE is known
7358 - Save or restore as many registers in *MASK_PTR as possible.
7359 The instruction saves the first registers at the top of the
7360 allocated area, with the other registers below it.
7362 - Save NARGS argument registers above the allocated area.
7364 (NARGS is always zero if RESTORE_P.)
7366 The SAVE and RESTORE instructions cannot save and restore all general
7367 registers, so there may be some registers left over for the caller to
7368 handle. Destructively modify *MASK_PTR so that it contains the registers
7369 that still need to be saved or restored. The caller can save these
7370 registers in the memory immediately below *OFFSET_PTR, which is a
7371 byte offset from the bottom of the allocated stack area. */
7374 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
7375 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
7379 HOST_WIDE_INT offset
, top_offset
;
7380 unsigned int i
, regno
;
7383 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
7385 /* Calculate the number of elements in the PARALLEL. We need one element
7386 for the stack adjustment, one for each argument register save, and one
7387 for each additional register move. */
7389 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
7390 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
7393 /* Create the final PARALLEL. */
7394 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
7397 /* Add the stack pointer adjustment. */
7398 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7399 plus_constant (stack_pointer_rtx
,
7400 restore_p
? size
: -size
));
7401 RTX_FRAME_RELATED_P (set
) = 1;
7402 XVECEXP (pattern
, 0, n
++) = set
;
7404 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7405 top_offset
= restore_p
? size
: 0;
7407 /* Save the arguments. */
7408 for (i
= 0; i
< nargs
; i
++)
7410 offset
= top_offset
+ i
* UNITS_PER_WORD
;
7411 set
= mips16e_save_restore_reg (restore_p
, offset
, GP_ARG_FIRST
+ i
);
7412 XVECEXP (pattern
, 0, n
++) = set
;
7415 /* Then fill in the other register moves. */
7416 offset
= top_offset
;
7417 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
7419 regno
= mips16e_save_restore_regs
[i
];
7420 if (BITSET_P (*mask_ptr
, regno
))
7422 offset
-= UNITS_PER_WORD
;
7423 set
= mips16e_save_restore_reg (restore_p
, offset
, regno
);
7424 XVECEXP (pattern
, 0, n
++) = set
;
7425 *mask_ptr
&= ~(1 << regno
);
7429 /* Tell the caller what offset it should use for the remaining registers. */
7430 *offset_ptr
= size
+ (offset
- top_offset
);
7432 gcc_assert (n
== XVECLEN (pattern
, 0));
7437 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7438 pointer. Return true if PATTERN matches the kind of instruction
7439 generated by mips16e_build_save_restore. If INFO is nonnull,
7440 initialize it when returning true. */
7443 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
7444 struct mips16e_save_restore_info
*info
)
7446 unsigned int i
, nargs
, mask
, extra
;
7447 HOST_WIDE_INT top_offset
, save_offset
, offset
;
7448 rtx set
, reg
, mem
, base
;
7451 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
7454 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7455 top_offset
= adjust
> 0 ? adjust
: 0;
7457 /* Interpret all other members of the PARALLEL. */
7458 save_offset
= top_offset
- UNITS_PER_WORD
;
7462 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
7464 /* Check that we have a SET. */
7465 set
= XVECEXP (pattern
, 0, n
);
7466 if (GET_CODE (set
) != SET
)
7469 /* Check that the SET is a load (if restoring) or a store
7471 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
7475 /* Check that the address is the sum of the stack pointer and a
7476 possibly-zero constant offset. */
7477 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
7478 if (base
!= stack_pointer_rtx
)
7481 /* Check that SET's other operand is a register. */
7482 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
7486 /* Check for argument saves. */
7487 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
7488 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
7490 else if (offset
== save_offset
)
7492 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
7493 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
7496 mask
|= 1 << REGNO (reg
);
7497 save_offset
-= UNITS_PER_WORD
;
7503 /* Check that the restrictions on register ranges are met. */
7505 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
7506 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
7507 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
7508 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
7512 /* Make sure that the topmost argument register is not saved twice.
7513 The checks above ensure that the same is then true for the other
7514 argument registers. */
7515 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
7518 /* Pass back information, if requested. */
7521 info
->nargs
= nargs
;
7523 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
7529 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7530 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7531 the null terminator. */
7534 mips16e_add_register_range (char *s
, unsigned int min_reg
,
7535 unsigned int max_reg
)
7537 if (min_reg
!= max_reg
)
7538 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
7540 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
7544 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7545 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7548 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
7550 static char buffer
[300];
7552 struct mips16e_save_restore_info info
;
7553 unsigned int i
, end
;
7556 /* Parse the pattern. */
7557 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
7560 /* Add the mnemonic. */
7561 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
7564 /* Save the arguments. */
7566 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
7567 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
7568 else if (info
.nargs
== 1)
7569 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
7571 /* Emit the amount of stack space to allocate or deallocate. */
7572 s
+= sprintf (s
, "%d", (int) info
.size
);
7574 /* Save or restore $16. */
7575 if (BITSET_P (info
.mask
, 16))
7576 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
7578 /* Save or restore $17. */
7579 if (BITSET_P (info
.mask
, 17))
7580 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
7582 /* Save or restore registers in the range $s2...$s8, which
7583 mips16e_s2_s8_regs lists in decreasing order. Note that this
7584 is a software register range; the hardware registers are not
7585 numbered consecutively. */
7586 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
7587 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
7589 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
7590 mips16e_s2_s8_regs
[i
]);
7592 /* Save or restore registers in the range $a0...$a3. */
7593 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
7594 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
7596 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
7597 mips16e_a0_a3_regs
[end
- 1]);
7599 /* Save or restore $31. */
7600 if (BITSET_P (info
.mask
, 31))
7601 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 31]);
7606 /* Return true if the current function has an insn that implicitly
7610 mips_function_has_gp_insn (void)
7612 /* Don't bother rechecking if we found one last time. */
7613 if (!cfun
->machine
->has_gp_insn_p
)
7617 push_topmost_sequence ();
7618 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7619 if (USEFUL_INSN_P (insn
)
7620 && (get_attr_got (insn
) != GOT_UNSET
7621 || mips_small_data_pattern_p (PATTERN (insn
))))
7623 cfun
->machine
->has_gp_insn_p
= true;
7626 pop_topmost_sequence ();
7628 return cfun
->machine
->has_gp_insn_p
;
7631 /* Return the register that should be used as the global pointer
7632 within this function. Return 0 if the function doesn't need
7633 a global pointer. */
7636 mips_global_pointer (void)
7640 /* $gp is always available unless we're using a GOT. */
7641 if (!TARGET_USE_GOT
)
7642 return GLOBAL_POINTER_REGNUM
;
7644 /* We must always provide $gp when it is used implicitly. */
7645 if (!TARGET_EXPLICIT_RELOCS
)
7646 return GLOBAL_POINTER_REGNUM
;
7648 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7650 if (current_function_profile
)
7651 return GLOBAL_POINTER_REGNUM
;
7653 /* If the function has a nonlocal goto, $gp must hold the correct
7654 global pointer for the target function. */
7655 if (current_function_has_nonlocal_goto
)
7656 return GLOBAL_POINTER_REGNUM
;
7658 /* If the gp is never referenced, there's no need to initialize it.
7659 Note that reload can sometimes introduce constant pool references
7660 into a function that otherwise didn't need them. For example,
7661 suppose we have an instruction like:
7663 (set (reg:DF R1) (float:DF (reg:SI R2)))
7665 If R2 turns out to be constant such as 1, the instruction may have a
7666 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7667 using this constant if R2 doesn't get allocated to a register.
7669 In cases like these, reload will have added the constant to the pool
7670 but no instruction will yet refer to it. */
7671 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM
)
7672 && !current_function_uses_const_pool
7673 && !mips_function_has_gp_insn ())
7676 /* We need a global pointer, but perhaps we can use a call-clobbered
7677 register instead of $gp. */
7678 if (TARGET_CALL_SAVED_GP
&& current_function_is_leaf
)
7679 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
7680 if (!df_regs_ever_live_p (regno
)
7681 && call_really_used_regs
[regno
]
7682 && !fixed_regs
[regno
]
7683 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
7686 return GLOBAL_POINTER_REGNUM
;
7689 /* Return true if the current function returns its value in a floating-point
7690 register in MIPS16 mode. */
7693 mips16_cfun_returns_in_fpr_p (void)
7695 tree return_type
= DECL_RESULT (current_function_decl
);
7696 return (TARGET_MIPS16
7697 && TARGET_HARD_FLOAT_ABI
7698 && !aggregate_value_p (return_type
, current_function_decl
)
7699 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
7702 /* Return true if the current function must save register REGNO. */
7705 mips_save_reg_p (unsigned int regno
)
7707 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7708 if we have not chosen a call-clobbered substitute. */
7709 if (regno
== GLOBAL_POINTER_REGNUM
)
7710 return TARGET_CALL_SAVED_GP
&& cfun
->machine
->global_pointer
== regno
;
7712 /* Check call-saved registers. */
7713 if ((current_function_saves_all_registers
|| df_regs_ever_live_p (regno
))
7714 && !call_really_used_regs
[regno
])
7717 /* Save both registers in an FPR pair if either one is used. This is
7718 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7719 register to be used without the even register. */
7720 if (FP_REG_P (regno
)
7721 && MAX_FPRS_PER_FMT
== 2
7722 && df_regs_ever_live_p (regno
+ 1)
7723 && !call_really_used_regs
[regno
+ 1])
7726 /* We need to save the old frame pointer before setting up a new one. */
7727 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
7730 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7731 if (current_function_profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
7734 /* We need to save the incoming return address if it is ever clobbered
7735 within the function, if __builtin_eh_return is being used to set a
7736 different return address, or if a stub is being used to return a
7738 if (regno
== GP_REG_FIRST
+ 31
7739 && (df_regs_ever_live_p (regno
)
7740 || current_function_calls_eh_return
7741 || mips16_cfun_returns_in_fpr_p ()))
7747 /* Populate the current function's mips_frame_info structure.
7749 MIPS stack frames look like:
7751 +-------------------------------+
7753 | incoming stack arguments |
7755 +-------------------------------+
7757 | caller-allocated save area |
7758 A | for register arguments |
7760 +-------------------------------+ <-- incoming stack pointer
7762 | callee-allocated save area |
7763 B | for arguments that are |
7764 | split between registers and |
7767 +-------------------------------+ <-- arg_pointer_rtx
7769 C | callee-allocated save area |
7770 | for register varargs |
7772 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
7773 | | + UNITS_PER_HWFPVALUE
7776 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
7777 | | + UNITS_PER_WORD
7780 +-------------------------------+
7782 | local variables | | var_size
7784 +-------------------------------+
7786 | $gp save area | | cprestore_size
7788 P +-------------------------------+ <-- hard_frame_pointer_rtx for
7790 | outgoing stack arguments |
7792 +-------------------------------+
7794 | caller-allocated save area |
7795 | for register arguments |
7797 +-------------------------------+ <-- stack_pointer_rtx
7799 hard_frame_pointer_rtx for
7802 At least two of A, B and C will be empty.
7804 Dynamic stack allocations such as alloca insert data at point P.
7805 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7806 hard_frame_pointer_rtx unchanged. */
7809 mips_compute_frame_info (void)
7811 struct mips_frame_info
*frame
;
7812 HOST_WIDE_INT offset
, size
;
7813 unsigned int regno
, i
;
7815 frame
= &cfun
->machine
->frame
;
7816 memset (frame
, 0, sizeof (*frame
));
7817 size
= get_frame_size ();
7819 cfun
->machine
->global_pointer
= mips_global_pointer ();
7821 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
7822 area and the $gp save slot. This area isn't needed in leaf functions,
7823 but if the target-independent frame size is nonzero, we're committed
7824 to allocating it anyway. */
7825 if (size
== 0 && current_function_is_leaf
)
7827 /* The MIPS 3.0 linker does not like functions that dynamically
7828 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7829 looks like we are trying to create a second frame pointer to the
7830 function, so allocate some stack space to make it happy. */
7831 if (current_function_calls_alloca
)
7832 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
7834 frame
->args_size
= 0;
7835 frame
->cprestore_size
= 0;
7839 frame
->args_size
= current_function_outgoing_args_size
;
7840 frame
->cprestore_size
= STARTING_FRAME_OFFSET
- frame
->args_size
;
7842 offset
= frame
->args_size
+ frame
->cprestore_size
;
7844 /* Move above the local variables. */
7845 frame
->var_size
= MIPS_STACK_ALIGN (size
);
7846 offset
+= frame
->var_size
;
7848 /* Find out which GPRs we need to save. */
7849 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
7850 if (mips_save_reg_p (regno
))
7853 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
7856 /* If this function calls eh_return, we must also save and restore the
7857 EH data registers. */
7858 if (current_function_calls_eh_return
)
7859 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7862 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
7865 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
7866 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
7867 save all later registers too. */
7868 if (GENERATE_MIPS16E_SAVE_RESTORE
)
7870 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
7871 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
7872 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
7873 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
7876 /* Move above the GPR save area. */
7877 if (frame
->num_gp
> 0)
7879 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
7880 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
7883 /* Find out which FPRs we need to save. This loop must iterate over
7884 the same space as its companion in mips_for_each_saved_reg. */
7885 if (TARGET_HARD_FLOAT
)
7886 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
7887 if (mips_save_reg_p (regno
))
7889 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
7890 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
7893 /* Move above the FPR save area. */
7894 if (frame
->num_fp
> 0)
7896 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
7897 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
7900 /* Move above the callee-allocated varargs save area. */
7901 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
7902 frame
->arg_pointer_offset
= offset
;
7904 /* Move above the callee-allocated area for pretend stack arguments. */
7905 offset
+= current_function_pretend_args_size
;
7906 frame
->total_size
= offset
;
7908 /* Work out the offsets of the save areas from the top of the frame. */
7909 if (frame
->gp_sp_offset
> 0)
7910 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
7911 if (frame
->fp_sp_offset
> 0)
7912 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
7914 /* MIPS16 code offsets the frame pointer by the size of the outgoing
7915 arguments. This tends to increase the chances of using unextended
7916 instructions for local variables and incoming arguments. */
7918 frame
->hard_frame_pointer_offset
= frame
->args_size
;
7921 /* Return the style of GP load sequence that is being used for the
7922 current function. */
7924 enum mips_loadgp_style
7925 mips_current_loadgp_style (void)
7927 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== 0)
7933 if (TARGET_ABSOLUTE_ABICALLS
)
7934 return LOADGP_ABSOLUTE
;
7936 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
7939 /* Implement FRAME_POINTER_REQUIRED. */
7942 mips_frame_pointer_required (void)
7944 /* If the function contains dynamic stack allocations, we need to
7945 use the frame pointer to access the static parts of the frame. */
7946 if (current_function_calls_alloca
)
7949 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
7950 reload may be unable to compute the address of a local variable,
7951 since there is no way to add a large constant to the stack pointer
7952 without using a second temporary register. */
7955 mips_compute_frame_info ();
7956 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
7963 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
7964 or argument pointer. TO is either the stack pointer or hard frame
7968 mips_initial_elimination_offset (int from
, int to
)
7970 HOST_WIDE_INT offset
;
7972 mips_compute_frame_info ();
7974 /* Set OFFSET to the offset from the soft frame pointer, which is also
7975 the offset from the end-of-prologue stack pointer. */
7978 case FRAME_POINTER_REGNUM
:
7982 case ARG_POINTER_REGNUM
:
7983 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
7990 if (to
== HARD_FRAME_POINTER_REGNUM
)
7991 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7996 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
7999 mips_extra_live_on_entry (bitmap regs
)
8003 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8004 the global pointer. */
8005 if (!TARGET_ABSOLUTE_ABICALLS
)
8006 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
8008 /* See the comment above load_call<mode> for details. */
8009 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
8013 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8017 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
8022 return get_hard_reg_initial_val (Pmode
, GP_REG_FIRST
+ 31);
8025 /* Emit code to change the current function's return address to
8026 ADDRESS. SCRATCH is available as a scratch register, if needed.
8027 ADDRESS and SCRATCH are both word-mode GPRs. */
8030 mips_set_return_address (rtx address
, rtx scratch
)
8034 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, 31));
8035 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
8036 cfun
->machine
->frame
.gp_sp_offset
);
8037 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
8040 /* Restore $gp from its save slot. Valid only when using o32 or
8044 mips_restore_gp (void)
8048 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
);
8050 base
= frame_pointer_needed
? hard_frame_pointer_rtx
: stack_pointer_rtx
;
8051 address
= mips_add_offset (pic_offset_table_rtx
, base
,
8052 current_function_outgoing_args_size
);
8053 mips_emit_move (pic_offset_table_rtx
, gen_frame_mem (Pmode
, address
));
8054 if (!TARGET_EXPLICIT_RELOCS
)
8055 emit_insn (gen_blockage ());
8058 /* A function to save or store a register. The first argument is the
8059 register and the second is the stack slot. */
8060 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
8062 /* Use FN to save or restore register REGNO. MODE is the register's
8063 mode and OFFSET is the offset of its save slot from the current
8067 mips_save_restore_reg (enum machine_mode mode
, int regno
,
8068 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
8072 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
8073 fn (gen_rtx_REG (mode
, regno
), mem
);
8076 /* Call FN for each register that is saved by the current function.
8077 SP_OFFSET is the offset of the current stack pointer from the start
8081 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
8083 enum machine_mode fpr_mode
;
8084 HOST_WIDE_INT offset
;
8087 /* Save registers starting from high to low. The debuggers prefer at least
8088 the return register be stored at func+4, and also it allows us not to
8089 need a nop in the epilogue if at least one register is reloaded in
8090 addition to return address. */
8091 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
8092 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
8093 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
8095 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
8096 offset
-= UNITS_PER_WORD
;
8099 /* This loop must iterate over the same space as its companion in
8100 mips_compute_frame_info. */
8101 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
8102 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
8103 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
8104 regno
>= FP_REG_FIRST
;
8105 regno
-= MAX_FPRS_PER_FMT
)
8106 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
8108 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
8109 offset
-= GET_MODE_SIZE (fpr_mode
);
8113 /* If we're generating n32 or n64 abicalls, and the current function
8114 does not use $28 as its global pointer, emit a cplocal directive.
8115 Use pic_offset_table_rtx as the argument to the directive. */
8118 mips_output_cplocal (void)
8120 if (!TARGET_EXPLICIT_RELOCS
8121 && cfun
->machine
->global_pointer
> 0
8122 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
8123 output_asm_insn (".cplocal %+", 0);
8126 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8129 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8133 #ifdef SDB_DEBUGGING_INFO
8134 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
8135 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
8138 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8139 floating-point arguments. */
8141 && TARGET_HARD_FLOAT_ABI
8142 && current_function_args_info
.fp_code
!= 0)
8143 mips16_build_function_stub ();
8145 /* Select the MIPS16 mode for this function. */
8147 fprintf (file
, "\t.set\tmips16\n");
8149 fprintf (file
, "\t.set\tnomips16\n");
8151 if (!FUNCTION_NAME_ALREADY_DECLARED
)
8153 /* Get the function name the same way that toplev.c does before calling
8154 assemble_start_function. This is needed so that the name used here
8155 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8156 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8158 if (!flag_inhibit_size_directive
)
8160 fputs ("\t.ent\t", file
);
8161 assemble_name (file
, fnname
);
8165 assemble_name (file
, fnname
);
8166 fputs (":\n", file
);
8169 /* Stop mips_file_end from treating this function as external. */
8170 if (TARGET_IRIX
&& mips_abi
== ABI_32
)
8171 TREE_ASM_WRITTEN (DECL_NAME (cfun
->decl
)) = 1;
8173 /* Output MIPS-specific frame information. */
8174 if (!flag_inhibit_size_directive
)
8176 const struct mips_frame_info
*frame
;
8178 frame
= &cfun
->machine
->frame
;
8180 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8182 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
8183 "# vars= " HOST_WIDE_INT_PRINT_DEC
8185 ", args= " HOST_WIDE_INT_PRINT_DEC
8186 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
8187 reg_names
[frame_pointer_needed
8188 ? HARD_FRAME_POINTER_REGNUM
8189 : STACK_POINTER_REGNUM
],
8190 (frame_pointer_needed
8191 ? frame
->total_size
- frame
->hard_frame_pointer_offset
8192 : frame
->total_size
),
8193 reg_names
[GP_REG_FIRST
+ 31],
8195 frame
->num_gp
, frame
->num_fp
,
8197 frame
->cprestore_size
);
8199 /* .mask MASK, OFFSET. */
8200 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
8201 frame
->mask
, frame
->gp_save_offset
);
8203 /* .fmask MASK, OFFSET. */
8204 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
8205 frame
->fmask
, frame
->fp_save_offset
);
8208 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
8209 Also emit the ".set noreorder; .set nomacro" sequence for functions
8211 if (mips_current_loadgp_style () == LOADGP_OLDABI
)
8213 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
8214 if (!cfun
->machine
->all_noreorder_p
)
8215 output_asm_insn ("%(.cpload\t%^%)", 0);
8217 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8219 else if (cfun
->machine
->all_noreorder_p
)
8220 output_asm_insn ("%(%<", 0);
8222 /* Tell the assembler which register we're using as the global
8223 pointer. This is needed for thunks, since they can use either
8224 explicit relocs or assembler macros. */
8225 mips_output_cplocal ();
8228 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
8231 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8232 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8234 /* Reinstate the normal $gp. */
8235 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
8236 mips_output_cplocal ();
8238 if (cfun
->machine
->all_noreorder_p
)
8240 /* Avoid using %>%) since it adds excess whitespace. */
8241 output_asm_insn (".set\tmacro", 0);
8242 output_asm_insn (".set\treorder", 0);
8243 set_noreorder
= set_nomacro
= 0;
8246 if (!FUNCTION_NAME_ALREADY_DECLARED
&& !flag_inhibit_size_directive
)
8250 /* Get the function name the same way that toplev.c does before calling
8251 assemble_start_function. This is needed so that the name used here
8252 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8253 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8254 fputs ("\t.end\t", file
);
8255 assemble_name (file
, fnname
);
8260 /* Save register REG to MEM. Make the instruction frame-related. */
8263 mips_save_reg (rtx reg
, rtx mem
)
8265 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
8269 if (mips_split_64bit_move_p (mem
, reg
))
8270 mips_split_doubleword_move (mem
, reg
);
8272 mips_emit_move (mem
, reg
);
8274 x1
= mips_frame_set (mips_subword (mem
, false),
8275 mips_subword (reg
, false));
8276 x2
= mips_frame_set (mips_subword (mem
, true),
8277 mips_subword (reg
, true));
8278 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
8283 && REGNO (reg
) != GP_REG_FIRST
+ 31
8284 && !M16_REG_P (REGNO (reg
)))
8286 /* Save a non-MIPS16 register by moving it through a temporary.
8287 We don't need to do this for $31 since there's a special
8288 instruction for it. */
8289 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg
)), reg
);
8290 mips_emit_move (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
8293 mips_emit_move (mem
, reg
);
8295 mips_set_frame_expr (mips_frame_set (mem
, reg
));
8299 /* The __gnu_local_gp symbol. */
8301 static GTY(()) rtx mips_gnu_local_gp
;
8303 /* If we're generating n32 or n64 abicalls, emit instructions
8304 to set up the global pointer. */
8307 mips_emit_loadgp (void)
8309 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
8311 pic_reg
= pic_offset_table_rtx
;
8312 switch (mips_current_loadgp_style ())
8314 case LOADGP_ABSOLUTE
:
8315 if (mips_gnu_local_gp
== NULL
)
8317 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
8318 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
8320 emit_insn (Pmode
== SImode
8321 ? gen_loadgp_absolute_si (pic_reg
, mips_gnu_local_gp
)
8322 : gen_loadgp_absolute_di (pic_reg
, mips_gnu_local_gp
));
8326 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
8327 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
8328 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
8329 emit_insn (Pmode
== SImode
8330 ? gen_loadgp_newabi_si (pic_reg
, offset
, incoming_address
)
8331 : gen_loadgp_newabi_di (pic_reg
, offset
, incoming_address
));
8332 if (!TARGET_EXPLICIT_RELOCS
)
8333 emit_insn (gen_loadgp_blockage ());
8337 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
8338 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
8339 emit_insn (Pmode
== SImode
8340 ? gen_loadgp_rtp_si (pic_reg
, base
, index
)
8341 : gen_loadgp_rtp_di (pic_reg
, base
, index
));
8342 if (!TARGET_EXPLICIT_RELOCS
)
8343 emit_insn (gen_loadgp_blockage ());
8351 /* Expand the "prologue" pattern. */
8354 mips_expand_prologue (void)
8356 const struct mips_frame_info
*frame
;
8361 if (cfun
->machine
->global_pointer
> 0)
8362 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
8364 frame
= &cfun
->machine
->frame
;
8365 size
= frame
->total_size
;
8367 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8368 bytes beforehand; this is enough to cover the register save area
8369 without going out of range. */
8370 if ((frame
->mask
| frame
->fmask
) != 0)
8372 HOST_WIDE_INT step1
;
8374 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
8375 if (GENERATE_MIPS16E_SAVE_RESTORE
)
8377 HOST_WIDE_INT offset
;
8378 unsigned int mask
, regno
;
8380 /* Try to merge argument stores into the save instruction. */
8381 nargs
= mips16e_collect_argument_saves ();
8383 /* Build the save instruction. */
8385 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
8387 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8390 /* Check if we need to save other registers. */
8391 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
8392 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
8394 offset
-= UNITS_PER_WORD
;
8395 mips_save_restore_reg (word_mode
, regno
,
8396 offset
, mips_save_reg
);
8401 insn
= gen_add3_insn (stack_pointer_rtx
,
8404 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8406 mips_for_each_saved_reg (size
, mips_save_reg
);
8410 /* Allocate the rest of the frame. */
8413 if (SMALL_OPERAND (-size
))
8414 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
8416 GEN_INT (-size
)))) = 1;
8419 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
8422 /* There are no instructions to add or subtract registers
8423 from the stack pointer, so use the frame pointer as a
8424 temporary. We should always be using a frame pointer
8425 in this case anyway. */
8426 gcc_assert (frame_pointer_needed
);
8427 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8428 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
8429 hard_frame_pointer_rtx
,
8430 MIPS_PROLOGUE_TEMP (Pmode
)));
8431 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
8434 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
8436 MIPS_PROLOGUE_TEMP (Pmode
)));
8438 /* Describe the combined effect of the previous instructions. */
8440 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8441 plus_constant (stack_pointer_rtx
, -size
)));
8445 /* Set up the frame pointer, if we're using one. */
8446 if (frame_pointer_needed
)
8448 HOST_WIDE_INT offset
;
8450 offset
= frame
->hard_frame_pointer_offset
;
8453 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8454 RTX_FRAME_RELATED_P (insn
) = 1;
8456 else if (SMALL_OPERAND (offset
))
8458 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
8459 stack_pointer_rtx
, GEN_INT (offset
));
8460 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8464 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
8465 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8466 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
8467 hard_frame_pointer_rtx
,
8468 MIPS_PROLOGUE_TEMP (Pmode
)));
8470 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
8471 plus_constant (stack_pointer_rtx
, offset
)));
8475 mips_emit_loadgp ();
8477 /* Initialize the $gp save slot. */
8478 if (frame
->cprestore_size
> 0)
8479 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size
)));
8481 /* If we are profiling, make sure no instructions are scheduled before
8482 the call to mcount. */
8483 if (current_function_profile
)
8484 emit_insn (gen_blockage ());
8487 /* Emit instructions to restore register REG from slot MEM. */
8490 mips_restore_reg (rtx reg
, rtx mem
)
8492 /* There's no MIPS16 instruction to load $31 directly. Load into
8493 $7 instead and adjust the return insn appropriately. */
8494 if (TARGET_MIPS16
&& REGNO (reg
) == GP_REG_FIRST
+ 31)
8495 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
8497 if (TARGET_MIPS16
&& !M16_REG_P (REGNO (reg
)))
8499 /* Can't restore directly; move through a temporary. */
8500 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
8501 mips_emit_move (reg
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
8504 mips_emit_move (reg
, mem
);
8507 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
8511 mips_expand_epilogue (bool sibcall_p
)
8513 const struct mips_frame_info
*frame
;
8514 HOST_WIDE_INT step1
, step2
;
8517 if (!sibcall_p
&& mips_can_use_return_insn ())
8519 emit_jump_insn (gen_return ());
8523 /* In MIPS16 mode, if the return value should go into a floating-point
8524 register, we need to call a helper routine to copy it over. */
8525 if (mips16_cfun_returns_in_fpr_p ())
8526 mips16_copy_fpr_return_value ();
8528 /* Split the frame into two. STEP1 is the amount of stack we should
8529 deallocate before restoring the registers. STEP2 is the amount we
8530 should deallocate afterwards.
8532 Start off by assuming that no registers need to be restored. */
8533 frame
= &cfun
->machine
->frame
;
8534 step1
= frame
->total_size
;
8537 /* Work out which register holds the frame address. */
8538 if (!frame_pointer_needed
)
8539 base
= stack_pointer_rtx
;
8542 base
= hard_frame_pointer_rtx
;
8543 step1
-= frame
->hard_frame_pointer_offset
;
8546 /* If we need to restore registers, deallocate as much stack as
8547 possible in the second step without going out of range. */
8548 if ((frame
->mask
| frame
->fmask
) != 0)
8550 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
8554 /* Set TARGET to BASE + STEP1. */
8560 /* Get an rtx for STEP1 that we can add to BASE. */
8561 adjust
= GEN_INT (step1
);
8562 if (!SMALL_OPERAND (step1
))
8564 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
8565 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
8568 /* Normal mode code can copy the result straight into $sp. */
8570 target
= stack_pointer_rtx
;
8572 emit_insn (gen_add3_insn (target
, base
, adjust
));
8575 /* Copy TARGET into the stack pointer. */
8576 if (target
!= stack_pointer_rtx
)
8577 mips_emit_move (stack_pointer_rtx
, target
);
8579 /* If we're using addressing macros, $gp is implicitly used by all
8580 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8582 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
8583 emit_insn (gen_blockage ());
8585 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
8587 unsigned int regno
, mask
;
8588 HOST_WIDE_INT offset
;
8591 /* Generate the restore instruction. */
8593 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
8595 /* Restore any other registers manually. */
8596 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
8597 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
8599 offset
-= UNITS_PER_WORD
;
8600 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
8603 /* Restore the remaining registers and deallocate the final bit
8605 emit_insn (restore
);
8609 /* Restore the registers. */
8610 mips_for_each_saved_reg (frame
->total_size
- step2
, mips_restore_reg
);
8612 /* Deallocate the final bit of the frame. */
8614 emit_insn (gen_add3_insn (stack_pointer_rtx
,
8619 /* Add in the __builtin_eh_return stack adjustment. We need to
8620 use a temporary in MIPS16 code. */
8621 if (current_function_calls_eh_return
)
8625 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
8626 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
8627 MIPS_EPILOGUE_TEMP (Pmode
),
8628 EH_RETURN_STACKADJ_RTX
));
8629 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
8632 emit_insn (gen_add3_insn (stack_pointer_rtx
,
8634 EH_RETURN_STACKADJ_RTX
));
8641 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8642 path will restore the return address into $7 rather than $31. */
8644 && !GENERATE_MIPS16E_SAVE_RESTORE
8645 && BITSET_P (frame
->mask
, 31))
8646 regno
= GP_REG_FIRST
+ 7;
8648 regno
= GP_REG_FIRST
+ 31;
8649 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, regno
)));
8653 /* Return nonzero if this function is known to have a null epilogue.
8654 This allows the optimizer to omit jumps to jumps if no stack
8658 mips_can_use_return_insn (void)
8660 if (!reload_completed
)
8663 if (current_function_profile
)
8666 /* In MIPS16 mode, a function that returns a floating-point value
8667 needs to arrange to copy the return value into the floating-point
8669 if (mips16_cfun_returns_in_fpr_p ())
8672 return cfun
->machine
->frame
.total_size
== 0;
8675 /* Return true if register REGNO can store a value of mode MODE.
8676 The result of this function is cached in mips_hard_regno_mode_ok. */
8679 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
8682 enum mode_class
class;
8684 if (mode
== CCV2mode
)
8687 && (regno
- ST_REG_FIRST
) % 2 == 0);
8689 if (mode
== CCV4mode
)
8692 && (regno
- ST_REG_FIRST
) % 4 == 0);
8697 return regno
== FPSW_REGNUM
;
8699 return (ST_REG_P (regno
)
8701 || FP_REG_P (regno
));
8704 size
= GET_MODE_SIZE (mode
);
8705 class = GET_MODE_CLASS (mode
);
8707 if (GP_REG_P (regno
))
8708 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
8710 if (FP_REG_P (regno
)
8711 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
8712 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
8714 /* Allow TFmode for CCmode reloads. */
8715 if (mode
== TFmode
&& ISA_HAS_8CC
)
8718 if (class == MODE_FLOAT
8719 || class == MODE_COMPLEX_FLOAT
8720 || class == MODE_VECTOR_FLOAT
)
8721 return size
<= UNITS_PER_FPVALUE
;
8723 /* Allow integer modes that fit into a single register. We need
8724 to put integers into FPRs when using instructions like CVT
8725 and TRUNC. There's no point allowing sizes smaller than a word,
8726 because the FPU has no appropriate load/store instructions. */
8727 if (class == MODE_INT
)
8728 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
8731 if (ACC_REG_P (regno
)
8732 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
8734 if (size
<= UNITS_PER_WORD
)
8737 if (size
<= UNITS_PER_WORD
* 2)
8738 return (DSP_ACC_REG_P (regno
)
8739 ? ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0
8740 : regno
== MD_REG_FIRST
);
8743 if (ALL_COP_REG_P (regno
))
8744 return class == MODE_INT
&& size
<= UNITS_PER_WORD
;
8746 if (regno
== GOT_VERSION_REGNUM
)
8747 return mode
== SImode
;
8752 /* Implement HARD_REGNO_NREGS. */
8755 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
8757 if (ST_REG_P (regno
))
8758 /* The size of FP status registers is always 4, because they only hold
8759 CCmode values, and CCmode is always considered to be 4 bytes wide. */
8760 return (GET_MODE_SIZE (mode
) + 3) / 4;
8762 if (FP_REG_P (regno
))
8763 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
8765 /* All other registers are word-sized. */
8766 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8769 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
8770 in mips_hard_regno_nregs. */
8773 mips_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
8779 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) class]);
8780 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
8782 size
= MIN (size
, 4);
8783 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
8785 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
8787 size
= MIN (size
, UNITS_PER_FPREG
);
8788 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
8790 if (!hard_reg_set_empty_p (left
))
8791 size
= MIN (size
, UNITS_PER_WORD
);
8792 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
8795 /* Implement CANNOT_CHANGE_MODE_CLASS. */
8798 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED
,
8799 enum machine_mode to ATTRIBUTE_UNUSED
,
8800 enum reg_class
class)
8802 /* There are several problems with changing the modes of values
8803 in floating-point registers:
8805 - When a multi-word value is stored in paired floating-point
8806 registers, the first register always holds the low word.
8807 We therefore can't allow FPRs to change between single-word
8808 and multi-word modes on big-endian targets.
8810 - GCC assumes that each word of a multiword register can be accessed
8811 individually using SUBREGs. This is not true for floating-point
8812 registers if they are bigger than a word.
8814 - Loading a 32-bit value into a 64-bit floating-point register
8815 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8816 We can't allow FPRs to change from SImode to to a wider mode on
8819 - If the FPU has already interpreted a value in one format, we must
8820 not ask it to treat the value as having a different format.
8822 We therefore disallow all mode changes involving FPRs. */
8823 return reg_classes_intersect_p (FP_REGS
, class);
8826 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
8829 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
8834 return TARGET_HARD_FLOAT
;
8837 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
8840 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
8847 /* Implement MODES_TIEABLE_P. */
8850 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
8852 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
8853 prefer to put one of them in FPRs. */
8854 return (mode1
== mode2
8855 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
8856 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
8859 /* Implement PREFERRED_RELOAD_CLASS. */
8862 mips_preferred_reload_class (rtx x
, enum reg_class
class)
8864 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, class))
8867 if (reg_class_subset_p (FP_REGS
, class)
8868 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
8871 if (reg_class_subset_p (GR_REGS
, class))
8874 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, class))
8880 /* Implement REGISTER_MOVE_COST. */
8883 mips_register_move_cost (enum machine_mode mode
,
8884 enum reg_class to
, enum reg_class from
)
8888 /* ??? We cannot move general registers into HI and LO because
8889 MIPS16 has no MTHI and MTLO instructions. Make the cost of
8890 moves in the opposite direction just as high, which stops the
8891 register allocators from using HI and LO for pseudos. */
8892 if (reg_class_subset_p (from
, GENERAL_REGS
)
8893 && reg_class_subset_p (to
, GENERAL_REGS
))
8895 if (reg_class_subset_p (from
, M16_REGS
)
8896 || reg_class_subset_p (to
, M16_REGS
))
8902 else if (reg_class_subset_p (from
, GENERAL_REGS
))
8904 if (reg_class_subset_p (to
, GENERAL_REGS
))
8906 if (reg_class_subset_p (to
, FP_REGS
))
8908 if (reg_class_subset_p (to
, ALL_COP_AND_GR_REGS
))
8910 if (reg_class_subset_p (to
, ACC_REGS
))
8913 else if (reg_class_subset_p (to
, GENERAL_REGS
))
8915 if (reg_class_subset_p (from
, FP_REGS
))
8917 if (reg_class_subset_p (from
, ST_REGS
))
8918 /* LUI followed by MOVF. */
8920 if (reg_class_subset_p (from
, ALL_COP_AND_GR_REGS
))
8922 if (reg_class_subset_p (from
, ACC_REGS
))
8925 else if (reg_class_subset_p (from
, FP_REGS
))
8927 if (reg_class_subset_p (to
, FP_REGS
)
8928 && mips_mode_ok_for_mov_fmt_p (mode
))
8930 if (reg_class_subset_p (to
, ST_REGS
))
8931 /* An expensive sequence. */
8938 /* Return the register class required for a secondary register when
8939 copying between one of the registers in CLASS and value X, which
8940 has mode MODE. X is the source of the move if IN_P, otherwise it
8941 is the destination. Return NO_REGS if no secondary register is
8945 mips_secondary_reload_class (enum reg_class
class,
8946 enum machine_mode mode
, rtx x
, bool in_p
)
8950 /* If X is a constant that cannot be loaded into $25, it must be loaded
8951 into some other GPR. No other register class allows a direct move. */
8952 if (mips_dangerous_for_la25_p (x
))
8953 return reg_class_subset_p (class, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
8955 regno
= true_regnum (x
);
8958 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
8959 if (!reg_class_subset_p (class, M16_REGS
) && !M16_REG_P (regno
))
8962 /* We can't really copy to HI or LO at all in MIPS16 mode. */
8963 if (in_p
? reg_classes_intersect_p (class, ACC_REGS
) : ACC_REG_P (regno
))
8969 /* Copying from accumulator registers to anywhere other than a general
8970 register requires a temporary general register. */
8971 if (reg_class_subset_p (class, ACC_REGS
))
8972 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
8973 if (ACC_REG_P (regno
))
8974 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
8976 /* We can only copy a value to a condition code register from a
8977 floating-point register, and even then we require a scratch
8978 floating-point register. We can only copy a value out of a
8979 condition-code register into a general register. */
8980 if (reg_class_subset_p (class, ST_REGS
))
8984 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
8986 if (ST_REG_P (regno
))
8990 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
8993 if (reg_class_subset_p (class, FP_REGS
))
8996 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
8997 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
8998 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9001 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
9002 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9005 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (x
))
9006 /* We can force the constant to memory and use lwc1
9007 and ldc1. As above, we will use pairs of lwc1s if
9008 ldc1 is not supported. */
9011 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
9012 /* In this case we can use mov.fmt. */
9015 /* Otherwise, we need to reload through an integer register. */
9018 if (FP_REG_P (regno
))
9019 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
9024 /* Implement TARGET_MODE_REP_EXTENDED. */
9027 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
9029 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
9030 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
9036 /* Implement TARGET_VALID_POINTER_MODE. */
9039 mips_valid_pointer_mode (enum machine_mode mode
)
9041 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
9044 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
9047 mips_vector_mode_supported_p (enum machine_mode mode
)
9052 return TARGET_PAIRED_SINGLE_FLOAT
;
9069 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9072 mips_scalar_mode_supported_p (enum machine_mode mode
)
9074 if (ALL_FIXED_POINT_MODE_P (mode
)
9075 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
9078 return default_scalar_mode_supported_p (mode
);
9081 /* Implement TARGET_INIT_LIBFUNCS. */
9083 #include "config/gofast.h"
9086 mips_init_libfuncs (void)
9088 if (TARGET_FIX_VR4120
)
9090 /* Register the special divsi3 and modsi3 functions needed to work
9091 around VR4120 division errata. */
9092 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
9093 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
9096 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
9098 /* Register the MIPS16 -mhard-float stubs. */
9099 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
9100 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
9101 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
9102 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
9104 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
9105 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
9106 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
9107 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
9108 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
9109 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
9110 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
9112 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
9113 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
9114 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
9116 if (TARGET_DOUBLE_FLOAT
)
9118 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
9119 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
9120 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
9121 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
9123 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
9124 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
9125 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
9126 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
9127 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
9128 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
9129 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
9131 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
9132 "__mips16_extendsfdf2");
9133 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
9134 "__mips16_truncdfsf2");
9135 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
9136 "__mips16_fix_truncdfsi");
9137 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
9138 "__mips16_floatsidf");
9139 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
9140 "__mips16_floatunsidf");
9144 /* Register the gofast functions if selected using --enable-gofast. */
9145 gofast_maybe_init_libfuncs ();
9148 /* Return the length of INSN. LENGTH is the initial length computed by
9149 attributes in the machine-description file. */
9152 mips_adjust_insn_length (rtx insn
, int length
)
9154 /* A unconditional jump has an unfilled delay slot if it is not part
9155 of a sequence. A conditional jump normally has a delay slot, but
9156 does not on MIPS16. */
9157 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
9160 /* See how many nops might be needed to avoid hardware hazards. */
9161 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
9162 switch (get_attr_hazard (insn
))
9176 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
9177 the .md file length attributes are 4-based for both modes.
9178 Adjust the MIPS16 ones here. */
9185 /* Return an asm sequence to start a noat block and load the address
9186 of a label into $1. */
9189 mips_output_load_label (void)
9191 if (TARGET_EXPLICIT_RELOCS
)
9195 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9198 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9201 if (ISA_HAS_LOAD_DELAY
)
9202 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9203 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9207 if (Pmode
== DImode
)
9208 return "%[dla\t%@,%0";
9210 return "%[la\t%@,%0";
9214 /* Return the assembly code for INSN, which has the operands given by
9215 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9216 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9217 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9218 version of BRANCH_IF_TRUE. */
9221 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
9222 const char *branch_if_true
,
9223 const char *branch_if_false
)
9225 unsigned int length
;
9226 rtx taken
, not_taken
;
9228 length
= get_attr_length (insn
);
9231 /* Just a simple conditional branch. */
9232 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9233 return branch_if_true
;
9236 /* Generate a reversed branch around a direct jump. This fallback does
9237 not use branch-likely instructions. */
9238 mips_branch_likely
= false;
9239 not_taken
= gen_label_rtx ();
9240 taken
= operands
[1];
9242 /* Generate the reversed branch to NOT_TAKEN. */
9243 operands
[1] = not_taken
;
9244 output_asm_insn (branch_if_false
, operands
);
9246 /* If INSN has a delay slot, we must provide delay slots for both the
9247 branch to NOT_TAKEN and the conditional jump. We must also ensure
9248 that INSN's delay slot is executed in the appropriate cases. */
9251 /* This first delay slot will always be executed, so use INSN's
9252 delay slot if is not annulled. */
9253 if (!INSN_ANNULLED_BRANCH_P (insn
))
9255 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9256 asm_out_file
, optimize
, 1, NULL
);
9257 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9260 output_asm_insn ("nop", 0);
9261 fprintf (asm_out_file
, "\n");
9264 /* Output the unconditional branch to TAKEN. */
9266 output_asm_insn ("j\t%0%/", &taken
);
9269 output_asm_insn (mips_output_load_label (), &taken
);
9270 output_asm_insn ("jr\t%@%]%/", 0);
9273 /* Now deal with its delay slot; see above. */
9276 /* This delay slot will only be executed if the branch is taken.
9277 Use INSN's delay slot if is annulled. */
9278 if (INSN_ANNULLED_BRANCH_P (insn
))
9280 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9281 asm_out_file
, optimize
, 1, NULL
);
9282 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9285 output_asm_insn ("nop", 0);
9286 fprintf (asm_out_file
, "\n");
9289 /* Output NOT_TAKEN. */
9290 targetm
.asm_out
.internal_label (asm_out_file
, "L",
9291 CODE_LABEL_NUMBER (not_taken
));
9295 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9296 if some ordering condition is true. The condition is given by
9297 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9298 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9299 its second is always zero. */
9302 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
9304 const char *branch
[2];
9306 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9307 Make BRANCH[0] branch on the inverse condition. */
9308 switch (GET_CODE (operands
[0]))
9310 /* These cases are equivalent to comparisons against zero. */
9312 inverted_p
= !inverted_p
;
9315 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%1");
9316 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%1");
9319 /* These cases are always true or always false. */
9321 inverted_p
= !inverted_p
;
9324 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%1");
9325 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%1");
9329 branch
[!inverted_p
] = MIPS_BRANCH ("b%C0z", "%2,%1");
9330 branch
[inverted_p
] = MIPS_BRANCH ("b%N0z", "%2,%1");
9333 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
9336 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
9337 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
9339 When working around R4000 and R4400 errata, we need to make sure that
9340 the division is not immediately followed by a shift[1][2]. We also
9341 need to stop the division from being put into a branch delay slot[3].
9342 The easiest way to avoid both problems is to add a nop after the
9343 division. When a divide-by-zero check is needed, this nop can be
9344 used to fill the branch delay slot.
9346 [1] If a double-word or a variable shift executes immediately
9347 after starting an integer division, the shift may give an
9348 incorrect result. See quotations of errata #16 and #28 from
9349 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9350 in mips.md for details.
9352 [2] A similar bug to [1] exists for all revisions of the
9353 R4000 and the R4400 when run in an MC configuration.
9354 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9356 "19. In this following sequence:
9358 ddiv (or ddivu or div or divu)
9359 dsll32 (or dsrl32, dsra32)
9361 if an MPT stall occurs, while the divide is slipping the cpu
9362 pipeline, then the following double shift would end up with an
9365 Workaround: The compiler needs to avoid generating any
9366 sequence with divide followed by extended double shift."
9368 This erratum is also present in "MIPS R4400MC Errata, Processor
9369 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9370 & 3.0" as errata #10 and #4, respectively.
9372 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9373 (also valid for MIPS R4000MC processors):
9375 "52. R4000SC: This bug does not apply for the R4000PC.
9377 There are two flavors of this bug:
9379 1) If the instruction just after divide takes an RF exception
9380 (tlb-refill, tlb-invalid) and gets an instruction cache
9381 miss (both primary and secondary) and the line which is
9382 currently in secondary cache at this index had the first
9383 data word, where the bits 5..2 are set, then R4000 would
9384 get a wrong result for the div.
9389 ------------------- # end-of page. -tlb-refill
9394 ------------------- # end-of page. -tlb-invalid
9397 2) If the divide is in the taken branch delay slot, where the
9398 target takes RF exception and gets an I-cache miss for the
9399 exception vector or where I-cache miss occurs for the
9400 target address, under the above mentioned scenarios, the
9401 div would get wrong results.
9404 j r2 # to next page mapped or unmapped
9405 div r8,r9 # this bug would be there as long
9406 # as there is an ICache miss and
9407 nop # the "data pattern" is present
9410 beq r0, r0, NextPage # to Next page
9414 This bug is present for div, divu, ddiv, and ddivu
9417 Workaround: For item 1), OS could make sure that the next page
9418 after the divide instruction is also mapped. For item 2), the
9419 compiler could make sure that the divide instruction is not in
9420 the branch delay slot."
9422 These processors have PRId values of 0x00004220 and 0x00004300 for
9423 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9426 mips_output_division (const char *division
, rtx
*operands
)
9431 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
9433 output_asm_insn (s
, operands
);
9436 if (TARGET_CHECK_ZERO_DIV
)
9440 output_asm_insn (s
, operands
);
9441 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
9443 else if (GENERATE_DIVIDE_TRAPS
)
9445 output_asm_insn (s
, operands
);
9450 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
9451 output_asm_insn (s
, operands
);
9452 s
= "break\t7%)\n1:";
9458 /* Return true if IN_INSN is a multiply-add or multiply-subtract
9459 instruction and if OUT_INSN assigns to the accumulator operand. */
9462 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
9466 x
= single_set (in_insn
);
9472 if (GET_CODE (x
) == PLUS
9473 && GET_CODE (XEXP (x
, 0)) == MULT
9474 && reg_set_p (XEXP (x
, 1), out_insn
))
9477 if (GET_CODE (x
) == MINUS
9478 && GET_CODE (XEXP (x
, 1)) == MULT
9479 && reg_set_p (XEXP (x
, 0), out_insn
))
9485 /* True if the dependency between OUT_INSN and IN_INSN is on the store
9486 data rather than the address. We need this because the cprestore
9487 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
9488 which causes the default routine to abort. We just return false
9492 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
9494 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
9497 return !store_data_bypass_p (out_insn
, in_insn
);
9500 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9501 dependencies have no cost, except on the 20Kc where output-dependence
9502 is treated like input-dependence. */
9505 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
9506 rtx dep ATTRIBUTE_UNUSED
, int cost
)
9508 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
9511 if (REG_NOTE_KIND (link
) != 0)
9516 /* Return the number of instructions that can be issued per cycle. */
9519 mips_issue_rate (void)
9523 case PROCESSOR_74KC
:
9524 case PROCESSOR_74KF2_1
:
9525 case PROCESSOR_74KF1_1
:
9526 case PROCESSOR_74KF3_2
:
9527 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9528 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9529 but in reality only a maximum of 3 insns can be issued as
9530 floating-point loads and stores also require a slot in the
9534 case PROCESSOR_20KC
:
9535 case PROCESSOR_R4130
:
9536 case PROCESSOR_R5400
:
9537 case PROCESSOR_R5500
:
9538 case PROCESSOR_R7000
:
9539 case PROCESSOR_R9000
:
9543 case PROCESSOR_SB1A
:
9544 /* This is actually 4, but we get better performance if we claim 3.
9545 This is partly because of unwanted speculative code motion with the
9546 larger number, and partly because in most common cases we can't
9547 reach the theoretical max of 4. */
9555 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9556 be as wide as the scheduling freedom in the DFA. */
9559 mips_multipass_dfa_lookahead (void)
9561 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9568 /* Remove the instruction at index LOWER from ready queue READY and
9569 reinsert it in front of the instruction at index HIGHER. LOWER must
9573 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
9578 new_head
= ready
[lower
];
9579 for (i
= lower
; i
< higher
; i
++)
9580 ready
[i
] = ready
[i
+ 1];
9581 ready
[i
] = new_head
;
9584 /* If the priority of the instruction at POS2 in the ready queue READY
9585 is within LIMIT units of that of the instruction at POS1, swap the
9586 instructions if POS2 is not already less than POS1. */
9589 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
9592 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
9597 ready
[pos1
] = ready
[pos2
];
9602 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9603 that may clobber hi or lo. */
9604 static rtx mips_macc_chains_last_hilo
;
9606 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9607 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9610 mips_macc_chains_record (rtx insn
)
9612 if (get_attr_may_clobber_hilo (insn
))
9613 mips_macc_chains_last_hilo
= insn
;
9616 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9617 has NREADY elements, looking for a multiply-add or multiply-subtract
9618 instruction that is cumulative with mips_macc_chains_last_hilo.
9619 If there is one, promote it ahead of anything else that might
9620 clobber hi or lo. */
9623 mips_macc_chains_reorder (rtx
*ready
, int nready
)
9627 if (mips_macc_chains_last_hilo
!= 0)
9628 for (i
= nready
- 1; i
>= 0; i
--)
9629 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
9631 for (j
= nready
- 1; j
> i
; j
--)
9632 if (recog_memoized (ready
[j
]) >= 0
9633 && get_attr_may_clobber_hilo (ready
[j
]))
9635 mips_promote_ready (ready
, i
, j
);
9642 /* The last instruction to be scheduled. */
9643 static rtx vr4130_last_insn
;
9645 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9646 points to an rtx that is initially an instruction. Nullify the rtx
9647 if the instruction uses the value of register X. */
9650 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
9655 insn_ptr
= (rtx
*) data
;
9658 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
9662 /* Return true if there is true register dependence between vr4130_last_insn
9666 vr4130_true_reg_dependence_p (rtx insn
)
9668 note_stores (PATTERN (vr4130_last_insn
),
9669 vr4130_true_reg_dependence_p_1
, &insn
);
9673 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9674 the ready queue and that INSN2 is the instruction after it, return
9675 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9676 in which INSN1 and INSN2 can probably issue in parallel, but for
9677 which (INSN2, INSN1) should be less sensitive to instruction
9678 alignment than (INSN1, INSN2). See 4130.md for more details. */
9681 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
9683 sd_iterator_def sd_it
;
9686 /* Check for the following case:
9688 1) there is some other instruction X with an anti dependence on INSN1;
9689 2) X has a higher priority than INSN2; and
9690 3) X is an arithmetic instruction (and thus has no unit restrictions).
9692 If INSN1 is the last instruction blocking X, it would better to
9693 choose (INSN1, X) over (INSN2, INSN1). */
9694 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
9695 if (DEP_TYPE (dep
) == REG_DEP_ANTI
9696 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
9697 && recog_memoized (DEP_CON (dep
)) >= 0
9698 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
9701 if (vr4130_last_insn
!= 0
9702 && recog_memoized (insn1
) >= 0
9703 && recog_memoized (insn2
) >= 0)
9705 /* See whether INSN1 and INSN2 use different execution units,
9706 or if they are both ALU-type instructions. If so, they can
9707 probably execute in parallel. */
9708 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
9709 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
9710 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
9712 /* If only one of the instructions has a dependence on
9713 vr4130_last_insn, prefer to schedule the other one first. */
9714 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
9715 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
9716 if (dep1_p
!= dep2_p
)
9719 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9720 is not an ALU-type instruction and if INSN1 uses the same
9721 execution unit. (Note that if this condition holds, we already
9722 know that INSN2 uses a different execution unit.) */
9723 if (class1
!= VR4130_CLASS_ALU
9724 && recog_memoized (vr4130_last_insn
) >= 0
9725 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
9732 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9733 queue with at least two instructions. Swap the first two if
9734 vr4130_swap_insns_p says that it could be worthwhile. */
9737 vr4130_reorder (rtx
*ready
, int nready
)
9739 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
9740 mips_promote_ready (ready
, nready
- 2, nready
- 1);
9743 /* Record whether last 74k AGEN instruction was a load or store. */
9744 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
9746 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
9747 resets to TYPE_UNKNOWN state. */
9750 mips_74k_agen_init (rtx insn
)
9752 if (!insn
|| !NONJUMP_INSN_P (insn
))
9753 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
9756 enum attr_type type
= get_attr_type (insn
);
9757 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
9758 mips_last_74k_agen_insn
= type
;
9762 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
9763 loads to be grouped together, and multiple stores to be grouped
9764 together. Swap things around in the ready queue to make this happen. */
9767 mips_74k_agen_reorder (rtx
*ready
, int nready
)
9770 int store_pos
, load_pos
;
9775 for (i
= nready
- 1; i
>= 0; i
--)
9777 rtx insn
= ready
[i
];
9778 if (USEFUL_INSN_P (insn
))
9779 switch (get_attr_type (insn
))
9782 if (store_pos
== -1)
9796 if (load_pos
== -1 || store_pos
== -1)
9799 switch (mips_last_74k_agen_insn
)
9802 /* Prefer to schedule loads since they have a higher latency. */
9804 /* Swap loads to the front of the queue. */
9805 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
9808 /* Swap stores to the front of the queue. */
9809 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
9816 /* Implement TARGET_SCHED_INIT. */
9819 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9820 int max_ready ATTRIBUTE_UNUSED
)
9822 mips_macc_chains_last_hilo
= 0;
9823 vr4130_last_insn
= 0;
9824 mips_74k_agen_init (NULL_RTX
);
9827 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
9830 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9831 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
9833 if (!reload_completed
9836 mips_macc_chains_reorder (ready
, *nreadyp
);
9838 if (reload_completed
9840 && !TARGET_VR4130_ALIGN
9842 vr4130_reorder (ready
, *nreadyp
);
9845 mips_74k_agen_reorder (ready
, *nreadyp
);
9847 return mips_issue_rate ();
9850 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9853 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9856 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
9857 if (USEFUL_INSN_P (insn
))
9860 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9861 mips_macc_chains_record (insn
);
9862 vr4130_last_insn
= insn
;
9864 mips_74k_agen_init (insn
);
9869 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9870 return the first operand of the associated PREF or PREFX insn. */
9873 mips_prefetch_cookie (rtx write
, rtx locality
)
9875 /* store_streamed / load_streamed. */
9876 if (INTVAL (locality
) <= 0)
9877 return GEN_INT (INTVAL (write
) + 4);
9880 if (INTVAL (locality
) <= 2)
9883 /* store_retained / load_retained. */
9884 return GEN_INT (INTVAL (write
) + 6);
9887 /* This structure describes a single built-in function. */
9888 struct mips_builtin_description
{
9889 /* The code of the main .md file instruction. See mips_builtin_type
9890 for more information. */
9891 enum insn_code icode
;
9893 /* The floating-point comparison code to use with ICODE, if any. */
9894 enum mips_fp_condition cond
;
9896 /* The name of the built-in function. */
9899 /* Specifies how the function should be expanded. */
9900 enum mips_builtin_type builtin_type
;
9902 /* The function's prototype. */
9903 enum mips_function_type function_type
;
9905 /* The target flags required for this function. */
9909 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9910 FUNCTION_TYPE and TARGET_FLAGS are mips_builtin_description fields. */
9911 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9912 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9913 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9915 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
9916 require TARGET_FLAGS. */
9917 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9918 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9919 "__builtin_mips_" #INSN "_" #COND "_s", \
9920 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9921 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9922 "__builtin_mips_" #INSN "_" #COND "_d", \
9923 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9925 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9926 The lower and upper forms require TARGET_FLAGS while the any and all
9927 forms require MASK_MIPS3D. */
9928 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9929 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9930 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9931 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9932 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9933 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9934 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9935 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9936 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9937 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9938 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9939 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9940 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9942 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9943 require MASK_MIPS3D. */
9944 #define CMP_4S_BUILTINS(INSN, COND) \
9945 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9946 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9947 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9949 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9950 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9951 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9954 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9955 instruction requires TARGET_FLAGS. */
9956 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9957 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9958 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9959 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9961 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9962 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
9963 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9966 /* Define all the built-in functions related to C.cond.fmt condition COND. */
9967 #define CMP_BUILTINS(COND) \
9968 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9969 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
9970 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
9971 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9972 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
9973 CMP_4S_BUILTINS (c, COND), \
9974 CMP_4S_BUILTINS (cabs, COND)
9976 static const struct mips_builtin_description mips_ps_bdesc
[] = {
9977 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
9978 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
9979 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
9980 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
9981 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, MASK_PAIRED_SINGLE_FLOAT
),
9982 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
9983 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
9984 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
9986 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
9987 MASK_PAIRED_SINGLE_FLOAT
),
9988 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
9989 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
9990 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
9991 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
9993 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
9994 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
9995 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
9996 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
9997 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
9998 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10000 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10001 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10002 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10003 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10004 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10005 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10007 MIPS_FP_CONDITIONS (CMP_BUILTINS
)
10010 /* Built-in functions for the SB-1 processor. */
10012 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10014 static const struct mips_builtin_description mips_sb1_bdesc
[] = {
10015 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
)
10018 /* Built-in functions for the DSP ASE. */
10020 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10021 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10022 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10023 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10024 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10026 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10027 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10028 mips_builtin_description fields. */
10029 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10030 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10031 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10033 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10034 branch instruction. TARGET_FLAGS is a mips_builtin_description field. */
10035 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10036 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10037 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10039 static const struct mips_builtin_description mips_dsp_bdesc
[] = {
10040 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10041 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10042 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10043 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10044 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10045 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10046 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10047 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10048 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10049 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10050 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10051 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10052 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10053 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, MASK_DSP
),
10054 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, MASK_DSP
),
10055 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10056 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10057 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10058 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10059 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10060 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10061 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10062 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10063 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10064 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10065 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10066 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10067 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10068 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10069 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10070 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10071 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10072 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10073 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10074 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10075 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10076 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10077 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10078 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10079 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10080 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10081 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10082 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10083 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10084 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10085 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, MASK_DSP
),
10086 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, MASK_DSP
),
10087 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10088 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10089 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10090 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10091 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10092 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10093 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10094 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10095 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10096 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10097 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10098 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10099 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, MASK_DSP
),
10100 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10101 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10102 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10103 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10104 BPOSGE_BUILTIN (32, MASK_DSP
),
10106 /* The following are for the MIPS DSP ASE REV 2. */
10107 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, MASK_DSPR2
),
10108 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10109 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10110 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10111 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10112 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10113 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10114 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10115 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10116 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10117 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10118 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10119 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10120 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10121 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10122 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10123 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10124 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10125 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10126 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10127 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10128 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSPR2
),
10129 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10130 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10131 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10132 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10133 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10134 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10135 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10136 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10137 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10138 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10139 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10140 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
)
10143 static const struct mips_builtin_description mips_dsp_32only_bdesc
[] = {
10144 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10145 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10146 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10147 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10148 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10149 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10150 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10151 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10152 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10153 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10154 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10155 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10156 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10157 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10158 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10159 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10160 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10161 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10162 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10163 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10164 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10166 /* The following are for the MIPS DSP ASE REV 2. */
10167 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10168 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10169 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10170 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10171 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10172 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10173 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10174 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, MASK_DSPR2
),
10175 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, MASK_DSPR2
),
10176 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10177 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10178 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10179 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10180 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10181 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
)
10184 /* This structure describes an array of mips_builtin_description entries. */
10185 struct mips_bdesc_map
{
10186 /* The array that this entry describes. */
10187 const struct mips_builtin_description
*bdesc
;
10189 /* The number of entries in BDESC. */
10192 /* The target processor that supports the functions in BDESC.
10193 PROCESSOR_MAX means we enable them for all processors. */
10194 enum processor_type proc
;
10196 /* The functions in BDESC are not supported if any of these
10197 target flags are set. */
10198 int unsupported_target_flags
;
10201 /* All MIPS-specific built-in functions. */
10202 static const struct mips_bdesc_map mips_bdesc_arrays
[] = {
10203 { mips_ps_bdesc
, ARRAY_SIZE (mips_ps_bdesc
), PROCESSOR_MAX
, 0 },
10204 { mips_sb1_bdesc
, ARRAY_SIZE (mips_sb1_bdesc
), PROCESSOR_SB1
, 0 },
10205 { mips_dsp_bdesc
, ARRAY_SIZE (mips_dsp_bdesc
), PROCESSOR_MAX
, 0 },
10206 { mips_dsp_32only_bdesc
, ARRAY_SIZE (mips_dsp_32only_bdesc
),
10207 PROCESSOR_MAX
, MASK_64BIT
}
10210 /* MODE is a vector mode whose elements have type TYPE. Return the type
10211 of the vector itself. */
10214 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
10216 static tree types
[(int) MAX_MACHINE_MODE
];
10218 if (types
[(int) mode
] == NULL_TREE
)
10219 types
[(int) mode
] = build_vector_type_for_mode (type
, mode
);
10220 return types
[(int) mode
];
10223 /* Source-level argument types. */
10224 #define MIPS_ATYPE_VOID void_type_node
10225 #define MIPS_ATYPE_INT integer_type_node
10226 #define MIPS_ATYPE_POINTER ptr_type_node
10228 /* Standard mode-based argument types. */
10229 #define MIPS_ATYPE_SI intSI_type_node
10230 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10231 #define MIPS_ATYPE_DI intDI_type_node
10232 #define MIPS_ATYPE_SF float_type_node
10233 #define MIPS_ATYPE_DF double_type_node
10235 /* Vector argument types. */
10236 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10237 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10238 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10240 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10241 their associated MIPS_ATYPEs. */
10242 #define MIPS_FTYPE_ATYPES1(A, B) \
10243 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10245 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10246 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10248 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10249 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10251 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10252 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10255 /* Return the function type associated with function prototype TYPE. */
10258 mips_build_function_type (enum mips_function_type type
)
10260 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
10262 if (types
[(int) type
] == NULL_TREE
)
10265 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10266 case MIPS_FTYPE_NAME##NUM ARGS: \
10267 types[(int) type] \
10268 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10271 #include "config/mips/mips-ftypes.def"
10272 #undef DEF_MIPS_FTYPE
10274 gcc_unreachable ();
10277 return types
[(int) type
];
10280 /* Implement TARGET_INIT_BUILTINS. */
10283 mips_init_builtins (void)
10285 const struct mips_builtin_description
*d
;
10286 const struct mips_bdesc_map
*m
;
10287 unsigned int offset
;
10289 /* Iterate through all of the bdesc arrays, initializing all of the
10290 builtin functions. */
10292 for (m
= mips_bdesc_arrays
;
10293 m
< &mips_bdesc_arrays
[ARRAY_SIZE (mips_bdesc_arrays
)];
10296 if ((m
->proc
== PROCESSOR_MAX
|| m
->proc
== mips_arch
)
10297 && (m
->unsupported_target_flags
& target_flags
) == 0)
10298 for (d
= m
->bdesc
; d
< &m
->bdesc
[m
->size
]; d
++)
10299 if ((d
->target_flags
& target_flags
) == d
->target_flags
)
10300 add_builtin_function (d
->name
,
10301 mips_build_function_type (d
->function_type
),
10302 d
- m
->bdesc
+ offset
,
10303 BUILT_IN_MD
, NULL
, NULL
);
10308 /* Take argument ARGNO from EXP's argument list and convert it into a
10309 form suitable for input operand OPNO of instruction ICODE. Return the
10313 mips_prepare_builtin_arg (enum insn_code icode
,
10314 unsigned int opno
, tree exp
, unsigned int argno
)
10317 enum machine_mode mode
;
10319 value
= expand_normal (CALL_EXPR_ARG (exp
, argno
));
10320 mode
= insn_data
[icode
].operand
[opno
].mode
;
10321 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
10323 value
= copy_to_mode_reg (mode
, value
);
10324 /* Check the predicate again. */
10325 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
10327 error ("invalid argument to built-in function");
10335 /* Return an rtx suitable for output operand OP of instruction ICODE.
10336 If TARGET is non-null, try to use it where possible. */
10339 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
10341 enum machine_mode mode
;
10343 mode
= insn_data
[icode
].operand
[op
].mode
;
10344 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
10345 target
= gen_reg_rtx (mode
);
10350 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
10351 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
10352 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
10353 suggests a good place to put the result. */
10356 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
10359 rtx ops
[MAX_RECOG_OPERANDS
];
10362 /* Map any target to operand 0. */
10366 ops
[opno
] = mips_prepare_builtin_target (icode
, opno
, target
);
10370 /* Map the arguments to the other operands. The n_operands value
10371 for an expander includes match_dups and match_scratches as well as
10372 match_operands, so n_operands is only an upper bound on the number
10373 of arguments to the expander function. */
10374 gcc_assert (opno
+ call_expr_nargs (exp
) <= insn_data
[icode
].n_operands
);
10375 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++, opno
++)
10376 ops
[opno
] = mips_prepare_builtin_arg (icode
, opno
, exp
, argno
);
10381 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
10385 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
10389 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
10393 gcc_unreachable ();
10398 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
10399 function; TYPE says which. EXP is the CALL_EXPR that calls the
10400 function, ICODE is the instruction that should be used to compare
10401 the first two arguments, and COND is the condition it should test.
10402 TARGET, if nonnull, suggests a good place to put the result. */
10405 mips_expand_builtin_movtf (enum mips_builtin_type type
,
10406 enum insn_code icode
, enum mips_fp_condition cond
,
10407 rtx target
, tree exp
)
10409 rtx cmp_result
, op0
, op1
;
10411 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10412 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 0);
10413 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 1);
10414 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
10416 icode
= CODE_FOR_mips_cond_move_tf_ps
;
10417 target
= mips_prepare_builtin_target (icode
, 0, target
);
10418 if (type
== MIPS_BUILTIN_MOVT
)
10420 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 2);
10421 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 3);
10425 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 2);
10426 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 3);
10428 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
10432 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10433 into TARGET otherwise. Return TARGET. */
10436 mips_builtin_branch_and_move (rtx condition
, rtx target
,
10437 rtx value_if_true
, rtx value_if_false
)
10439 rtx true_label
, done_label
;
10441 true_label
= gen_label_rtx ();
10442 done_label
= gen_label_rtx ();
10444 /* First assume that CONDITION is false. */
10445 mips_emit_move (target
, value_if_false
);
10447 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10448 emit_jump_insn (gen_condjump (condition
, true_label
));
10449 emit_jump_insn (gen_jump (done_label
));
10452 /* Fix TARGET if CONDITION is true. */
10453 emit_label (true_label
);
10454 mips_emit_move (target
, value_if_true
);
10456 emit_label (done_label
);
10460 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
10461 the CALL_EXPR that calls the function, ICODE is the code of the
10462 comparison instruction, and COND is the condition it should test.
10463 TARGET, if nonnull, suggests a good place to put the boolean result. */
10466 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
10467 enum insn_code icode
, enum mips_fp_condition cond
,
10468 rtx target
, tree exp
)
10470 rtx offset
, condition
, cmp_result
, args
[MAX_RECOG_OPERANDS
];
10473 if (target
== 0 || GET_MODE (target
) != SImode
)
10474 target
= gen_reg_rtx (SImode
);
10476 /* The instruction should have a target operand, an operand for each
10477 argument, and an operand for COND. */
10478 gcc_assert (call_expr_nargs (exp
) + 2 == insn_data
[icode
].n_operands
);
10480 /* Prepare the operands to the comparison. */
10481 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10482 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
10483 args
[argno
] = mips_prepare_builtin_arg (icode
, argno
+ 1, exp
, argno
);
10485 switch (insn_data
[icode
].n_operands
)
10488 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
10493 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
10494 args
[2], args
[3], GEN_INT (cond
)));
10498 gcc_unreachable ();
10501 /* If the comparison sets more than one register, we define the result
10502 to be 0 if all registers are false and -1 if all registers are true.
10503 The value of the complete result is indeterminate otherwise. */
10504 switch (builtin_type
)
10506 case MIPS_BUILTIN_CMP_ALL
:
10507 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
10508 return mips_builtin_branch_and_move (condition
, target
,
10509 const0_rtx
, const1_rtx
);
10511 case MIPS_BUILTIN_CMP_UPPER
:
10512 case MIPS_BUILTIN_CMP_LOWER
:
10513 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
10514 condition
= gen_single_cc (cmp_result
, offset
);
10515 return mips_builtin_branch_and_move (condition
, target
,
10516 const1_rtx
, const0_rtx
);
10519 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
10520 return mips_builtin_branch_and_move (condition
, target
,
10521 const1_rtx
, const0_rtx
);
10525 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
10526 if nonnull, suggests a good place to put the boolean result. */
10529 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
10531 rtx condition
, cmp_result
;
10534 if (target
== 0 || GET_MODE (target
) != SImode
)
10535 target
= gen_reg_rtx (SImode
);
10537 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
10539 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
10544 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
10545 return mips_builtin_branch_and_move (condition
, target
,
10546 const1_rtx
, const0_rtx
);
10549 /* EXP is a CALL_EXPR that calls the function described by BDESC.
10550 Expand the call and return an rtx for its return value.
10551 TARGET, if nonnull, suggests a good place to put this value. */
10554 mips_expand_builtin_1 (const struct mips_builtin_description
*bdesc
,
10555 tree exp
, rtx target
)
10557 switch (bdesc
->builtin_type
)
10559 case MIPS_BUILTIN_DIRECT
:
10560 return mips_expand_builtin_direct (bdesc
->icode
, target
, exp
, true);
10562 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
10563 return mips_expand_builtin_direct (bdesc
->icode
, target
, exp
, false);
10565 case MIPS_BUILTIN_MOVT
:
10566 case MIPS_BUILTIN_MOVF
:
10567 return mips_expand_builtin_movtf (bdesc
->builtin_type
, bdesc
->icode
,
10568 bdesc
->cond
, target
, exp
);
10570 case MIPS_BUILTIN_CMP_ANY
:
10571 case MIPS_BUILTIN_CMP_ALL
:
10572 case MIPS_BUILTIN_CMP_UPPER
:
10573 case MIPS_BUILTIN_CMP_LOWER
:
10574 case MIPS_BUILTIN_CMP_SINGLE
:
10575 return mips_expand_builtin_compare (bdesc
->builtin_type
, bdesc
->icode
,
10576 bdesc
->cond
, target
, exp
);
10578 case MIPS_BUILTIN_BPOSGE32
:
10579 return mips_expand_builtin_bposge (bdesc
->builtin_type
, target
);
10581 gcc_unreachable ();
10584 /* Implement TARGET_EXPAND_BUILTIN. */
10587 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10588 enum machine_mode mode ATTRIBUTE_UNUSED
,
10589 int ignore ATTRIBUTE_UNUSED
)
10592 unsigned int fcode
;
10593 const struct mips_bdesc_map
*m
;
10595 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10596 fcode
= DECL_FUNCTION_CODE (fndecl
);
10599 error ("built-in function %qs not supported for MIPS16",
10600 IDENTIFIER_POINTER (DECL_NAME (fndecl
)));
10604 for (m
= mips_bdesc_arrays
;
10605 m
< &mips_bdesc_arrays
[ARRAY_SIZE (mips_bdesc_arrays
)];
10608 if (fcode
< m
->size
)
10609 return mips_expand_builtin_1 (m
->bdesc
+ fcode
, exp
, target
);
10612 gcc_unreachable ();
10615 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
10616 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10617 struct mips16_constant
{
10618 struct mips16_constant
*next
;
10621 enum machine_mode mode
;
10624 /* Information about an incomplete MIPS16 constant pool. FIRST is the
10625 first constant, HIGHEST_ADDRESS is the highest address that the first
10626 byte of the pool can have, and INSN_ADDRESS is the current instruction
10628 struct mips16_constant_pool
{
10629 struct mips16_constant
*first
;
10630 int highest_address
;
10634 /* Add constant VALUE to POOL and return its label. MODE is the
10635 value's mode (used for CONST_INTs, etc.). */
10638 mips16_add_constant (struct mips16_constant_pool
*pool
,
10639 rtx value
, enum machine_mode mode
)
10641 struct mips16_constant
**p
, *c
;
10642 bool first_of_size_p
;
10644 /* See whether the constant is already in the pool. If so, return the
10645 existing label, otherwise leave P pointing to the place where the
10646 constant should be added.
10648 Keep the pool sorted in increasing order of mode size so that we can
10649 reduce the number of alignments needed. */
10650 first_of_size_p
= true;
10651 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
10653 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
10654 return (*p
)->label
;
10655 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
10657 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
10658 first_of_size_p
= false;
10661 /* In the worst case, the constant needed by the earliest instruction
10662 will end up at the end of the pool. The entire pool must then be
10663 accessible from that instruction.
10665 When adding the first constant, set the pool's highest address to
10666 the address of the first out-of-range byte. Adjust this address
10667 downwards each time a new constant is added. */
10668 if (pool
->first
== 0)
10669 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
10670 of the instruction with the lowest two bits clear. The base PC
10671 value for LDPC has the lowest three bits clear. Assume the worst
10672 case here; namely that the PC-relative instruction occupies the
10673 last 2 bytes in an aligned word. */
10674 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
10675 pool
->highest_address
-= GET_MODE_SIZE (mode
);
10676 if (first_of_size_p
)
10677 /* Take into account the worst possible padding due to alignment. */
10678 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
10680 /* Create a new entry. */
10681 c
= XNEW (struct mips16_constant
);
10684 c
->label
= gen_label_rtx ();
10691 /* Output constant VALUE after instruction INSN and return the last
10692 instruction emitted. MODE is the mode of the constant. */
10695 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
10697 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
10699 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
10700 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
10703 if (SCALAR_FLOAT_MODE_P (mode
))
10704 return emit_insn_after (gen_consttable_float (value
), insn
);
10706 if (VECTOR_MODE_P (mode
))
10710 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
10711 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
10712 CONST_VECTOR_ELT (value
, i
), insn
);
10716 gcc_unreachable ();
10719 /* Dump out the constants in CONSTANTS after INSN. */
10722 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
10724 struct mips16_constant
*c
, *next
;
10728 for (c
= constants
; c
!= NULL
; c
= next
)
10730 /* If necessary, increase the alignment of PC. */
10731 if (align
< GET_MODE_SIZE (c
->mode
))
10733 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
10734 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
10736 align
= GET_MODE_SIZE (c
->mode
);
10738 insn
= emit_label_after (c
->label
, insn
);
10739 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
10745 emit_barrier_after (insn
);
10748 /* Return the length of instruction INSN. */
10751 mips16_insn_length (rtx insn
)
10755 rtx body
= PATTERN (insn
);
10756 if (GET_CODE (body
) == ADDR_VEC
)
10757 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
10758 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
10759 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
10761 return get_attr_length (insn
);
10764 /* If *X is a symbolic constant that refers to the constant pool, add
10765 the constant to POOL and rewrite *X to use the constant's label. */
10768 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
10770 rtx base
, offset
, label
;
10772 split_const (*x
, &base
, &offset
);
10773 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
10775 label
= mips16_add_constant (pool
, get_pool_constant (base
),
10776 get_pool_mode (base
));
10777 base
= gen_rtx_LABEL_REF (Pmode
, label
);
10778 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
10782 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10783 INSN is the instruction we're rewriting and POOL points to the current
10785 struct mips16_rewrite_pool_refs_info
{
10787 struct mips16_constant_pool
*pool
;
10790 /* Rewrite *X so that constant pool references refer to the constant's
10791 label instead. DATA points to a mips16_rewrite_pool_refs_info
10795 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
10797 struct mips16_rewrite_pool_refs_info
*info
= data
;
10799 if (force_to_mem_operand (*x
, Pmode
))
10801 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
10802 validate_change (info
->insn
, x
, mem
, false);
10807 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
10811 if (TARGET_MIPS16_TEXT_LOADS
)
10812 mips16_rewrite_pool_constant (info
->pool
, x
);
10814 return GET_CODE (*x
) == CONST
? -1 : 0;
10817 /* Build MIPS16 constant pools. */
10820 mips16_lay_out_constants (void)
10822 struct mips16_constant_pool pool
;
10823 struct mips16_rewrite_pool_refs_info info
;
10826 if (!TARGET_MIPS16_PCREL_LOADS
)
10830 memset (&pool
, 0, sizeof (pool
));
10831 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10833 /* Rewrite constant pool references in INSN. */
10838 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
10841 pool
.insn_address
+= mips16_insn_length (insn
);
10843 if (pool
.first
!= NULL
)
10845 /* If there are no natural barriers between the first user of
10846 the pool and the highest acceptable address, we'll need to
10847 create a new instruction to jump around the constant pool.
10848 In the worst case, this instruction will be 4 bytes long.
10850 If it's too late to do this transformation after INSN,
10851 do it immediately before INSN. */
10852 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
10856 label
= gen_label_rtx ();
10858 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
10859 JUMP_LABEL (jump
) = label
;
10860 LABEL_NUSES (label
) = 1;
10861 barrier
= emit_barrier_after (jump
);
10863 emit_label_after (label
, barrier
);
10864 pool
.insn_address
+= 4;
10867 /* See whether the constant pool is now out of range of the first
10868 user. If so, output the constants after the previous barrier.
10869 Note that any instructions between BARRIER and INSN (inclusive)
10870 will use negative offsets to refer to the pool. */
10871 if (pool
.insn_address
> pool
.highest_address
)
10873 mips16_emit_constants (pool
.first
, barrier
);
10877 else if (BARRIER_P (insn
))
10881 mips16_emit_constants (pool
.first
, get_last_insn ());
10884 /* A temporary variable used by for_each_rtx callbacks, etc. */
10885 static rtx mips_sim_insn
;
10887 /* A structure representing the state of the processor pipeline.
10888 Used by the mips_sim_* family of functions. */
10890 /* The maximum number of instructions that can be issued in a cycle.
10891 (Caches mips_issue_rate.) */
10892 unsigned int issue_rate
;
10894 /* The current simulation time. */
10897 /* How many more instructions can be issued in the current cycle. */
10898 unsigned int insns_left
;
10900 /* LAST_SET[X].INSN is the last instruction to set register X.
10901 LAST_SET[X].TIME is the time at which that instruction was issued.
10902 INSN is null if no instruction has yet set register X. */
10906 } last_set
[FIRST_PSEUDO_REGISTER
];
10908 /* The pipeline's current DFA state. */
10912 /* Reset STATE to the initial simulation state. */
10915 mips_sim_reset (struct mips_sim
*state
)
10918 state
->insns_left
= state
->issue_rate
;
10919 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
10920 state_reset (state
->dfa_state
);
10923 /* Initialize STATE before its first use. DFA_STATE points to an
10924 allocated but uninitialized DFA state. */
10927 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
10929 state
->issue_rate
= mips_issue_rate ();
10930 state
->dfa_state
= dfa_state
;
10931 mips_sim_reset (state
);
10934 /* Advance STATE by one clock cycle. */
10937 mips_sim_next_cycle (struct mips_sim
*state
)
10940 state
->insns_left
= state
->issue_rate
;
10941 state_transition (state
->dfa_state
, 0);
10944 /* Advance simulation state STATE until instruction INSN can read
10948 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
10950 unsigned int regno
, end_regno
;
10952 end_regno
= END_REGNO (reg
);
10953 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
10954 if (state
->last_set
[regno
].insn
!= 0)
10958 t
= (state
->last_set
[regno
].time
10959 + insn_latency (state
->last_set
[regno
].insn
, insn
));
10960 while (state
->time
< t
)
10961 mips_sim_next_cycle (state
);
10965 /* A for_each_rtx callback. If *X is a register, advance simulation state
10966 DATA until mips_sim_insn can read the register's value. */
10969 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
10972 mips_sim_wait_reg (data
, mips_sim_insn
, *x
);
10976 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
10979 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
10981 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
10984 /* Advance simulation state STATE until all of INSN's register
10985 dependencies are satisfied. */
10988 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
10990 mips_sim_insn
= insn
;
10991 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
10994 /* Advance simulation state STATE until the units required by
10995 instruction INSN are available. */
10998 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
11002 tmp_state
= alloca (state_size ());
11003 while (state
->insns_left
== 0
11004 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
11005 state_transition (tmp_state
, insn
) >= 0))
11006 mips_sim_next_cycle (state
);
11009 /* Advance simulation state STATE until INSN is ready to issue. */
11012 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
11014 mips_sim_wait_regs (state
, insn
);
11015 mips_sim_wait_units (state
, insn
);
11018 /* mips_sim_insn has just set X. Update the LAST_SET array
11019 in simulation state DATA. */
11022 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
11024 struct mips_sim
*state
;
11029 unsigned int regno
, end_regno
;
11031 end_regno
= END_REGNO (x
);
11032 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
11034 state
->last_set
[regno
].insn
= mips_sim_insn
;
11035 state
->last_set
[regno
].time
= state
->time
;
11040 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11041 can issue immediately (i.e., that mips_sim_wait_insn has already
11045 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
11047 state_transition (state
->dfa_state
, insn
);
11048 state
->insns_left
--;
11050 mips_sim_insn
= insn
;
11051 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
11054 /* Simulate issuing a NOP in state STATE. */
11057 mips_sim_issue_nop (struct mips_sim
*state
)
11059 if (state
->insns_left
== 0)
11060 mips_sim_next_cycle (state
);
11061 state
->insns_left
--;
11064 /* Update simulation state STATE so that it's ready to accept the instruction
11065 after INSN. INSN should be part of the main rtl chain, not a member of a
11069 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
11071 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11073 mips_sim_issue_nop (state
);
11075 switch (GET_CODE (SEQ_BEGIN (insn
)))
11079 /* We can't predict the processor state after a call or label. */
11080 mips_sim_reset (state
);
11084 /* The delay slots of branch likely instructions are only executed
11085 when the branch is taken. Therefore, if the caller has simulated
11086 the delay slot instruction, STATE does not really reflect the state
11087 of the pipeline for the instruction after the delay slot. Also,
11088 branch likely instructions tend to incur a penalty when not taken,
11089 so there will probably be an extra delay between the branch and
11090 the instruction after the delay slot. */
11091 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
11092 mips_sim_reset (state
);
11100 /* The VR4130 pipeline issues aligned pairs of instructions together,
11101 but it stalls the second instruction if it depends on the first.
11102 In order to cut down the amount of logic required, this dependence
11103 check is not based on a full instruction decode. Instead, any non-SPECIAL
11104 instruction is assumed to modify the register specified by bits 20-16
11105 (which is usually the "rt" field).
11107 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
11108 input, so we can end up with a false dependence between the branch
11109 and its delay slot. If this situation occurs in instruction INSN,
11110 try to avoid it by swapping rs and rt. */
11113 vr4130_avoid_branch_rt_conflict (rtx insn
)
11117 first
= SEQ_BEGIN (insn
);
11118 second
= SEQ_END (insn
);
11120 && NONJUMP_INSN_P (second
)
11121 && GET_CODE (PATTERN (first
)) == SET
11122 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
11123 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
11125 /* Check for the right kind of condition. */
11126 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
11127 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
11128 && REG_P (XEXP (cond
, 0))
11129 && REG_P (XEXP (cond
, 1))
11130 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
11131 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
11133 /* SECOND mentions the rt register but not the rs register. */
11134 rtx tmp
= XEXP (cond
, 0);
11135 XEXP (cond
, 0) = XEXP (cond
, 1);
11136 XEXP (cond
, 1) = tmp
;
11141 /* Implement -mvr4130-align. Go through each basic block and simulate the
11142 processor pipeline. If we find that a pair of instructions could execute
11143 in parallel, and the first of those instructions is not 8-byte aligned,
11144 insert a nop to make it aligned. */
11147 vr4130_align_insns (void)
11149 struct mips_sim state
;
11150 rtx insn
, subinsn
, last
, last2
, next
;
11155 /* LAST is the last instruction before INSN to have a nonzero length.
11156 LAST2 is the last such instruction before LAST. */
11160 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11163 mips_sim_init (&state
, alloca (state_size ()));
11164 for (insn
= get_insns (); insn
!= 0; insn
= next
)
11166 unsigned int length
;
11168 next
= NEXT_INSN (insn
);
11170 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11171 This isn't really related to the alignment pass, but we do it on
11172 the fly to avoid a separate instruction walk. */
11173 vr4130_avoid_branch_rt_conflict (insn
);
11175 if (USEFUL_INSN_P (insn
))
11176 FOR_EACH_SUBINSN (subinsn
, insn
)
11178 mips_sim_wait_insn (&state
, subinsn
);
11180 /* If we want this instruction to issue in parallel with the
11181 previous one, make sure that the previous instruction is
11182 aligned. There are several reasons why this isn't worthwhile
11183 when the second instruction is a call:
11185 - Calls are less likely to be performance critical,
11186 - There's a good chance that the delay slot can execute
11187 in parallel with the call.
11188 - The return address would then be unaligned.
11190 In general, if we're going to insert a nop between instructions
11191 X and Y, it's better to insert it immediately after X. That
11192 way, if the nop makes Y aligned, it will also align any labels
11193 between X and Y. */
11194 if (state
.insns_left
!= state
.issue_rate
11195 && !CALL_P (subinsn
))
11197 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
11199 /* SUBINSN is the first instruction in INSN and INSN is
11200 aligned. We want to align the previous instruction
11201 instead, so insert a nop between LAST2 and LAST.
11203 Note that LAST could be either a single instruction
11204 or a branch with a delay slot. In the latter case,
11205 LAST, like INSN, is already aligned, but the delay
11206 slot must have some extra delay that stops it from
11207 issuing at the same time as the branch. We therefore
11208 insert a nop before the branch in order to align its
11210 emit_insn_after (gen_nop (), last2
);
11213 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
11215 /* SUBINSN is the delay slot of INSN, but INSN is
11216 currently unaligned. Insert a nop between
11217 LAST and INSN to align it. */
11218 emit_insn_after (gen_nop (), last
);
11222 mips_sim_issue_insn (&state
, subinsn
);
11224 mips_sim_finish_insn (&state
, insn
);
11226 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11227 length
= get_attr_length (insn
);
11230 /* If the instruction is an asm statement or multi-instruction
11231 mips.md patern, the length is only an estimate. Insert an
11232 8 byte alignment after it so that the following instructions
11233 can be handled correctly. */
11234 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
11235 && (recog_memoized (insn
) < 0 || length
>= 8))
11237 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
11238 next
= NEXT_INSN (next
);
11239 mips_sim_next_cycle (&state
);
11242 else if (length
& 4)
11243 aligned_p
= !aligned_p
;
11248 /* See whether INSN is an aligned label. */
11249 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
11255 /* This structure records that the current function has a LO_SUM
11256 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
11257 the largest offset applied to BASE by all such LO_SUMs. */
11258 struct mips_lo_sum_offset
{
11260 HOST_WIDE_INT offset
;
11263 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
11266 mips_hash_base (rtx base
)
11268 int do_not_record_p
;
11270 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
11273 /* Hash-table callbacks for mips_lo_sum_offsets. */
11276 mips_lo_sum_offset_hash (const void *entry
)
11278 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
11282 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
11284 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
11285 (const_rtx
) value
);
11288 /* Look up symbolic constant X in HTAB, which is a hash table of
11289 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
11290 paired with a recorded LO_SUM, otherwise record X in the table. */
11293 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
11297 struct mips_lo_sum_offset
*entry
;
11299 /* Split X into a base and offset. */
11300 split_const (x
, &base
, &offset
);
11301 if (UNSPEC_ADDRESS_P (base
))
11302 base
= UNSPEC_ADDRESS (base
);
11304 /* Look up the base in the hash table. */
11305 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
11309 entry
= (struct mips_lo_sum_offset
*) *slot
;
11310 if (option
== INSERT
)
11314 entry
= XNEW (struct mips_lo_sum_offset
);
11315 entry
->base
= base
;
11316 entry
->offset
= INTVAL (offset
);
11321 if (INTVAL (offset
) > entry
->offset
)
11322 entry
->offset
= INTVAL (offset
);
11325 return INTVAL (offset
) <= entry
->offset
;
11328 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
11329 Record every LO_SUM in *LOC. */
11332 mips_record_lo_sum (rtx
*loc
, void *data
)
11334 if (GET_CODE (*loc
) == LO_SUM
)
11335 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
11339 /* Return true if INSN is a SET of an orphaned high-part relocation.
11340 HTAB is a hash table of mips_lo_sum_offsets that describes all the
11341 LO_SUMs in the current function. */
11344 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
11346 enum mips_symbol_type type
;
11349 set
= single_set (insn
);
11352 /* Check for %his. */
11354 if (GET_CODE (x
) == HIGH
11355 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
11356 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
11358 /* Check for local %gots (and %got_pages, which is redundant but OK). */
11359 if (GET_CODE (x
) == UNSPEC
11360 && XINT (x
, 1) == UNSPEC_LOAD_GOT
11361 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
11362 SYMBOL_CONTEXT_LEA
, &type
)
11363 && type
== SYMBOL_GOTOFF_PAGE
)
11364 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
11369 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
11370 INSN and a previous instruction, avoid it by inserting nops after
11373 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
11374 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
11375 before using the value of that register. *HILO_DELAY counts the
11376 number of instructions since the last hilo hazard (that is,
11377 the number of instructions since the last MFLO or MFHI).
11379 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
11380 for the next instruction.
11382 LO_REG is an rtx for the LO register, used in dependence checking. */
11385 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
11386 rtx
*delayed_reg
, rtx lo_reg
)
11391 pattern
= PATTERN (insn
);
11393 /* Do not put the whole function in .set noreorder if it contains
11394 an asm statement. We don't know whether there will be hazards
11395 between the asm statement and the gcc-generated code. */
11396 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
11397 cfun
->machine
->all_noreorder_p
= false;
11399 /* Ignore zero-length instructions (barriers and the like). */
11400 ninsns
= get_attr_length (insn
) / 4;
11404 /* Work out how many nops are needed. Note that we only care about
11405 registers that are explicitly mentioned in the instruction's pattern.
11406 It doesn't matter that calls use the argument registers or that they
11407 clobber hi and lo. */
11408 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
11409 nops
= 2 - *hilo_delay
;
11410 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
11415 /* Insert the nops between this instruction and the previous one.
11416 Each new nop takes us further from the last hilo hazard. */
11417 *hilo_delay
+= nops
;
11419 emit_insn_after (gen_hazard_nop (), after
);
11421 /* Set up the state for the next instruction. */
11422 *hilo_delay
+= ninsns
;
11424 if (INSN_CODE (insn
) >= 0)
11425 switch (get_attr_hazard (insn
))
11435 set
= single_set (insn
);
11437 *delayed_reg
= SET_DEST (set
);
11442 /* Go through the instruction stream and insert nops where necessary.
11443 Also delete any high-part relocations whose partnering low parts
11444 are now all dead. See if the whole function can then be put into
11445 .set noreorder and .set nomacro. */
11448 mips_reorg_process_insns (void)
11450 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
11454 /* Force all instructions to be split into their final form. */
11455 split_all_insns_noflow ();
11457 /* Recalculate instruction lengths without taking nops into account. */
11458 cfun
->machine
->ignore_hazard_length_p
= true;
11459 shorten_branches (get_insns ());
11461 cfun
->machine
->all_noreorder_p
= true;
11463 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
11464 if (!TARGET_EXPLICIT_RELOCS
)
11465 cfun
->machine
->all_noreorder_p
= false;
11467 /* Profiled functions can't be all noreorder because the profiler
11468 support uses assembler macros. */
11469 if (current_function_profile
)
11470 cfun
->machine
->all_noreorder_p
= false;
11472 /* Code compiled with -mfix-vr4120 can't be all noreorder because
11473 we rely on the assembler to work around some errata. */
11474 if (TARGET_FIX_VR4120
)
11475 cfun
->machine
->all_noreorder_p
= false;
11477 /* The same is true for -mfix-vr4130 if we might generate MFLO or
11478 MFHI instructions. Note that we avoid using MFLO and MFHI if
11479 the VR4130 MACC and DMACC instructions are available instead;
11480 see the *mfhilo_{si,di}_macc patterns. */
11481 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
11482 cfun
->machine
->all_noreorder_p
= false;
11484 htab
= htab_create (37, mips_lo_sum_offset_hash
,
11485 mips_lo_sum_offset_eq
, free
);
11487 /* Make a first pass over the instructions, recording all the LO_SUMs. */
11488 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
11489 FOR_EACH_SUBINSN (subinsn
, insn
)
11490 if (INSN_P (subinsn
))
11491 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
11496 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
11498 /* Make a second pass over the instructions. Delete orphaned
11499 high-part relocations or turn them into NOPs. Avoid hazards
11500 by inserting NOPs. */
11501 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
11503 next_insn
= NEXT_INSN (insn
);
11506 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
11508 /* If we find an orphaned high-part relocation in a delay
11509 slot, it's easier to turn that instruction into a NOP than
11510 to delete it. The delay slot will be a NOP either way. */
11511 FOR_EACH_SUBINSN (subinsn
, insn
)
11512 if (INSN_P (subinsn
))
11514 if (mips_orphaned_high_part_p (htab
, subinsn
))
11516 PATTERN (subinsn
) = gen_nop ();
11517 INSN_CODE (subinsn
) = CODE_FOR_nop
;
11519 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
11520 &delayed_reg
, lo_reg
);
11526 /* INSN is a single instruction. Delete it if it's an
11527 orphaned high-part relocation. */
11528 if (mips_orphaned_high_part_p (htab
, insn
))
11529 delete_insn (insn
);
11532 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
11533 &delayed_reg
, lo_reg
);
11540 htab_delete (htab
);
11543 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
11548 mips16_lay_out_constants ();
11549 if (mips_base_delayed_branch
)
11550 dbr_schedule (get_insns ());
11551 mips_reorg_process_insns ();
11552 if (TARGET_EXPLICIT_RELOCS
&& TUNE_MIPS4130
&& TARGET_VR4130_ALIGN
)
11553 vr4130_align_insns ();
11556 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
11557 in order to avoid duplicating too much logic from elsewhere. */
11560 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11561 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11564 rtx
this, temp1
, temp2
, insn
, fnaddr
;
11565 bool use_sibcall_p
;
11567 /* Pretend to be a post-reload pass while generating rtl. */
11568 reload_completed
= 1;
11570 /* Mark the end of the (empty) prologue. */
11571 emit_note (NOTE_INSN_PROLOGUE_END
);
11573 /* Determine if we can use a sibcall to call FUNCTION directly. */
11574 fnaddr
= XEXP (DECL_RTL (function
), 0);
11575 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
11576 && const_call_insn_operand (fnaddr
, Pmode
));
11578 /* Determine if we need to load FNADDR from the GOT. */
11579 if (!use_sibcall_p
)
11580 switch (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))
11582 case SYMBOL_GOT_PAGE_OFST
:
11583 case SYMBOL_GOT_DISP
:
11584 /* Pick a global pointer. Use a call-clobbered register if
11585 TARGET_CALL_SAVED_GP. */
11586 cfun
->machine
->global_pointer
=
11587 TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
11588 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11590 /* Set up the global pointer for n32 or n64 abicalls. */
11591 mips_emit_loadgp ();
11598 /* We need two temporary registers in some cases. */
11599 temp1
= gen_rtx_REG (Pmode
, 2);
11600 temp2
= gen_rtx_REG (Pmode
, 3);
11602 /* Find out which register contains the "this" pointer. */
11603 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11604 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
11606 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
11608 /* Add DELTA to THIS. */
11611 rtx offset
= GEN_INT (delta
);
11612 if (!SMALL_OPERAND (delta
))
11614 mips_emit_move (temp1
, offset
);
11617 emit_insn (gen_add3_insn (this, this, offset
));
11620 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
11621 if (vcall_offset
!= 0)
11625 /* Set TEMP1 to *THIS. */
11626 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this));
11628 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
11629 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
11631 /* Load the offset and add it to THIS. */
11632 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
11633 emit_insn (gen_add3_insn (this, this, temp1
));
11636 /* Jump to the target function. Use a sibcall if direct jumps are
11637 allowed, otherwise load the address into a register first. */
11640 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
11641 SIBLING_CALL_P (insn
) = 1;
11645 /* This is messy. GAS treats "la $25,foo" as part of a call
11646 sequence and may allow a global "foo" to be lazily bound.
11647 The general move patterns therefore reject this combination.
11649 In this context, lazy binding would actually be OK
11650 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
11651 TARGET_CALL_SAVED_GP; see mips_load_call_address.
11652 We must therefore load the address via a temporary
11653 register if mips_dangerous_for_la25_p.
11655 If we jump to the temporary register rather than $25, the assembler
11656 can use the move insn to fill the jump's delay slot. */
11657 if (TARGET_USE_PIC_FN_ADDR_REG
11658 && !mips_dangerous_for_la25_p (fnaddr
))
11659 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11660 mips_load_call_address (temp1
, fnaddr
, true);
11662 if (TARGET_USE_PIC_FN_ADDR_REG
11663 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
11664 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
11665 emit_jump_insn (gen_indirect_jump (temp1
));
11668 /* Run just enough of rest_of_compilation. This sequence was
11669 "borrowed" from alpha.c. */
11670 insn
= get_insns ();
11671 insn_locators_alloc ();
11672 split_all_insns_noflow ();
11673 mips16_lay_out_constants ();
11674 shorten_branches (insn
);
11675 final_start_function (insn
, file
, 1);
11676 final (insn
, file
, 1);
11677 final_end_function ();
11679 /* Clean up the vars set above. Note that final_end_function resets
11680 the global pointer for us. */
11681 reload_completed
= 0;
11684 /* The last argument passed to mips_set_mips16_mode, or negative if the
11685 function hasn't been called yet. */
11686 static GTY(()) int was_mips16_p
= -1;
11688 /* Set up the target-dependent global state so that it matches the
11689 current function's ISA mode. */
11692 mips_set_mips16_mode (int mips16_p
)
11694 if (mips16_p
== was_mips16_p
)
11697 /* Restore base settings of various flags. */
11698 target_flags
= mips_base_target_flags
;
11699 flag_schedule_insns
= mips_base_schedule_insns
;
11700 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
11701 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
11702 align_loops
= mips_base_align_loops
;
11703 align_jumps
= mips_base_align_jumps
;
11704 align_functions
= mips_base_align_functions
;
11708 /* Switch to MIPS16 mode. */
11709 target_flags
|= MASK_MIPS16
;
11711 /* Don't run the scheduler before reload, since it tends to
11712 increase register pressure. */
11713 flag_schedule_insns
= 0;
11715 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
11716 the whole function to be in a single section. */
11717 flag_reorder_blocks_and_partition
= 0;
11719 /* Don't move loop invariants, because it tends to increase
11720 register pressure. It also introduces an extra move in cases
11721 where the constant is the first operand in a two-operand binary
11722 instruction, or when it forms a register argument to a functon
11724 flag_move_loop_invariants
= 0;
11726 /* Silently disable -mexplicit-relocs since it doesn't apply
11727 to MIPS16 code. Even so, it would overly pedantic to warn
11728 about "-mips16 -mexplicit-relocs", especially given that
11729 we use a %gprel() operator. */
11730 target_flags
&= ~MASK_EXPLICIT_RELOCS
;
11732 /* Experiments suggest we get the best overall section-anchor
11733 results from using the range of an unextended LW or SW. Code
11734 that makes heavy use of byte or short accesses can do better
11735 with ranges of 0...31 and 0...63 respectively, but most code is
11736 sensitive to the range of LW and SW instead. */
11737 targetm
.min_anchor_offset
= 0;
11738 targetm
.max_anchor_offset
= 127;
11740 if (flag_pic
|| TARGET_ABICALLS
)
11741 sorry ("MIPS16 PIC");
11743 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
11744 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
11748 /* Switch to normal (non-MIPS16) mode. */
11749 target_flags
&= ~MASK_MIPS16
;
11751 /* Provide default values for align_* for 64-bit targets. */
11754 if (align_loops
== 0)
11756 if (align_jumps
== 0)
11758 if (align_functions
== 0)
11759 align_functions
= 8;
11762 targetm
.min_anchor_offset
= -32768;
11763 targetm
.max_anchor_offset
= 32767;
11766 /* (Re)initialize MIPS target internals for new ISA. */
11767 mips_init_relocs ();
11769 if (was_mips16_p
>= 0)
11770 /* Reinitialize target-dependent state. */
11773 was_mips16_p
= mips16_p
;
11776 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
11777 function should use the MIPS16 ISA and switch modes accordingly. */
11780 mips_set_current_function (tree fndecl
)
11782 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
11785 /* Allocate a chunk of memory for per-function machine-dependent data. */
11787 static struct machine_function
*
11788 mips_init_machine_status (void)
11790 return ((struct machine_function
*)
11791 ggc_alloc_cleared (sizeof (struct machine_function
)));
11794 /* Return the processor associated with the given ISA level, or null
11795 if the ISA isn't valid. */
11797 static const struct mips_cpu_info
*
11798 mips_cpu_info_from_isa (int isa
)
11802 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
11803 if (mips_cpu_info_table
[i
].isa
== isa
)
11804 return mips_cpu_info_table
+ i
;
11809 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
11810 with a final "000" replaced by "k". Ignore case.
11812 Note: this function is shared between GCC and GAS. */
11815 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
11817 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
11818 given
++, canonical
++;
11820 return ((*given
== 0 && *canonical
== 0)
11821 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
11824 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
11825 CPU name. We've traditionally allowed a lot of variation here.
11827 Note: this function is shared between GCC and GAS. */
11830 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
11832 /* First see if the name matches exactly, or with a final "000"
11833 turned into "k". */
11834 if (mips_strict_matching_cpu_name_p (canonical
, given
))
11837 /* If not, try comparing based on numerical designation alone.
11838 See if GIVEN is an unadorned number, or 'r' followed by a number. */
11839 if (TOLOWER (*given
) == 'r')
11841 if (!ISDIGIT (*given
))
11844 /* Skip over some well-known prefixes in the canonical name,
11845 hoping to find a number there too. */
11846 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
11848 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
11850 else if (TOLOWER (canonical
[0]) == 'r')
11853 return mips_strict_matching_cpu_name_p (canonical
, given
);
11856 /* Return the mips_cpu_info entry for the processor or ISA given
11857 by CPU_STRING. Return null if the string isn't recognized.
11859 A similar function exists in GAS. */
11861 static const struct mips_cpu_info
*
11862 mips_parse_cpu (const char *cpu_string
)
11867 /* In the past, we allowed upper-case CPU names, but it doesn't
11868 work well with the multilib machinery. */
11869 for (s
= cpu_string
; *s
!= 0; s
++)
11872 warning (0, "CPU names must be lower case");
11876 /* 'from-abi' selects the most compatible architecture for the given
11877 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
11878 EABIs, we have to decide whether we're using the 32-bit or 64-bit
11880 if (strcasecmp (cpu_string
, "from-abi") == 0)
11881 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
11882 : ABI_NEEDS_64BIT_REGS
? 3
11883 : (TARGET_64BIT
? 3 : 1));
11885 /* 'default' has traditionally been a no-op. Probably not very useful. */
11886 if (strcasecmp (cpu_string
, "default") == 0)
11889 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
11890 if (mips_matching_cpu_name_p (mips_cpu_info_table
[i
].name
, cpu_string
))
11891 return mips_cpu_info_table
+ i
;
11896 /* Set up globals to generate code for the ISA or processor
11897 described by INFO. */
11900 mips_set_architecture (const struct mips_cpu_info
*info
)
11904 mips_arch_info
= info
;
11905 mips_arch
= info
->cpu
;
11906 mips_isa
= info
->isa
;
11910 /* Likewise for tuning. */
11913 mips_set_tune (const struct mips_cpu_info
*info
)
11917 mips_tune_info
= info
;
11918 mips_tune
= info
->cpu
;
11922 /* Implement TARGET_HANDLE_OPTION. */
11925 mips_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
11930 if (strcmp (arg
, "32") == 0)
11932 else if (strcmp (arg
, "o64") == 0)
11933 mips_abi
= ABI_O64
;
11934 else if (strcmp (arg
, "n32") == 0)
11935 mips_abi
= ABI_N32
;
11936 else if (strcmp (arg
, "64") == 0)
11938 else if (strcmp (arg
, "eabi") == 0)
11939 mips_abi
= ABI_EABI
;
11946 return mips_parse_cpu (arg
) != 0;
11949 mips_isa_option_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
11950 return mips_isa_option_info
!= 0;
11952 case OPT_mno_flush_func
:
11953 mips_cache_flush_func
= NULL
;
11956 case OPT_mcode_readable_
:
11957 if (strcmp (arg
, "yes") == 0)
11958 mips_code_readable
= CODE_READABLE_YES
;
11959 else if (strcmp (arg
, "pcrel") == 0)
11960 mips_code_readable
= CODE_READABLE_PCREL
;
11961 else if (strcmp (arg
, "no") == 0)
11962 mips_code_readable
= CODE_READABLE_NO
;
11972 /* Implement OVERRIDE_OPTIONS. */
11975 mips_override_options (void)
11977 int i
, start
, regno
, mode
;
11979 #ifdef SUBTARGET_OVERRIDE_OPTIONS
11980 SUBTARGET_OVERRIDE_OPTIONS
;
11983 /* Set the small data limit. */
11984 mips_small_data_threshold
= (g_switch_set
11986 : MIPS_DEFAULT_GVALUE
);
11988 /* The following code determines the architecture and register size.
11989 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
11990 The GAS and GCC code should be kept in sync as much as possible. */
11992 if (mips_arch_string
!= 0)
11993 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
11995 if (mips_isa_option_info
!= 0)
11997 if (mips_arch_info
== 0)
11998 mips_set_architecture (mips_isa_option_info
);
11999 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
12000 error ("%<-%s%> conflicts with the other architecture options, "
12001 "which specify a %s processor",
12002 mips_isa_option_info
->name
,
12003 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
12006 if (mips_arch_info
== 0)
12008 #ifdef MIPS_CPU_STRING_DEFAULT
12009 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
12011 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
12015 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
12016 error ("%<-march=%s%> is not compatible with the selected ABI",
12017 mips_arch_info
->name
);
12019 /* Optimize for mips_arch, unless -mtune selects a different processor. */
12020 if (mips_tune_string
!= 0)
12021 mips_set_tune (mips_parse_cpu (mips_tune_string
));
12023 if (mips_tune_info
== 0)
12024 mips_set_tune (mips_arch_info
);
12026 if ((target_flags_explicit
& MASK_64BIT
) != 0)
12028 /* The user specified the size of the integer registers. Make sure
12029 it agrees with the ABI and ISA. */
12030 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
12031 error ("%<-mgp64%> used with a 32-bit processor");
12032 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
12033 error ("%<-mgp32%> used with a 64-bit ABI");
12034 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
12035 error ("%<-mgp64%> used with a 32-bit ABI");
12039 /* Infer the integer register size from the ABI and processor.
12040 Restrict ourselves to 32-bit registers if that's all the
12041 processor has, or if the ABI cannot handle 64-bit registers. */
12042 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
12043 target_flags
&= ~MASK_64BIT
;
12045 target_flags
|= MASK_64BIT
;
12048 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
12050 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
12051 error ("unsupported combination: %s", "-mfp64 -msingle-float");
12052 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
12053 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
12054 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
12056 if (!ISA_HAS_MXHC1
)
12057 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
12058 " the target supports the mfhc1 and mthc1 instructions");
12059 else if (mips_abi
!= ABI_32
)
12060 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
12066 /* -msingle-float selects 32-bit float registers. Otherwise the
12067 float registers should be the same size as the integer ones. */
12068 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
12069 target_flags
|= MASK_FLOAT64
;
12071 target_flags
&= ~MASK_FLOAT64
;
12074 /* End of code shared with GAS. */
12076 /* If no -mlong* option was given, infer it from the other options. */
12077 if ((target_flags_explicit
& MASK_LONG64
) == 0)
12079 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
12080 target_flags
|= MASK_LONG64
;
12082 target_flags
&= ~MASK_LONG64
;
12085 if (!TARGET_OLDABI
)
12086 flag_pcc_struct_return
= 0;
12088 /* Decide which rtx_costs structure to use. */
12090 mips_cost
= &mips_rtx_cost_optimize_size
;
12092 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
12094 /* If the user hasn't specified a branch cost, use the processor's
12096 if (mips_branch_cost
== 0)
12097 mips_branch_cost
= mips_cost
->branch_cost
;
12099 /* If neither -mbranch-likely nor -mno-branch-likely was given
12100 on the command line, set MASK_BRANCHLIKELY based on the target
12101 architecture and tuning flags. Annulled delay slots are a
12102 size win, so we only consider the processor-specific tuning
12103 for !optimize_size. */
12104 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
12106 if (ISA_HAS_BRANCHLIKELY
12108 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
12109 target_flags
|= MASK_BRANCHLIKELY
;
12111 target_flags
&= ~MASK_BRANCHLIKELY
;
12113 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
12114 warning (0, "the %qs architecture does not support branch-likely"
12115 " instructions", mips_arch_info
->name
);
12117 /* The effect of -mabicalls isn't defined for the EABI. */
12118 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
12120 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12121 target_flags
&= ~MASK_ABICALLS
;
12124 /* MIPS16 cannot generate PIC yet. */
12125 if (TARGET_MIPS16
&& (flag_pic
|| TARGET_ABICALLS
))
12127 sorry ("MIPS16 PIC");
12128 target_flags
&= ~MASK_ABICALLS
;
12129 flag_pic
= flag_pie
= flag_shlib
= 0;
12132 if (TARGET_ABICALLS
)
12133 /* We need to set flag_pic for executables as well as DSOs
12134 because we may reference symbols that are not defined in
12135 the final executable. (MIPS does not use things like
12136 copy relocs, for example.)
12138 Also, there is a body of code that uses __PIC__ to distinguish
12139 between -mabicalls and -mno-abicalls code. */
12142 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12143 faster code, but at the expense of more nops. Enable it at -O3 and
12145 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
12146 target_flags
|= MASK_VR4130_ALIGN
;
12148 /* Prefer a call to memcpy over inline code when optimizing for size,
12149 though see MOVE_RATIO in mips.h. */
12150 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
12151 target_flags
|= MASK_MEMCPY
;
12153 /* If we have a nonzero small-data limit, check that the -mgpopt
12154 setting is consistent with the other target flags. */
12155 if (mips_small_data_threshold
> 0)
12159 if (!TARGET_MIPS16
&& !TARGET_EXPLICIT_RELOCS
)
12160 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12162 TARGET_LOCAL_SDATA
= false;
12163 TARGET_EXTERN_SDATA
= false;
12167 if (TARGET_VXWORKS_RTP
)
12168 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12170 if (TARGET_ABICALLS
)
12171 warning (0, "cannot use small-data accesses for %qs",
12176 #ifdef MIPS_TFMODE_FORMAT
12177 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
12180 /* Make sure that the user didn't turn off paired single support when
12181 MIPS-3D support is requested. */
12183 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
12184 && !TARGET_PAIRED_SINGLE_FLOAT
)
12185 error ("%<-mips3d%> requires %<-mpaired-single%>");
12187 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12189 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
12191 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12192 and TARGET_HARD_FLOAT_ABI are both true. */
12193 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
12194 error ("%qs must be used with %qs",
12195 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
12196 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
12198 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12200 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
12201 warning (0, "the %qs architecture does not support paired-single"
12202 " instructions", mips_arch_info
->name
);
12204 /* If TARGET_DSPR2, enable MASK_DSP. */
12206 target_flags
|= MASK_DSP
;
12208 mips_init_print_operand_punct ();
12210 /* Set up array to map GCC register number to debug register number.
12211 Ignore the special purpose register numbers. */
12213 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12215 mips_dbx_regno
[i
] = INVALID_REGNUM
;
12216 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
12217 mips_dwarf_regno
[i
] = i
;
12219 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
12222 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
12223 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
12224 mips_dbx_regno
[i
] = i
+ start
;
12226 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
12227 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
12228 mips_dbx_regno
[i
] = i
+ start
;
12230 /* Accumulator debug registers use big-endian ordering. */
12231 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
12232 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
12233 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
12234 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
12235 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
12237 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
12238 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
12241 /* Set up mips_hard_regno_mode_ok. */
12242 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
12243 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12244 mips_hard_regno_mode_ok
[(int)mode
][regno
]
12245 = mips_hard_regno_mode_ok_p (regno
, mode
);
12247 /* Function to allocate machine-dependent function status. */
12248 init_machine_status
= &mips_init_machine_status
;
12250 /* Default to working around R4000 errata only if the processor
12251 was selected explicitly. */
12252 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
12253 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
12254 target_flags
|= MASK_FIX_R4000
;
12256 /* Default to working around R4400 errata only if the processor
12257 was selected explicitly. */
12258 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
12259 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
12260 target_flags
|= MASK_FIX_R4400
;
12262 /* Save base state of options. */
12263 mips_base_mips16
= TARGET_MIPS16
;
12264 mips_base_target_flags
= target_flags
;
12265 mips_base_delayed_branch
= flag_delayed_branch
;
12266 mips_base_schedule_insns
= flag_schedule_insns
;
12267 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
12268 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
12269 mips_base_align_loops
= align_loops
;
12270 mips_base_align_jumps
= align_jumps
;
12271 mips_base_align_functions
= align_functions
;
12273 /* Now select the ISA mode. */
12274 mips_set_mips16_mode (mips_base_mips16
);
12276 /* We call dbr_schedule from within mips_reorg. */
12277 flag_delayed_branch
= 0;
12280 /* Swap the register information for registers I and I + 1, which
12281 currently have the wrong endianness. Note that the registers'
12282 fixedness and call-clobberedness might have been set on the
12286 mips_swap_registers (unsigned int i
)
12291 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12292 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12294 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
12295 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
12296 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
12297 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
12303 /* Implement CONDITIONAL_REGISTER_USAGE. */
12306 mips_conditional_register_usage (void)
12312 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
12313 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12315 if (!TARGET_HARD_FLOAT
)
12319 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
12320 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12321 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
12322 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12324 else if (! ISA_HAS_8CC
)
12328 /* We only have a single condition-code register. We implement
12329 this by fixing all the condition-code registers and generating
12330 RTL that refers directly to ST_REG_FIRST. */
12331 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
12332 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12334 /* In MIPS16 mode, we permit the $t temporary registers to be used
12335 for reload. We prohibit the unused $s registers, since they
12336 are call-saved, and saving them via a MIPS16 register would
12337 probably waste more time than just reloading the value. */
12340 fixed_regs
[18] = call_used_regs
[18] = 1;
12341 fixed_regs
[19] = call_used_regs
[19] = 1;
12342 fixed_regs
[20] = call_used_regs
[20] = 1;
12343 fixed_regs
[21] = call_used_regs
[21] = 1;
12344 fixed_regs
[22] = call_used_regs
[22] = 1;
12345 fixed_regs
[23] = call_used_regs
[23] = 1;
12346 fixed_regs
[26] = call_used_regs
[26] = 1;
12347 fixed_regs
[27] = call_used_regs
[27] = 1;
12348 fixed_regs
[30] = call_used_regs
[30] = 1;
12350 /* $f20-$f23 are call-clobbered for n64. */
12351 if (mips_abi
== ABI_64
)
12354 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
12355 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
12357 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
12359 if (mips_abi
== ABI_N32
)
12362 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
12363 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
12365 /* Make sure that double-register accumulator values are correctly
12366 ordered for the current endianness. */
12367 if (TARGET_LITTLE_ENDIAN
)
12369 unsigned int regno
;
12371 mips_swap_registers (MD_REG_FIRST
);
12372 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
12373 mips_swap_registers (regno
);
12377 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
12378 other registers for instructions for which it is possible. This
12379 encourages the compiler to use CMP in cases where an XOR would
12380 require some register shuffling. */
12383 mips_order_regs_for_local_alloc (void)
12387 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12388 reg_alloc_order
[i
] = i
;
12392 /* It really doesn't matter where we put register 0, since it is
12393 a fixed register anyhow. */
12394 reg_alloc_order
[0] = 24;
12395 reg_alloc_order
[24] = 0;
12399 /* Initialize the GCC target structure. */
12400 #undef TARGET_ASM_ALIGNED_HI_OP
12401 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
12402 #undef TARGET_ASM_ALIGNED_SI_OP
12403 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
12404 #undef TARGET_ASM_ALIGNED_DI_OP
12405 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
12407 #undef TARGET_ASM_FUNCTION_PROLOGUE
12408 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
12409 #undef TARGET_ASM_FUNCTION_EPILOGUE
12410 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
12411 #undef TARGET_ASM_SELECT_RTX_SECTION
12412 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
12413 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
12414 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
12416 #undef TARGET_SCHED_INIT
12417 #define TARGET_SCHED_INIT mips_sched_init
12418 #undef TARGET_SCHED_REORDER
12419 #define TARGET_SCHED_REORDER mips_sched_reorder
12420 #undef TARGET_SCHED_REORDER2
12421 #define TARGET_SCHED_REORDER2 mips_sched_reorder
12422 #undef TARGET_SCHED_VARIABLE_ISSUE
12423 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
12424 #undef TARGET_SCHED_ADJUST_COST
12425 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
12426 #undef TARGET_SCHED_ISSUE_RATE
12427 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
12428 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12429 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12430 mips_multipass_dfa_lookahead
12432 #undef TARGET_DEFAULT_TARGET_FLAGS
12433 #define TARGET_DEFAULT_TARGET_FLAGS \
12435 | TARGET_CPU_DEFAULT \
12436 | TARGET_ENDIAN_DEFAULT \
12437 | TARGET_FP_EXCEPTIONS_DEFAULT \
12438 | MASK_CHECK_ZERO_DIV \
12440 #undef TARGET_HANDLE_OPTION
12441 #define TARGET_HANDLE_OPTION mips_handle_option
12443 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12444 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
12446 #undef TARGET_INSERT_ATTRIBUTES
12447 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
12448 #undef TARGET_MERGE_DECL_ATTRIBUTES
12449 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
12450 #undef TARGET_SET_CURRENT_FUNCTION
12451 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
12453 #undef TARGET_VALID_POINTER_MODE
12454 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
12455 #undef TARGET_RTX_COSTS
12456 #define TARGET_RTX_COSTS mips_rtx_costs
12457 #undef TARGET_ADDRESS_COST
12458 #define TARGET_ADDRESS_COST mips_address_cost
12460 #undef TARGET_IN_SMALL_DATA_P
12461 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
12463 #undef TARGET_MACHINE_DEPENDENT_REORG
12464 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
12466 #undef TARGET_ASM_FILE_START
12467 #define TARGET_ASM_FILE_START mips_file_start
12468 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12469 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12471 #undef TARGET_INIT_LIBFUNCS
12472 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
12474 #undef TARGET_BUILD_BUILTIN_VA_LIST
12475 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
12476 #undef TARGET_EXPAND_BUILTIN_VA_START
12477 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
12478 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12479 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
12481 #undef TARGET_PROMOTE_FUNCTION_ARGS
12482 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
12483 #undef TARGET_PROMOTE_FUNCTION_RETURN
12484 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
12485 #undef TARGET_PROMOTE_PROTOTYPES
12486 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
12488 #undef TARGET_RETURN_IN_MEMORY
12489 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
12490 #undef TARGET_RETURN_IN_MSB
12491 #define TARGET_RETURN_IN_MSB mips_return_in_msb
12493 #undef TARGET_ASM_OUTPUT_MI_THUNK
12494 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
12495 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12496 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12498 #undef TARGET_SETUP_INCOMING_VARARGS
12499 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
12500 #undef TARGET_STRICT_ARGUMENT_NAMING
12501 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
12502 #undef TARGET_MUST_PASS_IN_STACK
12503 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12504 #undef TARGET_PASS_BY_REFERENCE
12505 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
12506 #undef TARGET_CALLEE_COPIES
12507 #define TARGET_CALLEE_COPIES mips_callee_copies
12508 #undef TARGET_ARG_PARTIAL_BYTES
12509 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
12511 #undef TARGET_MODE_REP_EXTENDED
12512 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
12514 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12515 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
12517 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12518 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
12520 #undef TARGET_INIT_BUILTINS
12521 #define TARGET_INIT_BUILTINS mips_init_builtins
12522 #undef TARGET_EXPAND_BUILTIN
12523 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
12525 #undef TARGET_HAVE_TLS
12526 #define TARGET_HAVE_TLS HAVE_AS_TLS
12528 #undef TARGET_CANNOT_FORCE_CONST_MEM
12529 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
12531 #undef TARGET_ENCODE_SECTION_INFO
12532 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
12534 #undef TARGET_ATTRIBUTE_TABLE
12535 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
12536 /* All our function attributes are related to how out-of-line copies should
12537 be compiled or called. They don't in themselves prevent inlining. */
12538 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
12539 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
12541 #undef TARGET_EXTRA_LIVE_ON_ENTRY
12542 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
12544 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12545 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
12546 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
12547 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
12549 #undef TARGET_COMP_TYPE_ATTRIBUTES
12550 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
12552 #ifdef HAVE_AS_DTPRELWORD
12553 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12554 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
12556 #undef TARGET_DWARF_REGISTER_SPAN
12557 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
12559 struct gcc_target targetm
= TARGET_INITIALIZER
;
12561 #include "gt-mips.h"