1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* The integrated register allocator (IRA) is a
22 regional register allocator performing graph coloring on a top-down
23 traversal of nested regions. Graph coloring in a region is based
24 on Chaitin-Briggs algorithm. It is called integrated because
25 register coalescing, register live range splitting, and choosing a
26 better hard register are done on-the-fly during coloring. Register
27 coalescing and choosing a cheaper hard register is done by hard
28 register preferencing during hard register assigning. The live
29 range splitting is a byproduct of the regional register allocation.
31 Major IRA notions are:
33 o *Region* is a part of CFG where graph coloring based on
34 Chaitin-Briggs algorithm is done. IRA can work on any set of
35 nested CFG regions forming a tree. Currently the regions are
36 the entire function for the root region and natural loops for
37 the other regions. Therefore data structure representing a
38 region is called loop_tree_node.
40 o *Allocno class* is a register class used for allocation of
41 given allocno. It means that only hard register of given
42 register class can be assigned to given allocno. In reality,
43 even smaller subset of (*profitable*) hard registers can be
44 assigned. In rare cases, the subset can be even smaller
45 because our modification of Chaitin-Briggs algorithm requires
46 that sets of hard registers can be assigned to allocnos forms a
47 forest, i.e. the sets can be ordered in a way where any
48 previous set is not intersected with given set or is a superset
51 o *Pressure class* is a register class belonging to a set of
52 register classes containing all of the hard-registers available
53 for register allocation. The set of all pressure classes for a
54 target is defined in the corresponding machine-description file
55 according some criteria. Register pressure is calculated only
56 for pressure classes and it affects some IRA decisions as
57 forming allocation regions.
59 o *Allocno* represents the live range of a pseudo-register in a
60 region. Besides the obvious attributes like the corresponding
61 pseudo-register number, allocno class, conflicting allocnos and
62 conflicting hard-registers, there are a few allocno attributes
63 which are important for understanding the allocation algorithm:
65 - *Live ranges*. This is a list of ranges of *program points*
66 where the allocno lives. Program points represent places
67 where a pseudo can be born or become dead (there are
68 approximately two times more program points than the insns)
69 and they are represented by integers starting with 0. The
70 live ranges are used to find conflicts between allocnos.
71 They also play very important role for the transformation of
72 the IRA internal representation of several regions into a one
73 region representation. The later is used during the reload
74 pass work because each allocno represents all of the
75 corresponding pseudo-registers.
77 - *Hard-register costs*. This is a vector of size equal to the
78 number of available hard-registers of the allocno class. The
79 cost of a callee-clobbered hard-register for an allocno is
80 increased by the cost of save/restore code around the calls
81 through the given allocno's life. If the allocno is a move
82 instruction operand and another operand is a hard-register of
83 the allocno class, the cost of the hard-register is decreased
86 When an allocno is assigned, the hard-register with minimal
87 full cost is used. Initially, a hard-register's full cost is
88 the corresponding value from the hard-register's cost vector.
89 If the allocno is connected by a *copy* (see below) to
90 another allocno which has just received a hard-register, the
91 cost of the hard-register is decreased. Before choosing a
92 hard-register for an allocno, the allocno's current costs of
93 the hard-registers are modified by the conflict hard-register
94 costs of all of the conflicting allocnos which are not
97 - *Conflict hard-register costs*. This is a vector of the same
98 size as the hard-register costs vector. To permit an
99 unassigned allocno to get a better hard-register, IRA uses
100 this vector to calculate the final full cost of the
101 available hard-registers. Conflict hard-register costs of an
102 unassigned allocno are also changed with a change of the
103 hard-register cost of the allocno when a copy involving the
104 allocno is processed as described above. This is done to
105 show other unassigned allocnos that a given allocno prefers
106 some hard-registers in order to remove the move instruction
107 corresponding to the copy.
109 o *Cap*. If a pseudo-register does not live in a region but
110 lives in a nested region, IRA creates a special allocno called
111 a cap in the outer region. A region cap is also created for a
114 o *Copy*. Allocnos can be connected by copies. Copies are used
115 to modify hard-register costs for allocnos during coloring.
116 Such modifications reflects a preference to use the same
117 hard-register for the allocnos connected by copies. Usually
118 copies are created for move insns (in this case it results in
119 register coalescing). But IRA also creates copies for operands
120 of an insn which should be assigned to the same hard-register
121 due to constraints in the machine description (it usually
122 results in removing a move generated in reload to satisfy
123 the constraints) and copies referring to the allocno which is
124 the output operand of an instruction and the allocno which is
125 an input operand dying in the instruction (creation of such
126 copies results in less register shuffling). IRA *does not*
127 create copies between the same register allocnos from different
128 regions because we use another technique for propagating
129 hard-register preference on the borders of regions.
131 Allocnos (including caps) for the upper region in the region tree
132 *accumulate* information important for coloring from allocnos with
133 the same pseudo-register from nested regions. This includes
134 hard-register and memory costs, conflicts with hard-registers,
135 allocno conflicts, allocno copies and more. *Thus, attributes for
136 allocnos in a region have the same values as if the region had no
137 subregions*. It means that attributes for allocnos in the
138 outermost region corresponding to the function have the same values
139 as though the allocation used only one region which is the entire
140 function. It also means that we can look at IRA work as if the
141 first IRA did allocation for all function then it improved the
142 allocation for loops then their subloops and so on.
144 IRA major passes are:
146 o Building IRA internal representation which consists of the
149 * First, IRA builds regions and creates allocnos (file
150 ira-build.c) and initializes most of their attributes.
152 * Then IRA finds an allocno class for each allocno and
153 calculates its initial (non-accumulated) cost of memory and
154 each hard-register of its allocno class (file ira-cost.c).
156 * IRA creates live ranges of each allocno, calulates register
157 pressure for each pressure class in each region, sets up
158 conflict hard registers for each allocno and info about calls
159 the allocno lives through (file ira-lives.c).
161 * IRA removes low register pressure loops from the regions
162 mostly to speed IRA up (file ira-build.c).
164 * IRA propagates accumulated allocno info from lower region
165 allocnos to corresponding upper region allocnos (file
168 * IRA creates all caps (file ira-build.c).
170 * Having live-ranges of allocnos and their classes, IRA creates
171 conflicting allocnos for each allocno. Conflicting allocnos
172 are stored as a bit vector or array of pointers to the
173 conflicting allocnos whatever is more profitable (file
174 ira-conflicts.c). At this point IRA creates allocno copies.
176 o Coloring. Now IRA has all necessary info to start graph coloring
177 process. It is done in each region on top-down traverse of the
178 region tree (file ira-color.c). There are following subpasses:
180 * Finding profitable hard registers of corresponding allocno
181 class for each allocno. For example, only callee-saved hard
182 registers are frequently profitable for allocnos living
183 through colors. If the profitable hard register set of
184 allocno does not form a tree based on subset relation, we use
185 some approximation to form the tree. This approximation is
186 used to figure out trivial colorability of allocnos. The
187 approximation is a pretty rare case.
189 * Putting allocnos onto the coloring stack. IRA uses Briggs
190 optimistic coloring which is a major improvement over
191 Chaitin's coloring. Therefore IRA does not spill allocnos at
192 this point. There is some freedom in the order of putting
193 allocnos on the stack which can affect the final result of
194 the allocation. IRA uses some heuristics to improve the
195 order. The major one is to form *threads* from colorable
196 allocnos and push them on the stack by threads. Thread is a
197 set of non-conflicting colorable allocnos connected by
198 copies. The thread contains allocnos from the colorable
199 bucket or colorable allocnos already pushed onto the coloring
200 stack. Pushing thread allocnos one after another onto the
201 stack increases chances of removing copies when the allocnos
202 get the same hard reg.
204 We also use a modification of Chaitin-Briggs algorithm which
205 works for intersected register classes of allocnos. To
206 figure out trivial colorability of allocnos, the mentioned
207 above tree of hard register sets is used. To get an idea how
208 the algorithm works in i386 example, let us consider an
209 allocno to which any general hard register can be assigned.
210 If the allocno conflicts with eight allocnos to which only
211 EAX register can be assigned, given allocno is still
212 trivially colorable because all conflicting allocnos might be
213 assigned only to EAX and all other general hard registers are
216 To get an idea of the used trivial colorability criterion, it
217 is also useful to read article "Graph-Coloring Register
218 Allocation for Irregular Architectures" by Michael D. Smith
219 and Glen Holloway. Major difference between the article
220 approach and approach used in IRA is that Smith's approach
221 takes register classes only from machine description and IRA
222 calculate register classes from intermediate code too
223 (e.g. an explicit usage of hard registers in RTL code for
224 parameter passing can result in creation of additional
225 register classes which contain or exclude the hard
226 registers). That makes IRA approach useful for improving
227 coloring even for architectures with regular register files
228 and in fact some benchmarking shows the improvement for
229 regular class architectures is even bigger than for irregular
230 ones. Another difference is that Smith's approach chooses
231 intersection of classes of all insn operands in which a given
232 pseudo occurs. IRA can use bigger classes if it is still
233 more profitable than memory usage.
235 * Popping the allocnos from the stack and assigning them hard
236 registers. If IRA can not assign a hard register to an
237 allocno and the allocno is coalesced, IRA undoes the
238 coalescing and puts the uncoalesced allocnos onto the stack in
239 the hope that some such allocnos will get a hard register
240 separately. If IRA fails to assign hard register or memory
241 is more profitable for it, IRA spills the allocno. IRA
242 assigns the allocno the hard-register with minimal full
243 allocation cost which reflects the cost of usage of the
244 hard-register for the allocno and cost of usage of the
245 hard-register for allocnos conflicting with given allocno.
247 * Chaitin-Briggs coloring assigns as many pseudos as possible
248 to hard registers. After coloringh we try to improve
249 allocation with cost point of view. We improve the
250 allocation by spilling some allocnos and assigning the freed
251 hard registers to other allocnos if it decreases the overall
254 * After allocno assigning in the region, IRA modifies the hard
255 register and memory costs for the corresponding allocnos in
256 the subregions to reflect the cost of possible loads, stores,
257 or moves on the border of the region and its subregions.
258 When default regional allocation algorithm is used
259 (-fira-algorithm=mixed), IRA just propagates the assignment
260 for allocnos if the register pressure in the region for the
261 corresponding pressure class is less than number of available
262 hard registers for given pressure class.
264 o Spill/restore code moving. When IRA performs an allocation
265 by traversing regions in top-down order, it does not know what
266 happens below in the region tree. Therefore, sometimes IRA
267 misses opportunities to perform a better allocation. A simple
268 optimization tries to improve allocation in a region having
269 subregions and containing in another region. If the
270 corresponding allocnos in the subregion are spilled, it spills
271 the region allocno if it is profitable. The optimization
272 implements a simple iterative algorithm performing profitable
273 transformations while they are still possible. It is fast in
274 practice, so there is no real need for a better time complexity
277 o Code change. After coloring, two allocnos representing the
278 same pseudo-register outside and inside a region respectively
279 may be assigned to different locations (hard-registers or
280 memory). In this case IRA creates and uses a new
281 pseudo-register inside the region and adds code to move allocno
282 values on the region's borders. This is done during top-down
283 traversal of the regions (file ira-emit.c). In some
284 complicated cases IRA can create a new allocno to move allocno
285 values (e.g. when a swap of values stored in two hard-registers
286 is needed). At this stage, the new allocno is marked as
287 spilled. IRA still creates the pseudo-register and the moves
288 on the region borders even when both allocnos were assigned to
289 the same hard-register. If the reload pass spills a
290 pseudo-register for some reason, the effect will be smaller
291 because another allocno will still be in the hard-register. In
292 most cases, this is better then spilling both allocnos. If
293 reload does not change the allocation for the two
294 pseudo-registers, the trivial move will be removed by
295 post-reload optimizations. IRA does not generate moves for
296 allocnos assigned to the same hard register when the default
297 regional allocation algorithm is used and the register pressure
298 in the region for the corresponding pressure class is less than
299 number of available hard registers for given pressure class.
300 IRA also does some optimizations to remove redundant stores and
301 to reduce code duplication on the region borders.
303 o Flattening internal representation. After changing code, IRA
304 transforms its internal representation for several regions into
305 one region representation (file ira-build.c). This process is
306 called IR flattening. Such process is more complicated than IR
307 rebuilding would be, but is much faster.
309 o After IR flattening, IRA tries to assign hard registers to all
310 spilled allocnos. This is impelemented by a simple and fast
311 priority coloring algorithm (see function
312 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
313 created during the code change pass can be assigned to hard
316 o At the end IRA calls the reload pass. The reload pass
317 communicates with IRA through several functions in file
318 ira-color.c to improve its decisions in
320 * sharing stack slots for the spilled pseudos based on IRA info
321 about pseudo-register conflicts.
323 * reassigning hard-registers to all spilled pseudos at the end
324 of each reload iteration.
326 * choosing a better hard-register to spill based on IRA info
327 about pseudo-register live ranges and the register pressure
328 in places where the pseudo-register lives.
330 IRA uses a lot of data representing the target processors. These
331 data are initilized in file ira.c.
333 If function has no loops (or the loops are ignored when
334 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
335 coloring (only instead of separate pass of coalescing, we use hard
336 register preferencing). In such case, IRA works much faster
337 because many things are not made (like IR flattening, the
338 spill/restore optimization, and the code change).
340 Literature is worth to read for better understanding the code:
342 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
343 Graph Coloring Register Allocation.
345 o David Callahan, Brian Koblenz. Register allocation via
346 hierarchical graph coloring.
348 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
349 Coloring Register Allocation: A Study of the Chaitin-Briggs and
350 Callahan-Koblenz Algorithms.
352 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
353 Register Allocation Based on Graph Fusion.
355 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
356 Allocation for Irregular Architectures
358 o Vladimir Makarov. The Integrated Register Allocator for GCC.
360 o Vladimir Makarov. The top-down register allocator for irregular
361 register file architectures.
368 #include "coretypes.h"
378 #include "hard-reg-set.h"
379 #include "basic-block.h"
384 #include "tree-pass.h"
388 #include "diagnostic-core.h"
389 #include "function.h"
395 #include "rtl-iter.h"
396 #include "shrink-wrap.h"
398 struct target_ira default_target_ira
;
399 struct target_ira_int default_target_ira_int
;
400 #if SWITCHABLE_TARGET
401 struct target_ira
*this_target_ira
= &default_target_ira
;
402 struct target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
405 /* A modified value of flag `-fira-verbose' used internally. */
406 int internal_flag_ira_verbose
;
408 /* Dump file of the allocator if it is not NULL. */
411 /* The number of elements in the following array. */
412 int ira_spilled_reg_stack_slots_num
;
414 /* The following array contains info about spilled pseudo-registers
415 stack slots used in current function so far. */
416 struct ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
418 /* Correspondingly overall cost of the allocation, overall cost before
419 reload, cost of the allocnos assigned to hard-registers, cost of
420 the allocnos assigned to memory, cost of loads, stores and register
421 move insns generated for pseudo-register live range splitting (see
423 int ira_overall_cost
, overall_cost_before
;
424 int ira_reg_cost
, ira_mem_cost
;
425 int ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
426 int ira_move_loops_num
, ira_additional_jumps_num
;
428 /* All registers that can be eliminated. */
430 HARD_REG_SET eliminable_regset
;
432 /* Value of max_reg_num () before IRA work start. This value helps
433 us to recognize a situation when new pseudos were created during
435 static int max_regno_before_ira
;
437 /* Temporary hard reg set used for a different calculation. */
438 static HARD_REG_SET temp_hard_regset
;
440 #define last_mode_for_init_move_cost \
441 (this_target_ira_int->x_last_mode_for_init_move_cost)
444 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
446 setup_reg_mode_hard_regset (void)
448 int i
, m
, hard_regno
;
450 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
451 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
453 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
454 for (i
= hard_regno_nregs
[hard_regno
][m
] - 1; i
>= 0; i
--)
455 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
456 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
462 #define no_unit_alloc_regs \
463 (this_target_ira_int->x_no_unit_alloc_regs)
465 /* The function sets up the three arrays declared above. */
467 setup_class_hard_regs (void)
469 int cl
, i
, hard_regno
, n
;
470 HARD_REG_SET processed_hard_reg_set
;
472 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
473 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
475 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
476 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
477 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
478 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
480 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
481 ira_class_hard_reg_index
[cl
][i
] = -1;
483 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
485 #ifdef REG_ALLOC_ORDER
486 hard_regno
= reg_alloc_order
[i
];
490 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
492 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
493 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
494 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
497 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
498 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
501 ira_class_hard_regs_num
[cl
] = n
;
502 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
503 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
504 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
505 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
509 /* Set up global variables defining info about hard registers for the
510 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
511 that we can use the hard frame pointer for the allocation. */
513 setup_alloc_regs (bool use_hard_frame_p
)
515 #ifdef ADJUST_REG_ALLOC_ORDER
516 ADJUST_REG_ALLOC_ORDER
;
518 COPY_HARD_REG_SET (no_unit_alloc_regs
, fixed_reg_set
);
519 if (! use_hard_frame_p
)
520 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
521 setup_class_hard_regs ();
526 #define alloc_reg_class_subclasses \
527 (this_target_ira_int->x_alloc_reg_class_subclasses)
529 /* Initialize the table of subclasses of each reg class. */
531 setup_reg_subclasses (void)
534 HARD_REG_SET temp_hard_regset2
;
536 for (i
= 0; i
< N_REG_CLASSES
; i
++)
537 for (j
= 0; j
< N_REG_CLASSES
; j
++)
538 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
540 for (i
= 0; i
< N_REG_CLASSES
; i
++)
542 if (i
== (int) NO_REGS
)
545 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
546 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
547 if (hard_reg_set_empty_p (temp_hard_regset
))
549 for (j
= 0; j
< N_REG_CLASSES
; j
++)
554 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[j
]);
555 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
556 if (! hard_reg_set_subset_p (temp_hard_regset
,
559 p
= &alloc_reg_class_subclasses
[j
][0];
560 while (*p
!= LIM_REG_CLASSES
) p
++;
561 *p
= (enum reg_class
) i
;
568 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
570 setup_class_subset_and_memory_move_costs (void)
572 int cl
, cl2
, mode
, cost
;
573 HARD_REG_SET temp_hard_regset2
;
575 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
576 ira_memory_move_cost
[mode
][NO_REGS
][0]
577 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
578 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
580 if (cl
!= (int) NO_REGS
)
581 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
583 ira_max_memory_move_cost
[mode
][cl
][0]
584 = ira_memory_move_cost
[mode
][cl
][0]
585 = memory_move_cost ((enum machine_mode
) mode
,
586 (reg_class_t
) cl
, false);
587 ira_max_memory_move_cost
[mode
][cl
][1]
588 = ira_memory_move_cost
[mode
][cl
][1]
589 = memory_move_cost ((enum machine_mode
) mode
,
590 (reg_class_t
) cl
, true);
591 /* Costs for NO_REGS are used in cost calculation on the
592 1st pass when the preferred register classes are not
593 known yet. In this case we take the best scenario. */
594 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
595 > ira_memory_move_cost
[mode
][cl
][0])
596 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
597 = ira_memory_move_cost
[mode
][NO_REGS
][0]
598 = ira_memory_move_cost
[mode
][cl
][0];
599 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
600 > ira_memory_move_cost
[mode
][cl
][1])
601 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
602 = ira_memory_move_cost
[mode
][NO_REGS
][1]
603 = ira_memory_move_cost
[mode
][cl
][1];
606 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
607 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
609 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
610 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
611 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
612 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
613 ira_class_subset_p
[cl
][cl2
]
614 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
615 if (! hard_reg_set_empty_p (temp_hard_regset2
)
616 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
617 reg_class_contents
[cl
]))
618 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
620 cost
= ira_memory_move_cost
[mode
][cl2
][0];
621 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
622 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
623 cost
= ira_memory_move_cost
[mode
][cl2
][1];
624 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
625 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
628 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
629 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
631 ira_memory_move_cost
[mode
][cl
][0]
632 = ira_max_memory_move_cost
[mode
][cl
][0];
633 ira_memory_move_cost
[mode
][cl
][1]
634 = ira_max_memory_move_cost
[mode
][cl
][1];
636 setup_reg_subclasses ();
641 /* Define the following macro if allocation through malloc if
643 #define IRA_NO_OBSTACK
645 #ifndef IRA_NO_OBSTACK
646 /* Obstack used for storing all dynamic data (except bitmaps) of the
648 static struct obstack ira_obstack
;
651 /* Obstack used for storing all bitmaps of the IRA. */
652 static struct bitmap_obstack ira_bitmap_obstack
;
654 /* Allocate memory of size LEN for IRA data. */
656 ira_allocate (size_t len
)
660 #ifndef IRA_NO_OBSTACK
661 res
= obstack_alloc (&ira_obstack
, len
);
668 /* Free memory ADDR allocated for IRA data. */
670 ira_free (void *addr ATTRIBUTE_UNUSED
)
672 #ifndef IRA_NO_OBSTACK
680 /* Allocate and returns bitmap for IRA. */
682 ira_allocate_bitmap (void)
684 return BITMAP_ALLOC (&ira_bitmap_obstack
);
687 /* Free bitmap B allocated for IRA. */
689 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
696 /* Output information about allocation of all allocnos (except for
697 caps) into file F. */
699 ira_print_disposition (FILE *f
)
705 fprintf (f
, "Disposition:");
706 max_regno
= max_reg_num ();
707 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
708 for (a
= ira_regno_allocno_map
[i
];
710 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
715 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
716 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
717 fprintf (f
, "b%-3d", bb
->index
);
719 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
720 if (ALLOCNO_HARD_REGNO (a
) >= 0)
721 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
728 /* Outputs information about allocation of all allocnos into
731 ira_debug_disposition (void)
733 ira_print_disposition (stderr
);
738 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
739 register class containing stack registers or NO_REGS if there are
740 no stack registers. To find this class, we iterate through all
741 register pressure classes and choose the first register pressure
742 class containing all the stack registers and having the biggest
745 setup_stack_reg_pressure_class (void)
747 ira_stack_reg_pressure_class
= NO_REGS
;
752 HARD_REG_SET temp_hard_regset2
;
754 CLEAR_HARD_REG_SET (temp_hard_regset
);
755 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
756 SET_HARD_REG_BIT (temp_hard_regset
, i
);
758 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
760 cl
= ira_pressure_classes
[i
];
761 COPY_HARD_REG_SET (temp_hard_regset2
, temp_hard_regset
);
762 AND_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
763 size
= hard_reg_set_size (temp_hard_regset2
);
767 ira_stack_reg_pressure_class
= cl
;
774 /* Find pressure classes which are register classes for which we
775 calculate register pressure in IRA, register pressure sensitive
776 insn scheduling, and register pressure sensitive loop invariant
779 To make register pressure calculation easy, we always use
780 non-intersected register pressure classes. A move of hard
781 registers from one register pressure class is not more expensive
782 than load and store of the hard registers. Most likely an allocno
783 class will be a subset of a register pressure class and in many
784 cases a register pressure class. That makes usage of register
785 pressure classes a good approximation to find a high register
788 setup_pressure_classes (void)
790 int cost
, i
, n
, curr
;
792 enum reg_class pressure_classes
[N_REG_CLASSES
];
794 HARD_REG_SET temp_hard_regset2
;
798 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
800 if (ira_class_hard_regs_num
[cl
] == 0)
802 if (ira_class_hard_regs_num
[cl
] != 1
803 /* A register class without subclasses may contain a few
804 hard registers and movement between them is costly
805 (e.g. SPARC FPCC registers). We still should consider it
806 as a candidate for a pressure class. */
807 && alloc_reg_class_subclasses
[cl
][0] < cl
)
809 /* Check that the moves between any hard registers of the
810 current class are not more expensive for a legal mode
811 than load/store of the hard registers of the current
812 class. Such class is a potential candidate to be a
813 register pressure class. */
814 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
816 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
817 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
818 AND_COMPL_HARD_REG_SET (temp_hard_regset
,
819 ira_prohibited_class_mode_regs
[cl
][m
]);
820 if (hard_reg_set_empty_p (temp_hard_regset
))
822 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
823 cost
= ira_register_move_cost
[m
][cl
][cl
];
824 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
825 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
828 if (m
>= NUM_MACHINE_MODES
)
833 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
834 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
835 /* Remove so far added pressure classes which are subset of the
836 current candidate class. Prefer GENERAL_REGS as a pressure
837 register class to another class containing the same
838 allocatable hard registers. We do this because machine
839 dependent cost hooks might give wrong costs for the latter
840 class but always give the right cost for the former class
842 for (i
= 0; i
< n
; i
++)
844 cl2
= pressure_classes
[i
];
845 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
846 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
847 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
848 && (! hard_reg_set_equal_p (temp_hard_regset
, temp_hard_regset2
)
849 || cl2
== (int) GENERAL_REGS
))
851 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
855 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
856 && (! hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
)
857 || cl
== (int) GENERAL_REGS
))
859 if (hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
))
861 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
863 /* If the current candidate is a subset of a so far added
864 pressure class, don't add it to the list of the pressure
867 pressure_classes
[curr
++] = (enum reg_class
) cl
;
870 #ifdef ENABLE_IRA_CHECKING
872 HARD_REG_SET ignore_hard_regs
;
874 /* Check pressure classes correctness: here we check that hard
875 registers from all register pressure classes contains all hard
876 registers available for the allocation. */
877 CLEAR_HARD_REG_SET (temp_hard_regset
);
878 CLEAR_HARD_REG_SET (temp_hard_regset2
);
879 COPY_HARD_REG_SET (ignore_hard_regs
, no_unit_alloc_regs
);
880 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
882 /* For some targets (like MIPS with MD_REGS), there are some
883 classes with hard registers available for allocation but
884 not able to hold value of any mode. */
885 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
886 if (contains_reg_of_mode
[cl
][m
])
888 if (m
>= NUM_MACHINE_MODES
)
890 IOR_HARD_REG_SET (ignore_hard_regs
, reg_class_contents
[cl
]);
893 for (i
= 0; i
< n
; i
++)
894 if ((int) pressure_classes
[i
] == cl
)
896 IOR_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
898 IOR_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
900 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
901 /* Some targets (like SPARC with ICC reg) have alocatable regs
902 for which no reg class is defined. */
903 if (REGNO_REG_CLASS (i
) == NO_REGS
)
904 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
905 AND_COMPL_HARD_REG_SET (temp_hard_regset
, ignore_hard_regs
);
906 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, ignore_hard_regs
);
907 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
910 ira_pressure_classes_num
= 0;
911 for (i
= 0; i
< n
; i
++)
913 cl
= (int) pressure_classes
[i
];
914 ira_reg_pressure_class_p
[cl
] = true;
915 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
917 setup_stack_reg_pressure_class ();
920 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
921 whose register move cost between any registers of the class is the
922 same as for all its subclasses. We use the data to speed up the
923 2nd pass of calculations of allocno costs. */
925 setup_uniform_class_p (void)
929 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
931 ira_uniform_class_p
[cl
] = false;
932 if (ira_class_hard_regs_num
[cl
] == 0)
934 /* We can not use alloc_reg_class_subclasses here because move
935 cost hooks does not take into account that some registers are
936 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
937 is element of alloc_reg_class_subclasses for GENERAL_REGS
938 because SSE regs are unavailable. */
939 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
941 if (ira_class_hard_regs_num
[cl2
] == 0)
943 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
944 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
946 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
947 if (ira_register_move_cost
[m
][cl
][cl
]
948 != ira_register_move_cost
[m
][cl2
][cl2
])
951 if (m
< NUM_MACHINE_MODES
)
954 if (cl2
== LIM_REG_CLASSES
)
955 ira_uniform_class_p
[cl
] = true;
959 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
960 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
962 Target may have many subtargets and not all target hard regiters can
963 be used for allocation, e.g. x86 port in 32-bit mode can not use
964 hard registers introduced in x86-64 like r8-r15). Some classes
965 might have the same allocatable hard registers, e.g. INDEX_REGS
966 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
967 calculations efforts we introduce allocno classes which contain
968 unique non-empty sets of allocatable hard-registers.
970 Pseudo class cost calculation in ira-costs.c is very expensive.
971 Therefore we are trying to decrease number of classes involved in
972 such calculation. Register classes used in the cost calculation
973 are called important classes. They are allocno classes and other
974 non-empty classes whose allocatable hard register sets are inside
975 of an allocno class hard register set. From the first sight, it
976 looks like that they are just allocno classes. It is not true. In
977 example of x86-port in 32-bit mode, allocno classes will contain
978 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
979 registers are the same for the both classes). The important
980 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
981 because a machine description insn constraint may refers for
982 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
983 of the insn constraints. */
985 setup_allocno_and_important_classes (void)
989 HARD_REG_SET temp_hard_regset2
;
990 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
993 /* Collect classes which contain unique sets of allocatable hard
994 registers. Prefer GENERAL_REGS to other classes containing the
995 same set of hard registers. */
996 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
998 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
999 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1000 for (j
= 0; j
< n
; j
++)
1003 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
1004 AND_COMPL_HARD_REG_SET (temp_hard_regset2
,
1005 no_unit_alloc_regs
);
1006 if (hard_reg_set_equal_p (temp_hard_regset
,
1011 classes
[n
++] = (enum reg_class
) i
;
1012 else if (i
== GENERAL_REGS
)
1013 /* Prefer general regs. For i386 example, it means that
1014 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1015 (all of them consists of the same available hard
1017 classes
[j
] = (enum reg_class
) i
;
1019 classes
[n
] = LIM_REG_CLASSES
;
1021 /* Set up classes which can be used for allocnos as classes
1022 conatining non-empty unique sets of allocatable hard
1024 ira_allocno_classes_num
= 0;
1025 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1026 if (ira_class_hard_regs_num
[cl
] > 0)
1027 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1028 ira_important_classes_num
= 0;
1029 /* Add non-allocno classes containing to non-empty set of
1030 allocatable hard regs. */
1031 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1032 if (ira_class_hard_regs_num
[cl
] > 0)
1034 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1035 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1037 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1039 COPY_HARD_REG_SET (temp_hard_regset2
,
1040 reg_class_contents
[ira_allocno_classes
[j
]]);
1041 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
1042 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1044 else if (hard_reg_set_subset_p (temp_hard_regset
,
1048 if (set_p
&& j
>= ira_allocno_classes_num
)
1049 ira_important_classes
[ira_important_classes_num
++]
1050 = (enum reg_class
) cl
;
1052 /* Now add allocno classes to the important classes. */
1053 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1054 ira_important_classes
[ira_important_classes_num
++]
1055 = ira_allocno_classes
[j
];
1056 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1058 ira_reg_allocno_class_p
[cl
] = false;
1059 ira_reg_pressure_class_p
[cl
] = false;
1061 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1062 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1063 setup_pressure_classes ();
1064 setup_uniform_class_p ();
1067 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1068 given by array CLASSES of length CLASSES_NUM. The function is used
1069 make translation any reg class to an allocno class or to an
1070 pressure class. This translation is necessary for some
1071 calculations when we can use only allocno or pressure classes and
1072 such translation represents an approximate representation of all
1075 The translation in case when allocatable hard register set of a
1076 given class is subset of allocatable hard register set of a class
1077 in CLASSES is pretty simple. We use smallest classes from CLASSES
1078 containing a given class. If allocatable hard register set of a
1079 given class is not a subset of any corresponding set of a class
1080 from CLASSES, we use the cheapest (with load/store point of view)
1081 class from CLASSES whose set intersects with given class set */
1083 setup_class_translate_array (enum reg_class
*class_translate
,
1084 int classes_num
, enum reg_class
*classes
)
1087 enum reg_class aclass
, best_class
, *cl_ptr
;
1088 int i
, cost
, min_cost
, best_cost
;
1090 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1091 class_translate
[cl
] = NO_REGS
;
1093 for (i
= 0; i
< classes_num
; i
++)
1095 aclass
= classes
[i
];
1096 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1097 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1099 if (class_translate
[cl
] == NO_REGS
)
1100 class_translate
[cl
] = aclass
;
1101 class_translate
[aclass
] = aclass
;
1103 /* For classes which are not fully covered by one of given classes
1104 (in other words covered by more one given class), use the
1106 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1108 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1110 best_class
= NO_REGS
;
1111 best_cost
= INT_MAX
;
1112 for (i
= 0; i
< classes_num
; i
++)
1114 aclass
= classes
[i
];
1115 COPY_HARD_REG_SET (temp_hard_regset
,
1116 reg_class_contents
[aclass
]);
1117 AND_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1118 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1119 if (! hard_reg_set_empty_p (temp_hard_regset
))
1122 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1124 cost
= (ira_memory_move_cost
[mode
][aclass
][0]
1125 + ira_memory_move_cost
[mode
][aclass
][1]);
1126 if (min_cost
> cost
)
1129 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1131 best_class
= aclass
;
1132 best_cost
= min_cost
;
1136 class_translate
[cl
] = best_class
;
1140 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1141 IRA_PRESSURE_CLASS_TRANSLATE. */
1143 setup_class_translate (void)
1145 setup_class_translate_array (ira_allocno_class_translate
,
1146 ira_allocno_classes_num
, ira_allocno_classes
);
1147 setup_class_translate_array (ira_pressure_class_translate
,
1148 ira_pressure_classes_num
, ira_pressure_classes
);
1151 /* Order numbers of allocno classes in original target allocno class
1152 array, -1 for non-allocno classes. */
1153 static int allocno_class_order
[N_REG_CLASSES
];
1155 /* The function used to sort the important classes. */
1157 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1159 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1160 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1161 enum reg_class tcl1
, tcl2
;
1164 tcl1
= ira_allocno_class_translate
[cl1
];
1165 tcl2
= ira_allocno_class_translate
[cl2
];
1166 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1167 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1169 return (int) cl1
- (int) cl2
;
1172 /* For correct work of function setup_reg_class_relation we need to
1173 reorder important classes according to the order of their allocno
1174 classes. It places important classes containing the same
1175 allocatable hard register set adjacent to each other and allocno
1176 class with the allocatable hard register set right after the other
1177 important classes with the same set.
1179 In example from comments of function
1180 setup_allocno_and_important_classes, it places LEGACY_REGS and
1181 GENERAL_REGS close to each other and GENERAL_REGS is after
1184 reorder_important_classes (void)
1188 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1189 allocno_class_order
[i
] = -1;
1190 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1191 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1192 qsort (ira_important_classes
, ira_important_classes_num
,
1193 sizeof (enum reg_class
), comp_reg_classes_func
);
1194 for (i
= 0; i
< ira_important_classes_num
; i
++)
1195 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1198 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1199 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1200 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1201 please see corresponding comments in ira-int.h. */
1203 setup_reg_class_relations (void)
1205 int i
, cl1
, cl2
, cl3
;
1206 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1207 bool important_class_p
[N_REG_CLASSES
];
1209 memset (important_class_p
, 0, sizeof (important_class_p
));
1210 for (i
= 0; i
< ira_important_classes_num
; i
++)
1211 important_class_p
[ira_important_classes
[i
]] = true;
1212 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1214 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1215 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1217 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1218 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1219 ira_reg_class_subset
[cl1
][cl2
] = NO_REGS
;
1220 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl1
]);
1221 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1222 COPY_HARD_REG_SET (temp_set2
, reg_class_contents
[cl2
]);
1223 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1224 if (hard_reg_set_empty_p (temp_hard_regset
)
1225 && hard_reg_set_empty_p (temp_set2
))
1227 /* The both classes have no allocatable hard registers
1228 -- take all class hard registers into account and use
1229 reg_class_subunion and reg_class_superunion. */
1232 cl3
= reg_class_subclasses
[cl1
][i
];
1233 if (cl3
== LIM_REG_CLASSES
)
1235 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1236 (enum reg_class
) cl3
))
1237 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1239 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1240 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1243 ira_reg_classes_intersect_p
[cl1
][cl2
]
1244 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1245 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1246 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1248 /* CL1 and CL2 are important classes and CL1 allocatable
1249 hard register set is inside of CL2 allocatable hard
1250 registers -- make CL1 a superset of CL2. */
1253 p
= &ira_reg_class_super_classes
[cl1
][0];
1254 while (*p
!= LIM_REG_CLASSES
)
1256 *p
++ = (enum reg_class
) cl2
;
1257 *p
= LIM_REG_CLASSES
;
1259 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1260 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1261 COPY_HARD_REG_SET (intersection_set
, reg_class_contents
[cl1
]);
1262 AND_HARD_REG_SET (intersection_set
, reg_class_contents
[cl2
]);
1263 AND_COMPL_HARD_REG_SET (intersection_set
, no_unit_alloc_regs
);
1264 COPY_HARD_REG_SET (union_set
, reg_class_contents
[cl1
]);
1265 IOR_HARD_REG_SET (union_set
, reg_class_contents
[cl2
]);
1266 AND_COMPL_HARD_REG_SET (union_set
, no_unit_alloc_regs
);
1267 for (cl3
= 0; cl3
< N_REG_CLASSES
; cl3
++)
1269 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl3
]);
1270 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1271 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1273 /* CL3 allocatable hard register set is inside of
1274 intersection of allocatable hard register sets
1276 if (important_class_p
[cl3
])
1281 [(int) ira_reg_class_intersect
[cl1
][cl2
]]);
1282 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1283 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1284 /* If the allocatable hard register sets are
1285 the same, prefer GENERAL_REGS or the
1286 smallest class for debugging
1288 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1289 && (cl3
== GENERAL_REGS
1290 || ((ira_reg_class_intersect
[cl1
][cl2
]
1292 && hard_reg_set_subset_p
1293 (reg_class_contents
[cl3
],
1296 ira_reg_class_intersect
[cl1
][cl2
]])))))
1297 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1301 reg_class_contents
[(int) ira_reg_class_subset
[cl1
][cl2
]]);
1302 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1303 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1304 /* Ignore unavailable hard registers and prefer
1305 smallest class for debugging purposes. */
1306 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1307 && hard_reg_set_subset_p
1308 (reg_class_contents
[cl3
],
1310 [(int) ira_reg_class_subset
[cl1
][cl2
]])))
1311 ira_reg_class_subset
[cl1
][cl2
] = (enum reg_class
) cl3
;
1313 if (important_class_p
[cl3
]
1314 && hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1316 /* CL3 allocatbale hard register set is inside of
1317 union of allocatable hard register sets of CL1
1321 reg_class_contents
[(int) ira_reg_class_subunion
[cl1
][cl2
]]);
1322 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1323 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1324 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1326 && (! hard_reg_set_equal_p (temp_set2
,
1328 || cl3
== GENERAL_REGS
1329 /* If the allocatable hard register sets are the
1330 same, prefer GENERAL_REGS or the smallest
1331 class for debugging purposes. */
1332 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1333 && hard_reg_set_subset_p
1334 (reg_class_contents
[cl3
],
1336 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1337 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1339 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1341 /* CL3 allocatable hard register set contains union
1342 of allocatable hard register sets of CL1 and
1346 reg_class_contents
[(int) ira_reg_class_superunion
[cl1
][cl2
]]);
1347 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1348 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1349 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1351 && (! hard_reg_set_equal_p (temp_set2
,
1353 || cl3
== GENERAL_REGS
1354 /* If the allocatable hard register sets are the
1355 same, prefer GENERAL_REGS or the smallest
1356 class for debugging purposes. */
1357 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1358 && hard_reg_set_subset_p
1359 (reg_class_contents
[cl3
],
1361 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1362 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1369 /* Output all unifrom and important classes into file F. */
1371 print_unform_and_important_classes (FILE *f
)
1373 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1376 fprintf (f
, "Uniform classes:\n");
1377 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1378 if (ira_uniform_class_p
[cl
])
1379 fprintf (f
, " %s", reg_class_names
[cl
]);
1380 fprintf (f
, "\nImportant classes:\n");
1381 for (i
= 0; i
< ira_important_classes_num
; i
++)
1382 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1386 /* Output all possible allocno or pressure classes and their
1387 translation map into file F. */
1389 print_translated_classes (FILE *f
, bool pressure_p
)
1391 int classes_num
= (pressure_p
1392 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1393 enum reg_class
*classes
= (pressure_p
1394 ? ira_pressure_classes
: ira_allocno_classes
);
1395 enum reg_class
*class_translate
= (pressure_p
1396 ? ira_pressure_class_translate
1397 : ira_allocno_class_translate
);
1398 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1401 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1402 for (i
= 0; i
< classes_num
; i
++)
1403 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1404 fprintf (f
, "\nClass translation:\n");
1405 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1406 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1407 reg_class_names
[class_translate
[i
]]);
1410 /* Output all possible allocno and translation classes and the
1411 translation maps into stderr. */
1413 ira_debug_allocno_classes (void)
1415 print_unform_and_important_classes (stderr
);
1416 print_translated_classes (stderr
, false);
1417 print_translated_classes (stderr
, true);
1420 /* Set up different arrays concerning class subsets, allocno and
1421 important classes. */
1423 find_reg_classes (void)
1425 setup_allocno_and_important_classes ();
1426 setup_class_translate ();
1427 reorder_important_classes ();
1428 setup_reg_class_relations ();
1433 /* Set up the array above. */
1435 setup_hard_regno_aclass (void)
1439 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1442 ira_hard_regno_allocno_class
[i
]
1443 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1445 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1449 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1450 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1452 cl
= ira_allocno_classes
[j
];
1453 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1455 ira_hard_regno_allocno_class
[i
] = cl
;
1465 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1467 setup_reg_class_nregs (void)
1471 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1473 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1474 ira_reg_class_max_nregs
[cl
][m
]
1475 = ira_reg_class_min_nregs
[cl
][m
]
1476 = targetm
.class_max_nregs ((reg_class_t
) cl
, (enum machine_mode
) m
);
1477 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1479 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1481 if (ira_reg_class_min_nregs
[cl2
][m
]
1482 < ira_reg_class_min_nregs
[cl
][m
])
1483 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1489 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON.
1490 This function is called once IRA_CLASS_HARD_REGS has been initialized. */
1492 setup_prohibited_class_mode_regs (void)
1494 int j
, k
, hard_regno
, cl
, last_hard_regno
, count
;
1496 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1498 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1499 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1500 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1503 last_hard_regno
= -1;
1504 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1505 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1507 hard_regno
= ira_class_hard_regs
[cl
][k
];
1508 if (! HARD_REGNO_MODE_OK (hard_regno
, (enum machine_mode
) j
))
1509 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1511 else if (in_hard_reg_set_p (temp_hard_regset
,
1512 (enum machine_mode
) j
, hard_regno
))
1514 last_hard_regno
= hard_regno
;
1518 ira_class_singleton
[cl
][j
] = (count
== 1 ? last_hard_regno
: -1);
1523 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1524 spanning from one register pressure class to another one. It is
1525 called after defining the pressure classes. */
1527 clarify_prohibited_class_mode_regs (void)
1529 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1531 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1532 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1534 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs
[cl
][j
]);
1535 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1537 hard_regno
= ira_class_hard_regs
[cl
][k
];
1538 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1540 nregs
= hard_regno_nregs
[hard_regno
][j
];
1541 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1543 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1547 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1548 for (nregs
-- ;nregs
>= 0; nregs
--)
1549 if (((enum reg_class
) pclass
1550 != ira_pressure_class_translate
[REGNO_REG_CLASS
1551 (hard_regno
+ nregs
)]))
1553 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1557 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1559 add_to_hard_reg_set (&ira_useful_class_mode_regs
[cl
][j
],
1560 (enum machine_mode
) j
, hard_regno
);
1565 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1566 and IRA_MAY_MOVE_OUT_COST for MODE. */
1568 ira_init_register_move_cost (enum machine_mode mode
)
1570 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1571 bool all_match
= true;
1572 unsigned int cl1
, cl2
;
1574 ira_assert (ira_register_move_cost
[mode
] == NULL
1575 && ira_may_move_in_cost
[mode
] == NULL
1576 && ira_may_move_out_cost
[mode
] == NULL
);
1577 ira_assert (have_regs_of_mode
[mode
]);
1578 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1579 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1582 if (!contains_reg_of_mode
[cl1
][mode
]
1583 || !contains_reg_of_mode
[cl2
][mode
])
1585 if ((ira_reg_class_max_nregs
[cl1
][mode
]
1586 > ira_class_hard_regs_num
[cl1
])
1587 || (ira_reg_class_max_nregs
[cl2
][mode
]
1588 > ira_class_hard_regs_num
[cl2
]))
1591 cost
= (ira_memory_move_cost
[mode
][cl1
][0]
1592 + ira_memory_move_cost
[mode
][cl2
][1]) * 2;
1596 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1597 (enum reg_class
) cl2
);
1598 ira_assert (cost
< 65535);
1600 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1601 last_move_cost
[cl1
][cl2
] = cost
;
1603 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1605 ira_register_move_cost
[mode
]
1606 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1607 ira_may_move_in_cost
[mode
]
1608 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1609 ira_may_move_out_cost
[mode
]
1610 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1613 last_mode_for_init_move_cost
= mode
;
1614 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1615 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1616 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1617 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1618 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1621 enum reg_class
*p1
, *p2
;
1623 if (last_move_cost
[cl1
][cl2
] == 65535)
1625 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1626 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1627 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1631 cost
= last_move_cost
[cl1
][cl2
];
1633 for (p2
= ®_class_subclasses
[cl2
][0];
1634 *p2
!= LIM_REG_CLASSES
; p2
++)
1635 if (ira_class_hard_regs_num
[*p2
] > 0
1636 && (ira_reg_class_max_nregs
[*p2
][mode
]
1637 <= ira_class_hard_regs_num
[*p2
]))
1638 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1640 for (p1
= ®_class_subclasses
[cl1
][0];
1641 *p1
!= LIM_REG_CLASSES
; p1
++)
1642 if (ira_class_hard_regs_num
[*p1
] > 0
1643 && (ira_reg_class_max_nregs
[*p1
][mode
]
1644 <= ira_class_hard_regs_num
[*p1
]))
1645 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1647 ira_assert (cost
<= 65535);
1648 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1650 if (ira_class_subset_p
[cl1
][cl2
])
1651 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1653 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1655 if (ira_class_subset_p
[cl2
][cl1
])
1656 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1658 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1665 /* This is called once during compiler work. It sets up
1666 different arrays whose values don't depend on the compiled
1669 ira_init_once (void)
1671 ira_init_costs_once ();
1675 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1676 ira_may_move_out_cost for each mode. */
1678 free_register_move_costs (void)
1682 /* Reset move_cost and friends, making sure we only free shared
1683 table entries once. */
1684 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1685 if (ira_register_move_cost
[mode
])
1688 i
< mode
&& (ira_register_move_cost
[i
]
1689 != ira_register_move_cost
[mode
]);
1694 free (ira_register_move_cost
[mode
]);
1695 free (ira_may_move_in_cost
[mode
]);
1696 free (ira_may_move_out_cost
[mode
]);
1699 memset (ira_register_move_cost
, 0, sizeof ira_register_move_cost
);
1700 memset (ira_may_move_in_cost
, 0, sizeof ira_may_move_in_cost
);
1701 memset (ira_may_move_out_cost
, 0, sizeof ira_may_move_out_cost
);
1702 last_mode_for_init_move_cost
= -1;
1705 /* This is called every time when register related information is
1710 free_register_move_costs ();
1711 setup_reg_mode_hard_regset ();
1712 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1713 setup_class_subset_and_memory_move_costs ();
1714 setup_reg_class_nregs ();
1715 setup_prohibited_class_mode_regs ();
1716 find_reg_classes ();
1717 clarify_prohibited_class_mode_regs ();
1718 setup_hard_regno_aclass ();
1722 /* Function called once at the end of compiler work. */
1724 ira_finish_once (void)
1726 ira_finish_costs_once ();
1727 free_register_move_costs ();
1732 #define ira_prohibited_mode_move_regs_initialized_p \
1733 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1735 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1737 setup_prohibited_mode_move_regs (void)
1740 rtx test_reg1
, test_reg2
, move_pat
, move_insn
;
1742 if (ira_prohibited_mode_move_regs_initialized_p
)
1744 ira_prohibited_mode_move_regs_initialized_p
= true;
1745 test_reg1
= gen_rtx_REG (VOIDmode
, 0);
1746 test_reg2
= gen_rtx_REG (VOIDmode
, 0);
1747 move_pat
= gen_rtx_SET (VOIDmode
, test_reg1
, test_reg2
);
1748 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, move_pat
, 0, -1, 0);
1749 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1751 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1752 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1754 if (! HARD_REGNO_MODE_OK (j
, (enum machine_mode
) i
))
1756 SET_REGNO_RAW (test_reg1
, j
);
1757 PUT_MODE (test_reg1
, (enum machine_mode
) i
);
1758 SET_REGNO_RAW (test_reg2
, j
);
1759 PUT_MODE (test_reg2
, (enum machine_mode
) i
);
1760 INSN_CODE (move_insn
) = -1;
1761 recog_memoized (move_insn
);
1762 if (INSN_CODE (move_insn
) < 0)
1764 extract_insn (move_insn
);
1765 if (! constrain_operands (1))
1767 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1774 /* Setup possible alternatives in ALTS for INSN. */
1776 ira_setup_alts (rtx insn
, HARD_REG_SET
&alts
)
1778 /* MAP nalt * nop -> start of constraints for given operand and
1780 static vec
<const char *> insn_constraints
;
1785 int commutative
= -1;
1787 extract_insn (insn
);
1788 CLEAR_HARD_REG_SET (alts
);
1789 insn_constraints
.release ();
1790 insn_constraints
.safe_grow_cleared (recog_data
.n_operands
1791 * recog_data
.n_alternatives
+ 1);
1792 /* Check that the hard reg set is enough for holding all
1793 alternatives. It is hard to imagine the situation when the
1794 assertion is wrong. */
1795 ira_assert (recog_data
.n_alternatives
1796 <= (int) MAX (sizeof (HARD_REG_ELT_TYPE
) * CHAR_BIT
,
1797 FIRST_PSEUDO_REGISTER
));
1798 for (curr_swapped
= false;; curr_swapped
= true)
1800 /* Calculate some data common for all alternatives to speed up the
1802 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1804 for (nalt
= 0, p
= recog_data
.constraints
[nop
];
1805 nalt
< recog_data
.n_alternatives
;
1808 insn_constraints
[nop
* recog_data
.n_alternatives
+ nalt
] = p
;
1809 while (*p
&& *p
!= ',')
1815 for (nalt
= 0; nalt
< recog_data
.n_alternatives
; nalt
++)
1817 if (!TEST_BIT (recog_data
.enabled_alternatives
, nalt
)
1818 || TEST_HARD_REG_BIT (alts
, nalt
))
1821 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1825 op
= recog_data
.operand
[nop
];
1826 p
= insn_constraints
[nop
* recog_data
.n_alternatives
+ nalt
];
1827 if (*p
== 0 || *p
== ',')
1831 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
1841 /* We only support one commutative marker, the
1842 first one. We already set commutative
1844 if (commutative
< 0)
1848 case '0': case '1': case '2': case '3': case '4':
1849 case '5': case '6': case '7': case '8': case '9':
1859 enum constraint_num cn
= lookup_constraint (p
);
1860 switch (get_constraint_type (cn
))
1863 if (reg_class_for_constraint (cn
) != NO_REGS
)
1868 if (CONST_INT_P (op
)
1869 && (insn_const_int_ok_for_constraint
1879 if (constraint_satisfied_p (op
, cn
))
1886 while (p
+= len
, c
);
1891 if (nop
>= recog_data
.n_operands
)
1892 SET_HARD_REG_BIT (alts
, nalt
);
1894 if (commutative
< 0)
1898 op
= recog_data
.operand
[commutative
];
1899 recog_data
.operand
[commutative
] = recog_data
.operand
[commutative
+ 1];
1900 recog_data
.operand
[commutative
+ 1] = op
;
1905 /* Return the number of the output non-early clobber operand which
1906 should be the same in any case as operand with number OP_NUM (or
1907 negative value if there is no such operand). The function takes
1908 only really possible alternatives into consideration. */
1910 ira_get_dup_out_num (int op_num
, HARD_REG_SET
&alts
)
1912 int curr_alt
, c
, original
, dup
;
1913 bool ignore_p
, use_commut_op_p
;
1916 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
1918 /* We should find duplications only for input operands. */
1919 if (recog_data
.operand_type
[op_num
] != OP_IN
)
1921 str
= recog_data
.constraints
[op_num
];
1922 use_commut_op_p
= false;
1925 rtx op
= recog_data
.operand
[op_num
];
1927 for (curr_alt
= 0, ignore_p
= !TEST_HARD_REG_BIT (alts
, curr_alt
),
1938 ignore_p
= !TEST_HARD_REG_BIT (alts
, curr_alt
);
1940 else if (! ignore_p
)
1947 enum constraint_num cn
= lookup_constraint (str
);
1948 enum reg_class cl
= reg_class_for_constraint (cn
);
1950 && !targetm
.class_likely_spilled_p (cl
))
1952 if (constraint_satisfied_p (op
, cn
))
1957 case '0': case '1': case '2': case '3': case '4':
1958 case '5': case '6': case '7': case '8': case '9':
1959 if (original
!= -1 && original
!= c
)
1964 str
+= CONSTRAINT_LEN (c
, str
);
1969 for (ignore_p
= false, str
= recog_data
.constraints
[original
- '0'];
1977 else if (*str
== '#')
1979 else if (! ignore_p
)
1982 dup
= original
- '0';
1983 /* It is better ignore an alternative with early clobber. */
1984 else if (*str
== '&')
1990 if (use_commut_op_p
)
1992 use_commut_op_p
= true;
1993 if (recog_data
.constraints
[op_num
][0] == '%')
1994 str
= recog_data
.constraints
[op_num
+ 1];
1995 else if (op_num
> 0 && recog_data
.constraints
[op_num
- 1][0] == '%')
1996 str
= recog_data
.constraints
[op_num
- 1];
2005 /* Search forward to see if the source register of a copy insn dies
2006 before either it or the destination register is modified, but don't
2007 scan past the end of the basic block. If so, we can replace the
2008 source with the destination and let the source die in the copy
2011 This will reduce the number of registers live in that range and may
2012 enable the destination and the source coalescing, thus often saving
2013 one register in addition to a register-register copy. */
2016 decrease_live_ranges_number (void)
2020 rtx set
, src
, dest
, dest_death
, q
, note
;
2024 if (! flag_expensive_optimizations
)
2028 fprintf (ira_dump_file
, "Starting decreasing number of live ranges...\n");
2030 FOR_EACH_BB_FN (bb
, cfun
)
2031 FOR_BB_INSNS (bb
, insn
)
2033 set
= single_set (insn
);
2036 src
= SET_SRC (set
);
2037 dest
= SET_DEST (set
);
2038 if (! REG_P (src
) || ! REG_P (dest
)
2039 || find_reg_note (insn
, REG_DEAD
, src
))
2041 sregno
= REGNO (src
);
2042 dregno
= REGNO (dest
);
2044 /* We don't want to mess with hard regs if register classes
2046 if (sregno
== dregno
2047 || (targetm
.small_register_classes_for_mode_p (GET_MODE (src
))
2048 && (sregno
< FIRST_PSEUDO_REGISTER
2049 || dregno
< FIRST_PSEUDO_REGISTER
))
2050 /* We don't see all updates to SP if they are in an
2051 auto-inc memory reference, so we must disallow this
2052 optimization on them. */
2053 || sregno
== STACK_POINTER_REGNUM
2054 || dregno
== STACK_POINTER_REGNUM
)
2057 dest_death
= NULL_RTX
;
2059 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
2063 if (BLOCK_FOR_INSN (p
) != bb
)
2066 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
2067 /* If SRC is an asm-declared register, it must not be
2068 replaced in any asm. Unfortunately, the REG_EXPR
2069 tree for the asm variable may be absent in the SRC
2070 rtx, so we can't check the actual register
2071 declaration easily (the asm operand will have it,
2072 though). To avoid complicating the test for a rare
2073 case, we just don't perform register replacement
2074 for a hard reg mentioned in an asm. */
2075 || (sregno
< FIRST_PSEUDO_REGISTER
2076 && asm_noperands (PATTERN (p
)) >= 0
2077 && reg_overlap_mentioned_p (src
, PATTERN (p
)))
2078 /* Don't change hard registers used by a call. */
2079 || (CALL_P (p
) && sregno
< FIRST_PSEUDO_REGISTER
2080 && find_reg_fusage (p
, USE
, src
))
2081 /* Don't change a USE of a register. */
2082 || (GET_CODE (PATTERN (p
)) == USE
2083 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
2086 /* See if all of SRC dies in P. This test is slightly
2087 more conservative than it needs to be. */
2088 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
))
2089 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
2093 /* We can do the optimization. Scan forward from INSN
2094 again, replacing regs as we go. Set FAILED if a
2095 replacement can't be done. In that case, we can't
2096 move the death note for SRC. This should be
2099 /* Set to stop at next insn. */
2100 for (q
= next_real_insn (insn
);
2101 q
!= next_real_insn (p
);
2102 q
= next_real_insn (q
))
2104 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
2106 /* If SRC is a hard register, we might miss
2107 some overlapping registers with
2108 validate_replace_rtx, so we would have to
2109 undo it. We can't if DEST is present in
2110 the insn, so fail in that combination of
2112 if (sregno
< FIRST_PSEUDO_REGISTER
2113 && reg_mentioned_p (dest
, PATTERN (q
)))
2116 /* Attempt to replace all uses. */
2117 else if (!validate_replace_rtx (src
, dest
, q
))
2120 /* If this succeeded, but some part of the
2121 register is still present, undo the
2123 else if (sregno
< FIRST_PSEUDO_REGISTER
2124 && reg_overlap_mentioned_p (src
, PATTERN (q
)))
2126 validate_replace_rtx (dest
, src
, q
);
2131 /* If DEST dies here, remove the death note and
2132 save it for later. Make sure ALL of DEST dies
2133 here; again, this is overly conservative. */
2135 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)))
2137 if (GET_MODE (XEXP (dest_death
, 0)) == GET_MODE (dest
))
2138 remove_note (q
, dest_death
);
2149 /* Move death note of SRC from P to INSN. */
2150 remove_note (p
, note
);
2151 XEXP (note
, 1) = REG_NOTES (insn
);
2152 REG_NOTES (insn
) = note
;
2155 /* DEST is also dead if INSN has a REG_UNUSED note for
2159 = find_regno_note (insn
, REG_UNUSED
, dregno
)))
2161 PUT_REG_NOTE_KIND (dest_death
, REG_DEAD
);
2162 remove_note (insn
, dest_death
);
2165 /* Put death note of DEST on P if we saw it die. */
2168 XEXP (dest_death
, 1) = REG_NOTES (p
);
2169 REG_NOTES (p
) = dest_death
;
2174 /* If SRC is a hard register which is set or killed in
2175 some other way, we can't do this optimization. */
2176 else if (sregno
< FIRST_PSEUDO_REGISTER
&& dead_or_set_p (p
, src
))
2184 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
2186 ira_bad_reload_regno_1 (int regno
, rtx x
)
2190 enum reg_class pref
;
2192 /* We only deal with pseudo regs. */
2193 if (! x
|| GET_CODE (x
) != REG
)
2196 x_regno
= REGNO (x
);
2197 if (x_regno
< FIRST_PSEUDO_REGISTER
)
2200 /* If the pseudo prefers REGNO explicitly, then do not consider
2201 REGNO a bad spill choice. */
2202 pref
= reg_preferred_class (x_regno
);
2203 if (reg_class_size
[pref
] == 1)
2204 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
2206 /* If the pseudo conflicts with REGNO, then we consider REGNO a
2207 poor choice for a reload regno. */
2208 a
= ira_regno_allocno_map
[x_regno
];
2209 n
= ALLOCNO_NUM_OBJECTS (a
);
2210 for (i
= 0; i
< n
; i
++)
2212 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2213 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
2219 /* Return nonzero if REGNO is a particularly bad choice for reloading
2222 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
2224 return (ira_bad_reload_regno_1 (regno
, in
)
2225 || ira_bad_reload_regno_1 (regno
, out
));
2228 /* Add register clobbers from asm statements. */
2230 compute_regs_asm_clobbered (void)
2234 FOR_EACH_BB_FN (bb
, cfun
)
2237 FOR_BB_INSNS_REVERSE (bb
, insn
)
2241 if (NONDEBUG_INSN_P (insn
) && extract_asm_operands (PATTERN (insn
)))
2242 FOR_EACH_INSN_DEF (def
, insn
)
2244 unsigned int dregno
= DF_REF_REGNO (def
);
2245 if (HARD_REGISTER_NUM_P (dregno
))
2246 add_to_hard_reg_set (&crtl
->asm_clobbers
,
2247 GET_MODE (DF_REF_REAL_REG (def
)),
2255 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and
2258 ira_setup_eliminable_regset (void)
2260 #ifdef ELIMINABLE_REGS
2262 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2264 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
2265 sp for alloca. So we can't eliminate the frame pointer in that
2266 case. At some point, we should improve this by emitting the
2267 sp-adjusting insns for this case. */
2268 frame_pointer_needed
2269 = (! flag_omit_frame_pointer
2270 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
2271 /* We need the frame pointer to catch stack overflow exceptions
2272 if the stack pointer is moving. */
2273 || (flag_stack_check
&& STACK_CHECK_MOVING_SP
)
2274 || crtl
->accesses_prior_frames
2275 || (SUPPORTS_STACK_ALIGNMENT
&& crtl
->stack_realign_needed
)
2276 /* We need a frame pointer for all Cilk Plus functions that use
2278 || (flag_cilkplus
&& cfun
->is_cilk_function
)
2279 || targetm
.frame_pointer_required ());
2281 /* The chance that FRAME_POINTER_NEEDED is changed from inspecting
2282 RTL is very small. So if we use frame pointer for RA and RTL
2283 actually prevents this, we will spill pseudos assigned to the
2284 frame pointer in LRA. */
2286 if (frame_pointer_needed
)
2287 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2289 COPY_HARD_REG_SET (ira_no_alloc_regs
, no_unit_alloc_regs
);
2290 CLEAR_HARD_REG_SET (eliminable_regset
);
2292 compute_regs_asm_clobbered ();
2294 /* Build the regset of all eliminable registers and show we can't
2295 use those that we already know won't be eliminated. */
2296 #ifdef ELIMINABLE_REGS
2297 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2300 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
2301 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
2303 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
2305 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
2308 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
2310 else if (cannot_elim
)
2311 error ("%s cannot be used in asm here",
2312 reg_names
[eliminables
[i
].from
]);
2314 df_set_regs_ever_live (eliminables
[i
].from
, true);
2316 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2317 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
2319 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
2320 if (frame_pointer_needed
)
2321 SET_HARD_REG_BIT (ira_no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
2323 else if (frame_pointer_needed
)
2324 error ("%s cannot be used in asm here",
2325 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
2327 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2331 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
2333 SET_HARD_REG_BIT (eliminable_regset
, FRAME_POINTER_REGNUM
);
2334 if (frame_pointer_needed
)
2335 SET_HARD_REG_BIT (ira_no_alloc_regs
, FRAME_POINTER_REGNUM
);
2337 else if (frame_pointer_needed
)
2338 error ("%s cannot be used in asm here", reg_names
[FRAME_POINTER_REGNUM
]);
2340 df_set_regs_ever_live (FRAME_POINTER_REGNUM
, true);
2346 /* Vector of substitutions of register numbers,
2347 used to map pseudo regs into hardware regs.
2348 This is set up as a result of register allocation.
2349 Element N is the hard reg assigned to pseudo reg N,
2350 or is -1 if no hard reg was assigned.
2351 If N is a hard reg number, element N is N. */
2352 short *reg_renumber
;
2354 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
2355 the allocation found by IRA. */
2357 setup_reg_renumber (void)
2359 int regno
, hard_regno
;
2361 ira_allocno_iterator ai
;
2363 caller_save_needed
= 0;
2364 FOR_EACH_ALLOCNO (a
, ai
)
2366 if (ira_use_lra_p
&& ALLOCNO_CAP_MEMBER (a
) != NULL
)
2368 /* There are no caps at this point. */
2369 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
2370 if (! ALLOCNO_ASSIGNED_P (a
))
2371 /* It can happen if A is not referenced but partially anticipated
2372 somewhere in a region. */
2373 ALLOCNO_ASSIGNED_P (a
) = true;
2374 ira_free_allocno_updated_costs (a
);
2375 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2376 regno
= ALLOCNO_REGNO (a
);
2377 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
2378 if (hard_regno
>= 0)
2381 enum reg_class pclass
;
2384 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
2385 nwords
= ALLOCNO_NUM_OBJECTS (a
);
2386 for (i
= 0; i
< nwords
; i
++)
2388 obj
= ALLOCNO_OBJECT (a
, i
);
2389 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
2390 reg_class_contents
[pclass
]);
2392 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0
2393 && ira_hard_reg_set_intersection_p (hard_regno
, ALLOCNO_MODE (a
),
2396 ira_assert (!optimize
|| flag_caller_saves
2397 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
2398 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2399 || regno
>= ira_reg_equiv_len
2400 || ira_equiv_no_lvalue_p (regno
));
2401 caller_save_needed
= 1;
2407 /* Set up allocno assignment flags for further allocation
2410 setup_allocno_assignment_flags (void)
2414 ira_allocno_iterator ai
;
2416 FOR_EACH_ALLOCNO (a
, ai
)
2418 if (! ALLOCNO_ASSIGNED_P (a
))
2419 /* It can happen if A is not referenced but partially anticipated
2420 somewhere in a region. */
2421 ira_free_allocno_updated_costs (a
);
2422 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2423 /* Don't assign hard registers to allocnos which are destination
2424 of removed store at the end of loop. It has no sense to keep
2425 the same value in different hard registers. It is also
2426 impossible to assign hard registers correctly to such
2427 allocnos because the cost info and info about intersected
2428 calls are incorrect for them. */
2429 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2430 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2431 || (ALLOCNO_MEMORY_COST (a
)
2432 - ALLOCNO_CLASS_COST (a
)) < 0);
2435 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2436 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2440 /* Evaluate overall allocation cost and the costs for using hard
2441 registers and memory for allocnos. */
2443 calculate_allocation_cost (void)
2445 int hard_regno
, cost
;
2447 ira_allocno_iterator ai
;
2449 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2450 FOR_EACH_ALLOCNO (a
, ai
)
2452 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2453 ira_assert (hard_regno
< 0
2454 || (ira_hard_reg_in_set_p
2455 (hard_regno
, ALLOCNO_MODE (a
),
2456 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2459 cost
= ALLOCNO_MEMORY_COST (a
);
2460 ira_mem_cost
+= cost
;
2462 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2464 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2465 [ira_class_hard_reg_index
2466 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2467 ira_reg_cost
+= cost
;
2471 cost
= ALLOCNO_CLASS_COST (a
);
2472 ira_reg_cost
+= cost
;
2474 ira_overall_cost
+= cost
;
2477 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2479 fprintf (ira_dump_file
,
2480 "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n",
2481 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2482 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2483 fprintf (ira_dump_file
, "+++ move loops %d, new jumps %d\n",
2484 ira_move_loops_num
, ira_additional_jumps_num
);
2489 #ifdef ENABLE_IRA_CHECKING
2490 /* Check the correctness of the allocation. We do need this because
2491 of complicated code to transform more one region internal
2492 representation into one region representation. */
2494 check_allocation (void)
2497 int hard_regno
, nregs
, conflict_nregs
;
2498 ira_allocno_iterator ai
;
2500 FOR_EACH_ALLOCNO (a
, ai
)
2502 int n
= ALLOCNO_NUM_OBJECTS (a
);
2505 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2506 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2508 nregs
= hard_regno_nregs
[hard_regno
][ALLOCNO_MODE (a
)];
2510 /* We allocated a single hard register. */
2513 /* We allocated multiple hard registers, and we will test
2514 conflicts in a granularity of single hard regs. */
2517 for (i
= 0; i
< n
; i
++)
2519 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2520 ira_object_t conflict_obj
;
2521 ira_object_conflict_iterator oci
;
2522 int this_regno
= hard_regno
;
2525 if (REG_WORDS_BIG_ENDIAN
)
2526 this_regno
+= n
- i
- 1;
2530 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2532 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2533 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2534 if (conflict_hard_regno
< 0)
2539 [conflict_hard_regno
][ALLOCNO_MODE (conflict_a
)]);
2541 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2542 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2544 if (REG_WORDS_BIG_ENDIAN
)
2545 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2546 - OBJECT_SUBWORD (conflict_obj
) - 1);
2548 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2552 if ((conflict_hard_regno
<= this_regno
2553 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2554 || (this_regno
<= conflict_hard_regno
2555 && conflict_hard_regno
< this_regno
+ nregs
))
2557 fprintf (stderr
, "bad allocation for %d and %d\n",
2558 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2567 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should
2568 be already calculated. */
2570 setup_reg_equiv_init (void)
2573 int max_regno
= max_reg_num ();
2575 for (i
= 0; i
< max_regno
; i
++)
2576 reg_equiv_init (i
) = ira_reg_equiv
[i
].init_insns
;
2579 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS
2580 are insns which were generated for such movement. It is assumed
2581 that FROM_REGNO and TO_REGNO always have the same value at the
2582 point of any move containing such registers. This function is used
2583 to update equiv info for register shuffles on the region borders
2584 and for caller save/restore insns. */
2586 ira_update_equiv_info_by_shuffle_insn (int to_regno
, int from_regno
, rtx_insn
*insns
)
2591 if (! ira_reg_equiv
[from_regno
].defined_p
2592 && (! ira_reg_equiv
[to_regno
].defined_p
2593 || ((x
= ira_reg_equiv
[to_regno
].memory
) != NULL_RTX
2594 && ! MEM_READONLY_P (x
))))
2597 if (NEXT_INSN (insn
) != NULL_RTX
)
2599 if (! ira_reg_equiv
[to_regno
].defined_p
)
2601 ira_assert (ira_reg_equiv
[to_regno
].init_insns
== NULL_RTX
);
2604 ira_reg_equiv
[to_regno
].defined_p
= false;
2605 ira_reg_equiv
[to_regno
].memory
2606 = ira_reg_equiv
[to_regno
].constant
2607 = ira_reg_equiv
[to_regno
].invariant
2608 = ira_reg_equiv
[to_regno
].init_insns
= NULL_RTX
;
2609 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2610 fprintf (ira_dump_file
,
2611 " Invalidating equiv info for reg %d\n", to_regno
);
2614 /* It is possible that FROM_REGNO still has no equivalence because
2615 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd
2616 insn was not processed yet. */
2617 if (ira_reg_equiv
[from_regno
].defined_p
)
2619 ira_reg_equiv
[to_regno
].defined_p
= true;
2620 if ((x
= ira_reg_equiv
[from_regno
].memory
) != NULL_RTX
)
2622 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
2623 && ira_reg_equiv
[from_regno
].constant
== NULL_RTX
);
2624 ira_assert (ira_reg_equiv
[to_regno
].memory
== NULL_RTX
2625 || rtx_equal_p (ira_reg_equiv
[to_regno
].memory
, x
));
2626 ira_reg_equiv
[to_regno
].memory
= x
;
2627 if (! MEM_READONLY_P (x
))
2628 /* We don't add the insn to insn init list because memory
2629 equivalence is just to say what memory is better to use
2630 when the pseudo is spilled. */
2633 else if ((x
= ira_reg_equiv
[from_regno
].constant
) != NULL_RTX
)
2635 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
);
2636 ira_assert (ira_reg_equiv
[to_regno
].constant
== NULL_RTX
2637 || rtx_equal_p (ira_reg_equiv
[to_regno
].constant
, x
));
2638 ira_reg_equiv
[to_regno
].constant
= x
;
2642 x
= ira_reg_equiv
[from_regno
].invariant
;
2643 ira_assert (x
!= NULL_RTX
);
2644 ira_assert (ira_reg_equiv
[to_regno
].invariant
== NULL_RTX
2645 || rtx_equal_p (ira_reg_equiv
[to_regno
].invariant
, x
));
2646 ira_reg_equiv
[to_regno
].invariant
= x
;
2648 if (find_reg_note (insn
, REG_EQUIV
, x
) == NULL_RTX
)
2650 note
= set_unique_reg_note (insn
, REG_EQUIV
, x
);
2651 gcc_assert (note
!= NULL_RTX
);
2652 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2654 fprintf (ira_dump_file
,
2655 " Adding equiv note to insn %u for reg %d ",
2656 INSN_UID (insn
), to_regno
);
2657 dump_value_slim (ira_dump_file
, x
, 1);
2658 fprintf (ira_dump_file
, "\n");
2662 ira_reg_equiv
[to_regno
].init_insns
2663 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
2664 ira_reg_equiv
[to_regno
].init_insns
);
2665 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2666 fprintf (ira_dump_file
,
2667 " Adding equiv init move insn %u to reg %d\n",
2668 INSN_UID (insn
), to_regno
);
2671 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2674 fix_reg_equiv_init (void)
2676 int max_regno
= max_reg_num ();
2677 int i
, new_regno
, max
;
2678 rtx x
, prev
, next
, insn
, set
;
2680 if (max_regno_before_ira
< max_regno
)
2682 max
= vec_safe_length (reg_equivs
);
2684 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2685 for (prev
= NULL_RTX
, x
= reg_equiv_init (i
);
2691 set
= single_set (insn
);
2692 ira_assert (set
!= NULL_RTX
2693 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2694 if (REG_P (SET_DEST (set
))
2695 && ((int) REGNO (SET_DEST (set
)) == i
2696 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2697 new_regno
= REGNO (SET_DEST (set
));
2698 else if (REG_P (SET_SRC (set
))
2699 && ((int) REGNO (SET_SRC (set
)) == i
2700 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2701 new_regno
= REGNO (SET_SRC (set
));
2708 /* Remove the wrong list element. */
2709 if (prev
== NULL_RTX
)
2710 reg_equiv_init (i
) = next
;
2712 XEXP (prev
, 1) = next
;
2713 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2714 reg_equiv_init (new_regno
) = x
;
2720 #ifdef ENABLE_IRA_CHECKING
2721 /* Print redundant memory-memory copies. */
2723 print_redundant_copies (void)
2727 ira_copy_t cp
, next_cp
;
2728 ira_allocno_iterator ai
;
2730 FOR_EACH_ALLOCNO (a
, ai
)
2732 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2735 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2736 if (hard_regno
>= 0)
2738 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2740 next_cp
= cp
->next_first_allocno_copy
;
2743 next_cp
= cp
->next_second_allocno_copy
;
2744 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2745 && cp
->insn
!= NULL_RTX
2746 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2747 fprintf (ira_dump_file
,
2748 " Redundant move from %d(freq %d):%d\n",
2749 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2755 /* Setup preferred and alternative classes for new pseudo-registers
2756 created by IRA starting with START. */
2758 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2761 int max_regno
= max_reg_num ();
2763 for (i
= start
; i
< max_regno
; i
++)
2765 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2766 ira_assert (i
!= old_regno
);
2767 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2768 reg_alternate_class (old_regno
),
2769 reg_allocno_class (old_regno
));
2770 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2771 fprintf (ira_dump_file
,
2772 " New r%d: setting preferred %s, alternative %s\n",
2773 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2774 reg_class_names
[reg_alternate_class (old_regno
)]);
2779 /* The number of entries allocated in teg_info. */
2780 static int allocated_reg_info_size
;
2782 /* Regional allocation can create new pseudo-registers. This function
2783 expands some arrays for pseudo-registers. */
2785 expand_reg_info (void)
2788 int size
= max_reg_num ();
2791 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2792 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2793 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2794 allocated_reg_info_size
= size
;
2797 /* Return TRUE if there is too high register pressure in the function.
2798 It is used to decide when stack slot sharing is worth to do. */
2800 too_high_register_pressure_p (void)
2803 enum reg_class pclass
;
2805 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2807 pclass
= ira_pressure_classes
[i
];
2808 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2816 /* Indicate that hard register number FROM was eliminated and replaced with
2817 an offset from hard register number TO. The status of hard registers live
2818 at the start of a basic block is updated by replacing a use of FROM with
2822 mark_elimination (int from
, int to
)
2827 FOR_EACH_BB_FN (bb
, cfun
)
2830 if (bitmap_bit_p (r
, from
))
2832 bitmap_clear_bit (r
, from
);
2833 bitmap_set_bit (r
, to
);
2837 r
= DF_LIVE_IN (bb
);
2838 if (bitmap_bit_p (r
, from
))
2840 bitmap_clear_bit (r
, from
);
2841 bitmap_set_bit (r
, to
);
2848 /* The length of the following array. */
2849 int ira_reg_equiv_len
;
2851 /* Info about equiv. info for each register. */
2852 struct ira_reg_equiv_s
*ira_reg_equiv
;
2854 /* Expand ira_reg_equiv if necessary. */
2856 ira_expand_reg_equiv (void)
2858 int old
= ira_reg_equiv_len
;
2860 if (ira_reg_equiv_len
> max_reg_num ())
2862 ira_reg_equiv_len
= max_reg_num () * 3 / 2 + 1;
2864 = (struct ira_reg_equiv_s
*) xrealloc (ira_reg_equiv
,
2866 * sizeof (struct ira_reg_equiv_s
));
2867 gcc_assert (old
< ira_reg_equiv_len
);
2868 memset (ira_reg_equiv
+ old
, 0,
2869 sizeof (struct ira_reg_equiv_s
) * (ira_reg_equiv_len
- old
));
2873 init_reg_equiv (void)
2875 ira_reg_equiv_len
= 0;
2876 ira_reg_equiv
= NULL
;
2877 ira_expand_reg_equiv ();
2881 finish_reg_equiv (void)
2883 free (ira_reg_equiv
);
2890 /* Set when a REG_EQUIV note is found or created. Use to
2891 keep track of what memory accesses might be created later,
2895 /* The list of each instruction which initializes this register. */
2897 /* Loop depth is used to recognize equivalences which appear
2898 to be present within the same loop (or in an inner loop). */
2900 /* Nonzero if this had a preexisting REG_EQUIV note. */
2901 int is_arg_equivalence
;
2902 /* Set when an attempt should be made to replace a register
2903 with the associated src_p entry. */
2907 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2908 structure for that register. */
2909 static struct equivalence
*reg_equiv
;
2911 /* Used for communication between the following two functions: contains
2912 a MEM that we wish to ensure remains unchanged. */
2913 static rtx equiv_mem
;
2915 /* Set nonzero if EQUIV_MEM is modified. */
2916 static int equiv_mem_modified
;
2918 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2919 Called via note_stores. */
2921 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2922 void *data ATTRIBUTE_UNUSED
)
2925 && reg_overlap_mentioned_p (dest
, equiv_mem
))
2927 && anti_dependence (equiv_mem
, dest
)))
2928 equiv_mem_modified
= 1;
2931 /* Verify that no store between START and the death of REG invalidates
2932 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2933 by storing into an overlapping memory location, or with a non-const
2936 Return 1 if MEMREF remains valid. */
2938 validate_equiv_mem (rtx_insn
*start
, rtx reg
, rtx memref
)
2944 equiv_mem_modified
= 0;
2946 /* If the memory reference has side effects or is volatile, it isn't a
2947 valid equivalence. */
2948 if (side_effects_p (memref
))
2951 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
2953 if (! INSN_P (insn
))
2956 if (find_reg_note (insn
, REG_DEAD
, reg
))
2959 /* This used to ignore readonly memory and const/pure calls. The problem
2960 is the equivalent form may reference a pseudo which gets assigned a
2961 call clobbered hard reg. When we later replace REG with its
2962 equivalent form, the value in the call-clobbered reg has been
2963 changed and all hell breaks loose. */
2967 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
2969 /* If a register mentioned in MEMREF is modified via an
2970 auto-increment, we lose the equivalence. Do the same if one
2971 dies; although we could extend the life, it doesn't seem worth
2974 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2975 if ((REG_NOTE_KIND (note
) == REG_INC
2976 || REG_NOTE_KIND (note
) == REG_DEAD
)
2977 && REG_P (XEXP (note
, 0))
2978 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
2985 /* Returns zero if X is known to be invariant. */
2987 equiv_init_varies_p (rtx x
)
2989 RTX_CODE code
= GET_CODE (x
);
2996 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
3005 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
3008 if (MEM_VOLATILE_P (x
))
3017 fmt
= GET_RTX_FORMAT (code
);
3018 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3021 if (equiv_init_varies_p (XEXP (x
, i
)))
3024 else if (fmt
[i
] == 'E')
3027 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3028 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
3035 /* Returns nonzero if X (used to initialize register REGNO) is movable.
3036 X is only movable if the registers it uses have equivalent initializations
3037 which appear to be within the same loop (or in an inner loop) and movable
3038 or if they are not candidates for local_alloc and don't vary. */
3040 equiv_init_movable_p (rtx x
, int regno
)
3044 enum rtx_code code
= GET_CODE (x
);
3049 return equiv_init_movable_p (SET_SRC (x
), regno
);
3064 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
3065 && reg_equiv
[REGNO (x
)].replace
)
3066 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
3067 && ! rtx_varies_p (x
, 0)));
3069 case UNSPEC_VOLATILE
:
3073 if (MEM_VOLATILE_P (x
))
3082 fmt
= GET_RTX_FORMAT (code
);
3083 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3087 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
3091 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3092 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
3100 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is
3103 contains_replace_regs (rtx x
)
3107 enum rtx_code code
= GET_CODE (x
);
3121 return reg_equiv
[REGNO (x
)].replace
;
3127 fmt
= GET_RTX_FORMAT (code
);
3128 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3132 if (contains_replace_regs (XEXP (x
, i
)))
3136 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3137 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
3145 /* TRUE if X references a memory location that would be affected by a store
3148 memref_referenced_p (rtx memref
, rtx x
)
3152 enum rtx_code code
= GET_CODE (x
);
3167 return (reg_equiv
[REGNO (x
)].replacement
3168 && memref_referenced_p (memref
,
3169 reg_equiv
[REGNO (x
)].replacement
));
3172 if (true_dependence (memref
, VOIDmode
, x
))
3177 /* If we are setting a MEM, it doesn't count (its address does), but any
3178 other SET_DEST that has a MEM in it is referencing the MEM. */
3179 if (MEM_P (SET_DEST (x
)))
3181 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
3184 else if (memref_referenced_p (memref
, SET_DEST (x
)))
3187 return memref_referenced_p (memref
, SET_SRC (x
));
3193 fmt
= GET_RTX_FORMAT (code
);
3194 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3198 if (memref_referenced_p (memref
, XEXP (x
, i
)))
3202 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3203 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
3211 /* TRUE if some insn in the range (START, END] references a memory location
3212 that would be affected by a store to MEMREF. */
3214 memref_used_between_p (rtx memref
, rtx_insn
*start
, rtx_insn
*end
)
3218 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
3219 insn
= NEXT_INSN (insn
))
3221 if (!NONDEBUG_INSN_P (insn
))
3224 if (memref_referenced_p (memref
, PATTERN (insn
)))
3227 /* Nonconst functions may access memory. */
3228 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
3235 /* Mark REG as having no known equivalence.
3236 Some instructions might have been processed before and furnished
3237 with REG_EQUIV notes for this register; these notes will have to be
3239 STORE is the piece of RTL that does the non-constant / conflicting
3240 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
3241 but needs to be there because this function is called from note_stores. */
3243 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
3244 void *data ATTRIBUTE_UNUSED
)
3251 regno
= REGNO (reg
);
3252 list
= reg_equiv
[regno
].init_insns
;
3253 if (list
== const0_rtx
)
3255 reg_equiv
[regno
].init_insns
= const0_rtx
;
3256 reg_equiv
[regno
].replacement
= NULL_RTX
;
3257 /* This doesn't matter for equivalences made for argument registers, we
3258 should keep their initialization insns. */
3259 if (reg_equiv
[regno
].is_arg_equivalence
)
3261 ira_reg_equiv
[regno
].defined_p
= false;
3262 ira_reg_equiv
[regno
].init_insns
= NULL_RTX
;
3263 for (; list
; list
= XEXP (list
, 1))
3265 rtx insn
= XEXP (list
, 0);
3266 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
3270 /* Check whether the SUBREG is a paradoxical subreg and set the result
3274 set_paradoxical_subreg (rtx_insn
*insn
, bool *pdx_subregs
)
3276 subrtx_iterator::array_type array
;
3277 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
3279 const_rtx subreg
= *iter
;
3280 if (GET_CODE (subreg
) == SUBREG
)
3282 const_rtx reg
= SUBREG_REG (subreg
);
3283 if (REG_P (reg
) && paradoxical_subreg_p (subreg
))
3284 pdx_subregs
[REGNO (reg
)] = true;
3289 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
3290 equivalent replacement. */
3293 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
3297 bitmap cleared_regs
= (bitmap
) data
;
3298 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
3299 return simplify_replace_fn_rtx (copy_rtx (*reg_equiv
[REGNO (loc
)].src_p
),
3300 NULL_RTX
, adjust_cleared_regs
, data
);
3305 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
3306 static int recorded_label_ref
;
3308 /* Find registers that are equivalent to a single value throughout the
3309 compilation (either because they can be referenced in memory or are
3310 set once from a single constant). Lower their priority for a
3313 If such a register is only referenced once, try substituting its
3314 value into the using insn. If it succeeds, we can eliminate the
3315 register completely.
3317 Initialize init_insns in ira_reg_equiv array.
3319 Return non-zero if jump label rebuilding should be done. */
3321 update_equiv_regs (void)
3326 bitmap cleared_regs
;
3329 /* We need to keep track of whether or not we recorded a LABEL_REF so
3330 that we know if the jump optimizer needs to be rerun. */
3331 recorded_label_ref
= 0;
3333 /* Use pdx_subregs to show whether a reg is used in a paradoxical
3335 pdx_subregs
= XCNEWVEC (bool, max_regno
);
3337 reg_equiv
= XCNEWVEC (struct equivalence
, max_regno
);
3340 init_alias_analysis ();
3342 /* Scan insns and set pdx_subregs[regno] if the reg is used in a
3343 paradoxical subreg. Don't set such reg sequivalent to a mem,
3344 because lra will not substitute such equiv memory in order to
3345 prevent access beyond allocated memory for paradoxical memory subreg. */
3346 FOR_EACH_BB_FN (bb
, cfun
)
3347 FOR_BB_INSNS (bb
, insn
)
3348 if (NONDEBUG_INSN_P (insn
))
3349 set_paradoxical_subreg (insn
, pdx_subregs
);
3351 /* Scan the insns and find which registers have equivalences. Do this
3352 in a separate scan of the insns because (due to -fcse-follow-jumps)
3353 a register can be set below its use. */
3354 FOR_EACH_BB_FN (bb
, cfun
)
3356 loop_depth
= bb_loop_depth (bb
);
3358 for (insn
= BB_HEAD (bb
);
3359 insn
!= NEXT_INSN (BB_END (bb
));
3360 insn
= NEXT_INSN (insn
))
3367 if (! INSN_P (insn
))
3370 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3371 if (REG_NOTE_KIND (note
) == REG_INC
)
3372 no_equiv (XEXP (note
, 0), note
, NULL
);
3374 set
= single_set (insn
);
3376 /* If this insn contains more (or less) than a single SET,
3377 only mark all destinations as having no known equivalence. */
3380 note_stores (PATTERN (insn
), no_equiv
, NULL
);
3383 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3387 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
3389 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
3391 note_stores (part
, no_equiv
, NULL
);
3395 dest
= SET_DEST (set
);
3396 src
= SET_SRC (set
);
3398 /* See if this is setting up the equivalence between an argument
3399 register and its stack slot. */
3400 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3403 gcc_assert (REG_P (dest
));
3404 regno
= REGNO (dest
);
3406 /* Note that we don't want to clear init_insns in
3407 ira_reg_equiv even if there are multiple sets of this
3409 reg_equiv
[regno
].is_arg_equivalence
= 1;
3411 /* The insn result can have equivalence memory although
3412 the equivalence is not set up by the insn. We add
3413 this insn to init insns as it is a flag for now that
3414 regno has an equivalence. We will remove the insn
3415 from init insn list later. */
3416 if (rtx_equal_p (src
, XEXP (note
, 0)) || MEM_P (XEXP (note
, 0)))
3417 ira_reg_equiv
[regno
].init_insns
3418 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3419 ira_reg_equiv
[regno
].init_insns
);
3421 /* Continue normally in case this is a candidate for
3428 /* We only handle the case of a pseudo register being set
3429 once, or always to the same value. */
3430 /* ??? The mn10200 port breaks if we add equivalences for
3431 values that need an ADDRESS_REGS register and set them equivalent
3432 to a MEM of a pseudo. The actual problem is in the over-conservative
3433 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
3434 calculate_needs, but we traditionally work around this problem
3435 here by rejecting equivalences when the destination is in a register
3436 that's likely spilled. This is fragile, of course, since the
3437 preferred class of a pseudo depends on all instructions that set
3441 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
3442 || reg_equiv
[regno
].init_insns
== const0_rtx
3443 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
3444 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
3446 /* This might be setting a SUBREG of a pseudo, a pseudo that is
3447 also set somewhere else to a constant. */
3448 note_stores (set
, no_equiv
, NULL
);
3452 /* Don't set reg (if pdx_subregs[regno] == true) equivalent to a mem. */
3453 if (MEM_P (src
) && pdx_subregs
[regno
])
3455 note_stores (set
, no_equiv
, NULL
);
3459 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
3461 /* cse sometimes generates function invariants, but doesn't put a
3462 REG_EQUAL note on the insn. Since this note would be redundant,
3463 there's no point creating it earlier than here. */
3464 if (! note
&& ! rtx_varies_p (src
, 0))
3465 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
3467 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
3468 since it represents a function call */
3469 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
3472 if (DF_REG_DEF_COUNT (regno
) != 1
3474 || rtx_varies_p (XEXP (note
, 0), 0)
3475 || (reg_equiv
[regno
].replacement
3476 && ! rtx_equal_p (XEXP (note
, 0),
3477 reg_equiv
[regno
].replacement
))))
3479 no_equiv (dest
, set
, NULL
);
3482 /* Record this insn as initializing this register. */
3483 reg_equiv
[regno
].init_insns
3484 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
3486 /* If this register is known to be equal to a constant, record that
3487 it is always equivalent to the constant. */
3488 if (DF_REG_DEF_COUNT (regno
) == 1
3489 && note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
3491 rtx note_value
= XEXP (note
, 0);
3492 remove_note (insn
, note
);
3493 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
3496 /* If this insn introduces a "constant" register, decrease the priority
3497 of that register. Record this insn if the register is only used once
3498 more and the equivalence value is the same as our source.
3500 The latter condition is checked for two reasons: First, it is an
3501 indication that it may be more efficient to actually emit the insn
3502 as written (if no registers are available, reload will substitute
3503 the equivalence). Secondly, it avoids problems with any registers
3504 dying in this insn whose death notes would be missed.
3506 If we don't have a REG_EQUIV note, see if this insn is loading
3507 a register used only in one basic block from a MEM. If so, and the
3508 MEM remains unchanged for the life of the register, add a REG_EQUIV
3511 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3513 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3514 && MEM_P (SET_SRC (set
))
3515 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
3516 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (SET_SRC (set
)));
3520 int regno
= REGNO (dest
);
3521 rtx x
= XEXP (note
, 0);
3523 /* If we haven't done so, record for reload that this is an
3524 equivalencing insn. */
3525 if (!reg_equiv
[regno
].is_arg_equivalence
)
3526 ira_reg_equiv
[regno
].init_insns
3527 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3528 ira_reg_equiv
[regno
].init_insns
);
3530 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
3531 We might end up substituting the LABEL_REF for uses of the
3532 pseudo here or later. That kind of transformation may turn an
3533 indirect jump into a direct jump, in which case we must rerun the
3534 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
3535 if (GET_CODE (x
) == LABEL_REF
3536 || (GET_CODE (x
) == CONST
3537 && GET_CODE (XEXP (x
, 0)) == PLUS
3538 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)))
3539 recorded_label_ref
= 1;
3541 reg_equiv
[regno
].replacement
= x
;
3542 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
3543 reg_equiv
[regno
].loop_depth
= loop_depth
;
3545 /* Don't mess with things live during setjmp. */
3546 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
3548 /* Note that the statement below does not affect the priority
3550 REG_LIVE_LENGTH (regno
) *= 2;
3552 /* If the register is referenced exactly twice, meaning it is
3553 set once and used once, indicate that the reference may be
3554 replaced by the equivalence we computed above. Do this
3555 even if the register is only used in one block so that
3556 dependencies can be handled where the last register is
3557 used in a different block (i.e. HIGH / LO_SUM sequences)
3558 and to reduce the number of registers alive across
3561 if (REG_N_REFS (regno
) == 2
3562 && (rtx_equal_p (x
, src
)
3563 || ! equiv_init_varies_p (src
))
3564 && NONJUMP_INSN_P (insn
)
3565 && equiv_init_movable_p (PATTERN (insn
), regno
))
3566 reg_equiv
[regno
].replace
= 1;
3575 /* A second pass, to gather additional equivalences with memory. This needs
3576 to be done after we know which registers we are going to replace. */
3578 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3583 if (! INSN_P (insn
))
3586 set
= single_set (insn
);
3590 dest
= SET_DEST (set
);
3591 src
= SET_SRC (set
);
3593 /* If this sets a MEM to the contents of a REG that is only used
3594 in a single basic block, see if the register is always equivalent
3595 to that memory location and if moving the store from INSN to the
3596 insn that set REG is safe. If so, put a REG_EQUIV note on the
3599 Don't add a REG_EQUIV note if the insn already has one. The existing
3600 REG_EQUIV is likely more useful than the one we are adding.
3602 If one of the regs in the address has reg_equiv[REGNO].replace set,
3603 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
3604 optimization may move the set of this register immediately before
3605 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
3606 the mention in the REG_EQUIV note would be to an uninitialized
3609 if (MEM_P (dest
) && REG_P (src
)
3610 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3611 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3612 && DF_REG_DEF_COUNT (regno
) == 1
3613 && reg_equiv
[regno
].init_insns
!= 0
3614 && reg_equiv
[regno
].init_insns
!= const0_rtx
3615 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
3616 REG_EQUIV
, NULL_RTX
)
3617 && ! contains_replace_regs (XEXP (dest
, 0))
3618 && ! pdx_subregs
[regno
])
3620 rtx_insn
*init_insn
=
3621 as_a
<rtx_insn
*> (XEXP (reg_equiv
[regno
].init_insns
, 0));
3622 if (validate_equiv_mem (init_insn
, src
, dest
)
3623 && ! memref_used_between_p (dest
, init_insn
, insn
)
3624 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3626 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3628 /* This insn makes the equivalence, not the one initializing
3630 ira_reg_equiv
[regno
].init_insns
3631 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3632 df_notes_rescan (init_insn
);
3637 cleared_regs
= BITMAP_ALLOC (NULL
);
3638 /* Now scan all regs killed in an insn to see if any of them are
3639 registers only used that once. If so, see if we can replace the
3640 reference with the equivalent form. If we can, delete the
3641 initializing reference and this register will go away. If we
3642 can't replace the reference, and the initializing reference is
3643 within the same loop (or in an inner loop), then move the register
3644 initialization just before the use, so that they are in the same
3646 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3648 loop_depth
= bb_loop_depth (bb
);
3649 for (insn
= BB_END (bb
);
3650 insn
!= PREV_INSN (BB_HEAD (bb
));
3651 insn
= PREV_INSN (insn
))
3655 if (! INSN_P (insn
))
3658 /* Don't substitute into a non-local goto, this confuses CFG. */
3660 && find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3663 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
3665 if (REG_NOTE_KIND (link
) == REG_DEAD
3666 /* Make sure this insn still refers to the register. */
3667 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
3669 int regno
= REGNO (XEXP (link
, 0));
3672 if (! reg_equiv
[regno
].replace
3673 || reg_equiv
[regno
].loop_depth
< loop_depth
3674 /* There is no sense to move insns if live range
3675 shrinkage or register pressure-sensitive
3676 scheduling were done because it will not
3677 improve allocation but worsen insn schedule
3678 with a big probability. */
3679 || flag_live_range_shrinkage
3680 || (flag_sched_pressure
&& flag_schedule_insns
))
3683 /* reg_equiv[REGNO].replace gets set only when
3684 REG_N_REFS[REGNO] is 2, i.e. the register is set
3685 once and used once. (If it were only set, but
3686 not used, flow would have deleted the setting
3687 insns.) Hence there can only be one insn in
3688 reg_equiv[REGNO].init_insns. */
3689 gcc_assert (reg_equiv
[regno
].init_insns
3690 && !XEXP (reg_equiv
[regno
].init_insns
, 1));
3691 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
3693 /* We may not move instructions that can throw, since
3694 that changes basic block boundaries and we are not
3695 prepared to adjust the CFG to match. */
3696 if (can_throw_internal (equiv_insn
))
3699 if (asm_noperands (PATTERN (equiv_insn
)) < 0
3700 && validate_replace_rtx (regno_reg_rtx
[regno
],
3701 *(reg_equiv
[regno
].src_p
), insn
))
3707 /* Find the last note. */
3708 for (last_link
= link
; XEXP (last_link
, 1);
3709 last_link
= XEXP (last_link
, 1))
3712 /* Append the REG_DEAD notes from equiv_insn. */
3713 equiv_link
= REG_NOTES (equiv_insn
);
3717 equiv_link
= XEXP (equiv_link
, 1);
3718 if (REG_NOTE_KIND (note
) == REG_DEAD
)
3720 remove_note (equiv_insn
, note
);
3721 XEXP (last_link
, 1) = note
;
3722 XEXP (note
, 1) = NULL_RTX
;
3727 remove_death (regno
, insn
);
3728 SET_REG_N_REFS (regno
, 0);
3729 REG_FREQ (regno
) = 0;
3730 delete_insn (equiv_insn
);
3732 reg_equiv
[regno
].init_insns
3733 = XEXP (reg_equiv
[regno
].init_insns
, 1);
3735 ira_reg_equiv
[regno
].init_insns
= NULL_RTX
;
3736 bitmap_set_bit (cleared_regs
, regno
);
3738 /* Move the initialization of the register to just before
3739 INSN. Update the flow information. */
3740 else if (prev_nondebug_insn (insn
) != equiv_insn
)
3744 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
3745 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
3746 REG_NOTES (equiv_insn
) = 0;
3747 /* Rescan it to process the notes. */
3748 df_insn_rescan (new_insn
);
3750 /* Make sure this insn is recognized before
3751 reload begins, otherwise
3752 eliminate_regs_in_insn will die. */
3753 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
3755 delete_insn (equiv_insn
);
3757 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3759 REG_BASIC_BLOCK (regno
) = bb
->index
;
3760 REG_N_CALLS_CROSSED (regno
) = 0;
3761 REG_FREQ_CALLS_CROSSED (regno
) = 0;
3762 REG_N_THROWING_CALLS_CROSSED (regno
) = 0;
3763 REG_LIVE_LENGTH (regno
) = 2;
3765 if (insn
== BB_HEAD (bb
))
3766 BB_HEAD (bb
) = PREV_INSN (insn
);
3768 ira_reg_equiv
[regno
].init_insns
3769 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3770 bitmap_set_bit (cleared_regs
, regno
);
3777 if (!bitmap_empty_p (cleared_regs
))
3779 FOR_EACH_BB_FN (bb
, cfun
)
3781 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3782 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3785 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3786 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3789 /* Last pass - adjust debug insns referencing cleared regs. */
3790 if (MAY_HAVE_DEBUG_INSNS
)
3791 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3792 if (DEBUG_INSN_P (insn
))
3794 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3795 INSN_VAR_LOCATION_LOC (insn
)
3796 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3797 adjust_cleared_regs
,
3798 (void *) cleared_regs
);
3799 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3800 df_insn_rescan (insn
);
3804 BITMAP_FREE (cleared_regs
);
3809 end_alias_analysis ();
3812 return recorded_label_ref
;
3817 /* Set up fields memory, constant, and invariant from init_insns in
3818 the structures of array ira_reg_equiv. */
3820 setup_reg_equiv (void)
3823 rtx elem
, prev_elem
, next_elem
, insn
, set
, x
;
3825 for (i
= FIRST_PSEUDO_REGISTER
; i
< ira_reg_equiv_len
; i
++)
3826 for (prev_elem
= NULL
, elem
= ira_reg_equiv
[i
].init_insns
;
3828 prev_elem
= elem
, elem
= next_elem
)
3830 next_elem
= XEXP (elem
, 1);
3831 insn
= XEXP (elem
, 0);
3832 set
= single_set (insn
);
3834 /* Init insns can set up equivalence when the reg is a destination or
3835 a source (in this case the destination is memory). */
3836 if (set
!= 0 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))))
3838 if ((x
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL
)
3841 if (REG_P (SET_DEST (set
))
3842 && REGNO (SET_DEST (set
)) == (unsigned int) i
3843 && ! rtx_equal_p (SET_SRC (set
), x
) && MEM_P (x
))
3845 /* This insn reporting the equivalence but
3846 actually not setting it. Remove it from the
3848 if (prev_elem
== NULL
)
3849 ira_reg_equiv
[i
].init_insns
= next_elem
;
3851 XEXP (prev_elem
, 1) = next_elem
;
3855 else if (REG_P (SET_DEST (set
))
3856 && REGNO (SET_DEST (set
)) == (unsigned int) i
)
3860 gcc_assert (REG_P (SET_SRC (set
))
3861 && REGNO (SET_SRC (set
)) == (unsigned int) i
);
3864 if (! function_invariant_p (x
)
3866 /* A function invariant is often CONSTANT_P but may
3867 include a register. We promise to only pass
3868 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
3869 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
3871 /* It can happen that a REG_EQUIV note contains a MEM
3872 that is not a legitimate memory operand. As later
3873 stages of reload assume that all addresses found in
3874 the lra_regno_equiv_* arrays were originally
3875 legitimate, we ignore such REG_EQUIV notes. */
3876 if (memory_operand (x
, VOIDmode
))
3878 ira_reg_equiv
[i
].defined_p
= true;
3879 ira_reg_equiv
[i
].memory
= x
;
3882 else if (function_invariant_p (x
))
3884 enum machine_mode mode
;
3886 mode
= GET_MODE (SET_DEST (set
));
3887 if (GET_CODE (x
) == PLUS
3888 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
3889 /* This is PLUS of frame pointer and a constant,
3891 ira_reg_equiv
[i
].invariant
= x
;
3892 else if (targetm
.legitimate_constant_p (mode
, x
))
3893 ira_reg_equiv
[i
].constant
= x
;
3896 ira_reg_equiv
[i
].memory
= force_const_mem (mode
, x
);
3897 if (ira_reg_equiv
[i
].memory
== NULL_RTX
)
3899 ira_reg_equiv
[i
].defined_p
= false;
3900 ira_reg_equiv
[i
].init_insns
= NULL_RTX
;
3904 ira_reg_equiv
[i
].defined_p
= true;
3909 ira_reg_equiv
[i
].defined_p
= false;
3910 ira_reg_equiv
[i
].init_insns
= NULL_RTX
;
3917 /* Print chain C to FILE. */
3919 print_insn_chain (FILE *file
, struct insn_chain
*c
)
3921 fprintf (file
, "insn=%d, ", INSN_UID (c
->insn
));
3922 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
3923 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
3927 /* Print all reload_insn_chains to FILE. */
3929 print_insn_chains (FILE *file
)
3931 struct insn_chain
*c
;
3932 for (c
= reload_insn_chain
; c
; c
= c
->next
)
3933 print_insn_chain (file
, c
);
3936 /* Return true if pseudo REGNO should be added to set live_throughout
3937 or dead_or_set of the insn chains for reload consideration. */
3939 pseudo_for_reload_consideration_p (int regno
)
3941 /* Consider spilled pseudos too for IRA because they still have a
3942 chance to get hard-registers in the reload when IRA is used. */
3943 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
3946 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using
3947 REG to the number of nregs, and INIT_VALUE to get the
3948 initialization. ALLOCNUM need not be the regno of REG. */
3950 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
3951 bitmap live_subregs_used
, int allocnum
, rtx reg
)
3953 unsigned int regno
= REGNO (SUBREG_REG (reg
));
3954 int size
= GET_MODE_SIZE (GET_MODE (regno_reg_rtx
[regno
]));
3956 gcc_assert (size
> 0);
3958 /* Been there, done that. */
3959 if (bitmap_bit_p (live_subregs_used
, allocnum
))
3962 /* Create a new one. */
3963 if (live_subregs
[allocnum
] == NULL
)
3964 live_subregs
[allocnum
] = sbitmap_alloc (size
);
3966 /* If the entire reg was live before blasting into subregs, we need
3967 to init all of the subregs to ones else init to 0. */
3969 bitmap_ones (live_subregs
[allocnum
]);
3971 bitmap_clear (live_subregs
[allocnum
]);
3973 bitmap_set_bit (live_subregs_used
, allocnum
);
3976 /* Walk the insns of the current function and build reload_insn_chain,
3977 and record register life information. */
3979 build_insn_chain (void)
3982 struct insn_chain
**p
= &reload_insn_chain
;
3984 struct insn_chain
*c
= NULL
;
3985 struct insn_chain
*next
= NULL
;
3986 bitmap live_relevant_regs
= BITMAP_ALLOC (NULL
);
3987 bitmap elim_regset
= BITMAP_ALLOC (NULL
);
3988 /* live_subregs is a vector used to keep accurate information about
3989 which hardregs are live in multiword pseudos. live_subregs and
3990 live_subregs_used are indexed by pseudo number. The live_subreg
3991 entry for a particular pseudo is only used if the corresponding
3992 element is non zero in live_subregs_used. The sbitmap size of
3993 live_subreg[allocno] is number of bytes that the pseudo can
3995 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
3996 bitmap live_subregs_used
= BITMAP_ALLOC (NULL
);
3998 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3999 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
4000 bitmap_set_bit (elim_regset
, i
);
4001 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
4006 CLEAR_REG_SET (live_relevant_regs
);
4007 bitmap_clear (live_subregs_used
);
4009 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
), 0, i
, bi
)
4011 if (i
>= FIRST_PSEUDO_REGISTER
)
4013 bitmap_set_bit (live_relevant_regs
, i
);
4016 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
),
4017 FIRST_PSEUDO_REGISTER
, i
, bi
)
4019 if (pseudo_for_reload_consideration_p (i
))
4020 bitmap_set_bit (live_relevant_regs
, i
);
4023 FOR_BB_INSNS_REVERSE (bb
, insn
)
4025 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4027 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4030 c
= new_insn_chain ();
4037 c
->block
= bb
->index
;
4039 if (NONDEBUG_INSN_P (insn
))
4040 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4042 unsigned int regno
= DF_REF_REGNO (def
);
4044 /* Ignore may clobbers because these are generated
4045 from calls. However, every other kind of def is
4046 added to dead_or_set. */
4047 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
4049 if (regno
< FIRST_PSEUDO_REGISTER
)
4051 if (!fixed_regs
[regno
])
4052 bitmap_set_bit (&c
->dead_or_set
, regno
);
4054 else if (pseudo_for_reload_consideration_p (regno
))
4055 bitmap_set_bit (&c
->dead_or_set
, regno
);
4058 if ((regno
< FIRST_PSEUDO_REGISTER
4059 || reg_renumber
[regno
] >= 0
4061 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
4063 rtx reg
= DF_REF_REG (def
);
4065 /* We can model subregs, but not if they are
4066 wrapped in ZERO_EXTRACTS. */
4067 if (GET_CODE (reg
) == SUBREG
4068 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
))
4070 unsigned int start
= SUBREG_BYTE (reg
);
4071 unsigned int last
= start
4072 + GET_MODE_SIZE (GET_MODE (reg
));
4075 (bitmap_bit_p (live_relevant_regs
, regno
),
4076 live_subregs
, live_subregs_used
, regno
, reg
);
4078 if (!DF_REF_FLAGS_IS_SET
4079 (def
, DF_REF_STRICT_LOW_PART
))
4081 /* Expand the range to cover entire words.
4082 Bytes added here are "don't care". */
4084 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
4085 last
= ((last
+ UNITS_PER_WORD
- 1)
4086 / UNITS_PER_WORD
* UNITS_PER_WORD
);
4089 /* Ignore the paradoxical bits. */
4090 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4091 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4093 while (start
< last
)
4095 bitmap_clear_bit (live_subregs
[regno
], start
);
4099 if (bitmap_empty_p (live_subregs
[regno
]))
4101 bitmap_clear_bit (live_subregs_used
, regno
);
4102 bitmap_clear_bit (live_relevant_regs
, regno
);
4105 /* Set live_relevant_regs here because
4106 that bit has to be true to get us to
4107 look at the live_subregs fields. */
4108 bitmap_set_bit (live_relevant_regs
, regno
);
4112 /* DF_REF_PARTIAL is generated for
4113 subregs, STRICT_LOW_PART, and
4114 ZERO_EXTRACT. We handle the subreg
4115 case above so here we have to keep from
4116 modeling the def as a killing def. */
4117 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
4119 bitmap_clear_bit (live_subregs_used
, regno
);
4120 bitmap_clear_bit (live_relevant_regs
, regno
);
4126 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
4127 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4129 if (NONDEBUG_INSN_P (insn
))
4130 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4132 unsigned int regno
= DF_REF_REGNO (use
);
4133 rtx reg
= DF_REF_REG (use
);
4135 /* DF_REF_READ_WRITE on a use means that this use
4136 is fabricated from a def that is a partial set
4137 to a multiword reg. Here, we only model the
4138 subreg case that is not wrapped in ZERO_EXTRACT
4139 precisely so we do not need to look at the
4141 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
4142 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
4143 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
4146 /* Add the last use of each var to dead_or_set. */
4147 if (!bitmap_bit_p (live_relevant_regs
, regno
))
4149 if (regno
< FIRST_PSEUDO_REGISTER
)
4151 if (!fixed_regs
[regno
])
4152 bitmap_set_bit (&c
->dead_or_set
, regno
);
4154 else if (pseudo_for_reload_consideration_p (regno
))
4155 bitmap_set_bit (&c
->dead_or_set
, regno
);
4158 if (regno
< FIRST_PSEUDO_REGISTER
4159 || pseudo_for_reload_consideration_p (regno
))
4161 if (GET_CODE (reg
) == SUBREG
4162 && !DF_REF_FLAGS_IS_SET (use
,
4164 | DF_REF_ZERO_EXTRACT
))
4166 unsigned int start
= SUBREG_BYTE (reg
);
4167 unsigned int last
= start
4168 + GET_MODE_SIZE (GET_MODE (reg
));
4171 (bitmap_bit_p (live_relevant_regs
, regno
),
4172 live_subregs
, live_subregs_used
, regno
, reg
);
4174 /* Ignore the paradoxical bits. */
4175 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4176 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4178 while (start
< last
)
4180 bitmap_set_bit (live_subregs
[regno
], start
);
4185 /* Resetting the live_subregs_used is
4186 effectively saying do not use the subregs
4187 because we are reading the whole
4189 bitmap_clear_bit (live_subregs_used
, regno
);
4190 bitmap_set_bit (live_relevant_regs
, regno
);
4196 /* FIXME!! The following code is a disaster. Reload needs to see the
4197 labels and jump tables that are just hanging out in between
4198 the basic blocks. See pr33676. */
4199 insn
= BB_HEAD (bb
);
4201 /* Skip over the barriers and cruft. */
4202 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
4203 || BLOCK_FOR_INSN (insn
) == bb
))
4204 insn
= PREV_INSN (insn
);
4206 /* While we add anything except barriers and notes, the focus is
4207 to get the labels and jump tables into the
4208 reload_insn_chain. */
4211 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4213 if (BLOCK_FOR_INSN (insn
))
4216 c
= new_insn_chain ();
4222 /* The block makes no sense here, but it is what the old
4224 c
->block
= bb
->index
;
4226 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4228 insn
= PREV_INSN (insn
);
4232 reload_insn_chain
= c
;
4235 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
4236 if (live_subregs
[i
] != NULL
)
4237 sbitmap_free (live_subregs
[i
]);
4238 free (live_subregs
);
4239 BITMAP_FREE (live_subregs_used
);
4240 BITMAP_FREE (live_relevant_regs
);
4241 BITMAP_FREE (elim_regset
);
4244 print_insn_chains (dump_file
);
4247 /* Examine the rtx found in *LOC, which is read or written to as determined
4248 by TYPE. Return false if we find a reason why an insn containing this
4249 rtx should not be moved (such as accesses to non-constant memory), true
4252 rtx_moveable_p (rtx
*loc
, enum op_type type
)
4256 enum rtx_code code
= GET_CODE (x
);
4259 code
= GET_CODE (x
);
4269 return type
== OP_IN
;
4275 if (x
== frame_pointer_rtx
)
4277 if (HARD_REGISTER_P (x
))
4283 if (type
== OP_IN
&& MEM_READONLY_P (x
))
4284 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
4288 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
4289 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
4291 case STRICT_LOW_PART
:
4292 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
4296 return (rtx_moveable_p (&XEXP (x
, 0), type
)
4297 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
4298 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
4301 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
4307 fmt
= GET_RTX_FORMAT (code
);
4308 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4312 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
4315 else if (fmt
[i
] == 'E')
4316 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4318 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
4325 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
4326 to give dominance relationships between two insns I1 and I2. */
4328 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
4330 basic_block bb1
= BLOCK_FOR_INSN (i1
);
4331 basic_block bb2
= BLOCK_FOR_INSN (i2
);
4334 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
4335 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
4338 /* Record the range of register numbers added by find_moveable_pseudos. */
4339 int first_moveable_pseudo
, last_moveable_pseudo
;
4341 /* These two vectors hold data for every register added by
4342 find_movable_pseudos, with index 0 holding data for the
4343 first_moveable_pseudo. */
4344 /* The original home register. */
4345 static vec
<rtx
> pseudo_replaced_reg
;
4347 /* Look for instances where we have an instruction that is known to increase
4348 register pressure, and whose result is not used immediately. If it is
4349 possible to move the instruction downwards to just before its first use,
4350 split its lifetime into two ranges. We create a new pseudo to compute the
4351 value, and emit a move instruction just before the first use. If, after
4352 register allocation, the new pseudo remains unallocated, the function
4353 move_unallocated_pseudos then deletes the move instruction and places
4354 the computation just before the first use.
4356 Such a move is safe and profitable if all the input registers remain live
4357 and unchanged between the original computation and its first use. In such
4358 a situation, the computation is known to increase register pressure, and
4359 moving it is known to at least not worsen it.
4361 We restrict moves to only those cases where a register remains unallocated,
4362 in order to avoid interfering too much with the instruction schedule. As
4363 an exception, we may move insns which only modify their input register
4364 (typically induction variables), as this increases the freedom for our
4365 intended transformation, and does not limit the second instruction
4369 find_moveable_pseudos (void)
4372 int max_regs
= max_reg_num ();
4373 int max_uid
= get_max_uid ();
4375 int *uid_luid
= XNEWVEC (int, max_uid
);
4376 rtx_insn
**closest_uses
= XNEWVEC (rtx_insn
*, max_regs
);
4377 /* A set of registers which are live but not modified throughout a block. */
4378 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
,
4379 last_basic_block_for_fn (cfun
));
4380 /* A set of registers which only exist in a given basic block. */
4381 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
,
4382 last_basic_block_for_fn (cfun
));
4383 /* A set of registers which are set once, in an instruction that can be
4384 moved freely downwards, but are otherwise transparent to a block. */
4385 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
,
4386 last_basic_block_for_fn (cfun
));
4387 bitmap_head live
, used
, set
, interesting
, unusable_as_input
;
4389 bitmap_initialize (&interesting
, 0);
4391 first_moveable_pseudo
= max_regs
;
4392 pseudo_replaced_reg
.release ();
4393 pseudo_replaced_reg
.safe_grow_cleared (max_regs
);
4396 calculate_dominance_info (CDI_DOMINATORS
);
4399 bitmap_initialize (&live
, 0);
4400 bitmap_initialize (&used
, 0);
4401 bitmap_initialize (&set
, 0);
4402 bitmap_initialize (&unusable_as_input
, 0);
4403 FOR_EACH_BB_FN (bb
, cfun
)
4406 bitmap transp
= bb_transp_live
+ bb
->index
;
4407 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
4408 bitmap local
= bb_local
+ bb
->index
;
4410 bitmap_initialize (local
, 0);
4411 bitmap_initialize (transp
, 0);
4412 bitmap_initialize (moveable
, 0);
4413 bitmap_copy (&live
, df_get_live_out (bb
));
4414 bitmap_and_into (&live
, df_get_live_in (bb
));
4415 bitmap_copy (transp
, &live
);
4416 bitmap_clear (moveable
);
4417 bitmap_clear (&live
);
4418 bitmap_clear (&used
);
4419 bitmap_clear (&set
);
4420 FOR_BB_INSNS (bb
, insn
)
4421 if (NONDEBUG_INSN_P (insn
))
4423 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4426 uid_luid
[INSN_UID (insn
)] = i
++;
4428 def
= df_single_def (insn_info
);
4429 use
= df_single_use (insn_info
);
4432 && DF_REF_REGNO (use
) == DF_REF_REGNO (def
)
4433 && !bitmap_bit_p (&set
, DF_REF_REGNO (use
))
4434 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
4436 unsigned regno
= DF_REF_REGNO (use
);
4437 bitmap_set_bit (moveable
, regno
);
4438 bitmap_set_bit (&set
, regno
);
4439 bitmap_set_bit (&used
, regno
);
4440 bitmap_clear_bit (transp
, regno
);
4443 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4445 unsigned regno
= DF_REF_REGNO (use
);
4446 bitmap_set_bit (&used
, regno
);
4447 if (bitmap_clear_bit (moveable
, regno
))
4448 bitmap_clear_bit (transp
, regno
);
4451 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4453 unsigned regno
= DF_REF_REGNO (def
);
4454 bitmap_set_bit (&set
, regno
);
4455 bitmap_clear_bit (transp
, regno
);
4456 bitmap_clear_bit (moveable
, regno
);
4461 bitmap_clear (&live
);
4462 bitmap_clear (&used
);
4463 bitmap_clear (&set
);
4465 FOR_EACH_BB_FN (bb
, cfun
)
4467 bitmap local
= bb_local
+ bb
->index
;
4470 FOR_BB_INSNS (bb
, insn
)
4471 if (NONDEBUG_INSN_P (insn
))
4473 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4475 rtx closest_use
, note
;
4478 bool all_dominated
, all_local
;
4479 enum machine_mode mode
;
4481 def
= df_single_def (insn_info
);
4482 /* There must be exactly one def in this insn. */
4483 if (!def
|| !single_set (insn
))
4485 /* This must be the only definition of the reg. We also limit
4486 which modes we deal with so that we can assume we can generate
4487 move instructions. */
4488 regno
= DF_REF_REGNO (def
);
4489 mode
= GET_MODE (DF_REF_REG (def
));
4490 if (DF_REG_DEF_COUNT (regno
) != 1
4491 || !DF_REF_INSN_INFO (def
)
4492 || HARD_REGISTER_NUM_P (regno
)
4493 || DF_REG_EQ_USE_COUNT (regno
) > 0
4494 || (!INTEGRAL_MODE_P (mode
) && !FLOAT_MODE_P (mode
)))
4496 def_insn
= DF_REF_INSN (def
);
4498 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
4499 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
4505 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
4507 bitmap_set_bit (&unusable_as_input
, regno
);
4511 use
= DF_REG_USE_CHAIN (regno
);
4512 all_dominated
= true;
4514 closest_use
= NULL_RTX
;
4515 for (; use
; use
= DF_REF_NEXT_REG (use
))
4518 if (!DF_REF_INSN_INFO (use
))
4520 all_dominated
= false;
4524 insn
= DF_REF_INSN (use
);
4525 if (DEBUG_INSN_P (insn
))
4527 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
4529 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
4530 all_dominated
= false;
4531 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
4533 if (closest_use
== NULL_RTX
)
4535 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
4537 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
4538 closest_use
= const0_rtx
;
4544 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
4549 bitmap_set_bit (local
, regno
);
4550 if (closest_use
== const0_rtx
|| closest_use
== NULL
4551 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
4554 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
4555 closest_use
== const0_rtx
|| closest_use
== NULL
4556 ? " (no unique first use)" : "");
4560 if (reg_referenced_p (cc0_rtx
, PATTERN (closest_use
)))
4563 fprintf (dump_file
, "Reg %d: closest user uses cc0\n",
4568 bitmap_set_bit (&interesting
, regno
);
4569 /* If we get here, we know closest_use is a non-NULL insn
4570 (as opposed to const_0_rtx). */
4571 closest_uses
[regno
] = as_a
<rtx_insn
*> (closest_use
);
4573 if (dump_file
&& (all_local
|| all_dominated
))
4575 fprintf (dump_file
, "Reg %u:", regno
);
4577 fprintf (dump_file
, " local to bb %d", bb
->index
);
4579 fprintf (dump_file
, " def dominates all uses");
4580 if (closest_use
!= const0_rtx
)
4581 fprintf (dump_file
, " has unique first use");
4582 fputs ("\n", dump_file
);
4587 EXECUTE_IF_SET_IN_BITMAP (&interesting
, 0, i
, bi
)
4589 df_ref def
= DF_REG_DEF_CHAIN (i
);
4590 rtx_insn
*def_insn
= DF_REF_INSN (def
);
4591 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
4592 bitmap def_bb_local
= bb_local
+ def_block
->index
;
4593 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
4594 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
4595 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
4596 rtx_insn
*use_insn
= closest_uses
[i
];
4599 bool all_transp
= true;
4601 if (!REG_P (DF_REF_REG (def
)))
4607 fprintf (dump_file
, "Reg %u not local to one basic block\n",
4611 if (reg_equiv_init (i
) != NULL_RTX
)
4614 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
4618 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
4621 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
4622 INSN_UID (def_insn
), i
);
4626 fprintf (dump_file
, "Examining insn %d, def for %d\n",
4627 INSN_UID (def_insn
), i
);
4628 FOR_EACH_INSN_USE (use
, def_insn
)
4630 unsigned regno
= DF_REF_REGNO (use
);
4631 if (bitmap_bit_p (&unusable_as_input
, regno
))
4635 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
4638 if (!bitmap_bit_p (def_bb_transp
, regno
))
4640 if (bitmap_bit_p (def_bb_moveable
, regno
)
4641 && !control_flow_insn_p (use_insn
)
4643 && !sets_cc0_p (use_insn
)
4647 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
4649 rtx_insn
*x
= NEXT_INSN (def_insn
);
4650 while (!modified_in_p (DF_REF_REG (use
), x
))
4652 gcc_assert (x
!= use_insn
);
4656 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
4657 regno
, INSN_UID (x
));
4658 emit_insn_after (PATTERN (x
), use_insn
);
4659 set_insn_deleted (x
);
4664 fprintf (dump_file
, " input reg %u modified between def and use\n",
4675 if (!dbg_cnt (ira_move
))
4678 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
4682 rtx def_reg
= DF_REF_REG (def
);
4683 rtx newreg
= ira_create_new_reg (def_reg
);
4684 if (validate_change (def_insn
, DF_REF_REAL_LOC (def
), newreg
, 0))
4686 unsigned nregno
= REGNO (newreg
);
4687 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
4689 pseudo_replaced_reg
[nregno
] = def_reg
;
4694 FOR_EACH_BB_FN (bb
, cfun
)
4696 bitmap_clear (bb_local
+ bb
->index
);
4697 bitmap_clear (bb_transp_live
+ bb
->index
);
4698 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
4700 bitmap_clear (&interesting
);
4701 bitmap_clear (&unusable_as_input
);
4703 free (closest_uses
);
4705 free (bb_transp_live
);
4706 free (bb_moveable_reg_sets
);
4708 last_moveable_pseudo
= max_reg_num ();
4710 fix_reg_equiv_init ();
4712 regstat_free_n_sets_and_refs ();
4714 regstat_init_n_sets_and_refs ();
4715 regstat_compute_ri ();
4716 free_dominance_info (CDI_DOMINATORS
);
4719 /* If SET pattern SET is an assignment from a hard register to a pseudo which
4720 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return
4721 the destination. Otherwise return NULL. */
4724 interesting_dest_for_shprep_1 (rtx set
, basic_block call_dom
)
4726 rtx src
= SET_SRC (set
);
4727 rtx dest
= SET_DEST (set
);
4728 if (!REG_P (src
) || !HARD_REGISTER_P (src
)
4729 || !REG_P (dest
) || HARD_REGISTER_P (dest
)
4730 || (call_dom
&& !bitmap_bit_p (df_get_live_in (call_dom
), REGNO (dest
))))
4735 /* If insn is interesting for parameter range-splitting shring-wrapping
4736 preparation, i.e. it is a single set from a hard register to a pseudo, which
4737 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a
4738 parallel statement with only one such statement, return the destination.
4739 Otherwise return NULL. */
4742 interesting_dest_for_shprep (rtx_insn
*insn
, basic_block call_dom
)
4746 rtx pat
= PATTERN (insn
);
4747 if (GET_CODE (pat
) == SET
)
4748 return interesting_dest_for_shprep_1 (pat
, call_dom
);
4750 if (GET_CODE (pat
) != PARALLEL
)
4753 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
4755 rtx sub
= XVECEXP (pat
, 0, i
);
4756 if (GET_CODE (sub
) == USE
|| GET_CODE (sub
) == CLOBBER
)
4758 if (GET_CODE (sub
) != SET
4759 || side_effects_p (sub
))
4761 rtx dest
= interesting_dest_for_shprep_1 (sub
, call_dom
);
4770 /* Split live ranges of pseudos that are loaded from hard registers in the
4771 first BB in a BB that dominates all non-sibling call if such a BB can be
4772 found and is not in a loop. Return true if the function has made any
4776 split_live_ranges_for_shrink_wrap (void)
4778 basic_block bb
, call_dom
= NULL
;
4779 basic_block first
= single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
4780 rtx_insn
*insn
, *last_interesting_insn
= NULL
;
4781 bitmap_head need_new
, reachable
;
4782 vec
<basic_block
> queue
;
4784 if (!SHRINK_WRAPPING_ENABLED
)
4787 bitmap_initialize (&need_new
, 0);
4788 bitmap_initialize (&reachable
, 0);
4789 queue
.create (n_basic_blocks_for_fn (cfun
));
4791 FOR_EACH_BB_FN (bb
, cfun
)
4792 FOR_BB_INSNS (bb
, insn
)
4793 if (CALL_P (insn
) && !SIBLING_CALL_P (insn
))
4797 bitmap_clear (&need_new
);
4798 bitmap_clear (&reachable
);
4803 bitmap_set_bit (&need_new
, bb
->index
);
4804 bitmap_set_bit (&reachable
, bb
->index
);
4805 queue
.quick_push (bb
);
4809 if (queue
.is_empty ())
4811 bitmap_clear (&need_new
);
4812 bitmap_clear (&reachable
);
4817 while (!queue
.is_empty ())
4823 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4824 if (e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
4825 && bitmap_set_bit (&reachable
, e
->dest
->index
))
4826 queue
.quick_push (e
->dest
);
4830 FOR_BB_INSNS (first
, insn
)
4832 rtx dest
= interesting_dest_for_shprep (insn
, NULL
);
4836 if (DF_REG_DEF_COUNT (REGNO (dest
)) > 1)
4838 bitmap_clear (&need_new
);
4839 bitmap_clear (&reachable
);
4843 for (df_ref use
= DF_REG_USE_CHAIN (REGNO(dest
));
4845 use
= DF_REF_NEXT_REG (use
))
4847 int ubbi
= DF_REF_BB (use
)->index
;
4848 if (bitmap_bit_p (&reachable
, ubbi
))
4849 bitmap_set_bit (&need_new
, ubbi
);
4851 last_interesting_insn
= insn
;
4854 bitmap_clear (&reachable
);
4855 if (!last_interesting_insn
)
4857 bitmap_clear (&need_new
);
4861 call_dom
= nearest_common_dominator_for_set (CDI_DOMINATORS
, &need_new
);
4862 bitmap_clear (&need_new
);
4863 if (call_dom
== first
)
4866 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
4867 while (bb_loop_depth (call_dom
) > 0)
4868 call_dom
= get_immediate_dominator (CDI_DOMINATORS
, call_dom
);
4869 loop_optimizer_finalize ();
4871 if (call_dom
== first
)
4874 calculate_dominance_info (CDI_POST_DOMINATORS
);
4875 if (dominated_by_p (CDI_POST_DOMINATORS
, first
, call_dom
))
4877 free_dominance_info (CDI_POST_DOMINATORS
);
4880 free_dominance_info (CDI_POST_DOMINATORS
);
4883 fprintf (dump_file
, "Will split live ranges of parameters at BB %i\n",
4887 FOR_BB_INSNS (first
, insn
)
4889 rtx dest
= interesting_dest_for_shprep (insn
, call_dom
);
4893 rtx newreg
= NULL_RTX
;
4895 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
4897 rtx_insn
*uin
= DF_REF_INSN (use
);
4898 next
= DF_REF_NEXT_REG (use
);
4900 basic_block ubb
= BLOCK_FOR_INSN (uin
);
4902 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
4905 newreg
= ira_create_new_reg (dest
);
4906 validate_change (uin
, DF_REF_REAL_LOC (use
), newreg
, true);
4912 rtx new_move
= gen_move_insn (newreg
, dest
);
4913 emit_insn_after (new_move
, bb_note (call_dom
));
4916 fprintf (dump_file
, "Split live-range of register ");
4917 print_rtl_single (dump_file
, dest
);
4922 if (insn
== last_interesting_insn
)
4925 apply_change_group ();
4929 /* Perform the second half of the transformation started in
4930 find_moveable_pseudos. We look for instances where the newly introduced
4931 pseudo remains unallocated, and remove it by moving the definition to
4932 just before its use, replacing the move instruction generated by
4933 find_moveable_pseudos. */
4935 move_unallocated_pseudos (void)
4938 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
4939 if (reg_renumber
[i
] < 0)
4941 int idx
= i
- first_moveable_pseudo
;
4942 rtx other_reg
= pseudo_replaced_reg
[idx
];
4943 rtx_insn
*def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
4944 /* The use must follow all definitions of OTHER_REG, so we can
4945 insert the new definition immediately after any of them. */
4946 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
4947 rtx_insn
*move_insn
= DF_REF_INSN (other_def
);
4948 rtx_insn
*newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
4953 fprintf (dump_file
, "moving def of %d (insn %d now) ",
4954 REGNO (other_reg
), INSN_UID (def_insn
));
4956 delete_insn (move_insn
);
4957 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
4958 delete_insn (DF_REF_INSN (other_def
));
4959 delete_insn (def_insn
);
4961 set
= single_set (newinsn
);
4962 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
4963 gcc_assert (success
);
4965 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
4966 INSN_UID (newinsn
), i
);
4967 SET_REG_N_REFS (i
, 0);
4971 /* If the backend knows where to allocate pseudos for hard
4972 register initial values, register these allocations now. */
4974 allocate_initial_values (void)
4976 if (targetm
.allocate_initial_value
)
4981 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
4983 if (! initial_value_entry (i
, &hreg
, &preg
))
4986 x
= targetm
.allocate_initial_value (hreg
);
4987 regno
= REGNO (preg
);
4988 if (x
&& REG_N_SETS (regno
) <= 1)
4991 reg_equiv_memory_loc (regno
) = x
;
4997 gcc_assert (REG_P (x
));
4998 new_regno
= REGNO (x
);
4999 reg_renumber
[regno
] = new_regno
;
5000 /* Poke the regno right into regno_reg_rtx so that even
5001 fixed regs are accepted. */
5002 SET_REGNO (preg
, new_regno
);
5003 /* Update global register liveness information. */
5004 FOR_EACH_BB_FN (bb
, cfun
)
5006 if (REGNO_REG_SET_P (df_get_live_in (bb
), regno
))
5007 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
5008 if (REGNO_REG_SET_P (df_get_live_out (bb
), regno
))
5009 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
5015 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
5021 /* True when we use LRA instead of reload pass for the current
5025 /* True if we have allocno conflicts. It is false for non-optimized
5026 mode or when the conflict table is too big. */
5027 bool ira_conflicts_p
;
5029 /* Saved between IRA and reload. */
5030 static int saved_flag_ira_share_spill_slots
;
5032 /* This is the main entry of IRA. */
5037 int ira_max_point_before_emit
;
5039 bool saved_flag_caller_saves
= flag_caller_saves
;
5040 enum ira_region saved_flag_ira_region
= flag_ira_region
;
5042 ira_conflicts_p
= optimize
> 0;
5044 ira_use_lra_p
= targetm
.lra_p ();
5045 /* If there are too many pseudos and/or basic blocks (e.g. 10K
5046 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will
5047 use simplified and faster algorithms in LRA. */
5050 && max_reg_num () >= (1 << 26) / last_basic_block_for_fn (cfun
));
5053 /* It permits to skip live range splitting in LRA. */
5054 flag_caller_saves
= false;
5055 /* There is no sense to do regional allocation when we use
5057 flag_ira_region
= IRA_REGION_ONE
;
5058 ira_conflicts_p
= false;
5061 #ifndef IRA_NO_OBSTACK
5062 gcc_obstack_init (&ira_obstack
);
5064 bitmap_obstack_initialize (&ira_bitmap_obstack
);
5066 /* LRA uses its own infrastructure to handle caller save registers. */
5067 if (flag_caller_saves
&& !ira_use_lra_p
)
5068 init_caller_save ();
5070 if (flag_ira_verbose
< 10)
5072 internal_flag_ira_verbose
= flag_ira_verbose
;
5077 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
5078 ira_dump_file
= stderr
;
5081 setup_prohibited_mode_move_regs ();
5082 decrease_live_ranges_number ();
5083 df_note_add_problem ();
5085 /* DF_LIVE can't be used in the register allocator, too many other
5086 parts of the compiler depend on using the "classic" liveness
5087 interpretation of the DF_LR problem. See PR38711.
5088 Remove the problem, so that we don't spend time updating it in
5089 any of the df_analyze() calls during IRA/LRA. */
5091 df_remove_problem (df_live
);
5092 gcc_checking_assert (df_live
== NULL
);
5094 #ifdef ENABLE_CHECKING
5095 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
5100 if (ira_conflicts_p
)
5102 calculate_dominance_info (CDI_DOMINATORS
);
5104 if (split_live_ranges_for_shrink_wrap ())
5107 free_dominance_info (CDI_DOMINATORS
);
5110 df_clear_flags (DF_NO_INSN_RESCAN
);
5112 regstat_init_n_sets_and_refs ();
5113 regstat_compute_ri ();
5115 /* If we are not optimizing, then this is the only place before
5116 register allocation where dataflow is done. And that is needed
5117 to generate these warnings. */
5119 generate_setjmp_warnings ();
5121 /* Determine if the current function is a leaf before running IRA
5122 since this can impact optimizations done by the prologue and
5123 epilogue thus changing register elimination offsets. */
5124 crtl
->is_leaf
= leaf_function_p ();
5126 if (resize_reg_info () && flag_ira_loop_pressure
)
5127 ira_set_pseudo_classes (true, ira_dump_file
);
5129 rebuild_p
= update_equiv_regs ();
5131 setup_reg_equiv_init ();
5133 if (optimize
&& rebuild_p
)
5135 timevar_push (TV_JUMP
);
5136 rebuild_jump_labels (get_insns ());
5137 if (purge_all_dead_edges ())
5138 delete_unreachable_blocks ();
5139 timevar_pop (TV_JUMP
);
5142 allocated_reg_info_size
= max_reg_num ();
5144 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
5147 /* It is not worth to do such improvement when we use a simple
5148 allocation because of -O0 usage or because the function is too
5150 if (ira_conflicts_p
)
5151 find_moveable_pseudos ();
5153 max_regno_before_ira
= max_reg_num ();
5154 ira_setup_eliminable_regset ();
5156 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
5157 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
5158 ira_move_loops_num
= ira_additional_jumps_num
= 0;
5160 ira_assert (current_loops
== NULL
);
5161 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
5162 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
| LOOPS_HAVE_RECORDED_EXITS
);
5164 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5165 fprintf (ira_dump_file
, "Building IRA IR\n");
5166 loops_p
= ira_build ();
5168 ira_assert (ira_conflicts_p
|| !loops_p
);
5170 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
5171 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
5172 /* It is just wasting compiler's time to pack spilled pseudos into
5173 stack slots in this case -- prohibit it. We also do this if
5174 there is setjmp call because a variable not modified between
5175 setjmp and longjmp the compiler is required to preserve its
5176 value and sharing slots does not guarantee it. */
5177 flag_ira_share_spill_slots
= FALSE
;
5181 ira_max_point_before_emit
= ira_max_point
;
5183 ira_initiate_emit_data ();
5187 max_regno
= max_reg_num ();
5188 if (ira_conflicts_p
)
5192 if (! ira_use_lra_p
)
5193 ira_initiate_assign ();
5202 ira_allocno_iterator ai
;
5204 FOR_EACH_ALLOCNO (a
, ai
)
5205 ALLOCNO_REGNO (a
) = REGNO (ALLOCNO_EMIT_DATA (a
)->reg
);
5209 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5210 fprintf (ira_dump_file
, "Flattening IR\n");
5211 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
5213 /* New insns were generated: add notes and recalculate live
5217 /* ??? Rebuild the loop tree, but why? Does the loop tree
5218 change if new insns were generated? Can that be handled
5219 by updating the loop tree incrementally? */
5220 loop_optimizer_finalize ();
5221 free_dominance_info (CDI_DOMINATORS
);
5222 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
5223 | LOOPS_HAVE_RECORDED_EXITS
);
5225 if (! ira_use_lra_p
)
5227 setup_allocno_assignment_flags ();
5228 ira_initiate_assign ();
5229 ira_reassign_conflict_allocnos (max_regno
);
5234 ira_finish_emit_data ();
5236 setup_reg_renumber ();
5238 calculate_allocation_cost ();
5240 #ifdef ENABLE_IRA_CHECKING
5241 if (ira_conflicts_p
)
5242 check_allocation ();
5245 if (max_regno
!= max_regno_before_ira
)
5247 regstat_free_n_sets_and_refs ();
5249 regstat_init_n_sets_and_refs ();
5250 regstat_compute_ri ();
5253 overall_cost_before
= ira_overall_cost
;
5254 if (! ira_conflicts_p
)
5258 fix_reg_equiv_init ();
5260 #ifdef ENABLE_IRA_CHECKING
5261 print_redundant_copies ();
5264 ira_spilled_reg_stack_slots_num
= 0;
5265 ira_spilled_reg_stack_slots
5266 = ((struct ira_spilled_reg_stack_slot
*)
5267 ira_allocate (max_regno
5268 * sizeof (struct ira_spilled_reg_stack_slot
)));
5269 memset (ira_spilled_reg_stack_slots
, 0,
5270 max_regno
* sizeof (struct ira_spilled_reg_stack_slot
));
5272 allocate_initial_values ();
5274 /* See comment for find_moveable_pseudos call. */
5275 if (ira_conflicts_p
)
5276 move_unallocated_pseudos ();
5278 /* Restore original values. */
5281 flag_caller_saves
= saved_flag_caller_saves
;
5282 flag_ira_region
= saved_flag_ira_region
;
5292 if (flag_ira_verbose
< 10)
5293 ira_dump_file
= dump_file
;
5295 timevar_push (TV_RELOAD
);
5298 if (current_loops
!= NULL
)
5300 loop_optimizer_finalize ();
5301 free_dominance_info (CDI_DOMINATORS
);
5303 FOR_ALL_BB_FN (bb
, cfun
)
5304 bb
->loop_father
= NULL
;
5305 current_loops
= NULL
;
5307 if (ira_conflicts_p
)
5308 ira_free (ira_spilled_reg_stack_slots
);
5312 lra (ira_dump_file
);
5313 /* ???!!! Move it before lra () when we use ira_reg_equiv in
5315 vec_free (reg_equivs
);
5321 df_set_flags (DF_NO_INSN_RESCAN
);
5322 build_insn_chain ();
5324 need_dce
= reload (get_insns (), ira_conflicts_p
);
5328 timevar_pop (TV_RELOAD
);
5330 timevar_push (TV_IRA
);
5332 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5334 ira_free (ira_spilled_reg_stack_slots
);
5335 ira_finish_assign ();
5338 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
5339 && overall_cost_before
!= ira_overall_cost
)
5340 fprintf (ira_dump_file
, "+++Overall after reload %d\n", ira_overall_cost
);
5342 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
5344 if (! ira_use_lra_p
)
5347 if (current_loops
!= NULL
)
5349 loop_optimizer_finalize ();
5350 free_dominance_info (CDI_DOMINATORS
);
5352 FOR_ALL_BB_FN (bb
, cfun
)
5353 bb
->loop_father
= NULL
;
5354 current_loops
= NULL
;
5357 regstat_free_n_sets_and_refs ();
5361 cleanup_cfg (CLEANUP_EXPENSIVE
);
5363 finish_reg_equiv ();
5365 bitmap_obstack_release (&ira_bitmap_obstack
);
5366 #ifndef IRA_NO_OBSTACK
5367 obstack_free (&ira_obstack
, NULL
);
5370 /* The code after the reload has changed so much that at this point
5371 we might as well just rescan everything. Note that
5372 df_rescan_all_insns is not going to help here because it does not
5373 touch the artificial uses and defs. */
5374 df_finish_pass (true);
5375 df_scan_alloc (NULL
);
5380 df_live_add_problem ();
5381 df_live_set_all_dirty ();
5387 if (need_dce
&& optimize
)
5390 /* Diagnose uses of the hard frame pointer when it is used as a global
5391 register. Often we can get away with letting the user appropriate
5392 the frame pointer, but we should let them know when code generation
5393 makes that impossible. */
5394 if (global_regs
[HARD_FRAME_POINTER_REGNUM
] && frame_pointer_needed
)
5396 tree decl
= global_regs_decl
[HARD_FRAME_POINTER_REGNUM
];
5397 error_at (DECL_SOURCE_LOCATION (current_function_decl
),
5398 "frame pointer required, but reserved");
5399 inform (DECL_SOURCE_LOCATION (decl
), "for %qD", decl
);
5402 timevar_pop (TV_IRA
);
5405 /* Run the integrated register allocator. */
5409 const pass_data pass_data_ira
=
5411 RTL_PASS
, /* type */
5413 OPTGROUP_NONE
, /* optinfo_flags */
5415 0, /* properties_required */
5416 0, /* properties_provided */
5417 0, /* properties_destroyed */
5418 0, /* todo_flags_start */
5419 TODO_do_not_ggc_collect
, /* todo_flags_finish */
5422 class pass_ira
: public rtl_opt_pass
5425 pass_ira (gcc::context
*ctxt
)
5426 : rtl_opt_pass (pass_data_ira
, ctxt
)
5429 /* opt_pass methods: */
5430 virtual unsigned int execute (function
*)
5436 }; // class pass_ira
5441 make_pass_ira (gcc::context
*ctxt
)
5443 return new pass_ira (ctxt
);
5448 const pass_data pass_data_reload
=
5450 RTL_PASS
, /* type */
5451 "reload", /* name */
5452 OPTGROUP_NONE
, /* optinfo_flags */
5453 TV_RELOAD
, /* tv_id */
5454 0, /* properties_required */
5455 0, /* properties_provided */
5456 0, /* properties_destroyed */
5457 0, /* todo_flags_start */
5458 0, /* todo_flags_finish */
5461 class pass_reload
: public rtl_opt_pass
5464 pass_reload (gcc::context
*ctxt
)
5465 : rtl_opt_pass (pass_data_reload
, ctxt
)
5468 /* opt_pass methods: */
5469 virtual unsigned int execute (function
*)
5475 }; // class pass_reload
5480 make_pass_reload (gcc::context
*ctxt
)
5482 return new pass_reload (ctxt
);