1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2023 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
45 Here is block diagram of LRA passes:
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56 | Remove |----> ------------>| register | |
57 | scratches | ^ | displacements | |
58 ----------- | ---------------- |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
80 -------------------------
82 To speed up the process:
83 o We process only insns affected by changes on previous
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
98 o data used for assigning (preferred hard regs, costs etc).
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
105 #include "coretypes.h"
112 #include "memmodel.h"
120 #include "cfgbuild.h"
123 #include "print-rtl.h"
124 #include "function-abi.h"
126 /* Dump bitmap SET with TITLE and BB INDEX. */
128 lra_dump_bitmap_with_title (const char *title
, bitmap set
, int index
)
133 static const int max_nums_on_line
= 10;
135 if (bitmap_empty_p (set
))
137 fprintf (lra_dump_file
, " %s %d:", title
, index
);
138 fprintf (lra_dump_file
, "\n");
139 count
= max_nums_on_line
+ 1;
140 EXECUTE_IF_SET_IN_BITMAP (set
, 0, i
, bi
)
142 if (count
> max_nums_on_line
)
144 fprintf (lra_dump_file
, "\n ");
147 fprintf (lra_dump_file
, " %4u", i
);
150 fprintf (lra_dump_file
, "\n");
153 /* Hard registers currently not available for allocation. It can
154 changed after some hard registers become not eliminable. */
155 HARD_REG_SET lra_no_alloc_regs
;
157 static int get_new_reg_value (void);
158 static void expand_reg_info (void);
159 static void invalidate_insn_recog_data (int);
160 static int get_insn_freq (rtx_insn
*);
161 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
,
163 /* Expand all regno related info needed for LRA. */
165 expand_reg_data (int old
)
169 ira_expand_reg_equiv ();
170 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
171 lra_change_class (i
, ALL_REGS
, " Set", true);
174 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
175 or of VOIDmode, use MD_MODE for the new reg. Initialize its
176 register class to RCLASS. Print message about assigning class
177 RCLASS containing new register name TITLE unless it is NULL. Use
178 attributes of ORIGINAL if it is a register. The created register
179 will have unique held value. */
181 lra_create_new_reg_with_unique_value (machine_mode md_mode
, rtx original
,
182 enum reg_class rclass
,
183 HARD_REG_SET
*exclude_start_hard_regs
,
189 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
191 lra_assert (mode
!= VOIDmode
);
192 new_reg
= gen_reg_rtx (mode
);
193 if (original
== NULL_RTX
|| ! REG_P (original
))
195 if (lra_dump_file
!= NULL
)
196 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
200 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
201 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
202 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
203 REG_POINTER (new_reg
) = REG_POINTER (original
);
204 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
205 if (lra_dump_file
!= NULL
)
206 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
207 REGNO (new_reg
), REGNO (original
));
209 if (lra_dump_file
!= NULL
)
212 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
213 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
214 title
, REGNO (new_reg
));
215 fprintf (lra_dump_file
, "\n");
217 expand_reg_data (max_reg_num ());
218 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
219 if (exclude_start_hard_regs
!= NULL
)
220 lra_reg_info
[REGNO (new_reg
)].exclude_start_hard_regs
221 = *exclude_start_hard_regs
;
225 /* Analogous to the previous function but also inherits value of
228 lra_create_new_reg (machine_mode md_mode
, rtx original
, enum reg_class rclass
,
229 HARD_REG_SET
*exclude_start_hard_regs
, const char *title
)
234 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
,
235 exclude_start_hard_regs
, title
);
236 if (original
!= NULL_RTX
&& REG_P (original
))
237 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
241 /* Set up for REGNO unique hold value. */
243 lra_set_regno_unique_value (int regno
)
245 lra_reg_info
[regno
].val
= get_new_reg_value ();
248 /* Invalidate INSN related info used by LRA. The info should never be
251 lra_invalidate_insn_data (rtx_insn
*insn
)
253 lra_invalidate_insn_regno_info (insn
);
254 invalidate_insn_recog_data (INSN_UID (insn
));
257 /* Mark INSN deleted and invalidate the insn related info used by
260 lra_set_insn_deleted (rtx_insn
*insn
)
262 lra_invalidate_insn_data (insn
);
263 SET_INSN_DELETED (insn
);
266 /* Delete an unneeded INSN and any previous insns who sole purpose is
267 loading data that is dead in INSN. */
269 lra_delete_dead_insn (rtx_insn
*insn
)
271 rtx_insn
*prev
= prev_real_insn (insn
);
274 /* If the previous insn sets a register that dies in our insn,
276 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
277 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
278 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
279 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
280 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
281 lra_delete_dead_insn (prev
);
283 lra_set_insn_deleted (insn
);
286 /* Emit insn x = y + z. Return NULL if we failed to do it.
287 Otherwise, return the insn. We don't use gen_add3_insn as it might
290 emit_add3_insn (rtx x
, rtx y
, rtx z
)
294 last
= get_last_insn ();
296 if (have_addptr3_insn (x
, y
, z
))
298 rtx_insn
*insn
= gen_addptr3_insn (x
, y
, z
);
300 /* If the target provides an "addptr" pattern it hopefully does
301 for a reason. So falling back to the normal add would be
303 lra_assert (insn
!= NULL_RTX
);
308 rtx_insn
*insn
= emit_insn (gen_rtx_SET (x
, gen_rtx_PLUS (GET_MODE (y
),
310 if (recog_memoized (insn
) < 0)
312 delete_insns_since (last
);
318 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
321 emit_add2_insn (rtx x
, rtx y
)
323 rtx_insn
*insn
= emit_add3_insn (x
, x
, y
);
324 if (insn
== NULL_RTX
)
326 insn
= gen_add2_insn (x
, y
);
327 if (insn
!= NULL_RTX
)
333 /* Target checks operands through operand predicates to recognize an
334 insn. We should have a special precaution to generate add insns
335 which are frequent results of elimination.
337 Emit insns for x = y + z. X can be used to store intermediate
338 values and should be not in Y and Z when we use X to store an
339 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
340 + disp] where base and index are registers, disp and scale are
341 constants. Y should contain base if it is present, Z should
342 contain disp if any. index[*scale] can be part of Y or Z. */
344 lra_emit_add (rtx x
, rtx y
, rtx z
)
348 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
351 rtx_insn
*add3_insn
= emit_add3_insn (x
, y
, z
);
352 old
= max_reg_num ();
353 if (add3_insn
!= NULL
)
357 disp
= a2
= NULL_RTX
;
358 if (GET_CODE (y
) == PLUS
)
372 index_scale
= scale
= NULL_RTX
;
373 if (GET_CODE (a1
) == MULT
)
376 index
= XEXP (a1
, 0);
377 scale
= XEXP (a1
, 1);
380 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
383 index
= XEXP (a2
, 0);
384 scale
= XEXP (a2
, 1);
392 if ((base
!= NULL_RTX
&& ! (REG_P (base
) || GET_CODE (base
) == SUBREG
))
393 || (index
!= NULL_RTX
394 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
395 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
396 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
398 /* Probably we have no 3 op add. Last chance is to use 2-op
399 add insn. To succeed, don't move Z to X as an address
400 segment always comes in Y. Otherwise, we might fail when
401 adding the address segment to register. */
402 lra_assert (x
!= y
&& x
!= z
);
403 emit_move_insn (x
, y
);
404 rtx_insn
*insn
= emit_add2_insn (x
, z
);
405 lra_assert (insn
!= NULL_RTX
);
409 if (index_scale
== NULL_RTX
)
411 if (disp
== NULL_RTX
)
413 /* Generate x = index_scale; x = x + base. */
414 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
415 emit_move_insn (x
, index_scale
);
416 rtx_insn
*insn
= emit_add2_insn (x
, base
);
417 lra_assert (insn
!= NULL_RTX
);
419 else if (scale
== NULL_RTX
)
421 /* Try x = base + disp. */
422 lra_assert (base
!= NULL_RTX
);
423 last
= get_last_insn ();
424 rtx_insn
*move_insn
=
425 emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
), base
, disp
));
426 if (recog_memoized (move_insn
) < 0)
428 delete_insns_since (last
);
429 /* Generate x = disp; x = x + base. */
430 emit_move_insn (x
, disp
);
431 rtx_insn
*add2_insn
= emit_add2_insn (x
, base
);
432 lra_assert (add2_insn
!= NULL_RTX
);
434 /* Generate x = x + index. */
435 if (index
!= NULL_RTX
)
437 rtx_insn
*insn
= emit_add2_insn (x
, index
);
438 lra_assert (insn
!= NULL_RTX
);
443 /* Try x = index_scale; x = x + disp; x = x + base. */
444 last
= get_last_insn ();
445 rtx_insn
*move_insn
= emit_move_insn (x
, index_scale
);
447 if (recog_memoized (move_insn
) >= 0)
449 rtx_insn
*insn
= emit_add2_insn (x
, disp
);
450 if (insn
!= NULL_RTX
)
452 if (base
== NULL_RTX
)
456 insn
= emit_add2_insn (x
, base
);
457 if (insn
!= NULL_RTX
)
466 delete_insns_since (last
);
467 /* Generate x = disp; x = x + base; x = x + index_scale. */
468 emit_move_insn (x
, disp
);
469 if (base
!= NULL_RTX
)
471 insn
= emit_add2_insn (x
, base
);
472 lra_assert (insn
!= NULL_RTX
);
474 insn
= emit_add2_insn (x
, index_scale
);
475 lra_assert (insn
!= NULL_RTX
);
480 /* Functions emit_... can create pseudos -- so expand the pseudo
482 if (old
!= max_reg_num ())
483 expand_reg_data (old
);
486 /* The number of emitted reload insns so far. */
487 int lra_curr_reload_num
;
489 static void remove_insn_scratches (rtx_insn
*insn
);
491 /* Emit x := y, processing special case when y = u + v or y = u + v *
492 scale + w through emit_add (Y can be an address which is base +
493 index reg * scale + displacement in general case). X may be used
494 as intermediate result therefore it should be not in Y. */
496 lra_emit_move (rtx x
, rtx y
)
501 if (GET_CODE (y
) != PLUS
)
503 if (rtx_equal_p (x
, y
))
505 old
= max_reg_num ();
507 insn
= (GET_CODE (x
) != STRICT_LOW_PART
508 ? emit_move_insn (x
, y
) : emit_insn (gen_rtx_SET (x
, y
)));
509 /* The move pattern may require scratch registers, so convert them
510 into real registers now. */
511 if (insn
!= NULL_RTX
)
512 remove_insn_scratches (insn
);
514 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
515 /* Function emit_move can create pseudos -- so expand the pseudo
517 if (old
!= max_reg_num ())
518 expand_reg_data (old
);
521 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
524 /* Update insn operands which are duplication of operands whose
525 numbers are in array of NOPS (with end marker -1). The insn is
526 represented by its LRA internal representation ID. */
528 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
531 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
533 for (i
= 0; i
< static_id
->n_dups
; i
++)
534 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
535 if (static_id
->dup_num
[i
] == nop
)
536 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
541 /* This page contains code dealing with info about registers in the
544 /* Pools for insn reg info. */
545 object_allocator
<lra_insn_reg
> lra_insn_reg_pool ("insn regs");
547 /* Create LRA insn related info about a reference to REGNO in INSN
548 with TYPE (in/out/inout), biggest reference mode MODE, flag that it
549 is reference through subreg (SUBREG_P), and reference to the next
550 insn reg info (NEXT). If REGNO can be early clobbered,
551 alternatives in which it can be early clobbered are given by
552 EARLY_CLOBBER_ALTS. */
553 static struct lra_insn_reg
*
554 new_insn_reg (rtx_insn
*insn
, int regno
, enum op_type type
,
555 machine_mode mode
, bool subreg_p
,
556 alternative_mask early_clobber_alts
,
557 struct lra_insn_reg
*next
)
559 lra_insn_reg
*ir
= lra_insn_reg_pool
.allocate ();
561 ir
->biggest_mode
= mode
;
562 if (NONDEBUG_INSN_P (insn
)
563 && partial_subreg_p (lra_reg_info
[regno
].biggest_mode
, mode
))
564 lra_reg_info
[regno
].biggest_mode
= mode
;
565 ir
->subreg_p
= subreg_p
;
566 ir
->early_clobber_alts
= early_clobber_alts
;
572 /* Free insn reg info list IR. */
574 free_insn_regs (struct lra_insn_reg
*ir
)
576 struct lra_insn_reg
*next_ir
;
578 for (; ir
!= NULL
; ir
= next_ir
)
581 lra_insn_reg_pool
.remove (ir
);
585 /* Finish pool for insn reg info. */
587 finish_insn_regs (void)
589 lra_insn_reg_pool
.release ();
594 /* This page contains code dealing LRA insn info (or in other words
595 LRA internal insn representation). */
597 /* Map INSN_CODE -> the static insn data. This info is valid during
598 all translation unit. */
599 struct lra_static_insn_data
*insn_code_data
[NUM_INSN_CODES
];
601 /* Debug insns are represented as a special insn with one input
602 operand which is RTL expression in var_location. */
604 /* The following data are used as static insn operand data for all
605 debug insns. If structure lra_operand_data is changed, the
606 initializer should be changed too. */
607 static struct lra_operand_data debug_operand_data
=
609 NULL
, /* alternative */
610 0, /* early_clobber_alts */
611 E_VOIDmode
, /* We are not interesting in the operand mode. */
616 /* The following data are used as static insn data for all debug
617 bind insns. If structure lra_static_insn_data is changed, the
618 initializer should be changed too. */
619 static struct lra_static_insn_data debug_bind_static_data
=
622 0, /* Duplication operands #. */
623 -1, /* Commutative operand #. */
624 1, /* Operands #. There is only one operand which is debug RTL
626 0, /* Duplications #. */
627 0, /* Alternatives #. We are not interesting in alternatives
628 because we does not proceed debug_insns for reloads. */
629 NULL
, /* Hard registers referenced in machine description. */
630 NULL
/* Descriptions of operands in alternatives. */
633 /* The following data are used as static insn data for all debug
634 marker insns. If structure lra_static_insn_data is changed, the
635 initializer should be changed too. */
636 static struct lra_static_insn_data debug_marker_static_data
=
639 0, /* Duplication operands #. */
640 -1, /* Commutative operand #. */
641 0, /* Operands #. There isn't any operand. */
642 0, /* Duplications #. */
643 0, /* Alternatives #. We are not interesting in alternatives
644 because we does not proceed debug_insns for reloads. */
645 NULL
, /* Hard registers referenced in machine description. */
646 NULL
/* Descriptions of operands in alternatives. */
649 /* Called once per compiler work to initialize some LRA data related
652 init_insn_code_data_once (void)
654 memset (insn_code_data
, 0, sizeof (insn_code_data
));
657 /* Called once per compiler work to finalize some LRA data related to
660 finish_insn_code_data_once (void)
662 for (unsigned int i
= 0; i
< NUM_INSN_CODES
; i
++)
664 if (insn_code_data
[i
] != NULL
)
666 free (insn_code_data
[i
]);
667 insn_code_data
[i
] = NULL
;
672 /* Return static insn data, allocate and setup if necessary. Although
673 dup_num is static data (it depends only on icode), to set it up we
674 need to extract insn first. So recog_data should be valid for
675 normal insn (ICODE >= 0) before the call. */
676 static struct lra_static_insn_data
*
677 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
679 struct lra_static_insn_data
*data
;
682 lra_assert (icode
< (int) NUM_INSN_CODES
);
683 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
685 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
686 n_bytes
= sizeof (struct lra_static_insn_data
)
687 + sizeof (struct lra_operand_data
) * nop
688 + sizeof (int) * ndup
;
689 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
690 data
->operand_alternative
= NULL
;
691 data
->n_operands
= nop
;
693 data
->n_alternatives
= nalt
;
694 data
->operand
= ((struct lra_operand_data
*)
695 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
696 data
->dup_num
= ((int *) ((char *) data
->operand
697 + sizeof (struct lra_operand_data
) * nop
));
702 insn_code_data
[icode
] = data
;
703 for (i
= 0; i
< nop
; i
++)
705 data
->operand
[i
].constraint
706 = insn_data
[icode
].operand
[i
].constraint
;
707 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
708 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
709 data
->operand
[i
].is_operator
710 = insn_data
[icode
].operand
[i
].is_operator
;
711 data
->operand
[i
].type
712 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
713 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
715 data
->operand
[i
].is_address
= false;
717 for (i
= 0; i
< ndup
; i
++)
718 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
723 /* The current length of the following array. */
724 int lra_insn_recog_data_len
;
726 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
727 lra_insn_recog_data_t
*lra_insn_recog_data
;
729 /* Alloc pool we allocate entries for lra_insn_recog_data from. */
730 static object_allocator
<class lra_insn_recog_data
>
731 lra_insn_recog_data_pool ("insn recog data pool");
733 /* Initialize LRA data about insns. */
735 init_insn_recog_data (void)
737 lra_insn_recog_data_len
= 0;
738 lra_insn_recog_data
= NULL
;
741 /* Expand, if necessary, LRA data about insns. */
743 check_and_expand_insn_recog_data (int index
)
747 if (lra_insn_recog_data_len
> index
)
749 old
= lra_insn_recog_data_len
;
750 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
751 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
753 lra_insn_recog_data_len
);
754 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
755 lra_insn_recog_data
[i
] = NULL
;
758 /* Finish LRA DATA about insn. */
760 free_insn_recog_data (lra_insn_recog_data_t data
)
762 if (data
->operand_loc
!= NULL
)
763 free (data
->operand_loc
);
764 if (data
->dup_loc
!= NULL
)
765 free (data
->dup_loc
);
766 if (data
->arg_hard_regs
!= NULL
)
767 free (data
->arg_hard_regs
);
768 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
770 if (data
->insn_static_data
->operand_alternative
!= NULL
)
771 free (const_cast <operand_alternative
*>
772 (data
->insn_static_data
->operand_alternative
));
773 free_insn_regs (data
->insn_static_data
->hard_regs
);
774 free (data
->insn_static_data
);
776 free_insn_regs (data
->regs
);
778 lra_insn_recog_data_pool
.remove (data
);
781 /* Pools for copies. */
782 static object_allocator
<lra_copy
> lra_copy_pool ("lra copies");
784 /* Finish LRA data about all insns. */
786 finish_insn_recog_data (void)
789 lra_insn_recog_data_t data
;
791 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
792 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
793 free_insn_recog_data (data
);
795 lra_copy_pool
.release ();
796 lra_insn_reg_pool
.release ();
797 lra_insn_recog_data_pool
.release ();
798 free (lra_insn_recog_data
);
801 /* Setup info about operands in alternatives of LRA DATA of insn. */
803 setup_operand_alternative (lra_insn_recog_data_t data
,
804 const operand_alternative
*op_alt
)
807 int icode
= data
->icode
;
808 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
810 static_data
->commutative
= -1;
811 nop
= static_data
->n_operands
;
812 nalt
= static_data
->n_alternatives
;
813 static_data
->operand_alternative
= op_alt
;
814 for (i
= 0; i
< nop
; i
++)
816 static_data
->operand
[i
].early_clobber_alts
= 0;
817 static_data
->operand
[i
].is_address
= false;
818 if (static_data
->operand
[i
].constraint
[0] == '%')
820 /* We currently only support one commutative pair of operands. */
821 if (static_data
->commutative
< 0)
822 static_data
->commutative
= i
;
824 lra_assert (icode
< 0); /* Asm */
825 /* The last operand should not be marked commutative. */
826 lra_assert (i
!= nop
- 1);
829 for (j
= 0; j
< nalt
; j
++)
830 for (i
= 0; i
< nop
; i
++, op_alt
++)
832 if (op_alt
->earlyclobber
)
833 static_data
->operand
[i
].early_clobber_alts
|= (alternative_mask
) 1 << j
;
834 static_data
->operand
[i
].is_address
|= op_alt
->is_address
;
838 /* Recursively process X and collect info about registers, which are
839 not the insn operands, in X with TYPE (in/out/inout) and flag that
840 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
841 to LIST. X is a part of insn given by DATA. Return the result
843 static struct lra_insn_reg
*
844 collect_non_operand_hard_regs (rtx_insn
*insn
, rtx
*x
,
845 lra_insn_recog_data_t data
,
846 struct lra_insn_reg
*list
,
847 enum op_type type
, bool early_clobber
)
849 int i
, j
, regno
, last
;
852 struct lra_insn_reg
*curr
;
854 enum rtx_code code
= GET_CODE (op
);
855 const char *fmt
= GET_RTX_FORMAT (code
);
857 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
858 if (! data
->insn_static_data
->operand
[i
].is_operator
859 && x
== data
->operand_loc
[i
])
860 /* It is an operand loc. Stop here. */
862 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
863 if (x
== data
->dup_loc
[i
])
864 /* It is a dup loc. Stop here. */
866 mode
= GET_MODE (op
);
870 mode
= wider_subreg_mode (op
);
871 if (read_modify_subreg_p (op
))
873 op
= SUBREG_REG (op
);
874 code
= GET_CODE (op
);
878 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
880 /* Process all regs even unallocatable ones as we need info
881 about all regs for rematerialization pass. */
882 for (last
= end_hard_regno (mode
, regno
); regno
< last
; regno
++)
884 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
885 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
886 && curr
->biggest_mode
== mode
)
888 if (curr
->type
!= type
)
889 curr
->type
= OP_INOUT
;
891 curr
->early_clobber_alts
= ALL_ALTERNATIVES
;
896 /* This is a new hard regno or the info cannot be
897 integrated into the found structure. */
901 /* This clobber is to inform popping floating
903 && ! (FIRST_STACK_REG
<= regno
904 && regno
<= LAST_STACK_REG
));
906 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
907 early_clobber
? ALL_ALTERNATIVES
: 0, list
);
915 list
= collect_non_operand_hard_regs (insn
, &SET_DEST (op
), data
,
916 list
, OP_OUT
, false);
917 list
= collect_non_operand_hard_regs (insn
, &SET_SRC (op
), data
,
921 /* We treat clobber of non-operand hard registers as early clobber. */
922 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 0), data
,
925 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
926 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 0), data
,
927 list
, OP_INOUT
, false);
929 case PRE_MODIFY
: case POST_MODIFY
:
930 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 0), data
,
931 list
, OP_INOUT
, false);
932 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, 1), data
,
936 fmt
= GET_RTX_FORMAT (code
);
937 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
940 list
= collect_non_operand_hard_regs (insn
, &XEXP (op
, i
), data
,
942 else if (fmt
[i
] == 'E')
943 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
944 list
= collect_non_operand_hard_regs (insn
, &XVECEXP (op
, i
, j
),
945 data
, list
, OP_IN
, false);
951 /* Set up and return info about INSN. Set up the info if it is not set up
953 lra_insn_recog_data_t
954 lra_set_insn_recog_data (rtx_insn
*insn
)
956 lra_insn_recog_data_t data
;
959 unsigned int uid
= INSN_UID (insn
);
960 struct lra_static_insn_data
*insn_static_data
;
962 check_and_expand_insn_recog_data (uid
);
963 if (DEBUG_INSN_P (insn
))
967 icode
= INSN_CODE (insn
);
969 /* It might be a new simple insn which is not recognized yet. */
970 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
972 data
= lra_insn_recog_data_pool
.allocate ();
973 lra_insn_recog_data
[uid
] = data
;
975 data
->used_insn_alternative
= LRA_UNKNOWN_ALT
;
978 if (DEBUG_INSN_P (insn
))
980 data
->dup_loc
= NULL
;
981 data
->arg_hard_regs
= NULL
;
982 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
983 if (DEBUG_BIND_INSN_P (insn
))
985 data
->insn_static_data
= &debug_bind_static_data
;
986 data
->operand_loc
= XNEWVEC (rtx
*, 1);
987 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
989 else if (DEBUG_MARKER_INSN_P (insn
))
991 data
->insn_static_data
= &debug_marker_static_data
;
992 data
->operand_loc
= NULL
;
999 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1000 const char *constraints
[MAX_RECOG_OPERANDS
];
1002 nop
= asm_noperands (PATTERN (insn
));
1003 data
->operand_loc
= data
->dup_loc
= NULL
;
1007 /* It is a special insn like USE or CLOBBER. We should
1008 recognize any regular insn otherwise LRA can do nothing
1010 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
1011 || GET_CODE (PATTERN (insn
)) == CLOBBER
1012 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
1013 data
->insn_static_data
= insn_static_data
1014 = get_static_insn_data (-1, 0, 0, nalt
);
1018 /* expand_asm_operands makes sure there aren't too many
1020 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
1022 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
1023 /* Now get the operand values and constraints out of the
1025 decode_asm_operands (PATTERN (insn
), NULL
,
1027 constraints
, operand_mode
, NULL
);
1029 for (const char *p
=constraints
[0]; *p
; p
++)
1031 data
->insn_static_data
= insn_static_data
1032 = get_static_insn_data (-1, nop
, 0, nalt
);
1033 for (i
= 0; i
< nop
; i
++)
1035 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
1036 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
1037 insn_static_data
->operand
[i
].strict_low
= false;
1038 insn_static_data
->operand
[i
].is_operator
= false;
1039 insn_static_data
->operand
[i
].is_address
= false;
1042 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1043 insn_static_data
->operand
[i
].type
1044 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1045 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1047 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
1050 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
,
1052 preprocess_constraints (nop
, nalt
, constraints
, op_alt
,
1054 setup_operand_alternative (data
, op_alt
);
1059 insn_extract (insn
);
1060 data
->insn_static_data
= insn_static_data
1061 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1062 insn_data
[icode
].n_dups
,
1063 insn_data
[icode
].n_alternatives
);
1064 n
= insn_static_data
->n_operands
;
1069 locs
= XNEWVEC (rtx
*, n
);
1070 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1072 data
->operand_loc
= locs
;
1073 n
= insn_static_data
->n_dups
;
1078 locs
= XNEWVEC (rtx
*, n
);
1079 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1081 data
->dup_loc
= locs
;
1082 data
->preferred_alternatives
= get_preferred_alternatives (insn
);
1083 const operand_alternative
*op_alt
= preprocess_insn_constraints (icode
);
1084 if (!insn_static_data
->operand_alternative
)
1085 setup_operand_alternative (data
, op_alt
);
1086 else if (op_alt
!= insn_static_data
->operand_alternative
)
1087 insn_static_data
->operand_alternative
= op_alt
;
1089 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1090 insn_static_data
->hard_regs
= NULL
;
1092 insn_static_data
->hard_regs
1093 = collect_non_operand_hard_regs (insn
, &PATTERN (insn
), data
,
1094 NULL
, OP_IN
, false);
1095 data
->arg_hard_regs
= NULL
;
1100 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1103 /* Finding implicit hard register usage. We believe it will be
1104 not changed whatever transformations are used. Call insns
1105 are such example. */
1106 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1108 link
= XEXP (link
, 1))
1109 if (((use_p
= GET_CODE (XEXP (link
, 0)) == USE
)
1110 || GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1111 && REG_P (XEXP (XEXP (link
, 0), 0)))
1113 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1114 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1115 /* It is an argument register. */
1116 for (i
= REG_NREGS (XEXP (XEXP (link
, 0), 0)) - 1; i
>= 0; i
--)
1117 arg_hard_regs
[n_hard_regs
++]
1118 = regno
+ i
+ (use_p
? 0 : FIRST_PSEUDO_REGISTER
);
1121 if (n_hard_regs
!= 0)
1123 arg_hard_regs
[n_hard_regs
++] = -1;
1124 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1125 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1126 sizeof (int) * n_hard_regs
);
1129 /* Some output operand can be recognized only from the context not
1130 from the constraints which are empty in this case. Call insn may
1131 contain a hard register in set destination with empty constraint
1132 and extract_insn treats them as an input. */
1133 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1137 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1139 /* ??? Should we treat 'X' the same way. It looks to me that
1140 'X' means anything and empty constraint means we do not
1142 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1143 || operand
->is_operator
)
1145 pat
= PATTERN (insn
);
1146 if (GET_CODE (pat
) == SET
)
1148 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1151 else if (GET_CODE (pat
) == PARALLEL
)
1153 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1155 set
= XVECEXP (PATTERN (insn
), 0, j
);
1156 if (GET_CODE (set
) == SET
1157 && &SET_DEST (set
) == data
->operand_loc
[i
])
1165 operand
->type
= OP_OUT
;
1170 /* Return info about insn give by UID. The info should be already set
1172 static lra_insn_recog_data_t
1173 get_insn_recog_data_by_uid (int uid
)
1175 lra_insn_recog_data_t data
;
1177 data
= lra_insn_recog_data
[uid
];
1178 lra_assert (data
!= NULL
);
1182 /* Invalidate all info about insn given by its UID. */
1184 invalidate_insn_recog_data (int uid
)
1186 lra_insn_recog_data_t data
;
1188 data
= lra_insn_recog_data
[uid
];
1189 lra_assert (data
!= NULL
);
1190 free_insn_recog_data (data
);
1191 lra_insn_recog_data
[uid
] = NULL
;
1194 /* Update all the insn info about INSN. It is usually called when
1195 something in the insn was changed. Return the updated info. */
1196 lra_insn_recog_data_t
1197 lra_update_insn_recog_data (rtx_insn
*insn
)
1199 lra_insn_recog_data_t data
;
1201 unsigned int uid
= INSN_UID (insn
);
1202 struct lra_static_insn_data
*insn_static_data
;
1203 poly_int64 sp_offset
= 0;
1205 check_and_expand_insn_recog_data (uid
);
1206 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1207 && data
->icode
!= INSN_CODE (insn
))
1209 sp_offset
= data
->sp_offset
;
1210 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1211 invalidate_insn_recog_data (uid
);
1216 data
= lra_get_insn_recog_data (insn
);
1217 /* Initiate or restore SP offset. */
1218 data
->sp_offset
= sp_offset
;
1221 insn_static_data
= data
->insn_static_data
;
1222 data
->used_insn_alternative
= LRA_UNKNOWN_ALT
;
1223 if (DEBUG_INSN_P (insn
))
1225 if (data
->icode
< 0)
1228 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1229 const char *constraints
[MAX_RECOG_OPERANDS
];
1231 nop
= asm_noperands (PATTERN (insn
));
1234 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1235 /* Now get the operand values and constraints out of the
1237 decode_asm_operands (PATTERN (insn
), NULL
,
1239 constraints
, operand_mode
, NULL
);
1242 for (int i
= 0; i
< nop
; i
++)
1244 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1245 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1246 && ! insn_static_data
->operand
[i
].is_operator
);
1250 for (int i
= 0; i
< insn_static_data
->n_operands
; i
++)
1252 (insn_static_data
->operand
[i
].type
1253 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1254 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1259 insn_extract (insn
);
1260 n
= insn_static_data
->n_operands
;
1262 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1263 n
= insn_static_data
->n_dups
;
1265 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1266 lra_assert (check_bool_attrs (insn
));
1271 /* Set up that INSN is using alternative ALT now. */
1273 lra_set_used_insn_alternative (rtx_insn
*insn
, int alt
)
1275 lra_insn_recog_data_t data
;
1277 data
= lra_get_insn_recog_data (insn
);
1278 data
->used_insn_alternative
= alt
;
1281 /* Set up that insn with UID is using alternative ALT now. The insn
1282 info should be already set up. */
1284 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1286 lra_insn_recog_data_t data
;
1288 check_and_expand_insn_recog_data (uid
);
1289 data
= lra_insn_recog_data
[uid
];
1290 lra_assert (data
!= NULL
);
1291 data
->used_insn_alternative
= alt
;
1296 /* This page contains code dealing with common register info and
1299 /* The size of the following array. */
1300 static int reg_info_size
;
1301 /* Common info about each register. */
1302 class lra_reg
*lra_reg_info
;
1304 HARD_REG_SET hard_regs_spilled_into
;
1306 /* Last register value. */
1307 static int last_reg_value
;
1309 /* Return new register value. */
1311 get_new_reg_value (void)
1313 return ++last_reg_value
;
1316 /* Vec referring to pseudo copies. */
1317 static vec
<lra_copy_t
> copy_vec
;
1319 /* Initialize I-th element of lra_reg_info. */
1321 initialize_lra_reg_info_element (int i
)
1323 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1325 lra_reg_info
[i
].no_stack_p
= false;
1327 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1328 CLEAR_HARD_REG_SET (lra_reg_info
[i
].exclude_start_hard_regs
);
1329 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1330 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1331 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1332 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1333 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1334 lra_reg_info
[i
].live_ranges
= NULL
;
1335 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1336 lra_reg_info
[i
].last_reload
= 0;
1337 lra_reg_info
[i
].restore_rtx
= NULL_RTX
;
1338 lra_reg_info
[i
].val
= get_new_reg_value ();
1339 lra_reg_info
[i
].offset
= 0;
1340 lra_reg_info
[i
].copies
= NULL
;
1343 /* Initialize common reg info and copies. */
1345 init_reg_info (void)
1350 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1351 lra_reg_info
= XNEWVEC (class lra_reg
, reg_info_size
);
1352 for (i
= 0; i
< reg_info_size
; i
++)
1353 initialize_lra_reg_info_element (i
);
1354 copy_vec
.truncate (0);
1355 CLEAR_HARD_REG_SET (hard_regs_spilled_into
);
1359 /* Finish common reg info and copies. */
1361 finish_reg_info (void)
1365 for (i
= 0; i
< reg_info_size
; i
++)
1366 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1367 free (lra_reg_info
);
1371 /* Expand common reg info if it is necessary. */
1373 expand_reg_info (void)
1375 int i
, old
= reg_info_size
;
1377 if (reg_info_size
> max_reg_num ())
1379 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1380 lra_reg_info
= XRESIZEVEC (class lra_reg
, lra_reg_info
, reg_info_size
);
1381 for (i
= old
; i
< reg_info_size
; i
++)
1382 initialize_lra_reg_info_element (i
);
1385 /* Free all copies. */
1387 lra_free_copies (void)
1391 while (copy_vec
.length () != 0)
1393 cp
= copy_vec
.pop ();
1394 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1395 lra_copy_pool
.remove (cp
);
1399 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1400 frequency is FREQ. */
1402 lra_create_copy (int regno1
, int regno2
, int freq
)
1407 lra_assert (regno1
!= regno2
);
1408 regno1_dest_p
= true;
1409 if (regno1
> regno2
)
1411 std::swap (regno1
, regno2
);
1412 regno1_dest_p
= false;
1414 cp
= lra_copy_pool
.allocate ();
1415 copy_vec
.safe_push (cp
);
1416 cp
->regno1_dest_p
= regno1_dest_p
;
1418 cp
->regno1
= regno1
;
1419 cp
->regno2
= regno2
;
1420 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1421 lra_reg_info
[regno1
].copies
= cp
;
1422 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1423 lra_reg_info
[regno2
].copies
= cp
;
1424 if (lra_dump_file
!= NULL
)
1425 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1426 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1429 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1432 lra_get_copy (int n
)
1434 if (n
>= (int) copy_vec
.length ())
1441 /* This page contains code dealing with info about registers in
1444 /* Process X of INSN recursively and add info (operand type is given
1445 by TYPE) about registers in X to the insn DATA. If X can be early
1446 clobbered, alternatives in which it can be early clobbered are given
1447 by EARLY_CLOBBER_ALTS. */
1449 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
,
1450 rtx_insn
*insn
, enum op_type type
,
1451 alternative_mask early_clobber_alts
)
1458 struct lra_insn_reg
*curr
;
1460 code
= GET_CODE (x
);
1461 mode
= GET_MODE (x
);
1463 if (GET_CODE (x
) == SUBREG
)
1465 mode
= wider_subreg_mode (x
);
1466 if (read_modify_subreg_p (x
))
1469 code
= GET_CODE (x
);
1474 /* Process all regs even unallocatable ones as we need info about
1475 all regs for rematerialization pass. */
1477 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, INSN_UID (insn
)))
1479 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1480 early_clobber_alts
, data
->regs
);
1485 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1486 if (curr
->regno
== regno
)
1488 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1489 /* The info cannot be integrated into the found
1491 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1492 subreg_p
, early_clobber_alts
,
1496 if (curr
->type
!= type
)
1497 curr
->type
= OP_INOUT
;
1498 curr
->early_clobber_alts
|= early_clobber_alts
;
1509 add_regs_to_insn_regno_info (data
, SET_DEST (x
), insn
, OP_OUT
, 0);
1510 add_regs_to_insn_regno_info (data
, SET_SRC (x
), insn
, OP_IN
, 0);
1513 /* We treat clobber of non-operand hard registers as early
1515 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), insn
, OP_OUT
,
1518 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1519 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), insn
, OP_INOUT
, 0);
1521 case PRE_MODIFY
: case POST_MODIFY
:
1522 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), insn
, OP_INOUT
, 0);
1523 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), insn
, OP_IN
, 0);
1526 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1527 /* Some targets place small structures in registers for return
1528 values of functions, and those registers are wrapped in
1529 PARALLEL that we may see as the destination of a SET. Here
1532 (call_insn 13 12 14 2 (set (parallel:BLK [
1533 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1535 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1536 (const_int 8 [0x8]))
1538 (call (mem:QI (symbol_ref:DI (... */
1540 fmt
= GET_RTX_FORMAT (code
);
1541 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1544 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), insn
, type
, 0);
1545 else if (fmt
[i
] == 'E')
1547 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1548 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), insn
,
1555 /* Return execution frequency of INSN. */
1557 get_insn_freq (rtx_insn
*insn
)
1559 basic_block bb
= BLOCK_FOR_INSN (insn
);
1561 gcc_checking_assert (bb
!= NULL
);
1562 return REG_FREQ_FROM_BB (bb
);
1565 /* Invalidate all reg info of INSN with DATA and execution frequency
1566 FREQ. Update common info about the invalidated registers. */
1568 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx_insn
*insn
,
1574 struct lra_insn_reg
*ir
, *next_ir
;
1576 uid
= INSN_UID (insn
);
1577 debug_p
= DEBUG_INSN_P (insn
);
1578 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1582 lra_insn_reg_pool
.remove (ir
);
1583 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1584 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1586 lra_reg_info
[i
].nrefs
--;
1587 lra_reg_info
[i
].freq
-= freq
;
1588 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1594 /* Invalidate all reg info of INSN. Update common info about the
1595 invalidated registers. */
1597 lra_invalidate_insn_regno_info (rtx_insn
*insn
)
1599 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1600 get_insn_freq (insn
));
1603 /* Update common reg info from reg info of insn given by its DATA and
1604 execution frequency FREQ. */
1606 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1609 struct lra_insn_reg
*ir
;
1611 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1612 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1614 lra_reg_info
[i
].nrefs
++;
1615 lra_reg_info
[i
].freq
+= freq
;
1619 /* Set up insn reg info of INSN. Update common reg info from reg info
1622 lra_update_insn_regno_info (rtx_insn
*insn
)
1625 lra_insn_recog_data_t data
;
1626 struct lra_static_insn_data
*static_data
;
1630 if (! INSN_P (insn
))
1632 data
= lra_get_insn_recog_data (insn
);
1633 static_data
= data
->insn_static_data
;
1634 freq
= NONDEBUG_INSN_P (insn
) ? get_insn_freq (insn
) : 0;
1635 invalidate_insn_data_regno_info (data
, insn
, freq
);
1636 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1637 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], insn
,
1638 static_data
->operand
[i
].type
,
1639 static_data
->operand
[i
].early_clobber_alts
);
1640 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1641 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), insn
,
1642 code
== USE
? OP_IN
: OP_OUT
, 0);
1644 /* On some targets call insns can refer to pseudos in memory in
1645 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1646 consider their occurrences in calls for different
1647 transformations (e.g. inheritance) with given pseudos. */
1648 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1650 link
= XEXP (link
, 1))
1652 code
= GET_CODE (XEXP (link
, 0));
1653 if ((code
== USE
|| code
== CLOBBER
)
1654 && MEM_P (XEXP (XEXP (link
, 0), 0)))
1655 add_regs_to_insn_regno_info (data
, XEXP (XEXP (link
, 0), 0), insn
,
1656 code
== USE
? OP_IN
: OP_OUT
, 0);
1658 if (NONDEBUG_INSN_P (insn
))
1659 setup_insn_reg_info (data
, freq
);
1662 /* Return reg info of insn given by it UID. */
1663 struct lra_insn_reg
*
1664 lra_get_insn_regs (int uid
)
1666 lra_insn_recog_data_t data
;
1668 data
= get_insn_recog_data_by_uid (uid
);
1674 /* Recursive hash function for RTL X. */
1676 lra_rtx_hash (rtx x
)
1686 code
= GET_CODE (x
);
1687 val
+= (int) code
+ 4095;
1689 /* Some RTL can be compared nonrecursively. */
1693 return val
+ REGNO (x
);
1696 return iterative_hash_object (XEXP (x
, 0), val
);
1699 return iterative_hash_object (XSTR (x
, 0), val
);
1707 return val
+ UINTVAL (x
);
1713 /* Hash the elements. */
1714 fmt
= GET_RTX_FORMAT (code
);
1715 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1720 val
+= XWINT (x
, i
);
1730 val
+= XVECLEN (x
, i
);
1732 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1733 val
+= lra_rtx_hash (XVECEXP (x
, i
, j
));
1737 val
+= lra_rtx_hash (XEXP (x
, i
));
1742 val
+= htab_hash_string (XSTR (x
, i
));
1750 /* It is believed that rtx's at this level will never
1751 contain anything but integers and other rtx's, except for
1752 within LABEL_REFs and SYMBOL_REFs. */
1762 /* This page contains code dealing with stack of the insns which
1763 should be processed by the next constraint pass. */
1765 /* Bitmap used to put an insn on the stack only in one exemplar. */
1766 static sbitmap lra_constraint_insn_stack_bitmap
;
1768 /* The stack itself. */
1769 vec
<rtx_insn
*> lra_constraint_insn_stack
;
1771 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1772 info for INSN, otherwise only update it if INSN is not already on the
1775 lra_push_insn_1 (rtx_insn
*insn
, bool always_update
)
1777 unsigned int uid
= INSN_UID (insn
);
1779 lra_update_insn_regno_info (insn
);
1780 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1781 lra_constraint_insn_stack_bitmap
=
1782 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1783 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1785 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1786 if (! always_update
)
1787 lra_update_insn_regno_info (insn
);
1788 lra_constraint_insn_stack
.safe_push (insn
);
1791 /* Put INSN on the stack. */
1793 lra_push_insn (rtx_insn
*insn
)
1795 lra_push_insn_1 (insn
, false);
1798 /* Put INSN on the stack and update its reg info. */
1800 lra_push_insn_and_update_insn_regno_info (rtx_insn
*insn
)
1802 lra_push_insn_1 (insn
, true);
1805 /* Put insn with UID on the stack. */
1807 lra_push_insn_by_uid (unsigned int uid
)
1809 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1812 /* Take the last-inserted insns off the stack and return it. */
1816 rtx_insn
*insn
= lra_constraint_insn_stack
.pop ();
1817 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1821 /* Return the current size of the insn stack. */
1823 lra_insn_stack_length (void)
1825 return lra_constraint_insn_stack
.length ();
1828 /* Push insns FROM to TO (excluding it) going in reverse order. */
1830 push_insns (rtx_insn
*from
, rtx_insn
*to
)
1834 if (from
== NULL_RTX
)
1836 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1838 lra_push_insn (insn
);
1841 /* Set up and return sp offset for insns in range [FROM, LAST]. The offset is
1842 taken from the next BB insn after LAST or zero if there in such
1845 setup_sp_offset (rtx_insn
*from
, rtx_insn
*last
)
1847 rtx_insn
*before
= next_nonnote_nondebug_insn_bb (last
);
1848 poly_int64 offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1849 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1851 for (rtx_insn
*insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1853 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1854 offset
= lra_update_sp_offset (PATTERN (insn
), offset
);
1859 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1860 insns onto the stack. Print about emitting the insns with
1863 lra_process_new_insns (rtx_insn
*insn
, rtx_insn
*before
, rtx_insn
*after
,
1866 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1868 if (lra_dump_file
!= NULL
)
1870 dump_insn_slim (lra_dump_file
, insn
);
1871 if (before
!= NULL_RTX
)
1873 fprintf (lra_dump_file
," %s before:\n", title
);
1874 dump_rtl_slim (lra_dump_file
, before
, NULL
, -1, 0);
1877 if (before
!= NULL_RTX
)
1879 if (cfun
->can_throw_non_call_exceptions
)
1880 copy_reg_eh_region_note_forward (insn
, before
, NULL
);
1881 emit_insn_before (before
, insn
);
1882 poly_int64 old_sp_offset
= lra_get_insn_recog_data (insn
)->sp_offset
;
1883 poly_int64 new_sp_offset
= setup_sp_offset (before
, PREV_INSN (insn
));
1884 if (maybe_ne (old_sp_offset
, new_sp_offset
))
1886 if (lra_dump_file
!= NULL
)
1888 fprintf (lra_dump_file
, " Changing sp offset from ");
1889 print_dec (old_sp_offset
, lra_dump_file
);
1890 fprintf (lra_dump_file
, " to ");
1891 print_dec (new_sp_offset
, lra_dump_file
);
1892 fprintf (lra_dump_file
, " for insn");
1893 dump_rtl_slim (lra_dump_file
, insn
, NULL
, -1, 0);
1895 lra_get_insn_recog_data (insn
)->sp_offset
= new_sp_offset
;
1896 eliminate_regs_in_insn (insn
, false, false,
1897 old_sp_offset
- new_sp_offset
);
1898 lra_push_insn (insn
);
1900 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1902 if (after
!= NULL_RTX
)
1904 if (cfun
->can_throw_non_call_exceptions
)
1905 copy_reg_eh_region_note_forward (insn
, after
, NULL
);
1906 if (! JUMP_P (insn
))
1910 if (lra_dump_file
!= NULL
)
1912 fprintf (lra_dump_file
, " %s after:\n", title
);
1913 dump_rtl_slim (lra_dump_file
, after
, NULL
, -1, 0);
1916 NEXT_INSN (last
) != NULL_RTX
;
1917 last
= NEXT_INSN (last
))
1919 emit_insn_after (after
, insn
);
1920 push_insns (last
, insn
);
1921 setup_sp_offset (after
, last
);
1925 /* Put output reload insns on successor BBs: */
1929 FOR_EACH_EDGE (e
, ei
, BLOCK_FOR_INSN (insn
)->succs
)
1930 if (e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
))
1932 /* We already made the edge no-critical in ira.cc::ira */
1933 lra_assert (!EDGE_CRITICAL_P (e
));
1934 rtx_insn
*curr
, *tmp
= BB_HEAD (e
->dest
);
1936 tmp
= NEXT_INSN (tmp
);
1937 if (NOTE_INSN_BASIC_BLOCK_P (tmp
))
1938 tmp
= NEXT_INSN (tmp
);
1939 /* Do not put reload insns if it is the last BB
1940 without actual insns. */
1944 for (curr
= after
; curr
!= NULL_RTX
; curr
= NEXT_INSN (curr
))
1945 emit_insn (copy_insn (PATTERN (curr
)));
1946 rtx_insn
*copy
= get_insns (), *last
= get_last_insn ();
1948 if (lra_dump_file
!= NULL
)
1950 fprintf (lra_dump_file
, " %s after in bb%d:\n", title
,
1952 dump_rtl_slim (lra_dump_file
, copy
, NULL
, -1, 0);
1954 /* Use the right emit func for setting up BB_END/BB_HEAD: */
1955 if (BB_END (e
->dest
) == PREV_INSN (tmp
))
1956 emit_insn_after_noloc (copy
, PREV_INSN (tmp
), e
->dest
);
1958 emit_insn_before_noloc (copy
, tmp
, e
->dest
);
1959 push_insns (last
, PREV_INSN (copy
));
1960 setup_sp_offset (copy
, last
);
1961 /* We can ignore BB live info here as it and reg notes
1962 will be updated before the next assignment
1967 if (lra_dump_file
!= NULL
)
1968 fprintf (lra_dump_file
, "\n");
1969 if (cfun
->can_throw_non_call_exceptions
)
1971 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
1972 if (note
&& !insn_could_throw_p (insn
))
1973 remove_note (insn
, note
);
1978 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1979 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
1980 DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any
1983 lra_substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
, bool subreg_p
,
1987 bool result
= false;
1995 code
= GET_CODE (x
);
1996 if (code
== SUBREG
&& subreg_p
)
1998 rtx subst
, inner
= SUBREG_REG (x
);
1999 /* Transform subreg of constant while we still have inner mode
2000 of the subreg. The subreg internal should not be an insn
2002 if (REG_P (inner
) && (int) REGNO (inner
) == old_regno
2003 && CONSTANT_P (new_reg
)
2004 && (subst
= simplify_subreg (GET_MODE (x
), new_reg
, GET_MODE (inner
),
2005 SUBREG_BYTE (x
))) != NULL_RTX
)
2012 else if (code
== REG
&& (int) REGNO (x
) == old_regno
)
2014 machine_mode mode
= GET_MODE (x
);
2015 machine_mode inner_mode
= GET_MODE (new_reg
);
2017 if (mode
!= inner_mode
2018 && ! (CONST_SCALAR_INT_P (new_reg
) && SCALAR_INT_MODE_P (mode
)))
2020 poly_uint64 offset
= 0;
2021 if (partial_subreg_p (mode
, inner_mode
)
2022 && SCALAR_INT_MODE_P (inner_mode
))
2023 offset
= subreg_lowpart_offset (mode
, inner_mode
);
2025 new_reg
= gen_rtx_raw_SUBREG (mode
, new_reg
, offset
);
2027 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, offset
);
2033 /* Scan all the operand sub-expressions. */
2034 fmt
= GET_RTX_FORMAT (code
);
2035 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2042 || code
== ZERO_EXTEND
2043 || code
== SIGN_EXTEND
2045 || code
== UNSIGNED_FLOAT
))
2047 rtx y
= XEXP (x
, 0);
2048 if (lra_substitute_pseudo (&y
, old_regno
,
2049 new_reg
, subreg_p
, debug_p
))
2052 if (CONST_SCALAR_INT_P (y
))
2055 y
= simplify_subreg (GET_MODE (x
), y
,
2056 GET_MODE (SUBREG_REG (x
)),
2059 y
= simplify_unary_operation (code
, GET_MODE (x
), y
,
2060 GET_MODE (XEXP (x
, 0)));
2064 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
2070 else if (lra_substitute_pseudo (&XEXP (x
, i
), old_regno
,
2071 new_reg
, subreg_p
, debug_p
))
2074 else if (fmt
[i
] == 'E')
2076 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2077 if (lra_substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
,
2078 new_reg
, subreg_p
, debug_p
))
2085 /* Call lra_substitute_pseudo within an insn. Try to simplify subreg
2086 of constant if SUBREG_P. This won't update the insn ptr, just the
2087 contents of the insn. */
2089 lra_substitute_pseudo_within_insn (rtx_insn
*insn
, int old_regno
,
2090 rtx new_reg
, bool subreg_p
)
2093 return lra_substitute_pseudo (&loc
, old_regno
, new_reg
, subreg_p
,
2094 DEBUG_INSN_P (insn
));
2099 /* Return new register of the same mode as ORIGINAL of class ALL_REGS.
2100 Used in ira_remove_scratches. */
2102 get_scratch_reg (rtx original
)
2104 return lra_create_new_reg (GET_MODE (original
), original
, ALL_REGS
,
2108 /* Remove all insn scratches in INSN. */
2110 remove_insn_scratches (rtx_insn
*insn
)
2112 if (ira_remove_insn_scratches (insn
, true, lra_dump_file
, get_scratch_reg
))
2113 df_insn_rescan (insn
);
2116 /* Remove all insn scratches in the current function. */
2118 remove_scratches (void)
2123 FOR_EACH_BB_FN (bb
, cfun
)
2124 FOR_BB_INSNS (bb
, insn
)
2126 remove_insn_scratches (insn
);
2129 /* Function checks RTL for correctness. If FINAL_P is true, it is
2130 done at the end of LRA and the check is more rigorous. */
2132 check_rtl (bool final_p
)
2137 lra_assert (! final_p
|| reload_completed
);
2138 FOR_EACH_BB_FN (bb
, cfun
)
2139 FOR_BB_INSNS (bb
, insn
)
2140 if (NONDEBUG_INSN_P (insn
)
2141 && GET_CODE (PATTERN (insn
)) != USE
2142 && GET_CODE (PATTERN (insn
)) != CLOBBER
2143 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
2147 extract_constrain_insn (insn
);
2150 /* LRA code is based on assumption that all addresses can be
2151 correctly decomposed. LRA can generate reloads for
2152 decomposable addresses. The decomposition code checks the
2153 correctness of the addresses. So we don't need to check
2154 the addresses here. Don't call insn_invalid_p here, it can
2155 change the code at this stage. */
2156 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
2157 fatal_insn_not_found (insn
);
2161 /* Determine if the current function has an exception receiver block
2162 that reaches the exit block via non-exceptional edges */
2164 has_nonexceptional_receiver (void)
2168 basic_block
*tos
, *worklist
, bb
;
2170 /* If we're not optimizing, then just err on the safe side. */
2174 /* First determine which blocks can reach exit via normal paths. */
2175 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
2177 FOR_EACH_BB_FN (bb
, cfun
)
2178 bb
->flags
&= ~BB_REACHABLE
;
2180 /* Place the exit block on our worklist. */
2181 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
2182 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
2184 /* Iterate: find everything reachable from what we've already seen. */
2185 while (tos
!= worklist
)
2189 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
2190 if (e
->flags
& EDGE_ABNORMAL
)
2197 basic_block src
= e
->src
;
2199 if (!(src
->flags
& BB_REACHABLE
))
2201 src
->flags
|= BB_REACHABLE
;
2207 /* No exceptional block reached exit unexceptionally. */
2211 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2212 We change pseudos by hard registers without notification of DF and
2213 that can make the notes obsolete. DF-infrastructure does not deal
2214 with REG_INC notes -- so we should regenerate them here. */
2216 update_inc_notes (void)
2222 FOR_EACH_BB_FN (bb
, cfun
)
2223 FOR_BB_INSNS (bb
, insn
)
2224 if (NONDEBUG_INSN_P (insn
))
2226 pnote
= ®_NOTES (insn
);
2229 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2230 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2231 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2232 *pnote
= XEXP (*pnote
, 1);
2234 pnote
= &XEXP (*pnote
, 1);
2238 add_auto_inc_notes (insn
, PATTERN (insn
));
2242 /* Set to 1 while in lra. */
2243 int lra_in_progress
;
2245 /* Start of pseudo regnos before the LRA. */
2246 int lra_new_regno_start
;
2248 /* Start of reload pseudo regnos before the new spill pass. */
2249 int lra_constraint_new_regno_start
;
2251 /* Avoid spilling pseudos with regno more than the following value if
2253 int lra_bad_spill_regno_start
;
2255 /* A pseudo of Pmode. */
2256 rtx lra_pmode_pseudo
;
2258 /* Inheritance pseudo regnos before the new spill pass. */
2259 bitmap_head lra_inheritance_pseudos
;
2261 /* Split regnos before the new spill pass. */
2262 bitmap_head lra_split_regs
;
2264 /* Reload pseudo regnos before the new assignment pass which still can
2265 be spilled after the assignment pass as memory is also accepted in
2266 insns for the reload pseudos. */
2267 bitmap_head lra_optional_reload_pseudos
;
2269 /* Pseudo regnos used for subreg reloads before the new assignment
2270 pass. Such pseudos still can be spilled after the assignment
2272 bitmap_head lra_subreg_reload_pseudos
;
2274 /* File used for output of LRA debug information. */
2275 FILE *lra_dump_file
;
2277 /* True if we split hard reg after the last constraint sub-pass. */
2278 bool lra_hard_reg_split_p
;
2280 /* True if we found an asm error. */
2281 bool lra_asm_error_p
;
2283 /* True if we should try spill into registers of different classes
2284 instead of memory. */
2285 bool lra_reg_spill_p
;
2287 /* Set up value LRA_REG_SPILL_P. */
2289 setup_reg_spill_flag (void)
2293 if (targetm
.spill_class
!= NULL
)
2294 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2295 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2296 if (targetm
.spill_class ((enum reg_class
) cl
,
2297 (machine_mode
) mode
) != NO_REGS
)
2299 lra_reg_spill_p
= true;
2302 lra_reg_spill_p
= false;
2305 /* True if the current function is too big to use regular algorithms
2306 in LRA. In other words, we should use simpler and faster algorithms
2307 in LRA. It also means we should not worry about generation code
2308 for caller saves. The value is set up in IRA. */
2311 /* Major LRA entry function. F is a file should be used to dump LRA
2317 bool live_p
, inserted_p
;
2320 lra_asm_error_p
= false;
2321 lra_pmode_pseudo
= gen_reg_rtx (Pmode
);
2323 timevar_push (TV_LRA
);
2325 /* Make sure that the last insn is a note. Some subsequent passes
2327 emit_note (NOTE_INSN_DELETED
);
2329 lra_no_alloc_regs
= ira_no_alloc_regs
;
2334 init_insn_recog_data ();
2336 /* Some quick check on RTL generated by previous passes. */
2340 lra_in_progress
= 1;
2342 lra_live_range_iter
= lra_coalesce_iter
= lra_constraint_iter
= 0;
2343 lra_assignment_iter
= lra_assignment_iter_after_spill
= 0;
2344 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2345 lra_rematerialization_iter
= 0;
2347 setup_reg_spill_flag ();
2349 /* Function remove_scratches can creates new pseudos for clobbers --
2350 so set up lra_constraint_new_regno_start before its call to
2351 permit changing reg classes for pseudos created by this
2353 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2354 lra_bad_spill_regno_start
= INT_MAX
;
2355 remove_scratches ();
2357 /* A function that has a non-local label that can reach the exit
2358 block via non-exceptional paths must save all call-saved
2360 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2361 crtl
->saves_all_registers
= 1;
2363 if (crtl
->saves_all_registers
)
2364 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2365 if (!crtl
->abi
->clobbers_full_reg_p (i
)
2367 && !LOCAL_REGNO (i
))
2368 df_set_regs_ever_live (i
, true);
2370 /* We don't DF from now and avoid its using because it is to
2371 expensive when a lot of RTL changes are made. */
2372 df_set_flags (DF_NO_INSN_RESCAN
);
2373 lra_constraint_insn_stack
.create (get_max_uid ());
2374 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2375 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2376 lra_live_ranges_init ();
2377 lra_constraints_init ();
2378 lra_curr_reload_num
= 0;
2379 push_insns (get_last_insn (), NULL
);
2380 /* It is needed for the 1st coalescing. */
2381 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2382 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2383 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2384 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2386 if (maybe_ne (get_frame_size (), 0) && crtl
->stack_alignment_needed
)
2387 /* If we have a stack frame, we must align it now. The stack size
2388 may be a part of the offset computation for register
2390 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2396 bool reloads_p
= lra_constraints (lra_constraint_iter
== 0);
2397 /* Constraint transformations may result in that eliminable
2398 hard regs become uneliminable and pseudos which use them
2399 should be spilled. It is better to do it before pseudo
2402 For example, rs6000 can make
2403 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2404 to use a constant pool. */
2405 lra_eliminate (false, false);
2406 /* We should try to assign hard registers to scratches even
2407 if there were no RTL transformations in lra_constraints.
2408 Also we should check IRA assignments on the first
2409 iteration as they can be wrong because of early clobbers
2410 operands which are ignored in IRA. */
2411 if (! reloads_p
&& lra_constraint_iter
> 1)
2413 /* Stack is not empty here only when there are changes
2414 during the elimination sub-pass. */
2415 if (bitmap_empty_p (lra_constraint_insn_stack_bitmap
))
2418 /* If there are no reloads but changing due
2419 elimination, restart the constraint sub-pass
2423 /* Do inheritance only for regular algorithms. */
2427 lra_clear_live_ranges ();
2429 lra_hard_reg_split_p
= false;
2432 /* We need live ranges for lra_assign -- so build them.
2433 But don't remove dead insns or change global live
2434 info as we can undo inheritance transformations after
2435 inheritance pseudo assigning. */
2436 lra_create_live_ranges (true, !lra_simple_p
);
2438 /* If we don't spill non-reload and non-inheritance
2439 pseudos, there is no sense to run memory-memory move
2440 coalescing. If inheritance pseudos were spilled, the
2441 memory-memory moves involving them will be removed by
2442 pass undoing inheritance. */
2444 lra_assign (fails_p
);
2447 bool spill_p
= !lra_assign (fails_p
);
2449 if (lra_undo_inheritance ())
2451 if (spill_p
&& ! fails_p
)
2455 lra_create_live_ranges (true, true);
2458 if (lra_coalesce ())
2462 lra_clear_live_ranges ();
2466 /* It is a very rare case. It is the last hope to
2467 split a hard regno live range for a reload
2470 lra_clear_live_ranges ();
2472 if (! lra_split_hard_reg_for ())
2474 lra_hard_reg_split_p
= true;
2477 while (fails_p
&& !lra_asm_error_p
);
2479 /* We need the correct reg notes for work of constraint sub-pass. */
2480 lra_create_live_ranges (true, true);
2484 /* Don't clear optional reloads bitmap until all constraints are
2485 satisfied as we need to differ them from regular reloads. */
2486 bitmap_clear (&lra_optional_reload_pseudos
);
2487 bitmap_clear (&lra_subreg_reload_pseudos
);
2488 bitmap_clear (&lra_inheritance_pseudos
);
2489 bitmap_clear (&lra_split_regs
);
2492 /* We need full live info for spilling pseudos into
2493 registers instead of memory. */
2494 lra_create_live_ranges (lra_reg_spill_p
, true);
2497 /* We should check necessity for spilling here as the above live
2498 range pass can remove spilled pseudos. */
2499 if (! lra_need_for_spills_p ())
2501 /* Now we know what pseudos should be spilled. Try to
2502 rematerialize them first. */
2505 /* We need full live info -- see the comment above. */
2506 lra_create_live_ranges (lra_reg_spill_p
, true);
2508 if (! lra_need_for_spills_p ())
2510 if (lra_need_for_scratch_reg_p ())
2516 /* Assignment of stack slots changes elimination offsets for
2517 some eliminations. So update the offsets here. */
2518 lra_eliminate (false, false);
2519 lra_constraint_new_regno_start
= max_reg_num ();
2520 if (lra_bad_spill_regno_start
== INT_MAX
2521 && lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
2522 && lra_rematerialization_iter
> LRA_MAX_REMATERIALIZATION_PASSES
)
2523 /* After switching off inheritance and rematerialization
2524 passes, avoid spilling reload pseudos will be created to
2525 prevent LRA cycling in some complicated cases. */
2526 lra_bad_spill_regno_start
= lra_constraint_new_regno_start
;
2527 lra_assignment_iter_after_spill
= 0;
2529 ira_restore_scratches (lra_dump_file
);
2530 lra_eliminate (true, false);
2531 lra_final_code_change ();
2532 lra_in_progress
= 0;
2534 lra_clear_live_ranges ();
2535 lra_live_ranges_finish ();
2536 lra_constraints_finish ();
2538 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2539 lra_constraint_insn_stack
.release ();
2540 finish_insn_recog_data ();
2541 regstat_free_n_sets_and_refs ();
2543 reload_completed
= 1;
2544 update_inc_notes ();
2546 inserted_p
= fixup_abnormal_edges ();
2548 /* We've possibly turned single trapping insn into multiple ones. */
2549 if (cfun
->can_throw_non_call_exceptions
)
2551 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
2552 bitmap_ones (blocks
);
2553 find_many_sub_basic_blocks (blocks
);
2557 commit_edge_insertions ();
2559 /* Replacing pseudos with their memory equivalents might have
2560 created shared rtx. Subsequent passes would get confused
2561 by this, so unshare everything here. */
2562 unshare_all_rtl_again (get_insns ());
2567 timevar_pop (TV_LRA
);
2570 /* Called once per compiler to initialize LRA data once. */
2572 lra_init_once (void)
2574 init_insn_code_data_once ();
2577 /* Called once per compiler to finish LRA data which are initialize
2580 lra_finish_once (void)
2582 finish_insn_code_data_once ();