| blob | 7b71616a2fa1c6a9488d5dec537344a37dbf4902 |
1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2014 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
42 #if SWITCHABLE_TARGET
44 #endif
50 rtx);
53 rtx);
58 rtx);
72 /* Return a constant integer mask value of mode MODE with BITSIZE ones
73 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
74 The mask is truncated if necessary to the width of mode MODE. The
75 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
79 {
80 return immed_wide_int_const
83 }
85 /* Test whether a value is zero of a power of two. */
86 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
87 (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0)
89 struct init_expmed_rtl
90 {
91 rtx reg;
92 rtx plus;
93 rtx neg;
94 rtx mult;
95 rtx sdiv;
96 rtx udiv;
97 rtx sdiv_32;
98 rtx smod_32;
99 rtx wide_mult;
100 rtx wide_lshr;
101 rtx wide_trunc;
102 rtx shift;
103 rtx shift_mult;
104 rtx shift_add;
105 rtx shift_sub0;
106 rtx shift_sub1;
107 rtx zext;
108 rtx trunc;
112 };
114 static void
117 {
119 rtx which;
121 /* We're given no information about the true size of a partial integer,
122 only the size of the "full" integer it requires for storage. For
123 comparison purposes here, reduce the bit size by one in that case. */
129 /* Assume cost of zero-extend and sign-extend is the same. */
134 }
136 static void
139 {
174 {
179 }
183 {
191 }
194 {
198 }
200 {
203 {
213 }
214 }
215 }
217 void
219 {
226 {
229 }
231 /* Avoid using hard regs in ways which may be unsupported. */
252 {
269 }
272 {
275 }
276 else
298 }
300 /* Return an rtx representing minus the value of X.
301 MODE is the intended mode of the result,
302 useful if X is a CONST_INT. */
304 rtx
306 {
313 }
315 /* Adjust bitfield memory MEM so that it points to the first unit of mode
316 MODE that contains a bitfield of size BITSIZE at bit position BITNUM.
317 If MODE is BLKmode, return a reference to every byte in the bitfield.
318 Set *NEW_BITNUM to the bit position of the field within the new memory. */
320 static rtx
325 {
327 {
333 }
334 else
335 {
340 }
341 }
343 /* The caller wants to perform insertion or extraction PATTERN on a
344 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
345 BITREGION_START and BITREGION_END are as for store_bit_field
346 and FIELDMODE is the natural mode of the field.
348 Search for a mode that is compatible with the memory access
349 restrictions and (where applicable) with a register insertion or
350 extraction. Return the new memory on success, storing the adjusted
351 bit position in *NEW_BITNUM. Return null otherwise. */
353 static rtx
356 HOST_WIDE_INT bitnum,
361 {
367 {
368 /* We can use a memory in BEST_MODE. See whether this is true for
369 any wider modes. All other things being equal, we prefer to
370 use the widest mode possible because it tends to expose more
371 CSE opportunities. */
373 {
374 /* Limit the search to the mode required by the corresponding
375 register insertion or extraction instruction, if any. */
377 extraction_insn insn;
380 fieldmode))
387 }
389 new_bitnum);
390 }
392 }
394 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
395 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
396 offset is then BITNUM / BITS_PER_UNIT. */
398 static bool
402 {
407 else
409 }
411 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
412 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
413 Return false if the access would touch memory outside the range
414 BITREGION_START to BITREGION_END for conformance to the C++ memory
415 model. */
417 static bool
423 {
426 /* -fstrict-volatile-bitfields must be enabled and we must have a
427 volatile MEM. */
433 /* Non-integral modes likely only happen with packed structures.
434 Punt. */
438 /* The bit size must not be larger than the field mode, and
439 the field mode must not be larger than a word. */
443 /* Check for cases of unaligned fields that must be split. */
445 || (STRICT_ALIGNMENT
449 /* Check for cases where the C++ memory model applies. */
456 }
458 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
459 bit number BITNUM can be treated as a simple value of mode MODE. */
461 static bool
464 {
471 }
472 \f
473 /* Try to use instruction INSV to store VALUE into a field of OP0.
474 BITSIZE and BITNUM are as for store_bit_field. */
476 static bool
480 rtx value)
481 {
483 rtx value1;
494 /* Get a reference to the first byte of the field. */
497 else
498 {
499 /* Convert from counting within OP0 to counting in OP_MODE. */
503 /* If xop0 is a register, we need it in OP_MODE
504 to make it acceptable to the format of insv. */
506 /* We can't just change the mode, because this might clobber op0,
507 and we will need the original value of op0 if insv fails. */
511 }
513 /* If the destination is a paradoxical subreg such that we need a
514 truncate to the inner mode, perform the insertion on a temporary and
515 truncate the result to the original destination. Note that we can't
516 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
517 X) 0)) is (reg:N X). */
521 op_mode))
522 {
527 }
529 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
530 "backwards" from the size of the unit we are inserting into.
531 Otherwise, we count bits from the most significant on a
532 BYTES/BITS_BIG_ENDIAN machine. */
537 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
540 {
542 {
543 /* Optimization: Don't bother really extending VALUE
544 if it has all the bits we will actually use. However,
545 if we must narrow it, be sure we do it correctly. */
548 {
549 rtx tmp;
555 value1),
558 }
559 else
561 }
564 else
565 /* Parse phase is supposed to make VALUE's data type
566 match that of the component reference, which is a type
567 at least as wide as the field; so VALUE should have
568 a mode that corresponds to that type. */
570 }
577 {
581 }
584 }
586 /* A subroutine of store_bit_field, with the same arguments. Return true
587 if the operation could be implemented.
589 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
590 no other way of implementing the operation. If FALLBACK_P is false,
591 return false instead. */
593 static bool
600 {
602 rtx orig_value;
605 {
606 /* The following line once was done only if WORDS_BIG_ENDIAN,
607 but I think that is a mistake. WORDS_BIG_ENDIAN is
608 meaningful at a much higher level; when structures are copied
609 between memory and regs, the higher-numbered regs
610 always get higher addresses. */
615 /* Paradoxical subregs need special handling on big endian machines. */
617 {
624 }
625 else
630 }
632 /* No action is needed if the target is a register and if the field
633 lies completely outside that register. This can occur if the source
634 code contains an out-of-bounds access to a small array. */
638 /* Use vec_set patterns for inserting parts of vectors whenever
639 available. */
646 {
658 }
660 /* If the target is a register, overwriting the entire object, or storing
661 a full-word or multi-word field can be done with just a SUBREG. */
666 {
667 /* Use the subreg machinery either to narrow OP0 to the required
668 words or to cope with mode punning between equal-sized modes.
669 In the latter case, use subreg on the rhs side, not lhs. */
670 rtx sub;
673 {
676 {
679 }
680 }
681 else
682 {
686 {
689 }
690 }
691 }
693 /* If the target is memory, storing any naturally aligned field can be
694 done with a simple store. For targets that support fast unaligned
695 memory, any naturally sized, unit aligned field can be done directly. */
697 {
701 }
703 /* Make sure we are playing with integral modes. Pun with subregs
704 if we aren't. This must come after the entire register case above,
705 since that case is valid for any mode. The following cases are only
706 valid for integral modes. */
707 {
710 {
713 else
714 {
717 }
718 }
719 }
721 /* Storing an lsb-aligned field in a register
722 can be done with a movstrict instruction. */
728 {
735 {
736 /* Else we've got some float mode source being extracted into
737 a different float mode destination -- this combination of
738 subregs results in Severe Tire Damage. */
743 }
747 {
751 /* Shrink the source operand to FIELDMODE. */
755 }
756 }
758 /* Handle fields bigger than a word. */
761 {
762 /* Here we transfer the words of the field
763 in the order least significant first.
764 This is because the most significant word is the one which may
765 be less than full.
766 However, only do that if the value is not BLKmode. */
773 /* This is the mode we must force value to, so that there will be enough
774 subwords to extract. Note that fieldmode will often (always?) be
775 VOIDmode, because that is what store_field uses to indicate that this
776 is a bit field, but passing VOIDmode to operand_subword_force
777 is not allowed. */
784 {
785 /* If I is 0, use the low-order word in both field and target;
786 if I is 1, use the next to lowest word; and so on. */
800 /* If the remaining chunk doesn't have full wordsize we have
801 to make sure that for big endian machines the higher order
802 bits are used. */
805 value_word,
809 OPTAB_LIB_WIDEN);
814 word_mode,
816 {
819 }
820 }
822 }
824 /* If VALUE has a floating-point or complex mode, access it as an
825 integer of the corresponding size. This can occur on a machine
826 with 64 bit registers that uses SFmode for float. It can also
827 occur for unaligned float or complex fields. */
832 {
835 }
837 /* If OP0 is a multi-word register, narrow it to the affected word.
838 If the region spans two words, defer to store_split_bit_field. */
840 {
846 {
853 }
854 }
856 /* From here on we can assume that the field to be stored in fits
857 within a word. If the destination is a register, it too fits
858 in a word. */
860 extraction_insn insv;
864 fieldmode)
868 /* If OP0 is a memory, try copying it to a register and seeing if a
869 cheap register alternative is available. */
871 {
873 fieldmode)
879 /* Try loading part of OP0 into a register, inserting the bitfield
880 into that, and then copying the result back to OP0. */
886 {
891 {
894 }
896 }
897 }
905 }
907 /* Generate code to store value from rtx VALUE
908 into a bit-field within structure STR_RTX
909 containing BITSIZE bits starting at bit BITNUM.
911 BITREGION_START is bitpos of the first bitfield in this region.
912 BITREGION_END is the bitpos of the ending bitfield in this region.
913 These two fields are 0, if the C++ memory model does not apply,
914 or we are not interested in keeping track of bitfield regions.
916 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
918 void
924 rtx value)
925 {
926 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
929 {
930 /* Storing any naturally aligned field can be done with a simple
931 store. For targets that support fast unaligned memory, any
932 naturally sized, unit aligned field can be done directly. */
934 {
938 }
939 else
940 {
943 /* Explicitly override the C/C++ memory model; ignore the
944 bit range so that we can do the access in the mode mandated
945 by -fstrict-volatile-bitfields instead. */
947 }
950 }
952 /* Under the C++0x memory model, we must not touch bits outside the
953 bit region. Adjust the address to start at the beginning of the
954 bit region. */
956 {
972 }
978 }
979 \f
980 /* Use shifts and boolean operations to store VALUE into a bit field of
981 width BITSIZE in OP0, starting at bit BITNUM. */
983 static void
988 rtx value)
989 {
990 /* There is a case not handled here:
991 a structure with a known alignment of just a halfword
992 and a field split across two aligned halfwords within the structure.
993 Or likewise a structure with a known alignment of just a byte
994 and a field split across two bytes.
995 Such cases are not supposed to be able to occur. */
998 {
1007 {
1008 /* The only way this should occur is if the field spans word
1009 boundaries. */
1013 }
1016 }
1019 }
1021 /* Helper function for store_fixed_bit_field, stores
1022 the bit field always using the MODE of OP0. */
1024 static void
1027 rtx value)
1028 {
1030 rtx temp;
1037 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1038 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1041 /* BITNUM is the distance between our msb
1042 and that of the containing datum.
1043 Convert it to the distance from the lsb. */
1046 /* Now BITNUM is always the distance between our lsb
1047 and that of OP0. */
1049 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1050 we must first convert its mode to MODE. */
1053 {
1067 }
1068 else
1069 {
1083 }
1085 /* Now clear the chosen bits in OP0,
1086 except that if VALUE is -1 we need not bother. */
1087 /* We keep the intermediates in registers to allow CSE to combine
1088 consecutive bitfield assignments. */
1093 {
1098 }
1100 /* Now logical-or VALUE into OP0, unless it is zero. */
1103 {
1107 }
1110 {
1113 }
1114 }
1115 \f
1116 /* Store a bit field that is split across multiple accessible memory objects.
1118 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1119 BITSIZE is the field width; BITPOS the position of its first bit
1120 (within the word).
1121 VALUE is the value to store.
1123 This does not yet handle fields wider than BITS_PER_WORD. */
1125 static void
1130 rtx value)
1131 {
1135 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1136 much at a time. */
1139 else
1142 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1143 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1144 again, and we will mutually recurse forever. */
1148 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1149 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1150 that VALUE might be a floating-point constant. */
1152 {
1157 else
1162 }
1165 {
1174 /* When region of bytes we can touch is restricted, decrease
1175 UNIT close to the end of the region as needed. If op0 is a REG
1176 or SUBREG of REG, don't do this, as there can't be data races
1177 on a register and we can expand shorter code in some cases. */
1183 {
1186 }
1188 /* THISSIZE must not overrun a word boundary. Otherwise,
1189 store_fixed_bit_field will call us again, and we will mutually
1190 recurse forever. */
1195 {
1196 /* Fetch successively less significant portions. */
1201 else
1202 {
1204 /* The args are chosen so that the last part includes the
1205 lsb. Give extract_bit_field the value it needs (with
1206 endianness compensation) to fetch the piece we want. */
1210 }
1211 }
1212 else
1213 {
1214 /* Fetch successively more significant portions. */
1219 else
1222 }
1224 /* If OP0 is a register, then handle OFFSET here.
1226 When handling multiword bitfields, extract_bit_field may pass
1227 down a word_mode SUBREG of a larger REG for a bitfield that actually
1228 crosses a word boundary. Thus, for a SUBREG, we must find
1229 the current word starting from the base register. */
1231 {
1237 else
1241 }
1243 {
1247 else
1251 }
1252 else
1255 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1256 it is just an out-of-bounds access. Ignore it. */
1261 }
1262 }
1263 \f
1264 /* A subroutine of extract_bit_field_1 that converts return value X
1265 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1266 to extract_bit_field. */
1268 static rtx
1271 {
1275 /* If the x mode is not a scalar integral, first convert to the
1276 integer mode of that size and then access it as a floating-point
1277 value via a SUBREG. */
1279 {
1286 }
1289 }
1291 /* Try to use an ext(z)v pattern to extract a field from OP0.
1292 Return the extracted value on success, otherwise return null.
1293 EXT_MODE is the mode of the extraction and the other arguments
1294 are as for extract_bit_field. */
1296 static rtx
1302 {
1313 /* Get a reference to the first byte of the field. */
1316 else
1317 {
1318 /* Convert from counting within OP0 to counting in EXT_MODE. */
1322 /* If op0 is a register, we need it in EXT_MODE to make it
1323 acceptable to the format of ext(z)v. */
1328 }
1330 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1331 "backwards" from the size of the unit we are extracting from.
1332 Otherwise, we count bits from the most significant on a
1333 BYTES/BITS_BIG_ENDIAN machine. */
1342 {
1343 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1344 between the mode of the extraction (word_mode) and the target
1345 mode. Instead, create a temporary and use convert_move to set
1346 the target. */
1349 {
1354 }
1355 else
1357 }
1364 {
1371 }
1373 }
1375 /* A subroutine of extract_bit_field, with the same arguments.
1376 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1377 if we can find no other means of implementing the operation.
1378 if FALLBACK_P is false, return NULL instead. */
1380 static rtx
1385 {
1394 {
1397 }
1399 /* If we have an out-of-bounds access to a register, just return an
1400 uninitialized register of the required mode. This can occur if the
1401 source code contains an out-of-bounds access to a small array. */
1409 {
1410 /* We're trying to extract a full register from itself. */
1412 }
1414 /* See if we can get a better vector mode before extracting. */
1418 {
1431 else
1440 }
1442 /* Use vec_extract patterns for extracting parts of vectors whenever
1443 available. */
1449 {
1460 {
1465 }
1466 }
1468 /* Make sure we are playing with integral modes. Pun with subregs
1469 if we aren't. */
1470 {
1473 {
1477 {
1480 /* If we got a SUBREG, force it into a register since we
1481 aren't going to be able to do another SUBREG on it. */
1484 }
1486 {
1489 MODE_INT);
1495 }
1496 else
1497 {
1502 }
1503 }
1504 }
1506 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1507 If that's wrong, the solution is to test for it and set TARGET to 0
1508 if needed. */
1510 /* Get the mode of the field to use for atomic access or subreg
1511 conversion. */
1514 {
1519 }
1522 /* Extraction of a full MODE1 value can be done with a subreg as long
1523 as the least significant bit of the value is the least significant
1524 bit of either OP0 or a word of OP0. */
1529 {
1534 }
1536 /* Extraction of a full MODE1 value can be done with a load as long as
1537 the field is on a byte boundary and is sufficiently aligned. */
1539 {
1542 }
1544 /* Handle fields bigger than a word. */
1547 {
1548 /* Here we transfer the words of the field
1549 in the order least significant first.
1550 This is because the most significant word is the one which may
1551 be less than full. */
1561 /* Indicate for flow that the entire target reg is being set. */
1566 {
1567 /* If I is 0, use the low-order word in both field and target;
1568 if I is 1, use the next to lowest word; and so on. */
1569 /* Word number in TARGET to use. */
1570 unsigned int wordnum
1571 = (backwards
1574 /* Offset from start of field in OP0. */
1581 rtx result_part
1589 {
1592 }
1596 }
1599 {
1600 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1601 need to be zero'd out. */
1603 {
1608 emit_move_insn
1612 const0_rtx);
1613 }
1615 }
1617 /* Signed bit field: sign-extend with two arithmetic shifts. */
1622 }
1624 /* If OP0 is a multi-word register, narrow it to the affected word.
1625 If the region spans two words, defer to extract_split_bit_field. */
1627 {
1632 {
1637 }
1638 }
1640 /* From here on we know the desired field is smaller than a word.
1641 If OP0 is a register, it too fits within a word. */
1643 extraction_insn extv;
1645 /* ??? We could limit the structure size to the part of OP0 that
1646 contains the field, with appropriate checks for endianness
1647 and TRULY_NOOP_TRUNCATION. */
1650 tmode))
1651 {
1654 tmode);
1657 }
1659 /* If OP0 is a memory, try copying it to a register and seeing if a
1660 cheap register alternative is available. */
1662 {
1664 tmode))
1665 {
1669 tmode);
1672 }
1676 /* Try loading part of OP0 into a register and extracting the
1677 bitfield from that. */
1682 {
1690 }
1691 }
1696 /* Find a correspondingly-sized integer field, so we can apply
1697 shifts and masks to it. */
1701 /* Should probably push op0 out to memory and then do a load. */
1707 }
1709 /* Generate code to extract a byte-field from STR_RTX
1710 containing BITSIZE bits, starting at BITNUM,
1711 and put it in TARGET if possible (if TARGET is nonzero).
1712 Regardless of TARGET, we return the rtx for where the value is placed.
1714 STR_RTX is the structure containing the byte (a REG or MEM).
1715 UNSIGNEDP is nonzero if this is an unsigned bit field.
1716 MODE is the natural mode of the field value once extracted.
1717 TMODE is the mode the caller would like the value to have;
1718 but the value may be returned with type MODE instead.
1720 If a TARGET is specified and we can store in it at no extra cost,
1721 we do so, and return TARGET.
1722 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1723 if they are equally easy. */
1725 rtx
1729 {
1732 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1737 else
1741 {
1742 rtx result;
1744 /* Extraction of a full MODE1 value can be done with a load as long as
1745 the field is on a byte boundary and is sufficiently aligned. */
1749 else
1750 {
1755 }
1758 }
1762 }
1763 \f
1764 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1765 from bit BITNUM of OP0.
1767 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1768 If TARGET is nonzero, attempts to store the value there
1769 and return TARGET, but this is not guaranteed.
1770 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1772 static rtx
1777 {
1779 {
1780 enum machine_mode mode
1785 /* The only way this should occur is if the field spans word
1786 boundaries. */
1790 }
1794 }
1796 /* Helper function for extract_fixed_bit_field, extracts
1797 the bit field always using the MODE of OP0. */
1799 static rtx
1804 {
1808 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1809 for invalid input, such as extract equivalent of f5 from
1810 gcc.dg/pr48335-2.c. */
1813 /* BITNUM is the distance between our msb and that of OP0.
1814 Convert it to the distance from the lsb. */
1817 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1818 We have reduced the big-endian case to the little-endian case. */
1821 {
1823 {
1824 /* If the field does not already start at the lsb,
1825 shift it so it does. */
1826 /* Maybe propagate the target for the shift. */
1831 }
1832 /* Convert the value to the desired mode. */
1836 /* Unless the msb of the field used to be the msb when we shifted,
1837 mask out the upper bits. */
1844 }
1846 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1847 then arithmetic-shift its lsb to the lsb of the word. */
1850 /* Find the narrowest integer mode that contains the field. */
1855 {
1858 }
1864 {
1866 /* Maybe propagate the target for the shift. */
1869 }
1873 }
1875 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1876 VALUE << BITPOS. */
1878 static rtx
1881 {
1883 }
1884 \f
1885 /* Extract a bit field that is split across two words
1886 and return an RTX for the result.
1888 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1889 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1890 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1892 static rtx
1895 {
1901 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1902 much at a time. */
1905 else
1909 {
1918 /* THISSIZE must not overrun a word boundary. Otherwise,
1919 extract_fixed_bit_field will call us again, and we will mutually
1920 recurse forever. */
1924 /* If OP0 is a register, then handle OFFSET here.
1926 When handling multiword bitfields, extract_bit_field may pass
1927 down a word_mode SUBREG of a larger REG for a bitfield that actually
1928 crosses a word boundary. Thus, for a SUBREG, we must find
1929 the current word starting from the base register. */
1931 {
1936 }
1938 {
1941 }
1942 else
1945 /* Extract the parts in bit-counting order,
1946 whose meaning is determined by BYTES_PER_UNIT.
1947 OFFSET is in UNITs, and UNIT is in bits. */
1952 /* Shift this part into place for the result. */
1954 {
1958 }
1959 else
1960 {
1964 }
1968 else
1969 /* Combine the parts with bitwise or. This works
1970 because we extracted each part as an unsigned bit field. */
1972 OPTAB_LIB_WIDEN);
1975 }
1977 /* Unsigned bit field: we are done. */
1980 /* Signed bit field: sign-extend with two arithmetic shifts. */
1985 }
1986 \f
1987 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
1988 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
1989 MODE, fill the upper bits with zeros. Fail if the layout of either
1990 mode is unknown (as for CC modes) or if the extraction would involve
1991 unprofitable mode punning. Return the value on success, otherwise
1992 return null.
1994 This is different from gen_lowpart* in these respects:
1996 - the returned value must always be considered an rvalue
1998 - when MODE is wider than SRC_MODE, the extraction involves
1999 a zero extension
2001 - when MODE is smaller than SRC_MODE, the extraction involves
2002 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2004 In other words, this routine performs a computation, whereas the
2005 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2006 operations. */
2008 rtx
2010 {
2017 {
2018 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2019 fails, it will happily create (subreg (symbol_ref)) or similar
2020 invalid SUBREGs. */
2032 }
2039 {
2043 }
2059 }
2060 \f
2061 /* Add INC into TARGET. */
2063 void
2065 {
2071 }
2073 /* Subtract DEC from TARGET. */
2075 void
2077 {
2083 }
2084 \f
2085 /* Output a shift instruction for expression code CODE,
2086 with SHIFTED being the rtx for the value to shift,
2087 and AMOUNT the rtx for the amount to shift by.
2088 Store the result in the rtx TARGET, if that is convenient.
2089 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2090 Return the rtx for where the value is. */
2092 static rtx
2095 {
2114 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2115 shift amount is a vector, use the vector/vector shift patterns. */
2117 {
2123 }
2125 /* Previously detected shift-counts computed by NEGATE_EXPR
2126 and shifted in the other direction; but that does not work
2127 on all machines. */
2130 {
2141 }
2143 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2144 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2145 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2146 amount instead. */
2151 {
2155 }
2160 /* Check whether its cheaper to implement a left shift by a constant
2161 bit count by a sequence of additions. */
2170 {
2173 {
2177 }
2179 }
2182 {
2189 else
2193 {
2194 /* Widening does not work for rotation. */
2198 {
2199 /* If we have been unable to open-code this by a rotation,
2200 do it as the IOR of two shifts. I.e., to rotate A
2201 by N bits, compute
2202 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2203 where C is the bitsize of A.
2205 It is theoretically possible that the target machine might
2206 not be able to perform either shift and hence we would
2207 be making two libcalls rather than just the one for the
2208 shift (similarly if IOR could not be done). We will allow
2209 this extremely unlikely lossage to avoid complicating the
2210 code below. */
2214 rtx temp1;
2222 else
2223 {
2224 other_amount
2228 other_amount
2231 }
2242 }
2247 }
2253 /* Do arithmetic shifts.
2254 Also, if we are going to widen the operand, we can just as well
2255 use an arithmetic right-shift instead of a logical one. */
2258 {
2261 /* If trying to widen a log shift to an arithmetic shift,
2262 don't accept an arithmetic shift of the same size. */
2266 /* Arithmetic shift */
2271 }
2273 /* We used to try extzv here for logical right shifts, but that was
2274 only useful for one machine, the VAX, and caused poor code
2275 generation there for lshrdi3, so the code was deleted and a
2276 define_expand for lshrsi3 was added to vax.md. */
2277 }
2281 }
2283 /* Output a shift instruction for expression code CODE,
2284 with SHIFTED being the rtx for the value to shift,
2285 and AMOUNT the amount to shift by.
2286 Store the result in the rtx TARGET, if that is convenient.
2287 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2288 Return the rtx for where the value is. */
2290 rtx
2293 {
2296 }
2298 /* Output a shift instruction for expression code CODE,
2299 with SHIFTED being the rtx for the value to shift,
2300 and AMOUNT the tree for the amount to shift by.
2301 Store the result in the rtx TARGET, if that is convenient.
2302 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2303 Return the rtx for where the value is. */
2305 rtx
2308 {
2311 }
2313 \f
2314 /* Indicates the type of fixup needed after a constant multiplication.
2315 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2316 the result should be negated, and ADD_VARIANT means that the
2317 multiplicand should be added to the result. */
2331 /* Compute and return the best algorithm for multiplying by T.
2332 The algorithm must cost less than cost_limit
2333 If retval.cost >= COST_LIMIT, no algorithm was found and all
2334 other field of the returned struct are undefined.
2335 MODE is the machine mode of the multiplication. */
2337 static void
2340 {
2355 /* Indicate that no algorithm is yet found. If no algorithm
2356 is found, this value will be returned and indicate failure. */
2364 /* Be prepared for vector modes. */
2371 /* Restrict the bits of "t" to the multiplication's mode. */
2374 /* t == 1 can be done in zero cost. */
2376 {
2382 }
2384 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2385 fail now. */
2387 {
2390 else
2391 {
2397 }
2398 }
2400 /* We'll be needing a couple extra algorithm structures now. */
2406 /* Compute the hash index. */
2409 /* See if we already know what to do for T. */
2416 {
2420 {
2421 /* The cache tells us that it's impossible to synthesize
2422 multiplication by T within entry_ptr->cost. */
2424 /* COST_LIMIT is at least as restrictive as the one
2425 recorded in the hash table, in which case we have no
2426 hope of synthesizing a multiplication. Just
2427 return. */
2430 /* If we get here, COST_LIMIT is less restrictive than the
2431 one recorded in the hash table, so we may be able to
2432 synthesize a multiplication. Proceed as if we didn't
2433 have the cache entry. */
2434 }
2435 else
2436 {
2438 /* The cached algorithm shows that this multiplication
2439 requires more cost than COST_LIMIT. Just return. This
2440 way, we don't clobber this cache entry with
2441 alg_impossible but retain useful information. */
2447 {
2467 }
2468 }
2469 }
2471 /* If we have a group of zero bits at the low-order part of T, try
2472 multiplying by the remaining bits and then doing a shift. */
2475 {
2476 do_alg_shift:
2479 {
2481 /* The function expand_shift will choose between a shift and
2482 a sequence of additions, so the observed cost is given as
2483 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2494 {
2500 }
2502 /* See if treating ORIG_T as a signed number yields a better
2503 sequence. Try this sequence only for a negative ORIG_T
2504 as it would be useless for a non-negative ORIG_T. */
2506 {
2507 /* Shift ORIG_T as follows because a right shift of a
2508 negative-valued signed type is implementation
2509 defined. */
2511 /* The function expand_shift will choose between a shift
2512 and a sequence of additions, so the observed cost is
2513 given as MIN (m * add_cost(speed, mode),
2514 shift_cost(speed, mode, m)). */
2525 {
2531 }
2532 }
2533 }
2536 }
2538 /* If we have an odd number, add or subtract one. */
2540 {
2543 do_alg_addsub_t_m2:
2545 ;
2546 /* If T was -1, then W will be zero after the loop. This is another
2547 case where T ends with ...111. Handling this with (T + 1) and
2548 subtract 1 produces slightly better code and results in algorithm
2549 selection much faster than treating it like the ...0111 case
2550 below. */
2553 /* Reject the case where t is 3.
2554 Thus we prefer addition in that case. */
2556 {
2557 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2567 {
2573 }
2574 }
2575 else
2576 {
2577 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2587 {
2593 }
2594 }
2596 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2597 quickly with a - a * n for some appropriate constant n. */
2600 {
2610 {
2616 }
2617 }
2621 }
2623 /* Look for factors of t of the form
2624 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2625 If we find such a factor, we can multiply by t using an algorithm that
2626 multiplies by q, shift the result by m and add/subtract it to itself.
2628 We search for large factors first and loop down, even if large factors
2629 are less probable than small; if we find a large factor we will find a
2630 good sequence quickly, and therefore be able to prune (by decreasing
2631 COST_LIMIT) the search. */
2633 do_alg_addsub_factor:
2635 {
2641 {
2642 /* If the target has a cheap shift-and-add instruction use
2643 that in preference to a shift insn followed by an add insn.
2644 Assume that the shift-and-add is "atomic" with a latency
2645 equal to its cost, otherwise assume that on superscalar
2646 hardware the shift may be executed concurrently with the
2647 earlier steps in the algorithm. */
2650 {
2653 }
2654 else
2666 {
2672 }
2673 /* Other factors will have been taken care of in the recursion. */
2675 }
2680 {
2681 /* If the target has a cheap shift-and-subtract insn use
2682 that in preference to a shift insn followed by a sub insn.
2683 Assume that the shift-and-sub is "atomic" with a latency
2684 equal to it's cost, otherwise assume that on superscalar
2685 hardware the shift may be executed concurrently with the
2686 earlier steps in the algorithm. */
2689 {
2692 }
2693 else
2705 {
2711 }
2713 }
2714 }
2718 /* Try shift-and-add (load effective address) instructions,
2719 i.e. do a*3, a*5, a*9. */
2721 {
2722 do_alg_add_t2_m:
2727 {
2736 {
2742 }
2743 }
2747 do_alg_sub_t2_m:
2752 {
2761 {
2767 }
2768 }
2771 }
2773 done:
2774 /* If best_cost has not decreased, we have not found any algorithm. */
2776 {
2777 /* We failed to find an algorithm. Record alg_impossible for
2778 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2779 we are asked to find an algorithm for T within the same or
2780 lower COST_LIMIT, we can immediately return to the
2781 caller. */
2788 }
2790 /* Cache the result. */
2792 {
2799 }
2801 /* If we are getting a too long sequence for `struct algorithm'
2802 to record, make this search fail. */
2806 /* Copy the algorithm from temporary space to the space at alg_out.
2807 We avoid using structure assignment because the majority of
2808 best_alg is normally undefined, and this is a critical function. */
2815 }
2816 \f
2817 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2818 Try three variations:
2820 - a shift/add sequence based on VAL itself
2821 - a shift/add sequence based on -VAL, followed by a negation
2822 - a shift/add sequence based on VAL - 1, followed by an addition.
2824 Return true if the cheapest of these cost less than MULT_COST,
2825 describing the algorithm in *ALG and final fixup in *VARIANT. */
2827 static bool
2831 {
2837 /* Fail quickly for impossible bounds. */
2841 /* Ensure that mult_cost provides a reasonable upper bound.
2842 Any constant multiplication can be performed with less
2843 than 2 * bits additions. */
2853 /* This works only if the inverted value actually fits in an
2854 `unsigned int' */
2856 {
2859 {
2862 }
2863 else
2864 {
2867 }
2874 }
2876 /* This proves very useful for division-by-constant. */
2879 {
2882 }
2883 else
2884 {
2887 }
2896 }
2898 /* A subroutine of expand_mult, used for constant multiplications.
2899 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2900 convenient. Use the shift/add sequence described by ALG and apply
2901 the final fixup specified by VARIANT. */
2903 static rtx
2907 {
2908 HOST_WIDE_INT val_so_far;
2914 /* Avoid referencing memory over and over and invalid sharing
2915 on SUBREGs. */
2918 /* ACCUM starts out either as OP0 or as a zero, depending on
2919 the first operation. */
2922 {
2925 }
2927 {
2930 }
2931 else
2935 {
2938 rtx add_target
2943 rtx accum_inner;
2946 {
2949 /* REG_EQUAL note will be attached to the following insn. */
2994 (add_target
3001 }
3004 {
3005 /* Write a REG_EQUAL note on the last insn so that we can cse
3006 multiplication sequences. Note that if ACCUM is a SUBREG,
3007 we've set the inner register and must properly indicate that. */
3011 {
3015 }
3021 accum_inner);
3022 }
3023 }
3026 {
3029 }
3031 {
3034 }
3036 /* Compare only the bits of val and val_so_far that are significant
3037 in the result mode, to avoid sign-/zero-extension confusion. */
3046 }
3048 /* Perform a multiplication and return an rtx for the result.
3049 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3050 TARGET is a suggestion for where to store the result (an rtx).
3052 We check specially for a constant integer as OP1.
3053 If you want this check for OP0 as well, then before calling
3054 you should swap the two operands if OP0 would be constant. */
3056 rtx
3059 {
3062 rtx scalar_op1;
3068 {
3072 }
3074 /* For vectors, there are several simplifications that can be made if
3075 all elements of the vector constant are identical. */
3078 {
3084 }
3087 {
3088 rtx fake_reg;
3089 HOST_WIDE_INT coeff;
3104 /* If mode is integer vector mode, check if the backend supports
3105 vector lshift (by scalar or vector) at all. If not, we can't use
3106 synthetized multiply. */
3112 /* These are the operations that are potentially turned into
3113 a sequence of shifts and additions. */
3116 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3117 less than or equal in size to `unsigned int' this doesn't matter.
3118 If the mode is larger than `unsigned int', then synth_mult works
3119 only if the constant value exactly fits in an `unsigned int' without
3120 any truncation. This means that multiplying by negative values does
3121 not work; results are off by 2^32 on a 32 bit machine. */
3123 {
3126 }
3127 #if TARGET_SUPPORTS_WIDE_INT
3129 #else
3131 #endif
3132 {
3134 /* Perfect power of 2 (other than 1, which is handled above). */
3138 else
3140 }
3141 else
3144 /* We used to test optimize here, on the grounds that it's better to
3145 produce a smaller program when -O is not used. But this causes
3146 such a terrible slowdown sometimes that it seems better to always
3147 use synth_mult. */
3149 /* Special case powers of two. */
3157 /* Attempt to handle multiplication of DImode values by negative
3158 coefficients, by performing the multiplication by a positive
3159 multiplier and then inverting the result. */
3161 {
3162 /* Its safe to use -coeff even for INT_MIN, as the
3163 result is interpreted as an unsigned coefficient.
3164 Exclude cost of op0 from max_cost to match the cost
3165 calculation of the synth_mult. */
3172 /* Special case powers of two. */
3174 {
3178 }
3181 max_cost))
3182 {
3186 }
3188 }
3190 /* Exclude cost of op0 from max_cost to match the cost
3191 calculation of the synth_mult. */
3196 }
3197 skip_synth:
3199 /* Expand x*2.0 as x+x. */
3201 {
3202 REAL_VALUE_TYPE d;
3206 {
3210 }
3211 }
3212 skip_scalar:
3214 /* This used to use umul_optab if unsigned, but for non-widening multiply
3215 there is no difference between signed and unsigned. */
3220 }
3222 /* Return a cost estimate for multiplying a register by the given
3223 COEFFicient in the given MODE and SPEED. */
3225 int
3227 {
3236 else
3238 }
3240 /* Perform a widening multiplication and return an rtx for the result.
3241 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3242 TARGET is a suggestion for where to store the result (an rtx).
3243 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3244 or smul_widen_optab.
3246 We check specially for a constant integer as OP1, comparing the
3247 cost of a widening multiply against the cost of a sequence of shifts
3248 and adds. */
3250 rtx
3253 {
3255 rtx cop1;
3264 {
3270 /* Special case powers of two. */
3272 {
3276 }
3278 /* Exclude cost of op0 from max_cost to match the cost
3279 calculation of the synth_mult. */
3282 max_cost))
3283 {
3287 }
3288 }
3291 }
3292 \f
3293 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3294 replace division by D, and put the least significant N bits of the result
3295 in *MULTIPLIER_PTR and return the most significant bit.
3297 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3298 needed precision is in PRECISION (should be <= N).
3300 PRECISION should be as small as possible so this function can choose
3301 multiplier more freely.
3303 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3304 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3306 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3307 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3309 unsigned HOST_WIDE_INT
3313 {
3317 /* lgup = ceil(log2(divisor)); */
3325 /* mlow = 2^(N + lgup)/d */
3329 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3333 /* If precision == N, then mlow, mhigh exceed 2^N
3334 (but they do not exceed 2^(N+1)). */
3336 /* Reduce to lowest terms. */
3338 {
3340 HOST_BITS_PER_WIDE_INT);
3342 HOST_BITS_PER_WIDE_INT);
3348 }
3353 {
3357 }
3358 else
3359 {
3362 }
3363 }
3365 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3366 congruent to 1 (mod 2**N). */
3368 static unsigned HOST_WIDE_INT
3370 {
3371 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3373 /* The algorithm notes that the choice y = x satisfies
3374 x*y == 1 mod 2^3, since x is assumed odd.
3375 Each iteration doubles the number of bits of significance in y. */
3386 {
3389 }
3391 }
3393 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3394 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3395 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3396 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3397 become signed.
3399 The result is put in TARGET if that is convenient.
3401 MODE is the mode of operation. */
3403 rtx
3406 {
3407 rtx tem;
3413 adj_operand
3415 adj_operand);
3421 target);
3424 }
3426 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3428 static rtx
3430 {
3442 }
3444 /* Like expmed_mult_highpart, but only consider using a multiplication
3445 optab. OP1 is an rtx for the constant operand. */
3447 static rtx
3450 {
3453 optab moptab;
3454 rtx tem;
3463 /* Firstly, try using a multiplication insn that only generates the needed
3464 high part of the product, and in the sign flavor of unsignedp. */
3466 {
3472 }
3474 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3475 Need to adjust the result after the multiplication. */
3480 {
3485 /* We used the wrong signedness. Adjust the result. */
3488 }
3490 /* Try widening multiplication. */
3494 {
3499 }
3501 /* Try widening the mode and perform a non-widening multiplication. */
3506 {
3510 /* We need to widen the operands, for example to ensure the
3511 constant multiplier is correctly sign or zero extended.
3512 Use a sequence to clean-up any instructions emitted by
3513 the conversions if things don't work out. */
3523 {
3526 }
3527 }
3529 /* Try widening multiplication of opposite signedness, and adjust. */
3536 {
3540 {
3542 /* We used the wrong signedness. Adjust the result. */
3545 }
3546 }
3549 }
3551 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3552 putting the high half of the result in TARGET if that is convenient,
3553 and return where the result is. If the operation can not be performed,
3554 0 is returned.
3556 MODE is the mode of operation and result.
3558 UNSIGNEDP nonzero means unsigned multiply.
3560 MAX_COST is the total allowed cost for the expanded RTL. */
3562 static rtx
3565 {
3572 rtx tem;
3576 /* We can't support modes wider than HOST_BITS_PER_INT. */
3581 /* We can't optimize modes wider than BITS_PER_WORD.
3582 ??? We might be able to perform double-word arithmetic if
3583 mode == word_mode, however all the cost calculations in
3584 synth_mult etc. assume single-word operations. */
3591 /* Check whether we try to multiply by a negative constant. */
3593 {
3596 }
3598 /* See whether shift/add multiplication is cheap enough. */
3601 {
3602 /* See whether the specialized multiplication optabs are
3603 cheaper than the shift/add version. */
3613 /* Adjust result for signedness. */
3618 }
3621 }
3624 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3626 static rtx
3628 {
3637 /* Avoid conditional branches when they're expensive. */
3640 {
3644 {
3649 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3650 which instruction sequence to use. If logical right shifts
3651 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3652 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3658 {
3670 }
3671 else
3672 {
3684 }
3686 }
3687 }
3689 /* Mask contains the mode's signbit and the significant bits of the
3690 modulus. By including the signbit in the operation, many targets
3691 can avoid an explicit compare operation in the following comparison
3692 against zero. */
3718 }
3720 /* Expand signed division of OP0 by a power of two D in mode MODE.
3721 This routine is only called for positive values of D. */
3723 static rtx
3725 {
3726 rtx temp;
3735 {
3741 }
3743 #ifdef HAVE_conditional_move
3746 {
3747 rtx temp2;
3755 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3759 {
3764 }
3766 }
3767 #endif
3771 {
3781 else
3787 }
3795 }
3796 \f
3797 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3798 if that is convenient, and returning where the result is.
3799 You may request either the quotient or the remainder as the result;
3800 specify REM_FLAG nonzero to get the remainder.
3802 CODE is the expression code for which kind of division this is;
3803 it controls how rounding is done. MODE is the machine mode to use.
3804 UNSIGNEDP nonzero means do unsigned division. */
3806 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3807 and then correct it by or'ing in missing high bits
3808 if result of ANDI is nonzero.
3809 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3810 This could optimize to a bfexts instruction.
3811 But C doesn't use these operations, so their optimizations are
3812 left for later. */
3813 /* ??? For modulo, we don't actually need the highpart of the first product,
3814 the low part will do nicely. And for small divisors, the second multiply
3815 can also be a low-part only multiply or even be completely left out.
3816 E.g. to calculate the remainder of a division by 3 with a 32 bit
3817 multiply, multiply with 0x55555556 and extract the upper two bits;
3818 the result is exact for inputs up to 0x1fffffff.
3819 The input range can be reduced by using cross-sum rules.
3820 For odd divisors >= 3, the following table gives right shift counts
3821 so that if a number is shifted by an integer multiple of the given
3822 amount, the remainder stays the same:
3823 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3824 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3825 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3826 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3827 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3829 Cross-sum rules for even numbers can be derived by leaving as many bits
3830 to the right alone as the divisor has zeros to the right.
3831 E.g. if x is an unsigned 32 bit number:
3832 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3833 */
3835 rtx
3838 {
3840 rtx tquotient;
3853 {
3859 }
3861 /*
3862 This is the structure of expand_divmod:
3864 First comes code to fix up the operands so we can perform the operations
3865 correctly and efficiently.
3867 Second comes a switch statement with code specific for each rounding mode.
3868 For some special operands this code emits all RTL for the desired
3869 operation, for other cases, it generates only a quotient and stores it in
3870 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3871 to indicate that it has not done anything.
3873 Last comes code that finishes the operation. If QUOTIENT is set and
3874 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3875 QUOTIENT is not set, it is computed using trunc rounding.
3877 We try to generate special code for division and remainder when OP1 is a
3878 constant. If |OP1| = 2**n we can use shifts and some other fast
3879 operations. For other values of OP1, we compute a carefully selected
3880 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3881 by m.
3883 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3884 half of the product. Different strategies for generating the product are
3885 implemented in expmed_mult_highpart.
3887 If what we actually want is the remainder, we generate that by another
3888 by-constant multiplication and a subtraction. */
3890 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3891 code below will malfunction if we are, so check here and handle
3892 the special case if so. */
3896 /* When dividing by -1, we could get an overflow.
3897 negv_optab can handle overflows. */
3899 {
3904 }
3907 /* Don't use the function value register as a target
3908 since we have to read it as well as write it,
3909 and function-inlining gets confused by this. */
3911 /* Don't clobber an operand while doing a multi-step calculation. */
3919 /* Get the mode in which to perform this computation. Normally it will
3920 be MODE, but sometimes we can't do the desired operation in MODE.
3921 If so, pick a wider mode in which we can do the operation. Convert
3922 to that mode at the start to avoid repeated conversions.
3924 First see what operations we need. These depend on the expression
3925 we are evaluating. (We assume that divxx3 insns exist under the
3926 same conditions that modxx3 insns and that these insns don't normally
3927 fail. If these assumptions are not correct, we may generate less
3928 efficient code in some cases.)
3930 Then see if we find a mode in which we can open-code that operation
3931 (either a division, modulus, or shift). Finally, check for the smallest
3932 mode for which we can do the operation with a library call. */
3934 /* We might want to refine this now that we have division-by-constant
3935 optimization. Since expmed_mult_highpart tries so many variants, it is
3936 not straightforward to generalize this. Maybe we should make an array
3937 of possible modes in init_expmed? Save this for GCC 2.7. */
3943 ? optab1
3959 /* If we still couldn't find a mode, use MODE, but expand_binop will
3960 probably die. */
3966 else
3970 #if 0
3971 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3972 (mode), and thereby get better code when OP1 is a constant. Do that
3973 later. It will require going over all usages of SIZE below. */
3975 #endif
3977 /* Only deduct something for a REM if the last divide done was
3978 for a different constant. Then set the constant of the last
3979 divide. */
3980 max_cost = (unsignedp
3990 /* Now convert to the best mode to use. */
3992 {
3996 /* convert_modes may have placed op1 into a register, so we
3997 must recompute the following. */
3999 op1_is_pow2 = (op1_is_constant
4001 || (! unsignedp
4003 }
4005 /* If one of the operands is a volatile MEM, copy it into a register. */
4012 /* If we need the remainder or if OP1 is constant, we need to
4013 put OP0 in a register in case it has any queued subexpressions. */
4019 /* Promote floor rounding to trunc rounding for unsigned operations. */
4021 {
4028 }
4032 {
4036 {
4038 {
4046 {
4049 {
4050 unsigned HOST_WIDE_INT mask
4052 remainder
4056 OPTAB_LIB_WIDEN);
4059 }
4062 }
4064 {
4066 {
4067 /* Most significant bit of divisor is set; emit an scc
4068 insn. */
4071 }
4072 else
4073 {
4074 /* Find a suitable multiplier and right shift count
4075 instead of multiplying with D. */
4080 /* If the suggested multiplier is more than SIZE bits,
4081 we can do better for even divisors, using an
4082 initial right shift. */
4084 {
4090 }
4091 else
4095 {
4101 extra_cost
4105 t1 = expmed_mult_highpart
4113 NULL_RTX);
4118 NULL_RTX);
4119 quotient = expand_shift
4122 }
4123 else
4124 {
4131 t1 = expand_shift
4134 extra_cost
4137 t2 = expmed_mult_highpart
4143 quotient = expand_shift
4146 }
4147 }
4148 }
4156 quotient);
4157 }
4159 {
4162 rtx mlr;
4166 /* Since d might be INT_MIN, we have to cast to
4167 unsigned HOST_WIDE_INT before negating to avoid
4168 undefined signed overflow. */
4173 /* n rem d = n rem -d */
4175 {
4178 }
4187 {
4188 /* This case is not handled correctly below. */
4193 }
4195 && (rem_flag
4198 /* We assume that cheap metric is true if the
4199 optab has an expander for this mode. */
4202 compute_mode)
4205 compute_mode)
4207 ;
4209 {
4211 {
4215 }
4225 compute_mode),
4227 else
4230 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4231 negate the quotient. */
4233 {
4240 gen_int_mode
4242 compute_mode)),
4243 quotient);
4247 }
4248 }
4250 {
4254 {
4264 t1 = expmed_mult_highpart
4269 t2 = expand_shift
4272 t3 = expand_shift
4276 quotient
4279 tquotient);
4280 else
4281 quotient
4284 tquotient);
4285 }
4286 else
4287 {
4306 NULL_RTX);
4307 t3 = expand_shift
4310 t4 = expand_shift
4314 quotient
4317 tquotient);
4318 else
4319 quotient
4322 tquotient);
4323 }
4324 }
4332 quotient);
4333 }
4335 }
4336 fail1:
4342 /* We will come here only for signed operations. */
4344 {
4350 {
4351 /* We could just as easily deal with negative constants here,
4352 but it does not seem worth the trouble for GCC 2.6. */
4354 {
4357 {
4358 unsigned HOST_WIDE_INT mask
4360 remainder = expand_binop
4366 }
4367 quotient = expand_shift
4370 }
4371 else
4372 {
4381 {
4382 t1 = expand_shift
4390 t3 = expmed_mult_highpart
4394 {
4395 t4 = expand_shift
4400 OPTAB_WIDEN);
4401 }
4402 }
4403 }
4404 }
4405 else
4406 {
4412 nsign = expand_shift
4416 NULL_RTX);
4420 {
4421 rtx t5;
4426 tquotient);
4427 }
4428 }
4429 }
4435 /* Try using an instruction that produces both the quotient and
4436 remainder, using truncation. We can easily compensate the quotient
4437 or remainder to get floor rounding, once we have the remainder.
4438 Notice that we compute also the final remainder value here,
4439 and return the result right away. */
4444 {
4445 remainder
4448 }
4449 else
4450 {
4451 quotient
4454 }
4458 {
4459 /* This could be computed with a branch-less sequence.
4460 Save that for later. */
4461 rtx tem;
4471 }
4473 /* No luck with division elimination or divmod. Have to do it
4474 by conditionally adjusting op0 *and* the result. */
4475 {
4477 rtx adjusted_op0;
4478 rtx tem;
4516 }
4522 {
4524 {
4536 {
4543 }
4544 else
4547 tquotient);
4549 }
4551 /* Try using an instruction that produces both the quotient and
4552 remainder, using truncation. We can easily compensate the
4553 quotient or remainder to get ceiling rounding, once we have the
4554 remainder. Notice that we compute also the final remainder
4555 value here, and return the result right away. */
4560 {
4564 }
4565 else
4566 {
4570 }
4574 {
4575 /* This could be computed with a branch-less sequence.
4576 Save that for later. */
4584 }
4586 /* No luck with division elimination or divmod. Have to do it
4587 by conditionally adjusting op0 *and* the result. */
4588 {
4609 }
4610 }
4612 {
4615 {
4616 /* This is extremely similar to the code for the unsigned case
4617 above. For 2.7 we should merge these variants, but for
4618 2.6.1 I don't want to touch the code for unsigned since that
4619 get used in C. The signed case will only be used by other
4620 languages (Ada). */
4633 {
4640 }
4641 else
4644 tquotient);
4646 }
4648 /* Try using an instruction that produces both the quotient and
4649 remainder, using truncation. We can easily compensate the
4650 quotient or remainder to get ceiling rounding, once we have the
4651 remainder. Notice that we compute also the final remainder
4652 value here, and return the result right away. */
4656 {
4660 }
4661 else
4662 {
4666 }
4670 {
4671 /* This could be computed with a branch-less sequence.
4672 Save that for later. */
4673 rtx tem;
4684 }
4686 /* No luck with division elimination or divmod. Have to do it
4687 by conditionally adjusting op0 *and* the result. */
4688 {
4690 rtx adjusted_op0;
4691 rtx tem;
4731 }
4732 }
4737 {
4741 rtx t1;
4755 quotient);
4756 }
4762 {
4763 rtx tem;
4769 {
4770 rtx tem;
4776 }
4783 }
4784 else
4785 {
4792 {
4793 rtx tem;
4799 }
4820 }
4825 }
4828 {
4833 {
4834 /* Try to produce the remainder without producing the quotient.
4835 If we seem to have a divmod pattern that does not require widening,
4836 don't try widening here. We should really have a WIDEN argument
4837 to expand_twoval_binop, since what we'd really like to do here is
4838 1) try a mod insn in compute_mode
4839 2) try a divmod insn in compute_mode
4840 3) try a div insn in compute_mode and multiply-subtract to get
4841 remainder
4842 4) try the same things with widening allowed. */
4843 remainder
4846 unsignedp,
4851 {
4852 /* No luck there. Can we do remainder and divide at once
4853 without a library call? */
4856 ? udivmod_optab
4861 }
4865 }
4867 /* Produce the quotient. Try a quotient insn, but not a library call.
4868 If we have a divmod in this mode, use it in preference to widening
4869 the div (for this test we assume it will not fail). Note that optab2
4870 is set to the one of the two optabs that the call below will use. */
4871 quotient
4874 unsignedp,
4880 {
4881 /* No luck there. Try a quotient-and-remainder insn,
4882 keeping the quotient alone. */
4887 {
4890 /* Still no luck. If we are not computing the remainder,
4891 use a library call for the quotient. */
4896 }
4897 }
4898 }
4901 {
4906 {
4907 /* No divide instruction either. Use library for remainder. */
4911 /* No remainder function. Try a quotient-and-remainder
4912 function, keeping the remainder. */
4914 {
4922 }
4923 }
4924 else
4925 {
4926 /* We divided. Now finish doing X - Y * (X / Y). */
4931 OPTAB_LIB_WIDEN);
4932 }
4933 }
4936 }
4937 \f
4938 /* Return a tree node with data type TYPE, describing the value of X.
4939 Usually this is an VAR_DECL, if there is no obvious better choice.
4940 X may be an expression, however we only support those expressions
4941 generated by loop.c. */
4943 tree
4945 {
4946 tree t;
4949 {
4961 else
4962 {
4963 REAL_VALUE_TYPE d;
4967 }
4972 {
4978 /* Build a tree with vector elements. */
4981 {
4984 }
4987 }
5023 else
5048 /* else fall through. */
5053 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5054 address mode to pointer mode. */
5056 x = convert_memory_address_addr_space
5059 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5060 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5064 }
5065 }
5066 \f
5067 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5068 and returning TARGET.
5070 If TARGET is 0, a pseudo-register or constant is returned. */
5072 rtx
5074 {
5087 }
5089 /* Helper function for emit_store_flag. */
5090 static rtx
5095 {
5105 {
5108 }
5122 {
5125 }
5128 /* If we are converting to a wider mode, first convert to
5129 TARGET_MODE, then normalize. This produces better combining
5130 opportunities on machines that have a SIGN_EXTRACT when we are
5131 testing a single bit. This mostly benefits the 68k.
5133 If STORE_FLAG_VALUE does not have the sign bit set when
5134 interpreted in MODE, we can do this conversion as unsigned, which
5135 is usually more efficient. */
5137 {
5140 STORE_FLAG_VALUE));
5143 }
5144 else
5147 /* If we want to keep subexpressions around, don't reuse our last
5148 target. */
5152 /* Now normalize to the proper value in MODE. Sometimes we don't
5153 have to do anything. */
5155 ;
5156 /* STORE_FLAG_VALUE might be the most negative number, so write
5157 the comparison this way to avoid a compiler-time warning. */
5161 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5162 it hard to use a value of just the sign bit due to ANSI integer
5163 constant typing rules. */
5168 else
5169 {
5175 }
5177 /* If we were converting to a smaller mode, do the conversion now. */
5179 {
5182 }
5183 else
5185 }
5188 /* A subroutine of emit_store_flag only including "tricks" that do not
5189 need a recursive call. These are kept separate to avoid infinite
5190 loops. */
5192 static rtx
5196 {
5197 rtx subtarget;
5202 rtx tem;
5208 /* If one operand is constant, make it the second one. Only do this
5209 if the other operand is not constant as well. */
5212 {
5217 }
5222 /* For some comparisons with 1 and -1, we can convert this to
5223 comparisons with zero. This will often produce more opportunities for
5224 store-flag insns. */
5227 {
5254 }
5256 /* If we are comparing a double-word integer with zero or -1, we can
5257 convert the comparison into one involving a single word. */
5261 {
5264 {
5267 /* Do a logical OR or AND of the two words and compare the
5268 result. */
5274 OPTAB_DIRECT);
5279 }
5281 {
5282 rtx op0h;
5284 /* If testing the sign bit, can just test on high word. */
5287 mode));
5290 }
5291 else
5295 {
5306 }
5307 }
5309 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5310 complement of A (for GE) and shifting the sign bit to the low bit. */
5315 {
5321 /* If the result is to be wider than OP0, it is best to convert it
5322 first. If it is to be narrower, it is *incorrect* to convert it
5323 first. */
5325 {
5328 }
5339 /* If we are supposed to produce a 0/1 value, we want to do
5340 a logical shift from the sign bit to the low-order bit; for
5341 a -1/0 value, we do an arithmetic shift. */
5350 }
5355 {
5359 {
5367 {
5372 }
5374 }
5375 }
5378 }
5380 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5381 and storing in TARGET. Normally return TARGET.
5382 Return 0 if that cannot be done.
5384 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5385 it is VOIDmode, they cannot both be CONST_INT.
5387 UNSIGNEDP is for the case where we have to widen the operands
5388 to perform the operation. It says to use zero-extension.
5390 NORMALIZEP is 1 if we should convert the result to be either zero
5391 or one. Normalize is -1 if we should convert the result to be
5392 either zero or -1. If NORMALIZEP is zero, the result will be left
5393 "raw" out of the scc insn. */
5395 rtx
5398 {
5401 rtx subtarget;
5405 /* If we compare constants, we shouldn't use a store-flag operation,
5406 but a constant load. We can get there via the vanilla route that
5407 usually generates a compare-branch sequence, but will in this case
5408 fold the comparison to a constant, and thus elide the branch. */
5413 target_mode);
5417 /* If we reached here, we can't do this with a scc insn, however there
5418 are some comparisons that can be done in other ways. Don't do any
5419 of these cases if branches are very cheap. */
5423 /* See what we need to return. We can only return a 1, -1, or the
5424 sign bit. */
5427 {
5432 ;
5433 else
5435 }
5439 /* If optimizing, use different pseudo registers for each insn, instead
5440 of reusing the same pseudo. This leads to better CSE, but slows
5441 down the compiler, since there are more pseudos */
5442 subtarget = (!optimize
5446 /* For floating-point comparisons, try the reverse comparison or try
5447 changing the "orderedness" of the comparison. */
5449 {
5458 {
5462 /* For the reverse comparison, use either an addition or a XOR. */
5466 {
5473 }
5477 {
5483 }
5484 }
5488 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5494 /* If there are no NaNs, the first comparison should always fall through.
5495 Effectively change the comparison to the other one. */
5497 {
5500 target_mode);
5501 }
5503 #ifdef HAVE_conditional_move
5504 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5505 conditional move. */
5514 else
5521 #else
5523 #endif
5524 }
5526 /* The remaining tricks only apply to integer comparisons. */
5531 /* If this is an equality comparison of integers, we can try to exclusive-or
5532 (or subtract) the two operands and use a recursive call to try the
5533 comparison with zero. Don't do any of these cases if branches are
5534 very cheap. */
5537 {
5539 OPTAB_WIDEN);
5543 OPTAB_WIDEN);
5551 }
5553 /* For integer comparisons, try the reverse comparison. However, for
5554 small X and if we'd have anyway to extend, implementing "X != 0"
5555 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5562 {
5566 /* Again, for the reverse comparison, use either an addition or a XOR. */
5570 {
5577 }
5581 {
5587 }
5592 }
5594 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5595 the constant zero. Reject all other comparisons at this point. Only
5596 do LE and GT if branches are expensive since they are expensive on
5597 2-operand machines. */
5605 /* Try to put the result of the comparison in the sign bit. Assume we can't
5606 do the necessary operation below. */
5610 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5611 the sign bit set. */
5614 {
5615 /* This is destructive, so SUBTARGET can't be OP0. */
5620 OPTAB_WIDEN);
5623 OPTAB_WIDEN);
5624 }
5626 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5627 number of bits in the mode of OP0, minus one. */
5630 {
5638 OPTAB_WIDEN);
5639 }
5642 {
5643 /* For EQ or NE, one way to do the comparison is to apply an operation
5644 that converts the operand into a positive number if it is nonzero
5645 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5646 for NE we negate. This puts the result in the sign bit. Then we
5647 normalize with a shift, if needed.
5649 Two operations that can do the above actions are ABS and FFS, so try
5650 them. If that doesn't work, and MODE is smaller than a full word,
5651 we can use zero-extension to the wider mode (an unsigned conversion)
5652 as the operation. */
5654 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5655 that is compensated by the subsequent overflow when subtracting
5656 one / negating. */
5663 {
5666 }
5669 {
5673 else
5675 }
5677 /* If we couldn't do it that way, for NE we can "or" the two's complement
5678 of the value with itself. For EQ, we take the one's complement of
5679 that "or", which is an extra insn, so we only handle EQ if branches
5680 are expensive. */
5686 {
5692 OPTAB_WIDEN);
5696 }
5697 }
5705 {
5707 ;
5709 {
5712 }
5714 {
5717 }
5718 }
5719 else
5723 }
5725 /* Like emit_store_flag, but always succeeds. */
5727 rtx
5730 {
5731 rtx tem;
5735 /* First see if emit_store_flag can do the job. */
5743 /* If this failed, we have to do this with set/compare/jump/set code.
5744 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5751 {
5758 }
5764 /* Jump in the right direction if the target cannot implement CODE
5765 but can jump on its reverse condition. */
5772 {
5776 else
5779 /* Canonicalize to UNORDERED for the libcall. */
5782 {
5786 }
5787 }
5798 }
5799 \f
5800 /* Perform possibly multi-word comparison and conditional jump to LABEL
5801 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5802 now a thin wrapper around do_compare_rtx_and_jump. */
5804 static void
5807 {
5811 }