| blob | e20e0592ca16048b9edaf98fe9ea9a3c1f1b8eb0 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
57 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
58 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
60 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
61 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
62 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
65 /* Vector mapping INSN_UIDs to luids.
66 The luids are like uids but increase monotonically always.
67 We use them to see whether a jump comes from outside a given loop. */
71 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
72 number the insn is contained in. */
76 /* 1 + largest uid of any insn. */
80 /* 1 + luid of last insn. */
84 /* Number of loops detected in current function. Used as index to the
85 next few tables. */
89 /* Bound on pseudo register number before loop optimization.
90 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
93 /* The value to pass to the next call of reg_scan_update. */
96 #define obstack_chunk_alloc xmalloc
97 #define obstack_chunk_free free
98 \f
99 /* During the analysis of a loop, a chain of `struct movable's
100 is made to record all the movable insns found.
101 Then the entire chain can be scanned to decide which to move. */
103 struct movable
104 {
109 of any registers used within the LIBCALL. */
111 that must be moved with this one. */
114 may be adjusted when matching movables
115 that load the same value are found. */
117 including other movables that force this
118 or match this one. */
122 /* If PARTIAL is 1, GLOBAL means something different:
123 that the reg is live outside the range from where it is set
124 to the following label. */
128 In particular, moving it does not make it
129 invariant. */
131 load SRC, rather than copying INSN. */
133 first insn of a consecutive sets group. */
136 that we should avoid changing when clearing
137 the rest of the reg. */
141 };
146 /* Forward declarations. */
160 #if 0
162 #endif
192 rtx *));
273 {
274 rtx r1;
275 rtx r2;
279 {
280 rtx match;
281 rtx replacement;
282 rtx insn;
285 /* Nonzero iff INSN is between START and END, inclusive. */
286 #define INSN_IN_RANGE_P(INSN, START, END) \
287 (INSN_UID (INSN) < max_uid_for_loop \
288 && INSN_LUID (INSN) >= INSN_LUID (START) \
289 && INSN_LUID (INSN) <= INSN_LUID (END))
291 /* Indirect_jump_in_function is computed once per function. */
299 rtx));
300 \f
301 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
302 copy the value of the strength reduced giv to its original register. */
305 /* Cost of using a register, to normalize the benefits of a giv. */
308 void
310 {
316 }
317 \f
318 /* Compute the mapping from uids to luids.
319 LUIDs are numbers assigned to insns, like uids,
320 except that luids increase monotonically through the code.
321 Start at insn START and stop just before END. Assign LUIDs
322 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
323 static int
327 {
329 rtx insn;
332 {
335 /* Don't assign luids to line-number NOTEs, so that the distance in
336 luids between two insns is not affected by -g. */
340 else
341 /* Give a line number note the same luid as preceding insn. */
343 }
345 }
346 \f
347 /* Entry point of this file. Perform loop optimization
348 on the current function. F is the first insn of the function
349 and DUMPFILE is a stream for output of a trace of actions taken
350 (or 0 if none should be output). */
352 void
354 /* f is the first instruction of a chain of insns for one function */
355 rtx f;
358 {
374 /* Count the number of loops. */
378 {
381 max_loop_num++;
382 }
384 /* Don't waste time if no loops. */
390 /* Get size to use for tables indexed by uids.
391 Leave some space for labels allocated by find_and_verify_loops. */
398 /* Allocate storage for array of loops. */
402 /* Find and process each loop.
403 First, find them, and record them in order of their beginnings. */
406 /* Allocate and initialize auxiliary loop information. */
411 /* Now find all register lifetimes. This must be done after
412 find_and_verify_loops, because it might reorder the insns in the
413 function. */
416 /* This must occur after reg_scan so that registers created by gcse
417 will have entries in the register tables.
419 We could have added a call to reg_scan after gcse_main in toplev.c,
420 but moving this call to init_alias_analysis is more efficient. */
423 /* See if we went too far. Note that get_max_uid already returns
424 one more that the maximum uid of all insn. */
427 /* Now reset it to the actual size we need. See above. */
430 /* find_and_verify_loops has already called compute_luids, but it
431 might have rearranged code afterwards, so we need to recompute
432 the luids now. */
435 /* Don't leave gaps in uid_luid for insns that have been
436 deleted. It is possible that the first or last insn
437 using some register has been deleted by cross-jumping.
438 Make sure that uid_luid for that former insn's uid
439 points to the general area where that insn used to be. */
441 {
445 }
450 /* Determine if the function has indirect jump. On some systems
451 this prevents low overhead loop instructions from being used. */
454 /* Now scan the loops, last ones first, since this means inner ones are done
455 before outer ones. */
457 {
462 }
464 /* If there were lexical blocks inside the loop, they have been
465 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
466 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
467 the BLOCKs as well. */
473 /* Clean up. */
478 }
479 \f
480 /* Returns the next insn, in execution order, after INSN. START and
481 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
482 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
483 insn-stream; it is used with loops that are entered near the
484 bottom. */
486 static rtx
489 rtx insn;
490 {
494 {
496 /* Go to the top of the loop, and continue there. */
498 else
499 /* We're done. */
501 }
504 /* We're done. */
508 }
510 /* Optimize one loop described by LOOP. */
512 /* ??? Could also move memory writes out of loops if the destination address
513 is invariant, the source is invariant, the memory write is not volatile,
514 and if we can prove that no read inside the loop can read this address
515 before the write occurs. If there is a read of this address after the
516 write, then we can also mark the memory read as invariant. */
518 static void
522 {
528 rtx p;
529 /* 1 if we are scanning insns that could be executed zero times. */
531 /* 1 if we are scanning insns that might never be executed
532 due to a subroutine call which might exit before they are reached. */
534 /* Jump insn that enters the loop, or 0 if control drops in. */
536 /* Number of insns in the loop. */
540 /* The SET from an insn, if it is the only SET in the insn. */
542 /* Chain describing insns movable in current loop. */
544 /* Ratio of extra register life span we can justify
545 for saving an instruction. More if loop doesn't call subroutines
546 since in that case saving an insn makes more difference
547 and more registers are available. */
549 /* Nonzero if we are scanning instructions in a sub-loop. */
557 /* Determine whether this loop starts with a jump down to a test at
558 the end. This will occur for a small number of loops with a test
559 that is too complex to duplicate in front of the loop.
561 We search for the first insn or label in the loop, skipping NOTEs.
562 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
563 (because we might have a loop executed only once that contains a
564 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
565 (in case we have a degenerate loop).
567 Note that if we mistakenly think that a loop is entered at the top
568 when, in fact, it is entered at the exit test, the only effect will be
569 slightly poorer optimization. Making the opposite error can generate
570 incorrect code. Since very few loops now start with a jump to the
571 exit test, the code here to detect that case is very conservative. */
574 p != loop_end
580 ;
584 /* If loop end is the end of the current function, then emit a
585 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
586 note insn. This is the position we use when sinking insns out of
587 the loop. */
590 else
593 /* Set up variables describing this loop. */
597 /* If loop has a jump before the first label,
598 the true entry is the target of that jump.
599 Start scan from there.
600 But record in LOOP->TOP the place where the end-test jumps
601 back to so we can scan that after the end of the loop. */
603 {
606 /* Loop entry must be unconditional jump (and not a RETURN) */
609 /* Check to see whether the jump actually
610 jumps out of the loop (meaning it's no loop).
611 This case can happen for things like
612 do {..} while (0). If this label was generated previously
613 by loop, we can't tell anything about it and have to reject
614 the loop. */
616 {
619 }
620 }
622 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
623 as required by loop_reg_used_before_p. So skip such loops. (This
624 test may never be true, but it's best to play it safe.)
626 Also, skip loops where we do not start scanning at a label. This
627 test also rejects loops starting with a JUMP_INSN that failed the
628 test above. */
632 {
637 }
639 /* Allocate extra space for REGs that might be created by load_mems.
640 We allocate a little extra slop as well, in the hopes that we
641 won't have to reallocate the regs array. */
646 {
652 }
654 /* Scan through the loop finding insns that are safe to move.
655 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
656 this reg will be considered invariant for subsequent insns.
657 We consider whether subsequent insns use the reg
658 in deciding whether it is worth actually moving.
660 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
661 and therefore it is possible that the insns we are scanning
662 would never be executed. At such times, we must make sure
663 that it is safe to execute the insn once instead of zero times.
664 When MAYBE_NEVER is 0, all insns will be executed at least once
665 so that is not a problem. */
670 {
675 {
682 /* Figure out what to use as a source of this insn. If a REG_EQUIV
683 note is given or if a REG_EQUAL note with a constant operand is
684 specified, use it as the source and mark that we should move
685 this insn by calling emit_move_insn rather that duplicating the
686 insn.
688 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
689 is present. */
693 else
694 {
699 {
701 /* A libcall block can use regs that don't appear in
702 the equivalent expression. To move the libcall,
703 we must move those regs too. */
705 }
706 }
708 /* For parallels, add any possible uses to the depencies, as we can't move
709 the insn without resolving them first. */
711 {
713 {
717 }
718 }
720 /* Don't try to optimize a register that was made
721 by loop-optimization for an inner loop.
722 We don't know its life-span, so we can't compute the benefit. */
724 ;
726 than the one where it is set (meaning that
727 something after this point in the loop might
728 depend on its value before the set). */
730 /* And the set is not guaranteed to be executed once
731 the loop starts, or the value before the set is
732 needed before the set occurs...
734 ??? Note we have quadratic behaviour here, mitigated
735 by the fact that the previous test will often fail for
736 large loops. Rather than re-scanning the entire loop
737 each time for register usage, we should build tables
738 of the register usage and use them here instead. */
739 && (maybe_never
741 /* It is unsafe to move the set.
743 This code used to consider it OK to move a set of a variable
744 which was not created by the user and not used in an exit test.
745 That behavior is incorrect and was removed. */
746 ;
751 || (tem1
752 = consec_sets_invariant_p
755 p)))
756 /* If the insn can cause a trap (such as divide by zero),
757 can't move it unless it's guaranteed to be executed
758 once loop is entered. Even a function call might
759 prevent the trap insn from being reached
760 (since it might exit!) */
763 {
767 /* A potential lossage is where we have a case where two insns
768 can be combined as long as they are both in the loop, but
769 we move one of them outside the loop. For large loops,
770 this can lose. The most common case of this is the address
771 of a function being called.
773 Therefore, if this register is marked as being used exactly
774 once if we are in a loop with calls (a "large loop"), see if
775 we can replace the usage of this register with the source
776 of this SET. If we can, delete this insn.
778 Don't do this if P has a REG_RETVAL note or if we have
779 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
791 && (! SMALL_REGISTER_CLASSES
794 /* This test is not redundant; SET_SRC (set) might be
795 a call-clobbered register and the life of REGNO
796 might span a call. */
802 {
803 /* Replace any usage in a REG_EQUAL note. Must copy the
804 new source, so that we don't get rtx sharing between the
805 SET_SOURCE and REG_NOTES of insn p. */
815 }
833 /* Set M->cond if either loop_invariant_p
834 or consec_sets_invariant_p returned 2
835 (only conditionally invariant). */
844 /* Add M to the end of the chain MOVABLES. */
848 {
849 /* It is possible for the first instruction to have a
850 REG_EQUAL note but a non-invariant SET_SRC, so we must
851 remember the status of the first instruction in case
852 the last instruction doesn't have a REG_EQUAL note. */
855 /* Skip this insn, not checking REG_LIBCALL notes. */
857 /* Skip the consecutive insns, if there are any. */
859 /* Back up to the last insn of the consecutive group. */
862 /* We must now reset m->move_insn, m->is_equiv, and possibly
863 m->set_src to correspond to the effects of all the
864 insns. */
868 else
869 {
873 else
876 }
878 }
879 }
880 /* If this register is always set within a STRICT_LOW_PART
881 or set to zero, then its high bytes are constant.
882 So clear them outside the loop and within the loop
883 just load the low bytes.
884 We must check that the machine has an instruction to do so.
885 Also, if the value loaded into the register
886 depends on the same register, this cannot be done. */
896 {
899 {
913 /* If the insn may not be executed on some cycles,
914 we can't clear the whole reg; clear just high part.
915 Not even if the reg is used only within this loop.
916 Consider this:
917 while (1)
918 while (s != t) {
919 if (foo ()) x = *s;
920 use (x);
921 }
922 Clearing x before the inner loop could clobber a value
923 being saved from the last time around the outer loop.
924 However, if the reg is not used outside this loop
925 and all uses of the register are in the same
926 basic block as the store, there is no problem.
928 If this insn was made by loop, we don't know its
929 INSN_LUID and hence must make a conservative
930 assumption. */
933 || (labels_in_range_p
937 else
945 /* Add M to the end of the chain MOVABLES. */
947 }
948 }
949 }
950 /* Past a call insn, we get to insns which might not be executed
951 because the call might exit. This matters for insns that trap.
952 Constant and pure call insns always return, so they don't count. */
955 /* Past a label or a jump, we get to insns for which we
956 can't count on whether or how many times they will be
957 executed during each iteration. Therefore, we can
958 only move out sets of trivial variables
959 (those not used after the loop). */
960 /* Similar code appears twice in strength_reduce. */
962 /* If we enter the loop in the middle, and scan around to the
963 beginning, don't set maybe_never for that. This must be an
964 unconditional jump, otherwise the code at the top of the
965 loop might never be executed. Unconditional jumps are
966 followed by a barrier then the loop_end. */
972 {
973 /* At the virtual top of a converted loop, insns are again known to
974 be executed: logically, the loop begins here even though the exit
975 code has been duplicated. */
979 loop_depth++;
981 loop_depth--;
982 }
983 }
985 /* If one movable subsumes another, ignore that other. */
989 /* For each movable insn, see if the reg that it loads
990 leads when it dies right into another conditionally movable insn.
991 If so, record that the second insn "forces" the first one,
992 since the second can be moved only if the first is. */
996 /* See if there are multiple movable insns that load the same value.
997 If there are, make all but the first point at the first one
998 through the `match' field, and add the priorities of them
999 all together as the priority of the first. */
1003 /* Now consider each movable insn to decide whether it is worth moving.
1004 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1006 Generally this increases code size, so do not move moveables when
1007 optimizing for code size. */
1012 /* Now candidates that still are negative are those not moved.
1013 Change regs->array[I].set_in_loop to indicate that those are not actually
1014 invariant. */
1019 /* Now that we've moved some things out of the loop, we might be able to
1020 hoist even more memory references. */
1023 /* Recalculate regs->array if load_mems has created new registers. */
1031 ;
1038 {
1040 /* Ensure our label doesn't go away. */
1051 }
1054 /* The movable information is required for strength reduction. */
1060 }
1061 \f
1062 /* Add elements to *OUTPUT to record all the pseudo-regs
1063 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1065 void
1069 {
1077 {
1095 }
1099 {
1103 {
1112 }
1113 }
1114 }
1115 \f
1116 /* Check what regs are referred to in the libcall block ending with INSN,
1117 aside from those mentioned in the equivalent value.
1118 If there are none, return 0.
1119 If there are one or more, return an EXPR_LIST containing all of them. */
1121 rtx
1124 {
1129 /* First, find all the regs used in the libcall block
1130 that are not mentioned as inputs to the result. */
1133 {
1138 }
1141 }
1142 \f
1143 /* Return 1 if all uses of REG
1144 are between INSN and the end of the basic block. */
1146 static int
1149 {
1151 rtx p;
1156 /* Search this basic block for the already recorded last use of the reg. */
1158 {
1160 {
1166 /* Ordinary insn: if this is the last use, we win. */
1172 /* Jump insn: if this is the last use, we win. */
1175 /* Otherwise, it's the end of the basic block, so we lose. */
1180 /* It's the end of the basic block, so we lose. */
1185 }
1186 }
1188 /* The "last use" that was recorded can't be found after the first
1189 use. This can happen when the last use was deleted while
1190 processing an inner loop, this inner loop was then completely
1191 unrolled, and the outer loop is always exited after the inner loop,
1192 so that everything after the first use becomes a single basic block. */
1194 }
1195 \f
1196 /* Compute the benefit of eliminating the insns in the block whose
1197 last insn is LAST. This may be a group of insns used to compute a
1198 value directly or can contain a library call. */
1200 static int
1202 rtx last;
1203 {
1204 rtx insn;
1209 {
1212 routine. */
1216 benefit++;
1217 }
1220 }
1221 \f
1222 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1224 static rtx
1226 rtx insn;
1228 {
1230 {
1231 rtx temp;
1233 /* If first insn of libcall sequence, skip to end. */
1234 /* Do this at start of loop, since INSN is guaranteed to
1235 be an insn here. */
1240 do
1243 }
1246 }
1248 /* Ignore any movable whose insn falls within a libcall
1249 which is part of another movable.
1250 We make use of the fact that the movable for the libcall value
1251 was made later and so appears later on the chain. */
1253 static void
1256 {
1260 {
1261 /* Is this a movable for the value of a libcall? */
1264 {
1265 rtx insn;
1266 /* Check for earlier movables inside that range,
1267 and mark them invalid. We cannot use LUIDs here because
1268 insns created by loop.c for prior loops don't have LUIDs.
1269 Rather than reject all such insns from movables, we just
1270 explicitly check each insn in the libcall (since invariant
1271 libcalls aren't that common). */
1276 }
1277 }
1278 }
1280 /* For each movable insn, see if the reg that it loads
1281 leads when it dies right into another conditionally movable insn.
1282 If so, record that the second insn "forces" the first one,
1283 since the second can be moved only if the first is. */
1285 static void
1288 {
1291 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1293 {
1296 /* ??? Could this be a bug? What if CSE caused the
1297 register of M1 to be used after this insn?
1298 Since CSE does not update regno_last_uid,
1299 this insn M->insn might not be where it dies.
1300 But very likely this doesn't matter; what matters is
1301 that M's reg is computed from M1's reg. */
1306 /* If m->consec, m->set_src isn't valid. */
1310 /* Increase the priority of the moving the first insn
1311 since it permits the second to be moved as well. */
1313 {
1317 }
1318 }
1319 }
1320 \f
1321 /* Find invariant expressions that are equal and can be combined into
1322 one register. */
1324 static void
1328 {
1333 /* Regs that are set more than once are not allowed to match
1334 or be matched. I'm no longer sure why not. */
1335 /* Perhaps testing m->consec_sets would be more appropriate here? */
1340 {
1347 /* We want later insns to match the first one. Don't make the first
1348 one match any later ones. So start this loop at m->next. */
1352 /* A reg used outside the loop mustn't be eliminated. */
1354 /* A reg used for zero-extending mustn't be eliminated. */
1357 ||
1358 (
1359 /* Can combine regs with different modes loaded from the
1360 same constant only if the modes are the same or
1361 if both are integer modes with M wider or the same
1362 width as M1. The check for integer is redundant, but
1363 safe, since the only case of differing destination
1364 modes with equal sources is when both sources are
1365 VOIDmode, i.e., CONST_INT. */
1371 /* See if the source of M1 says it matches M. */
1378 {
1384 }
1385 }
1387 /* Now combine the regs used for zero-extension.
1388 This can be done for those not marked `global'
1389 provided their lives don't overlap. */
1393 {
1396 /* Combine all the registers for extension from mode MODE.
1397 Don't combine any that are used outside this loop. */
1401 {
1407 {
1408 /* First one: don't check for overlap, just record it. */
1411 }
1413 /* Make sure they extend to the same mode.
1414 (Almost always true.) */
1418 /* We already have one: check for overlap with those
1419 already combined together. */
1426 /* No overlap: we can combine this with the others. */
1432 overlap:
1433 ;
1434 }
1435 }
1437 /* Clean up. */
1439 }
1441 /* Returns the number of movable instructions in LOOP that were not
1442 moved outside the loop. */
1444 static int
1447 {
1456 }
1458 \f
1459 /* Return 1 if regs X and Y will become the same if moved. */
1461 static int
1465 {
1482 }
1484 /* Return 1 if X and Y are identical-looking rtx's.
1485 This is the Lisp function EQUAL for rtx arguments.
1487 If two registers are matching movables or a movable register and an
1488 equivalent constant, consider them equal. */
1490 static int
1495 {
1509 /* If we have a register and a constant, they may sometimes be
1510 equal. */
1513 {
1518 }
1521 {
1526 }
1528 /* Otherwise, rtx's of different codes cannot be equal. */
1532 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1533 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1538 /* These three types of rtx's can be compared nonrecursively. */
1547 /* Compare the elements. If any pair of corresponding elements
1548 fail to match, return 0 for the whole things. */
1552 {
1554 {
1566 /* Two vectors must have the same length. */
1570 /* And the corresponding elements must match. */
1589 /* These are just backpointers, so they don't matter. */
1595 /* It is believed that rtx's at this level will never
1596 contain anything but integers and other rtx's,
1597 except for within LABEL_REFs and SYMBOL_REFs. */
1600 }
1601 }
1603 }
1604 \f
1605 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1606 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1607 references is incremented once for each added note. */
1609 static void
1611 rtx x;
1612 rtx insns;
1613 {
1617 rtx insn;
1620 {
1621 /* This code used to ignore labels that referred to dispatch tables to
1622 avoid flow generating (slighly) worse code.
1624 We no longer ignore such label references (see LABEL_REF handling in
1625 mark_jump_label for additional information). */
1628 {
1633 }
1634 }
1638 {
1644 }
1645 }
1646 \f
1647 /* Scan MOVABLES, and move the insns that deserve to be moved.
1648 If two matching movables are combined, replace one reg with the
1649 other throughout. */
1651 static void
1657 {
1665 /* Map of pseudo-register replacements to handle combining
1666 when we move several insns that load the same value
1667 into different pseudo-registers. */
1672 {
1673 /* Describe this movable insn. */
1676 {
1697 }
1699 /* Ignore the insn if it's already done (it matched something else).
1700 Otherwise, see if it is now safe to move. */
1712 {
1717 /* We have an insn that is safe to move.
1718 Compute its desirability. */
1729 /* An insn MUST be moved if we already moved something else
1730 which is safe only if this one is moved too: that is,
1731 if already_moved[REGNO] is nonzero. */
1733 /* An insn is desirable to move if the new lifetime of the
1734 register is no more than THRESHOLD times the old lifetime.
1735 If it's not desirable, it means the loop is so big
1736 that moving won't speed things up much,
1737 and it is liable to make register usage worse. */
1739 /* It is also desirable to move if it can be moved at no
1740 extra cost because something else was already moved. */
1743 || flag_move_all_movables
1748 {
1753 /* Now move the insns that set the reg. */
1756 {
1759 /* Find the end of this chain of matching regs.
1760 Thus, we load each reg in the chain from that one reg.
1761 And that reg is loaded with 0 directly,
1762 since it has ->match == 0. */
1768 /* Mark the moved, invariant reg as being allowed to
1769 share a hard reg with the other matching invariant. */
1773 regs_may_share
1776 regs_may_share));
1784 }
1785 /* If we are to re-generate the item being moved with a
1786 new move insn, first delete what we have and then emit
1787 the move insn before the loop. */
1789 {
1793 {
1794 /* If this is the first insn of a library call sequence,
1795 skip to the end. */
1800 /* If this is the last insn of a libcall sequence, then
1801 delete every insn in the sequence except the last.
1802 The last insn is handled in the normal manner. */
1805 {
1809 }
1814 /* simplify_giv_expr expects that it can walk the insns
1815 at m->insn forwards and see this old sequence we are
1816 tossing here. delete_insn does preserve the next
1817 pointers, but when we skip over a NOTE we must fix
1818 it up. Otherwise that code walks into the non-deleted
1819 insn stream. */
1822 }
1841 /* The more regs we move, the less we like moving them. */
1843 }
1844 else
1845 {
1847 {
1850 /* If first insn of libcall sequence, skip to end. */
1851 /* Do this at start of loop, since p is guaranteed to
1852 be an insn here. */
1857 /* If last insn of libcall sequence, move all
1858 insns except the last before the loop. The last
1859 insn is handled in the normal manner. */
1862 {
1870 {
1871 rtx body;
1872 rtx n;
1873 rtx next;
1880 /* Find the next insn after TEMP,
1881 not counting USE or NOTE insns. */
1889 /* If that is the call, this may be the insn
1890 that loads the function address.
1892 Extract the function address from the insn
1893 that loads it into a register.
1894 If this insn was cse'd, we get incorrect code.
1896 So emit a new move insn that copies the
1897 function address into the register that the
1898 call insn will use. flow.c will delete any
1899 redundant stores that we have created. */
1904 NULL_RTX)))
1905 {
1911 }
1912 /* We have the call insn.
1913 If it uses the register we suspect it might,
1914 load it with the correct address directly. */
1919 gen_move_insn
1923 {
1925 /* Because the USAGE information potentially
1926 contains objects other than hard registers
1927 we need to copy it. */
1931 }
1932 else
1940 }
1943 }
1945 {
1946 /* P sets REG to zero; but we should clear only
1947 the bits that are not covered by the mode
1948 m->savemode. */
1950 rtx sequence;
1951 rtx tem;
1954 tem = expand_simple_binop
1967 }
1969 {
1971 /* Because the USAGE information potentially
1972 contains objects other than hard registers
1973 we need to copy it. */
1977 }
1979 {
1980 rtx seq;
1981 /* The SET_SRC might not be invariant, so we must
1982 use the REG_EQUAL note. */
1997 }
1998 else
2002 {
2005 /* If there is a REG_EQUAL note present whose value
2006 is not loop invariant, then delete it, since it
2007 may cause problems with later optimization passes.
2008 It is possible for cse to create such notes
2009 like this as a result of record_jump_cond. */
2014 }
2023 /* If library call, now fix the REG_NOTES that contain
2024 insn pointers, namely REG_LIBCALL on FIRST
2025 and REG_RETVAL on I1. */
2027 {
2031 }
2037 /* simplify_giv_expr expects that it can walk the insns
2038 at m->insn forwards and see this old sequence we are
2039 tossing here. delete_insn does preserve the next
2040 pointers, but when we skip over a NOTE we must fix
2041 it up. Otherwise that code walks into the non-deleted
2042 insn stream. */
2045 }
2047 /* The more regs we move, the less we like moving them. */
2049 }
2051 /* Any other movable that loads the same register
2052 MUST be moved. */
2055 /* This reg has been moved out of one loop. */
2058 /* The reg set here is now invariant. */
2064 /* Change the length-of-life info for the register
2065 to say it lives at least the full length of this loop.
2066 This will help guide optimizations in outer loops. */
2069 /* This is the old insn before all the moved insns.
2070 We can't use the moved insn because it is out of range
2071 in uid_luid. Only the old insns have luids. */
2076 /* Combine with this moved insn any other matching movables. */
2081 {
2082 rtx temp;
2084 /* Schedule the reg loaded by M1
2085 for replacement so that shares the reg of M.
2086 If the modes differ (only possible in restricted
2087 circumstances, make a SUBREG.
2089 Note this assumes that the target dependent files
2090 treat REG and SUBREG equally, including within
2091 GO_IF_LEGITIMATE_ADDRESS and in all the
2092 predicates since we never verify that replacing the
2093 original register with a SUBREG results in a
2094 recognizable insn. */
2097 else
2102 /* Get rid of the matching insn
2103 and prevent further processing of it. */
2106 /* if library call, delete all insn except last, which
2107 is deleted below */
2109 NULL_RTX)))
2110 {
2114 }
2117 /* Any other movable that loads the same register
2118 MUST be moved. */
2121 /* The reg merged here is now invariant,
2122 if the reg it matches is invariant. */
2125 }
2126 }
2129 }
2135 }
2140 /* Go through all the instructions in the loop, making
2141 all the register substitutions scheduled in REG_MAP. */
2145 {
2149 }
2151 /* Clean up. */
2154 }
2157 static void
2161 {
2164 else
2167 }
2170 static void
2173 {
2178 {
2181 }
2182 }
2183 \f
2184 #if 0
2185 /* Scan X and replace the address of any MEM in it with ADDR.
2186 REG is the address that MEM should have before the replacement. */
2188 static void
2191 {
2200 {
2212 /* Short cut for very common case. */
2217 /* Short cut for very common case. */
2222 /* If this MEM uses a reg other than the one we expected,
2223 something is wrong. */
2231 }
2235 {
2239 {
2243 }
2244 }
2245 }
2246 #endif
2247 \f
2248 /* Return the number of memory refs to addresses that vary
2249 in the rtx X. */
2251 static int
2254 rtx x;
2255 {
2266 {
2283 }
2288 {
2292 {
2296 }
2297 }
2299 }
2300 \f
2301 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2302 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2303 `unknown_address_altered', `unknown_constant_address_altered', and
2304 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2305 list `store_mems' in LOOP. */
2307 static void
2310 {
2312 rtx insn;
2316 /* The label after END. Jumping here is just like falling off the
2317 end of the loop. We use next_nonnote_insn instead of next_label
2318 as a hedge against the (pathological) case where some actual insn
2319 might end up between the two. */
2341 {
2343 {
2346 }
2347 }
2351 {
2353 {
2355 {
2357 /* Count number of loops contained in this one. */
2359 }
2361 {
2363 }
2364 }
2366 {
2368 {
2371 }
2373 }
2375 {
2395 {
2397 {
2400 }
2401 else
2402 {
2404 }
2406 do
2407 {
2409 {
2411 {
2412 /* Something tricky. */
2415 }
2418 {
2419 /* A jump outside the current loop. */
2422 }
2423 }
2427 }
2429 }
2430 }
2433 }
2435 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2437 anywhere. */
2439 /* We don't want loads for MEMs moved to a location before the
2440 one at which their stack memory becomes allocated. (Note
2441 that this is not a problem for malloc, etc., since those
2442 require actual function calls. */
2443 && ! current_function_calls_alloca
2444 /* There are ways to leave the loop other than falling off the
2445 end. */
2451 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2452 that loop_invariant_p and load_mems can use true_dependence
2453 to determine what is really clobbered. */
2455 {
2458 loop_info->store_mems
2460 }
2462 {
2466 loop_info->store_mems
2468 }
2469 }
2470 \f
2471 /* Scan the function looking for loops. Record the start and end of each loop.
2472 Also mark as invalid loops any loops that contain a setjmp or are branched
2473 to from outside the loop. */
2475 static void
2477 rtx f;
2479 {
2480 rtx insn;
2481 rtx label;
2491 /* If there are jumps to undefined labels,
2492 treat them as jumps out of any/all loops.
2493 This also avoids writing past end of tables when there are no loops. */
2496 /* Find boundaries of loops, mark which loops are contained within
2497 loops, and invalidate loops that have setjmp. */
2502 {
2505 {
2509 num_loops++;
2533 }
2537 {
2538 /* In this case, we must invalidate our current loop and any
2539 enclosing loop. */
2541 {
2547 }
2548 }
2550 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2551 enclosing loop, but this doesn't matter. */
2553 }
2555 /* Any loop containing a label used in an initializer must be invalidated,
2556 because it can be jumped into from anywhere. */
2559 {
2563 }
2565 /* Any loop containing a label used for an exception handler must be
2566 invalidated, because it can be jumped into from anywhere. */
2569 {
2573 }
2575 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2576 loop that it is not contained within, that loop is marked invalid.
2577 If any INSN or CALL_INSN uses a label's address, then the loop containing
2578 that label is marked invalid, because it could be jumped into from
2579 anywhere.
2581 Also look for blocks of code ending in an unconditional branch that
2582 exits the loop. If such a block is surrounded by a conditional
2583 branch around the block, move the block elsewhere (see below) and
2584 invert the jump to point to the code block. This may eliminate a
2585 label in our loop and will simplify processing by both us and a
2586 possible second cse pass. */
2590 {
2594 {
2597 {
2601 }
2602 }
2609 /* See if this is an unconditional branch outside the loop. */
2617 {
2618 rtx p;
2624 /* Go backwards until we reach the start of the loop, a label,
2625 or a JUMP_INSN. */
2632 ;
2634 /* Check for the case where we have a jump to an inner nested
2635 loop, and do not perform the optimization in that case. */
2638 {
2641 {
2646 }
2647 }
2649 /* Make sure that the target of P is within the current loop. */
2655 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2656 we have a block of code to try to move.
2658 We look backward and then forward from the target of INSN
2659 to find a BARRIER at the same loop depth as the target.
2660 If we find such a BARRIER, we make a new label for the start
2661 of the block, invert the jump in P and point it to that label,
2662 and move the block of code to the spot we found. */
2667 /* Just ignore jumps to labels that were never emitted.
2668 These always indicate compilation errors. */
2672 /* If it's not safe to move the sequence, then we
2673 mustn't try. */
2676 {
2677 rtx target
2681 rtx tmp;
2683 /* Search for possible garbage past the conditional jumps
2684 and look for the last barrier. */
2692 /* Don't move things inside a tablejump. */
2705 /* Don't move things inside a tablejump. */
2716 {
2720 /* Ensure our label doesn't go away. */
2723 /* Verify that uid_loop is large enough and that
2724 we can invert P. */
2726 {
2729 /* If no suitable BARRIER was found, create a suitable
2730 one before TARGET. Since TARGET is a fall through
2731 path, we'll need to insert an jump around our block
2732 and a add a BARRIER before TARGET.
2734 This creates an extra unconditional jump outside
2735 the loop. However, the benefits of removing rarely
2736 executed instructions from inside the loop usually
2737 outweighs the cost of the extra unconditional jump
2738 outside the loop. */
2740 {
2741 rtx temp;
2748 }
2750 /* Include the BARRIER after INSN and copy the
2751 block after LOC. */
2755 /* All those insns are now in TARGET_LOOP. */
2761 /* The label jumped to by INSN is no longer a loop
2762 exit. Unless INSN does not have a label (e.g.,
2763 it is a RETURN insn), search loop->exit_labels
2764 to find its label_ref, and remove it. Also turn
2765 off LABEL_OUTSIDE_LOOP_P bit. */
2767 {
2769 r;
2772 {
2776 else
2779 }
2785 /* If we didn't find it, then something is
2786 wrong. */
2789 }
2791 /* P is now a jump outside the loop, so it must be put
2792 in loop->exit_labels, and marked as such.
2793 The easiest way to do this is to just call
2794 mark_loop_jump again for P. */
2797 /* If INSN now jumps to the insn after it,
2798 delete INSN. */
2803 }
2805 /* Continue the loop after where the conditional
2806 branch used to jump, since the only branch insn
2807 in the block (if it still remains) is an inter-loop
2808 branch and hence needs no processing. */
2814 /* This loop will be continued with NEXT_INSN (insn). */
2816 }
2817 }
2818 }
2819 }
2820 }
2822 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2823 loops it is contained in, mark the target loop invalid.
2825 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2827 static void
2829 rtx x;
2831 {
2837 {
2849 /* There could be a label reference in here. */
2861 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2873 /* Link together all labels that branch outside the loop. This
2874 is used by final_[bg]iv_value and the loop unrolling code. Also
2875 mark this LABEL_REF so we know that this branch should predict
2876 false. */
2878 /* A check to make sure the label is not in an inner nested loop,
2879 since this does not count as a loop exit. */
2881 {
2886 }
2887 else
2891 {
2900 }
2902 /* If this is inside a loop, but not in the current loop or one enclosed
2903 by it, it invalidates at least one loop. */
2908 /* We must invalidate every nested loop containing the target of this
2909 label, except those that also contain the jump insn. */
2912 {
2913 /* Stop when we reach a loop that also contains the jump insn. */
2918 /* If we get here, we know we need to invalidate a loop. */
2925 }
2929 /* If this is not setting pc, ignore. */
2951 /* Strictly speaking this is not a jump into the loop, only a possible
2952 jump out of the loop. However, we have no way to link the destination
2953 of this jump onto the list of exit labels. To be safe we mark this
2954 loop and any containing loops as invalid. */
2956 {
2958 {
2964 }
2965 }
2967 }
2968 }
2969 \f
2970 /* Return nonzero if there is a label in the range from
2971 insn INSN to and including the insn whose luid is END
2972 INSN must have an assigned luid (i.e., it must not have
2973 been previously created by loop.c). */
2975 static int
2977 rtx insn;
2979 {
2981 {
2985 }
2988 }
2990 /* Record that a memory reference X is being set. */
2992 static void
2994 rtx x;
2995 rtx y ATTRIBUTE_UNUSED;
2997 {
3003 /* Count number of memory writes.
3004 This affects heuristics in strength_reduce. */
3007 /* BLKmode MEM means all memory is clobbered. */
3009 {
3012 else
3016 }
3020 }
3022 /* X is a value modified by an INSN that references a biv inside a loop
3023 exit test (ie, X is somehow related to the value of the biv). If X
3024 is a pseudo that is used more than once, then the biv is (effectively)
3025 used more than once. DATA is a pointer to a loop_regs structure. */
3027 static void
3029 rtx x;
3030 rtx y ATTRIBUTE_UNUSED;
3032 {
3047 /* If we do not have usage information, or if we know the register
3048 is used more than once, note that fact for check_dbra_loop. */
3053 }
3054 \f
3055 /* Return nonzero if the rtx X is invariant over the current loop.
3057 The value is 2 if we refer to something only conditionally invariant.
3059 A memory ref is invariant if it is not volatile and does not conflict
3060 with anything stored in `loop_info->store_mems'. */
3062 int
3066 {
3073 rtx mem_list_entry;
3079 {
3087 /* A LABEL_REF is normally invariant, however, if we are unrolling
3088 loops, and this label is inside the loop, then it isn't invariant.
3089 This is because each unrolled copy of the loop body will have
3090 a copy of this label. If this was invariant, then an insn loading
3091 the address of this label into a register might get moved outside
3092 the loop, and then each loop body would end up using the same label.
3094 We don't know the loop bounds here though, so just fail for all
3095 labels. */
3098 else
3107 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3108 since the reg might be set by initialization within the loop. */
3125 /* Volatile memory references must be rejected. Do this before
3126 checking for read-only items, so that volatile read-only items
3127 will be rejected also. */
3131 /* See if there is any dependence between a store and this load. */
3134 {
3140 }
3142 /* It's not invalidated by a store in memory
3143 but we must still verify the address is invariant. */
3147 /* Don't mess with insns declared volatile. */
3154 }
3158 {
3160 {
3166 }
3168 {
3171 {
3177 }
3179 }
3180 }
3183 }
3184 \f
3185 /* Return nonzero if all the insns in the loop that set REG
3186 are INSN and the immediately following insns,
3187 and if each of those insns sets REG in an invariant way
3188 (not counting uses of REG in them).
3190 The value is 2 if some of these insns are only conditionally invariant.
3192 We assume that INSN itself is the first set of REG
3193 and that its source is invariant. */
3195 static int
3200 {
3204 rtx temp;
3205 /* Number of sets we have to insist on finding after INSN. */
3211 /* If N_SETS hit the limit, we can't rely on its value. */
3218 {
3220 rtx set;
3225 /* If library call, skip to end of it. */
3234 {
3239 {
3240 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3241 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3242 notes are OK. */
3248 }
3249 }
3251 count--;
3253 {
3256 }
3257 }
3260 /* If loop_invariant_p ever returned 2, we return 2. */
3262 }
3264 #if 0
3265 /* I don't think this condition is sufficient to allow INSN
3266 to be moved, so we no longer test it. */
3268 /* Return 1 if all insns in the basic block of INSN and following INSN
3269 that set REG are invariant according to TABLE. */
3271 static int
3275 {
3280 {
3289 {
3292 }
3293 }
3294 }
3296 \f
3297 /* Look at all uses (not sets) of registers in X. For each, if it is
3298 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3299 a different insn, set USAGE[REGNO] to const0_rtx. */
3301 static void
3304 rtx insn;
3305 rtx x;
3306 {
3318 {
3319 /* Don't count SET_DEST if it is a REG; otherwise count things
3320 in SET_DEST because if a register is partially modified, it won't
3321 show up as a potential movable so we don't care how USAGE is set
3322 for it. */
3326 }
3327 else
3329 {
3335 }
3336 }
3337 \f
3338 /* Count and record any set in X which is contained in INSN. Update
3339 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3340 in X. */
3342 static void
3347 {
3349 /* Don't move a reg that has an explicit clobber.
3350 It's not worth the pain to try to do it correctly. */
3354 {
3362 {
3364 /* If this is the first setting of this reg
3365 in current basic block, and it was set before,
3366 it must be set in two basic blocks, so it cannot
3367 be moved out of the loop. */
3371 /* If this is not first setting in current basic block,
3372 see if reg was used in between previous one and this.
3373 If so, neither one can be moved. */
3380 }
3381 }
3382 }
3383 \f
3384 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3385 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3386 contained in insn INSN is used by any insn that precedes INSN in
3387 cyclic order starting from the loop entry point.
3389 We don't want to use INSN_LUID here because if we restrict INSN to those
3390 that have a valid INSN_LUID, it means we cannot move an invariant out
3391 from an inner loop past two loops. */
3393 static int
3397 {
3399 rtx p;
3401 /* Scan forward checking for register usage. If we hit INSN, we
3402 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3404 {
3410 }
3413 }
3414 \f
3415 /* A "basic induction variable" or biv is a pseudo reg that is set
3416 (within this loop) only by incrementing or decrementing it. */
3417 /* A "general induction variable" or giv is a pseudo reg whose
3418 value is a linear function of a biv. */
3420 /* Bivs are recognized by `basic_induction_var';
3421 Givs by `general_induction_var'. */
3423 /* Communication with routines called via `note_stores'. */
3427 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3431 /* ??? Unfinished optimizations, and possible future optimizations,
3432 for the strength reduction code. */
3434 /* ??? The interaction of biv elimination, and recognition of 'constant'
3435 bivs, may cause problems. */
3437 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3438 performance problems.
3440 Perhaps don't eliminate things that can be combined with an addressing
3441 mode. Find all givs that have the same biv, mult_val, and add_val;
3442 then for each giv, check to see if its only use dies in a following
3443 memory address. If so, generate a new memory address and check to see
3444 if it is valid. If it is valid, then store the modified memory address,
3445 otherwise, mark the giv as not done so that it will get its own iv. */
3447 /* ??? Could try to optimize branches when it is known that a biv is always
3448 positive. */
3450 /* ??? When replace a biv in a compare insn, we should replace with closest
3451 giv so that an optimized branch can still be recognized by the combiner,
3452 e.g. the VAX acb insn. */
3454 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3455 was rerun in loop_optimize whenever a register was added or moved.
3456 Also, some of the optimizations could be a little less conservative. */
3457 \f
3458 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3459 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3460 callback.
3462 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3463 loop iteration except for the last one.
3465 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3466 loop iteration.
3467 */
3468 void
3471 loop_insn_callback fncall;
3472 {
3473 /* This is 1 if current insn is not executed at least once for every loop
3474 iteration. */
3479 rtx p;
3481 /* If loop_scan_start points to the loop exit test, we have to be wary of
3482 subversive use of gotos inside expression statements. */
3486 /* Scan through loop to find all possible bivs. */
3491 {
3494 /* Past CODE_LABEL, we get to insns that may be executed multiple
3495 times. The only way we can be sure that they can't is if every
3496 jump insn between here and the end of the loop either
3497 returns, exits the loop, is a jump to a location that is still
3498 behind the label, or is a jump to the loop start. */
3501 {
3507 {
3512 {
3515 else
3519 }
3527 {
3530 }
3531 }
3532 }
3534 /* Past a jump, we get to insns for which we can't count
3535 on whether they will be executed during each iteration. */
3536 /* This code appears twice in strength_reduce. There is also similar
3537 code in scan_loop. */
3539 /* If we enter the loop in the middle, and scan around to the
3540 beginning, don't set not_every_iteration for that.
3541 This can be any kind of jump, since we want to know if insns
3542 will be executed if the loop is executed. */
3547 {
3550 /* If this is a jump outside the loop, then it also doesn't
3551 matter. Check to see if the target of this branch is on the
3552 loop->exits_labels list. */
3560 }
3563 {
3564 /* At the virtual top of a converted loop, insns are again known to
3565 be executed each iteration: logically, the loop begins here
3566 even though the exit code has been duplicated.
3568 Insns are also again known to be executed each iteration at
3569 the LOOP_CONT note. */
3575 loop_depth++;
3577 loop_depth--;
3578 }
3580 /* Note if we pass a loop latch. If we do, then we can not clear
3581 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3582 a loop since a jump before the last CODE_LABEL may have started
3583 a new loop iteration.
3585 Note that LOOP_TOP is only set for rotated loops and we need
3586 this check for all loops, so compare against the CODE_LABEL
3587 which immediately follows LOOP_START. */
3592 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3593 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3594 or not an insn is known to be executed each iteration of the
3595 loop, whether or not any iterations are known to occur.
3597 Therefore, if we have just passed a label and have no more labels
3598 between here and the test insn of the loop, and we have not passed
3599 a jump to the top of the loop, then we know these insns will be
3600 executed each iteration. */
3603 && !past_loop_latch
3608 }
3609 }
3610 \f
3611 static void
3614 {
3617 /* Temporary list pointers for traversing ivs->list. */
3624 /* Scan ivs->list to remove all regs that proved not to be bivs.
3625 Make a sanity check against regs->n_times_set. */
3627 {
3629 /* Above happens if register modified by subreg, etc. */
3630 /* Make sure it is not recognized as a basic induction var: */
3632 /* If never incremented, it is invariant that we decided not to
3633 move. So leave it alone. */
3635 {
3646 }
3647 else
3648 {
3653 }
3654 }
3655 }
3658 /* Determine how BIVS are initialised by looking through pre-header
3659 extended basic block. */
3660 static void
3663 {
3665 /* Temporary list pointers for traversing ivs->list. */
3668 rtx p;
3670 /* Find initial value for each biv by searching backwards from loop_start,
3671 halting at first label. Also record any test condition. */
3675 {
3676 rtx test;
3686 /* Record any test of a biv that branches around the loop if no store
3687 between it and the start of loop. We only care about tests with
3688 constants and registers and only certain of those. */
3698 {
3699 /* If an NE test, we have an initial value! */
3701 {
3705 }
3706 else
3708 }
3709 }
3710 }
3713 /* Look at the each biv and see if we can say anything better about its
3714 initial value from any initializing insns set up above. (This is done
3715 in two passes to avoid missing SETs in a PARALLEL.) */
3716 static void
3719 {
3721 /* Temporary list pointers for traversing ivs->list. */
3726 {
3727 rtx src;
3728 rtx note;
3733 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3734 is a constant, use the value of that. */
3740 else
3753 {
3757 {
3760 }
3761 }
3762 /* If we can't make it a giv,
3763 let biv keep initial value of "itself". */
3766 }
3767 }
3770 /* Search the loop for general induction variables. */
3772 static void
3775 {
3777 }
3780 /* For each giv for which we still don't know whether or not it is
3781 replaceable, check to see if it is replaceable because its final value
3782 can be calculated. */
3784 static void
3787 {
3792 {
3798 }
3799 }
3802 /* Return non-zero if it is possible to eliminate the biv BL provided
3803 all givs are reduced. This is possible if either the reg is not
3804 used outside the loop, or we can compute what its final value will
3805 be. */
3807 static int
3813 {
3814 /* For architectures with a decrement_and_branch_until_zero insn,
3815 don't do this if we put a REG_NONNEG note on the endtest for this
3816 biv. */
3818 #ifdef HAVE_decrement_and_branch_until_zero
3820 {
3825 }
3826 #endif
3828 /* Check that biv is used outside loop or if it has a final value.
3829 Compare against bl->init_insn rather than loop->start. We aren't
3830 concerned with any uses of the biv between init_insn and
3831 loop->start since these won't be affected by the value of the biv
3832 elsewhere in the function, so long as init_insn doesn't use the
3833 biv itself. */
3844 {
3852 }
3854 }
3857 /* Reduce each giv of BL that we have decided to reduce. */
3859 static void
3863 {
3867 {
3870 {
3873 /* If the code for derived givs immediately below has already
3874 allocated a new_reg, we must keep it. */
3878 #ifdef AUTO_INC_DEC
3879 /* If the target has auto-increment addressing modes, and
3880 this is an address giv, then try to put the increment
3881 immediately after its use, so that flow can create an
3882 auto-increment addressing mode. */
3885 /* We don't handle reversed biv's because bl->biv->insn
3886 does not have a valid INSN_LUID. */
3890 {
3891 /* If other giv's have been combined with this one, then
3892 this will work only if all uses of the other giv's occur
3893 before this giv's insn. This is difficult to check.
3895 We simplify this by looking for the common case where
3896 there is one DEST_REG giv, and this giv's insn is the
3897 last use of the dest_reg of that DEST_REG giv. If the
3898 increment occurs after the address giv, then we can
3899 perform the optimization. (Otherwise, the increment
3900 would have to go before other_giv, and we would not be
3901 able to combine it with the address giv to get an
3902 auto-inc address.) */
3904 {
3909 {
3912 else
3914 }
3921 }
3922 /* Check for case where increment is before the address
3923 giv. Do this test in "loop order". */
3932 else
3935 #ifdef HAVE_cc0
3936 {
3937 rtx prev;
3939 /* We can't put an insn immediately after one setting
3940 cc0, or immediately before one using cc0. */
3947 }
3948 #endif
3952 }
3953 #endif
3955 /* For each place where the biv is incremented, add an insn
3956 to increment the new, reduced reg for the giv. */
3958 {
3959 rtx insert_before;
3965 else
3973 /* A multiply is acceptable here
3974 since this is presumed to be seldom executed. */
3978 }
3980 /* Add code at loop start to initialize giv's reduced reg. */
3985 }
3986 }
3987 }
3990 /* Check for givs whose first use is their definition and whose
3991 last use is the definition of another giv. If so, it is likely
3992 dead and should not be used to derive another giv nor to
3993 eliminate a biv. */
3995 static void
3999 {
4003 {
4010 {
4016 }
4017 }
4018 }
4021 static void
4026 {
4030 {
4037 /* Update expression if this was combined, in case other giv was
4038 replaced. */
4043 /* See if this register is known to be a pointer to something. If
4044 so, see if we can find the alignment. First see if there is a
4045 destination register that is a pointer. If so, this shares the
4046 alignment too. Next see if we can deduce anything from the
4047 computational information. If not, and this is a DEST_ADDR
4048 giv, at least we know that it's a pointer, though we don't know
4049 the alignment. */
4057 {
4066 }
4070 {
4078 }
4083 /* Store reduced reg as the address in the memref where we found
4084 this giv. */
4087 {
4089 }
4090 else
4091 {
4092 /* Not replaceable; emit an insn to set the original giv reg from
4093 the reduced giv, same as above. */
4096 }
4098 /* When a loop is reversed, givs which depend on the reversed
4099 biv, and which are live outside the loop, must be set to their
4100 correct final value. This insn is only needed if the giv is
4101 not replaceable. The correct final value is the same as the
4102 value that the giv starts the reversed loop with. */
4112 {
4117 }
4118 }
4119 }
4122 static int
4127 rtx test_reg;
4128 {
4137 /* Reduce benefit if not replaceable, since we will insert a
4138 move-insn to replace the insn that calculates this giv. Don't do
4139 this unless the giv is a user variable, since it will often be
4140 marked non-replaceable because of the duplication of the exit
4141 code outside the loop. In such a case, the copies we insert are
4142 dead and will be deleted. So they don't have a cost. Similar
4143 situations exist. */
4144 /* ??? The new final_[bg]iv_value code does a much better job of
4145 finding replaceable giv's, and hence this code may no longer be
4146 necessary. */
4151 /* Decrease the benefit to count the add-insns that we will insert
4152 to increment the reduced reg for the giv. ??? This can
4153 overestimate the run-time cost of the additional insns, e.g. if
4154 there are multiple basic blocks that increment the biv, but only
4155 one of these blocks is executed during each iteration. There is
4156 no good way to detect cases like this with the current structure
4157 of the loop optimizer. This code is more accurate for
4158 determining code size than run-time benefits. */
4161 /* Decide whether to strength-reduce this giv or to leave the code
4162 unchanged (recompute it from the biv each time it is used). This
4163 decision can be made independently for each giv. */
4165 #ifdef AUTO_INC_DEC
4166 /* Attempt to guess whether autoincrement will handle some of the
4167 new add insns; if so, increase BENEFIT (undo the subtraction of
4168 add_cost that was done above). */
4170 /* Increasing the benefit is risky, since this is only a guess.
4171 Avoid increasing register pressure in cases where there would
4172 be no other benefit from reducing this giv. */
4175 {
4190 }
4191 #endif
4194 }
4197 /* Free IV structures for LOOP. */
4199 static void
4202 {
4209 {
4215 {
4218 }
4220 {
4223 }
4227 }
4228 }
4231 /* Perform strength reduction and induction variable elimination.
4233 Pseudo registers created during this function will be beyond the
4234 last valid index in several tables including
4235 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4236 problem here, because the added registers cannot be givs outside of
4237 their loop, and hence will never be reconsidered. But scan_loop
4238 must check regnos to make sure they are in bounds. */
4240 static void
4244 {
4248 rtx p;
4249 /* Temporary list pointer for traversing ivs->list. */
4251 /* Ratio of extra register life span we can justify
4252 for saving an instruction. More if loop doesn't call subroutines
4253 since in that case saving an insn makes more difference
4254 and more registers are available. */
4255 /* ??? could set this to last value of threshold in move_movables */
4257 /* Map of pseudo-register replacements. */
4269 /* Find all BIVs in loop. */
4272 /* Exit if there are no bivs. */
4274 {
4275 /* Can still unroll the loop anyways, but indicate that there is no
4276 strength reduction info available. */
4282 }
4284 /* Determine how BIVS are initialised by looking through pre-header
4285 extended basic block. */
4288 /* Look at the each biv and see if we can say anything better about its
4289 initial value from any initializing insns set up above. */
4292 /* Search the loop for general induction variables. */
4295 /* Try to calculate and save the number of loop iterations. This is
4296 set to zero if the actual number can not be calculated. This must
4297 be called after all giv's have been identified, since otherwise it may
4298 fail if the iteration variable is a giv. */
4301 /* Now for each giv for which we still don't know whether or not it is
4302 replaceable, check to see if it is replaceable because its final value
4303 can be calculated. This must be done after loop_iterations is called,
4304 so that final_giv_value will work correctly. */
4307 /* Try to prove that the loop counter variable (if any) is always
4308 nonnegative; if so, record that fact with a REG_NONNEG note
4309 so that "decrement and branch until zero" insn can be used. */
4312 /* Create reg_map to hold substitutions for replaceable giv regs.
4313 Some givs might have been made from biv increments, so look at
4314 ivs->reg_iv_type for a suitable size. */
4318 /* Examine each iv class for feasibility of strength reduction/induction
4319 variable elimination. */
4322 {
4326 /* Test whether it will be possible to eliminate this biv
4327 provided all givs are reduced. */
4330 /* This will be true at the end, if all givs which depend on this
4331 biv have been strength reduced.
4332 We can't (currently) eliminate the biv unless this is so. */
4335 /* Check each extension dependent giv in this class to see if its
4336 root biv is safe from wrapping in the interior mode. */
4339 /* Combine all giv's for this iv_class. */
4343 {
4351 /* If an insn is not to be strength reduced, then set its ignore
4352 flag, and clear bl->all_reduced. */
4354 /* A giv that depends on a reversed biv must be reduced if it is
4355 used after the loop exit, otherwise, it would have the wrong
4356 value after the loop exit. To make it simple, just reduce all
4357 of such giv's whether or not we know they are used after the loop
4358 exit. */
4363 {
4371 }
4372 else
4373 {
4374 /* Check that we can increment the reduced giv without a
4375 multiply insn. If not, reject it. */
4380 {
4388 }
4389 }
4390 }
4392 /* Check for givs whose first use is their definition and whose
4393 last use is the definition of another giv. If so, it is likely
4394 dead and should not be used to derive another giv nor to
4395 eliminate a biv. */
4398 /* Reduce each giv that we decided to reduce. */
4401 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4402 as not reduced.
4404 For each giv register that can be reduced now: if replaceable,
4405 substitute reduced reg wherever the old giv occurs;
4406 else add new move insn "giv_reg = reduced_reg". */
4409 /* All the givs based on the biv bl have been reduced if they
4410 merit it. */
4412 /* For each giv not marked as maybe dead that has been combined with a
4413 second giv, clear any "maybe dead" mark on that second giv.
4414 v->new_reg will either be or refer to the register of the giv it
4415 combined with.
4417 Doing this clearing avoids problems in biv elimination where
4418 a giv's new_reg is a complex value that can't be put in the
4419 insn but the giv combined with (with a reg as new_reg) is
4420 marked maybe_dead. Since the register will be used in either
4421 case, we'd prefer it be used from the simpler giv. */
4427 /* Try to eliminate the biv, if it is a candidate.
4428 This won't work if ! bl->all_reduced,
4429 since the givs we planned to use might not have been reduced.
4431 We have to be careful that we didn't initially think we could
4432 eliminate this biv because of a giv that we now think may be
4433 dead and shouldn't be used as a biv replacement.
4435 Also, there is the possibility that we may have a giv that looks
4436 like it can be used to eliminate a biv, but the resulting insn
4437 isn't valid. This can happen, for example, on the 88k, where a
4438 JUMP_INSN can compare a register only with zero. Attempts to
4439 replace it with a compare with a constant will fail.
4441 Note that in cases where this call fails, we may have replaced some
4442 of the occurrences of the biv with a giv, but no harm was done in
4443 doing so in the rare cases where it can occur. */
4447 {
4448 /* ?? If we created a new test to bypass the loop entirely,
4449 or otherwise drop straight in, based on this test, then
4450 we might want to rewrite it also. This way some later
4451 pass has more hope of removing the initialization of this
4452 biv entirely. */
4454 /* If final_value != 0, then the biv may be used after loop end
4455 and we must emit an insn to set it just in case.
4457 Reversed bivs already have an insn after the loop setting their
4458 value, so we don't need another one. We can't calculate the
4459 proper final value for such a biv here anyways. */
4467 }
4468 }
4470 /* Go through all the instructions in the loop, making all the
4471 register substitutions scheduled in REG_MAP. */
4476 {
4480 }
4483 {
4484 /* When we completely unroll a loop we will likely not need the increment
4485 of the loop BIV and we will not need the conditional branch at the
4486 end of the loop. */
4489 #ifdef HAVE_cc0
4490 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
4491 need the comparison before the conditional branch at the end of the
4492 loop. */
4494 #endif
4496 /* We'll need one copy for each loop iteration. */
4499 /* A little slop to account for the ability to remove initialization
4500 code, better CSE, and other secondary benefits of completely
4501 unrolling some loops. */
4504 /* Clamp the value. */
4507 }
4509 /* Unroll loops from within strength reduction so that we can use the
4510 induction variable information that strength_reduce has already
4511 collected. Always unroll loops that would be as small or smaller
4512 unrolled than when rolled. */
4518 #ifdef HAVE_doloop_end
4523 /* In case number of iterations is known, drop branch prediction note
4524 in the branch. Do that only in second loop pass, as loop unrolling
4525 may change the number of iterations performed. */
4528 {
4531 PRED_LOOP_ITERATIONS,
4533 }
4541 }
4542 \f
4543 /*Record all basic induction variables calculated in the insn. */
4544 static rtx
4547 rtx p;
4550 {
4552 rtx set;
4553 rtx dest_reg;
4554 rtx inc_val;
4555 rtx mult_val;
4561 {
4566 {
4571 {
4572 /* It is a possible basic induction variable.
4573 Create and initialize an induction structure for it. */
4581 }
4584 }
4585 }
4587 }
4588 \f
4589 /* Record all givs calculated in the insn.
4590 A register is a giv if: it is only set once, it is a function of a
4591 biv and a constant (or invariant), and it is not a biv. */
4592 static rtx
4595 rtx p;
4598 {
4601 rtx set;
4602 /* Look for a general induction variable in a register. */
4607 {
4608 rtx src_reg;
4609 rtx dest_reg;
4610 rtx add_val;
4611 rtx mult_val;
4612 rtx ext_val;
4615 rtx last_consec_insn;
4624 /* Equivalent expression is a giv. */
4629 /* Don't try to handle any regs made by loop optimization.
4630 We have nothing on them in regno_first_uid, etc. */
4632 /* Don't recognize a BASIC_INDUCT_VAR here. */
4634 /* This must be the only place where the register is set. */
4636 /* or all sets must be consecutive and make a giv. */
4641 {
4645 /* If this is a library call, increase benefit. */
4649 /* Skip the consecutive insns, if there are any. */
4657 }
4658 }
4660 #ifndef DONT_REDUCE_ADDR
4661 /* Look for givs which are memory addresses. */
4662 /* This resulted in worse code on a VAX 8600. I wonder if it
4663 still does. */
4666 maybe_multiple);
4667 #endif
4669 /* Update the status of whether giv can derive other givs. This can
4670 change when we pass a label or an insn that updates a biv. */
4675 }
4676 \f
4677 /* Return 1 if X is a valid source for an initial value (or as value being
4678 compared against in an initial test).
4680 X must be either a register or constant and must not be clobbered between
4681 the current insn and the start of the loop.
4683 INSN is the insn containing X. */
4685 static int
4687 rtx x;
4688 rtx insn;
4690 rtx loop_start;
4691 {
4695 /* Only consider pseudos we know about initialized in insns whose luids
4696 we know. */
4701 /* Don't use call-clobbered registers across a call which clobbers it. On
4702 some machines, don't use any hard registers at all. */
4704 && (SMALL_REGISTER_CLASSES
4708 /* Don't use registers that have been clobbered before the start of the
4709 loop. */
4714 }
4715 \f
4716 /* Scan X for memory refs and check each memory address
4717 as a possible giv. INSN is the insn whose pattern X comes from.
4718 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4719 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
4720 more thanonce in each loop iteration. */
4722 static void
4725 rtx x;
4726 rtx insn;
4728 {
4738 {
4754 {
4755 rtx src_reg;
4756 rtx add_val;
4757 rtx mult_val;
4758 rtx ext_val;
4761 /* This code used to disable creating GIVs with mult_val == 1 and
4762 add_val == 0. However, this leads to lost optimizations when
4763 it comes time to combine a set of related DEST_ADDR GIVs, since
4764 this one would not be seen. */
4769 {
4770 /* Found one; record it. */
4779 }
4780 }
4785 }
4787 /* Recursively scan the subexpressions for other mem refs. */
4793 maybe_multiple);
4797 maybe_multiple);
4798 }
4799 \f
4800 /* Fill in the data about one biv update.
4801 V is the `struct induction' in which we record the biv. (It is
4802 allocated by the caller, with alloca.)
4803 INSN is the insn that sets it.
4804 DEST_REG is the biv's reg.
4806 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4807 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4808 being set to INC_VAL.
4810 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4811 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4812 can be executed more than once per iteration. If MAYBE_MULTIPLE
4813 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4814 executed exactly once per iteration. */
4816 static void
4821 rtx insn;
4822 rtx dest_reg;
4823 rtx inc_val;
4824 rtx mult_val;
4828 {
4844 /* Add this to the reg's iv_class, creating a class
4845 if this is the first incrementation of the reg. */
4849 {
4850 /* Create and initialize new iv_class. */
4860 /* Set initial value to the reg itself. */
4863 /* We haven't seen the initializing insn yet */
4873 /* Add this class to ivs->list. */
4877 /* Put it in the array of biv register classes. */
4879 }
4881 /* Update IV_CLASS entry for this biv. */
4890 }
4891 \f
4892 /* Fill in the data about one giv.
4893 V is the `struct induction' in which we record the giv. (It is
4894 allocated by the caller, with alloca.)
4895 INSN is the insn that sets it.
4896 BENEFIT estimates the savings from deleting this insn.
4897 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4898 into a register or is used as a memory address.
4900 SRC_REG is the biv reg which the giv is computed from.
4901 DEST_REG is the giv's reg (if the giv is stored in a reg).
4902 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4903 LOCATION points to the place where this giv's value appears in INSN. */
4905 static void
4910 rtx insn;
4911 rtx src_reg;
4912 rtx dest_reg;
4918 {
4923 rtx temp;
4925 /* Attempt to prove constantness of the values. Don't let simplity_rtx
4926 undo the MULT canonicalization that we performed earlier. */
4956 /* The v->always_computable field is used in update_giv_derive, to
4957 determine whether a giv can be used to derive another giv. For a
4958 DEST_REG giv, INSN computes a new value for the giv, so its value
4959 isn't computable if INSN insn't executed every iteration.
4960 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4961 it does not compute a new value. Hence the value is always computable
4962 regardless of whether INSN is executed each iteration. */
4966 else
4972 {
4975 }
4977 {
4982 /* If the lifetime is zero, it means that this register is
4983 really a dead store. So mark this as a giv that can be
4984 ignored. This will not prevent the biv from being eliminated. */
4990 }
4992 /* Add the giv to the class of givs computed from one biv. */
4996 {
4999 /* Don't count DEST_ADDR. This is supposed to count the number of
5000 insns that calculate givs. */
5004 }
5005 else
5006 /* Fatal error, biv missing for this giv? */
5011 else
5012 {
5013 /* The giv can be replaced outright by the reduced register only if all
5014 of the following conditions are true:
5015 - the insn that sets the giv is always executed on any iteration
5016 on which the giv is used at all
5017 (there are two ways to deduce this:
5018 either the insn is executed on every iteration,
5019 or all uses follow that insn in the same basic block),
5020 - the giv is not used outside the loop
5021 - no assignments to the biv occur during the giv's lifetime. */
5024 /* Previous line always fails if INSN was moved by loop opt. */
5027 && (! not_every_iteration
5029 {
5030 /* Now check that there are no assignments to the biv within the
5031 giv's lifetime. This requires two separate checks. */
5033 /* Check each biv update, and fail if any are between the first
5034 and last use of the giv.
5036 If this loop contains an inner loop that was unrolled, then
5037 the insn modifying the biv may have been emitted by the loop
5038 unrolling code, and hence does not have a valid luid. Just
5039 mark the biv as not replaceable in this case. It is not very
5040 useful as a biv, because it is used in two different loops.
5041 It is very unlikely that we would be able to optimize the giv
5042 using this biv anyways. */
5046 {
5052 {
5056 }
5057 }
5059 /* If there are any backwards branches that go from after the
5060 biv update to before it, then this giv is not replaceable. */
5064 {
5068 }
5069 }
5070 else
5071 {
5072 /* May still be replaceable, we don't have enough info here to
5073 decide. */
5076 }
5077 }
5079 /* Record whether the add_val contains a const_int, for later use by
5080 combine_givs. */
5081 {
5086 ;
5090 {
5092 {
5097 else
5099 }
5102 }
5103 }
5107 }
5109 /* All this does is determine whether a giv can be made replaceable because
5110 its final value can be calculated. This code can not be part of record_giv
5111 above, because final_giv_value requires that the number of loop iterations
5112 be known, and that can not be accurately calculated until after all givs
5113 have been identified. */
5115 static void
5119 {
5126 /* DEST_ADDR givs will never reach here, because they are always marked
5127 replaceable above in record_giv. */
5129 /* The giv can be replaced outright by the reduced register only if all
5130 of the following conditions are true:
5131 - the insn that sets the giv is always executed on any iteration
5132 on which the giv is used at all
5133 (there are two ways to deduce this:
5134 either the insn is executed on every iteration,
5135 or all uses follow that insn in the same basic block),
5136 - its final value can be calculated (this condition is different
5137 than the one above in record_giv)
5138 - it's not used before the it's set
5139 - no assignments to the biv occur during the giv's lifetime. */
5141 #if 0
5142 /* This is only called now when replaceable is known to be false. */
5143 /* Clear replaceable, so that it won't confuse final_giv_value. */
5145 #endif
5149 {
5152 rtx last_giv_use;
5156 /* When trying to determine whether or not a biv increment occurs
5157 during the lifetime of the giv, we can ignore uses of the variable
5158 outside the loop because final_value is true. Hence we can not
5159 use regno_last_uid and regno_first_uid as above in record_giv. */
5161 /* Search the loop to determine whether any assignments to the
5162 biv occur during the giv's lifetime. Start with the insn
5163 that sets the giv, and search around the loop until we come
5164 back to that insn again.
5166 Also fail if there is a jump within the giv's lifetime that jumps
5167 to somewhere outside the lifetime but still within the loop. This
5168 catches spaghetti code where the execution order is not linear, and
5169 hence the above test fails. Here we assume that the giv lifetime
5170 does not extend from one iteration of the loop to the next, so as
5171 to make the test easier. Since the lifetime isn't known yet,
5172 this requires two loops. See also record_giv above. */
5177 {
5180 {
5183 }
5189 {
5190 /* It is possible for the BIV increment to use the GIV if we
5191 have a cycle. Thus we must be sure to check each insn for
5192 both BIV and GIV uses, and we must check for BIV uses
5193 first. */
5200 {
5202 {
5206 }
5208 }
5209 }
5210 }
5212 /* Now that the lifetime of the giv is known, check for branches
5213 from within the lifetime to outside the lifetime if it is still
5214 replaceable. */
5217 {
5220 {
5233 {
5242 }
5243 }
5244 }
5246 /* If it is replaceable, then save the final value. */
5249 }
5254 }
5255 \f
5256 /* Update the status of whether a giv can derive other givs.
5258 We need to do something special if there is or may be an update to the biv
5259 between the time the giv is defined and the time it is used to derive
5260 another giv.
5262 In addition, a giv that is only conditionally set is not allowed to
5263 derive another giv once a label has been passed.
5265 The cases we look at are when a label or an update to a biv is passed. */
5267 static void
5270 rtx p;
5271 {
5275 rtx tem;
5278 /* Search all IV classes, then all bivs, and finally all givs.
5280 There are three cases we are concerned with. First we have the situation
5281 of a giv that is only updated conditionally. In that case, it may not
5282 derive any givs after a label is passed.
5284 The second case is when a biv update occurs, or may occur, after the
5285 definition of a giv. For certain biv updates (see below) that are
5286 known to occur between the giv definition and use, we can adjust the
5287 giv definition. For others, or when the biv update is conditional,
5288 we must prevent the giv from deriving any other givs. There are two
5289 sub-cases within this case.
5291 If this is a label, we are concerned with any biv update that is done
5292 conditionally, since it may be done after the giv is defined followed by
5293 a branch here (actually, we need to pass both a jump and a label, but
5294 this extra tracking doesn't seem worth it).
5296 If this is a jump, we are concerned about any biv update that may be
5297 executed multiple times. We are actually only concerned about
5298 backward jumps, but it is probably not worth performing the test
5299 on the jump again here.
5301 If this is a biv update, we must adjust the giv status to show that a
5302 subsequent biv update was performed. If this adjustment cannot be done,
5303 the giv cannot derive further givs. */
5309 {
5311 {
5312 /* If cant_derive is already true, there is no point in
5313 checking all of these conditions again. */
5317 /* If this giv is conditionally set and we have passed a label,
5318 it cannot derive anything. */
5322 /* Skip givs that have mult_val == 0, since
5323 they are really invariants. Also skip those that are
5324 replaceable, since we know their lifetime doesn't contain
5325 any biv update. */
5329 /* The only way we can allow this giv to derive another
5330 is if this is a biv increment and we can form the product
5331 of biv->add_val and giv->mult_val. In this case, we will
5332 be able to compute a compensation. */
5334 {
5335 rtx ext_val_dummy;
5346 tem = simplify_giv_expr
5353 else
5355 }
5359 }
5360 }
5361 }
5362 \f
5363 /* Check whether an insn is an increment legitimate for a basic induction var.
5364 X is the source of insn P, or a part of it.
5365 MODE is the mode in which X should be interpreted.
5367 DEST_REG is the putative biv, also the destination of the insn.
5368 We accept patterns of these forms:
5369 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5370 REG = INVARIANT + REG
5372 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5373 store the additive term into *INC_VAL, and store the place where
5374 we found the additive term into *LOCATION.
5376 If X is an assignment of an invariant into DEST_REG, we set
5377 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5379 We also want to detect a BIV when it corresponds to a variable
5380 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5381 of the variable may be a PLUS that adds a SUBREG of that variable to
5382 an invariant and then sign- or zero-extends the result of the PLUS
5383 into the variable.
5385 Most GIVs in such cases will be in the promoted mode, since that is the
5386 probably the natural computation mode (and almost certainly the mode
5387 used for addresses) on the machine. So we view the pseudo-reg containing
5388 the variable as the BIV, as if it were simply incremented.
5390 Note that treating the entire pseudo as a BIV will result in making
5391 simple increments to any GIVs based on it. However, if the variable
5392 overflows in its declared mode but not its promoted mode, the result will
5393 be incorrect. This is acceptable if the variable is signed, since
5394 overflows in such cases are undefined, but not if it is unsigned, since
5395 those overflows are defined. So we only check for SIGN_EXTEND and
5396 not ZERO_EXTEND.
5398 If we cannot find a biv, we return 0. */
5400 static int
5405 rtx dest_reg;
5406 rtx p;
5410 {
5418 {
5424 {
5426 }
5431 {
5433 }
5434 else
5447 /* If this is a SUBREG for a promoted variable, check the inner
5448 value. */
5456 /* If this register is assigned in a previous insn, look at its
5457 source, but don't go outside the loop or past a label. */
5459 /* If this sets a register to itself, we would repeat any previous
5460 biv increment if we applied this strategy blindly. */
5466 {
5467 rtx dest;
5468 do
5469 {
5471 }
5500 }
5501 /* Fall through. */
5503 /* Can accept constant setting of biv only when inside inner most loop.
5504 Otherwise, a biv of an inner loop may be incorrectly recognized
5505 as a biv of the outer loop,
5506 causing code to be moved INTO the inner loop. */
5513 /* convert_modes aborts if we try to convert to or from CCmode, so just
5514 exclude that case. It is very unlikely that a condition code value
5515 would be a useful iterator anyways. */
5519 {
5520 /* Possible bug here? Perhaps we don't know the mode of X. */
5524 }
5525 else
5533 /* Similar, since this can be a sign extension. */
5538 ;
5552 location);
5557 }
5558 }
5559 \f
5560 /* A general induction variable (giv) is any quantity that is a linear
5561 function of a basic induction variable,
5562 i.e. giv = biv * mult_val + add_val.
5563 The coefficients can be any loop invariant quantity.
5564 A giv need not be computed directly from the biv;
5565 it can be computed by way of other givs. */
5567 /* Determine whether X computes a giv.
5568 If it does, return a nonzero value
5569 which is the benefit from eliminating the computation of X;
5570 set *SRC_REG to the register of the biv that it is computed from;
5571 set *ADD_VAL and *MULT_VAL to the coefficients,
5572 such that the value of X is biv * mult + add; */
5574 static int
5578 rtx x;
5586 {
5590 /* If this is an invariant, forget it, it isn't a giv. */
5601 {
5604 /* Since this is now an invariant and wasn't before, it must be a giv
5605 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5606 with. */
5613 /* This is equivalent to a BIV. */
5620 /* Either (plus (biv) (invar)) or
5621 (plus (mult (biv) (invar_1)) (invar_2)). */
5623 {
5626 }
5627 else
5628 {
5631 }
5636 /* ADD_VAL is zero. */
5644 }
5646 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5647 unless they are CONST_INT). */
5655 else
5658 /* Always return true if this is a giv so it will be detected as such,
5659 even if the benefit is zero or negative. This allows elimination
5660 of bivs that might otherwise not be eliminated. */
5662 }
5663 \f
5664 /* Given an expression, X, try to form it as a linear function of a biv.
5665 We will canonicalize it to be of the form
5666 (plus (mult (BIV) (invar_1))
5667 (invar_2))
5668 with possible degeneracies.
5670 The invariant expressions must each be of a form that can be used as a
5671 machine operand. We surround then with a USE rtx (a hack, but localized
5672 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5673 routine; it is the caller's responsibility to strip them.
5675 If no such canonicalization is possible (i.e., two biv's are used or an
5676 expression that is neither invariant nor a biv or giv), this routine
5677 returns 0.
5679 For a non-zero return, the result will have a code of CONST_INT, USE,
5680 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5682 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5687 static rtx
5690 rtx x;
5693 {
5698 rtx tem;
5700 /* If this is not an integer mode, or if we cannot do arithmetic in this
5701 mode, this can't be a giv. */
5708 {
5715 /* Put constant last, CONST_INT last if both constant. */
5723 /* Handle addition of zero, then addition of an invariant. */
5728 {
5731 /* Adding two invariants must result in an invariant, so enclose
5732 addition operation inside a USE and return it. */
5742 else
5751 /* biv + invar or mult + invar. Return sum. */
5755 /* (a + invar_1) + invar_2. Associate. */
5756 return
5762 arg1)),
5767 }
5769 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5770 MULT to reduce cases. */
5776 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5777 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5778 Recurse to associate the second PLUS. */
5783 return
5791 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5807 /* Handle "a - b" as "a + b * (-1)". */
5813 constm1_rtx)),
5822 /* Put constant last, CONST_INT last if both constant. */
5827 /* If second argument is not now constant, not giv. */
5831 /* Handle multiply by 0 or 1. */
5839 {
5841 /* biv * invar. Done. */
5845 /* Product of two constants. */
5849 /* invar * invar is a giv, but attempt to simplify it somehow. */
5855 {
5856 /* (invar_0 * invar_1) * invar_2. Associate. */
5863 arg1)),
5865 }
5866 /* Porpagate the MULT expressions to the intermost nodes. */
5868 {
5869 /* (invar_0 + invar_1) * invar_2. Distribute. */
5875 arg1),
5879 arg1)),
5881 }
5885 /* (a * invar_1) * invar_2. Associate. */
5891 arg1)),
5895 /* (a + invar_1) * invar_2. Distribute. */
5900 arg1),
5903 arg1)),
5908 }
5911 /* Shift by constant is multiply by power of two. */
5915 return
5924 /* "-a" is "a * (-1)" */
5930 /* "~a" is "-a - 1". Silly, but easy. */
5934 const1_rtx),
5938 /* Already in proper form for invariant. */
5944 /* Conditionally recognize extensions of simple IVs. After we've
5945 computed loop traversal counts and verified the range of the
5946 source IV, we'll reevaluate this as a GIV. */
5948 {
5951 {
5954 }
5955 }
5959 /* If this is a new register, we can't deal with it. */
5963 /* Check for biv or giv. */
5965 {
5969 {
5972 /* Form expression from giv and add benefit. Ensure this giv
5973 can derive another and subtract any needed adjustment if so. */
5975 /* Increasing the benefit here is risky. The only case in which it
5976 is arguably correct is if this is the only use of V. In other
5977 cases, this will artificially inflate the benefit of the current
5978 giv, and lead to suboptimal code. Thus, it is disabled, since
5979 potentially not reducing an only marginally beneficial giv is
5980 less harmful than reducing many givs that are not really
5981 beneficial. */
5982 {
5986 }
5999 {
6002 }
6003 else
6004 {
6007 }
6009 }
6012 do_default:
6013 /* If it isn't an induction variable, and it is invariant, we
6014 may be able to simplify things further by looking through
6015 the bits we just moved outside the loop. */
6017 {
6023 {
6024 /* Ok, we found a match. Substitute and simplify. */
6026 /* If we match another movable, we must use that, as
6027 this one is going away. */
6032 /* If consec is non-zero, this is a member of a group of
6033 instructions that were moved together. We handle this
6034 case only to the point of seeking to the last insn and
6035 looking for a REG_EQUAL. Fail if we don't find one. */
6037 {
6040 do
6041 {
6043 }
6049 }
6050 else
6051 {
6055 }
6058 {
6059 /* What we are most interested in is pointer
6060 arithmetic on invariants -- only take
6061 patterns we may be able to do something with. */
6067 {
6069 benefit);
6072 }
6077 {
6082 }
6083 }
6085 }
6086 }
6088 }
6090 /* Fall through to general case. */
6092 /* If invariant, return as USE (unless CONST_INT).
6093 Otherwise, not giv. */
6098 {
6107 }
6108 else
6110 }
6111 }
6113 /* This routine folds invariants such that there is only ever one
6114 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6116 static rtx
6119 {
6125 {
6128 }
6131 {
6134 }
6135 else
6136 {
6139 }
6140 }
6142 static rtx
6146 {
6148 {
6152 else
6155 }
6158 else
6161 }
6162 \f
6163 /* Help detect a giv that is calculated by several consecutive insns;
6164 for example,
6165 giv = biv * M
6166 giv = giv + A
6167 The caller has already identified the first insn P as having a giv as dest;
6168 we check that all other insns that set the same register follow
6169 immediately after P, that they alter nothing else,
6170 and that the result of the last is still a giv.
6172 The value is 0 if the reg set in P is not really a giv.
6173 Otherwise, the value is the amount gained by eliminating
6174 all the consecutive insns that compute the value.
6176 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6177 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6179 The coefficients of the ultimate giv value are stored in
6180 *MULT_VAL and *ADD_VAL. */
6182 static int
6187 rtx p;
6188 rtx src_reg;
6189 rtx dest_reg;
6194 {
6200 rtx temp;
6201 rtx set;
6203 /* Indicate that this is a giv so that we can update the value produced in
6204 each insn of the multi-insn sequence.
6206 This induction structure will be used only by the call to
6207 general_induction_var below, so we can allocate it on our stack.
6208 If this is a giv, our caller will replace the induct var entry with
6209 a new induction structure. */
6230 {
6234 /* If libcall, skip to end of call sequence. */
6245 /* Giv created by equivalent expression. */
6251 {
6255 count--;
6259 }
6261 {
6262 /* Allow insns that set something other than this giv to a
6263 constant. Such insns are needed on machines which cannot
6264 include long constants and should not disqualify a giv. */
6273 }
6274 }
6279 }
6280 \f
6281 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6282 represented by G1. If no such expression can be found, or it is clear that
6283 it cannot possibly be a valid address, 0 is returned.
6285 To perform the computation, we note that
6286 G1 = x * v + a and
6287 G2 = y * v + b
6288 where `v' is the biv.
6290 So G2 = (y/b) * G1 + (b - a*y/x).
6292 Note that MULT = y/x.
6294 Update: A and B are now allowed to be additive expressions such that
6295 B contains all variables in A. That is, computing B-A will not require
6296 subtracting variables. */
6298 static rtx
6301 {
6302 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6307 /* If MULT is not 1, we cannot handle A with non-constants, since we
6308 would then be required to subtract multiples of the registers in A.
6309 This is theoretically possible, and may even apply to some Fortran
6310 constructs, but it is a lot of work and we do not attempt it here. */
6315 /* In general these structures are sorted top to bottom (down the PLUS
6316 chain), but not left to right across the PLUS. If B is a higher
6317 order giv than A, we can strip one level and recurse. If A is higher
6318 order, we'll eventually bail out, but won't know that until the end.
6319 If they are the same, we'll strip one level around this loop. */
6322 {
6334 /* We matched: remove one reg completely. */
6337 /* An alternate match. */
6340 /* An alternate match. */
6342 else
6343 {
6344 /* Indicates an extra register in B. Strip one level from B and
6345 recurse, hoping B was the higher order expression. */
6350 }
6351 }
6353 /* Here we are at the last level of A, go through the cases hoping to
6354 get rid of everything but a constant. */
6357 {
6370 }
6372 {
6374 }
6376 {
6381 }
6383 {
6388 else
6390 }
6395 }
6397 rtx
6400 {
6403 /* The value that G1 will be multiplied by must be a constant integer. Also,
6404 the only chance we have of getting a valid address is if b*c/a (see above
6405 for notation) is also an integer. */
6408 {
6413 }
6416 else
6417 {
6418 /* ??? Find out if the one is a multiple of the other? */
6420 }
6424 {
6425 /* Failed. If we've got a multiplication factor between G1 and G2,
6426 scale G1's addend and try again. */
6428 {
6432 {
6433 HOST_WIDE_INT m;
6437 }
6438 else
6439 {
6441 mult);
6442 }
6445 }
6446 }
6450 /* Form simplified final result. */
6455 else
6460 else
6461 {
6464 {
6468 }
6471 }
6472 }
6473 \f
6474 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6475 represented by G1. This indicates that G2 should be combined with G1 and
6476 that G2 can use (either directly or via an address expression) a register
6477 used to represent G1. */
6479 static rtx
6482 {
6485 /* With the introduction of ext dependant givs, we must care for modes.
6486 G2 must not use a wider mode than G1. */
6496 /* If these givs are identical, they can be combined. We use the results
6497 of express_from because the addends are not in a canonical form, so
6498 rtx_equal_p is a weaker test. */
6499 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6500 combination to be the other way round. */
6503 {
6505 }
6507 /* If G2 can be expressed as a function of G1 and that function is valid
6508 as an address and no more expensive than using a register for G2,
6509 the expression of G2 in terms of G1 can be used. */
6513 /* ??? Looses, especially with -fforce-addr, where *g2->location
6514 will always be a register, and so anything more complicated
6515 gets discarded. */
6516 #if 0
6517 #ifdef ADDRESS_COST
6519 #else
6521 #endif
6522 #endif
6523 )
6524 {
6526 }
6529 }
6530 \f
6531 /* Check each extension dependant giv in this class to see if its
6532 root biv is safe from wrapping in the interior mode, which would
6533 make the giv illegal. */
6535 static void
6539 {
6542 HOST_WIDE_INT start_val;
6548 /* Make sure the iteration data is available. We must have
6549 constants in order to be certain of no overflow. */
6550 /* ??? An unknown iteration count with an increment of +-1
6551 combined with friendly exit tests of against an invariant
6552 value is also ameanable to optimization. Not implemented. */
6558 /* Make sure the host can represent the arithmetic. */
6560 {
6562 HOST_WIDE_INT s_end_val;
6574 /* Check for host arithmatic overflow. */
6576 {
6578 HOST_WIDE_INT s_max;
6585 /* Check zero extension of biv ok. */
6587 /* Check for host arithmatic overflow. */
6588 && (neg_incr
6591 /* Check for target arithmetic overflow. */
6592 && (neg_incr
6595 {
6597 }
6599 /* Check sign extension of biv ok. */
6600 /* ??? While it is true that overflow with signed and pointer
6601 arithmetic is undefined, I fear too many programmers don't
6602 keep this fact in mind -- myself included on occasion.
6603 So leave alone with the signed overflow optimizations. */
6605 /* Check for host arithmatic overflow. */
6606 && (neg_incr
6609 /* Check for target arithmetic overflow. */
6610 && (neg_incr
6613 {
6615 }
6616 }
6617 }
6619 /* Invalidate givs that fail the tests. */
6622 {
6627 {
6636 /* We don't know whether this value is being used as either
6637 signed or unsigned, so to safely truncate we must satisfy
6638 both. The initial check here verifies the BIV itself;
6639 once that is successful we may check its range wrt the
6640 derived GIV. */
6642 {
6646 /* We know from the above that both endpoints are nonnegative,
6647 and that there is no wrapping. Verify that both endpoints
6648 are within the (signed) range of the outer mode. */
6651 }
6656 }
6659 {
6661 {
6665 }
6666 }
6667 else
6668 {
6670 {
6675 else
6676 {
6681 else
6683 }
6688 }
6691 }
6692 }
6693 }
6695 /* Generate a version of VALUE in a mode appropriate for initializing V. */
6697 rtx
6700 rtx value;
6701 {
6707 /* Recall that check_ext_dependant_givs verified that the known bounds
6708 of a biv did not overflow or wrap with respect to the extension for
6709 the giv. Therefore, constants need no additional adjustment. */
6713 /* Otherwise, we must adjust the value to compensate for the
6714 differing modes of the biv and the giv. */
6716 }
6717 \f
6718 struct combine_givs_stats
6719 {
6722 };
6724 static int
6728 {
6735 /* Stabilize the sort. */
6739 }
6741 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6742 any other. If so, point SAME to the giv combined with and set NEW_REG to
6743 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6744 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6746 static void
6750 {
6751 /* Additional benefit to add for being combined multiple times. */
6759 /* Count givs, because bl->giv_count is incorrect here. */
6763 giv_count++;
6765 giv_array
6776 {
6778 rtx single_use;
6783 /* If a DEST_REG GIV is used only once, do not allow it to combine
6784 with anything, for in doing so we will gain nothing that cannot
6785 be had by simply letting the GIV with which we would have combined
6786 to be reduced on its own. The losage shows up in particular with
6787 DEST_ADDR targets on hosts with reg+reg addressing, though it can
6788 be seen elsewhere as well. */
6795 /* Add an additional weight for zero addends. */
6800 {
6801 rtx this_combine;
6806 {
6809 }
6810 }
6812 }
6814 /* Iterate, combining until we can't. */
6815 restart:
6819 {
6822 {
6828 }
6830 }
6833 {
6839 /* If it has already been combined, skip. */
6844 {
6847 /* If it has already been combined, skip. */
6849 {
6854 /* For destination, we now may replace by mem expression instead
6855 of register. This changes the costs considerably, so add the
6856 compensation. */
6866 /* ??? The new final_[bg]iv_value code does a much better job
6867 of finding replaceable giv's, and hence this code may no
6868 longer be necessary. */
6872 /* To help optimize the next set of combinations, remove
6873 this giv from the benefits of other potential mates. */
6875 {
6879 }
6886 }
6887 }
6889 /* To help optimize the next set of combinations, remove
6890 this giv from the benefits of other potential mates. */
6892 {
6894 {
6898 }
6902 /* We've finished with this giv, and everything it touched.
6903 Restart the combination so that proper weights for the
6904 rest of the givs are properly taken into account. */
6905 /* ??? Ideally we would compact the arrays at this point, so
6906 as to not cover old ground. But sanely compacting
6907 can_combine is tricky. */
6909 }
6910 }
6912 /* Clean up. */
6915 }
6916 \f
6917 /* Generate sequence for REG = B * M + A. */
6919 static rtx
6925 {
6926 rtx seq;
6927 rtx result;
6930 /* Use unsigned arithmetic. */
6938 }
6941 /* Update registers created in insn sequence SEQ. */
6943 static void
6946 rtx seq;
6947 {
6948 /* Update register info for alias analysis. */
6951 {
6954 {
6958 }
6959 }
6960 else
6961 {
6965 }
6966 }
6969 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
6971 void
6978 basic_block before_bb;
6979 rtx before_insn;
6980 {
6981 rtx seq;
6984 {
6987 }
6989 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6992 /* Increase the lifetime of any invariants moved further in code. */
6999 /* It is possible that the expansion created lots of new registers.
7000 Iterate over the sequence we just created and record them all. */
7002 }
7005 /* Emit insns in loop pre-header to set REG = B * M + A. */
7007 void
7014 {
7015 rtx seq;
7017 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7020 /* Increase the lifetime of any invariants moved further in code.
7021 ???? Is this really necessary? */
7028 /* It is possible that the expansion created lots of new registers.
7029 Iterate over the sequence we just created and record them all. */
7031 }
7034 /* Emit insns after loop to set REG = B * M + A. */
7036 void
7043 {
7044 rtx seq;
7046 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7051 /* It is possible that the expansion created lots of new registers.
7052 Iterate over the sequence we just created and record them all. */
7054 }
7058 /* Similar to gen_add_mult, but compute cost rather than generating
7059 sequence. */
7061 static int
7067 {
7077 {
7082 }
7085 }
7086 \f
7087 /* Test whether A * B can be computed without
7088 an actual multiply insn. Value is 1 if so. */
7090 static int
7092 rtx a;
7093 rtx b;
7094 {
7096 rtx tmp;
7099 /* If only one is constant, make it B. */
7103 /* If first constant, both constant, so don't need multiply. */
7107 /* If second not constant, neither is constant, so would need multiply. */
7111 /* One operand is constant, so might not need multiply insn. Generate the
7112 code for the multiply and see if a call or multiply, or long sequence
7113 of insns is generated. */
7121 {
7126 else
7128 {
7137 {
7140 }
7141 }
7142 }
7152 }
7153 \f
7154 /* Check to see if loop can be terminated by a "decrement and branch until
7155 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7156 Also try reversing an increment loop to a decrement loop
7157 to see if the optimization can be performed.
7158 Value is nonzero if optimization was performed. */
7160 /* This is useful even if the architecture doesn't have such an insn,
7161 because it might change a loops which increments from 0 to n to a loop
7162 which decrements from n to 0. A loop that decrements to zero is usually
7163 faster than one that increments from zero. */
7165 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7166 such as approx_final_value, biv_total_increment, loop_iterations, and
7167 final_[bg]iv_value. */
7169 static int
7173 {
7178 rtx reg;
7179 rtx jump_label;
7180 rtx final_value;
7181 rtx start_value;
7182 rtx new_add_val;
7183 rtx comparison;
7184 rtx before_comparison;
7185 rtx p;
7186 rtx jump;
7187 rtx first_compare;
7192 /* If last insn is a conditional branch, and the insn before tests a
7193 register value, try to optimize it. Otherwise, we can't do anything. */
7202 /* Try to compute whether the compare/branch at the loop end is one or
7203 two instructions. */
7209 else
7212 {
7213 /* If more than one condition is present to control the loop, then
7214 do not proceed, as this function does not know how to rewrite
7215 loop tests with more than one condition.
7217 Look backwards from the first insn in the last comparison
7218 sequence and see if we've got another comparison sequence. */
7220 rtx jump1;
7224 }
7226 /* Check all of the bivs to see if the compare uses one of them.
7227 Skip biv's set more than once because we can't guarantee that
7228 it will be zero on the last iteration. Also skip if the biv is
7229 used between its update and the test insn. */
7232 {
7237 first_compare))
7239 }
7244 /* Look for the case where the basic induction variable is always
7245 nonnegative, and equals zero on the last iteration.
7246 In this case, add a reg_note REG_NONNEG, which allows the
7247 m68k DBRA instruction to be used. */
7255 {
7256 /* Initial value must be greater than 0,
7257 init_val % -dec_value == 0 to ensure that it equals zero on
7258 the last iteration */
7264 {
7265 /* register always nonnegative, add REG_NOTE to branch */
7273 }
7275 /* If the decrement is 1 and the value was tested as >= 0 before
7276 the loop, then we can safely optimize. */
7278 {
7291 {
7299 }
7300 }
7301 }
7304 {
7305 /* Try to change inc to dec, so can apply above optimization. */
7306 /* Can do this if:
7307 all registers modified are induction variables or invariant,
7308 all memory references have non-overlapping addresses
7309 (obviously true if only one write)
7310 allow 2 insns for the compare/jump at the end of the loop. */
7311 /* Also, we must avoid any instructions which use both the reversed
7312 biv and another biv. Such instructions will fail if the loop is
7313 reversed. We meet this condition by requiring that either
7314 no_use_except_counting is true, or else that there is only
7315 one biv. */
7317 /* 1 if the iteration var is used only to count iterations. */
7319 /* 1 if the loop has no memory store, or it has a single memory store
7320 which is reversible. */
7324 {
7328 /* If there are no givs for this biv, and the only exit is the
7329 fall through at the end of the loop, then
7330 see if perhaps there are no uses except to count. */
7334 {
7339 /* An insn that sets the biv is okay. */
7340 ;
7344 {
7345 /* If either of these insns uses the biv and sets a pseudo
7346 that has more than one usage, then the biv has uses
7347 other than counting since it's used to derive a value
7348 that is used more than one time. */
7350 regs);
7352 {
7355 }
7356 }
7358 {
7361 }
7362 }
7364 /* A biv has uses besides counting if it is used to set another biv. */
7367 {
7370 }
7371 }
7374 /* No need to worry about MEMs. */
7375 ;
7377 {
7382 /* If the loop has a single store, and the destination address is
7383 invariant, then we can't reverse the loop, because this address
7384 might then have the wrong value at loop exit.
7385 This would work if the source was invariant also, however, in that
7386 case, the insn should have been moved out of the loop. */
7389 {
7392 /* If we could prove that each of the memory locations
7393 written to was different, then we could reverse the
7394 store -- but we don't presently have any way of
7395 knowing that. */
7398 /* If the store depends on a register that is set after the
7399 store, it depends on the initial value, and is thus not
7400 reversible. */
7402 {
7409 }
7410 }
7411 }
7412 else
7415 /* This code only acts for innermost loops. Also it simplifies
7416 the memory address check by only reversing loops with
7417 zero or one memory access.
7418 Two memory accesses could involve parts of the same array,
7419 and that can't be reversed.
7420 If the biv is used only for counting, than we don't need to worry
7421 about all these things. */
7426 && reversible_mem_store
7431 {
7432 rtx tem;
7434 /* Loop can be reversed. */
7438 /* Now check other conditions:
7440 The increment must be a constant, as must the initial value,
7441 and the comparison code must be LT.
7443 This test can probably be improved since +/- 1 in the constant
7444 can be obtained by changing LT to LE and vice versa; this is
7445 confusing. */
7448 /* for constants, LE gets turned into LT */
7452 {
7463 comparison_const_width
7465 else
7466 comparison_const_width
7470 comparison_sign_mask
7473 /* If the comparison value is not a loop invariant, then we
7474 can not reverse this loop.
7476 ??? If the insns which initialize the comparison value as
7477 a whole compute an invariant result, then we could move
7478 them out of the loop and proceed with loop reversal. */
7486 /* Normalize the initial value if it is an integer and
7487 has no other use except as a counter. This will allow
7488 a few more loops to be reversed. */
7492 {
7494 /* The code below requires comparison_val to be a multiple
7495 of add_val in order to do the loop reversal, so
7496 round up comparison_val to a multiple of add_val.
7497 Since comparison_value is constant, we know that the
7498 current comparison code is LT. */
7500 comparison_val
7502 /* We postpone overflow checks for COMPARISON_VAL here;
7503 even if there is an overflow, we might still be able to
7504 reverse the loop, if converting the loop exit test to
7505 NE is possible. */
7507 }
7509 /* First check if we can do a vanilla loop reversal. */
7511 /* If we have a decrement_and_branch_on_count,
7512 prefer the NE test, since this will allow that
7513 instruction to be generated. Note that we must
7514 use a vanilla loop reversal if the biv is used to
7515 calculate a giv or has a non-counting use. */
7516 #if ! defined (HAVE_decrement_and_branch_until_zero) \
7517 && defined (HAVE_decrement_and_branch_on_count)
7521 #endif
7523 /* Now do postponed overflow checks on COMPARISON_VAL. */
7526 {
7527 /* Register will always be nonnegative, with value
7528 0 on last iteration */
7532 }
7536 {
7539 }
7540 else
7546 /* If the initial value is not zero, or if the comparison
7547 value is not an exact multiple of the increment, then we
7548 can not reverse this loop. */
7551 {
7554 }
7555 else
7556 {
7559 }
7563 /* Reset these in case we normalized the initial value
7564 and comparison value above. */
7567 {
7569 final_value
7571 }
7574 /* Save some info needed to produce the new insns. */
7579 /* Set start_value; if this is not a CONST_INT, we need
7580 to generate a SUB.
7581 Initialize biv to start_value before loop start.
7582 The old initializing insn will be deleted as a
7583 dead store by flow.c. */
7586 {
7589 }
7591 {
7599 start_value
7605 }
7607 {
7610 initial_value);
7614 start_value
7617 }
7618 else
7619 /* We could handle the other cases too, but it'll be
7620 better to have a testcase first. */
7623 /* We may not have a single insn which can increment a reg, so
7624 create a sequence to hold all the insns from expand_inc. */
7633 /* Update biv info to reflect its new status. */
7638 /* Update loop info. */
7647 /* Inc LABEL_NUSES so that delete_insn will
7648 not delete the label. */
7651 /* Emit an insn after the end of the loop to set the biv's
7652 proper exit value if it is used anywhere outside the loop. */
7658 /* Delete compare/branch at end of loop. */
7663 /* Add new compare/branch insn at end of loop. */
7675 ;
7681 {
7683 {
7684 /* Increment of LABEL_NUSES done above. */
7685 /* Register is now always nonnegative,
7686 so add REG_NONNEG note to the branch. */
7689 }
7691 }
7693 /* No insn may reference both the reversed and another biv or it
7694 will fail (see comment near the top of the loop reversal
7695 code).
7696 Earlier on, we have verified that the biv has no use except
7697 counting, or it is the only biv in this function.
7698 However, the code that computes no_use_except_counting does
7699 not verify reg notes. It's possible to have an insn that
7700 references another biv, and has a REG_EQUAL note with an
7701 expression based on the reversed biv. To avoid this case,
7702 remove all REG_EQUAL notes based on the reversed biv
7703 here. */
7706 {
7709 /* If this is a set of a GIV based on the reversed biv, any
7710 REG_EQUAL notes should still be correct. */
7717 {
7722 else
7724 }
7725 }
7727 /* Mark that this biv has been reversed. Each giv which depends
7728 on this biv, and which is also live past the end of the loop
7729 will have to be fixed up. */
7734 {
7738 else
7740 }
7743 }
7744 }
7745 }
7748 }
7749 \f
7750 /* Verify whether the biv BL appears to be eliminable,
7751 based on the insns in the loop that refer to it.
7753 If ELIMINATE_P is non-zero, actually do the elimination.
7755 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
7756 determine whether invariant insns should be placed inside or at the
7757 start of the loop. */
7759 static int
7765 {
7768 rtx p;
7770 /* Scan all insns in the loop, stopping if we find one that uses the
7771 biv in a way that we cannot eliminate. */
7774 {
7779 /* If this is a libcall that sets a giv, skip ahead to its end. */
7781 {
7785 {
7790 {
7797 }
7798 }
7799 }
7804 {
7810 }
7811 }
7814 {
7819 }
7822 }
7823 \f
7824 /* INSN and REFERENCE are instructions in the same insn chain.
7825 Return non-zero if INSN is first. */
7827 int
7830 {
7834 {
7835 /* Start with test for not first so that INSN == REFERENCE yields not
7836 first. */
7842 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
7843 previous insn, hence the <= comparison below does not work if
7844 P is a note. */
7855 }
7856 }
7858 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
7859 the offset that we have to take into account due to auto-increment /
7860 div derivation is zero. */
7861 static int
7864 rtx insn;
7865 {
7866 /* If the giv V had the auto-inc address optimization applied
7867 to it, and INSN occurs between the giv insn and the biv
7868 insn, then we'd have to adjust the value used here.
7869 This is rare, so we don't bother to make this possible. */
7878 }
7880 /* If BL appears in X (part of the pattern of INSN), see if we can
7881 eliminate its use. If so, return 1. If not, return 0.
7883 If BIV does not appear in X, return 1.
7885 If ELIMINATE_P is non-zero, actually do the elimination.
7886 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
7887 Depending on how many items have been moved out of the loop, it
7888 will either be before INSN (when WHERE_INSN is non-zero) or at the
7889 start of the loop (when WHERE_INSN is zero). */
7891 static int
7897 basic_block where_bb;
7898 rtx where_insn;
7899 {
7905 #ifdef HAVE_cc0
7907 #endif
7913 {
7915 /* If we haven't already been able to do something with this BIV,
7916 we can't eliminate it. */
7922 /* If this sets the BIV, it is not a problem. */
7926 /* If this is an insn that defines a giv, it is also ok because
7927 it will go away when the giv is reduced. */
7932 #ifdef HAVE_cc0
7934 {
7935 /* Can replace with any giv that was reduced and
7936 that has (MULT_VAL != 0) and (ADD_VAL == 0).
7937 Require a constant for MULT_VAL, so we know it's nonzero.
7938 ??? We disable this optimization to avoid potential
7939 overflows. */
7947 {
7954 /* If the giv has the opposite direction of change,
7955 then reverse the comparison. */
7959 else
7962 /* We can probably test that giv's reduced reg. */
7965 }
7967 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
7968 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
7969 Require a constant for MULT_VAL, so we know it's nonzero.
7970 ??? Do this only if ADD_VAL is a pointer to avoid a potential
7971 overflow problem. */
7983 {
7990 /* If the giv has the opposite direction of change,
7991 then reverse the comparison. */
7995 else
7999 /* Replace biv with the giv's reduced register. */
8004 /* Insn doesn't support that constant or invariant. Copy it
8005 into a register (it will be a loop invariant.) */
8012 /* Substitute the new register for its invariant value in
8013 the compare expression. */
8017 }
8018 }
8019 #endif
8026 /* See if either argument is the biv. */
8031 else
8035 {
8036 /* First try to replace with any giv that has constant positive
8037 mult_val and constant add_val. We might be able to support
8038 negative mult_val, but it seems complex to do it in general. */
8050 {
8057 /* Replace biv with the giv's reduced reg. */
8060 /* If all constants are actually constant integers and
8061 the derived constant can be directly placed in the COMPARE,
8062 do so. */
8066 {
8071 }
8072 else
8073 {
8074 /* Otherwise, load it into a register. */
8080 }
8083 }
8085 /* Look for giv with positive constant mult_val and nonconst add_val.
8086 Insert insns to calculate new compare value.
8087 ??? Turn this off due to possible overflow. */
8095 {
8096 rtx tem;
8106 /* Replace biv with giv's reduced register. */
8110 /* Compute value to compare against. */
8114 /* Use it in this insn. */
8118 }
8119 }
8121 {
8123 {
8124 /* Look for giv with constant positive mult_val and nonconst
8125 add_val. Insert insns to compute new compare value.
8126 ??? Turn this off due to possible overflow. */
8133 {
8134 rtx tem;
8144 /* Replace biv with giv's reduced register. */
8148 /* Compute value to compare against. */
8155 }
8156 }
8158 /* This code has problems. Basically, you can't know when
8159 seeing if we will eliminate BL, whether a particular giv
8160 of ARG will be reduced. If it isn't going to be reduced,
8161 we can't eliminate BL. We can try forcing it to be reduced,
8162 but that can generate poor code.
8164 The problem is that the benefit of reducing TV, below should
8165 be increased if BL can actually be eliminated, but this means
8166 we might have to do a topological sort of the order in which
8167 we try to process biv. It doesn't seem worthwhile to do
8168 this sort of thing now. */
8170 #if 0
8171 /* Otherwise the reg compared with had better be a biv. */
8176 /* Look for a pair of givs, one for each biv,
8177 with identical coefficients. */
8179 {
8191 {
8198 /* Replace biv with its giv's reduced reg. */
8200 /* Replace other operand with the other giv's
8201 reduced reg. */
8204 }
8205 }
8206 #endif
8207 }
8209 /* If we get here, the biv can't be eliminated. */
8213 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8214 biv is used in it, since it will be replaced. */
8222 }
8224 /* See if any subexpression fails elimination. */
8227 {
8229 {
8242 }
8243 }
8246 }
8247 \f
8248 /* Return nonzero if the last use of REG
8249 is in an insn following INSN in the same basic block. */
8251 static int
8253 rtx reg;
8254 rtx insn;
8255 {
8256 rtx n;
8260 {
8263 }
8265 }
8266 \f
8267 /* Called via `note_stores' to record the initial value of a biv. Here we
8268 just record the location of the set and process it later. */
8270 static void
8272 rtx dest;
8273 rtx set;
8275 {
8286 /* If this is the first set found, record it. */
8288 {
8291 }
8292 }
8293 \f
8294 /* If any of the registers in X are "old" and currently have a last use earlier
8295 than INSN, update them to have a last use of INSN. Their actual last use
8296 will be the previous insn but it will not have a valid uid_luid so we can't
8297 use it. X must be a source expression only. */
8299 static void
8301 rtx x;
8302 rtx insn;
8303 {
8304 /* Check for the case where INSN does not have a valid luid. In this case,
8305 there is no need to modify the regno_last_uid, as this can only happen
8306 when code is inserted after the loop_end to set a pseudo's final value,
8307 and hence this insn will never be the last use of x.
8308 ???? This comment is not correct. See for example loop_givs_reduce.
8309 This may insert an insn before another new insn. */
8313 {
8315 }
8316 else
8317 {
8321 {
8327 }
8328 }
8329 }
8330 \f
8331 /* Given an insn INSN and condition COND, return the condition in a
8332 canonical form to simplify testing by callers. Specifically:
8334 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8335 (2) Both operands will be machine operands; (cc0) will have been replaced.
8336 (3) If an operand is a constant, it will be the second operand.
8337 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8338 for GE, GEU, and LEU.
8340 If the condition cannot be understood, or is an inequality floating-point
8341 comparison which needs to be reversed, 0 will be returned.
8343 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8345 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8346 insn used in locating the condition was found. If a replacement test
8347 of the condition is desired, it should be placed in front of that
8348 insn and we will be sure that the inputs are still valid.
8350 If WANT_REG is non-zero, we wish the condition to be relative to that
8351 register, if possible. Therefore, do not canonicalize the condition
8352 further. */
8354 rtx
8356 rtx insn;
8357 rtx cond;
8360 rtx want_reg;
8361 {
8364 rtx set;
8365 rtx tem;
8383 /* If we are comparing a register with zero, see if the register is set
8384 in the previous insn to a COMPARE or a comparison operation. Perform
8385 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8386 in cse.c */
8391 {
8392 /* Set non-zero when we find something of interest. */
8395 #ifdef HAVE_cc0
8396 /* If comparison with cc0, import actual comparison from compare
8397 insn. */
8399 {
8410 }
8411 #endif
8413 /* If this is a COMPARE, pick up the two things being compared. */
8415 {
8419 }
8423 /* Go back to the previous insn. Stop if it is not an INSN. We also
8424 stop if it isn't a single set or if it has a REG_INC note because
8425 we don't want to bother dealing with it. */
8439 /* If this is setting OP0, get what it sets it to if it looks
8440 relevant. */
8442 {
8445 /* ??? We may not combine comparisons done in a CCmode with
8446 comparisons not done in a CCmode. This is to aid targets
8447 like Alpha that have an IEEE compliant EQ instruction, and
8448 a non-IEEE compliant BEQ instruction. The use of CCmode is
8449 actually artificial, simply to prevent the combination, but
8450 should not affect other platforms.
8452 However, we must allow VOIDmode comparisons to match either
8453 CCmode or non-CCmode comparison, because some ports have
8454 modeless comparisons inside branch patterns.
8456 ??? This mode check should perhaps look more like the mode check
8457 in simplify_comparison in combine. */
8465 && (STORE_FLAG_VALUE
8468 #ifdef FLOAT_STORE_FLAG_VALUE
8471 && (REAL_VALUE_NEGATIVE
8473 #endif
8474 ))
8485 && (STORE_FLAG_VALUE
8488 #ifdef FLOAT_STORE_FLAG_VALUE
8491 && (REAL_VALUE_NEGATIVE
8493 #endif
8494 ))
8500 {
8503 }
8504 else
8506 }
8509 /* If this sets OP0, but not directly, we have to give up. */
8513 {
8517 {
8522 }
8527 }
8528 }
8530 /* If constant is first, put it last. */
8534 /* If OP0 is the result of a comparison, we weren't able to find what
8535 was really being compared, so fail. */
8539 /* Canonicalize any ordered comparison with integers involving equality
8540 if we can do computations in the relevant mode and we do not
8541 overflow. */
8546 {
8549 unsigned HOST_WIDE_INT max_val
8553 {
8559 /* When cross-compiling, const_val might be sign-extended from
8560 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
8580 }
8581 }
8583 #ifdef HAVE_cc0
8584 /* Never return CC0; return zero instead. */
8587 #endif
8590 }
8592 /* Given a jump insn JUMP, return the condition that will cause it to branch
8593 to its JUMP_LABEL. If the condition cannot be understood, or is an
8594 inequality floating-point comparison which needs to be reversed, 0 will
8595 be returned.
8597 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8598 insn used in locating the condition was found. If a replacement test
8599 of the condition is desired, it should be placed in front of that
8600 insn and we will be sure that the inputs are still valid. */
8602 rtx
8604 rtx jump;
8606 {
8607 rtx cond;
8609 rtx set;
8611 /* If this is not a standard conditional jump, we can't parse it. */
8619 /* If this branches to JUMP_LABEL when the condition is false, reverse
8620 the condition. */
8621 reverse
8626 }
8628 /* Similar to above routine, except that we also put an invariant last
8629 unless both operands are invariants. */
8631 rtx
8634 rtx x;
8635 {
8645 }
8647 /* Scan the function and determine whether it has indirect (computed) jumps.
8649 This is taken mostly from flow.c; similar code exists elsewhere
8650 in the compiler. It may be useful to put this into rtlanal.c. */
8651 static int
8653 rtx start;
8654 {
8655 rtx insn;
8662 }
8664 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
8665 documentation for LOOP_MEMS for the definition of `appropriate'.
8666 This function is called from prescan_loop via for_each_rtx. */
8668 static int
8672 {
8681 {
8686 /* We're not interested in MEMs that are only clobbered. */
8690 /* We're not interested in the MEM associated with a
8691 CONST_DOUBLE, so there's no need to traverse into this. */
8695 /* We're not interested in any MEMs that only appear in notes. */
8699 /* This is not a MEM. */
8701 }
8703 /* See if we've already seen this MEM. */
8706 {
8708 /* The modes of the two memory accesses are different. If
8709 this happens, something tricky is going on, and we just
8710 don't optimize accesses to this MEM. */
8714 }
8716 /* Resize the array, if necessary. */
8718 {
8721 else
8727 }
8729 /* Actually insert the MEM. */
8731 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
8732 because we can't put it in a register. We still store it in the
8733 table, though, so that if we see the same address later, but in a
8734 non-BLK mode, we'll not think we can optimize it at that point. */
8740 }
8743 /* Allocate REGS->ARRAY or reallocate it if it is too small.
8745 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
8746 register that is modified by an insn between FROM and TO. If the
8747 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
8748 more, stop incrementing it, to avoid overflow.
8750 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
8751 register I is used, if it is only used once. Otherwise, it is set
8752 to 0 (for no uses) or const0_rtx for more than one use. This
8753 parameter may be zero, in which case this processing is not done.
8755 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
8756 optimize register I. */
8758 static void
8762 {
8765 /* last_set[n] is nonzero iff reg n has been set in the current
8766 basic block. In that case, it is the insn that last set reg n. */
8768 rtx insn;
8774 /* Grow the regs array if not allocated or too small. */
8776 {
8782 /* Zero the new elements. */
8785 }
8787 /* Clear previously scanned fields but do not clear n_times_set. */
8789 {
8793 }
8797 /* Scan the loop, recording register usage. */
8800 {
8802 {
8803 /* Record registers that have exactly one use. */
8806 /* Include uses in REG_EQUAL notes. */
8814 {
8818 last_set);
8819 }
8820 }
8824 }
8827 {
8830 }
8832 #ifdef AVOID_CCMODE_COPIES
8833 /* Don't try to move insns which set CC registers if we should not
8834 create CCmode register copies. */
8838 #endif
8840 /* Set regs->array[I].n_times_set for the new registers. */
8845 }
8847 /* Returns the number of real INSNs in the LOOP. */
8849 static int
8852 {
8854 rtx insn;
8862 }
8864 /* Move MEMs into registers for the duration of the loop. */
8866 static void
8869 {
8876 rtx end_label;
8877 /* Nonzero if the next instruction may never be executed. */
8884 /* We cannot use next_label here because it skips over normal insns. */
8889 /* Check to see if it's possible that some instructions in the loop are
8890 never executed. Also check if there is a goto out of the loop other
8891 than right after the end of the loop. */
8895 {
8899 /* If we enter the loop in the middle, and scan
8900 around to the beginning, don't set maybe_never
8901 for that. This must be an unconditional jump,
8902 otherwise the code at the top of the loop might
8903 never be executed. Unconditional jumps are
8904 followed a by barrier then loop end. */
8909 {
8910 /* If this is a jump outside of the loop but not right
8911 after the end of the loop, we would have to emit new fixup
8912 sequences for each such label. */
8914 JUMP_INSN is executed, we must be conservative. */
8923 /* Something complicated. */
8925 else
8926 /* If there are any more instructions in the loop, they
8927 might not be reached. */
8929 }
8932 }
8934 /* Find start of the extended basic block that enters the loop. */
8938 ;
8943 /* Build table of mems that get set to constant values before the
8944 loop. */
8948 /* Actually move the MEMs. */
8950 {
8951 regset_head load_copies;
8952 regset_head store_copies;
8954 rtx reg;
8956 rtx mem_list_entry;
8960 /* There's no telling whether or not MEM is modified. */
8963 /* Go through the MEMs written to in the loop to see if this
8964 one is aliased by one of them. */
8967 {
8972 {
8973 /* MEM is indeed aliased by this store. */
8976 }
8978 }
8984 /* If this MEM is written to, we must be sure that there
8985 are no reads from another MEM that aliases this one. */
8987 {
8991 {
8995 VOIDmode,
8997 rtx_varies_p))
8998 {
8999 /* It's not safe to hoist loop_info->mems[i] out of
9000 the loop because writes to it might not be
9001 seen by reads from loop_info->mems[j]. */
9004 }
9005 }
9006 }
9009 /* We can't access the MEM outside the loop; it might
9010 cause a trap that wouldn't have happened otherwise. */
9014 /* We thought we were going to lift this MEM out of the
9015 loop, but later discovered that we could not. */
9021 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9022 order to keep scan_loop from moving stores to this MEM
9023 out of the loop just because this REG is neither a
9024 user-variable nor used in the loop test. */
9029 /* Now, replace all references to the MEM with the
9030 corresponding pseudos. */
9035 {
9037 {
9038 rtx set;
9042 /* See if this copies the mem into a register that isn't
9043 modified afterwards. We'll try to do copy propagation
9044 a little further on. */
9046 /* @@@ This test is _way_ too conservative. */
9047 && ! maybe_never
9055 /* See if this copies the mem from a register that isn't
9056 modified afterwards. We'll try to remove the
9057 redundant copy later on by doing a little register
9058 renaming and copy propagation. This will help
9059 to untangle things for the BIV detection code. */
9061 && ! maybe_never
9069 /* Replace the memory reference with the shadow register. */
9072 }
9077 }
9080 /* We couldn't replace all occurrences of the MEM. */
9082 else
9083 {
9084 /* Load the memory immediately before LOOP->START, which is
9085 the NOTE_LOOP_BEG. */
9087 rtx set;
9093 {
9097 {
9101 /* Extending hard register lifetimes causes crash
9102 on SRC targets. Doing so on non-SRC is
9103 probably also not good idea, since we most
9104 probably have pseudoregister equivalence as
9105 well. */
9108 }
9109 /* Use the constant equivalence if that is cheap enough. */
9115 {
9118 }
9120 /* If best_equiv is nonzero, we know that MEM is set to a
9121 constant or register before the loop. We will use this
9122 knowledge to initialize the shadow register with that
9123 constant or reg rather than by loading from MEM. */
9126 }
9131 {
9134 {
9137 }
9138 }
9146 {
9148 {
9151 }
9153 /* Store the memory immediately after END, which is
9154 the NOTE_LOOP_END. */
9157 }
9160 {
9165 }
9167 /* Attempt a bit of copy propagation. This helps untangle the
9168 data flow, and enables {basic,general}_induction_var to find
9169 more bivs/givs. */
9170 EXECUTE_IF_SET_IN_REG_SET
9172 {
9174 });
9177 EXECUTE_IF_SET_IN_REG_SET
9179 {
9181 });
9183 }
9184 }
9187 {
9188 /* Now, we need to replace all references to the previous exit
9189 label with the new one. */
9190 rtx_pair rr;
9195 {
9198 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9199 field. This is not handled by for_each_rtx because it doesn't
9200 handle unprinted ('0') fields. We need to update JUMP_LABEL
9201 because the immediately following unroll pass will use it.
9202 replace_label would not work anyways, because that only handles
9203 LABEL_REFs. */
9206 }
9207 }
9210 }
9212 /* For communication between note_reg_stored and its caller. */
9213 struct note_reg_stored_arg
9214 {
9216 rtx reg;
9217 };
9219 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9220 is equal to ARG. */
9221 static void
9225 {
9229 }
9231 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9232 There must be exactly one insn that sets this pseudo; it will be
9233 deleted if all replacements succeed and we can prove that the register
9234 is not used after the loop. */
9236 static void
9239 rtx replacement;
9241 {
9242 /* This is the reg that we are copying from. */
9245 rtx insn;
9246 /* These help keep track of whether we replaced all uses of the reg. */
9253 {
9254 rtx set;
9256 /* Only substitute within one extended basic block from the initializing
9257 insn. */
9264 /* Is this the initializing insn? */
9269 {
9276 }
9278 /* Only substitute after seeing the initializing insn. */
9280 {
9287 /* Stop replacing when REPLACEMENT is modified. */
9292 {
9295 /* It is possible that we've turned previously valid REG_EQUAL to
9296 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
9297 REPLACEMENT is modified, we get different meaning. */
9301 }
9302 }
9303 }
9307 {
9311 {
9312 rtx first;
9313 rtx retval_note;
9315 /* Assume we're just deleting INIT_INSN. */
9317 /* Look for REG_RETVAL note. If we're deleting the end of
9318 the libcall sequence, the whole sequence can go. */
9320 /* If we found a REG_RETVAL note, find the first instruction
9321 in the sequence. */
9325 /* Delete the instructions. */
9327 }
9330 }
9331 }
9333 /* Replace all the instructions from FIRST up to and including LAST
9334 with NOTE_INSN_DELETED notes. */
9336 static void
9338 rtx first;
9339 rtx last;
9340 {
9342 {
9349 /* If this was the LAST instructions we're supposed to delete,
9350 we're done. */
9355 }
9356 }
9358 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
9359 loop LOOP if the order of the sets of these registers can be
9360 swapped. There must be exactly one insn within the loop that sets
9361 this pseudo followed immediately by a move insn that sets
9362 REPLACEMENT with REGNO. */
9363 static void
9366 rtx replacement;
9368 {
9369 rtx insn;
9378 {
9379 /* Search for the insn that copies REGNO to NEW_REGNO? */
9387 }
9390 {
9391 rtx prev_insn;
9392 rtx prev_set;
9394 /* Some DEF-USE info would come in handy here to make this
9395 function more general. For now, just check the previous insn
9396 which is the most likely candidate for setting REGNO. */
9404 {
9405 /* We have:
9406 (set (reg regno) (expr))
9407 (set (reg new_regno) (reg regno))
9409 so try converting this to:
9410 (set (reg new_regno) (expr))
9411 (set (reg regno) (reg new_regno))
9413 The former construct is often generated when a global
9414 variable used for an induction variable is shadowed by a
9415 register (NEW_REGNO). The latter construct improves the
9416 chances of GIV replacement and BIV elimination. */
9426 {
9433 /* Update first use of REGNO. */
9437 /* Now perform copy propagation to hopefully
9438 remove all uses of REGNO within the loop. */
9440 }
9441 }
9442 }
9443 }
9445 /* Replace MEM with its associated pseudo register. This function is
9446 called from load_mems via for_each_rtx. DATA is actually a pointer
9447 to a structure describing the instruction currently being scanned
9448 and the MEM we are currently replacing. */
9450 static int
9454 {
9462 {
9467 /* We're not interested in the MEM associated with a
9468 CONST_DOUBLE, so there's no need to traverse into one. */
9472 /* This is not a MEM. */
9474 }
9477 /* This is not the MEM we are currently replacing. */
9480 /* Actually replace the MEM. */
9484 }
9486 static void
9488 rtx insn;
9489 rtx mem;
9490 rtx reg;
9491 {
9492 loop_replace_args args;
9499 }
9501 /* Replace one register with another. Called through for_each_rtx; PX points
9502 to the rtx being scanned. DATA is actually a pointer to
9503 a structure of arguments. */
9505 static int
9509 {
9520 }
9522 static void
9524 rtx insn;
9525 rtx reg;
9526 rtx replacement;
9527 {
9528 loop_replace_args args;
9535 }
9537 /* Replace occurrences of the old exit label for the loop with the new
9538 one. DATA is an rtx_pair containing the old and new labels,
9539 respectively. */
9541 static int
9545 {
9564 }
9565 \f
9566 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
9567 (ignored in the interim). */
9569 static rtx
9572 basic_block where_bb ATTRIBUTE_UNUSED;
9573 rtx where_insn;
9574 rtx pattern;
9575 {
9577 }
9580 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
9581 in basic block WHERE_BB (ignored in the interim) within the loop
9582 otherwise hoist PATTERN into the loop pre-header. */
9584 rtx
9587 basic_block where_bb ATTRIBUTE_UNUSED;
9588 rtx where_insn;
9589 rtx pattern;
9590 {
9594 }
9597 /* Emit call insn for PATTERN before WHERE_INSN in basic block
9598 WHERE_BB (ignored in the interim) within the loop. */
9600 static rtx
9603 basic_block where_bb ATTRIBUTE_UNUSED;
9604 rtx where_insn;
9605 rtx pattern;
9606 {
9608 }
9611 /* Hoist insn for PATTERN into the loop pre-header. */
9613 rtx
9616 rtx pattern;
9617 {
9619 }
9622 /* Hoist call insn for PATTERN into the loop pre-header. */
9624 static rtx
9627 rtx pattern;
9628 {
9630 }
9633 /* Sink insn for PATTERN after the loop end. */
9635 rtx
9638 rtx pattern;
9639 {
9641 }
9644 /* If the loop has multiple exits, emit insn for PATTERN before the
9645 loop to ensure that it will always be executed no matter how the
9646 loop exits. Otherwise, emit the insn for PATTERN after the loop,
9647 since this is slightly more efficient. */
9649 static rtx
9652 rtx pattern;
9653 {
9656 else
9658 }
9659 \f
9660 static void
9665 {
9673 iv_num++;
9678 {
9681 }
9682 }
9685 static void
9690 {
9692 rtx incr;
9703 {
9706 }
9708 {
9711 }
9715 {
9719 }
9722 {
9726 }
9728 /* List the increments. */
9730 {
9734 }
9736 /* List the givs. */
9738 {
9743 else
9746 }
9747 }
9750 static void
9755 {
9766 {
9770 }
9773 }
9776 static void
9781 {
9788 else
9804 {
9806 {
9818 }
9819 }
9830 {
9834 }
9837 }
9840 void
9843 {
9845 }
9848 void
9851 {
9853 }
9856 void
9859 {
9861 }
9864 void
9867 {
9869 }
9872 #define LOOP_BLOCK_NUM_1(INSN) \
9873 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
9875 /* The notes do not have an assigned block, so look at the next insn. */
9876 #define LOOP_BLOCK_NUM(INSN) \
9877 ((INSN) ? (GET_CODE (INSN) == NOTE \
9878 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
9879 : LOOP_BLOCK_NUM_1 (INSN)) \
9880 : -1)
9882 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
9884 static void
9889 {
9890 rtx label;
9895 /* Print diagnostics to compare our concept of a loop with
9896 what the loop notes say. */
9911 {
9931 {
9934 {
9937 }
9938 }
9941 /* This can happen when a marked loop appears as two nested loops,
9942 say from while (a || b) {}. The inner loop won't match
9943 the loop markers but the outer one will. */
9946 }
9947 }
9949 /* Call this function from the debugger to dump LOOP. */
9951 void
9954 {
9956 }
9958 /* Call this function from the debugger to dump LOOPS. */
9960 void
9963 {
9965 }