1 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
3 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
4 enable PC-relative addressing for -mcpu=future.
5 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
6 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
7 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
8 suppress PC-relative addressing.
9 (rs6000_option_override_internal): Split up error messages
10 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
13 2020-04-25 Jakub Jelinek <jakub@redhat.com>
14 Richard Biener <rguenther@suse.de>
16 PR tree-optimization/94734
17 PR tree-optimization/89430
18 * tree-ssa-phiopt.c: Include tree-eh.h.
19 (cond_store_replacement): Return false if an automatic variable
20 access could trap. If -fstore-data-races, don't return false
21 just because an automatic variable is addressable.
23 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
25 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
27 (add<mode>_sext_dup2_exec): Likewise.
29 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
32 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
33 endian byteshift_val calculation.
35 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
37 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
39 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
41 * config/aarch64/arm_sve.h: Add a comment.
43 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
45 PR rtl-optimization/94708
46 * combine.c (simplify_if_then_else): Add check for
47 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
49 2020-04-23 Martin Sebor <msebor@redhat.com>
52 * common.opt (-Wno-frame-larger-than): New option.
53 (-Wno-larger-than, -Wno-stack-usage): Same.
55 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
57 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
59 (mov<mode>_exec): Likewise.
60 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
61 (<convop><mode><vndi>2_exec): Likewise.
63 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
65 PR tree-optimization/94717
66 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
67 of the stores doesn't have the same landing pad number as the first.
68 (coalesce_immediate_stores): Do not try to coalesce the store using
69 bswap if it doesn't have the same landing pad number as the first.
71 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
73 * gcc/doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
74 Replace outdated link to ELFv2 ABI.
76 2020-04-23 Jakub Jelinek <jakub@redhat.com>
79 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
83 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
84 temporarily with non-final second operand and updating it later,
85 push COMPOUND_EXPRs into a vector and process it in reverse,
86 creating COMPOUND_EXPRs with the final operands.
88 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
91 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
92 bti c and bti j handling.
94 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
95 Thomas Schwinge <thomas@codesourcery.com>
99 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
100 t_async and the wait arguments.
102 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
104 PR tree-optimization/94727
105 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
106 comparing invariant scalar booleans.
108 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
109 Jakub Jelinek <jakub@redhat.com>
112 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
113 empty base class artificial fields.
114 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
115 different after this fix.
117 2020-04-23 Jakub Jelinek <jakub@redhat.com>
120 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
121 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
122 if the same type has been diagnosed most recently already.
124 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
126 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
128 (__arm_vbicq_n_s16): Likewise.
129 (__arm_vbicq_n_u32): Likewise.
130 (__arm_vbicq_n_s32): Likewise.
131 (__arm_vbicq): Likewise.
132 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
133 (__arm_vbicq_n_s32): Likewise.
134 (__arm_vbicq_n_u16): Likewise.
135 (__arm_vbicq_n_u32): Likewise.
136 (__arm_vdupq_m_n_s8): Likewise.
137 (__arm_vdupq_m_n_s16): Likewise.
138 (__arm_vdupq_m_n_s32): Likewise.
139 (__arm_vdupq_m_n_u8): Likewise.
140 (__arm_vdupq_m_n_u16): Likewise.
141 (__arm_vdupq_m_n_u32): Likewise.
142 (__arm_vdupq_m_n_f16): Likewise.
143 (__arm_vdupq_m_n_f32): Likewise.
144 (__arm_vldrhq_gather_offset_s16): Likewise.
145 (__arm_vldrhq_gather_offset_s32): Likewise.
146 (__arm_vldrhq_gather_offset_u16): Likewise.
147 (__arm_vldrhq_gather_offset_u32): Likewise.
148 (__arm_vldrhq_gather_offset_f16): Likewise.
149 (__arm_vldrhq_gather_offset_z_s16): Likewise.
150 (__arm_vldrhq_gather_offset_z_s32): Likewise.
151 (__arm_vldrhq_gather_offset_z_u16): Likewise.
152 (__arm_vldrhq_gather_offset_z_u32): Likewise.
153 (__arm_vldrhq_gather_offset_z_f16): Likewise.
154 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
155 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
156 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
157 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
158 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
159 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
160 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
161 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
162 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
163 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
164 (__arm_vldrwq_gather_offset_s32): Likewise.
165 (__arm_vldrwq_gather_offset_u32): Likewise.
166 (__arm_vldrwq_gather_offset_f32): Likewise.
167 (__arm_vldrwq_gather_offset_z_s32): Likewise.
168 (__arm_vldrwq_gather_offset_z_u32): Likewise.
169 (__arm_vldrwq_gather_offset_z_f32): Likewise.
170 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
171 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
172 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
173 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
174 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
175 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
176 (__arm_vdwdupq_x_n_u8): Likewise.
177 (__arm_vdwdupq_x_n_u16): Likewise.
178 (__arm_vdwdupq_x_n_u32): Likewise.
179 (__arm_viwdupq_x_n_u8): Likewise.
180 (__arm_viwdupq_x_n_u16): Likewise.
181 (__arm_viwdupq_x_n_u32): Likewise.
182 (__arm_vidupq_x_n_u8): Likewise.
183 (__arm_vddupq_x_n_u8): Likewise.
184 (__arm_vidupq_x_n_u16): Likewise.
185 (__arm_vddupq_x_n_u16): Likewise.
186 (__arm_vidupq_x_n_u32): Likewise.
187 (__arm_vddupq_x_n_u32): Likewise.
188 (__arm_vldrdq_gather_offset_s64): Likewise.
189 (__arm_vldrdq_gather_offset_u64): Likewise.
190 (__arm_vldrdq_gather_offset_z_s64): Likewise.
191 (__arm_vldrdq_gather_offset_z_u64): Likewise.
192 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
193 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
194 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
195 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
196 (__arm_vidupq_m_n_u8): Likewise.
197 (__arm_vidupq_m_n_u16): Likewise.
198 (__arm_vidupq_m_n_u32): Likewise.
199 (__arm_vddupq_m_n_u8): Likewise.
200 (__arm_vddupq_m_n_u16): Likewise.
201 (__arm_vddupq_m_n_u32): Likewise.
202 (__arm_vidupq_n_u16): Likewise.
203 (__arm_vidupq_n_u32): Likewise.
204 (__arm_vidupq_n_u8): Likewise.
205 (__arm_vddupq_n_u16): Likewise.
206 (__arm_vddupq_n_u32): Likewise.
207 (__arm_vddupq_n_u8): Likewise.
209 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
211 * doc/install.texi (D-Specific Options): Document
212 --enable-libphobos-checking and --with-libphobos-druntime-only.
214 2020-04-23 Jakub Jelinek <jakub@redhat.com>
217 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
218 cxx17_empty_base_seen argument. Pass it to recursive calls.
219 Ignore cxx17_empty_base_field_p fields after setting
220 *cxx17_empty_base_seen to true.
221 (rs6000_discover_homogeneous_aggregate): Adjust
222 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
223 aggregates with C++17 empty base fields.
226 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
227 if last_decl is error_mark_node or has such a TREE_TYPE.
230 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
231 if last_decl is error_mark_node or has such a TREE_TYPE.
233 2020-04-22 Felix Yang <felix.yang@huawei.com>
236 * config/aarch64/aarch64.h (TARGET_SVE):
237 Add && !TARGET_GENERAL_REGS_ONLY.
238 (TARGET_SVE2): Add && TARGET_SVE.
239 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
240 TARGET_SVE2_SM4): Add && TARGET_SVE2.
241 * config/aarch64/aarch64-sve-builtins.h
242 (sve_switcher::m_old_general_regs_only): New member.
243 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
245 (reported_missing_registers_p): New variable.
246 (check_required_extensions): Call check_required_registers before
247 return if all required extenstions are present.
248 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
249 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
250 global_options.x_target_flags.
251 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
252 global_options.x_target_flags if m_old_general_regs_only is true.
254 2020-04-22 Zackery Spytz <zspytz@gmail.com>
256 * doc/extend.exi: Add "free" to list of other builtin functions
259 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
262 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
264 (store_quadpti): Ditto.
265 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
266 plq will be used and doesn't need it.
267 (atomic_store<mode>): Ditto, for pstq.
269 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
271 * doc/invoke.texi: Update flags turned on by -O3.
273 2020-04-22 Jakub Jelinek <jakub@redhat.com>
276 * config/ia64/ia64.c (hfa_element_mode): Ignore
277 cxx17_empty_base_field_p fields.
280 * calls.h (cxx17_empty_base_field_p): Declare.
281 * calls.c (cxx17_empty_base_field_p): Define.
283 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
285 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
287 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
288 Andre Vieira <andre.simoesdiasvieira@arm.com>
289 Mihail Ionescu <mihail.ionescu@arm.com>
291 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
292 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
293 (ALL_QUIRKS): Add quirk_no_asmcpu.
294 (cortex-m55): Define new cpu.
295 * config/arm/arm-tables.opt: Regenerate.
296 * config/arm/arm-tune.md: Likewise.
297 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
299 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
301 PR tree-optimization/94700
302 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
303 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
304 of similarly-structured but distinct vector types.
306 2020-04-21 Martin Sebor <msebor@redhat.com>
309 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
310 the computation of the lower bound of the source access size.
311 (builtin_access::generic_overlap): Remove a hack for setting ranges
314 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
316 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
317 (ASM_WEAKEN_DECL): New define.
318 (HAVE_GAS_WEAKREF): Undefine.
320 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
322 PR tree-optimization/94683
323 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
324 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
325 but distinct vector types.
327 2020-04-21 Jakub Jelinek <jakub@redhat.com>
330 * stor-layout.c (place_field, finalize_record_size): Don't emit
331 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
332 * ubsan.c (ubsan_get_type_descriptor_type,
333 ubsan_get_source_location_type, ubsan_create_data): Set
335 * asan.c (asan_global_struct): Likewise.
337 2020-04-21 Duan bo <duanbo3@huawei.com>
340 * config/aarch64/aarch64.c: Add an error message for option conflict.
341 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
342 incompatible with -fpic, -fPIC and -mabi=ilp32.
344 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
347 * omp-low.c (new_omp_context): Remove assignments to
348 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
350 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
352 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
353 ("popcountv2di2_vx"): Use simplify_gen_subreg.
355 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
358 * config/s390/s390-builtin-types.def: Add 3 new function modes.
359 * config/s390/s390-builtins.def: Add mode dependent low-level
360 builtin and map the overloaded builtins to these.
361 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
362 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
364 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
366 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
367 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
368 estimated VF and is no worse at double the estimated VF.
370 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
373 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
374 order of arguments to rtx_vector_builder.
375 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
376 When extending the trailing constants to a full vector, replace any
377 variables with zeros.
379 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
382 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
385 2020-04-20 Martin Liska <mliska@suse.cz>
387 * symtab.c (symtab_node::dump_references): Add space after
389 (symtab_node::dump_referring): Likewise.
391 2020-04-18 Jeff Law <law@redhat.com>
394 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
397 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
399 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
400 attributes): Document d_runtime_has_std_library.
402 2020-04-17 Jeff Law <law@redhat.com>
404 PR rtl-optimization/90275
405 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
406 when the destination has a REG_UNUSED note.
408 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
411 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
414 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
416 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
417 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
418 cost of load and store insns if one loop iteration has enough scalar
419 elements to use an Advanced SIMD LDP or STP.
420 (aarch64_add_stmt_cost): Update call accordingly.
422 2020-04-17 Jakub Jelinek <jakub@redhat.com>
423 Jeff Law <law@redhat.com>
426 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
427 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
428 or pos + len >= 32, or pos + len is equal to operands[2] precision
429 and operands[2] is not a register operand. During splitting perform
430 SImode AND if operands[0] doesn't have CCZmode and pos + len is
431 equal to mode precision.
433 2020-04-17 Richard Biener <rguenther@suse.de>
436 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
438 * dwarf2out.c (dw_val_equal_p): Fix pasto in
439 dw_val_class_vms_delta comparison.
440 * optabs.c (expand_binop_directly): Fix pasto in commutation
442 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
445 2020-04-17 Jakub Jelinek <jakub@redhat.com>
447 PR rtl-optimization/94618
448 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
449 insn is the BB_END of its block, but also when it is only followed
450 by DEBUG_INSNs in its block.
452 PR tree-optimization/94621
453 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
454 Move id->adjust_array_error_bounds check first in the condition.
456 2020-04-17 Martin Liska <mliska@suse.cz>
457 Jonathan Yong <10walls@gmail.com>
459 PR gcov-profile/94570
460 * coverage.c (coverage_init): Use separator properly.
462 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
464 PR rtl-optimization/93974
465 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
466 (rs6000_cannot_substitute_mem_equiv_p): New function.
468 2020-04-16 Martin Jambor <mjambor@suse.cz>
471 * ipa-inline.h (ipa_saved_clone_sources): Declare.
472 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
473 (save_inline_function_body): Link the new body holder with the
475 * cgraph.c: Include ipa-inline.h.
476 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
477 the statement in ipa_saved_clone_sources.
478 * cgraphunit.c: Include ipa-inline.h.
479 (expand_all_functions): Free ipa_saved_clone_sources.
481 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
484 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
485 the VNx16BI lowpart of the recursively-generated constant.
487 2020-04-16 Martin Liska <mliska@suse.cz>
488 Jakub Jelinek <jakub@redhat.com>
491 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
492 DECL_IS_REPLACEABLE_OPERATOR during cloning.
493 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
494 (propagate_necessity): Check operator names.
496 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
498 PR rtl-optimization/94605
499 * early-remat.c (early_remat::process_block): Handle insns that
500 set multiple candidate registers.
501 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
503 PR gcov-profile/93401
504 * common.opt (profile-prefix-path): New option.
505 * coverae.c: Include diagnostics.h.
506 (coverage_init): Strip profile prefix path.
507 * doc/invoke.texi (-fprofile-prefix-path): Document.
509 2020-04-16 Richard Biener <rguenther@suse.de>
512 * expr.c (emit_move_multi_word): Do not generate code when
513 the destination part is undefined_operand_subword_p.
514 * lower-subreg.c (resolve_clobber): Look through a paradoxica
517 2020-04-16 Martin Jambor <mjambor@suse.cz>
519 PR tree-optimization/94598
520 * tree-sra.c (verify_sra_access_forest): Fix verification of total
521 scalarization accesses under access to one-element arrays.
523 2020-04-16 Jakub Jelinek <jakub@redhat.com>
526 * function.c (assign_parm_find_data_types): Add workaround for
527 BROKEN_VALUE_INITIALIZATION compilers.
529 2020-04-16 Richard Biener <rguenther@suse.de>
531 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
534 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
537 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
538 Require OPTION_MASK_ISA_SSE2.
540 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
543 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
544 Don't construct a dump_context temporary to call static method.
546 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
548 * config/aarch64/falkor-tag-collision-avoidance.c
549 (valid_src_p): Check for aarch64_address_info type before
550 accessing base field.
552 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
554 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
555 (V_sz_elem2): Remove unused mode attribute.
557 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
559 * config/arm/arm.md (arm_movdi): Disallow for MVE.
561 2020-04-15 Richard Biener <rguenther@suse.de>
564 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
565 alias_sets_conflict_p for pointers.
567 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
570 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
571 (extendhisi2_internal): Add %v1 before the load instructions.
573 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
576 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
577 use PC-relative addressing for TLS references.
579 2020-04-14 Martin Jambor <mjambor@suse.cz>
582 * ipa-sra.c: Include internal-fn.h.
583 (enum isra_scan_context): Update comment.
584 (scan_function): Treat calls to internal_functions like loads or stores.
586 2020-04-14 Yang Yang <yangyang305@huawei.com>
588 PR tree-optimization/94574
589 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
590 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
592 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
595 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
597 2020-04-13 Martin Sebor <msebor@redhat.com>
599 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
600 -Wformat-truncation. Move -Wzero-length-bounds last.
601 (-Wrestrict): Document positive form of option enabled by -Wall.
603 2020-04-13 Zachary Spytz <zspytz@gmail.com>
605 * doc/extend.texi: Add realloc to list of built-in functions
606 are recognized by the compiler.
608 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
611 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
612 pointer in word_mode for eh_return epilogues.
614 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
616 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
617 memory references in %B, %C and %D operand selectors when the inner
618 operand is a post increment address.
620 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
622 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
623 reference by 4 bytes, and %D memory reference by 6 bytes.
625 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
628 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
629 condition for V4SI, V8HI and V16QI modes.
631 2020-04-11 Jakub Jelinek <jakub@redhat.com>
635 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
638 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
642 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
643 "#pragma omp declare target" has also been applied.
645 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
647 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
648 when to emit the epilogue_helper insn.
649 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
652 2020-04-09 Jakub Jelinek <jakub@redhat.com>
655 * cselib.h (cselib_record_sp_cfa_base_equiv,
656 cselib_sp_derived_value_p): Declare.
657 * cselib.c (cselib_record_sp_cfa_base_equiv,
658 cselib_sp_derived_value_p): New functions.
659 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
660 cselib_sp_derived_value_p values.
661 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
662 start of extended basic blocks other than the first one
663 for !frame_pointer_needed functions.
665 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
667 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
668 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
669 (aarch64_sve2048_hw): Document.
670 * config/aarch64/aarch64-protos.h
671 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
672 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
673 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
674 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
676 (find_type_suffix_for_scalar_type): Use it instead of comparing
678 (function_resolver::infer_vector_or_tuple_type): Likewise.
679 (function_resolver::require_vector_type): Likewise.
680 (handle_arm_sve_vector_bits_attribute): New function.
681 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
682 (aarch64_attribute_table): Add arm_sve_vector_bits.
683 (aarch64_return_in_memory_1):
684 (pure_scalable_type_info::piece::get_rtx): New function.
685 (pure_scalable_type_info::num_zr): Likewise.
686 (pure_scalable_type_info::num_pr): Likewise.
687 (pure_scalable_type_info::get_rtx): Likewise.
688 (pure_scalable_type_info::analyze): Likewise.
689 (pure_scalable_type_info::analyze_registers): Likewise.
690 (pure_scalable_type_info::analyze_array): Likewise.
691 (pure_scalable_type_info::analyze_record): Likewise.
692 (pure_scalable_type_info::add_piece): Likewise.
693 (aarch64_some_values_include_pst_objects_p): Likewise.
694 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
695 to analyze whether the type is returned in SVE registers.
696 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
697 is passed in SVE registers.
698 (aarch64_pass_by_reference_1): New function, extracted from...
699 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
700 to analyze whether the type is a pure scalable type and, if so,
701 whether it should be passed by reference.
702 (aarch64_return_in_msb): Return false for pure scalable types.
703 (aarch64_function_value_1): Fold back into...
704 (aarch64_function_value): ...this function. Use
705 pure_scalable_type_info to analyze whether the type is a pure
706 scalable type and, if so, which registers it should use. Handle
707 types that include pure scalable types but are not themselves
709 (aarch64_return_in_memory_1): New function, split out from...
710 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
711 to analyze whether the type is a pure scalable type and, if so,
712 whether it should be returned by reference.
713 (aarch64_layout_arg): Remove orig_mode argument. Use
714 pure_scalable_type_info to analyze whether the type is a pure
715 scalable type and, if so, which registers it should use. Handle
716 types that include pure scalable types but are not themselves
718 (aarch64_function_arg): Update call accordingly.
719 (aarch64_function_arg_advance): Likewise.
720 (aarch64_pad_reg_upward): On big-endian targets, return false for
721 pure scalable types that are smaller than 16 bytes.
722 (aarch64_member_type_forces_blk): New function.
723 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
724 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
725 correspond to built-in SVE types. Do not rely on a vector mode
726 if the type includes an pure scalable type. When returning true,
727 assert that the mode is not an SVE mode.
728 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
729 built-in types here. When returning true, assert that the type
730 does not have an SVE mode.
731 (aarch64_can_change_mode_class): Don't allow anything to change
732 between a predicate mode and a non-predicate mode. Also don't
733 allow changes between SVE vector modes and other modes that
734 might be bigger than 128 bits.
735 (aarch64_invalid_binary_op): Reject binary operations that mix
736 SVE and GNU vector types.
737 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
739 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
741 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
743 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
744 (sizeless_type_p): New functions.
745 (register_builtin_types): Apply make_type_sizeless to the type.
746 (register_tuple_type): Likewise.
747 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
749 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
751 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
754 2020-04-09 Martin Jambor <mjambor@suse.cz>
755 Richard Biener <rguenther@suse.de>
757 PR tree-optimization/94482
758 * tree-sra.c (create_access_replacement): Dump new replacement with
760 (sra_modify_expr): Fix handling of cases when the original EXPR writes
761 to only part of the replacement.
762 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
763 the first operand of combinations into REAL/IMAGPART_EXPR and
766 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
768 * doc/sourcebuild.texi (check-function-bodies): Treat the third
769 parameter as a list of option regexps and require each regexp
772 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
775 * config/aarch64/falkor-tag-collision-avoidance.c
776 (valid_src_p): Fix missing rtx type check.
778 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
779 Richard Biener <rguenther@suse.de>
781 PR tree-optimization/93674
782 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
783 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
784 or non-mode precision type, add candidate in unsigned type with the
787 2020-04-08 Clement Chigot <clement.chigot@atos.net>
789 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
790 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
791 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
793 2020-04-08 Jakub Jelinek <jakub@redhat.com>
796 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
798 * reload1.c (eliminate_regs_1): Avoid creating
799 (plus (reg) (const_int 0)) in DEBUG_INSNs.
801 PR tree-optimization/94524
802 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
803 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
804 op1 rather than op1 itself at the end. Punt for signed modulo by
805 most negative constant.
806 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
807 modulo by most negative constant.
809 2020-04-08 Richard Biener <rguenther@suse.de>
811 PR rtl-optimization/93946
812 * cse.c (cse_insn): Record the tabled expression in
813 src_related. Verify a redundant store removal is valid.
815 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
818 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
819 ENDBR at function entry if function will be called indirectly.
821 2020-04-08 Jakub Jelinek <jakub@redhat.com>
824 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
827 2020-04-08 Martin Liska <mliska@suse.cz>
830 * gimple.c (gimple_call_operator_delete_p): Rename to...
831 (gimple_call_replaceable_operator_delete_p): ... this.
832 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
833 * gimple.h (gimple_call_operator_delete_p): Rename to ...
834 (gimple_call_replaceable_operator_delete_p): ... this.
835 * tree-core.h (tree_function_decl): Add replaceable_operator
837 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
838 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
839 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
840 (eliminate_unnecessary_stmts): Likewise.
841 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
842 Pack DECL_IS_REPLACEABLE_OPERATOR.
843 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
844 Unpack the field here.
845 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
846 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
847 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
848 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
849 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
850 replaceable operator flags.
852 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
853 Matthew Malcomson <matthew.malcomson@arm.com>
855 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
856 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
857 (CX_TERNARY_QUALIFIERS): Likewise.
858 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
859 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
860 (arm_init_acle_builtins): Initialize CDE builtins.
861 (arm_expand_acle_builtin): Check CDE constant operands.
862 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
863 of CDE constant operand.
864 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
866 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
867 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
868 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
869 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
870 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
871 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
872 * config/arm/arm_cde_builtins.def: New file.
873 * config/arm/iterators.md (V_reg): New attribute of SI.
874 * config/arm/predicates.md (const_int_coproc_operand): New.
875 (const_int_vcde1_operand, const_int_vcde2_operand): New.
876 (const_int_vcde3_operand): New.
877 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
878 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
879 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
880 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
882 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
884 * config.gcc: Add arm_cde.h.
885 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
886 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
887 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
888 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
889 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
890 * config/arm/arm.h (TARGET_CDE): New macro.
891 * config/arm/arm_cde.h: New file.
892 * doc/invoke.texi: Document CDE options +cdecp[0-7].
893 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
895 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
897 2020-04-08 Jakub Jelinek <jakub@redhat.com>
899 PR rtl-optimization/94516
900 * postreload.c: Include rtl-iter.h.
901 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
902 looking for all MEMs with RTX_AUTOINC operand.
903 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
905 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
907 * omp-grid.c (grid_eliminate_combined_simd_part): Use
908 OMP_CLAUSE_CODE to access the omp clause code.
910 2020-04-07 Jeff Law <law@redhat.com>
912 PR rtl-optimization/92264
913 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
914 the destination is the stack pointer.
916 2020-04-07 Jakub Jelinek <jakub@redhat.com>
918 PR rtl-optimization/94291
919 PR rtl-optimization/84169
920 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
921 must be a REG or SUBREG of REG; if it is not one of these, don't
924 2020-04-07 Richard Biener <rguenther@suse.de>
927 * gimplify.c (gimplify_addr_expr): Also consider generated
930 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
932 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
934 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
936 * config/arm/arm_mve.h: Cast some pointers to expected types.
938 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
940 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
941 same with '__arm_' prefix.
943 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
945 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
947 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
949 * config/arm/arm.c (arm_mve_immediate_check): Removed.
950 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
951 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
952 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
953 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
954 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
955 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
957 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
959 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
961 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
963 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
964 * config/arm/mve/md: Fix v[id]wdup patterns.
966 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
968 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
969 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
971 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
973 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
974 and remove const_ptr enums.
976 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
978 * config/arm/arm_mve.h (vsubq_n): Merge with...
980 (vmulq_n): Merge with...
982 (__ARM_mve_typeid): Simplify scalar and constant detection.
984 2020-04-07 Jakub Jelinek <jakub@redhat.com>
987 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
988 for inter-lane permutation for 64-byte modes.
991 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
992 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
993 Assume it is a REG after that instead of testing it and doing FAIL
994 otherwise. Formatting fix.
996 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
998 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
1000 2020-04-07 Jakub Jelinek <jakub@redhat.com>
1003 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
1004 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
1006 2020-04-06 Jakub Jelinek <jakub@redhat.com>
1008 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
1009 + const0_rtx return the SP_DERIVED_VALUE_P.
1011 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
1013 PR rtl-optimization/92989
1014 * lra-lives.c (process_bb_lives): Do not treat eh_return data
1015 registers as being live at the beginning of the EH receiver.
1017 2020-04-05 Zachary Spytz <zspytz@gmail.com>
1019 * extend.texi: Add free to list of ISO C90 functions that
1020 are recognized by the compiler.
1022 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
1024 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
1027 * config/microblaze/microblaze.md (trap): Update output pattern.
1029 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
1030 Jakub Jelinek <jakub@redhat.com>
1033 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
1034 arrays, pointer-to-members, function types and qualifiers when
1035 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
1036 to emit type again on definition.
1038 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
1041 * ipa-fnsummary.c (vrp_will_run_p): New function.
1042 (fre_will_run_p): New function.
1043 (evaluate_properties_for_edge): Use it.
1044 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
1045 !optimize_debug to optimize_debug.
1047 2020-04-04 Jakub Jelinek <jakub@redhat.com>
1049 PR rtl-optimization/94468
1050 * cselib.c (references_value_p): Formatting fix.
1051 (cselib_useless_value_p): New function.
1052 (discard_useless_locs, discard_useless_values,
1053 cselib_invalidate_regno_val, cselib_invalidate_mem,
1054 cselib_record_set): Use it instead of
1055 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
1058 * tree-iterator.h (expr_single): Declare.
1059 * tree-iterator.c (expr_single): New function.
1060 * tree.h (protected_set_expr_location_if_unset): Declare.
1061 * tree.c (protected_set_expr_location): Use expr_single.
1062 (protected_set_expr_location_if_unset): New function.
1064 2020-04-03 Jeff Law <law@redhat.com>
1066 PR rtl-optimization/92264
1067 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
1068 reloading of auto-increment addressing modes.
1070 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
1073 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
1076 2020-04-03 Jeff Law <law@redhat.com>
1078 PR rtl-optimization/92264
1079 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
1080 post-increment addressing of source operands as well as residuals
1081 when computing any adjustments to the input pointer.
1083 2020-04-03 Jakub Jelinek <jakub@redhat.com>
1086 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
1087 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
1088 second half of first lane from first lane of second operand and
1089 first half of second lane from second lane of first operand.
1091 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
1093 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
1095 2020-04-03 Tamar Christina <tamar.christina@arm.com>
1098 * common/config/aarch64/aarch64-common.c
1099 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
1101 2020-04-03 Richard Biener <rguenther@suse.de>
1104 * tree.c (array_ref_low_bound): Deal with released SSA names
1107 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
1109 * config/gcn/gcn.c (print_operand): Handle unordered comparison
1111 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
1112 comparison operators.
1114 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
1116 PR tree-optimization/94443
1117 * tree-vect-loop.c (vectorizable_live_operation): Use
1118 gsi_insert_seq_before to replace gsi_insert_before.
1120 2020-04-03 Martin Liska <mliska@suse.cz>
1123 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
1124 Compare type attributes for gimple_call_fntypes.
1126 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
1128 * alias.c (get_alias_set): Fix comment typos.
1130 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
1133 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
1134 attribute checking used by TYPE.
1136 2020-04-02 Martin Jambor <mjambor@suse.cz>
1139 * ipa-sra.c (struct caller_issues): New fields candidate and
1140 call_from_outside_comdat.
1141 (check_for_caller_issues): Check for calls from outsied of
1142 candidate's same_comdat_group.
1143 (check_all_callers_for_issues): Set up issues.candidate, check result
1145 (mark_callers_calls_comdat_local): New function.
1146 (process_isra_node_results): Set calls_comdat_local of callers if
1149 2020-04-02 Richard Biener <rguenther@suse.de>
1152 * common.opt (ffinite-loops): Initialize to zero.
1153 * opts.c (default_options_table): Remove OPT_ffinite_loops
1155 * cfgloop.h (loop::finite_p): New member.
1156 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
1157 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
1159 * lto-streamer-in.c (input_cfg): Stream finite_p.
1160 * lto-streamer-out.c (output_cfg): Likewise.
1161 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
1162 from flag_finite_loops at CFG build time.
1163 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
1164 finite_p flag instead of flag_finite_loops.
1165 * doc/invoke.texi (ffinite-loops): Adjust documentation of
1168 2020-04-02 Richard Biener <rguenther@suse.de>
1171 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
1172 DW_TAG_imported_unit.
1174 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
1176 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
1177 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
1180 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
1182 PR tree-optimization/94401
1183 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
1184 access type when loading halves of vector to avoid peeling for gaps.
1186 2020-04-02 Jakub Jelinek <jakub@redhat.com>
1188 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
1189 between a string literal and MIPS_SYSVERSION_SPEC macro.
1191 2020-04-02 Martin Jambor <mjambor@suse.cz>
1193 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
1195 2020-04-02 Jakub Jelinek <jakub@redhat.com>
1197 PR rtl-optimization/92264
1198 * params.opt (-param=max-find-base-term-values=): Decrease default
1201 PR rtl-optimization/92264
1202 * rtl.h (struct rtx_def): Mention that call bit is used as
1203 SP_DERIVED_VALUE_P in cselib.c.
1204 * cselib.c (SP_DERIVED_VALUE_P): Define.
1205 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
1206 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
1207 val_rtx and sp based expression where offsets cancel each other.
1208 (preserve_constants_and_equivs): Formatting fix.
1209 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
1210 locs list for cfa_base_preserved_val if needed. Formatting fix.
1211 (autoinc_split): If the to be returned value is a REG, MEM or
1212 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
1213 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
1214 (rtx_equal_for_cselib_1): Call autoinc_split even if both
1215 expressions are PLUS in Pmode with CONST_INT second operands.
1216 Handle SP_DERIVED_VALUE_P cases.
1217 (cselib_hash_plus_const_int): New function.
1218 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
1219 second operand, as well as for PRE_DEC etc. that ought to be
1220 hashed the same way.
1221 (cselib_subst_to_values): Substitute PLUS with Pmode and
1222 CONST_INT operand if the first operand is a VALUE which has
1223 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
1224 SP_DERIVED_VALUE_P + adjusted offset.
1225 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
1226 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
1227 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
1228 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
1229 on the sp value before calling cselib_add_permanent_equiv on the
1231 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
1232 in the insn without REG_INC note.
1233 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
1234 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
1237 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
1238 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
1240 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1243 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
1244 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
1245 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
1246 intrinsic defintion by adding a new builtin call to writeback into base
1248 (__arm_vldrdq_gather_base_wb_u64): Likewise.
1249 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
1250 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
1251 (__arm_vldrwq_gather_base_wb_s32): Likewise.
1252 (__arm_vldrwq_gather_base_wb_u32): Likewise.
1253 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
1254 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
1255 (__arm_vldrwq_gather_base_wb_f32): Likewise.
1256 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
1257 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
1258 builtin's qualifier.
1259 (vldrdq_gather_base_wb_z_u): Likewise.
1260 (vldrwq_gather_base_wb_u): Likewise.
1261 (vldrdq_gather_base_wb_u): Likewise.
1262 (vldrwq_gather_base_wb_z_s): Likewise.
1263 (vldrwq_gather_base_wb_z_f): Likewise.
1264 (vldrdq_gather_base_wb_z_s): Likewise.
1265 (vldrwq_gather_base_wb_s): Likewise.
1266 (vldrwq_gather_base_wb_f): Likewise.
1267 (vldrdq_gather_base_wb_s): Likewise.
1268 (vldrwq_gather_base_nowb_z_u): Define builtin.
1269 (vldrdq_gather_base_nowb_z_u): Likewise.
1270 (vldrwq_gather_base_nowb_u): Likewise.
1271 (vldrdq_gather_base_nowb_u): Likewise.
1272 (vldrwq_gather_base_nowb_z_s): Likewise.
1273 (vldrwq_gather_base_nowb_z_f): Likewise.
1274 (vldrdq_gather_base_nowb_z_s): Likewise.
1275 (vldrwq_gather_base_nowb_s): Likewise.
1276 (vldrwq_gather_base_nowb_f): Likewise.
1277 (vldrdq_gather_base_nowb_s): Likewise.
1278 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
1280 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
1281 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
1282 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
1283 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
1284 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
1285 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
1286 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
1287 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
1288 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
1289 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
1290 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
1292 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
1294 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
1295 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
1296 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
1297 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
1298 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
1299 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
1300 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
1301 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
1302 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
1304 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
1305 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
1306 Remove constraints from expander.
1307 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
1308 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
1309 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
1310 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
1311 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
1312 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
1314 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
1316 PR rtl-optimization/94123
1317 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
1318 flag_split_wide_types_early.
1320 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
1322 * doc/extend.texi (Common Function Attributes): Fix typo.
1324 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
1327 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
1330 2020-04-01 Zackery Spytz <zspytz@gmail.com>
1332 * doc/extend.texi: Fix a typo in the documentation of the
1333 copy function attribute.
1335 2020-04-01 Jakub Jelinek <jakub@redhat.com>
1338 * tree-object-size.c (pass_object_sizes::execute): Don't call
1339 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
1340 call replace_call_with_value.
1342 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
1344 PR tree-optimization/94043
1345 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
1346 phi for vec_lhs and use it for lane extraction.
1348 2020-03-31 Felix Yang <felix.yang@huawei.com>
1350 PR tree-optimization/94398
1351 * tree-vect-stmts.c (vectorizable_store): Instead of calling
1352 vect_supportable_dr_alignment, set alignment_support_scheme to
1353 dr_unaligned_supported for gather-scatter accesses.
1354 (vectorizable_load): Likewise.
1356 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
1358 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
1360 (vnsi, VnSI, vndi, VnDI): New mode attributes.
1361 (mov<mode>): Use <VnDI> in place of V64DI.
1362 (mov<mode>_exec): Likewise.
1363 (mov<mode>_sgprbase): Likewise.
1364 (reload_out<mode>): Likewise.
1365 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
1366 (gather_load<mode>v64si): Rename to ...
1367 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
1368 and <VnDI> in place of V64DI.
1369 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
1370 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
1371 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
1372 (scatter_store<mode>v64si): Rename to ...
1373 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
1374 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
1375 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
1376 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
1377 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
1378 (ds_bpermute<mode>): Use <VnSI>.
1379 (addv64si3_vcc<exec_vcc>): Rename to ...
1380 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
1381 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
1382 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
1383 (addcv64si3<exec_vcc>): Rename to ...
1384 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
1385 (subv64si3_vcc<exec_vcc>): Rename to ...
1386 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
1387 (subcv64si3<exec_vcc>): Rename to ...
1388 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
1389 (addv64di3): Rename to ...
1390 (add<mode>3): ... this, and use V_DI.
1391 (addv64di3_exec): Rename to ...
1392 (add<mode>3_exec): ... this, and use V_DI.
1393 (subv64di3): Rename to ...
1394 (sub<mode>3): ... this, and use V_DI.
1395 (subv64di3_exec): Rename to ...
1396 (sub<mode>3_exec): ... this, and use V_DI.
1397 (addv64di3_zext): Rename to ...
1398 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
1399 (addv64di3_zext_exec): Rename to ...
1400 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
1401 (addv64di3_zext_dup): Rename to ...
1402 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
1403 (addv64di3_zext_dup_exec): Rename to ...
1404 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
1405 (addv64di3_zext_dup2): Rename to ...
1406 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
1407 (addv64di3_zext_dup2_exec): Rename to ...
1408 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
1409 (addv64di3_sext_dup2): Rename to ...
1410 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
1411 (addv64di3_sext_dup2_exec): Rename to ...
1412 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
1413 (<su>mulv64si3_highpart<exec>): Rename to ...
1414 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
1415 (mulv64di3): Rename to ...
1416 (mul<mode>3): ... this, and use V_DI and <VnSI>.
1417 (mulv64di3_exec): Rename to ...
1418 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
1419 (mulv64di3_zext): Rename to ...
1420 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
1421 (mulv64di3_zext_exec): Rename to ...
1422 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
1423 (mulv64di3_zext_dup2): Rename to ...
1424 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
1425 (mulv64di3_zext_dup2_exec): Rename to ...
1426 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
1427 (<expander>v64di3): Rename to ...
1428 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
1429 (<expander>v64di3_exec): Rename to ...
1430 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
1431 (<expander>v64si3<exec>): Rename to ...
1432 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
1433 (v<expander>v64si3<exec>): Rename to ...
1434 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
1435 (<expander>v64si3<exec>): Rename to ...
1436 (<expander><vnsi>3<exec>): ... this, and use V_SI.
1437 (subv64df3<exec>): Rename to ...
1438 (sub<mode>3<exec>): ... this, and use V_DF.
1439 (truncv64di<mode>2): Rename to ...
1440 (trunc<vndi><mode>2): ... this, and use <VnDI>.
1441 (truncv64di<mode>2_exec): Rename to ...
1442 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
1443 (<convop><mode>v64di2): Rename to ...
1444 (<convop><mode><vndi>2): ... this, and use <VnDI>.
1445 (<convop><mode>v64di2_exec): Rename to ...
1446 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
1447 (vec_cmp<u>v64qidi): Rename to ...
1448 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
1449 (vec_cmp<u>v64qidi_exec): Rename to ...
1450 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
1451 (vcond_mask_<mode>di): Use <VnDI>.
1452 (maskload<mode>di): Likewise.
1453 (maskstore<mode>di): Likewise.
1454 (mask_gather_load<mode>v64si): Rename to ...
1455 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
1456 (mask_scatter_store<mode>v64si): Rename to ...
1457 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
1458 (*<reduc_op>_dpp_shr_v64di): Rename to ...
1459 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
1460 (*plus_carry_in_dpp_shr_v64si): Rename to ...
1461 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
1462 (*plus_carry_dpp_shr_v64di): Rename to ...
1463 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
1464 (vec_seriesv64si): Rename to ...
1465 (vec_series<mode>): ... this, and use V_SI.
1466 (vec_seriesv64di): Rename to ...
1467 (vec_series<mode>): ... this, and use V_DI.
1469 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
1471 * config/arc/arc.c (arc_print_operand): Use
1472 HOST_WIDE_INT_PRINT_DEC macro.
1474 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
1476 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
1478 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1480 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
1482 (__arm_vbicq): Likewise.
1484 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
1486 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
1488 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1490 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
1491 common section of both MVE Integer and MVE Floating Point.
1493 (vaddlvq_p): Likewise.
1494 (vaddvaq): Likewise.
1495 (vaddvq_p): Likewise.
1496 (vcmpcsq): Likewise.
1497 (vmlsdavxq): Likewise.
1498 (vmlsdavq): Likewise.
1499 (vmladavxq): Likewise.
1500 (vmladavq): Likewise.
1502 (vminavq): Likewise.
1504 (vmaxavq): Likewise.
1505 (vmlaldavq): Likewise.
1506 (vcmphiq): Likewise.
1507 (vaddlvaq): Likewise.
1508 (vrmlaldavhq): Likewise.
1509 (vrmlaldavhxq): Likewise.
1510 (vrmlsldavhq): Likewise.
1511 (vrmlsldavhxq): Likewise.
1512 (vmlsldavxq): Likewise.
1513 (vmlsldavq): Likewise.
1515 (vrmlaldavhaq): Likewise.
1516 (vcmpgeq_m_n): Likewise.
1517 (vmlsdavxq_p): Likewise.
1518 (vmlsdavq_p): Likewise.
1519 (vmlsdavaxq): Likewise.
1520 (vmlsdavaq): Likewise.
1521 (vaddvaq_p): Likewise.
1522 (vcmpcsq_m_n): Likewise.
1523 (vcmpcsq_m): Likewise.
1524 (vmladavxq_p): Likewise.
1525 (vmladavq_p): Likewise.
1526 (vmladavaxq): Likewise.
1527 (vmladavaq): Likewise.
1528 (vminvq_p): Likewise.
1529 (vminavq_p): Likewise.
1530 (vmaxvq_p): Likewise.
1531 (vmaxavq_p): Likewise.
1532 (vcmphiq_m): Likewise.
1533 (vaddlvaq_p): Likewise.
1534 (vmlaldavaq): Likewise.
1535 (vmlaldavaxq): Likewise.
1536 (vmlaldavq_p): Likewise.
1537 (vmlaldavxq_p): Likewise.
1538 (vmlsldavaq): Likewise.
1539 (vmlsldavaxq): Likewise.
1540 (vmlsldavq_p): Likewise.
1541 (vmlsldavxq_p): Likewise.
1542 (vrmlaldavhaxq): Likewise.
1543 (vrmlaldavhq_p): Likewise.
1544 (vrmlaldavhxq_p): Likewise.
1545 (vrmlsldavhaq): Likewise.
1546 (vrmlsldavhaxq): Likewise.
1547 (vrmlsldavhq_p): Likewise.
1548 (vrmlsldavhxq_p): Likewise.
1549 (vabavq_p): Likewise.
1550 (vmladavaq_p): Likewise.
1551 (vstrbq_scatter_offset): Likewise.
1552 (vstrbq_p): Likewise.
1553 (vstrbq_scatter_offset_p): Likewise.
1554 (vstrdq_scatter_base_p): Likewise.
1555 (vstrdq_scatter_base): Likewise.
1556 (vstrdq_scatter_offset_p): Likewise.
1557 (vstrdq_scatter_offset): Likewise.
1558 (vstrdq_scatter_shifted_offset_p): Likewise.
1559 (vstrdq_scatter_shifted_offset): Likewise.
1560 (vmaxq_x): Likewise.
1561 (vminq_x): Likewise.
1562 (vmovlbq_x): Likewise.
1563 (vmovltq_x): Likewise.
1564 (vmulhq_x): Likewise.
1565 (vmullbq_int_x): Likewise.
1566 (vmullbq_poly_x): Likewise.
1567 (vmulltq_int_x): Likewise.
1568 (vmulltq_poly_x): Likewise.
1571 2020-03-31 Jakub Jelinek <jakub@redhat.com>
1574 * config/aarch64/constraints.md (Uph): New constraint.
1575 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
1576 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
1579 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
1580 Jakub Jelinek <jakub@redhat.com>
1583 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
1584 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
1586 2020-03-31 Jakub Jelinek <jakub@redhat.com>
1588 PR tree-optimization/94403
1589 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
1590 ENUMERAL_TYPE lhs_type.
1592 PR rtl-optimization/94344
1593 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
1594 conversions, either on both operands of |^+ or just one. Handle
1595 also extra same precision conversion on RSHIFT_EXPR first operand
1596 provided RSHIFT_EXPR is performed in unsigned type.
1598 2020-03-30 David Malcolm <dmalcolm@redhat.com>
1600 * lra.c (finish_insn_code_data_once): Set the array elements
1601 to NULL after freeing them.
1603 2020-03-30 Andreas Schwab <schwab@suse.de>
1605 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
1608 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
1610 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
1611 to skip defining builtins based on builtin_mask.
1613 2020-03-30 Jakub Jelinek <jakub@redhat.com>
1616 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
1617 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
1618 operand is a register. Don't enable masked variants for V*[QH]Imode.
1621 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
1622 <store_mask_constraint> instead of m in output operand constraint.
1623 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
1626 2020-03-30 Alan Modra <amodra@gmail.com>
1628 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
1629 (rs6000_indirect_call_template_1): Adjust to suit.
1630 * config/rs6000/rs6000.md (call_local): Merge call_local32,
1631 call_local64, and call_local_aix.
1632 (call_value_local): Simlarly.
1633 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
1634 and disable pattern when CALL_LONG.
1635 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
1636 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
1637 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
1639 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
1642 * doc/invoke.texi: Update -falign-functions, -falign-loops and
1643 -falign-jumps documentation.
1645 2020-03-29 Martin Liska <mliska@suse.cz>
1648 * cgraphunit.c (process_function_and_variable_attributes): Remove
1649 double 'attribute' words.
1651 2020-03-29 John David Anglin <dave.anglin@bell.net>
1653 * gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
1656 2020-03-28 Jakub Jelinek <jakub@redhat.com>
1659 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
1660 to true after setting size to integer_one_node.
1662 PR tree-optimization/94329
1663 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
1664 on the last stmt in a bb, make sure gsi_prev isn't done immediately
1667 2020-03-27 Alan Modra <amodra@gmail.com>
1670 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
1671 for PLT16_LO and PLT_PCREL.
1672 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
1673 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
1674 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
1676 2020-03-27 Martin Sebor <msebor@redhat.com>
1679 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
1681 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
1683 * config/gcn/gcn-valu.md:
1684 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
1685 (VEC_1REG_MODE): Delete.
1686 (VEC_1REG_ALT): Delete.
1687 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
1688 (VEC_1REG_INT_MODE): Delete.
1689 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
1690 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
1691 (VEC_2REG_MODE): Rename to V_2REG throughout.
1692 (VEC_REG_MODE): Rename to V_noHI throughout.
1693 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
1694 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
1695 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
1696 (VEC_INT_MODE): Delete.
1697 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
1698 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
1699 (FP_MODE): Delete and replace with FP throughout.
1700 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
1701 (VCMP_MODE): Rename to V_noQI throughout and move to top.
1702 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
1703 * config/gcn/gcn.md (FP): New mode iterator.
1704 (FP_1REG): New mode iterator.
1706 2020-03-27 David Malcolm <dmalcolm@redhat.com>
1708 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
1709 now emits two .dot files.
1710 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
1711 (graphviz_out::end_tr): Only close a TR, not a TD.
1712 (graphviz_out::begin_td): New.
1713 (graphviz_out::end_td): New.
1714 (graphviz_out::begin_trtd): New, replacing the old implementation
1715 of graphviz_out::begin_tr.
1716 (graphviz_out::end_tdtr): New, replacing the old implementation
1717 of graphviz_out::end_tr.
1718 * graphviz.h (graphviz_out::begin_td): New decl.
1719 (graphviz_out::end_td): New decl.
1720 (graphviz_out::begin_trtd): New decl.
1721 (graphviz_out::end_tdtr): New decl.
1723 2020-03-27 Richard Biener <rguenther@suse.de>
1726 * dwarf2out.c (should_emit_struct_debug): Return false for
1729 2020-03-27 Richard Biener <rguenther@suse.de>
1731 PR tree-optimization/94352
1732 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
1734 (ssa_propagation_engine::ssa_propagate): ... here after
1735 initializing curr_order.
1737 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
1739 PR tree-optimization/90332
1740 * tree-vect-stmts.c (vector_vector_composition_type): New function.
1741 (get_group_load_store_type): Adjust to call
1742 vector_vector_composition_type, extend it to construct with scalar
1744 (vectorizable_load): Likewise.
1746 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
1748 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
1749 (create_ddg_dep_no_link): Likewise.
1750 (add_cross_iteration_register_deps): Move debug instruction check.
1751 Other minor refactoring.
1752 (add_intra_loop_mem_dep): Do not check for debug instructions.
1753 (add_inter_loop_mem_dep): Likewise.
1754 (build_intra_loop_deps): Likewise.
1755 (create_ddg): Do not include debug insns into the graph.
1756 * ddg.h (struct ddg): Remove num_debug field.
1757 * modulo-sched.c (doloop_register_get): Adjust condition.
1758 (res_MII): Remove DDG num_debug field usage.
1759 (sms_schedule_by_order): Use assertion against debug insns.
1760 (ps_has_conflicts): Drop debug insn check.
1762 2020-03-26 Jakub Jelinek <jakub@redhat.com>
1765 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
1766 that contains exactly one non-DEBUG_BEGIN_STMT statement.
1769 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
1770 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
1771 a single non-debug stmt followed by one or more debug stmts.
1772 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
1773 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
1774 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
1775 gimple_seq_last to check if outer_stmt gbind could be reused and
1776 if yes and it is surrounded by any debug stmts, move them into the
1779 PR rtl-optimization/92264
1780 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
1781 for sp based values in !frame_pointer_needed
1782 && !ACCUMULATE_OUTGOING_ARGS functions.
1784 2020-03-26 Felix Yang <felix.yang@huawei.com>
1786 PR tree-optimization/94269
1787 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
1789 operation to single basic block.
1791 2020-03-25 Jeff Law <law@redhat.com>
1793 PR rtl-optimization/90275
1794 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
1797 2020-03-25 Jakub Jelinek <jakub@redhat.com>
1800 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
1801 mode rather than VOIDmode.
1803 2020-03-25 Martin Sebor <msebor@redhat.com>
1806 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
1807 even for alloca calls resulting from system macro expansion.
1808 Include inlining context in all warnings.
1810 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
1813 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
1814 FPRs to change between SDmode and DDmode.
1816 2020-03-25 Martin Sebor <msebor@redhat.com>
1818 PR tree-optimization/94131
1819 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
1821 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
1822 types have constant sizes.
1824 2020-03-25 Martin Liska <mliska@suse.cz>
1827 * configure.ac: Report error only when --with-zstd
1829 * configure: Regenerate.
1831 2020-03-25 Jakub Jelinek <jakub@redhat.com>
1834 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
1835 INSN_CODE (insn) to -1 when changing the pattern.
1837 2020-03-25 Martin Liska <mliska@suse.cz>
1841 * config/i386/i386-features.c (make_resolver_func): Drop
1842 public flag for resolver.
1843 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
1844 group for resolver and drop public flag if possible.
1845 * multiple_target.c (create_dispatcher_calls): Drop unique_name
1846 and resolution as we want to enable LTO privatization of the default
1849 2020-03-25 Martin Liska <mliska@suse.cz>
1852 * configure.ac: Respect --without-zstd and report
1853 error when we can't find header file with --with-zstd.
1854 * configure: Regenerate.
1856 2020-03-25 Jakub Jelinek <jakub@redhat.com>
1859 * varasm.c (output_constructor_array_range): If local->index
1860 RANGE_EXPR doesn't start at the current location in the constructor,
1861 skip needed number of bytes using assemble_zeros or assert we don't
1865 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
1866 counter instead of DECL_UID.
1868 PR tree-optimization/94300
1869 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
1870 is positive, make sure that off + size isn't larger than needed_len.
1872 2020-03-25 Richard Biener <rguenther@suse.de>
1873 Jakub Jelinek <jakub@redhat.com>
1876 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
1878 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
1880 * doc/sourcebuild.texi (ARM-specific attributes): Add
1882 (Features for dg-add-options): Add arm_fp_dp.
1884 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
1887 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
1889 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
1892 * omp-offload.c (omp_finish_file): Fix target-link handling if
1893 targetm_common.have_named_sections is false.
1895 2020-03-24 Jakub Jelinek <jakub@redhat.com>
1898 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
1902 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
1903 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
1904 If not after and at *incr_pos is a debug stmt, set stmt location to
1905 location of next non-debug stmt after it if any.
1908 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
1909 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
1910 worklist or set GF_PLF_2 just because it is used in a debug stmt in
1911 another bb. Formatting improvements.
1914 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
1915 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
1916 regardless of whether TREE_NO_WARNING is set on it or whether
1917 warn_unused_function is true or not.
1919 2020-03-23 Jeff Law <law@redhat.com>
1921 PR rtl-optimization/90275
1924 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
1925 (simplify_logical_relational_operation): Use it.
1927 2020-03-23 Jakub Jelinek <jakub@redhat.com>
1930 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
1931 ultimate rhs and if returned something different, reconstructing
1934 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
1936 * opts.c (print_filtered_help): Improve the help text for alias options.
1938 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1939 Andre Vieira <andre.simoesdiasvieira@arm.com>
1940 Mihail Ionescu <mihail.ionescu@arm.com>
1942 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
1943 (vshlcq_m_u8): Likewise.
1944 (vshlcq_m_s16): Likewise.
1945 (vshlcq_m_u16): Likewise.
1946 (vshlcq_m_s32): Likewise.
1947 (vshlcq_m_u32): Likewise.
1948 (__arm_vshlcq_m_s8): Define intrinsic.
1949 (__arm_vshlcq_m_u8): Likewise.
1950 (__arm_vshlcq_m_s16): Likewise.
1951 (__arm_vshlcq_m_u16): Likewise.
1952 (__arm_vshlcq_m_s32): Likewise.
1953 (__arm_vshlcq_m_u32): Likewise.
1954 (vshlcq_m): Define polymorphic variant.
1955 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
1956 Use builtin qualifier.
1957 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
1958 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
1959 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
1960 (mve_vshlcq_m_<supf><mode>): Likewise.
1962 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1964 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
1965 (UQSHL_QUALIFIERS): Likewise.
1966 (ASRL_QUALIFIERS): Likewise.
1967 (SQSHL_QUALIFIERS): Likewise.
1968 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
1970 (sqrshr): Define macro.
1971 (sqrshrl): Likewise.
1972 (sqrshrl_sat48): Likewise.
1978 (uqrshll): Likewise.
1979 (uqrshll_sat48): Likewise.
1986 (__arm_lsll): Define intrinsic.
1987 (__arm_asrl): Likewise.
1988 (__arm_uqrshll): Likewise.
1989 (__arm_uqrshll_sat48): Likewise.
1990 (__arm_sqrshrl): Likewise.
1991 (__arm_sqrshrl_sat48): Likewise.
1992 (__arm_uqshll): Likewise.
1993 (__arm_urshrl): Likewise.
1994 (__arm_srshrl): Likewise.
1995 (__arm_sqshll): Likewise.
1996 (__arm_uqrshl): Likewise.
1997 (__arm_sqrshr): Likewise.
1998 (__arm_uqshl): Likewise.
1999 (__arm_urshr): Likewise.
2000 (__arm_sqshl): Likewise.
2001 (__arm_srshr): Likewise.
2002 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
2004 (UQSHL_QUALIFIERS): Likewise.
2005 (ASRL_QUALIFIERS): Likewise.
2006 (SQSHL_QUALIFIERS): Likewise.
2007 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
2008 (mve_sqrshrl_sat<supf>_di): Likewise.
2009 (mve_uqrshl_si): Likewise.
2010 (mve_sqrshr_si): Likewise.
2011 (mve_uqshll_di): Likewise.
2012 (mve_urshrl_di): Likewise.
2013 (mve_uqshl_si): Likewise.
2014 (mve_urshr_si): Likewise.
2015 (mve_sqshl_si): Likewise.
2016 (mve_srshr_si): Likewise.
2017 (mve_srshrl_di): Likewise.
2018 (mve_sqshll_di): Likewise.
2020 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2021 Andre Vieira <andre.simoesdiasvieira@arm.com>
2022 Mihail Ionescu <mihail.ionescu@arm.com>
2024 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
2025 (vsetq_lane_f32): Likewise.
2026 (vsetq_lane_s16): Likewise.
2027 (vsetq_lane_s32): Likewise.
2028 (vsetq_lane_s8): Likewise.
2029 (vsetq_lane_s64): Likewise.
2030 (vsetq_lane_u8): Likewise.
2031 (vsetq_lane_u16): Likewise.
2032 (vsetq_lane_u32): Likewise.
2033 (vsetq_lane_u64): Likewise.
2034 (vgetq_lane_f16): Likewise.
2035 (vgetq_lane_f32): Likewise.
2036 (vgetq_lane_s16): Likewise.
2037 (vgetq_lane_s32): Likewise.
2038 (vgetq_lane_s8): Likewise.
2039 (vgetq_lane_s64): Likewise.
2040 (vgetq_lane_u8): Likewise.
2041 (vgetq_lane_u16): Likewise.
2042 (vgetq_lane_u32): Likewise.
2043 (vgetq_lane_u64): Likewise.
2044 (__ARM_NUM_LANES): Likewise.
2045 (__ARM_LANEQ): Likewise.
2046 (__ARM_CHECK_LANEQ): Likewise.
2047 (__arm_vsetq_lane_s16): Define intrinsic.
2048 (__arm_vsetq_lane_s32): Likewise.
2049 (__arm_vsetq_lane_s8): Likewise.
2050 (__arm_vsetq_lane_s64): Likewise.
2051 (__arm_vsetq_lane_u8): Likewise.
2052 (__arm_vsetq_lane_u16): Likewise.
2053 (__arm_vsetq_lane_u32): Likewise.
2054 (__arm_vsetq_lane_u64): Likewise.
2055 (__arm_vgetq_lane_s16): Likewise.
2056 (__arm_vgetq_lane_s32): Likewise.
2057 (__arm_vgetq_lane_s8): Likewise.
2058 (__arm_vgetq_lane_s64): Likewise.
2059 (__arm_vgetq_lane_u8): Likewise.
2060 (__arm_vgetq_lane_u16): Likewise.
2061 (__arm_vgetq_lane_u32): Likewise.
2062 (__arm_vgetq_lane_u64): Likewise.
2063 (__arm_vsetq_lane_f16): Likewise.
2064 (__arm_vsetq_lane_f32): Likewise.
2065 (__arm_vgetq_lane_f16): Likewise.
2066 (__arm_vgetq_lane_f32): Likewise.
2067 (vgetq_lane): Define polymorphic variant.
2068 (vsetq_lane): Likewise.
2069 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
2071 (mve_vec_extractv2didi): Likewise.
2072 (mve_vec_extract_sext_internal<mode>): Likewise.
2073 (mve_vec_extract_zext_internal<mode>): Likewise.
2074 (mve_vec_set<mode>_internal): Likewise.
2075 (mve_vec_setv2di_internal): Likewise.
2076 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
2078 (vec_extract<mode><V_elem_l>): Rename to
2079 "neon_vec_extract<mode><V_elem_l>".
2080 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
2081 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
2082 pattern common for MVE and NEON.
2083 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
2086 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
2088 * config/arm/mve.md (earlyclobber_32): New mode attribute.
2089 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
2090 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
2092 2020-03-23 Richard Biener <rguenther@suse.de>
2094 PR tree-optimization/94261
2095 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
2096 IL operand swapping code.
2097 (vect_slp_rearrange_stmts): Do not arrange isomorphic
2098 nodes that would need operation code adjustments.
2100 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
2102 * doc/install.texi (amdgcn-*-amdhsa): Renamed
2103 from amdgcn-unknown-amdhsa; change
2104 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
2106 2020-03-23 Richard Biener <rguenther@suse.de>
2109 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
2110 directly rather than also folding it via build_fold_addr_expr.
2112 2020-03-23 Richard Biener <rguenther@suse.de>
2114 PR tree-optimization/94266
2115 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
2116 addresses of TARGET_MEM_REFs.
2118 2020-03-23 Martin Liska <mliska@suse.cz>
2121 * symtab.c (symtab_node::clone_references): Save speculative_id
2122 as ref may be overwritten by create_reference.
2123 (symtab_node::clone_referring): Likewise.
2124 (symtab_node::clone_reference): Likewise.
2126 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
2128 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
2129 references to Darwin.
2130 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
2131 unconditionally and comment on why.
2133 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
2135 * config/darwin.c (darwin_mergeable_constant_section): Collect
2136 section anchor checks into the caller.
2137 (machopic_select_section): Collect section anchor checks into
2138 the determination of 'effective zero-size' objects. When the
2139 size is unknown, assume it is non-zero, and thus return the
2140 'generic' section for the DECL.
2142 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
2145 * gcc/config/darwin.opt: Amend options descriptions.
2147 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
2149 PR rtl-optimization/94052
2150 * lra-constraints.c (simplify_operand_subreg): Reload the inner
2151 register of a paradoxical subreg if simplify_subreg_regno fails
2152 to give a valid hard register for the outer mode.
2154 2020-03-20 Martin Jambor <mjambor@suse.cz>
2156 PR tree-optimization/93435
2157 * params.opt (sra-max-propagations): New parameter.
2158 * tree-sra.c (propagation_budget): New variable.
2159 (budget_for_propagation_access): New function.
2160 (propagate_subaccesses_from_rhs): Use it.
2161 (propagate_subaccesses_from_lhs): Likewise.
2162 (propagate_all_subaccesses): Set up and destroy propagation_budget.
2164 2020-03-20 Carl Love <cel@us.ibm.com>
2167 * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal):
2168 Add check for TARGET_FPRND for Power 7 or newer.
2170 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
2173 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
2174 (cgraph_edge::redirect_callee): Move here; likewise.
2175 (cgraph_node::remove_callees): Update calls_comdat_local flag.
2176 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
2178 (cgraph_node::check_calls_comdat_local_p): New member function.
2179 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
2180 (cgraph_edge::redirect_callee): Move offline.
2181 * ipa-fnsummary.c (compute_fn_summary): Do not compute
2182 calls_comdat_local flag here.
2183 * ipa-inline-transform.c (inline_call): Fix updating of
2184 calls_comdat_local flag.
2185 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
2186 * symtab.c (symtab_node::add_to_same_comdat_group): Update
2187 calls_comdat_local flag.
2189 2020-03-20 Richard Biener <rguenther@suse.de>
2191 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
2192 from the possibly modified root.
2194 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2195 Andre Vieira <andre.simoesdiasvieira@arm.com>
2196 Mihail Ionescu <mihail.ionescu@arm.com>
2198 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
2199 (vst1q_p_s8): Likewise.
2200 (vst2q_s8): Likewise.
2201 (vst2q_u8): Likewise.
2202 (vld1q_z_u8): Likewise.
2203 (vld1q_z_s8): Likewise.
2204 (vld2q_s8): Likewise.
2205 (vld2q_u8): Likewise.
2206 (vld4q_s8): Likewise.
2207 (vld4q_u8): Likewise.
2208 (vst1q_p_u16): Likewise.
2209 (vst1q_p_s16): Likewise.
2210 (vst2q_s16): Likewise.
2211 (vst2q_u16): Likewise.
2212 (vld1q_z_u16): Likewise.
2213 (vld1q_z_s16): Likewise.
2214 (vld2q_s16): Likewise.
2215 (vld2q_u16): Likewise.
2216 (vld4q_s16): Likewise.
2217 (vld4q_u16): Likewise.
2218 (vst1q_p_u32): Likewise.
2219 (vst1q_p_s32): Likewise.
2220 (vst2q_s32): Likewise.
2221 (vst2q_u32): Likewise.
2222 (vld1q_z_u32): Likewise.
2223 (vld1q_z_s32): Likewise.
2224 (vld2q_s32): Likewise.
2225 (vld2q_u32): Likewise.
2226 (vld4q_s32): Likewise.
2227 (vld4q_u32): Likewise.
2228 (vld4q_f16): Likewise.
2229 (vld2q_f16): Likewise.
2230 (vld1q_z_f16): Likewise.
2231 (vst2q_f16): Likewise.
2232 (vst1q_p_f16): Likewise.
2233 (vld4q_f32): Likewise.
2234 (vld2q_f32): Likewise.
2235 (vld1q_z_f32): Likewise.
2236 (vst2q_f32): Likewise.
2237 (vst1q_p_f32): Likewise.
2238 (__arm_vst1q_p_u8): Define intrinsic.
2239 (__arm_vst1q_p_s8): Likewise.
2240 (__arm_vst2q_s8): Likewise.
2241 (__arm_vst2q_u8): Likewise.
2242 (__arm_vld1q_z_u8): Likewise.
2243 (__arm_vld1q_z_s8): Likewise.
2244 (__arm_vld2q_s8): Likewise.
2245 (__arm_vld2q_u8): Likewise.
2246 (__arm_vld4q_s8): Likewise.
2247 (__arm_vld4q_u8): Likewise.
2248 (__arm_vst1q_p_u16): Likewise.
2249 (__arm_vst1q_p_s16): Likewise.
2250 (__arm_vst2q_s16): Likewise.
2251 (__arm_vst2q_u16): Likewise.
2252 (__arm_vld1q_z_u16): Likewise.
2253 (__arm_vld1q_z_s16): Likewise.
2254 (__arm_vld2q_s16): Likewise.
2255 (__arm_vld2q_u16): Likewise.
2256 (__arm_vld4q_s16): Likewise.
2257 (__arm_vld4q_u16): Likewise.
2258 (__arm_vst1q_p_u32): Likewise.
2259 (__arm_vst1q_p_s32): Likewise.
2260 (__arm_vst2q_s32): Likewise.
2261 (__arm_vst2q_u32): Likewise.
2262 (__arm_vld1q_z_u32): Likewise.
2263 (__arm_vld1q_z_s32): Likewise.
2264 (__arm_vld2q_s32): Likewise.
2265 (__arm_vld2q_u32): Likewise.
2266 (__arm_vld4q_s32): Likewise.
2267 (__arm_vld4q_u32): Likewise.
2268 (__arm_vld4q_f16): Likewise.
2269 (__arm_vld2q_f16): Likewise.
2270 (__arm_vld1q_z_f16): Likewise.
2271 (__arm_vst2q_f16): Likewise.
2272 (__arm_vst1q_p_f16): Likewise.
2273 (__arm_vld4q_f32): Likewise.
2274 (__arm_vld2q_f32): Likewise.
2275 (__arm_vld1q_z_f32): Likewise.
2276 (__arm_vst2q_f32): Likewise.
2277 (__arm_vst1q_p_f32): Likewise.
2278 (vld1q_z): Define polymorphic variant.
2281 (vst1q_p): Likewise.
2283 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
2285 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
2286 (mve_vld2q<mode>): Likewise.
2287 (mve_vld4q<mode>): Likewise.
2289 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2290 Andre Vieira <andre.simoesdiasvieira@arm.com>
2291 Mihail Ionescu <mihail.ionescu@arm.com>
2293 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
2294 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
2295 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
2296 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
2297 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
2298 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
2299 * config/arm/arm_mve.h (vadciq_s32): Define macro.
2300 (vadciq_u32): Likewise.
2301 (vadciq_m_s32): Likewise.
2302 (vadciq_m_u32): Likewise.
2303 (vadcq_s32): Likewise.
2304 (vadcq_u32): Likewise.
2305 (vadcq_m_s32): Likewise.
2306 (vadcq_m_u32): Likewise.
2307 (vsbciq_s32): Likewise.
2308 (vsbciq_u32): Likewise.
2309 (vsbciq_m_s32): Likewise.
2310 (vsbciq_m_u32): Likewise.
2311 (vsbcq_s32): Likewise.
2312 (vsbcq_u32): Likewise.
2313 (vsbcq_m_s32): Likewise.
2314 (vsbcq_m_u32): Likewise.
2315 (__arm_vadciq_s32): Define intrinsic.
2316 (__arm_vadciq_u32): Likewise.
2317 (__arm_vadciq_m_s32): Likewise.
2318 (__arm_vadciq_m_u32): Likewise.
2319 (__arm_vadcq_s32): Likewise.
2320 (__arm_vadcq_u32): Likewise.
2321 (__arm_vadcq_m_s32): Likewise.
2322 (__arm_vadcq_m_u32): Likewise.
2323 (__arm_vsbciq_s32): Likewise.
2324 (__arm_vsbciq_u32): Likewise.
2325 (__arm_vsbciq_m_s32): Likewise.
2326 (__arm_vsbciq_m_u32): Likewise.
2327 (__arm_vsbcq_s32): Likewise.
2328 (__arm_vsbcq_u32): Likewise.
2329 (__arm_vsbcq_m_s32): Likewise.
2330 (__arm_vsbcq_m_u32): Likewise.
2331 (vadciq_m): Define polymorphic variant.
2333 (vadcq_m): Likewise.
2335 (vsbciq_m): Likewise.
2337 (vsbcq_m): Likewise.
2339 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
2341 (BINOP_UNONE_UNONE_UNONE): Likewise.
2342 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
2343 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
2344 * config/arm/mve.md (VADCIQ): Define iterator.
2345 (VADCIQ_M): Likewise.
2347 (VSBCQ_M): Likewise.
2349 (VSBCIQ_M): Likewise.
2351 (VADCQ_M): Likewise.
2352 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
2353 (mve_vadciq_<supf>v4si): Likewise.
2354 (mve_vadcq_m_<supf>v4si): Likewise.
2355 (mve_vadcq_<supf>v4si): Likewise.
2356 (mve_vsbciq_m_<supf>v4si): Likewise.
2357 (mve_vsbciq_<supf>v4si): Likewise.
2358 (mve_vsbcq_m_<supf>v4si): Likewise.
2359 (mve_vsbcq_<supf>v4si): Likewise.
2360 (get_fpscr_nzcvqc): Define isns.
2361 (set_fpscr_nzcvqc): Define isns.
2362 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
2363 (UNSPEC_SET_FPSCR_NZCVQC): Define.
2365 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2367 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
2368 (vddupq_x_n_u16): Likewise.
2369 (vddupq_x_n_u32): Likewise.
2370 (vddupq_x_wb_u8): Likewise.
2371 (vddupq_x_wb_u16): Likewise.
2372 (vddupq_x_wb_u32): Likewise.
2373 (vdwdupq_x_n_u8): Likewise.
2374 (vdwdupq_x_n_u16): Likewise.
2375 (vdwdupq_x_n_u32): Likewise.
2376 (vdwdupq_x_wb_u8): Likewise.
2377 (vdwdupq_x_wb_u16): Likewise.
2378 (vdwdupq_x_wb_u32): Likewise.
2379 (vidupq_x_n_u8): Likewise.
2380 (vidupq_x_n_u16): Likewise.
2381 (vidupq_x_n_u32): Likewise.
2382 (vidupq_x_wb_u8): Likewise.
2383 (vidupq_x_wb_u16): Likewise.
2384 (vidupq_x_wb_u32): Likewise.
2385 (viwdupq_x_n_u8): Likewise.
2386 (viwdupq_x_n_u16): Likewise.
2387 (viwdupq_x_n_u32): Likewise.
2388 (viwdupq_x_wb_u8): Likewise.
2389 (viwdupq_x_wb_u16): Likewise.
2390 (viwdupq_x_wb_u32): Likewise.
2391 (vdupq_x_n_s8): Likewise.
2392 (vdupq_x_n_s16): Likewise.
2393 (vdupq_x_n_s32): Likewise.
2394 (vdupq_x_n_u8): Likewise.
2395 (vdupq_x_n_u16): Likewise.
2396 (vdupq_x_n_u32): Likewise.
2397 (vminq_x_s8): Likewise.
2398 (vminq_x_s16): Likewise.
2399 (vminq_x_s32): Likewise.
2400 (vminq_x_u8): Likewise.
2401 (vminq_x_u16): Likewise.
2402 (vminq_x_u32): Likewise.
2403 (vmaxq_x_s8): Likewise.
2404 (vmaxq_x_s16): Likewise.
2405 (vmaxq_x_s32): Likewise.
2406 (vmaxq_x_u8): Likewise.
2407 (vmaxq_x_u16): Likewise.
2408 (vmaxq_x_u32): Likewise.
2409 (vabdq_x_s8): Likewise.
2410 (vabdq_x_s16): Likewise.
2411 (vabdq_x_s32): Likewise.
2412 (vabdq_x_u8): Likewise.
2413 (vabdq_x_u16): Likewise.
2414 (vabdq_x_u32): Likewise.
2415 (vabsq_x_s8): Likewise.
2416 (vabsq_x_s16): Likewise.
2417 (vabsq_x_s32): Likewise.
2418 (vaddq_x_s8): Likewise.
2419 (vaddq_x_s16): Likewise.
2420 (vaddq_x_s32): Likewise.
2421 (vaddq_x_n_s8): Likewise.
2422 (vaddq_x_n_s16): Likewise.
2423 (vaddq_x_n_s32): Likewise.
2424 (vaddq_x_u8): Likewise.
2425 (vaddq_x_u16): Likewise.
2426 (vaddq_x_u32): Likewise.
2427 (vaddq_x_n_u8): Likewise.
2428 (vaddq_x_n_u16): Likewise.
2429 (vaddq_x_n_u32): Likewise.
2430 (vclsq_x_s8): Likewise.
2431 (vclsq_x_s16): Likewise.
2432 (vclsq_x_s32): Likewise.
2433 (vclzq_x_s8): Likewise.
2434 (vclzq_x_s16): Likewise.
2435 (vclzq_x_s32): Likewise.
2436 (vclzq_x_u8): Likewise.
2437 (vclzq_x_u16): Likewise.
2438 (vclzq_x_u32): Likewise.
2439 (vnegq_x_s8): Likewise.
2440 (vnegq_x_s16): Likewise.
2441 (vnegq_x_s32): Likewise.
2442 (vmulhq_x_s8): Likewise.
2443 (vmulhq_x_s16): Likewise.
2444 (vmulhq_x_s32): Likewise.
2445 (vmulhq_x_u8): Likewise.
2446 (vmulhq_x_u16): Likewise.
2447 (vmulhq_x_u32): Likewise.
2448 (vmullbq_poly_x_p8): Likewise.
2449 (vmullbq_poly_x_p16): Likewise.
2450 (vmullbq_int_x_s8): Likewise.
2451 (vmullbq_int_x_s16): Likewise.
2452 (vmullbq_int_x_s32): Likewise.
2453 (vmullbq_int_x_u8): Likewise.
2454 (vmullbq_int_x_u16): Likewise.
2455 (vmullbq_int_x_u32): Likewise.
2456 (vmulltq_poly_x_p8): Likewise.
2457 (vmulltq_poly_x_p16): Likewise.
2458 (vmulltq_int_x_s8): Likewise.
2459 (vmulltq_int_x_s16): Likewise.
2460 (vmulltq_int_x_s32): Likewise.
2461 (vmulltq_int_x_u8): Likewise.
2462 (vmulltq_int_x_u16): Likewise.
2463 (vmulltq_int_x_u32): Likewise.
2464 (vmulq_x_s8): Likewise.
2465 (vmulq_x_s16): Likewise.
2466 (vmulq_x_s32): Likewise.
2467 (vmulq_x_n_s8): Likewise.
2468 (vmulq_x_n_s16): Likewise.
2469 (vmulq_x_n_s32): Likewise.
2470 (vmulq_x_u8): Likewise.
2471 (vmulq_x_u16): Likewise.
2472 (vmulq_x_u32): Likewise.
2473 (vmulq_x_n_u8): Likewise.
2474 (vmulq_x_n_u16): Likewise.
2475 (vmulq_x_n_u32): Likewise.
2476 (vsubq_x_s8): Likewise.
2477 (vsubq_x_s16): Likewise.
2478 (vsubq_x_s32): Likewise.
2479 (vsubq_x_n_s8): Likewise.
2480 (vsubq_x_n_s16): Likewise.
2481 (vsubq_x_n_s32): Likewise.
2482 (vsubq_x_u8): Likewise.
2483 (vsubq_x_u16): Likewise.
2484 (vsubq_x_u32): Likewise.
2485 (vsubq_x_n_u8): Likewise.
2486 (vsubq_x_n_u16): Likewise.
2487 (vsubq_x_n_u32): Likewise.
2488 (vcaddq_rot90_x_s8): Likewise.
2489 (vcaddq_rot90_x_s16): Likewise.
2490 (vcaddq_rot90_x_s32): Likewise.
2491 (vcaddq_rot90_x_u8): Likewise.
2492 (vcaddq_rot90_x_u16): Likewise.
2493 (vcaddq_rot90_x_u32): Likewise.
2494 (vcaddq_rot270_x_s8): Likewise.
2495 (vcaddq_rot270_x_s16): Likewise.
2496 (vcaddq_rot270_x_s32): Likewise.
2497 (vcaddq_rot270_x_u8): Likewise.
2498 (vcaddq_rot270_x_u16): Likewise.
2499 (vcaddq_rot270_x_u32): Likewise.
2500 (vhaddq_x_n_s8): Likewise.
2501 (vhaddq_x_n_s16): Likewise.
2502 (vhaddq_x_n_s32): Likewise.
2503 (vhaddq_x_n_u8): Likewise.
2504 (vhaddq_x_n_u16): Likewise.
2505 (vhaddq_x_n_u32): Likewise.
2506 (vhaddq_x_s8): Likewise.
2507 (vhaddq_x_s16): Likewise.
2508 (vhaddq_x_s32): Likewise.
2509 (vhaddq_x_u8): Likewise.
2510 (vhaddq_x_u16): Likewise.
2511 (vhaddq_x_u32): Likewise.
2512 (vhcaddq_rot90_x_s8): Likewise.
2513 (vhcaddq_rot90_x_s16): Likewise.
2514 (vhcaddq_rot90_x_s32): Likewise.
2515 (vhcaddq_rot270_x_s8): Likewise.
2516 (vhcaddq_rot270_x_s16): Likewise.
2517 (vhcaddq_rot270_x_s32): Likewise.
2518 (vhsubq_x_n_s8): Likewise.
2519 (vhsubq_x_n_s16): Likewise.
2520 (vhsubq_x_n_s32): Likewise.
2521 (vhsubq_x_n_u8): Likewise.
2522 (vhsubq_x_n_u16): Likewise.
2523 (vhsubq_x_n_u32): Likewise.
2524 (vhsubq_x_s8): Likewise.
2525 (vhsubq_x_s16): Likewise.
2526 (vhsubq_x_s32): Likewise.
2527 (vhsubq_x_u8): Likewise.
2528 (vhsubq_x_u16): Likewise.
2529 (vhsubq_x_u32): Likewise.
2530 (vrhaddq_x_s8): Likewise.
2531 (vrhaddq_x_s16): Likewise.
2532 (vrhaddq_x_s32): Likewise.
2533 (vrhaddq_x_u8): Likewise.
2534 (vrhaddq_x_u16): Likewise.
2535 (vrhaddq_x_u32): Likewise.
2536 (vrmulhq_x_s8): Likewise.
2537 (vrmulhq_x_s16): Likewise.
2538 (vrmulhq_x_s32): Likewise.
2539 (vrmulhq_x_u8): Likewise.
2540 (vrmulhq_x_u16): Likewise.
2541 (vrmulhq_x_u32): Likewise.
2542 (vandq_x_s8): Likewise.
2543 (vandq_x_s16): Likewise.
2544 (vandq_x_s32): Likewise.
2545 (vandq_x_u8): Likewise.
2546 (vandq_x_u16): Likewise.
2547 (vandq_x_u32): Likewise.
2548 (vbicq_x_s8): Likewise.
2549 (vbicq_x_s16): Likewise.
2550 (vbicq_x_s32): Likewise.
2551 (vbicq_x_u8): Likewise.
2552 (vbicq_x_u16): Likewise.
2553 (vbicq_x_u32): Likewise.
2554 (vbrsrq_x_n_s8): Likewise.
2555 (vbrsrq_x_n_s16): Likewise.
2556 (vbrsrq_x_n_s32): Likewise.
2557 (vbrsrq_x_n_u8): Likewise.
2558 (vbrsrq_x_n_u16): Likewise.
2559 (vbrsrq_x_n_u32): Likewise.
2560 (veorq_x_s8): Likewise.
2561 (veorq_x_s16): Likewise.
2562 (veorq_x_s32): Likewise.
2563 (veorq_x_u8): Likewise.
2564 (veorq_x_u16): Likewise.
2565 (veorq_x_u32): Likewise.
2566 (vmovlbq_x_s8): Likewise.
2567 (vmovlbq_x_s16): Likewise.
2568 (vmovlbq_x_u8): Likewise.
2569 (vmovlbq_x_u16): Likewise.
2570 (vmovltq_x_s8): Likewise.
2571 (vmovltq_x_s16): Likewise.
2572 (vmovltq_x_u8): Likewise.
2573 (vmovltq_x_u16): Likewise.
2574 (vmvnq_x_s8): Likewise.
2575 (vmvnq_x_s16): Likewise.
2576 (vmvnq_x_s32): Likewise.
2577 (vmvnq_x_u8): Likewise.
2578 (vmvnq_x_u16): Likewise.
2579 (vmvnq_x_u32): Likewise.
2580 (vmvnq_x_n_s16): Likewise.
2581 (vmvnq_x_n_s32): Likewise.
2582 (vmvnq_x_n_u16): Likewise.
2583 (vmvnq_x_n_u32): Likewise.
2584 (vornq_x_s8): Likewise.
2585 (vornq_x_s16): Likewise.
2586 (vornq_x_s32): Likewise.
2587 (vornq_x_u8): Likewise.
2588 (vornq_x_u16): Likewise.
2589 (vornq_x_u32): Likewise.
2590 (vorrq_x_s8): Likewise.
2591 (vorrq_x_s16): Likewise.
2592 (vorrq_x_s32): Likewise.
2593 (vorrq_x_u8): Likewise.
2594 (vorrq_x_u16): Likewise.
2595 (vorrq_x_u32): Likewise.
2596 (vrev16q_x_s8): Likewise.
2597 (vrev16q_x_u8): Likewise.
2598 (vrev32q_x_s8): Likewise.
2599 (vrev32q_x_s16): Likewise.
2600 (vrev32q_x_u8): Likewise.
2601 (vrev32q_x_u16): Likewise.
2602 (vrev64q_x_s8): Likewise.
2603 (vrev64q_x_s16): Likewise.
2604 (vrev64q_x_s32): Likewise.
2605 (vrev64q_x_u8): Likewise.
2606 (vrev64q_x_u16): Likewise.
2607 (vrev64q_x_u32): Likewise.
2608 (vrshlq_x_s8): Likewise.
2609 (vrshlq_x_s16): Likewise.
2610 (vrshlq_x_s32): Likewise.
2611 (vrshlq_x_u8): Likewise.
2612 (vrshlq_x_u16): Likewise.
2613 (vrshlq_x_u32): Likewise.
2614 (vshllbq_x_n_s8): Likewise.
2615 (vshllbq_x_n_s16): Likewise.
2616 (vshllbq_x_n_u8): Likewise.
2617 (vshllbq_x_n_u16): Likewise.
2618 (vshlltq_x_n_s8): Likewise.
2619 (vshlltq_x_n_s16): Likewise.
2620 (vshlltq_x_n_u8): Likewise.
2621 (vshlltq_x_n_u16): Likewise.
2622 (vshlq_x_s8): Likewise.
2623 (vshlq_x_s16): Likewise.
2624 (vshlq_x_s32): Likewise.
2625 (vshlq_x_u8): Likewise.
2626 (vshlq_x_u16): Likewise.
2627 (vshlq_x_u32): Likewise.
2628 (vshlq_x_n_s8): Likewise.
2629 (vshlq_x_n_s16): Likewise.
2630 (vshlq_x_n_s32): Likewise.
2631 (vshlq_x_n_u8): Likewise.
2632 (vshlq_x_n_u16): Likewise.
2633 (vshlq_x_n_u32): Likewise.
2634 (vrshrq_x_n_s8): Likewise.
2635 (vrshrq_x_n_s16): Likewise.
2636 (vrshrq_x_n_s32): Likewise.
2637 (vrshrq_x_n_u8): Likewise.
2638 (vrshrq_x_n_u16): Likewise.
2639 (vrshrq_x_n_u32): Likewise.
2640 (vshrq_x_n_s8): Likewise.
2641 (vshrq_x_n_s16): Likewise.
2642 (vshrq_x_n_s32): Likewise.
2643 (vshrq_x_n_u8): Likewise.
2644 (vshrq_x_n_u16): Likewise.
2645 (vshrq_x_n_u32): Likewise.
2646 (vdupq_x_n_f16): Likewise.
2647 (vdupq_x_n_f32): Likewise.
2648 (vminnmq_x_f16): Likewise.
2649 (vminnmq_x_f32): Likewise.
2650 (vmaxnmq_x_f16): Likewise.
2651 (vmaxnmq_x_f32): Likewise.
2652 (vabdq_x_f16): Likewise.
2653 (vabdq_x_f32): Likewise.
2654 (vabsq_x_f16): Likewise.
2655 (vabsq_x_f32): Likewise.
2656 (vaddq_x_f16): Likewise.
2657 (vaddq_x_f32): Likewise.
2658 (vaddq_x_n_f16): Likewise.
2659 (vaddq_x_n_f32): Likewise.
2660 (vnegq_x_f16): Likewise.
2661 (vnegq_x_f32): Likewise.
2662 (vmulq_x_f16): Likewise.
2663 (vmulq_x_f32): Likewise.
2664 (vmulq_x_n_f16): Likewise.
2665 (vmulq_x_n_f32): Likewise.
2666 (vsubq_x_f16): Likewise.
2667 (vsubq_x_f32): Likewise.
2668 (vsubq_x_n_f16): Likewise.
2669 (vsubq_x_n_f32): Likewise.
2670 (vcaddq_rot90_x_f16): Likewise.
2671 (vcaddq_rot90_x_f32): Likewise.
2672 (vcaddq_rot270_x_f16): Likewise.
2673 (vcaddq_rot270_x_f32): Likewise.
2674 (vcmulq_x_f16): Likewise.
2675 (vcmulq_x_f32): Likewise.
2676 (vcmulq_rot90_x_f16): Likewise.
2677 (vcmulq_rot90_x_f32): Likewise.
2678 (vcmulq_rot180_x_f16): Likewise.
2679 (vcmulq_rot180_x_f32): Likewise.
2680 (vcmulq_rot270_x_f16): Likewise.
2681 (vcmulq_rot270_x_f32): Likewise.
2682 (vcvtaq_x_s16_f16): Likewise.
2683 (vcvtaq_x_s32_f32): Likewise.
2684 (vcvtaq_x_u16_f16): Likewise.
2685 (vcvtaq_x_u32_f32): Likewise.
2686 (vcvtnq_x_s16_f16): Likewise.
2687 (vcvtnq_x_s32_f32): Likewise.
2688 (vcvtnq_x_u16_f16): Likewise.
2689 (vcvtnq_x_u32_f32): Likewise.
2690 (vcvtpq_x_s16_f16): Likewise.
2691 (vcvtpq_x_s32_f32): Likewise.
2692 (vcvtpq_x_u16_f16): Likewise.
2693 (vcvtpq_x_u32_f32): Likewise.
2694 (vcvtmq_x_s16_f16): Likewise.
2695 (vcvtmq_x_s32_f32): Likewise.
2696 (vcvtmq_x_u16_f16): Likewise.
2697 (vcvtmq_x_u32_f32): Likewise.
2698 (vcvtbq_x_f32_f16): Likewise.
2699 (vcvttq_x_f32_f16): Likewise.
2700 (vcvtq_x_f16_u16): Likewise.
2701 (vcvtq_x_f16_s16): Likewise.
2702 (vcvtq_x_f32_s32): Likewise.
2703 (vcvtq_x_f32_u32): Likewise.
2704 (vcvtq_x_n_f16_s16): Likewise.
2705 (vcvtq_x_n_f16_u16): Likewise.
2706 (vcvtq_x_n_f32_s32): Likewise.
2707 (vcvtq_x_n_f32_u32): Likewise.
2708 (vcvtq_x_s16_f16): Likewise.
2709 (vcvtq_x_s32_f32): Likewise.
2710 (vcvtq_x_u16_f16): Likewise.
2711 (vcvtq_x_u32_f32): Likewise.
2712 (vcvtq_x_n_s16_f16): Likewise.
2713 (vcvtq_x_n_s32_f32): Likewise.
2714 (vcvtq_x_n_u16_f16): Likewise.
2715 (vcvtq_x_n_u32_f32): Likewise.
2716 (vrndq_x_f16): Likewise.
2717 (vrndq_x_f32): Likewise.
2718 (vrndnq_x_f16): Likewise.
2719 (vrndnq_x_f32): Likewise.
2720 (vrndmq_x_f16): Likewise.
2721 (vrndmq_x_f32): Likewise.
2722 (vrndpq_x_f16): Likewise.
2723 (vrndpq_x_f32): Likewise.
2724 (vrndaq_x_f16): Likewise.
2725 (vrndaq_x_f32): Likewise.
2726 (vrndxq_x_f16): Likewise.
2727 (vrndxq_x_f32): Likewise.
2728 (vandq_x_f16): Likewise.
2729 (vandq_x_f32): Likewise.
2730 (vbicq_x_f16): Likewise.
2731 (vbicq_x_f32): Likewise.
2732 (vbrsrq_x_n_f16): Likewise.
2733 (vbrsrq_x_n_f32): Likewise.
2734 (veorq_x_f16): Likewise.
2735 (veorq_x_f32): Likewise.
2736 (vornq_x_f16): Likewise.
2737 (vornq_x_f32): Likewise.
2738 (vorrq_x_f16): Likewise.
2739 (vorrq_x_f32): Likewise.
2740 (vrev32q_x_f16): Likewise.
2741 (vrev64q_x_f16): Likewise.
2742 (vrev64q_x_f32): Likewise.
2743 (__arm_vddupq_x_n_u8): Define intrinsic.
2744 (__arm_vddupq_x_n_u16): Likewise.
2745 (__arm_vddupq_x_n_u32): Likewise.
2746 (__arm_vddupq_x_wb_u8): Likewise.
2747 (__arm_vddupq_x_wb_u16): Likewise.
2748 (__arm_vddupq_x_wb_u32): Likewise.
2749 (__arm_vdwdupq_x_n_u8): Likewise.
2750 (__arm_vdwdupq_x_n_u16): Likewise.
2751 (__arm_vdwdupq_x_n_u32): Likewise.
2752 (__arm_vdwdupq_x_wb_u8): Likewise.
2753 (__arm_vdwdupq_x_wb_u16): Likewise.
2754 (__arm_vdwdupq_x_wb_u32): Likewise.
2755 (__arm_vidupq_x_n_u8): Likewise.
2756 (__arm_vidupq_x_n_u16): Likewise.
2757 (__arm_vidupq_x_n_u32): Likewise.
2758 (__arm_vidupq_x_wb_u8): Likewise.
2759 (__arm_vidupq_x_wb_u16): Likewise.
2760 (__arm_vidupq_x_wb_u32): Likewise.
2761 (__arm_viwdupq_x_n_u8): Likewise.
2762 (__arm_viwdupq_x_n_u16): Likewise.
2763 (__arm_viwdupq_x_n_u32): Likewise.
2764 (__arm_viwdupq_x_wb_u8): Likewise.
2765 (__arm_viwdupq_x_wb_u16): Likewise.
2766 (__arm_viwdupq_x_wb_u32): Likewise.
2767 (__arm_vdupq_x_n_s8): Likewise.
2768 (__arm_vdupq_x_n_s16): Likewise.
2769 (__arm_vdupq_x_n_s32): Likewise.
2770 (__arm_vdupq_x_n_u8): Likewise.
2771 (__arm_vdupq_x_n_u16): Likewise.
2772 (__arm_vdupq_x_n_u32): Likewise.
2773 (__arm_vminq_x_s8): Likewise.
2774 (__arm_vminq_x_s16): Likewise.
2775 (__arm_vminq_x_s32): Likewise.
2776 (__arm_vminq_x_u8): Likewise.
2777 (__arm_vminq_x_u16): Likewise.
2778 (__arm_vminq_x_u32): Likewise.
2779 (__arm_vmaxq_x_s8): Likewise.
2780 (__arm_vmaxq_x_s16): Likewise.
2781 (__arm_vmaxq_x_s32): Likewise.
2782 (__arm_vmaxq_x_u8): Likewise.
2783 (__arm_vmaxq_x_u16): Likewise.
2784 (__arm_vmaxq_x_u32): Likewise.
2785 (__arm_vabdq_x_s8): Likewise.
2786 (__arm_vabdq_x_s16): Likewise.
2787 (__arm_vabdq_x_s32): Likewise.
2788 (__arm_vabdq_x_u8): Likewise.
2789 (__arm_vabdq_x_u16): Likewise.
2790 (__arm_vabdq_x_u32): Likewise.
2791 (__arm_vabsq_x_s8): Likewise.
2792 (__arm_vabsq_x_s16): Likewise.
2793 (__arm_vabsq_x_s32): Likewise.
2794 (__arm_vaddq_x_s8): Likewise.
2795 (__arm_vaddq_x_s16): Likewise.
2796 (__arm_vaddq_x_s32): Likewise.
2797 (__arm_vaddq_x_n_s8): Likewise.
2798 (__arm_vaddq_x_n_s16): Likewise.
2799 (__arm_vaddq_x_n_s32): Likewise.
2800 (__arm_vaddq_x_u8): Likewise.
2801 (__arm_vaddq_x_u16): Likewise.
2802 (__arm_vaddq_x_u32): Likewise.
2803 (__arm_vaddq_x_n_u8): Likewise.
2804 (__arm_vaddq_x_n_u16): Likewise.
2805 (__arm_vaddq_x_n_u32): Likewise.
2806 (__arm_vclsq_x_s8): Likewise.
2807 (__arm_vclsq_x_s16): Likewise.
2808 (__arm_vclsq_x_s32): Likewise.
2809 (__arm_vclzq_x_s8): Likewise.
2810 (__arm_vclzq_x_s16): Likewise.
2811 (__arm_vclzq_x_s32): Likewise.
2812 (__arm_vclzq_x_u8): Likewise.
2813 (__arm_vclzq_x_u16): Likewise.
2814 (__arm_vclzq_x_u32): Likewise.
2815 (__arm_vnegq_x_s8): Likewise.
2816 (__arm_vnegq_x_s16): Likewise.
2817 (__arm_vnegq_x_s32): Likewise.
2818 (__arm_vmulhq_x_s8): Likewise.
2819 (__arm_vmulhq_x_s16): Likewise.
2820 (__arm_vmulhq_x_s32): Likewise.
2821 (__arm_vmulhq_x_u8): Likewise.
2822 (__arm_vmulhq_x_u16): Likewise.
2823 (__arm_vmulhq_x_u32): Likewise.
2824 (__arm_vmullbq_poly_x_p8): Likewise.
2825 (__arm_vmullbq_poly_x_p16): Likewise.
2826 (__arm_vmullbq_int_x_s8): Likewise.
2827 (__arm_vmullbq_int_x_s16): Likewise.
2828 (__arm_vmullbq_int_x_s32): Likewise.
2829 (__arm_vmullbq_int_x_u8): Likewise.
2830 (__arm_vmullbq_int_x_u16): Likewise.
2831 (__arm_vmullbq_int_x_u32): Likewise.
2832 (__arm_vmulltq_poly_x_p8): Likewise.
2833 (__arm_vmulltq_poly_x_p16): Likewise.
2834 (__arm_vmulltq_int_x_s8): Likewise.
2835 (__arm_vmulltq_int_x_s16): Likewise.
2836 (__arm_vmulltq_int_x_s32): Likewise.
2837 (__arm_vmulltq_int_x_u8): Likewise.
2838 (__arm_vmulltq_int_x_u16): Likewise.
2839 (__arm_vmulltq_int_x_u32): Likewise.
2840 (__arm_vmulq_x_s8): Likewise.
2841 (__arm_vmulq_x_s16): Likewise.
2842 (__arm_vmulq_x_s32): Likewise.
2843 (__arm_vmulq_x_n_s8): Likewise.
2844 (__arm_vmulq_x_n_s16): Likewise.
2845 (__arm_vmulq_x_n_s32): Likewise.
2846 (__arm_vmulq_x_u8): Likewise.
2847 (__arm_vmulq_x_u16): Likewise.
2848 (__arm_vmulq_x_u32): Likewise.
2849 (__arm_vmulq_x_n_u8): Likewise.
2850 (__arm_vmulq_x_n_u16): Likewise.
2851 (__arm_vmulq_x_n_u32): Likewise.
2852 (__arm_vsubq_x_s8): Likewise.
2853 (__arm_vsubq_x_s16): Likewise.
2854 (__arm_vsubq_x_s32): Likewise.
2855 (__arm_vsubq_x_n_s8): Likewise.
2856 (__arm_vsubq_x_n_s16): Likewise.
2857 (__arm_vsubq_x_n_s32): Likewise.
2858 (__arm_vsubq_x_u8): Likewise.
2859 (__arm_vsubq_x_u16): Likewise.
2860 (__arm_vsubq_x_u32): Likewise.
2861 (__arm_vsubq_x_n_u8): Likewise.
2862 (__arm_vsubq_x_n_u16): Likewise.
2863 (__arm_vsubq_x_n_u32): Likewise.
2864 (__arm_vcaddq_rot90_x_s8): Likewise.
2865 (__arm_vcaddq_rot90_x_s16): Likewise.
2866 (__arm_vcaddq_rot90_x_s32): Likewise.
2867 (__arm_vcaddq_rot90_x_u8): Likewise.
2868 (__arm_vcaddq_rot90_x_u16): Likewise.
2869 (__arm_vcaddq_rot90_x_u32): Likewise.
2870 (__arm_vcaddq_rot270_x_s8): Likewise.
2871 (__arm_vcaddq_rot270_x_s16): Likewise.
2872 (__arm_vcaddq_rot270_x_s32): Likewise.
2873 (__arm_vcaddq_rot270_x_u8): Likewise.
2874 (__arm_vcaddq_rot270_x_u16): Likewise.
2875 (__arm_vcaddq_rot270_x_u32): Likewise.
2876 (__arm_vhaddq_x_n_s8): Likewise.
2877 (__arm_vhaddq_x_n_s16): Likewise.
2878 (__arm_vhaddq_x_n_s32): Likewise.
2879 (__arm_vhaddq_x_n_u8): Likewise.
2880 (__arm_vhaddq_x_n_u16): Likewise.
2881 (__arm_vhaddq_x_n_u32): Likewise.
2882 (__arm_vhaddq_x_s8): Likewise.
2883 (__arm_vhaddq_x_s16): Likewise.
2884 (__arm_vhaddq_x_s32): Likewise.
2885 (__arm_vhaddq_x_u8): Likewise.
2886 (__arm_vhaddq_x_u16): Likewise.
2887 (__arm_vhaddq_x_u32): Likewise.
2888 (__arm_vhcaddq_rot90_x_s8): Likewise.
2889 (__arm_vhcaddq_rot90_x_s16): Likewise.
2890 (__arm_vhcaddq_rot90_x_s32): Likewise.
2891 (__arm_vhcaddq_rot270_x_s8): Likewise.
2892 (__arm_vhcaddq_rot270_x_s16): Likewise.
2893 (__arm_vhcaddq_rot270_x_s32): Likewise.
2894 (__arm_vhsubq_x_n_s8): Likewise.
2895 (__arm_vhsubq_x_n_s16): Likewise.
2896 (__arm_vhsubq_x_n_s32): Likewise.
2897 (__arm_vhsubq_x_n_u8): Likewise.
2898 (__arm_vhsubq_x_n_u16): Likewise.
2899 (__arm_vhsubq_x_n_u32): Likewise.
2900 (__arm_vhsubq_x_s8): Likewise.
2901 (__arm_vhsubq_x_s16): Likewise.
2902 (__arm_vhsubq_x_s32): Likewise.
2903 (__arm_vhsubq_x_u8): Likewise.
2904 (__arm_vhsubq_x_u16): Likewise.
2905 (__arm_vhsubq_x_u32): Likewise.
2906 (__arm_vrhaddq_x_s8): Likewise.
2907 (__arm_vrhaddq_x_s16): Likewise.
2908 (__arm_vrhaddq_x_s32): Likewise.
2909 (__arm_vrhaddq_x_u8): Likewise.
2910 (__arm_vrhaddq_x_u16): Likewise.
2911 (__arm_vrhaddq_x_u32): Likewise.
2912 (__arm_vrmulhq_x_s8): Likewise.
2913 (__arm_vrmulhq_x_s16): Likewise.
2914 (__arm_vrmulhq_x_s32): Likewise.
2915 (__arm_vrmulhq_x_u8): Likewise.
2916 (__arm_vrmulhq_x_u16): Likewise.
2917 (__arm_vrmulhq_x_u32): Likewise.
2918 (__arm_vandq_x_s8): Likewise.
2919 (__arm_vandq_x_s16): Likewise.
2920 (__arm_vandq_x_s32): Likewise.
2921 (__arm_vandq_x_u8): Likewise.
2922 (__arm_vandq_x_u16): Likewise.
2923 (__arm_vandq_x_u32): Likewise.
2924 (__arm_vbicq_x_s8): Likewise.
2925 (__arm_vbicq_x_s16): Likewise.
2926 (__arm_vbicq_x_s32): Likewise.
2927 (__arm_vbicq_x_u8): Likewise.
2928 (__arm_vbicq_x_u16): Likewise.
2929 (__arm_vbicq_x_u32): Likewise.
2930 (__arm_vbrsrq_x_n_s8): Likewise.
2931 (__arm_vbrsrq_x_n_s16): Likewise.
2932 (__arm_vbrsrq_x_n_s32): Likewise.
2933 (__arm_vbrsrq_x_n_u8): Likewise.
2934 (__arm_vbrsrq_x_n_u16): Likewise.
2935 (__arm_vbrsrq_x_n_u32): Likewise.
2936 (__arm_veorq_x_s8): Likewise.
2937 (__arm_veorq_x_s16): Likewise.
2938 (__arm_veorq_x_s32): Likewise.
2939 (__arm_veorq_x_u8): Likewise.
2940 (__arm_veorq_x_u16): Likewise.
2941 (__arm_veorq_x_u32): Likewise.
2942 (__arm_vmovlbq_x_s8): Likewise.
2943 (__arm_vmovlbq_x_s16): Likewise.
2944 (__arm_vmovlbq_x_u8): Likewise.
2945 (__arm_vmovlbq_x_u16): Likewise.
2946 (__arm_vmovltq_x_s8): Likewise.
2947 (__arm_vmovltq_x_s16): Likewise.
2948 (__arm_vmovltq_x_u8): Likewise.
2949 (__arm_vmovltq_x_u16): Likewise.
2950 (__arm_vmvnq_x_s8): Likewise.
2951 (__arm_vmvnq_x_s16): Likewise.
2952 (__arm_vmvnq_x_s32): Likewise.
2953 (__arm_vmvnq_x_u8): Likewise.
2954 (__arm_vmvnq_x_u16): Likewise.
2955 (__arm_vmvnq_x_u32): Likewise.
2956 (__arm_vmvnq_x_n_s16): Likewise.
2957 (__arm_vmvnq_x_n_s32): Likewise.
2958 (__arm_vmvnq_x_n_u16): Likewise.
2959 (__arm_vmvnq_x_n_u32): Likewise.
2960 (__arm_vornq_x_s8): Likewise.
2961 (__arm_vornq_x_s16): Likewise.
2962 (__arm_vornq_x_s32): Likewise.
2963 (__arm_vornq_x_u8): Likewise.
2964 (__arm_vornq_x_u16): Likewise.
2965 (__arm_vornq_x_u32): Likewise.
2966 (__arm_vorrq_x_s8): Likewise.
2967 (__arm_vorrq_x_s16): Likewise.
2968 (__arm_vorrq_x_s32): Likewise.
2969 (__arm_vorrq_x_u8): Likewise.
2970 (__arm_vorrq_x_u16): Likewise.
2971 (__arm_vorrq_x_u32): Likewise.
2972 (__arm_vrev16q_x_s8): Likewise.
2973 (__arm_vrev16q_x_u8): Likewise.
2974 (__arm_vrev32q_x_s8): Likewise.
2975 (__arm_vrev32q_x_s16): Likewise.
2976 (__arm_vrev32q_x_u8): Likewise.
2977 (__arm_vrev32q_x_u16): Likewise.
2978 (__arm_vrev64q_x_s8): Likewise.
2979 (__arm_vrev64q_x_s16): Likewise.
2980 (__arm_vrev64q_x_s32): Likewise.
2981 (__arm_vrev64q_x_u8): Likewise.
2982 (__arm_vrev64q_x_u16): Likewise.
2983 (__arm_vrev64q_x_u32): Likewise.
2984 (__arm_vrshlq_x_s8): Likewise.
2985 (__arm_vrshlq_x_s16): Likewise.
2986 (__arm_vrshlq_x_s32): Likewise.
2987 (__arm_vrshlq_x_u8): Likewise.
2988 (__arm_vrshlq_x_u16): Likewise.
2989 (__arm_vrshlq_x_u32): Likewise.
2990 (__arm_vshllbq_x_n_s8): Likewise.
2991 (__arm_vshllbq_x_n_s16): Likewise.
2992 (__arm_vshllbq_x_n_u8): Likewise.
2993 (__arm_vshllbq_x_n_u16): Likewise.
2994 (__arm_vshlltq_x_n_s8): Likewise.
2995 (__arm_vshlltq_x_n_s16): Likewise.
2996 (__arm_vshlltq_x_n_u8): Likewise.
2997 (__arm_vshlltq_x_n_u16): Likewise.
2998 (__arm_vshlq_x_s8): Likewise.
2999 (__arm_vshlq_x_s16): Likewise.
3000 (__arm_vshlq_x_s32): Likewise.
3001 (__arm_vshlq_x_u8): Likewise.
3002 (__arm_vshlq_x_u16): Likewise.
3003 (__arm_vshlq_x_u32): Likewise.
3004 (__arm_vshlq_x_n_s8): Likewise.
3005 (__arm_vshlq_x_n_s16): Likewise.
3006 (__arm_vshlq_x_n_s32): Likewise.
3007 (__arm_vshlq_x_n_u8): Likewise.
3008 (__arm_vshlq_x_n_u16): Likewise.
3009 (__arm_vshlq_x_n_u32): Likewise.
3010 (__arm_vrshrq_x_n_s8): Likewise.
3011 (__arm_vrshrq_x_n_s16): Likewise.
3012 (__arm_vrshrq_x_n_s32): Likewise.
3013 (__arm_vrshrq_x_n_u8): Likewise.
3014 (__arm_vrshrq_x_n_u16): Likewise.
3015 (__arm_vrshrq_x_n_u32): Likewise.
3016 (__arm_vshrq_x_n_s8): Likewise.
3017 (__arm_vshrq_x_n_s16): Likewise.
3018 (__arm_vshrq_x_n_s32): Likewise.
3019 (__arm_vshrq_x_n_u8): Likewise.
3020 (__arm_vshrq_x_n_u16): Likewise.
3021 (__arm_vshrq_x_n_u32): Likewise.
3022 (__arm_vdupq_x_n_f16): Likewise.
3023 (__arm_vdupq_x_n_f32): Likewise.
3024 (__arm_vminnmq_x_f16): Likewise.
3025 (__arm_vminnmq_x_f32): Likewise.
3026 (__arm_vmaxnmq_x_f16): Likewise.
3027 (__arm_vmaxnmq_x_f32): Likewise.
3028 (__arm_vabdq_x_f16): Likewise.
3029 (__arm_vabdq_x_f32): Likewise.
3030 (__arm_vabsq_x_f16): Likewise.
3031 (__arm_vabsq_x_f32): Likewise.
3032 (__arm_vaddq_x_f16): Likewise.
3033 (__arm_vaddq_x_f32): Likewise.
3034 (__arm_vaddq_x_n_f16): Likewise.
3035 (__arm_vaddq_x_n_f32): Likewise.
3036 (__arm_vnegq_x_f16): Likewise.
3037 (__arm_vnegq_x_f32): Likewise.
3038 (__arm_vmulq_x_f16): Likewise.
3039 (__arm_vmulq_x_f32): Likewise.
3040 (__arm_vmulq_x_n_f16): Likewise.
3041 (__arm_vmulq_x_n_f32): Likewise.
3042 (__arm_vsubq_x_f16): Likewise.
3043 (__arm_vsubq_x_f32): Likewise.
3044 (__arm_vsubq_x_n_f16): Likewise.
3045 (__arm_vsubq_x_n_f32): Likewise.
3046 (__arm_vcaddq_rot90_x_f16): Likewise.
3047 (__arm_vcaddq_rot90_x_f32): Likewise.
3048 (__arm_vcaddq_rot270_x_f16): Likewise.
3049 (__arm_vcaddq_rot270_x_f32): Likewise.
3050 (__arm_vcmulq_x_f16): Likewise.
3051 (__arm_vcmulq_x_f32): Likewise.
3052 (__arm_vcmulq_rot90_x_f16): Likewise.
3053 (__arm_vcmulq_rot90_x_f32): Likewise.
3054 (__arm_vcmulq_rot180_x_f16): Likewise.
3055 (__arm_vcmulq_rot180_x_f32): Likewise.
3056 (__arm_vcmulq_rot270_x_f16): Likewise.
3057 (__arm_vcmulq_rot270_x_f32): Likewise.
3058 (__arm_vcvtaq_x_s16_f16): Likewise.
3059 (__arm_vcvtaq_x_s32_f32): Likewise.
3060 (__arm_vcvtaq_x_u16_f16): Likewise.
3061 (__arm_vcvtaq_x_u32_f32): Likewise.
3062 (__arm_vcvtnq_x_s16_f16): Likewise.
3063 (__arm_vcvtnq_x_s32_f32): Likewise.
3064 (__arm_vcvtnq_x_u16_f16): Likewise.
3065 (__arm_vcvtnq_x_u32_f32): Likewise.
3066 (__arm_vcvtpq_x_s16_f16): Likewise.
3067 (__arm_vcvtpq_x_s32_f32): Likewise.
3068 (__arm_vcvtpq_x_u16_f16): Likewise.
3069 (__arm_vcvtpq_x_u32_f32): Likewise.
3070 (__arm_vcvtmq_x_s16_f16): Likewise.
3071 (__arm_vcvtmq_x_s32_f32): Likewise.
3072 (__arm_vcvtmq_x_u16_f16): Likewise.
3073 (__arm_vcvtmq_x_u32_f32): Likewise.
3074 (__arm_vcvtbq_x_f32_f16): Likewise.
3075 (__arm_vcvttq_x_f32_f16): Likewise.
3076 (__arm_vcvtq_x_f16_u16): Likewise.
3077 (__arm_vcvtq_x_f16_s16): Likewise.
3078 (__arm_vcvtq_x_f32_s32): Likewise.
3079 (__arm_vcvtq_x_f32_u32): Likewise.
3080 (__arm_vcvtq_x_n_f16_s16): Likewise.
3081 (__arm_vcvtq_x_n_f16_u16): Likewise.
3082 (__arm_vcvtq_x_n_f32_s32): Likewise.
3083 (__arm_vcvtq_x_n_f32_u32): Likewise.
3084 (__arm_vcvtq_x_s16_f16): Likewise.
3085 (__arm_vcvtq_x_s32_f32): Likewise.
3086 (__arm_vcvtq_x_u16_f16): Likewise.
3087 (__arm_vcvtq_x_u32_f32): Likewise.
3088 (__arm_vcvtq_x_n_s16_f16): Likewise.
3089 (__arm_vcvtq_x_n_s32_f32): Likewise.
3090 (__arm_vcvtq_x_n_u16_f16): Likewise.
3091 (__arm_vcvtq_x_n_u32_f32): Likewise.
3092 (__arm_vrndq_x_f16): Likewise.
3093 (__arm_vrndq_x_f32): Likewise.
3094 (__arm_vrndnq_x_f16): Likewise.
3095 (__arm_vrndnq_x_f32): Likewise.
3096 (__arm_vrndmq_x_f16): Likewise.
3097 (__arm_vrndmq_x_f32): Likewise.
3098 (__arm_vrndpq_x_f16): Likewise.
3099 (__arm_vrndpq_x_f32): Likewise.
3100 (__arm_vrndaq_x_f16): Likewise.
3101 (__arm_vrndaq_x_f32): Likewise.
3102 (__arm_vrndxq_x_f16): Likewise.
3103 (__arm_vrndxq_x_f32): Likewise.
3104 (__arm_vandq_x_f16): Likewise.
3105 (__arm_vandq_x_f32): Likewise.
3106 (__arm_vbicq_x_f16): Likewise.
3107 (__arm_vbicq_x_f32): Likewise.
3108 (__arm_vbrsrq_x_n_f16): Likewise.
3109 (__arm_vbrsrq_x_n_f32): Likewise.
3110 (__arm_veorq_x_f16): Likewise.
3111 (__arm_veorq_x_f32): Likewise.
3112 (__arm_vornq_x_f16): Likewise.
3113 (__arm_vornq_x_f32): Likewise.
3114 (__arm_vorrq_x_f16): Likewise.
3115 (__arm_vorrq_x_f32): Likewise.
3116 (__arm_vrev32q_x_f16): Likewise.
3117 (__arm_vrev64q_x_f16): Likewise.
3118 (__arm_vrev64q_x_f32): Likewise.
3119 (vabdq_x): Define polymorphic variant.
3120 (vabsq_x): Likewise.
3121 (vaddq_x): Likewise.
3122 (vandq_x): Likewise.
3123 (vbicq_x): Likewise.
3124 (vbrsrq_x): Likewise.
3125 (vcaddq_rot270_x): Likewise.
3126 (vcaddq_rot90_x): Likewise.
3127 (vcmulq_rot180_x): Likewise.
3128 (vcmulq_rot270_x): Likewise.
3129 (vcmulq_x): Likewise.
3130 (vcvtq_x): Likewise.
3131 (vcvtq_x_n): Likewise.
3132 (vcvtnq_m): Likewise.
3133 (veorq_x): Likewise.
3134 (vmaxnmq_x): Likewise.
3135 (vminnmq_x): Likewise.
3136 (vmulq_x): Likewise.
3137 (vnegq_x): Likewise.
3138 (vornq_x): Likewise.
3139 (vorrq_x): Likewise.
3140 (vrev32q_x): Likewise.
3141 (vrev64q_x): Likewise.
3142 (vrndaq_x): Likewise.
3143 (vrndmq_x): Likewise.
3144 (vrndnq_x): Likewise.
3145 (vrndpq_x): Likewise.
3146 (vrndq_x): Likewise.
3147 (vrndxq_x): Likewise.
3148 (vsubq_x): Likewise.
3149 (vcmulq_rot90_x): Likewise.
3151 (vclsq_x): Likewise.
3152 (vclzq_x): Likewise.
3153 (vhaddq_x): Likewise.
3154 (vhcaddq_rot270_x): Likewise.
3155 (vhcaddq_rot90_x): Likewise.
3156 (vhsubq_x): Likewise.
3157 (vmaxq_x): Likewise.
3158 (vminq_x): Likewise.
3159 (vmovlbq_x): Likewise.
3160 (vmovltq_x): Likewise.
3161 (vmulhq_x): Likewise.
3162 (vmullbq_int_x): Likewise.
3163 (vmullbq_poly_x): Likewise.
3164 (vmulltq_int_x): Likewise.
3165 (vmulltq_poly_x): Likewise.
3166 (vmvnq_x): Likewise.
3167 (vrev16q_x): Likewise.
3168 (vrhaddq_x): Likewise.
3169 (vrmulhq_x): Likewise.
3170 (vrshlq_x): Likewise.
3171 (vrshrq_x): Likewise.
3172 (vshllbq_x): Likewise.
3173 (vshlltq_x): Likewise.
3174 (vshlq_x_n): Likewise.
3175 (vshlq_x): Likewise.
3176 (vdwdupq_x_u8): Likewise.
3177 (vdwdupq_x_u16): Likewise.
3178 (vdwdupq_x_u32): Likewise.
3179 (viwdupq_x_u8): Likewise.
3180 (viwdupq_x_u16): Likewise.
3181 (viwdupq_x_u32): Likewise.
3182 (vidupq_x_u8): Likewise.
3183 (vddupq_x_u8): Likewise.
3184 (vidupq_x_u16): Likewise.
3185 (vddupq_x_u16): Likewise.
3186 (vidupq_x_u32): Likewise.
3187 (vddupq_x_u32): Likewise.
3188 (vshrq_x): Likewise.
3190 2020-03-20 Richard Biener <rguenther@suse.de>
3192 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
3193 to vectorize for CTOR defs.
3195 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3196 Andre Vieira <andre.simoesdiasvieira@arm.com>
3197 Mihail Ionescu <mihail.ionescu@arm.com>
3199 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
3201 (LDRGBWBU_QUALIFIERS): Likewise.
3202 (LDRGBWBS_Z_QUALIFIERS): Likewise.
3203 (LDRGBWBU_Z_QUALIFIERS): Likewise.
3204 (STRSBWBS_QUALIFIERS): Likewise.
3205 (STRSBWBU_QUALIFIERS): Likewise.
3206 (STRSBWBS_P_QUALIFIERS): Likewise.
3207 (STRSBWBU_P_QUALIFIERS): Likewise.
3208 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
3209 (vldrdq_gather_base_wb_u64): Likewise.
3210 (vldrdq_gather_base_wb_z_s64): Likewise.
3211 (vldrdq_gather_base_wb_z_u64): Likewise.
3212 (vldrwq_gather_base_wb_f32): Likewise.
3213 (vldrwq_gather_base_wb_s32): Likewise.
3214 (vldrwq_gather_base_wb_u32): Likewise.
3215 (vldrwq_gather_base_wb_z_f32): Likewise.
3216 (vldrwq_gather_base_wb_z_s32): Likewise.
3217 (vldrwq_gather_base_wb_z_u32): Likewise.
3218 (vstrdq_scatter_base_wb_p_s64): Likewise.
3219 (vstrdq_scatter_base_wb_p_u64): Likewise.
3220 (vstrdq_scatter_base_wb_s64): Likewise.
3221 (vstrdq_scatter_base_wb_u64): Likewise.
3222 (vstrwq_scatter_base_wb_p_s32): Likewise.
3223 (vstrwq_scatter_base_wb_p_f32): Likewise.
3224 (vstrwq_scatter_base_wb_p_u32): Likewise.
3225 (vstrwq_scatter_base_wb_s32): Likewise.
3226 (vstrwq_scatter_base_wb_u32): Likewise.
3227 (vstrwq_scatter_base_wb_f32): Likewise.
3228 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
3229 (__arm_vldrdq_gather_base_wb_u64): Likewise.
3230 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
3231 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
3232 (__arm_vldrwq_gather_base_wb_s32): Likewise.
3233 (__arm_vldrwq_gather_base_wb_u32): Likewise.
3234 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
3235 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
3236 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
3237 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
3238 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
3239 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
3240 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
3241 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
3242 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
3243 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
3244 (__arm_vldrwq_gather_base_wb_f32): Likewise.
3245 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
3246 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
3247 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
3248 (vstrwq_scatter_base_wb): Define polymorphic variant.
3249 (vstrwq_scatter_base_wb_p): Likewise.
3250 (vstrdq_scatter_base_wb_p): Likewise.
3251 (vstrdq_scatter_base_wb): Likewise.
3252 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
3254 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
3256 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
3257 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
3258 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
3259 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
3260 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
3261 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
3262 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
3263 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
3264 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
3265 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
3266 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
3267 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
3268 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
3269 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
3270 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
3271 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
3272 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
3273 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
3274 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
3275 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
3276 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
3277 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
3278 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
3279 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
3280 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
3281 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
3282 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
3283 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
3284 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
3286 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3287 Andre Vieira <andre.simoesdiasvieira@arm.com>
3288 Mihail Ionescu <mihail.ionescu@arm.com>
3290 * config/arm/arm-builtins.c
3291 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
3293 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
3294 (vddupq_m_n_u32): Likewise.
3295 (vddupq_m_n_u16): Likewise.
3296 (vddupq_m_wb_u8): Likewise.
3297 (vddupq_m_wb_u16): Likewise.
3298 (vddupq_m_wb_u32): Likewise.
3299 (vddupq_n_u8): Likewise.
3300 (vddupq_n_u32): Likewise.
3301 (vddupq_n_u16): Likewise.
3302 (vddupq_wb_u8): Likewise.
3303 (vddupq_wb_u16): Likewise.
3304 (vddupq_wb_u32): Likewise.
3305 (vdwdupq_m_n_u8): Likewise.
3306 (vdwdupq_m_n_u32): Likewise.
3307 (vdwdupq_m_n_u16): Likewise.
3308 (vdwdupq_m_wb_u8): Likewise.
3309 (vdwdupq_m_wb_u32): Likewise.
3310 (vdwdupq_m_wb_u16): Likewise.
3311 (vdwdupq_n_u8): Likewise.
3312 (vdwdupq_n_u32): Likewise.
3313 (vdwdupq_n_u16): Likewise.
3314 (vdwdupq_wb_u8): Likewise.
3315 (vdwdupq_wb_u32): Likewise.
3316 (vdwdupq_wb_u16): Likewise.
3317 (vidupq_m_n_u8): Likewise.
3318 (vidupq_m_n_u32): Likewise.
3319 (vidupq_m_n_u16): Likewise.
3320 (vidupq_m_wb_u8): Likewise.
3321 (vidupq_m_wb_u16): Likewise.
3322 (vidupq_m_wb_u32): Likewise.
3323 (vidupq_n_u8): Likewise.
3324 (vidupq_n_u32): Likewise.
3325 (vidupq_n_u16): Likewise.
3326 (vidupq_wb_u8): Likewise.
3327 (vidupq_wb_u16): Likewise.
3328 (vidupq_wb_u32): Likewise.
3329 (viwdupq_m_n_u8): Likewise.
3330 (viwdupq_m_n_u32): Likewise.
3331 (viwdupq_m_n_u16): Likewise.
3332 (viwdupq_m_wb_u8): Likewise.
3333 (viwdupq_m_wb_u32): Likewise.
3334 (viwdupq_m_wb_u16): Likewise.
3335 (viwdupq_n_u8): Likewise.
3336 (viwdupq_n_u32): Likewise.
3337 (viwdupq_n_u16): Likewise.
3338 (viwdupq_wb_u8): Likewise.
3339 (viwdupq_wb_u32): Likewise.
3340 (viwdupq_wb_u16): Likewise.
3341 (__arm_vddupq_m_n_u8): Define intrinsic.
3342 (__arm_vddupq_m_n_u32): Likewise.
3343 (__arm_vddupq_m_n_u16): Likewise.
3344 (__arm_vddupq_m_wb_u8): Likewise.
3345 (__arm_vddupq_m_wb_u16): Likewise.
3346 (__arm_vddupq_m_wb_u32): Likewise.
3347 (__arm_vddupq_n_u8): Likewise.
3348 (__arm_vddupq_n_u32): Likewise.
3349 (__arm_vddupq_n_u16): Likewise.
3350 (__arm_vdwdupq_m_n_u8): Likewise.
3351 (__arm_vdwdupq_m_n_u32): Likewise.
3352 (__arm_vdwdupq_m_n_u16): Likewise.
3353 (__arm_vdwdupq_m_wb_u8): Likewise.
3354 (__arm_vdwdupq_m_wb_u32): Likewise.
3355 (__arm_vdwdupq_m_wb_u16): Likewise.
3356 (__arm_vdwdupq_n_u8): Likewise.
3357 (__arm_vdwdupq_n_u32): Likewise.
3358 (__arm_vdwdupq_n_u16): Likewise.
3359 (__arm_vdwdupq_wb_u8): Likewise.
3360 (__arm_vdwdupq_wb_u32): Likewise.
3361 (__arm_vdwdupq_wb_u16): Likewise.
3362 (__arm_vidupq_m_n_u8): Likewise.
3363 (__arm_vidupq_m_n_u32): Likewise.
3364 (__arm_vidupq_m_n_u16): Likewise.
3365 (__arm_vidupq_n_u8): Likewise.
3366 (__arm_vidupq_m_wb_u8): Likewise.
3367 (__arm_vidupq_m_wb_u16): Likewise.
3368 (__arm_vidupq_m_wb_u32): Likewise.
3369 (__arm_vidupq_n_u32): Likewise.
3370 (__arm_vidupq_n_u16): Likewise.
3371 (__arm_vidupq_wb_u8): Likewise.
3372 (__arm_vidupq_wb_u16): Likewise.
3373 (__arm_vidupq_wb_u32): Likewise.
3374 (__arm_vddupq_wb_u8): Likewise.
3375 (__arm_vddupq_wb_u16): Likewise.
3376 (__arm_vddupq_wb_u32): Likewise.
3377 (__arm_viwdupq_m_n_u8): Likewise.
3378 (__arm_viwdupq_m_n_u32): Likewise.
3379 (__arm_viwdupq_m_n_u16): Likewise.
3380 (__arm_viwdupq_m_wb_u8): Likewise.
3381 (__arm_viwdupq_m_wb_u32): Likewise.
3382 (__arm_viwdupq_m_wb_u16): Likewise.
3383 (__arm_viwdupq_n_u8): Likewise.
3384 (__arm_viwdupq_n_u32): Likewise.
3385 (__arm_viwdupq_n_u16): Likewise.
3386 (__arm_viwdupq_wb_u8): Likewise.
3387 (__arm_viwdupq_wb_u32): Likewise.
3388 (__arm_viwdupq_wb_u16): Likewise.
3389 (vidupq_m): Define polymorphic variant.
3390 (vddupq_m): Likewise.
3391 (vidupq_u16): Likewise.
3392 (vidupq_u32): Likewise.
3393 (vidupq_u8): Likewise.
3394 (vddupq_u16): Likewise.
3395 (vddupq_u32): Likewise.
3396 (vddupq_u8): Likewise.
3397 (viwdupq_m): Likewise.
3398 (viwdupq_u16): Likewise.
3399 (viwdupq_u32): Likewise.
3400 (viwdupq_u8): Likewise.
3401 (vdwdupq_m): Likewise.
3402 (vdwdupq_u16): Likewise.
3403 (vdwdupq_u32): Likewise.
3404 (vdwdupq_u8): Likewise.
3405 * config/arm/arm_mve_builtins.def
3406 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
3408 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
3409 (mve_vidupq_u<mode>_insn): Likewise.
3410 (mve_vidupq_m_n_u<mode>): Likewise.
3411 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
3412 (mve_vddupq_n_u<mode>): Likewise.
3413 (mve_vddupq_u<mode>_insn): Likewise.
3414 (mve_vddupq_m_n_u<mode>): Likewise.
3415 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
3416 (mve_vdwdupq_n_u<mode>): Likewise.
3417 (mve_vdwdupq_wb_u<mode>): Likewise.
3418 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
3419 (mve_vdwdupq_m_n_u<mode>): Likewise.
3420 (mve_vdwdupq_m_wb_u<mode>): Likewise.
3421 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
3422 (mve_viwdupq_n_u<mode>): Likewise.
3423 (mve_viwdupq_wb_u<mode>): Likewise.
3424 (mve_viwdupq_wb_u<mode>_insn): Likewise.
3425 (mve_viwdupq_m_n_u<mode>): Likewise.
3426 (mve_viwdupq_m_wb_u<mode>): Likewise.
3427 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
3429 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3431 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
3432 (vreinterpretq_s16_s64): Likewise.
3433 (vreinterpretq_s16_s8): Likewise.
3434 (vreinterpretq_s16_u16): Likewise.
3435 (vreinterpretq_s16_u32): Likewise.
3436 (vreinterpretq_s16_u64): Likewise.
3437 (vreinterpretq_s16_u8): Likewise.
3438 (vreinterpretq_s32_s16): Likewise.
3439 (vreinterpretq_s32_s64): Likewise.
3440 (vreinterpretq_s32_s8): Likewise.
3441 (vreinterpretq_s32_u16): Likewise.
3442 (vreinterpretq_s32_u32): Likewise.
3443 (vreinterpretq_s32_u64): Likewise.
3444 (vreinterpretq_s32_u8): Likewise.
3445 (vreinterpretq_s64_s16): Likewise.
3446 (vreinterpretq_s64_s32): Likewise.
3447 (vreinterpretq_s64_s8): Likewise.
3448 (vreinterpretq_s64_u16): Likewise.
3449 (vreinterpretq_s64_u32): Likewise.
3450 (vreinterpretq_s64_u64): Likewise.
3451 (vreinterpretq_s64_u8): Likewise.
3452 (vreinterpretq_s8_s16): Likewise.
3453 (vreinterpretq_s8_s32): Likewise.
3454 (vreinterpretq_s8_s64): Likewise.
3455 (vreinterpretq_s8_u16): Likewise.
3456 (vreinterpretq_s8_u32): Likewise.
3457 (vreinterpretq_s8_u64): Likewise.
3458 (vreinterpretq_s8_u8): Likewise.
3459 (vreinterpretq_u16_s16): Likewise.
3460 (vreinterpretq_u16_s32): Likewise.
3461 (vreinterpretq_u16_s64): Likewise.
3462 (vreinterpretq_u16_s8): Likewise.
3463 (vreinterpretq_u16_u32): Likewise.
3464 (vreinterpretq_u16_u64): Likewise.
3465 (vreinterpretq_u16_u8): Likewise.
3466 (vreinterpretq_u32_s16): Likewise.
3467 (vreinterpretq_u32_s32): Likewise.
3468 (vreinterpretq_u32_s64): Likewise.
3469 (vreinterpretq_u32_s8): Likewise.
3470 (vreinterpretq_u32_u16): Likewise.
3471 (vreinterpretq_u32_u64): Likewise.
3472 (vreinterpretq_u32_u8): Likewise.
3473 (vreinterpretq_u64_s16): Likewise.
3474 (vreinterpretq_u64_s32): Likewise.
3475 (vreinterpretq_u64_s64): Likewise.
3476 (vreinterpretq_u64_s8): Likewise.
3477 (vreinterpretq_u64_u16): Likewise.
3478 (vreinterpretq_u64_u32): Likewise.
3479 (vreinterpretq_u64_u8): Likewise.
3480 (vreinterpretq_u8_s16): Likewise.
3481 (vreinterpretq_u8_s32): Likewise.
3482 (vreinterpretq_u8_s64): Likewise.
3483 (vreinterpretq_u8_s8): Likewise.
3484 (vreinterpretq_u8_u16): Likewise.
3485 (vreinterpretq_u8_u32): Likewise.
3486 (vreinterpretq_u8_u64): Likewise.
3487 (vreinterpretq_s32_f16): Likewise.
3488 (vreinterpretq_s32_f32): Likewise.
3489 (vreinterpretq_u16_f16): Likewise.
3490 (vreinterpretq_u16_f32): Likewise.
3491 (vreinterpretq_u32_f16): Likewise.
3492 (vreinterpretq_u32_f32): Likewise.
3493 (vreinterpretq_u64_f16): Likewise.
3494 (vreinterpretq_u64_f32): Likewise.
3495 (vreinterpretq_u8_f16): Likewise.
3496 (vreinterpretq_u8_f32): Likewise.
3497 (vreinterpretq_f16_f32): Likewise.
3498 (vreinterpretq_f16_s16): Likewise.
3499 (vreinterpretq_f16_s32): Likewise.
3500 (vreinterpretq_f16_s64): Likewise.
3501 (vreinterpretq_f16_s8): Likewise.
3502 (vreinterpretq_f16_u16): Likewise.
3503 (vreinterpretq_f16_u32): Likewise.
3504 (vreinterpretq_f16_u64): Likewise.
3505 (vreinterpretq_f16_u8): Likewise.
3506 (vreinterpretq_f32_f16): Likewise.
3507 (vreinterpretq_f32_s16): Likewise.
3508 (vreinterpretq_f32_s32): Likewise.
3509 (vreinterpretq_f32_s64): Likewise.
3510 (vreinterpretq_f32_s8): Likewise.
3511 (vreinterpretq_f32_u16): Likewise.
3512 (vreinterpretq_f32_u32): Likewise.
3513 (vreinterpretq_f32_u64): Likewise.
3514 (vreinterpretq_f32_u8): Likewise.
3515 (vreinterpretq_s16_f16): Likewise.
3516 (vreinterpretq_s16_f32): Likewise.
3517 (vreinterpretq_s64_f16): Likewise.
3518 (vreinterpretq_s64_f32): Likewise.
3519 (vreinterpretq_s8_f16): Likewise.
3520 (vreinterpretq_s8_f32): Likewise.
3521 (vuninitializedq_u8): Likewise.
3522 (vuninitializedq_u16): Likewise.
3523 (vuninitializedq_u32): Likewise.
3524 (vuninitializedq_u64): Likewise.
3525 (vuninitializedq_s8): Likewise.
3526 (vuninitializedq_s16): Likewise.
3527 (vuninitializedq_s32): Likewise.
3528 (vuninitializedq_s64): Likewise.
3529 (vuninitializedq_f16): Likewise.
3530 (vuninitializedq_f32): Likewise.
3531 (__arm_vuninitializedq_u8): Define intrinsic.
3532 (__arm_vuninitializedq_u16): Likewise.
3533 (__arm_vuninitializedq_u32): Likewise.
3534 (__arm_vuninitializedq_u64): Likewise.
3535 (__arm_vuninitializedq_s8): Likewise.
3536 (__arm_vuninitializedq_s16): Likewise.
3537 (__arm_vuninitializedq_s32): Likewise.
3538 (__arm_vuninitializedq_s64): Likewise.
3539 (__arm_vreinterpretq_s16_s32): Likewise.
3540 (__arm_vreinterpretq_s16_s64): Likewise.
3541 (__arm_vreinterpretq_s16_s8): Likewise.
3542 (__arm_vreinterpretq_s16_u16): Likewise.
3543 (__arm_vreinterpretq_s16_u32): Likewise.
3544 (__arm_vreinterpretq_s16_u64): Likewise.
3545 (__arm_vreinterpretq_s16_u8): Likewise.
3546 (__arm_vreinterpretq_s32_s16): Likewise.
3547 (__arm_vreinterpretq_s32_s64): Likewise.
3548 (__arm_vreinterpretq_s32_s8): Likewise.
3549 (__arm_vreinterpretq_s32_u16): Likewise.
3550 (__arm_vreinterpretq_s32_u32): Likewise.
3551 (__arm_vreinterpretq_s32_u64): Likewise.
3552 (__arm_vreinterpretq_s32_u8): Likewise.
3553 (__arm_vreinterpretq_s64_s16): Likewise.
3554 (__arm_vreinterpretq_s64_s32): Likewise.
3555 (__arm_vreinterpretq_s64_s8): Likewise.
3556 (__arm_vreinterpretq_s64_u16): Likewise.
3557 (__arm_vreinterpretq_s64_u32): Likewise.
3558 (__arm_vreinterpretq_s64_u64): Likewise.
3559 (__arm_vreinterpretq_s64_u8): Likewise.
3560 (__arm_vreinterpretq_s8_s16): Likewise.
3561 (__arm_vreinterpretq_s8_s32): Likewise.
3562 (__arm_vreinterpretq_s8_s64): Likewise.
3563 (__arm_vreinterpretq_s8_u16): Likewise.
3564 (__arm_vreinterpretq_s8_u32): Likewise.
3565 (__arm_vreinterpretq_s8_u64): Likewise.
3566 (__arm_vreinterpretq_s8_u8): Likewise.
3567 (__arm_vreinterpretq_u16_s16): Likewise.
3568 (__arm_vreinterpretq_u16_s32): Likewise.
3569 (__arm_vreinterpretq_u16_s64): Likewise.
3570 (__arm_vreinterpretq_u16_s8): Likewise.
3571 (__arm_vreinterpretq_u16_u32): Likewise.
3572 (__arm_vreinterpretq_u16_u64): Likewise.
3573 (__arm_vreinterpretq_u16_u8): Likewise.
3574 (__arm_vreinterpretq_u32_s16): Likewise.
3575 (__arm_vreinterpretq_u32_s32): Likewise.
3576 (__arm_vreinterpretq_u32_s64): Likewise.
3577 (__arm_vreinterpretq_u32_s8): Likewise.
3578 (__arm_vreinterpretq_u32_u16): Likewise.
3579 (__arm_vreinterpretq_u32_u64): Likewise.
3580 (__arm_vreinterpretq_u32_u8): Likewise.
3581 (__arm_vreinterpretq_u64_s16): Likewise.
3582 (__arm_vreinterpretq_u64_s32): Likewise.
3583 (__arm_vreinterpretq_u64_s64): Likewise.
3584 (__arm_vreinterpretq_u64_s8): Likewise.
3585 (__arm_vreinterpretq_u64_u16): Likewise.
3586 (__arm_vreinterpretq_u64_u32): Likewise.
3587 (__arm_vreinterpretq_u64_u8): Likewise.
3588 (__arm_vreinterpretq_u8_s16): Likewise.
3589 (__arm_vreinterpretq_u8_s32): Likewise.
3590 (__arm_vreinterpretq_u8_s64): Likewise.
3591 (__arm_vreinterpretq_u8_s8): Likewise.
3592 (__arm_vreinterpretq_u8_u16): Likewise.
3593 (__arm_vreinterpretq_u8_u32): Likewise.
3594 (__arm_vreinterpretq_u8_u64): Likewise.
3595 (__arm_vuninitializedq_f16): Likewise.
3596 (__arm_vuninitializedq_f32): Likewise.
3597 (__arm_vreinterpretq_s32_f16): Likewise.
3598 (__arm_vreinterpretq_s32_f32): Likewise.
3599 (__arm_vreinterpretq_s16_f16): Likewise.
3600 (__arm_vreinterpretq_s16_f32): Likewise.
3601 (__arm_vreinterpretq_s64_f16): Likewise.
3602 (__arm_vreinterpretq_s64_f32): Likewise.
3603 (__arm_vreinterpretq_s8_f16): Likewise.
3604 (__arm_vreinterpretq_s8_f32): Likewise.
3605 (__arm_vreinterpretq_u16_f16): Likewise.
3606 (__arm_vreinterpretq_u16_f32): Likewise.
3607 (__arm_vreinterpretq_u32_f16): Likewise.
3608 (__arm_vreinterpretq_u32_f32): Likewise.
3609 (__arm_vreinterpretq_u64_f16): Likewise.
3610 (__arm_vreinterpretq_u64_f32): Likewise.
3611 (__arm_vreinterpretq_u8_f16): Likewise.
3612 (__arm_vreinterpretq_u8_f32): Likewise.
3613 (__arm_vreinterpretq_f16_f32): Likewise.
3614 (__arm_vreinterpretq_f16_s16): Likewise.
3615 (__arm_vreinterpretq_f16_s32): Likewise.
3616 (__arm_vreinterpretq_f16_s64): Likewise.
3617 (__arm_vreinterpretq_f16_s8): Likewise.
3618 (__arm_vreinterpretq_f16_u16): Likewise.
3619 (__arm_vreinterpretq_f16_u32): Likewise.
3620 (__arm_vreinterpretq_f16_u64): Likewise.
3621 (__arm_vreinterpretq_f16_u8): Likewise.
3622 (__arm_vreinterpretq_f32_f16): Likewise.
3623 (__arm_vreinterpretq_f32_s16): Likewise.
3624 (__arm_vreinterpretq_f32_s32): Likewise.
3625 (__arm_vreinterpretq_f32_s64): Likewise.
3626 (__arm_vreinterpretq_f32_s8): Likewise.
3627 (__arm_vreinterpretq_f32_u16): Likewise.
3628 (__arm_vreinterpretq_f32_u32): Likewise.
3629 (__arm_vreinterpretq_f32_u64): Likewise.
3630 (__arm_vreinterpretq_f32_u8): Likewise.
3631 (vuninitializedq): Define polymorphic variant.
3632 (vreinterpretq_f16): Likewise.
3633 (vreinterpretq_f32): Likewise.
3634 (vreinterpretq_s16): Likewise.
3635 (vreinterpretq_s32): Likewise.
3636 (vreinterpretq_s64): Likewise.
3637 (vreinterpretq_s8): Likewise.
3638 (vreinterpretq_u16): Likewise.
3639 (vreinterpretq_u32): Likewise.
3640 (vreinterpretq_u64): Likewise.
3641 (vreinterpretq_u8): Likewise.
3643 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3644 Andre Vieira <andre.simoesdiasvieira@arm.com>
3645 Mihail Ionescu <mihail.ionescu@arm.com>
3647 * config/arm/arm_mve.h (vaddq_s8): Define macro.
3648 (vaddq_s16): Likewise.
3649 (vaddq_s32): Likewise.
3650 (vaddq_u8): Likewise.
3651 (vaddq_u16): Likewise.
3652 (vaddq_u32): Likewise.
3653 (vaddq_f16): Likewise.
3654 (vaddq_f32): Likewise.
3655 (__arm_vaddq_s8): Define intrinsic.
3656 (__arm_vaddq_s16): Likewise.
3657 (__arm_vaddq_s32): Likewise.
3658 (__arm_vaddq_u8): Likewise.
3659 (__arm_vaddq_u16): Likewise.
3660 (__arm_vaddq_u32): Likewise.
3661 (__arm_vaddq_f16): Likewise.
3662 (__arm_vaddq_f32): Likewise.
3663 (vaddq): Define polymorphic variant.
3664 * config/arm/iterators.md (VNIM): Define mode iterator for common types
3665 Neon, IWMMXT and MVE.
3666 (VNINOTM): Likewise.
3667 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
3668 (mve_vaddq_f<mode>): Define RTL pattern.
3669 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
3670 (addv8hf3_neon): Define RTL pattern.
3671 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
3673 (addv8hf3): Define standard RTL pattern for MVE and Neon.
3674 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
3676 2020-03-20 Martin Liska <mliska@suse.cz>
3679 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
3680 build_ref_for_offset function was used and it transforms off to bytes
3683 2020-03-20 Richard Biener <rguenther@suse.de>
3685 PR tree-optimization/94266
3686 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
3687 type of the underlying object to adjust for the containing
3690 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
3692 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
3693 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
3694 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
3696 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
3698 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
3700 2020-03-20 Jakub Jelinek <jakub@redhat.com>
3702 PR tree-optimization/94224
3703 * gimple-ssa-store-merging.c
3704 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
3705 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
3708 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
3710 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
3712 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
3715 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
3716 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
3718 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
3721 * cgraphunit.c (process_function_and_variable_attributes): warn
3722 for flatten attribute on alias.
3723 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
3725 2020-03-19 Martin Liska <mliska@suse.cz>
3727 * lto-section-in.c: Add ext_symtab.
3728 * lto-streamer-out.c (write_symbol_extension_info): New.
3729 (produce_symtab_extension): New.
3730 (produce_asm_for_decls): Stream also produce_symtab_extension.
3731 * lto-streamer.h (enum lto_section_type): New section.
3733 2020-03-19 Jakub Jelinek <jakub@redhat.com>
3735 PR tree-optimization/94211
3736 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
3737 instead of estimate_num_insns for bb_seq (middle_bb). Rename
3738 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
3741 2020-03-19 Richard Biener <rguenther@suse.de>
3744 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
3745 and build_ref_for_offset.
3747 2020-03-19 Richard Biener <rguenther@suse.de>
3750 * fold-const.c (fold_binary_loc): Avoid using
3751 build_fold_addr_expr when we really want an ADDR_EXPR.
3753 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
3755 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
3758 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
3760 PR rtl-optimization/90275
3761 * cse.c (cse_insn): Delete no-op register moves too.
3763 2020-03-18 Martin Sebor <msebor@redhat.com>
3766 * cgraphunit.c (process_function_and_variable_attributes): Also
3767 complain about weakref function definitions and drop all effects
3770 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3771 Mihail Ionescu <mihail.ionescu@arm.com>
3772 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3774 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
3775 (vstrdq_scatter_base_p_u64): Likewise.
3776 (vstrdq_scatter_base_s64): Likewise.
3777 (vstrdq_scatter_base_u64): Likewise.
3778 (vstrdq_scatter_offset_p_s64): Likewise.
3779 (vstrdq_scatter_offset_p_u64): Likewise.
3780 (vstrdq_scatter_offset_s64): Likewise.
3781 (vstrdq_scatter_offset_u64): Likewise.
3782 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
3783 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
3784 (vstrdq_scatter_shifted_offset_s64): Likewise.
3785 (vstrdq_scatter_shifted_offset_u64): Likewise.
3786 (vstrhq_scatter_offset_f16): Likewise.
3787 (vstrhq_scatter_offset_p_f16): Likewise.
3788 (vstrhq_scatter_shifted_offset_f16): Likewise.
3789 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
3790 (vstrwq_scatter_base_f32): Likewise.
3791 (vstrwq_scatter_base_p_f32): Likewise.
3792 (vstrwq_scatter_offset_f32): Likewise.
3793 (vstrwq_scatter_offset_p_f32): Likewise.
3794 (vstrwq_scatter_offset_p_s32): Likewise.
3795 (vstrwq_scatter_offset_p_u32): Likewise.
3796 (vstrwq_scatter_offset_s32): Likewise.
3797 (vstrwq_scatter_offset_u32): Likewise.
3798 (vstrwq_scatter_shifted_offset_f32): Likewise.
3799 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
3800 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
3801 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
3802 (vstrwq_scatter_shifted_offset_s32): Likewise.
3803 (vstrwq_scatter_shifted_offset_u32): Likewise.
3804 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
3805 (__arm_vstrdq_scatter_base_p_u64): Likewise.
3806 (__arm_vstrdq_scatter_base_s64): Likewise.
3807 (__arm_vstrdq_scatter_base_u64): Likewise.
3808 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
3809 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
3810 (__arm_vstrdq_scatter_offset_s64): Likewise.
3811 (__arm_vstrdq_scatter_offset_u64): Likewise.
3812 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
3813 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
3814 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
3815 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
3816 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
3817 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
3818 (__arm_vstrwq_scatter_offset_s32): Likewise.
3819 (__arm_vstrwq_scatter_offset_u32): Likewise.
3820 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
3821 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
3822 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
3823 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
3824 (__arm_vstrhq_scatter_offset_f16): Likewise.
3825 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
3826 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
3827 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
3828 (__arm_vstrwq_scatter_base_f32): Likewise.
3829 (__arm_vstrwq_scatter_base_p_f32): Likewise.
3830 (__arm_vstrwq_scatter_offset_f32): Likewise.
3831 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
3832 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
3833 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
3834 (vstrhq_scatter_offset): Define polymorphic variant.
3835 (vstrhq_scatter_offset_p): Likewise.
3836 (vstrhq_scatter_shifted_offset): Likewise.
3837 (vstrhq_scatter_shifted_offset_p): Likewise.
3838 (vstrwq_scatter_base): Likewise.
3839 (vstrwq_scatter_base_p): Likewise.
3840 (vstrwq_scatter_offset): Likewise.
3841 (vstrwq_scatter_offset_p): Likewise.
3842 (vstrwq_scatter_shifted_offset): Likewise.
3843 (vstrwq_scatter_shifted_offset_p): Likewise.
3844 (vstrdq_scatter_base_p): Likewise.
3845 (vstrdq_scatter_base): Likewise.
3846 (vstrdq_scatter_offset_p): Likewise.
3847 (vstrdq_scatter_offset): Likewise.
3848 (vstrdq_scatter_shifted_offset_p): Likewise.
3849 (vstrdq_scatter_shifted_offset): Likewise.
3850 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
3851 (STRSBS_P): Likewise.
3853 (STRSBU_P): Likewise.
3855 (STRSS_P): Likewise.
3857 (STRSU_P): Likewise.
3858 * config/arm/constraints.md (Ri): Define.
3859 * config/arm/mve.md (VSTRDSBQ): Define iterator.
3860 (VSTRDSOQ): Likewise.
3861 (VSTRDSSOQ): Likewise.
3862 (VSTRWSOQ): Likewise.
3863 (VSTRWSSOQ): Likewise.
3864 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
3865 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
3866 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
3867 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
3868 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
3869 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
3870 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
3871 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
3872 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
3873 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
3874 (mve_vstrwq_scatter_base_fv4sf): Likewise.
3875 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
3876 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
3877 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
3878 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
3879 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
3880 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
3881 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
3882 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
3883 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
3884 * config/arm/predicates.md (Ri): Define predicate to check immediate
3885 is the range +/-1016 and multiple of 8.
3887 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3888 Mihail Ionescu <mihail.ionescu@arm.com>
3889 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3891 * config/arm/arm_mve.h (vst1q_f32): Define macro.
3892 (vst1q_f16): Likewise.
3893 (vst1q_s8): Likewise.
3894 (vst1q_s32): Likewise.
3895 (vst1q_s16): Likewise.
3896 (vst1q_u8): Likewise.
3897 (vst1q_u32): Likewise.
3898 (vst1q_u16): Likewise.
3899 (vstrhq_f16): Likewise.
3900 (vstrhq_scatter_offset_s32): Likewise.
3901 (vstrhq_scatter_offset_s16): Likewise.
3902 (vstrhq_scatter_offset_u32): Likewise.
3903 (vstrhq_scatter_offset_u16): Likewise.
3904 (vstrhq_scatter_offset_p_s32): Likewise.
3905 (vstrhq_scatter_offset_p_s16): Likewise.
3906 (vstrhq_scatter_offset_p_u32): Likewise.
3907 (vstrhq_scatter_offset_p_u16): Likewise.
3908 (vstrhq_scatter_shifted_offset_s32): Likewise.
3909 (vstrhq_scatter_shifted_offset_s16): Likewise.
3910 (vstrhq_scatter_shifted_offset_u32): Likewise.
3911 (vstrhq_scatter_shifted_offset_u16): Likewise.
3912 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
3913 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
3914 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
3915 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
3916 (vstrhq_s32): Likewise.
3917 (vstrhq_s16): Likewise.
3918 (vstrhq_u32): Likewise.
3919 (vstrhq_u16): Likewise.
3920 (vstrhq_p_f16): Likewise.
3921 (vstrhq_p_s32): Likewise.
3922 (vstrhq_p_s16): Likewise.
3923 (vstrhq_p_u32): Likewise.
3924 (vstrhq_p_u16): Likewise.
3925 (vstrwq_f32): Likewise.
3926 (vstrwq_s32): Likewise.
3927 (vstrwq_u32): Likewise.
3928 (vstrwq_p_f32): Likewise.
3929 (vstrwq_p_s32): Likewise.
3930 (vstrwq_p_u32): Likewise.
3931 (__arm_vst1q_s8): Define intrinsic.
3932 (__arm_vst1q_s32): Likewise.
3933 (__arm_vst1q_s16): Likewise.
3934 (__arm_vst1q_u8): Likewise.
3935 (__arm_vst1q_u32): Likewise.
3936 (__arm_vst1q_u16): Likewise.
3937 (__arm_vstrhq_scatter_offset_s32): Likewise.
3938 (__arm_vstrhq_scatter_offset_s16): Likewise.
3939 (__arm_vstrhq_scatter_offset_u32): Likewise.
3940 (__arm_vstrhq_scatter_offset_u16): Likewise.
3941 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
3942 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
3943 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
3944 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
3945 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
3946 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
3947 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
3948 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
3949 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
3950 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
3951 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
3952 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
3953 (__arm_vstrhq_s32): Likewise.
3954 (__arm_vstrhq_s16): Likewise.
3955 (__arm_vstrhq_u32): Likewise.
3956 (__arm_vstrhq_u16): Likewise.
3957 (__arm_vstrhq_p_s32): Likewise.
3958 (__arm_vstrhq_p_s16): Likewise.
3959 (__arm_vstrhq_p_u32): Likewise.
3960 (__arm_vstrhq_p_u16): Likewise.
3961 (__arm_vstrwq_s32): Likewise.
3962 (__arm_vstrwq_u32): Likewise.
3963 (__arm_vstrwq_p_s32): Likewise.
3964 (__arm_vstrwq_p_u32): Likewise.
3965 (__arm_vstrwq_p_f32): Likewise.
3966 (__arm_vstrwq_f32): Likewise.
3967 (__arm_vst1q_f32): Likewise.
3968 (__arm_vst1q_f16): Likewise.
3969 (__arm_vstrhq_f16): Likewise.
3970 (__arm_vstrhq_p_f16): Likewise.
3971 (vst1q): Define polymorphic variant.
3973 (vstrhq_p): Likewise.
3974 (vstrhq_scatter_offset_p): Likewise.
3975 (vstrhq_scatter_offset): Likewise.
3976 (vstrhq_scatter_shifted_offset_p): Likewise.
3977 (vstrhq_scatter_shifted_offset): Likewise.
3978 (vstrwq_p): Likewise.
3980 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
3983 (STRSS_P): Likewise.
3985 (STRSU_P): Likewise.
3988 * config/arm/mve.md (VST1Q): Define iterator.
3989 (VSTRHSOQ): Likewise.
3990 (VSTRHSSOQ): Likewise.
3993 (mve_vstrhq_fv8hf): Define RTL pattern.
3994 (mve_vstrhq_p_fv8hf): Likewise.
3995 (mve_vstrhq_p_<supf><mode>): Likewise.
3996 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
3997 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
3998 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
3999 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
4000 (mve_vstrhq_<supf><mode>): Likewise.
4001 (mve_vstrwq_fv4sf): Likewise.
4002 (mve_vstrwq_p_fv4sf): Likewise.
4003 (mve_vstrwq_p_<supf>v4si): Likewise.
4004 (mve_vstrwq_<supf>v4si): Likewise.
4005 (mve_vst1q_f<mode>): Define expand.
4006 (mve_vst1q_<supf><mode>): Likewise.
4008 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4009 Mihail Ionescu <mihail.ionescu@arm.com>
4010 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4012 * config/arm/arm_mve.h (vld1q_s8): Define macro.
4013 (vld1q_s32): Likewise.
4014 (vld1q_s16): Likewise.
4015 (vld1q_u8): Likewise.
4016 (vld1q_u32): Likewise.
4017 (vld1q_u16): Likewise.
4018 (vldrhq_gather_offset_s32): Likewise.
4019 (vldrhq_gather_offset_s16): Likewise.
4020 (vldrhq_gather_offset_u32): Likewise.
4021 (vldrhq_gather_offset_u16): Likewise.
4022 (vldrhq_gather_offset_z_s32): Likewise.
4023 (vldrhq_gather_offset_z_s16): Likewise.
4024 (vldrhq_gather_offset_z_u32): Likewise.
4025 (vldrhq_gather_offset_z_u16): Likewise.
4026 (vldrhq_gather_shifted_offset_s32): Likewise.
4027 (vldrhq_gather_shifted_offset_s16): Likewise.
4028 (vldrhq_gather_shifted_offset_u32): Likewise.
4029 (vldrhq_gather_shifted_offset_u16): Likewise.
4030 (vldrhq_gather_shifted_offset_z_s32): Likewise.
4031 (vldrhq_gather_shifted_offset_z_s16): Likewise.
4032 (vldrhq_gather_shifted_offset_z_u32): Likewise.
4033 (vldrhq_gather_shifted_offset_z_u16): Likewise.
4034 (vldrhq_s32): Likewise.
4035 (vldrhq_s16): Likewise.
4036 (vldrhq_u32): Likewise.
4037 (vldrhq_u16): Likewise.
4038 (vldrhq_z_s32): Likewise.
4039 (vldrhq_z_s16): Likewise.
4040 (vldrhq_z_u32): Likewise.
4041 (vldrhq_z_u16): Likewise.
4042 (vldrwq_s32): Likewise.
4043 (vldrwq_u32): Likewise.
4044 (vldrwq_z_s32): Likewise.
4045 (vldrwq_z_u32): Likewise.
4046 (vld1q_f32): Likewise.
4047 (vld1q_f16): Likewise.
4048 (vldrhq_f16): Likewise.
4049 (vldrhq_z_f16): Likewise.
4050 (vldrwq_f32): Likewise.
4051 (vldrwq_z_f32): Likewise.
4052 (__arm_vld1q_s8): Define intrinsic.
4053 (__arm_vld1q_s32): Likewise.
4054 (__arm_vld1q_s16): Likewise.
4055 (__arm_vld1q_u8): Likewise.
4056 (__arm_vld1q_u32): Likewise.
4057 (__arm_vld1q_u16): Likewise.
4058 (__arm_vldrhq_gather_offset_s32): Likewise.
4059 (__arm_vldrhq_gather_offset_s16): Likewise.
4060 (__arm_vldrhq_gather_offset_u32): Likewise.
4061 (__arm_vldrhq_gather_offset_u16): Likewise.
4062 (__arm_vldrhq_gather_offset_z_s32): Likewise.
4063 (__arm_vldrhq_gather_offset_z_s16): Likewise.
4064 (__arm_vldrhq_gather_offset_z_u32): Likewise.
4065 (__arm_vldrhq_gather_offset_z_u16): Likewise.
4066 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
4067 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
4068 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
4069 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
4070 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
4071 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
4072 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
4073 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
4074 (__arm_vldrhq_s32): Likewise.
4075 (__arm_vldrhq_s16): Likewise.
4076 (__arm_vldrhq_u32): Likewise.
4077 (__arm_vldrhq_u16): Likewise.
4078 (__arm_vldrhq_z_s32): Likewise.
4079 (__arm_vldrhq_z_s16): Likewise.
4080 (__arm_vldrhq_z_u32): Likewise.
4081 (__arm_vldrhq_z_u16): Likewise.
4082 (__arm_vldrwq_s32): Likewise.
4083 (__arm_vldrwq_u32): Likewise.
4084 (__arm_vldrwq_z_s32): Likewise.
4085 (__arm_vldrwq_z_u32): Likewise.
4086 (__arm_vld1q_f32): Likewise.
4087 (__arm_vld1q_f16): Likewise.
4088 (__arm_vldrwq_f32): Likewise.
4089 (__arm_vldrwq_z_f32): Likewise.
4090 (__arm_vldrhq_z_f16): Likewise.
4091 (__arm_vldrhq_f16): Likewise.
4092 (vld1q): Define polymorphic variant.
4093 (vldrhq_gather_offset): Likewise.
4094 (vldrhq_gather_offset_z): Likewise.
4095 (vldrhq_gather_shifted_offset): Likewise.
4096 (vldrhq_gather_shifted_offset_z): Likewise.
4097 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
4101 (LDRGU_Z): Likewise.
4103 (LDRGS_Z): Likewise.
4105 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
4106 (V_sz_elem1): Likewise.
4107 (VLD1Q): Define iterator.
4108 (VLDRHGOQ): Likewise.
4109 (VLDRHGSOQ): Likewise.
4112 (mve_vldrhq_fv8hf): Define RTL pattern.
4113 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
4114 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
4115 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
4116 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
4117 (mve_vldrhq_<supf><mode>): Likewise.
4118 (mve_vldrhq_z_fv8hf): Likewise.
4119 (mve_vldrhq_z_<supf><mode>): Likewise.
4120 (mve_vldrwq_fv4sf): Likewise.
4121 (mve_vldrwq_<supf>v4si): Likewise.
4122 (mve_vldrwq_z_fv4sf): Likewise.
4123 (mve_vldrwq_z_<supf>v4si): Likewise.
4124 (mve_vld1q_f<mode>): Define RTL expand pattern.
4125 (mve_vld1q_<supf><mode>): Likewise.
4127 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4128 Mihail Ionescu <mihail.ionescu@arm.com>
4129 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4131 * config/arm/arm_mve.h (vld1q_s8): Define macro.
4132 (vld1q_s32): Likewise.
4133 (vld1q_s16): Likewise.
4134 (vld1q_u8): Likewise.
4135 (vld1q_u32): Likewise.
4136 (vld1q_u16): Likewise.
4137 (vldrhq_gather_offset_s32): Likewise.
4138 (vldrhq_gather_offset_s16): Likewise.
4139 (vldrhq_gather_offset_u32): Likewise.
4140 (vldrhq_gather_offset_u16): Likewise.
4141 (vldrhq_gather_offset_z_s32): Likewise.
4142 (vldrhq_gather_offset_z_s16): Likewise.
4143 (vldrhq_gather_offset_z_u32): Likewise.
4144 (vldrhq_gather_offset_z_u16): Likewise.
4145 (vldrhq_gather_shifted_offset_s32): Likewise.
4146 (vldrhq_gather_shifted_offset_s16): Likewise.
4147 (vldrhq_gather_shifted_offset_u32): Likewise.
4148 (vldrhq_gather_shifted_offset_u16): Likewise.
4149 (vldrhq_gather_shifted_offset_z_s32): Likewise.
4150 (vldrhq_gather_shifted_offset_z_s16): Likewise.
4151 (vldrhq_gather_shifted_offset_z_u32): Likewise.
4152 (vldrhq_gather_shifted_offset_z_u16): Likewise.
4153 (vldrhq_s32): Likewise.
4154 (vldrhq_s16): Likewise.
4155 (vldrhq_u32): Likewise.
4156 (vldrhq_u16): Likewise.
4157 (vldrhq_z_s32): Likewise.
4158 (vldrhq_z_s16): Likewise.
4159 (vldrhq_z_u32): Likewise.
4160 (vldrhq_z_u16): Likewise.
4161 (vldrwq_s32): Likewise.
4162 (vldrwq_u32): Likewise.
4163 (vldrwq_z_s32): Likewise.
4164 (vldrwq_z_u32): Likewise.
4165 (vld1q_f32): Likewise.
4166 (vld1q_f16): Likewise.
4167 (vldrhq_f16): Likewise.
4168 (vldrhq_z_f16): Likewise.
4169 (vldrwq_f32): Likewise.
4170 (vldrwq_z_f32): Likewise.
4171 (__arm_vld1q_s8): Define intrinsic.
4172 (__arm_vld1q_s32): Likewise.
4173 (__arm_vld1q_s16): Likewise.
4174 (__arm_vld1q_u8): Likewise.
4175 (__arm_vld1q_u32): Likewise.
4176 (__arm_vld1q_u16): Likewise.
4177 (__arm_vldrhq_gather_offset_s32): Likewise.
4178 (__arm_vldrhq_gather_offset_s16): Likewise.
4179 (__arm_vldrhq_gather_offset_u32): Likewise.
4180 (__arm_vldrhq_gather_offset_u16): Likewise.
4181 (__arm_vldrhq_gather_offset_z_s32): Likewise.
4182 (__arm_vldrhq_gather_offset_z_s16): Likewise.
4183 (__arm_vldrhq_gather_offset_z_u32): Likewise.
4184 (__arm_vldrhq_gather_offset_z_u16): Likewise.
4185 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
4186 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
4187 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
4188 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
4189 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
4190 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
4191 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
4192 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
4193 (__arm_vldrhq_s32): Likewise.
4194 (__arm_vldrhq_s16): Likewise.
4195 (__arm_vldrhq_u32): Likewise.
4196 (__arm_vldrhq_u16): Likewise.
4197 (__arm_vldrhq_z_s32): Likewise.
4198 (__arm_vldrhq_z_s16): Likewise.
4199 (__arm_vldrhq_z_u32): Likewise.
4200 (__arm_vldrhq_z_u16): Likewise.
4201 (__arm_vldrwq_s32): Likewise.
4202 (__arm_vldrwq_u32): Likewise.
4203 (__arm_vldrwq_z_s32): Likewise.
4204 (__arm_vldrwq_z_u32): Likewise.
4205 (__arm_vld1q_f32): Likewise.
4206 (__arm_vld1q_f16): Likewise.
4207 (__arm_vldrwq_f32): Likewise.
4208 (__arm_vldrwq_z_f32): Likewise.
4209 (__arm_vldrhq_z_f16): Likewise.
4210 (__arm_vldrhq_f16): Likewise.
4211 (vld1q): Define polymorphic variant.
4212 (vldrhq_gather_offset): Likewise.
4213 (vldrhq_gather_offset_z): Likewise.
4214 (vldrhq_gather_shifted_offset): Likewise.
4215 (vldrhq_gather_shifted_offset_z): Likewise.
4216 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
4220 (LDRGU_Z): Likewise.
4222 (LDRGS_Z): Likewise.
4224 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
4225 (V_sz_elem1): Likewise.
4226 (VLD1Q): Define iterator.
4227 (VLDRHGOQ): Likewise.
4228 (VLDRHGSOQ): Likewise.
4231 (mve_vldrhq_fv8hf): Define RTL pattern.
4232 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
4233 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
4234 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
4235 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
4236 (mve_vldrhq_<supf><mode>): Likewise.
4237 (mve_vldrhq_z_fv8hf): Likewise.
4238 (mve_vldrhq_z_<supf><mode>): Likewise.
4239 (mve_vldrwq_fv4sf): Likewise.
4240 (mve_vldrwq_<supf>v4si): Likewise.
4241 (mve_vldrwq_z_fv4sf): Likewise.
4242 (mve_vldrwq_z_<supf>v4si): Likewise.
4243 (mve_vld1q_f<mode>): Define RTL expand pattern.
4244 (mve_vld1q_<supf><mode>): Likewise.
4246 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4247 Mihail Ionescu <mihail.ionescu@arm.com>
4248 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4250 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
4252 (LDRGBU_Z_QUALIFIERS): Likewise.
4253 (LDRGS_Z_QUALIFIERS): Likewise.
4254 (LDRGU_Z_QUALIFIERS): Likewise.
4255 (LDRS_Z_QUALIFIERS): Likewise.
4256 (LDRU_Z_QUALIFIERS): Likewise.
4257 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
4258 (vldrbq_gather_offset_z_u8): Likewise.
4259 (vldrbq_gather_offset_z_s32): Likewise.
4260 (vldrbq_gather_offset_z_u16): Likewise.
4261 (vldrbq_gather_offset_z_u32): Likewise.
4262 (vldrbq_gather_offset_z_s8): Likewise.
4263 (vldrbq_z_s16): Likewise.
4264 (vldrbq_z_u8): Likewise.
4265 (vldrbq_z_s8): Likewise.
4266 (vldrbq_z_s32): Likewise.
4267 (vldrbq_z_u16): Likewise.
4268 (vldrbq_z_u32): Likewise.
4269 (vldrwq_gather_base_z_u32): Likewise.
4270 (vldrwq_gather_base_z_s32): Likewise.
4271 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
4272 (__arm_vldrbq_gather_offset_z_s32): Likewise.
4273 (__arm_vldrbq_gather_offset_z_s16): Likewise.
4274 (__arm_vldrbq_gather_offset_z_u8): Likewise.
4275 (__arm_vldrbq_gather_offset_z_u32): Likewise.
4276 (__arm_vldrbq_gather_offset_z_u16): Likewise.
4277 (__arm_vldrbq_z_s8): Likewise.
4278 (__arm_vldrbq_z_s32): Likewise.
4279 (__arm_vldrbq_z_s16): Likewise.
4280 (__arm_vldrbq_z_u8): Likewise.
4281 (__arm_vldrbq_z_u32): Likewise.
4282 (__arm_vldrbq_z_u16): Likewise.
4283 (__arm_vldrwq_gather_base_z_s32): Likewise.
4284 (__arm_vldrwq_gather_base_z_u32): Likewise.
4285 (vldrbq_gather_offset_z): Define polymorphic variant.
4286 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
4288 (LDRGBU_Z_QUALIFIERS): Likewise.
4289 (LDRGS_Z_QUALIFIERS): Likewise.
4290 (LDRGU_Z_QUALIFIERS): Likewise.
4291 (LDRS_Z_QUALIFIERS): Likewise.
4292 (LDRU_Z_QUALIFIERS): Likewise.
4293 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
4295 (mve_vldrbq_z_<supf><mode>): Likewise.
4296 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
4298 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4299 Mihail Ionescu <mihail.ionescu@arm.com>
4300 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4302 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
4304 (STRU_P_QUALIFIERS): Likewise.
4305 (STRSU_P_QUALIFIERS): Likewise.
4306 (STRSS_P_QUALIFIERS): Likewise.
4307 (STRSBS_P_QUALIFIERS): Likewise.
4308 (STRSBU_P_QUALIFIERS): Likewise.
4309 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
4310 (vstrbq_p_s32): Likewise.
4311 (vstrbq_p_s16): Likewise.
4312 (vstrbq_p_u8): Likewise.
4313 (vstrbq_p_u32): Likewise.
4314 (vstrbq_p_u16): Likewise.
4315 (vstrbq_scatter_offset_p_s8): Likewise.
4316 (vstrbq_scatter_offset_p_s32): Likewise.
4317 (vstrbq_scatter_offset_p_s16): Likewise.
4318 (vstrbq_scatter_offset_p_u8): Likewise.
4319 (vstrbq_scatter_offset_p_u32): Likewise.
4320 (vstrbq_scatter_offset_p_u16): Likewise.
4321 (vstrwq_scatter_base_p_s32): Likewise.
4322 (vstrwq_scatter_base_p_u32): Likewise.
4323 (__arm_vstrbq_p_s8): Define intrinsic.
4324 (__arm_vstrbq_p_s32): Likewise.
4325 (__arm_vstrbq_p_s16): Likewise.
4326 (__arm_vstrbq_p_u8): Likewise.
4327 (__arm_vstrbq_p_u32): Likewise.
4328 (__arm_vstrbq_p_u16): Likewise.
4329 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
4330 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
4331 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
4332 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
4333 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
4334 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
4335 (__arm_vstrwq_scatter_base_p_s32): Likewise.
4336 (__arm_vstrwq_scatter_base_p_u32): Likewise.
4337 (vstrbq_p): Define polymorphic variant.
4338 (vstrbq_scatter_offset_p): Likewise.
4339 (vstrwq_scatter_base_p): Likewise.
4340 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
4342 (STRU_P_QUALIFIERS): Likewise.
4343 (STRSU_P_QUALIFIERS): Likewise.
4344 (STRSS_P_QUALIFIERS): Likewise.
4345 (STRSBS_P_QUALIFIERS): Likewise.
4346 (STRSBU_P_QUALIFIERS): Likewise.
4347 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
4349 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
4350 (mve_vstrbq_p_<supf><mode>): Likewise.
4352 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4353 Mihail Ionescu <mihail.ionescu@arm.com>
4354 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4356 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
4358 (LDRGS_QUALIFIERS): Likewise.
4359 (LDRS_QUALIFIERS): Likewise.
4360 (LDRU_QUALIFIERS): Likewise.
4361 (LDRGBS_QUALIFIERS): Likewise.
4362 (LDRGBU_QUALIFIERS): Likewise.
4363 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
4364 (vldrbq_gather_offset_s8): Likewise.
4365 (vldrbq_s8): Likewise.
4366 (vldrbq_u8): Likewise.
4367 (vldrbq_gather_offset_u16): Likewise.
4368 (vldrbq_gather_offset_s16): Likewise.
4369 (vldrbq_s16): Likewise.
4370 (vldrbq_u16): Likewise.
4371 (vldrbq_gather_offset_u32): Likewise.
4372 (vldrbq_gather_offset_s32): Likewise.
4373 (vldrbq_s32): Likewise.
4374 (vldrbq_u32): Likewise.
4375 (vldrwq_gather_base_s32): Likewise.
4376 (vldrwq_gather_base_u32): Likewise.
4377 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
4378 (__arm_vldrbq_gather_offset_s8): Likewise.
4379 (__arm_vldrbq_s8): Likewise.
4380 (__arm_vldrbq_u8): Likewise.
4381 (__arm_vldrbq_gather_offset_u16): Likewise.
4382 (__arm_vldrbq_gather_offset_s16): Likewise.
4383 (__arm_vldrbq_s16): Likewise.
4384 (__arm_vldrbq_u16): Likewise.
4385 (__arm_vldrbq_gather_offset_u32): Likewise.
4386 (__arm_vldrbq_gather_offset_s32): Likewise.
4387 (__arm_vldrbq_s32): Likewise.
4388 (__arm_vldrbq_u32): Likewise.
4389 (__arm_vldrwq_gather_base_s32): Likewise.
4390 (__arm_vldrwq_gather_base_u32): Likewise.
4391 (vldrbq_gather_offset): Define polymorphic variant.
4392 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
4394 (LDRGS_QUALIFIERS): Likewise.
4395 (LDRS_QUALIFIERS): Likewise.
4396 (LDRU_QUALIFIERS): Likewise.
4397 (LDRGBS_QUALIFIERS): Likewise.
4398 (LDRGBU_QUALIFIERS): Likewise.
4399 * config/arm/mve.md (VLDRBGOQ): Define iterator.
4401 (VLDRWGBQ): Likewise.
4402 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
4403 (mve_vldrbq_<supf><mode>): Likewise.
4404 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
4406 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4407 Mihail Ionescu <mihail.ionescu@arm.com>
4408 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4410 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
4411 (STRU_QUALIFIERS): Likewise.
4412 (STRSS_QUALIFIERS): Likewise.
4413 (STRSU_QUALIFIERS): Likewise.
4414 (STRSBS_QUALIFIERS): Likewise.
4415 (STRSBU_QUALIFIERS): Likewise.
4416 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
4417 (vstrbq_u8): Likewise.
4418 (vstrbq_u16): Likewise.
4419 (vstrbq_scatter_offset_s8): Likewise.
4420 (vstrbq_scatter_offset_u8): Likewise.
4421 (vstrbq_scatter_offset_u16): Likewise.
4422 (vstrbq_s16): Likewise.
4423 (vstrbq_u32): Likewise.
4424 (vstrbq_scatter_offset_s16): Likewise.
4425 (vstrbq_scatter_offset_u32): Likewise.
4426 (vstrbq_s32): Likewise.
4427 (vstrbq_scatter_offset_s32): Likewise.
4428 (vstrwq_scatter_base_s32): Likewise.
4429 (vstrwq_scatter_base_u32): Likewise.
4430 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
4431 (__arm_vstrbq_scatter_offset_s32): Likewise.
4432 (__arm_vstrbq_scatter_offset_s16): Likewise.
4433 (__arm_vstrbq_scatter_offset_u8): Likewise.
4434 (__arm_vstrbq_scatter_offset_u32): Likewise.
4435 (__arm_vstrbq_scatter_offset_u16): Likewise.
4436 (__arm_vstrbq_s8): Likewise.
4437 (__arm_vstrbq_s32): Likewise.
4438 (__arm_vstrbq_s16): Likewise.
4439 (__arm_vstrbq_u8): Likewise.
4440 (__arm_vstrbq_u32): Likewise.
4441 (__arm_vstrbq_u16): Likewise.
4442 (__arm_vstrwq_scatter_base_s32): Likewise.
4443 (__arm_vstrwq_scatter_base_u32): Likewise.
4444 (vstrbq): Define polymorphic variant.
4445 (vstrbq_scatter_offset): Likewise.
4446 (vstrwq_scatter_base): Likewise.
4447 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
4449 (STRU_QUALIFIERS): Likewise.
4450 (STRSS_QUALIFIERS): Likewise.
4451 (STRSU_QUALIFIERS): Likewise.
4452 (STRSBS_QUALIFIERS): Likewise.
4453 (STRSBU_QUALIFIERS): Likewise.
4454 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
4455 (VSTRWSBQ): Define iterators.
4456 (VSTRBSOQ): Likewise.
4458 (mve_vstrbq_<supf><mode>): Define RTL pattern.
4459 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
4460 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
4462 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4463 Mihail Ionescu <mihail.ionescu@arm.com>
4464 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4466 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
4467 (vabdq_m_f16): Likewise.
4468 (vaddq_m_f32): Likewise.
4469 (vaddq_m_f16): Likewise.
4470 (vaddq_m_n_f32): Likewise.
4471 (vaddq_m_n_f16): Likewise.
4472 (vandq_m_f32): Likewise.
4473 (vandq_m_f16): Likewise.
4474 (vbicq_m_f32): Likewise.
4475 (vbicq_m_f16): Likewise.
4476 (vbrsrq_m_n_f32): Likewise.
4477 (vbrsrq_m_n_f16): Likewise.
4478 (vcaddq_rot270_m_f32): Likewise.
4479 (vcaddq_rot270_m_f16): Likewise.
4480 (vcaddq_rot90_m_f32): Likewise.
4481 (vcaddq_rot90_m_f16): Likewise.
4482 (vcmlaq_m_f32): Likewise.
4483 (vcmlaq_m_f16): Likewise.
4484 (vcmlaq_rot180_m_f32): Likewise.
4485 (vcmlaq_rot180_m_f16): Likewise.
4486 (vcmlaq_rot270_m_f32): Likewise.
4487 (vcmlaq_rot270_m_f16): Likewise.
4488 (vcmlaq_rot90_m_f32): Likewise.
4489 (vcmlaq_rot90_m_f16): Likewise.
4490 (vcmulq_m_f32): Likewise.
4491 (vcmulq_m_f16): Likewise.
4492 (vcmulq_rot180_m_f32): Likewise.
4493 (vcmulq_rot180_m_f16): Likewise.
4494 (vcmulq_rot270_m_f32): Likewise.
4495 (vcmulq_rot270_m_f16): Likewise.
4496 (vcmulq_rot90_m_f32): Likewise.
4497 (vcmulq_rot90_m_f16): Likewise.
4498 (vcvtq_m_n_s32_f32): Likewise.
4499 (vcvtq_m_n_s16_f16): Likewise.
4500 (vcvtq_m_n_u32_f32): Likewise.
4501 (vcvtq_m_n_u16_f16): Likewise.
4502 (veorq_m_f32): Likewise.
4503 (veorq_m_f16): Likewise.
4504 (vfmaq_m_f32): Likewise.
4505 (vfmaq_m_f16): Likewise.
4506 (vfmaq_m_n_f32): Likewise.
4507 (vfmaq_m_n_f16): Likewise.
4508 (vfmasq_m_n_f32): Likewise.
4509 (vfmasq_m_n_f16): Likewise.
4510 (vfmsq_m_f32): Likewise.
4511 (vfmsq_m_f16): Likewise.
4512 (vmaxnmq_m_f32): Likewise.
4513 (vmaxnmq_m_f16): Likewise.
4514 (vminnmq_m_f32): Likewise.
4515 (vminnmq_m_f16): Likewise.
4516 (vmulq_m_f32): Likewise.
4517 (vmulq_m_f16): Likewise.
4518 (vmulq_m_n_f32): Likewise.
4519 (vmulq_m_n_f16): Likewise.
4520 (vornq_m_f32): Likewise.
4521 (vornq_m_f16): Likewise.
4522 (vorrq_m_f32): Likewise.
4523 (vorrq_m_f16): Likewise.
4524 (vsubq_m_f32): Likewise.
4525 (vsubq_m_f16): Likewise.
4526 (vsubq_m_n_f32): Likewise.
4527 (vsubq_m_n_f16): Likewise.
4528 (__attribute__): Likewise.
4529 (__arm_vabdq_m_f32): Likewise.
4530 (__arm_vabdq_m_f16): Likewise.
4531 (__arm_vaddq_m_f32): Likewise.
4532 (__arm_vaddq_m_f16): Likewise.
4533 (__arm_vaddq_m_n_f32): Likewise.
4534 (__arm_vaddq_m_n_f16): Likewise.
4535 (__arm_vandq_m_f32): Likewise.
4536 (__arm_vandq_m_f16): Likewise.
4537 (__arm_vbicq_m_f32): Likewise.
4538 (__arm_vbicq_m_f16): Likewise.
4539 (__arm_vbrsrq_m_n_f32): Likewise.
4540 (__arm_vbrsrq_m_n_f16): Likewise.
4541 (__arm_vcaddq_rot270_m_f32): Likewise.
4542 (__arm_vcaddq_rot270_m_f16): Likewise.
4543 (__arm_vcaddq_rot90_m_f32): Likewise.
4544 (__arm_vcaddq_rot90_m_f16): Likewise.
4545 (__arm_vcmlaq_m_f32): Likewise.
4546 (__arm_vcmlaq_m_f16): Likewise.
4547 (__arm_vcmlaq_rot180_m_f32): Likewise.
4548 (__arm_vcmlaq_rot180_m_f16): Likewise.
4549 (__arm_vcmlaq_rot270_m_f32): Likewise.
4550 (__arm_vcmlaq_rot270_m_f16): Likewise.
4551 (__arm_vcmlaq_rot90_m_f32): Likewise.
4552 (__arm_vcmlaq_rot90_m_f16): Likewise.
4553 (__arm_vcmulq_m_f32): Likewise.
4554 (__arm_vcmulq_m_f16): Likewise.
4555 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
4556 (__arm_vcmulq_rot180_m_f16): Likewise.
4557 (__arm_vcmulq_rot270_m_f32): Likewise.
4558 (__arm_vcmulq_rot270_m_f16): Likewise.
4559 (__arm_vcmulq_rot90_m_f32): Likewise.
4560 (__arm_vcmulq_rot90_m_f16): Likewise.
4561 (__arm_vcvtq_m_n_s32_f32): Likewise.
4562 (__arm_vcvtq_m_n_s16_f16): Likewise.
4563 (__arm_vcvtq_m_n_u32_f32): Likewise.
4564 (__arm_vcvtq_m_n_u16_f16): Likewise.
4565 (__arm_veorq_m_f32): Likewise.
4566 (__arm_veorq_m_f16): Likewise.
4567 (__arm_vfmaq_m_f32): Likewise.
4568 (__arm_vfmaq_m_f16): Likewise.
4569 (__arm_vfmaq_m_n_f32): Likewise.
4570 (__arm_vfmaq_m_n_f16): Likewise.
4571 (__arm_vfmasq_m_n_f32): Likewise.
4572 (__arm_vfmasq_m_n_f16): Likewise.
4573 (__arm_vfmsq_m_f32): Likewise.
4574 (__arm_vfmsq_m_f16): Likewise.
4575 (__arm_vmaxnmq_m_f32): Likewise.
4576 (__arm_vmaxnmq_m_f16): Likewise.
4577 (__arm_vminnmq_m_f32): Likewise.
4578 (__arm_vminnmq_m_f16): Likewise.
4579 (__arm_vmulq_m_f32): Likewise.
4580 (__arm_vmulq_m_f16): Likewise.
4581 (__arm_vmulq_m_n_f32): Likewise.
4582 (__arm_vmulq_m_n_f16): Likewise.
4583 (__arm_vornq_m_f32): Likewise.
4584 (__arm_vornq_m_f16): Likewise.
4585 (__arm_vorrq_m_f32): Likewise.
4586 (__arm_vorrq_m_f16): Likewise.
4587 (__arm_vsubq_m_f32): Likewise.
4588 (__arm_vsubq_m_f16): Likewise.
4589 (__arm_vsubq_m_n_f32): Likewise.
4590 (__arm_vsubq_m_n_f16): Likewise.
4591 (vabdq_m): Define polymorphic variant.
4592 (vaddq_m): Likewise.
4593 (vaddq_m_n): Likewise.
4594 (vandq_m): Likewise.
4595 (vbicq_m): Likewise.
4596 (vbrsrq_m_n): Likewise.
4597 (vcaddq_rot270_m): Likewise.
4598 (vcaddq_rot90_m): Likewise.
4599 (vcmlaq_m): Likewise.
4600 (vcmlaq_rot180_m): Likewise.
4601 (vcmlaq_rot270_m): Likewise.
4602 (vcmlaq_rot90_m): Likewise.
4603 (vcmulq_m): Likewise.
4604 (vcmulq_rot180_m): Likewise.
4605 (vcmulq_rot270_m): Likewise.
4606 (vcmulq_rot90_m): Likewise.
4607 (veorq_m): Likewise.
4608 (vfmaq_m): Likewise.
4609 (vfmaq_m_n): Likewise.
4610 (vfmasq_m_n): Likewise.
4611 (vfmsq_m): Likewise.
4612 (vmaxnmq_m): Likewise.
4613 (vminnmq_m): Likewise.
4614 (vmulq_m): Likewise.
4615 (vmulq_m_n): Likewise.
4616 (vornq_m): Likewise.
4617 (vsubq_m): Likewise.
4618 (vsubq_m_n): Likewise.
4619 (vorrq_m): Likewise.
4620 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
4622 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4623 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
4624 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
4625 (mve_vaddq_m_f<mode>): Likewise.
4626 (mve_vaddq_m_n_f<mode>): Likewise.
4627 (mve_vandq_m_f<mode>): Likewise.
4628 (mve_vbicq_m_f<mode>): Likewise.
4629 (mve_vbrsrq_m_n_f<mode>): Likewise.
4630 (mve_vcaddq_rot270_m_f<mode>): Likewise.
4631 (mve_vcaddq_rot90_m_f<mode>): Likewise.
4632 (mve_vcmlaq_m_f<mode>): Likewise.
4633 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
4634 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
4635 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
4636 (mve_vcmulq_m_f<mode>): Likewise.
4637 (mve_vcmulq_rot180_m_f<mode>): Likewise.
4638 (mve_vcmulq_rot270_m_f<mode>): Likewise.
4639 (mve_vcmulq_rot90_m_f<mode>): Likewise.
4640 (mve_veorq_m_f<mode>): Likewise.
4641 (mve_vfmaq_m_f<mode>): Likewise.
4642 (mve_vfmaq_m_n_f<mode>): Likewise.
4643 (mve_vfmasq_m_n_f<mode>): Likewise.
4644 (mve_vfmsq_m_f<mode>): Likewise.
4645 (mve_vmaxnmq_m_f<mode>): Likewise.
4646 (mve_vminnmq_m_f<mode>): Likewise.
4647 (mve_vmulq_m_f<mode>): Likewise.
4648 (mve_vmulq_m_n_f<mode>): Likewise.
4649 (mve_vornq_m_f<mode>): Likewise.
4650 (mve_vorrq_m_f<mode>): Likewise.
4651 (mve_vsubq_m_f<mode>): Likewise.
4652 (mve_vsubq_m_n_f<mode>): Likewise.
4654 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4655 Mihail Ionescu <mihail.ionescu@arm.com>
4656 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4658 * config/arm/arm-protos.h (arm_mve_immediate_check):
4659 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
4660 mode and interger value.
4661 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
4662 (vmlaldavaq_p_s16): Likewise.
4663 (vmlaldavaq_p_u32): Likewise.
4664 (vmlaldavaq_p_u16): Likewise.
4665 (vmlaldavaxq_p_s32): Likewise.
4666 (vmlaldavaxq_p_s16): Likewise.
4667 (vmlaldavaxq_p_u32): Likewise.
4668 (vmlaldavaxq_p_u16): Likewise.
4669 (vmlsldavaq_p_s32): Likewise.
4670 (vmlsldavaq_p_s16): Likewise.
4671 (vmlsldavaxq_p_s32): Likewise.
4672 (vmlsldavaxq_p_s16): Likewise.
4673 (vmullbq_poly_m_p8): Likewise.
4674 (vmullbq_poly_m_p16): Likewise.
4675 (vmulltq_poly_m_p8): Likewise.
4676 (vmulltq_poly_m_p16): Likewise.
4677 (vqdmullbq_m_n_s32): Likewise.
4678 (vqdmullbq_m_n_s16): Likewise.
4679 (vqdmullbq_m_s32): Likewise.
4680 (vqdmullbq_m_s16): Likewise.
4681 (vqdmulltq_m_n_s32): Likewise.
4682 (vqdmulltq_m_n_s16): Likewise.
4683 (vqdmulltq_m_s32): Likewise.
4684 (vqdmulltq_m_s16): Likewise.
4685 (vqrshrnbq_m_n_s32): Likewise.
4686 (vqrshrnbq_m_n_s16): Likewise.
4687 (vqrshrnbq_m_n_u32): Likewise.
4688 (vqrshrnbq_m_n_u16): Likewise.
4689 (vqrshrntq_m_n_s32): Likewise.
4690 (vqrshrntq_m_n_s16): Likewise.
4691 (vqrshrntq_m_n_u32): Likewise.
4692 (vqrshrntq_m_n_u16): Likewise.
4693 (vqrshrunbq_m_n_s32): Likewise.
4694 (vqrshrunbq_m_n_s16): Likewise.
4695 (vqrshruntq_m_n_s32): Likewise.
4696 (vqrshruntq_m_n_s16): Likewise.
4697 (vqshrnbq_m_n_s32): Likewise.
4698 (vqshrnbq_m_n_s16): Likewise.
4699 (vqshrnbq_m_n_u32): Likewise.
4700 (vqshrnbq_m_n_u16): Likewise.
4701 (vqshrntq_m_n_s32): Likewise.
4702 (vqshrntq_m_n_s16): Likewise.
4703 (vqshrntq_m_n_u32): Likewise.
4704 (vqshrntq_m_n_u16): Likewise.
4705 (vqshrunbq_m_n_s32): Likewise.
4706 (vqshrunbq_m_n_s16): Likewise.
4707 (vqshruntq_m_n_s32): Likewise.
4708 (vqshruntq_m_n_s16): Likewise.
4709 (vrmlaldavhaq_p_s32): Likewise.
4710 (vrmlaldavhaq_p_u32): Likewise.
4711 (vrmlaldavhaxq_p_s32): Likewise.
4712 (vrmlsldavhaq_p_s32): Likewise.
4713 (vrmlsldavhaxq_p_s32): Likewise.
4714 (vrshrnbq_m_n_s32): Likewise.
4715 (vrshrnbq_m_n_s16): Likewise.
4716 (vrshrnbq_m_n_u32): Likewise.
4717 (vrshrnbq_m_n_u16): Likewise.
4718 (vrshrntq_m_n_s32): Likewise.
4719 (vrshrntq_m_n_s16): Likewise.
4720 (vrshrntq_m_n_u32): Likewise.
4721 (vrshrntq_m_n_u16): Likewise.
4722 (vshllbq_m_n_s8): Likewise.
4723 (vshllbq_m_n_s16): Likewise.
4724 (vshllbq_m_n_u8): Likewise.
4725 (vshllbq_m_n_u16): Likewise.
4726 (vshlltq_m_n_s8): Likewise.
4727 (vshlltq_m_n_s16): Likewise.
4728 (vshlltq_m_n_u8): Likewise.
4729 (vshlltq_m_n_u16): Likewise.
4730 (vshrnbq_m_n_s32): Likewise.
4731 (vshrnbq_m_n_s16): Likewise.
4732 (vshrnbq_m_n_u32): Likewise.
4733 (vshrnbq_m_n_u16): Likewise.
4734 (vshrntq_m_n_s32): Likewise.
4735 (vshrntq_m_n_s16): Likewise.
4736 (vshrntq_m_n_u32): Likewise.
4737 (vshrntq_m_n_u16): Likewise.
4738 (__arm_vmlaldavaq_p_s32): Define intrinsic.
4739 (__arm_vmlaldavaq_p_s16): Likewise.
4740 (__arm_vmlaldavaq_p_u32): Likewise.
4741 (__arm_vmlaldavaq_p_u16): Likewise.
4742 (__arm_vmlaldavaxq_p_s32): Likewise.
4743 (__arm_vmlaldavaxq_p_s16): Likewise.
4744 (__arm_vmlaldavaxq_p_u32): Likewise.
4745 (__arm_vmlaldavaxq_p_u16): Likewise.
4746 (__arm_vmlsldavaq_p_s32): Likewise.
4747 (__arm_vmlsldavaq_p_s16): Likewise.
4748 (__arm_vmlsldavaxq_p_s32): Likewise.
4749 (__arm_vmlsldavaxq_p_s16): Likewise.
4750 (__arm_vmullbq_poly_m_p8): Likewise.
4751 (__arm_vmullbq_poly_m_p16): Likewise.
4752 (__arm_vmulltq_poly_m_p8): Likewise.
4753 (__arm_vmulltq_poly_m_p16): Likewise.
4754 (__arm_vqdmullbq_m_n_s32): Likewise.
4755 (__arm_vqdmullbq_m_n_s16): Likewise.
4756 (__arm_vqdmullbq_m_s32): Likewise.
4757 (__arm_vqdmullbq_m_s16): Likewise.
4758 (__arm_vqdmulltq_m_n_s32): Likewise.
4759 (__arm_vqdmulltq_m_n_s16): Likewise.
4760 (__arm_vqdmulltq_m_s32): Likewise.
4761 (__arm_vqdmulltq_m_s16): Likewise.
4762 (__arm_vqrshrnbq_m_n_s32): Likewise.
4763 (__arm_vqrshrnbq_m_n_s16): Likewise.
4764 (__arm_vqrshrnbq_m_n_u32): Likewise.
4765 (__arm_vqrshrnbq_m_n_u16): Likewise.
4766 (__arm_vqrshrntq_m_n_s32): Likewise.
4767 (__arm_vqrshrntq_m_n_s16): Likewise.
4768 (__arm_vqrshrntq_m_n_u32): Likewise.
4769 (__arm_vqrshrntq_m_n_u16): Likewise.
4770 (__arm_vqrshrunbq_m_n_s32): Likewise.
4771 (__arm_vqrshrunbq_m_n_s16): Likewise.
4772 (__arm_vqrshruntq_m_n_s32): Likewise.
4773 (__arm_vqrshruntq_m_n_s16): Likewise.
4774 (__arm_vqshrnbq_m_n_s32): Likewise.
4775 (__arm_vqshrnbq_m_n_s16): Likewise.
4776 (__arm_vqshrnbq_m_n_u32): Likewise.
4777 (__arm_vqshrnbq_m_n_u16): Likewise.
4778 (__arm_vqshrntq_m_n_s32): Likewise.
4779 (__arm_vqshrntq_m_n_s16): Likewise.
4780 (__arm_vqshrntq_m_n_u32): Likewise.
4781 (__arm_vqshrntq_m_n_u16): Likewise.
4782 (__arm_vqshrunbq_m_n_s32): Likewise.
4783 (__arm_vqshrunbq_m_n_s16): Likewise.
4784 (__arm_vqshruntq_m_n_s32): Likewise.
4785 (__arm_vqshruntq_m_n_s16): Likewise.
4786 (__arm_vrmlaldavhaq_p_s32): Likewise.
4787 (__arm_vrmlaldavhaq_p_u32): Likewise.
4788 (__arm_vrmlaldavhaxq_p_s32): Likewise.
4789 (__arm_vrmlsldavhaq_p_s32): Likewise.
4790 (__arm_vrmlsldavhaxq_p_s32): Likewise.
4791 (__arm_vrshrnbq_m_n_s32): Likewise.
4792 (__arm_vrshrnbq_m_n_s16): Likewise.
4793 (__arm_vrshrnbq_m_n_u32): Likewise.
4794 (__arm_vrshrnbq_m_n_u16): Likewise.
4795 (__arm_vrshrntq_m_n_s32): Likewise.
4796 (__arm_vrshrntq_m_n_s16): Likewise.
4797 (__arm_vrshrntq_m_n_u32): Likewise.
4798 (__arm_vrshrntq_m_n_u16): Likewise.
4799 (__arm_vshllbq_m_n_s8): Likewise.
4800 (__arm_vshllbq_m_n_s16): Likewise.
4801 (__arm_vshllbq_m_n_u8): Likewise.
4802 (__arm_vshllbq_m_n_u16): Likewise.
4803 (__arm_vshlltq_m_n_s8): Likewise.
4804 (__arm_vshlltq_m_n_s16): Likewise.
4805 (__arm_vshlltq_m_n_u8): Likewise.
4806 (__arm_vshlltq_m_n_u16): Likewise.
4807 (__arm_vshrnbq_m_n_s32): Likewise.
4808 (__arm_vshrnbq_m_n_s16): Likewise.
4809 (__arm_vshrnbq_m_n_u32): Likewise.
4810 (__arm_vshrnbq_m_n_u16): Likewise.
4811 (__arm_vshrntq_m_n_s32): Likewise.
4812 (__arm_vshrntq_m_n_s16): Likewise.
4813 (__arm_vshrntq_m_n_u32): Likewise.
4814 (__arm_vshrntq_m_n_u16): Likewise.
4815 (vmullbq_poly_m): Define polymorphic variant.
4816 (vmulltq_poly_m): Likewise.
4817 (vshllbq_m): Likewise.
4818 (vshrntq_m_n): Likewise.
4819 (vshrnbq_m_n): Likewise.
4820 (vshlltq_m_n): Likewise.
4821 (vshllbq_m_n): Likewise.
4822 (vrshrntq_m_n): Likewise.
4823 (vrshrnbq_m_n): Likewise.
4824 (vqshruntq_m_n): Likewise.
4825 (vqshrunbq_m_n): Likewise.
4826 (vqdmullbq_m_n): Likewise.
4827 (vqdmullbq_m): Likewise.
4828 (vqdmulltq_m_n): Likewise.
4829 (vqdmulltq_m): Likewise.
4830 (vqrshrnbq_m_n): Likewise.
4831 (vqrshrntq_m_n): Likewise.
4832 (vqrshrunbq_m_n): Likewise.
4833 (vqrshruntq_m_n): Likewise.
4834 (vqshrnbq_m_n): Likewise.
4835 (vqshrntq_m_n): Likewise.
4836 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
4838 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4839 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
4840 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4841 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
4842 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
4843 (VMLALDAVAXQ_P): Likewise.
4844 (VQRSHRNBQ_M_N): Likewise.
4845 (VQRSHRNTQ_M_N): Likewise.
4846 (VQSHRNBQ_M_N): Likewise.
4847 (VQSHRNTQ_M_N): Likewise.
4848 (VRSHRNBQ_M_N): Likewise.
4849 (VRSHRNTQ_M_N): Likewise.
4850 (VSHLLBQ_M_N): Likewise.
4851 (VSHLLTQ_M_N): Likewise.
4852 (VSHRNBQ_M_N): Likewise.
4853 (VSHRNTQ_M_N): Likewise.
4854 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
4855 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
4856 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
4857 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
4858 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
4859 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
4860 (mve_vrmlaldavhaq_p_sv4si): Likewise.
4861 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
4862 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
4863 (mve_vshllbq_m_n_<supf><mode>): Likewise.
4864 (mve_vshlltq_m_n_<supf><mode>): Likewise.
4865 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
4866 (mve_vshrntq_m_n_<supf><mode>): Likewise.
4867 (mve_vmlsldavaq_p_s<mode>): Likewise.
4868 (mve_vmlsldavaxq_p_s<mode>): Likewise.
4869 (mve_vmullbq_poly_m_p<mode>): Likewise.
4870 (mve_vmulltq_poly_m_p<mode>): Likewise.
4871 (mve_vqdmullbq_m_n_s<mode>): Likewise.
4872 (mve_vqdmullbq_m_s<mode>): Likewise.
4873 (mve_vqdmulltq_m_n_s<mode>): Likewise.
4874 (mve_vqdmulltq_m_s<mode>): Likewise.
4875 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
4876 (mve_vqrshruntq_m_n_s<mode>): Likewise.
4877 (mve_vqshrunbq_m_n_s<mode>): Likewise.
4878 (mve_vqshruntq_m_n_s<mode>): Likewise.
4879 (mve_vrmlaldavhaq_p_uv4si): Likewise.
4880 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
4881 (mve_vrmlsldavhaq_p_sv4si): Likewise.
4882 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
4884 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4885 Mihail Ionescu <mihail.ionescu@arm.com>
4886 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4888 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
4889 (vabdq_m_s32): Likewise.
4890 (vabdq_m_s16): Likewise.
4891 (vabdq_m_u8): Likewise.
4892 (vabdq_m_u32): Likewise.
4893 (vabdq_m_u16): Likewise.
4894 (vaddq_m_n_s8): Likewise.
4895 (vaddq_m_n_s32): Likewise.
4896 (vaddq_m_n_s16): Likewise.
4897 (vaddq_m_n_u8): Likewise.
4898 (vaddq_m_n_u32): Likewise.
4899 (vaddq_m_n_u16): Likewise.
4900 (vaddq_m_s8): Likewise.
4901 (vaddq_m_s32): Likewise.
4902 (vaddq_m_s16): Likewise.
4903 (vaddq_m_u8): Likewise.
4904 (vaddq_m_u32): Likewise.
4905 (vaddq_m_u16): Likewise.
4906 (vandq_m_s8): Likewise.
4907 (vandq_m_s32): Likewise.
4908 (vandq_m_s16): Likewise.
4909 (vandq_m_u8): Likewise.
4910 (vandq_m_u32): Likewise.
4911 (vandq_m_u16): Likewise.
4912 (vbicq_m_s8): Likewise.
4913 (vbicq_m_s32): Likewise.
4914 (vbicq_m_s16): Likewise.
4915 (vbicq_m_u8): Likewise.
4916 (vbicq_m_u32): Likewise.
4917 (vbicq_m_u16): Likewise.
4918 (vbrsrq_m_n_s8): Likewise.
4919 (vbrsrq_m_n_s32): Likewise.
4920 (vbrsrq_m_n_s16): Likewise.
4921 (vbrsrq_m_n_u8): Likewise.
4922 (vbrsrq_m_n_u32): Likewise.
4923 (vbrsrq_m_n_u16): Likewise.
4924 (vcaddq_rot270_m_s8): Likewise.
4925 (vcaddq_rot270_m_s32): Likewise.
4926 (vcaddq_rot270_m_s16): Likewise.
4927 (vcaddq_rot270_m_u8): Likewise.
4928 (vcaddq_rot270_m_u32): Likewise.
4929 (vcaddq_rot270_m_u16): Likewise.
4930 (vcaddq_rot90_m_s8): Likewise.
4931 (vcaddq_rot90_m_s32): Likewise.
4932 (vcaddq_rot90_m_s16): Likewise.
4933 (vcaddq_rot90_m_u8): Likewise.
4934 (vcaddq_rot90_m_u32): Likewise.
4935 (vcaddq_rot90_m_u16): Likewise.
4936 (veorq_m_s8): Likewise.
4937 (veorq_m_s32): Likewise.
4938 (veorq_m_s16): Likewise.
4939 (veorq_m_u8): Likewise.
4940 (veorq_m_u32): Likewise.
4941 (veorq_m_u16): Likewise.
4942 (vhaddq_m_n_s8): Likewise.
4943 (vhaddq_m_n_s32): Likewise.
4944 (vhaddq_m_n_s16): Likewise.
4945 (vhaddq_m_n_u8): Likewise.
4946 (vhaddq_m_n_u32): Likewise.
4947 (vhaddq_m_n_u16): Likewise.
4948 (vhaddq_m_s8): Likewise.
4949 (vhaddq_m_s32): Likewise.
4950 (vhaddq_m_s16): Likewise.
4951 (vhaddq_m_u8): Likewise.
4952 (vhaddq_m_u32): Likewise.
4953 (vhaddq_m_u16): Likewise.
4954 (vhcaddq_rot270_m_s8): Likewise.
4955 (vhcaddq_rot270_m_s32): Likewise.
4956 (vhcaddq_rot270_m_s16): Likewise.
4957 (vhcaddq_rot90_m_s8): Likewise.
4958 (vhcaddq_rot90_m_s32): Likewise.
4959 (vhcaddq_rot90_m_s16): Likewise.
4960 (vhsubq_m_n_s8): Likewise.
4961 (vhsubq_m_n_s32): Likewise.
4962 (vhsubq_m_n_s16): Likewise.
4963 (vhsubq_m_n_u8): Likewise.
4964 (vhsubq_m_n_u32): Likewise.
4965 (vhsubq_m_n_u16): Likewise.
4966 (vhsubq_m_s8): Likewise.
4967 (vhsubq_m_s32): Likewise.
4968 (vhsubq_m_s16): Likewise.
4969 (vhsubq_m_u8): Likewise.
4970 (vhsubq_m_u32): Likewise.
4971 (vhsubq_m_u16): Likewise.
4972 (vmaxq_m_s8): Likewise.
4973 (vmaxq_m_s32): Likewise.
4974 (vmaxq_m_s16): Likewise.
4975 (vmaxq_m_u8): Likewise.
4976 (vmaxq_m_u32): Likewise.
4977 (vmaxq_m_u16): Likewise.
4978 (vminq_m_s8): Likewise.
4979 (vminq_m_s32): Likewise.
4980 (vminq_m_s16): Likewise.
4981 (vminq_m_u8): Likewise.
4982 (vminq_m_u32): Likewise.
4983 (vminq_m_u16): Likewise.
4984 (vmladavaq_p_s8): Likewise.
4985 (vmladavaq_p_s32): Likewise.
4986 (vmladavaq_p_s16): Likewise.
4987 (vmladavaq_p_u8): Likewise.
4988 (vmladavaq_p_u32): Likewise.
4989 (vmladavaq_p_u16): Likewise.
4990 (vmladavaxq_p_s8): Likewise.
4991 (vmladavaxq_p_s32): Likewise.
4992 (vmladavaxq_p_s16): Likewise.
4993 (vmlaq_m_n_s8): Likewise.
4994 (vmlaq_m_n_s32): Likewise.
4995 (vmlaq_m_n_s16): Likewise.
4996 (vmlaq_m_n_u8): Likewise.
4997 (vmlaq_m_n_u32): Likewise.
4998 (vmlaq_m_n_u16): Likewise.
4999 (vmlasq_m_n_s8): Likewise.
5000 (vmlasq_m_n_s32): Likewise.
5001 (vmlasq_m_n_s16): Likewise.
5002 (vmlasq_m_n_u8): Likewise.
5003 (vmlasq_m_n_u32): Likewise.
5004 (vmlasq_m_n_u16): Likewise.
5005 (vmlsdavaq_p_s8): Likewise.
5006 (vmlsdavaq_p_s32): Likewise.
5007 (vmlsdavaq_p_s16): Likewise.
5008 (vmlsdavaxq_p_s8): Likewise.
5009 (vmlsdavaxq_p_s32): Likewise.
5010 (vmlsdavaxq_p_s16): Likewise.
5011 (vmulhq_m_s8): Likewise.
5012 (vmulhq_m_s32): Likewise.
5013 (vmulhq_m_s16): Likewise.
5014 (vmulhq_m_u8): Likewise.
5015 (vmulhq_m_u32): Likewise.
5016 (vmulhq_m_u16): Likewise.
5017 (vmullbq_int_m_s8): Likewise.
5018 (vmullbq_int_m_s32): Likewise.
5019 (vmullbq_int_m_s16): Likewise.
5020 (vmullbq_int_m_u8): Likewise.
5021 (vmullbq_int_m_u32): Likewise.
5022 (vmullbq_int_m_u16): Likewise.
5023 (vmulltq_int_m_s8): Likewise.
5024 (vmulltq_int_m_s32): Likewise.
5025 (vmulltq_int_m_s16): Likewise.
5026 (vmulltq_int_m_u8): Likewise.
5027 (vmulltq_int_m_u32): Likewise.
5028 (vmulltq_int_m_u16): Likewise.
5029 (vmulq_m_n_s8): Likewise.
5030 (vmulq_m_n_s32): Likewise.
5031 (vmulq_m_n_s16): Likewise.
5032 (vmulq_m_n_u8): Likewise.
5033 (vmulq_m_n_u32): Likewise.
5034 (vmulq_m_n_u16): Likewise.
5035 (vmulq_m_s8): Likewise.
5036 (vmulq_m_s32): Likewise.
5037 (vmulq_m_s16): Likewise.
5038 (vmulq_m_u8): Likewise.
5039 (vmulq_m_u32): Likewise.
5040 (vmulq_m_u16): Likewise.
5041 (vornq_m_s8): Likewise.
5042 (vornq_m_s32): Likewise.
5043 (vornq_m_s16): Likewise.
5044 (vornq_m_u8): Likewise.
5045 (vornq_m_u32): Likewise.
5046 (vornq_m_u16): Likewise.
5047 (vorrq_m_s8): Likewise.
5048 (vorrq_m_s32): Likewise.
5049 (vorrq_m_s16): Likewise.
5050 (vorrq_m_u8): Likewise.
5051 (vorrq_m_u32): Likewise.
5052 (vorrq_m_u16): Likewise.
5053 (vqaddq_m_n_s8): Likewise.
5054 (vqaddq_m_n_s32): Likewise.
5055 (vqaddq_m_n_s16): Likewise.
5056 (vqaddq_m_n_u8): Likewise.
5057 (vqaddq_m_n_u32): Likewise.
5058 (vqaddq_m_n_u16): Likewise.
5059 (vqaddq_m_s8): Likewise.
5060 (vqaddq_m_s32): Likewise.
5061 (vqaddq_m_s16): Likewise.
5062 (vqaddq_m_u8): Likewise.
5063 (vqaddq_m_u32): Likewise.
5064 (vqaddq_m_u16): Likewise.
5065 (vqdmladhq_m_s8): Likewise.
5066 (vqdmladhq_m_s32): Likewise.
5067 (vqdmladhq_m_s16): Likewise.
5068 (vqdmladhxq_m_s8): Likewise.
5069 (vqdmladhxq_m_s32): Likewise.
5070 (vqdmladhxq_m_s16): Likewise.
5071 (vqdmlahq_m_n_s8): Likewise.
5072 (vqdmlahq_m_n_s32): Likewise.
5073 (vqdmlahq_m_n_s16): Likewise.
5074 (vqdmlahq_m_n_u8): Likewise.
5075 (vqdmlahq_m_n_u32): Likewise.
5076 (vqdmlahq_m_n_u16): Likewise.
5077 (vqdmlsdhq_m_s8): Likewise.
5078 (vqdmlsdhq_m_s32): Likewise.
5079 (vqdmlsdhq_m_s16): Likewise.
5080 (vqdmlsdhxq_m_s8): Likewise.
5081 (vqdmlsdhxq_m_s32): Likewise.
5082 (vqdmlsdhxq_m_s16): Likewise.
5083 (vqdmulhq_m_n_s8): Likewise.
5084 (vqdmulhq_m_n_s32): Likewise.
5085 (vqdmulhq_m_n_s16): Likewise.
5086 (vqdmulhq_m_s8): Likewise.
5087 (vqdmulhq_m_s32): Likewise.
5088 (vqdmulhq_m_s16): Likewise.
5089 (vqrdmladhq_m_s8): Likewise.
5090 (vqrdmladhq_m_s32): Likewise.
5091 (vqrdmladhq_m_s16): Likewise.
5092 (vqrdmladhxq_m_s8): Likewise.
5093 (vqrdmladhxq_m_s32): Likewise.
5094 (vqrdmladhxq_m_s16): Likewise.
5095 (vqrdmlahq_m_n_s8): Likewise.
5096 (vqrdmlahq_m_n_s32): Likewise.
5097 (vqrdmlahq_m_n_s16): Likewise.
5098 (vqrdmlahq_m_n_u8): Likewise.
5099 (vqrdmlahq_m_n_u32): Likewise.
5100 (vqrdmlahq_m_n_u16): Likewise.
5101 (vqrdmlashq_m_n_s8): Likewise.
5102 (vqrdmlashq_m_n_s32): Likewise.
5103 (vqrdmlashq_m_n_s16): Likewise.
5104 (vqrdmlashq_m_n_u8): Likewise.
5105 (vqrdmlashq_m_n_u32): Likewise.
5106 (vqrdmlashq_m_n_u16): Likewise.
5107 (vqrdmlsdhq_m_s8): Likewise.
5108 (vqrdmlsdhq_m_s32): Likewise.
5109 (vqrdmlsdhq_m_s16): Likewise.
5110 (vqrdmlsdhxq_m_s8): Likewise.
5111 (vqrdmlsdhxq_m_s32): Likewise.
5112 (vqrdmlsdhxq_m_s16): Likewise.
5113 (vqrdmulhq_m_n_s8): Likewise.
5114 (vqrdmulhq_m_n_s32): Likewise.
5115 (vqrdmulhq_m_n_s16): Likewise.
5116 (vqrdmulhq_m_s8): Likewise.
5117 (vqrdmulhq_m_s32): Likewise.
5118 (vqrdmulhq_m_s16): Likewise.
5119 (vqrshlq_m_s8): Likewise.
5120 (vqrshlq_m_s32): Likewise.
5121 (vqrshlq_m_s16): Likewise.
5122 (vqrshlq_m_u8): Likewise.
5123 (vqrshlq_m_u32): Likewise.
5124 (vqrshlq_m_u16): Likewise.
5125 (vqshlq_m_n_s8): Likewise.
5126 (vqshlq_m_n_s32): Likewise.
5127 (vqshlq_m_n_s16): Likewise.
5128 (vqshlq_m_n_u8): Likewise.
5129 (vqshlq_m_n_u32): Likewise.
5130 (vqshlq_m_n_u16): Likewise.
5131 (vqshlq_m_s8): Likewise.
5132 (vqshlq_m_s32): Likewise.
5133 (vqshlq_m_s16): Likewise.
5134 (vqshlq_m_u8): Likewise.
5135 (vqshlq_m_u32): Likewise.
5136 (vqshlq_m_u16): Likewise.
5137 (vqsubq_m_n_s8): Likewise.
5138 (vqsubq_m_n_s32): Likewise.
5139 (vqsubq_m_n_s16): Likewise.
5140 (vqsubq_m_n_u8): Likewise.
5141 (vqsubq_m_n_u32): Likewise.
5142 (vqsubq_m_n_u16): Likewise.
5143 (vqsubq_m_s8): Likewise.
5144 (vqsubq_m_s32): Likewise.
5145 (vqsubq_m_s16): Likewise.
5146 (vqsubq_m_u8): Likewise.
5147 (vqsubq_m_u32): Likewise.
5148 (vqsubq_m_u16): Likewise.
5149 (vrhaddq_m_s8): Likewise.
5150 (vrhaddq_m_s32): Likewise.
5151 (vrhaddq_m_s16): Likewise.
5152 (vrhaddq_m_u8): Likewise.
5153 (vrhaddq_m_u32): Likewise.
5154 (vrhaddq_m_u16): Likewise.
5155 (vrmulhq_m_s8): Likewise.
5156 (vrmulhq_m_s32): Likewise.
5157 (vrmulhq_m_s16): Likewise.
5158 (vrmulhq_m_u8): Likewise.
5159 (vrmulhq_m_u32): Likewise.
5160 (vrmulhq_m_u16): Likewise.
5161 (vrshlq_m_s8): Likewise.
5162 (vrshlq_m_s32): Likewise.
5163 (vrshlq_m_s16): Likewise.
5164 (vrshlq_m_u8): Likewise.
5165 (vrshlq_m_u32): Likewise.
5166 (vrshlq_m_u16): Likewise.
5167 (vrshrq_m_n_s8): Likewise.
5168 (vrshrq_m_n_s32): Likewise.
5169 (vrshrq_m_n_s16): Likewise.
5170 (vrshrq_m_n_u8): Likewise.
5171 (vrshrq_m_n_u32): Likewise.
5172 (vrshrq_m_n_u16): Likewise.
5173 (vshlq_m_n_s8): Likewise.
5174 (vshlq_m_n_s32): Likewise.
5175 (vshlq_m_n_s16): Likewise.
5176 (vshlq_m_n_u8): Likewise.
5177 (vshlq_m_n_u32): Likewise.
5178 (vshlq_m_n_u16): Likewise.
5179 (vshrq_m_n_s8): Likewise.
5180 (vshrq_m_n_s32): Likewise.
5181 (vshrq_m_n_s16): Likewise.
5182 (vshrq_m_n_u8): Likewise.
5183 (vshrq_m_n_u32): Likewise.
5184 (vshrq_m_n_u16): Likewise.
5185 (vsliq_m_n_s8): Likewise.
5186 (vsliq_m_n_s32): Likewise.
5187 (vsliq_m_n_s16): Likewise.
5188 (vsliq_m_n_u8): Likewise.
5189 (vsliq_m_n_u32): Likewise.
5190 (vsliq_m_n_u16): Likewise.
5191 (vsubq_m_n_s8): Likewise.
5192 (vsubq_m_n_s32): Likewise.
5193 (vsubq_m_n_s16): Likewise.
5194 (vsubq_m_n_u8): Likewise.
5195 (vsubq_m_n_u32): Likewise.
5196 (vsubq_m_n_u16): Likewise.
5197 (__arm_vabdq_m_s8): Define intrinsic.
5198 (__arm_vabdq_m_s32): Likewise.
5199 (__arm_vabdq_m_s16): Likewise.
5200 (__arm_vabdq_m_u8): Likewise.
5201 (__arm_vabdq_m_u32): Likewise.
5202 (__arm_vabdq_m_u16): Likewise.
5203 (__arm_vaddq_m_n_s8): Likewise.
5204 (__arm_vaddq_m_n_s32): Likewise.
5205 (__arm_vaddq_m_n_s16): Likewise.
5206 (__arm_vaddq_m_n_u8): Likewise.
5207 (__arm_vaddq_m_n_u32): Likewise.
5208 (__arm_vaddq_m_n_u16): Likewise.
5209 (__arm_vaddq_m_s8): Likewise.
5210 (__arm_vaddq_m_s32): Likewise.
5211 (__arm_vaddq_m_s16): Likewise.
5212 (__arm_vaddq_m_u8): Likewise.
5213 (__arm_vaddq_m_u32): Likewise.
5214 (__arm_vaddq_m_u16): Likewise.
5215 (__arm_vandq_m_s8): Likewise.
5216 (__arm_vandq_m_s32): Likewise.
5217 (__arm_vandq_m_s16): Likewise.
5218 (__arm_vandq_m_u8): Likewise.
5219 (__arm_vandq_m_u32): Likewise.
5220 (__arm_vandq_m_u16): Likewise.
5221 (__arm_vbicq_m_s8): Likewise.
5222 (__arm_vbicq_m_s32): Likewise.
5223 (__arm_vbicq_m_s16): Likewise.
5224 (__arm_vbicq_m_u8): Likewise.
5225 (__arm_vbicq_m_u32): Likewise.
5226 (__arm_vbicq_m_u16): Likewise.
5227 (__arm_vbrsrq_m_n_s8): Likewise.
5228 (__arm_vbrsrq_m_n_s32): Likewise.
5229 (__arm_vbrsrq_m_n_s16): Likewise.
5230 (__arm_vbrsrq_m_n_u8): Likewise.
5231 (__arm_vbrsrq_m_n_u32): Likewise.
5232 (__arm_vbrsrq_m_n_u16): Likewise.
5233 (__arm_vcaddq_rot270_m_s8): Likewise.
5234 (__arm_vcaddq_rot270_m_s32): Likewise.
5235 (__arm_vcaddq_rot270_m_s16): Likewise.
5236 (__arm_vcaddq_rot270_m_u8): Likewise.
5237 (__arm_vcaddq_rot270_m_u32): Likewise.
5238 (__arm_vcaddq_rot270_m_u16): Likewise.
5239 (__arm_vcaddq_rot90_m_s8): Likewise.
5240 (__arm_vcaddq_rot90_m_s32): Likewise.
5241 (__arm_vcaddq_rot90_m_s16): Likewise.
5242 (__arm_vcaddq_rot90_m_u8): Likewise.
5243 (__arm_vcaddq_rot90_m_u32): Likewise.
5244 (__arm_vcaddq_rot90_m_u16): Likewise.
5245 (__arm_veorq_m_s8): Likewise.
5246 (__arm_veorq_m_s32): Likewise.
5247 (__arm_veorq_m_s16): Likewise.
5248 (__arm_veorq_m_u8): Likewise.
5249 (__arm_veorq_m_u32): Likewise.
5250 (__arm_veorq_m_u16): Likewise.
5251 (__arm_vhaddq_m_n_s8): Likewise.
5252 (__arm_vhaddq_m_n_s32): Likewise.
5253 (__arm_vhaddq_m_n_s16): Likewise.
5254 (__arm_vhaddq_m_n_u8): Likewise.
5255 (__arm_vhaddq_m_n_u32): Likewise.
5256 (__arm_vhaddq_m_n_u16): Likewise.
5257 (__arm_vhaddq_m_s8): Likewise.
5258 (__arm_vhaddq_m_s32): Likewise.
5259 (__arm_vhaddq_m_s16): Likewise.
5260 (__arm_vhaddq_m_u8): Likewise.
5261 (__arm_vhaddq_m_u32): Likewise.
5262 (__arm_vhaddq_m_u16): Likewise.
5263 (__arm_vhcaddq_rot270_m_s8): Likewise.
5264 (__arm_vhcaddq_rot270_m_s32): Likewise.
5265 (__arm_vhcaddq_rot270_m_s16): Likewise.
5266 (__arm_vhcaddq_rot90_m_s8): Likewise.
5267 (__arm_vhcaddq_rot90_m_s32): Likewise.
5268 (__arm_vhcaddq_rot90_m_s16): Likewise.
5269 (__arm_vhsubq_m_n_s8): Likewise.
5270 (__arm_vhsubq_m_n_s32): Likewise.
5271 (__arm_vhsubq_m_n_s16): Likewise.
5272 (__arm_vhsubq_m_n_u8): Likewise.
5273 (__arm_vhsubq_m_n_u32): Likewise.
5274 (__arm_vhsubq_m_n_u16): Likewise.
5275 (__arm_vhsubq_m_s8): Likewise.
5276 (__arm_vhsubq_m_s32): Likewise.
5277 (__arm_vhsubq_m_s16): Likewise.
5278 (__arm_vhsubq_m_u8): Likewise.
5279 (__arm_vhsubq_m_u32): Likewise.
5280 (__arm_vhsubq_m_u16): Likewise.
5281 (__arm_vmaxq_m_s8): Likewise.
5282 (__arm_vmaxq_m_s32): Likewise.
5283 (__arm_vmaxq_m_s16): Likewise.
5284 (__arm_vmaxq_m_u8): Likewise.
5285 (__arm_vmaxq_m_u32): Likewise.
5286 (__arm_vmaxq_m_u16): Likewise.
5287 (__arm_vminq_m_s8): Likewise.
5288 (__arm_vminq_m_s32): Likewise.
5289 (__arm_vminq_m_s16): Likewise.
5290 (__arm_vminq_m_u8): Likewise.
5291 (__arm_vminq_m_u32): Likewise.
5292 (__arm_vminq_m_u16): Likewise.
5293 (__arm_vmladavaq_p_s8): Likewise.
5294 (__arm_vmladavaq_p_s32): Likewise.
5295 (__arm_vmladavaq_p_s16): Likewise.
5296 (__arm_vmladavaq_p_u8): Likewise.
5297 (__arm_vmladavaq_p_u32): Likewise.
5298 (__arm_vmladavaq_p_u16): Likewise.
5299 (__arm_vmladavaxq_p_s8): Likewise.
5300 (__arm_vmladavaxq_p_s32): Likewise.
5301 (__arm_vmladavaxq_p_s16): Likewise.
5302 (__arm_vmlaq_m_n_s8): Likewise.
5303 (__arm_vmlaq_m_n_s32): Likewise.
5304 (__arm_vmlaq_m_n_s16): Likewise.
5305 (__arm_vmlaq_m_n_u8): Likewise.
5306 (__arm_vmlaq_m_n_u32): Likewise.
5307 (__arm_vmlaq_m_n_u16): Likewise.
5308 (__arm_vmlasq_m_n_s8): Likewise.
5309 (__arm_vmlasq_m_n_s32): Likewise.
5310 (__arm_vmlasq_m_n_s16): Likewise.
5311 (__arm_vmlasq_m_n_u8): Likewise.
5312 (__arm_vmlasq_m_n_u32): Likewise.
5313 (__arm_vmlasq_m_n_u16): Likewise.
5314 (__arm_vmlsdavaq_p_s8): Likewise.
5315 (__arm_vmlsdavaq_p_s32): Likewise.
5316 (__arm_vmlsdavaq_p_s16): Likewise.
5317 (__arm_vmlsdavaxq_p_s8): Likewise.
5318 (__arm_vmlsdavaxq_p_s32): Likewise.
5319 (__arm_vmlsdavaxq_p_s16): Likewise.
5320 (__arm_vmulhq_m_s8): Likewise.
5321 (__arm_vmulhq_m_s32): Likewise.
5322 (__arm_vmulhq_m_s16): Likewise.
5323 (__arm_vmulhq_m_u8): Likewise.
5324 (__arm_vmulhq_m_u32): Likewise.
5325 (__arm_vmulhq_m_u16): Likewise.
5326 (__arm_vmullbq_int_m_s8): Likewise.
5327 (__arm_vmullbq_int_m_s32): Likewise.
5328 (__arm_vmullbq_int_m_s16): Likewise.
5329 (__arm_vmullbq_int_m_u8): Likewise.
5330 (__arm_vmullbq_int_m_u32): Likewise.
5331 (__arm_vmullbq_int_m_u16): Likewise.
5332 (__arm_vmulltq_int_m_s8): Likewise.
5333 (__arm_vmulltq_int_m_s32): Likewise.
5334 (__arm_vmulltq_int_m_s16): Likewise.
5335 (__arm_vmulltq_int_m_u8): Likewise.
5336 (__arm_vmulltq_int_m_u32): Likewise.
5337 (__arm_vmulltq_int_m_u16): Likewise.
5338 (__arm_vmulq_m_n_s8): Likewise.
5339 (__arm_vmulq_m_n_s32): Likewise.
5340 (__arm_vmulq_m_n_s16): Likewise.
5341 (__arm_vmulq_m_n_u8): Likewise.
5342 (__arm_vmulq_m_n_u32): Likewise.
5343 (__arm_vmulq_m_n_u16): Likewise.
5344 (__arm_vmulq_m_s8): Likewise.
5345 (__arm_vmulq_m_s32): Likewise.
5346 (__arm_vmulq_m_s16): Likewise.
5347 (__arm_vmulq_m_u8): Likewise.
5348 (__arm_vmulq_m_u32): Likewise.
5349 (__arm_vmulq_m_u16): Likewise.
5350 (__arm_vornq_m_s8): Likewise.
5351 (__arm_vornq_m_s32): Likewise.
5352 (__arm_vornq_m_s16): Likewise.
5353 (__arm_vornq_m_u8): Likewise.
5354 (__arm_vornq_m_u32): Likewise.
5355 (__arm_vornq_m_u16): Likewise.
5356 (__arm_vorrq_m_s8): Likewise.
5357 (__arm_vorrq_m_s32): Likewise.
5358 (__arm_vorrq_m_s16): Likewise.
5359 (__arm_vorrq_m_u8): Likewise.
5360 (__arm_vorrq_m_u32): Likewise.
5361 (__arm_vorrq_m_u16): Likewise.
5362 (__arm_vqaddq_m_n_s8): Likewise.
5363 (__arm_vqaddq_m_n_s32): Likewise.
5364 (__arm_vqaddq_m_n_s16): Likewise.
5365 (__arm_vqaddq_m_n_u8): Likewise.
5366 (__arm_vqaddq_m_n_u32): Likewise.
5367 (__arm_vqaddq_m_n_u16): Likewise.
5368 (__arm_vqaddq_m_s8): Likewise.
5369 (__arm_vqaddq_m_s32): Likewise.
5370 (__arm_vqaddq_m_s16): Likewise.
5371 (__arm_vqaddq_m_u8): Likewise.
5372 (__arm_vqaddq_m_u32): Likewise.
5373 (__arm_vqaddq_m_u16): Likewise.
5374 (__arm_vqdmladhq_m_s8): Likewise.
5375 (__arm_vqdmladhq_m_s32): Likewise.
5376 (__arm_vqdmladhq_m_s16): Likewise.
5377 (__arm_vqdmladhxq_m_s8): Likewise.
5378 (__arm_vqdmladhxq_m_s32): Likewise.
5379 (__arm_vqdmladhxq_m_s16): Likewise.
5380 (__arm_vqdmlahq_m_n_s8): Likewise.
5381 (__arm_vqdmlahq_m_n_s32): Likewise.
5382 (__arm_vqdmlahq_m_n_s16): Likewise.
5383 (__arm_vqdmlahq_m_n_u8): Likewise.
5384 (__arm_vqdmlahq_m_n_u32): Likewise.
5385 (__arm_vqdmlahq_m_n_u16): Likewise.
5386 (__arm_vqdmlsdhq_m_s8): Likewise.
5387 (__arm_vqdmlsdhq_m_s32): Likewise.
5388 (__arm_vqdmlsdhq_m_s16): Likewise.
5389 (__arm_vqdmlsdhxq_m_s8): Likewise.
5390 (__arm_vqdmlsdhxq_m_s32): Likewise.
5391 (__arm_vqdmlsdhxq_m_s16): Likewise.
5392 (__arm_vqdmulhq_m_n_s8): Likewise.
5393 (__arm_vqdmulhq_m_n_s32): Likewise.
5394 (__arm_vqdmulhq_m_n_s16): Likewise.
5395 (__arm_vqdmulhq_m_s8): Likewise.
5396 (__arm_vqdmulhq_m_s32): Likewise.
5397 (__arm_vqdmulhq_m_s16): Likewise.
5398 (__arm_vqrdmladhq_m_s8): Likewise.
5399 (__arm_vqrdmladhq_m_s32): Likewise.
5400 (__arm_vqrdmladhq_m_s16): Likewise.
5401 (__arm_vqrdmladhxq_m_s8): Likewise.
5402 (__arm_vqrdmladhxq_m_s32): Likewise.
5403 (__arm_vqrdmladhxq_m_s16): Likewise.
5404 (__arm_vqrdmlahq_m_n_s8): Likewise.
5405 (__arm_vqrdmlahq_m_n_s32): Likewise.
5406 (__arm_vqrdmlahq_m_n_s16): Likewise.
5407 (__arm_vqrdmlahq_m_n_u8): Likewise.
5408 (__arm_vqrdmlahq_m_n_u32): Likewise.
5409 (__arm_vqrdmlahq_m_n_u16): Likewise.
5410 (__arm_vqrdmlashq_m_n_s8): Likewise.
5411 (__arm_vqrdmlashq_m_n_s32): Likewise.
5412 (__arm_vqrdmlashq_m_n_s16): Likewise.
5413 (__arm_vqrdmlashq_m_n_u8): Likewise.
5414 (__arm_vqrdmlashq_m_n_u32): Likewise.
5415 (__arm_vqrdmlashq_m_n_u16): Likewise.
5416 (__arm_vqrdmlsdhq_m_s8): Likewise.
5417 (__arm_vqrdmlsdhq_m_s32): Likewise.
5418 (__arm_vqrdmlsdhq_m_s16): Likewise.
5419 (__arm_vqrdmlsdhxq_m_s8): Likewise.
5420 (__arm_vqrdmlsdhxq_m_s32): Likewise.
5421 (__arm_vqrdmlsdhxq_m_s16): Likewise.
5422 (__arm_vqrdmulhq_m_n_s8): Likewise.
5423 (__arm_vqrdmulhq_m_n_s32): Likewise.
5424 (__arm_vqrdmulhq_m_n_s16): Likewise.
5425 (__arm_vqrdmulhq_m_s8): Likewise.
5426 (__arm_vqrdmulhq_m_s32): Likewise.
5427 (__arm_vqrdmulhq_m_s16): Likewise.
5428 (__arm_vqrshlq_m_s8): Likewise.
5429 (__arm_vqrshlq_m_s32): Likewise.
5430 (__arm_vqrshlq_m_s16): Likewise.
5431 (__arm_vqrshlq_m_u8): Likewise.
5432 (__arm_vqrshlq_m_u32): Likewise.
5433 (__arm_vqrshlq_m_u16): Likewise.
5434 (__arm_vqshlq_m_n_s8): Likewise.
5435 (__arm_vqshlq_m_n_s32): Likewise.
5436 (__arm_vqshlq_m_n_s16): Likewise.
5437 (__arm_vqshlq_m_n_u8): Likewise.
5438 (__arm_vqshlq_m_n_u32): Likewise.
5439 (__arm_vqshlq_m_n_u16): Likewise.
5440 (__arm_vqshlq_m_s8): Likewise.
5441 (__arm_vqshlq_m_s32): Likewise.
5442 (__arm_vqshlq_m_s16): Likewise.
5443 (__arm_vqshlq_m_u8): Likewise.
5444 (__arm_vqshlq_m_u32): Likewise.
5445 (__arm_vqshlq_m_u16): Likewise.
5446 (__arm_vqsubq_m_n_s8): Likewise.
5447 (__arm_vqsubq_m_n_s32): Likewise.
5448 (__arm_vqsubq_m_n_s16): Likewise.
5449 (__arm_vqsubq_m_n_u8): Likewise.
5450 (__arm_vqsubq_m_n_u32): Likewise.
5451 (__arm_vqsubq_m_n_u16): Likewise.
5452 (__arm_vqsubq_m_s8): Likewise.
5453 (__arm_vqsubq_m_s32): Likewise.
5454 (__arm_vqsubq_m_s16): Likewise.
5455 (__arm_vqsubq_m_u8): Likewise.
5456 (__arm_vqsubq_m_u32): Likewise.
5457 (__arm_vqsubq_m_u16): Likewise.
5458 (__arm_vrhaddq_m_s8): Likewise.
5459 (__arm_vrhaddq_m_s32): Likewise.
5460 (__arm_vrhaddq_m_s16): Likewise.
5461 (__arm_vrhaddq_m_u8): Likewise.
5462 (__arm_vrhaddq_m_u32): Likewise.
5463 (__arm_vrhaddq_m_u16): Likewise.
5464 (__arm_vrmulhq_m_s8): Likewise.
5465 (__arm_vrmulhq_m_s32): Likewise.
5466 (__arm_vrmulhq_m_s16): Likewise.
5467 (__arm_vrmulhq_m_u8): Likewise.
5468 (__arm_vrmulhq_m_u32): Likewise.
5469 (__arm_vrmulhq_m_u16): Likewise.
5470 (__arm_vrshlq_m_s8): Likewise.
5471 (__arm_vrshlq_m_s32): Likewise.
5472 (__arm_vrshlq_m_s16): Likewise.
5473 (__arm_vrshlq_m_u8): Likewise.
5474 (__arm_vrshlq_m_u32): Likewise.
5475 (__arm_vrshlq_m_u16): Likewise.
5476 (__arm_vrshrq_m_n_s8): Likewise.
5477 (__arm_vrshrq_m_n_s32): Likewise.
5478 (__arm_vrshrq_m_n_s16): Likewise.
5479 (__arm_vrshrq_m_n_u8): Likewise.
5480 (__arm_vrshrq_m_n_u32): Likewise.
5481 (__arm_vrshrq_m_n_u16): Likewise.
5482 (__arm_vshlq_m_n_s8): Likewise.
5483 (__arm_vshlq_m_n_s32): Likewise.
5484 (__arm_vshlq_m_n_s16): Likewise.
5485 (__arm_vshlq_m_n_u8): Likewise.
5486 (__arm_vshlq_m_n_u32): Likewise.
5487 (__arm_vshlq_m_n_u16): Likewise.
5488 (__arm_vshrq_m_n_s8): Likewise.
5489 (__arm_vshrq_m_n_s32): Likewise.
5490 (__arm_vshrq_m_n_s16): Likewise.
5491 (__arm_vshrq_m_n_u8): Likewise.
5492 (__arm_vshrq_m_n_u32): Likewise.
5493 (__arm_vshrq_m_n_u16): Likewise.
5494 (__arm_vsliq_m_n_s8): Likewise.
5495 (__arm_vsliq_m_n_s32): Likewise.
5496 (__arm_vsliq_m_n_s16): Likewise.
5497 (__arm_vsliq_m_n_u8): Likewise.
5498 (__arm_vsliq_m_n_u32): Likewise.
5499 (__arm_vsliq_m_n_u16): Likewise.
5500 (__arm_vsubq_m_n_s8): Likewise.
5501 (__arm_vsubq_m_n_s32): Likewise.
5502 (__arm_vsubq_m_n_s16): Likewise.
5503 (__arm_vsubq_m_n_u8): Likewise.
5504 (__arm_vsubq_m_n_u32): Likewise.
5505 (__arm_vsubq_m_n_u16): Likewise.
5506 (vqdmladhq_m): Define polymorphic variant.
5507 (vqdmladhxq_m): Likewise.
5508 (vqdmlsdhq_m): Likewise.
5509 (vqdmlsdhxq_m): Likewise.
5510 (vabdq_m): Likewise.
5511 (vandq_m): Likewise.
5512 (vbicq_m): Likewise.
5513 (vbrsrq_m_n): Likewise.
5514 (vcaddq_rot270_m): Likewise.
5515 (vcaddq_rot90_m): Likewise.
5516 (veorq_m): Likewise.
5517 (vmaxq_m): Likewise.
5518 (vminq_m): Likewise.
5519 (vmladavaq_p): Likewise.
5520 (vmlaq_m_n): Likewise.
5521 (vmlasq_m_n): Likewise.
5522 (vmulhq_m): Likewise.
5523 (vmullbq_int_m): Likewise.
5524 (vmulltq_int_m): Likewise.
5525 (vornq_m): Likewise.
5526 (vorrq_m): Likewise.
5527 (vqdmlahq_m_n): Likewise.
5528 (vqrdmlahq_m_n): Likewise.
5529 (vqrdmlashq_m_n): Likewise.
5530 (vqrshlq_m): Likewise.
5531 (vqshlq_m_n): Likewise.
5532 (vqshlq_m): Likewise.
5533 (vrhaddq_m): Likewise.
5534 (vrmulhq_m): Likewise.
5535 (vrshlq_m): Likewise.
5536 (vrshrq_m_n): Likewise.
5537 (vshlq_m_n): Likewise.
5538 (vshrq_m_n): Likewise.
5539 (vsliq_m): Likewise.
5540 (vaddq_m_n): Likewise.
5541 (vaddq_m): Likewise.
5542 (vhaddq_m_n): Likewise.
5543 (vhaddq_m): Likewise.
5544 (vhcaddq_rot270_m): Likewise.
5545 (vhcaddq_rot90_m): Likewise.
5546 (vhsubq_m): Likewise.
5547 (vhsubq_m_n): Likewise.
5548 (vmulq_m_n): Likewise.
5549 (vmulq_m): Likewise.
5550 (vqaddq_m_n): Likewise.
5551 (vqaddq_m): Likewise.
5552 (vqdmulhq_m_n): Likewise.
5553 (vqdmulhq_m): Likewise.
5554 (vsubq_m_n): Likewise.
5555 (vsliq_m_n): Likewise.
5556 (vqsubq_m_n): Likewise.
5557 (vqsubq_m): Likewise.
5558 (vqrdmulhq_m): Likewise.
5559 (vqrdmulhq_m_n): Likewise.
5560 (vqrdmlsdhxq_m): Likewise.
5561 (vqrdmlsdhq_m): Likewise.
5562 (vqrdmladhq_m): Likewise.
5563 (vqrdmladhxq_m): Likewise.
5564 (vmlsdavaxq_p): Likewise.
5565 (vmlsdavaq_p): Likewise.
5566 (vmladavaxq_p): Likewise.
5567 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
5569 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
5570 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
5571 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
5572 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
5573 * config/arm/mve.md (VHSUBQ_M): Define iterators.
5574 (VSLIQ_M_N): Likewise.
5575 (VQRDMLAHQ_M_N): Likewise.
5576 (VRSHLQ_M): Likewise.
5577 (VMINQ_M): Likewise.
5578 (VMULLBQ_INT_M): Likewise.
5579 (VMULHQ_M): Likewise.
5580 (VMULQ_M): Likewise.
5581 (VHSUBQ_M_N): Likewise.
5582 (VHADDQ_M_N): Likewise.
5583 (VORRQ_M): Likewise.
5584 (VRMULHQ_M): Likewise.
5585 (VQADDQ_M): Likewise.
5586 (VRSHRQ_M_N): Likewise.
5587 (VQSUBQ_M_N): Likewise.
5588 (VADDQ_M): Likewise.
5589 (VORNQ_M): Likewise.
5590 (VQDMLAHQ_M_N): Likewise.
5591 (VRHADDQ_M): Likewise.
5592 (VQSHLQ_M): Likewise.
5593 (VANDQ_M): Likewise.
5594 (VBICQ_M): Likewise.
5595 (VSHLQ_M_N): Likewise.
5596 (VCADDQ_ROT270_M): Likewise.
5597 (VQRSHLQ_M): Likewise.
5598 (VQADDQ_M_N): Likewise.
5599 (VADDQ_M_N): Likewise.
5600 (VMAXQ_M): Likewise.
5601 (VQSUBQ_M): Likewise.
5602 (VMLASQ_M_N): Likewise.
5603 (VMLADAVAQ_P): Likewise.
5604 (VBRSRQ_M_N): Likewise.
5605 (VMULQ_M_N): Likewise.
5606 (VCADDQ_ROT90_M): Likewise.
5607 (VMULLTQ_INT_M): Likewise.
5608 (VEORQ_M): Likewise.
5609 (VSHRQ_M_N): Likewise.
5610 (VSUBQ_M_N): Likewise.
5611 (VHADDQ_M): Likewise.
5612 (VABDQ_M): Likewise.
5613 (VQRDMLASHQ_M_N): Likewise.
5614 (VMLAQ_M_N): Likewise.
5615 (VQSHLQ_M_N): Likewise.
5616 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
5617 (mve_vaddq_m_n_<supf><mode>): Likewise.
5618 (mve_vaddq_m_<supf><mode>): Likewise.
5619 (mve_vandq_m_<supf><mode>): Likewise.
5620 (mve_vbicq_m_<supf><mode>): Likewise.
5621 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
5622 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
5623 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
5624 (mve_veorq_m_<supf><mode>): Likewise.
5625 (mve_vhaddq_m_n_<supf><mode>): Likewise.
5626 (mve_vhaddq_m_<supf><mode>): Likewise.
5627 (mve_vhsubq_m_n_<supf><mode>): Likewise.
5628 (mve_vhsubq_m_<supf><mode>): Likewise.
5629 (mve_vmaxq_m_<supf><mode>): Likewise.
5630 (mve_vminq_m_<supf><mode>): Likewise.
5631 (mve_vmladavaq_p_<supf><mode>): Likewise.
5632 (mve_vmlaq_m_n_<supf><mode>): Likewise.
5633 (mve_vmlasq_m_n_<supf><mode>): Likewise.
5634 (mve_vmulhq_m_<supf><mode>): Likewise.
5635 (mve_vmullbq_int_m_<supf><mode>): Likewise.
5636 (mve_vmulltq_int_m_<supf><mode>): Likewise.
5637 (mve_vmulq_m_n_<supf><mode>): Likewise.
5638 (mve_vmulq_m_<supf><mode>): Likewise.
5639 (mve_vornq_m_<supf><mode>): Likewise.
5640 (mve_vorrq_m_<supf><mode>): Likewise.
5641 (mve_vqaddq_m_n_<supf><mode>): Likewise.
5642 (mve_vqaddq_m_<supf><mode>): Likewise.
5643 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
5644 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
5645 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
5646 (mve_vqrshlq_m_<supf><mode>): Likewise.
5647 (mve_vqshlq_m_n_<supf><mode>): Likewise.
5648 (mve_vqshlq_m_<supf><mode>): Likewise.
5649 (mve_vqsubq_m_n_<supf><mode>): Likewise.
5650 (mve_vqsubq_m_<supf><mode>): Likewise.
5651 (mve_vrhaddq_m_<supf><mode>): Likewise.
5652 (mve_vrmulhq_m_<supf><mode>): Likewise.
5653 (mve_vrshlq_m_<supf><mode>): Likewise.
5654 (mve_vrshrq_m_n_<supf><mode>): Likewise.
5655 (mve_vshlq_m_n_<supf><mode>): Likewise.
5656 (mve_vshrq_m_n_<supf><mode>): Likewise.
5657 (mve_vsliq_m_n_<supf><mode>): Likewise.
5658 (mve_vsubq_m_n_<supf><mode>): Likewise.
5659 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
5660 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
5661 (mve_vmladavaxq_p_s<mode>): Likewise.
5662 (mve_vmlsdavaq_p_s<mode>): Likewise.
5663 (mve_vmlsdavaxq_p_s<mode>): Likewise.
5664 (mve_vqdmladhq_m_s<mode>): Likewise.
5665 (mve_vqdmladhxq_m_s<mode>): Likewise.
5666 (mve_vqdmlsdhq_m_s<mode>): Likewise.
5667 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
5668 (mve_vqdmulhq_m_n_s<mode>): Likewise.
5669 (mve_vqdmulhq_m_s<mode>): Likewise.
5670 (mve_vqrdmladhq_m_s<mode>): Likewise.
5671 (mve_vqrdmladhxq_m_s<mode>): Likewise.
5672 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
5673 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
5674 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
5675 (mve_vqrdmulhq_m_s<mode>): Likewise.
5677 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5678 Mihail Ionescu <mihail.ionescu@arm.com>
5679 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5681 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
5682 Define builtin qualifier.
5683 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
5684 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5685 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
5686 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5687 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5688 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5689 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
5690 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
5691 (vsubq_m_s8): Likewise.
5692 (vcvtq_m_n_f16_u16): Likewise.
5693 (vqshluq_m_n_s8): Likewise.
5694 (vabavq_p_s8): Likewise.
5695 (vsriq_m_n_u8): Likewise.
5696 (vshlq_m_u8): Likewise.
5697 (vsubq_m_u8): Likewise.
5698 (vabavq_p_u8): Likewise.
5699 (vshlq_m_s8): Likewise.
5700 (vcvtq_m_n_f16_s16): Likewise.
5701 (vsriq_m_n_s16): Likewise.
5702 (vsubq_m_s16): Likewise.
5703 (vcvtq_m_n_f32_u32): Likewise.
5704 (vqshluq_m_n_s16): Likewise.
5705 (vabavq_p_s16): Likewise.
5706 (vsriq_m_n_u16): Likewise.
5707 (vshlq_m_u16): Likewise.
5708 (vsubq_m_u16): Likewise.
5709 (vabavq_p_u16): Likewise.
5710 (vshlq_m_s16): Likewise.
5711 (vcvtq_m_n_f32_s32): Likewise.
5712 (vsriq_m_n_s32): Likewise.
5713 (vsubq_m_s32): Likewise.
5714 (vqshluq_m_n_s32): Likewise.
5715 (vabavq_p_s32): Likewise.
5716 (vsriq_m_n_u32): Likewise.
5717 (vshlq_m_u32): Likewise.
5718 (vsubq_m_u32): Likewise.
5719 (vabavq_p_u32): Likewise.
5720 (vshlq_m_s32): Likewise.
5721 (__arm_vsriq_m_n_s8): Define intrinsic.
5722 (__arm_vsubq_m_s8): Likewise.
5723 (__arm_vqshluq_m_n_s8): Likewise.
5724 (__arm_vabavq_p_s8): Likewise.
5725 (__arm_vsriq_m_n_u8): Likewise.
5726 (__arm_vshlq_m_u8): Likewise.
5727 (__arm_vsubq_m_u8): Likewise.
5728 (__arm_vabavq_p_u8): Likewise.
5729 (__arm_vshlq_m_s8): Likewise.
5730 (__arm_vsriq_m_n_s16): Likewise.
5731 (__arm_vsubq_m_s16): Likewise.
5732 (__arm_vqshluq_m_n_s16): Likewise.
5733 (__arm_vabavq_p_s16): Likewise.
5734 (__arm_vsriq_m_n_u16): Likewise.
5735 (__arm_vshlq_m_u16): Likewise.
5736 (__arm_vsubq_m_u16): Likewise.
5737 (__arm_vabavq_p_u16): Likewise.
5738 (__arm_vshlq_m_s16): Likewise.
5739 (__arm_vsriq_m_n_s32): Likewise.
5740 (__arm_vsubq_m_s32): Likewise.
5741 (__arm_vqshluq_m_n_s32): Likewise.
5742 (__arm_vabavq_p_s32): Likewise.
5743 (__arm_vsriq_m_n_u32): Likewise.
5744 (__arm_vshlq_m_u32): Likewise.
5745 (__arm_vsubq_m_u32): Likewise.
5746 (__arm_vabavq_p_u32): Likewise.
5747 (__arm_vshlq_m_s32): Likewise.
5748 (__arm_vcvtq_m_n_f16_u16): Likewise.
5749 (__arm_vcvtq_m_n_f16_s16): Likewise.
5750 (__arm_vcvtq_m_n_f32_u32): Likewise.
5751 (__arm_vcvtq_m_n_f32_s32): Likewise.
5752 (vcvtq_m_n): Define polymorphic variant.
5753 (vqshluq_m_n): Likewise.
5754 (vshlq_m): Likewise.
5755 (vsriq_m_n): Likewise.
5756 (vsubq_m): Likewise.
5757 (vabavq_p): Likewise.
5758 * config/arm/arm_mve_builtins.def
5759 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
5760 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
5761 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5762 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
5763 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5764 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5765 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5766 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
5767 * config/arm/mve.md (VABAVQ_P): Define iterator.
5768 (VSHLQ_M): Likewise.
5769 (VSRIQ_M_N): Likewise.
5770 (VSUBQ_M): Likewise.
5771 (VCVTQ_M_N_TO_F): Likewise.
5772 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
5773 (mve_vqshluq_m_n_s<mode>): Likewise.
5774 (mve_vshlq_m_<supf><mode>): Likewise.
5775 (mve_vsriq_m_n_<supf><mode>): Likewise.
5776 (mve_vsubq_m_<supf><mode>): Likewise.
5777 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
5779 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5780 Mihail Ionescu <mihail.ionescu@arm.com>
5781 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5783 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
5784 (vrmlsldavhaq_s32): Likewise.
5785 (vrmlsldavhaxq_s32): Likewise.
5786 (vaddlvaq_p_s32): Likewise.
5787 (vcvtbq_m_f16_f32): Likewise.
5788 (vcvtbq_m_f32_f16): Likewise.
5789 (vcvttq_m_f16_f32): Likewise.
5790 (vcvttq_m_f32_f16): Likewise.
5791 (vrev16q_m_s8): Likewise.
5792 (vrev32q_m_f16): Likewise.
5793 (vrmlaldavhq_p_s32): Likewise.
5794 (vrmlaldavhxq_p_s32): Likewise.
5795 (vrmlsldavhq_p_s32): Likewise.
5796 (vrmlsldavhxq_p_s32): Likewise.
5797 (vaddlvaq_p_u32): Likewise.
5798 (vrev16q_m_u8): Likewise.
5799 (vrmlaldavhq_p_u32): Likewise.
5800 (vmvnq_m_n_s16): Likewise.
5801 (vorrq_m_n_s16): Likewise.
5802 (vqrshrntq_n_s16): Likewise.
5803 (vqshrnbq_n_s16): Likewise.
5804 (vqshrntq_n_s16): Likewise.
5805 (vrshrnbq_n_s16): Likewise.
5806 (vrshrntq_n_s16): Likewise.
5807 (vshrnbq_n_s16): Likewise.
5808 (vshrntq_n_s16): Likewise.
5809 (vcmlaq_f16): Likewise.
5810 (vcmlaq_rot180_f16): Likewise.
5811 (vcmlaq_rot270_f16): Likewise.
5812 (vcmlaq_rot90_f16): Likewise.
5813 (vfmaq_f16): Likewise.
5814 (vfmaq_n_f16): Likewise.
5815 (vfmasq_n_f16): Likewise.
5816 (vfmsq_f16): Likewise.
5817 (vmlaldavaq_s16): Likewise.
5818 (vmlaldavaxq_s16): Likewise.
5819 (vmlsldavaq_s16): Likewise.
5820 (vmlsldavaxq_s16): Likewise.
5821 (vabsq_m_f16): Likewise.
5822 (vcvtmq_m_s16_f16): Likewise.
5823 (vcvtnq_m_s16_f16): Likewise.
5824 (vcvtpq_m_s16_f16): Likewise.
5825 (vcvtq_m_s16_f16): Likewise.
5826 (vdupq_m_n_f16): Likewise.
5827 (vmaxnmaq_m_f16): Likewise.
5828 (vmaxnmavq_p_f16): Likewise.
5829 (vmaxnmvq_p_f16): Likewise.
5830 (vminnmaq_m_f16): Likewise.
5831 (vminnmavq_p_f16): Likewise.
5832 (vminnmvq_p_f16): Likewise.
5833 (vmlaldavq_p_s16): Likewise.
5834 (vmlaldavxq_p_s16): Likewise.
5835 (vmlsldavq_p_s16): Likewise.
5836 (vmlsldavxq_p_s16): Likewise.
5837 (vmovlbq_m_s8): Likewise.
5838 (vmovltq_m_s8): Likewise.
5839 (vmovnbq_m_s16): Likewise.
5840 (vmovntq_m_s16): Likewise.
5841 (vnegq_m_f16): Likewise.
5842 (vpselq_f16): Likewise.
5843 (vqmovnbq_m_s16): Likewise.
5844 (vqmovntq_m_s16): Likewise.
5845 (vrev32q_m_s8): Likewise.
5846 (vrev64q_m_f16): Likewise.
5847 (vrndaq_m_f16): Likewise.
5848 (vrndmq_m_f16): Likewise.
5849 (vrndnq_m_f16): Likewise.
5850 (vrndpq_m_f16): Likewise.
5851 (vrndq_m_f16): Likewise.
5852 (vrndxq_m_f16): Likewise.
5853 (vcmpeqq_m_n_f16): Likewise.
5854 (vcmpgeq_m_f16): Likewise.
5855 (vcmpgeq_m_n_f16): Likewise.
5856 (vcmpgtq_m_f16): Likewise.
5857 (vcmpgtq_m_n_f16): Likewise.
5858 (vcmpleq_m_f16): Likewise.
5859 (vcmpleq_m_n_f16): Likewise.
5860 (vcmpltq_m_f16): Likewise.
5861 (vcmpltq_m_n_f16): Likewise.
5862 (vcmpneq_m_f16): Likewise.
5863 (vcmpneq_m_n_f16): Likewise.
5864 (vmvnq_m_n_u16): Likewise.
5865 (vorrq_m_n_u16): Likewise.
5866 (vqrshruntq_n_s16): Likewise.
5867 (vqshrunbq_n_s16): Likewise.
5868 (vqshruntq_n_s16): Likewise.
5869 (vcvtmq_m_u16_f16): Likewise.
5870 (vcvtnq_m_u16_f16): Likewise.
5871 (vcvtpq_m_u16_f16): Likewise.
5872 (vcvtq_m_u16_f16): Likewise.
5873 (vqmovunbq_m_s16): Likewise.
5874 (vqmovuntq_m_s16): Likewise.
5875 (vqrshrntq_n_u16): Likewise.
5876 (vqshrnbq_n_u16): Likewise.
5877 (vqshrntq_n_u16): Likewise.
5878 (vrshrnbq_n_u16): Likewise.
5879 (vrshrntq_n_u16): Likewise.
5880 (vshrnbq_n_u16): Likewise.
5881 (vshrntq_n_u16): Likewise.
5882 (vmlaldavaq_u16): Likewise.
5883 (vmlaldavaxq_u16): Likewise.
5884 (vmlaldavq_p_u16): Likewise.
5885 (vmlaldavxq_p_u16): Likewise.
5886 (vmovlbq_m_u8): Likewise.
5887 (vmovltq_m_u8): Likewise.
5888 (vmovnbq_m_u16): Likewise.
5889 (vmovntq_m_u16): Likewise.
5890 (vqmovnbq_m_u16): Likewise.
5891 (vqmovntq_m_u16): Likewise.
5892 (vrev32q_m_u8): Likewise.
5893 (vmvnq_m_n_s32): Likewise.
5894 (vorrq_m_n_s32): Likewise.
5895 (vqrshrntq_n_s32): Likewise.
5896 (vqshrnbq_n_s32): Likewise.
5897 (vqshrntq_n_s32): Likewise.
5898 (vrshrnbq_n_s32): Likewise.
5899 (vrshrntq_n_s32): Likewise.
5900 (vshrnbq_n_s32): Likewise.
5901 (vshrntq_n_s32): Likewise.
5902 (vcmlaq_f32): Likewise.
5903 (vcmlaq_rot180_f32): Likewise.
5904 (vcmlaq_rot270_f32): Likewise.
5905 (vcmlaq_rot90_f32): Likewise.
5906 (vfmaq_f32): Likewise.
5907 (vfmaq_n_f32): Likewise.
5908 (vfmasq_n_f32): Likewise.
5909 (vfmsq_f32): Likewise.
5910 (vmlaldavaq_s32): Likewise.
5911 (vmlaldavaxq_s32): Likewise.
5912 (vmlsldavaq_s32): Likewise.
5913 (vmlsldavaxq_s32): Likewise.
5914 (vabsq_m_f32): Likewise.
5915 (vcvtmq_m_s32_f32): Likewise.
5916 (vcvtnq_m_s32_f32): Likewise.
5917 (vcvtpq_m_s32_f32): Likewise.
5918 (vcvtq_m_s32_f32): Likewise.
5919 (vdupq_m_n_f32): Likewise.
5920 (vmaxnmaq_m_f32): Likewise.
5921 (vmaxnmavq_p_f32): Likewise.
5922 (vmaxnmvq_p_f32): Likewise.
5923 (vminnmaq_m_f32): Likewise.
5924 (vminnmavq_p_f32): Likewise.
5925 (vminnmvq_p_f32): Likewise.
5926 (vmlaldavq_p_s32): Likewise.
5927 (vmlaldavxq_p_s32): Likewise.
5928 (vmlsldavq_p_s32): Likewise.
5929 (vmlsldavxq_p_s32): Likewise.
5930 (vmovlbq_m_s16): Likewise.
5931 (vmovltq_m_s16): Likewise.
5932 (vmovnbq_m_s32): Likewise.
5933 (vmovntq_m_s32): Likewise.
5934 (vnegq_m_f32): Likewise.
5935 (vpselq_f32): Likewise.
5936 (vqmovnbq_m_s32): Likewise.
5937 (vqmovntq_m_s32): Likewise.
5938 (vrev32q_m_s16): Likewise.
5939 (vrev64q_m_f32): Likewise.
5940 (vrndaq_m_f32): Likewise.
5941 (vrndmq_m_f32): Likewise.
5942 (vrndnq_m_f32): Likewise.
5943 (vrndpq_m_f32): Likewise.
5944 (vrndq_m_f32): Likewise.
5945 (vrndxq_m_f32): Likewise.
5946 (vcmpeqq_m_n_f32): Likewise.
5947 (vcmpgeq_m_f32): Likewise.
5948 (vcmpgeq_m_n_f32): Likewise.
5949 (vcmpgtq_m_f32): Likewise.
5950 (vcmpgtq_m_n_f32): Likewise.
5951 (vcmpleq_m_f32): Likewise.
5952 (vcmpleq_m_n_f32): Likewise.
5953 (vcmpltq_m_f32): Likewise.
5954 (vcmpltq_m_n_f32): Likewise.
5955 (vcmpneq_m_f32): Likewise.
5956 (vcmpneq_m_n_f32): Likewise.
5957 (vmvnq_m_n_u32): Likewise.
5958 (vorrq_m_n_u32): Likewise.
5959 (vqrshruntq_n_s32): Likewise.
5960 (vqshrunbq_n_s32): Likewise.
5961 (vqshruntq_n_s32): Likewise.
5962 (vcvtmq_m_u32_f32): Likewise.
5963 (vcvtnq_m_u32_f32): Likewise.
5964 (vcvtpq_m_u32_f32): Likewise.
5965 (vcvtq_m_u32_f32): Likewise.
5966 (vqmovunbq_m_s32): Likewise.
5967 (vqmovuntq_m_s32): Likewise.
5968 (vqrshrntq_n_u32): Likewise.
5969 (vqshrnbq_n_u32): Likewise.
5970 (vqshrntq_n_u32): Likewise.
5971 (vrshrnbq_n_u32): Likewise.
5972 (vrshrntq_n_u32): Likewise.
5973 (vshrnbq_n_u32): Likewise.
5974 (vshrntq_n_u32): Likewise.
5975 (vmlaldavaq_u32): Likewise.
5976 (vmlaldavaxq_u32): Likewise.
5977 (vmlaldavq_p_u32): Likewise.
5978 (vmlaldavxq_p_u32): Likewise.
5979 (vmovlbq_m_u16): Likewise.
5980 (vmovltq_m_u16): Likewise.
5981 (vmovnbq_m_u32): Likewise.
5982 (vmovntq_m_u32): Likewise.
5983 (vqmovnbq_m_u32): Likewise.
5984 (vqmovntq_m_u32): Likewise.
5985 (vrev32q_m_u16): Likewise.
5986 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
5987 (__arm_vrmlsldavhaq_s32): Likewise.
5988 (__arm_vrmlsldavhaxq_s32): Likewise.
5989 (__arm_vaddlvaq_p_s32): Likewise.
5990 (__arm_vrev16q_m_s8): Likewise.
5991 (__arm_vrmlaldavhq_p_s32): Likewise.
5992 (__arm_vrmlaldavhxq_p_s32): Likewise.
5993 (__arm_vrmlsldavhq_p_s32): Likewise.
5994 (__arm_vrmlsldavhxq_p_s32): Likewise.
5995 (__arm_vaddlvaq_p_u32): Likewise.
5996 (__arm_vrev16q_m_u8): Likewise.
5997 (__arm_vrmlaldavhq_p_u32): Likewise.
5998 (__arm_vmvnq_m_n_s16): Likewise.
5999 (__arm_vorrq_m_n_s16): Likewise.
6000 (__arm_vqrshrntq_n_s16): Likewise.
6001 (__arm_vqshrnbq_n_s16): Likewise.
6002 (__arm_vqshrntq_n_s16): Likewise.
6003 (__arm_vrshrnbq_n_s16): Likewise.
6004 (__arm_vrshrntq_n_s16): Likewise.
6005 (__arm_vshrnbq_n_s16): Likewise.
6006 (__arm_vshrntq_n_s16): Likewise.
6007 (__arm_vmlaldavaq_s16): Likewise.
6008 (__arm_vmlaldavaxq_s16): Likewise.
6009 (__arm_vmlsldavaq_s16): Likewise.
6010 (__arm_vmlsldavaxq_s16): Likewise.
6011 (__arm_vmlaldavq_p_s16): Likewise.
6012 (__arm_vmlaldavxq_p_s16): Likewise.
6013 (__arm_vmlsldavq_p_s16): Likewise.
6014 (__arm_vmlsldavxq_p_s16): Likewise.
6015 (__arm_vmovlbq_m_s8): Likewise.
6016 (__arm_vmovltq_m_s8): Likewise.
6017 (__arm_vmovnbq_m_s16): Likewise.
6018 (__arm_vmovntq_m_s16): Likewise.
6019 (__arm_vqmovnbq_m_s16): Likewise.
6020 (__arm_vqmovntq_m_s16): Likewise.
6021 (__arm_vrev32q_m_s8): Likewise.
6022 (__arm_vmvnq_m_n_u16): Likewise.
6023 (__arm_vorrq_m_n_u16): Likewise.
6024 (__arm_vqrshruntq_n_s16): Likewise.
6025 (__arm_vqshrunbq_n_s16): Likewise.
6026 (__arm_vqshruntq_n_s16): Likewise.
6027 (__arm_vqmovunbq_m_s16): Likewise.
6028 (__arm_vqmovuntq_m_s16): Likewise.
6029 (__arm_vqrshrntq_n_u16): Likewise.
6030 (__arm_vqshrnbq_n_u16): Likewise.
6031 (__arm_vqshrntq_n_u16): Likewise.
6032 (__arm_vrshrnbq_n_u16): Likewise.
6033 (__arm_vrshrntq_n_u16): Likewise.
6034 (__arm_vshrnbq_n_u16): Likewise.
6035 (__arm_vshrntq_n_u16): Likewise.
6036 (__arm_vmlaldavaq_u16): Likewise.
6037 (__arm_vmlaldavaxq_u16): Likewise.
6038 (__arm_vmlaldavq_p_u16): Likewise.
6039 (__arm_vmlaldavxq_p_u16): Likewise.
6040 (__arm_vmovlbq_m_u8): Likewise.
6041 (__arm_vmovltq_m_u8): Likewise.
6042 (__arm_vmovnbq_m_u16): Likewise.
6043 (__arm_vmovntq_m_u16): Likewise.
6044 (__arm_vqmovnbq_m_u16): Likewise.
6045 (__arm_vqmovntq_m_u16): Likewise.
6046 (__arm_vrev32q_m_u8): Likewise.
6047 (__arm_vmvnq_m_n_s32): Likewise.
6048 (__arm_vorrq_m_n_s32): Likewise.
6049 (__arm_vqrshrntq_n_s32): Likewise.
6050 (__arm_vqshrnbq_n_s32): Likewise.
6051 (__arm_vqshrntq_n_s32): Likewise.
6052 (__arm_vrshrnbq_n_s32): Likewise.
6053 (__arm_vrshrntq_n_s32): Likewise.
6054 (__arm_vshrnbq_n_s32): Likewise.
6055 (__arm_vshrntq_n_s32): Likewise.
6056 (__arm_vmlaldavaq_s32): Likewise.
6057 (__arm_vmlaldavaxq_s32): Likewise.
6058 (__arm_vmlsldavaq_s32): Likewise.
6059 (__arm_vmlsldavaxq_s32): Likewise.
6060 (__arm_vmlaldavq_p_s32): Likewise.
6061 (__arm_vmlaldavxq_p_s32): Likewise.
6062 (__arm_vmlsldavq_p_s32): Likewise.
6063 (__arm_vmlsldavxq_p_s32): Likewise.
6064 (__arm_vmovlbq_m_s16): Likewise.
6065 (__arm_vmovltq_m_s16): Likewise.
6066 (__arm_vmovnbq_m_s32): Likewise.
6067 (__arm_vmovntq_m_s32): Likewise.
6068 (__arm_vqmovnbq_m_s32): Likewise.
6069 (__arm_vqmovntq_m_s32): Likewise.
6070 (__arm_vrev32q_m_s16): Likewise.
6071 (__arm_vmvnq_m_n_u32): Likewise.
6072 (__arm_vorrq_m_n_u32): Likewise.
6073 (__arm_vqrshruntq_n_s32): Likewise.
6074 (__arm_vqshrunbq_n_s32): Likewise.
6075 (__arm_vqshruntq_n_s32): Likewise.
6076 (__arm_vqmovunbq_m_s32): Likewise.
6077 (__arm_vqmovuntq_m_s32): Likewise.
6078 (__arm_vqrshrntq_n_u32): Likewise.
6079 (__arm_vqshrnbq_n_u32): Likewise.
6080 (__arm_vqshrntq_n_u32): Likewise.
6081 (__arm_vrshrnbq_n_u32): Likewise.
6082 (__arm_vrshrntq_n_u32): Likewise.
6083 (__arm_vshrnbq_n_u32): Likewise.
6084 (__arm_vshrntq_n_u32): Likewise.
6085 (__arm_vmlaldavaq_u32): Likewise.
6086 (__arm_vmlaldavaxq_u32): Likewise.
6087 (__arm_vmlaldavq_p_u32): Likewise.
6088 (__arm_vmlaldavxq_p_u32): Likewise.
6089 (__arm_vmovlbq_m_u16): Likewise.
6090 (__arm_vmovltq_m_u16): Likewise.
6091 (__arm_vmovnbq_m_u32): Likewise.
6092 (__arm_vmovntq_m_u32): Likewise.
6093 (__arm_vqmovnbq_m_u32): Likewise.
6094 (__arm_vqmovntq_m_u32): Likewise.
6095 (__arm_vrev32q_m_u16): Likewise.
6096 (__arm_vcvtbq_m_f16_f32): Likewise.
6097 (__arm_vcvtbq_m_f32_f16): Likewise.
6098 (__arm_vcvttq_m_f16_f32): Likewise.
6099 (__arm_vcvttq_m_f32_f16): Likewise.
6100 (__arm_vrev32q_m_f16): Likewise.
6101 (__arm_vcmlaq_f16): Likewise.
6102 (__arm_vcmlaq_rot180_f16): Likewise.
6103 (__arm_vcmlaq_rot270_f16): Likewise.
6104 (__arm_vcmlaq_rot90_f16): Likewise.
6105 (__arm_vfmaq_f16): Likewise.
6106 (__arm_vfmaq_n_f16): Likewise.
6107 (__arm_vfmasq_n_f16): Likewise.
6108 (__arm_vfmsq_f16): Likewise.
6109 (__arm_vabsq_m_f16): Likewise.
6110 (__arm_vcvtmq_m_s16_f16): Likewise.
6111 (__arm_vcvtnq_m_s16_f16): Likewise.
6112 (__arm_vcvtpq_m_s16_f16): Likewise.
6113 (__arm_vcvtq_m_s16_f16): Likewise.
6114 (__arm_vdupq_m_n_f16): Likewise.
6115 (__arm_vmaxnmaq_m_f16): Likewise.
6116 (__arm_vmaxnmavq_p_f16): Likewise.
6117 (__arm_vmaxnmvq_p_f16): Likewise.
6118 (__arm_vminnmaq_m_f16): Likewise.
6119 (__arm_vminnmavq_p_f16): Likewise.
6120 (__arm_vminnmvq_p_f16): Likewise.
6121 (__arm_vnegq_m_f16): Likewise.
6122 (__arm_vpselq_f16): Likewise.
6123 (__arm_vrev64q_m_f16): Likewise.
6124 (__arm_vrndaq_m_f16): Likewise.
6125 (__arm_vrndmq_m_f16): Likewise.
6126 (__arm_vrndnq_m_f16): Likewise.
6127 (__arm_vrndpq_m_f16): Likewise.
6128 (__arm_vrndq_m_f16): Likewise.
6129 (__arm_vrndxq_m_f16): Likewise.
6130 (__arm_vcmpeqq_m_n_f16): Likewise.
6131 (__arm_vcmpgeq_m_f16): Likewise.
6132 (__arm_vcmpgeq_m_n_f16): Likewise.
6133 (__arm_vcmpgtq_m_f16): Likewise.
6134 (__arm_vcmpgtq_m_n_f16): Likewise.
6135 (__arm_vcmpleq_m_f16): Likewise.
6136 (__arm_vcmpleq_m_n_f16): Likewise.
6137 (__arm_vcmpltq_m_f16): Likewise.
6138 (__arm_vcmpltq_m_n_f16): Likewise.
6139 (__arm_vcmpneq_m_f16): Likewise.
6140 (__arm_vcmpneq_m_n_f16): Likewise.
6141 (__arm_vcvtmq_m_u16_f16): Likewise.
6142 (__arm_vcvtnq_m_u16_f16): Likewise.
6143 (__arm_vcvtpq_m_u16_f16): Likewise.
6144 (__arm_vcvtq_m_u16_f16): Likewise.
6145 (__arm_vcmlaq_f32): Likewise.
6146 (__arm_vcmlaq_rot180_f32): Likewise.
6147 (__arm_vcmlaq_rot270_f32): Likewise.
6148 (__arm_vcmlaq_rot90_f32): Likewise.
6149 (__arm_vfmaq_f32): Likewise.
6150 (__arm_vfmaq_n_f32): Likewise.
6151 (__arm_vfmasq_n_f32): Likewise.
6152 (__arm_vfmsq_f32): Likewise.
6153 (__arm_vabsq_m_f32): Likewise.
6154 (__arm_vcvtmq_m_s32_f32): Likewise.
6155 (__arm_vcvtnq_m_s32_f32): Likewise.
6156 (__arm_vcvtpq_m_s32_f32): Likewise.
6157 (__arm_vcvtq_m_s32_f32): Likewise.
6158 (__arm_vdupq_m_n_f32): Likewise.
6159 (__arm_vmaxnmaq_m_f32): Likewise.
6160 (__arm_vmaxnmavq_p_f32): Likewise.
6161 (__arm_vmaxnmvq_p_f32): Likewise.
6162 (__arm_vminnmaq_m_f32): Likewise.
6163 (__arm_vminnmavq_p_f32): Likewise.
6164 (__arm_vminnmvq_p_f32): Likewise.
6165 (__arm_vnegq_m_f32): Likewise.
6166 (__arm_vpselq_f32): Likewise.
6167 (__arm_vrev64q_m_f32): Likewise.
6168 (__arm_vrndaq_m_f32): Likewise.
6169 (__arm_vrndmq_m_f32): Likewise.
6170 (__arm_vrndnq_m_f32): Likewise.
6171 (__arm_vrndpq_m_f32): Likewise.
6172 (__arm_vrndq_m_f32): Likewise.
6173 (__arm_vrndxq_m_f32): Likewise.
6174 (__arm_vcmpeqq_m_n_f32): Likewise.
6175 (__arm_vcmpgeq_m_f32): Likewise.
6176 (__arm_vcmpgeq_m_n_f32): Likewise.
6177 (__arm_vcmpgtq_m_f32): Likewise.
6178 (__arm_vcmpgtq_m_n_f32): Likewise.
6179 (__arm_vcmpleq_m_f32): Likewise.
6180 (__arm_vcmpleq_m_n_f32): Likewise.
6181 (__arm_vcmpltq_m_f32): Likewise.
6182 (__arm_vcmpltq_m_n_f32): Likewise.
6183 (__arm_vcmpneq_m_f32): Likewise.
6184 (__arm_vcmpneq_m_n_f32): Likewise.
6185 (__arm_vcvtmq_m_u32_f32): Likewise.
6186 (__arm_vcvtnq_m_u32_f32): Likewise.
6187 (__arm_vcvtpq_m_u32_f32): Likewise.
6188 (__arm_vcvtq_m_u32_f32): Likewise.
6189 (vcvtq_m): Define polymorphic variant.
6190 (vabsq_m): Likewise.
6192 (vcmlaq_rot180): Likewise.
6193 (vcmlaq_rot270): Likewise.
6194 (vcmlaq_rot90): Likewise.
6195 (vcmpeqq_m_n): Likewise.
6196 (vcmpgeq_m_n): Likewise.
6197 (vrndxq_m): Likewise.
6198 (vrndq_m): Likewise.
6199 (vrndpq_m): Likewise.
6200 (vcmpgtq_m_n): Likewise.
6201 (vcmpgtq_m): Likewise.
6202 (vcmpleq_m): Likewise.
6203 (vcmpleq_m_n): Likewise.
6204 (vcmpltq_m_n): Likewise.
6205 (vcmpltq_m): Likewise.
6206 (vcmpneq_m): Likewise.
6207 (vcmpneq_m_n): Likewise.
6208 (vcvtbq_m): Likewise.
6209 (vcvttq_m): Likewise.
6210 (vcvtmq_m): Likewise.
6211 (vcvtnq_m): Likewise.
6212 (vcvtpq_m): Likewise.
6213 (vdupq_m_n): Likewise.
6214 (vfmaq_n): Likewise.
6216 (vfmasq_n): Likewise.
6218 (vmaxnmaq_m): Likewise.
6219 (vmaxnmavq_m): Likewise.
6220 (vmaxnmvq_m): Likewise.
6221 (vmaxnmavq_p): Likewise.
6222 (vmaxnmvq_p): Likewise.
6223 (vminnmaq_m): Likewise.
6224 (vminnmavq_p): Likewise.
6225 (vminnmvq_p): Likewise.
6226 (vrndnq_m): Likewise.
6227 (vrndaq_m): Likewise.
6228 (vrndmq_m): Likewise.
6229 (vrev64q_m): Likewise.
6230 (vrev32q_m): Likewise.
6232 (vnegq_m): Likewise.
6233 (vcmpgeq_m): Likewise.
6234 (vshrntq_n): Likewise.
6235 (vrshrntq_n): Likewise.
6236 (vmovlbq_m): Likewise.
6237 (vmovnbq_m): Likewise.
6238 (vmovntq_m): Likewise.
6239 (vmvnq_m_n): Likewise.
6240 (vmvnq_m): Likewise.
6241 (vshrnbq_n): Likewise.
6242 (vrshrnbq_n): Likewise.
6243 (vqshruntq_n): Likewise.
6244 (vrev16q_m): Likewise.
6245 (vqshrunbq_n): Likewise.
6246 (vqshrntq_n): Likewise.
6247 (vqrshruntq_n): Likewise.
6248 (vqrshrntq_n): Likewise.
6249 (vqshrnbq_n): Likewise.
6250 (vqmovuntq_m): Likewise.
6251 (vqmovntq_m): Likewise.
6252 (vqmovnbq_m): Likewise.
6253 (vorrq_m_n): Likewise.
6254 (vmovltq_m): Likewise.
6255 (vqmovunbq_m): Likewise.
6256 (vaddlvaq_p): Likewise.
6257 (vmlaldavaq): Likewise.
6258 (vmlaldavaxq): Likewise.
6259 (vmlaldavq_p): Likewise.
6260 (vmlaldavxq_p): Likewise.
6261 (vmlsldavaq): Likewise.
6262 (vmlsldavaxq): Likewise.
6263 (vmlsldavq_p): Likewise.
6264 (vmlsldavxq_p): Likewise.
6265 (vrmlaldavhaxq): Likewise.
6266 (vrmlaldavhq_p): Likewise.
6267 (vrmlaldavhxq_p): Likewise.
6268 (vrmlsldavhaq): Likewise.
6269 (vrmlsldavhaxq): Likewise.
6270 (vrmlsldavhq_p): Likewise.
6271 (vrmlsldavhxq_p): Likewise.
6272 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
6274 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
6275 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
6276 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
6277 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
6278 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
6279 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
6280 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
6281 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
6282 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
6283 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
6284 (MVE_pred3): Likewise.
6285 (MVE_constraint1): Likewise.
6286 (MVE_pred1): Likewise.
6287 (VMLALDAVQ_P): Define iterator.
6288 (VQMOVNBQ_M): Likewise.
6289 (VMOVLTQ_M): Likewise.
6290 (VMOVNBQ_M): Likewise.
6291 (VRSHRNTQ_N): Likewise.
6292 (VORRQ_M_N): Likewise.
6293 (VREV32Q_M): Likewise.
6294 (VREV16Q_M): Likewise.
6295 (VQRSHRNTQ_N): Likewise.
6296 (VMOVNTQ_M): Likewise.
6297 (VMOVLBQ_M): Likewise.
6298 (VMLALDAVAQ): Likewise.
6299 (VQSHRNBQ_N): Likewise.
6300 (VSHRNBQ_N): Likewise.
6301 (VRSHRNBQ_N): Likewise.
6302 (VMLALDAVXQ_P): Likewise.
6303 (VQMOVNTQ_M): Likewise.
6304 (VMVNQ_M_N): Likewise.
6305 (VQSHRNTQ_N): Likewise.
6306 (VMLALDAVAXQ): Likewise.
6307 (VSHRNTQ_N): Likewise.
6308 (VCVTMQ_M): Likewise.
6309 (VCVTNQ_M): Likewise.
6310 (VCVTPQ_M): Likewise.
6311 (VCVTQ_M_N_FROM_F): Likewise.
6312 (VCVTQ_M_FROM_F): Likewise.
6313 (VRMLALDAVHQ_P): Likewise.
6314 (VADDLVAQ_P): Likewise.
6315 (mve_vrndq_m_f<mode>): Define RTL pattern.
6316 (mve_vabsq_m_f<mode>): Likewise.
6317 (mve_vaddlvaq_p_<supf>v4si): Likewise.
6318 (mve_vcmlaq_f<mode>): Likewise.
6319 (mve_vcmlaq_rot180_f<mode>): Likewise.
6320 (mve_vcmlaq_rot270_f<mode>): Likewise.
6321 (mve_vcmlaq_rot90_f<mode>): Likewise.
6322 (mve_vcmpeqq_m_n_f<mode>): Likewise.
6323 (mve_vcmpgeq_m_f<mode>): Likewise.
6324 (mve_vcmpgeq_m_n_f<mode>): Likewise.
6325 (mve_vcmpgtq_m_f<mode>): Likewise.
6326 (mve_vcmpgtq_m_n_f<mode>): Likewise.
6327 (mve_vcmpleq_m_f<mode>): Likewise.
6328 (mve_vcmpleq_m_n_f<mode>): Likewise.
6329 (mve_vcmpltq_m_f<mode>): Likewise.
6330 (mve_vcmpltq_m_n_f<mode>): Likewise.
6331 (mve_vcmpneq_m_f<mode>): Likewise.
6332 (mve_vcmpneq_m_n_f<mode>): Likewise.
6333 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
6334 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
6335 (mve_vcvttq_m_f16_f32v8hf): Likewise.
6336 (mve_vcvttq_m_f32_f16v4sf): Likewise.
6337 (mve_vdupq_m_n_f<mode>): Likewise.
6338 (mve_vfmaq_f<mode>): Likewise.
6339 (mve_vfmaq_n_f<mode>): Likewise.
6340 (mve_vfmasq_n_f<mode>): Likewise.
6341 (mve_vfmsq_f<mode>): Likewise.
6342 (mve_vmaxnmaq_m_f<mode>): Likewise.
6343 (mve_vmaxnmavq_p_f<mode>): Likewise.
6344 (mve_vmaxnmvq_p_f<mode>): Likewise.
6345 (mve_vminnmaq_m_f<mode>): Likewise.
6346 (mve_vminnmavq_p_f<mode>): Likewise.
6347 (mve_vminnmvq_p_f<mode>): Likewise.
6348 (mve_vmlaldavaq_<supf><mode>): Likewise.
6349 (mve_vmlaldavaxq_<supf><mode>): Likewise.
6350 (mve_vmlaldavq_p_<supf><mode>): Likewise.
6351 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
6352 (mve_vmlsldavaq_s<mode>): Likewise.
6353 (mve_vmlsldavaxq_s<mode>): Likewise.
6354 (mve_vmlsldavq_p_s<mode>): Likewise.
6355 (mve_vmlsldavxq_p_s<mode>): Likewise.
6356 (mve_vmovlbq_m_<supf><mode>): Likewise.
6357 (mve_vmovltq_m_<supf><mode>): Likewise.
6358 (mve_vmovnbq_m_<supf><mode>): Likewise.
6359 (mve_vmovntq_m_<supf><mode>): Likewise.
6360 (mve_vmvnq_m_n_<supf><mode>): Likewise.
6361 (mve_vnegq_m_f<mode>): Likewise.
6362 (mve_vorrq_m_n_<supf><mode>): Likewise.
6363 (mve_vpselq_f<mode>): Likewise.
6364 (mve_vqmovnbq_m_<supf><mode>): Likewise.
6365 (mve_vqmovntq_m_<supf><mode>): Likewise.
6366 (mve_vqmovunbq_m_s<mode>): Likewise.
6367 (mve_vqmovuntq_m_s<mode>): Likewise.
6368 (mve_vqrshrntq_n_<supf><mode>): Likewise.
6369 (mve_vqrshruntq_n_s<mode>): Likewise.
6370 (mve_vqshrnbq_n_<supf><mode>): Likewise.
6371 (mve_vqshrntq_n_<supf><mode>): Likewise.
6372 (mve_vqshrunbq_n_s<mode>): Likewise.
6373 (mve_vqshruntq_n_s<mode>): Likewise.
6374 (mve_vrev32q_m_fv8hf): Likewise.
6375 (mve_vrev32q_m_<supf><mode>): Likewise.
6376 (mve_vrev64q_m_f<mode>): Likewise.
6377 (mve_vrmlaldavhaxq_sv4si): Likewise.
6378 (mve_vrmlaldavhxq_p_sv4si): Likewise.
6379 (mve_vrmlsldavhaxq_sv4si): Likewise.
6380 (mve_vrmlsldavhq_p_sv4si): Likewise.
6381 (mve_vrmlsldavhxq_p_sv4si): Likewise.
6382 (mve_vrndaq_m_f<mode>): Likewise.
6383 (mve_vrndmq_m_f<mode>): Likewise.
6384 (mve_vrndnq_m_f<mode>): Likewise.
6385 (mve_vrndpq_m_f<mode>): Likewise.
6386 (mve_vrndxq_m_f<mode>): Likewise.
6387 (mve_vrshrnbq_n_<supf><mode>): Likewise.
6388 (mve_vrshrntq_n_<supf><mode>): Likewise.
6389 (mve_vshrnbq_n_<supf><mode>): Likewise.
6390 (mve_vshrntq_n_<supf><mode>): Likewise.
6391 (mve_vcvtmq_m_<supf><mode>): Likewise.
6392 (mve_vcvtpq_m_<supf><mode>): Likewise.
6393 (mve_vcvtnq_m_<supf><mode>): Likewise.
6394 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
6395 (mve_vrev16q_m_<supf>v16qi): Likewise.
6396 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
6397 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
6398 (mve_vrmlsldavhaq_sv4si): Likewise.
6400 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6401 Mihail Ionescu <mihail.ionescu@arm.com>
6402 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6404 * config/arm/arm_mve.h (vpselq_u8): Define macro.
6405 (vpselq_s8): Likewise.
6406 (vrev64q_m_u8): Likewise.
6407 (vqrdmlashq_n_u8): Likewise.
6408 (vqrdmlahq_n_u8): Likewise.
6409 (vqdmlahq_n_u8): Likewise.
6410 (vmvnq_m_u8): Likewise.
6411 (vmlasq_n_u8): Likewise.
6412 (vmlaq_n_u8): Likewise.
6413 (vmladavq_p_u8): Likewise.
6414 (vmladavaq_u8): Likewise.
6415 (vminvq_p_u8): Likewise.
6416 (vmaxvq_p_u8): Likewise.
6417 (vdupq_m_n_u8): Likewise.
6418 (vcmpneq_m_u8): Likewise.
6419 (vcmpneq_m_n_u8): Likewise.
6420 (vcmphiq_m_u8): Likewise.
6421 (vcmphiq_m_n_u8): Likewise.
6422 (vcmpeqq_m_u8): Likewise.
6423 (vcmpeqq_m_n_u8): Likewise.
6424 (vcmpcsq_m_u8): Likewise.
6425 (vcmpcsq_m_n_u8): Likewise.
6426 (vclzq_m_u8): Likewise.
6427 (vaddvaq_p_u8): Likewise.
6428 (vsriq_n_u8): Likewise.
6429 (vsliq_n_u8): Likewise.
6430 (vshlq_m_r_u8): Likewise.
6431 (vrshlq_m_n_u8): Likewise.
6432 (vqshlq_m_r_u8): Likewise.
6433 (vqrshlq_m_n_u8): Likewise.
6434 (vminavq_p_s8): Likewise.
6435 (vminaq_m_s8): Likewise.
6436 (vmaxavq_p_s8): Likewise.
6437 (vmaxaq_m_s8): Likewise.
6438 (vcmpneq_m_s8): Likewise.
6439 (vcmpneq_m_n_s8): Likewise.
6440 (vcmpltq_m_s8): Likewise.
6441 (vcmpltq_m_n_s8): Likewise.
6442 (vcmpleq_m_s8): Likewise.
6443 (vcmpleq_m_n_s8): Likewise.
6444 (vcmpgtq_m_s8): Likewise.
6445 (vcmpgtq_m_n_s8): Likewise.
6446 (vcmpgeq_m_s8): Likewise.
6447 (vcmpgeq_m_n_s8): Likewise.
6448 (vcmpeqq_m_s8): Likewise.
6449 (vcmpeqq_m_n_s8): Likewise.
6450 (vshlq_m_r_s8): Likewise.
6451 (vrshlq_m_n_s8): Likewise.
6452 (vrev64q_m_s8): Likewise.
6453 (vqshlq_m_r_s8): Likewise.
6454 (vqrshlq_m_n_s8): Likewise.
6455 (vqnegq_m_s8): Likewise.
6456 (vqabsq_m_s8): Likewise.
6457 (vnegq_m_s8): Likewise.
6458 (vmvnq_m_s8): Likewise.
6459 (vmlsdavxq_p_s8): Likewise.
6460 (vmlsdavq_p_s8): Likewise.
6461 (vmladavxq_p_s8): Likewise.
6462 (vmladavq_p_s8): Likewise.
6463 (vminvq_p_s8): Likewise.
6464 (vmaxvq_p_s8): Likewise.
6465 (vdupq_m_n_s8): Likewise.
6466 (vclzq_m_s8): Likewise.
6467 (vclsq_m_s8): Likewise.
6468 (vaddvaq_p_s8): Likewise.
6469 (vabsq_m_s8): Likewise.
6470 (vqrdmlsdhxq_s8): Likewise.
6471 (vqrdmlsdhq_s8): Likewise.
6472 (vqrdmlashq_n_s8): Likewise.
6473 (vqrdmlahq_n_s8): Likewise.
6474 (vqrdmladhxq_s8): Likewise.
6475 (vqrdmladhq_s8): Likewise.
6476 (vqdmlsdhxq_s8): Likewise.
6477 (vqdmlsdhq_s8): Likewise.
6478 (vqdmlahq_n_s8): Likewise.
6479 (vqdmladhxq_s8): Likewise.
6480 (vqdmladhq_s8): Likewise.
6481 (vmlsdavaxq_s8): Likewise.
6482 (vmlsdavaq_s8): Likewise.
6483 (vmlasq_n_s8): Likewise.
6484 (vmlaq_n_s8): Likewise.
6485 (vmladavaxq_s8): Likewise.
6486 (vmladavaq_s8): Likewise.
6487 (vsriq_n_s8): Likewise.
6488 (vsliq_n_s8): Likewise.
6489 (vpselq_u16): Likewise.
6490 (vpselq_s16): Likewise.
6491 (vrev64q_m_u16): Likewise.
6492 (vqrdmlashq_n_u16): Likewise.
6493 (vqrdmlahq_n_u16): Likewise.
6494 (vqdmlahq_n_u16): Likewise.
6495 (vmvnq_m_u16): Likewise.
6496 (vmlasq_n_u16): Likewise.
6497 (vmlaq_n_u16): Likewise.
6498 (vmladavq_p_u16): Likewise.
6499 (vmladavaq_u16): Likewise.
6500 (vminvq_p_u16): Likewise.
6501 (vmaxvq_p_u16): Likewise.
6502 (vdupq_m_n_u16): Likewise.
6503 (vcmpneq_m_u16): Likewise.
6504 (vcmpneq_m_n_u16): Likewise.
6505 (vcmphiq_m_u16): Likewise.
6506 (vcmphiq_m_n_u16): Likewise.
6507 (vcmpeqq_m_u16): Likewise.
6508 (vcmpeqq_m_n_u16): Likewise.
6509 (vcmpcsq_m_u16): Likewise.
6510 (vcmpcsq_m_n_u16): Likewise.
6511 (vclzq_m_u16): Likewise.
6512 (vaddvaq_p_u16): Likewise.
6513 (vsriq_n_u16): Likewise.
6514 (vsliq_n_u16): Likewise.
6515 (vshlq_m_r_u16): Likewise.
6516 (vrshlq_m_n_u16): Likewise.
6517 (vqshlq_m_r_u16): Likewise.
6518 (vqrshlq_m_n_u16): Likewise.
6519 (vminavq_p_s16): Likewise.
6520 (vminaq_m_s16): Likewise.
6521 (vmaxavq_p_s16): Likewise.
6522 (vmaxaq_m_s16): Likewise.
6523 (vcmpneq_m_s16): Likewise.
6524 (vcmpneq_m_n_s16): Likewise.
6525 (vcmpltq_m_s16): Likewise.
6526 (vcmpltq_m_n_s16): Likewise.
6527 (vcmpleq_m_s16): Likewise.
6528 (vcmpleq_m_n_s16): Likewise.
6529 (vcmpgtq_m_s16): Likewise.
6530 (vcmpgtq_m_n_s16): Likewise.
6531 (vcmpgeq_m_s16): Likewise.
6532 (vcmpgeq_m_n_s16): Likewise.
6533 (vcmpeqq_m_s16): Likewise.
6534 (vcmpeqq_m_n_s16): Likewise.
6535 (vshlq_m_r_s16): Likewise.
6536 (vrshlq_m_n_s16): Likewise.
6537 (vrev64q_m_s16): Likewise.
6538 (vqshlq_m_r_s16): Likewise.
6539 (vqrshlq_m_n_s16): Likewise.
6540 (vqnegq_m_s16): Likewise.
6541 (vqabsq_m_s16): Likewise.
6542 (vnegq_m_s16): Likewise.
6543 (vmvnq_m_s16): Likewise.
6544 (vmlsdavxq_p_s16): Likewise.
6545 (vmlsdavq_p_s16): Likewise.
6546 (vmladavxq_p_s16): Likewise.
6547 (vmladavq_p_s16): Likewise.
6548 (vminvq_p_s16): Likewise.
6549 (vmaxvq_p_s16): Likewise.
6550 (vdupq_m_n_s16): Likewise.
6551 (vclzq_m_s16): Likewise.
6552 (vclsq_m_s16): Likewise.
6553 (vaddvaq_p_s16): Likewise.
6554 (vabsq_m_s16): Likewise.
6555 (vqrdmlsdhxq_s16): Likewise.
6556 (vqrdmlsdhq_s16): Likewise.
6557 (vqrdmlashq_n_s16): Likewise.
6558 (vqrdmlahq_n_s16): Likewise.
6559 (vqrdmladhxq_s16): Likewise.
6560 (vqrdmladhq_s16): Likewise.
6561 (vqdmlsdhxq_s16): Likewise.
6562 (vqdmlsdhq_s16): Likewise.
6563 (vqdmlahq_n_s16): Likewise.
6564 (vqdmladhxq_s16): Likewise.
6565 (vqdmladhq_s16): Likewise.
6566 (vmlsdavaxq_s16): Likewise.
6567 (vmlsdavaq_s16): Likewise.
6568 (vmlasq_n_s16): Likewise.
6569 (vmlaq_n_s16): Likewise.
6570 (vmladavaxq_s16): Likewise.
6571 (vmladavaq_s16): Likewise.
6572 (vsriq_n_s16): Likewise.
6573 (vsliq_n_s16): Likewise.
6574 (vpselq_u32): Likewise.
6575 (vpselq_s32): Likewise.
6576 (vrev64q_m_u32): Likewise.
6577 (vqrdmlashq_n_u32): Likewise.
6578 (vqrdmlahq_n_u32): Likewise.
6579 (vqdmlahq_n_u32): Likewise.
6580 (vmvnq_m_u32): Likewise.
6581 (vmlasq_n_u32): Likewise.
6582 (vmlaq_n_u32): Likewise.
6583 (vmladavq_p_u32): Likewise.
6584 (vmladavaq_u32): Likewise.
6585 (vminvq_p_u32): Likewise.
6586 (vmaxvq_p_u32): Likewise.
6587 (vdupq_m_n_u32): Likewise.
6588 (vcmpneq_m_u32): Likewise.
6589 (vcmpneq_m_n_u32): Likewise.
6590 (vcmphiq_m_u32): Likewise.
6591 (vcmphiq_m_n_u32): Likewise.
6592 (vcmpeqq_m_u32): Likewise.
6593 (vcmpeqq_m_n_u32): Likewise.
6594 (vcmpcsq_m_u32): Likewise.
6595 (vcmpcsq_m_n_u32): Likewise.
6596 (vclzq_m_u32): Likewise.
6597 (vaddvaq_p_u32): Likewise.
6598 (vsriq_n_u32): Likewise.
6599 (vsliq_n_u32): Likewise.
6600 (vshlq_m_r_u32): Likewise.
6601 (vrshlq_m_n_u32): Likewise.
6602 (vqshlq_m_r_u32): Likewise.
6603 (vqrshlq_m_n_u32): Likewise.
6604 (vminavq_p_s32): Likewise.
6605 (vminaq_m_s32): Likewise.
6606 (vmaxavq_p_s32): Likewise.
6607 (vmaxaq_m_s32): Likewise.
6608 (vcmpneq_m_s32): Likewise.
6609 (vcmpneq_m_n_s32): Likewise.
6610 (vcmpltq_m_s32): Likewise.
6611 (vcmpltq_m_n_s32): Likewise.
6612 (vcmpleq_m_s32): Likewise.
6613 (vcmpleq_m_n_s32): Likewise.
6614 (vcmpgtq_m_s32): Likewise.
6615 (vcmpgtq_m_n_s32): Likewise.
6616 (vcmpgeq_m_s32): Likewise.
6617 (vcmpgeq_m_n_s32): Likewise.
6618 (vcmpeqq_m_s32): Likewise.
6619 (vcmpeqq_m_n_s32): Likewise.
6620 (vshlq_m_r_s32): Likewise.
6621 (vrshlq_m_n_s32): Likewise.
6622 (vrev64q_m_s32): Likewise.
6623 (vqshlq_m_r_s32): Likewise.
6624 (vqrshlq_m_n_s32): Likewise.
6625 (vqnegq_m_s32): Likewise.
6626 (vqabsq_m_s32): Likewise.
6627 (vnegq_m_s32): Likewise.
6628 (vmvnq_m_s32): Likewise.
6629 (vmlsdavxq_p_s32): Likewise.
6630 (vmlsdavq_p_s32): Likewise.
6631 (vmladavxq_p_s32): Likewise.
6632 (vmladavq_p_s32): Likewise.
6633 (vminvq_p_s32): Likewise.
6634 (vmaxvq_p_s32): Likewise.
6635 (vdupq_m_n_s32): Likewise.
6636 (vclzq_m_s32): Likewise.
6637 (vclsq_m_s32): Likewise.
6638 (vaddvaq_p_s32): Likewise.
6639 (vabsq_m_s32): Likewise.
6640 (vqrdmlsdhxq_s32): Likewise.
6641 (vqrdmlsdhq_s32): Likewise.
6642 (vqrdmlashq_n_s32): Likewise.
6643 (vqrdmlahq_n_s32): Likewise.
6644 (vqrdmladhxq_s32): Likewise.
6645 (vqrdmladhq_s32): Likewise.
6646 (vqdmlsdhxq_s32): Likewise.
6647 (vqdmlsdhq_s32): Likewise.
6648 (vqdmlahq_n_s32): Likewise.
6649 (vqdmladhxq_s32): Likewise.
6650 (vqdmladhq_s32): Likewise.
6651 (vmlsdavaxq_s32): Likewise.
6652 (vmlsdavaq_s32): Likewise.
6653 (vmlasq_n_s32): Likewise.
6654 (vmlaq_n_s32): Likewise.
6655 (vmladavaxq_s32): Likewise.
6656 (vmladavaq_s32): Likewise.
6657 (vsriq_n_s32): Likewise.
6658 (vsliq_n_s32): Likewise.
6659 (vpselq_u64): Likewise.
6660 (vpselq_s64): Likewise.
6661 (__arm_vpselq_u8): Define intrinsic.
6662 (__arm_vpselq_s8): Likewise.
6663 (__arm_vrev64q_m_u8): Likewise.
6664 (__arm_vqrdmlashq_n_u8): Likewise.
6665 (__arm_vqrdmlahq_n_u8): Likewise.
6666 (__arm_vqdmlahq_n_u8): Likewise.
6667 (__arm_vmvnq_m_u8): Likewise.
6668 (__arm_vmlasq_n_u8): Likewise.
6669 (__arm_vmlaq_n_u8): Likewise.
6670 (__arm_vmladavq_p_u8): Likewise.
6671 (__arm_vmladavaq_u8): Likewise.
6672 (__arm_vminvq_p_u8): Likewise.
6673 (__arm_vmaxvq_p_u8): Likewise.
6674 (__arm_vdupq_m_n_u8): Likewise.
6675 (__arm_vcmpneq_m_u8): Likewise.
6676 (__arm_vcmpneq_m_n_u8): Likewise.
6677 (__arm_vcmphiq_m_u8): Likewise.
6678 (__arm_vcmphiq_m_n_u8): Likewise.
6679 (__arm_vcmpeqq_m_u8): Likewise.
6680 (__arm_vcmpeqq_m_n_u8): Likewise.
6681 (__arm_vcmpcsq_m_u8): Likewise.
6682 (__arm_vcmpcsq_m_n_u8): Likewise.
6683 (__arm_vclzq_m_u8): Likewise.
6684 (__arm_vaddvaq_p_u8): Likewise.
6685 (__arm_vsriq_n_u8): Likewise.
6686 (__arm_vsliq_n_u8): Likewise.
6687 (__arm_vshlq_m_r_u8): Likewise.
6688 (__arm_vrshlq_m_n_u8): Likewise.
6689 (__arm_vqshlq_m_r_u8): Likewise.
6690 (__arm_vqrshlq_m_n_u8): Likewise.
6691 (__arm_vminavq_p_s8): Likewise.
6692 (__arm_vminaq_m_s8): Likewise.
6693 (__arm_vmaxavq_p_s8): Likewise.
6694 (__arm_vmaxaq_m_s8): Likewise.
6695 (__arm_vcmpneq_m_s8): Likewise.
6696 (__arm_vcmpneq_m_n_s8): Likewise.
6697 (__arm_vcmpltq_m_s8): Likewise.
6698 (__arm_vcmpltq_m_n_s8): Likewise.
6699 (__arm_vcmpleq_m_s8): Likewise.
6700 (__arm_vcmpleq_m_n_s8): Likewise.
6701 (__arm_vcmpgtq_m_s8): Likewise.
6702 (__arm_vcmpgtq_m_n_s8): Likewise.
6703 (__arm_vcmpgeq_m_s8): Likewise.
6704 (__arm_vcmpgeq_m_n_s8): Likewise.
6705 (__arm_vcmpeqq_m_s8): Likewise.
6706 (__arm_vcmpeqq_m_n_s8): Likewise.
6707 (__arm_vshlq_m_r_s8): Likewise.
6708 (__arm_vrshlq_m_n_s8): Likewise.
6709 (__arm_vrev64q_m_s8): Likewise.
6710 (__arm_vqshlq_m_r_s8): Likewise.
6711 (__arm_vqrshlq_m_n_s8): Likewise.
6712 (__arm_vqnegq_m_s8): Likewise.
6713 (__arm_vqabsq_m_s8): Likewise.
6714 (__arm_vnegq_m_s8): Likewise.
6715 (__arm_vmvnq_m_s8): Likewise.
6716 (__arm_vmlsdavxq_p_s8): Likewise.
6717 (__arm_vmlsdavq_p_s8): Likewise.
6718 (__arm_vmladavxq_p_s8): Likewise.
6719 (__arm_vmladavq_p_s8): Likewise.
6720 (__arm_vminvq_p_s8): Likewise.
6721 (__arm_vmaxvq_p_s8): Likewise.
6722 (__arm_vdupq_m_n_s8): Likewise.
6723 (__arm_vclzq_m_s8): Likewise.
6724 (__arm_vclsq_m_s8): Likewise.
6725 (__arm_vaddvaq_p_s8): Likewise.
6726 (__arm_vabsq_m_s8): Likewise.
6727 (__arm_vqrdmlsdhxq_s8): Likewise.
6728 (__arm_vqrdmlsdhq_s8): Likewise.
6729 (__arm_vqrdmlashq_n_s8): Likewise.
6730 (__arm_vqrdmlahq_n_s8): Likewise.
6731 (__arm_vqrdmladhxq_s8): Likewise.
6732 (__arm_vqrdmladhq_s8): Likewise.
6733 (__arm_vqdmlsdhxq_s8): Likewise.
6734 (__arm_vqdmlsdhq_s8): Likewise.
6735 (__arm_vqdmlahq_n_s8): Likewise.
6736 (__arm_vqdmladhxq_s8): Likewise.
6737 (__arm_vqdmladhq_s8): Likewise.
6738 (__arm_vmlsdavaxq_s8): Likewise.
6739 (__arm_vmlsdavaq_s8): Likewise.
6740 (__arm_vmlasq_n_s8): Likewise.
6741 (__arm_vmlaq_n_s8): Likewise.
6742 (__arm_vmladavaxq_s8): Likewise.
6743 (__arm_vmladavaq_s8): Likewise.
6744 (__arm_vsriq_n_s8): Likewise.
6745 (__arm_vsliq_n_s8): Likewise.
6746 (__arm_vpselq_u16): Likewise.
6747 (__arm_vpselq_s16): Likewise.
6748 (__arm_vrev64q_m_u16): Likewise.
6749 (__arm_vqrdmlashq_n_u16): Likewise.
6750 (__arm_vqrdmlahq_n_u16): Likewise.
6751 (__arm_vqdmlahq_n_u16): Likewise.
6752 (__arm_vmvnq_m_u16): Likewise.
6753 (__arm_vmlasq_n_u16): Likewise.
6754 (__arm_vmlaq_n_u16): Likewise.
6755 (__arm_vmladavq_p_u16): Likewise.
6756 (__arm_vmladavaq_u16): Likewise.
6757 (__arm_vminvq_p_u16): Likewise.
6758 (__arm_vmaxvq_p_u16): Likewise.
6759 (__arm_vdupq_m_n_u16): Likewise.
6760 (__arm_vcmpneq_m_u16): Likewise.
6761 (__arm_vcmpneq_m_n_u16): Likewise.
6762 (__arm_vcmphiq_m_u16): Likewise.
6763 (__arm_vcmphiq_m_n_u16): Likewise.
6764 (__arm_vcmpeqq_m_u16): Likewise.
6765 (__arm_vcmpeqq_m_n_u16): Likewise.
6766 (__arm_vcmpcsq_m_u16): Likewise.
6767 (__arm_vcmpcsq_m_n_u16): Likewise.
6768 (__arm_vclzq_m_u16): Likewise.
6769 (__arm_vaddvaq_p_u16): Likewise.
6770 (__arm_vsriq_n_u16): Likewise.
6771 (__arm_vsliq_n_u16): Likewise.
6772 (__arm_vshlq_m_r_u16): Likewise.
6773 (__arm_vrshlq_m_n_u16): Likewise.
6774 (__arm_vqshlq_m_r_u16): Likewise.
6775 (__arm_vqrshlq_m_n_u16): Likewise.
6776 (__arm_vminavq_p_s16): Likewise.
6777 (__arm_vminaq_m_s16): Likewise.
6778 (__arm_vmaxavq_p_s16): Likewise.
6779 (__arm_vmaxaq_m_s16): Likewise.
6780 (__arm_vcmpneq_m_s16): Likewise.
6781 (__arm_vcmpneq_m_n_s16): Likewise.
6782 (__arm_vcmpltq_m_s16): Likewise.
6783 (__arm_vcmpltq_m_n_s16): Likewise.
6784 (__arm_vcmpleq_m_s16): Likewise.
6785 (__arm_vcmpleq_m_n_s16): Likewise.
6786 (__arm_vcmpgtq_m_s16): Likewise.
6787 (__arm_vcmpgtq_m_n_s16): Likewise.
6788 (__arm_vcmpgeq_m_s16): Likewise.
6789 (__arm_vcmpgeq_m_n_s16): Likewise.
6790 (__arm_vcmpeqq_m_s16): Likewise.
6791 (__arm_vcmpeqq_m_n_s16): Likewise.
6792 (__arm_vshlq_m_r_s16): Likewise.
6793 (__arm_vrshlq_m_n_s16): Likewise.
6794 (__arm_vrev64q_m_s16): Likewise.
6795 (__arm_vqshlq_m_r_s16): Likewise.
6796 (__arm_vqrshlq_m_n_s16): Likewise.
6797 (__arm_vqnegq_m_s16): Likewise.
6798 (__arm_vqabsq_m_s16): Likewise.
6799 (__arm_vnegq_m_s16): Likewise.
6800 (__arm_vmvnq_m_s16): Likewise.
6801 (__arm_vmlsdavxq_p_s16): Likewise.
6802 (__arm_vmlsdavq_p_s16): Likewise.
6803 (__arm_vmladavxq_p_s16): Likewise.
6804 (__arm_vmladavq_p_s16): Likewise.
6805 (__arm_vminvq_p_s16): Likewise.
6806 (__arm_vmaxvq_p_s16): Likewise.
6807 (__arm_vdupq_m_n_s16): Likewise.
6808 (__arm_vclzq_m_s16): Likewise.
6809 (__arm_vclsq_m_s16): Likewise.
6810 (__arm_vaddvaq_p_s16): Likewise.
6811 (__arm_vabsq_m_s16): Likewise.
6812 (__arm_vqrdmlsdhxq_s16): Likewise.
6813 (__arm_vqrdmlsdhq_s16): Likewise.
6814 (__arm_vqrdmlashq_n_s16): Likewise.
6815 (__arm_vqrdmlahq_n_s16): Likewise.
6816 (__arm_vqrdmladhxq_s16): Likewise.
6817 (__arm_vqrdmladhq_s16): Likewise.
6818 (__arm_vqdmlsdhxq_s16): Likewise.
6819 (__arm_vqdmlsdhq_s16): Likewise.
6820 (__arm_vqdmlahq_n_s16): Likewise.
6821 (__arm_vqdmladhxq_s16): Likewise.
6822 (__arm_vqdmladhq_s16): Likewise.
6823 (__arm_vmlsdavaxq_s16): Likewise.
6824 (__arm_vmlsdavaq_s16): Likewise.
6825 (__arm_vmlasq_n_s16): Likewise.
6826 (__arm_vmlaq_n_s16): Likewise.
6827 (__arm_vmladavaxq_s16): Likewise.
6828 (__arm_vmladavaq_s16): Likewise.
6829 (__arm_vsriq_n_s16): Likewise.
6830 (__arm_vsliq_n_s16): Likewise.
6831 (__arm_vpselq_u32): Likewise.
6832 (__arm_vpselq_s32): Likewise.
6833 (__arm_vrev64q_m_u32): Likewise.
6834 (__arm_vqrdmlashq_n_u32): Likewise.
6835 (__arm_vqrdmlahq_n_u32): Likewise.
6836 (__arm_vqdmlahq_n_u32): Likewise.
6837 (__arm_vmvnq_m_u32): Likewise.
6838 (__arm_vmlasq_n_u32): Likewise.
6839 (__arm_vmlaq_n_u32): Likewise.
6840 (__arm_vmladavq_p_u32): Likewise.
6841 (__arm_vmladavaq_u32): Likewise.
6842 (__arm_vminvq_p_u32): Likewise.
6843 (__arm_vmaxvq_p_u32): Likewise.
6844 (__arm_vdupq_m_n_u32): Likewise.
6845 (__arm_vcmpneq_m_u32): Likewise.
6846 (__arm_vcmpneq_m_n_u32): Likewise.
6847 (__arm_vcmphiq_m_u32): Likewise.
6848 (__arm_vcmphiq_m_n_u32): Likewise.
6849 (__arm_vcmpeqq_m_u32): Likewise.
6850 (__arm_vcmpeqq_m_n_u32): Likewise.
6851 (__arm_vcmpcsq_m_u32): Likewise.
6852 (__arm_vcmpcsq_m_n_u32): Likewise.
6853 (__arm_vclzq_m_u32): Likewise.
6854 (__arm_vaddvaq_p_u32): Likewise.
6855 (__arm_vsriq_n_u32): Likewise.
6856 (__arm_vsliq_n_u32): Likewise.
6857 (__arm_vshlq_m_r_u32): Likewise.
6858 (__arm_vrshlq_m_n_u32): Likewise.
6859 (__arm_vqshlq_m_r_u32): Likewise.
6860 (__arm_vqrshlq_m_n_u32): Likewise.
6861 (__arm_vminavq_p_s32): Likewise.
6862 (__arm_vminaq_m_s32): Likewise.
6863 (__arm_vmaxavq_p_s32): Likewise.
6864 (__arm_vmaxaq_m_s32): Likewise.
6865 (__arm_vcmpneq_m_s32): Likewise.
6866 (__arm_vcmpneq_m_n_s32): Likewise.
6867 (__arm_vcmpltq_m_s32): Likewise.
6868 (__arm_vcmpltq_m_n_s32): Likewise.
6869 (__arm_vcmpleq_m_s32): Likewise.
6870 (__arm_vcmpleq_m_n_s32): Likewise.
6871 (__arm_vcmpgtq_m_s32): Likewise.
6872 (__arm_vcmpgtq_m_n_s32): Likewise.
6873 (__arm_vcmpgeq_m_s32): Likewise.
6874 (__arm_vcmpgeq_m_n_s32): Likewise.
6875 (__arm_vcmpeqq_m_s32): Likewise.
6876 (__arm_vcmpeqq_m_n_s32): Likewise.
6877 (__arm_vshlq_m_r_s32): Likewise.
6878 (__arm_vrshlq_m_n_s32): Likewise.
6879 (__arm_vrev64q_m_s32): Likewise.
6880 (__arm_vqshlq_m_r_s32): Likewise.
6881 (__arm_vqrshlq_m_n_s32): Likewise.
6882 (__arm_vqnegq_m_s32): Likewise.
6883 (__arm_vqabsq_m_s32): Likewise.
6884 (__arm_vnegq_m_s32): Likewise.
6885 (__arm_vmvnq_m_s32): Likewise.
6886 (__arm_vmlsdavxq_p_s32): Likewise.
6887 (__arm_vmlsdavq_p_s32): Likewise.
6888 (__arm_vmladavxq_p_s32): Likewise.
6889 (__arm_vmladavq_p_s32): Likewise.
6890 (__arm_vminvq_p_s32): Likewise.
6891 (__arm_vmaxvq_p_s32): Likewise.
6892 (__arm_vdupq_m_n_s32): Likewise.
6893 (__arm_vclzq_m_s32): Likewise.
6894 (__arm_vclsq_m_s32): Likewise.
6895 (__arm_vaddvaq_p_s32): Likewise.
6896 (__arm_vabsq_m_s32): Likewise.
6897 (__arm_vqrdmlsdhxq_s32): Likewise.
6898 (__arm_vqrdmlsdhq_s32): Likewise.
6899 (__arm_vqrdmlashq_n_s32): Likewise.
6900 (__arm_vqrdmlahq_n_s32): Likewise.
6901 (__arm_vqrdmladhxq_s32): Likewise.
6902 (__arm_vqrdmladhq_s32): Likewise.
6903 (__arm_vqdmlsdhxq_s32): Likewise.
6904 (__arm_vqdmlsdhq_s32): Likewise.
6905 (__arm_vqdmlahq_n_s32): Likewise.
6906 (__arm_vqdmladhxq_s32): Likewise.
6907 (__arm_vqdmladhq_s32): Likewise.
6908 (__arm_vmlsdavaxq_s32): Likewise.
6909 (__arm_vmlsdavaq_s32): Likewise.
6910 (__arm_vmlasq_n_s32): Likewise.
6911 (__arm_vmlaq_n_s32): Likewise.
6912 (__arm_vmladavaxq_s32): Likewise.
6913 (__arm_vmladavaq_s32): Likewise.
6914 (__arm_vsriq_n_s32): Likewise.
6915 (__arm_vsliq_n_s32): Likewise.
6916 (__arm_vpselq_u64): Likewise.
6917 (__arm_vpselq_s64): Likewise.
6918 (vcmpneq_m_n): Define polymorphic variant.
6919 (vcmpneq_m): Likewise.
6920 (vqrdmlsdhq): Likewise.
6921 (vqrdmlsdhxq): Likewise.
6922 (vqrshlq_m_n): Likewise.
6923 (vqshlq_m_r): Likewise.
6924 (vrev64q_m): Likewise.
6925 (vrshlq_m_n): Likewise.
6926 (vshlq_m_r): Likewise.
6927 (vsliq_n): Likewise.
6928 (vsriq_n): Likewise.
6929 (vqrdmlashq_n): Likewise.
6930 (vqrdmlahq): Likewise.
6931 (vqrdmladhxq): Likewise.
6932 (vqrdmladhq): Likewise.
6933 (vqnegq_m): Likewise.
6934 (vqdmlsdhxq): Likewise.
6935 (vabsq_m): Likewise.
6936 (vclsq_m): Likewise.
6937 (vclzq_m): Likewise.
6938 (vcmpgeq_m): Likewise.
6939 (vcmpgeq_m_n): Likewise.
6940 (vdupq_m_n): Likewise.
6941 (vmaxaq_m): Likewise.
6942 (vmlaq_n): Likewise.
6943 (vmlasq_n): Likewise.
6944 (vmvnq_m): Likewise.
6945 (vnegq_m): Likewise.
6947 (vqdmlahq_n): Likewise.
6948 (vqrdmlahq_n): Likewise.
6949 (vqdmlsdhq): Likewise.
6950 (vqdmladhq): Likewise.
6951 (vqabsq_m): Likewise.
6952 (vminaq_m): Likewise.
6953 (vrmlaldavhaq): Likewise.
6954 (vmlsdavxq_p): Likewise.
6955 (vmlsdavq_p): Likewise.
6956 (vmlsdavaxq): Likewise.
6957 (vmlsdavaq): Likewise.
6958 (vaddvaq_p): Likewise.
6959 (vcmpcsq_m_n): Likewise.
6960 (vcmpcsq_m): Likewise.
6961 (vcmpeqq_m_n): Likewise.
6962 (vcmpeqq_m): Likewise.
6963 (vmladavxq_p): Likewise.
6964 (vmladavq_p): Likewise.
6965 (vmladavaxq): Likewise.
6966 (vmladavaq): Likewise.
6967 (vminvq_p): Likewise.
6968 (vminavq_p): Likewise.
6969 (vmaxvq_p): Likewise.
6970 (vmaxavq_p): Likewise.
6971 (vcmpltq_m_n): Likewise.
6972 (vcmpltq_m): Likewise.
6973 (vcmpleq_m): Likewise.
6974 (vcmpleq_m_n): Likewise.
6975 (vcmphiq_m_n): Likewise.
6976 (vcmphiq_m): Likewise.
6977 (vcmpgtq_m_n): Likewise.
6978 (vcmpgtq_m): Likewise.
6979 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
6981 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
6982 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
6983 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
6984 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
6985 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
6986 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
6987 * config/arm/constraints.md (Rc): Define constraint to check constant is
6988 in the range of 0 to 15.
6989 (Re): Define constraint to check constant is in the range of 0 to 31.
6990 * config/arm/mve.md (VADDVAQ_P): Define iterator.
6991 (VCLZQ_M): Likewise.
6992 (VCMPEQQ_M_N): Likewise.
6993 (VCMPEQQ_M): Likewise.
6994 (VCMPNEQ_M_N): Likewise.
6995 (VCMPNEQ_M): Likewise.
6996 (VDUPQ_M_N): Likewise.
6997 (VMAXVQ_P): Likewise.
6998 (VMINVQ_P): Likewise.
6999 (VMLADAVAQ): Likewise.
7000 (VMLADAVQ_P): Likewise.
7001 (VMLAQ_N): Likewise.
7002 (VMLASQ_N): Likewise.
7003 (VMVNQ_M): Likewise.
7005 (VQDMLAHQ_N): Likewise.
7006 (VQRDMLAHQ_N): Likewise.
7007 (VQRDMLASHQ_N): Likewise.
7008 (VQRSHLQ_M_N): Likewise.
7009 (VQSHLQ_M_R): Likewise.
7010 (VREV64Q_M): Likewise.
7011 (VRSHLQ_M_N): Likewise.
7012 (VSHLQ_M_R): Likewise.
7013 (VSLIQ_N): Likewise.
7014 (VSRIQ_N): Likewise.
7015 (mve_vabsq_m_s<mode>): Define RTL pattern.
7016 (mve_vaddvaq_p_<supf><mode>): Likewise.
7017 (mve_vclsq_m_s<mode>): Likewise.
7018 (mve_vclzq_m_<supf><mode>): Likewise.
7019 (mve_vcmpcsq_m_n_u<mode>): Likewise.
7020 (mve_vcmpcsq_m_u<mode>): Likewise.
7021 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
7022 (mve_vcmpeqq_m_<supf><mode>): Likewise.
7023 (mve_vcmpgeq_m_n_s<mode>): Likewise.
7024 (mve_vcmpgeq_m_s<mode>): Likewise.
7025 (mve_vcmpgtq_m_n_s<mode>): Likewise.
7026 (mve_vcmpgtq_m_s<mode>): Likewise.
7027 (mve_vcmphiq_m_n_u<mode>): Likewise.
7028 (mve_vcmphiq_m_u<mode>): Likewise.
7029 (mve_vcmpleq_m_n_s<mode>): Likewise.
7030 (mve_vcmpleq_m_s<mode>): Likewise.
7031 (mve_vcmpltq_m_n_s<mode>): Likewise.
7032 (mve_vcmpltq_m_s<mode>): Likewise.
7033 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
7034 (mve_vcmpneq_m_<supf><mode>): Likewise.
7035 (mve_vdupq_m_n_<supf><mode>): Likewise.
7036 (mve_vmaxaq_m_s<mode>): Likewise.
7037 (mve_vmaxavq_p_s<mode>): Likewise.
7038 (mve_vmaxvq_p_<supf><mode>): Likewise.
7039 (mve_vminaq_m_s<mode>): Likewise.
7040 (mve_vminavq_p_s<mode>): Likewise.
7041 (mve_vminvq_p_<supf><mode>): Likewise.
7042 (mve_vmladavaq_<supf><mode>): Likewise.
7043 (mve_vmladavq_p_<supf><mode>): Likewise.
7044 (mve_vmladavxq_p_s<mode>): Likewise.
7045 (mve_vmlaq_n_<supf><mode>): Likewise.
7046 (mve_vmlasq_n_<supf><mode>): Likewise.
7047 (mve_vmlsdavq_p_s<mode>): Likewise.
7048 (mve_vmlsdavxq_p_s<mode>): Likewise.
7049 (mve_vmvnq_m_<supf><mode>): Likewise.
7050 (mve_vnegq_m_s<mode>): Likewise.
7051 (mve_vpselq_<supf><mode>): Likewise.
7052 (mve_vqabsq_m_s<mode>): Likewise.
7053 (mve_vqdmlahq_n_<supf><mode>): Likewise.
7054 (mve_vqnegq_m_s<mode>): Likewise.
7055 (mve_vqrdmladhq_s<mode>): Likewise.
7056 (mve_vqrdmladhxq_s<mode>): Likewise.
7057 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
7058 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
7059 (mve_vqrdmlsdhq_s<mode>): Likewise.
7060 (mve_vqrdmlsdhxq_s<mode>): Likewise.
7061 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
7062 (mve_vqshlq_m_r_<supf><mode>): Likewise.
7063 (mve_vrev64q_m_<supf><mode>): Likewise.
7064 (mve_vrshlq_m_n_<supf><mode>): Likewise.
7065 (mve_vshlq_m_r_<supf><mode>): Likewise.
7066 (mve_vsliq_n_<supf><mode>): Likewise.
7067 (mve_vsriq_n_<supf><mode>): Likewise.
7068 (mve_vqdmlsdhxq_s<mode>): Likewise.
7069 (mve_vqdmlsdhq_s<mode>): Likewise.
7070 (mve_vqdmladhxq_s<mode>): Likewise.
7071 (mve_vqdmladhq_s<mode>): Likewise.
7072 (mve_vmlsdavaxq_s<mode>): Likewise.
7073 (mve_vmlsdavaq_s<mode>): Likewise.
7074 (mve_vmladavaxq_s<mode>): Likewise.
7075 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
7076 matching constraint Rc.
7077 (mve_imm_31): Define predicate to check the matching constraint Re.
7079 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
7081 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
7082 (vec_cmp<mode>di_dup): Likewise.
7083 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
7085 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
7087 * config/gcn/gcn-valu.md (COND_MODE): Delete.
7088 (COND_INT_MODE): Delete.
7089 (cond_op): Add "mult".
7090 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
7091 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
7093 2020-03-18 Richard Biener <rguenther@suse.de>
7096 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
7097 partial int modes or not mode-precision integer types for
7100 2020-03-18 Jakub Jelinek <jakub@redhat.com>
7102 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
7104 * config/arc/arc.c (frame_stack_add): Likewise.
7105 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
7107 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
7108 * tree-ssa-strlen.h (handle_printf_call): Likewise.
7109 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
7110 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
7112 2020-03-18 Duan bo <duanbo3@huawei.com>
7115 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
7116 (@ldr_got_tiny_<mode>): New pattern.
7117 (ldr_got_tiny_sidi): Likewise.
7118 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
7119 them to handle SYMBOL_TINY_GOT for ILP32.
7121 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
7123 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
7124 call-preserved for SVE PCS functions.
7125 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
7126 Optimize the case in which there are no following vector save slots.
7128 2020-03-18 Richard Biener <rguenther@suse.de>
7131 * fold-const.c (build_fold_addr_expr): Convert address to
7133 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
7134 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
7135 to build the ADDR_EXPR which we don't really want to simplify.
7136 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
7137 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
7138 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
7139 (simplify_builtin_call): Strip useless type conversions.
7140 * tree-ssa-strlen.c (new_strinfo): Likewise.
7142 2020-03-17 Alexey Neyman <stilor@att.net>
7145 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
7146 the debug level is terse and the declaration is public. Do not
7148 (dwarf2out_decl): Same.
7149 (add_type_attribute): Return immediately if debug level is
7152 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
7154 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
7156 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
7157 Mihail Ionescu <mihail.ionescu@arm.com>
7158 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7160 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
7161 Define qualifier for ternary operands.
7162 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
7163 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7164 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7165 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
7166 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
7167 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7168 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7169 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
7170 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7171 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7172 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
7173 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
7174 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
7175 * config/arm/arm_mve.h (vabavq_s8): Define macro.
7176 (vabavq_s16): Likewise.
7177 (vabavq_s32): Likewise.
7178 (vbicq_m_n_s16): Likewise.
7179 (vbicq_m_n_s32): Likewise.
7180 (vbicq_m_n_u16): Likewise.
7181 (vbicq_m_n_u32): Likewise.
7182 (vcmpeqq_m_f16): Likewise.
7183 (vcmpeqq_m_f32): Likewise.
7184 (vcvtaq_m_s16_f16): Likewise.
7185 (vcvtaq_m_u16_f16): Likewise.
7186 (vcvtaq_m_s32_f32): Likewise.
7187 (vcvtaq_m_u32_f32): Likewise.
7188 (vcvtq_m_f16_s16): Likewise.
7189 (vcvtq_m_f16_u16): Likewise.
7190 (vcvtq_m_f32_s32): Likewise.
7191 (vcvtq_m_f32_u32): Likewise.
7192 (vqrshrnbq_n_s16): Likewise.
7193 (vqrshrnbq_n_u16): Likewise.
7194 (vqrshrnbq_n_s32): Likewise.
7195 (vqrshrnbq_n_u32): Likewise.
7196 (vqrshrunbq_n_s16): Likewise.
7197 (vqrshrunbq_n_s32): Likewise.
7198 (vrmlaldavhaq_s32): Likewise.
7199 (vrmlaldavhaq_u32): Likewise.
7200 (vshlcq_s8): Likewise.
7201 (vshlcq_u8): Likewise.
7202 (vshlcq_s16): Likewise.
7203 (vshlcq_u16): Likewise.
7204 (vshlcq_s32): Likewise.
7205 (vshlcq_u32): Likewise.
7206 (vabavq_u8): Likewise.
7207 (vabavq_u16): Likewise.
7208 (vabavq_u32): Likewise.
7209 (__arm_vabavq_s8): Define intrinsic.
7210 (__arm_vabavq_s16): Likewise.
7211 (__arm_vabavq_s32): Likewise.
7212 (__arm_vabavq_u8): Likewise.
7213 (__arm_vabavq_u16): Likewise.
7214 (__arm_vabavq_u32): Likewise.
7215 (__arm_vbicq_m_n_s16): Likewise.
7216 (__arm_vbicq_m_n_s32): Likewise.
7217 (__arm_vbicq_m_n_u16): Likewise.
7218 (__arm_vbicq_m_n_u32): Likewise.
7219 (__arm_vqrshrnbq_n_s16): Likewise.
7220 (__arm_vqrshrnbq_n_u16): Likewise.
7221 (__arm_vqrshrnbq_n_s32): Likewise.
7222 (__arm_vqrshrnbq_n_u32): Likewise.
7223 (__arm_vqrshrunbq_n_s16): Likewise.
7224 (__arm_vqrshrunbq_n_s32): Likewise.
7225 (__arm_vrmlaldavhaq_s32): Likewise.
7226 (__arm_vrmlaldavhaq_u32): Likewise.
7227 (__arm_vshlcq_s8): Likewise.
7228 (__arm_vshlcq_u8): Likewise.
7229 (__arm_vshlcq_s16): Likewise.
7230 (__arm_vshlcq_u16): Likewise.
7231 (__arm_vshlcq_s32): Likewise.
7232 (__arm_vshlcq_u32): Likewise.
7233 (__arm_vcmpeqq_m_f16): Likewise.
7234 (__arm_vcmpeqq_m_f32): Likewise.
7235 (__arm_vcvtaq_m_s16_f16): Likewise.
7236 (__arm_vcvtaq_m_u16_f16): Likewise.
7237 (__arm_vcvtaq_m_s32_f32): Likewise.
7238 (__arm_vcvtaq_m_u32_f32): Likewise.
7239 (__arm_vcvtq_m_f16_s16): Likewise.
7240 (__arm_vcvtq_m_f16_u16): Likewise.
7241 (__arm_vcvtq_m_f32_s32): Likewise.
7242 (__arm_vcvtq_m_f32_u32): Likewise.
7243 (vcvtaq_m): Define polymorphic variant.
7244 (vcvtq_m): Likewise.
7247 (vbicq_m_n): Likewise.
7248 (vqrshrnbq_n): Likewise.
7249 (vqrshrunbq_n): Likewise.
7250 * config/arm/arm_mve_builtins.def
7251 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
7252 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
7253 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7254 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7255 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
7256 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
7257 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7258 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7259 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
7260 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7261 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7262 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
7263 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
7264 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
7265 * config/arm/mve.md (VBICQ_M_N): Define iterator.
7266 (VCVTAQ_M): Likewise.
7267 (VCVTQ_M_TO_F): Likewise.
7268 (VQRSHRNBQ_N): Likewise.
7271 (VRMLALDAVHAQ): Likewise.
7272 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
7273 (mve_vcmpeqq_m_f<mode>): Likewise.
7274 (mve_vcvtaq_m_<supf><mode>): Likewise.
7275 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
7276 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
7277 (mve_vqrshrunbq_n_s<mode>): Likewise.
7278 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
7279 (mve_vabavq_<supf><mode>): Likewise.
7280 (mve_vshlcq_<supf><mode>): Likewise.
7281 (mve_vshlcq_<supf><mode>): Likewise.
7282 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
7283 (mve_vshlcq_carry_<supf><mode>): Likewise.
7285 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
7286 Mihail Ionescu <mihail.ionescu@arm.com>
7287 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7289 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
7290 (vqmovnbq_u16): Likewise.
7291 (vmulltq_poly_p8): Likewise.
7292 (vmullbq_poly_p8): Likewise.
7293 (vmovntq_u16): Likewise.
7294 (vmovnbq_u16): Likewise.
7295 (vmlaldavxq_u16): Likewise.
7296 (vmlaldavq_u16): Likewise.
7297 (vqmovuntq_s16): Likewise.
7298 (vqmovunbq_s16): Likewise.
7299 (vshlltq_n_u8): Likewise.
7300 (vshllbq_n_u8): Likewise.
7301 (vorrq_n_u16): Likewise.
7302 (vbicq_n_u16): Likewise.
7303 (vcmpneq_n_f16): Likewise.
7304 (vcmpneq_f16): Likewise.
7305 (vcmpltq_n_f16): Likewise.
7306 (vcmpltq_f16): Likewise.
7307 (vcmpleq_n_f16): Likewise.
7308 (vcmpleq_f16): Likewise.
7309 (vcmpgtq_n_f16): Likewise.
7310 (vcmpgtq_f16): Likewise.
7311 (vcmpgeq_n_f16): Likewise.
7312 (vcmpgeq_f16): Likewise.
7313 (vcmpeqq_n_f16): Likewise.
7314 (vcmpeqq_f16): Likewise.
7315 (vsubq_f16): Likewise.
7316 (vqmovntq_s16): Likewise.
7317 (vqmovnbq_s16): Likewise.
7318 (vqdmulltq_s16): Likewise.
7319 (vqdmulltq_n_s16): Likewise.
7320 (vqdmullbq_s16): Likewise.
7321 (vqdmullbq_n_s16): Likewise.
7322 (vorrq_f16): Likewise.
7323 (vornq_f16): Likewise.
7324 (vmulq_n_f16): Likewise.
7325 (vmulq_f16): Likewise.
7326 (vmovntq_s16): Likewise.
7327 (vmovnbq_s16): Likewise.
7328 (vmlsldavxq_s16): Likewise.
7329 (vmlsldavq_s16): Likewise.
7330 (vmlaldavxq_s16): Likewise.
7331 (vmlaldavq_s16): Likewise.
7332 (vminnmvq_f16): Likewise.
7333 (vminnmq_f16): Likewise.
7334 (vminnmavq_f16): Likewise.
7335 (vminnmaq_f16): Likewise.
7336 (vmaxnmvq_f16): Likewise.
7337 (vmaxnmq_f16): Likewise.
7338 (vmaxnmavq_f16): Likewise.
7339 (vmaxnmaq_f16): Likewise.
7340 (veorq_f16): Likewise.
7341 (vcmulq_rot90_f16): Likewise.
7342 (vcmulq_rot270_f16): Likewise.
7343 (vcmulq_rot180_f16): Likewise.
7344 (vcmulq_f16): Likewise.
7345 (vcaddq_rot90_f16): Likewise.
7346 (vcaddq_rot270_f16): Likewise.
7347 (vbicq_f16): Likewise.
7348 (vandq_f16): Likewise.
7349 (vaddq_n_f16): Likewise.
7350 (vabdq_f16): Likewise.
7351 (vshlltq_n_s8): Likewise.
7352 (vshllbq_n_s8): Likewise.
7353 (vorrq_n_s16): Likewise.
7354 (vbicq_n_s16): Likewise.
7355 (vqmovntq_u32): Likewise.
7356 (vqmovnbq_u32): Likewise.
7357 (vmulltq_poly_p16): Likewise.
7358 (vmullbq_poly_p16): Likewise.
7359 (vmovntq_u32): Likewise.
7360 (vmovnbq_u32): Likewise.
7361 (vmlaldavxq_u32): Likewise.
7362 (vmlaldavq_u32): Likewise.
7363 (vqmovuntq_s32): Likewise.
7364 (vqmovunbq_s32): Likewise.
7365 (vshlltq_n_u16): Likewise.
7366 (vshllbq_n_u16): Likewise.
7367 (vorrq_n_u32): Likewise.
7368 (vbicq_n_u32): Likewise.
7369 (vcmpneq_n_f32): Likewise.
7370 (vcmpneq_f32): Likewise.
7371 (vcmpltq_n_f32): Likewise.
7372 (vcmpltq_f32): Likewise.
7373 (vcmpleq_n_f32): Likewise.
7374 (vcmpleq_f32): Likewise.
7375 (vcmpgtq_n_f32): Likewise.
7376 (vcmpgtq_f32): Likewise.
7377 (vcmpgeq_n_f32): Likewise.
7378 (vcmpgeq_f32): Likewise.
7379 (vcmpeqq_n_f32): Likewise.
7380 (vcmpeqq_f32): Likewise.
7381 (vsubq_f32): Likewise.
7382 (vqmovntq_s32): Likewise.
7383 (vqmovnbq_s32): Likewise.
7384 (vqdmulltq_s32): Likewise.
7385 (vqdmulltq_n_s32): Likewise.
7386 (vqdmullbq_s32): Likewise.
7387 (vqdmullbq_n_s32): Likewise.
7388 (vorrq_f32): Likewise.
7389 (vornq_f32): Likewise.
7390 (vmulq_n_f32): Likewise.
7391 (vmulq_f32): Likewise.
7392 (vmovntq_s32): Likewise.
7393 (vmovnbq_s32): Likewise.
7394 (vmlsldavxq_s32): Likewise.
7395 (vmlsldavq_s32): Likewise.
7396 (vmlaldavxq_s32): Likewise.
7397 (vmlaldavq_s32): Likewise.
7398 (vminnmvq_f32): Likewise.
7399 (vminnmq_f32): Likewise.
7400 (vminnmavq_f32): Likewise.
7401 (vminnmaq_f32): Likewise.
7402 (vmaxnmvq_f32): Likewise.
7403 (vmaxnmq_f32): Likewise.
7404 (vmaxnmavq_f32): Likewise.
7405 (vmaxnmaq_f32): Likewise.
7406 (veorq_f32): Likewise.
7407 (vcmulq_rot90_f32): Likewise.
7408 (vcmulq_rot270_f32): Likewise.
7409 (vcmulq_rot180_f32): Likewise.
7410 (vcmulq_f32): Likewise.
7411 (vcaddq_rot90_f32): Likewise.
7412 (vcaddq_rot270_f32): Likewise.
7413 (vbicq_f32): Likewise.
7414 (vandq_f32): Likewise.
7415 (vaddq_n_f32): Likewise.
7416 (vabdq_f32): Likewise.
7417 (vshlltq_n_s16): Likewise.
7418 (vshllbq_n_s16): Likewise.
7419 (vorrq_n_s32): Likewise.
7420 (vbicq_n_s32): Likewise.
7421 (vrmlaldavhq_u32): Likewise.
7422 (vctp8q_m): Likewise.
7423 (vctp64q_m): Likewise.
7424 (vctp32q_m): Likewise.
7425 (vctp16q_m): Likewise.
7426 (vaddlvaq_u32): Likewise.
7427 (vrmlsldavhxq_s32): Likewise.
7428 (vrmlsldavhq_s32): Likewise.
7429 (vrmlaldavhxq_s32): Likewise.
7430 (vrmlaldavhq_s32): Likewise.
7431 (vcvttq_f16_f32): Likewise.
7432 (vcvtbq_f16_f32): Likewise.
7433 (vaddlvaq_s32): Likewise.
7434 (__arm_vqmovntq_u16): Define intrinsic.
7435 (__arm_vqmovnbq_u16): Likewise.
7436 (__arm_vmulltq_poly_p8): Likewise.
7437 (__arm_vmullbq_poly_p8): Likewise.
7438 (__arm_vmovntq_u16): Likewise.
7439 (__arm_vmovnbq_u16): Likewise.
7440 (__arm_vmlaldavxq_u16): Likewise.
7441 (__arm_vmlaldavq_u16): Likewise.
7442 (__arm_vqmovuntq_s16): Likewise.
7443 (__arm_vqmovunbq_s16): Likewise.
7444 (__arm_vshlltq_n_u8): Likewise.
7445 (__arm_vshllbq_n_u8): Likewise.
7446 (__arm_vorrq_n_u16): Likewise.
7447 (__arm_vbicq_n_u16): Likewise.
7448 (__arm_vcmpneq_n_f16): Likewise.
7449 (__arm_vcmpneq_f16): Likewise.
7450 (__arm_vcmpltq_n_f16): Likewise.
7451 (__arm_vcmpltq_f16): Likewise.
7452 (__arm_vcmpleq_n_f16): Likewise.
7453 (__arm_vcmpleq_f16): Likewise.
7454 (__arm_vcmpgtq_n_f16): Likewise.
7455 (__arm_vcmpgtq_f16): Likewise.
7456 (__arm_vcmpgeq_n_f16): Likewise.
7457 (__arm_vcmpgeq_f16): Likewise.
7458 (__arm_vcmpeqq_n_f16): Likewise.
7459 (__arm_vcmpeqq_f16): Likewise.
7460 (__arm_vsubq_f16): Likewise.
7461 (__arm_vqmovntq_s16): Likewise.
7462 (__arm_vqmovnbq_s16): Likewise.
7463 (__arm_vqdmulltq_s16): Likewise.
7464 (__arm_vqdmulltq_n_s16): Likewise.
7465 (__arm_vqdmullbq_s16): Likewise.
7466 (__arm_vqdmullbq_n_s16): Likewise.
7467 (__arm_vorrq_f16): Likewise.
7468 (__arm_vornq_f16): Likewise.
7469 (__arm_vmulq_n_f16): Likewise.
7470 (__arm_vmulq_f16): Likewise.
7471 (__arm_vmovntq_s16): Likewise.
7472 (__arm_vmovnbq_s16): Likewise.
7473 (__arm_vmlsldavxq_s16): Likewise.
7474 (__arm_vmlsldavq_s16): Likewise.
7475 (__arm_vmlaldavxq_s16): Likewise.
7476 (__arm_vmlaldavq_s16): Likewise.
7477 (__arm_vminnmvq_f16): Likewise.
7478 (__arm_vminnmq_f16): Likewise.
7479 (__arm_vminnmavq_f16): Likewise.
7480 (__arm_vminnmaq_f16): Likewise.
7481 (__arm_vmaxnmvq_f16): Likewise.
7482 (__arm_vmaxnmq_f16): Likewise.
7483 (__arm_vmaxnmavq_f16): Likewise.
7484 (__arm_vmaxnmaq_f16): Likewise.
7485 (__arm_veorq_f16): Likewise.
7486 (__arm_vcmulq_rot90_f16): Likewise.
7487 (__arm_vcmulq_rot270_f16): Likewise.
7488 (__arm_vcmulq_rot180_f16): Likewise.
7489 (__arm_vcmulq_f16): Likewise.
7490 (__arm_vcaddq_rot90_f16): Likewise.
7491 (__arm_vcaddq_rot270_f16): Likewise.
7492 (__arm_vbicq_f16): Likewise.
7493 (__arm_vandq_f16): Likewise.
7494 (__arm_vaddq_n_f16): Likewise.
7495 (__arm_vabdq_f16): Likewise.
7496 (__arm_vshlltq_n_s8): Likewise.
7497 (__arm_vshllbq_n_s8): Likewise.
7498 (__arm_vorrq_n_s16): Likewise.
7499 (__arm_vbicq_n_s16): Likewise.
7500 (__arm_vqmovntq_u32): Likewise.
7501 (__arm_vqmovnbq_u32): Likewise.
7502 (__arm_vmulltq_poly_p16): Likewise.
7503 (__arm_vmullbq_poly_p16): Likewise.
7504 (__arm_vmovntq_u32): Likewise.
7505 (__arm_vmovnbq_u32): Likewise.
7506 (__arm_vmlaldavxq_u32): Likewise.
7507 (__arm_vmlaldavq_u32): Likewise.
7508 (__arm_vqmovuntq_s32): Likewise.
7509 (__arm_vqmovunbq_s32): Likewise.
7510 (__arm_vshlltq_n_u16): Likewise.
7511 (__arm_vshllbq_n_u16): Likewise.
7512 (__arm_vorrq_n_u32): Likewise.
7513 (__arm_vbicq_n_u32): Likewise.
7514 (__arm_vcmpneq_n_f32): Likewise.
7515 (__arm_vcmpneq_f32): Likewise.
7516 (__arm_vcmpltq_n_f32): Likewise.
7517 (__arm_vcmpltq_f32): Likewise.
7518 (__arm_vcmpleq_n_f32): Likewise.
7519 (__arm_vcmpleq_f32): Likewise.
7520 (__arm_vcmpgtq_n_f32): Likewise.
7521 (__arm_vcmpgtq_f32): Likewise.
7522 (__arm_vcmpgeq_n_f32): Likewise.
7523 (__arm_vcmpgeq_f32): Likewise.
7524 (__arm_vcmpeqq_n_f32): Likewise.
7525 (__arm_vcmpeqq_f32): Likewise.
7526 (__arm_vsubq_f32): Likewise.
7527 (__arm_vqmovntq_s32): Likewise.
7528 (__arm_vqmovnbq_s32): Likewise.
7529 (__arm_vqdmulltq_s32): Likewise.
7530 (__arm_vqdmulltq_n_s32): Likewise.
7531 (__arm_vqdmullbq_s32): Likewise.
7532 (__arm_vqdmullbq_n_s32): Likewise.
7533 (__arm_vorrq_f32): Likewise.
7534 (__arm_vornq_f32): Likewise.
7535 (__arm_vmulq_n_f32): Likewise.
7536 (__arm_vmulq_f32): Likewise.
7537 (__arm_vmovntq_s32): Likewise.
7538 (__arm_vmovnbq_s32): Likewise.
7539 (__arm_vmlsldavxq_s32): Likewise.
7540 (__arm_vmlsldavq_s32): Likewise.
7541 (__arm_vmlaldavxq_s32): Likewise.
7542 (__arm_vmlaldavq_s32): Likewise.
7543 (__arm_vminnmvq_f32): Likewise.
7544 (__arm_vminnmq_f32): Likewise.
7545 (__arm_vminnmavq_f32): Likewise.
7546 (__arm_vminnmaq_f32): Likewise.
7547 (__arm_vmaxnmvq_f32): Likewise.
7548 (__arm_vmaxnmq_f32): Likewise.
7549 (__arm_vmaxnmavq_f32): Likewise.
7550 (__arm_vmaxnmaq_f32): Likewise.
7551 (__arm_veorq_f32): Likewise.
7552 (__arm_vcmulq_rot90_f32): Likewise.
7553 (__arm_vcmulq_rot270_f32): Likewise.
7554 (__arm_vcmulq_rot180_f32): Likewise.
7555 (__arm_vcmulq_f32): Likewise.
7556 (__arm_vcaddq_rot90_f32): Likewise.
7557 (__arm_vcaddq_rot270_f32): Likewise.
7558 (__arm_vbicq_f32): Likewise.
7559 (__arm_vandq_f32): Likewise.
7560 (__arm_vaddq_n_f32): Likewise.
7561 (__arm_vabdq_f32): Likewise.
7562 (__arm_vshlltq_n_s16): Likewise.
7563 (__arm_vshllbq_n_s16): Likewise.
7564 (__arm_vorrq_n_s32): Likewise.
7565 (__arm_vbicq_n_s32): Likewise.
7566 (__arm_vrmlaldavhq_u32): Likewise.
7567 (__arm_vctp8q_m): Likewise.
7568 (__arm_vctp64q_m): Likewise.
7569 (__arm_vctp32q_m): Likewise.
7570 (__arm_vctp16q_m): Likewise.
7571 (__arm_vaddlvaq_u32): Likewise.
7572 (__arm_vrmlsldavhxq_s32): Likewise.
7573 (__arm_vrmlsldavhq_s32): Likewise.
7574 (__arm_vrmlaldavhxq_s32): Likewise.
7575 (__arm_vrmlaldavhq_s32): Likewise.
7576 (__arm_vcvttq_f16_f32): Likewise.
7577 (__arm_vcvtbq_f16_f32): Likewise.
7578 (__arm_vaddlvaq_s32): Likewise.
7579 (vst4q): Define polymorphic variant.
7586 (vrev64q): Likewise.
7588 (vdupq_n): Likewise.
7590 (vrev32q): Likewise.
7591 (vcvtbq_f32): Likewise.
7592 (vcvttq_f32): Likewise.
7594 (vsubq_n): Likewise.
7595 (vbrsrq_n): Likewise.
7596 (vcvtq_n): Likewise.
7600 (vaddq_n): Likewise.
7604 (vmulq_n): Likewise.
7606 (vcaddq_rot270): Likewise.
7607 (vcmpeqq_n): Likewise.
7608 (vcmpeqq): Likewise.
7609 (vcaddq_rot90): Likewise.
7610 (vcmpgeq_n): Likewise.
7611 (vcmpgeq): Likewise.
7612 (vcmpgtq_n): Likewise.
7613 (vcmpgtq): Likewise.
7614 (vcmpgtq): Likewise.
7615 (vcmpleq_n): Likewise.
7616 (vcmpleq_n): Likewise.
7617 (vcmpleq): Likewise.
7618 (vcmpleq): Likewise.
7619 (vcmpltq_n): Likewise.
7620 (vcmpltq_n): Likewise.
7621 (vcmpltq): Likewise.
7622 (vcmpltq): Likewise.
7623 (vcmpneq_n): Likewise.
7624 (vcmpneq_n): Likewise.
7625 (vcmpneq): Likewise.
7626 (vcmpneq): Likewise.
7629 (vcmulq_rot180): Likewise.
7630 (vcmulq_rot180): Likewise.
7631 (vcmulq_rot270): Likewise.
7632 (vcmulq_rot270): Likewise.
7633 (vcmulq_rot90): Likewise.
7634 (vcmulq_rot90): Likewise.
7637 (vmaxnmaq): Likewise.
7638 (vmaxnmaq): Likewise.
7639 (vmaxnmavq): Likewise.
7640 (vmaxnmavq): Likewise.
7641 (vmaxnmq): Likewise.
7642 (vmaxnmq): Likewise.
7643 (vmaxnmvq): Likewise.
7644 (vmaxnmvq): Likewise.
7645 (vminnmaq): Likewise.
7646 (vminnmaq): Likewise.
7647 (vminnmavq): Likewise.
7648 (vminnmavq): Likewise.
7649 (vminnmq): Likewise.
7650 (vminnmq): Likewise.
7651 (vminnmvq): Likewise.
7652 (vminnmvq): Likewise.
7653 (vbicq_n): Likewise.
7654 (vqmovntq): Likewise.
7655 (vqmovntq): Likewise.
7656 (vqmovnbq): Likewise.
7657 (vqmovnbq): Likewise.
7658 (vmulltq_poly): Likewise.
7659 (vmulltq_poly): Likewise.
7660 (vmullbq_poly): Likewise.
7661 (vmullbq_poly): Likewise.
7662 (vmovntq): Likewise.
7663 (vmovntq): Likewise.
7664 (vmovnbq): Likewise.
7665 (vmovnbq): Likewise.
7666 (vmlaldavxq): Likewise.
7667 (vmlaldavxq): Likewise.
7668 (vqmovuntq): Likewise.
7669 (vqmovuntq): Likewise.
7670 (vshlltq_n): Likewise.
7671 (vshlltq_n): Likewise.
7672 (vshllbq_n): Likewise.
7673 (vshllbq_n): Likewise.
7674 (vorrq_n): Likewise.
7675 (vorrq_n): Likewise.
7676 (vmlaldavq): Likewise.
7677 (vmlaldavq): Likewise.
7678 (vqmovunbq): Likewise.
7679 (vqmovunbq): Likewise.
7680 (vqdmulltq_n): Likewise.
7681 (vqdmulltq_n): Likewise.
7682 (vqdmulltq): Likewise.
7683 (vqdmulltq): Likewise.
7684 (vqdmullbq_n): Likewise.
7685 (vqdmullbq_n): Likewise.
7686 (vqdmullbq): Likewise.
7687 (vqdmullbq): Likewise.
7688 (vaddlvaq): Likewise.
7689 (vaddlvaq): Likewise.
7690 (vrmlaldavhq): Likewise.
7691 (vrmlaldavhq): Likewise.
7692 (vrmlaldavhxq): Likewise.
7693 (vrmlaldavhxq): Likewise.
7694 (vrmlsldavhq): Likewise.
7695 (vrmlsldavhq): Likewise.
7696 (vrmlsldavhxq): Likewise.
7697 (vrmlsldavhxq): Likewise.
7698 (vmlsldavxq): Likewise.
7699 (vmlsldavxq): Likewise.
7700 (vmlsldavq): Likewise.
7701 (vmlsldavq): Likewise.
7702 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
7703 (BINOP_NONE_NONE_NONE): Likewise.
7704 (BINOP_UNONE_NONE_NONE): Likewise.
7705 (BINOP_UNONE_UNONE_IMM): Likewise.
7706 (BINOP_UNONE_UNONE_NONE): Likewise.
7707 (BINOP_UNONE_UNONE_UNONE): Likewise.
7708 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
7709 (mve_vaddlvaq_<supf>v4si): Likewise.
7710 (mve_vaddq_n_f<mode>): Likewise.
7711 (mve_vandq_f<mode>): Likewise.
7712 (mve_vbicq_f<mode>): Likewise.
7713 (mve_vbicq_n_<supf><mode>): Likewise.
7714 (mve_vcaddq_rot270_f<mode>): Likewise.
7715 (mve_vcaddq_rot90_f<mode>): Likewise.
7716 (mve_vcmpeqq_f<mode>): Likewise.
7717 (mve_vcmpeqq_n_f<mode>): Likewise.
7718 (mve_vcmpgeq_f<mode>): Likewise.
7719 (mve_vcmpgeq_n_f<mode>): Likewise.
7720 (mve_vcmpgtq_f<mode>): Likewise.
7721 (mve_vcmpgtq_n_f<mode>): Likewise.
7722 (mve_vcmpleq_f<mode>): Likewise.
7723 (mve_vcmpleq_n_f<mode>): Likewise.
7724 (mve_vcmpltq_f<mode>): Likewise.
7725 (mve_vcmpltq_n_f<mode>): Likewise.
7726 (mve_vcmpneq_f<mode>): Likewise.
7727 (mve_vcmpneq_n_f<mode>): Likewise.
7728 (mve_vcmulq_f<mode>): Likewise.
7729 (mve_vcmulq_rot180_f<mode>): Likewise.
7730 (mve_vcmulq_rot270_f<mode>): Likewise.
7731 (mve_vcmulq_rot90_f<mode>): Likewise.
7732 (mve_vctp<mode1>q_mhi): Likewise.
7733 (mve_vcvtbq_f16_f32v8hf): Likewise.
7734 (mve_vcvttq_f16_f32v8hf): Likewise.
7735 (mve_veorq_f<mode>): Likewise.
7736 (mve_vmaxnmaq_f<mode>): Likewise.
7737 (mve_vmaxnmavq_f<mode>): Likewise.
7738 (mve_vmaxnmq_f<mode>): Likewise.
7739 (mve_vmaxnmvq_f<mode>): Likewise.
7740 (mve_vminnmaq_f<mode>): Likewise.
7741 (mve_vminnmavq_f<mode>): Likewise.
7742 (mve_vminnmq_f<mode>): Likewise.
7743 (mve_vminnmvq_f<mode>): Likewise.
7744 (mve_vmlaldavq_<supf><mode>): Likewise.
7745 (mve_vmlaldavxq_<supf><mode>): Likewise.
7746 (mve_vmlsldavq_s<mode>): Likewise.
7747 (mve_vmlsldavxq_s<mode>): Likewise.
7748 (mve_vmovnbq_<supf><mode>): Likewise.
7749 (mve_vmovntq_<supf><mode>): Likewise.
7750 (mve_vmulq_f<mode>): Likewise.
7751 (mve_vmulq_n_f<mode>): Likewise.
7752 (mve_vornq_f<mode>): Likewise.
7753 (mve_vorrq_f<mode>): Likewise.
7754 (mve_vorrq_n_<supf><mode>): Likewise.
7755 (mve_vqdmullbq_n_s<mode>): Likewise.
7756 (mve_vqdmullbq_s<mode>): Likewise.
7757 (mve_vqdmulltq_n_s<mode>): Likewise.
7758 (mve_vqdmulltq_s<mode>): Likewise.
7759 (mve_vqmovnbq_<supf><mode>): Likewise.
7760 (mve_vqmovntq_<supf><mode>): Likewise.
7761 (mve_vqmovunbq_s<mode>): Likewise.
7762 (mve_vqmovuntq_s<mode>): Likewise.
7763 (mve_vrmlaldavhxq_sv4si): Likewise.
7764 (mve_vrmlsldavhq_sv4si): Likewise.
7765 (mve_vrmlsldavhxq_sv4si): Likewise.
7766 (mve_vshllbq_n_<supf><mode>): Likewise.
7767 (mve_vshlltq_n_<supf><mode>): Likewise.
7768 (mve_vsubq_f<mode>): Likewise.
7769 (mve_vmulltq_poly_p<mode>): Likewise.
7770 (mve_vmullbq_poly_p<mode>): Likewise.
7771 (mve_vrmlaldavhq_<supf>v4si): Likewise.
7773 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
7774 Mihail Ionescu <mihail.ionescu@arm.com>
7775 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7777 * config/arm/arm_mve.h (vsubq_u8): Define macro.
7778 (vsubq_n_u8): Likewise.
7779 (vrmulhq_u8): Likewise.
7780 (vrhaddq_u8): Likewise.
7781 (vqsubq_u8): Likewise.
7782 (vqsubq_n_u8): Likewise.
7783 (vqaddq_u8): Likewise.
7784 (vqaddq_n_u8): Likewise.
7785 (vorrq_u8): Likewise.
7786 (vornq_u8): Likewise.
7787 (vmulq_u8): Likewise.
7788 (vmulq_n_u8): Likewise.
7789 (vmulltq_int_u8): Likewise.
7790 (vmullbq_int_u8): Likewise.
7791 (vmulhq_u8): Likewise.
7792 (vmladavq_u8): Likewise.
7793 (vminvq_u8): Likewise.
7794 (vminq_u8): Likewise.
7795 (vmaxvq_u8): Likewise.
7796 (vmaxq_u8): Likewise.
7797 (vhsubq_u8): Likewise.
7798 (vhsubq_n_u8): Likewise.
7799 (vhaddq_u8): Likewise.
7800 (vhaddq_n_u8): Likewise.
7801 (veorq_u8): Likewise.
7802 (vcmpneq_n_u8): Likewise.
7803 (vcmphiq_u8): Likewise.
7804 (vcmphiq_n_u8): Likewise.
7805 (vcmpeqq_u8): Likewise.
7806 (vcmpeqq_n_u8): Likewise.
7807 (vcmpcsq_u8): Likewise.
7808 (vcmpcsq_n_u8): Likewise.
7809 (vcaddq_rot90_u8): Likewise.
7810 (vcaddq_rot270_u8): Likewise.
7811 (vbicq_u8): Likewise.
7812 (vandq_u8): Likewise.
7813 (vaddvq_p_u8): Likewise.
7814 (vaddvaq_u8): Likewise.
7815 (vaddq_n_u8): Likewise.
7816 (vabdq_u8): Likewise.
7817 (vshlq_r_u8): Likewise.
7818 (vrshlq_u8): Likewise.
7819 (vrshlq_n_u8): Likewise.
7820 (vqshlq_u8): Likewise.
7821 (vqshlq_r_u8): Likewise.
7822 (vqrshlq_u8): Likewise.
7823 (vqrshlq_n_u8): Likewise.
7824 (vminavq_s8): Likewise.
7825 (vminaq_s8): Likewise.
7826 (vmaxavq_s8): Likewise.
7827 (vmaxaq_s8): Likewise.
7828 (vbrsrq_n_u8): Likewise.
7829 (vshlq_n_u8): Likewise.
7830 (vrshrq_n_u8): Likewise.
7831 (vqshlq_n_u8): Likewise.
7832 (vcmpneq_n_s8): Likewise.
7833 (vcmpltq_s8): Likewise.
7834 (vcmpltq_n_s8): Likewise.
7835 (vcmpleq_s8): Likewise.
7836 (vcmpleq_n_s8): Likewise.
7837 (vcmpgtq_s8): Likewise.
7838 (vcmpgtq_n_s8): Likewise.
7839 (vcmpgeq_s8): Likewise.
7840 (vcmpgeq_n_s8): Likewise.
7841 (vcmpeqq_s8): Likewise.
7842 (vcmpeqq_n_s8): Likewise.
7843 (vqshluq_n_s8): Likewise.
7844 (vaddvq_p_s8): Likewise.
7845 (vsubq_s8): Likewise.
7846 (vsubq_n_s8): Likewise.
7847 (vshlq_r_s8): Likewise.
7848 (vrshlq_s8): Likewise.
7849 (vrshlq_n_s8): Likewise.
7850 (vrmulhq_s8): Likewise.
7851 (vrhaddq_s8): Likewise.
7852 (vqsubq_s8): Likewise.
7853 (vqsubq_n_s8): Likewise.
7854 (vqshlq_s8): Likewise.
7855 (vqshlq_r_s8): Likewise.
7856 (vqrshlq_s8): Likewise.
7857 (vqrshlq_n_s8): Likewise.
7858 (vqrdmulhq_s8): Likewise.
7859 (vqrdmulhq_n_s8): Likewise.
7860 (vqdmulhq_s8): Likewise.
7861 (vqdmulhq_n_s8): Likewise.
7862 (vqaddq_s8): Likewise.
7863 (vqaddq_n_s8): Likewise.
7864 (vorrq_s8): Likewise.
7865 (vornq_s8): Likewise.
7866 (vmulq_s8): Likewise.
7867 (vmulq_n_s8): Likewise.
7868 (vmulltq_int_s8): Likewise.
7869 (vmullbq_int_s8): Likewise.
7870 (vmulhq_s8): Likewise.
7871 (vmlsdavxq_s8): Likewise.
7872 (vmlsdavq_s8): Likewise.
7873 (vmladavxq_s8): Likewise.
7874 (vmladavq_s8): Likewise.
7875 (vminvq_s8): Likewise.
7876 (vminq_s8): Likewise.
7877 (vmaxvq_s8): Likewise.
7878 (vmaxq_s8): Likewise.
7879 (vhsubq_s8): Likewise.
7880 (vhsubq_n_s8): Likewise.
7881 (vhcaddq_rot90_s8): Likewise.
7882 (vhcaddq_rot270_s8): Likewise.
7883 (vhaddq_s8): Likewise.
7884 (vhaddq_n_s8): Likewise.
7885 (veorq_s8): Likewise.
7886 (vcaddq_rot90_s8): Likewise.
7887 (vcaddq_rot270_s8): Likewise.
7888 (vbrsrq_n_s8): Likewise.
7889 (vbicq_s8): Likewise.
7890 (vandq_s8): Likewise.
7891 (vaddvaq_s8): Likewise.
7892 (vaddq_n_s8): Likewise.
7893 (vabdq_s8): Likewise.
7894 (vshlq_n_s8): Likewise.
7895 (vrshrq_n_s8): Likewise.
7896 (vqshlq_n_s8): Likewise.
7897 (vsubq_u16): Likewise.
7898 (vsubq_n_u16): Likewise.
7899 (vrmulhq_u16): Likewise.
7900 (vrhaddq_u16): Likewise.
7901 (vqsubq_u16): Likewise.
7902 (vqsubq_n_u16): Likewise.
7903 (vqaddq_u16): Likewise.
7904 (vqaddq_n_u16): Likewise.
7905 (vorrq_u16): Likewise.
7906 (vornq_u16): Likewise.
7907 (vmulq_u16): Likewise.
7908 (vmulq_n_u16): Likewise.
7909 (vmulltq_int_u16): Likewise.
7910 (vmullbq_int_u16): Likewise.
7911 (vmulhq_u16): Likewise.
7912 (vmladavq_u16): Likewise.
7913 (vminvq_u16): Likewise.
7914 (vminq_u16): Likewise.
7915 (vmaxvq_u16): Likewise.
7916 (vmaxq_u16): Likewise.
7917 (vhsubq_u16): Likewise.
7918 (vhsubq_n_u16): Likewise.
7919 (vhaddq_u16): Likewise.
7920 (vhaddq_n_u16): Likewise.
7921 (veorq_u16): Likewise.
7922 (vcmpneq_n_u16): Likewise.
7923 (vcmphiq_u16): Likewise.
7924 (vcmphiq_n_u16): Likewise.
7925 (vcmpeqq_u16): Likewise.
7926 (vcmpeqq_n_u16): Likewise.
7927 (vcmpcsq_u16): Likewise.
7928 (vcmpcsq_n_u16): Likewise.
7929 (vcaddq_rot90_u16): Likewise.
7930 (vcaddq_rot270_u16): Likewise.
7931 (vbicq_u16): Likewise.
7932 (vandq_u16): Likewise.
7933 (vaddvq_p_u16): Likewise.
7934 (vaddvaq_u16): Likewise.
7935 (vaddq_n_u16): Likewise.
7936 (vabdq_u16): Likewise.
7937 (vshlq_r_u16): Likewise.
7938 (vrshlq_u16): Likewise.
7939 (vrshlq_n_u16): Likewise.
7940 (vqshlq_u16): Likewise.
7941 (vqshlq_r_u16): Likewise.
7942 (vqrshlq_u16): Likewise.
7943 (vqrshlq_n_u16): Likewise.
7944 (vminavq_s16): Likewise.
7945 (vminaq_s16): Likewise.
7946 (vmaxavq_s16): Likewise.
7947 (vmaxaq_s16): Likewise.
7948 (vbrsrq_n_u16): Likewise.
7949 (vshlq_n_u16): Likewise.
7950 (vrshrq_n_u16): Likewise.
7951 (vqshlq_n_u16): Likewise.
7952 (vcmpneq_n_s16): Likewise.
7953 (vcmpltq_s16): Likewise.
7954 (vcmpltq_n_s16): Likewise.
7955 (vcmpleq_s16): Likewise.
7956 (vcmpleq_n_s16): Likewise.
7957 (vcmpgtq_s16): Likewise.
7958 (vcmpgtq_n_s16): Likewise.
7959 (vcmpgeq_s16): Likewise.
7960 (vcmpgeq_n_s16): Likewise.
7961 (vcmpeqq_s16): Likewise.
7962 (vcmpeqq_n_s16): Likewise.
7963 (vqshluq_n_s16): Likewise.
7964 (vaddvq_p_s16): Likewise.
7965 (vsubq_s16): Likewise.
7966 (vsubq_n_s16): Likewise.
7967 (vshlq_r_s16): Likewise.
7968 (vrshlq_s16): Likewise.
7969 (vrshlq_n_s16): Likewise.
7970 (vrmulhq_s16): Likewise.
7971 (vrhaddq_s16): Likewise.
7972 (vqsubq_s16): Likewise.
7973 (vqsubq_n_s16): Likewise.
7974 (vqshlq_s16): Likewise.
7975 (vqshlq_r_s16): Likewise.
7976 (vqrshlq_s16): Likewise.
7977 (vqrshlq_n_s16): Likewise.
7978 (vqrdmulhq_s16): Likewise.
7979 (vqrdmulhq_n_s16): Likewise.
7980 (vqdmulhq_s16): Likewise.
7981 (vqdmulhq_n_s16): Likewise.
7982 (vqaddq_s16): Likewise.
7983 (vqaddq_n_s16): Likewise.
7984 (vorrq_s16): Likewise.
7985 (vornq_s16): Likewise.
7986 (vmulq_s16): Likewise.
7987 (vmulq_n_s16): Likewise.
7988 (vmulltq_int_s16): Likewise.
7989 (vmullbq_int_s16): Likewise.
7990 (vmulhq_s16): Likewise.
7991 (vmlsdavxq_s16): Likewise.
7992 (vmlsdavq_s16): Likewise.
7993 (vmladavxq_s16): Likewise.
7994 (vmladavq_s16): Likewise.
7995 (vminvq_s16): Likewise.
7996 (vminq_s16): Likewise.
7997 (vmaxvq_s16): Likewise.
7998 (vmaxq_s16): Likewise.
7999 (vhsubq_s16): Likewise.
8000 (vhsubq_n_s16): Likewise.
8001 (vhcaddq_rot90_s16): Likewise.
8002 (vhcaddq_rot270_s16): Likewise.
8003 (vhaddq_s16): Likewise.
8004 (vhaddq_n_s16): Likewise.
8005 (veorq_s16): Likewise.
8006 (vcaddq_rot90_s16): Likewise.
8007 (vcaddq_rot270_s16): Likewise.
8008 (vbrsrq_n_s16): Likewise.
8009 (vbicq_s16): Likewise.
8010 (vandq_s16): Likewise.
8011 (vaddvaq_s16): Likewise.
8012 (vaddq_n_s16): Likewise.
8013 (vabdq_s16): Likewise.
8014 (vshlq_n_s16): Likewise.
8015 (vrshrq_n_s16): Likewise.
8016 (vqshlq_n_s16): Likewise.
8017 (vsubq_u32): Likewise.
8018 (vsubq_n_u32): Likewise.
8019 (vrmulhq_u32): Likewise.
8020 (vrhaddq_u32): Likewise.
8021 (vqsubq_u32): Likewise.
8022 (vqsubq_n_u32): Likewise.
8023 (vqaddq_u32): Likewise.
8024 (vqaddq_n_u32): Likewise.
8025 (vorrq_u32): Likewise.
8026 (vornq_u32): Likewise.
8027 (vmulq_u32): Likewise.
8028 (vmulq_n_u32): Likewise.
8029 (vmulltq_int_u32): Likewise.
8030 (vmullbq_int_u32): Likewise.
8031 (vmulhq_u32): Likewise.
8032 (vmladavq_u32): Likewise.
8033 (vminvq_u32): Likewise.
8034 (vminq_u32): Likewise.
8035 (vmaxvq_u32): Likewise.
8036 (vmaxq_u32): Likewise.
8037 (vhsubq_u32): Likewise.
8038 (vhsubq_n_u32): Likewise.
8039 (vhaddq_u32): Likewise.
8040 (vhaddq_n_u32): Likewise.
8041 (veorq_u32): Likewise.
8042 (vcmpneq_n_u32): Likewise.
8043 (vcmphiq_u32): Likewise.
8044 (vcmphiq_n_u32): Likewise.
8045 (vcmpeqq_u32): Likewise.
8046 (vcmpeqq_n_u32): Likewise.
8047 (vcmpcsq_u32): Likewise.
8048 (vcmpcsq_n_u32): Likewise.
8049 (vcaddq_rot90_u32): Likewise.
8050 (vcaddq_rot270_u32): Likewise.
8051 (vbicq_u32): Likewise.
8052 (vandq_u32): Likewise.
8053 (vaddvq_p_u32): Likewise.
8054 (vaddvaq_u32): Likewise.
8055 (vaddq_n_u32): Likewise.
8056 (vabdq_u32): Likewise.
8057 (vshlq_r_u32): Likewise.
8058 (vrshlq_u32): Likewise.
8059 (vrshlq_n_u32): Likewise.
8060 (vqshlq_u32): Likewise.
8061 (vqshlq_r_u32): Likewise.
8062 (vqrshlq_u32): Likewise.
8063 (vqrshlq_n_u32): Likewise.
8064 (vminavq_s32): Likewise.
8065 (vminaq_s32): Likewise.
8066 (vmaxavq_s32): Likewise.
8067 (vmaxaq_s32): Likewise.
8068 (vbrsrq_n_u32): Likewise.
8069 (vshlq_n_u32): Likewise.
8070 (vrshrq_n_u32): Likewise.
8071 (vqshlq_n_u32): Likewise.
8072 (vcmpneq_n_s32): Likewise.
8073 (vcmpltq_s32): Likewise.
8074 (vcmpltq_n_s32): Likewise.
8075 (vcmpleq_s32): Likewise.
8076 (vcmpleq_n_s32): Likewise.
8077 (vcmpgtq_s32): Likewise.
8078 (vcmpgtq_n_s32): Likewise.
8079 (vcmpgeq_s32): Likewise.
8080 (vcmpgeq_n_s32): Likewise.
8081 (vcmpeqq_s32): Likewise.
8082 (vcmpeqq_n_s32): Likewise.
8083 (vqshluq_n_s32): Likewise.
8084 (vaddvq_p_s32): Likewise.
8085 (vsubq_s32): Likewise.
8086 (vsubq_n_s32): Likewise.
8087 (vshlq_r_s32): Likewise.
8088 (vrshlq_s32): Likewise.
8089 (vrshlq_n_s32): Likewise.
8090 (vrmulhq_s32): Likewise.
8091 (vrhaddq_s32): Likewise.
8092 (vqsubq_s32): Likewise.
8093 (vqsubq_n_s32): Likewise.
8094 (vqshlq_s32): Likewise.
8095 (vqshlq_r_s32): Likewise.
8096 (vqrshlq_s32): Likewise.
8097 (vqrshlq_n_s32): Likewise.
8098 (vqrdmulhq_s32): Likewise.
8099 (vqrdmulhq_n_s32): Likewise.
8100 (vqdmulhq_s32): Likewise.
8101 (vqdmulhq_n_s32): Likewise.
8102 (vqaddq_s32): Likewise.
8103 (vqaddq_n_s32): Likewise.
8104 (vorrq_s32): Likewise.
8105 (vornq_s32): Likewise.
8106 (vmulq_s32): Likewise.
8107 (vmulq_n_s32): Likewise.
8108 (vmulltq_int_s32): Likewise.
8109 (vmullbq_int_s32): Likewise.
8110 (vmulhq_s32): Likewise.
8111 (vmlsdavxq_s32): Likewise.
8112 (vmlsdavq_s32): Likewise.
8113 (vmladavxq_s32): Likewise.
8114 (vmladavq_s32): Likewise.
8115 (vminvq_s32): Likewise.
8116 (vminq_s32): Likewise.
8117 (vmaxvq_s32): Likewise.
8118 (vmaxq_s32): Likewise.
8119 (vhsubq_s32): Likewise.
8120 (vhsubq_n_s32): Likewise.
8121 (vhcaddq_rot90_s32): Likewise.
8122 (vhcaddq_rot270_s32): Likewise.
8123 (vhaddq_s32): Likewise.
8124 (vhaddq_n_s32): Likewise.
8125 (veorq_s32): Likewise.
8126 (vcaddq_rot90_s32): Likewise.
8127 (vcaddq_rot270_s32): Likewise.
8128 (vbrsrq_n_s32): Likewise.
8129 (vbicq_s32): Likewise.
8130 (vandq_s32): Likewise.
8131 (vaddvaq_s32): Likewise.
8132 (vaddq_n_s32): Likewise.
8133 (vabdq_s32): Likewise.
8134 (vshlq_n_s32): Likewise.
8135 (vrshrq_n_s32): Likewise.
8136 (vqshlq_n_s32): Likewise.
8137 (__arm_vsubq_u8): Define intrinsic.
8138 (__arm_vsubq_n_u8): Likewise.
8139 (__arm_vrmulhq_u8): Likewise.
8140 (__arm_vrhaddq_u8): Likewise.
8141 (__arm_vqsubq_u8): Likewise.
8142 (__arm_vqsubq_n_u8): Likewise.
8143 (__arm_vqaddq_u8): Likewise.
8144 (__arm_vqaddq_n_u8): Likewise.
8145 (__arm_vorrq_u8): Likewise.
8146 (__arm_vornq_u8): Likewise.
8147 (__arm_vmulq_u8): Likewise.
8148 (__arm_vmulq_n_u8): Likewise.
8149 (__arm_vmulltq_int_u8): Likewise.
8150 (__arm_vmullbq_int_u8): Likewise.
8151 (__arm_vmulhq_u8): Likewise.
8152 (__arm_vmladavq_u8): Likewise.
8153 (__arm_vminvq_u8): Likewise.
8154 (__arm_vminq_u8): Likewise.
8155 (__arm_vmaxvq_u8): Likewise.
8156 (__arm_vmaxq_u8): Likewise.
8157 (__arm_vhsubq_u8): Likewise.
8158 (__arm_vhsubq_n_u8): Likewise.
8159 (__arm_vhaddq_u8): Likewise.
8160 (__arm_vhaddq_n_u8): Likewise.
8161 (__arm_veorq_u8): Likewise.
8162 (__arm_vcmpneq_n_u8): Likewise.
8163 (__arm_vcmphiq_u8): Likewise.
8164 (__arm_vcmphiq_n_u8): Likewise.
8165 (__arm_vcmpeqq_u8): Likewise.
8166 (__arm_vcmpeqq_n_u8): Likewise.
8167 (__arm_vcmpcsq_u8): Likewise.
8168 (__arm_vcmpcsq_n_u8): Likewise.
8169 (__arm_vcaddq_rot90_u8): Likewise.
8170 (__arm_vcaddq_rot270_u8): Likewise.
8171 (__arm_vbicq_u8): Likewise.
8172 (__arm_vandq_u8): Likewise.
8173 (__arm_vaddvq_p_u8): Likewise.
8174 (__arm_vaddvaq_u8): Likewise.
8175 (__arm_vaddq_n_u8): Likewise.
8176 (__arm_vabdq_u8): Likewise.
8177 (__arm_vshlq_r_u8): Likewise.
8178 (__arm_vrshlq_u8): Likewise.
8179 (__arm_vrshlq_n_u8): Likewise.
8180 (__arm_vqshlq_u8): Likewise.
8181 (__arm_vqshlq_r_u8): Likewise.
8182 (__arm_vqrshlq_u8): Likewise.
8183 (__arm_vqrshlq_n_u8): Likewise.
8184 (__arm_vminavq_s8): Likewise.
8185 (__arm_vminaq_s8): Likewise.
8186 (__arm_vmaxavq_s8): Likewise.
8187 (__arm_vmaxaq_s8): Likewise.
8188 (__arm_vbrsrq_n_u8): Likewise.
8189 (__arm_vshlq_n_u8): Likewise.
8190 (__arm_vrshrq_n_u8): Likewise.
8191 (__arm_vqshlq_n_u8): Likewise.
8192 (__arm_vcmpneq_n_s8): Likewise.
8193 (__arm_vcmpltq_s8): Likewise.
8194 (__arm_vcmpltq_n_s8): Likewise.
8195 (__arm_vcmpleq_s8): Likewise.
8196 (__arm_vcmpleq_n_s8): Likewise.
8197 (__arm_vcmpgtq_s8): Likewise.
8198 (__arm_vcmpgtq_n_s8): Likewise.
8199 (__arm_vcmpgeq_s8): Likewise.
8200 (__arm_vcmpgeq_n_s8): Likewise.
8201 (__arm_vcmpeqq_s8): Likewise.
8202 (__arm_vcmpeqq_n_s8): Likewise.
8203 (__arm_vqshluq_n_s8): Likewise.
8204 (__arm_vaddvq_p_s8): Likewise.
8205 (__arm_vsubq_s8): Likewise.
8206 (__arm_vsubq_n_s8): Likewise.
8207 (__arm_vshlq_r_s8): Likewise.
8208 (__arm_vrshlq_s8): Likewise.
8209 (__arm_vrshlq_n_s8): Likewise.
8210 (__arm_vrmulhq_s8): Likewise.
8211 (__arm_vrhaddq_s8): Likewise.
8212 (__arm_vqsubq_s8): Likewise.
8213 (__arm_vqsubq_n_s8): Likewise.
8214 (__arm_vqshlq_s8): Likewise.
8215 (__arm_vqshlq_r_s8): Likewise.
8216 (__arm_vqrshlq_s8): Likewise.
8217 (__arm_vqrshlq_n_s8): Likewise.
8218 (__arm_vqrdmulhq_s8): Likewise.
8219 (__arm_vqrdmulhq_n_s8): Likewise.
8220 (__arm_vqdmulhq_s8): Likewise.
8221 (__arm_vqdmulhq_n_s8): Likewise.
8222 (__arm_vqaddq_s8): Likewise.
8223 (__arm_vqaddq_n_s8): Likewise.
8224 (__arm_vorrq_s8): Likewise.
8225 (__arm_vornq_s8): Likewise.
8226 (__arm_vmulq_s8): Likewise.
8227 (__arm_vmulq_n_s8): Likewise.
8228 (__arm_vmulltq_int_s8): Likewise.
8229 (__arm_vmullbq_int_s8): Likewise.
8230 (__arm_vmulhq_s8): Likewise.
8231 (__arm_vmlsdavxq_s8): Likewise.
8232 (__arm_vmlsdavq_s8): Likewise.
8233 (__arm_vmladavxq_s8): Likewise.
8234 (__arm_vmladavq_s8): Likewise.
8235 (__arm_vminvq_s8): Likewise.
8236 (__arm_vminq_s8): Likewise.
8237 (__arm_vmaxvq_s8): Likewise.
8238 (__arm_vmaxq_s8): Likewise.
8239 (__arm_vhsubq_s8): Likewise.
8240 (__arm_vhsubq_n_s8): Likewise.
8241 (__arm_vhcaddq_rot90_s8): Likewise.
8242 (__arm_vhcaddq_rot270_s8): Likewise.
8243 (__arm_vhaddq_s8): Likewise.
8244 (__arm_vhaddq_n_s8): Likewise.
8245 (__arm_veorq_s8): Likewise.
8246 (__arm_vcaddq_rot90_s8): Likewise.
8247 (__arm_vcaddq_rot270_s8): Likewise.
8248 (__arm_vbrsrq_n_s8): Likewise.
8249 (__arm_vbicq_s8): Likewise.
8250 (__arm_vandq_s8): Likewise.
8251 (__arm_vaddvaq_s8): Likewise.
8252 (__arm_vaddq_n_s8): Likewise.
8253 (__arm_vabdq_s8): Likewise.
8254 (__arm_vshlq_n_s8): Likewise.
8255 (__arm_vrshrq_n_s8): Likewise.
8256 (__arm_vqshlq_n_s8): Likewise.
8257 (__arm_vsubq_u16): Likewise.
8258 (__arm_vsubq_n_u16): Likewise.
8259 (__arm_vrmulhq_u16): Likewise.
8260 (__arm_vrhaddq_u16): Likewise.
8261 (__arm_vqsubq_u16): Likewise.
8262 (__arm_vqsubq_n_u16): Likewise.
8263 (__arm_vqaddq_u16): Likewise.
8264 (__arm_vqaddq_n_u16): Likewise.
8265 (__arm_vorrq_u16): Likewise.
8266 (__arm_vornq_u16): Likewise.
8267 (__arm_vmulq_u16): Likewise.
8268 (__arm_vmulq_n_u16): Likewise.
8269 (__arm_vmulltq_int_u16): Likewise.
8270 (__arm_vmullbq_int_u16): Likewise.
8271 (__arm_vmulhq_u16): Likewise.
8272 (__arm_vmladavq_u16): Likewise.
8273 (__arm_vminvq_u16): Likewise.
8274 (__arm_vminq_u16): Likewise.
8275 (__arm_vmaxvq_u16): Likewise.
8276 (__arm_vmaxq_u16): Likewise.
8277 (__arm_vhsubq_u16): Likewise.
8278 (__arm_vhsubq_n_u16): Likewise.
8279 (__arm_vhaddq_u16): Likewise.
8280 (__arm_vhaddq_n_u16): Likewise.
8281 (__arm_veorq_u16): Likewise.
8282 (__arm_vcmpneq_n_u16): Likewise.
8283 (__arm_vcmphiq_u16): Likewise.
8284 (__arm_vcmphiq_n_u16): Likewise.
8285 (__arm_vcmpeqq_u16): Likewise.
8286 (__arm_vcmpeqq_n_u16): Likewise.
8287 (__arm_vcmpcsq_u16): Likewise.
8288 (__arm_vcmpcsq_n_u16): Likewise.
8289 (__arm_vcaddq_rot90_u16): Likewise.
8290 (__arm_vcaddq_rot270_u16): Likewise.
8291 (__arm_vbicq_u16): Likewise.
8292 (__arm_vandq_u16): Likewise.
8293 (__arm_vaddvq_p_u16): Likewise.
8294 (__arm_vaddvaq_u16): Likewise.
8295 (__arm_vaddq_n_u16): Likewise.
8296 (__arm_vabdq_u16): Likewise.
8297 (__arm_vshlq_r_u16): Likewise.
8298 (__arm_vrshlq_u16): Likewise.
8299 (__arm_vrshlq_n_u16): Likewise.
8300 (__arm_vqshlq_u16): Likewise.
8301 (__arm_vqshlq_r_u16): Likewise.
8302 (__arm_vqrshlq_u16): Likewise.
8303 (__arm_vqrshlq_n_u16): Likewise.
8304 (__arm_vminavq_s16): Likewise.
8305 (__arm_vminaq_s16): Likewise.
8306 (__arm_vmaxavq_s16): Likewise.
8307 (__arm_vmaxaq_s16): Likewise.
8308 (__arm_vbrsrq_n_u16): Likewise.
8309 (__arm_vshlq_n_u16): Likewise.
8310 (__arm_vrshrq_n_u16): Likewise.
8311 (__arm_vqshlq_n_u16): Likewise.
8312 (__arm_vcmpneq_n_s16): Likewise.
8313 (__arm_vcmpltq_s16): Likewise.
8314 (__arm_vcmpltq_n_s16): Likewise.
8315 (__arm_vcmpleq_s16): Likewise.
8316 (__arm_vcmpleq_n_s16): Likewise.
8317 (__arm_vcmpgtq_s16): Likewise.
8318 (__arm_vcmpgtq_n_s16): Likewise.
8319 (__arm_vcmpgeq_s16): Likewise.
8320 (__arm_vcmpgeq_n_s16): Likewise.
8321 (__arm_vcmpeqq_s16): Likewise.
8322 (__arm_vcmpeqq_n_s16): Likewise.
8323 (__arm_vqshluq_n_s16): Likewise.
8324 (__arm_vaddvq_p_s16): Likewise.
8325 (__arm_vsubq_s16): Likewise.
8326 (__arm_vsubq_n_s16): Likewise.
8327 (__arm_vshlq_r_s16): Likewise.
8328 (__arm_vrshlq_s16): Likewise.
8329 (__arm_vrshlq_n_s16): Likewise.
8330 (__arm_vrmulhq_s16): Likewise.
8331 (__arm_vrhaddq_s16): Likewise.
8332 (__arm_vqsubq_s16): Likewise.
8333 (__arm_vqsubq_n_s16): Likewise.
8334 (__arm_vqshlq_s16): Likewise.
8335 (__arm_vqshlq_r_s16): Likewise.
8336 (__arm_vqrshlq_s16): Likewise.
8337 (__arm_vqrshlq_n_s16): Likewise.
8338 (__arm_vqrdmulhq_s16): Likewise.
8339 (__arm_vqrdmulhq_n_s16): Likewise.
8340 (__arm_vqdmulhq_s16): Likewise.
8341 (__arm_vqdmulhq_n_s16): Likewise.
8342 (__arm_vqaddq_s16): Likewise.
8343 (__arm_vqaddq_n_s16): Likewise.
8344 (__arm_vorrq_s16): Likewise.
8345 (__arm_vornq_s16): Likewise.
8346 (__arm_vmulq_s16): Likewise.
8347 (__arm_vmulq_n_s16): Likewise.
8348 (__arm_vmulltq_int_s16): Likewise.
8349 (__arm_vmullbq_int_s16): Likewise.
8350 (__arm_vmulhq_s16): Likewise.
8351 (__arm_vmlsdavxq_s16): Likewise.
8352 (__arm_vmlsdavq_s16): Likewise.
8353 (__arm_vmladavxq_s16): Likewise.
8354 (__arm_vmladavq_s16): Likewise.
8355 (__arm_vminvq_s16): Likewise.
8356 (__arm_vminq_s16): Likewise.
8357 (__arm_vmaxvq_s16): Likewise.
8358 (__arm_vmaxq_s16): Likewise.
8359 (__arm_vhsubq_s16): Likewise.
8360 (__arm_vhsubq_n_s16): Likewise.
8361 (__arm_vhcaddq_rot90_s16): Likewise.
8362 (__arm_vhcaddq_rot270_s16): Likewise.
8363 (__arm_vhaddq_s16): Likewise.
8364 (__arm_vhaddq_n_s16): Likewise.
8365 (__arm_veorq_s16): Likewise.
8366 (__arm_vcaddq_rot90_s16): Likewise.
8367 (__arm_vcaddq_rot270_s16): Likewise.
8368 (__arm_vbrsrq_n_s16): Likewise.
8369 (__arm_vbicq_s16): Likewise.
8370 (__arm_vandq_s16): Likewise.
8371 (__arm_vaddvaq_s16): Likewise.
8372 (__arm_vaddq_n_s16): Likewise.
8373 (__arm_vabdq_s16): Likewise.
8374 (__arm_vshlq_n_s16): Likewise.
8375 (__arm_vrshrq_n_s16): Likewise.
8376 (__arm_vqshlq_n_s16): Likewise.
8377 (__arm_vsubq_u32): Likewise.
8378 (__arm_vsubq_n_u32): Likewise.
8379 (__arm_vrmulhq_u32): Likewise.
8380 (__arm_vrhaddq_u32): Likewise.
8381 (__arm_vqsubq_u32): Likewise.
8382 (__arm_vqsubq_n_u32): Likewise.
8383 (__arm_vqaddq_u32): Likewise.
8384 (__arm_vqaddq_n_u32): Likewise.
8385 (__arm_vorrq_u32): Likewise.
8386 (__arm_vornq_u32): Likewise.
8387 (__arm_vmulq_u32): Likewise.
8388 (__arm_vmulq_n_u32): Likewise.
8389 (__arm_vmulltq_int_u32): Likewise.
8390 (__arm_vmullbq_int_u32): Likewise.
8391 (__arm_vmulhq_u32): Likewise.
8392 (__arm_vmladavq_u32): Likewise.
8393 (__arm_vminvq_u32): Likewise.
8394 (__arm_vminq_u32): Likewise.
8395 (__arm_vmaxvq_u32): Likewise.
8396 (__arm_vmaxq_u32): Likewise.
8397 (__arm_vhsubq_u32): Likewise.
8398 (__arm_vhsubq_n_u32): Likewise.
8399 (__arm_vhaddq_u32): Likewise.
8400 (__arm_vhaddq_n_u32): Likewise.
8401 (__arm_veorq_u32): Likewise.
8402 (__arm_vcmpneq_n_u32): Likewise.
8403 (__arm_vcmphiq_u32): Likewise.
8404 (__arm_vcmphiq_n_u32): Likewise.
8405 (__arm_vcmpeqq_u32): Likewise.
8406 (__arm_vcmpeqq_n_u32): Likewise.
8407 (__arm_vcmpcsq_u32): Likewise.
8408 (__arm_vcmpcsq_n_u32): Likewise.
8409 (__arm_vcaddq_rot90_u32): Likewise.
8410 (__arm_vcaddq_rot270_u32): Likewise.
8411 (__arm_vbicq_u32): Likewise.
8412 (__arm_vandq_u32): Likewise.
8413 (__arm_vaddvq_p_u32): Likewise.
8414 (__arm_vaddvaq_u32): Likewise.
8415 (__arm_vaddq_n_u32): Likewise.
8416 (__arm_vabdq_u32): Likewise.
8417 (__arm_vshlq_r_u32): Likewise.
8418 (__arm_vrshlq_u32): Likewise.
8419 (__arm_vrshlq_n_u32): Likewise.
8420 (__arm_vqshlq_u32): Likewise.
8421 (__arm_vqshlq_r_u32): Likewise.
8422 (__arm_vqrshlq_u32): Likewise.
8423 (__arm_vqrshlq_n_u32): Likewise.
8424 (__arm_vminavq_s32): Likewise.
8425 (__arm_vminaq_s32): Likewise.
8426 (__arm_vmaxavq_s32): Likewise.
8427 (__arm_vmaxaq_s32): Likewise.
8428 (__arm_vbrsrq_n_u32): Likewise.
8429 (__arm_vshlq_n_u32): Likewise.
8430 (__arm_vrshrq_n_u32): Likewise.
8431 (__arm_vqshlq_n_u32): Likewise.
8432 (__arm_vcmpneq_n_s32): Likewise.
8433 (__arm_vcmpltq_s32): Likewise.
8434 (__arm_vcmpltq_n_s32): Likewise.
8435 (__arm_vcmpleq_s32): Likewise.
8436 (__arm_vcmpleq_n_s32): Likewise.
8437 (__arm_vcmpgtq_s32): Likewise.
8438 (__arm_vcmpgtq_n_s32): Likewise.
8439 (__arm_vcmpgeq_s32): Likewise.
8440 (__arm_vcmpgeq_n_s32): Likewise.
8441 (__arm_vcmpeqq_s32): Likewise.
8442 (__arm_vcmpeqq_n_s32): Likewise.
8443 (__arm_vqshluq_n_s32): Likewise.
8444 (__arm_vaddvq_p_s32): Likewise.
8445 (__arm_vsubq_s32): Likewise.
8446 (__arm_vsubq_n_s32): Likewise.
8447 (__arm_vshlq_r_s32): Likewise.
8448 (__arm_vrshlq_s32): Likewise.
8449 (__arm_vrshlq_n_s32): Likewise.
8450 (__arm_vrmulhq_s32): Likewise.
8451 (__arm_vrhaddq_s32): Likewise.
8452 (__arm_vqsubq_s32): Likewise.
8453 (__arm_vqsubq_n_s32): Likewise.
8454 (__arm_vqshlq_s32): Likewise.
8455 (__arm_vqshlq_r_s32): Likewise.
8456 (__arm_vqrshlq_s32): Likewise.
8457 (__arm_vqrshlq_n_s32): Likewise.
8458 (__arm_vqrdmulhq_s32): Likewise.
8459 (__arm_vqrdmulhq_n_s32): Likewise.
8460 (__arm_vqdmulhq_s32): Likewise.
8461 (__arm_vqdmulhq_n_s32): Likewise.
8462 (__arm_vqaddq_s32): Likewise.
8463 (__arm_vqaddq_n_s32): Likewise.
8464 (__arm_vorrq_s32): Likewise.
8465 (__arm_vornq_s32): Likewise.
8466 (__arm_vmulq_s32): Likewise.
8467 (__arm_vmulq_n_s32): Likewise.
8468 (__arm_vmulltq_int_s32): Likewise.
8469 (__arm_vmullbq_int_s32): Likewise.
8470 (__arm_vmulhq_s32): Likewise.
8471 (__arm_vmlsdavxq_s32): Likewise.
8472 (__arm_vmlsdavq_s32): Likewise.
8473 (__arm_vmladavxq_s32): Likewise.
8474 (__arm_vmladavq_s32): Likewise.
8475 (__arm_vminvq_s32): Likewise.
8476 (__arm_vminq_s32): Likewise.
8477 (__arm_vmaxvq_s32): Likewise.
8478 (__arm_vmaxq_s32): Likewise.
8479 (__arm_vhsubq_s32): Likewise.
8480 (__arm_vhsubq_n_s32): Likewise.
8481 (__arm_vhcaddq_rot90_s32): Likewise.
8482 (__arm_vhcaddq_rot270_s32): Likewise.
8483 (__arm_vhaddq_s32): Likewise.
8484 (__arm_vhaddq_n_s32): Likewise.
8485 (__arm_veorq_s32): Likewise.
8486 (__arm_vcaddq_rot90_s32): Likewise.
8487 (__arm_vcaddq_rot270_s32): Likewise.
8488 (__arm_vbrsrq_n_s32): Likewise.
8489 (__arm_vbicq_s32): Likewise.
8490 (__arm_vandq_s32): Likewise.
8491 (__arm_vaddvaq_s32): Likewise.
8492 (__arm_vaddq_n_s32): Likewise.
8493 (__arm_vabdq_s32): Likewise.
8494 (__arm_vshlq_n_s32): Likewise.
8495 (__arm_vrshrq_n_s32): Likewise.
8496 (__arm_vqshlq_n_s32): Likewise.
8497 (vsubq): Define polymorphic variant.
8498 (vsubq_n): Likewise.
8499 (vshlq_r): Likewise.
8500 (vrshlq_n): Likewise.
8502 (vrmulhq): Likewise.
8503 (vrhaddq): Likewise.
8504 (vqsubq_n): Likewise.
8507 (vqshlq_r): Likewise.
8508 (vqshluq): Likewise.
8509 (vrshrq_n): Likewise.
8510 (vshlq_n): Likewise.
8511 (vqshluq_n): Likewise.
8512 (vqshlq_n): Likewise.
8513 (vqrshlq_n): Likewise.
8514 (vqrshlq): Likewise.
8515 (vqrdmulhq_n): Likewise.
8516 (vqrdmulhq): Likewise.
8517 (vqdmulhq_n): Likewise.
8518 (vqdmulhq): Likewise.
8519 (vqaddq_n): Likewise.
8521 (vorrq_n): Likewise.
8524 (vmulq_n): Likewise.
8526 (vmulltq_int): Likewise.
8527 (vmullbq_int): Likewise.
8533 (vhsubq_n): Likewise.
8535 (vhcaddq_rot90): Likewise.
8536 (vhcaddq_rot270): Likewise.
8537 (vhaddq_n): Likewise.
8540 (vcaddq_rot90): Likewise.
8541 (vcaddq_rot270): Likewise.
8542 (vbrsrq_n): Likewise.
8543 (vbicq_n): Likewise.
8546 (vaddq_n): Likewise.
8549 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
8550 (BINOP_NONE_NONE_NONE): Likewise.
8551 (BINOP_NONE_NONE_UNONE): Likewise.
8552 (BINOP_UNONE_NONE_IMM): Likewise.
8553 (BINOP_UNONE_NONE_NONE): Likewise.
8554 (BINOP_UNONE_UNONE_IMM): Likewise.
8555 (BINOP_UNONE_UNONE_NONE): Likewise.
8556 (BINOP_UNONE_UNONE_UNONE): Likewise.
8557 * config/arm/constraints.md (Ra): Define constraint to check constant is
8558 in the range of 0 to 7.
8559 (Rg): Define constriant to check the constant is one among 1, 2, 4
8561 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
8562 (mve_vaddq_n_<supf>): Likewise.
8563 (mve_vaddvaq_<supf>): Likewise.
8564 (mve_vaddvq_p_<supf>): Likewise.
8565 (mve_vandq_<supf>): Likewise.
8566 (mve_vbicq_<supf>): Likewise.
8567 (mve_vbrsrq_n_<supf>): Likewise.
8568 (mve_vcaddq_rot270_<supf>): Likewise.
8569 (mve_vcaddq_rot90_<supf>): Likewise.
8570 (mve_vcmpcsq_n_u): Likewise.
8571 (mve_vcmpcsq_u): Likewise.
8572 (mve_vcmpeqq_n_<supf>): Likewise.
8573 (mve_vcmpeqq_<supf>): Likewise.
8574 (mve_vcmpgeq_n_s): Likewise.
8575 (mve_vcmpgeq_s): Likewise.
8576 (mve_vcmpgtq_n_s): Likewise.
8577 (mve_vcmpgtq_s): Likewise.
8578 (mve_vcmphiq_n_u): Likewise.
8579 (mve_vcmphiq_u): Likewise.
8580 (mve_vcmpleq_n_s): Likewise.
8581 (mve_vcmpleq_s): Likewise.
8582 (mve_vcmpltq_n_s): Likewise.
8583 (mve_vcmpltq_s): Likewise.
8584 (mve_vcmpneq_n_<supf>): Likewise.
8585 (mve_vddupq_n_u): Likewise.
8586 (mve_veorq_<supf>): Likewise.
8587 (mve_vhaddq_n_<supf>): Likewise.
8588 (mve_vhaddq_<supf>): Likewise.
8589 (mve_vhcaddq_rot270_s): Likewise.
8590 (mve_vhcaddq_rot90_s): Likewise.
8591 (mve_vhsubq_n_<supf>): Likewise.
8592 (mve_vhsubq_<supf>): Likewise.
8593 (mve_vidupq_n_u): Likewise.
8594 (mve_vmaxaq_s): Likewise.
8595 (mve_vmaxavq_s): Likewise.
8596 (mve_vmaxq_<supf>): Likewise.
8597 (mve_vmaxvq_<supf>): Likewise.
8598 (mve_vminaq_s): Likewise.
8599 (mve_vminavq_s): Likewise.
8600 (mve_vminq_<supf>): Likewise.
8601 (mve_vminvq_<supf>): Likewise.
8602 (mve_vmladavq_<supf>): Likewise.
8603 (mve_vmladavxq_s): Likewise.
8604 (mve_vmlsdavq_s): Likewise.
8605 (mve_vmlsdavxq_s): Likewise.
8606 (mve_vmulhq_<supf>): Likewise.
8607 (mve_vmullbq_int_<supf>): Likewise.
8608 (mve_vmulltq_int_<supf>): Likewise.
8609 (mve_vmulq_n_<supf>): Likewise.
8610 (mve_vmulq_<supf>): Likewise.
8611 (mve_vornq_<supf>): Likewise.
8612 (mve_vorrq_<supf>): Likewise.
8613 (mve_vqaddq_n_<supf>): Likewise.
8614 (mve_vqaddq_<supf>): Likewise.
8615 (mve_vqdmulhq_n_s): Likewise.
8616 (mve_vqdmulhq_s): Likewise.
8617 (mve_vqrdmulhq_n_s): Likewise.
8618 (mve_vqrdmulhq_s): Likewise.
8619 (mve_vqrshlq_n_<supf>): Likewise.
8620 (mve_vqrshlq_<supf>): Likewise.
8621 (mve_vqshlq_n_<supf>): Likewise.
8622 (mve_vqshlq_r_<supf>): Likewise.
8623 (mve_vqshlq_<supf>): Likewise.
8624 (mve_vqshluq_n_s): Likewise.
8625 (mve_vqsubq_n_<supf>): Likewise.
8626 (mve_vqsubq_<supf>): Likewise.
8627 (mve_vrhaddq_<supf>): Likewise.
8628 (mve_vrmulhq_<supf>): Likewise.
8629 (mve_vrshlq_n_<supf>): Likewise.
8630 (mve_vrshlq_<supf>): Likewise.
8631 (mve_vrshrq_n_<supf>): Likewise.
8632 (mve_vshlq_n_<supf>): Likewise.
8633 (mve_vshlq_r_<supf>): Likewise.
8634 (mve_vsubq_n_<supf>): Likewise.
8635 (mve_vsubq_<supf>): Likewise.
8636 * config/arm/predicates.md (mve_imm_7): Define predicate to check
8637 the matching constraint Ra.
8638 (mve_imm_selective_upto_8): Define predicate to check the matching
8641 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8642 Mihail Ionescu <mihail.ionescu@arm.com>
8643 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8645 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
8646 qualifier for binary operands.
8647 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
8648 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
8649 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
8650 (vaddlvq_p_u32): Likewise.
8651 (vcmpneq_s8): Likewise.
8652 (vcmpneq_s16): Likewise.
8653 (vcmpneq_s32): Likewise.
8654 (vcmpneq_u8): Likewise.
8655 (vcmpneq_u16): Likewise.
8656 (vcmpneq_u32): Likewise.
8657 (vshlq_s8): Likewise.
8658 (vshlq_s16): Likewise.
8659 (vshlq_s32): Likewise.
8660 (vshlq_u8): Likewise.
8661 (vshlq_u16): Likewise.
8662 (vshlq_u32): Likewise.
8663 (__arm_vaddlvq_p_s32): Define intrinsic.
8664 (__arm_vaddlvq_p_u32): Likewise.
8665 (__arm_vcmpneq_s8): Likewise.
8666 (__arm_vcmpneq_s16): Likewise.
8667 (__arm_vcmpneq_s32): Likewise.
8668 (__arm_vcmpneq_u8): Likewise.
8669 (__arm_vcmpneq_u16): Likewise.
8670 (__arm_vcmpneq_u32): Likewise.
8671 (__arm_vshlq_s8): Likewise.
8672 (__arm_vshlq_s16): Likewise.
8673 (__arm_vshlq_s32): Likewise.
8674 (__arm_vshlq_u8): Likewise.
8675 (__arm_vshlq_u16): Likewise.
8676 (__arm_vshlq_u32): Likewise.
8677 (vaddlvq_p): Define polymorphic variant.
8678 (vcmpneq): Likewise.
8680 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
8682 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
8683 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
8684 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
8685 (mve_vcmpneq_<supf><mode>): Likewise.
8686 (mve_vshlq_<supf><mode>): Likewise.
8688 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8689 Mihail Ionescu <mihail.ionescu@arm.com>
8690 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8692 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
8693 qualifier for binary operands.
8694 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8695 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
8696 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
8697 (vcvtq_n_s32_f32): Likewise.
8698 (vcvtq_n_u16_f16): Likewise.
8699 (vcvtq_n_u32_f32): Likewise.
8700 (vcreateq_u8): Likewise.
8701 (vcreateq_u16): Likewise.
8702 (vcreateq_u32): Likewise.
8703 (vcreateq_u64): Likewise.
8704 (vcreateq_s8): Likewise.
8705 (vcreateq_s16): Likewise.
8706 (vcreateq_s32): Likewise.
8707 (vcreateq_s64): Likewise.
8708 (vshrq_n_s8): Likewise.
8709 (vshrq_n_s16): Likewise.
8710 (vshrq_n_s32): Likewise.
8711 (vshrq_n_u8): Likewise.
8712 (vshrq_n_u16): Likewise.
8713 (vshrq_n_u32): Likewise.
8714 (__arm_vcreateq_u8): Define intrinsic.
8715 (__arm_vcreateq_u16): Likewise.
8716 (__arm_vcreateq_u32): Likewise.
8717 (__arm_vcreateq_u64): Likewise.
8718 (__arm_vcreateq_s8): Likewise.
8719 (__arm_vcreateq_s16): Likewise.
8720 (__arm_vcreateq_s32): Likewise.
8721 (__arm_vcreateq_s64): Likewise.
8722 (__arm_vshrq_n_s8): Likewise.
8723 (__arm_vshrq_n_s16): Likewise.
8724 (__arm_vshrq_n_s32): Likewise.
8725 (__arm_vshrq_n_u8): Likewise.
8726 (__arm_vshrq_n_u16): Likewise.
8727 (__arm_vshrq_n_u32): Likewise.
8728 (__arm_vcvtq_n_s16_f16): Likewise.
8729 (__arm_vcvtq_n_s32_f32): Likewise.
8730 (__arm_vcvtq_n_u16_f16): Likewise.
8731 (__arm_vcvtq_n_u32_f32): Likewise.
8732 (vshrq_n): Define polymorphic variant.
8733 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
8735 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8736 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
8737 * config/arm/constraints.md (Rb): Define constraint to check constant is
8738 in the range of 1 to 8.
8739 (Rf): Define constraint to check constant is in the range of 1 to 32.
8740 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
8741 (mve_vshrq_n_<supf><mode>): Likewise.
8742 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
8743 * config/arm/predicates.md (mve_imm_8): Define predicate to check
8744 the matching constraint Rb.
8745 (mve_imm_32): Define predicate to check the matching constraint Rf.
8747 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8748 Mihail Ionescu <mihail.ionescu@arm.com>
8749 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8751 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
8752 qualifier for binary operands.
8753 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
8754 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
8755 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
8756 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
8757 (vsubq_n_f32): Likewise.
8758 (vbrsrq_n_f16): Likewise.
8759 (vbrsrq_n_f32): Likewise.
8760 (vcvtq_n_f16_s16): Likewise.
8761 (vcvtq_n_f32_s32): Likewise.
8762 (vcvtq_n_f16_u16): Likewise.
8763 (vcvtq_n_f32_u32): Likewise.
8764 (vcreateq_f16): Likewise.
8765 (vcreateq_f32): Likewise.
8766 (__arm_vsubq_n_f16): Define intrinsic.
8767 (__arm_vsubq_n_f32): Likewise.
8768 (__arm_vbrsrq_n_f16): Likewise.
8769 (__arm_vbrsrq_n_f32): Likewise.
8770 (__arm_vcvtq_n_f16_s16): Likewise.
8771 (__arm_vcvtq_n_f32_s32): Likewise.
8772 (__arm_vcvtq_n_f16_u16): Likewise.
8773 (__arm_vcvtq_n_f32_u32): Likewise.
8774 (__arm_vcreateq_f16): Likewise.
8775 (__arm_vcreateq_f32): Likewise.
8776 (vsubq): Define polymorphic variant.
8778 (vcvtq_n): Likewise.
8779 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
8781 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
8782 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
8783 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
8784 * config/arm/constraints.md (Rd): Define constraint to check constant is
8785 in the range of 1 to 16.
8786 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
8787 mve_vbrsrq_n_f<mode>: Likewise.
8788 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
8789 mve_vcreateq_f<mode>: Likewise.
8790 * config/arm/predicates.md (mve_imm_16): Define predicate to check
8791 the matching constraint Rd.
8793 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8794 Mihail Ionescu <mihail.ionescu@arm.com>
8795 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8797 * config/arm/arm-builtins.c (hi_UP): Define mode.
8798 * config/arm/arm.h (IS_VPR_REGNUM): Move.
8799 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
8800 (APSRQ_REGNUM): Modify.
8801 (APSRGE_REGNUM): Modify.
8802 * config/arm/arm_mve.h (vctp16q): Define macro.
8803 (vctp32q): Likewise.
8804 (vctp64q): Likewise.
8807 (__arm_vctp16q): Define intrinsic.
8808 (__arm_vctp32q): Likewise.
8809 (__arm_vctp64q): Likewise.
8810 (__arm_vctp8q): Likewise.
8811 (__arm_vpnot): Likewise.
8812 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
8814 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
8815 (mve_vpnothi): Likewise.
8817 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8818 Mihail Ionescu <mihail.ionescu@arm.com>
8819 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8821 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
8822 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
8823 (vdupq_n_s16): Likewise.
8824 (vdupq_n_s32): Likewise.
8825 (vabsq_s8): Likewise.
8826 (vabsq_s16): Likewise.
8827 (vabsq_s32): Likewise.
8828 (vclsq_s8): Likewise.
8829 (vclsq_s16): Likewise.
8830 (vclsq_s32): Likewise.
8831 (vclzq_s8): Likewise.
8832 (vclzq_s16): Likewise.
8833 (vclzq_s32): Likewise.
8834 (vnegq_s8): Likewise.
8835 (vnegq_s16): Likewise.
8836 (vnegq_s32): Likewise.
8837 (vaddlvq_s32): Likewise.
8838 (vaddvq_s8): Likewise.
8839 (vaddvq_s16): Likewise.
8840 (vaddvq_s32): Likewise.
8841 (vmovlbq_s8): Likewise.
8842 (vmovlbq_s16): Likewise.
8843 (vmovltq_s8): Likewise.
8844 (vmovltq_s16): Likewise.
8845 (vmvnq_s8): Likewise.
8846 (vmvnq_s16): Likewise.
8847 (vmvnq_s32): Likewise.
8848 (vrev16q_s8): Likewise.
8849 (vrev32q_s8): Likewise.
8850 (vrev32q_s16): Likewise.
8851 (vqabsq_s8): Likewise.
8852 (vqabsq_s16): Likewise.
8853 (vqabsq_s32): Likewise.
8854 (vqnegq_s8): Likewise.
8855 (vqnegq_s16): Likewise.
8856 (vqnegq_s32): Likewise.
8857 (vcvtaq_s16_f16): Likewise.
8858 (vcvtaq_s32_f32): Likewise.
8859 (vcvtnq_s16_f16): Likewise.
8860 (vcvtnq_s32_f32): Likewise.
8861 (vcvtpq_s16_f16): Likewise.
8862 (vcvtpq_s32_f32): Likewise.
8863 (vcvtmq_s16_f16): Likewise.
8864 (vcvtmq_s32_f32): Likewise.
8865 (vmvnq_u8): Likewise.
8866 (vmvnq_u16): Likewise.
8867 (vmvnq_u32): Likewise.
8868 (vdupq_n_u8): Likewise.
8869 (vdupq_n_u16): Likewise.
8870 (vdupq_n_u32): Likewise.
8871 (vclzq_u8): Likewise.
8872 (vclzq_u16): Likewise.
8873 (vclzq_u32): Likewise.
8874 (vaddvq_u8): Likewise.
8875 (vaddvq_u16): Likewise.
8876 (vaddvq_u32): Likewise.
8877 (vrev32q_u8): Likewise.
8878 (vrev32q_u16): Likewise.
8879 (vmovltq_u8): Likewise.
8880 (vmovltq_u16): Likewise.
8881 (vmovlbq_u8): Likewise.
8882 (vmovlbq_u16): Likewise.
8883 (vrev16q_u8): Likewise.
8884 (vaddlvq_u32): Likewise.
8885 (vcvtpq_u16_f16): Likewise.
8886 (vcvtpq_u32_f32): Likewise.
8887 (vcvtnq_u16_f16): Likewise.
8888 (vcvtmq_u16_f16): Likewise.
8889 (vcvtmq_u32_f32): Likewise.
8890 (vcvtaq_u16_f16): Likewise.
8891 (vcvtaq_u32_f32): Likewise.
8892 (__arm_vdupq_n_s8): Define intrinsic.
8893 (__arm_vdupq_n_s16): Likewise.
8894 (__arm_vdupq_n_s32): Likewise.
8895 (__arm_vabsq_s8): Likewise.
8896 (__arm_vabsq_s16): Likewise.
8897 (__arm_vabsq_s32): Likewise.
8898 (__arm_vclsq_s8): Likewise.
8899 (__arm_vclsq_s16): Likewise.
8900 (__arm_vclsq_s32): Likewise.
8901 (__arm_vclzq_s8): Likewise.
8902 (__arm_vclzq_s16): Likewise.
8903 (__arm_vclzq_s32): Likewise.
8904 (__arm_vnegq_s8): Likewise.
8905 (__arm_vnegq_s16): Likewise.
8906 (__arm_vnegq_s32): Likewise.
8907 (__arm_vaddlvq_s32): Likewise.
8908 (__arm_vaddvq_s8): Likewise.
8909 (__arm_vaddvq_s16): Likewise.
8910 (__arm_vaddvq_s32): Likewise.
8911 (__arm_vmovlbq_s8): Likewise.
8912 (__arm_vmovlbq_s16): Likewise.
8913 (__arm_vmovltq_s8): Likewise.
8914 (__arm_vmovltq_s16): Likewise.
8915 (__arm_vmvnq_s8): Likewise.
8916 (__arm_vmvnq_s16): Likewise.
8917 (__arm_vmvnq_s32): Likewise.
8918 (__arm_vrev16q_s8): Likewise.
8919 (__arm_vrev32q_s8): Likewise.
8920 (__arm_vrev32q_s16): Likewise.
8921 (__arm_vqabsq_s8): Likewise.
8922 (__arm_vqabsq_s16): Likewise.
8923 (__arm_vqabsq_s32): Likewise.
8924 (__arm_vqnegq_s8): Likewise.
8925 (__arm_vqnegq_s16): Likewise.
8926 (__arm_vqnegq_s32): Likewise.
8927 (__arm_vmvnq_u8): Likewise.
8928 (__arm_vmvnq_u16): Likewise.
8929 (__arm_vmvnq_u32): Likewise.
8930 (__arm_vdupq_n_u8): Likewise.
8931 (__arm_vdupq_n_u16): Likewise.
8932 (__arm_vdupq_n_u32): Likewise.
8933 (__arm_vclzq_u8): Likewise.
8934 (__arm_vclzq_u16): Likewise.
8935 (__arm_vclzq_u32): Likewise.
8936 (__arm_vaddvq_u8): Likewise.
8937 (__arm_vaddvq_u16): Likewise.
8938 (__arm_vaddvq_u32): Likewise.
8939 (__arm_vrev32q_u8): Likewise.
8940 (__arm_vrev32q_u16): Likewise.
8941 (__arm_vmovltq_u8): Likewise.
8942 (__arm_vmovltq_u16): Likewise.
8943 (__arm_vmovlbq_u8): Likewise.
8944 (__arm_vmovlbq_u16): Likewise.
8945 (__arm_vrev16q_u8): Likewise.
8946 (__arm_vaddlvq_u32): Likewise.
8947 (__arm_vcvtpq_u16_f16): Likewise.
8948 (__arm_vcvtpq_u32_f32): Likewise.
8949 (__arm_vcvtnq_u16_f16): Likewise.
8950 (__arm_vcvtmq_u16_f16): Likewise.
8951 (__arm_vcvtmq_u32_f32): Likewise.
8952 (__arm_vcvtaq_u16_f16): Likewise.
8953 (__arm_vcvtaq_u32_f32): Likewise.
8954 (__arm_vcvtaq_s16_f16): Likewise.
8955 (__arm_vcvtaq_s32_f32): Likewise.
8956 (__arm_vcvtnq_s16_f16): Likewise.
8957 (__arm_vcvtnq_s32_f32): Likewise.
8958 (__arm_vcvtpq_s16_f16): Likewise.
8959 (__arm_vcvtpq_s32_f32): Likewise.
8960 (__arm_vcvtmq_s16_f16): Likewise.
8961 (__arm_vcvtmq_s32_f32): Likewise.
8962 (vdupq_n): Define polymorphic variant.
8967 (vaddlvq): Likewise.
8969 (vmovlbq): Likewise.
8970 (vmovltq): Likewise.
8972 (vrev16q): Likewise.
8973 (vrev32q): Likewise.
8976 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
8977 (UNOP_SNONE_NONE): Likewise.
8978 (UNOP_UNONE_UNONE): Likewise.
8979 (UNOP_UNONE_NONE): Likewise.
8980 * config/arm/constraints.md (e): Define new constriant to allow only
8982 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
8983 (mve_vnegq_s<mode>): Likewise.
8984 (mve_vmvnq_<supf><mode>): Likewise.
8985 (mve_vdupq_n_<supf><mode>): Likewise.
8986 (mve_vclzq_<supf><mode>): Likewise.
8987 (mve_vclsq_s<mode>): Likewise.
8988 (mve_vaddvq_<supf><mode>): Likewise.
8989 (mve_vabsq_s<mode>): Likewise.
8990 (mve_vrev32q_<supf><mode>): Likewise.
8991 (mve_vmovltq_<supf><mode>): Likewise.
8992 (mve_vmovlbq_<supf><mode>): Likewise.
8993 (mve_vcvtpq_<supf><mode>): Likewise.
8994 (mve_vcvtnq_<supf><mode>): Likewise.
8995 (mve_vcvtmq_<supf><mode>): Likewise.
8996 (mve_vcvtaq_<supf><mode>): Likewise.
8997 (mve_vrev16q_<supf>v16qi): Likewise.
8998 (mve_vaddlvq_<supf>v4si): Likewise.
9000 2020-03-17 Jakub Jelinek <jakub@redhat.com>
9002 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
9004 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
9006 * read-rtl-function.c (find_param_by_name,
9007 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
9009 * spellcheck.c (get_edit_distance_cutoff): Likewise.
9010 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
9011 * tree.def (SWITCH_EXPR): Likewise.
9012 * selftest.c (assert_str_contains): Likewise.
9013 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
9015 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
9016 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
9017 * langhooks.h (struct lang_hooks_for_decls): Likewise.
9018 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
9019 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
9021 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
9022 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
9023 * tree.c (component_ref_size): Likewise.
9024 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
9025 * gimple-ssa-sprintf.c (get_string_length, format_string,
9026 format_directive): Likewise.
9027 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
9028 * input.c (string_concat_db::get_string_concatenation,
9029 test_lexer_string_locations_ucn4): Likewise.
9030 * cfgexpand.c (pass_expand::execute): Likewise.
9031 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
9032 maybe_diag_overlap): Likewise.
9033 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
9034 * shrink-wrap.c (spread_components): Likewise.
9035 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
9037 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
9039 * dwarf2out.c (dwarf2out_early_finish): Likewise.
9040 * gimple-ssa-store-merging.c: Likewise.
9041 * ira-costs.c (record_operand_costs): Likewise.
9042 * tree-vect-loop.c (vectorizable_reduction): Likewise.
9043 * target.def (dispatch): Likewise.
9044 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
9045 in documentation text.
9046 * doc/tm.texi: Regenerated.
9047 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
9048 duplicated word issue in a comment.
9049 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
9050 * config/i386/i386-features.c (remove_partial_avx_dependency):
9052 * config/msp430/msp430.c (msp430_select_section): Likewise.
9053 * config/gcn/gcn-run.c (load_image): Likewise.
9054 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
9055 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
9056 * config/aarch64/falkor-tag-collision-avoidance.c
9057 (single_dest_per_chain): Likewise.
9058 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
9059 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
9060 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
9061 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
9063 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
9064 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
9065 * config/rs6000/rs6000-logue.c
9066 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
9067 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
9068 Fix various other issues in the comment.
9070 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
9072 * config/arm/t-rmprofile: create new multilib for
9073 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
9076 2020-03-17 Jakub Jelinek <jakub@redhat.com>
9078 PR tree-optimization/94015
9079 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
9080 function where EXP is address of the bytes being stored rather than
9081 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
9082 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
9083 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
9084 calling native_encode_expr if host or target doesn't have 8-bit
9085 chars. Formatting fixes.
9086 (count_nonzero_bytes_addr): New function.
9088 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9089 Mihail Ionescu <mihail.ionescu@arm.com>
9090 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9092 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
9093 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
9094 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
9095 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
9096 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
9097 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
9098 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
9099 (vmvnq_n_s32): Likewise.
9100 (vrev64q_s8): Likewise.
9101 (vrev64q_s16): Likewise.
9102 (vrev64q_s32): Likewise.
9103 (vcvtq_s16_f16): Likewise.
9104 (vcvtq_s32_f32): Likewise.
9105 (vrev64q_u8): Likewise.
9106 (vrev64q_u16): Likewise.
9107 (vrev64q_u32): Likewise.
9108 (vmvnq_n_u16): Likewise.
9109 (vmvnq_n_u32): Likewise.
9110 (vcvtq_u16_f16): Likewise.
9111 (vcvtq_u32_f32): Likewise.
9112 (__arm_vmvnq_n_s16): Define intrinsic.
9113 (__arm_vmvnq_n_s32): Likewise.
9114 (__arm_vrev64q_s8): Likewise.
9115 (__arm_vrev64q_s16): Likewise.
9116 (__arm_vrev64q_s32): Likewise.
9117 (__arm_vrev64q_u8): Likewise.
9118 (__arm_vrev64q_u16): Likewise.
9119 (__arm_vrev64q_u32): Likewise.
9120 (__arm_vmvnq_n_u16): Likewise.
9121 (__arm_vmvnq_n_u32): Likewise.
9122 (__arm_vcvtq_s16_f16): Likewise.
9123 (__arm_vcvtq_s32_f32): Likewise.
9124 (__arm_vcvtq_u16_f16): Likewise.
9125 (__arm_vcvtq_u32_f32): Likewise.
9126 (vrev64q): Define polymorphic variant.
9127 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
9128 (UNOP_SNONE_NONE): Likewise.
9129 (UNOP_SNONE_IMM): Likewise.
9130 (UNOP_UNONE_UNONE): Likewise.
9131 (UNOP_UNONE_NONE): Likewise.
9132 (UNOP_UNONE_IMM): Likewise.
9133 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
9134 (mve_vcvtq_from_f_<supf><mode>): Likewise.
9135 (mve_vmvnq_n_<supf><mode>): Likewise.
9137 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9138 Mihail Ionescu <mihail.ionescu@arm.com>
9139 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9141 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
9142 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
9143 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
9144 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
9145 (vrndxq_f32): Likewise.
9146 (vrndq_f16) Likewise.
9147 (vrndq_f32): Likewise.
9148 (vrndpq_f16): Likewise.
9149 (vrndpq_f32): Likewise.
9150 (vrndnq_f16): Likewise.
9151 (vrndnq_f32): Likewise.
9152 (vrndmq_f16): Likewise.
9153 (vrndmq_f32): Likewise.
9154 (vrndaq_f16): Likewise.
9155 (vrndaq_f32): Likewise.
9156 (vrev64q_f16): Likewise.
9157 (vrev64q_f32): Likewise.
9158 (vnegq_f16): Likewise.
9159 (vnegq_f32): Likewise.
9160 (vdupq_n_f16): Likewise.
9161 (vdupq_n_f32): Likewise.
9162 (vabsq_f16): Likewise.
9163 (vabsq_f32): Likewise.
9164 (vrev32q_f16): Likewise.
9165 (vcvttq_f32_f16): Likewise.
9166 (vcvtbq_f32_f16): Likewise.
9167 (vcvtq_f16_s16): Likewise.
9168 (vcvtq_f32_s32): Likewise.
9169 (vcvtq_f16_u16): Likewise.
9170 (vcvtq_f32_u32): Likewise.
9171 (__arm_vrndxq_f16): Define intrinsic.
9172 (__arm_vrndxq_f32): Likewise.
9173 (__arm_vrndq_f16): Likewise.
9174 (__arm_vrndq_f32): Likewise.
9175 (__arm_vrndpq_f16): Likewise.
9176 (__arm_vrndpq_f32): Likewise.
9177 (__arm_vrndnq_f16): Likewise.
9178 (__arm_vrndnq_f32): Likewise.
9179 (__arm_vrndmq_f16): Likewise.
9180 (__arm_vrndmq_f32): Likewise.
9181 (__arm_vrndaq_f16): Likewise.
9182 (__arm_vrndaq_f32): Likewise.
9183 (__arm_vrev64q_f16): Likewise.
9184 (__arm_vrev64q_f32): Likewise.
9185 (__arm_vnegq_f16): Likewise.
9186 (__arm_vnegq_f32): Likewise.
9187 (__arm_vdupq_n_f16): Likewise.
9188 (__arm_vdupq_n_f32): Likewise.
9189 (__arm_vabsq_f16): Likewise.
9190 (__arm_vabsq_f32): Likewise.
9191 (__arm_vrev32q_f16): Likewise.
9192 (__arm_vcvttq_f32_f16): Likewise.
9193 (__arm_vcvtbq_f32_f16): Likewise.
9194 (__arm_vcvtq_f16_s16): Likewise.
9195 (__arm_vcvtq_f32_s32): Likewise.
9196 (__arm_vcvtq_f16_u16): Likewise.
9197 (__arm_vcvtq_f32_u32): Likewise.
9198 (vrndxq): Define polymorphic variants.
9204 (vrev64q): Likewise.
9207 (vrev32q): Likewise.
9208 (vcvtbq_f32): Likewise.
9209 (vcvttq_f32): Likewise.
9211 * config/arm/arm_mve_builtins.def (VAR2): Define.
9213 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
9214 (mve_vrndq_f<mode>): Likewise.
9215 (mve_vrndpq_f<mode>): Likewise.
9216 (mve_vrndnq_f<mode>): Likewise.
9217 (mve_vrndmq_f<mode>): Likewise.
9218 (mve_vrndaq_f<mode>): Likewise.
9219 (mve_vrev64q_f<mode>): Likewise.
9220 (mve_vnegq_f<mode>): Likewise.
9221 (mve_vdupq_n_f<mode>): Likewise.
9222 (mve_vabsq_f<mode>): Likewise.
9223 (mve_vrev32q_fv8hf): Likewise.
9224 (mve_vcvttq_f32_f16v4sf): Likewise.
9225 (mve_vcvtbq_f32_f16v4sf): Likewise.
9226 (mve_vcvtq_to_f_<supf><mode>): Likewise.
9228 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9229 Mihail Ionescu <mihail.ionescu@arm.com>
9230 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9232 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
9234 (ARM_BUILTIN_MVE_PATTERN_START): Define.
9235 (arm_init_mve_builtins): Define function.
9236 (arm_init_builtins): Add TARGET_HAVE_MVE check.
9237 (arm_expand_builtin_1): Check the range of fcode.
9238 (arm_expand_mve_builtin): Define function to expand MVE builtins.
9239 (arm_expand_builtin): Check the range of fcode.
9240 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
9242 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
9243 (vst4q_s8): Define macro.
9244 (vst4q_s16): Likewise.
9245 (vst4q_s32): Likewise.
9246 (vst4q_u8): Likewise.
9247 (vst4q_u16): Likewise.
9248 (vst4q_u32): Likewise.
9249 (vst4q_f16): Likewise.
9250 (vst4q_f32): Likewise.
9251 (__arm_vst4q_s8): Define inline builtin.
9252 (__arm_vst4q_s16): Likewise.
9253 (__arm_vst4q_s32): Likewise.
9254 (__arm_vst4q_u8): Likewise.
9255 (__arm_vst4q_u16): Likewise.
9256 (__arm_vst4q_u32): Likewise.
9257 (__arm_vst4q_f16): Likewise.
9258 (__arm_vst4q_f32): Likewise.
9259 (__ARM_mve_typeid): Define macro with MVE types.
9260 (__ARM_mve_coerce): Define macro with _Generic feature.
9261 (vst4q): Define polymorphic variant for different vst4q builtins.
9262 * config/arm/arm_mve_builtins.def: New file.
9263 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
9265 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
9266 (unspec): Define unspec.
9267 (mve_vst4q<mode>): Define RTL pattern.
9268 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
9270 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
9272 (define_split): Allow OI mode split for MVE after reload.
9273 (define_split): Allow XI mode split for MVE after reload.
9274 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
9275 (arm-builtins.o): Likewise.
9277 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
9279 * c-typeck.c (process_init_element): Handle constructor_type with
9280 type size represented by POLY_INT_CST.
9282 2020-03-17 Jakub Jelinek <jakub@redhat.com>
9284 PR tree-optimization/94187
9285 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
9286 nchars - offset < nbytes.
9289 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
9290 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
9291 for code-generation.
9293 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
9296 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
9297 after changing memory subreg.
9299 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9300 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9302 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
9303 emulator calls for dobule precision arithmetic operations for MVE.
9305 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9306 Mihail Ionescu <mihail.ionescu@arm.com>
9307 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9309 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
9310 feature bit is on and -mfpu=auto is passed as compiler option, do not
9311 generate error on not finding any matching fpu. Because in this case
9312 fpu is not required.
9313 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
9314 enabled for MVE and also for all VFP extensions.
9315 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
9317 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
9318 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
9319 along with feature bits mve_float.
9320 (mve): Modify add options in armv8.1-m.main arch for MVE.
9321 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
9323 * config/arm/arm.c (use_return_insn): Replace the
9324 check with TARGET_VFP_BASE.
9325 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
9327 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
9328 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
9330 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
9331 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
9333 (arm_compute_frame_layout): Likewise.
9334 (arm_save_coproc_regs): Likewise.
9335 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
9337 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
9338 with equivalent macro TARGET_VFP_BASE.
9339 (arm_expand_epilogue_apcs_frame): Likewise.
9340 (arm_expand_epilogue): Likewise.
9341 (arm_conditional_register_usage): Likewise.
9342 (arm_declare_function_name): Add check to skip printing .fpu directive
9343 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
9345 * config/arm/arm.h (TARGET_VFP_BASE): Define.
9346 * config/arm/arm.md (arch): Add "mve" to arch.
9347 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
9348 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
9349 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
9350 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
9352 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
9353 to not allow for MVE.
9354 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
9356 (VUNSPEC_GET_FPSCR): Define.
9357 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
9358 instructions which move to general-purpose Register from Floating-point
9359 Special register and vice-versa.
9360 (thumb2_movhi_fp16): Likewise.
9361 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
9362 with MCR and MRC instructions which set and get Floating-point Status
9363 and Control Register (FPSCR).
9364 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
9366 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
9367 float move patterns in MVE.
9368 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
9369 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
9370 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
9371 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
9372 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
9373 TARGET_VFP_BASE check.
9374 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
9375 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
9377 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
9378 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
9382 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9383 Mihail Ionescu <mihail.ionescu@arm.com>
9384 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9386 * config.gcc (arm_mve.h): Include mve intrinsics header file.
9387 * config/arm/aout.h (p0): Add new register name for MVE predicated
9389 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
9390 common to Neon and MVE.
9391 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
9392 (arm_init_simd_builtin_types): Disable poly types for MVE.
9393 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
9394 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
9395 ARM_BUILTIN_NEON_LANE_CHECK.
9396 (mve_dereference_pointer): Add function.
9397 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
9399 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
9400 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
9401 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
9402 with floating point enabled.
9403 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
9404 simd_immediate_valid_for_move.
9405 (simd_immediate_valid_for_move): Renamed from
9406 neon_immediate_valid_for_move function.
9407 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
9408 error if vfpv2 feature bit is disabled and mve feature bit is also
9409 disabled for HARD_FLOAT_ABI.
9410 (use_return_insn): Check to not push VFP regs for MVE.
9411 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
9413 (aapcs_vfp_allocate_return_reg): Likewise.
9414 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
9415 address operand for MVE.
9416 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
9417 (neon_valid_immediate): Rename to simd_valid_immediate.
9418 (simd_valid_immediate): Rename from neon_valid_immediate.
9419 (simd_valid_immediate): MVE check on size of vector is 128 bits.
9420 (neon_immediate_valid_for_move): Rename to
9421 simd_immediate_valid_for_move.
9422 (simd_immediate_valid_for_move): Rename from
9423 neon_immediate_valid_for_move.
9424 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
9426 (neon_make_constant): Modify call to neon_valid_immediate function.
9427 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
9429 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
9430 (arm_compute_frame_layout): Calculate space for saved VFP registers for
9432 (arm_save_coproc_regs): Save coproc registers for MVE.
9433 (arm_print_operand): Add case 'E' to print memory operands for MVE.
9434 (arm_print_operand_address): Check to print register number for MVE.
9435 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
9436 (arm_modes_tieable_p): Check to allow structure mode for MVE.
9437 (arm_regno_class): Add VPR_REGNUM check.
9438 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
9440 (arm_expand_epilogue): MVE check for enabling pop instructions in
9442 (arm_print_asm_arch_directives): Modify function to disable print of
9443 .arch_extension "mve" and "fp" for cases where MVE is enabled with
9445 (arm_vector_mode_supported_p): Check for modes available in MVE interger
9446 and MVE floating point.
9447 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
9449 (arm_conditional_register_usage): Enable usage of conditional regsiter
9451 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
9452 (arm_declare_function_name): Modify function to disable print of
9453 .arch_extension "mve" and "fp" for cases where MVE is enabled with
9455 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
9456 when target general registers are required.
9457 (TARGET_HAVE_MVE_FLOAT): Likewise.
9458 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
9460 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
9461 which indicate this is not available for across function calls.
9462 (FIRST_PSEUDO_REGISTER): Modify.
9463 (VALID_MVE_MODE): Define valid MVE mode.
9464 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
9465 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
9466 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
9467 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
9469 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
9470 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
9471 (enum reg_class): Add VPR_REG entry.
9472 (REG_CLASS_NAMES): Add VPR_REG entry.
9473 * config/arm/arm.md (VPR_REGNUM): Define.
9474 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
9475 "unconditional" instructions.
9476 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
9477 (movdf_soft_insn): Modify RTL to not allow for MVE.
9478 (vfp_pop_multiple_with_writeback): Enable for MVE.
9479 (include "mve.md"): Include mve.md file.
9480 * config/arm/arm_mve.h: Add MVE intrinsics head file.
9481 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
9482 for vector predicated operands.
9483 * config/arm/iterators.md (VNIM1): Define.
9485 (VHFBF_split): Define
9486 * config/arm/mve.md: New file.
9487 (mve_mov<mode>): Define RTL for move, store and load in MVE.
9488 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
9490 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
9491 simd_immediate_valid_for_move.
9492 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
9493 is common to MVE and NEON to vec-common.md file.
9494 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
9495 * config/arm/predicates.md (vpr_register_operand): Define.
9496 * config/arm/t-arm: Add mve.md file.
9497 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
9499 (mve_store): Add MVE instructions mve_store to attribute "type".
9500 (mve_load): Add MVE instructions mve_load to attribute "type".
9501 (is_mve_type): Define attribute.
9502 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
9503 standard move patterns in MVE along with NEON and IWMMXT with mode
9505 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
9506 and IWMMXT with mode iterator V8HF.
9507 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
9509 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
9510 simd_immediate_valid_for_move.
9513 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
9516 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
9517 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
9519 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
9521 2020-03-16 Jakub Jelinek <jakub@redhat.com>
9524 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
9527 PR tree-optimization/94166
9528 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
9529 as secondary comparison key.
9531 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
9533 PR tree-optimization/94125
9534 * tree-loop-distribution.c
9535 (loop_distribution::break_alias_scc_partitions): Update post order
9536 number for merged scc.
9538 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
9541 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
9543 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
9544 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
9545 and ext_sse_reg_operand check.
9547 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
9549 * common.opt: Avoid redundancy in the help text.
9550 * config/arc/arc.opt: Likewise.
9551 * config/cr16/cr16.opt: Likewise.
9553 2020-03-14 Jakub Jelinek <jakub@redhat.com>
9556 * tree-nested.c (convert_nonlocal_omp_clauses,
9557 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
9558 with C/C++ array sections.
9560 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
9563 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
9564 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
9567 2020-03-14 Jakub Jelinek <jakub@redhat.com>
9569 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
9570 "a an" to "an" in a comment.
9571 * hsa-common.h (is_a_helper): Likewise.
9572 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
9573 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
9574 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
9576 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
9579 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
9580 64-bit value by 64 bits (UB).
9582 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
9584 PR rtl-optimization/92303
9585 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
9587 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
9589 PR rtl-optimization/94148
9590 PR rtl-optimization/94042
9591 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
9592 (df_worklist_propagate_forward): New parameter last_change_age, use
9593 that instead of bb->aux.
9594 (df_worklist_propagate_backward): Ditto.
9595 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
9597 2020-03-13 Richard Biener <rguenther@suse.de>
9599 PR tree-optimization/94163
9600 * tree-ssa-pre.c (create_expression_by_pieces): Check
9601 whether alignment would be zero.
9603 2020-03-13 Martin Liska <mliska@suse.cz>
9606 * lto-wrapper.c (run_gcc): Use concat for appending
9607 to collect_gcc_options.
9609 2020-03-13 Jakub Jelinek <jakub@redhat.com>
9612 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
9615 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
9618 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
9619 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
9620 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
9621 TARGET_AVX512VL and ext_sse_reg_operand check.
9623 2020-03-13 Bu Le <bule1@huawei.com>
9626 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
9627 (-param=aarch64-double-recp-precision=): New options.
9628 * doc/invoke.texi: Document them.
9629 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
9630 instead of hard-coding the choice of 1 for float and 2 for double.
9632 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
9634 PR rtl-optimization/94119
9635 * resource.h (clear_hashed_info_until_next_barrier): Declare.
9636 * resource.c (clear_hashed_info_until_next_barrier): New function.
9637 * reorg.c (add_to_delay_list): Fix formatting.
9638 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
9639 the next instruction after removing a BARRIER.
9641 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
9644 * expmed.c (store_integral_bit_field): For fields larger than a word,
9645 call extract_bit_field on the value if the mode is BLKmode. Remove
9646 specific path for big-endian targets and tidy things up a little bit.
9648 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
9650 PR rtl-optimization/90275
9651 * cse.c (cse_insn): Delete no-op register moves too.
9653 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
9655 * config/rx/rx.md (CTRLREG_CPEN): Remove.
9656 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
9658 2020-03-12 Richard Biener <rguenther@suse.de>
9660 PR tree-optimization/94103
9661 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
9662 punning when the mode precision is not sufficient.
9664 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
9667 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
9668 MODE_V1DF and MODE_V2SF.
9669 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
9670 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
9673 2020-03-12 Jakub Jelinek <jakub@redhat.com>
9675 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
9676 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
9677 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
9678 * doc/tm.texi: Regenerated.
9680 PR tree-optimization/94130
9681 * tree-ssa-dse.c: Include gimplify.h.
9682 (increment_start_addr): If stmt has lhs, drop the lhs from call and
9683 set it after the call to the original value of the first argument.
9685 (decrement_count): Formatting fix.
9687 2020-03-11 Delia Burduv <delia.burduv@arm.com>
9689 * config/arm/arm-builtins.c
9690 (arm_init_simd_builtin_scalar_types): New.
9691 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
9692 (vld2q_bf16): Used new builtin type.
9693 (vld3_bf16): Used new builtin type.
9694 (vld3q_bf16): Used new builtin type.
9695 (vld4_bf16): Used new builtin type.
9696 (vld4q_bf16): Used new builtin type.
9697 (vld2_dup_bf16): Used new builtin type.
9698 (vld2q_dup_bf16): Used new builtin type.
9699 (vld3_dup_bf16): Used new builtin type.
9700 (vld3q_dup_bf16): Used new builtin type.
9701 (vld4_dup_bf16): Used new builtin type.
9702 (vld4q_dup_bf16): Used new builtin type.
9704 2020-03-11 Jakub Jelinek <jakub@redhat.com>
9707 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
9708 at the start to switch to data section. Don't print extra newline if
9709 .globl directive has not been emitted.
9711 2020-03-11 Richard Biener <rguenther@suse.de>
9713 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
9716 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
9719 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
9720 whose type is a qualified union.
9722 2020-03-11 Jakub Jelinek <jakub@redhat.com>
9725 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
9726 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
9729 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
9731 (get_nth_most_common_value): Use abs_hwi instead of abs.
9734 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
9735 is rvc_normal, otherwise use real_to_decimal to print the number to
9738 PR tree-optimization/94114
9739 * tree-loop-distribution.c (generate_memset_builtin): Call
9740 rewrite_to_non_trapping_overflow even on mem.
9741 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
9744 2020-03-10 Jeff Law <law@redhat.com>
9746 * config/bfin/bfin.md (movsi_insv): Add length attribute.
9748 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
9751 * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
9752 NAN and SIGNED_ZEROR for smax/smin.
9754 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
9757 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
9758 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
9760 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
9762 * loop-iv.c (find_simple_exit): Make it static.
9763 * cfgloop.h: Remove the corresponding prototype.
9765 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
9767 * ddg.c (create_ddg): Fix intendation.
9768 (set_recurrence_length): Likewise.
9769 (create_ddg_all_sccs): Likewise.
9771 2020-03-10 Jakub Jelinek <jakub@redhat.com>
9774 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
9775 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
9778 2020-03-09 Jason Merrill <jason@redhat.com>
9780 * gdbinit.in (pgs): Fix typo in documentation.
9782 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
9786 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
9788 PR rtl-optimization/93564
9789 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
9790 do not honor reg alloc order.
9792 2020-03-09 Andrew Pinski <apinski@marvell.com>
9795 * doc/extend.texi (x86 Operand Modifiers): Fix column
9798 2020-03-09 Martin Liska <mliska@suse.cz>
9801 * config/rs6000/rs6000.c (rs6000_option_override_internal):
9802 Remove set of str_align_loops and str_align_jumps as these
9803 should be set in previous 2 conditions in the function.
9805 2020-03-09 Jakub Jelinek <jakub@redhat.com>
9807 PR rtl-optimization/94045
9808 * params.opt (-param=max-find-base-term-values=): New option.
9809 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
9810 in a single toplevel find_base_term call.
9812 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
9815 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
9816 * config/aarch64/aarch64-simd.md
9817 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
9818 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
9819 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
9820 * config/aarch64/arm_neon.h:
9821 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
9822 (vmlal_lane_u16): Likewise.
9823 (vmlal_lane_s32): Likewise.
9824 (vmlal_lane_u32): Likewise.
9825 (vmlal_laneq_s16): Likewise.
9826 (vmlal_laneq_u16): Likewise.
9827 (vmlal_laneq_s32): Likewise.
9828 (vmlal_laneq_u32): Likewise.
9829 (vmull_lane_s16): Likewise.
9830 (vmull_lane_u16): Likewise.
9831 (vmull_lane_s32): Likewise.
9832 (vmull_lane_u32): Likewise.
9833 (vmull_laneq_s16): Likewise.
9834 (vmull_laneq_u16): Likewise.
9835 (vmull_laneq_s32): Likewise.
9836 (vmull_laneq_u32): Likewise.
9837 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
9840 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
9842 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
9843 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
9844 (aarch64_mls_elt<mode>): Likewise.
9845 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
9846 (aarch64_fma4_elt<mode>): Likewise.
9847 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
9848 (aarch64_fma4_elt_to_64v2df): Likewise.
9849 (aarch64_fnma4_elt<mode>): Likewise.
9850 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
9851 (aarch64_fnma4_elt_to_64v2df): Likewise.
9853 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
9855 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
9856 Specify movprfx attribute.
9857 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
9859 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
9862 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
9864 (TARGET_NO_FP_IN_TOC): Same.
9865 * config/rs6000/aix71.h: Same.
9866 * config/rs6000/aix72.h: Same.
9868 2020-03-06 Andrew Pinski <apinski@marvell.com>
9869 Jeff Law <law@redhat.com>
9871 PR rtl-optimization/93996
9872 * haifa-sched.c (remove_notes): Be more careful when adding
9875 2020-03-06 Delia Burduv <delia.burduv@arm.com>
9877 * config/arm/arm_neon.h (vld2_bf16): New.
9883 (vld2_dup_bf16): New.
9884 (vld2q_dup_bf16): New.
9885 (vld3_dup_bf16): New.
9886 (vld3q_dup_bf16): New.
9887 (vld4_dup_bf16): New.
9888 (vld4q_dup_bf16): New.
9889 * config/arm/arm_neon_builtins.def
9890 (vld2): Changed to VAR13 and added v4bf, v8bf
9891 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
9892 (vld3): Changed to VAR13 and added v4bf, v8bf
9893 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
9894 (vld4): Changed to VAR13 and added v4bf, v8bf
9895 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
9896 * config/arm/iterators.md (VDXBF2): New iterator.
9897 *config/arm/neon.md (neon_vld2): Use new iterators.
9898 (neon_vld2_dup<mode): Use new iterators.
9899 (neon_vld3<mode>): Likewise.
9900 (neon_vld3qa<mode>): Likewise.
9901 (neon_vld3qb<mode>): Likewise.
9902 (neon_vld3_dup<mode>): Likewise.
9903 (neon_vld4<mode>): Likewise.
9904 (neon_vld4qa<mode>): Likewise.
9905 (neon_vld4qb<mode>): Likewise.
9906 (neon_vld4_dup<mode>): Likewise.
9907 (neon_vld2_dupv8bf): New.
9908 (neon_vld3_dupv8bf): Likewise.
9909 (neon_vld4_dupv8bf): Likewise.
9911 2020-03-06 Delia Burduv <delia.burduv@arm.com>
9913 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
9914 (bfloat16x8x2_t): New typedef.
9915 (bfloat16x4x3_t): New typedef.
9916 (bfloat16x8x3_t): New typedef.
9917 (bfloat16x4x4_t): New typedef.
9918 (bfloat16x8x4_t): New typedef.
9925 * config/arm/arm-builtins.c (v2bf_UP): Define.
9927 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
9928 * config/arm/arm-modes.def (V2BF): New mode.
9929 * config/arm/arm-simd-builtin-types.def
9930 (Bfloat16x2_t): New entry.
9931 * config/arm/arm_neon_builtins.def
9932 (vst2): Changed to VAR13 and added v4bf, v8bf
9933 (vst3): Changed to VAR13 and added v4bf, v8bf
9934 (vst4): Changed to VAR13 and added v4bf, v8bf
9935 * config/arm/iterators.md (VDXBF): New iterator.
9936 (VQ2BF): New iterator.
9937 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
9938 (neon_vst2<mode>): Used new iterators.
9939 (neon_vst3<mode>): Used new iterators.
9940 (neon_vst3<mode>): Used new iterators.
9941 (neon_vst3qa<mode>): Used new iterators.
9942 (neon_vst3qb<mode>): Used new iterators.
9943 (neon_vst4<mode>): Used new iterators.
9944 (neon_vst4<mode>): Used new iterators.
9945 (neon_vst4qa<mode>): Used new iterators.
9946 (neon_vst4qb<mode>): Used new iterators.
9948 2020-03-06 Delia Burduv <delia.burduv@arm.com>
9950 * config/aarch64/aarch64-simd-builtins.def
9951 (bfcvtn): New built-in function.
9952 (bfcvtn_q): New built-in function.
9953 (bfcvtn2): New built-in function.
9954 (bfcvt): New built-in function.
9955 * config/aarch64/aarch64-simd.md
9956 (aarch64_bfcvtn<q><mode>): New pattern.
9957 (aarch64_bfcvtn2v8bf): New pattern.
9958 (aarch64_bfcvtbf): New pattern.
9959 * config/aarch64/arm_bf16.h (float32_t): New typedef.
9960 (vcvth_bf16_f32): New intrinsic.
9961 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
9962 (vcvtq_low_bf16_f32): New intrinsic.
9963 (vcvtq_high_bf16_f32): New intrinsic.
9964 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
9965 (UNSPEC_BFCVTN): New UNSPEC.
9966 (UNSPEC_BFCVTN2): New UNSPEC.
9967 (UNSPEC_BFCVT): New UNSPEC.
9968 * config/arm/types.md (bf_cvt): New type.
9970 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
9972 * config/s390/s390.md ("tabort"): Get rid of two consecutive
9973 blanks in format string.
9975 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
9979 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
9980 * config/i386/i386.c (ix86_get_ssemov): New function.
9981 (ix86_output_ssemov): Likewise.
9982 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
9983 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
9985 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
9986 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
9987 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
9988 (*movti_internal): Likewise.
9989 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
9991 2020-03-05 Jeff Law <law@redhat.com>
9993 PR tree-optimization/91890
9994 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
9995 Use gimple_or_expr_nonartificial_location.
9996 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
9997 Use gimple_or_expr_nonartificial_location.
9998 * gimple.c (gimple_or_expr_nonartificial_location): New function.
9999 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
10000 * tree-ssa-strlen.c (maybe_warn_overflow): Use
10001 gimple_or_expr_nonartificial_location.
10002 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
10003 (maybe_warn_pointless_strcmp): Likewise.
10005 2020-03-05 Jakub Jelinek <jakub@redhat.com>
10008 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
10009 SRC and MASK arguments to __m128 from __m128d.
10010 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
10012 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
10014 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
10015 argument to __m128i from __m128d.
10016 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
10018 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
10019 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
10022 2020-03-05 Delia Burduv <delia.burduv@arm.com>
10024 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
10025 (vbfmlalbq_f32): New.
10026 (vbfmlaltq_f32): New.
10027 (vbfmlalbq_lane_f32): New.
10028 (vbfmlaltq_lane_f32): New.
10029 (vbfmlalbq_laneq_f32): New.
10030 (vbfmlaltq_laneq_f32): New.
10031 * config/arm/arm_neon_builtins.def (vmmla): New.
10036 (vfmab_laneq): New.
10037 (vfmat_laneq): New.
10038 * config/arm/iterators.md (BF_MA): New int iterator.
10039 (bt): New int attribute.
10040 (VQXBF): Copy of VQX with V8BF.
10041 * config/arm/neon.md (neon_vmmlav8bf): New insn.
10042 (neon_vfma<bt>v8bf): New insn.
10043 (neon_vfma<bt>_lanev8bf): New insn.
10044 (neon_vfma<bt>_laneqv8bf): New expand.
10045 (neon_vget_high<mode>): Changed iterator to VQXBF.
10046 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
10047 (UNSPEC_BFMAB): New UNSPEC.
10048 (UNSPEC_BFMAT): New UNSPEC.
10050 2020-03-05 Jakub Jelinek <jakub@redhat.com>
10052 PR middle-end/93399
10053 * tree-pretty-print.h (pretty_print_string): Declare.
10054 * tree-pretty-print.c (pretty_print_string): Remove forward
10055 declaration, no longer static. Change nbytes parameter type
10056 from unsigned to size_t.
10057 * print-rtl.c (print_value) <case CONST_STRING>: Use
10058 pretty_print_string and for shrink way too long strings.
10060 2020-03-05 Richard Biener <rguenther@suse.de>
10061 Jakub Jelinek <jakub@redhat.com>
10063 PR tree-optimization/93582
10064 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
10065 last operand as signed when looking for memset offset. Formatting
10068 2020-03-04 Andrew Pinski <apinski@marvell.com>
10071 * value-prof.c (dump_histogram_value): Use std::abs.
10073 2020-03-04 Martin Sebor <msebor@redhat.com>
10075 PR tree-optimization/93986
10076 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
10077 operands to the same precision widest_int to avoid ICEs.
10079 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
10082 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
10083 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
10084 for OPTION_MASK_ALTIVEC.
10086 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
10088 * config.gcc: Include the glibc-stdint.h header for zTPF.
10090 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
10092 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
10093 direct FPR-GPR copies.
10094 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
10097 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
10099 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
10100 operands to the prologue_tpf expander.
10101 (s390_emit_epilogue): Likewise.
10102 (s390_option_override_internal): Do error checking and setup for
10104 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
10105 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
10106 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
10107 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
10108 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
10109 operands for the check flag and the branch target.
10110 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
10111 ("mtpf-trace-hook-prologue-target")
10112 ("mtpf-trace-hook-epilogue-check")
10113 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
10115 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
10116 options are for debugging purposes and will not be documented
10119 2020-03-04 Jakub Jelinek <jakub@redhat.com>
10122 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
10124 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
10125 argument. Change pd argument so that it can be modified. Turn
10126 constant non-CONSTRUCTOR store into non-constant if it is too large.
10127 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
10129 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
10132 2020-02-04 Richard Biener <rguenther@suse.de>
10134 PR tree-optimization/93964
10135 * graphite-isl-ast-to-gimple.c
10136 (gcc_expression_from_isl_ast_expr_id): Add intermediate
10137 conversion for pointer to integer converts.
10138 * graphite-scop-detection.c (assign_parameter_index_in_region):
10141 2020-03-04 Martin Liska <mliska@suse.cz>
10145 * doc/invoke.texi: Clarify --help=language and --help=common
10148 2020-03-04 Jakub Jelinek <jakub@redhat.com>
10150 PR tree-optimization/94001
10151 * tree-tailcall.c (process_assignment): Before comparing op1 to
10152 *ass_var, verify *ass_var is non-NULL.
10154 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
10157 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
10160 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
10162 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
10163 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
10164 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
10165 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
10166 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
10167 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
10168 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
10169 (V_bf_low, V_bf_cvt_m): New mode attributes.
10170 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
10171 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
10172 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
10173 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
10174 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
10176 2020-03-03 Jakub Jelinek <jakub@redhat.com>
10178 PR tree-optimization/93582
10179 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
10180 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
10181 members, initialize them in the constructor and if mask is non-NULL,
10182 artificially push_partial_def {} for the portions of the mask that
10184 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
10185 val and return (void *)-1. Formatting fix.
10186 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
10188 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
10189 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
10191 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
10193 (visit_stmt): Formatting fix.
10195 2020-03-03 Richard Biener <rguenther@suse.de>
10197 PR tree-optimization/93946
10198 * alias.h (refs_same_for_tbaa_p): Declare.
10199 * alias.c (refs_same_for_tbaa_p): New function.
10200 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
10202 * tree-ssa-scopedtables.h
10203 (avail_exprs_stack::lookup_avail_expr): Add output argument
10204 giving access to the hashtable entry.
10205 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
10207 * tree-ssa-dom.c: Include alias.h.
10208 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
10209 removing redundant store.
10210 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
10211 (ao_ref_init_from_vn_reference): Adjust prototype.
10212 (vn_reference_lookup_pieces): Likewise.
10213 (vn_reference_insert_pieces): Likewise.
10214 * tree-ssa-sccvn.c: Track base alias set in addition to alias
10216 (eliminate_dom_walker::eliminate_stmt): Also check base alias
10217 set when removing redundant stores.
10218 (visit_reference_op_store): Likewise.
10219 * dse.c (record_store): Adjust valdity check for redundant
10222 2020-03-03 Jakub Jelinek <jakub@redhat.com>
10225 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
10227 PR rtl-optimization/94002
10228 * explow.c (plus_constant): Punt if cst has VOIDmode and
10229 get_pool_mode is different from mode.
10231 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10233 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
10234 address has an offset which fits the scalling constraint for a
10235 load/store operation.
10236 (legitimate_scaled_address_p): Update use
10237 leigitimate_small_data_address_p.
10238 (arc_print_operand): Likewise.
10239 (arc_legitimate_address_p): Likewise.
10240 (legitimate_small_data_address_p): Likewise.
10242 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10244 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
10245 (fnmasf4_fpu): Likewise.
10247 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10249 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
10251 (subdi3): Likewise.
10252 (adddi3_i): Remove pattern.
10253 (subdi3_i): Likewise.
10255 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10257 * config/arc/arc.md (eh_return): Add length info.
10259 2020-03-02 David Malcolm <dmalcolm@redhat.com>
10261 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
10263 2020-03-02 David Malcolm <dmalcolm@redhat.com>
10265 * doc/invoke.texi (Static Analyzer Options): Add
10266 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
10269 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
10272 * config/i386/i386.md (movstrict<mode>): Allow only
10273 registers with VALID_INT_MODE_P modes.
10275 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
10277 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
10278 (reduc_insn): Use 'U' and 'B' operand codes.
10279 (reduc_<reduc_op>_scal_<mode>): Allow all types.
10280 (reduc_<reduc_op>_scal_v64di): Delete.
10281 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
10282 (*plus_carry_dpp_shr_v64si): Change to ...
10283 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
10284 (mov_from_lane63_v64di): Change to ...
10285 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
10286 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
10287 Support UNSPEC_MOV_DPP_SHR output formats.
10288 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
10289 Add "use_extends" reductions.
10290 (print_operand_address): Add 'I' and 'U' codes.
10291 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
10293 2020-03-02 Martin Liska <mliska@suse.cz>
10295 * lto-wrapper.c: Fix typo in comment about
10296 C++ standard version.
10298 2020-03-01 Martin Sebor <msebor@redhat.com>
10301 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
10303 2020-03-01 Martin Sebor <msebor@redhat.com>
10305 PR middle-end/93829
10306 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
10307 of a pointer in the outermost ADDR_EXPRs.
10309 2020-02-28 Jeff Law <law@redhat.com>
10311 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
10312 * config/v850/v850.c (v850_asm_trampoline_template): Update
10315 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
10318 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
10321 2020-02-28 Martin Liska <mliska@suse.cz>
10324 * configure.ac: Improve detection of ld_date by requiring
10325 either two dashes or none.
10326 * configure: Regenerate.
10328 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
10330 PR rtl-optimization/93564
10331 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
10332 do not honor reg alloc order.
10334 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
10337 * config/aarch64/aarch64.c (aarch64_override_options): Fix
10338 misleading warning string.
10340 2020-02-27 Martin Sebor <msebor@redhat.com>
10342 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
10344 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
10347 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
10348 Split the insn into two parts. This insn only does variable
10349 extract from a register.
10350 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
10351 variable extract from memory.
10352 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
10353 only does variable extract from a register.
10354 (vsx_extract_v4sf_var_load): New insn, do variable extract from
10356 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
10357 into two parts. This insn only does variable extract from a
10359 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
10360 do variable extract from memory.
10362 2020-02-27 Martin Jambor <mjambor@suse.cz>
10363 Feng Xue <fxue@os.amperecomputing.com>
10366 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
10367 new function calls_same_node_or_its_all_contexts_clone_p.
10368 (cgraph_edge_brings_value_p): Use it.
10369 (cgraph_edge_brings_value_p): Likewise.
10370 (self_recursive_pass_through_p): Return false if caller is a clone.
10371 (self_recursive_agg_pass_through_p): Likewise.
10373 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
10375 PR middle-end/92152
10376 * alias.c (ends_tbaa_access_path_p): Break out from ...
10377 (component_uses_parent_alias_set_from): ... here.
10378 * alias.h (ends_tbaa_access_path_p): Declare.
10379 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
10380 handle trailing arrays past end of tbaa access path.
10381 (aliasing_component_refs_p): ... here; likewise.
10382 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
10383 path; disambiguate also past end of it.
10384 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
10387 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
10389 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
10390 beginning of the file.
10391 (vcreate_bf16, vcombine_bf16): New.
10392 (vdup_n_bf16, vdupq_n_bf16): New.
10393 (vdup_lane_bf16, vdup_laneq_bf16): New.
10394 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
10395 (vduph_lane_bf16, vduph_laneq_bf16): New.
10396 (vset_lane_bf16, vsetq_lane_bf16): New.
10397 (vget_lane_bf16, vgetq_lane_bf16): New.
10398 (vget_high_bf16, vget_low_bf16): New.
10399 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
10400 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
10401 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
10402 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
10403 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
10404 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
10405 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
10406 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
10407 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
10408 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
10409 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
10410 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
10411 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
10412 (vreinterpretq_bf16_p128): New.
10413 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
10414 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
10415 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
10416 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
10417 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
10418 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
10419 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
10420 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
10421 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
10422 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
10423 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
10424 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
10425 (vreinterpretq_p128_bf16): New.
10426 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
10427 (V_elem): Likewise.
10428 (V_elem_l): Likewise.
10429 (VD_LANE): Likewise.
10431 (V_DOUBLE): Likewise.
10432 (VDQX): Add V4BF and V8BF.
10433 (V_two_elem, V_three_elem, V_four_elem): Likewise.
10435 (V_HALF): Likewise.
10436 (V_double_vector_mode): Likewise.
10437 (V_cmp_result): Likewise.
10438 (V_uf_sclr): Likewise.
10439 (V_sz_elem): Likewise.
10440 (Is_d_reg): Likewise.
10441 (V_mode_nunits): Likewise.
10442 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
10444 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
10446 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
10447 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
10448 (<expander><mode>3<exec>): Likewise.
10449 (<expander><mode>3): New.
10450 (v<expander><mode>3): New.
10451 (<expander><mode>3): New.
10452 (<expander><mode>3<exec>): Rename to ...
10453 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
10454 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
10456 2020-02-27 Alexandre Oliva <oliva@adacore.com>
10458 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
10461 2020-02-27 Richard Biener <rguenther@suse.de>
10463 PR tree-optimization/93508
10464 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
10465 non-_CHK variants. Valueize their length arguments.
10467 2020-02-27 Richard Biener <rguenther@suse.de>
10469 PR tree-optimization/93953
10470 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
10471 to the hash-map entry.
10473 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
10475 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
10477 2020-02-27 Mark Williams <mwilliams@fb.com>
10479 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
10480 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
10481 -ffile-prefix-map and -fmacro-prefix-map.
10482 * lto-streamer-out.c: Include file-prefix-map.h.
10483 (lto_output_location): Remap the file part of locations.
10485 2020-02-27 Jakub Jelinek <jakub@redhat.com>
10488 * gimplify.c (gimplify_init_constructor): Don't promote readonly
10489 DECL_REGISTER variables to TREE_STATIC.
10491 PR tree-optimization/93582
10492 PR tree-optimization/93945
10493 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
10494 non-zero INTEGER_CST second argument and ref->offset or ref->size
10495 not a multiple of BITS_PER_UNIT.
10497 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
10499 * doc/install.texi (Binaries): Update description of BullFreeware.
10501 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
10505 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
10506 C++ Language Options, Warning Options, and Static Analyzer
10507 Options lists. Document negative form of options enabled by
10508 default. Move some things around to more accurately sort
10509 warnings by category.
10510 (C++ Dialect Options, Warning Options, Static Analyzer
10511 Options): Document negative form of options when enabled by
10512 default. Move some things around to more accurately sort
10513 warnings by category. Add some missing index entries.
10514 Light copy-editing.
10516 2020-02-26 Carl Love <cel@us.ibm.com>
10519 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
10520 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
10521 for the vector unsigned short arguments. It is also listed as the
10522 name of the built-in for arguments vector unsigned short,
10523 vector unsigned int and vector unsigned long long built-ins. The
10524 name of the builtins for these arguments should be:
10525 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
10526 __builtin_crypto_vpmsumd respectively.
10528 2020-02-26 Richard Biener <rguenther@suse.de>
10530 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
10531 and load permutation.
10533 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
10535 PR middle-end/93843
10536 * optabs-tree.c (supportable_convert_operation): Reject types with
10539 2020-02-26 David Malcolm <dmalcolm@redhat.com>
10541 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
10543 2020-02-26 Jakub Jelinek <jakub@redhat.com>
10545 PR tree-optimization/93820
10546 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
10547 argument to ALL_INTEGER_CST_P boolean.
10548 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
10549 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
10550 adjacent INTEGER_CST store into merged_store->only_constants like
10553 2020-02-25 Jakub Jelinek <jakub@redhat.com>
10556 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
10558 * cfghooks.c (verify_flow_info): Likewise.
10559 * predict.c (combine_predictions_for_bb): Likewise.
10560 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
10561 sucessor -> successor.
10562 (find_traces_1_round): Fix comment typo, destinarion -> destination.
10563 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
10565 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
10566 message typo, sucessors -> successors.
10568 2020-02-25 Martin Sebor <msebor@redhat.com>
10570 * doc/extend.texi (attribute access): Correct an example.
10572 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
10574 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
10576 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
10577 (VAR15, VAR16): New.
10578 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
10579 (VD): Enable for V4BF.
10581 (VQ): Enable for V8BF.
10583 (VQ_NO2E): Likewise.
10584 (VDBL, Vdbl): Add V4BF.
10585 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
10586 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
10587 (bfloat16x8x2_t): Likewise.
10588 (bfloat16x4x3_t): Likewise.
10589 (bfloat16x8x3_t): Likewise.
10590 (bfloat16x4x4_t): Likewise.
10591 (bfloat16x8x4_t): Likewise.
10592 (vcombine_bf16): New.
10593 (vld1_bf16, vld1_bf16_x2): New.
10594 (vld1_bf16_x3, vld1_bf16_x4): New.
10595 (vld1q_bf16, vld1q_bf16_x2): New.
10596 (vld1q_bf16_x3, vld1q_bf16_x4): New.
10597 (vld1_lane_bf16): New.
10598 (vld1q_lane_bf16): New.
10599 (vld1_dup_bf16): New.
10600 (vld1q_dup_bf16): New.
10603 (vld2_dup_bf16): New.
10604 (vld2q_dup_bf16): New.
10607 (vld3_dup_bf16): New.
10608 (vld3q_dup_bf16): New.
10611 (vld4_dup_bf16): New.
10612 (vld4q_dup_bf16): New.
10613 (vst1_bf16, vst1_bf16_x2): New.
10614 (vst1_bf16_x3, vst1_bf16_x4): New.
10615 (vst1q_bf16, vst1q_bf16_x2): New.
10616 (vst1q_bf16_x3, vst1q_bf16_x4): New.
10617 (vst1_lane_bf16): New.
10618 (vst1q_lane_bf16): New.
10626 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
10628 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
10629 (VALL_F16): Likewise.
10630 (VALLDI_F16): Likewise.
10632 (Vetype): Likewise.
10633 (vswap_width_name): Likewise.
10634 (VSWAP_WIDTH): Likewise.
10638 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
10639 (vget_lane_bf16, vgetq_lane_bf16): New.
10640 (vcreate_bf16): New.
10641 (vdup_n_bf16, vdupq_n_bf16): New.
10642 (vdup_lane_bf16, vdup_laneq_bf16): New.
10643 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
10644 (vduph_lane_bf16, vduph_laneq_bf16): New.
10645 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
10646 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
10647 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
10648 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
10649 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
10650 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
10651 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
10652 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
10653 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
10654 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
10655 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
10656 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
10657 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
10658 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
10659 (vreinterpretq_bf16_p128): New.
10660 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
10661 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
10662 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
10663 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
10664 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
10665 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
10666 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
10667 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
10668 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
10669 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
10670 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
10671 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
10672 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
10673 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
10674 (vreinterpretq_p128_bf16): New.
10676 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
10678 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
10679 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
10680 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
10681 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
10682 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
10683 * config/arm/iterators.md (VSF2BF): New attribute.
10684 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
10685 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
10686 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
10688 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
10690 * config/arm/arm.md (required_for_purecode): New attribute.
10691 (enabled): Handle required_for_purecode.
10692 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
10693 work with -mpure-code.
10695 2020-02-25 Jakub Jelinek <jakub@redhat.com>
10697 PR rtl-optimization/93908
10698 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
10701 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
10703 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
10705 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
10707 * doc/install.texi (--enable-checking): Adjust wording.
10709 2020-02-25 Richard Biener <rguenther@suse.de>
10711 PR tree-optimization/93868
10712 * tree-vect-slp.c (slp_copy_subtree): New function.
10713 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
10714 re-arranging stmts in it.
10716 2020-02-25 Jakub Jelinek <jakub@redhat.com>
10718 PR middle-end/93874
10719 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
10720 dummy function and remove it at the end.
10722 PR translation/93864
10723 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
10724 paramter -> parameter.
10725 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
10726 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
10728 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
10730 * doc/install.texi (--enable-checking): Properly document current
10732 (--enable-stage1-checking): Minor clarification about bootstrap.
10734 2020-02-24 David Malcolm <dmalcolm@redhat.com>
10737 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
10738 -fanalyzer-checker=taint is also required.
10739 (-fanalyzer-checker=): Note that providing this option enables the
10740 given checker, and doing so may be required for checkers that are
10741 disabled by default.
10743 2020-02-24 David Malcolm <dmalcolm@redhat.com>
10745 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
10746 significant control flow events; add a "3" which shows all
10747 control flow events; the old "3" becomes "4".
10749 2020-02-24 Jakub Jelinek <jakub@redhat.com>
10751 PR tree-optimization/93582
10752 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
10753 pd.offset and pd.size to be counted in bits rather than bytes, add
10754 support for maxsizei that is not a multiple of BITS_PER_UNIT and
10755 handle bitfield stores and loads.
10756 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
10757 uncomparable quantities - bytes vs. bits. Allow push_partial_def
10758 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
10759 pd.offset/pd.size to be counted in bits rather than bytes.
10760 Formatting fix. Rename shadowed len variable to buflen.
10762 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
10763 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
10766 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
10767 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
10768 * opts-common.c (parse_options_from_collect_gcc_options): New function.
10769 (prepend_xassembler_to_collect_as_options): Likewise.
10770 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
10771 (prepend_xassembler_to_collect_as_options): Likewise.
10772 * lto-opts.c (lto_write_options): Stream assembler options
10773 in COLLECT_AS_OPTIONS.
10774 * lto-wrapper.c (xassembler_options_error): New static variable.
10775 (get_options_from_collect_gcc_options): Move parsing options code to
10776 parse_options_from_collect_gcc_options and call it.
10777 (merge_and_complain): Validate -Xassembler options.
10778 (append_compiler_options): Handle OPT_Xassembler.
10779 (run_gcc): Append command line -Xassembler options to
10780 collect_gcc_options.
10781 * doc/invoke.texi: Add documentation about using Xassembler
10784 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
10786 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
10788 (riscv_rtx_costs): Update cost model for LTGT.
10790 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
10792 PR rtl-optimization/93564
10793 * ira-color.c (struct update_cost_queue_elem): New member start.
10794 (queue_update_cost, get_next_update_cost): Add new arg start.
10795 (allocnos_conflict_p): New function.
10796 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
10797 Add checking conflicts with allocnos_conflict_p.
10798 (update_costs_from_prefs, restore_costs_from_copies): Adjust
10799 update_costs_from_allocno calls.
10800 (update_conflict_hard_regno_costs): Add checking conflicts with
10801 allocnos_conflict_p. Adjust calls of queue_update_cost and
10802 get_next_update_cost.
10803 (assign_hard_reg): Adjust calls of queue_update_cost. Add
10805 (bucket_allocno_compare_func): Restore previous version.
10807 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
10809 * gcc/config/pa/pa.c (pa_function_value): Fix check for word and
10810 double-word size when handling aggregate return values.
10811 * gcc/config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
10812 that homogeneous SFmode and DFmode aggregates are passed and returned
10813 in general registers.
10815 2020-02-21 Jakub Jelinek <jakub@redhat.com>
10817 PR translation/93759
10818 * opts.c (print_filtered_help): Translate help before appending
10819 messages to it rather than after that.
10821 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
10823 PR rtl-optimization/PR92989
10824 * lra-lives.c (process_bb_lives): Restore the original order
10825 of the bb liveness update. Call make_hard_regno_dead for each
10826 register clobbered at the start of an EH receiver.
10828 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
10831 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
10832 self-recursively generated.
10834 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
10837 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
10840 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
10842 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
10843 Document new target supports option.
10845 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
10847 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
10848 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
10849 * config/arm/iterators.md (MATMUL): New iterator.
10850 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
10851 (mmla_sfx): New attribute.
10852 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
10853 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
10854 (UNSPEC_MATMUL_US): New.
10856 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
10858 * config/arm/arm.md: Prevent scalar shifts from being used when big
10861 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
10862 Richard Biener <rguenther@suse.de>
10864 PR tree-optimization/93586
10865 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
10866 after mismatched array refs; do not sure type size information to
10867 recover from unmatched referneces with !flag_strict_aliasing_p.
10869 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
10871 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
10872 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
10873 (scatter_store<mode>): Rename to ...
10874 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
10875 (scatter<mode>_exec): Delete. Move contents ...
10876 (mask_scatter_store<mode>): ... here, and rename that to ...
10877 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
10878 Remove mode conversion.
10879 (mask_gather_load<mode>): Rename to ...
10880 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
10881 Remove mode conversion.
10882 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
10884 2020-02-21 Martin Jambor <mjambor@suse.cz>
10886 PR tree-optimization/93845
10887 * tree-sra.c (verify_sra_access_forest): Only test access size of
10890 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
10892 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
10893 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
10894 (addv64di3_exec): Likewise.
10895 (subv64di3): Likewise.
10896 (subv64di3_exec): Likewise.
10897 (addv64di3_zext): Likewise.
10898 (addv64di3_zext_exec): Likewise.
10899 (addv64di3_zext_dup): Likewise.
10900 (addv64di3_zext_dup_exec): Likewise.
10901 (addv64di3_zext_dup2): Likewise.
10902 (addv64di3_zext_dup2_exec): Likewise.
10903 (addv64di3_sext_dup2): Likewise.
10904 (addv64di3_sext_dup2_exec): Likewise.
10905 (<expander>v64di3): Likewise.
10906 (<expander>v64di3_exec): Likewise.
10907 (*<reduc_op>_dpp_shr_v64di): Likewise.
10908 (*plus_carry_dpp_shr_v64di): Likewise.
10909 * config/gcn/gcn.md (adddi3): Likewise.
10910 (addptrdi3): Likewise.
10911 (<expander>di3): Likewise.
10913 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
10915 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
10917 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10919 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
10920 support. Use aarch64_emit_mult instead of emitting multiplication
10921 instructions directly.
10922 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
10923 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
10925 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10927 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
10928 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
10929 instead of emitting multiplication instructions directly.
10930 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
10931 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
10932 (@aarch64_frecps<mode>): New expanders.
10934 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10936 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
10937 on and produce uint64_ts rather than ints.
10938 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
10939 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
10941 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10943 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
10944 an unused xmsk register when handling approximate rsqrt.
10946 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10948 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
10949 flag_finite_math_only condition.
10951 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
10954 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
10955 to destination operand for shufps alternative.
10956 (*vec_extractv2si_1): Ditto.
10958 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
10961 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
10964 2020-02-20 Martin Liska <mliska@suse.cz>
10966 PR translation/93831
10967 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
10969 2020-02-20 Martin Liska <mliska@suse.cz>
10971 PR translation/93830
10972 * common/config/avr/avr-common.c: Remote trailing "|".
10974 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
10976 * collect2.c (maybe_run_lto_and_relink): Fix typo in
10979 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
10981 PR tree-optimization/93767
10982 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
10983 access-size bias from the offset calculations for negative strides.
10985 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
10987 * collect2.c (c_file, o_file): Make const again.
10988 (ldout,lderrout, dump_ld_file): Remove.
10989 (tool_cleanup): Avoid calling not signal-safe functions.
10990 (maybe_run_lto_and_relink): Avoid possible signal handler
10991 access to unintialzed memory (lto_o_files).
10992 (main): Avoid leaking temp files in $TMPDIR.
10993 Initialize c_file/o_file with concat, which avoids exposing
10994 uninitialized memory to signal handler, which calls unlink(!).
10995 Avoid calling maybe_unlink when the main function returns,
10996 since the atexit handler is already doing this.
10997 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
10999 2020-02-19 Martin Jambor <mjambor@suse.cz>
11001 PR tree-optimization/93776
11002 * tree-sra.c (create_access): Do not create zero size accesses.
11003 (get_access_for_expr): Do not search for zero sized accesses.
11005 2020-02-19 Martin Jambor <mjambor@suse.cz>
11007 PR tree-optimization/93667
11008 * tree-sra.c (scalarizable_type_p): Return false if record fields
11009 do not follow wach other.
11011 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
11013 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
11014 rather than fmv.x.s/fmv.s.x.
11016 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
11018 * config/aarch64/aarch64-simd-builtins.def
11019 (intrinsic_vec_smult_lo_): New.
11020 (intrinsic_vec_umult_lo_): Likewise.
11021 (vec_widen_smult_hi_): Likewise.
11022 (vec_widen_umult_hi_): Likewise.
11023 * config/aarch64/aarch64-simd.md
11024 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
11025 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
11026 (vmull_high_s16): Likewise.
11027 (vmull_high_s32): Likewise.
11028 (vmull_high_u8): Likewise.
11029 (vmull_high_u16): Likewise.
11030 (vmull_high_u32): Likewise.
11031 (vmull_s8): Likewise.
11032 (vmull_s16): Likewise.
11033 (vmull_s32): Likewise.
11034 (vmull_u8): Likewise.
11035 (vmull_u16): Likewise.
11036 (vmull_u32): Likewise.
11038 2020-02-18 Martin Liska <mliska@suse.cz>
11040 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
11041 bootstrap by missing removal of invalid sanity check.
11043 2020-02-18 Martin Liska <mliska@suse.cz>
11046 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
11047 Always compare LHS of gimple_assign.
11049 2020-02-18 Martin Liska <mliska@suse.cz>
11052 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
11053 and return type of functions.
11054 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
11055 Drop MALLOC attribute for void functions.
11056 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
11057 malloc_state for a new VOID clone.
11059 2020-02-18 Martin Liska <mliska@suse.cz>
11062 * common.opt: Add -fprofile-reproducibility.
11063 * doc/invoke.texi: Document it.
11064 * value-prof.c (dump_histogram_value):
11065 Document and support behavior for counters[0]
11066 being a negative value.
11067 (get_nth_most_common_value): Handle negative
11068 counters[0] in respect to flag_profile_reproducible.
11070 2020-02-18 Jakub Jelinek <jakub@redhat.com>
11073 * cgraph.c (verify_speculative_call): Use speculative_id instead of
11074 speculative_uid in messages. Remove trailing whitespace from error
11075 message. Use num_speculative_call_targets instead of
11076 num_speculative_targets in a message.
11077 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
11078 edge messages and stmt instead of cal_stmt in reference message.
11080 PR tree-optimization/93780
11081 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
11082 before calling build_vector_type.
11083 (execute_update_addresses_taken): Likewise.
11086 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
11087 typo, functoin -> function.
11088 * tree.c (free_lang_data_in_decl): Fix comment typo,
11089 functoin -> function.
11090 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
11092 2020-02-17 David Malcolm <dmalcolm@redhat.com>
11094 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
11096 (print_option_information): Don't call get_option_url if URLs
11099 2020-02-17 Alexandre Oliva <oliva@adacore.com>
11101 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
11102 handling of register_common-less targets.
11104 2020-02-17 Martin Liska <mliska@suse.cz>
11107 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
11109 2020-02-17 Martin Liska <mliska@suse.cz>
11111 PR translation/93755
11112 * config/rs6000/rs6000.c (rs6000_option_override_internal):
11115 2020-02-17 Martin Liska <mliska@suse.cz>
11118 * config/rx/elf.opt: Fix typo.
11120 2020-02-17 Richard Biener <rguenther@suse.de>
11123 * opts-global.c (print_ignored_options): Use inform and
11126 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
11129 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
11131 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
11134 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
11135 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
11137 2020-02-15 Jason Merrill <jason@redhat.com>
11139 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
11141 2020-02-15 Jakub Jelinek <jakub@redhat.com>
11143 PR tree-optimization/93744
11144 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
11145 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
11146 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
11147 sure @2 in the first and @1 in the other patterns has no side-effects.
11149 2020-02-15 David Malcolm <dmalcolm@redhat.com>
11150 Bernd Edlinger <bernd.edlinger@hotmail.de>
11154 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
11155 * configure.ac (--with-diagnostics-urls): New configuration
11156 option, based on --with-diagnostics-color.
11157 (DIAGNOSTICS_URLS_DEFAULT): New define.
11158 * config.h: Regenerate.
11159 * configure: Regenerate.
11160 * diagnostic.c (diagnostic_urls_init): Handle -1 for
11161 DIAGNOSTICS_URLS_DEFAULT from configure-time
11162 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
11163 and TERM_URLS environment variable.
11164 * diagnostic-url.h (diagnostic_url_format): New enum type.
11165 (diagnostic_urls_enabled_p): rename to...
11166 (determine_url_format): ... this, and change return type.
11167 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
11168 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
11169 the linux console, and mingw.
11170 (diagnostic_urls_enabled_p): rename to...
11171 (determine_url_format): ... this, and adjust.
11172 * pretty-print.h (pretty_printer::show_urls): rename to...
11173 (pretty_printer::url_format): ... this, and change to enum.
11174 * pretty-print.c (pretty_printer::pretty_printer,
11175 pp_begin_url, pp_end_url, test_urls): Adjust.
11176 * doc/install.texi (--with-diagnostics-urls): Document the new
11177 configuration option.
11178 (--with-diagnostics-color): Document the existing interaction
11179 with GCC_COLORS better.
11180 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
11181 vindex reference. Update description of defaults based on the above.
11182 (-fdiagnostics-color): Update description of how -fdiagnostics-color
11183 interacts with GCC_COLORS.
11185 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
11188 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
11189 conjunction with TARGET_GNU_TLS in early return.
11191 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
11193 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
11194 the mode is not wider than UNITS_PER_WORD.
11196 2020-02-14 Martin Jambor <mjambor@suse.cz>
11198 PR tree-optimization/93516
11199 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
11200 access of the same type as the parent.
11201 (propagate_subaccesses_from_lhs): Likewise.
11203 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
11206 * config/i386/avx512vbmi2intrin.h
11207 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
11208 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
11209 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
11210 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
11211 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
11212 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
11213 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
11214 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
11215 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
11216 of lacking a closing parenthesis.
11217 * config/i386/avx512vbmi2vlintrin.h
11218 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
11219 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
11220 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
11221 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
11222 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
11223 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
11224 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
11225 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
11226 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
11227 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
11228 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
11229 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
11230 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
11231 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
11232 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
11233 _mm_shldi_epi32, _mm_mask_shldi_epi32,
11234 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
11235 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
11237 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
11240 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
11241 the target function entry.
11243 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11245 * common/config/arc/arc-common.c (arc_option_optimization_table):
11246 Disable if-conversion step when optimized for size.
11248 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11250 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
11251 R12-R15 are always in ARCOMPACT16_REGS register class.
11252 * config/arc/arc.opt (mq-class): Deprecate.
11253 * config/arc/constraint.md ("q"): Remove dependency on mq-class
11255 * doc/invoke.texi (mq-class): Update text.
11256 * common/config/arc/arc-common.c (arc_option_optimization_table):
11259 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11261 * config/arc/arc.c (arc_insn_cost): New function.
11262 (TARGET_INSN_COST): Define.
11263 * config/arc/arc.md (cost): New attribute.
11264 (add_n): Use arc_nonmemory_operand.
11265 (ashlsi3_insn): Likewise, also update constraints.
11266 (ashrsi3_insn): Likewise.
11267 (rotrsi3): Likewise.
11268 (add_shift): Likewise.
11269 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
11271 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11273 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
11275 (umulsidi_600): Likewise.
11277 2020-02-13 Jakub Jelinek <jakub@redhat.com>
11280 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
11281 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
11282 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
11283 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
11284 pass __A to the builtin followed by __W instead of __A followed by
11286 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
11287 _mm512_mask_popcnt_epi64): Likewise.
11288 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
11289 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
11290 _mm256_mask_popcnt_epi64): Likewise.
11292 PR tree-optimization/93582
11293 * fold-const.h (shift_bytes_in_array_left,
11294 shift_bytes_in_array_right): Declare.
11295 * fold-const.c (shift_bytes_in_array_left,
11296 shift_bytes_in_array_right): New function, moved from
11297 gimple-ssa-store-merging.c, no longer static.
11298 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
11299 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
11300 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
11301 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
11302 shift_bytes_in_array.
11303 (verify_shift_bytes_in_array): Rename to ...
11304 (verify_shift_bytes_in_array_left): ... this. Use
11305 shift_bytes_in_array_left instead of shift_bytes_in_array.
11306 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
11307 instead of verify_shift_bytes_in_array.
11308 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
11309 / native_interpret_expr where the store covers all needed bits,
11310 punt on PDP-endian, otherwise allow all involved offsets and sizes
11311 not to be byte-aligned.
11314 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
11315 use const_0_to_255_operand predicate instead of immediate_operand.
11316 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
11317 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
11318 vgf2p8affineinvqb_<mode><mask_name>,
11319 vgf2p8affineqb_<mode><mask_name>): Drop mode from
11320 const_0_to_255_operand predicated operands.
11322 2020-02-12 Jeff Law <law@redhat.com>
11324 * config/h8300/h8300.md (comparison shortening peepholes): Use
11325 a mode iterator to merge the HImode and SImode peepholes.
11327 2020-02-12 Jakub Jelinek <jakub@redhat.com>
11329 PR middle-end/93663
11330 * real.c (is_even): Make static. Function comment fix.
11331 (is_halfway_below): Make static, don't assert R is not inf/nan,
11332 instead return false for those. Small formatting fixes.
11334 2020-02-12 Martin Sebor <msebor@redhat.com>
11336 PR middle-end/93646
11337 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
11338 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
11339 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
11340 (strlen_check_and_optimize_call): Adjust callee name.
11342 2020-02-12 Jeff Law <law@redhat.com>
11344 * config/h8300/h8300.md (comparison shortening peepholes): Drop
11345 (and (xor)) variant. Combine other two into single peephole.
11347 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
11349 PR rtl-optimization/93565
11350 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
11352 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
11354 * config/aarch64/aarch64-simd.md
11355 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
11356 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
11357 generating separate ADDV and zero_extend patterns.
11358 * config/aarch64/iterators.md (VDQV_E): New iterator.
11360 2020-02-12 Jeff Law <law@redhat.com>
11362 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
11363 expanders, splits, etc.
11364 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
11365 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
11366 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
11367 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
11368 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
11369 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
11370 function prototype.
11371 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
11373 2020-02-12 Jakub Jelinek <jakub@redhat.com>
11376 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
11377 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
11378 TARGET_AVX512DQ from condition.
11379 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
11380 instead of <mask_mode512bit_condition> in condition. If
11381 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
11383 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
11386 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
11389 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
11391 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
11393 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
11394 where strlen is more legible.
11395 (rs6000_builtin_vectorized_libmass): Ditto.
11396 (rs6000_print_options_internal): Ditto.
11398 2020-02-11 Martin Sebor <msebor@redhat.com>
11400 PR tree-optimization/93683
11401 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
11403 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
11405 * config/rs6000/predicates.md (cint34_operand): Rename the
11406 -mprefixed-addr option to be -mprefixed.
11407 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
11408 the -mprefixed-addr option to be -mprefixed.
11409 (OTHER_FUTURE_MASKS): Likewise.
11410 (POWERPC_MASKS): Likewise.
11411 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
11412 the -mprefixed-addr option to be -mprefixed. Change error
11413 messages to refer to -mprefixed.
11414 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
11416 (rs6000_legitimate_offset_address_p): Likewise.
11417 (rs6000_mode_dependent_address): Likewise.
11418 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
11419 "-mprefixed" for target attributes and pragmas.
11420 (address_to_insn_form): Rename the -mprefixed-addr option to be
11422 (rs6000_adjust_insn_length): Likewise.
11423 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
11424 -mprefixed-addr option to be -mprefixed.
11425 (ASM_OUTPUT_OPCODE): Likewise.
11426 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
11427 -mprefixed-addr option to be -mprefixed.
11428 * config/rs6000/rs6000.opt (-mprefixed): Rename the
11429 -mprefixed-addr option to be prefixed. Change the option from
11430 being undocumented to being documented.
11431 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
11432 -mprefixed option. Update the -mpcrel documentation to mention
11435 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
11437 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
11438 including FIRST_PSEUDO_REGISTER - 1.
11439 * ira-color.c (print_hard_reg_set): Ditto.
11441 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
11443 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
11444 (USTERNOP_QUALIFIERS): New define.
11445 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
11446 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
11447 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
11448 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
11449 * config/arm/arm_neon.h (vusdot_s32): New.
11450 (vusdot_lane_s32): New.
11451 (vusdotq_lane_s32): New.
11452 (vsudot_lane_s32): New.
11453 (vsudotq_lane_s32): New.
11454 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
11455 * config/arm/iterators.md (DOTPROD_I8MM): New.
11456 (sup, opsuffix): Add <us/su>.
11457 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
11458 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
11460 2020-02-11 Richard Biener <rguenther@suse.de>
11462 PR tree-optimization/93661
11463 PR tree-optimization/93662
11464 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
11465 tree_to_poly_int64.
11466 * tree-sra.c (get_access_for_expr): Likewise.
11468 2020-02-10 Jakub Jelinek <jakub@redhat.com>
11471 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
11472 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
11473 Change condition from TARGET_AVX2 to TARGET_AVX.
11475 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
11478 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
11479 argument of strncmp.
11481 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
11483 Try to generate zero-based comparisons.
11484 * config/cris/cris.c (cris_reduce_compare): New function.
11485 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
11486 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
11487 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
11489 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
11492 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
11493 in Thumb state and also as a destination in Arm state. Add T16
11496 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
11498 * md.texi (Define Subst): Match closing paren in example.
11500 2020-02-10 Jakub Jelinek <jakub@redhat.com>
11504 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
11505 arguments of strncmp.
11507 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
11510 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
11511 but different source value.
11512 (adjust_callers_for_value_intersection): New function.
11513 (gather_edges_for_value): Adjust order of callers to let a
11514 non-self-recursive caller be the first element.
11515 (self_recursive_pass_through_p): Add a new parameter "simple", and
11516 check generalized self-recursive pass-through jump function.
11517 (self_recursive_agg_pass_through_p): Likewise.
11518 (find_more_scalar_values_for_callers_subset): Compute value from
11519 pass-through jump function for self-recursive.
11520 (intersect_with_plats): Cleanup previous implementation code for value
11521 itersection with self-recursive call edge.
11522 (intersect_with_agg_replacements): Likewise.
11523 (intersect_aggregates_with_edge): Deduce value from pass-through jump
11524 function for self-recursive call edge. Cleanup previous implementation
11525 code for value intersection with self-recursive call edge.
11526 (decide_whether_version_node): Remove dead callers and adjust order
11527 to let a non-self-recursive caller be the first element.
11529 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
11531 * recog.c: Move pass_split_before_sched2 code in front of
11532 pass_split_before_regstack.
11533 (pass_data_split_before_sched2): Rename pass to split3 from split4.
11534 (pass_data_split_before_regstack): Rename pass to split4 from split3.
11535 (rest_of_handle_split_before_sched2): Remove.
11536 (pass_split_before_sched2::execute): Unconditionally call
11538 (enable_split_before_sched2): New function.
11539 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
11540 (pass_split_before_regstack::gate): Ditto.
11541 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
11542 Update name check for renamed split4 pass.
11543 * config/sh/sh.c (register_sh_passes): Update pass insertion
11544 point for renamed split4 pass.
11546 2020-02-09 Jakub Jelinek <jakub@redhat.com>
11548 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
11549 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
11550 copying them around between host and target.
11552 2020-02-08 Andrew Pinski <apinski@marvell.com>
11555 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
11556 STRICT_ALIGNMENT also.
11558 2020-02-08 Jim Wilson <jimw@sifive.com>
11561 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
11563 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
11564 Jakub Jelinek <jakub@redhat.com>
11567 * config/i386/i386.h (CALL_USED_REGISTERS): Make
11568 xmm16-xmm31 call-used even in 64-bit ms-abi.
11570 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
11572 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
11573 (simd_ummla, simd_usmmla): Likewise.
11574 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
11575 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
11576 (vusmmlaq_s32): New.
11578 2020-02-07 Richard Biener <rguenther@suse.de>
11580 PR middle-end/93519
11581 * tree-inline.c (fold_marked_statements): Do a PRE walk,
11582 skipping unreachable regions.
11583 (optimize_inline_calls): Skip folding stmts when we didn't
11586 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
11589 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
11590 Don't return aggregates with only SFmode and DFmode in SSE
11592 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
11594 2020-02-07 Jakub Jelinek <jakub@redhat.com>
11597 * config/rs6000/rs6000-logue.c
11598 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
11599 if it fails, move rs into end_addr and retry. Add
11600 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
11601 the insn pattern doesn't describe well what exactly happens to
11605 * config/i386/predicates.md (avx_identity_operand): Remove.
11606 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
11607 (avx_<castmode><avxsizesuffix>_<castmode>,
11608 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
11609 a VEC_CONCAT of the operand and UNSPEC_CAST.
11610 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
11611 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
11615 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
11616 recog_data.insn if distance_non_agu_define changed it.
11618 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
11621 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
11622 we only had X-FORM (reg+reg) addressing for vectors. Also before
11623 ISA 3.0, we only had X-FORM addressing for scalars in the
11624 traditional Altivec registers.
11626 2020-02-06 <zhongyunde@huawei.com>
11627 Vladimir Makarov <vmakarov@redhat.com>
11629 PR rtl-optimization/93561
11630 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
11631 hard register range.
11633 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
11635 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
11638 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
11640 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
11641 where the low and the high 32 bits are equal to each other specially,
11642 with an rldimi instruction.
11644 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
11646 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
11648 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
11650 * config/arm/arm-tables.opt: Regenerate.
11652 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
11655 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
11656 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
11657 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
11659 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
11661 PR rtl-optimization/87763
11662 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
11664 2020-02-06 Delia Burduv <delia.burduv@arm.com>
11666 * config/aarch64/aarch64-simd-builtins.def
11667 (bfmlaq): New built-in function.
11668 (bfmlalb): New built-in function.
11669 (bfmlalt): New built-in function.
11670 (bfmlalb_lane): New built-in function.
11671 (bfmlalt_lane): New built-in function.
11672 * config/aarch64/aarch64-simd.md
11673 (aarch64_bfmmlaqv4sf): New pattern.
11674 (aarch64_bfmlal<bt>v4sf): New pattern.
11675 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
11676 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
11677 (vbfmlalbq_f32): New intrinsic.
11678 (vbfmlaltq_f32): New intrinsic.
11679 (vbfmlalbq_lane_f32): New intrinsic.
11680 (vbfmlaltq_lane_f32): New intrinsic.
11681 (vbfmlalbq_laneq_f32): New intrinsic.
11682 (vbfmlaltq_laneq_f32): New intrinsic.
11683 * config/aarch64/iterators.md (BF_MLA): New int iterator.
11684 (bt): New int attribute.
11686 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
11688 * config/i386/i386.md (*pushtf): Emit "#" instead of
11689 calling gcc_unreachable in insn output.
11692 (*pushsf_rex64): Ditto for alternatives other than 1.
11693 (*pushsf): Ditto for alternatives other than 1.
11695 2020-02-06 Martin Liska <mliska@suse.cz>
11697 PR gcov-profile/91971
11698 PR gcov-profile/93466
11699 * coverage.c (coverage_init): Revert mangling of
11700 path into filename. It can lead to huge filename length.
11701 Creation of subfolders seem more natural.
11703 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
11706 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
11707 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
11708 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
11710 2020-02-06 Jakub Jelinek <jakub@redhat.com>
11713 * config/i386/predicates.md (avx_identity_operand): New predicate.
11714 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
11715 define_insn_and_split.
11718 * omp-low.c (use_pointer_for_field): For nested constructs, also
11719 look for map clauses on target construct.
11720 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
11721 taskreg_nesting_level.
11724 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
11725 shared clause, call omp_notice_variable on outer context if any.
11727 2020-02-05 Jason Merrill <jason@redhat.com>
11730 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
11731 non-zero address even if weak and not yet defined.
11733 2020-02-05 Martin Sebor <msebor@redhat.com>
11735 PR tree-optimization/92765
11736 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
11737 * tree-ssa-strlen.c (compute_string_length): Remove.
11738 (determine_min_objsize): Remove.
11739 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
11740 Avoid using type size as the upper bound on string length.
11741 (handle_builtin_string_cmp): Add an argument. Adjust.
11742 (strlen_check_and_optimize_call): Pass additional argument to
11743 handle_builtin_string_cmp.
11745 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
11747 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
11748 (*pushdi2_rex64 peephole2): Unconditionally split after
11749 epilogue_completed.
11750 (*ashl<mode>3_doubleword): Ditto.
11751 (*<shift_insn><mode>3_doubleword): Ditto.
11753 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
11756 * config/rs6000/rs6000.c (get_vector_offset): Fix
11758 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
11760 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
11762 2020-02-05 David Malcolm <dmalcolm@redhat.com>
11764 * doc/analyzer.texi
11765 (Special Functions for Debugging the Analyzer): Update description
11766 of __analyzer_dump_exploded_nodes.
11768 2020-02-05 Jakub Jelinek <jakub@redhat.com>
11771 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
11772 include sets and not clobbers in the vzeroupper pattern.
11773 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
11774 the parallel has 17 (64-bit) or 9 (32-bit) elts.
11775 (*avx_vzeroupper_1): New define_insn_and_split.
11778 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
11779 don't run when !optimize.
11780 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
11783 2020-02-05 Richard Biener <rguenther@suse.de>
11785 PR middle-end/90648
11786 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
11787 checks before matching calls.
11789 2020-02-05 Jakub Jelinek <jakub@redhat.com>
11791 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
11792 function comment typo.
11794 PR middle-end/93555
11795 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
11796 simd_clone_create failed when i == 0, adjust clone->nargs by
11799 2020-02-05 Martin Liska <mliska@suse.cz>
11802 * doc/invoke.texi: Document that one should
11803 not combine ASLR and -fpch.
11805 2020-02-04 Richard Biener <rguenther@suse.de>
11807 PR tree-optimization/93538
11808 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
11810 2020-02-04 Richard Biener <rguenther@suse.de>
11812 PR tree-optimization/91123
11813 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
11814 (vn_walk_cb_data::last_vuse): New member.
11815 (vn_walk_cb_data::saved_operands): Likewsie.
11816 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
11817 (vn_walk_cb_data::push_partial_def): Use finish.
11818 (vn_reference_lookup_2): Update last_vuse and use finish if
11819 we've saved operands.
11820 (vn_reference_lookup_3): Use finish and update calls to
11821 push_partial_defs everywhere. When translating through
11822 memcpy or aggregate copies save off operands and alias-set.
11823 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
11824 operation for redundant store removal.
11826 2020-02-04 Richard Biener <rguenther@suse.de>
11828 PR tree-optimization/92819
11829 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
11830 generating more stmts than before.
11832 2020-02-04 Martin Liska <mliska@suse.cz>
11834 * config/arm/arm.c (arm_gen_far_branch): Move the function
11835 outside of selftests.
11837 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11839 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
11840 function to adjust PC-relative vector addresses.
11841 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
11842 handle vectors with PC-relative addresses.
11844 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11846 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
11848 (hard_reg_and_mode_to_addr_mask): Delete.
11849 (rs6000_adjust_vec_address): If the original vector address
11850 was REG+REG or REG+OFFSET and the element is not zero, do the add
11851 of the elements in the original address before adding the offset
11852 for the vector element. Use address_to_insn_form to validate the
11853 address using the register being loaded, rather than guessing
11854 whether the address is a DS-FORM or DQ-FORM address.
11856 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11858 * config/rs6000/rs6000.c (get_vector_offset): New helper function
11859 to calculate the offset in memory from the start of a vector of a
11860 particular element. Add code to keep the element number in
11861 bounds if the element number is variable.
11862 (rs6000_adjust_vec_address): Move calculation of offset of the
11863 vector element to get_vector_offset.
11864 (rs6000_split_vec_extract_var): Do not do the initial AND of
11865 element here, move the code to get_vector_offset.
11867 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11869 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
11872 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
11874 * config/rs6000/constraints.md: Improve documentation.
11876 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
11879 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
11880 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
11882 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
11884 * config.gcc: Remove "carrizo" support.
11885 * config/gcn/gcn-opts.h (processor_type): Likewise.
11886 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
11887 * config/gcn/gcn.opt (gpu_type): Likewise.
11888 * config/gcn/t-omp-device: Likewise.
11890 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
11893 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
11894 * config/arm/arm.c (arm_gen_far_branch): New function
11895 arm_gen_far_branch.
11896 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
11898 2020-02-03 Julian Brown <julian@codesourcery.com>
11899 Tobias Burnus <tobias@codesourcery.com>
11901 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
11903 2020-02-03 Jakub Jelinek <jakub@redhat.com>
11906 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
11907 valid RTL to sum up the lowest and second lowest bytes of the popcnt
11910 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
11912 PR rtl-optimization/91333
11913 * ira-color.c (struct allocno_color_data): Add member
11915 (init_allocno_threads): Set the member up.
11916 (bucket_allocno_compare_func): Add compare hard reg
11919 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
11921 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
11923 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
11924 * config.in: Regenerated.
11925 * configure: Regenerated.
11926 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
11927 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
11928 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
11930 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
11932 * configure: Regenerate.
11934 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
11936 PR rtl-optimization/91333
11937 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
11938 reg preferences comparison up.
11940 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
11942 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
11943 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
11944 aarch64-sve-builtins-base.h.
11945 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
11946 aarch64-sve-builtins-base.cc.
11947 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
11948 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
11949 (svcvtnt): Declare.
11950 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
11951 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
11952 (svcvtnt): New functions.
11953 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
11954 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
11955 (svcvtnt): New functions.
11956 (svcvt): Add a form that converts f32 to bf16.
11957 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
11958 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
11960 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
11961 Treat B as bfloat16_t.
11962 (ternary_bfloat_lane_base): New class.
11963 (ternary_bfloat_def): Likewise.
11964 (ternary_bfloat): New shape.
11965 (ternary_bfloat_lane_def): New class.
11966 (ternary_bfloat_lane): New shape.
11967 (ternary_bfloat_lanex2_def): New class.
11968 (ternary_bfloat_lanex2): New shape.
11969 (ternary_bfloat_opt_n_def): New class.
11970 (ternary_bfloat_opt_n): New shape.
11971 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
11972 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
11973 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
11974 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
11975 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
11976 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
11977 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
11978 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
11979 the pattern off the narrow mode instead of the wider one.
11980 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
11981 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
11982 (sve_fp_op): Handle them.
11983 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
11984 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
11986 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
11988 * config/aarch64/arm_sve.h: Include arm_bf16.h.
11989 * config/aarch64/aarch64-modes.def (BF): Move definition before
11990 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
11991 (SVE_MODES): Handle BF modes.
11992 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
11994 (aarch64_full_sve_mode): Likewise.
11995 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
11997 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
11998 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
11999 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
12000 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
12002 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
12004 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
12005 (TYPES_all_data): Add bf16.
12006 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
12007 (register_tuple_type): Increase buffer size.
12008 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
12009 (bf16): New type suffix.
12010 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
12011 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
12012 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
12013 Change type from all_data to all_arith.
12014 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
12015 (svminp): Likewise.
12017 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
12018 Matthew Malcomson <matthew.malcomson@arm.com>
12019 Richard Sandiford <richard.sandiford@arm.com>
12021 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
12022 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
12023 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
12024 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
12025 __ARM_FEATURE_MATMUL_FP64.
12026 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
12027 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
12028 be disabled at the same time.
12029 (f32mm): New extension.
12030 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
12031 (AARCH64_FL_F64MM): Bump to the next bit up.
12032 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
12033 (TARGET_SVE_F64MM): New macros.
12034 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
12035 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
12036 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
12037 (UNSPEC_ZIP2Q): New unspeccs.
12038 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
12039 (optab, sur, perm_insn): Handle the new unspecs.
12040 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
12041 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
12042 TARGET_SVE_F64MM instead of separate tests.
12043 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
12044 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
12045 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
12046 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
12047 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
12048 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
12049 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
12050 (TYPES_s_signed): New macro.
12051 (TYPES_s_integer): Use it.
12052 (TYPES_d_float): New macro.
12053 (TYPES_d_data): Use it.
12054 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
12055 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
12056 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
12057 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
12058 (svmmla): New shape.
12059 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
12060 template parameters.
12061 (ternary_resize2_lane_base): Likewise.
12062 (ternary_resize2_base): New class.
12063 (ternary_qq_lane_base): Likewise.
12064 (ternary_intq_uintq_lane_def): Likewise.
12065 (ternary_intq_uintq_lane): New shape.
12066 (ternary_intq_uintq_opt_n_def): New class
12067 (ternary_intq_uintq_opt_n): New shape.
12068 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
12069 (ternary_uintq_intq_def): New class.
12070 (ternary_uintq_intq): New shape.
12071 (ternary_uintq_intq_lane_def): New class.
12072 (ternary_uintq_intq_lane): New shape.
12073 (ternary_uintq_intq_opt_n_def): New class.
12074 (ternary_uintq_intq_opt_n): New shape.
12075 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
12076 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
12077 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
12078 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
12080 (svdotprod_lane_impl): ...this new class.
12081 (svmmla_impl, svusdot_impl): New classes.
12082 (svdot_lane): Update to use svdotprod_lane_impl.
12083 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
12084 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
12086 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
12087 function, with no types defined.
12088 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
12089 AARCH64_FL_I8MM functions.
12090 (svmmla): New AARCH64_FL_F32MM function.
12091 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
12092 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
12093 AARCH64_FL_F64MM function.
12094 (REQUIRED_EXTENSIONS):
12096 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
12098 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
12101 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
12103 * config/i386/i386.md (*movoi_internal_avx): Do not check for
12104 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
12105 (*movti_internal): Do not check for
12106 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
12107 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
12108 just after check for TARGET_AVX.
12109 (*movdf_internal): Ditto.
12110 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
12111 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
12112 * config/i386/sse.md (mov<mode>_internal): Only check
12113 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
12114 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
12115 (<sse>_andnot<mode>3<mask_name>): Move check for
12116 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
12117 (<code><mode>3<mask_name>): Ditto.
12118 (*andnot<mode>3): Ditto.
12119 (*andnottf3): Ditto.
12120 (*<code><mode>3): Ditto.
12121 (*<code>tf3): Ditto.
12122 (*andnot<VI:mode>3): Remove
12123 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
12124 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
12125 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
12126 (sse4_1_blendv<ssemodesuffix>): Ditto.
12127 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
12128 Explain that tune applies to 128bit instructions only.
12130 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
12132 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
12133 to definition of hsa_kernel_description. Parse assembly to find SGPR
12134 and VGPR count of kernel and store in hsa_kernel_description.
12136 2020-01-31 Tamar Christina <tamar.christina@arm.com>
12138 PR rtl-optimization/91838
12139 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
12140 to truncate if allowed or reject combination.
12142 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
12144 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
12145 (find_inv_vars_cb): Likewise.
12147 2020-01-31 David Malcolm <dmalcolm@redhat.com>
12149 * calls.c (special_function_p): Split out the check for DECL_NAME
12150 being non-NULL and fndecl being extern at file scope into a
12151 new maybe_special_function_p and call it. Drop check for fndecl
12152 being non-NULL that was after a usage of DECL_NAME (fndecl).
12153 * tree.h (maybe_special_function_p): New inline function.
12155 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
12157 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
12158 (mask_gather_load<mode>): ... here, and zero-initialize the
12160 (maskload<mode>di): Zero-initialize the destination.
12161 * config/gcn/gcn.c:
12163 2020-01-30 David Malcolm <dmalcolm@redhat.com>
12166 * doc/analyzer.texi (Limitations): Note that constraints on
12167 floating-point values are currently ignored.
12169 2020-01-30 Jakub Jelinek <jakub@redhat.com>
12172 * symtab.c (symtab_node::noninterposable_alias): If localalias
12173 already exists, but is not usable, append numbers after it until
12174 a unique name is found. Formatting fix.
12176 PR middle-end/93505
12177 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
12180 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
12182 * config/gcn/gcn.c (print_operand): Handle LTGT.
12183 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
12185 2020-01-30 Richard Biener <rguenther@suse.de>
12187 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
12188 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
12190 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
12192 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
12193 without a DECL in .data.rel.ro.local.
12195 2020-01-30 Jakub Jelinek <jakub@redhat.com>
12198 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
12202 * config/i386/sse.md
12203 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
12204 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
12205 any_extend code iterator instead of always zero_extend.
12206 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
12207 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
12208 Use any_extend code iterator instead of always zero_extend.
12209 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
12210 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
12211 Use any_extend code iterator instead of always zero_extend.
12212 (*sse2_pmovmskb_ext): New define_insn.
12213 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
12216 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
12217 (*popcountsi2_zext_falsedep): New define_insn.
12219 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
12221 * config.in: Regenerated.
12222 * configure: Regenerated.
12224 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
12227 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
12228 LLVM's assembler changed the default in version 9.
12230 2020-01-24 Jeff Law <law@redhat.com>
12232 PR tree-optimization/89689
12233 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
12235 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
12239 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12241 PR rtl-optimization/87763
12242 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
12243 simplification to handle subregs as well as bare regs.
12244 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
12246 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
12249 * ira.c (ira): Revert use of simplified LRA algorithm.
12251 2020-01-29 Martin Jambor <mjambor@suse.cz>
12253 PR tree-optimization/92706
12254 * tree-sra.c (struct access): Fields first_link, last_link,
12255 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
12256 next_rhs_queued and grp_rhs_queued respectively, new fields
12257 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
12258 (struct assign_link): Field next renamed to next_rhs, new field
12259 next_lhs. Updated comment.
12260 (work_queue_head): Renamed to rhs_work_queue_head.
12261 (lhs_work_queue_head): New variable.
12262 (add_link_to_lhs): New function.
12263 (relink_to_new_repr): Also relink LHS lists.
12264 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
12265 (add_access_to_lhs_work_queue): New function.
12266 (pop_access_from_work_queue): Renamed to
12267 pop_access_from_rhs_work_queue.
12268 (pop_access_from_lhs_work_queue): New function.
12269 (build_accesses_from_assign): Also add links to LHS lists and to LHS
12271 (child_would_conflict_in_lacc): Renamed to
12272 child_would_conflict_in_acc. Adjusted parameter names.
12273 (create_artificial_child_access): New parameter set_grp_read, use it.
12274 (subtree_mark_written_and_enqueue): Renamed to
12275 subtree_mark_written_and_rhs_enqueue.
12276 (propagate_subaccesses_across_link): Renamed to
12277 propagate_subaccesses_from_rhs.
12278 (propagate_subaccesses_from_lhs): New function.
12279 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
12282 2020-01-29 Martin Jambor <mjambor@suse.cz>
12284 PR tree-optimization/92706
12285 * tree-sra.c (struct access): Adjust comment of
12286 grp_total_scalarization.
12287 (find_access_in_subtree): Look for single children spanning an entire
12289 (scalarizable_type_p): Allow register accesses, adjust callers.
12290 (completely_scalarize): Remove function.
12291 (scalarize_elem): Likewise.
12292 (create_total_scalarization_access): Likewise.
12293 (sort_and_splice_var_accesses): Do not track total scalarization
12295 (analyze_access_subtree): New parameter totally, adjust to new meaning
12296 of grp_total_scalarization.
12297 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
12298 (can_totally_scalarize_forest_p): New function.
12299 (create_total_scalarization_access): Likewise.
12300 (create_total_access_and_reshape): Likewise.
12301 (total_should_skip_creating_access): Likewise.
12302 (totally_scalarize_subtree): Likewise.
12303 (analyze_all_variable_accesses): Perform total scalarization after
12304 subaccess propagation using the new functions above.
12305 (initialize_constant_pool_replacements): Output initializers by
12306 traversing the access tree.
12308 2020-01-29 Martin Jambor <mjambor@suse.cz>
12310 * tree-sra.c (verify_sra_access_forest): New function.
12311 (verify_all_sra_access_forests): Likewise.
12312 (create_artificial_child_access): Set parent.
12313 (analyze_all_variable_accesses): Call the verifier.
12315 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12317 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
12318 if called on indirect edge.
12319 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
12320 speculative call if needed.
12322 2020-01-29 Richard Biener <rguenther@suse.de>
12324 PR tree-optimization/93428
12325 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
12326 permutation when the load node is created.
12327 (vect_analyze_slp_instance): Re-use it here.
12329 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12331 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
12333 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
12335 PR rtl-optimization/93272
12336 * ira-lives.c (process_out_of_region_eh_regs): New function.
12337 (process_bb_node_lives): Call it.
12339 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12341 * coverage.c (read_counts_file): Make error message lowercase.
12343 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12345 * profile-count.c (profile_quality_display_names): Fix ordering.
12347 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12350 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
12351 hash only when edge is first within the sequence.
12352 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
12353 (symbol_table::create_edge): Do not set target_prob.
12354 (cgraph_edge::remove_caller): Watch for speculative calls when updating
12355 the call site hash.
12356 (cgraph_edge::make_speculative): Drop target_prob parameter.
12357 (cgraph_edge::speculative_call_info): Remove.
12358 (cgraph_edge::first_speculative_call_target): New member function.
12359 (update_call_stmt_hash_for_removing_direct_edge): New function.
12360 (cgraph_edge::resolve_speculation): Rewrite to new API.
12361 (cgraph_edge::speculative_call_for_target): New member function.
12362 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
12363 multiple speculation targets.
12364 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
12366 (verify_speculative_call): Verify that targets form an interval.
12367 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
12368 (cgraph_edge::first_speculative_call_target): New member function.
12369 (cgraph_edge::next_speculative_call_target): New member function.
12370 (cgraph_edge::speculative_call_target_ref): New member function.
12371 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
12372 (cgraph_edge): Remove target_prob.
12373 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
12374 Fix handling of speculative calls.
12375 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
12376 * ipa-fnsummary.c (analyze_function_body): Likewise.
12377 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
12378 * ipa-profile.c (dump_histogram): Fix formating.
12379 (ipa_profile_generate_summary): Watch for overflows.
12380 (ipa_profile): Do not require probablity to be 1/2; update to new API.
12381 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
12382 (update_indirect_edges_after_inlining): Update to new API.
12383 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
12385 * profile-count.h: (profile_probability::adjusted): New.
12386 * tree-inline.c (copy_bb): Update to new speculative call API; fix
12387 updating of profile.
12388 * value-prof.c (gimple_ic_transform): Rename to ...
12389 (dump_ic_profile): ... this one; update dumping.
12390 (stream_in_histogram_value): Fix formating.
12391 (gimple_value_profile_transformations): Update.
12393 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
12396 * config/i386/i386.md (*movoi_internal_avx): Remove
12397 TARGET_SSE_TYPELESS_STORES check.
12398 (*movti_internal): Prefer TARGET_AVX over
12399 TARGET_SSE_TYPELESS_STORES.
12400 (*movtf_internal): Likewise.
12401 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
12402 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
12403 from TARGET_SSE_TYPELESS_STORES.
12405 2020-01-28 David Malcolm <dmalcolm@redhat.com>
12407 * diagnostic-core.h (warning_at): Rename overload to...
12408 (warning_meta): ...this.
12409 (emit_diagnostic_valist): Delete decl of overload taking
12410 diagnostic_metadata.
12411 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
12412 (warning_at): Rename overload taking diagnostic_metadata to...
12413 (warning_meta): ...this.
12415 2020-01-28 Richard Biener <rguenther@suse.de>
12417 PR tree-optimization/93439
12418 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
12419 * tree-cfg.c (move_sese_region_to_fn): ... here.
12420 (verify_types_in_gimple_reference): Verify used cliques are
12423 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
12426 * config/i386/i386-options.c (set_ix86_tune_features): Add an
12427 argument of a pointer to struct gcc_options and pass it to
12428 parse_mtune_ctrl_str.
12429 (ix86_function_specific_restore): Pass opts to
12430 set_ix86_tune_features.
12431 (ix86_option_override_internal): Likewise.
12432 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
12433 gcc_options and use it for x_ix86_tune_ctrl_string.
12435 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12437 PR rtl-optimization/87763
12438 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
12439 simplification to handle subregs as well as bare regs.
12440 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
12442 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12444 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
12445 for reduction chains that (now) include a call.
12447 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12449 PR tree-optimization/92822
12450 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
12451 out the don't-care elements of a vector whose significant elements
12452 are duplicates, make the don't-care elements duplicates too.
12454 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12456 PR tree-optimization/93434
12457 * tree-predcom.c (split_data_refs_to_components): Record which
12458 components have had aliasing loads removed. Prevent store-store
12459 commoning for all such components.
12461 2020-01-28 Jakub Jelinek <jakub@redhat.com>
12464 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
12465 -1 or is_vshift is true, use new_vector with number of elts npatterns
12466 rather than new_unary_operation.
12468 PR tree-optimization/93454
12469 * gimple-fold.c (fold_array_ctor_reference): Perform
12470 elt_size.to_uhwi () just once, instead of calling it in every
12471 iteration. Punt if that value is above size of the temporary
12472 buffer. Decrease third native_encode_expr argument when
12473 bufoff + elt_sz is above size of buf.
12475 2020-01-27 Joseph Myers <joseph@codesourcery.com>
12477 * config/mips/mips.c (mips_declare_object_name)
12478 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
12480 2020-01-27 Martin Liska <mliska@suse.cz>
12482 PR gcov-profile/93403
12483 * tree-profile.c (gimple_init_gcov_profiler): Generate
12484 both __gcov_indirect_call_profiler_v4 and
12485 __gcov_indirect_call_profiler_v4_atomic.
12487 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12490 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
12492 (@aarch64_split_simd_mov<mode>): Use it.
12493 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
12494 Leave the vec_extract patterns to handle 2-element vectors.
12495 (aarch64_simd_mov_from_<mode>high): Likewise.
12496 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
12497 (vec_extractv2dfv1df): Likewise.
12499 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12501 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
12502 jump conditions for *compare_condjump<GPI:mode>.
12504 2020-01-27 David Malcolm <dmalcolm@redhat.com>
12507 * digraph.cc (test_edge::test_edge): Specify template for base
12510 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
12512 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
12514 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
12516 * config/arc/arc-protos.h (gen_mlo): Remove.
12517 (gen_mhi): Likewise.
12518 * config/arc/arc.c (AUX_MULHI): Define.
12519 (arc_must_save_reister): Special handling for r58/59.
12520 (arc_compute_frame_size): Consider mlo/mhi registers.
12521 (arc_save_callee_saves): Emit fp/sp move only when emit_move
12523 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
12524 mlo/mhi name selection.
12525 (arc_restore_callee_saves): Don't early restore blink when ISR.
12526 (arc_expand_prologue): Add mlo/mhi saving.
12527 (arc_expand_epilogue): Add mlo/mhi restoring.
12530 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
12531 numbering when MUL64 option is used.
12532 (DWARF2_FRAME_REG_OUT): Define.
12533 * config/arc/arc.md (arc600_stall): New pattern.
12534 (VUNSPEC_ARC_ARC600_STALL): Define.
12535 (mulsi64): Use correct mlo/mhi registers.
12536 (mulsi_600): Clean it up.
12537 * config/arc/predicates.md (mlo_operand): Remove any dependency on
12539 (mhi_operand): Likewise.
12541 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
12542 Petro Karashchenko <petro.karashchenko@ring.com>
12544 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
12545 attributes if needed.
12546 (prepare_move_operands): Generate special unspec instruction for
12548 (arc_isuncached_mem_p): Propagate uncached attribute to each
12550 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
12551 (VUNSPEC_ARC_STDI): Likewise.
12552 (ALLI): New mode iterator.
12553 (mALLI): New mode attribute.
12554 (lddi): New instruction pattern.
12556 (stdidi_split): Split instruction for architectures which are not
12557 supporting ll64 option.
12558 (lddidi_split): Likewise.
12560 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12562 PR rtl-optimization/92989
12563 * lra-lives.c (process_bb_lives): Update the live-in set before
12564 processing additional clobbers.
12566 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12568 PR rtl-optimization/93170
12569 * cselib.c (cselib_invalidate_regno_val): New function, split out
12571 (cselib_invalidate_regno): ...here.
12572 (cselib_invalidated_by_call_p): New function.
12573 (cselib_process_insn): Iterate over all the hard-register entries in
12574 REG_VALUES and invalidate any that cross call-clobbered registers.
12576 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12578 * dojump.c (split_comparison): Use HONOR_NANS rather than
12579 HONOR_SNANS when splitting LTGT.
12581 2020-01-27 Martin Liska <mliska@suse.cz>
12584 * opts.c (print_filtered_help): Exclude language-specific
12585 options from --help=common unless enabled in all FEs.
12587 2020-01-27 Martin Liska <mliska@suse.cz>
12589 * opts.c (print_help): Exclude params from
12590 all except --help=param.
12592 2020-01-27 Martin Liska <mliska@suse.cz>
12595 * config/i386/i386-features.c (make_resolver_func):
12596 Align the code with ppc64 target implementation.
12597 Do not generate a unique name for resolver function.
12599 2020-01-27 Richard Biener <rguenther@suse.de>
12601 PR tree-optimization/93397
12602 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
12603 converted reduction chain SLP graph adjustment.
12605 2020-01-26 Marek Polacek <polacek@redhat.com>
12608 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
12611 2020-01-26 Jason Merrill <jason@redhat.com>
12614 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
12617 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
12619 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
12620 (rx_setmem): Likewise.
12622 2020-01-26 Jakub Jelinek <jakub@redhat.com>
12625 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
12626 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
12627 drop <di> from constraint of last operand.
12630 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
12631 TARGET_AVX2 and V4DFmode not in the split condition, but in the
12632 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
12634 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
12637 * ipa-cp.c (get_info_about_necessary_edges): Remove value
12640 2020-01-24 Jeff Law <law@redhat.com>
12642 PR tree-optimization/92788
12643 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
12646 2020-01-24 Jakub Jelinek <jakub@redhat.com>
12649 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
12650 *avx_vperm_broadcast_<mode>,
12651 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
12652 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
12653 Move before avx2_perm<mode>/avx512f_perm<mode>.
12656 * simplify-rtx.c (simplify_const_unary_operation,
12657 simplify_const_binary_operation): Punt for mode precision above
12658 MAX_BITSIZE_MODE_ANY_INT.
12660 2020-01-24 Andrew Pinski <apinski@marvell.com>
12662 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
12663 alu.shift_reg to 0.
12665 2020-01-24 Jeff Law <law@redhat.com>
12668 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
12669 for REGs. Call output_operand_lossage to get more reasonable
12672 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
12674 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
12675 gcn_fp_compare_operator.
12676 (vec_cmpu<mode>di): Use gcn_compare_operator.
12677 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
12678 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
12679 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
12680 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
12681 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
12682 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
12683 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
12684 gcn_fp_compare_operator.
12685 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
12686 gcn_fp_compare_operator.
12687 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
12688 gcn_fp_compare_operator.
12689 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
12690 gcn_fp_compare_operator.
12692 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
12694 * doc/install.texi (Cross-Compiler-Specific Options): Document
12695 `--with-toolexeclibdir' option.
12697 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
12699 * target.def (flags_regnum): Also mention effect on delay slot filling.
12700 * doc/tm.texi: Regenerate.
12702 2020-01-23 Jeff Law <law@redhat.com>
12704 PR translation/90162
12705 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
12707 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
12710 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
12713 2020-01-23 Jakub Jelinek <jakub@redhat.com>
12715 PR rtl-optimization/93402
12716 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
12719 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
12721 * config.in: Regenerated.
12722 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
12723 for TARGET_LIBC_GNUSTACK.
12724 * configure: Regenerated.
12725 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
12726 found to be 2.31 or greater.
12728 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
12730 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
12732 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
12733 (mips_asm_file_end): New function. Delegate to
12734 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
12735 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
12737 2020-01-23 Jakub Jelinek <jakub@redhat.com>
12740 * config/i386/i386-modes.def (POImode): New mode.
12741 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
12742 * config/i386/i386.md (DPWI): New mode attribute.
12743 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
12744 (QWI): Rename to...
12745 (QPWI): ... this. Use POI instead of OI for TImode.
12746 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
12747 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
12750 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
12753 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
12755 (speculation_tracker_rev): New pattern.
12756 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
12757 Use speculation_tracker_rev to track the inverse condition.
12759 2020-01-23 Richard Biener <rguenther@suse.de>
12761 PR tree-optimization/93381
12762 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
12763 alias-set of the def as argument and record the first one.
12764 (vn_walk_cb_data::first_set): New member.
12765 (vn_reference_lookup_3): Pass the alias-set of the current def
12766 to push_partial_def. Fix alias-set used in the aggregate copy
12768 (vn_reference_lookup): Consistently set *last_vuse_ptr.
12769 * real.c (clear_significand_below): Fix out-of-bound access.
12771 2020-01-23 Jakub Jelinek <jakub@redhat.com>
12774 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
12775 New define_insn patterns.
12777 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
12779 * doc/sourcebuild.texi (check-function-bodies): Add an
12780 optional target/xfail selector.
12782 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
12784 PR rtl-optimization/93124
12785 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
12786 bare USE and CLOBBER insns.
12788 2020-01-22 Andrew Pinski <apinski@marvell.com>
12790 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
12792 2020-01-22 David Malcolm <dmalcolm@redhat.com>
12795 * gdbinit.in (break-on-saved-diagnostic): Update for move of
12796 diagnostic_manager into "ana" namespace.
12797 * selftest-run-tests.c (selftest::run_tests): Update for move of
12798 selftest::run_analyzer_selftests to
12799 ana::selftest::run_analyzer_selftests.
12801 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
12803 * cfgexpand.c (union_stack_vars): Update the size.
12805 2020-01-22 Richard Biener <rguenther@suse.de>
12807 PR tree-optimization/93381
12808 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
12809 throughout, handle all conversions the same.
12811 2020-01-22 Jakub Jelinek <jakub@redhat.com>
12814 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
12815 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
12816 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
12817 Call force_reg on high_in2 unconditionally.
12819 2020-01-22 Martin Liska <mliska@suse.cz>
12821 PR tree-optimization/92924
12822 * profile.c (compute_value_histograms): Divide
12823 all counter values.
12825 2020-01-22 Jakub Jelinek <jakub@redhat.com>
12828 * output.h (assemble_name_resolve): Declare.
12829 * varasm.c (assemble_name_resolve): New function.
12830 (assemble_name): Use it.
12831 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
12833 2020-01-22 Joseph Myers <joseph@codesourcery.com>
12835 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
12836 update_web_docs_git instead of update_web_docs_svn.
12838 2020-01-21 Andrew Pinski <apinski@marvell.com>
12841 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
12842 as PTR mode. Have operand 1 as being modeless, it can be P mode.
12843 (*tlsgd_small_<mode>): Likewise.
12844 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
12845 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
12846 register. Convert that register back to dest using convert_mode.
12848 2020-01-21 Jim Wilson <jimw@sifive.com>
12850 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
12853 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
12854 Uros Bizjak <ubizjak@gmail.com>
12857 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
12859 (legitimize_tls_address): Do GNU2 TLS address computation in
12860 ptr_mode and zero-extend result to Pmode.
12861 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
12862 :P with :PTR and Pmode with ptr_mode.
12863 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
12864 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
12865 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
12867 2020-01-21 Jakub Jelinek <jakub@redhat.com>
12870 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
12871 the last two operands are CONST_INT_P before using them as such.
12873 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
12875 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
12876 to get the integer element types.
12878 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
12880 * config/aarch64/aarch64-sve-builtins.h
12881 (function_expander::convert_to_pmode): Declare.
12882 * config/aarch64/aarch64-sve-builtins.cc
12883 (function_expander::convert_to_pmode): New function.
12884 (function_expander::get_contiguous_base): Use it.
12885 (function_expander::prepare_gather_address_operands): Likewise.
12886 * config/aarch64/aarch64-sve-builtins-sve2.cc
12887 (svwhilerw_svwhilewr_impl::expand): Likewise.
12889 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
12892 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
12893 cfun->machine->label_is_assembled.
12894 (aarch64_print_patchable_function_entry): New.
12895 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
12896 * config/aarch64/aarch64.h (struct machine_function): New field,
12897 label_is_assembled.
12899 2020-01-21 David Malcolm <dmalcolm@redhat.com>
12902 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
12905 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
12908 * cgraph.c (cgraph_edge::resolve_speculation,
12909 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
12910 call_stmt_site_hash.
12912 2020-01-21 Martin Liska <mliska@suse.cz>
12914 * config/rs6000/rs6000.c (common_mode_defined): Remove
12917 2020-01-21 Richard Biener <rguenther@suse.de>
12919 PR tree-optimization/92328
12920 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
12921 type when value-numbering same-sized store by inserting a
12923 (eliminate_dom_walker::eliminate_stmt): When eliminating
12924 a redundant store handle bit-reinterpretation of the same value.
12926 2020-01-21 Andrew Pinski <apinski@marvel.com>
12929 * tree-into-ssa.c (prepare_block_for_update_1): Split out
12931 (prepare_block_for_update): This. Use a worklist instead of
12934 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
12936 * gcc/config/arm/arm.c (clear_operation_p):
12937 Initialise last_regno, skip first iteration
12938 based on the first_set value and use ints instead
12939 of the unnecessary HOST_WIDE_INTs.
12941 2020-01-21 Jakub Jelinek <jakub@redhat.com>
12944 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
12945 compare_mode other than SFmode or DFmode.
12947 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
12950 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
12951 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
12952 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
12954 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
12956 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
12958 2020-01-20 Andrew Pinski <apinski@marvell.com>
12960 PR middle-end/93242
12961 * targhooks.c (default_print_patchable_function_entry): Use
12962 output_asm_insn to emit the nop instruction.
12964 2020-01-20 Fangrui Song <maskray@google.com>
12966 PR middle-end/93194
12967 * targhooks.c (default_print_patchable_function_entry): Align to
12970 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
12973 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
12974 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
12975 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
12976 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
12977 (*tls_dynamic_gnu2_lea_64): Renamed to ...
12978 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
12979 Remove the {q} suffix from lea.
12980 (*tls_dynamic_gnu2_call_64): Renamed to ...
12981 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
12982 (*tls_dynamic_gnu2_combine_64): Renamed to ...
12983 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
12984 Pass Pmode to gen_tls_dynamic_gnu2_64.
12986 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
12988 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
12990 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
12992 * config/aarch64/aarch64-sve-builtins-base.cc
12993 (svld1ro_impl::memory_vector_mode): Remove parameter name.
12995 2020-01-20 Richard Biener <rguenther@suse.de>
12998 * dwarf2out.c (prune_unused_types): Unconditionally mark
12999 called function DIEs.
13001 2020-01-20 Martin Liska <mliska@suse.cz>
13003 PR tree-optimization/93199
13004 * tree-eh.c (struct leh_state): Add
13005 new field outer_non_cleanup.
13006 (cleanup_is_dead_in): Pass leh_state instead
13007 of eh_region. Add a checking that state->outer_non_cleanup
13008 points to outer non-clean up region.
13009 (lower_try_finally): Record outer_non_cleanup
13011 (lower_catch): Likewise.
13012 (lower_eh_filter): Likewise.
13013 (lower_eh_must_not_throw): Likewise.
13014 (lower_cleanup): Likewise.
13016 2020-01-20 Richard Biener <rguenther@suse.de>
13018 PR tree-optimization/93094
13019 * tree-vectorizer.h (vect_loop_versioning): Adjust.
13020 (vect_transform_loop): Likewise.
13021 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
13022 loop_vectorized_call to vect_transform_loop.
13023 * tree-vect-loop.c (vect_transform_loop): Pass down
13024 loop_vectorized_call to vect_loop_versioning.
13025 * tree-vect-loop-manip.c (vect_loop_versioning): Use
13026 the earlier discovered loop_vectorized_call.
13028 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
13030 * doc/contribute.texi: Update for SVN -> Git transition.
13031 * doc/install.texi: Likewise.
13033 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
13036 * cgraph.c (cgraph_edge::make_speculative): Increase number of
13037 speculative targets.
13038 (verify_speculative_call): New function
13039 (cgraph_node::verify_node): Use it.
13040 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
13043 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
13046 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
13047 (cgraph_edge::make_direct): Remove all indirect targets.
13048 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
13049 (cgraph_node::verify_node): Verify that only one call_stmt or
13050 lto_stmt_uid is set.
13051 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
13053 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
13054 (lto_output_ref): Simplify streaming of stmt.
13055 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
13057 2020-01-18 Tamar Christina <tamar.christina@arm.com>
13059 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
13060 Mark parameter unused.
13062 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
13064 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
13066 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
13068 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
13070 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
13072 * Makefile.in: Add coroutine-passes.o.
13073 * builtin-types.def (BT_CONST_SIZE): New.
13074 (BT_FN_BOOL_PTR): New.
13075 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
13076 * builtins.def (DEF_COROUTINE_BUILTIN): New.
13077 * coroutine-builtins.def: New file.
13078 * coroutine-passes.cc: New file.
13079 * function.h (struct GTY function): Add a bit to indicate that the
13080 function is a coroutine component.
13081 * internal-fn.c (expand_CO_FRAME): New.
13082 (expand_CO_YIELD): New.
13083 (expand_CO_SUSPN): New.
13084 (expand_CO_ACTOR): New.
13085 * internal-fn.def (CO_ACTOR): New.
13089 * passes.def: Add pass_coroutine_lower_builtins,
13090 pass_coroutine_early_expand_ifns.
13091 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
13092 (make_pass_coroutine_early_expand_ifns): New.
13093 * doc/invoke.texi: Document the fcoroutines command line
13096 2020-01-18 Jakub Jelinek <jakub@redhat.com>
13098 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
13101 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
13102 after checking the argument is a REG. Don't use REGNO (reg)
13103 again to set last_regno, reuse regno variable instead.
13105 2020-01-17 David Malcolm <dmalcolm@redhat.com>
13107 * doc/analyzer.texi (Limitations): Add note about NaN.
13109 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13110 Sudakshina Das <sudi.das@arm.com>
13112 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
13113 and valid immediate.
13114 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
13115 (lshrdi3): Generate thumb2_lsrl for valid immediates.
13116 * config/arm/constraints.md (Pg): New.
13117 * config/arm/predicates.md (long_shift_imm): New.
13118 (arm_reg_or_long_shift_imm): Likewise.
13119 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
13120 (thumb2_lsll): Likewise.
13121 (thumb2_lsrl): New.
13123 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13124 Sudakshina Das <sudi.das@arm.com>
13126 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
13127 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
13128 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
13129 register pairs for doubleword quantities for ARMv8.1M-Mainline.
13130 * config/arm/thumb2.md (thumb2_asrl): New.
13131 (thumb2_lsll): Likewise.
13133 2020-01-17 Jakub Jelinek <jakub@redhat.com>
13135 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
13138 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
13140 * gdbinit.in (help-gcc-hooks): New command.
13141 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
13142 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
13145 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
13147 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
13148 correct target macro.
13150 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
13152 * config/aarch64/aarch64-protos.h
13153 (aarch64_sve_ld1ro_operand_p): New.
13154 * config/aarch64/aarch64-sve-builtins-base.cc
13155 (class load_replicate): New.
13156 (class svld1ro_impl): New.
13157 (class svld1rq_impl): Change to inherit from load_replicate.
13158 (svld1ro): New sve intrinsic function base.
13159 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
13160 New DEF_SVE_FUNCTION.
13161 * config/aarch64/aarch64-sve-builtins-base.h
13162 (svld1ro): New decl.
13163 * config/aarch64/aarch64-sve-builtins.cc
13164 (function_expander::add_mem_operand): Modify assert to allow
13166 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
13168 * config/aarch64/aarch64.c
13169 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
13170 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
13171 (aarch64_sve_ld1ro_operand_p): New.
13172 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
13173 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
13174 * config/aarch64/predicates.md
13175 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
13177 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
13179 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
13180 Introduce this ACLE specified predefined macro.
13181 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
13182 (fp): Disabling this disables f64mm.
13183 (simd): Disabling this disables f64mm.
13184 (fp16): Disabling this disables f64mm.
13185 (sve): Disabling this disables f64mm.
13186 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
13187 (AARCH64_ISA_F64MM): New.
13188 (TARGET_F64MM): New.
13189 * doc/invoke.texi (f64mm): Document new option.
13191 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
13193 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
13194 (neoversen1_tunings): Likewise.
13196 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
13199 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
13200 Add assert to ensure prolog has been emitted.
13201 (aarch64_split_atomic_op): Likewise.
13202 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
13203 Use epilogue_completed rather than reload_completed.
13204 (aarch64_atomic_exchange<mode>): Likewise.
13205 (aarch64_atomic_<atomic_optab><mode>): Likewise.
13206 (atomic_nand<mode>): Likewise.
13207 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
13208 (atomic_fetch_nand<mode>): Likewise.
13209 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
13210 (atomic_nand_fetch<mode>): Likewise.
13212 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
13215 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
13217 (REVERSE_CONDITION): Delete.
13218 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
13219 (CCFP_CCFPE): Likewise.
13220 (e): New mode attribute.
13221 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
13222 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
13223 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
13224 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
13225 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
13226 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
13227 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
13228 name of generator from gen_ccmpdi to gen_ccmpccdi.
13229 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
13230 the previous comparison but aren't able to, use the new ccmp_rev
13233 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
13235 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
13236 than testing directly for INTEGER_CST.
13237 (gimplify_target_expr, gimplify_omp_depend): Likewise.
13239 2020-01-17 Jakub Jelinek <jakub@redhat.com>
13241 PR tree-optimization/93292
13242 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
13243 get_vectype_for_scalar_type returns NULL.
13245 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
13247 * params.opt (-param=max-predicted-iterations): Increase range from 0.
13248 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
13250 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
13252 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
13254 * params.opt: (max-predicted-iterations): Set bounds.
13255 * predict.c (real_almost_one, real_br_prob_base,
13256 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
13257 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
13258 probabilities; do not truncate to reg_br_prob_bases.
13259 (estimate_loops_at_level): Pass max_cyclic_prob.
13260 (estimate_loops): Compute max_cyclic_prob.
13261 (estimate_bb_frequencies): Do not initialize real_*; update calculation
13263 * profile-count.c (profile_probability::to_sreal): New.
13264 * profile-count.h (class sreal): Move up in file.
13265 (profile_probability::to_sreal): Declare.
13267 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13270 (arm_invalid_conversion): New function for target hook.
13271 (arm_invalid_unary_op): New function for target hook.
13272 (arm_invalid_binary_op): New function for target hook.
13274 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13276 * config.gcc: Add arm_bf16.h.
13277 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
13278 (arm_simd_builtin_std_type): Add BFmode.
13279 (arm_init_simd_builtin_types): Define element types for vector types.
13280 (arm_init_bf16_types): New function.
13281 (arm_init_builtins): Add arm_init_bf16_types function call.
13282 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
13283 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
13284 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
13285 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
13286 (arm_vector_mode_supported_p): Add V4BF, V8BF.
13287 (arm_mangle_type): Add __bf16.
13288 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
13289 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
13290 arm_bf16_ptr_type_node.
13291 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
13292 define_split between ARM registers.
13293 * config/arm/arm_bf16.h: New file.
13294 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
13295 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
13296 (VQXMOV): Add V8BF.
13297 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
13298 * config/arm/vfp.md: Add BFmode to movhf patterns.
13300 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
13301 Andre Vieira <andre.simoesdiasvieira@arm.com>
13303 * config/arm/arm-cpus.in (mve, mve_float): New features.
13304 (dsp, mve, mve.fp): New options.
13305 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
13306 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
13307 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
13309 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13310 Thomas Preud'homme <thomas.preudhomme@arm.com>
13312 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
13314 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
13315 error for using -mcmse when targeting Armv8.1-M Mainline.
13317 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13318 Thomas Preud'homme <thomas.preudhomme@arm.com>
13320 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
13321 address in r4 when targeting Armv8.1-M Mainline.
13322 (nonsecure_call_value_internal): Likewise.
13323 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
13324 a register match_operand again. Emit BLXNS when targeting
13325 Armv8.1-M Mainline.
13326 (nonsecure_call_value_reg_thumb2): Likewise.
13328 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13329 Thomas Preud'homme <thomas.preudhomme@arm.com>
13331 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
13332 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
13333 variable as true when floating-point ABI is not hard. Replace
13334 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
13335 Generate VLSTM and VLLDM instruction respectively before and
13336 after a function call to cmse_nonsecure_call function.
13337 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
13338 (VUNSPEC_VLLDM): Likewise.
13339 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
13340 (lazy_load_multiple_insn): Likewise.
13342 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13343 Thomas Preud'homme <thomas.preudhomme@arm.com>
13345 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
13346 (arm_emit_vfp_multi_reg_pop): Likewise.
13347 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
13348 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
13349 restore callee-saved VFP registers.
13351 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13352 Thomas Preud'homme <thomas.preudhomme@arm.com>
13354 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
13355 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
13356 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
13357 callee-saved GPRs as well as clear ip register before doing a nonsecure
13358 call then restore callee-saved GPRs after it when targeting
13359 Armv8.1-M Mainline.
13360 (arm_reorg): Adapt to function rename.
13362 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13363 Thomas Preud'homme <thomas.preudhomme@arm.com>
13365 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
13366 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
13367 clear_vfp_multiple pattern based on a new vfp parameter.
13368 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
13369 targeting Armv8.1-M Mainline.
13370 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
13371 unconditionally when targeting Armv8.1-M Mainline architecture. Check
13372 whether VFP registers are available before looking call_used_regs for a
13374 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
13375 of prototype of clear_operation_p.
13376 (clear_vfp_multiple_operation): New predicate.
13377 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
13378 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
13380 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13381 Thomas Preud'homme <thomas.preudhomme@arm.com>
13383 * config/arm/arm-protos.h (clear_operation_p): Declare.
13384 * config/arm/arm.c (clear_operation_p): New function.
13385 (cmse_clear_registers): Generate clear_multiple instruction pattern if
13386 targeting Armv8.1-M Mainline or successor.
13387 (output_return_instruction): Only output APSR register clearing if
13388 Armv8.1-M Mainline instructions not available.
13389 (thumb_exit): Likewise.
13390 * config/arm/predicates.md (clear_multiple_operation): New predicate.
13391 * config/arm/thumb2.md (clear_apsr): New define_insn.
13392 (clear_multiple): Likewise.
13393 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
13395 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13396 Thomas Preud'homme <thomas.preudhomme@arm.com>
13398 * config/arm/arm.c (fp_sysreg_names): Declare and define.
13399 (use_return_insn): Also return false for Armv8.1-M Mainline.
13400 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
13401 Mainline instructions are available.
13402 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
13403 when targeting Armv8.1-M Mainline Security Extensions.
13404 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
13405 Mainline entry function.
13406 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
13407 targeting Armv8.1-M Mainline or successor.
13408 (arm_expand_epilogue): Fix indentation of caller-saved register
13409 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
13411 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
13412 (FP_SYSREGS): Likewise.
13413 (enum vfp_sysregs_encoding): Define enum.
13414 (fp_sysreg_names): Declare.
13415 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
13416 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
13417 (pop_fpsysreg_insn): Likewise.
13419 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13420 Thomas Preud'homme <thomas.preudhomme@arm.com>
13422 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
13423 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
13424 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
13425 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
13426 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
13427 (ARMv8_1m_main): New feature group.
13428 (armv8.1-m.main): New architecture.
13429 * config/arm/arm-tables.opt: Regenerate.
13430 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
13431 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
13432 (arm_options_perform_arch_sanity_checks): Error out when targeting
13433 Armv8.1-M Mainline Security Extensions.
13434 * config/arm/arm.h (arm_arch8_1m_main): Declare.
13436 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13438 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
13439 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
13440 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
13441 aarch64_bfdot_laneq): New.
13442 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
13443 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
13444 vbfdotq_laneq_f32): New.
13445 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
13446 VBFMLA_W, VBF): New.
13447 (isquadop): Add V4BF, V8BF.
13449 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13451 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
13452 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
13453 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
13454 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
13455 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
13456 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
13457 usdot_laneq, sudot_lane,sudot_laneq): New.
13458 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
13459 (aarch64_<sur>dot_lane): New.
13460 * config/aarch64/arm_neon.h (vusdot_s32): New.
13461 (vusdotq_s32): New.
13462 (vusdot_lane_s32): New.
13463 (vsudot_lane_s32): New.
13464 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
13465 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
13467 2020-01-16 Martin Liska <mliska@suse.cz>
13469 * value-prof.c (dump_histogram_value): Fix
13470 obvious spacing issue.
13472 2020-01-16 Andrew Pinski <apinski@marvell.com>
13474 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
13475 !storage_order_barrier_p.
13477 2020-01-16 Andrew Pinski <apinski@marvell.com>
13479 * sched-int.h (_dep): Add unused bit-field field for the padding.
13480 * sched-deps.c (init_dep_1): Init unused field.
13482 2020-01-16 Andrew Pinski <apinski@marvell.com>
13484 * optabs.h (create_expand_operand): Initialize target field also.
13486 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
13488 PR tree-optimization/92429
13489 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
13490 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
13492 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
13495 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
13497 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
13498 aarch64_sve_int_mode to each mode.
13500 2020-01-15 David Malcolm <dmalcolm@redhat.com>
13502 * doc/analyzer.texi (Overview): Add note about
13503 -fdump-ipa-analyzer.
13505 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
13507 PR tree-optimization/93231
13508 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
13509 input_type is unsigned. Use tree_to_shwi for shift constant.
13510 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
13511 (simplify_count_trailing_zeroes): Add test to handle known non-zero
13512 inputs more efficiently.
13514 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
13516 * config/i386/i386.md (*movsf_internal): Do not require
13517 SSE2 ISA for alternatives 14 and 15.
13519 2020-01-15 Richard Biener <rguenther@suse.de>
13521 PR middle-end/93273
13522 * tree-eh.c (sink_clobbers): If we already visited the destination
13523 block do not defer insertion.
13524 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
13525 the purpose of defered insertion.
13527 2020-01-15 Jakub Jelinek <jakub@redhat.com>
13529 * BASE-VER: Bump to 10.0.1.
13531 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
13533 PR tree-optimization/93247
13534 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
13535 type of the stmt that we're going to vectorize.
13537 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
13539 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
13540 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
13543 2020-01-15 Martin Liska <mliska@suse.cz>
13545 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
13546 2 calls of streamer_read_hwi in a function call.
13548 2020-01-15 Richard Biener <rguenther@suse.de>
13550 * alias.c (record_alias_subset): Avoid redundant work when
13551 subset is already recorded.
13553 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13555 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
13556 the analyzer options provide CWE identifiers.
13558 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13560 * tree-diagnostic-path.cc (path_summary::event_range::print):
13561 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
13562 using get_pure_location.
13564 2020-01-15 Jakub Jelinek <jakub@redhat.com>
13566 PR tree-optimization/93262
13567 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
13568 perform head trimming only if the last argument is constant,
13569 either all ones, or larger or equal to head trim, in the latter
13570 case decrease the last argument by head_trim.
13572 PR tree-optimization/93249
13573 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
13574 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
13575 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
13576 perform head trim unless we can prove there are no '\0' chars
13577 from the source among the first head_trim chars.
13579 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13581 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
13583 2020-01-15 Jakub Jelinek <jakub@redhat.com>
13586 * config/i386/sse.md
13587 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
13588 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
13589 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
13590 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
13591 just a single alternative instead of two, make operands 1 and 2
13594 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
13597 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
13600 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13602 * Makefile.in (lang_opt_files): Add analyzer.opt.
13603 (ANALYZER_OBJS): New.
13604 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
13605 tristate.o and ANALYZER_OBJS.
13606 (TEXI_GCCINT_FILES): Add analyzer.texi.
13607 * common.opt (-fanalyzer): New driver option.
13608 * config.in: Regenerate.
13609 * configure: Regenerate.
13610 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
13611 (gccdepdir): Also create depdir for "analyzer" subdir.
13612 * digraph.cc: New file.
13613 * digraph.h: New file.
13614 * doc/analyzer.texi: New file.
13615 * doc/gccint.texi ("Static Analyzer") New menu item.
13616 (analyzer.texi): Include it.
13617 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
13618 ("Warning Options"): Add static analysis warnings to the list.
13619 (-Wno-analyzer-double-fclose): New option.
13620 (-Wno-analyzer-double-free): New option.
13621 (-Wno-analyzer-exposure-through-output-file): New option.
13622 (-Wno-analyzer-file-leak): New option.
13623 (-Wno-analyzer-free-of-non-heap): New option.
13624 (-Wno-analyzer-malloc-leak): New option.
13625 (-Wno-analyzer-possible-null-argument): New option.
13626 (-Wno-analyzer-possible-null-dereference): New option.
13627 (-Wno-analyzer-null-argument): New option.
13628 (-Wno-analyzer-null-dereference): New option.
13629 (-Wno-analyzer-stale-setjmp-buffer): New option.
13630 (-Wno-analyzer-tainted-array-index): New option.
13631 (-Wno-analyzer-use-after-free): New option.
13632 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
13633 (-Wno-analyzer-use-of-uninitialized-value): New option.
13634 (-Wanalyzer-too-complex): New option.
13635 (-fanalyzer-call-summaries): New warning.
13636 (-fanalyzer-checker=): New warning.
13637 (-fanalyzer-fine-grained): New warning.
13638 (-fno-analyzer-state-merge): New warning.
13639 (-fno-analyzer-state-purge): New warning.
13640 (-fanalyzer-transitivity): New warning.
13641 (-fanalyzer-verbose-edges): New warning.
13642 (-fanalyzer-verbose-state-changes): New warning.
13643 (-fanalyzer-verbosity=): New warning.
13644 (-fdump-analyzer): New warning.
13645 (-fdump-analyzer-callgraph): New warning.
13646 (-fdump-analyzer-exploded-graph): New warning.
13647 (-fdump-analyzer-exploded-nodes): New warning.
13648 (-fdump-analyzer-exploded-nodes-2): New warning.
13649 (-fdump-analyzer-exploded-nodes-3): New warning.
13650 (-fdump-analyzer-supergraph): New warning.
13651 * doc/sourcebuild.texi (dg-require-dot): New.
13652 (dg-check-dot): New.
13653 * gdbinit.in (break-on-saved-diagnostic): New command.
13654 * graphviz.cc: New file.
13655 * graphviz.h: New file.
13656 * ordered-hash-map-tests.cc: New file.
13657 * ordered-hash-map.h: New file.
13658 * passes.def (pass_analyzer): Add before
13659 pass_ipa_whole_program_visibility.
13660 * selftest-run-tests.c (selftest::run_tests): Call
13661 selftest::ordered_hash_map_tests_cc_tests.
13662 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
13664 * shortest-paths.h: New file.
13665 * timevar.def (TV_ANALYZER): New timevar.
13666 (TV_ANALYZER_SUPERGRAPH): Likewise.
13667 (TV_ANALYZER_STATE_PURGE): Likewise.
13668 (TV_ANALYZER_PLAN): Likewise.
13669 (TV_ANALYZER_SCC): Likewise.
13670 (TV_ANALYZER_WORKLIST): Likewise.
13671 (TV_ANALYZER_DUMP): Likewise.
13672 (TV_ANALYZER_DIAGNOSTICS): Likewise.
13673 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
13674 * tree-pass.h (make_pass_analyzer): New decl.
13675 * tristate.cc: New file.
13676 * tristate.h: New file.
13678 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
13681 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
13682 alternatives 9 and 10.
13684 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13686 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
13687 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
13688 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
13689 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
13690 (selftest::hash_map_tests_c_tests): Call it.
13691 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
13692 New static constant, using the value of = H::empty_zero_p.
13693 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
13694 from default_hash_traits <Value>.
13695 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
13697 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
13698 * hash-table.h (hash_table::alloc_entries): Guard the loop of
13699 calls to mark_empty with !Descriptor::empty_zero_p.
13700 (hash_table::empty_slow): Conditionalize the memset call with a
13701 check that Descriptor::empty_zero_p; otherwise, loop through the
13702 entries calling mark_empty on them.
13703 * hash-traits.h (int_hash::empty_zero_p): New static constant.
13704 (pointer_hash::empty_zero_p): Likewise.
13705 (pair_hash::empty_zero_p): Likewise.
13706 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
13708 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
13709 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
13710 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
13711 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
13712 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
13713 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
13714 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
13715 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
13716 * tree-vectorizer.h
13717 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
13720 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
13722 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
13723 fix typo on return value.
13725 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
13728 * cgraph.c (symbol_table::create_edge): Init speculative_id and
13730 (cgraph_edge::make_speculative): Add param for setting speculative_id
13732 (cgraph_edge::speculative_call_info): Update comments and find reference
13733 by speculative_id for multiple indirect targets.
13734 (cgraph_edge::resolve_speculation): Decrease the speculations
13735 for indirect edge, drop it's speculative if not direct target
13736 left. Update comments.
13737 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
13738 (cgraph_node::dump): Print num_speculative_call_targets.
13739 (cgraph_node::verify_node): Don't report error if speculative
13740 edge not include statement.
13741 (cgraph_edge::num_speculative_call_targets_p): New function.
13742 * cgraph.h (int common_target_id): Remove.
13743 (int common_target_probability): Remove.
13744 (num_speculative_call_targets): New variable.
13745 (make_speculative): Add param for setting speculative_id.
13746 (cgraph_edge::num_speculative_call_targets_p): New declare.
13747 (target_prob): New variable.
13748 (speculative_id): New variable.
13749 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
13750 call summaries for multiple speculative call targets.
13751 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
13752 * ipa-profile.c (struct speculative_call_target): New struct.
13753 (class speculative_call_summary): New class.
13754 (class speculative_call_summaries): New class.
13755 (call_sums): New variable.
13756 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
13757 (ipa_profile_write_edge_summary): New function.
13758 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
13759 (ipa_profile_dump_all_summaries): New function.
13760 (ipa_profile_read_edge_summary): New function.
13761 (ipa_profile_read_summary_section): New function.
13762 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
13763 (ipa_profile): Generate num_speculative_call_targets from
13765 * ipa-ref.h (speculative_id): New variable.
13766 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
13767 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
13768 common_target_probability. Stream out speculative_id and
13769 num_speculative_call_targets.
13770 (input_edge): Likewise.
13771 * predict.c (dump_prediction): Remove edges count assert to be
13773 * symtab.c (symtab_node::create_reference): Init speculative_id.
13774 (symtab_node::clone_references): Clone speculative_id.
13775 (symtab_node::clone_referring): Clone speculative_id.
13776 (symtab_node::clone_reference): Clone speculative_id.
13777 (symtab_node::clear_stmts_in_references): Clear speculative_id.
13778 * tree-inline.c (copy_bb): Duplicate all the speculative edges
13779 if indirect call contains multiple speculative targets.
13780 * value-prof.h (check_ic_target): Remove.
13781 * value-prof.c (gimple_value_profile_transformations):
13782 Use void function gimple_ic_transform.
13783 * value-prof.c (gimple_ic_transform): Handle topn case.
13784 Fix comment typos. Change it to a void function.
13786 2020-01-13 Andrew Pinski <apinski@marvell.com>
13788 * config/aarch64/aarch64-cores.def (octeontx2): New define.
13789 (octeontx2t98): New define.
13790 (octeontx2t96): New define.
13791 (octeontx2t93): New define.
13792 (octeontx2f95): New define.
13793 (octeontx2f95n): New define.
13794 (octeontx2f95mm): New define.
13795 * config/aarch64/aarch64-tune.md: Regenerate.
13796 * doc/invoke.texi (-mcpu=): Document the new cpu types.
13798 2020-01-13 Jason Merrill <jason@redhat.com>
13800 PR c++/33799 - destroy return value if local cleanup throws.
13801 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
13803 2020-01-13 Martin Liska <mliska@suse.cz>
13805 * ipa-cp.c (get_max_overall_size): Use newly
13806 renamed param param_ipa_cp_unit_growth.
13807 * params.opt: Remove legacy param name.
13809 2020-01-13 Martin Sebor <msebor@redhat.com>
13811 PR tree-optimization/93213
13812 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
13813 stores to be eliminated.
13815 2020-01-13 Martin Liska <mliska@suse.cz>
13817 * opts.c (print_help): Do not print CL_PARAM
13818 and CL_WARNING for CL_OPTIMIZATION.
13820 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
13823 * doc/invoke.texi (Warning Options): Add caveat about some warnings
13824 depending on optimization settings.
13826 2020-01-13 Jakub Jelinek <jakub@redhat.com>
13828 PR tree-optimization/90838
13829 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
13830 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
13831 argument rather than to initialize temporary for targets that
13832 don't use the mode argument at all. Initialize ctzval to avoid
13835 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
13837 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
13838 * tree-core.h: Document it.
13839 * gimplify.c (gimplify_omp_workshare): Set it.
13840 * omp-low.c (lower_omp_target): Use it.
13841 * tree-pretty-print.c (dump_omp_clause): Print it.
13843 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
13844 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
13846 2020-01-10 David Malcolm <dmalcolm@redhat.com>
13848 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
13849 * common.opt (fdiagnostics-path-format=): New option.
13850 (diagnostic_path_format): New enum.
13851 (fdiagnostics-show-path-depths): New option.
13852 * coretypes.h (diagnostic_event_id_t): New forward decl.
13853 * diagnostic-color.c (color_dict): Add "path".
13854 * diagnostic-event-id.h: New file.
13855 * diagnostic-format-json.cc (json_from_expanded_location): Make
13857 (json_end_diagnostic): Call context->make_json_for_path if it
13858 exists and the diagnostic has a path.
13859 (diagnostic_output_format_init): Clear context->print_path.
13860 * diagnostic-path.h: New file.
13861 * diagnostic-show-locus.c (colorizer::set_range): Special-case
13862 when printing a run of events in a diagnostic_path so that they
13863 all get the same color.
13864 (layout::m_diagnostic_path_p): New field.
13865 (layout::layout): Initialize it.
13866 (layout::print_any_labels): Don't colorize the label text for an
13867 event in a diagnostic_path.
13868 (gcc_rich_location::add_location_if_nearby): Add
13869 "restrict_to_current_line_spans" and "label" params. Pass the
13870 former to layout.maybe_add_location_range; pass the latter
13871 when calling add_range.
13872 * diagnostic.c: Include "diagnostic-path.h".
13873 (diagnostic_initialize): Initialize context->path_format and
13874 context->show_path_depths.
13875 (diagnostic_show_any_path): New function.
13876 (diagnostic_path::interprocedural_p): New function.
13877 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
13878 (simple_diagnostic_path::num_events): New function.
13879 (simple_diagnostic_path::get_event): New function.
13880 (simple_diagnostic_path::add_event): New function.
13881 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
13882 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
13883 (debug): New overload taking a diagnostic_path *.
13884 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
13885 * diagnostic.h (enum diagnostic_path_format): New enum.
13886 (json::value): New forward decl.
13887 (diagnostic_context::path_format): New field.
13888 (diagnostic_context::show_path_depths): New field.
13889 (diagnostic_context::print_path): New callback field.
13890 (diagnostic_context::make_json_for_path): New callback field.
13891 (diagnostic_show_any_path): New decl.
13892 (json_from_expanded_location): New decl.
13893 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
13894 (-fdiagnostics-show-path-depths): New option.
13895 (-fdiagnostics-color): Add "path" to description of default
13896 GCC_COLORS; describe it.
13897 (-fdiagnostics-format=json): Document how diagnostic paths are
13898 represented in the JSON output format.
13899 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
13900 Add optional params "restrict_to_current_line_spans" and "label".
13901 * opts.c (common_handle_option): Handle
13902 OPT_fdiagnostics_path_format_ and
13903 OPT_fdiagnostics_show_path_depths.
13904 * pretty-print.c: Include "diagnostic-event-id.h".
13905 (pp_format): Implement "%@" format code for printing
13906 diagnostic_event_id_t *.
13907 (selftest::test_pp_format): Add tests for "%@".
13908 * selftest-run-tests.c (selftest::run_tests): Call
13909 selftest::tree_diagnostic_path_cc_tests.
13910 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
13911 * toplev.c (general_init): Initialize global_dc->path_format and
13912 global_dc->show_path_depths.
13913 * tree-diagnostic-path.cc: New file.
13914 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
13915 non-static. Drop "diagnostic" param in favor of storing the
13916 original value of "where" and re-using it.
13917 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
13918 maybe_unwind_expanded_macro_loc.
13919 (tree_diagnostics_defaults): Initialize context->print_path and
13920 context->make_json_for_path.
13921 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
13923 (default_tree_make_json_for_path): New decl.
13924 (maybe_unwind_expanded_macro_loc): New decl.
13926 2020-01-10 Jakub Jelinek <jakub@redhat.com>
13928 PR tree-optimization/93210
13929 * fold-const.h (native_encode_initializer,
13930 can_native_interpret_type_p): Declare.
13931 * fold-const.c (native_encode_string): Fix up handling with off != -1,
13933 (native_encode_initializer): New function, moved from dwarf2out.c.
13934 Adjust to native_encode_expr compatible arguments, including dry-run
13935 and partial extraction modes. Don't handle STRING_CST.
13936 (can_native_interpret_type_p): No longer static.
13937 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
13938 offset / BITS_PER_UNIT fits into int and don't call it if
13939 can_native_interpret_type_p fails. If suboff is NULL and for
13940 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
13941 native_encode_initializer.
13942 (fold_const_aggregate_ref_1): Formatting fix.
13943 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
13944 (tree_add_const_value_attribute): Adjust caller.
13946 PR tree-optimization/90838
13947 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
13948 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
13949 CTZ_DEFINED_VALUE_AT_ZERO.
13951 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
13953 PR inline-asm/93027
13954 * lra-constraints.c (match_reload): Permit input operands have the
13955 same mode as output while other input operands have a different
13958 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
13960 PR tree-optimization/90838
13961 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
13962 (check_ctz_string): Likewise.
13963 (optimize_count_trailing_zeroes): Likewise.
13964 (simplify_count_trailing_zeroes): Likewise.
13965 (pass_forwprop::execute): Try ctz simplification.
13966 * match.pd: Add matching for ctz idioms.
13968 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13970 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
13972 (aarch64_invalid_unary_op): New function for target hook.
13973 (aarch64_invalid_binary_op): New function for target hook.
13975 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13977 * config.gcc: Add arm_bf16.h.
13978 * config/aarch64/aarch64-builtins.c
13979 (aarch64_simd_builtin_std_type): Add BFmode.
13980 (aarch64_init_simd_builtin_types): Define element types for vector
13982 (aarch64_init_bf16_types): New function.
13983 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
13984 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
13986 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
13987 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
13989 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
13990 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
13991 * config/aarch64/aarch64.c
13992 (aarch64_classify_vector_mode): Add support for BF types.
13993 (aarch64_gimplify_va_arg_expr): Add support for BF types.
13994 (aarch64_vq_mode): Add support for BF types.
13995 (aarch64_simd_container_mode): Add support for BF types.
13996 (aarch64_mangle_type): Add support for BF scalar type.
13997 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
13998 * config/aarch64/arm_bf16.h: New file.
13999 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
14000 * config/aarch64/iterators.md: Add BF types to mode attributes.
14001 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
14003 2020-01-10 Jason Merrill <jason@redhat.com>
14005 PR c++/93173 - incorrect tree sharing.
14006 * gimplify.c (copy_if_shared): No longer static.
14007 * gimplify.h: Declare it.
14009 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14011 * doc/invoke.texi (-msve-vector-bits=): Document that
14012 -msve-vector-bits=128 now generates VL-specific code for
14013 little-endian targets.
14014 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
14015 build_vector_type_for_mode to construct the data vector types.
14016 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
14017 VL-specific code for -msve-vector-bits=128 on little-endian targets.
14018 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
14019 for 128-bit vectors.
14021 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14023 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
14026 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14028 * config/aarch64/aarch64-builtins.c
14029 (aarch64_builtin_vectorized_function): Check for specific vector modes,
14030 rather than checking the number of elements and the element mode.
14032 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14034 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
14035 get_related_vectype_for_scalar_type rather than build_vector_type
14036 to create the index type for a conditional reduction.
14038 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14040 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
14041 for any type of gather or scatter, including strided accesses.
14043 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
14045 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
14048 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
14050 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
14051 get_dr_vinfo_offset
14052 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
14053 parameter and its use to reset DR_OFFSET's.
14054 (vect_transform_loop): Remove orig_drs_init argument.
14055 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
14056 member of dr_vec_info rather than the offset of the associated
14057 data_reference's innermost_loop_behavior.
14058 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
14059 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
14060 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
14061 get_dr_vinfo_offset.
14062 (vectorizable_store): Likewise.
14063 (vectorizable_load): Likewise.
14065 2020-01-10 Richard Biener <rguenther@suse.de>
14067 * gimple-ssa-store-merging
14068 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
14070 2020-01-10 Martin Liska <mliska@suse.cz>
14073 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
14074 encapsulation that was there before r280040.
14076 2020-01-10 Richard Biener <rguenther@suse.de>
14078 PR middle-end/93199
14079 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
14080 sequences to avoid walking them again for secondary opportunities.
14081 (pass_lower_eh_dispatch::execute): Instead actually insert
14084 2020-01-10 Richard Biener <rguenther@suse.de>
14086 PR middle-end/93199
14087 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
14088 (cleanup_all_empty_eh): Walk landing pads in reverse order to
14089 avoid quadraticness.
14091 2020-01-10 Martin Jambor <mjambor@suse.cz>
14093 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
14094 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
14095 to get param_ipa_sra_max_replacements.
14096 (param_splitting_across_edge): Pass the caller to
14097 pull_accesses_from_callee.
14099 2020-01-10 Martin Jambor <mjambor@suse.cz>
14101 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
14102 * ipa-cp.c (max_new_size): Removed.
14103 (orig_overall_size): New variable.
14104 (get_max_overall_size): New function.
14105 (estimate_local_effects): Use it. Adjust dump.
14106 (decide_about_value): Likewise.
14107 (ipcp_propagate_stage): Do not calculate max_new_size, just store
14108 orig_overall_size. Adjust dump.
14109 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
14111 2020-01-10 Martin Jambor <mjambor@suse.cz>
14113 * params.opt (param_ipa_max_agg_items): Mark as Optimization
14114 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
14115 instead of param_ipa_max_agg_items.
14116 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
14117 optimization info for the callee.
14119 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
14121 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
14122 markers if debug_inline_points is false.
14124 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14126 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
14128 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
14129 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
14130 aarch64-sve-builtins-sve2.h.
14131 (aarch64-sve-builtins-sve2.o): New rule.
14132 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
14133 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
14134 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
14135 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
14136 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
14137 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
14139 * config/aarch64/aarch64-sve.md: Update comments with SVE2
14140 instructions that are handled here.
14141 (@cond_asrd<mode>): Generalize to...
14142 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
14143 (*cond_asrd<mode>_2): Generalize to...
14144 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
14145 (*cond_asrd<mode>_z): Generalize to...
14146 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
14147 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
14148 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
14149 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
14150 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
14152 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
14153 (@aarch64_scatter_stnt<mode>): Likewise.
14154 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
14155 (@aarch64_mul_lane_<mode>): Likewise.
14156 (@aarch64_sve_suqadd<mode>_const): Likewise.
14157 (*<sur>h<addsub><mode>): Generalize to...
14158 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
14160 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
14161 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
14162 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
14163 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
14164 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
14165 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
14166 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
14167 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
14168 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
14169 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
14170 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
14171 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
14172 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
14173 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
14174 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
14175 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
14176 (@aarch64_sve2_xar<mode>): Likewise.
14177 (@aarch64_sve2_bcax<mode>): Likewise.
14178 (*aarch64_sve2_eor3<mode>): Rename to...
14179 (@aarch64_sve2_eor3<mode>): ...this.
14180 (@aarch64_sve2_bsl<mode>): New expander.
14181 (@aarch64_sve2_nbsl<mode>): Likewise.
14182 (@aarch64_sve2_bsl1n<mode>): Likewise.
14183 (@aarch64_sve2_bsl2n<mode>): Likewise.
14184 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
14185 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
14186 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
14187 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
14188 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
14189 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
14190 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
14191 (<su>mull<bt><Vwide>): Generalize to...
14192 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
14194 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
14195 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
14196 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
14197 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14198 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
14199 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14200 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
14201 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14202 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
14203 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14204 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
14205 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
14206 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
14207 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
14208 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
14209 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
14210 (<SHRNB:r>shrnb<mode>): Generalize to...
14211 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
14213 (<SHRNT:r>shrnt<mode>): Generalize to...
14214 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
14216 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
14217 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
14218 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
14219 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
14220 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
14221 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
14222 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
14223 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
14224 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
14225 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
14226 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
14227 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
14228 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
14229 (@aarch64_sve2_cvtnt<mode>): Likewise.
14230 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
14231 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
14232 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
14233 (@aarch64_sve2_cvtxnt<mode>): Likewise.
14234 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
14235 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
14236 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
14237 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
14238 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
14239 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
14240 (@aarch64_sve2_pmul<mode>): Likewise.
14241 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
14242 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
14243 (@aarch64_sve2_tbl2<mode>): Likewise.
14244 (@aarch64_sve2_tbx<mode>): Likewise.
14245 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
14246 (@aarch64_sve2_histcnt<mode>): Likewise.
14247 (@aarch64_sve2_histseg<mode>): Likewise.
14248 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
14249 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
14250 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
14251 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
14252 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
14253 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
14254 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
14255 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
14256 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
14257 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
14258 (SVE2_PMULL_PAIR_I): New mode iterators.
14259 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
14260 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
14261 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
14262 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
14263 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
14264 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
14265 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
14266 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
14267 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
14268 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
14269 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
14270 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
14271 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
14272 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
14273 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
14274 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
14275 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
14276 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
14277 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
14278 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
14279 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
14280 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
14281 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
14282 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
14283 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
14284 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
14285 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
14286 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
14287 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
14288 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
14289 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
14291 (VNARROW, Ventype): New mode attributes.
14292 (Vewtype): Handle VNx2DI. Fix typo in comment.
14293 (VDOUBLE): New mode attribute.
14294 (sve_lane_con): Handle VNx8HI.
14295 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
14296 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
14297 (sve_int_op, sve_int_op_rev): Handle the above codes.
14298 (sve_pred_int_rhs2_operand): Likewise.
14299 (MULLBT, SHRNB, SHRNT): Delete.
14300 (SVE_INT_SHIFT_IMM): New int iterator.
14301 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
14302 and UNSPEC_WHILEHS for TARGET_SVE2.
14303 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
14304 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
14305 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
14306 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
14307 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
14308 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
14309 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
14310 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
14311 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
14312 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
14313 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
14314 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
14315 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
14316 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
14317 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
14318 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
14319 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
14320 (optab): Handle the new unspecs.
14321 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
14323 (lr): Handle the new unspecs.
14325 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
14326 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
14327 (sve_int_qsub_op): New int attributes.
14328 (sve_fp_op, rot): Handle the new unspecs.
14329 * config/aarch64/aarch64-sve-builtins.h
14330 (function_resolver::require_matching_pointer_type): Declare.
14331 (function_resolver::resolve_unary): Add an optional boolean argument.
14332 (function_resolver::finish_opt_n_resolution): Add an optional
14333 type_suffix_index argument.
14334 (gimple_folder::redirect_call): Declare.
14335 (gimple_expander::prepare_gather_address_operands): Add an optional
14337 * config/aarch64/aarch64-sve-builtins.cc: Include
14338 aarch64-sve-builtins-sve2.h.
14339 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
14340 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
14341 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
14342 (TYPES_hsd_integer): Use TYPES_hsd_signed.
14343 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
14344 (TYPES_s_unsigned): Likewise.
14345 (TYPES_s_integer): Use TYPES_s_unsigned.
14346 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
14347 (TYPES_sd_integer): Use them.
14348 (TYPES_d_unsigned): New macro.
14349 (TYPES_d_integer): Use it.
14350 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
14351 (TYPES_cvt_narrow): Likewise.
14352 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
14353 (preds_mx): New variable.
14354 (function_builder::add_overloaded_function): Allow the new feature
14355 set to be more restrictive than the original one.
14356 (function_resolver::infer_pointer_type): Remove qualifiers from
14357 the pointer type before printing it.
14358 (function_resolver::require_matching_pointer_type): New function.
14359 (function_resolver::resolve_sv_displacement): Handle functions
14360 that don't support 32-bit vector indices or svint32_t vector offsets.
14361 (function_resolver::finish_opt_n_resolution): Take the inferred type
14362 as a separate argument.
14363 (function_resolver::resolve_unary): Optionally treat all forms in
14364 the same way as normal merging functions.
14365 (gimple_folder::redirect_call): New function.
14366 (function_expander::prepare_gather_address_operands): Add an argument
14367 that says whether scaled forms are available. If they aren't,
14368 handle scaling of vector indices and don't add the extension and
14370 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
14371 fall back to using cond_* instead.
14372 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
14373 Split out the member variables into...
14374 (rtx_code_function_base): ...this new base class.
14375 (rtx_code_function_rotated): Inherit rtx_code_function_base.
14376 (unspec_based_function): Split out the member variables into...
14377 (unspec_based_function_base): ...this new base class.
14378 (unspec_based_function_rotated): Inherit unspec_based_function_base.
14379 (unspec_based_function_exact_insn): New class.
14380 (unspec_based_add_function, unspec_based_add_lane_function)
14381 (unspec_based_lane_function, unspec_based_pred_function)
14382 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
14383 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
14384 (unspec_based_sub_function, unspec_based_sub_lane_function): New
14386 (unspec_based_fused_function): New class.
14387 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
14388 (unspec_based_fused_lane_function): New class.
14389 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
14391 (CODE_FOR_MODE1): New macro.
14392 (fixed_insn_function): New class.
14393 (while_comparison): Likewise.
14394 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
14395 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
14396 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
14397 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
14398 (load_gather_sv_restricted, shift_left_imm_long): Declare.
14399 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
14400 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
14401 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
14402 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
14403 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
14404 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
14405 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
14406 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
14407 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
14408 Also add an initial argument for unary_convert_narrowt, regardless
14409 of the predication type.
14410 (build_32_64): Allow loads and stores to specify MODE_none.
14411 (build_sv_index64, build_sv_uint_offset): New functions.
14412 (long_type_suffix): New function.
14413 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
14414 (binary_imm_long_base, load_gather_sv_base): Likewise.
14415 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
14416 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
14417 (unary_narrowb_base, unary_narrowt_base): Likewise.
14418 (binary_long_lane_def, binary_long_lane): New shape.
14419 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
14420 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
14421 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
14422 (binary_to_uint_def, binary_to_uint): Likewise.
14423 (binary_wide_def, binary_wide): Likewise.
14424 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
14425 (compare_def, compare): Likewise.
14426 (compare_ptr_def, compare_ptr): Likewise.
14427 (load_ext_gather_index_restricted_def,
14428 load_ext_gather_index_restricted): Likewise.
14429 (load_ext_gather_offset_restricted_def,
14430 load_ext_gather_offset_restricted): Likewise.
14431 (load_gather_sv_def): Inherit from load_gather_sv_base.
14432 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
14433 (shift_left_imm_def, shift_left_imm): Likewise.
14434 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
14435 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
14436 (store_scatter_index_restricted_def,
14437 store_scatter_index_restricted): Likewise.
14438 (store_scatter_offset_restricted_def,
14439 store_scatter_offset_restricted): Likewise.
14440 (tbl_tuple_def, tbl_tuple): Likewise.
14441 (ternary_long_lane_def, ternary_long_lane): Likewise.
14442 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
14443 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
14444 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
14445 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
14446 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
14447 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
14448 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
14449 (ternary_uint_def, ternary_uint): Likewise.
14450 (unary_convert): Fix typo in comment.
14451 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
14452 (unary_long_def, unary_long): Likewise.
14453 (unary_narrowb_def, unary_narrowb): Likewise.
14454 (unary_narrowt_def, unary_narrowt): Likewise.
14455 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
14456 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
14457 (unary_to_int_def, unary_to_int): Likewise.
14458 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
14459 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
14460 (svasrd_impl): Delete.
14461 (svcadd_impl::expand): Handle integer operations too.
14462 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
14463 new functions to derive the unspec numbers.
14464 (svmla_svmls_lane_impl): Replace with...
14465 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
14466 integer operations too.
14467 (svwhile_impl): Rename to...
14468 (svwhilelx_impl): ...this and inherit from while_comparison.
14469 (svasrd): Use unspec_based_function.
14470 (svmla_lane): Use svmla_lane_impl.
14471 (svmls_lane): Use svmls_lane_impl.
14472 (svrecpe, svrsqrte): Handle unsigned integer operations too.
14473 (svwhilele, svwhilelt): Use svwhilelx_impl.
14474 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
14475 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
14476 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
14477 * config/aarch64/aarch64-sve-builtins.def: Include
14478 aarch64-sve-builtins-sve2.def.
14480 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14482 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
14483 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
14484 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
14485 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
14486 immediates as well as vector ones.
14487 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
14488 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
14489 (aarch64_sve_qsub_immediate): Update calls accordingly.
14491 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14493 * config/aarch64/aarch64-sve2.md: Add banner comments.
14494 (<su>mulh<r>s<mode>3): Move further up file.
14495 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
14496 (*aarch64_sve2_sra<mode>): Move further down file.
14497 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
14499 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14501 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
14502 and UNSPEC_WHILEWR.
14503 (while_optab_cmp): Handle them.
14504 * config/aarch64/aarch64-sve.md
14505 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
14506 and add a "@" marker.
14507 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
14508 instead of gen_aarch64_sve2_while_ptest.
14509 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
14511 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14513 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
14514 (UNSPEC_WHILELE): ...this.
14515 (UNSPEC_WHILE_LO): Rename to...
14516 (UNSPEC_WHILELO): ...this.
14517 (UNSPEC_WHILE_LS): Rename to...
14518 (UNSPEC_WHILELS): ...this.
14519 (UNSPEC_WHILE_LT): Rename to...
14520 (UNSPEC_WHILELT): ...this.
14521 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
14522 (cmp_op, while_optab_cmp): Likewise.
14523 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
14524 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
14525 (svwhilelt): Likewise.
14527 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14529 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
14530 (unary_to_uint): Define.
14531 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
14532 (unary_count): Rename to...
14533 (unary_to_uint_def, unary_to_uint): ...this.
14534 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
14536 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14538 * config/aarch64/aarch64-sve-builtins-functions.h
14539 (code_for_mode_function): New class.
14540 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
14541 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
14542 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
14543 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
14544 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
14546 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14548 * config/aarch64/iterators.md (addsub): New code attribute.
14549 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
14551 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
14552 in the asm string and attributes. Fix indentation.
14553 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
14555 (@aarch64_sve_<optab><mode>): ...this.
14556 * config/aarch64/aarch64-sve-builtins.h
14557 (function_expander::expand_signed_unpred_op): Delete.
14558 * config/aarch64/aarch64-sve-builtins.cc
14559 (function_expander::expand_signed_unpred_op): Likewise.
14560 (function_expander::map_to_rtx_codes): If the optab isn't defined,
14561 try using code_for_aarch64_sve instead.
14562 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
14563 (svqsub_impl): Likewise.
14564 (svqadd, svqsub): Use rtx_code_function instead.
14566 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14568 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
14569 (HADDSUB, sur, addsub): Remove them.
14571 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14573 * tree-nrv.c (pass_return_slot::execute): Handle all internal
14574 functions the same way, rather than singling out those that
14575 aren't mapped directly to optabs.
14577 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14579 * target.def (compatible_vector_types_p): New target hook.
14580 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
14581 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
14582 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
14583 * doc/tm.texi: Regenerate.
14584 * gimple-expr.c: Include target.h.
14585 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
14586 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
14588 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
14589 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
14590 Use the original predicate if it already has a suitable type.
14592 2020-01-09 Martin Jambor <mjambor@suse.cz>
14594 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
14595 resolve_speculation and redirect_call_stmt_to_callee static. Change
14596 return type of set_call_stmt to cgraph_edge *.
14597 * auto-profile.c (afdo_indirect_call): Adjust call to
14598 redirect_call_stmt_to_callee.
14599 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
14600 make the this pointer explicit, adjust self-recursive calls and the
14601 call top make_direct. Return the resulting edge.
14602 (cgraph_edge::remove): Make this pointer explicit.
14603 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
14604 (cgraph_edge::make_direct): Likewise, adjust call to
14605 resolve_speculation.
14606 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
14607 call to set_call_stmt.
14608 (cgraph_update_edges_for_call_stmt_node): Update call to
14609 set_call_stmt and remove.
14610 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
14611 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
14612 (cgraph_node::create_edge_including_clones): Moved "first" definition
14613 of edge to the block where it was used. Adjusted calls to
14615 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
14616 cgraph_edge::remove.
14617 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
14618 make_direct and redirect_call_stmt_to_callee.
14619 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
14620 resolve_speculation and make_direct.
14621 * ipa-inline-transform.c (inline_transform): Adjust call to
14622 redirect_call_stmt_to_callee.
14623 (check_speculations_1):: Adjust call to resolve_speculation.
14624 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
14625 resolve-speculation.
14626 (inline_small_functions): Adjust call to resolve_speculation.
14627 (ipa_inline): Likewise.
14628 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
14630 * ipa-visibility.c (function_and_variable_visibility): Make iteration
14631 safe with regards to edge removal, adjust calls to
14632 redirect_call_stmt_to_callee.
14633 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
14634 and redirect_call_stmt_to_callee.
14635 * multiple_target.c (create_dispatcher_calls): Adjust call to
14636 redirect_call_stmt_to_callee
14637 (redirect_to_specific_clone): Likewise.
14638 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
14639 Adjust calls to cgraph_edge::remove.
14640 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
14641 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
14642 (expand_call_inline): Adjust call to cgraph_edge::remove.
14644 2020-01-09 Martin Liska <mliska@suse.cz>
14646 * params.opt: Set Optimization for
14647 param_max_speculative_devirt_maydefs.
14649 2020-01-09 Martin Sebor <msebor@redhat.com>
14651 PR middle-end/93200
14653 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
14655 2020-01-09 Martin Liska <mliska@suse.cz>
14657 * auto-profile.c (auto_profile): Use opt_for_fn
14659 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
14660 (propagate_vals_across_arith_jfunc): Likewise.
14661 (hint_time_bonus): Likewise.
14662 (incorporate_penalties): Likewise.
14663 (good_cloning_opportunity_p): Likewise.
14664 (perform_estimation_of_a_value): Likewise.
14665 (estimate_local_effects): Likewise.
14666 (ipcp_propagate_stage): Likewise.
14667 * ipa-fnsummary.c (decompose_param_expr): Likewise.
14668 (set_switch_stmt_execution_predicate): Likewise.
14669 (analyze_function_body): Likewise.
14670 * ipa-inline-analysis.c (offline_size): Likewise.
14671 * ipa-inline.c (early_inliner): Likewise.
14672 * ipa-prop.c (ipa_analyze_node): Likewise.
14673 (ipcp_transform_function): Likewise.
14674 * ipa-sra.c (process_scan_results): Likewise.
14675 (ipa_sra_summarize_function): Likewise.
14676 * params.opt: Rename ipcp-unit-growth to
14677 ipa-cp-unit-growth. Add Optimization for various
14678 IPA-related parameters.
14680 2020-01-09 Richard Biener <rguenther@suse.de>
14682 PR middle-end/93054
14683 * gimplify.c (gimplify_expr): Deal with NOP definitions.
14685 2020-01-09 Richard Biener <rguenther@suse.de>
14687 PR tree-optimization/93040
14688 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
14690 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
14692 * common/config/avr/avr-common.c (avr_option_optimization_table)
14693 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
14695 2020-01-09 Martin Liska <mliska@suse.cz>
14697 * cgraphclones.c (symbol_table::materialize_all_clones):
14698 Use cgraph_node::dump_name.
14700 2020-01-09 Jakub Jelinek <jakub@redhat.com>
14702 PR inline-asm/93202
14703 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
14704 output_operand_lossage instead of gcc_unreachable.
14705 * doc/md.texi (riscv f constraint): Fix typo.
14708 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
14709 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
14710 CONST_SCALAR_INT_P instead of CONST_INT_P.
14711 (*subv<mode>4_1): Rename to ...
14712 (subv<mode>4_1): ... this.
14713 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
14714 define_insn_and_split patterns.
14715 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
14718 2020-01-08 David Malcolm <dmalcolm@redhat.com>
14720 * vec.c (class selftest::count_dtor): New class.
14721 (selftest::test_auto_delete_vec): New test.
14722 (selftest::vec_c_tests): Call it.
14723 * vec.h (class auto_delete_vec): New class template.
14724 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
14726 2020-01-08 David Malcolm <dmalcolm@redhat.com>
14728 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
14730 2020-01-08 Jim Wilson <jimw@sifive.com>
14732 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
14733 use of TLS_MODEL_LOCAL_EXEC when not pic.
14735 2020-01-08 David Malcolm <dmalcolm@redhat.com>
14737 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
14740 2020-01-08 Jakub Jelinek <jakub@redhat.com>
14743 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
14744 *stack_protect_set_3 peephole2): Also check that the second
14745 insns source is general_operand.
14748 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
14749 predicate for output operand instead of register_operand.
14750 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
14751 memory destination and non-memory operands[2].
14753 2020-01-08 Martin Liska <mliska@suse.cz>
14755 * cgraph.c (cgraph_node::dump): Use ::dump_name or
14756 ::dump_asm_name instead of (::name or ::asm_name).
14757 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
14758 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
14759 (analyze_functions): Likewise.
14760 (expand_all_functions): Likewise.
14761 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
14762 (propagate_bits_across_jump_function): Likewise.
14763 (dump_profile_updates): Likewise.
14764 (ipcp_store_bits_results): Likewise.
14765 (ipcp_store_vr_results): Likewise.
14766 * ipa-devirt.c (dump_targets): Likewise.
14767 * ipa-fnsummary.c (analyze_function_body): Likewise.
14768 * ipa-hsa.c (check_warn_node_versionable): Likewise.
14769 (process_hsa_functions): Likewise.
14770 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
14771 (set_alias_uids): Likewise.
14772 * ipa-inline-transform.c (save_inline_function_body): Likewise.
14773 * ipa-inline.c (recursive_inlining): Likewise.
14774 (inline_to_all_callers_1): Likewise.
14775 (ipa_inline): Likewise.
14776 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
14777 (ipa_propagate_frequency): Likewise.
14778 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
14779 (remove_described_reference): Likewise.
14780 * ipa-pure-const.c (worse_state): Likewise.
14781 (check_retval_uses): Likewise.
14782 (analyze_function): Likewise.
14783 (propagate_pure_const): Likewise.
14784 (propagate_nothrow): Likewise.
14785 (dump_malloc_lattice): Likewise.
14786 (propagate_malloc): Likewise.
14787 (pass_local_pure_const::execute): Likewise.
14788 * ipa-visibility.c (optimize_weakref): Likewise.
14789 (function_and_variable_visibility): Likewise.
14790 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
14791 (ipa_discover_variable_flags): Likewise.
14792 * lto-streamer-out.c (output_function): Likewise.
14793 (output_constructor): Likewise.
14794 * tree-inline.c (copy_bb): Likewise.
14795 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
14796 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
14798 2020-01-08 Richard Biener <rguenther@suse.de>
14800 PR middle-end/93199
14801 * tree-eh.c (sink_clobbers): Update virtual operands for
14802 the first and last stmt only. Add a dry-run capability.
14803 (pass_lower_eh_dispatch::execute): Perform clobber sinking
14804 after CFG manipulations and in RPO order to catch all
14805 secondary opportunities reliably.
14807 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
14810 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
14812 2019-01-08 Richard Biener <rguenther@suse.de>
14814 PR middle-end/93199
14815 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
14816 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
14817 virtual operand, also updating SSA use.
14818 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
14819 Update stmt after resetting virtual operand.
14820 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
14821 * gimple-iterator.c (gsi_remove): When not removing the stmt
14822 permanently do not delink immediate uses or mark the stmt modified.
14824 2020-01-08 Martin Liska <mliska@suse.cz>
14826 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
14827 (ipa_call_context::estimate_size_and_time): Likewise.
14828 (inline_analyze_function): Likewise.
14830 2020-01-08 Martin Liska <mliska@suse.cz>
14832 * cgraph.c (cgraph_node::dump): Use systematically
14835 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
14837 Add -nodevicespecs option for avr.
14840 * config/avr/avr.opt (-nodevicespecs): New driver option.
14841 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
14842 "-specs=device-specs/..." if that option is not set.
14843 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
14845 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
14847 Implement 64-bit double functions for avr.
14850 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
14851 --with-double-comparison.
14852 * doc/install.texi: Document them.
14853 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
14854 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
14855 <WITH_DOUBLE_COMPARISON>: New built-in defines.
14856 * doc/invoke.texi (AVR Built-in Macros): Document them.
14857 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
14858 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
14859 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
14861 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
14864 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
14865 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
14866 when only building rm-profile multilibs.
14868 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
14871 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
14872 lattice for a value to check.
14873 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
14874 finite propagation in self-recursive scc.
14876 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
14878 * ipa-inline.c (caller_growth_limits): Restore the AND.
14880 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
14882 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
14883 (VEC_ALLREG_ALT): New iterator.
14884 (VEC_ALLREG_INT_MODE): New iterator.
14885 (VCMP_MODE): New iterator.
14886 (VCMP_MODE_INT): New iterator.
14887 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
14888 (vec_cmp<u>v64qidi): New define_expand.
14889 (vec_cmp<mode>di_exec): Use VCMP_MODE.
14890 (vec_cmpu<mode>di_exec): New define_expand.
14891 (vec_cmp<u>v64qidi_exec): New define_expand.
14892 (vec_cmp<mode>di_dup): Use VCMP_MODE.
14893 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
14894 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
14895 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
14896 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
14897 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
14898 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
14899 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
14900 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
14901 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
14903 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
14904 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
14906 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
14908 * config/gcn/constraints.md (DA): Update description and match.
14910 (Db): New constraint.
14911 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
14913 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
14914 Implement 'Db' mixed immediate type.
14915 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
14916 (addcv64si3_dup<exec_vcc>): Delete.
14917 (subcv64si3<exec_vcc>): Rework constraints.
14918 (addv64di3): Rework constraints.
14919 (addv64di3_exec): Rework constraints.
14920 (subv64di3): Rework constraints.
14921 (addv64di3_dup): Delete.
14922 (addv64di3_dup_exec): Delete.
14923 (addv64di3_zext): Rework constraints.
14924 (addv64di3_zext_exec): Rework constraints.
14925 (addv64di3_zext_dup): Rework constraints.
14926 (addv64di3_zext_dup_exec): Rework constraints.
14927 (addv64di3_zext_dup2): Rework constraints.
14928 (addv64di3_zext_dup2_exec): Rework constraints.
14929 (addv64di3_sext_dup2): Rework constraints.
14930 (addv64di3_sext_dup2_exec): Rework constraints.
14932 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
14934 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
14935 existing target checks.
14937 2020-01-07 Richard Biener <rguenther@suse.de>
14939 * doc/install.texi: Bump minimal supported MPC version.
14941 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
14943 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
14944 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
14945 * langhooks.c: Include stor-layout.h.
14946 (lhd_simulate_enum_decl): New function.
14947 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
14948 handle_arm_sve_h for the LTO frontend.
14949 (register_vector_type): Cope with null returns from pushdecl.
14951 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
14953 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
14954 (aarch64_sve::nvectors_if_data_type): Replace with...
14955 (aarch64_sve::builtin_type_p): ...this.
14956 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
14957 (find_vector_type): Delete.
14958 (add_sve_type_attribute): New function.
14959 (lookup_sve_type_attribute): Likewise.
14960 (register_builtin_types): Add an "SVE type" attribute to each type.
14961 (register_tuple_type): Likewise.
14962 (svbool_type_p, nvectors_if_data_type): Delete.
14963 (mangle_builtin_type): Use lookup_sve_type_attribute.
14964 (builtin_type_p): Likewise. Add an overload that returns the
14965 number of constituent vector and predicate registers.
14966 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
14967 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
14968 instead of aarch64_sve_argument_p.
14969 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
14970 (aarch64_pass_by_reference): Likewise.
14971 (aarch64_function_value_1): Likewise.
14972 (aarch64_return_in_memory): Likewise.
14973 (aarch64_layout_arg): Likewise.
14975 2020-01-07 Jakub Jelinek <jakub@redhat.com>
14977 PR tree-optimization/93156
14978 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
14979 least significant bit is always clear.
14981 PR tree-optimization/93118
14982 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
14983 simplifier with two intermediate conversions.
14985 2020-01-07 Martin Liska <mliska@suse.cz>
14987 * params.opt: Add Optimization for various parameters.
14989 2020-01-07 Martin Liska <mliska@suse.cz>
14992 * doc/extend.texi: Explain cloning for target_clone
14995 2020-01-07 Martin Liska <mliska@suse.cz>
14997 PR tree-optimization/92860
14998 * common.opt: Make in Optimization option
14999 as it is affected by -O0, which is an Optimization
15001 * tree-inline.c (tree_inlinable_function_p):
15002 Use opt_for_fn for warn_inline.
15003 (expand_call_inline): Likewise.
15005 2020-01-07 Martin Liska <mliska@suse.cz>
15007 PR tree-optimization/92860
15008 * common.opt: Make flag_ree as optimization
15011 2020-01-07 Martin Liska <mliska@suse.cz>
15013 PR optimization/92860
15014 * params.opt: Mark param_min_crossjump_insns with Optimization
15017 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
15019 * ipa-inline-analysis.c (estimate_growth): Fix typo.
15020 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
15022 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
15024 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
15025 helper function to return the valid addressing formats for a given
15026 hard register and mode.
15027 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
15029 * config/rs6000/constraints.md (Q constraint): Update
15031 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
15034 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
15035 Use 'Q' for doing vector extract from memory.
15036 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
15038 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
15039 doing vector extract from memory.
15040 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
15041 extract from memory.
15043 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
15044 for the offset being 34-bits when -mcpu=future is used.
15046 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
15048 * config/pa/pa.md: Revert change to use ordered_comparison_operator
15049 instead of cmpib_comparison_operator in cmpib patterns.
15050 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
15051 of cmpib_comparison_operator. Revise comment.
15053 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15055 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
15056 in an IFN_DIV_POW2 node to be equal.
15058 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15060 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
15061 (vect_check_scalar_mask): ...this.
15062 (vectorizable_store, vectorizable_load): Update call accordingly.
15063 (vectorizable_call): Use vect_check_scalar_mask to check the mask
15064 argument in calls to conditional internal functions.
15066 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
15068 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
15069 '0' matching inputs.
15070 (subv64di3_exec): Likewise.
15072 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
15074 * config/mips/mips.c (vr4130_align_insns): Fix typo.
15075 * doc/md.texi (movstr): Likewise.
15077 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
15079 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
15082 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15084 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
15086 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
15087 to a temporary file and use move-if-change to update the real
15088 file where necessary.
15090 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15092 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
15093 rather than Upa for CPY /M.
15095 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
15097 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
15100 2020-01-06 Martin Liska <mliska@suse.cz>
15102 PR tree-optimization/92860
15103 * params.opt: Mark param_max_combine_insns with Optimization
15106 2020-01-05 Jakub Jelinek <jakub@redhat.com>
15109 * config/i386/i386.md (SWIDWI): New mode iterator.
15110 (DWI, dwi): Add TImode variants.
15111 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
15112 <general_hilo_operand> instead of <general_operand>. Use
15113 CONST_SCALAR_INT_P instead of CONST_INT_P.
15114 (*addv<mode>4_1): Rename to ...
15115 (addv<mode>4_1): ... this.
15116 (QWI): New mode attribute.
15117 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
15118 define_insn_and_split patterns.
15119 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
15121 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
15122 <general_hilo_operand> instead of <general_operand>.
15123 (*addcarry<mode>_1): New define_insn.
15124 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
15126 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
15128 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
15129 Use "call" instead of "set".
15131 2020-01-03 Martin Jambor <mjambor@suse.cz>
15134 * ipa-cp.c (print_all_lattices): Skip functions without info.
15136 2020-01-03 Jakub Jelinek <jakub@redhat.com>
15139 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
15140 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
15141 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
15142 for 'e' simd clones.
15145 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
15147 (mprefer-vector-width=): Add Save.
15148 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
15149 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
15150 (ix86_debug_options, ix86_function_specific_print): Adjust
15151 ix86_target_string callers.
15152 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
15153 (ix86_valid_target_attribute_tree): Likewise.
15154 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
15155 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
15156 ix86_target_string caller.
15159 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
15160 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
15161 instead of gen_int_shift_amount + convert_modes.
15163 PR rtl-optimization/93088
15164 * loop-iv.c (find_single_def_src): Punt after looking through
15165 128 reg copies for regs with single definitions. Move definitions
15168 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
15170 * config/arm/arm-c.c (arm_cpu_builtins): Define
15171 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
15172 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
15173 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
15174 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
15175 * config/arm/arm-tables.opt: Regenerated.
15176 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
15177 arm_arch_i8mm and arm_arch_bf16 when enabled.
15178 * config/arm/arm.h (TARGET_I8MM): New macro.
15179 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
15180 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
15181 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
15182 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
15183 (v8_6_a_simd_variants): New.
15184 (v8_*_a_simd_variants): Add i8mm and bf16.
15185 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
15187 2020-01-02 Jakub Jelinek <jakub@redhat.com>
15190 * predict.c (compute_function_frequency): Don't call
15191 warn_function_cold on functions that already have cold attribute.
15193 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
15196 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
15197 COMDAT group function labels in .data.rel.ro.local section.
15198 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
15201 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
15202 comparison_operator in B and S integer comparisons. Likewise, use
15203 ordered_comparison_operator instead of cmpib_comparison_operator in
15205 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
15207 2020-01-01 Jakub Jelinek <jakub@redhat.com>
15209 Update copyright years.
15211 * gcc.c (process_command): Update copyright notice dates.
15212 * gcov-dump.c (print_version): Ditto.
15213 * gcov.c (print_version): Ditto.
15214 * gcov-tool.c (print_version): Ditto.
15215 * gengtype.c (create_file): Ditto.
15216 * doc/cpp.texi: Bump @copying's copyright year.
15217 * doc/cppinternals.texi: Ditto.
15218 * doc/gcc.texi: Ditto.
15219 * doc/gccint.texi: Ditto.
15220 * doc/gcov.texi: Ditto.
15221 * doc/install.texi: Ditto.
15222 * doc/invoke.texi: Ditto.
15224 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
15226 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
15229 2020-01-01 Jakub Jelinek <jakub@redhat.com>
15231 PR tree-optimization/93098
15232 * match.pd (popcount): For shift amounts, use integer_onep
15233 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
15234 tests. Make sure that precision is power of two larger than or equal
15235 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
15236 instead of ULL suffixed constants. Formatting fixes.
15238 Copyright (C) 2020 Free Software Foundation, Inc.
15240 Copying and distribution of this file, with or without modification,
15241 are permitted in any medium without royalty provided the copyright
15242 notice and this notice are preserved.