1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; This gcc Version 2 machine description is inspired by sparc.md and
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Uses of UNSPEC in this file:
31 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
32 (UNSPEC_GOTO 1) ; indirect_goto
33 (UNSPEC_DLTIND14R 2) ;
42 (UNSPEC_TLSLDM_PIC 11)
49 [(UNSPECV_BLOCKAGE 0) ; blockage
50 (UNSPECV_DCACHE 1) ; dcacheflush
51 (UNSPECV_ICACHE 2) ; icacheflush
52 (UNSPECV_OPC 3) ; outline_prologue_call
53 (UNSPECV_OEC 4) ; outline_epilogue_call
54 (UNSPECV_LONGJMP 5) ; builtin_longjmp
57 ;; Maximum pc-relative branch offsets.
59 ;; These numbers are a bit smaller than the maximum allowable offsets
60 ;; so that a few instructions may be inserted before the actual branch.
63 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
64 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
67 ;; Insn type. Used to default other attribute values.
69 ;; type "unary" insns have one input operand (1) and one output operand (0)
70 ;; type "binary" insns have two input operands (1,2) and one output (0)
73 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
74 (const_string "binary"))
76 (define_attr "pa_combine_type"
77 "fmpy,faddsub,uncond_branch,addmove,none"
78 (const_string "none"))
80 ;; Processor type (for scheduling, not code generation) -- this attribute
81 ;; must exactly match the processor_type enumeration in pa.h.
83 ;; FIXME: Add 800 scheduling for completeness?
85 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
87 ;; Length (in # of bytes).
88 (define_attr "length" ""
89 (cond [(eq_attr "type" "load,fpload")
90 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
91 (const_int 8) (const_int 4))
93 (eq_attr "type" "store,fpstore")
94 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
95 (const_int 8) (const_int 4))
97 (eq_attr "type" "binary,shift,nullshift")
98 (if_then_else (match_operand 2 "arith_operand" "")
99 (const_int 4) (const_int 12))
101 (eq_attr "type" "move,unary,shift,nullshift")
102 (if_then_else (match_operand 1 "arith_operand" "")
103 (const_int 4) (const_int 8))]
107 (define_asm_attributes
108 [(set_attr "length" "4")
109 (set_attr "type" "multi")])
111 ;; Attributes for instruction and branch scheduling
113 ;; For conditional branches.
114 (define_attr "in_branch_delay" "false,true"
115 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
116 (eq_attr "length" "4"))
117 (const_string "true")
118 (const_string "false")))
120 ;; Disallow instructions which use the FPU since they will tie up the FPU
121 ;; even if the instruction is nullified.
122 (define_attr "in_nullified_branch_delay" "false,true"
123 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
124 (eq_attr "length" "4"))
125 (const_string "true")
126 (const_string "false")))
128 ;; For calls and millicode calls. Allow unconditional branches in the
130 (define_attr "in_call_delay" "false,true"
131 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
132 (eq_attr "length" "4"))
133 (const_string "true")
134 (eq_attr "type" "uncond_branch")
135 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
137 (const_string "true")
138 (const_string "false"))]
139 (const_string "false")))
142 ;; Call delay slot description.
143 (define_delay (eq_attr "type" "call")
144 [(eq_attr "in_call_delay" "true") (nil) (nil)])
146 ;; Millicode call delay slot description.
147 (define_delay (eq_attr "type" "milli")
148 [(eq_attr "in_call_delay" "true") (nil) (nil)])
150 ;; Return and other similar instructions.
151 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
152 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
154 ;; Floating point conditional branch delay slot description.
155 (define_delay (eq_attr "type" "fbranch")
156 [(eq_attr "in_branch_delay" "true")
157 (eq_attr "in_nullified_branch_delay" "true")
160 ;; Integer conditional branch delay slot description.
161 ;; Nullification of conditional branches on the PA is dependent on the
162 ;; direction of the branch. Forward branches nullify true and
163 ;; backward branches nullify false. If the direction is unknown
164 ;; then nullification is not allowed.
165 (define_delay (eq_attr "type" "cbranch")
166 [(eq_attr "in_branch_delay" "true")
167 (and (eq_attr "in_nullified_branch_delay" "true")
168 (attr_flag "forward"))
169 (and (eq_attr "in_nullified_branch_delay" "true")
170 (attr_flag "backward"))])
172 (define_delay (and (eq_attr "type" "uncond_branch")
173 (eq (symbol_ref "following_call (insn)")
175 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
177 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
178 ;; load: 2, fpload: 3
179 ;; store, fpstore: 3, no D-cache operations should be scheduled.
181 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
183 ;; Instruction Time Unit Minimum Distance (unit contention)
190 ;; fmpyadd 3 ALU,MPY 2
191 ;; fmpysub 3 ALU,MPY 2
192 ;; fmpycfxt 3 ALU,MPY 2
195 ;; fdiv,sgl 10 MPY 10
196 ;; fdiv,dbl 12 MPY 12
197 ;; fsqrt,sgl 14 MPY 14
198 ;; fsqrt,dbl 18 MPY 18
200 ;; We don't model fmpyadd/fmpysub properly as those instructions
201 ;; keep both the FP ALU and MPY units busy. Given that these
202 ;; processors are obsolete, I'm not going to spend the time to
203 ;; model those instructions correctly.
205 (define_automaton "pa700")
206 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
208 (define_insn_reservation "W0" 4
209 (and (eq_attr "type" "fpcc")
210 (eq_attr "cpu" "700"))
213 (define_insn_reservation "W1" 3
214 (and (eq_attr "type" "fpalu")
215 (eq_attr "cpu" "700"))
218 (define_insn_reservation "W2" 3
219 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
220 (eq_attr "cpu" "700"))
223 (define_insn_reservation "W3" 10
224 (and (eq_attr "type" "fpdivsgl")
225 (eq_attr "cpu" "700"))
228 (define_insn_reservation "W4" 12
229 (and (eq_attr "type" "fpdivdbl")
230 (eq_attr "cpu" "700"))
233 (define_insn_reservation "W5" 14
234 (and (eq_attr "type" "fpsqrtsgl")
235 (eq_attr "cpu" "700"))
238 (define_insn_reservation "W6" 18
239 (and (eq_attr "type" "fpsqrtdbl")
240 (eq_attr "cpu" "700"))
243 (define_insn_reservation "W7" 2
244 (and (eq_attr "type" "load")
245 (eq_attr "cpu" "700"))
248 (define_insn_reservation "W8" 2
249 (and (eq_attr "type" "fpload")
250 (eq_attr "cpu" "700"))
253 (define_insn_reservation "W9" 3
254 (and (eq_attr "type" "store")
255 (eq_attr "cpu" "700"))
258 (define_insn_reservation "W10" 3
259 (and (eq_attr "type" "fpstore")
260 (eq_attr "cpu" "700"))
263 (define_insn_reservation "W11" 5
264 (and (eq_attr "type" "fpstore_load")
265 (eq_attr "cpu" "700"))
268 (define_insn_reservation "W12" 6
269 (and (eq_attr "type" "store_fpload")
270 (eq_attr "cpu" "700"))
273 (define_insn_reservation "W13" 1
274 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
275 (eq_attr "cpu" "700"))
278 ;; We have a bypass for all computations in the FP unit which feed an
279 ;; FP store as long as the sizes are the same.
280 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
281 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
282 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
283 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
284 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
286 ;; We have an "anti-bypass" for FP loads which feed an FP store.
287 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
289 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
290 ;; floating point computations with non-floating point computations (fp loads
291 ;; and stores are not fp computations).
293 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
294 ;; take two cycles, during which no Dcache operations should be scheduled.
295 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
296 ;; all have the same memory characteristics if one disregards cache misses.
298 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
299 ;; There's no value in modeling the ALU and MUL separately though
300 ;; since there can never be a functional unit conflict given the
301 ;; latency and issue rates for those units.
304 ;; Instruction Time Unit Minimum Distance (unit contention)
311 ;; fmpyadd 2 ALU,MPY 1
312 ;; fmpysub 2 ALU,MPY 1
313 ;; fmpycfxt 2 ALU,MPY 1
317 ;; fdiv,dbl 15 DIV 15
319 ;; fsqrt,dbl 15 DIV 15
321 (define_automaton "pa7100")
322 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
324 (define_insn_reservation "X0" 2
325 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
326 (eq_attr "cpu" "7100"))
329 (define_insn_reservation "X1" 8
330 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
331 (eq_attr "cpu" "7100"))
332 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
334 (define_insn_reservation "X2" 15
335 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
336 (eq_attr "cpu" "7100"))
337 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
339 (define_insn_reservation "X3" 2
340 (and (eq_attr "type" "load")
341 (eq_attr "cpu" "7100"))
344 (define_insn_reservation "X4" 2
345 (and (eq_attr "type" "fpload")
346 (eq_attr "cpu" "7100"))
349 (define_insn_reservation "X5" 2
350 (and (eq_attr "type" "store")
351 (eq_attr "cpu" "7100"))
352 "i_7100+mem_7100,mem_7100")
354 (define_insn_reservation "X6" 2
355 (and (eq_attr "type" "fpstore")
356 (eq_attr "cpu" "7100"))
357 "i_7100+mem_7100,mem_7100")
359 (define_insn_reservation "X7" 4
360 (and (eq_attr "type" "fpstore_load")
361 (eq_attr "cpu" "7100"))
362 "i_7100+mem_7100,mem_7100*3")
364 (define_insn_reservation "X8" 4
365 (and (eq_attr "type" "store_fpload")
366 (eq_attr "cpu" "7100"))
367 "i_7100+mem_7100,mem_7100*3")
369 (define_insn_reservation "X9" 1
370 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
371 (eq_attr "cpu" "7100"))
374 ;; We have a bypass for all computations in the FP unit which feed an
375 ;; FP store as long as the sizes are the same.
376 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
377 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
378 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
380 ;; We have an "anti-bypass" for FP loads which feed an FP store.
381 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
383 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
384 ;; There's no value in modeling the ALU and MUL separately though
385 ;; since there can never be a functional unit conflict that
386 ;; can be avoided given the latency, issue rates and mandatory
387 ;; one cycle cpu-wide lock for a double precision fp multiply.
390 ;; Instruction Time Unit Minimum Distance (unit contention)
397 ;; fmpyadd,sgl 2 ALU,MPY 1
398 ;; fmpyadd,dbl 3 ALU,MPY 2
399 ;; fmpysub,sgl 2 ALU,MPY 1
400 ;; fmpysub,dbl 3 ALU,MPY 2
401 ;; fmpycfxt,sgl 2 ALU,MPY 1
402 ;; fmpycfxt,dbl 3 ALU,MPY 2
407 ;; fdiv,dbl 15 DIV 15
409 ;; fsqrt,dbl 15 DIV 15
411 ;; The PA7200 is just like the PA7100LC except that there is
412 ;; no store-store penalty.
414 ;; The PA7300 is just like the PA7200 except that there is
415 ;; no store-load penalty.
417 ;; Note there are some aspects of the 7100LC we are not modeling
418 ;; at the moment. I'll be reviewing the 7100LC scheduling info
419 ;; shortly and updating this description.
423 ;; other issue modeling
425 (define_automaton "pa7100lc")
426 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
427 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
428 (define_cpu_unit "mem_7100lc" "pa7100lc")
430 ;; Double precision multiplies lock the entire CPU for one
431 ;; cycle. There is no way to avoid this lock and trying to
432 ;; schedule around the lock is pointless and thus there is no
433 ;; value in trying to model this lock.
435 ;; Not modeling the lock allows us to treat fp multiplies just
436 ;; like any other FP alu instruction. It allows for a smaller
437 ;; DFA and may reduce register pressure.
438 (define_insn_reservation "Y0" 2
439 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
440 (eq_attr "cpu" "7100LC,7200,7300"))
441 "f_7100lc,fpmac_7100lc")
443 ;; fp division and sqrt instructions lock the entire CPU for
444 ;; 7 cycles (single precision) or 14 cycles (double precision).
445 ;; There is no way to avoid this lock and trying to schedule
446 ;; around the lock is pointless and thus there is no value in
447 ;; trying to model this lock. Not modeling the lock allows
448 ;; for a smaller DFA and may reduce register pressure.
449 (define_insn_reservation "Y1" 1
450 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
451 (eq_attr "cpu" "7100LC,7200,7300"))
454 (define_insn_reservation "Y2" 2
455 (and (eq_attr "type" "load")
456 (eq_attr "cpu" "7100LC,7200,7300"))
457 "i1_7100lc+mem_7100lc")
459 (define_insn_reservation "Y3" 2
460 (and (eq_attr "type" "fpload")
461 (eq_attr "cpu" "7100LC,7200,7300"))
462 "i1_7100lc+mem_7100lc")
464 (define_insn_reservation "Y4" 2
465 (and (eq_attr "type" "store")
466 (eq_attr "cpu" "7100LC"))
467 "i1_7100lc+mem_7100lc,mem_7100lc")
469 (define_insn_reservation "Y5" 2
470 (and (eq_attr "type" "fpstore")
471 (eq_attr "cpu" "7100LC"))
472 "i1_7100lc+mem_7100lc,mem_7100lc")
474 (define_insn_reservation "Y6" 4
475 (and (eq_attr "type" "fpstore_load")
476 (eq_attr "cpu" "7100LC"))
477 "i1_7100lc+mem_7100lc,mem_7100lc*3")
479 (define_insn_reservation "Y7" 4
480 (and (eq_attr "type" "store_fpload")
481 (eq_attr "cpu" "7100LC"))
482 "i1_7100lc+mem_7100lc,mem_7100lc*3")
484 (define_insn_reservation "Y8" 1
485 (and (eq_attr "type" "shift,nullshift")
486 (eq_attr "cpu" "7100LC,7200,7300"))
489 (define_insn_reservation "Y9" 1
490 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
491 (eq_attr "cpu" "7100LC,7200,7300"))
492 "(i0_7100lc|i1_7100lc)")
494 ;; The 7200 has a store-load penalty
495 (define_insn_reservation "Y10" 2
496 (and (eq_attr "type" "store")
497 (eq_attr "cpu" "7200"))
498 "i1_7100lc,mem_7100lc")
500 (define_insn_reservation "Y11" 2
501 (and (eq_attr "type" "fpstore")
502 (eq_attr "cpu" "7200"))
503 "i1_7100lc,mem_7100lc")
505 (define_insn_reservation "Y12" 4
506 (and (eq_attr "type" "fpstore_load")
507 (eq_attr "cpu" "7200"))
508 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
510 (define_insn_reservation "Y13" 4
511 (and (eq_attr "type" "store_fpload")
512 (eq_attr "cpu" "7200"))
513 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
515 ;; The 7300 has no penalty for store-store or store-load
516 (define_insn_reservation "Y14" 2
517 (and (eq_attr "type" "store")
518 (eq_attr "cpu" "7300"))
521 (define_insn_reservation "Y15" 2
522 (and (eq_attr "type" "fpstore")
523 (eq_attr "cpu" "7300"))
526 (define_insn_reservation "Y16" 4
527 (and (eq_attr "type" "fpstore_load")
528 (eq_attr "cpu" "7300"))
529 "i1_7100lc,i1_7100lc+mem_7100lc")
531 (define_insn_reservation "Y17" 4
532 (and (eq_attr "type" "store_fpload")
533 (eq_attr "cpu" "7300"))
534 "i1_7100lc,i1_7100lc+mem_7100lc")
536 ;; We have an "anti-bypass" for FP loads which feed an FP store.
537 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
539 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
540 ;; traditional architecture.
542 ;; The PA8000 has a large (56) entry reorder buffer that is split between
543 ;; memory and non-memory operations.
545 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
546 ;; the function units, with the exception of branches and multi-output
547 ;; instructions. The PA8000 can retire two non-memory operations per cycle
548 ;; and two memory operations per cycle, only one of which may be a store.
550 ;; Given the large reorder buffer, the processor can hide most latencies.
551 ;; According to HP, they've got the best results by scheduling for retirement
552 ;; bandwidth with limited latency scheduling for floating point operations.
553 ;; Latency for integer operations and memory references is ignored.
556 ;; We claim floating point operations have a 2 cycle latency and are
557 ;; fully pipelined, except for div and sqrt which are not pipelined and
558 ;; take from 17 to 31 cycles to complete.
560 ;; It's worth noting that there is no way to saturate all the functional
561 ;; units on the PA8000 as there is not enough issue bandwidth.
563 (define_automaton "pa8000")
564 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
565 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
566 (define_cpu_unit "store_8000" "pa8000")
567 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
568 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
569 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
570 (define_reservation "im_8000" "im0_8000 | im1_8000")
571 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
572 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
573 (define_reservation "f_8000" "f0_8000 | f1_8000")
574 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
576 ;; We can issue any two memops per cycle, but we can only retire
577 ;; one memory store per cycle. We assume that the reorder buffer
578 ;; will hide any memory latencies per HP's recommendation.
579 (define_insn_reservation "Z0" 0
581 (eq_attr "type" "load,fpload")
582 (eq_attr "cpu" "8000"))
585 (define_insn_reservation "Z1" 0
587 (eq_attr "type" "store,fpstore")
588 (eq_attr "cpu" "8000"))
589 "im_8000,rm_8000+store_8000")
591 (define_insn_reservation "Z2" 0
592 (and (eq_attr "type" "fpstore_load,store_fpload")
593 (eq_attr "cpu" "8000"))
594 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
596 ;; We can issue and retire two non-memory operations per cycle with
597 ;; a few exceptions (branches). This group catches those we want
598 ;; to assume have zero latency.
599 (define_insn_reservation "Z3" 0
601 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
602 (eq_attr "cpu" "8000"))
605 ;; Branches use both slots in the non-memory issue and
607 (define_insn_reservation "Z4" 0
609 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
610 (eq_attr "cpu" "8000"))
611 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
613 ;; We partial latency schedule the floating point units.
614 ;; They can issue/retire two at a time in the non-memory
615 ;; units. We fix their latency at 2 cycles and they
616 ;; are fully pipelined.
617 (define_insn_reservation "Z5" 1
619 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
620 (eq_attr "cpu" "8000"))
621 "inm_8000,f_8000,rnm_8000")
623 ;; The fdivsqrt units are not pipelined and have a very long latency.
624 ;; To keep the DFA from exploding, we do not show all the
625 ;; reservations for the divsqrt unit.
626 (define_insn_reservation "Z6" 17
628 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
629 (eq_attr "cpu" "8000"))
630 "inm_8000,fdivsqrt_8000*6,rnm_8000")
632 (define_insn_reservation "Z7" 31
634 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
635 (eq_attr "cpu" "8000"))
636 "inm_8000,fdivsqrt_8000*6,rnm_8000")
638 ;; Operand and operator predicates and constraints
640 (include "predicates.md")
641 (include "constraints.md")
643 ;; Compare instructions.
644 ;; This controls RTL generation and register allocation.
646 ;; We generate RTL for comparisons and branches by having the cmpxx
647 ;; patterns store away the operands. Then, the scc and bcc patterns
648 ;; emit RTL for both the compare and the branch.
651 (define_expand "cmpdi"
653 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
654 (match_operand:DI 1 "register_operand" "")))]
659 hppa_compare_op0 = operands[0];
660 hppa_compare_op1 = operands[1];
661 hppa_branch_type = CMP_SI;
665 (define_expand "cmpsi"
667 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
668 (match_operand:SI 1 "arith5_operand" "")))]
672 hppa_compare_op0 = operands[0];
673 hppa_compare_op1 = operands[1];
674 hppa_branch_type = CMP_SI;
678 (define_expand "cmpsf"
680 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
681 (match_operand:SF 1 "reg_or_0_operand" "")))]
682 "! TARGET_SOFT_FLOAT"
685 hppa_compare_op0 = operands[0];
686 hppa_compare_op1 = operands[1];
687 hppa_branch_type = CMP_SF;
691 (define_expand "cmpdf"
693 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
694 (match_operand:DF 1 "reg_or_0_operand" "")))]
695 "! TARGET_SOFT_FLOAT"
698 hppa_compare_op0 = operands[0];
699 hppa_compare_op1 = operands[1];
700 hppa_branch_type = CMP_DF;
706 (match_operator:CCFP 2 "comparison_operator"
707 [(match_operand:SF 0 "reg_or_0_operand" "fG")
708 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
709 "! TARGET_SOFT_FLOAT"
710 "fcmp,sgl,%Y2 %f0,%f1"
711 [(set_attr "length" "4")
712 (set_attr "type" "fpcc")])
716 (match_operator:CCFP 2 "comparison_operator"
717 [(match_operand:DF 0 "reg_or_0_operand" "fG")
718 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
719 "! TARGET_SOFT_FLOAT"
720 "fcmp,dbl,%Y2 %f0,%f1"
721 [(set_attr "length" "4")
722 (set_attr "type" "fpcc")])
724 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
725 ;; placeholders. This is necessary in rare situations when a
726 ;; placeholder is re-emitted (see PR 8705).
728 (define_expand "movccfp"
730 (match_operand 0 "const_int_operand" ""))]
731 "! TARGET_SOFT_FLOAT"
734 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
738 ;; The following patterns are optimization placeholders. In almost
739 ;; all cases, the user of the condition code will be simplified and the
740 ;; original condition code setting insn should be eliminated.
742 (define_insn "*movccfp0"
745 "! TARGET_SOFT_FLOAT"
746 "fcmp,dbl,= %%fr0,%%fr0"
747 [(set_attr "length" "4")
748 (set_attr "type" "fpcc")])
750 (define_insn "*movccfp1"
753 "! TARGET_SOFT_FLOAT"
754 "fcmp,dbl,!= %%fr0,%%fr0"
755 [(set_attr "length" "4")
756 (set_attr "type" "fpcc")])
761 [(set (match_operand:SI 0 "register_operand" "")
767 /* fp scc patterns rarely match, and are not a win on the PA. */
768 if (hppa_branch_type != CMP_SI)
770 /* set up operands from compare. */
771 operands[1] = hppa_compare_op0;
772 operands[2] = hppa_compare_op1;
773 /* fall through and generate default code */
777 [(set (match_operand:SI 0 "register_operand" "")
783 /* fp scc patterns rarely match, and are not a win on the PA. */
784 if (hppa_branch_type != CMP_SI)
786 operands[1] = hppa_compare_op0;
787 operands[2] = hppa_compare_op1;
791 [(set (match_operand:SI 0 "register_operand" "")
797 /* fp scc patterns rarely match, and are not a win on the PA. */
798 if (hppa_branch_type != CMP_SI)
800 operands[1] = hppa_compare_op0;
801 operands[2] = hppa_compare_op1;
805 [(set (match_operand:SI 0 "register_operand" "")
811 /* fp scc patterns rarely match, and are not a win on the PA. */
812 if (hppa_branch_type != CMP_SI)
814 operands[1] = hppa_compare_op0;
815 operands[2] = hppa_compare_op1;
819 [(set (match_operand:SI 0 "register_operand" "")
825 /* fp scc patterns rarely match, and are not a win on the PA. */
826 if (hppa_branch_type != CMP_SI)
828 operands[1] = hppa_compare_op0;
829 operands[2] = hppa_compare_op1;
833 [(set (match_operand:SI 0 "register_operand" "")
839 /* fp scc patterns rarely match, and are not a win on the PA. */
840 if (hppa_branch_type != CMP_SI)
842 operands[1] = hppa_compare_op0;
843 operands[2] = hppa_compare_op1;
846 (define_expand "sltu"
847 [(set (match_operand:SI 0 "register_operand" "")
848 (ltu:SI (match_dup 1)
853 if (hppa_branch_type != CMP_SI)
855 operands[1] = hppa_compare_op0;
856 operands[2] = hppa_compare_op1;
859 (define_expand "sgtu"
860 [(set (match_operand:SI 0 "register_operand" "")
861 (gtu:SI (match_dup 1)
866 if (hppa_branch_type != CMP_SI)
868 operands[1] = hppa_compare_op0;
869 operands[2] = hppa_compare_op1;
872 (define_expand "sleu"
873 [(set (match_operand:SI 0 "register_operand" "")
874 (leu:SI (match_dup 1)
879 if (hppa_branch_type != CMP_SI)
881 operands[1] = hppa_compare_op0;
882 operands[2] = hppa_compare_op1;
885 (define_expand "sgeu"
886 [(set (match_operand:SI 0 "register_operand" "")
887 (geu:SI (match_dup 1)
892 if (hppa_branch_type != CMP_SI)
894 operands[1] = hppa_compare_op0;
895 operands[2] = hppa_compare_op1;
898 ;; Instruction canonicalization puts immediate operands second, which
899 ;; is the reverse of what we want.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (match_operator:SI 3 "comparison_operator"
904 [(match_operand:SI 1 "register_operand" "r")
905 (match_operand:SI 2 "arith11_operand" "rI")]))]
907 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (match_operator:DI 3 "comparison_operator"
914 [(match_operand:DI 1 "register_operand" "r")
915 (match_operand:DI 2 "arith11_operand" "rI")]))]
917 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 (define_insn "iorscc"
922 [(set (match_operand:SI 0 "register_operand" "=r")
923 (ior:SI (match_operator:SI 3 "comparison_operator"
924 [(match_operand:SI 1 "register_operand" "r")
925 (match_operand:SI 2 "arith11_operand" "rI")])
926 (match_operator:SI 6 "comparison_operator"
927 [(match_operand:SI 4 "register_operand" "r")
928 (match_operand:SI 5 "arith11_operand" "rI")])))]
930 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "12")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (ior:DI (match_operator:DI 3 "comparison_operator"
937 [(match_operand:DI 1 "register_operand" "r")
938 (match_operand:DI 2 "arith11_operand" "rI")])
939 (match_operator:DI 6 "comparison_operator"
940 [(match_operand:DI 4 "register_operand" "r")
941 (match_operand:DI 5 "arith11_operand" "rI")])))]
943 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
944 [(set_attr "type" "binary")
945 (set_attr "length" "12")])
947 ;; Combiner patterns for common operations performed with the output
948 ;; from an scc insn (negscc and incscc).
949 (define_insn "negscc"
950 [(set (match_operand:SI 0 "register_operand" "=r")
951 (neg:SI (match_operator:SI 3 "comparison_operator"
952 [(match_operand:SI 1 "register_operand" "r")
953 (match_operand:SI 2 "arith11_operand" "rI")])))]
955 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
956 [(set_attr "type" "binary")
957 (set_attr "length" "8")])
960 [(set (match_operand:DI 0 "register_operand" "=r")
961 (neg:DI (match_operator:DI 3 "comparison_operator"
962 [(match_operand:DI 1 "register_operand" "r")
963 (match_operand:DI 2 "arith11_operand" "rI")])))]
965 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
966 [(set_attr "type" "binary")
967 (set_attr "length" "8")])
969 ;; Patterns for adding/subtracting the result of a boolean expression from
970 ;; a register. First we have special patterns that make use of the carry
971 ;; bit, and output only two instructions. For the cases we can't in
972 ;; general do in two instructions, the incscc pattern at the end outputs
973 ;; two or three instructions.
976 [(set (match_operand:SI 0 "register_operand" "=r")
977 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
978 (match_operand:SI 3 "arith11_operand" "rI"))
979 (match_operand:SI 1 "register_operand" "r")))]
981 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
982 [(set_attr "type" "binary")
983 (set_attr "length" "8")])
986 [(set (match_operand:DI 0 "register_operand" "=r")
987 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
988 (match_operand:DI 3 "arith11_operand" "rI"))
989 (match_operand:DI 1 "register_operand" "r")))]
991 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
992 [(set_attr "type" "binary")
993 (set_attr "length" "8")])
995 ; This need only accept registers for op3, since canonicalization
996 ; replaces geu with gtu when op3 is an integer.
998 [(set (match_operand:SI 0 "register_operand" "=r")
999 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
1000 (match_operand:SI 3 "register_operand" "r"))
1001 (match_operand:SI 1 "register_operand" "r")))]
1003 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
1004 [(set_attr "type" "binary")
1005 (set_attr "length" "8")])
1008 [(set (match_operand:DI 0 "register_operand" "=r")
1009 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
1010 (match_operand:DI 3 "register_operand" "r"))
1011 (match_operand:DI 1 "register_operand" "r")))]
1013 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
1014 [(set_attr "type" "binary")
1015 (set_attr "length" "8")])
1017 ; Match only integers for op3 here. This is used as canonical form of the
1018 ; geu pattern when op3 is an integer. Don't match registers since we can't
1019 ; make better code than the general incscc pattern.
1021 [(set (match_operand:SI 0 "register_operand" "=r")
1022 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
1023 (match_operand:SI 3 "int11_operand" "I"))
1024 (match_operand:SI 1 "register_operand" "r")))]
1026 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
1027 [(set_attr "type" "binary")
1028 (set_attr "length" "8")])
1031 [(set (match_operand:DI 0 "register_operand" "=r")
1032 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
1033 (match_operand:DI 3 "int11_operand" "I"))
1034 (match_operand:DI 1 "register_operand" "r")))]
1036 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
1037 [(set_attr "type" "binary")
1038 (set_attr "length" "8")])
1040 (define_insn "incscc"
1041 [(set (match_operand:SI 0 "register_operand" "=r,r")
1042 (plus:SI (match_operator:SI 4 "comparison_operator"
1043 [(match_operand:SI 2 "register_operand" "r,r")
1044 (match_operand:SI 3 "arith11_operand" "rI,rI")])
1045 (match_operand:SI 1 "register_operand" "0,?r")))]
1048 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
1049 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1050 [(set_attr "type" "binary,binary")
1051 (set_attr "length" "8,12")])
1054 [(set (match_operand:DI 0 "register_operand" "=r,r")
1055 (plus:DI (match_operator:DI 4 "comparison_operator"
1056 [(match_operand:DI 2 "register_operand" "r,r")
1057 (match_operand:DI 3 "arith11_operand" "rI,rI")])
1058 (match_operand:DI 1 "register_operand" "0,?r")))]
1061 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
1062 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1063 [(set_attr "type" "binary,binary")
1064 (set_attr "length" "8,12")])
1067 [(set (match_operand:SI 0 "register_operand" "=r")
1068 (minus:SI (match_operand:SI 1 "register_operand" "r")
1069 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1070 (match_operand:SI 3 "arith11_operand" "rI"))))]
1072 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1073 [(set_attr "type" "binary")
1074 (set_attr "length" "8")])
1077 [(set (match_operand:DI 0 "register_operand" "=r")
1078 (minus:DI (match_operand:DI 1 "register_operand" "r")
1079 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1080 (match_operand:DI 3 "arith11_operand" "rI"))))]
1082 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1083 [(set_attr "type" "binary")
1084 (set_attr "length" "8")])
1087 [(set (match_operand:SI 0 "register_operand" "=r")
1088 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1089 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1090 (match_operand:SI 3 "arith11_operand" "rI")))
1091 (match_operand:SI 4 "register_operand" "r")))]
1093 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1094 [(set_attr "type" "binary")
1095 (set_attr "length" "8")])
1098 [(set (match_operand:DI 0 "register_operand" "=r")
1099 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1100 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1101 (match_operand:DI 3 "arith11_operand" "rI")))
1102 (match_operand:DI 4 "register_operand" "r")))]
1104 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1105 [(set_attr "type" "binary")
1106 (set_attr "length" "8")])
1108 ; This need only accept registers for op3, since canonicalization
1109 ; replaces ltu with leu when op3 is an integer.
1111 [(set (match_operand:SI 0 "register_operand" "=r")
1112 (minus:SI (match_operand:SI 1 "register_operand" "r")
1113 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1114 (match_operand:SI 3 "register_operand" "r"))))]
1116 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1117 [(set_attr "type" "binary")
1118 (set_attr "length" "8")])
1121 [(set (match_operand:DI 0 "register_operand" "=r")
1122 (minus:DI (match_operand:DI 1 "register_operand" "r")
1123 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1124 (match_operand:DI 3 "register_operand" "r"))))]
1126 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1127 [(set_attr "type" "binary")
1128 (set_attr "length" "8")])
1131 [(set (match_operand:SI 0 "register_operand" "=r")
1132 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1133 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1134 (match_operand:SI 3 "register_operand" "r")))
1135 (match_operand:SI 4 "register_operand" "r")))]
1137 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1138 [(set_attr "type" "binary")
1139 (set_attr "length" "8")])
1142 [(set (match_operand:DI 0 "register_operand" "=r")
1143 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1144 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1145 (match_operand:DI 3 "register_operand" "r")))
1146 (match_operand:DI 4 "register_operand" "r")))]
1148 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1149 [(set_attr "type" "binary")
1150 (set_attr "length" "8")])
1152 ; Match only integers for op3 here. This is used as canonical form of the
1153 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1154 ; make better code than the general incscc pattern.
1156 [(set (match_operand:SI 0 "register_operand" "=r")
1157 (minus:SI (match_operand:SI 1 "register_operand" "r")
1158 (leu:SI (match_operand:SI 2 "register_operand" "r")
1159 (match_operand:SI 3 "int11_operand" "I"))))]
1161 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1162 [(set_attr "type" "binary")
1163 (set_attr "length" "8")])
1166 [(set (match_operand:DI 0 "register_operand" "=r")
1167 (minus:DI (match_operand:DI 1 "register_operand" "r")
1168 (leu:DI (match_operand:DI 2 "register_operand" "r")
1169 (match_operand:DI 3 "int11_operand" "I"))))]
1171 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1172 [(set_attr "type" "binary")
1173 (set_attr "length" "8")])
1176 [(set (match_operand:SI 0 "register_operand" "=r")
1177 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1178 (leu:SI (match_operand:SI 2 "register_operand" "r")
1179 (match_operand:SI 3 "int11_operand" "I")))
1180 (match_operand:SI 4 "register_operand" "r")))]
1182 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1183 [(set_attr "type" "binary")
1184 (set_attr "length" "8")])
1187 [(set (match_operand:DI 0 "register_operand" "=r")
1188 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1189 (leu:DI (match_operand:DI 2 "register_operand" "r")
1190 (match_operand:DI 3 "int11_operand" "I")))
1191 (match_operand:DI 4 "register_operand" "r")))]
1193 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1194 [(set_attr "type" "binary")
1195 (set_attr "length" "8")])
1197 (define_insn "decscc"
1198 [(set (match_operand:SI 0 "register_operand" "=r,r")
1199 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1200 (match_operator:SI 4 "comparison_operator"
1201 [(match_operand:SI 2 "register_operand" "r,r")
1202 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1205 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1206 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1207 [(set_attr "type" "binary,binary")
1208 (set_attr "length" "8,12")])
1211 [(set (match_operand:DI 0 "register_operand" "=r,r")
1212 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1213 (match_operator:DI 4 "comparison_operator"
1214 [(match_operand:DI 2 "register_operand" "r,r")
1215 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1218 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1219 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1220 [(set_attr "type" "binary,binary")
1221 (set_attr "length" "8,12")])
1223 ; Patterns for max and min. (There is no need for an earlyclobber in the
1224 ; last alternative since the middle alternative will match if op0 == op1.)
1226 (define_insn "sminsi3"
1227 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1228 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1229 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1232 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1233 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1234 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1235 [(set_attr "type" "multi,multi,multi")
1236 (set_attr "length" "8,8,8")])
1238 (define_insn "smindi3"
1239 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1240 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1241 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1244 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1245 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1246 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1247 [(set_attr "type" "multi,multi,multi")
1248 (set_attr "length" "8,8,8")])
1250 (define_insn "uminsi3"
1251 [(set (match_operand:SI 0 "register_operand" "=r,r")
1252 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1253 (match_operand:SI 2 "arith11_operand" "r,I")))]
1256 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1257 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1258 [(set_attr "type" "multi,multi")
1259 (set_attr "length" "8,8")])
1261 (define_insn "umindi3"
1262 [(set (match_operand:DI 0 "register_operand" "=r,r")
1263 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1264 (match_operand:DI 2 "arith11_operand" "r,I")))]
1267 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1268 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1269 [(set_attr "type" "multi,multi")
1270 (set_attr "length" "8,8")])
1272 (define_insn "smaxsi3"
1273 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1274 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1275 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1278 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1279 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1280 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1281 [(set_attr "type" "multi,multi,multi")
1282 (set_attr "length" "8,8,8")])
1284 (define_insn "smaxdi3"
1285 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1286 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1287 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1290 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1291 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1292 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1293 [(set_attr "type" "multi,multi,multi")
1294 (set_attr "length" "8,8,8")])
1296 (define_insn "umaxsi3"
1297 [(set (match_operand:SI 0 "register_operand" "=r,r")
1298 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1299 (match_operand:SI 2 "arith11_operand" "r,I")))]
1302 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1303 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1304 [(set_attr "type" "multi,multi")
1305 (set_attr "length" "8,8")])
1307 (define_insn "umaxdi3"
1308 [(set (match_operand:DI 0 "register_operand" "=r,r")
1309 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1310 (match_operand:DI 2 "arith11_operand" "r,I")))]
1313 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1314 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1315 [(set_attr "type" "multi,multi")
1316 (set_attr "length" "8,8")])
1318 (define_insn "abssi2"
1319 [(set (match_operand:SI 0 "register_operand" "=r")
1320 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1322 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1323 [(set_attr "type" "multi")
1324 (set_attr "length" "8")])
1326 (define_insn "absdi2"
1327 [(set (match_operand:DI 0 "register_operand" "=r")
1328 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1330 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1331 [(set_attr "type" "multi")
1332 (set_attr "length" "8")])
1334 ;;; Experimental conditional move patterns
1336 (define_expand "movsicc"
1337 [(set (match_operand:SI 0 "register_operand" "")
1339 (match_operator 1 "comparison_operator"
1342 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1343 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1347 enum rtx_code code = GET_CODE (operands[1]);
1349 if (hppa_branch_type != CMP_SI)
1352 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1353 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1356 /* operands[1] is currently the result of compare_from_rtx. We want to
1357 emit a compare of the original operands. */
1358 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1359 operands[4] = hppa_compare_op0;
1360 operands[5] = hppa_compare_op1;
1363 ;; We used to accept any register for op1.
1365 ;; However, it loses sometimes because the compiler will end up using
1366 ;; different registers for op0 and op1 in some critical cases. local-alloc
1367 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1369 ;; If/when global register allocation supports tying we should allow any
1370 ;; register for op1 again.
1372 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1374 (match_operator 2 "comparison_operator"
1375 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1376 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1377 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1381 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1382 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1383 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1384 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1385 [(set_attr "type" "multi,multi,multi,nullshift")
1386 (set_attr "length" "8,8,8,8")])
1389 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1391 (match_operator 5 "comparison_operator"
1392 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1393 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1394 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1395 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1398 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1399 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1400 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1401 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1402 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1403 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1404 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1405 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1406 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1407 (set_attr "length" "8,8,8,8,8,8,8,8")])
1409 (define_expand "movdicc"
1410 [(set (match_operand:DI 0 "register_operand" "")
1412 (match_operator 1 "comparison_operator"
1415 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1416 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1420 enum rtx_code code = GET_CODE (operands[1]);
1422 if (hppa_branch_type != CMP_SI)
1425 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1426 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1429 /* operands[1] is currently the result of compare_from_rtx. We want to
1430 emit a compare of the original operands. */
1431 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1432 operands[4] = hppa_compare_op0;
1433 operands[5] = hppa_compare_op1;
1436 ; We need the first constraint alternative in order to avoid
1437 ; earlyclobbers on all other alternatives.
1439 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1441 (match_operator 2 "comparison_operator"
1442 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1443 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1444 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1448 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1449 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1450 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1451 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1452 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1453 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1454 (set_attr "length" "8,8,8,8,8")])
1457 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1459 (match_operator 5 "comparison_operator"
1460 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1461 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1462 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1463 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1466 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1467 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1468 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1469 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1470 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1471 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1472 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1473 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1474 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1475 (set_attr "length" "8,8,8,8,8,8,8,8")])
1477 ;; Conditional Branches
1479 (define_expand "beq"
1481 (if_then_else (eq (match_dup 1) (match_dup 2))
1482 (label_ref (match_operand 0 "" ""))
1487 if (hppa_branch_type != CMP_SI)
1489 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1490 emit_bcond_fp (NE, operands[0]);
1493 /* set up operands from compare. */
1494 operands[1] = hppa_compare_op0;
1495 operands[2] = hppa_compare_op1;
1496 /* fall through and generate default code */
1499 (define_expand "bne"
1501 (if_then_else (ne (match_dup 1) (match_dup 2))
1502 (label_ref (match_operand 0 "" ""))
1507 if (hppa_branch_type != CMP_SI)
1509 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1510 emit_bcond_fp (NE, operands[0]);
1513 operands[1] = hppa_compare_op0;
1514 operands[2] = hppa_compare_op1;
1517 (define_expand "bgt"
1519 (if_then_else (gt (match_dup 1) (match_dup 2))
1520 (label_ref (match_operand 0 "" ""))
1525 if (hppa_branch_type != CMP_SI)
1527 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1528 emit_bcond_fp (NE, operands[0]);
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "blt"
1537 (if_then_else (lt (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1546 emit_bcond_fp (NE, operands[0]);
1549 operands[1] = hppa_compare_op0;
1550 operands[2] = hppa_compare_op1;
1553 (define_expand "bge"
1555 (if_then_else (ge (match_dup 1) (match_dup 2))
1556 (label_ref (match_operand 0 "" ""))
1561 if (hppa_branch_type != CMP_SI)
1563 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1564 emit_bcond_fp (NE, operands[0]);
1567 operands[1] = hppa_compare_op0;
1568 operands[2] = hppa_compare_op1;
1571 (define_expand "ble"
1573 (if_then_else (le (match_dup 1) (match_dup 2))
1574 (label_ref (match_operand 0 "" ""))
1579 if (hppa_branch_type != CMP_SI)
1581 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1582 emit_bcond_fp (NE, operands[0]);
1585 operands[1] = hppa_compare_op0;
1586 operands[2] = hppa_compare_op1;
1589 (define_expand "bgtu"
1591 (if_then_else (gtu (match_dup 1) (match_dup 2))
1592 (label_ref (match_operand 0 "" ""))
1597 if (hppa_branch_type != CMP_SI)
1599 operands[1] = hppa_compare_op0;
1600 operands[2] = hppa_compare_op1;
1603 (define_expand "bltu"
1605 (if_then_else (ltu (match_dup 1) (match_dup 2))
1606 (label_ref (match_operand 0 "" ""))
1611 if (hppa_branch_type != CMP_SI)
1613 operands[1] = hppa_compare_op0;
1614 operands[2] = hppa_compare_op1;
1617 (define_expand "bgeu"
1619 (if_then_else (geu (match_dup 1) (match_dup 2))
1620 (label_ref (match_operand 0 "" ""))
1625 if (hppa_branch_type != CMP_SI)
1627 operands[1] = hppa_compare_op0;
1628 operands[2] = hppa_compare_op1;
1631 (define_expand "bleu"
1633 (if_then_else (leu (match_dup 1) (match_dup 2))
1634 (label_ref (match_operand 0 "" ""))
1639 if (hppa_branch_type != CMP_SI)
1641 operands[1] = hppa_compare_op0;
1642 operands[2] = hppa_compare_op1;
1645 (define_expand "bltgt"
1647 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1648 (label_ref (match_operand 0 "" ""))
1653 if (hppa_branch_type == CMP_SI)
1655 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1656 emit_bcond_fp (NE, operands[0]);
1660 (define_expand "bunle"
1662 (if_then_else (unle (match_dup 1) (match_dup 2))
1663 (label_ref (match_operand 0 "" ""))
1668 if (hppa_branch_type == CMP_SI)
1670 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1671 emit_bcond_fp (NE, operands[0]);
1675 (define_expand "bunlt"
1677 (if_then_else (unlt (match_dup 1) (match_dup 2))
1678 (label_ref (match_operand 0 "" ""))
1683 if (hppa_branch_type == CMP_SI)
1685 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1686 emit_bcond_fp (NE, operands[0]);
1690 (define_expand "bunge"
1692 (if_then_else (unge (match_dup 1) (match_dup 2))
1693 (label_ref (match_operand 0 "" ""))
1698 if (hppa_branch_type == CMP_SI)
1700 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1701 emit_bcond_fp (NE, operands[0]);
1705 (define_expand "bungt"
1707 (if_then_else (ungt (match_dup 1) (match_dup 2))
1708 (label_ref (match_operand 0 "" ""))
1713 if (hppa_branch_type == CMP_SI)
1715 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1716 emit_bcond_fp (NE, operands[0]);
1720 (define_expand "buneq"
1722 (if_then_else (uneq (match_dup 1) (match_dup 2))
1723 (label_ref (match_operand 0 "" ""))
1728 if (hppa_branch_type == CMP_SI)
1730 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1731 emit_bcond_fp (NE, operands[0]);
1735 (define_expand "bunordered"
1737 (if_then_else (unordered (match_dup 1) (match_dup 2))
1738 (label_ref (match_operand 0 "" ""))
1743 if (hppa_branch_type == CMP_SI)
1745 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1746 emit_bcond_fp (NE, operands[0]);
1750 (define_expand "bordered"
1752 (if_then_else (ordered (match_dup 1) (match_dup 2))
1753 (label_ref (match_operand 0 "" ""))
1758 if (hppa_branch_type == CMP_SI)
1760 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1761 emit_bcond_fp (NE, operands[0]);
1765 ;; Match the branch patterns.
1768 ;; Note a long backward conditional branch with an annulled delay slot
1769 ;; has a length of 12.
1773 (match_operator 3 "comparison_operator"
1774 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1775 (match_operand:SI 2 "arith5_operand" "rL")])
1776 (label_ref (match_operand 0 "" ""))
1781 return output_cbranch (operands, 0, insn);
1783 [(set_attr "type" "cbranch")
1784 (set (attr "length")
1785 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1786 (const_int MAX_12BIT_OFFSET))
1788 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1789 (const_int MAX_17BIT_OFFSET))
1791 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1793 (eq (symbol_ref "flag_pic") (const_int 0))
1797 ;; Match the negated branch.
1802 (match_operator 3 "comparison_operator"
1803 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1804 (match_operand:SI 2 "arith5_operand" "rL")])
1806 (label_ref (match_operand 0 "" ""))))]
1810 return output_cbranch (operands, 1, insn);
1812 [(set_attr "type" "cbranch")
1813 (set (attr "length")
1814 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1815 (const_int MAX_12BIT_OFFSET))
1817 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1818 (const_int MAX_17BIT_OFFSET))
1820 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1822 (eq (symbol_ref "flag_pic") (const_int 0))
1829 (match_operator 3 "comparison_operator"
1830 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1831 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1832 (label_ref (match_operand 0 "" ""))
1837 return output_cbranch (operands, 0, insn);
1839 [(set_attr "type" "cbranch")
1840 (set (attr "length")
1841 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1842 (const_int MAX_12BIT_OFFSET))
1844 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1845 (const_int MAX_17BIT_OFFSET))
1847 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1849 (eq (symbol_ref "flag_pic") (const_int 0))
1853 ;; Match the negated branch.
1858 (match_operator 3 "comparison_operator"
1859 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1860 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1862 (label_ref (match_operand 0 "" ""))))]
1866 return output_cbranch (operands, 1, insn);
1868 [(set_attr "type" "cbranch")
1869 (set (attr "length")
1870 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1871 (const_int MAX_12BIT_OFFSET))
1873 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1874 (const_int MAX_17BIT_OFFSET))
1876 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1878 (eq (symbol_ref "flag_pic") (const_int 0))
1884 (match_operator 3 "cmpib_comparison_operator"
1885 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1886 (match_operand:DI 2 "arith5_operand" "rL")])
1887 (label_ref (match_operand 0 "" ""))
1892 return output_cbranch (operands, 0, insn);
1894 [(set_attr "type" "cbranch")
1895 (set (attr "length")
1896 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1897 (const_int MAX_12BIT_OFFSET))
1899 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1900 (const_int MAX_17BIT_OFFSET))
1902 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1904 (eq (symbol_ref "flag_pic") (const_int 0))
1908 ;; Match the negated branch.
1913 (match_operator 3 "cmpib_comparison_operator"
1914 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1915 (match_operand:DI 2 "arith5_operand" "rL")])
1917 (label_ref (match_operand 0 "" ""))))]
1921 return output_cbranch (operands, 1, insn);
1923 [(set_attr "type" "cbranch")
1924 (set (attr "length")
1925 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1926 (const_int MAX_12BIT_OFFSET))
1928 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1929 (const_int MAX_17BIT_OFFSET))
1931 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1933 (eq (symbol_ref "flag_pic") (const_int 0))
1937 ;; Branch on Bit patterns.
1941 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1943 (match_operand:SI 1 "uint5_operand" ""))
1945 (label_ref (match_operand 2 "" ""))
1950 return output_bb (operands, 0, insn, 0);
1952 [(set_attr "type" "cbranch")
1953 (set (attr "length")
1954 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1955 (const_int MAX_12BIT_OFFSET))
1957 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1958 (const_int MAX_17BIT_OFFSET))
1960 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1962 (eq (symbol_ref "flag_pic") (const_int 0))
1969 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1971 (match_operand:DI 1 "uint32_operand" ""))
1973 (label_ref (match_operand 2 "" ""))
1978 return output_bb (operands, 0, insn, 0);
1980 [(set_attr "type" "cbranch")
1981 (set (attr "length")
1982 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1983 (const_int MAX_12BIT_OFFSET))
1985 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1986 (const_int MAX_17BIT_OFFSET))
1988 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1990 (eq (symbol_ref "flag_pic") (const_int 0))
1997 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1999 (match_operand:SI 1 "uint5_operand" ""))
2002 (label_ref (match_operand 2 "" ""))))]
2006 return output_bb (operands, 1, insn, 0);
2008 [(set_attr "type" "cbranch")
2009 (set (attr "length")
2010 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2011 (const_int MAX_12BIT_OFFSET))
2013 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2014 (const_int MAX_17BIT_OFFSET))
2016 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2018 (eq (symbol_ref "flag_pic") (const_int 0))
2025 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2027 (match_operand:DI 1 "uint32_operand" ""))
2030 (label_ref (match_operand 2 "" ""))))]
2034 return output_bb (operands, 1, insn, 0);
2036 [(set_attr "type" "cbranch")
2037 (set (attr "length")
2038 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2039 (const_int MAX_12BIT_OFFSET))
2041 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2042 (const_int MAX_17BIT_OFFSET))
2044 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2046 (eq (symbol_ref "flag_pic") (const_int 0))
2053 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2055 (match_operand:SI 1 "uint5_operand" ""))
2057 (label_ref (match_operand 2 "" ""))
2062 return output_bb (operands, 0, insn, 1);
2064 [(set_attr "type" "cbranch")
2065 (set (attr "length")
2066 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2067 (const_int MAX_12BIT_OFFSET))
2069 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2070 (const_int MAX_17BIT_OFFSET))
2072 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2074 (eq (symbol_ref "flag_pic") (const_int 0))
2081 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2083 (match_operand:DI 1 "uint32_operand" ""))
2085 (label_ref (match_operand 2 "" ""))
2090 return output_bb (operands, 0, insn, 1);
2092 [(set_attr "type" "cbranch")
2093 (set (attr "length")
2094 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2095 (const_int MAX_12BIT_OFFSET))
2097 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2098 (const_int MAX_17BIT_OFFSET))
2100 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2102 (eq (symbol_ref "flag_pic") (const_int 0))
2109 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2111 (match_operand:SI 1 "uint5_operand" ""))
2114 (label_ref (match_operand 2 "" ""))))]
2118 return output_bb (operands, 1, insn, 1);
2120 [(set_attr "type" "cbranch")
2121 (set (attr "length")
2122 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2123 (const_int MAX_12BIT_OFFSET))
2125 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (const_int MAX_17BIT_OFFSET))
2128 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2130 (eq (symbol_ref "flag_pic") (const_int 0))
2137 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2139 (match_operand:DI 1 "uint32_operand" ""))
2142 (label_ref (match_operand 2 "" ""))))]
2146 return output_bb (operands, 1, insn, 1);
2148 [(set_attr "type" "cbranch")
2149 (set (attr "length")
2150 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2151 (const_int MAX_12BIT_OFFSET))
2153 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2154 (const_int MAX_17BIT_OFFSET))
2156 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2158 (eq (symbol_ref "flag_pic") (const_int 0))
2162 ;; Branch on Variable Bit patterns.
2166 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2168 (match_operand:SI 1 "register_operand" "q"))
2170 (label_ref (match_operand 2 "" ""))
2175 return output_bvb (operands, 0, insn, 0);
2177 [(set_attr "type" "cbranch")
2178 (set (attr "length")
2179 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2180 (const_int MAX_12BIT_OFFSET))
2182 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2183 (const_int MAX_17BIT_OFFSET))
2185 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2187 (eq (symbol_ref "flag_pic") (const_int 0))
2194 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2196 (match_operand:DI 1 "register_operand" "q"))
2198 (label_ref (match_operand 2 "" ""))
2203 return output_bvb (operands, 0, insn, 0);
2205 [(set_attr "type" "cbranch")
2206 (set (attr "length")
2207 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2208 (const_int MAX_12BIT_OFFSET))
2210 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2211 (const_int MAX_17BIT_OFFSET))
2213 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2215 (eq (symbol_ref "flag_pic") (const_int 0))
2222 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2224 (match_operand:SI 1 "register_operand" "q"))
2227 (label_ref (match_operand 2 "" ""))))]
2231 return output_bvb (operands, 1, insn, 0);
2233 [(set_attr "type" "cbranch")
2234 (set (attr "length")
2235 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2236 (const_int MAX_12BIT_OFFSET))
2238 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2239 (const_int MAX_17BIT_OFFSET))
2241 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2243 (eq (symbol_ref "flag_pic") (const_int 0))
2250 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2252 (match_operand:DI 1 "register_operand" "q"))
2255 (label_ref (match_operand 2 "" ""))))]
2259 return output_bvb (operands, 1, insn, 0);
2261 [(set_attr "type" "cbranch")
2262 (set (attr "length")
2263 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2264 (const_int MAX_12BIT_OFFSET))
2266 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2267 (const_int MAX_17BIT_OFFSET))
2269 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2271 (eq (symbol_ref "flag_pic") (const_int 0))
2278 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2280 (match_operand:SI 1 "register_operand" "q"))
2282 (label_ref (match_operand 2 "" ""))
2287 return output_bvb (operands, 0, insn, 1);
2289 [(set_attr "type" "cbranch")
2290 (set (attr "length")
2291 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2292 (const_int MAX_12BIT_OFFSET))
2294 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2295 (const_int MAX_17BIT_OFFSET))
2297 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2299 (eq (symbol_ref "flag_pic") (const_int 0))
2306 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2308 (match_operand:DI 1 "register_operand" "q"))
2310 (label_ref (match_operand 2 "" ""))
2315 return output_bvb (operands, 0, insn, 1);
2317 [(set_attr "type" "cbranch")
2318 (set (attr "length")
2319 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2320 (const_int MAX_12BIT_OFFSET))
2322 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2323 (const_int MAX_17BIT_OFFSET))
2325 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2327 (eq (symbol_ref "flag_pic") (const_int 0))
2334 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2336 (match_operand:SI 1 "register_operand" "q"))
2339 (label_ref (match_operand 2 "" ""))))]
2343 return output_bvb (operands, 1, insn, 1);
2345 [(set_attr "type" "cbranch")
2346 (set (attr "length")
2347 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2348 (const_int MAX_12BIT_OFFSET))
2350 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2351 (const_int MAX_17BIT_OFFSET))
2353 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2355 (eq (symbol_ref "flag_pic") (const_int 0))
2362 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2364 (match_operand:DI 1 "register_operand" "q"))
2367 (label_ref (match_operand 2 "" ""))))]
2371 return output_bvb (operands, 1, insn, 1);
2373 [(set_attr "type" "cbranch")
2374 (set (attr "length")
2375 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2376 (const_int MAX_12BIT_OFFSET))
2378 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2379 (const_int MAX_17BIT_OFFSET))
2381 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2383 (eq (symbol_ref "flag_pic") (const_int 0))
2387 ;; Floating point branches
2389 ;; ??? Nullification is handled differently from other branches.
2390 ;; If nullification is specified, the delay slot is nullified on any
2391 ;; taken branch regardless of branch direction.
2393 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2394 (label_ref (match_operand 0 "" ""))
2396 "!TARGET_SOFT_FLOAT"
2399 int length = get_attr_length (insn);
2401 int nullify, xdelay;
2404 return \"ftest\;b%* %l0\";
2406 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2410 xoperands[0] = GEN_INT (length - 8);
2416 xoperands[0] = GEN_INT (length - 4);
2420 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2422 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2423 return output_lbranch (operands[0], insn, xdelay);
2425 [(set_attr "type" "fbranch")
2426 (set (attr "length")
2427 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2428 (const_int MAX_17BIT_OFFSET))
2430 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2432 (eq (symbol_ref "flag_pic") (const_int 0))
2437 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2439 (label_ref (match_operand 0 "" ""))))]
2440 "!TARGET_SOFT_FLOAT"
2443 int length = get_attr_length (insn);
2445 int nullify, xdelay;
2448 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2450 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2454 xoperands[0] = GEN_INT (length - 4);
2460 xoperands[0] = GEN_INT (length);
2464 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2466 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2467 return output_lbranch (operands[0], insn, xdelay);
2469 [(set_attr "type" "fbranch")
2470 (set (attr "length")
2471 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2472 (const_int MAX_17BIT_OFFSET))
2474 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2476 (eq (symbol_ref "flag_pic") (const_int 0))
2480 ;; Move instructions
2482 (define_expand "movsi"
2483 [(set (match_operand:SI 0 "general_operand" "")
2484 (match_operand:SI 1 "general_operand" ""))]
2488 if (emit_move_sequence (operands, SImode, 0))
2492 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2493 (define_expand "reload_insi_r1"
2494 [(set (match_operand:SI 0 "register_operand" "=Z")
2495 (match_operand:SI 1 "non_hard_reg_operand" ""))
2496 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2500 if (emit_move_sequence (operands, SImode, operands[2]))
2503 /* We don't want the clobber emitted, so handle this ourselves. */
2504 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2508 ;; Handle SImode input reloads requiring a general register as a
2509 ;; scratch register.
2510 (define_expand "reload_insi"
2511 [(set (match_operand:SI 0 "register_operand" "=Z")
2512 (match_operand:SI 1 "non_hard_reg_operand" ""))
2513 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2517 if (emit_move_sequence (operands, SImode, operands[2]))
2520 /* We don't want the clobber emitted, so handle this ourselves. */
2521 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2525 ;; Handle SImode output reloads requiring a general register as a
2526 ;; scratch register.
2527 (define_expand "reload_outsi"
2528 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2529 (match_operand:SI 1 "register_operand" "Z"))
2530 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2534 if (emit_move_sequence (operands, SImode, operands[2]))
2537 /* We don't want the clobber emitted, so handle this ourselves. */
2538 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2543 [(set (match_operand:SI 0 "move_dest_operand"
2544 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2545 (match_operand:SI 1 "move_src_operand"
2546 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2547 "(register_operand (operands[0], SImode)
2548 || reg_or_0_operand (operands[1], SImode))
2549 && !TARGET_SOFT_FLOAT
2556 {zdepi|depwi,z} %Z1,%0
2560 {mfctl|mfctl,w} %%sar,%0
2564 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2565 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2566 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2567 (set_attr "pa_combine_type" "addmove")
2568 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2571 [(set (match_operand:SI 0 "move_dest_operand"
2572 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2573 (match_operand:SI 1 "move_src_operand"
2574 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2575 "(register_operand (operands[0], SImode)
2576 || reg_or_0_operand (operands[1], SImode))
2577 && !TARGET_SOFT_FLOAT
2584 {zdepi|depwi,z} %Z1,%0
2588 {mfctl|mfctl,w} %%sar,%0
2592 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2593 (set_attr "pa_combine_type" "addmove")
2594 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2597 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2598 (match_operand:SI 1 "register_operand" "f"))]
2600 && !TARGET_DISABLE_INDEXING
2601 && reload_completed"
2603 [(set_attr "type" "fpstore")
2604 (set_attr "pa_combine_type" "addmove")
2605 (set_attr "length" "4")])
2607 ; Rewrite RTL using an indexed store. This will allow the insn that
2608 ; computes the address to be deleted if the register it sets is dead.
2610 [(set (match_operand:SI 0 "register_operand" "")
2611 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2613 (match_operand:SI 2 "register_operand" "")))
2614 (set (mem:SI (match_dup 0))
2615 (match_operand:SI 3 "register_operand" ""))]
2617 && !TARGET_DISABLE_INDEXING
2618 && REG_OK_FOR_BASE_P (operands[2])
2619 && FP_REGNO_P (REGNO (operands[3]))"
2620 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2622 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2627 [(set (match_operand:SI 0 "register_operand" "")
2628 (plus:SI (match_operand:SI 2 "register_operand" "")
2629 (mult:SI (match_operand:SI 1 "register_operand" "")
2631 (set (mem:SI (match_dup 0))
2632 (match_operand:SI 3 "register_operand" ""))]
2634 && !TARGET_DISABLE_INDEXING
2635 && REG_OK_FOR_BASE_P (operands[2])
2636 && FP_REGNO_P (REGNO (operands[3]))"
2637 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2639 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2644 [(set (match_operand:DI 0 "register_operand" "")
2645 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2647 (match_operand:DI 2 "register_operand" "")))
2648 (set (mem:SI (match_dup 0))
2649 (match_operand:SI 3 "register_operand" ""))]
2651 && !TARGET_DISABLE_INDEXING
2653 && REG_OK_FOR_BASE_P (operands[2])
2654 && FP_REGNO_P (REGNO (operands[3]))"
2655 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2657 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2662 [(set (match_operand:DI 0 "register_operand" "")
2663 (plus:DI (match_operand:DI 2 "register_operand" "")
2664 (mult:DI (match_operand:DI 1 "register_operand" "")
2666 (set (mem:SI (match_dup 0))
2667 (match_operand:SI 3 "register_operand" ""))]
2669 && !TARGET_DISABLE_INDEXING
2671 && REG_OK_FOR_BASE_P (operands[2])
2672 && FP_REGNO_P (REGNO (operands[3]))"
2673 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2675 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2680 [(set (match_operand:SI 0 "register_operand" "")
2681 (plus:SI (match_operand:SI 1 "register_operand" "")
2682 (match_operand:SI 2 "register_operand" "")))
2683 (set (mem:SI (match_dup 0))
2684 (match_operand:SI 3 "register_operand" ""))]
2686 && !TARGET_DISABLE_INDEXING
2687 && TARGET_NO_SPACE_REGS
2688 && REG_OK_FOR_INDEX_P (operands[1])
2689 && REG_OK_FOR_BASE_P (operands[2])
2690 && FP_REGNO_P (REGNO (operands[3]))"
2691 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2693 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2697 [(set (match_operand:SI 0 "register_operand" "")
2698 (plus:SI (match_operand:SI 1 "register_operand" "")
2699 (match_operand:SI 2 "register_operand" "")))
2700 (set (mem:SI (match_dup 0))
2701 (match_operand:SI 3 "register_operand" ""))]
2703 && !TARGET_DISABLE_INDEXING
2704 && TARGET_NO_SPACE_REGS
2705 && REG_OK_FOR_BASE_P (operands[1])
2706 && REG_OK_FOR_INDEX_P (operands[2])
2707 && FP_REGNO_P (REGNO (operands[3]))"
2708 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2710 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2714 [(set (match_operand:DI 0 "register_operand" "")
2715 (plus:DI (match_operand:DI 1 "register_operand" "")
2716 (match_operand:DI 2 "register_operand" "")))
2717 (set (mem:SI (match_dup 0))
2718 (match_operand:SI 3 "register_operand" ""))]
2720 && !TARGET_DISABLE_INDEXING
2722 && TARGET_NO_SPACE_REGS
2723 && REG_OK_FOR_INDEX_P (operands[1])
2724 && REG_OK_FOR_BASE_P (operands[2])
2725 && FP_REGNO_P (REGNO (operands[3]))"
2726 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2728 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2732 [(set (match_operand:DI 0 "register_operand" "")
2733 (plus:DI (match_operand:DI 1 "register_operand" "")
2734 (match_operand:DI 2 "register_operand" "")))
2735 (set (mem:SI (match_dup 0))
2736 (match_operand:SI 3 "register_operand" ""))]
2738 && !TARGET_DISABLE_INDEXING
2740 && TARGET_NO_SPACE_REGS
2741 && REG_OK_FOR_BASE_P (operands[1])
2742 && REG_OK_FOR_INDEX_P (operands[2])
2743 && FP_REGNO_P (REGNO (operands[3]))"
2744 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2746 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2750 [(set (match_operand:SI 0 "move_dest_operand"
2751 "=r,r,r,r,r,r,Q,!*q,!r")
2752 (match_operand:SI 1 "move_src_operand"
2753 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2754 "(register_operand (operands[0], SImode)
2755 || reg_or_0_operand (operands[1], SImode))
2756 && TARGET_SOFT_FLOAT"
2762 {zdepi|depwi,z} %Z1,%0
2766 {mfctl|mfctl,w} %%sar,%0"
2767 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2768 (set_attr "pa_combine_type" "addmove")
2769 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2771 ;; Load or store with base-register modification.
2773 [(set (match_operand:SI 0 "register_operand" "=r")
2774 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2775 (match_operand:DI 2 "int5_operand" "L"))))
2777 (plus:DI (match_dup 1) (match_dup 2)))]
2780 [(set_attr "type" "load")
2781 (set_attr "length" "4")])
2783 ; And a zero extended variant.
2785 [(set (match_operand:DI 0 "register_operand" "=r")
2786 (zero_extend:DI (mem:SI
2788 (match_operand:DI 1 "register_operand" "+r")
2789 (match_operand:DI 2 "int5_operand" "L")))))
2791 (plus:DI (match_dup 1) (match_dup 2)))]
2794 [(set_attr "type" "load")
2795 (set_attr "length" "4")])
2797 (define_expand "pre_load"
2798 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2799 (mem (plus (match_operand 1 "register_operand" "")
2800 (match_operand 2 "pre_cint_operand" ""))))
2802 (plus (match_dup 1) (match_dup 2)))])]
2808 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2811 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2815 (define_insn "pre_ldw"
2816 [(set (match_operand:SI 0 "register_operand" "=r")
2817 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2818 (match_operand:SI 2 "pre_cint_operand" ""))))
2820 (plus:SI (match_dup 1) (match_dup 2)))]
2824 if (INTVAL (operands[2]) < 0)
2825 return \"{ldwm|ldw,mb} %2(%1),%0\";
2826 return \"{ldws|ldw},mb %2(%1),%0\";
2828 [(set_attr "type" "load")
2829 (set_attr "length" "4")])
2831 (define_insn "pre_ldd"
2832 [(set (match_operand:DI 0 "register_operand" "=r")
2833 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2834 (match_operand:DI 2 "pre_cint_operand" ""))))
2836 (plus:DI (match_dup 1) (match_dup 2)))]
2839 [(set_attr "type" "load")
2840 (set_attr "length" "4")])
2843 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2844 (match_operand:SI 1 "pre_cint_operand" "")))
2845 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2847 (plus:SI (match_dup 0) (match_dup 1)))]
2851 if (INTVAL (operands[1]) < 0)
2852 return \"{stwm|stw,mb} %r2,%1(%0)\";
2853 return \"{stws|stw},mb %r2,%1(%0)\";
2855 [(set_attr "type" "store")
2856 (set_attr "length" "4")])
2859 [(set (match_operand:SI 0 "register_operand" "=r")
2860 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2862 (plus:SI (match_dup 1)
2863 (match_operand:SI 2 "post_cint_operand" "")))]
2867 if (INTVAL (operands[2]) > 0)
2868 return \"{ldwm|ldw,ma} %2(%1),%0\";
2869 return \"{ldws|ldw},ma %2(%1),%0\";
2871 [(set_attr "type" "load")
2872 (set_attr "length" "4")])
2874 (define_expand "post_store"
2875 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2876 (match_operand 1 "reg_or_0_operand" ""))
2879 (match_operand 2 "post_cint_operand" "")))])]
2885 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2888 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2892 (define_insn "post_stw"
2893 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2894 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2896 (plus:SI (match_dup 0)
2897 (match_operand:SI 2 "post_cint_operand" "")))]
2901 if (INTVAL (operands[2]) > 0)
2902 return \"{stwm|stw,ma} %r1,%2(%0)\";
2903 return \"{stws|stw},ma %r1,%2(%0)\";
2905 [(set_attr "type" "store")
2906 (set_attr "length" "4")])
2908 (define_insn "post_std"
2909 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2910 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2912 (plus:DI (match_dup 0)
2913 (match_operand:DI 2 "post_cint_operand" "")))]
2916 [(set_attr "type" "store")
2917 (set_attr "length" "4")])
2919 ;; For loading the address of a label while generating PIC code.
2920 ;; Note since this pattern can be created at reload time (via movsi), all
2921 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2923 [(set (match_operand 0 "pmode_register_operand" "=a")
2924 (match_operand 1 "pic_label_operand" ""))]
2930 xoperands[0] = operands[0];
2931 xoperands[1] = operands[1];
2932 xoperands[2] = gen_label_rtx ();
2934 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2935 CODE_LABEL_NUMBER (xoperands[2]));
2936 output_asm_insn (\"mfia %0\", xoperands);
2938 /* If we're trying to load the address of a label that happens to be
2939 close, then we can use a shorter sequence. */
2940 if (GET_CODE (operands[1]) == LABEL_REF
2941 && !LABEL_REF_NONLOCAL_P (operands[1])
2942 && INSN_ADDRESSES_SET_P ()
2943 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2944 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2945 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2948 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2949 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2953 [(set_attr "type" "multi")
2954 (set_attr "length" "12")]) ; 8 or 12
2957 [(set (match_operand 0 "pmode_register_operand" "=a")
2958 (match_operand 1 "pic_label_operand" ""))]
2964 xoperands[0] = operands[0];
2965 xoperands[1] = operands[1];
2966 xoperands[2] = gen_label_rtx ();
2968 output_asm_insn (\"bl .+8,%0\", xoperands);
2969 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2970 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2971 CODE_LABEL_NUMBER (xoperands[2]));
2973 /* If we're trying to load the address of a label that happens to be
2974 close, then we can use a shorter sequence. */
2975 if (GET_CODE (operands[1]) == LABEL_REF
2976 && !LABEL_REF_NONLOCAL_P (operands[1])
2977 && INSN_ADDRESSES_SET_P ()
2978 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2979 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2980 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2983 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2984 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2988 [(set_attr "type" "multi")
2989 (set_attr "length" "16")]) ; 12 or 16
2992 [(set (match_operand:SI 0 "register_operand" "=a")
2993 (plus:SI (match_operand:SI 1 "register_operand" "r")
2994 (high:SI (match_operand 2 "" ""))))]
2995 "symbolic_operand (operands[2], Pmode)
2996 && ! function_label_operand (operands[2], Pmode)
2999 [(set_attr "type" "binary")
3000 (set_attr "length" "4")])
3003 [(set (match_operand:DI 0 "register_operand" "=a")
3004 (plus:DI (match_operand:DI 1 "register_operand" "r")
3005 (high:DI (match_operand 2 "" ""))))]
3006 "symbolic_operand (operands[2], Pmode)
3007 && ! function_label_operand (operands[2], Pmode)
3011 [(set_attr "type" "binary")
3012 (set_attr "length" "4")])
3014 ;; Always use addil rather than ldil;add sequences. This allows the
3015 ;; HP linker to eliminate the dp relocation if the symbolic operand
3016 ;; lives in the TEXT space.
3018 [(set (match_operand:SI 0 "register_operand" "=a")
3019 (high:SI (match_operand 1 "" "")))]
3020 "symbolic_operand (operands[1], Pmode)
3021 && ! function_label_operand (operands[1], Pmode)
3022 && ! read_only_operand (operands[1], Pmode)
3026 if (TARGET_LONG_LOAD_STORE)
3027 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
3029 return \"addil LR'%H1,%%r27\";
3031 [(set_attr "type" "binary")
3032 (set (attr "length")
3033 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
3038 ;; This is for use in the prologue/epilogue code. We need it
3039 ;; to add large constants to a stack pointer or frame pointer.
3040 ;; Because of the additional %r1 pressure, we probably do not
3041 ;; want to use this in general code, so make it available
3042 ;; only after reload.
3044 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
3045 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
3046 (high:SI (match_operand 2 "const_int_operand" ""))))]
3050 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3051 [(set_attr "type" "binary,binary")
3052 (set_attr "length" "4,8")])
3055 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
3056 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
3057 (high:DI (match_operand 2 "const_int_operand" ""))))]
3058 "reload_completed && TARGET_64BIT"
3061 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3062 [(set_attr "type" "binary,binary")
3063 (set_attr "length" "4,8")])
3066 [(set (match_operand:SI 0 "register_operand" "=r")
3067 (high:SI (match_operand 1 "" "")))]
3068 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
3069 && !is_function_label_plus_const (operands[1])"
3072 if (symbolic_operand (operands[1], Pmode))
3073 return \"ldil LR'%H1,%0\";
3075 return \"ldil L'%G1,%0\";
3077 [(set_attr "type" "move")
3078 (set_attr "length" "4")])
3081 [(set (match_operand:DI 0 "register_operand" "=r")
3082 (high:DI (match_operand 1 "const_int_operand" "")))]
3085 [(set_attr "type" "move")
3086 (set_attr "length" "4")])
3089 [(set (match_operand:DI 0 "register_operand" "=r")
3090 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3091 (match_operand:DI 2 "const_int_operand" "i")))]
3094 [(set_attr "type" "move")
3095 (set_attr "length" "4")])
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3100 (match_operand:SI 2 "immediate_operand" "i")))]
3101 "!is_function_label_plus_const (operands[2])"
3104 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
3106 if (symbolic_operand (operands[2], Pmode))
3107 return \"ldo RR'%G2(%1),%0\";
3109 return \"ldo R'%G2(%1),%0\";
3111 [(set_attr "type" "move")
3112 (set_attr "length" "4")])
3114 ;; Now that a symbolic_address plus a constant is broken up early
3115 ;; in the compilation phase (for better CSE) we need a special
3116 ;; combiner pattern to load the symbolic address plus the constant
3117 ;; in only 2 instructions. (For cases where the symbolic address
3118 ;; was not a common subexpression.)
3120 [(set (match_operand:SI 0 "register_operand" "")
3121 (match_operand:SI 1 "symbolic_operand" ""))
3122 (clobber (match_operand:SI 2 "register_operand" ""))]
3123 "! (flag_pic && pic_label_operand (operands[1], SImode))"
3124 [(set (match_dup 2) (high:SI (match_dup 1)))
3125 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
3128 ;; hppa_legitimize_address goes to a great deal of trouble to
3129 ;; create addresses which use indexing. In some cases, this
3130 ;; is a lose because there isn't any store instructions which
3131 ;; allow indexed addresses (with integer register source).
3133 ;; These define_splits try to turn a 3 insn store into
3134 ;; a 2 insn store with some creative RTL rewriting.
3136 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3137 (match_operand:SI 1 "shadd_operand" ""))
3138 (plus:SI (match_operand:SI 2 "register_operand" "")
3139 (match_operand:SI 3 "const_int_operand" ""))))
3140 (match_operand:SI 4 "register_operand" ""))
3141 (clobber (match_operand:SI 5 "register_operand" ""))]
3143 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3145 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3149 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3150 (match_operand:SI 1 "shadd_operand" ""))
3151 (plus:SI (match_operand:SI 2 "register_operand" "")
3152 (match_operand:SI 3 "const_int_operand" ""))))
3153 (match_operand:HI 4 "register_operand" ""))
3154 (clobber (match_operand:SI 5 "register_operand" ""))]
3156 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3158 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3162 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3163 (match_operand:SI 1 "shadd_operand" ""))
3164 (plus:SI (match_operand:SI 2 "register_operand" "")
3165 (match_operand:SI 3 "const_int_operand" ""))))
3166 (match_operand:QI 4 "register_operand" ""))
3167 (clobber (match_operand:SI 5 "register_operand" ""))]
3169 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3171 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3174 (define_expand "movhi"
3175 [(set (match_operand:HI 0 "general_operand" "")
3176 (match_operand:HI 1 "general_operand" ""))]
3180 if (emit_move_sequence (operands, HImode, 0))
3185 [(set (match_operand:HI 0 "move_dest_operand"
3186 "=r,r,r,r,r,Q,!*q,!r")
3187 (match_operand:HI 1 "move_src_operand"
3188 "r,J,N,K,RQ,rM,!rM,!*q"))]
3189 "(register_operand (operands[0], HImode)
3190 || reg_or_0_operand (operands[1], HImode))"
3195 {zdepi|depwi,z} %Z1,%0
3199 {mfctl|mfctl,w} %sar,%0"
3200 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3201 (set_attr "pa_combine_type" "addmove")
3202 (set_attr "length" "4,4,4,4,4,4,4,4")])
3205 [(set (match_operand:HI 0 "register_operand" "=r")
3206 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3207 (match_operand:SI 2 "int5_operand" "L"))))
3209 (plus:SI (match_dup 1) (match_dup 2)))]
3211 "{ldhs|ldh},mb %2(%1),%0"
3212 [(set_attr "type" "load")
3213 (set_attr "length" "4")])
3216 [(set (match_operand:HI 0 "register_operand" "=r")
3217 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3218 (match_operand:DI 2 "int5_operand" "L"))))
3220 (plus:DI (match_dup 1) (match_dup 2)))]
3223 [(set_attr "type" "load")
3224 (set_attr "length" "4")])
3226 ; And a zero extended variant.
3228 [(set (match_operand:DI 0 "register_operand" "=r")
3229 (zero_extend:DI (mem:HI
3231 (match_operand:DI 1 "register_operand" "+r")
3232 (match_operand:DI 2 "int5_operand" "L")))))
3234 (plus:DI (match_dup 1) (match_dup 2)))]
3237 [(set_attr "type" "load")
3238 (set_attr "length" "4")])
3241 [(set (match_operand:SI 0 "register_operand" "=r")
3242 (zero_extend:SI (mem:HI
3244 (match_operand:SI 1 "register_operand" "+r")
3245 (match_operand:SI 2 "int5_operand" "L")))))
3247 (plus:SI (match_dup 1) (match_dup 2)))]
3249 "{ldhs|ldh},mb %2(%1),%0"
3250 [(set_attr "type" "load")
3251 (set_attr "length" "4")])
3254 [(set (match_operand:SI 0 "register_operand" "=r")
3255 (zero_extend:SI (mem:HI
3257 (match_operand:DI 1 "register_operand" "+r")
3258 (match_operand:DI 2 "int5_operand" "L")))))
3260 (plus:DI (match_dup 1) (match_dup 2)))]
3263 [(set_attr "type" "load")
3264 (set_attr "length" "4")])
3267 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3268 (match_operand:SI 1 "int5_operand" "L")))
3269 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3271 (plus:SI (match_dup 0) (match_dup 1)))]
3273 "{sths|sth},mb %r2,%1(%0)"
3274 [(set_attr "type" "store")
3275 (set_attr "length" "4")])
3278 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3279 (match_operand:DI 1 "int5_operand" "L")))
3280 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3282 (plus:DI (match_dup 0) (match_dup 1)))]
3285 [(set_attr "type" "store")
3286 (set_attr "length" "4")])
3289 [(set (match_operand:HI 0 "register_operand" "=r")
3290 (plus:HI (match_operand:HI 1 "register_operand" "r")
3291 (match_operand 2 "const_int_operand" "J")))]
3294 [(set_attr "type" "binary")
3295 (set_attr "pa_combine_type" "addmove")
3296 (set_attr "length" "4")])
3298 (define_expand "movqi"
3299 [(set (match_operand:QI 0 "general_operand" "")
3300 (match_operand:QI 1 "general_operand" ""))]
3304 if (emit_move_sequence (operands, QImode, 0))
3309 [(set (match_operand:QI 0 "move_dest_operand"
3310 "=r,r,r,r,r,Q,!*q,!r")
3311 (match_operand:QI 1 "move_src_operand"
3312 "r,J,N,K,RQ,rM,!rM,!*q"))]
3313 "(register_operand (operands[0], QImode)
3314 || reg_or_0_operand (operands[1], QImode))"
3319 {zdepi|depwi,z} %Z1,%0
3323 {mfctl|mfctl,w} %%sar,%0"
3324 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3325 (set_attr "pa_combine_type" "addmove")
3326 (set_attr "length" "4,4,4,4,4,4,4,4")])
3329 [(set (match_operand:QI 0 "register_operand" "=r")
3330 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3331 (match_operand:SI 2 "int5_operand" "L"))))
3332 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3334 "{ldbs|ldb},mb %2(%1),%0"
3335 [(set_attr "type" "load")
3336 (set_attr "length" "4")])
3339 [(set (match_operand:QI 0 "register_operand" "=r")
3340 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3341 (match_operand:DI 2 "int5_operand" "L"))))
3342 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3345 [(set_attr "type" "load")
3346 (set_attr "length" "4")])
3348 ; Now the same thing with zero extensions.
3350 [(set (match_operand:DI 0 "register_operand" "=r")
3351 (zero_extend:DI (mem:QI (plus:DI
3352 (match_operand:DI 1 "register_operand" "+r")
3353 (match_operand:DI 2 "int5_operand" "L")))))
3354 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3357 [(set_attr "type" "load")
3358 (set_attr "length" "4")])
3361 [(set (match_operand:SI 0 "register_operand" "=r")
3362 (zero_extend:SI (mem:QI (plus:SI
3363 (match_operand:SI 1 "register_operand" "+r")
3364 (match_operand:SI 2 "int5_operand" "L")))))
3365 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3367 "{ldbs|ldb},mb %2(%1),%0"
3368 [(set_attr "type" "load")
3369 (set_attr "length" "4")])
3372 [(set (match_operand:SI 0 "register_operand" "=r")
3373 (zero_extend:SI (mem:QI (plus:DI
3374 (match_operand:DI 1 "register_operand" "+r")
3375 (match_operand:DI 2 "int5_operand" "L")))))
3376 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3379 [(set_attr "type" "load")
3380 (set_attr "length" "4")])
3383 [(set (match_operand:HI 0 "register_operand" "=r")
3384 (zero_extend:HI (mem:QI (plus:SI
3385 (match_operand:SI 1 "register_operand" "+r")
3386 (match_operand:SI 2 "int5_operand" "L")))))
3387 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3389 "{ldbs|ldb},mb %2(%1),%0"
3390 [(set_attr "type" "load")
3391 (set_attr "length" "4")])
3394 [(set (match_operand:HI 0 "register_operand" "=r")
3395 (zero_extend:HI (mem:QI (plus:DI
3396 (match_operand:DI 1 "register_operand" "+r")
3397 (match_operand:DI 2 "int5_operand" "L")))))
3398 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3401 [(set_attr "type" "load")
3402 (set_attr "length" "4")])
3405 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3406 (match_operand:SI 1 "int5_operand" "L")))
3407 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3409 (plus:SI (match_dup 0) (match_dup 1)))]
3411 "{stbs|stb},mb %r2,%1(%0)"
3412 [(set_attr "type" "store")
3413 (set_attr "length" "4")])
3416 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3417 (match_operand:DI 1 "int5_operand" "L")))
3418 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3420 (plus:DI (match_dup 0) (match_dup 1)))]
3423 [(set_attr "type" "store")
3424 (set_attr "length" "4")])
3426 ;; The definition of this insn does not really explain what it does,
3427 ;; but it should suffice that anything generated as this insn will be
3428 ;; recognized as a movmemsi operation, and that it will not successfully
3429 ;; combine with anything.
3430 (define_expand "movmemsi"
3431 [(parallel [(set (match_operand:BLK 0 "" "")
3432 (match_operand:BLK 1 "" ""))
3433 (clobber (match_dup 4))
3434 (clobber (match_dup 5))
3435 (clobber (match_dup 6))
3436 (clobber (match_dup 7))
3437 (clobber (match_dup 8))
3438 (use (match_operand:SI 2 "arith_operand" ""))
3439 (use (match_operand:SI 3 "const_int_operand" ""))])]
3440 "!TARGET_64BIT && optimize > 0"
3445 /* HP provides very fast block move library routine for the PA;
3446 this routine includes:
3448 4x4 byte at a time block moves,
3449 1x4 byte at a time with alignment checked at runtime with
3450 attempts to align the source and destination as needed
3453 With that in mind, here's the heuristics to try and guess when
3454 the inlined block move will be better than the library block
3457 If the size isn't constant, then always use the library routines.
3459 If the size is large in respect to the known alignment, then use
3460 the library routines.
3462 If the size is small in respect to the known alignment, then open
3463 code the copy (since that will lead to better scheduling).
3465 Else use the block move pattern. */
3467 /* Undetermined size, use the library routine. */
3468 if (GET_CODE (operands[2]) != CONST_INT)
3471 size = INTVAL (operands[2]);
3472 align = INTVAL (operands[3]);
3473 align = align > 4 ? 4 : align;
3475 /* If size/alignment is large, then use the library routines. */
3476 if (size / align > 16)
3479 /* This does happen, but not often enough to worry much about. */
3480 if (size / align < MOVE_RATIO)
3483 /* Fall through means we're going to use our block move pattern. */
3485 = replace_equiv_address (operands[0],
3486 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3488 = replace_equiv_address (operands[1],
3489 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3490 operands[4] = gen_reg_rtx (SImode);
3491 operands[5] = gen_reg_rtx (SImode);
3492 operands[6] = gen_reg_rtx (SImode);
3493 operands[7] = gen_reg_rtx (SImode);
3494 operands[8] = gen_reg_rtx (SImode);
3497 ;; The operand constraints are written like this to support both compile-time
3498 ;; and run-time determined byte counts. The expander and output_block_move
3499 ;; only support compile-time determined counts at this time.
3501 ;; If the count is run-time determined, the register with the byte count
3502 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3504 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3505 ;; broke this semantic for pseudo registers. We can't use match_scratch
3506 ;; as this requires two registers in the class R1_REGS when the MEMs for
3507 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3508 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3509 ;; respectively. We then split or peephole optimize after reload.
3510 (define_insn "movmemsi_prereload"
3511 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3512 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3513 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3514 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3515 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3516 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3517 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3518 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3519 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3522 [(set_attr "type" "multi,multi")])
3525 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3526 (match_operand:BLK 1 "memory_operand" ""))
3527 (clobber (match_operand:SI 2 "register_operand" ""))
3528 (clobber (match_operand:SI 3 "register_operand" ""))
3529 (clobber (match_operand:SI 6 "register_operand" ""))
3530 (clobber (match_operand:SI 7 "register_operand" ""))
3531 (clobber (match_operand:SI 8 "register_operand" ""))
3532 (use (match_operand:SI 4 "arith_operand" ""))
3533 (use (match_operand:SI 5 "const_int_operand" ""))])]
3534 "!TARGET_64BIT && reload_completed && !flag_peephole2
3535 && GET_CODE (operands[0]) == MEM
3536 && register_operand (XEXP (operands[0], 0), SImode)
3537 && GET_CODE (operands[1]) == MEM
3538 && register_operand (XEXP (operands[1], 0), SImode)"
3539 [(set (match_dup 7) (match_dup 9))
3540 (set (match_dup 8) (match_dup 10))
3541 (parallel [(set (match_dup 0) (match_dup 1))
3542 (clobber (match_dup 2))
3543 (clobber (match_dup 3))
3544 (clobber (match_dup 6))
3545 (clobber (match_dup 7))
3546 (clobber (match_dup 8))
3552 operands[9] = XEXP (operands[0], 0);
3553 operands[10] = XEXP (operands[1], 0);
3554 operands[0] = replace_equiv_address (operands[0], operands[7]);
3555 operands[1] = replace_equiv_address (operands[1], operands[8]);
3559 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3560 (match_operand:BLK 1 "memory_operand" ""))
3561 (clobber (match_operand:SI 2 "register_operand" ""))
3562 (clobber (match_operand:SI 3 "register_operand" ""))
3563 (clobber (match_operand:SI 6 "register_operand" ""))
3564 (clobber (match_operand:SI 7 "register_operand" ""))
3565 (clobber (match_operand:SI 8 "register_operand" ""))
3566 (use (match_operand:SI 4 "arith_operand" ""))
3567 (use (match_operand:SI 5 "const_int_operand" ""))])]
3569 && GET_CODE (operands[0]) == MEM
3570 && register_operand (XEXP (operands[0], 0), SImode)
3571 && GET_CODE (operands[1]) == MEM
3572 && register_operand (XEXP (operands[1], 0), SImode)"
3573 [(parallel [(set (match_dup 0) (match_dup 1))
3574 (clobber (match_dup 2))
3575 (clobber (match_dup 3))
3576 (clobber (match_dup 6))
3577 (clobber (match_dup 7))
3578 (clobber (match_dup 8))
3584 rtx addr = XEXP (operands[0], 0);
3585 if (dead_or_set_p (curr_insn, addr))
3589 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3590 operands[0] = replace_equiv_address (operands[0], operands[7]);
3593 addr = XEXP (operands[1], 0);
3594 if (dead_or_set_p (curr_insn, addr))
3598 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3599 operands[1] = replace_equiv_address (operands[1], operands[8]);
3603 (define_insn "movmemsi_postreload"
3604 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3605 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3606 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3607 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3608 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3609 (clobber (match_dup 0))
3610 (clobber (match_dup 1))
3611 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3612 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3614 "!TARGET_64BIT && reload_completed"
3615 "* return output_block_move (operands, !which_alternative);"
3616 [(set_attr "type" "multi,multi")])
3618 (define_expand "movmemdi"
3619 [(parallel [(set (match_operand:BLK 0 "" "")
3620 (match_operand:BLK 1 "" ""))
3621 (clobber (match_dup 4))
3622 (clobber (match_dup 5))
3623 (clobber (match_dup 6))
3624 (clobber (match_dup 7))
3625 (clobber (match_dup 8))
3626 (use (match_operand:DI 2 "arith_operand" ""))
3627 (use (match_operand:DI 3 "const_int_operand" ""))])]
3628 "TARGET_64BIT && optimize > 0"
3633 /* HP provides very fast block move library routine for the PA;
3634 this routine includes:
3636 4x4 byte at a time block moves,
3637 1x4 byte at a time with alignment checked at runtime with
3638 attempts to align the source and destination as needed
3641 With that in mind, here's the heuristics to try and guess when
3642 the inlined block move will be better than the library block
3645 If the size isn't constant, then always use the library routines.
3647 If the size is large in respect to the known alignment, then use
3648 the library routines.
3650 If the size is small in respect to the known alignment, then open
3651 code the copy (since that will lead to better scheduling).
3653 Else use the block move pattern. */
3655 /* Undetermined size, use the library routine. */
3656 if (GET_CODE (operands[2]) != CONST_INT)
3659 size = INTVAL (operands[2]);
3660 align = INTVAL (operands[3]);
3661 align = align > 8 ? 8 : align;
3663 /* If size/alignment is large, then use the library routines. */
3664 if (size / align > 16)
3667 /* This does happen, but not often enough to worry much about. */
3668 if (size / align < MOVE_RATIO)
3671 /* Fall through means we're going to use our block move pattern. */
3673 = replace_equiv_address (operands[0],
3674 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3676 = replace_equiv_address (operands[1],
3677 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3678 operands[4] = gen_reg_rtx (DImode);
3679 operands[5] = gen_reg_rtx (DImode);
3680 operands[6] = gen_reg_rtx (DImode);
3681 operands[7] = gen_reg_rtx (DImode);
3682 operands[8] = gen_reg_rtx (DImode);
3685 ;; The operand constraints are written like this to support both compile-time
3686 ;; and run-time determined byte counts. The expander and output_block_move
3687 ;; only support compile-time determined counts at this time.
3689 ;; If the count is run-time determined, the register with the byte count
3690 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3692 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3693 ;; broke this semantic for pseudo registers. We can't use match_scratch
3694 ;; as this requires two registers in the class R1_REGS when the MEMs for
3695 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3696 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3697 ;; respectively. We then split or peephole optimize after reload.
3698 (define_insn "movmemdi_prereload"
3699 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3700 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3701 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3702 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3703 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3704 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3705 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3706 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3707 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3710 [(set_attr "type" "multi,multi")])
3713 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3714 (match_operand:BLK 1 "memory_operand" ""))
3715 (clobber (match_operand:DI 2 "register_operand" ""))
3716 (clobber (match_operand:DI 3 "register_operand" ""))
3717 (clobber (match_operand:DI 6 "register_operand" ""))
3718 (clobber (match_operand:DI 7 "register_operand" ""))
3719 (clobber (match_operand:DI 8 "register_operand" ""))
3720 (use (match_operand:DI 4 "arith_operand" ""))
3721 (use (match_operand:DI 5 "const_int_operand" ""))])]
3722 "TARGET_64BIT && reload_completed && !flag_peephole2
3723 && GET_CODE (operands[0]) == MEM
3724 && register_operand (XEXP (operands[0], 0), DImode)
3725 && GET_CODE (operands[1]) == MEM
3726 && register_operand (XEXP (operands[1], 0), DImode)"
3727 [(set (match_dup 7) (match_dup 9))
3728 (set (match_dup 8) (match_dup 10))
3729 (parallel [(set (match_dup 0) (match_dup 1))
3730 (clobber (match_dup 2))
3731 (clobber (match_dup 3))
3732 (clobber (match_dup 6))
3733 (clobber (match_dup 7))
3734 (clobber (match_dup 8))
3740 operands[9] = XEXP (operands[0], 0);
3741 operands[10] = XEXP (operands[1], 0);
3742 operands[0] = replace_equiv_address (operands[0], operands[7]);
3743 operands[1] = replace_equiv_address (operands[1], operands[8]);
3747 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3748 (match_operand:BLK 1 "memory_operand" ""))
3749 (clobber (match_operand:DI 2 "register_operand" ""))
3750 (clobber (match_operand:DI 3 "register_operand" ""))
3751 (clobber (match_operand:DI 6 "register_operand" ""))
3752 (clobber (match_operand:DI 7 "register_operand" ""))
3753 (clobber (match_operand:DI 8 "register_operand" ""))
3754 (use (match_operand:DI 4 "arith_operand" ""))
3755 (use (match_operand:DI 5 "const_int_operand" ""))])]
3757 && GET_CODE (operands[0]) == MEM
3758 && register_operand (XEXP (operands[0], 0), DImode)
3759 && GET_CODE (operands[1]) == MEM
3760 && register_operand (XEXP (operands[1], 0), DImode)"
3761 [(parallel [(set (match_dup 0) (match_dup 1))
3762 (clobber (match_dup 2))
3763 (clobber (match_dup 3))
3764 (clobber (match_dup 6))
3765 (clobber (match_dup 7))
3766 (clobber (match_dup 8))
3772 rtx addr = XEXP (operands[0], 0);
3773 if (dead_or_set_p (curr_insn, addr))
3777 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3778 operands[0] = replace_equiv_address (operands[0], operands[7]);
3781 addr = XEXP (operands[1], 0);
3782 if (dead_or_set_p (curr_insn, addr))
3786 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3787 operands[1] = replace_equiv_address (operands[1], operands[8]);
3791 (define_insn "movmemdi_postreload"
3792 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3793 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3794 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3795 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3796 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3797 (clobber (match_dup 0))
3798 (clobber (match_dup 1))
3799 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3800 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3802 "TARGET_64BIT && reload_completed"
3803 "* return output_block_move (operands, !which_alternative);"
3804 [(set_attr "type" "multi,multi")])
3806 (define_expand "setmemsi"
3807 [(parallel [(set (match_operand:BLK 0 "" "")
3808 (match_operand 2 "const_int_operand" ""))
3809 (clobber (match_dup 4))
3810 (clobber (match_dup 5))
3811 (use (match_operand:SI 1 "arith_operand" ""))
3812 (use (match_operand:SI 3 "const_int_operand" ""))])]
3813 "!TARGET_64BIT && optimize > 0"
3818 /* If value to set is not zero, use the library routine. */
3819 if (operands[2] != const0_rtx)
3822 /* Undetermined size, use the library routine. */
3823 if (GET_CODE (operands[1]) != CONST_INT)
3826 size = INTVAL (operands[1]);
3827 align = INTVAL (operands[3]);
3828 align = align > 4 ? 4 : align;
3830 /* If size/alignment is large, then use the library routines. */
3831 if (size / align > 16)
3834 /* This does happen, but not often enough to worry much about. */
3835 if (size / align < MOVE_RATIO)
3838 /* Fall through means we're going to use our block clear pattern. */
3840 = replace_equiv_address (operands[0],
3841 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3842 operands[4] = gen_reg_rtx (SImode);
3843 operands[5] = gen_reg_rtx (SImode);
3846 (define_insn "clrmemsi_prereload"
3847 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3849 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3850 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3851 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3852 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3855 [(set_attr "type" "multi,multi")])
3858 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3860 (clobber (match_operand:SI 1 "register_operand" ""))
3861 (clobber (match_operand:SI 4 "register_operand" ""))
3862 (use (match_operand:SI 2 "arith_operand" ""))
3863 (use (match_operand:SI 3 "const_int_operand" ""))])]
3864 "!TARGET_64BIT && reload_completed && !flag_peephole2
3865 && GET_CODE (operands[0]) == MEM
3866 && register_operand (XEXP (operands[0], 0), SImode)"
3867 [(set (match_dup 4) (match_dup 5))
3868 (parallel [(set (match_dup 0) (const_int 0))
3869 (clobber (match_dup 1))
3870 (clobber (match_dup 4))
3876 operands[5] = XEXP (operands[0], 0);
3877 operands[0] = replace_equiv_address (operands[0], operands[4]);
3881 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3883 (clobber (match_operand:SI 1 "register_operand" ""))
3884 (clobber (match_operand:SI 4 "register_operand" ""))
3885 (use (match_operand:SI 2 "arith_operand" ""))
3886 (use (match_operand:SI 3 "const_int_operand" ""))])]
3888 && GET_CODE (operands[0]) == MEM
3889 && register_operand (XEXP (operands[0], 0), SImode)"
3890 [(parallel [(set (match_dup 0) (const_int 0))
3891 (clobber (match_dup 1))
3892 (clobber (match_dup 4))
3898 rtx addr = XEXP (operands[0], 0);
3899 if (dead_or_set_p (curr_insn, addr))
3903 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3904 operands[0] = replace_equiv_address (operands[0], operands[4]);
3908 (define_insn "clrmemsi_postreload"
3909 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3911 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3912 (clobber (match_dup 0))
3913 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3914 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3916 "!TARGET_64BIT && reload_completed"
3917 "* return output_block_clear (operands, !which_alternative);"
3918 [(set_attr "type" "multi,multi")])
3920 (define_expand "setmemdi"
3921 [(parallel [(set (match_operand:BLK 0 "" "")
3922 (match_operand 2 "const_int_operand" ""))
3923 (clobber (match_dup 4))
3924 (clobber (match_dup 5))
3925 (use (match_operand:DI 1 "arith_operand" ""))
3926 (use (match_operand:DI 3 "const_int_operand" ""))])]
3927 "TARGET_64BIT && optimize > 0"
3932 /* If value to set is not zero, use the library routine. */
3933 if (operands[2] != const0_rtx)
3936 /* Undetermined size, use the library routine. */
3937 if (GET_CODE (operands[1]) != CONST_INT)
3940 size = INTVAL (operands[1]);
3941 align = INTVAL (operands[3]);
3942 align = align > 8 ? 8 : align;
3944 /* If size/alignment is large, then use the library routines. */
3945 if (size / align > 16)
3948 /* This does happen, but not often enough to worry much about. */
3949 if (size / align < MOVE_RATIO)
3952 /* Fall through means we're going to use our block clear pattern. */
3954 = replace_equiv_address (operands[0],
3955 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3956 operands[4] = gen_reg_rtx (DImode);
3957 operands[5] = gen_reg_rtx (DImode);
3960 (define_insn "clrmemdi_prereload"
3961 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3963 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3964 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3965 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3966 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3969 [(set_attr "type" "multi,multi")])
3972 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3974 (clobber (match_operand:DI 1 "register_operand" ""))
3975 (clobber (match_operand:DI 4 "register_operand" ""))
3976 (use (match_operand:DI 2 "arith_operand" ""))
3977 (use (match_operand:DI 3 "const_int_operand" ""))])]
3978 "TARGET_64BIT && reload_completed && !flag_peephole2
3979 && GET_CODE (operands[0]) == MEM
3980 && register_operand (XEXP (operands[0], 0), DImode)"
3981 [(set (match_dup 4) (match_dup 5))
3982 (parallel [(set (match_dup 0) (const_int 0))
3983 (clobber (match_dup 1))
3984 (clobber (match_dup 4))
3990 operands[5] = XEXP (operands[0], 0);
3991 operands[0] = replace_equiv_address (operands[0], operands[4]);
3995 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3997 (clobber (match_operand:DI 1 "register_operand" ""))
3998 (clobber (match_operand:DI 4 "register_operand" ""))
3999 (use (match_operand:DI 2 "arith_operand" ""))
4000 (use (match_operand:DI 3 "const_int_operand" ""))])]
4002 && GET_CODE (operands[0]) == MEM
4003 && register_operand (XEXP (operands[0], 0), DImode)"
4004 [(parallel [(set (match_dup 0) (const_int 0))
4005 (clobber (match_dup 1))
4006 (clobber (match_dup 4))
4012 rtx addr = XEXP (operands[0], 0);
4013 if (dead_or_set_p (curr_insn, addr))
4017 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4018 operands[0] = replace_equiv_address (operands[0], operands[4]);
4022 (define_insn "clrmemdi_postreload"
4023 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
4025 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4026 (clobber (match_dup 0))
4027 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4028 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
4030 "TARGET_64BIT && reload_completed"
4031 "* return output_block_clear (operands, !which_alternative);"
4032 [(set_attr "type" "multi,multi")])
4034 ;; Floating point move insns
4036 ;; This pattern forces (set (reg:DF ...) (const_double ...))
4037 ;; to be reloaded by putting the constant into memory when
4038 ;; reg is a floating point register.
4040 ;; For integer registers we use ldil;ldo to set the appropriate
4043 ;; This must come before the movdf pattern, and it must be present
4044 ;; to handle obscure reloading cases.
4046 [(set (match_operand:DF 0 "register_operand" "=?r,f")
4047 (match_operand:DF 1 "" "?F,m"))]
4048 "GET_CODE (operands[1]) == CONST_DOUBLE
4049 && operands[1] != CONST0_RTX (DFmode)
4051 && !TARGET_SOFT_FLOAT"
4052 "* return (which_alternative == 0 ? output_move_double (operands)
4053 : \"fldd%F1 %1,%0\");"
4054 [(set_attr "type" "move,fpload")
4055 (set_attr "length" "16,4")])
4057 (define_expand "movdf"
4058 [(set (match_operand:DF 0 "general_operand" "")
4059 (match_operand:DF 1 "general_operand" ""))]
4063 if (GET_CODE (operands[1]) == CONST_DOUBLE
4064 && operands[1] != CONST0_RTX (DFmode))
4066 /* Reject CONST_DOUBLE loads to all hard registers when
4067 generating 64-bit code and to floating point registers
4068 when generating 32-bit code. */
4069 if (REG_P (operands[0])
4070 && HARD_REGISTER_P (operands[0])
4071 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
4075 operands[1] = force_const_mem (DFmode, operands[1]);
4078 if (emit_move_sequence (operands, DFmode, 0))
4082 ;; Handle DFmode input reloads requiring a general register as a
4083 ;; scratch register.
4084 (define_expand "reload_indf"
4085 [(set (match_operand:DF 0 "register_operand" "=Z")
4086 (match_operand:DF 1 "non_hard_reg_operand" ""))
4087 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4091 if (emit_move_sequence (operands, DFmode, operands[2]))
4094 /* We don't want the clobber emitted, so handle this ourselves. */
4095 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4099 ;; Handle DFmode output reloads requiring a general register as a
4100 ;; scratch register.
4101 (define_expand "reload_outdf"
4102 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
4103 (match_operand:DF 1 "register_operand" "Z"))
4104 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4108 if (emit_move_sequence (operands, DFmode, operands[2]))
4111 /* We don't want the clobber emitted, so handle this ourselves. */
4112 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4117 [(set (match_operand:DF 0 "move_dest_operand"
4118 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
4119 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4120 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
4121 "(register_operand (operands[0], DFmode)
4122 || reg_or_0_operand (operands[1], DFmode))
4123 && !(GET_CODE (operands[1]) == CONST_DOUBLE
4124 && GET_CODE (operands[0]) == MEM)
4126 && !TARGET_SOFT_FLOAT"
4129 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4130 || operands[1] == CONST0_RTX (DFmode))
4131 && !(REG_P (operands[0]) && REG_P (operands[1])
4132 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4133 return output_fp_move_double (operands);
4134 return output_move_double (operands);
4136 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
4137 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
4140 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
4141 (match_operand:DF 1 "reg_or_0_operand" "f"))]
4143 && !TARGET_DISABLE_INDEXING
4144 && reload_completed"
4146 [(set_attr "type" "fpstore")
4147 (set_attr "pa_combine_type" "addmove")
4148 (set_attr "length" "4")])
4151 [(set (match_operand:SI 0 "register_operand" "")
4152 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4154 (match_operand:SI 2 "register_operand" "")))
4155 (set (mem:DF (match_dup 0))
4156 (match_operand:DF 3 "register_operand" ""))]
4158 && !TARGET_DISABLE_INDEXING
4159 && REG_OK_FOR_BASE_P (operands[2])
4160 && FP_REGNO_P (REGNO (operands[3]))"
4161 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4163 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4168 [(set (match_operand:SI 0 "register_operand" "")
4169 (plus:SI (match_operand:SI 2 "register_operand" "")
4170 (mult:SI (match_operand:SI 1 "register_operand" "")
4172 (set (mem:DF (match_dup 0))
4173 (match_operand:DF 3 "register_operand" ""))]
4175 && !TARGET_DISABLE_INDEXING
4176 && REG_OK_FOR_BASE_P (operands[2])
4177 && FP_REGNO_P (REGNO (operands[3]))"
4178 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4180 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4185 [(set (match_operand:DI 0 "register_operand" "")
4186 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4188 (match_operand:DI 2 "register_operand" "")))
4189 (set (mem:DF (match_dup 0))
4190 (match_operand:DF 3 "register_operand" ""))]
4192 && !TARGET_DISABLE_INDEXING
4194 && REG_OK_FOR_BASE_P (operands[2])
4195 && FP_REGNO_P (REGNO (operands[3]))"
4196 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4198 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4203 [(set (match_operand:DI 0 "register_operand" "")
4204 (plus:DI (match_operand:DI 2 "register_operand" "")
4205 (mult:DI (match_operand:DI 1 "register_operand" "")
4207 (set (mem:DF (match_dup 0))
4208 (match_operand:DF 3 "register_operand" ""))]
4210 && !TARGET_DISABLE_INDEXING
4212 && REG_OK_FOR_BASE_P (operands[2])
4213 && FP_REGNO_P (REGNO (operands[3]))"
4214 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4216 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4221 [(set (match_operand:SI 0 "register_operand" "")
4222 (plus:SI (match_operand:SI 1 "register_operand" "")
4223 (match_operand:SI 2 "register_operand" "")))
4224 (set (mem:DF (match_dup 0))
4225 (match_operand:DF 3 "register_operand" ""))]
4227 && !TARGET_DISABLE_INDEXING
4228 && TARGET_NO_SPACE_REGS
4229 && REG_OK_FOR_INDEX_P (operands[1])
4230 && REG_OK_FOR_BASE_P (operands[2])
4231 && FP_REGNO_P (REGNO (operands[3]))"
4232 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
4234 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4238 [(set (match_operand:SI 0 "register_operand" "")
4239 (plus:SI (match_operand:SI 1 "register_operand" "")
4240 (match_operand:SI 2 "register_operand" "")))
4241 (set (mem:DF (match_dup 0))
4242 (match_operand:DF 3 "register_operand" ""))]
4244 && !TARGET_DISABLE_INDEXING
4245 && TARGET_NO_SPACE_REGS
4246 && REG_OK_FOR_BASE_P (operands[1])
4247 && REG_OK_FOR_INDEX_P (operands[2])
4248 && FP_REGNO_P (REGNO (operands[3]))"
4249 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
4251 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4255 [(set (match_operand:DI 0 "register_operand" "")
4256 (plus:DI (match_operand:DI 1 "register_operand" "")
4257 (match_operand:DI 2 "register_operand" "")))
4258 (set (mem:DF (match_dup 0))
4259 (match_operand:DF 3 "register_operand" ""))]
4261 && !TARGET_DISABLE_INDEXING
4263 && TARGET_NO_SPACE_REGS
4264 && REG_OK_FOR_INDEX_P (operands[1])
4265 && REG_OK_FOR_BASE_P (operands[2])
4266 && FP_REGNO_P (REGNO (operands[3]))"
4267 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4269 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4273 [(set (match_operand:DI 0 "register_operand" "")
4274 (plus:DI (match_operand:DI 1 "register_operand" "")
4275 (match_operand:DI 2 "register_operand" "")))
4276 (set (mem:DF (match_dup 0))
4277 (match_operand:DF 3 "register_operand" ""))]
4279 && !TARGET_DISABLE_INDEXING
4281 && TARGET_NO_SPACE_REGS
4282 && REG_OK_FOR_BASE_P (operands[1])
4283 && REG_OK_FOR_INDEX_P (operands[2])
4284 && FP_REGNO_P (REGNO (operands[3]))"
4285 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4287 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4291 [(set (match_operand:DF 0 "move_dest_operand"
4293 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4295 "(register_operand (operands[0], DFmode)
4296 || reg_or_0_operand (operands[1], DFmode))
4298 && TARGET_SOFT_FLOAT"
4301 return output_move_double (operands);
4303 [(set_attr "type" "move,store,store,load,load")
4304 (set_attr "length" "8,8,16,8,16")])
4307 [(set (match_operand:DF 0 "move_dest_operand"
4308 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4309 (match_operand:DF 1 "move_src_operand"
4310 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4311 "(register_operand (operands[0], DFmode)
4312 || reg_or_0_operand (operands[1], DFmode))
4313 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4324 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4325 (set_attr "pa_combine_type" "addmove")
4326 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4329 (define_expand "movdi"
4330 [(set (match_operand:DI 0 "general_operand" "")
4331 (match_operand:DI 1 "general_operand" ""))]
4335 /* Except for zero, we don't support loading a CONST_INT directly
4336 to a hard floating-point register since a scratch register is
4337 needed for the operation. While the operation could be handled
4338 before register allocation, the simplest solution is to fail. */
4340 && GET_CODE (operands[1]) == CONST_INT
4341 && operands[1] != CONST0_RTX (DImode)
4342 && REG_P (operands[0])
4343 && HARD_REGISTER_P (operands[0])
4344 && REGNO (operands[0]) >= 32)
4347 if (emit_move_sequence (operands, DImode, 0))
4351 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4352 (define_expand "reload_indi_r1"
4353 [(set (match_operand:DI 0 "register_operand" "=Z")
4354 (match_operand:DI 1 "non_hard_reg_operand" ""))
4355 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4359 if (emit_move_sequence (operands, DImode, operands[2]))
4362 /* We don't want the clobber emitted, so handle this ourselves. */
4363 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4367 ;; Handle DImode input reloads requiring a general register as a
4368 ;; scratch register.
4369 (define_expand "reload_indi"
4370 [(set (match_operand:DI 0 "register_operand" "=Z")
4371 (match_operand:DI 1 "non_hard_reg_operand" ""))
4372 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4376 if (emit_move_sequence (operands, DImode, operands[2]))
4379 /* We don't want the clobber emitted, so handle this ourselves. */
4380 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4384 ;; Handle DImode output reloads requiring a general register as a
4385 ;; scratch register.
4386 (define_expand "reload_outdi"
4387 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4388 (match_operand:DI 1 "register_operand" "Z"))
4389 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4393 if (emit_move_sequence (operands, DImode, operands[2]))
4396 /* We don't want the clobber emitted, so handle this ourselves. */
4397 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4402 [(set (match_operand:DI 0 "register_operand" "=r")
4403 (high:DI (match_operand 1 "" "")))]
4407 rtx op0 = operands[0];
4408 rtx op1 = operands[1];
4410 switch (GET_CODE (op1))
4413 #if HOST_BITS_PER_WIDE_INT <= 32
4414 operands[0] = operand_subword (op0, 1, 0, DImode);
4415 output_asm_insn (\"ldil L'%1,%0\", operands);
4417 operands[0] = operand_subword (op0, 0, 0, DImode);
4418 if (INTVAL (op1) < 0)
4419 output_asm_insn (\"ldi -1,%0\", operands);
4421 output_asm_insn (\"ldi 0,%0\", operands);
4423 operands[0] = operand_subword (op0, 1, 0, DImode);
4424 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4425 output_asm_insn (\"ldil L'%1,%0\", operands);
4427 operands[0] = operand_subword (op0, 0, 0, DImode);
4428 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4429 output_asm_insn (singlemove_string (operands), operands);
4434 operands[0] = operand_subword (op0, 1, 0, DImode);
4435 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4436 output_asm_insn (\"ldil L'%1,%0\", operands);
4438 operands[0] = operand_subword (op0, 0, 0, DImode);
4439 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4440 output_asm_insn (singlemove_string (operands), operands);
4448 [(set_attr "type" "move")
4449 (set_attr "length" "12")])
4452 [(set (match_operand:DI 0 "move_dest_operand"
4453 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4454 (match_operand:DI 1 "general_operand"
4455 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4456 "(register_operand (operands[0], DImode)
4457 || reg_or_0_operand (operands[1], DImode))
4459 && !TARGET_SOFT_FLOAT"
4462 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4463 || operands[1] == CONST0_RTX (DFmode))
4464 && !(REG_P (operands[0]) && REG_P (operands[1])
4465 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4466 return output_fp_move_double (operands);
4467 return output_move_double (operands);
4470 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4471 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4474 [(set (match_operand:DI 0 "move_dest_operand"
4475 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4476 (match_operand:DI 1 "move_src_operand"
4477 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4478 "(register_operand (operands[0], DImode)
4479 || reg_or_0_operand (operands[1], DImode))
4480 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4490 {mfctl|mfctl,w} %%sar,%0
4494 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4495 (set_attr "pa_combine_type" "addmove")
4496 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4499 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4500 (match_operand:DI 1 "register_operand" "f"))]
4503 && !TARGET_DISABLE_INDEXING
4504 && reload_completed"
4506 [(set_attr "type" "fpstore")
4507 (set_attr "pa_combine_type" "addmove")
4508 (set_attr "length" "4")])
4511 [(set (match_operand:DI 0 "register_operand" "")
4512 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4514 (match_operand:DI 2 "register_operand" "")))
4515 (set (mem:DI (match_dup 0))
4516 (match_operand:DI 3 "register_operand" ""))]
4518 && !TARGET_DISABLE_INDEXING
4520 && REG_OK_FOR_BASE_P (operands[2])
4521 && FP_REGNO_P (REGNO (operands[3]))"
4522 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4524 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4529 [(set (match_operand:DI 0 "register_operand" "")
4530 (plus:DI (match_operand:DI 2 "register_operand" "")
4531 (mult:DI (match_operand:DI 1 "register_operand" "")
4533 (set (mem:DI (match_dup 0))
4534 (match_operand:DI 3 "register_operand" ""))]
4536 && !TARGET_DISABLE_INDEXING
4538 && REG_OK_FOR_BASE_P (operands[2])
4539 && FP_REGNO_P (REGNO (operands[3]))"
4540 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4542 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4547 [(set (match_operand:DI 0 "register_operand" "")
4548 (plus:DI (match_operand:DI 1 "register_operand" "")
4549 (match_operand:DI 2 "register_operand" "")))
4550 (set (mem:DI (match_dup 0))
4551 (match_operand:DI 3 "register_operand" ""))]
4553 && !TARGET_DISABLE_INDEXING
4555 && TARGET_NO_SPACE_REGS
4556 && REG_OK_FOR_INDEX_P (operands[1])
4557 && REG_OK_FOR_BASE_P (operands[2])
4558 && FP_REGNO_P (REGNO (operands[3]))"
4559 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4561 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4565 [(set (match_operand:DI 0 "register_operand" "")
4566 (plus:DI (match_operand:DI 1 "register_operand" "")
4567 (match_operand:DI 2 "register_operand" "")))
4568 (set (mem:DI (match_dup 0))
4569 (match_operand:DI 3 "register_operand" ""))]
4571 && !TARGET_DISABLE_INDEXING
4573 && TARGET_NO_SPACE_REGS
4574 && REG_OK_FOR_BASE_P (operands[1])
4575 && REG_OK_FOR_INDEX_P (operands[2])
4576 && FP_REGNO_P (REGNO (operands[3]))"
4577 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4579 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4583 [(set (match_operand:DI 0 "move_dest_operand"
4585 (match_operand:DI 1 "general_operand"
4587 "(register_operand (operands[0], DImode)
4588 || reg_or_0_operand (operands[1], DImode))
4590 && TARGET_SOFT_FLOAT"
4593 return output_move_double (operands);
4595 [(set_attr "type" "move,store,store,load,load,multi")
4596 (set_attr "length" "8,8,16,8,16,16")])
4599 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4600 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4601 (match_operand:DI 2 "immediate_operand" "i,i")))]
4605 /* Don't output a 64-bit constant, since we can't trust the assembler to
4606 handle it correctly. */
4607 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4608 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4609 else if (HOST_BITS_PER_WIDE_INT > 32
4610 && GET_CODE (operands[2]) == CONST_INT)
4611 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4612 if (which_alternative == 1)
4613 output_asm_insn (\"copy %1,%0\", operands);
4614 return \"ldo R'%G2(%R1),%R0\";
4616 [(set_attr "type" "move,move")
4617 (set_attr "length" "4,8")])
4619 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4620 ;; to be reloaded by putting the constant into memory when
4621 ;; reg is a floating point register.
4623 ;; For integer registers we use ldil;ldo to set the appropriate
4626 ;; This must come before the movsf pattern, and it must be present
4627 ;; to handle obscure reloading cases.
4629 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4630 (match_operand:SF 1 "" "?F,m"))]
4631 "GET_CODE (operands[1]) == CONST_DOUBLE
4632 && operands[1] != CONST0_RTX (SFmode)
4633 && ! TARGET_SOFT_FLOAT"
4634 "* return (which_alternative == 0 ? singlemove_string (operands)
4635 : \" fldw%F1 %1,%0\");"
4636 [(set_attr "type" "move,fpload")
4637 (set_attr "length" "8,4")])
4639 (define_expand "movsf"
4640 [(set (match_operand:SF 0 "general_operand" "")
4641 (match_operand:SF 1 "general_operand" ""))]
4645 /* Reject CONST_DOUBLE loads to floating point registers. */
4646 if (GET_CODE (operands[1]) == CONST_DOUBLE
4647 && operands[1] != CONST0_RTX (SFmode)
4648 && REG_P (operands[0])
4649 && HARD_REGISTER_P (operands[0])
4650 && REGNO (operands[0]) >= 32)
4653 if (emit_move_sequence (operands, SFmode, 0))
4657 ;; Handle SFmode input reloads requiring a general register as a
4658 ;; scratch register.
4659 (define_expand "reload_insf"
4660 [(set (match_operand:SF 0 "register_operand" "=Z")
4661 (match_operand:SF 1 "non_hard_reg_operand" ""))
4662 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4666 if (emit_move_sequence (operands, SFmode, operands[2]))
4669 /* We don't want the clobber emitted, so handle this ourselves. */
4670 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4674 ;; Handle SFmode output reloads requiring a general register as a
4675 ;; scratch register.
4676 (define_expand "reload_outsf"
4677 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4678 (match_operand:SF 1 "register_operand" "Z"))
4679 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4683 if (emit_move_sequence (operands, SFmode, operands[2]))
4686 /* We don't want the clobber emitted, so handle this ourselves. */
4687 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4692 [(set (match_operand:SF 0 "move_dest_operand"
4693 "=f,!*r,f,*r,Q,Q,?*r,?f")
4694 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4695 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4696 "(register_operand (operands[0], SFmode)
4697 || reg_or_0_operand (operands[1], SFmode))
4698 && !TARGET_SOFT_FLOAT
4707 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4708 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4709 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4710 (set_attr "pa_combine_type" "addmove")
4711 (set_attr "length" "4,4,4,4,4,4,8,8")])
4714 [(set (match_operand:SF 0 "move_dest_operand"
4716 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4717 "fG,!*rG,RQ,RQ,f,*rG"))]
4718 "(register_operand (operands[0], SFmode)
4719 || reg_or_0_operand (operands[1], SFmode))
4720 && !TARGET_SOFT_FLOAT
4729 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4730 (set_attr "pa_combine_type" "addmove")
4731 (set_attr "length" "4,4,4,4,4,4")])
4734 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4735 (match_operand:SF 1 "register_operand" "f"))]
4737 && !TARGET_DISABLE_INDEXING
4738 && reload_completed"
4740 [(set_attr "type" "fpstore")
4741 (set_attr "pa_combine_type" "addmove")
4742 (set_attr "length" "4")])
4745 [(set (match_operand:SI 0 "register_operand" "")
4746 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4748 (match_operand:SI 2 "register_operand" "")))
4749 (set (mem:SF (match_dup 0))
4750 (match_operand:SF 3 "register_operand" ""))]
4752 && !TARGET_DISABLE_INDEXING
4753 && REG_OK_FOR_BASE_P (operands[2])
4754 && FP_REGNO_P (REGNO (operands[3]))"
4755 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4757 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4762 [(set (match_operand:SI 0 "register_operand" "")
4763 (plus:SI (match_operand:SI 2 "register_operand" "")
4764 (mult:SI (match_operand:SI 1 "register_operand" "")
4766 (set (mem:SF (match_dup 0))
4767 (match_operand:SF 3 "register_operand" ""))]
4769 && !TARGET_DISABLE_INDEXING
4770 && REG_OK_FOR_BASE_P (operands[2])
4771 && FP_REGNO_P (REGNO (operands[3]))"
4772 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4774 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4779 [(set (match_operand:DI 0 "register_operand" "")
4780 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4782 (match_operand:DI 2 "register_operand" "")))
4783 (set (mem:SF (match_dup 0))
4784 (match_operand:SF 3 "register_operand" ""))]
4786 && !TARGET_DISABLE_INDEXING
4788 && REG_OK_FOR_BASE_P (operands[2])
4789 && FP_REGNO_P (REGNO (operands[3]))"
4790 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4792 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4797 [(set (match_operand:DI 0 "register_operand" "")
4798 (plus:DI (match_operand:DI 2 "register_operand" "")
4799 (mult:DI (match_operand:DI 1 "register_operand" "")
4801 (set (mem:SF (match_dup 0))
4802 (match_operand:SF 3 "register_operand" ""))]
4804 && !TARGET_DISABLE_INDEXING
4806 && REG_OK_FOR_BASE_P (operands[2])
4807 && FP_REGNO_P (REGNO (operands[3]))"
4808 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4810 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4815 [(set (match_operand:SI 0 "register_operand" "")
4816 (plus:SI (match_operand:SI 1 "register_operand" "")
4817 (match_operand:SI 2 "register_operand" "")))
4818 (set (mem:SF (match_dup 0))
4819 (match_operand:SF 3 "register_operand" ""))]
4821 && !TARGET_DISABLE_INDEXING
4822 && TARGET_NO_SPACE_REGS
4823 && REG_OK_FOR_INDEX_P (operands[1])
4824 && REG_OK_FOR_BASE_P (operands[2])
4825 && FP_REGNO_P (REGNO (operands[3]))"
4826 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4828 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4832 [(set (match_operand:SI 0 "register_operand" "")
4833 (plus:SI (match_operand:SI 1 "register_operand" "")
4834 (match_operand:SI 2 "register_operand" "")))
4835 (set (mem:SF (match_dup 0))
4836 (match_operand:SF 3 "register_operand" ""))]
4838 && !TARGET_DISABLE_INDEXING
4839 && TARGET_NO_SPACE_REGS
4840 && REG_OK_FOR_BASE_P (operands[1])
4841 && REG_OK_FOR_INDEX_P (operands[2])
4842 && FP_REGNO_P (REGNO (operands[3]))"
4843 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4845 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4849 [(set (match_operand:DI 0 "register_operand" "")
4850 (plus:DI (match_operand:DI 1 "register_operand" "")
4851 (match_operand:DI 2 "register_operand" "")))
4852 (set (mem:SF (match_dup 0))
4853 (match_operand:SF 3 "register_operand" ""))]
4855 && !TARGET_DISABLE_INDEXING
4857 && TARGET_NO_SPACE_REGS
4858 && REG_OK_FOR_INDEX_P (operands[1])
4859 && REG_OK_FOR_BASE_P (operands[2])
4860 && FP_REGNO_P (REGNO (operands[3]))"
4861 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4863 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4867 [(set (match_operand:DI 0 "register_operand" "")
4868 (plus:DI (match_operand:DI 1 "register_operand" "")
4869 (match_operand:DI 2 "register_operand" "")))
4870 (set (mem:SF (match_dup 0))
4871 (match_operand:SF 3 "register_operand" ""))]
4873 && !TARGET_DISABLE_INDEXING
4875 && TARGET_NO_SPACE_REGS
4876 && REG_OK_FOR_BASE_P (operands[1])
4877 && REG_OK_FOR_INDEX_P (operands[2])
4878 && FP_REGNO_P (REGNO (operands[3]))"
4879 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4881 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4885 [(set (match_operand:SF 0 "move_dest_operand"
4887 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4889 "(register_operand (operands[0], SFmode)
4890 || reg_or_0_operand (operands[1], SFmode))
4891 && TARGET_SOFT_FLOAT"
4896 [(set_attr "type" "move,load,store")
4897 (set_attr "pa_combine_type" "addmove")
4898 (set_attr "length" "4,4,4")])
4902 ;;- zero extension instructions
4903 ;; We have define_expand for zero extension patterns to make sure the
4904 ;; operands get loaded into registers. The define_insns accept
4905 ;; memory operands. This gives us better overall code than just
4906 ;; having a pattern that does or does not accept memory operands.
4908 (define_expand "zero_extendqihi2"
4909 [(set (match_operand:HI 0 "register_operand" "")
4911 (match_operand:QI 1 "register_operand" "")))]
4916 [(set (match_operand:HI 0 "register_operand" "=r,r")
4918 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4919 "GET_CODE (operands[1]) != CONST_INT"
4921 {extru|extrw,u} %1,31,8,%0
4923 [(set_attr "type" "shift,load")
4924 (set_attr "length" "4,4")])
4926 (define_expand "zero_extendqisi2"
4927 [(set (match_operand:SI 0 "register_operand" "")
4929 (match_operand:QI 1 "register_operand" "")))]
4934 [(set (match_operand:SI 0 "register_operand" "=r,r")
4936 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4937 "GET_CODE (operands[1]) != CONST_INT"
4939 {extru|extrw,u} %1,31,8,%0
4941 [(set_attr "type" "shift,load")
4942 (set_attr "length" "4,4")])
4944 (define_expand "zero_extendhisi2"
4945 [(set (match_operand:SI 0 "register_operand" "")
4947 (match_operand:HI 1 "register_operand" "")))]
4952 [(set (match_operand:SI 0 "register_operand" "=r,r")
4954 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4955 "GET_CODE (operands[1]) != CONST_INT"
4957 {extru|extrw,u} %1,31,16,%0
4959 [(set_attr "type" "shift,load")
4960 (set_attr "length" "4,4")])
4962 (define_expand "zero_extendqidi2"
4963 [(set (match_operand:DI 0 "register_operand" "")
4965 (match_operand:QI 1 "register_operand" "")))]
4970 [(set (match_operand:DI 0 "register_operand" "=r,r")
4972 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4973 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4977 [(set_attr "type" "shift,load")
4978 (set_attr "length" "4,4")])
4980 (define_expand "zero_extendhidi2"
4981 [(set (match_operand:DI 0 "register_operand" "")
4983 (match_operand:HI 1 "register_operand" "")))]
4988 [(set (match_operand:DI 0 "register_operand" "=r,r")
4990 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4991 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4995 [(set_attr "type" "shift,load")
4996 (set_attr "length" "4,4")])
4998 (define_expand "zero_extendsidi2"
4999 [(set (match_operand:DI 0 "register_operand" "")
5001 (match_operand:SI 1 "register_operand" "")))]
5006 [(set (match_operand:DI 0 "register_operand" "=r,r")
5008 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
5009 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5013 [(set_attr "type" "shift,load")
5014 (set_attr "length" "4,4")])
5016 ;;- sign extension instructions
5018 (define_insn "extendhisi2"
5019 [(set (match_operand:SI 0 "register_operand" "=r")
5020 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
5022 "{extrs|extrw,s} %1,31,16,%0"
5023 [(set_attr "type" "shift")
5024 (set_attr "length" "4")])
5026 (define_insn "extendqihi2"
5027 [(set (match_operand:HI 0 "register_operand" "=r")
5028 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
5030 "{extrs|extrw,s} %1,31,8,%0"
5031 [(set_attr "type" "shift")
5032 (set_attr "length" "4")])
5034 (define_insn "extendqisi2"
5035 [(set (match_operand:SI 0 "register_operand" "=r")
5036 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
5038 "{extrs|extrw,s} %1,31,8,%0"
5039 [(set_attr "type" "shift")
5040 (set_attr "length" "4")])
5042 (define_insn "extendqidi2"
5043 [(set (match_operand:DI 0 "register_operand" "=r")
5044 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
5046 "extrd,s %1,63,8,%0"
5047 [(set_attr "type" "shift")
5048 (set_attr "length" "4")])
5050 (define_insn "extendhidi2"
5051 [(set (match_operand:DI 0 "register_operand" "=r")
5052 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
5054 "extrd,s %1,63,16,%0"
5055 [(set_attr "type" "shift")
5056 (set_attr "length" "4")])
5058 (define_insn "extendsidi2"
5059 [(set (match_operand:DI 0 "register_operand" "=r")
5060 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
5062 "extrd,s %1,63,32,%0"
5063 [(set_attr "type" "shift")
5064 (set_attr "length" "4")])
5067 ;; Conversions between float and double.
5069 (define_insn "extendsfdf2"
5070 [(set (match_operand:DF 0 "register_operand" "=f")
5072 (match_operand:SF 1 "register_operand" "f")))]
5073 "! TARGET_SOFT_FLOAT"
5074 "{fcnvff|fcnv},sgl,dbl %1,%0"
5075 [(set_attr "type" "fpalu")
5076 (set_attr "length" "4")])
5078 (define_insn "truncdfsf2"
5079 [(set (match_operand:SF 0 "register_operand" "=f")
5081 (match_operand:DF 1 "register_operand" "f")))]
5082 "! TARGET_SOFT_FLOAT"
5083 "{fcnvff|fcnv},dbl,sgl %1,%0"
5084 [(set_attr "type" "fpalu")
5085 (set_attr "length" "4")])
5087 ;; Conversion between fixed point and floating point.
5088 ;; Note that among the fix-to-float insns
5089 ;; the ones that start with SImode come first.
5090 ;; That is so that an operand that is a CONST_INT
5091 ;; (and therefore lacks a specific machine mode).
5092 ;; will be recognized as SImode (which is always valid)
5093 ;; rather than as QImode or HImode.
5095 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
5096 ;; to be reloaded by putting the constant into memory.
5097 ;; It must come before the more general floatsisf2 pattern.
5099 [(set (match_operand:SF 0 "register_operand" "=f")
5100 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
5101 "! TARGET_SOFT_FLOAT"
5102 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
5103 [(set_attr "type" "fpalu")
5104 (set_attr "length" "8")])
5106 (define_insn "floatsisf2"
5107 [(set (match_operand:SF 0 "register_operand" "=f")
5108 (float:SF (match_operand:SI 1 "register_operand" "f")))]
5109 "! TARGET_SOFT_FLOAT"
5110 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
5111 [(set_attr "type" "fpalu")
5112 (set_attr "length" "4")])
5114 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
5115 ;; to be reloaded by putting the constant into memory.
5116 ;; It must come before the more general floatsidf2 pattern.
5118 [(set (match_operand:DF 0 "register_operand" "=f")
5119 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
5120 "! TARGET_SOFT_FLOAT"
5121 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
5122 [(set_attr "type" "fpalu")
5123 (set_attr "length" "8")])
5125 (define_insn "floatsidf2"
5126 [(set (match_operand:DF 0 "register_operand" "=f")
5127 (float:DF (match_operand:SI 1 "register_operand" "f")))]
5128 "! TARGET_SOFT_FLOAT"
5129 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
5130 [(set_attr "type" "fpalu")
5131 (set_attr "length" "4")])
5133 (define_expand "floatunssisf2"
5134 [(set (subreg:SI (match_dup 2) 4)
5135 (match_operand:SI 1 "register_operand" ""))
5136 (set (subreg:SI (match_dup 2) 0)
5138 (set (match_operand:SF 0 "register_operand" "")
5139 (float:SF (match_dup 2)))]
5140 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5145 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
5148 operands[2] = gen_reg_rtx (DImode);
5151 (define_expand "floatunssidf2"
5152 [(set (subreg:SI (match_dup 2) 4)
5153 (match_operand:SI 1 "register_operand" ""))
5154 (set (subreg:SI (match_dup 2) 0)
5156 (set (match_operand:DF 0 "register_operand" "")
5157 (float:DF (match_dup 2)))]
5158 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5163 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
5166 operands[2] = gen_reg_rtx (DImode);
5169 (define_insn "floatdisf2"
5170 [(set (match_operand:SF 0 "register_operand" "=f")
5171 (float:SF (match_operand:DI 1 "register_operand" "f")))]
5172 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5173 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
5174 [(set_attr "type" "fpalu")
5175 (set_attr "length" "4")])
5177 (define_insn "floatdidf2"
5178 [(set (match_operand:DF 0 "register_operand" "=f")
5179 (float:DF (match_operand:DI 1 "register_operand" "f")))]
5180 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5181 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
5182 [(set_attr "type" "fpalu")
5183 (set_attr "length" "4")])
5185 ;; Convert a float to an actual integer.
5186 ;; Truncation is performed as part of the conversion.
5188 (define_insn "fix_truncsfsi2"
5189 [(set (match_operand:SI 0 "register_operand" "=f")
5190 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5191 "! TARGET_SOFT_FLOAT"
5192 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
5193 [(set_attr "type" "fpalu")
5194 (set_attr "length" "4")])
5196 (define_insn "fix_truncdfsi2"
5197 [(set (match_operand:SI 0 "register_operand" "=f")
5198 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5199 "! TARGET_SOFT_FLOAT"
5200 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
5201 [(set_attr "type" "fpalu")
5202 (set_attr "length" "4")])
5204 (define_insn "fix_truncsfdi2"
5205 [(set (match_operand:DI 0 "register_operand" "=f")
5206 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5207 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5208 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
5209 [(set_attr "type" "fpalu")
5210 (set_attr "length" "4")])
5212 (define_insn "fix_truncdfdi2"
5213 [(set (match_operand:DI 0 "register_operand" "=f")
5214 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5215 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5216 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
5217 [(set_attr "type" "fpalu")
5218 (set_attr "length" "4")])
5220 (define_insn "floatunssidf2_pa20"
5221 [(set (match_operand:DF 0 "register_operand" "=f")
5222 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
5223 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5225 [(set_attr "type" "fpalu")
5226 (set_attr "length" "4")])
5228 (define_insn "floatunssisf2_pa20"
5229 [(set (match_operand:SF 0 "register_operand" "=f")
5230 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
5231 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5233 [(set_attr "type" "fpalu")
5234 (set_attr "length" "4")])
5236 (define_insn "floatunsdisf2"
5237 [(set (match_operand:SF 0 "register_operand" "=f")
5238 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
5239 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5240 "fcnv,udw,sgl %1,%0"
5241 [(set_attr "type" "fpalu")
5242 (set_attr "length" "4")])
5244 (define_insn "floatunsdidf2"
5245 [(set (match_operand:DF 0 "register_operand" "=f")
5246 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
5247 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5248 "fcnv,udw,dbl %1,%0"
5249 [(set_attr "type" "fpalu")
5250 (set_attr "length" "4")])
5252 (define_insn "fixuns_truncsfsi2"
5253 [(set (match_operand:SI 0 "register_operand" "=f")
5254 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5255 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5256 "fcnv,t,sgl,uw %1,%0"
5257 [(set_attr "type" "fpalu")
5258 (set_attr "length" "4")])
5260 (define_insn "fixuns_truncdfsi2"
5261 [(set (match_operand:SI 0 "register_operand" "=f")
5262 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5263 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5264 "fcnv,t,dbl,uw %1,%0"
5265 [(set_attr "type" "fpalu")
5266 (set_attr "length" "4")])
5268 (define_insn "fixuns_truncsfdi2"
5269 [(set (match_operand:DI 0 "register_operand" "=f")
5270 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5271 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5272 "fcnv,t,sgl,udw %1,%0"
5273 [(set_attr "type" "fpalu")
5274 (set_attr "length" "4")])
5276 (define_insn "fixuns_truncdfdi2"
5277 [(set (match_operand:DI 0 "register_operand" "=f")
5278 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5279 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5280 "fcnv,t,dbl,udw %1,%0"
5281 [(set_attr "type" "fpalu")
5282 (set_attr "length" "4")])
5284 ;;- arithmetic instructions
5286 (define_expand "adddi3"
5287 [(set (match_operand:DI 0 "register_operand" "")
5288 (plus:DI (match_operand:DI 1 "register_operand" "")
5289 (match_operand:DI 2 "adddi3_operand" "")))]
5294 [(set (match_operand:DI 0 "register_operand" "=r")
5295 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5296 (match_operand:DI 2 "arith11_operand" "rI")))]
5300 if (GET_CODE (operands[2]) == CONST_INT)
5302 if (INTVAL (operands[2]) >= 0)
5303 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5305 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5308 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5310 [(set_attr "type" "binary")
5311 (set_attr "length" "8")])
5314 [(set (match_operand:DI 0 "register_operand" "=r,r")
5315 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5316 (match_operand:DI 2 "arith_operand" "r,J")))]
5321 [(set_attr "type" "binary,binary")
5322 (set_attr "pa_combine_type" "addmove")
5323 (set_attr "length" "4,4")])
5326 [(set (match_operand:DI 0 "register_operand" "=r")
5327 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5328 (match_operand:DI 2 "register_operand" "r")))]
5331 [(set_attr "type" "binary")
5332 (set_attr "length" "4")])
5335 [(set (match_operand:SI 0 "register_operand" "=r")
5336 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5337 (match_operand:SI 2 "register_operand" "r")))]
5340 [(set_attr "type" "binary")
5341 (set_attr "length" "4")])
5343 (define_expand "addvdi3"
5344 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5345 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
5346 (match_operand:DI 2 "arith11_operand" "")))
5347 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5348 (sign_extend:TI (match_dup 2)))
5349 (sign_extend:TI (plus:DI (match_dup 1)
5356 [(set (match_operand:DI 0 "register_operand" "=r,r")
5357 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
5358 (match_operand:DI 2 "arith11_operand" "r,I")))
5359 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5360 (sign_extend:TI (match_dup 2)))
5361 (sign_extend:TI (plus:DI (match_dup 1)
5367 addi,tsv,* %2,%1,%0"
5368 [(set_attr "type" "binary,binary")
5369 (set_attr "length" "4,4")])
5372 [(set (match_operand:DI 0 "register_operand" "=r")
5373 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5374 (match_operand:DI 2 "arith11_operand" "rI")))
5375 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5376 (sign_extend:TI (match_dup 2)))
5377 (sign_extend:TI (plus:DI (match_dup 1)
5383 if (GET_CODE (operands[2]) == CONST_INT)
5385 if (INTVAL (operands[2]) >= 0)
5386 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5388 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5391 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5393 [(set_attr "type" "binary")
5394 (set_attr "length" "8")])
5396 ;; define_splits to optimize cases of adding a constant integer
5397 ;; to a register when the constant does not fit in 14 bits. */
5399 [(set (match_operand:SI 0 "register_operand" "")
5400 (plus:SI (match_operand:SI 1 "register_operand" "")
5401 (match_operand:SI 2 "const_int_operand" "")))
5402 (clobber (match_operand:SI 4 "register_operand" ""))]
5403 "! cint_ok_for_move (INTVAL (operands[2]))
5404 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5405 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5406 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5409 int val = INTVAL (operands[2]);
5410 int low = (val < 0) ? -0x2000 : 0x1fff;
5411 int rest = val - low;
5413 operands[2] = GEN_INT (rest);
5414 operands[3] = GEN_INT (low);
5418 [(set (match_operand:SI 0 "register_operand" "")
5419 (plus:SI (match_operand:SI 1 "register_operand" "")
5420 (match_operand:SI 2 "const_int_operand" "")))
5421 (clobber (match_operand:SI 4 "register_operand" ""))]
5422 "! cint_ok_for_move (INTVAL (operands[2]))"
5423 [(set (match_dup 4) (match_dup 2))
5424 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5428 HOST_WIDE_INT intval = INTVAL (operands[2]);
5430 /* Try dividing the constant by 2, then 4, and finally 8 to see
5431 if we can get a constant which can be loaded into a register
5432 in a single instruction (cint_ok_for_move).
5434 If that fails, try to negate the constant and subtract it
5435 from our input operand. */
5436 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5438 operands[2] = GEN_INT (intval / 2);
5439 operands[3] = const2_rtx;
5441 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5443 operands[2] = GEN_INT (intval / 4);
5444 operands[3] = GEN_INT (4);
5446 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5448 operands[2] = GEN_INT (intval / 8);
5449 operands[3] = GEN_INT (8);
5451 else if (cint_ok_for_move (-intval))
5453 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5454 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5461 (define_insn "addsi3"
5462 [(set (match_operand:SI 0 "register_operand" "=r,r")
5463 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5464 (match_operand:SI 2 "arith_operand" "r,J")))]
5467 {addl|add,l} %1,%2,%0
5469 [(set_attr "type" "binary,binary")
5470 (set_attr "pa_combine_type" "addmove")
5471 (set_attr "length" "4,4")])
5473 (define_insn "addvsi3"
5474 [(set (match_operand:SI 0 "register_operand" "=r,r")
5475 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5476 (match_operand:SI 2 "arith11_operand" "r,I")))
5477 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5478 (sign_extend:DI (match_dup 2)))
5479 (sign_extend:DI (plus:SI (match_dup 1)
5484 {addo|add,tsv} %2,%1,%0
5485 {addio|addi,tsv} %2,%1,%0"
5486 [(set_attr "type" "binary,binary")
5487 (set_attr "length" "4,4")])
5489 (define_expand "subdi3"
5490 [(set (match_operand:DI 0 "register_operand" "")
5491 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5492 (match_operand:DI 2 "reg_or_0_operand" "")))]
5497 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5498 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5499 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5505 [(set_attr "type" "binary,binary,move")
5506 (set_attr "length" "4,4,4")])
5509 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5510 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5511 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5515 if (GET_CODE (operands[1]) == CONST_INT)
5517 if (INTVAL (operands[1]) >= 0)
5518 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5520 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5523 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5525 [(set_attr "type" "binary")
5526 (set (attr "length")
5527 (if_then_else (eq_attr "alternative" "0")
5529 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5534 (define_expand "subvdi3"
5535 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5536 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5537 (match_operand:DI 2 "reg_or_0_operand" "")))
5538 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5539 (sign_extend:TI (match_dup 2)))
5540 (sign_extend:TI (minus:DI (match_dup 1)
5547 [(set (match_operand:DI 0 "register_operand" "=r,r")
5548 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5549 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5550 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5551 (sign_extend:TI (match_dup 2)))
5552 (sign_extend:TI (minus:DI (match_dup 1)
5557 {subo|sub,tsv} %1,%2,%0
5558 {subio|subi,tsv} %1,%2,%0"
5559 [(set_attr "type" "binary,binary")
5560 (set_attr "length" "4,4")])
5563 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5564 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5565 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5566 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5567 (sign_extend:TI (match_dup 2)))
5568 (sign_extend:TI (minus:DI (match_dup 1)
5574 if (GET_CODE (operands[1]) == CONST_INT)
5576 if (INTVAL (operands[1]) >= 0)
5577 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5579 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5582 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5584 [(set_attr "type" "binary,binary")
5585 (set (attr "length")
5586 (if_then_else (eq_attr "alternative" "0")
5588 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5593 (define_expand "subsi3"
5594 [(set (match_operand:SI 0 "register_operand" "")
5595 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5596 (match_operand:SI 2 "register_operand" "")))]
5601 [(set (match_operand:SI 0 "register_operand" "=r,r")
5602 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5603 (match_operand:SI 2 "register_operand" "r,r")))]
5608 [(set_attr "type" "binary,binary")
5609 (set_attr "length" "4,4")])
5612 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5613 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5614 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5620 [(set_attr "type" "binary,binary,move")
5621 (set_attr "length" "4,4,4")])
5623 (define_insn "subvsi3"
5624 [(set (match_operand:SI 0 "register_operand" "=r,r")
5625 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5626 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5627 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5628 (sign_extend:DI (match_dup 2)))
5629 (sign_extend:DI (minus:SI (match_dup 1)
5634 {subo|sub,tsv} %1,%2,%0
5635 {subio|subi,tsv} %1,%2,%0"
5636 [(set_attr "type" "binary,binary")
5637 (set_attr "length" "4,4")])
5639 ;; Clobbering a "register_operand" instead of a match_scratch
5640 ;; in operand3 of millicode calls avoids spilling %r1 and
5641 ;; produces better code.
5643 ;; The mulsi3 insns set up registers for the millicode call.
5644 (define_expand "mulsi3"
5645 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5646 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5647 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5648 (clobber (match_dup 3))
5649 (clobber (reg:SI 26))
5650 (clobber (reg:SI 25))
5651 (clobber (match_dup 4))])
5652 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5656 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5657 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5659 rtx scratch = gen_reg_rtx (DImode);
5660 operands[1] = force_reg (SImode, operands[1]);
5661 operands[2] = force_reg (SImode, operands[2]);
5662 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5663 emit_insn (gen_movsi (operands[0],
5664 gen_rtx_SUBREG (SImode, scratch,
5665 GET_MODE_SIZE (SImode))));
5668 operands[3] = gen_reg_rtx (SImode);
5671 (define_insn "umulsidi3"
5672 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5673 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5674 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5675 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5677 [(set_attr "type" "fpmuldbl")
5678 (set_attr "length" "4")])
5681 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5682 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5683 (match_operand:DI 2 "uint32_operand" "f")))]
5684 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5686 [(set_attr "type" "fpmuldbl")
5687 (set_attr "length" "4")])
5690 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5691 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5692 (match_operand:DI 2 "uint32_operand" "f")))]
5693 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5695 [(set_attr "type" "fpmuldbl")
5696 (set_attr "length" "4")])
5699 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5700 (clobber (match_operand:SI 0 "register_operand" "=a"))
5701 (clobber (reg:SI 26))
5702 (clobber (reg:SI 25))
5703 (clobber (reg:SI 31))]
5705 "* return output_mul_insn (0, insn);"
5706 [(set_attr "type" "milli")
5707 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5710 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5711 (clobber (match_operand:SI 0 "register_operand" "=a"))
5712 (clobber (reg:SI 26))
5713 (clobber (reg:SI 25))
5714 (clobber (reg:SI 2))]
5716 "* return output_mul_insn (0, insn);"
5717 [(set_attr "type" "milli")
5718 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5720 (define_expand "muldi3"
5721 [(set (match_operand:DI 0 "register_operand" "")
5722 (mult:DI (match_operand:DI 1 "register_operand" "")
5723 (match_operand:DI 2 "register_operand" "")))]
5724 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5727 rtx low_product = gen_reg_rtx (DImode);
5728 rtx cross_product1 = gen_reg_rtx (DImode);
5729 rtx cross_product2 = gen_reg_rtx (DImode);
5730 rtx cross_scratch = gen_reg_rtx (DImode);
5731 rtx cross_product = gen_reg_rtx (DImode);
5732 rtx op1l, op1r, op2l, op2r;
5733 rtx op1shifted, op2shifted;
5735 op1shifted = gen_reg_rtx (DImode);
5736 op2shifted = gen_reg_rtx (DImode);
5737 op1l = gen_reg_rtx (SImode);
5738 op1r = gen_reg_rtx (SImode);
5739 op2l = gen_reg_rtx (SImode);
5740 op2r = gen_reg_rtx (SImode);
5742 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5744 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5746 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5747 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5748 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5749 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5751 /* Emit multiplies for the cross products. */
5752 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5753 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5755 /* Emit a multiply for the low sub-word. */
5756 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5758 /* Sum the cross products and shift them into proper position. */
5759 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5760 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5762 /* Add the cross product to the low product and store the result
5763 into the output operand . */
5764 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5768 ;;; Division and mod.
5769 (define_expand "divsi3"
5770 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5771 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5772 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5773 (clobber (match_dup 3))
5774 (clobber (match_dup 4))
5775 (clobber (reg:SI 26))
5776 (clobber (reg:SI 25))
5777 (clobber (match_dup 5))])
5778 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5782 operands[3] = gen_reg_rtx (SImode);
5785 operands[5] = gen_rtx_REG (SImode, 2);
5786 operands[4] = operands[5];
5790 operands[5] = gen_rtx_REG (SImode, 31);
5791 operands[4] = gen_reg_rtx (SImode);
5793 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5799 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5800 (clobber (match_operand:SI 1 "register_operand" "=a"))
5801 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5802 (clobber (reg:SI 26))
5803 (clobber (reg:SI 25))
5804 (clobber (reg:SI 31))]
5807 return output_div_insn (operands, 0, insn);"
5808 [(set_attr "type" "milli")
5809 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5813 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5814 (clobber (match_operand:SI 1 "register_operand" "=a"))
5815 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5816 (clobber (reg:SI 26))
5817 (clobber (reg:SI 25))
5818 (clobber (reg:SI 2))]
5821 return output_div_insn (operands, 0, insn);"
5822 [(set_attr "type" "milli")
5823 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5825 (define_expand "udivsi3"
5826 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5827 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5828 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5829 (clobber (match_dup 3))
5830 (clobber (match_dup 4))
5831 (clobber (reg:SI 26))
5832 (clobber (reg:SI 25))
5833 (clobber (match_dup 5))])
5834 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5838 operands[3] = gen_reg_rtx (SImode);
5842 operands[5] = gen_rtx_REG (SImode, 2);
5843 operands[4] = operands[5];
5847 operands[5] = gen_rtx_REG (SImode, 31);
5848 operands[4] = gen_reg_rtx (SImode);
5850 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5856 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5857 (clobber (match_operand:SI 1 "register_operand" "=a"))
5858 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5859 (clobber (reg:SI 26))
5860 (clobber (reg:SI 25))
5861 (clobber (reg:SI 31))]
5864 return output_div_insn (operands, 1, insn);"
5865 [(set_attr "type" "milli")
5866 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5870 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5871 (clobber (match_operand:SI 1 "register_operand" "=a"))
5872 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5873 (clobber (reg:SI 26))
5874 (clobber (reg:SI 25))
5875 (clobber (reg:SI 2))]
5878 return output_div_insn (operands, 1, insn);"
5879 [(set_attr "type" "milli")
5880 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5882 (define_expand "modsi3"
5883 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5884 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5885 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5886 (clobber (match_dup 3))
5887 (clobber (match_dup 4))
5888 (clobber (reg:SI 26))
5889 (clobber (reg:SI 25))
5890 (clobber (match_dup 5))])
5891 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5897 operands[5] = gen_rtx_REG (SImode, 2);
5898 operands[4] = operands[5];
5902 operands[5] = gen_rtx_REG (SImode, 31);
5903 operands[4] = gen_reg_rtx (SImode);
5905 operands[3] = gen_reg_rtx (SImode);
5909 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5910 (clobber (match_operand:SI 0 "register_operand" "=a"))
5911 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5912 (clobber (reg:SI 26))
5913 (clobber (reg:SI 25))
5914 (clobber (reg:SI 31))]
5917 return output_mod_insn (0, insn);"
5918 [(set_attr "type" "milli")
5919 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5922 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5923 (clobber (match_operand:SI 0 "register_operand" "=a"))
5924 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5925 (clobber (reg:SI 26))
5926 (clobber (reg:SI 25))
5927 (clobber (reg:SI 2))]
5930 return output_mod_insn (0, insn);"
5931 [(set_attr "type" "milli")
5932 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5934 (define_expand "umodsi3"
5935 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5936 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5937 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5938 (clobber (match_dup 3))
5939 (clobber (match_dup 4))
5940 (clobber (reg:SI 26))
5941 (clobber (reg:SI 25))
5942 (clobber (match_dup 5))])
5943 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5949 operands[5] = gen_rtx_REG (SImode, 2);
5950 operands[4] = operands[5];
5954 operands[5] = gen_rtx_REG (SImode, 31);
5955 operands[4] = gen_reg_rtx (SImode);
5957 operands[3] = gen_reg_rtx (SImode);
5961 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5962 (clobber (match_operand:SI 0 "register_operand" "=a"))
5963 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5964 (clobber (reg:SI 26))
5965 (clobber (reg:SI 25))
5966 (clobber (reg:SI 31))]
5969 return output_mod_insn (1, insn);"
5970 [(set_attr "type" "milli")
5971 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5974 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5975 (clobber (match_operand:SI 0 "register_operand" "=a"))
5976 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5977 (clobber (reg:SI 26))
5978 (clobber (reg:SI 25))
5979 (clobber (reg:SI 2))]
5982 return output_mod_insn (1, insn);"
5983 [(set_attr "type" "milli")
5984 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5986 ;;- and instructions
5987 ;; We define DImode `and` so with DImode `not` we can get
5988 ;; DImode `andn`. Other combinations are possible.
5990 (define_expand "anddi3"
5991 [(set (match_operand:DI 0 "register_operand" "")
5992 (and:DI (match_operand:DI 1 "register_operand" "")
5993 (match_operand:DI 2 "and_operand" "")))]
5997 /* Both operands must be register operands. */
5998 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6003 [(set (match_operand:DI 0 "register_operand" "=r")
6004 (and:DI (match_operand:DI 1 "register_operand" "%r")
6005 (match_operand:DI 2 "register_operand" "r")))]
6007 "and %1,%2,%0\;and %R1,%R2,%R0"
6008 [(set_attr "type" "binary")
6009 (set_attr "length" "8")])
6012 [(set (match_operand:DI 0 "register_operand" "=r,r")
6013 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
6014 (match_operand:DI 2 "and_operand" "rO,P")))]
6016 "* return output_64bit_and (operands); "
6017 [(set_attr "type" "binary")
6018 (set_attr "length" "4")])
6020 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
6021 ; constant with ldil;ldo.
6022 (define_insn "andsi3"
6023 [(set (match_operand:SI 0 "register_operand" "=r,r")
6024 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
6025 (match_operand:SI 2 "and_operand" "rO,P")))]
6027 "* return output_and (operands); "
6028 [(set_attr "type" "binary,shift")
6029 (set_attr "length" "4,4")])
6032 [(set (match_operand:DI 0 "register_operand" "=r")
6033 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6034 (match_operand:DI 2 "register_operand" "r")))]
6036 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
6037 [(set_attr "type" "binary")
6038 (set_attr "length" "8")])
6041 [(set (match_operand:DI 0 "register_operand" "=r")
6042 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6043 (match_operand:DI 2 "register_operand" "r")))]
6046 [(set_attr "type" "binary")
6047 (set_attr "length" "4")])
6050 [(set (match_operand:SI 0 "register_operand" "=r")
6051 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
6052 (match_operand:SI 2 "register_operand" "r")))]
6055 [(set_attr "type" "binary")
6056 (set_attr "length" "4")])
6058 (define_expand "iordi3"
6059 [(set (match_operand:DI 0 "register_operand" "")
6060 (ior:DI (match_operand:DI 1 "register_operand" "")
6061 (match_operand:DI 2 "ior_operand" "")))]
6065 /* Both operands must be register operands. */
6066 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6071 [(set (match_operand:DI 0 "register_operand" "=r")
6072 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6073 (match_operand:DI 2 "register_operand" "r")))]
6075 "or %1,%2,%0\;or %R1,%R2,%R0"
6076 [(set_attr "type" "binary")
6077 (set_attr "length" "8")])
6080 [(set (match_operand:DI 0 "register_operand" "=r,r")
6081 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
6082 (match_operand:DI 2 "ior_operand" "M,i")))]
6084 "* return output_64bit_ior (operands); "
6085 [(set_attr "type" "binary,shift")
6086 (set_attr "length" "4,4")])
6089 [(set (match_operand:DI 0 "register_operand" "=r")
6090 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6091 (match_operand:DI 2 "register_operand" "r")))]
6094 [(set_attr "type" "binary")
6095 (set_attr "length" "4")])
6097 ;; Need a define_expand because we've run out of CONST_OK... characters.
6098 (define_expand "iorsi3"
6099 [(set (match_operand:SI 0 "register_operand" "")
6100 (ior:SI (match_operand:SI 1 "register_operand" "")
6101 (match_operand:SI 2 "arith32_operand" "")))]
6105 if (! (ior_operand (operands[2], SImode)
6106 || register_operand (operands[2], SImode)))
6107 operands[2] = force_reg (SImode, operands[2]);
6111 [(set (match_operand:SI 0 "register_operand" "=r,r")
6112 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
6113 (match_operand:SI 2 "ior_operand" "M,i")))]
6115 "* return output_ior (operands); "
6116 [(set_attr "type" "binary,shift")
6117 (set_attr "length" "4,4")])
6120 [(set (match_operand:SI 0 "register_operand" "=r")
6121 (ior:SI (match_operand:SI 1 "register_operand" "%r")
6122 (match_operand:SI 2 "register_operand" "r")))]
6125 [(set_attr "type" "binary")
6126 (set_attr "length" "4")])
6128 (define_expand "xordi3"
6129 [(set (match_operand:DI 0 "register_operand" "")
6130 (xor:DI (match_operand:DI 1 "register_operand" "")
6131 (match_operand:DI 2 "register_operand" "")))]
6138 [(set (match_operand:DI 0 "register_operand" "=r")
6139 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6140 (match_operand:DI 2 "register_operand" "r")))]
6142 "xor %1,%2,%0\;xor %R1,%R2,%R0"
6143 [(set_attr "type" "binary")
6144 (set_attr "length" "8")])
6147 [(set (match_operand:DI 0 "register_operand" "=r")
6148 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6149 (match_operand:DI 2 "register_operand" "r")))]
6152 [(set_attr "type" "binary")
6153 (set_attr "length" "4")])
6155 (define_insn "xorsi3"
6156 [(set (match_operand:SI 0 "register_operand" "=r")
6157 (xor:SI (match_operand:SI 1 "register_operand" "%r")
6158 (match_operand:SI 2 "register_operand" "r")))]
6161 [(set_attr "type" "binary")
6162 (set_attr "length" "4")])
6164 (define_expand "negdi2"
6165 [(set (match_operand:DI 0 "register_operand" "")
6166 (neg:DI (match_operand:DI 1 "register_operand" "")))]
6171 [(set (match_operand:DI 0 "register_operand" "=r")
6172 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6174 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
6175 [(set_attr "type" "unary")
6176 (set_attr "length" "8")])
6179 [(set (match_operand:DI 0 "register_operand" "=r")
6180 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6183 [(set_attr "type" "unary")
6184 (set_attr "length" "4")])
6186 (define_expand "negvdi2"
6187 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6188 (neg:DI (match_operand:DI 1 "register_operand" "")))
6189 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6190 (sign_extend:TI (neg:DI (match_dup 1))))
6196 [(set (match_operand:DI 0 "register_operand" "=r")
6197 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6198 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6199 (sign_extend:TI (neg:DI (match_dup 1))))
6202 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
6203 [(set_attr "type" "unary")
6204 (set_attr "length" "8")])
6207 [(set (match_operand:DI 0 "register_operand" "=r")
6208 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6209 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6210 (sign_extend:TI (neg:DI (match_dup 1))))
6213 "sub,tsv %%r0,%1,%0"
6214 [(set_attr "type" "unary")
6215 (set_attr "length" "4")])
6217 (define_insn "negsi2"
6218 [(set (match_operand:SI 0 "register_operand" "=r")
6219 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
6222 [(set_attr "type" "unary")
6223 (set_attr "length" "4")])
6225 (define_insn "negvsi2"
6226 [(set (match_operand:SI 0 "register_operand" "=r")
6227 (neg:SI (match_operand:SI 1 "register_operand" "r")))
6228 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
6229 (sign_extend:DI (neg:SI (match_dup 1))))
6232 "{subo|sub,tsv} %%r0,%1,%0"
6233 [(set_attr "type" "unary")
6234 (set_attr "length" "4")])
6236 (define_expand "one_cmpldi2"
6237 [(set (match_operand:DI 0 "register_operand" "")
6238 (not:DI (match_operand:DI 1 "register_operand" "")))]
6245 [(set (match_operand:DI 0 "register_operand" "=r")
6246 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6248 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
6249 [(set_attr "type" "unary")
6250 (set_attr "length" "8")])
6253 [(set (match_operand:DI 0 "register_operand" "=r")
6254 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6257 [(set_attr "type" "unary")
6258 (set_attr "length" "4")])
6260 (define_insn "one_cmplsi2"
6261 [(set (match_operand:SI 0 "register_operand" "=r")
6262 (not:SI (match_operand:SI 1 "register_operand" "r")))]
6265 [(set_attr "type" "unary")
6266 (set_attr "length" "4")])
6268 ;; Floating point arithmetic instructions.
6270 (define_insn "adddf3"
6271 [(set (match_operand:DF 0 "register_operand" "=f")
6272 (plus:DF (match_operand:DF 1 "register_operand" "f")
6273 (match_operand:DF 2 "register_operand" "f")))]
6274 "! TARGET_SOFT_FLOAT"
6276 [(set_attr "type" "fpalu")
6277 (set_attr "pa_combine_type" "faddsub")
6278 (set_attr "length" "4")])
6280 (define_insn "addsf3"
6281 [(set (match_operand:SF 0 "register_operand" "=f")
6282 (plus:SF (match_operand:SF 1 "register_operand" "f")
6283 (match_operand:SF 2 "register_operand" "f")))]
6284 "! TARGET_SOFT_FLOAT"
6286 [(set_attr "type" "fpalu")
6287 (set_attr "pa_combine_type" "faddsub")
6288 (set_attr "length" "4")])
6290 (define_insn "subdf3"
6291 [(set (match_operand:DF 0 "register_operand" "=f")
6292 (minus:DF (match_operand:DF 1 "register_operand" "f")
6293 (match_operand:DF 2 "register_operand" "f")))]
6294 "! TARGET_SOFT_FLOAT"
6296 [(set_attr "type" "fpalu")
6297 (set_attr "pa_combine_type" "faddsub")
6298 (set_attr "length" "4")])
6300 (define_insn "subsf3"
6301 [(set (match_operand:SF 0 "register_operand" "=f")
6302 (minus:SF (match_operand:SF 1 "register_operand" "f")
6303 (match_operand:SF 2 "register_operand" "f")))]
6304 "! TARGET_SOFT_FLOAT"
6306 [(set_attr "type" "fpalu")
6307 (set_attr "pa_combine_type" "faddsub")
6308 (set_attr "length" "4")])
6310 (define_insn "muldf3"
6311 [(set (match_operand:DF 0 "register_operand" "=f")
6312 (mult:DF (match_operand:DF 1 "register_operand" "f")
6313 (match_operand:DF 2 "register_operand" "f")))]
6314 "! TARGET_SOFT_FLOAT"
6316 [(set_attr "type" "fpmuldbl")
6317 (set_attr "pa_combine_type" "fmpy")
6318 (set_attr "length" "4")])
6320 (define_insn "mulsf3"
6321 [(set (match_operand:SF 0 "register_operand" "=f")
6322 (mult:SF (match_operand:SF 1 "register_operand" "f")
6323 (match_operand:SF 2 "register_operand" "f")))]
6324 "! TARGET_SOFT_FLOAT"
6326 [(set_attr "type" "fpmulsgl")
6327 (set_attr "pa_combine_type" "fmpy")
6328 (set_attr "length" "4")])
6330 (define_insn "divdf3"
6331 [(set (match_operand:DF 0 "register_operand" "=f")
6332 (div:DF (match_operand:DF 1 "register_operand" "f")
6333 (match_operand:DF 2 "register_operand" "f")))]
6334 "! TARGET_SOFT_FLOAT"
6336 [(set_attr "type" "fpdivdbl")
6337 (set_attr "length" "4")])
6339 (define_insn "divsf3"
6340 [(set (match_operand:SF 0 "register_operand" "=f")
6341 (div:SF (match_operand:SF 1 "register_operand" "f")
6342 (match_operand:SF 2 "register_operand" "f")))]
6343 "! TARGET_SOFT_FLOAT"
6345 [(set_attr "type" "fpdivsgl")
6346 (set_attr "length" "4")])
6348 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6349 ;; negation can be done by subtracting from plus zero. However, this
6350 ;; violates the IEEE standard when negating plus and minus zero.
6351 (define_expand "negdf2"
6352 [(parallel [(set (match_operand:DF 0 "register_operand" "")
6353 (neg:DF (match_operand:DF 1 "register_operand" "")))
6354 (use (match_dup 2))])]
6355 "! TARGET_SOFT_FLOAT"
6357 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6358 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6361 operands[2] = force_reg (DFmode,
6362 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
6363 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
6368 (define_insn "negdf2_fast"
6369 [(set (match_operand:DF 0 "register_operand" "=f")
6370 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6371 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6375 return \"fneg,dbl %1,%0\";
6377 return \"fsub,dbl %%fr0,%1,%0\";
6379 [(set_attr "type" "fpalu")
6380 (set_attr "length" "4")])
6382 (define_expand "negsf2"
6383 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6384 (neg:SF (match_operand:SF 1 "register_operand" "")))
6385 (use (match_dup 2))])]
6386 "! TARGET_SOFT_FLOAT"
6388 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6389 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6392 operands[2] = force_reg (SFmode,
6393 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6394 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6399 (define_insn "negsf2_fast"
6400 [(set (match_operand:SF 0 "register_operand" "=f")
6401 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6402 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6406 return \"fneg,sgl %1,%0\";
6408 return \"fsub,sgl %%fr0,%1,%0\";
6410 [(set_attr "type" "fpalu")
6411 (set_attr "length" "4")])
6413 (define_insn "absdf2"
6414 [(set (match_operand:DF 0 "register_operand" "=f")
6415 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6416 "! TARGET_SOFT_FLOAT"
6418 [(set_attr "type" "fpalu")
6419 (set_attr "length" "4")])
6421 (define_insn "abssf2"
6422 [(set (match_operand:SF 0 "register_operand" "=f")
6423 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6424 "! TARGET_SOFT_FLOAT"
6426 [(set_attr "type" "fpalu")
6427 (set_attr "length" "4")])
6429 (define_insn "sqrtdf2"
6430 [(set (match_operand:DF 0 "register_operand" "=f")
6431 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6432 "! TARGET_SOFT_FLOAT"
6434 [(set_attr "type" "fpsqrtdbl")
6435 (set_attr "length" "4")])
6437 (define_insn "sqrtsf2"
6438 [(set (match_operand:SF 0 "register_operand" "=f")
6439 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6440 "! TARGET_SOFT_FLOAT"
6442 [(set_attr "type" "fpsqrtsgl")
6443 (set_attr "length" "4")])
6445 ;; PA 2.0 floating point instructions
6449 [(set (match_operand:DF 0 "register_operand" "=f")
6450 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6451 (match_operand:DF 2 "register_operand" "f"))
6452 (match_operand:DF 3 "register_operand" "f")))]
6453 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6454 "fmpyfadd,dbl %1,%2,%3,%0"
6455 [(set_attr "type" "fpmuldbl")
6456 (set_attr "length" "4")])
6459 [(set (match_operand:DF 0 "register_operand" "=f")
6460 (plus:DF (match_operand:DF 1 "register_operand" "f")
6461 (mult:DF (match_operand:DF 2 "register_operand" "f")
6462 (match_operand:DF 3 "register_operand" "f"))))]
6463 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6464 "fmpyfadd,dbl %2,%3,%1,%0"
6465 [(set_attr "type" "fpmuldbl")
6466 (set_attr "length" "4")])
6469 [(set (match_operand:SF 0 "register_operand" "=f")
6470 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6471 (match_operand:SF 2 "register_operand" "f"))
6472 (match_operand:SF 3 "register_operand" "f")))]
6473 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6474 "fmpyfadd,sgl %1,%2,%3,%0"
6475 [(set_attr "type" "fpmulsgl")
6476 (set_attr "length" "4")])
6479 [(set (match_operand:SF 0 "register_operand" "=f")
6480 (plus:SF (match_operand:SF 1 "register_operand" "f")
6481 (mult:SF (match_operand:SF 2 "register_operand" "f")
6482 (match_operand:SF 3 "register_operand" "f"))))]
6483 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6484 "fmpyfadd,sgl %2,%3,%1,%0"
6485 [(set_attr "type" "fpmulsgl")
6486 (set_attr "length" "4")])
6488 ; fmpynfadd patterns
6490 [(set (match_operand:DF 0 "register_operand" "=f")
6491 (minus:DF (match_operand:DF 1 "register_operand" "f")
6492 (mult:DF (match_operand:DF 2 "register_operand" "f")
6493 (match_operand:DF 3 "register_operand" "f"))))]
6494 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6495 "fmpynfadd,dbl %2,%3,%1,%0"
6496 [(set_attr "type" "fpmuldbl")
6497 (set_attr "length" "4")])
6500 [(set (match_operand:SF 0 "register_operand" "=f")
6501 (minus:SF (match_operand:SF 1 "register_operand" "f")
6502 (mult:SF (match_operand:SF 2 "register_operand" "f")
6503 (match_operand:SF 3 "register_operand" "f"))))]
6504 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6505 "fmpynfadd,sgl %2,%3,%1,%0"
6506 [(set_attr "type" "fpmulsgl")
6507 (set_attr "length" "4")])
6511 [(set (match_operand:DF 0 "register_operand" "=f")
6512 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6513 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6515 [(set_attr "type" "fpalu")
6516 (set_attr "length" "4")])
6519 [(set (match_operand:SF 0 "register_operand" "=f")
6520 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6521 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6523 [(set_attr "type" "fpalu")
6524 (set_attr "length" "4")])
6526 ;; Generating a fused multiply sequence is a win for this case as it will
6527 ;; reduce the latency for the fused case without impacting the plain
6530 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6531 ;; perform two operations with the result of the first feeding the second.
6533 [(set (match_operand:DF 0 "register_operand" "=f")
6534 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6535 (match_operand:DF 2 "register_operand" "f"))
6536 (match_operand:DF 3 "register_operand" "f")))
6537 (set (match_operand:DF 4 "register_operand" "=&f")
6538 (mult:DF (match_dup 1) (match_dup 2)))]
6539 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6540 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6541 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6543 [(set_attr "type" "fpmuldbl")
6544 (set_attr "length" "8")])
6546 ;; We want to split this up during scheduling since we want both insns
6547 ;; to schedule independently.
6549 [(set (match_operand:DF 0 "register_operand" "")
6550 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6551 (match_operand:DF 2 "register_operand" ""))
6552 (match_operand:DF 3 "register_operand" "")))
6553 (set (match_operand:DF 4 "register_operand" "")
6554 (mult:DF (match_dup 1) (match_dup 2)))]
6555 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6556 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6557 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6562 [(set (match_operand:SF 0 "register_operand" "=f")
6563 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6564 (match_operand:SF 2 "register_operand" "f"))
6565 (match_operand:SF 3 "register_operand" "f")))
6566 (set (match_operand:SF 4 "register_operand" "=&f")
6567 (mult:SF (match_dup 1) (match_dup 2)))]
6568 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6569 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6570 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6572 [(set_attr "type" "fpmuldbl")
6573 (set_attr "length" "8")])
6575 ;; We want to split this up during scheduling since we want both insns
6576 ;; to schedule independently.
6578 [(set (match_operand:SF 0 "register_operand" "")
6579 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6580 (match_operand:SF 2 "register_operand" ""))
6581 (match_operand:SF 3 "register_operand" "")))
6582 (set (match_operand:SF 4 "register_operand" "")
6583 (mult:SF (match_dup 1) (match_dup 2)))]
6584 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6585 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6586 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6590 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6593 [(set (match_operand:DF 0 "register_operand" "=f")
6594 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6595 (match_operand:DF 2 "register_operand" "f"))))]
6596 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6597 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6598 [(set_attr "type" "fpmuldbl")
6599 (set_attr "length" "4")])
6602 [(set (match_operand:SF 0 "register_operand" "=f")
6603 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6604 (match_operand:SF 2 "register_operand" "f"))))]
6605 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6606 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6607 [(set_attr "type" "fpmuldbl")
6608 (set_attr "length" "4")])
6611 [(set (match_operand:DF 0 "register_operand" "=f")
6612 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6613 (match_operand:DF 2 "register_operand" "f"))))
6614 (set (match_operand:DF 3 "register_operand" "=&f")
6615 (mult:DF (match_dup 1) (match_dup 2)))]
6616 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6617 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6618 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6620 [(set_attr "type" "fpmuldbl")
6621 (set_attr "length" "8")])
6624 [(set (match_operand:DF 0 "register_operand" "")
6625 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6626 (match_operand:DF 2 "register_operand" ""))))
6627 (set (match_operand:DF 3 "register_operand" "")
6628 (mult:DF (match_dup 1) (match_dup 2)))]
6629 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6630 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6631 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6635 [(set (match_operand:SF 0 "register_operand" "=f")
6636 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6637 (match_operand:SF 2 "register_operand" "f"))))
6638 (set (match_operand:SF 3 "register_operand" "=&f")
6639 (mult:SF (match_dup 1) (match_dup 2)))]
6640 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6641 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6642 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6644 [(set_attr "type" "fpmuldbl")
6645 (set_attr "length" "8")])
6648 [(set (match_operand:SF 0 "register_operand" "")
6649 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6650 (match_operand:SF 2 "register_operand" ""))))
6651 (set (match_operand:SF 3 "register_operand" "")
6652 (mult:SF (match_dup 1) (match_dup 2)))]
6653 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6654 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6655 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6658 ;; Now fused multiplies with the result of the multiply negated.
6660 [(set (match_operand:DF 0 "register_operand" "=f")
6661 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6662 (match_operand:DF 2 "register_operand" "f")))
6663 (match_operand:DF 3 "register_operand" "f")))]
6664 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6665 "fmpynfadd,dbl %1,%2,%3,%0"
6666 [(set_attr "type" "fpmuldbl")
6667 (set_attr "length" "4")])
6670 [(set (match_operand:SF 0 "register_operand" "=f")
6671 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6672 (match_operand:SF 2 "register_operand" "f")))
6673 (match_operand:SF 3 "register_operand" "f")))]
6674 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6675 "fmpynfadd,sgl %1,%2,%3,%0"
6676 [(set_attr "type" "fpmuldbl")
6677 (set_attr "length" "4")])
6680 [(set (match_operand:DF 0 "register_operand" "=f")
6681 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6682 (match_operand:DF 2 "register_operand" "f")))
6683 (match_operand:DF 3 "register_operand" "f")))
6684 (set (match_operand:DF 4 "register_operand" "=&f")
6685 (mult:DF (match_dup 1) (match_dup 2)))]
6686 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6687 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6688 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6690 [(set_attr "type" "fpmuldbl")
6691 (set_attr "length" "8")])
6694 [(set (match_operand:DF 0 "register_operand" "")
6695 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6696 (match_operand:DF 2 "register_operand" "")))
6697 (match_operand:DF 3 "register_operand" "")))
6698 (set (match_operand:DF 4 "register_operand" "")
6699 (mult:DF (match_dup 1) (match_dup 2)))]
6700 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6701 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6702 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6707 [(set (match_operand:SF 0 "register_operand" "=f")
6708 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6709 (match_operand:SF 2 "register_operand" "f")))
6710 (match_operand:SF 3 "register_operand" "f")))
6711 (set (match_operand:SF 4 "register_operand" "=&f")
6712 (mult:SF (match_dup 1) (match_dup 2)))]
6713 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6714 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6715 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6717 [(set_attr "type" "fpmuldbl")
6718 (set_attr "length" "8")])
6721 [(set (match_operand:SF 0 "register_operand" "")
6722 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6723 (match_operand:SF 2 "register_operand" "")))
6724 (match_operand:SF 3 "register_operand" "")))
6725 (set (match_operand:SF 4 "register_operand" "")
6726 (mult:SF (match_dup 1) (match_dup 2)))]
6727 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6728 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6729 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6734 [(set (match_operand:DF 0 "register_operand" "=f")
6735 (minus:DF (match_operand:DF 3 "register_operand" "f")
6736 (mult:DF (match_operand:DF 1 "register_operand" "f")
6737 (match_operand:DF 2 "register_operand" "f"))))
6738 (set (match_operand:DF 4 "register_operand" "=&f")
6739 (mult:DF (match_dup 1) (match_dup 2)))]
6740 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6741 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6742 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6744 [(set_attr "type" "fpmuldbl")
6745 (set_attr "length" "8")])
6748 [(set (match_operand:DF 0 "register_operand" "")
6749 (minus:DF (match_operand:DF 3 "register_operand" "")
6750 (mult:DF (match_operand:DF 1 "register_operand" "")
6751 (match_operand:DF 2 "register_operand" ""))))
6752 (set (match_operand:DF 4 "register_operand" "")
6753 (mult:DF (match_dup 1) (match_dup 2)))]
6754 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6755 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6756 (set (match_dup 0) (minus:DF (match_dup 3)
6757 (mult:DF (match_dup 1) (match_dup 2))))]
6761 [(set (match_operand:SF 0 "register_operand" "=f")
6762 (minus:SF (match_operand:SF 3 "register_operand" "f")
6763 (mult:SF (match_operand:SF 1 "register_operand" "f")
6764 (match_operand:SF 2 "register_operand" "f"))))
6765 (set (match_operand:SF 4 "register_operand" "=&f")
6766 (mult:SF (match_dup 1) (match_dup 2)))]
6767 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6768 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6769 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6771 [(set_attr "type" "fpmuldbl")
6772 (set_attr "length" "8")])
6775 [(set (match_operand:SF 0 "register_operand" "")
6776 (minus:SF (match_operand:SF 3 "register_operand" "")
6777 (mult:SF (match_operand:SF 1 "register_operand" "")
6778 (match_operand:SF 2 "register_operand" ""))))
6779 (set (match_operand:SF 4 "register_operand" "")
6780 (mult:SF (match_dup 1) (match_dup 2)))]
6781 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6782 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6783 (set (match_dup 0) (minus:SF (match_dup 3)
6784 (mult:SF (match_dup 1) (match_dup 2))))]
6788 [(set (match_operand:DF 0 "register_operand" "=f")
6789 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6790 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6791 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6792 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6794 [(set_attr "type" "fpalu")
6795 (set_attr "length" "8")])
6798 [(set (match_operand:DF 0 "register_operand" "")
6799 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6800 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6801 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6802 [(set (match_dup 2) (abs:DF (match_dup 1)))
6803 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6807 [(set (match_operand:SF 0 "register_operand" "=f")
6808 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6809 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6810 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6811 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6813 [(set_attr "type" "fpalu")
6814 (set_attr "length" "8")])
6817 [(set (match_operand:SF 0 "register_operand" "")
6818 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6819 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6820 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6821 [(set (match_dup 2) (abs:SF (match_dup 1)))
6822 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6825 ;;- Shift instructions
6827 ;; Optimized special case of shifting.
6830 [(set (match_operand:SI 0 "register_operand" "=r")
6831 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6835 [(set_attr "type" "load")
6836 (set_attr "length" "4")])
6839 [(set (match_operand:SI 0 "register_operand" "=r")
6840 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6844 [(set_attr "type" "load")
6845 (set_attr "length" "4")])
6848 [(set (match_operand:SI 0 "register_operand" "=r")
6849 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6850 (match_operand:SI 3 "shadd_operand" ""))
6851 (match_operand:SI 1 "register_operand" "r")))]
6853 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6854 [(set_attr "type" "binary")
6855 (set_attr "length" "4")])
6858 [(set (match_operand:DI 0 "register_operand" "=r")
6859 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6860 (match_operand:DI 3 "shadd_operand" ""))
6861 (match_operand:DI 1 "register_operand" "r")))]
6863 "shladd,l %2,%O3,%1,%0"
6864 [(set_attr "type" "binary")
6865 (set_attr "length" "4")])
6867 (define_expand "ashlsi3"
6868 [(set (match_operand:SI 0 "register_operand" "")
6869 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6870 (match_operand:SI 2 "arith32_operand" "")))]
6874 if (GET_CODE (operands[2]) != CONST_INT)
6876 rtx temp = gen_reg_rtx (SImode);
6877 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6878 if (GET_CODE (operands[1]) == CONST_INT)
6879 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6881 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6884 /* Make sure both inputs are not constants,
6885 there are no patterns for that. */
6886 operands[1] = force_reg (SImode, operands[1]);
6890 [(set (match_operand:SI 0 "register_operand" "=r")
6891 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6892 (match_operand:SI 2 "const_int_operand" "n")))]
6894 "{zdep|depw,z} %1,%P2,%L2,%0"
6895 [(set_attr "type" "shift")
6896 (set_attr "length" "4")])
6898 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6899 ; Doing it like this makes slightly better code since reload can
6900 ; replace a register with a known value in range -16..15 with a
6901 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6902 ; but since we have no more CONST_OK... characters, that is not
6904 (define_insn "zvdep32"
6905 [(set (match_operand:SI 0 "register_operand" "=r,r")
6906 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6907 (minus:SI (const_int 31)
6908 (match_operand:SI 2 "register_operand" "q,q"))))]
6911 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6912 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6913 [(set_attr "type" "shift,shift")
6914 (set_attr "length" "4,4")])
6916 (define_insn "zvdep_imm32"
6917 [(set (match_operand:SI 0 "register_operand" "=r")
6918 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6919 (minus:SI (const_int 31)
6920 (match_operand:SI 2 "register_operand" "q"))))]
6924 int x = INTVAL (operands[1]);
6925 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6926 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6927 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6929 [(set_attr "type" "shift")
6930 (set_attr "length" "4")])
6932 (define_insn "vdepi_ior"
6933 [(set (match_operand:SI 0 "register_operand" "=r")
6934 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6935 (minus:SI (const_int 31)
6936 (match_operand:SI 2 "register_operand" "q")))
6937 (match_operand:SI 3 "register_operand" "0")))]
6938 ; accept ...0001...1, can this be generalized?
6939 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6942 int x = INTVAL (operands[1]);
6943 operands[2] = GEN_INT (exact_log2 (x + 1));
6944 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6946 [(set_attr "type" "shift")
6947 (set_attr "length" "4")])
6949 (define_insn "vdepi_and"
6950 [(set (match_operand:SI 0 "register_operand" "=r")
6951 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6952 (minus:SI (const_int 31)
6953 (match_operand:SI 2 "register_operand" "q")))
6954 (match_operand:SI 3 "register_operand" "0")))]
6955 ; this can be generalized...!
6956 "INTVAL (operands[1]) == -2"
6959 int x = INTVAL (operands[1]);
6960 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6961 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6963 [(set_attr "type" "shift")
6964 (set_attr "length" "4")])
6966 (define_expand "ashldi3"
6967 [(set (match_operand:DI 0 "register_operand" "")
6968 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6969 (match_operand:DI 2 "arith32_operand" "")))]
6973 if (GET_CODE (operands[2]) != CONST_INT)
6975 rtx temp = gen_reg_rtx (DImode);
6976 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6977 if (GET_CODE (operands[1]) == CONST_INT)
6978 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6980 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6983 /* Make sure both inputs are not constants,
6984 there are no patterns for that. */
6985 operands[1] = force_reg (DImode, operands[1]);
6989 [(set (match_operand:DI 0 "register_operand" "=r")
6990 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6991 (match_operand:DI 2 "const_int_operand" "n")))]
6993 "depd,z %1,%p2,%Q2,%0"
6994 [(set_attr "type" "shift")
6995 (set_attr "length" "4")])
6997 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6998 ; Doing it like this makes slightly better code since reload can
6999 ; replace a register with a known value in range -16..15 with a
7000 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
7001 ; but since we have no more CONST_OK... characters, that is not
7003 (define_insn "zvdep64"
7004 [(set (match_operand:DI 0 "register_operand" "=r,r")
7005 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
7006 (minus:DI (const_int 63)
7007 (match_operand:DI 2 "register_operand" "q,q"))))]
7010 depd,z %1,%%sar,64,%0
7011 depdi,z %1,%%sar,64,%0"
7012 [(set_attr "type" "shift,shift")
7013 (set_attr "length" "4,4")])
7015 (define_insn "zvdep_imm64"
7016 [(set (match_operand:DI 0 "register_operand" "=r")
7017 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
7018 (minus:DI (const_int 63)
7019 (match_operand:DI 2 "register_operand" "q"))))]
7023 int x = INTVAL (operands[1]);
7024 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
7025 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
7026 return \"depdi,z %1,%%sar,%2,%0\";
7028 [(set_attr "type" "shift")
7029 (set_attr "length" "4")])
7032 [(set (match_operand:DI 0 "register_operand" "=r")
7033 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
7034 (minus:DI (const_int 63)
7035 (match_operand:DI 2 "register_operand" "q")))
7036 (match_operand:DI 3 "register_operand" "0")))]
7037 ; accept ...0001...1, can this be generalized?
7038 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
7041 int x = INTVAL (operands[1]);
7042 operands[2] = GEN_INT (exact_log2 (x + 1));
7043 return \"depdi -1,%%sar,%2,%0\";
7045 [(set_attr "type" "shift")
7046 (set_attr "length" "4")])
7049 [(set (match_operand:DI 0 "register_operand" "=r")
7050 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
7051 (minus:DI (const_int 63)
7052 (match_operand:DI 2 "register_operand" "q")))
7053 (match_operand:DI 3 "register_operand" "0")))]
7054 ; this can be generalized...!
7055 "TARGET_64BIT && INTVAL (operands[1]) == -2"
7058 int x = INTVAL (operands[1]);
7059 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7060 return \"depdi 0,%%sar,%2,%0\";
7062 [(set_attr "type" "shift")
7063 (set_attr "length" "4")])
7065 (define_expand "ashrsi3"
7066 [(set (match_operand:SI 0 "register_operand" "")
7067 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
7068 (match_operand:SI 2 "arith32_operand" "")))]
7072 if (GET_CODE (operands[2]) != CONST_INT)
7074 rtx temp = gen_reg_rtx (SImode);
7075 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
7076 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
7082 [(set (match_operand:SI 0 "register_operand" "=r")
7083 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7084 (match_operand:SI 2 "const_int_operand" "n")))]
7086 "{extrs|extrw,s} %1,%P2,%L2,%0"
7087 [(set_attr "type" "shift")
7088 (set_attr "length" "4")])
7090 (define_insn "vextrs32"
7091 [(set (match_operand:SI 0 "register_operand" "=r")
7092 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7093 (minus:SI (const_int 31)
7094 (match_operand:SI 2 "register_operand" "q"))))]
7096 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
7097 [(set_attr "type" "shift")
7098 (set_attr "length" "4")])
7100 (define_expand "ashrdi3"
7101 [(set (match_operand:DI 0 "register_operand" "")
7102 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7103 (match_operand:DI 2 "arith32_operand" "")))]
7107 if (GET_CODE (operands[2]) != CONST_INT)
7109 rtx temp = gen_reg_rtx (DImode);
7110 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7111 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
7117 [(set (match_operand:DI 0 "register_operand" "=r")
7118 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7119 (match_operand:DI 2 "const_int_operand" "n")))]
7121 "extrd,s %1,%p2,%Q2,%0"
7122 [(set_attr "type" "shift")
7123 (set_attr "length" "4")])
7125 (define_insn "vextrs64"
7126 [(set (match_operand:DI 0 "register_operand" "=r")
7127 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7128 (minus:DI (const_int 63)
7129 (match_operand:DI 2 "register_operand" "q"))))]
7131 "extrd,s %1,%%sar,64,%0"
7132 [(set_attr "type" "shift")
7133 (set_attr "length" "4")])
7135 (define_insn "lshrsi3"
7136 [(set (match_operand:SI 0 "register_operand" "=r,r")
7137 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
7138 (match_operand:SI 2 "arith32_operand" "q,n")))]
7141 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
7142 {extru|extrw,u} %1,%P2,%L2,%0"
7143 [(set_attr "type" "shift")
7144 (set_attr "length" "4")])
7146 (define_insn "lshrdi3"
7147 [(set (match_operand:DI 0 "register_operand" "=r,r")
7148 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
7149 (match_operand:DI 2 "arith32_operand" "q,n")))]
7152 shrpd %%r0,%1,%%sar,%0
7153 extrd,u %1,%p2,%Q2,%0"
7154 [(set_attr "type" "shift")
7155 (set_attr "length" "4")])
7157 (define_insn "rotrsi3"
7158 [(set (match_operand:SI 0 "register_operand" "=r,r")
7159 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
7160 (match_operand:SI 2 "arith32_operand" "q,n")))]
7164 if (GET_CODE (operands[2]) == CONST_INT)
7166 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
7167 return \"{shd|shrpw} %1,%1,%2,%0\";
7170 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
7172 [(set_attr "type" "shift")
7173 (set_attr "length" "4")])
7175 (define_expand "rotlsi3"
7176 [(set (match_operand:SI 0 "register_operand" "")
7177 (rotate:SI (match_operand:SI 1 "register_operand" "")
7178 (match_operand:SI 2 "arith32_operand" "")))]
7182 if (GET_CODE (operands[2]) != CONST_INT)
7184 rtx temp = gen_reg_rtx (SImode);
7185 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
7186 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
7189 /* Else expand normally. */
7193 [(set (match_operand:SI 0 "register_operand" "=r")
7194 (rotate:SI (match_operand:SI 1 "register_operand" "r")
7195 (match_operand:SI 2 "const_int_operand" "n")))]
7199 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
7200 return \"{shd|shrpw} %1,%1,%2,%0\";
7202 [(set_attr "type" "shift")
7203 (set_attr "length" "4")])
7206 [(set (match_operand:SI 0 "register_operand" "=r")
7207 (match_operator:SI 5 "plus_xor_ior_operator"
7208 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
7209 (match_operand:SI 3 "const_int_operand" "n"))
7210 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7211 (match_operand:SI 4 "const_int_operand" "n"))]))]
7212 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7213 "{shd|shrpw} %1,%2,%4,%0"
7214 [(set_attr "type" "shift")
7215 (set_attr "length" "4")])
7218 [(set (match_operand:SI 0 "register_operand" "=r")
7219 (match_operator:SI 5 "plus_xor_ior_operator"
7220 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7221 (match_operand:SI 4 "const_int_operand" "n"))
7222 (ashift:SI (match_operand:SI 1 "register_operand" "r")
7223 (match_operand:SI 3 "const_int_operand" "n"))]))]
7224 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7225 "{shd|shrpw} %1,%2,%4,%0"
7226 [(set_attr "type" "shift")
7227 (set_attr "length" "4")])
7230 [(set (match_operand:SI 0 "register_operand" "=r")
7231 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
7232 (match_operand:SI 2 "const_int_operand" ""))
7233 (match_operand:SI 3 "const_int_operand" "")))]
7234 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
7237 int cnt = INTVAL (operands[2]) & 31;
7238 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
7239 operands[2] = GEN_INT (31 - cnt);
7240 return \"{zdep|depw,z} %1,%2,%3,%0\";
7242 [(set_attr "type" "shift")
7243 (set_attr "length" "4")])
7245 ;; Unconditional and other jump instructions.
7247 ;; This is used for most returns.
7248 (define_insn "return_internal"
7255 return \"bve%* (%%r2)\";
7256 return \"bv%* %%r0(%%r2)\";
7258 [(set_attr "type" "branch")
7259 (set_attr "length" "4")])
7261 ;; This is used for eh returns which bypass the return stub.
7262 (define_insn "return_external_pic"
7264 (clobber (reg:SI 1))
7266 "!TARGET_NO_SPACE_REGS
7268 && flag_pic && current_function_calls_eh_return"
7269 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
7270 [(set_attr "type" "branch")
7271 (set_attr "length" "12")])
7273 (define_expand "prologue"
7276 "hppa_expand_prologue ();DONE;")
7278 (define_expand "sibcall_epilogue"
7283 hppa_expand_epilogue ();
7287 (define_expand "epilogue"
7294 /* Try to use the trivial return first. Else use the full epilogue. */
7295 if (reload_completed
7296 && !frame_pointer_needed
7297 && !df_regs_ever_live_p (2)
7298 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1))
7299 x = gen_return_internal ();
7302 hppa_expand_epilogue ();
7304 /* EH returns bypass the normal return stub. Thus, we must do an
7305 interspace branch to return from functions that call eh_return.
7306 This is only a problem for returns from shared code on ports
7307 using space registers. */
7308 if (!TARGET_NO_SPACE_REGS
7310 && flag_pic && current_function_calls_eh_return)
7311 x = gen_return_external_pic ();
7313 x = gen_return_internal ();
7319 ; Used by hppa_profile_hook to load the starting address of the current
7320 ; function; operand 1 contains the address of the label in operand 3
7321 (define_insn "load_offset_label_address"
7322 [(set (match_operand:SI 0 "register_operand" "=r")
7323 (plus:SI (match_operand:SI 1 "register_operand" "r")
7324 (minus:SI (match_operand:SI 2 "" "")
7325 (label_ref:SI (match_operand 3 "" "")))))]
7328 [(set_attr "type" "multi")
7329 (set_attr "length" "4")])
7331 ; Output a code label and load its address.
7332 (define_insn "lcla1"
7333 [(set (match_operand:SI 0 "register_operand" "=r")
7334 (label_ref:SI (match_operand 1 "" "")))
7339 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
7340 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7341 CODE_LABEL_NUMBER (operands[1]));
7344 [(set_attr "type" "multi")
7345 (set_attr "length" "8")])
7347 (define_insn "lcla2"
7348 [(set (match_operand:SI 0 "register_operand" "=r")
7349 (label_ref:SI (match_operand 1 "" "")))
7354 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7355 CODE_LABEL_NUMBER (operands[1]));
7358 [(set_attr "type" "move")
7359 (set_attr "length" "4")])
7361 (define_insn "blockage"
7362 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
7365 [(set_attr "length" "0")])
7368 [(set (pc) (label_ref (match_operand 0 "" "")))]
7372 /* An unconditional branch which can reach its target. */
7373 if (get_attr_length (insn) < 16)
7376 return output_lbranch (operands[0], insn, 1);
7378 [(set_attr "type" "uncond_branch")
7379 (set_attr "pa_combine_type" "uncond_branch")
7380 (set (attr "length")
7381 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7382 (if_then_else (lt (abs (minus (match_dup 0)
7383 (plus (pc) (const_int 8))))
7384 (const_int MAX_12BIT_OFFSET))
7387 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7388 (const_int MAX_17BIT_OFFSET))
7390 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7392 (eq (symbol_ref "flag_pic") (const_int 0))
7396 ;;; Hope this is only within a function...
7397 (define_insn "indirect_jump"
7398 [(set (pc) (match_operand 0 "register_operand" "r"))]
7399 "GET_MODE (operands[0]) == word_mode"
7401 [(set_attr "type" "branch")
7402 (set_attr "length" "4")])
7404 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7405 ;;; SOM target doesn't allow branching to a label inside a function.
7406 ;;; We also don't correctly compute branch distances for labels
7407 ;;; outside the current function. Thus, we use an indirect jump can't
7408 ;;; be optimized to a direct jump for all targets. We assume that
7409 ;;; the branch target is in the same space (i.e., nested function
7410 ;;; jumping to a label in an outer function in the same translation
7412 (define_expand "nonlocal_goto"
7413 [(use (match_operand 0 "general_operand" ""))
7414 (use (match_operand 1 "general_operand" ""))
7415 (use (match_operand 2 "general_operand" ""))
7416 (use (match_operand 3 "general_operand" ""))]
7419 rtx lab = operands[1];
7420 rtx stack = operands[2];
7421 rtx fp = operands[3];
7423 lab = copy_to_reg (lab);
7425 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7426 gen_rtx_MEM (BLKmode,
7427 gen_rtx_SCRATCH (VOIDmode))));
7428 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7429 gen_rtx_MEM (BLKmode,
7430 hard_frame_pointer_rtx)));
7432 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7433 instead of the hard_frame_pointer_rtx in the save area. As a
7434 result, an extra instruction is needed to adjust for the offset
7435 of the virtual stack variables and the frame pointer. */
7436 if (GET_CODE (fp) != REG)
7437 fp = force_reg (Pmode, fp);
7438 emit_move_insn (virtual_stack_vars_rtx, fp);
7440 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7442 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7443 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7445 /* Nonlocal goto jumps are only used between functions in the same
7446 translation unit. Thus, we can avoid the extra overhead of an
7448 emit_jump_insn (gen_indirect_goto (lab));
7453 (define_insn "indirect_goto"
7454 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7455 "GET_MODE (operands[0]) == word_mode"
7457 [(set_attr "type" "branch")
7458 (set_attr "length" "4")])
7460 ;;; This jump is used in branch tables where the insn length is fixed.
7461 ;;; The length of this insn is adjusted if the delay slot is not filled.
7462 (define_insn "short_jump"
7463 [(set (pc) (label_ref (match_operand 0 "" "")))
7467 [(set_attr "type" "btable_branch")
7468 (set_attr "length" "4")])
7470 ;; Subroutines of "casesi".
7471 ;; operand 0 is index
7472 ;; operand 1 is the minimum bound
7473 ;; operand 2 is the maximum bound - minimum bound + 1
7474 ;; operand 3 is CODE_LABEL for the table;
7475 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7477 (define_expand "casesi"
7478 [(match_operand:SI 0 "general_operand" "")
7479 (match_operand:SI 1 "const_int_operand" "")
7480 (match_operand:SI 2 "const_int_operand" "")
7481 (match_operand 3 "" "")
7482 (match_operand 4 "" "")]
7486 if (GET_CODE (operands[0]) != REG)
7487 operands[0] = force_reg (SImode, operands[0]);
7489 if (operands[1] != const0_rtx)
7491 rtx index = gen_reg_rtx (SImode);
7493 operands[1] = GEN_INT (-INTVAL (operands[1]));
7494 if (!INT_14_BITS (operands[1]))
7495 operands[1] = force_reg (SImode, operands[1]);
7496 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7497 operands[0] = index;
7500 /* In 64bit mode we must make sure to wipe the upper bits of the register
7501 just in case the addition overflowed or we had random bits in the
7502 high part of the register. */
7505 rtx index = gen_reg_rtx (DImode);
7507 emit_insn (gen_extendsidi2 (index, operands[0]));
7508 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
7511 if (!INT_5_BITS (operands[2]))
7512 operands[2] = force_reg (SImode, operands[2]);
7514 /* This branch prevents us finding an insn for the delay slot of the
7515 following vectored branch. It might be possible to use the delay
7516 slot if an index value of -1 was used to transfer to the out-of-range
7517 label. In order to do this, we would have to output the -1 vector
7518 element after the delay insn. The casesi output code would have to
7519 check if the casesi insn is in a delay branch sequence and output
7520 the delay insn if one is found. If this was done, then it might
7521 then be worthwhile to split the casesi patterns to improve scheduling.
7522 However, it's not clear that all this extra complexity is worth
7524 emit_insn (gen_cmpsi (operands[0], operands[2]));
7525 emit_jump_insn (gen_bgtu (operands[4]));
7527 if (TARGET_BIG_SWITCH)
7530 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7532 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7534 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7537 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7541 ;;; The rtl for this pattern doesn't accurately describe what the insn
7542 ;;; actually does, particularly when case-vector elements are exploded
7543 ;;; in pa_reorg. However, the initial SET in these patterns must show
7544 ;;; the connection of the insn to the following jump table.
7545 (define_insn "casesi0"
7546 [(set (pc) (mem:SI (plus:SI
7547 (mult:SI (match_operand:SI 0 "register_operand" "r")
7549 (label_ref (match_operand 1 "" "")))))]
7551 "blr,n %0,%%r0\;nop"
7552 [(set_attr "type" "multi")
7553 (set_attr "length" "8")])
7555 ;;; 32-bit code, absolute branch table.
7556 (define_insn "casesi32"
7557 [(set (pc) (mem:SI (plus:SI
7558 (mult:SI (match_operand:SI 0 "register_operand" "r")
7560 (label_ref (match_operand 1 "" "")))))
7561 (clobber (match_scratch:SI 2 "=&r"))]
7563 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7564 [(set_attr "type" "multi")
7565 (set_attr "length" "16")])
7567 ;;; 32-bit code, relative branch table.
7568 (define_insn "casesi32p"
7569 [(set (pc) (mem:SI (plus:SI
7570 (mult:SI (match_operand:SI 0 "register_operand" "r")
7572 (label_ref (match_operand 1 "" "")))))
7573 (clobber (match_scratch:SI 2 "=&r"))
7574 (clobber (match_scratch:SI 3 "=&r"))]
7576 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7577 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7578 [(set_attr "type" "multi")
7579 (set (attr "length")
7580 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7584 ;;; 64-bit code, 32-bit relative branch table.
7585 (define_insn "casesi64p"
7586 [(set (pc) (mem:DI (plus:DI
7587 (mult:DI (sign_extend:DI
7588 (match_operand:SI 0 "register_operand" "r"))
7590 (label_ref (match_operand 1 "" "")))))
7591 (clobber (match_scratch:DI 2 "=&r"))
7592 (clobber (match_scratch:DI 3 "=&r"))]
7594 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7595 add,l %2,%3,%3\;bv,n %%r0(%3)"
7596 [(set_attr "type" "multi")
7597 (set_attr "length" "24")])
7601 ;;- jump to subroutine
7603 (define_expand "call"
7604 [(parallel [(call (match_operand:SI 0 "" "")
7605 (match_operand 1 "" ""))
7606 (clobber (reg:SI 2))])]
7611 rtx nb = operands[1];
7613 if (TARGET_PORTABLE_RUNTIME)
7614 op = force_reg (SImode, XEXP (operands[0], 0));
7616 op = XEXP (operands[0], 0);
7620 if (!virtuals_instantiated)
7621 emit_move_insn (arg_pointer_rtx,
7622 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7626 /* The loop pass can generate new libcalls after the virtual
7627 registers are instantiated when fpregs are disabled because
7628 the only method that we have for doing DImode multiplication
7629 is with a libcall. This could be trouble if we haven't
7630 allocated enough space for the outgoing arguments. */
7631 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
7633 emit_move_insn (arg_pointer_rtx,
7634 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7635 GEN_INT (STACK_POINTER_OFFSET + 64)));
7639 /* Use two different patterns for calls to explicitly named functions
7640 and calls through function pointers. This is necessary as these two
7641 types of calls use different calling conventions, and CSE might try
7642 to change the named call into an indirect call in some cases (using
7643 two patterns keeps CSE from performing this optimization).
7645 We now use even more call patterns as there was a subtle bug in
7646 attempting to restore the pic register after a call using a simple
7647 move insn. During reload, a instruction involving a pseudo register
7648 with no explicit dependence on the PIC register can be converted
7649 to an equivalent load from memory using the PIC register. If we
7650 emit a simple move to restore the PIC register in the initial rtl
7651 generation, then it can potentially be repositioned during scheduling.
7652 and an instruction that eventually uses the PIC register may end up
7653 between the call and the PIC register restore.
7655 This only worked because there is a post call group of instructions
7656 that are scheduled with the call. These instructions are included
7657 in the same basic block as the call. However, calls can throw in
7658 C++ code and a basic block has to terminate at the call if the call
7659 can throw. This results in the PIC register restore being scheduled
7660 independently from the call. So, we now hide the save and restore
7661 of the PIC register in the call pattern until after reload. Then,
7662 we split the moves out. A small side benefit is that we now don't
7663 need to have a use of the PIC register in the return pattern and
7664 the final save/restore operation is not needed.
7666 I elected to just clobber %r4 in the PIC patterns and use it instead
7667 of trying to force hppa_pic_save_rtx () to a callee saved register.
7668 This might have required a new register class and constraint. It
7669 was also simpler to just handle the restore from a register than a
7673 if (GET_CODE (op) == SYMBOL_REF)
7674 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7677 op = force_reg (word_mode, op);
7678 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7683 if (GET_CODE (op) == SYMBOL_REF)
7686 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7688 call_insn = emit_call_insn (gen_call_symref (op, nb));
7692 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7694 emit_move_insn (tmpreg, force_reg (word_mode, op));
7696 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7698 call_insn = emit_call_insn (gen_call_reg (nb));
7705 ;; We use function calls to set the attribute length of calls and millicode
7706 ;; calls. This is necessary because of the large variety of call sequences.
7707 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7708 ;; we need the same calculation in several places, maintenance becomes a
7711 ;; However, this has a subtle impact on branch shortening. When the
7712 ;; expression used to set the length attribute of an instruction depends
7713 ;; on a relative address (e.g., pc or a branch address), genattrtab
7714 ;; notes that the insn's length is variable, and attempts to determine a
7715 ;; worst-case default length and code to compute an insn's current length.
7717 ;; The use of a function call hides the variable dependence of our calls
7718 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7719 ;; as variable and it only generates code for the default case using our
7720 ;; function call. Because of this, calls and millicode calls have a fixed
7721 ;; length in the branch shortening pass, and some branches will use a longer
7722 ;; code sequence than necessary. However, the length of any given call
7723 ;; will still reflect its final code location and it may be shorter than
7724 ;; the initial length estimate.
7726 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7727 ;; in the set. However, when genattrtab hits a function call in its attempt
7728 ;; to compute the default length, it marks the result as unknown and sets
7729 ;; the default result to MAX_INT ;-( One possible fix that would allow
7730 ;; calls to participate in branch shortening would be to make the call to
7731 ;; insn_default_length a target option. Then, we could massage unknown
7732 ;; results. Another fix might be to change genattrtab so that it just does
7733 ;; the call in the variable case as it already does for the fixed case.
7735 (define_insn "call_symref"
7736 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7737 (match_operand 1 "" "i"))
7738 (clobber (reg:SI 1))
7739 (clobber (reg:SI 2))
7740 (use (const_int 0))]
7741 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7744 output_arg_descriptor (insn);
7745 return output_call (insn, operands[0], 0);
7747 [(set_attr "type" "call")
7748 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7750 (define_insn "call_symref_pic"
7751 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7752 (match_operand 1 "" "i"))
7753 (clobber (reg:SI 1))
7754 (clobber (reg:SI 2))
7755 (clobber (reg:SI 4))
7757 (use (const_int 0))]
7758 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7761 output_arg_descriptor (insn);
7762 return output_call (insn, operands[0], 0);
7764 [(set_attr "type" "call")
7765 (set (attr "length")
7766 (plus (symbol_ref "attr_length_call (insn, 0)")
7767 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7769 ;; Split out the PIC register save and restore after reload. This is
7770 ;; done only if the function returns. As the split is done after reload,
7771 ;; there are some situations in which we unnecessarily save and restore
7772 ;; %r4. This happens when there is a single call and the PIC register
7773 ;; is "dead" after the call. This isn't easy to fix as the usage of
7774 ;; the PIC register isn't completely determined until the reload pass.
7776 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7777 (match_operand 1 "" ""))
7778 (clobber (reg:SI 1))
7779 (clobber (reg:SI 2))
7780 (clobber (reg:SI 4))
7782 (use (const_int 0))])]
7783 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7785 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7786 [(set (reg:SI 4) (reg:SI 19))
7787 (parallel [(call (mem:SI (match_dup 0))
7789 (clobber (reg:SI 1))
7790 (clobber (reg:SI 2))
7792 (use (const_int 0))])
7793 (set (reg:SI 19) (reg:SI 4))]
7796 ;; Remove the clobber of register 4 when optimizing. This has to be
7797 ;; done with a peephole optimization rather than a split because the
7798 ;; split sequence for a call must be longer than one instruction.
7800 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7801 (match_operand 1 "" ""))
7802 (clobber (reg:SI 1))
7803 (clobber (reg:SI 2))
7804 (clobber (reg:SI 4))
7806 (use (const_int 0))])]
7807 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7808 [(parallel [(call (mem:SI (match_dup 0))
7810 (clobber (reg:SI 1))
7811 (clobber (reg:SI 2))
7813 (use (const_int 0))])]
7816 (define_insn "*call_symref_pic_post_reload"
7817 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7818 (match_operand 1 "" "i"))
7819 (clobber (reg:SI 1))
7820 (clobber (reg:SI 2))
7822 (use (const_int 0))]
7823 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7826 output_arg_descriptor (insn);
7827 return output_call (insn, operands[0], 0);
7829 [(set_attr "type" "call")
7830 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7832 ;; This pattern is split if it is necessary to save and restore the
7834 (define_insn "call_symref_64bit"
7835 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7836 (match_operand 1 "" "i"))
7837 (clobber (reg:DI 1))
7838 (clobber (reg:DI 2))
7839 (clobber (reg:DI 4))
7842 (use (const_int 0))]
7846 output_arg_descriptor (insn);
7847 return output_call (insn, operands[0], 0);
7849 [(set_attr "type" "call")
7850 (set (attr "length")
7851 (plus (symbol_ref "attr_length_call (insn, 0)")
7852 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7854 ;; Split out the PIC register save and restore after reload. This is
7855 ;; done only if the function returns. As the split is done after reload,
7856 ;; there are some situations in which we unnecessarily save and restore
7857 ;; %r4. This happens when there is a single call and the PIC register
7858 ;; is "dead" after the call. This isn't easy to fix as the usage of
7859 ;; the PIC register isn't completely determined until the reload pass.
7861 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7862 (match_operand 1 "" ""))
7863 (clobber (reg:DI 1))
7864 (clobber (reg:DI 2))
7865 (clobber (reg:DI 4))
7868 (use (const_int 0))])]
7871 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7872 [(set (reg:DI 4) (reg:DI 27))
7873 (parallel [(call (mem:SI (match_dup 0))
7875 (clobber (reg:DI 1))
7876 (clobber (reg:DI 2))
7879 (use (const_int 0))])
7880 (set (reg:DI 27) (reg:DI 4))]
7883 ;; Remove the clobber of register 4 when optimizing. This has to be
7884 ;; done with a peephole optimization rather than a split because the
7885 ;; split sequence for a call must be longer than one instruction.
7887 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7888 (match_operand 1 "" ""))
7889 (clobber (reg:DI 1))
7890 (clobber (reg:DI 2))
7891 (clobber (reg:DI 4))
7894 (use (const_int 0))])]
7895 "TARGET_64BIT && reload_completed"
7896 [(parallel [(call (mem:SI (match_dup 0))
7898 (clobber (reg:DI 1))
7899 (clobber (reg:DI 2))
7902 (use (const_int 0))])]
7905 (define_insn "*call_symref_64bit_post_reload"
7906 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7907 (match_operand 1 "" "i"))
7908 (clobber (reg:DI 1))
7909 (clobber (reg:DI 2))
7912 (use (const_int 0))]
7916 output_arg_descriptor (insn);
7917 return output_call (insn, operands[0], 0);
7919 [(set_attr "type" "call")
7920 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7922 (define_insn "call_reg"
7923 [(call (mem:SI (reg:SI 22))
7924 (match_operand 0 "" "i"))
7925 (clobber (reg:SI 1))
7926 (clobber (reg:SI 2))
7927 (use (const_int 1))]
7931 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7933 [(set_attr "type" "dyncall")
7934 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7936 ;; This pattern is split if it is necessary to save and restore the
7938 (define_insn "call_reg_pic"
7939 [(call (mem:SI (reg:SI 22))
7940 (match_operand 0 "" "i"))
7941 (clobber (reg:SI 1))
7942 (clobber (reg:SI 2))
7943 (clobber (reg:SI 4))
7945 (use (const_int 1))]
7949 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7951 [(set_attr "type" "dyncall")
7952 (set (attr "length")
7953 (plus (symbol_ref "attr_length_indirect_call (insn)")
7954 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7956 ;; Split out the PIC register save and restore after reload. This is
7957 ;; done only if the function returns. As the split is done after reload,
7958 ;; there are some situations in which we unnecessarily save and restore
7959 ;; %r4. This happens when there is a single call and the PIC register
7960 ;; is "dead" after the call. This isn't easy to fix as the usage of
7961 ;; the PIC register isn't completely determined until the reload pass.
7963 [(parallel [(call (mem:SI (reg:SI 22))
7964 (match_operand 0 "" ""))
7965 (clobber (reg:SI 1))
7966 (clobber (reg:SI 2))
7967 (clobber (reg:SI 4))
7969 (use (const_int 1))])]
7972 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7973 [(set (reg:SI 4) (reg:SI 19))
7974 (parallel [(call (mem:SI (reg:SI 22))
7976 (clobber (reg:SI 1))
7977 (clobber (reg:SI 2))
7979 (use (const_int 1))])
7980 (set (reg:SI 19) (reg:SI 4))]
7983 ;; Remove the clobber of register 4 when optimizing. This has to be
7984 ;; done with a peephole optimization rather than a split because the
7985 ;; split sequence for a call must be longer than one instruction.
7987 [(parallel [(call (mem:SI (reg:SI 22))
7988 (match_operand 0 "" ""))
7989 (clobber (reg:SI 1))
7990 (clobber (reg:SI 2))
7991 (clobber (reg:SI 4))
7993 (use (const_int 1))])]
7994 "!TARGET_64BIT && reload_completed"
7995 [(parallel [(call (mem:SI (reg:SI 22))
7997 (clobber (reg:SI 1))
7998 (clobber (reg:SI 2))
8000 (use (const_int 1))])]
8003 (define_insn "*call_reg_pic_post_reload"
8004 [(call (mem:SI (reg:SI 22))
8005 (match_operand 0 "" "i"))
8006 (clobber (reg:SI 1))
8007 (clobber (reg:SI 2))
8009 (use (const_int 1))]
8013 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8015 [(set_attr "type" "dyncall")
8016 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8018 ;; This pattern is split if it is necessary to save and restore the
8020 (define_insn "call_reg_64bit"
8021 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8022 (match_operand 1 "" "i"))
8023 (clobber (reg:DI 2))
8024 (clobber (reg:DI 4))
8027 (use (const_int 1))]
8031 return output_indirect_call (insn, operands[0]);
8033 [(set_attr "type" "dyncall")
8034 (set (attr "length")
8035 (plus (symbol_ref "attr_length_indirect_call (insn)")
8036 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8038 ;; Split out the PIC register save and restore after reload. This is
8039 ;; done only if the function returns. As the split is done after reload,
8040 ;; there are some situations in which we unnecessarily save and restore
8041 ;; %r4. This happens when there is a single call and the PIC register
8042 ;; is "dead" after the call. This isn't easy to fix as the usage of
8043 ;; the PIC register isn't completely determined until the reload pass.
8045 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8046 (match_operand 1 "" ""))
8047 (clobber (reg:DI 2))
8048 (clobber (reg:DI 4))
8051 (use (const_int 1))])]
8054 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8055 [(set (reg:DI 4) (reg:DI 27))
8056 (parallel [(call (mem:SI (match_dup 0))
8058 (clobber (reg:DI 2))
8061 (use (const_int 1))])
8062 (set (reg:DI 27) (reg:DI 4))]
8065 ;; Remove the clobber of register 4 when optimizing. This has to be
8066 ;; done with a peephole optimization rather than a split because the
8067 ;; split sequence for a call must be longer than one instruction.
8069 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8070 (match_operand 1 "" ""))
8071 (clobber (reg:DI 2))
8072 (clobber (reg:DI 4))
8075 (use (const_int 1))])]
8076 "TARGET_64BIT && reload_completed"
8077 [(parallel [(call (mem:SI (match_dup 0))
8079 (clobber (reg:DI 2))
8082 (use (const_int 1))])]
8085 (define_insn "*call_reg_64bit_post_reload"
8086 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8087 (match_operand 1 "" "i"))
8088 (clobber (reg:DI 2))
8091 (use (const_int 1))]
8095 return output_indirect_call (insn, operands[0]);
8097 [(set_attr "type" "dyncall")
8098 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8100 (define_expand "call_value"
8101 [(parallel [(set (match_operand 0 "" "")
8102 (call (match_operand:SI 1 "" "")
8103 (match_operand 2 "" "")))
8104 (clobber (reg:SI 2))])]
8109 rtx dst = operands[0];
8110 rtx nb = operands[2];
8112 if (TARGET_PORTABLE_RUNTIME)
8113 op = force_reg (SImode, XEXP (operands[1], 0));
8115 op = XEXP (operands[1], 0);
8119 if (!virtuals_instantiated)
8120 emit_move_insn (arg_pointer_rtx,
8121 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8125 /* The loop pass can generate new libcalls after the virtual
8126 registers are instantiated when fpregs are disabled because
8127 the only method that we have for doing DImode multiplication
8128 is with a libcall. This could be trouble if we haven't
8129 allocated enough space for the outgoing arguments. */
8130 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8132 emit_move_insn (arg_pointer_rtx,
8133 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8134 GEN_INT (STACK_POINTER_OFFSET + 64)));
8138 /* Use two different patterns for calls to explicitly named functions
8139 and calls through function pointers. This is necessary as these two
8140 types of calls use different calling conventions, and CSE might try
8141 to change the named call into an indirect call in some cases (using
8142 two patterns keeps CSE from performing this optimization).
8144 We now use even more call patterns as there was a subtle bug in
8145 attempting to restore the pic register after a call using a simple
8146 move insn. During reload, a instruction involving a pseudo register
8147 with no explicit dependence on the PIC register can be converted
8148 to an equivalent load from memory using the PIC register. If we
8149 emit a simple move to restore the PIC register in the initial rtl
8150 generation, then it can potentially be repositioned during scheduling.
8151 and an instruction that eventually uses the PIC register may end up
8152 between the call and the PIC register restore.
8154 This only worked because there is a post call group of instructions
8155 that are scheduled with the call. These instructions are included
8156 in the same basic block as the call. However, calls can throw in
8157 C++ code and a basic block has to terminate at the call if the call
8158 can throw. This results in the PIC register restore being scheduled
8159 independently from the call. So, we now hide the save and restore
8160 of the PIC register in the call pattern until after reload. Then,
8161 we split the moves out. A small side benefit is that we now don't
8162 need to have a use of the PIC register in the return pattern and
8163 the final save/restore operation is not needed.
8165 I elected to just clobber %r4 in the PIC patterns and use it instead
8166 of trying to force hppa_pic_save_rtx () to a callee saved register.
8167 This might have required a new register class and constraint. It
8168 was also simpler to just handle the restore from a register than a
8172 if (GET_CODE (op) == SYMBOL_REF)
8173 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
8176 op = force_reg (word_mode, op);
8177 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
8182 if (GET_CODE (op) == SYMBOL_REF)
8185 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
8187 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
8191 rtx tmpreg = gen_rtx_REG (word_mode, 22);
8193 emit_move_insn (tmpreg, force_reg (word_mode, op));
8195 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
8197 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
8204 (define_insn "call_val_symref"
8205 [(set (match_operand 0 "" "")
8206 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8207 (match_operand 2 "" "i")))
8208 (clobber (reg:SI 1))
8209 (clobber (reg:SI 2))
8210 (use (const_int 0))]
8211 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8214 output_arg_descriptor (insn);
8215 return output_call (insn, operands[1], 0);
8217 [(set_attr "type" "call")
8218 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8220 (define_insn "call_val_symref_pic"
8221 [(set (match_operand 0 "" "")
8222 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8223 (match_operand 2 "" "i")))
8224 (clobber (reg:SI 1))
8225 (clobber (reg:SI 2))
8226 (clobber (reg:SI 4))
8228 (use (const_int 0))]
8229 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8232 output_arg_descriptor (insn);
8233 return output_call (insn, operands[1], 0);
8235 [(set_attr "type" "call")
8236 (set (attr "length")
8237 (plus (symbol_ref "attr_length_call (insn, 0)")
8238 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8240 ;; Split out the PIC register save and restore after reload. This is
8241 ;; done only if the function returns. As the split is done after reload,
8242 ;; there are some situations in which we unnecessarily save and restore
8243 ;; %r4. This happens when there is a single call and the PIC register
8244 ;; is "dead" after the call. This isn't easy to fix as the usage of
8245 ;; the PIC register isn't completely determined until the reload pass.
8247 [(parallel [(set (match_operand 0 "" "")
8248 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8249 (match_operand 2 "" "")))
8250 (clobber (reg:SI 1))
8251 (clobber (reg:SI 2))
8252 (clobber (reg:SI 4))
8254 (use (const_int 0))])]
8255 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
8257 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8258 [(set (reg:SI 4) (reg:SI 19))
8259 (parallel [(set (match_dup 0)
8260 (call (mem:SI (match_dup 1))
8262 (clobber (reg:SI 1))
8263 (clobber (reg:SI 2))
8265 (use (const_int 0))])
8266 (set (reg:SI 19) (reg:SI 4))]
8269 ;; Remove the clobber of register 4 when optimizing. This has to be
8270 ;; done with a peephole optimization rather than a split because the
8271 ;; split sequence for a call must be longer than one instruction.
8273 [(parallel [(set (match_operand 0 "" "")
8274 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8275 (match_operand 2 "" "")))
8276 (clobber (reg:SI 1))
8277 (clobber (reg:SI 2))
8278 (clobber (reg:SI 4))
8280 (use (const_int 0))])]
8281 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8282 [(parallel [(set (match_dup 0)
8283 (call (mem:SI (match_dup 1))
8285 (clobber (reg:SI 1))
8286 (clobber (reg:SI 2))
8288 (use (const_int 0))])]
8291 (define_insn "*call_val_symref_pic_post_reload"
8292 [(set (match_operand 0 "" "")
8293 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8294 (match_operand 2 "" "i")))
8295 (clobber (reg:SI 1))
8296 (clobber (reg:SI 2))
8298 (use (const_int 0))]
8299 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8302 output_arg_descriptor (insn);
8303 return output_call (insn, operands[1], 0);
8305 [(set_attr "type" "call")
8306 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8308 ;; This pattern is split if it is necessary to save and restore the
8310 (define_insn "call_val_symref_64bit"
8311 [(set (match_operand 0 "" "")
8312 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8313 (match_operand 2 "" "i")))
8314 (clobber (reg:DI 1))
8315 (clobber (reg:DI 2))
8316 (clobber (reg:DI 4))
8319 (use (const_int 0))]
8323 output_arg_descriptor (insn);
8324 return output_call (insn, operands[1], 0);
8326 [(set_attr "type" "call")
8327 (set (attr "length")
8328 (plus (symbol_ref "attr_length_call (insn, 0)")
8329 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8331 ;; Split out the PIC register save and restore after reload. This is
8332 ;; done only if the function returns. As the split is done after reload,
8333 ;; there are some situations in which we unnecessarily save and restore
8334 ;; %r4. This happens when there is a single call and the PIC register
8335 ;; is "dead" after the call. This isn't easy to fix as the usage of
8336 ;; the PIC register isn't completely determined until the reload pass.
8338 [(parallel [(set (match_operand 0 "" "")
8339 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8340 (match_operand 2 "" "")))
8341 (clobber (reg:DI 1))
8342 (clobber (reg:DI 2))
8343 (clobber (reg:DI 4))
8346 (use (const_int 0))])]
8349 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8350 [(set (reg:DI 4) (reg:DI 27))
8351 (parallel [(set (match_dup 0)
8352 (call (mem:SI (match_dup 1))
8354 (clobber (reg:DI 1))
8355 (clobber (reg:DI 2))
8358 (use (const_int 0))])
8359 (set (reg:DI 27) (reg:DI 4))]
8362 ;; Remove the clobber of register 4 when optimizing. This has to be
8363 ;; done with a peephole optimization rather than a split because the
8364 ;; split sequence for a call must be longer than one instruction.
8366 [(parallel [(set (match_operand 0 "" "")
8367 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8368 (match_operand 2 "" "")))
8369 (clobber (reg:DI 1))
8370 (clobber (reg:DI 2))
8371 (clobber (reg:DI 4))
8374 (use (const_int 0))])]
8375 "TARGET_64BIT && reload_completed"
8376 [(parallel [(set (match_dup 0)
8377 (call (mem:SI (match_dup 1))
8379 (clobber (reg:DI 1))
8380 (clobber (reg:DI 2))
8383 (use (const_int 0))])]
8386 (define_insn "*call_val_symref_64bit_post_reload"
8387 [(set (match_operand 0 "" "")
8388 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8389 (match_operand 2 "" "i")))
8390 (clobber (reg:DI 1))
8391 (clobber (reg:DI 2))
8394 (use (const_int 0))]
8398 output_arg_descriptor (insn);
8399 return output_call (insn, operands[1], 0);
8401 [(set_attr "type" "call")
8402 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8404 (define_insn "call_val_reg"
8405 [(set (match_operand 0 "" "")
8406 (call (mem:SI (reg:SI 22))
8407 (match_operand 1 "" "i")))
8408 (clobber (reg:SI 1))
8409 (clobber (reg:SI 2))
8410 (use (const_int 1))]
8414 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8416 [(set_attr "type" "dyncall")
8417 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8419 ;; This pattern is split if it is necessary to save and restore the
8421 (define_insn "call_val_reg_pic"
8422 [(set (match_operand 0 "" "")
8423 (call (mem:SI (reg:SI 22))
8424 (match_operand 1 "" "i")))
8425 (clobber (reg:SI 1))
8426 (clobber (reg:SI 2))
8427 (clobber (reg:SI 4))
8429 (use (const_int 1))]
8433 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8435 [(set_attr "type" "dyncall")
8436 (set (attr "length")
8437 (plus (symbol_ref "attr_length_indirect_call (insn)")
8438 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8440 ;; Split out the PIC register save and restore after reload. This is
8441 ;; done only if the function returns. As the split is done after reload,
8442 ;; there are some situations in which we unnecessarily save and restore
8443 ;; %r4. This happens when there is a single call and the PIC register
8444 ;; is "dead" after the call. This isn't easy to fix as the usage of
8445 ;; the PIC register isn't completely determined until the reload pass.
8447 [(parallel [(set (match_operand 0 "" "")
8448 (call (mem:SI (reg:SI 22))
8449 (match_operand 1 "" "")))
8450 (clobber (reg:SI 1))
8451 (clobber (reg:SI 2))
8452 (clobber (reg:SI 4))
8454 (use (const_int 1))])]
8457 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8458 [(set (reg:SI 4) (reg:SI 19))
8459 (parallel [(set (match_dup 0)
8460 (call (mem:SI (reg:SI 22))
8462 (clobber (reg:SI 1))
8463 (clobber (reg:SI 2))
8465 (use (const_int 1))])
8466 (set (reg:SI 19) (reg:SI 4))]
8469 ;; Remove the clobber of register 4 when optimizing. This has to be
8470 ;; done with a peephole optimization rather than a split because the
8471 ;; split sequence for a call must be longer than one instruction.
8473 [(parallel [(set (match_operand 0 "" "")
8474 (call (mem:SI (reg:SI 22))
8475 (match_operand 1 "" "")))
8476 (clobber (reg:SI 1))
8477 (clobber (reg:SI 2))
8478 (clobber (reg:SI 4))
8480 (use (const_int 1))])]
8481 "!TARGET_64BIT && reload_completed"
8482 [(parallel [(set (match_dup 0)
8483 (call (mem:SI (reg:SI 22))
8485 (clobber (reg:SI 1))
8486 (clobber (reg:SI 2))
8488 (use (const_int 1))])]
8491 (define_insn "*call_val_reg_pic_post_reload"
8492 [(set (match_operand 0 "" "")
8493 (call (mem:SI (reg:SI 22))
8494 (match_operand 1 "" "i")))
8495 (clobber (reg:SI 1))
8496 (clobber (reg:SI 2))
8498 (use (const_int 1))]
8502 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8504 [(set_attr "type" "dyncall")
8505 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8507 ;; This pattern is split if it is necessary to save and restore the
8509 (define_insn "call_val_reg_64bit"
8510 [(set (match_operand 0 "" "")
8511 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8512 (match_operand 2 "" "i")))
8513 (clobber (reg:DI 2))
8514 (clobber (reg:DI 4))
8517 (use (const_int 1))]
8521 return output_indirect_call (insn, operands[1]);
8523 [(set_attr "type" "dyncall")
8524 (set (attr "length")
8525 (plus (symbol_ref "attr_length_indirect_call (insn)")
8526 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8528 ;; Split out the PIC register save and restore after reload. This is
8529 ;; done only if the function returns. As the split is done after reload,
8530 ;; there are some situations in which we unnecessarily save and restore
8531 ;; %r4. This happens when there is a single call and the PIC register
8532 ;; is "dead" after the call. This isn't easy to fix as the usage of
8533 ;; the PIC register isn't completely determined until the reload pass.
8535 [(parallel [(set (match_operand 0 "" "")
8536 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8537 (match_operand 2 "" "")))
8538 (clobber (reg:DI 2))
8539 (clobber (reg:DI 4))
8542 (use (const_int 1))])]
8545 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8546 [(set (reg:DI 4) (reg:DI 27))
8547 (parallel [(set (match_dup 0)
8548 (call (mem:SI (match_dup 1))
8550 (clobber (reg:DI 2))
8553 (use (const_int 1))])
8554 (set (reg:DI 27) (reg:DI 4))]
8557 ;; Remove the clobber of register 4 when optimizing. This has to be
8558 ;; done with a peephole optimization rather than a split because the
8559 ;; split sequence for a call must be longer than one instruction.
8561 [(parallel [(set (match_operand 0 "" "")
8562 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8563 (match_operand 2 "" "")))
8564 (clobber (reg:DI 2))
8565 (clobber (reg:DI 4))
8568 (use (const_int 1))])]
8569 "TARGET_64BIT && reload_completed"
8570 [(parallel [(set (match_dup 0)
8571 (call (mem:SI (match_dup 1))
8573 (clobber (reg:DI 2))
8576 (use (const_int 1))])]
8579 (define_insn "*call_val_reg_64bit_post_reload"
8580 [(set (match_operand 0 "" "")
8581 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8582 (match_operand 2 "" "i")))
8583 (clobber (reg:DI 2))
8586 (use (const_int 1))]
8590 return output_indirect_call (insn, operands[1]);
8592 [(set_attr "type" "dyncall")
8593 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8595 ;; Call subroutine returning any type.
8597 (define_expand "untyped_call"
8598 [(parallel [(call (match_operand 0 "" "")
8600 (match_operand 1 "" "")
8601 (match_operand 2 "" "")])]
8607 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8609 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8611 rtx set = XVECEXP (operands[2], 0, i);
8612 emit_move_insn (SET_DEST (set), SET_SRC (set));
8615 /* The optimizer does not know that the call sets the function value
8616 registers we stored in the result block. We avoid problems by
8617 claiming that all hard registers are used and clobbered at this
8619 emit_insn (gen_blockage ());
8624 (define_expand "sibcall"
8625 [(call (match_operand:SI 0 "" "")
8626 (match_operand 1 "" ""))]
8627 "!TARGET_PORTABLE_RUNTIME"
8631 rtx nb = operands[1];
8633 op = XEXP (operands[0], 0);
8637 if (!virtuals_instantiated)
8638 emit_move_insn (arg_pointer_rtx,
8639 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8643 /* The loop pass can generate new libcalls after the virtual
8644 registers are instantiated when fpregs are disabled because
8645 the only method that we have for doing DImode multiplication
8646 is with a libcall. This could be trouble if we haven't
8647 allocated enough space for the outgoing arguments. */
8648 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8650 emit_move_insn (arg_pointer_rtx,
8651 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8652 GEN_INT (STACK_POINTER_OFFSET + 64)));
8656 /* Indirect sibling calls are not allowed. */
8658 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8660 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8662 call_insn = emit_call_insn (call_insn);
8665 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8667 /* We don't have to restore the PIC register. */
8669 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8674 (define_insn "sibcall_internal_symref"
8675 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8676 (match_operand 1 "" "i"))
8677 (clobber (reg:SI 1))
8679 (use (const_int 0))]
8680 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8683 output_arg_descriptor (insn);
8684 return output_call (insn, operands[0], 1);
8686 [(set_attr "type" "call")
8687 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8689 (define_insn "sibcall_internal_symref_64bit"
8690 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8691 (match_operand 1 "" "i"))
8692 (clobber (reg:DI 1))
8694 (use (const_int 0))]
8698 output_arg_descriptor (insn);
8699 return output_call (insn, operands[0], 1);
8701 [(set_attr "type" "call")
8702 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8704 (define_expand "sibcall_value"
8705 [(set (match_operand 0 "" "")
8706 (call (match_operand:SI 1 "" "")
8707 (match_operand 2 "" "")))]
8708 "!TARGET_PORTABLE_RUNTIME"
8712 rtx nb = operands[1];
8714 op = XEXP (operands[1], 0);
8718 if (!virtuals_instantiated)
8719 emit_move_insn (arg_pointer_rtx,
8720 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8724 /* The loop pass can generate new libcalls after the virtual
8725 registers are instantiated when fpregs are disabled because
8726 the only method that we have for doing DImode multiplication
8727 is with a libcall. This could be trouble if we haven't
8728 allocated enough space for the outgoing arguments. */
8729 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8731 emit_move_insn (arg_pointer_rtx,
8732 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8733 GEN_INT (STACK_POINTER_OFFSET + 64)));
8737 /* Indirect sibling calls are not allowed. */
8740 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8743 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8745 call_insn = emit_call_insn (call_insn);
8748 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8750 /* We don't have to restore the PIC register. */
8752 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8757 (define_insn "sibcall_value_internal_symref"
8758 [(set (match_operand 0 "" "")
8759 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8760 (match_operand 2 "" "i")))
8761 (clobber (reg:SI 1))
8763 (use (const_int 0))]
8764 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8767 output_arg_descriptor (insn);
8768 return output_call (insn, operands[1], 1);
8770 [(set_attr "type" "call")
8771 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8773 (define_insn "sibcall_value_internal_symref_64bit"
8774 [(set (match_operand 0 "" "")
8775 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8776 (match_operand 2 "" "i")))
8777 (clobber (reg:DI 1))
8779 (use (const_int 0))]
8783 output_arg_descriptor (insn);
8784 return output_call (insn, operands[1], 1);
8786 [(set_attr "type" "call")
8787 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8793 [(set_attr "type" "move")
8794 (set_attr "length" "4")])
8796 ;; These are just placeholders so we know where branch tables
8798 (define_insn "begin_brtab"
8803 /* Only GAS actually supports this pseudo-op. */
8805 return \".begin_brtab\";
8809 [(set_attr "type" "move")
8810 (set_attr "length" "0")])
8812 (define_insn "end_brtab"
8817 /* Only GAS actually supports this pseudo-op. */
8819 return \".end_brtab\";
8823 [(set_attr "type" "move")
8824 (set_attr "length" "0")])
8826 ;;; EH does longjmp's from and within the data section. Thus,
8827 ;;; an interspace branch is required for the longjmp implementation.
8828 ;;; Registers r1 and r2 are used as scratch registers for the jump
8830 (define_expand "interspace_jump"
8832 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8833 (clobber (match_dup 1))])]
8837 operands[1] = gen_rtx_REG (word_mode, 2);
8841 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8842 (clobber (reg:SI 2))]
8843 "TARGET_PA_20 && !TARGET_64BIT"
8845 [(set_attr "type" "branch")
8846 (set_attr "length" "4")])
8849 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8850 (clobber (reg:SI 2))]
8851 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8853 [(set_attr "type" "branch")
8854 (set_attr "length" "4")])
8857 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8858 (clobber (reg:SI 2))]
8860 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8861 [(set_attr "type" "branch")
8862 (set_attr "length" "12")])
8865 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8866 (clobber (reg:DI 2))]
8869 [(set_attr "type" "branch")
8870 (set_attr "length" "4")])
8872 (define_expand "builtin_longjmp"
8873 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8877 /* The elements of the buffer are, in order: */
8878 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8879 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8880 POINTER_SIZE / BITS_PER_UNIT));
8881 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8882 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8883 rtx pv = gen_rtx_REG (Pmode, 1);
8885 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8886 gen_rtx_MEM (BLKmode,
8887 gen_rtx_SCRATCH (VOIDmode))));
8888 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8889 gen_rtx_MEM (BLKmode,
8890 hard_frame_pointer_rtx)));
8892 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8893 instead of the hard_frame_pointer_rtx in the save area. We need
8894 to adjust for the offset between these two values when we have
8895 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8896 pattern, the receiver performs the adjustment. */
8897 #ifdef HAVE_nonlocal_goto
8898 if (HAVE_nonlocal_goto)
8899 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8902 emit_move_insn (hard_frame_pointer_rtx, fp);
8904 /* This bit is the same as expand_builtin_longjmp. */
8905 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8906 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8907 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8909 /* Load the label we are jumping through into r1 so that we know
8910 where to look for it when we get back to setjmp's function for
8911 restoring the gp. */
8912 emit_move_insn (pv, lab);
8914 /* Prevent the insns above from being scheduled into the delay slot
8915 of the interspace jump because the space register could change. */
8916 emit_insn (gen_blockage ());
8918 emit_jump_insn (gen_interspace_jump (pv));
8923 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8924 (define_expand "extzv"
8925 [(set (match_operand 0 "register_operand" "")
8926 (zero_extract (match_operand 1 "register_operand" "")
8927 (match_operand 2 "uint32_operand" "")
8928 (match_operand 3 "uint32_operand" "")))]
8932 HOST_WIDE_INT len = INTVAL (operands[2]);
8933 HOST_WIDE_INT pos = INTVAL (operands[3]);
8935 /* PA extraction insns don't support zero length bitfields or fields
8936 extending beyond the left or right-most bits. Also, we reject lengths
8937 equal to a word as they are better handled by the move patterns. */
8938 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8941 /* From mips.md: extract_bit_field doesn't verify that our source
8942 matches the predicate, so check it again here. */
8943 if (!register_operand (operands[1], VOIDmode))
8947 emit_insn (gen_extzv_64 (operands[0], operands[1],
8948 operands[2], operands[3]));
8950 emit_insn (gen_extzv_32 (operands[0], operands[1],
8951 operands[2], operands[3]));
8955 (define_insn "extzv_32"
8956 [(set (match_operand:SI 0 "register_operand" "=r")
8957 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8958 (match_operand:SI 2 "uint5_operand" "")
8959 (match_operand:SI 3 "uint5_operand" "")))]
8961 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8962 [(set_attr "type" "shift")
8963 (set_attr "length" "4")])
8966 [(set (match_operand:SI 0 "register_operand" "=r")
8967 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8969 (match_operand:SI 2 "register_operand" "q")))]
8971 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8972 [(set_attr "type" "shift")
8973 (set_attr "length" "4")])
8975 (define_insn "extzv_64"
8976 [(set (match_operand:DI 0 "register_operand" "=r")
8977 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8978 (match_operand:DI 2 "uint32_operand" "")
8979 (match_operand:DI 3 "uint32_operand" "")))]
8981 "extrd,u %1,%3+%2-1,%2,%0"
8982 [(set_attr "type" "shift")
8983 (set_attr "length" "4")])
8986 [(set (match_operand:DI 0 "register_operand" "=r")
8987 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8989 (match_operand:DI 2 "register_operand" "q")))]
8991 "extrd,u %1,%%sar,1,%0"
8992 [(set_attr "type" "shift")
8993 (set_attr "length" "4")])
8995 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8996 (define_expand "extv"
8997 [(set (match_operand 0 "register_operand" "")
8998 (sign_extract (match_operand 1 "register_operand" "")
8999 (match_operand 2 "uint32_operand" "")
9000 (match_operand 3 "uint32_operand" "")))]
9004 HOST_WIDE_INT len = INTVAL (operands[2]);
9005 HOST_WIDE_INT pos = INTVAL (operands[3]);
9007 /* PA extraction insns don't support zero length bitfields or fields
9008 extending beyond the left or right-most bits. Also, we reject lengths
9009 equal to a word as they are better handled by the move patterns. */
9010 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9013 /* From mips.md: extract_bit_field doesn't verify that our source
9014 matches the predicate, so check it again here. */
9015 if (!register_operand (operands[1], VOIDmode))
9019 emit_insn (gen_extv_64 (operands[0], operands[1],
9020 operands[2], operands[3]));
9022 emit_insn (gen_extv_32 (operands[0], operands[1],
9023 operands[2], operands[3]));
9027 (define_insn "extv_32"
9028 [(set (match_operand:SI 0 "register_operand" "=r")
9029 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9030 (match_operand:SI 2 "uint5_operand" "")
9031 (match_operand:SI 3 "uint5_operand" "")))]
9033 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
9034 [(set_attr "type" "shift")
9035 (set_attr "length" "4")])
9038 [(set (match_operand:SI 0 "register_operand" "=r")
9039 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9041 (match_operand:SI 2 "register_operand" "q")))]
9043 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
9044 [(set_attr "type" "shift")
9045 (set_attr "length" "4")])
9047 (define_insn "extv_64"
9048 [(set (match_operand:DI 0 "register_operand" "=r")
9049 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9050 (match_operand:DI 2 "uint32_operand" "")
9051 (match_operand:DI 3 "uint32_operand" "")))]
9053 "extrd,s %1,%3+%2-1,%2,%0"
9054 [(set_attr "type" "shift")
9055 (set_attr "length" "4")])
9058 [(set (match_operand:DI 0 "register_operand" "=r")
9059 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9061 (match_operand:DI 2 "register_operand" "q")))]
9063 "extrd,s %1,%%sar,1,%0"
9064 [(set_attr "type" "shift")
9065 (set_attr "length" "4")])
9067 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
9068 (define_expand "insv"
9069 [(set (zero_extract (match_operand 0 "register_operand" "")
9070 (match_operand 1 "uint32_operand" "")
9071 (match_operand 2 "uint32_operand" ""))
9072 (match_operand 3 "arith5_operand" ""))]
9076 HOST_WIDE_INT len = INTVAL (operands[1]);
9077 HOST_WIDE_INT pos = INTVAL (operands[2]);
9079 /* PA insertion insns don't support zero length bitfields or fields
9080 extending beyond the left or right-most bits. Also, we reject lengths
9081 equal to a word as they are better handled by the move patterns. */
9082 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9085 /* From mips.md: insert_bit_field doesn't verify that our destination
9086 matches the predicate, so check it again here. */
9087 if (!register_operand (operands[0], VOIDmode))
9091 emit_insn (gen_insv_64 (operands[0], operands[1],
9092 operands[2], operands[3]));
9094 emit_insn (gen_insv_32 (operands[0], operands[1],
9095 operands[2], operands[3]));
9099 (define_insn "insv_32"
9100 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
9101 (match_operand:SI 1 "uint5_operand" "")
9102 (match_operand:SI 2 "uint5_operand" ""))
9103 (match_operand:SI 3 "arith5_operand" "r,L"))]
9106 {dep|depw} %3,%2+%1-1,%1,%0
9107 {depi|depwi} %3,%2+%1-1,%1,%0"
9108 [(set_attr "type" "shift,shift")
9109 (set_attr "length" "4,4")])
9111 ;; Optimize insertion of const_int values of type 1...1xxxx.
9113 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
9114 (match_operand:SI 1 "uint5_operand" "")
9115 (match_operand:SI 2 "uint5_operand" ""))
9116 (match_operand:SI 3 "const_int_operand" ""))]
9117 "(INTVAL (operands[3]) & 0x10) != 0 &&
9118 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9121 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9122 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
9124 [(set_attr "type" "shift")
9125 (set_attr "length" "4")])
9127 (define_insn "insv_64"
9128 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
9129 (match_operand:DI 1 "uint32_operand" "")
9130 (match_operand:DI 2 "uint32_operand" ""))
9131 (match_operand:DI 3 "arith32_operand" "r,L"))]
9134 depd %3,%2+%1-1,%1,%0
9135 depdi %3,%2+%1-1,%1,%0"
9136 [(set_attr "type" "shift,shift")
9137 (set_attr "length" "4,4")])
9139 ;; Optimize insertion of const_int values of type 1...1xxxx.
9141 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9142 (match_operand:DI 1 "uint32_operand" "")
9143 (match_operand:DI 2 "uint32_operand" ""))
9144 (match_operand:DI 3 "const_int_operand" ""))]
9145 "(INTVAL (operands[3]) & 0x10) != 0
9147 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9150 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9151 return \"depdi %3,%2+%1-1,%1,%0\";
9153 [(set_attr "type" "shift")
9154 (set_attr "length" "4")])
9157 [(set (match_operand:DI 0 "register_operand" "=r")
9158 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9161 "depd,z %1,31,32,%0"
9162 [(set_attr "type" "shift")
9163 (set_attr "length" "4")])
9165 ;; This insn is used for some loop tests, typically loops reversed when
9166 ;; strength reduction is used. It is actually created when the instruction
9167 ;; combination phase combines the special loop test. Since this insn
9168 ;; is both a jump insn and has an output, it must deal with its own
9169 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
9170 ;; to not choose the register alternatives in the event a reload is needed.
9171 (define_insn "decrement_and_branch_until_zero"
9174 (match_operator 2 "comparison_operator"
9176 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
9177 (match_operand:SI 1 "int5_operand" "L,L,L"))
9179 (label_ref (match_operand 3 "" ""))
9182 (plus:SI (match_dup 0) (match_dup 1)))
9183 (clobber (match_scratch:SI 4 "=X,r,r"))]
9185 "* return output_dbra (operands, insn, which_alternative); "
9186 ;; Do not expect to understand this the first time through.
9187 [(set_attr "type" "cbranch,multi,multi")
9188 (set (attr "length")
9189 (if_then_else (eq_attr "alternative" "0")
9190 ;; Loop counter in register case
9191 ;; Short branch has length of 4
9192 ;; Long branch has length of 8, 20, 24 or 28
9193 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9194 (const_int MAX_12BIT_OFFSET))
9196 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9197 (const_int MAX_17BIT_OFFSET))
9199 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9201 (eq (symbol_ref "flag_pic") (const_int 0))
9205 ;; Loop counter in FP reg case.
9206 ;; Extra goo to deal with additional reload insns.
9207 (if_then_else (eq_attr "alternative" "1")
9208 (if_then_else (lt (match_dup 3) (pc))
9209 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9210 (const_int MAX_12BIT_OFFSET))
9212 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9213 (const_int MAX_17BIT_OFFSET))
9215 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9217 (eq (symbol_ref "flag_pic") (const_int 0))
9220 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9221 (const_int MAX_12BIT_OFFSET))
9223 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9224 (const_int MAX_17BIT_OFFSET))
9226 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9228 (eq (symbol_ref "flag_pic") (const_int 0))
9232 ;; Loop counter in memory case.
9233 ;; Extra goo to deal with additional reload insns.
9234 (if_then_else (lt (match_dup 3) (pc))
9235 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9236 (const_int MAX_12BIT_OFFSET))
9238 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9239 (const_int MAX_17BIT_OFFSET))
9241 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9243 (eq (symbol_ref "flag_pic") (const_int 0))
9246 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9247 (const_int MAX_12BIT_OFFSET))
9249 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9250 (const_int MAX_17BIT_OFFSET))
9252 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9254 (eq (symbol_ref "flag_pic") (const_int 0))
9256 (const_int 36))))))])
9261 (match_operator 2 "movb_comparison_operator"
9262 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9263 (label_ref (match_operand 3 "" ""))
9265 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9268 "* return output_movb (operands, insn, which_alternative, 0); "
9269 ;; Do not expect to understand this the first time through.
9270 [(set_attr "type" "cbranch,multi,multi,multi")
9271 (set (attr "length")
9272 (if_then_else (eq_attr "alternative" "0")
9273 ;; Loop counter in register case
9274 ;; Short branch has length of 4
9275 ;; Long branch has length of 8, 20, 24 or 28
9276 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9277 (const_int MAX_12BIT_OFFSET))
9279 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9280 (const_int MAX_17BIT_OFFSET))
9282 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9284 (eq (symbol_ref "flag_pic") (const_int 0))
9288 ;; Loop counter in FP reg case.
9289 ;; Extra goo to deal with additional reload insns.
9290 (if_then_else (eq_attr "alternative" "1")
9291 (if_then_else (lt (match_dup 3) (pc))
9292 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9293 (const_int MAX_12BIT_OFFSET))
9295 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9296 (const_int MAX_17BIT_OFFSET))
9298 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9300 (eq (symbol_ref "flag_pic") (const_int 0))
9303 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9304 (const_int MAX_12BIT_OFFSET))
9306 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9307 (const_int MAX_17BIT_OFFSET))
9309 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9311 (eq (symbol_ref "flag_pic") (const_int 0))
9315 ;; Loop counter in memory or sar case.
9316 ;; Extra goo to deal with additional reload insns.
9317 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9318 (const_int MAX_12BIT_OFFSET))
9320 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9321 (const_int MAX_17BIT_OFFSET))
9323 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9325 (eq (symbol_ref "flag_pic") (const_int 0))
9327 (const_int 32)))))])
9329 ;; Handle negated branch.
9333 (match_operator 2 "movb_comparison_operator"
9334 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9336 (label_ref (match_operand 3 "" ""))))
9337 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9340 "* return output_movb (operands, insn, which_alternative, 1); "
9341 ;; Do not expect to understand this the first time through.
9342 [(set_attr "type" "cbranch,multi,multi,multi")
9343 (set (attr "length")
9344 (if_then_else (eq_attr "alternative" "0")
9345 ;; Loop counter in register case
9346 ;; Short branch has length of 4
9347 ;; Long branch has length of 8
9348 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9349 (const_int MAX_12BIT_OFFSET))
9351 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9352 (const_int MAX_17BIT_OFFSET))
9354 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9356 (eq (symbol_ref "flag_pic") (const_int 0))
9360 ;; Loop counter in FP reg case.
9361 ;; Extra goo to deal with additional reload insns.
9362 (if_then_else (eq_attr "alternative" "1")
9363 (if_then_else (lt (match_dup 3) (pc))
9364 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9365 (const_int MAX_12BIT_OFFSET))
9367 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9368 (const_int MAX_17BIT_OFFSET))
9370 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9372 (eq (symbol_ref "flag_pic") (const_int 0))
9375 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9376 (const_int MAX_12BIT_OFFSET))
9378 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9379 (const_int MAX_17BIT_OFFSET))
9381 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9383 (eq (symbol_ref "flag_pic") (const_int 0))
9387 ;; Loop counter in memory or SAR case.
9388 ;; Extra goo to deal with additional reload insns.
9389 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9390 (const_int MAX_12BIT_OFFSET))
9392 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9393 (const_int MAX_17BIT_OFFSET))
9395 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9397 (eq (symbol_ref "flag_pic") (const_int 0))
9399 (const_int 32)))))])
9402 [(set (pc) (label_ref (match_operand 3 "" "" )))
9403 (set (match_operand:SI 0 "ireg_operand" "=r")
9404 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9405 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9406 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9409 return output_parallel_addb (operands, insn);
9411 [(set_attr "type" "parallel_branch")
9412 (set (attr "length")
9413 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9414 (const_int MAX_12BIT_OFFSET))
9416 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9417 (const_int MAX_17BIT_OFFSET))
9419 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9421 (eq (symbol_ref "flag_pic") (const_int 0))
9426 [(set (pc) (label_ref (match_operand 2 "" "" )))
9427 (set (match_operand:SF 0 "ireg_operand" "=r")
9428 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9432 return output_parallel_movb (operands, insn);
9434 [(set_attr "type" "parallel_branch")
9435 (set (attr "length")
9436 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9437 (const_int MAX_12BIT_OFFSET))
9439 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9440 (const_int MAX_17BIT_OFFSET))
9442 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9444 (eq (symbol_ref "flag_pic") (const_int 0))
9449 [(set (pc) (label_ref (match_operand 2 "" "" )))
9450 (set (match_operand:SI 0 "ireg_operand" "=r")
9451 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9455 return output_parallel_movb (operands, insn);
9457 [(set_attr "type" "parallel_branch")
9458 (set (attr "length")
9459 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9460 (const_int MAX_12BIT_OFFSET))
9462 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9463 (const_int MAX_17BIT_OFFSET))
9465 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9467 (eq (symbol_ref "flag_pic") (const_int 0))
9472 [(set (pc) (label_ref (match_operand 2 "" "" )))
9473 (set (match_operand:HI 0 "ireg_operand" "=r")
9474 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9478 return output_parallel_movb (operands, insn);
9480 [(set_attr "type" "parallel_branch")
9481 (set (attr "length")
9482 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9483 (const_int MAX_12BIT_OFFSET))
9485 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9486 (const_int MAX_17BIT_OFFSET))
9488 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9490 (eq (symbol_ref "flag_pic") (const_int 0))
9495 [(set (pc) (label_ref (match_operand 2 "" "" )))
9496 (set (match_operand:QI 0 "ireg_operand" "=r")
9497 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9501 return output_parallel_movb (operands, insn);
9503 [(set_attr "type" "parallel_branch")
9504 (set (attr "length")
9505 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9506 (const_int MAX_12BIT_OFFSET))
9508 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9509 (const_int MAX_17BIT_OFFSET))
9511 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9513 (eq (symbol_ref "flag_pic") (const_int 0))
9518 [(set (match_operand 0 "register_operand" "=f")
9519 (mult (match_operand 1 "register_operand" "f")
9520 (match_operand 2 "register_operand" "f")))
9521 (set (match_operand 3 "register_operand" "+f")
9522 (plus (match_operand 4 "register_operand" "f")
9523 (match_operand 5 "register_operand" "f")))]
9524 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9525 && reload_completed && fmpyaddoperands (operands)"
9528 if (GET_MODE (operands[0]) == DFmode)
9530 if (rtx_equal_p (operands[3], operands[5]))
9531 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9533 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9537 if (rtx_equal_p (operands[3], operands[5]))
9538 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9540 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9543 [(set_attr "type" "fpalu")
9544 (set_attr "length" "4")])
9547 [(set (match_operand 3 "register_operand" "+f")
9548 (plus (match_operand 4 "register_operand" "f")
9549 (match_operand 5 "register_operand" "f")))
9550 (set (match_operand 0 "register_operand" "=f")
9551 (mult (match_operand 1 "register_operand" "f")
9552 (match_operand 2 "register_operand" "f")))]
9553 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9554 && reload_completed && fmpyaddoperands (operands)"
9557 if (GET_MODE (operands[0]) == DFmode)
9559 if (rtx_equal_p (operands[3], operands[5]))
9560 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9562 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9566 if (rtx_equal_p (operands[3], operands[5]))
9567 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9569 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9572 [(set_attr "type" "fpalu")
9573 (set_attr "length" "4")])
9576 [(set (match_operand 0 "register_operand" "=f")
9577 (mult (match_operand 1 "register_operand" "f")
9578 (match_operand 2 "register_operand" "f")))
9579 (set (match_operand 3 "register_operand" "+f")
9580 (minus (match_operand 4 "register_operand" "f")
9581 (match_operand 5 "register_operand" "f")))]
9582 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9583 && reload_completed && fmpysuboperands (operands)"
9586 if (GET_MODE (operands[0]) == DFmode)
9587 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9589 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9591 [(set_attr "type" "fpalu")
9592 (set_attr "length" "4")])
9595 [(set (match_operand 3 "register_operand" "+f")
9596 (minus (match_operand 4 "register_operand" "f")
9597 (match_operand 5 "register_operand" "f")))
9598 (set (match_operand 0 "register_operand" "=f")
9599 (mult (match_operand 1 "register_operand" "f")
9600 (match_operand 2 "register_operand" "f")))]
9601 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9602 && reload_completed && fmpysuboperands (operands)"
9605 if (GET_MODE (operands[0]) == DFmode)
9606 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9608 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9610 [(set_attr "type" "fpalu")
9611 (set_attr "length" "4")])
9613 ;; Flush the I and D cache lines from the start address (operand0)
9614 ;; to the end address (operand1). No lines are flushed if the end
9615 ;; address is less than the start address (unsigned).
9617 ;; Because the range of memory flushed is variable and the size of
9618 ;; a MEM can only be a CONST_INT, the patterns specify that they
9619 ;; perform an unspecified volatile operation on all memory.
9621 ;; The address range for an icache flush must lie within a single
9622 ;; space on targets with non-equivalent space registers.
9624 ;; This is used by the trampoline code for nested functions.
9626 ;; Operand 0 contains the start address.
9627 ;; Operand 1 contains the end address.
9628 ;; Operand 2 contains the line length to use.
9629 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
9630 (define_insn "dcacheflush"
9632 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9633 (use (match_operand 0 "pmode_register_operand" "r"))
9634 (use (match_operand 1 "pmode_register_operand" "r"))
9635 (use (match_operand 2 "pmode_register_operand" "r"))
9636 (clobber (match_scratch 3 "=&0"))]
9641 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9643 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9645 [(set_attr "type" "multi")
9646 (set_attr "length" "12")])
9648 (define_insn "icacheflush"
9650 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9651 (use (match_operand 0 "pmode_register_operand" "r"))
9652 (use (match_operand 1 "pmode_register_operand" "r"))
9653 (use (match_operand 2 "pmode_register_operand" "r"))
9654 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9655 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9656 (clobber (match_scratch 5 "=&0"))]
9661 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9663 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9665 [(set_attr "type" "multi")
9666 (set_attr "length" "52")])
9668 ;; An out-of-line prologue.
9669 (define_insn "outline_prologue_call"
9670 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9671 (clobber (reg:SI 31))
9672 (clobber (reg:SI 22))
9673 (clobber (reg:SI 21))
9674 (clobber (reg:SI 20))
9675 (clobber (reg:SI 19))
9676 (clobber (reg:SI 1))]
9680 extern int frame_pointer_needed;
9682 /* We need two different versions depending on whether or not we
9683 need a frame pointer. Also note that we return to the instruction
9684 immediately after the branch rather than two instructions after the
9685 break as normally is the case. */
9686 if (frame_pointer_needed)
9688 /* Must import the magic millicode routine(s). */
9689 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9691 if (TARGET_PORTABLE_RUNTIME)
9693 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9694 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9698 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9702 /* Must import the magic millicode routine(s). */
9703 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9705 if (TARGET_PORTABLE_RUNTIME)
9707 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9708 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9711 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9715 [(set_attr "type" "multi")
9716 (set_attr "length" "8")])
9718 ;; An out-of-line epilogue.
9719 (define_insn "outline_epilogue_call"
9720 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9723 (clobber (reg:SI 31))
9724 (clobber (reg:SI 22))
9725 (clobber (reg:SI 21))
9726 (clobber (reg:SI 20))
9727 (clobber (reg:SI 19))
9728 (clobber (reg:SI 2))
9729 (clobber (reg:SI 1))]
9733 extern int frame_pointer_needed;
9735 /* We need two different versions depending on whether or not we
9736 need a frame pointer. Also note that we return to the instruction
9737 immediately after the branch rather than two instructions after the
9738 break as normally is the case. */
9739 if (frame_pointer_needed)
9741 /* Must import the magic millicode routine. */
9742 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9744 /* The out-of-line prologue will make sure we return to the right
9746 if (TARGET_PORTABLE_RUNTIME)
9748 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9749 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9753 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9757 /* Must import the magic millicode routine. */
9758 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9760 /* The out-of-line prologue will make sure we return to the right
9762 if (TARGET_PORTABLE_RUNTIME)
9764 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9765 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9768 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9772 [(set_attr "type" "multi")
9773 (set_attr "length" "8")])
9775 ;; Given a function pointer, canonicalize it so it can be
9776 ;; reliably compared to another function pointer. */
9777 (define_expand "canonicalize_funcptr_for_compare"
9778 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9779 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9780 (clobber (match_dup 2))
9781 (clobber (reg:SI 26))
9782 (clobber (reg:SI 22))
9783 (clobber (reg:SI 31))])
9784 (set (match_operand:SI 0 "register_operand" "")
9786 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9791 rtx canonicalize_funcptr_for_compare_libfunc
9792 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9794 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9795 operands[0], LCT_NORMAL, Pmode,
9796 1, operands[1], Pmode);
9800 operands[2] = gen_reg_rtx (SImode);
9801 if (GET_CODE (operands[1]) != REG)
9803 rtx tmp = gen_reg_rtx (Pmode);
9804 emit_move_insn (tmp, operands[1]);
9809 (define_insn "*$$sh_func_adrs"
9810 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9811 (clobber (match_operand:SI 0 "register_operand" "=a"))
9812 (clobber (reg:SI 26))
9813 (clobber (reg:SI 22))
9814 (clobber (reg:SI 31))]
9818 int length = get_attr_length (insn);
9821 xoperands[0] = GEN_INT (length - 8);
9822 xoperands[1] = GEN_INT (length - 16);
9824 /* Must import the magic millicode routine. */
9825 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9827 /* This is absolutely amazing.
9829 First, copy our input parameter into %r29 just in case we don't
9830 need to call $$sh_func_adrs. */
9831 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9832 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9834 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9835 we use %r26 unchanged. */
9836 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9837 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9839 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9840 4096, then again we use %r26 unchanged. */
9841 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9843 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9844 return output_millicode_call (insn,
9845 gen_rtx_SYMBOL_REF (SImode,
9846 \"$$sh_func_adrs\"));
9848 [(set_attr "type" "multi")
9849 (set (attr "length")
9850 (plus (symbol_ref "attr_length_millicode_call (insn)")
9853 ;; On the PA, the PIC register is call clobbered, so it must
9854 ;; be saved & restored around calls by the caller. If the call
9855 ;; doesn't return normally (nonlocal goto, or an exception is
9856 ;; thrown), then the code at the exception handler label must
9857 ;; restore the PIC register.
9858 (define_expand "exception_receiver"
9863 /* On the 64-bit port, we need a blockage because there is
9864 confusion regarding the dependence of the restore on the
9865 frame pointer. As a result, the frame pointer and pic
9866 register restores sometimes are interchanged erroneously. */
9868 emit_insn (gen_blockage ());
9869 /* Restore the PIC register using hppa_pic_save_rtx (). The
9870 PIC register is not saved in the frame in 64-bit ABI. */
9871 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9872 emit_insn (gen_blockage ());
9876 (define_expand "builtin_setjmp_receiver"
9877 [(label_ref (match_operand 0 "" ""))]
9882 emit_insn (gen_blockage ());
9883 /* Restore the PIC register. Hopefully, this will always be from
9884 a stack slot. The only registers that are valid after a
9885 builtin_longjmp are the stack and frame pointers. */
9886 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9887 emit_insn (gen_blockage ());
9891 ;; Allocate new stack space and update the saved stack pointer in the
9892 ;; frame marker. The HP C compilers also copy additional words in the
9893 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9894 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9895 ;; currently don't copy these values.
9897 ;; Since the copy of the frame marker can't be done atomically, I
9898 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9899 ;; The HP compilers appear to raise the stack and copy the frame
9900 ;; marker in a strict instruction sequence. This suggests that the
9901 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9902 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9903 ;; as GAS doesn't support it, or try to keep the instructions emitted
9904 ;; here in strict sequence.
9905 (define_expand "allocate_stack"
9906 [(match_operand 0 "" "")
9907 (match_operand 1 "" "")]
9913 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9914 in operand 0 before adjusting the stack. */
9915 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9916 anti_adjust_stack (operands[1]);
9917 if (TARGET_HPUX_UNWIND_LIBRARY)
9919 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9920 GEN_INT (TARGET_64BIT ? -8 : -4));
9921 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9923 if (!TARGET_64BIT && flag_pic)
9925 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9926 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9931 (define_expand "prefetch"
9932 [(match_operand 0 "address_operand" "")
9933 (match_operand 1 "const_int_operand" "")
9934 (match_operand 2 "const_int_operand" "")]
9937 int locality = INTVAL (operands[2]);
9939 gcc_assert (locality >= 0 && locality <= 3);
9941 /* Change operand[0] to a MEM as we don't have the infrastructure
9942 to output all the supported address modes for ldw/ldd when we use
9943 the address directly. However, we do have it for MEMs. */
9944 operands[0] = gen_rtx_MEM (QImode, operands[0]);
9946 /* If the address isn't valid for the prefetch, replace it. */
9949 if (!prefetch_nocc_operand (operands[0], QImode))
9951 = replace_equiv_address (operands[0],
9952 copy_to_mode_reg (Pmode,
9953 XEXP (operands[0], 0)));
9954 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
9958 if (!prefetch_cc_operand (operands[0], QImode))
9960 = replace_equiv_address (operands[0],
9961 copy_to_mode_reg (Pmode,
9962 XEXP (operands[0], 0)));
9963 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
9968 (define_insn "prefetch_cc"
9969 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
9970 (match_operand:SI 1 "const_int_operand" "n")
9971 (match_operand:SI 2 "const_int_operand" "n"))]
9972 "TARGET_PA_20 && operands[2] == const0_rtx"
9974 /* The SL cache-control completor indicates good spatial locality but
9975 poor temporal locality. The ldw instruction with a target of general
9976 register 0 prefetches a cache line for a read. The ldd instruction
9977 prefetches a cache line for a write. */
9978 static const char * const instr[2] = {
9979 "ldw%M0,sl %0,%%r0",
9982 int read_or_write = INTVAL (operands[1]);
9984 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9986 return instr [read_or_write];
9988 [(set_attr "type" "load")
9989 (set_attr "length" "4")])
9991 (define_insn "prefetch_nocc"
9992 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
9993 (match_operand:SI 1 "const_int_operand" "n,n")
9994 (match_operand:SI 2 "const_int_operand" "n,n"))]
9995 "TARGET_PA_20 && operands[2] != const0_rtx"
9997 /* The ldw instruction with a target of general register 0 prefetches
9998 a cache line for a read. The ldd instruction prefetches a cache line
10000 static const char * const instr[2][2] = {
10010 int read_or_write = INTVAL (operands[1]);
10012 gcc_assert (which_alternative == 0 || which_alternative == 1);
10013 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10015 return instr [which_alternative][read_or_write];
10017 [(set_attr "type" "load")
10018 (set_attr "length" "4")])
10022 (define_insn "tgd_load"
10023 [(set (match_operand:SI 0 "register_operand" "=r")
10024 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
10025 (clobber (reg:SI 1))
10030 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
10032 [(set_attr "type" "multi")
10033 (set_attr "length" "8")])
10035 (define_insn "tgd_load_pic"
10036 [(set (match_operand:SI 0 "register_operand" "=r")
10037 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
10038 (clobber (reg:SI 1))
10043 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
10045 [(set_attr "type" "multi")
10046 (set_attr "length" "8")])
10048 (define_insn "tld_load"
10049 [(set (match_operand:SI 0 "register_operand" "=r")
10050 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
10051 (clobber (reg:SI 1))
10056 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
10058 [(set_attr "type" "multi")
10059 (set_attr "length" "8")])
10061 (define_insn "tld_load_pic"
10062 [(set (match_operand:SI 0 "register_operand" "=r")
10063 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
10064 (clobber (reg:SI 1))
10069 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
10071 [(set_attr "type" "multi")
10072 (set_attr "length" "8")])
10074 (define_insn "tld_offset_load"
10075 [(set (match_operand:SI 0 "register_operand" "=r")
10076 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
10078 (match_operand:SI 2 "register_operand" "r")))
10079 (clobber (reg:SI 1))]
10083 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
10085 [(set_attr "type" "multi")
10086 (set_attr "length" "8")])
10088 (define_insn "tp_load"
10089 [(set (match_operand:SI 0 "register_operand" "=r")
10090 (unspec:SI [(const_int 0)] UNSPEC_TP))]
10093 [(set_attr "type" "multi")
10094 (set_attr "length" "4")])
10096 (define_insn "tie_load"
10097 [(set (match_operand:SI 0 "register_operand" "=r")
10098 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
10099 (clobber (reg:SI 1))
10104 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
10106 [(set_attr "type" "multi")
10107 (set_attr "length" "8")])
10109 (define_insn "tie_load_pic"
10110 [(set (match_operand:SI 0 "register_operand" "=r")
10111 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
10112 (clobber (reg:SI 1))
10117 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
10119 [(set_attr "type" "multi")
10120 (set_attr "length" "8")])
10122 (define_insn "tle_load"
10123 [(set (match_operand:SI 0 "register_operand" "=r")
10124 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
10126 (match_operand:SI 2 "register_operand" "r")))
10127 (clobber (reg:SI 1))]
10129 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
10130 [(set_attr "type" "multi")
10131 (set_attr "length" "8")])