| blob | 11188732bc74893128ac607f0da27471a1e6e34a |
1 ;; ??? This file needs auditing for thumb2
2 ;; Patterns for the Intel Wireless MMX technology architecture.
3 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it under
9 ;; the terms of the GNU General Public License as published by the Free
10 ;; Software Foundation; either version 3, or (at your option) any later
11 ;; version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Integer element sizes implemented by IWMMXT.
23 (define_mode_iterator VMMX [V2SI V4HI V8QI])
25 ;; Integer element sizes for shifts.
26 (define_mode_iterator VSHFT [V4HI V2SI DI])
28 ;; Determine element size suffix from vector mode.
29 (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
31 (define_insn "iwmmxt_iordi3"
32 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
33 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
34 (match_operand:DI 2 "register_operand" "y,r,r")))]
35 "TARGET_REALLY_IWMMXT"
36 "@
37 wor%?\\t%0, %1, %2
38 #
39 #"
40 [(set_attr "predicable" "yes")
41 (set_attr "length" "4,8,8")])
43 (define_insn "iwmmxt_xordi3"
44 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
45 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
46 (match_operand:DI 2 "register_operand" "y,r,r")))]
47 "TARGET_REALLY_IWMMXT"
48 "@
49 wxor%?\\t%0, %1, %2
50 #
51 #"
52 [(set_attr "predicable" "yes")
53 (set_attr "length" "4,8,8")])
55 (define_insn "iwmmxt_anddi3"
56 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
57 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
58 (match_operand:DI 2 "register_operand" "y,r,r")))]
59 "TARGET_REALLY_IWMMXT"
60 "@
61 wand%?\\t%0, %1, %2
62 #
63 #"
64 [(set_attr "predicable" "yes")
65 (set_attr "length" "4,8,8")])
67 (define_insn "iwmmxt_nanddi3"
68 [(set (match_operand:DI 0 "register_operand" "=y")
69 (and:DI (match_operand:DI 1 "register_operand" "y")
70 (not:DI (match_operand:DI 2 "register_operand" "y"))))]
71 "TARGET_REALLY_IWMMXT"
72 "wandn%?\\t%0, %1, %2"
73 [(set_attr "predicable" "yes")])
75 (define_insn "*iwmmxt_arm_movdi"
76 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
77 (match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))]
78 "TARGET_REALLY_IWMMXT
79 && ( register_operand (operands[0], DImode)
80 || register_operand (operands[1], DImode))"
81 "*
82 {
83 switch (which_alternative)
84 {
85 default:
86 return output_move_double (operands);
87 case 0:
88 return \"#\";
89 case 3:
90 return \"wmov%?\\t%0,%1\";
91 case 4:
92 return \"tmcrr%?\\t%0,%Q1,%R1\";
93 case 5:
94 return \"tmrrc%?\\t%Q0,%R0,%1\";
95 case 6:
96 return \"wldrd%?\\t%0,%1\";
97 case 7:
98 return \"wstrd%?\\t%1,%0\";
99 }
100 }"
101 [(set_attr "length" "8,8,8,4,4,4,4,4")
102 (set_attr "type" "*,load1,store2,*,*,*,*,*")
103 (set_attr "pool_range" "*,1020,*,*,*,*,*,*")
104 (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
105 )
107 (define_insn "*iwmmxt_movsi_insn"
108 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z")
109 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,Uy,z,z"))]
110 "TARGET_REALLY_IWMMXT
111 && ( register_operand (operands[0], SImode)
112 || register_operand (operands[1], SImode))"
113 "*
114 switch (which_alternative)
115 {
116 case 0: return \"mov\\t%0, %1\";
117 case 1: return \"mvn\\t%0, #%B1\";
118 case 2: return \"ldr\\t%0, %1\";
119 case 3: return \"str\\t%1, %0\";
120 case 4: return \"tmcr\\t%0, %1\";
121 case 5: return \"tmrc\\t%0, %1\";
122 case 6: return arm_output_load_gr (operands);
123 case 7: return \"wstrw\\t%1, %0\";
124 default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
125 }"
126 [(set_attr "type" "*,*,load1,store1,*,*,load1,store1,*")
127 (set_attr "length" "*,*,*, *,*,*, 16, *,8")
128 (set_attr "pool_range" "*,*,4096, *,*,*,1024, *,*")
129 (set_attr "neg_pool_range" "*,*,4084, *,*,*, *, 1012,*")
130 ;; Note - the "predicable" attribute is not allowed to have alternatives.
131 ;; Since the wSTRw wCx instruction is not predicable, we cannot support
132 ;; predicating any of the alternatives in this template. Instead,
133 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
134 (set_attr "predicable" "no")
135 ;; Also - we have to pretend that these insns clobber the condition code
136 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
137 ;; them.
138 (set_attr "conds" "clob")]
139 )
141 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
142 ;; cond_exec version explicitly, with appropriate constraints.
144 (define_insn "*cond_iwmmxt_movsi_insn"
145 [(cond_exec
146 (match_operator 2 "arm_comparison_operator"
147 [(match_operand 3 "cc_register" "")
148 (const_int 0)])
149 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
150 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
151 "TARGET_REALLY_IWMMXT
152 && ( register_operand (operands[0], SImode)
153 || register_operand (operands[1], SImode))"
154 "*
155 switch (which_alternative)
156 {
157 case 0: return \"mov%?\\t%0, %1\";
158 case 1: return \"mvn%?\\t%0, #%B1\";
159 case 2: return \"ldr%?\\t%0, %1\";
160 case 3: return \"str%?\\t%1, %0\";
161 case 4: return \"tmcr%?\\t%0, %1\";
162 default: return \"tmrc%?\\t%0, %1\";
163 }"
164 [(set_attr "type" "*,*,load1,store1,*,*")
165 (set_attr "pool_range" "*,*,4096, *,*,*")
166 (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
167 )
169 (define_insn "movv8qi_internal"
170 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
171 (match_operand:V8QI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
172 "TARGET_REALLY_IWMMXT"
173 "*
174 switch (which_alternative)
175 {
176 case 0: return \"wmov%?\\t%0, %1\";
177 case 1: return \"wstrd%?\\t%1, %0\";
178 case 2: return \"wldrd%?\\t%0, %1\";
179 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
180 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
181 case 5: return \"#\";
182 default: return output_move_double (operands);
183 }"
184 [(set_attr "predicable" "yes")
185 (set_attr "length" "4, 4, 4,4,4,8, 8")
186 (set_attr "type" "*,store1,load1,*,*,*,load1")
187 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
188 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
190 (define_insn "movv4hi_internal"
191 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
192 (match_operand:V4HI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
193 "TARGET_REALLY_IWMMXT"
194 "*
195 switch (which_alternative)
196 {
197 case 0: return \"wmov%?\\t%0, %1\";
198 case 1: return \"wstrd%?\\t%1, %0\";
199 case 2: return \"wldrd%?\\t%0, %1\";
200 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
201 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
202 case 5: return \"#\";
203 default: return output_move_double (operands);
204 }"
205 [(set_attr "predicable" "yes")
206 (set_attr "length" "4, 4, 4,4,4,8, 8")
207 (set_attr "type" "*,store1,load1,*,*,*,load1")
208 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
209 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
211 (define_insn "movv2si_internal"
212 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
213 (match_operand:V2SI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
214 "TARGET_REALLY_IWMMXT"
215 "*
216 switch (which_alternative)
217 {
218 case 0: return \"wmov%?\\t%0, %1\";
219 case 1: return \"wstrd%?\\t%1, %0\";
220 case 2: return \"wldrd%?\\t%0, %1\";
221 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
222 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
223 case 5: return \"#\";
224 default: return output_move_double (operands);
225 }"
226 [(set_attr "predicable" "yes")
227 (set_attr "length" "4, 4, 4,4,4,8, 24")
228 (set_attr "type" "*,store1,load1,*,*,*,load1")
229 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
230 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
232 ;; This pattern should not be needed. It is to match a
233 ;; wierd case generated by GCC when no optimizations are
234 ;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/
235 ;; compile/simd-5.c at -O0). The mode for operands[1] is
236 ;; deliberately omitted.
237 (define_insn "movv2si_internal_2"
238 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r")
239 (match_operand 1 "immediate_operand" "mi"))]
240 "TARGET_REALLY_IWMMXT"
241 "* return output_move_double (operands);"
242 [(set_attr "predicable" "yes")
243 (set_attr "length" "8")
244 (set_attr "type" "load1")
245 (set_attr "pool_range" "256")
246 (set_attr "neg_pool_range" "244")])
248 ;; Vector add/subtract
250 (define_insn "*add<mode>3_iwmmxt"
251 [(set (match_operand:VMMX 0 "register_operand" "=y")
252 (plus:VMMX (match_operand:VMMX 1 "register_operand" "y")
253 (match_operand:VMMX 2 "register_operand" "y")))]
254 "TARGET_REALLY_IWMMXT"
255 "wadd<MMX_char>%?\\t%0, %1, %2"
256 [(set_attr "predicable" "yes")])
258 (define_insn "ssaddv8qi3"
259 [(set (match_operand:V8QI 0 "register_operand" "=y")
260 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
261 (match_operand:V8QI 2 "register_operand" "y")))]
262 "TARGET_REALLY_IWMMXT"
263 "waddbss%?\\t%0, %1, %2"
264 [(set_attr "predicable" "yes")])
266 (define_insn "ssaddv4hi3"
267 [(set (match_operand:V4HI 0 "register_operand" "=y")
268 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
269 (match_operand:V4HI 2 "register_operand" "y")))]
270 "TARGET_REALLY_IWMMXT"
271 "waddhss%?\\t%0, %1, %2"
272 [(set_attr "predicable" "yes")])
274 (define_insn "ssaddv2si3"
275 [(set (match_operand:V2SI 0 "register_operand" "=y")
276 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
277 (match_operand:V2SI 2 "register_operand" "y")))]
278 "TARGET_REALLY_IWMMXT"
279 "waddwss%?\\t%0, %1, %2"
280 [(set_attr "predicable" "yes")])
282 (define_insn "usaddv8qi3"
283 [(set (match_operand:V8QI 0 "register_operand" "=y")
284 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
285 (match_operand:V8QI 2 "register_operand" "y")))]
286 "TARGET_REALLY_IWMMXT"
287 "waddbus%?\\t%0, %1, %2"
288 [(set_attr "predicable" "yes")])
290 (define_insn "usaddv4hi3"
291 [(set (match_operand:V4HI 0 "register_operand" "=y")
292 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
293 (match_operand:V4HI 2 "register_operand" "y")))]
294 "TARGET_REALLY_IWMMXT"
295 "waddhus%?\\t%0, %1, %2"
296 [(set_attr "predicable" "yes")])
298 (define_insn "usaddv2si3"
299 [(set (match_operand:V2SI 0 "register_operand" "=y")
300 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
301 (match_operand:V2SI 2 "register_operand" "y")))]
302 "TARGET_REALLY_IWMMXT"
303 "waddwus%?\\t%0, %1, %2"
304 [(set_attr "predicable" "yes")])
306 (define_insn "*sub<mode>3_iwmmxt"
307 [(set (match_operand:VMMX 0 "register_operand" "=y")
308 (minus:VMMX (match_operand:VMMX 1 "register_operand" "y")
309 (match_operand:VMMX 2 "register_operand" "y")))]
310 "TARGET_REALLY_IWMMXT"
311 "wsub<MMX_char>%?\\t%0, %1, %2"
312 [(set_attr "predicable" "yes")])
314 (define_insn "sssubv8qi3"
315 [(set (match_operand:V8QI 0 "register_operand" "=y")
316 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
317 (match_operand:V8QI 2 "register_operand" "y")))]
318 "TARGET_REALLY_IWMMXT"
319 "wsubbss%?\\t%0, %1, %2"
320 [(set_attr "predicable" "yes")])
322 (define_insn "sssubv4hi3"
323 [(set (match_operand:V4HI 0 "register_operand" "=y")
324 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
325 (match_operand:V4HI 2 "register_operand" "y")))]
326 "TARGET_REALLY_IWMMXT"
327 "wsubhss%?\\t%0, %1, %2"
328 [(set_attr "predicable" "yes")])
330 (define_insn "sssubv2si3"
331 [(set (match_operand:V2SI 0 "register_operand" "=y")
332 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
333 (match_operand:V2SI 2 "register_operand" "y")))]
334 "TARGET_REALLY_IWMMXT"
335 "wsubwss%?\\t%0, %1, %2"
336 [(set_attr "predicable" "yes")])
338 (define_insn "ussubv8qi3"
339 [(set (match_operand:V8QI 0 "register_operand" "=y")
340 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
341 (match_operand:V8QI 2 "register_operand" "y")))]
342 "TARGET_REALLY_IWMMXT"
343 "wsubbus%?\\t%0, %1, %2"
344 [(set_attr "predicable" "yes")])
346 (define_insn "ussubv4hi3"
347 [(set (match_operand:V4HI 0 "register_operand" "=y")
348 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
349 (match_operand:V4HI 2 "register_operand" "y")))]
350 "TARGET_REALLY_IWMMXT"
351 "wsubhus%?\\t%0, %1, %2"
352 [(set_attr "predicable" "yes")])
354 (define_insn "ussubv2si3"
355 [(set (match_operand:V2SI 0 "register_operand" "=y")
356 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
357 (match_operand:V2SI 2 "register_operand" "y")))]
358 "TARGET_REALLY_IWMMXT"
359 "wsubwus%?\\t%0, %1, %2"
360 [(set_attr "predicable" "yes")])
362 (define_insn "*mulv4hi3_iwmmxt"
363 [(set (match_operand:V4HI 0 "register_operand" "=y")
364 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
365 (match_operand:V4HI 2 "register_operand" "y")))]
366 "TARGET_REALLY_IWMMXT"
367 "wmulul%?\\t%0, %1, %2"
368 [(set_attr "predicable" "yes")])
370 (define_insn "smulv4hi3_highpart"
371 [(set (match_operand:V4HI 0 "register_operand" "=y")
372 (truncate:V4HI
373 (lshiftrt:V4SI
374 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
375 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
376 (const_int 16))))]
377 "TARGET_REALLY_IWMMXT"
378 "wmulsm%?\\t%0, %1, %2"
379 [(set_attr "predicable" "yes")])
381 (define_insn "umulv4hi3_highpart"
382 [(set (match_operand:V4HI 0 "register_operand" "=y")
383 (truncate:V4HI
384 (lshiftrt:V4SI
385 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
386 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
387 (const_int 16))))]
388 "TARGET_REALLY_IWMMXT"
389 "wmulum%?\\t%0, %1, %2"
390 [(set_attr "predicable" "yes")])
392 (define_insn "iwmmxt_wmacs"
393 [(set (match_operand:DI 0 "register_operand" "=y")
394 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
395 (match_operand:V4HI 2 "register_operand" "y")
396 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
397 "TARGET_REALLY_IWMMXT"
398 "wmacs%?\\t%0, %2, %3"
399 [(set_attr "predicable" "yes")])
401 (define_insn "iwmmxt_wmacsz"
402 [(set (match_operand:DI 0 "register_operand" "=y")
403 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
404 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
405 "TARGET_REALLY_IWMMXT"
406 "wmacsz%?\\t%0, %1, %2"
407 [(set_attr "predicable" "yes")])
409 (define_insn "iwmmxt_wmacu"
410 [(set (match_operand:DI 0 "register_operand" "=y")
411 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
412 (match_operand:V4HI 2 "register_operand" "y")
413 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
414 "TARGET_REALLY_IWMMXT"
415 "wmacu%?\\t%0, %2, %3"
416 [(set_attr "predicable" "yes")])
418 (define_insn "iwmmxt_wmacuz"
419 [(set (match_operand:DI 0 "register_operand" "=y")
420 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
421 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
422 "TARGET_REALLY_IWMMXT"
423 "wmacuz%?\\t%0, %1, %2"
424 [(set_attr "predicable" "yes")])
426 ;; Same as xordi3, but don't show input operands so that we don't think
427 ;; they are live.
428 (define_insn "iwmmxt_clrdi"
429 [(set (match_operand:DI 0 "register_operand" "=y")
430 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
431 "TARGET_REALLY_IWMMXT"
432 "wxor%?\\t%0, %0, %0"
433 [(set_attr "predicable" "yes")])
435 ;; Seems like cse likes to generate these, so we have to support them.
437 (define_insn "*iwmmxt_clrv8qi"
438 [(set (match_operand:V8QI 0 "register_operand" "=y")
439 (const_vector:V8QI [(const_int 0) (const_int 0)
440 (const_int 0) (const_int 0)
441 (const_int 0) (const_int 0)
442 (const_int 0) (const_int 0)]))]
443 "TARGET_REALLY_IWMMXT"
444 "wxor%?\\t%0, %0, %0"
445 [(set_attr "predicable" "yes")])
447 (define_insn "*iwmmxt_clrv4hi"
448 [(set (match_operand:V4HI 0 "register_operand" "=y")
449 (const_vector:V4HI [(const_int 0) (const_int 0)
450 (const_int 0) (const_int 0)]))]
451 "TARGET_REALLY_IWMMXT"
452 "wxor%?\\t%0, %0, %0"
453 [(set_attr "predicable" "yes")])
455 (define_insn "*iwmmxt_clrv2si"
456 [(set (match_operand:V2SI 0 "register_operand" "=y")
457 (const_vector:V2SI [(const_int 0) (const_int 0)]))]
458 "TARGET_REALLY_IWMMXT"
459 "wxor%?\\t%0, %0, %0"
460 [(set_attr "predicable" "yes")])
462 ;; Unsigned averages/sum of absolute differences
464 (define_insn "iwmmxt_uavgrndv8qi3"
465 [(set (match_operand:V8QI 0 "register_operand" "=y")
466 (ashiftrt:V8QI
467 (plus:V8QI (plus:V8QI
468 (match_operand:V8QI 1 "register_operand" "y")
469 (match_operand:V8QI 2 "register_operand" "y"))
470 (const_vector:V8QI [(const_int 1)
471 (const_int 1)
472 (const_int 1)
473 (const_int 1)
474 (const_int 1)
475 (const_int 1)
476 (const_int 1)
477 (const_int 1)]))
478 (const_int 1)))]
479 "TARGET_REALLY_IWMMXT"
480 "wavg2br%?\\t%0, %1, %2"
481 [(set_attr "predicable" "yes")])
483 (define_insn "iwmmxt_uavgrndv4hi3"
484 [(set (match_operand:V4HI 0 "register_operand" "=y")
485 (ashiftrt:V4HI
486 (plus:V4HI (plus:V4HI
487 (match_operand:V4HI 1 "register_operand" "y")
488 (match_operand:V4HI 2 "register_operand" "y"))
489 (const_vector:V4HI [(const_int 1)
490 (const_int 1)
491 (const_int 1)
492 (const_int 1)]))
493 (const_int 1)))]
494 "TARGET_REALLY_IWMMXT"
495 "wavg2hr%?\\t%0, %1, %2"
496 [(set_attr "predicable" "yes")])
499 (define_insn "iwmmxt_uavgv8qi3"
500 [(set (match_operand:V8QI 0 "register_operand" "=y")
501 (ashiftrt:V8QI (plus:V8QI
502 (match_operand:V8QI 1 "register_operand" "y")
503 (match_operand:V8QI 2 "register_operand" "y"))
504 (const_int 1)))]
505 "TARGET_REALLY_IWMMXT"
506 "wavg2b%?\\t%0, %1, %2"
507 [(set_attr "predicable" "yes")])
509 (define_insn "iwmmxt_uavgv4hi3"
510 [(set (match_operand:V4HI 0 "register_operand" "=y")
511 (ashiftrt:V4HI (plus:V4HI
512 (match_operand:V4HI 1 "register_operand" "y")
513 (match_operand:V4HI 2 "register_operand" "y"))
514 (const_int 1)))]
515 "TARGET_REALLY_IWMMXT"
516 "wavg2h%?\\t%0, %1, %2"
517 [(set_attr "predicable" "yes")])
519 (define_insn "iwmmxt_psadbw"
520 [(set (match_operand:V8QI 0 "register_operand" "=y")
521 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
522 (match_operand:V8QI 2 "register_operand" "y"))))]
523 "TARGET_REALLY_IWMMXT"
524 "psadbw%?\\t%0, %1, %2"
525 [(set_attr "predicable" "yes")])
528 ;; Insert/extract/shuffle
530 (define_insn "iwmmxt_tinsrb"
531 [(set (match_operand:V8QI 0 "register_operand" "=y")
532 (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0")
533 (vec_duplicate:V8QI
534 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
535 (match_operand:SI 3 "immediate_operand" "i")))]
536 "TARGET_REALLY_IWMMXT"
537 "tinsrb%?\\t%0, %2, %3"
538 [(set_attr "predicable" "yes")])
540 (define_insn "iwmmxt_tinsrh"
541 [(set (match_operand:V4HI 0 "register_operand" "=y")
542 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
543 (vec_duplicate:V4HI
544 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
545 (match_operand:SI 3 "immediate_operand" "i")))]
546 "TARGET_REALLY_IWMMXT"
547 "tinsrh%?\\t%0, %2, %3"
548 [(set_attr "predicable" "yes")])
550 (define_insn "iwmmxt_tinsrw"
551 [(set (match_operand:V2SI 0 "register_operand" "=y")
552 (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0")
553 (vec_duplicate:V2SI
554 (match_operand:SI 2 "nonimmediate_operand" "r"))
555 (match_operand:SI 3 "immediate_operand" "i")))]
556 "TARGET_REALLY_IWMMXT"
557 "tinsrw%?\\t%0, %2, %3"
558 [(set_attr "predicable" "yes")])
560 (define_insn "iwmmxt_textrmub"
561 [(set (match_operand:SI 0 "register_operand" "=r")
562 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
563 (parallel
564 [(match_operand:SI 2 "immediate_operand" "i")]))))]
565 "TARGET_REALLY_IWMMXT"
566 "textrmub%?\\t%0, %1, %2"
567 [(set_attr "predicable" "yes")])
569 (define_insn "iwmmxt_textrmsb"
570 [(set (match_operand:SI 0 "register_operand" "=r")
571 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
572 (parallel
573 [(match_operand:SI 2 "immediate_operand" "i")]))))]
574 "TARGET_REALLY_IWMMXT"
575 "textrmsb%?\\t%0, %1, %2"
576 [(set_attr "predicable" "yes")])
578 (define_insn "iwmmxt_textrmuh"
579 [(set (match_operand:SI 0 "register_operand" "=r")
580 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
581 (parallel
582 [(match_operand:SI 2 "immediate_operand" "i")]))))]
583 "TARGET_REALLY_IWMMXT"
584 "textrmuh%?\\t%0, %1, %2"
585 [(set_attr "predicable" "yes")])
587 (define_insn "iwmmxt_textrmsh"
588 [(set (match_operand:SI 0 "register_operand" "=r")
589 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
590 (parallel
591 [(match_operand:SI 2 "immediate_operand" "i")]))))]
592 "TARGET_REALLY_IWMMXT"
593 "textrmsh%?\\t%0, %1, %2"
594 [(set_attr "predicable" "yes")])
596 ;; There are signed/unsigned variants of this instruction, but they are
597 ;; pointless.
598 (define_insn "iwmmxt_textrmw"
599 [(set (match_operand:SI 0 "register_operand" "=r")
600 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
601 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
602 "TARGET_REALLY_IWMMXT"
603 "textrmsw%?\\t%0, %1, %2"
604 [(set_attr "predicable" "yes")])
606 (define_insn "iwmmxt_wshufh"
607 [(set (match_operand:V4HI 0 "register_operand" "=y")
608 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
609 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
610 "TARGET_REALLY_IWMMXT"
611 "wshufh%?\\t%0, %1, %2"
612 [(set_attr "predicable" "yes")])
614 ;; Mask-generating comparisons
615 ;;
616 ;; Note - you cannot use patterns like these here:
617 ;;
618 ;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
619 ;;
620 ;; Because GCC will assume that the truth value (1 or 0) is installed
621 ;; into the entire destination vector, (with the '1' going into the least
622 ;; significant element of the vector). This is not how these instructions
623 ;; behave.
624 ;;
625 ;; Unfortunately the current patterns are illegal. They are SET insns
626 ;; without a SET in them. They work in most cases for ordinary code
627 ;; generation, but there are circumstances where they can cause gcc to fail.
628 ;; XXX - FIXME.
630 (define_insn "eqv8qi3"
631 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
632 (match_operand:V8QI 1 "register_operand" "y")
633 (match_operand:V8QI 2 "register_operand" "y")]
634 VUNSPEC_WCMP_EQ)]
635 "TARGET_REALLY_IWMMXT"
636 "wcmpeqb%?\\t%0, %1, %2"
637 [(set_attr "predicable" "yes")])
639 (define_insn "eqv4hi3"
640 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
641 (match_operand:V4HI 1 "register_operand" "y")
642 (match_operand:V4HI 2 "register_operand" "y")]
643 VUNSPEC_WCMP_EQ)]
644 "TARGET_REALLY_IWMMXT"
645 "wcmpeqh%?\\t%0, %1, %2"
646 [(set_attr "predicable" "yes")])
648 (define_insn "eqv2si3"
649 [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
650 (match_operand:V2SI 1 "register_operand" "y")
651 (match_operand:V2SI 2 "register_operand" "y")]
652 VUNSPEC_WCMP_EQ)]
653 "TARGET_REALLY_IWMMXT"
654 "wcmpeqw%?\\t%0, %1, %2"
655 [(set_attr "predicable" "yes")])
657 (define_insn "gtuv8qi3"
658 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
659 (match_operand:V8QI 1 "register_operand" "y")
660 (match_operand:V8QI 2 "register_operand" "y")]
661 VUNSPEC_WCMP_GTU)]
662 "TARGET_REALLY_IWMMXT"
663 "wcmpgtub%?\\t%0, %1, %2"
664 [(set_attr "predicable" "yes")])
666 (define_insn "gtuv4hi3"
667 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
668 (match_operand:V4HI 1 "register_operand" "y")
669 (match_operand:V4HI 2 "register_operand" "y")]
670 VUNSPEC_WCMP_GTU)]
671 "TARGET_REALLY_IWMMXT"
672 "wcmpgtuh%?\\t%0, %1, %2"
673 [(set_attr "predicable" "yes")])
675 (define_insn "gtuv2si3"
676 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
677 (match_operand:V2SI 1 "register_operand" "y")
678 (match_operand:V2SI 2 "register_operand" "y")]
679 VUNSPEC_WCMP_GTU)]
680 "TARGET_REALLY_IWMMXT"
681 "wcmpgtuw%?\\t%0, %1, %2"
682 [(set_attr "predicable" "yes")])
684 (define_insn "gtv8qi3"
685 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
686 (match_operand:V8QI 1 "register_operand" "y")
687 (match_operand:V8QI 2 "register_operand" "y")]
688 VUNSPEC_WCMP_GT)]
689 "TARGET_REALLY_IWMMXT"
690 "wcmpgtsb%?\\t%0, %1, %2"
691 [(set_attr "predicable" "yes")])
693 (define_insn "gtv4hi3"
694 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
695 (match_operand:V4HI 1 "register_operand" "y")
696 (match_operand:V4HI 2 "register_operand" "y")]
697 VUNSPEC_WCMP_GT)]
698 "TARGET_REALLY_IWMMXT"
699 "wcmpgtsh%?\\t%0, %1, %2"
700 [(set_attr "predicable" "yes")])
702 (define_insn "gtv2si3"
703 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
704 (match_operand:V2SI 1 "register_operand" "y")
705 (match_operand:V2SI 2 "register_operand" "y")]
706 VUNSPEC_WCMP_GT)]
707 "TARGET_REALLY_IWMMXT"
708 "wcmpgtsw%?\\t%0, %1, %2"
709 [(set_attr "predicable" "yes")])
711 ;; Max/min insns
713 (define_insn "*smax<mode>3_iwmmxt"
714 [(set (match_operand:VMMX 0 "register_operand" "=y")
715 (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
716 (match_operand:VMMX 2 "register_operand" "y")))]
717 "TARGET_REALLY_IWMMXT"
718 "wmaxs<MMX_char>%?\\t%0, %1, %2"
719 [(set_attr "predicable" "yes")])
721 (define_insn "*umax<mode>3_iwmmxt"
722 [(set (match_operand:VMMX 0 "register_operand" "=y")
723 (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
724 (match_operand:VMMX 2 "register_operand" "y")))]
725 "TARGET_REALLY_IWMMXT"
726 "wmaxu<MMX_char>%?\\t%0, %1, %2"
727 [(set_attr "predicable" "yes")])
729 (define_insn "*smin<mode>3_iwmmxt"
730 [(set (match_operand:VMMX 0 "register_operand" "=y")
731 (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
732 (match_operand:VMMX 2 "register_operand" "y")))]
733 "TARGET_REALLY_IWMMXT"
734 "wmins<MMX_char>%?\\t%0, %1, %2"
735 [(set_attr "predicable" "yes")])
737 (define_insn "*umin<mode>3_iwmmxt"
738 [(set (match_operand:VMMX 0 "register_operand" "=y")
739 (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
740 (match_operand:VMMX 2 "register_operand" "y")))]
741 "TARGET_REALLY_IWMMXT"
742 "wminu<MMX_char>%?\\t%0, %1, %2"
743 [(set_attr "predicable" "yes")])
745 ;; Pack/unpack insns.
747 (define_insn "iwmmxt_wpackhss"
748 [(set (match_operand:V8QI 0 "register_operand" "=y")
749 (vec_concat:V8QI
750 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
751 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
752 "TARGET_REALLY_IWMMXT"
753 "wpackhss%?\\t%0, %1, %2"
754 [(set_attr "predicable" "yes")])
756 (define_insn "iwmmxt_wpackwss"
757 [(set (match_operand:V4HI 0 "register_operand" "=y")
758 (vec_concat:V4HI
759 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
760 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
761 "TARGET_REALLY_IWMMXT"
762 "wpackwss%?\\t%0, %1, %2"
763 [(set_attr "predicable" "yes")])
765 (define_insn "iwmmxt_wpackdss"
766 [(set (match_operand:V2SI 0 "register_operand" "=y")
767 (vec_concat:V2SI
768 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
769 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
770 "TARGET_REALLY_IWMMXT"
771 "wpackdss%?\\t%0, %1, %2"
772 [(set_attr "predicable" "yes")])
774 (define_insn "iwmmxt_wpackhus"
775 [(set (match_operand:V8QI 0 "register_operand" "=y")
776 (vec_concat:V8QI
777 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
778 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
779 "TARGET_REALLY_IWMMXT"
780 "wpackhus%?\\t%0, %1, %2"
781 [(set_attr "predicable" "yes")])
783 (define_insn "iwmmxt_wpackwus"
784 [(set (match_operand:V4HI 0 "register_operand" "=y")
785 (vec_concat:V4HI
786 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
787 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
788 "TARGET_REALLY_IWMMXT"
789 "wpackwus%?\\t%0, %1, %2"
790 [(set_attr "predicable" "yes")])
792 (define_insn "iwmmxt_wpackdus"
793 [(set (match_operand:V2SI 0 "register_operand" "=y")
794 (vec_concat:V2SI
795 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
796 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
797 "TARGET_REALLY_IWMMXT"
798 "wpackdus%?\\t%0, %1, %2"
799 [(set_attr "predicable" "yes")])
802 (define_insn "iwmmxt_wunpckihb"
803 [(set (match_operand:V8QI 0 "register_operand" "=y")
804 (vec_merge:V8QI
805 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
806 (parallel [(const_int 4)
807 (const_int 0)
808 (const_int 5)
809 (const_int 1)
810 (const_int 6)
811 (const_int 2)
812 (const_int 7)
813 (const_int 3)]))
814 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
815 (parallel [(const_int 0)
816 (const_int 4)
817 (const_int 1)
818 (const_int 5)
819 (const_int 2)
820 (const_int 6)
821 (const_int 3)
822 (const_int 7)]))
823 (const_int 85)))]
824 "TARGET_REALLY_IWMMXT"
825 "wunpckihb%?\\t%0, %1, %2"
826 [(set_attr "predicable" "yes")])
828 (define_insn "iwmmxt_wunpckihh"
829 [(set (match_operand:V4HI 0 "register_operand" "=y")
830 (vec_merge:V4HI
831 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
832 (parallel [(const_int 0)
833 (const_int 2)
834 (const_int 1)
835 (const_int 3)]))
836 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
837 (parallel [(const_int 2)
838 (const_int 0)
839 (const_int 3)
840 (const_int 1)]))
841 (const_int 5)))]
842 "TARGET_REALLY_IWMMXT"
843 "wunpckihh%?\\t%0, %1, %2"
844 [(set_attr "predicable" "yes")])
846 (define_insn "iwmmxt_wunpckihw"
847 [(set (match_operand:V2SI 0 "register_operand" "=y")
848 (vec_merge:V2SI
849 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
850 (parallel [(const_int 0)
851 (const_int 1)]))
852 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
853 (parallel [(const_int 1)
854 (const_int 0)]))
855 (const_int 1)))]
856 "TARGET_REALLY_IWMMXT"
857 "wunpckihw%?\\t%0, %1, %2"
858 [(set_attr "predicable" "yes")])
860 (define_insn "iwmmxt_wunpckilb"
861 [(set (match_operand:V8QI 0 "register_operand" "=y")
862 (vec_merge:V8QI
863 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
864 (parallel [(const_int 0)
865 (const_int 4)
866 (const_int 1)
867 (const_int 5)
868 (const_int 2)
869 (const_int 6)
870 (const_int 3)
871 (const_int 7)]))
872 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
873 (parallel [(const_int 4)
874 (const_int 0)
875 (const_int 5)
876 (const_int 1)
877 (const_int 6)
878 (const_int 2)
879 (const_int 7)
880 (const_int 3)]))
881 (const_int 85)))]
882 "TARGET_REALLY_IWMMXT"
883 "wunpckilb%?\\t%0, %1, %2"
884 [(set_attr "predicable" "yes")])
886 (define_insn "iwmmxt_wunpckilh"
887 [(set (match_operand:V4HI 0 "register_operand" "=y")
888 (vec_merge:V4HI
889 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
890 (parallel [(const_int 2)
891 (const_int 0)
892 (const_int 3)
893 (const_int 1)]))
894 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
895 (parallel [(const_int 0)
896 (const_int 2)
897 (const_int 1)
898 (const_int 3)]))
899 (const_int 5)))]
900 "TARGET_REALLY_IWMMXT"
901 "wunpckilh%?\\t%0, %1, %2"
902 [(set_attr "predicable" "yes")])
904 (define_insn "iwmmxt_wunpckilw"
905 [(set (match_operand:V2SI 0 "register_operand" "=y")
906 (vec_merge:V2SI
907 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
908 (parallel [(const_int 1)
909 (const_int 0)]))
910 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
911 (parallel [(const_int 0)
912 (const_int 1)]))
913 (const_int 1)))]
914 "TARGET_REALLY_IWMMXT"
915 "wunpckilw%?\\t%0, %1, %2"
916 [(set_attr "predicable" "yes")])
918 (define_insn "iwmmxt_wunpckehub"
919 [(set (match_operand:V4HI 0 "register_operand" "=y")
920 (zero_extend:V4HI
921 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
922 (parallel [(const_int 4) (const_int 5)
923 (const_int 6) (const_int 7)]))))]
924 "TARGET_REALLY_IWMMXT"
925 "wunpckehub%?\\t%0, %1"
926 [(set_attr "predicable" "yes")])
928 (define_insn "iwmmxt_wunpckehuh"
929 [(set (match_operand:V2SI 0 "register_operand" "=y")
930 (zero_extend:V2SI
931 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
932 (parallel [(const_int 2) (const_int 3)]))))]
933 "TARGET_REALLY_IWMMXT"
934 "wunpckehuh%?\\t%0, %1"
935 [(set_attr "predicable" "yes")])
937 (define_insn "iwmmxt_wunpckehuw"
938 [(set (match_operand:DI 0 "register_operand" "=y")
939 (zero_extend:DI
940 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
941 (parallel [(const_int 1)]))))]
942 "TARGET_REALLY_IWMMXT"
943 "wunpckehuw%?\\t%0, %1"
944 [(set_attr "predicable" "yes")])
946 (define_insn "iwmmxt_wunpckehsb"
947 [(set (match_operand:V4HI 0 "register_operand" "=y")
948 (sign_extend:V4HI
949 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
950 (parallel [(const_int 4) (const_int 5)
951 (const_int 6) (const_int 7)]))))]
952 "TARGET_REALLY_IWMMXT"
953 "wunpckehsb%?\\t%0, %1"
954 [(set_attr "predicable" "yes")])
956 (define_insn "iwmmxt_wunpckehsh"
957 [(set (match_operand:V2SI 0 "register_operand" "=y")
958 (sign_extend:V2SI
959 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
960 (parallel [(const_int 2) (const_int 3)]))))]
961 "TARGET_REALLY_IWMMXT"
962 "wunpckehsh%?\\t%0, %1"
963 [(set_attr "predicable" "yes")])
965 (define_insn "iwmmxt_wunpckehsw"
966 [(set (match_operand:DI 0 "register_operand" "=y")
967 (sign_extend:DI
968 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
969 (parallel [(const_int 1)]))))]
970 "TARGET_REALLY_IWMMXT"
971 "wunpckehsw%?\\t%0, %1"
972 [(set_attr "predicable" "yes")])
974 (define_insn "iwmmxt_wunpckelub"
975 [(set (match_operand:V4HI 0 "register_operand" "=y")
976 (zero_extend:V4HI
977 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
978 (parallel [(const_int 0) (const_int 1)
979 (const_int 2) (const_int 3)]))))]
980 "TARGET_REALLY_IWMMXT"
981 "wunpckelub%?\\t%0, %1"
982 [(set_attr "predicable" "yes")])
984 (define_insn "iwmmxt_wunpckeluh"
985 [(set (match_operand:V2SI 0 "register_operand" "=y")
986 (zero_extend:V2SI
987 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
988 (parallel [(const_int 0) (const_int 1)]))))]
989 "TARGET_REALLY_IWMMXT"
990 "wunpckeluh%?\\t%0, %1"
991 [(set_attr "predicable" "yes")])
993 (define_insn "iwmmxt_wunpckeluw"
994 [(set (match_operand:DI 0 "register_operand" "=y")
995 (zero_extend:DI
996 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
997 (parallel [(const_int 0)]))))]
998 "TARGET_REALLY_IWMMXT"
999 "wunpckeluw%?\\t%0, %1"
1000 [(set_attr "predicable" "yes")])
1002 (define_insn "iwmmxt_wunpckelsb"
1003 [(set (match_operand:V4HI 0 "register_operand" "=y")
1004 (sign_extend:V4HI
1005 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1006 (parallel [(const_int 0) (const_int 1)
1007 (const_int 2) (const_int 3)]))))]
1008 "TARGET_REALLY_IWMMXT"
1009 "wunpckelsb%?\\t%0, %1"
1010 [(set_attr "predicable" "yes")])
1012 (define_insn "iwmmxt_wunpckelsh"
1013 [(set (match_operand:V2SI 0 "register_operand" "=y")
1014 (sign_extend:V2SI
1015 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1016 (parallel [(const_int 0) (const_int 1)]))))]
1017 "TARGET_REALLY_IWMMXT"
1018 "wunpckelsh%?\\t%0, %1"
1019 [(set_attr "predicable" "yes")])
1021 (define_insn "iwmmxt_wunpckelsw"
1022 [(set (match_operand:DI 0 "register_operand" "=y")
1023 (sign_extend:DI
1024 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1025 (parallel [(const_int 0)]))))]
1026 "TARGET_REALLY_IWMMXT"
1027 "wunpckelsw%?\\t%0, %1"
1028 [(set_attr "predicable" "yes")])
1030 ;; Shifts
1032 (define_insn "rorv4hi3"
1033 [(set (match_operand:V4HI 0 "register_operand" "=y")
1034 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1035 (match_operand:SI 2 "register_operand" "z")))]
1036 "TARGET_REALLY_IWMMXT"
1037 "wrorhg%?\\t%0, %1, %2"
1038 [(set_attr "predicable" "yes")])
1040 (define_insn "rorv2si3"
1041 [(set (match_operand:V2SI 0 "register_operand" "=y")
1042 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1043 (match_operand:SI 2 "register_operand" "z")))]
1044 "TARGET_REALLY_IWMMXT"
1045 "wrorwg%?\\t%0, %1, %2"
1046 [(set_attr "predicable" "yes")])
1048 (define_insn "rordi3"
1049 [(set (match_operand:DI 0 "register_operand" "=y")
1050 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1051 (match_operand:SI 2 "register_operand" "z")))]
1052 "TARGET_REALLY_IWMMXT"
1053 "wrordg%?\\t%0, %1, %2"
1054 [(set_attr "predicable" "yes")])
1056 (define_insn "ashr<mode>3_iwmmxt"
1057 [(set (match_operand:VSHFT 0 "register_operand" "=y")
1058 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1059 (match_operand:SI 2 "register_operand" "z")))]
1060 "TARGET_REALLY_IWMMXT"
1061 "wsra<MMX_char>g%?\\t%0, %1, %2"
1062 [(set_attr "predicable" "yes")])
1064 (define_insn "lshr<mode>3_iwmmxt"
1065 [(set (match_operand:VSHFT 0 "register_operand" "=y")
1066 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1067 (match_operand:SI 2 "register_operand" "z")))]
1068 "TARGET_REALLY_IWMMXT"
1069 "wsrl<MMX_char>g%?\\t%0, %1, %2"
1070 [(set_attr "predicable" "yes")])
1072 (define_insn "ashl<mode>3_iwmmxt"
1073 [(set (match_operand:VSHFT 0 "register_operand" "=y")
1074 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1075 (match_operand:SI 2 "register_operand" "z")))]
1076 "TARGET_REALLY_IWMMXT"
1077 "wsll<MMX_char>g%?\\t%0, %1, %2"
1078 [(set_attr "predicable" "yes")])
1080 (define_insn "rorv4hi3_di"
1081 [(set (match_operand:V4HI 0 "register_operand" "=y")
1082 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1083 (match_operand:DI 2 "register_operand" "y")))]
1084 "TARGET_REALLY_IWMMXT"
1085 "wrorh%?\\t%0, %1, %2"
1086 [(set_attr "predicable" "yes")])
1088 (define_insn "rorv2si3_di"
1089 [(set (match_operand:V2SI 0 "register_operand" "=y")
1090 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1091 (match_operand:DI 2 "register_operand" "y")))]
1092 "TARGET_REALLY_IWMMXT"
1093 "wrorw%?\\t%0, %1, %2"
1094 [(set_attr "predicable" "yes")])
1096 (define_insn "rordi3_di"
1097 [(set (match_operand:DI 0 "register_operand" "=y")
1098 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1099 (match_operand:DI 2 "register_operand" "y")))]
1100 "TARGET_REALLY_IWMMXT"
1101 "wrord%?\\t%0, %1, %2"
1102 [(set_attr "predicable" "yes")])
1104 (define_insn "ashrv4hi3_di"
1105 [(set (match_operand:V4HI 0 "register_operand" "=y")
1106 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1107 (match_operand:DI 2 "register_operand" "y")))]
1108 "TARGET_REALLY_IWMMXT"
1109 "wsrah%?\\t%0, %1, %2"
1110 [(set_attr "predicable" "yes")])
1112 (define_insn "ashrv2si3_di"
1113 [(set (match_operand:V2SI 0 "register_operand" "=y")
1114 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1115 (match_operand:DI 2 "register_operand" "y")))]
1116 "TARGET_REALLY_IWMMXT"
1117 "wsraw%?\\t%0, %1, %2"
1118 [(set_attr "predicable" "yes")])
1120 (define_insn "ashrdi3_di"
1121 [(set (match_operand:DI 0 "register_operand" "=y")
1122 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1123 (match_operand:DI 2 "register_operand" "y")))]
1124 "TARGET_REALLY_IWMMXT"
1125 "wsrad%?\\t%0, %1, %2"
1126 [(set_attr "predicable" "yes")])
1128 (define_insn "lshrv4hi3_di"
1129 [(set (match_operand:V4HI 0 "register_operand" "=y")
1130 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1131 (match_operand:DI 2 "register_operand" "y")))]
1132 "TARGET_REALLY_IWMMXT"
1133 "wsrlh%?\\t%0, %1, %2"
1134 [(set_attr "predicable" "yes")])
1136 (define_insn "lshrv2si3_di"
1137 [(set (match_operand:V2SI 0 "register_operand" "=y")
1138 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1139 (match_operand:DI 2 "register_operand" "y")))]
1140 "TARGET_REALLY_IWMMXT"
1141 "wsrlw%?\\t%0, %1, %2"
1142 [(set_attr "predicable" "yes")])
1144 (define_insn "lshrdi3_di"
1145 [(set (match_operand:DI 0 "register_operand" "=y")
1146 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1147 (match_operand:DI 2 "register_operand" "y")))]
1148 "TARGET_REALLY_IWMMXT"
1149 "wsrld%?\\t%0, %1, %2"
1150 [(set_attr "predicable" "yes")])
1152 (define_insn "ashlv4hi3_di"
1153 [(set (match_operand:V4HI 0 "register_operand" "=y")
1154 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1155 (match_operand:DI 2 "register_operand" "y")))]
1156 "TARGET_REALLY_IWMMXT"
1157 "wsllh%?\\t%0, %1, %2"
1158 [(set_attr "predicable" "yes")])
1160 (define_insn "ashlv2si3_di"
1161 [(set (match_operand:V2SI 0 "register_operand" "=y")
1162 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1163 (match_operand:DI 2 "register_operand" "y")))]
1164 "TARGET_REALLY_IWMMXT"
1165 "wsllw%?\\t%0, %1, %2"
1166 [(set_attr "predicable" "yes")])
1168 (define_insn "ashldi3_di"
1169 [(set (match_operand:DI 0 "register_operand" "=y")
1170 (ashift:DI (match_operand:DI 1 "register_operand" "y")
1171 (match_operand:DI 2 "register_operand" "y")))]
1172 "TARGET_REALLY_IWMMXT"
1173 "wslld%?\\t%0, %1, %2"
1174 [(set_attr "predicable" "yes")])
1176 (define_insn "iwmmxt_wmadds"
1177 [(set (match_operand:V4HI 0 "register_operand" "=y")
1178 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1179 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1180 "TARGET_REALLY_IWMMXT"
1181 "wmadds%?\\t%0, %1, %2"
1182 [(set_attr "predicable" "yes")])
1184 (define_insn "iwmmxt_wmaddu"
1185 [(set (match_operand:V4HI 0 "register_operand" "=y")
1186 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1187 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1188 "TARGET_REALLY_IWMMXT"
1189 "wmaddu%?\\t%0, %1, %2"
1190 [(set_attr "predicable" "yes")])
1192 (define_insn "iwmmxt_tmia"
1193 [(set (match_operand:DI 0 "register_operand" "=y")
1194 (plus:DI (match_operand:DI 1 "register_operand" "0")
1195 (mult:DI (sign_extend:DI
1196 (match_operand:SI 2 "register_operand" "r"))
1197 (sign_extend:DI
1198 (match_operand:SI 3 "register_operand" "r")))))]
1199 "TARGET_REALLY_IWMMXT"
1200 "tmia%?\\t%0, %2, %3"
1201 [(set_attr "predicable" "yes")])
1203 (define_insn "iwmmxt_tmiaph"
1204 [(set (match_operand:DI 0 "register_operand" "=y")
1205 (plus:DI (match_operand:DI 1 "register_operand" "0")
1206 (plus:DI
1207 (mult:DI (sign_extend:DI
1208 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1209 (sign_extend:DI
1210 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1211 (mult:DI (sign_extend:DI
1212 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1213 (sign_extend:DI
1214 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1215 "TARGET_REALLY_IWMMXT"
1216 "tmiaph%?\\t%0, %2, %3"
1217 [(set_attr "predicable" "yes")])
1219 (define_insn "iwmmxt_tmiabb"
1220 [(set (match_operand:DI 0 "register_operand" "=y")
1221 (plus:DI (match_operand:DI 1 "register_operand" "0")
1222 (mult:DI (sign_extend:DI
1223 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1224 (sign_extend:DI
1225 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1226 "TARGET_REALLY_IWMMXT"
1227 "tmiabb%?\\t%0, %2, %3"
1228 [(set_attr "predicable" "yes")])
1230 (define_insn "iwmmxt_tmiatb"
1231 [(set (match_operand:DI 0 "register_operand" "=y")
1232 (plus:DI (match_operand:DI 1 "register_operand" "0")
1233 (mult:DI (sign_extend:DI
1234 (truncate:HI (ashiftrt:SI
1235 (match_operand:SI 2 "register_operand" "r")
1236 (const_int 16))))
1237 (sign_extend:DI
1238 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1239 "TARGET_REALLY_IWMMXT"
1240 "tmiatb%?\\t%0, %2, %3"
1241 [(set_attr "predicable" "yes")])
1243 (define_insn "iwmmxt_tmiabt"
1244 [(set (match_operand:DI 0 "register_operand" "=y")
1245 (plus:DI (match_operand:DI 1 "register_operand" "0")
1246 (mult:DI (sign_extend:DI
1247 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1248 (sign_extend:DI
1249 (truncate:HI (ashiftrt:SI
1250 (match_operand:SI 3 "register_operand" "r")
1251 (const_int 16)))))))]
1252 "TARGET_REALLY_IWMMXT"
1253 "tmiabt%?\\t%0, %2, %3"
1254 [(set_attr "predicable" "yes")])
1256 (define_insn "iwmmxt_tmiatt"
1257 [(set (match_operand:DI 0 "register_operand" "=y")
1258 (plus:DI (match_operand:DI 1 "register_operand" "0")
1259 (mult:DI (sign_extend:DI
1260 (truncate:HI (ashiftrt:SI
1261 (match_operand:SI 2 "register_operand" "r")
1262 (const_int 16))))
1263 (sign_extend:DI
1264 (truncate:HI (ashiftrt:SI
1265 (match_operand:SI 3 "register_operand" "r")
1266 (const_int 16)))))))]
1267 "TARGET_REALLY_IWMMXT"
1268 "tmiatt%?\\t%0, %2, %3"
1269 [(set_attr "predicable" "yes")])
1271 (define_insn "iwmmxt_tbcstqi"
1272 [(set (match_operand:V8QI 0 "register_operand" "=y")
1273 (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1274 "TARGET_REALLY_IWMMXT"
1275 "tbcstb%?\\t%0, %1"
1276 [(set_attr "predicable" "yes")])
1278 (define_insn "iwmmxt_tbcsthi"
1279 [(set (match_operand:V4HI 0 "register_operand" "=y")
1280 (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1281 "TARGET_REALLY_IWMMXT"
1282 "tbcsth%?\\t%0, %1"
1283 [(set_attr "predicable" "yes")])
1285 (define_insn "iwmmxt_tbcstsi"
1286 [(set (match_operand:V2SI 0 "register_operand" "=y")
1287 (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1288 "TARGET_REALLY_IWMMXT"
1289 "tbcstw%?\\t%0, %1"
1290 [(set_attr "predicable" "yes")])
1292 (define_insn "iwmmxt_tmovmskb"
1293 [(set (match_operand:SI 0 "register_operand" "=r")
1294 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1295 "TARGET_REALLY_IWMMXT"
1296 "tmovmskb%?\\t%0, %1"
1297 [(set_attr "predicable" "yes")])
1299 (define_insn "iwmmxt_tmovmskh"
1300 [(set (match_operand:SI 0 "register_operand" "=r")
1301 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1302 "TARGET_REALLY_IWMMXT"
1303 "tmovmskh%?\\t%0, %1"
1304 [(set_attr "predicable" "yes")])
1306 (define_insn "iwmmxt_tmovmskw"
1307 [(set (match_operand:SI 0 "register_operand" "=r")
1308 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1309 "TARGET_REALLY_IWMMXT"
1310 "tmovmskw%?\\t%0, %1"
1311 [(set_attr "predicable" "yes")])
1313 (define_insn "iwmmxt_waccb"
1314 [(set (match_operand:DI 0 "register_operand" "=y")
1315 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1316 "TARGET_REALLY_IWMMXT"
1317 "waccb%?\\t%0, %1"
1318 [(set_attr "predicable" "yes")])
1320 (define_insn "iwmmxt_wacch"
1321 [(set (match_operand:DI 0 "register_operand" "=y")
1322 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1323 "TARGET_REALLY_IWMMXT"
1324 "wacch%?\\t%0, %1"
1325 [(set_attr "predicable" "yes")])
1327 (define_insn "iwmmxt_waccw"
1328 [(set (match_operand:DI 0 "register_operand" "=y")
1329 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1330 "TARGET_REALLY_IWMMXT"
1331 "waccw%?\\t%0, %1"
1332 [(set_attr "predicable" "yes")])
1334 (define_insn "iwmmxt_walign"
1335 [(set (match_operand:V8QI 0 "register_operand" "=y,y")
1336 (subreg:V8QI (ashiftrt:TI
1337 (subreg:TI (vec_concat:V16QI
1338 (match_operand:V8QI 1 "register_operand" "y,y")
1339 (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1340 (mult:SI
1341 (match_operand:SI 3 "nonmemory_operand" "i,z")
1342 (const_int 8))) 0))]
1343 "TARGET_REALLY_IWMMXT"
1344 "@
1345 waligni%?\\t%0, %1, %2, %3
1346 walignr%U3%?\\t%0, %1, %2"
1347 [(set_attr "predicable" "yes")])
1349 (define_insn "iwmmxt_tmrc"
1350 [(set (match_operand:SI 0 "register_operand" "=r")
1351 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1352 VUNSPEC_TMRC))]
1353 "TARGET_REALLY_IWMMXT"
1354 "tmrc%?\\t%0, %w1"
1355 [(set_attr "predicable" "yes")])
1357 (define_insn "iwmmxt_tmcr"
1358 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1359 (match_operand:SI 1 "register_operand" "r")]
1360 VUNSPEC_TMCR)]
1361 "TARGET_REALLY_IWMMXT"
1362 "tmcr%?\\t%w0, %1"
1363 [(set_attr "predicable" "yes")])
1365 (define_insn "iwmmxt_wsadb"
1366 [(set (match_operand:V8QI 0 "register_operand" "=y")
1367 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1368 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1369 "TARGET_REALLY_IWMMXT"
1370 "wsadb%?\\t%0, %1, %2"
1371 [(set_attr "predicable" "yes")])
1373 (define_insn "iwmmxt_wsadh"
1374 [(set (match_operand:V4HI 0 "register_operand" "=y")
1375 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1376 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1377 "TARGET_REALLY_IWMMXT"
1378 "wsadh%?\\t%0, %1, %2"
1379 [(set_attr "predicable" "yes")])
1381 (define_insn "iwmmxt_wsadbz"
1382 [(set (match_operand:V8QI 0 "register_operand" "=y")
1383 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1384 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1385 "TARGET_REALLY_IWMMXT"
1386 "wsadbz%?\\t%0, %1, %2"
1387 [(set_attr "predicable" "yes")])
1389 (define_insn "iwmmxt_wsadhz"
1390 [(set (match_operand:V4HI 0 "register_operand" "=y")
1391 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1392 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1393 "TARGET_REALLY_IWMMXT"
1394 "wsadhz%?\\t%0, %1, %2"
1395 [(set_attr "predicable" "yes")])