| blob | fcf60cd08aa5971bd92af83c8f382b4f4fd91985 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
107 /* Number of attempts to combine instructions in this function. */
111 /* Number of attempts that got as far as substitution in this function. */
115 /* Number of instructions combined with added SETs in this function. */
119 /* Number of instructions combined in this function. */
123 /* Totals over entire compilation. */
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 \f
145 /* Record last point of death of (hard or pseudo) register n. */
146 rtx last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
149 rtx last_set;
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
158 following ways:
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
173 register's value
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
178 table.
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
196 rtx last_set_value;
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
203 /* Record the value of label_tick when the value for register n is placed in
204 last_set_value. */
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
231 zero.
233 If an entry is zero, it means that we don't know anything special. */
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
248 value. */
256 /* Record the luid of the last insn that invalidated memory
257 (anything that writes memory, and subroutine calls, but not pushes). */
261 /* Record the luid of the last CALL_INSN
262 so we can tell whether a potential combination crosses any calls. */
266 /* When `subst' is called, this is the insn that is being modified
267 (by combining in a previous insn). The PATTERN of this insn
268 is still the old pattern partially modified and it should not be
269 looked at, but this may be used to examine the successors of the insn
270 to judge whether a simplification is valid. */
274 /* This is the lowest LUID that `subst' is currently dealing with.
275 get_last_value will not return a value if the register was set at or
276 after this LUID. If not for this mechanism, we could get confused if
277 I2 or I1 in try_combine were an insn that used the old value of a register
278 to obtain a new value. In that case, we might erroneously get the
279 new value of the register when we wanted the old one. */
283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
284 must consider all these registers to be always live. */
288 /* This is an insn to which a LOG_LINKS entry has been added. If this
289 insn is the earlier than I2 or I3, combine should rescan starting at
290 that location. */
294 /* Basic block in which we are performing combines. */
298 \f
299 /* Length of the currently allocated uid_insn_cost array. */
303 /* The following array records the insn_rtx_cost for every insn
304 in the instruction stream. */
308 /* The following array records the LOG_LINKS for every insn in the
309 instruction stream as struct insn_link pointers. */
312 rtx insn;
314 };
318 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
319 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
321 #define FOR_EACH_LOG_LINK(L, INSN) \
322 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
324 /* Links for LOG_LINKS are allocated from this obstack. */
328 /* Allocate a link. */
332 {
339 }
341 /* Incremented for each basic block. */
345 /* Reset to label_tick for each extended basic block in scanning order. */
349 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
350 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
355 be safely used. It is zero while computing them and after combine has
356 completed. This former test prevents propagating values based on
357 previously set values, which can be incorrect if a variable is modified
358 in a loop. */
362 \f
363 /* Record one modification to rtl structure
364 to be undone by storing old_contents into *where. */
368 struct undo
369 {
374 };
376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
377 num_undo says how many are currently recorded.
379 other_insn is nonzero if we have modified some other insn in the process
380 of working on subst_insn. It must be verified too. */
382 struct undobuf
383 {
386 rtx other_insn;
387 };
391 /* Number of times the pseudo being substituted for
392 was found and replaced. */
472 \f
474 /* It is not safe to use ordinary gen_lowpart in combine.
475 See comments in gen_lowpart_for_combine. */
476 #undef RTL_HOOKS_GEN_LOWPART
477 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
479 /* Our implementation of gen_lowpart never emits a new pseudo. */
480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
484 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
494 \f
495 /* Convenience wrapper for the canonicalize_comparison target hook.
496 Target hooks cannot use enum rtx_code. */
500 {
504 }
506 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
507 PATTERN can not be split. Otherwise, it returns an insn sequence.
508 This is a wrapper around split_insns which ensures that the
509 reg_stat vector is made larger if the splitter creates a new
510 register. */
512 static rtx
514 {
515 rtx ret;
523 }
525 /* This is used by find_single_use to locate an rtx in LOC that
526 contains exactly one use of DEST, which is typically either a REG
527 or CC0. It returns a pointer to the innermost rtx expression
528 containing DEST. Appearances of DEST that are being used to
529 totally replace it are not counted. */
533 {
542 {
546 CASE_CONST_ANY:
551 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
552 of a REG that occupies all of the REG, the insn uses DEST if
553 it is mentioned in the destination or the source. Otherwise, we
554 need just check the source. */
574 }
576 /* If it wasn't one of the common cases above, check each expression and
577 vector of this code. Look for a unique usage of DEST. */
581 {
583 {
588 else
594 /* Duplicate usage. */
596 }
598 {
602 {
608 else
615 }
616 }
617 }
620 }
623 /* See if DEST, produced in INSN, is used only a single time in the
624 sequel. If so, return a pointer to the innermost rtx expression in which
625 it is used.
627 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
629 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
630 care about REG_DEAD notes or LOG_LINKS.
632 Otherwise, we find the single use by finding an insn that has a
633 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
634 only referenced once in that insn, we know that it must be the first
635 and last insn referencing DEST. */
639 {
640 basic_block bb;
641 rtx next;
645 #ifdef HAVE_cc0
647 {
657 }
658 #endif
668 {
674 {
679 }
680 }
683 }
684 \f
685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
686 insn. The substitution can be undone by undo_all. If INTO is already
687 set to NEWVAL, do not record this change. Because computing NEWVAL might
688 also call SUBST, we have to compute it before we put anything into
689 the undo table. */
691 static void
693 {
700 /* We'd like to catch as many invalid transformations here as
701 possible. Unfortunately, there are way too many mode changes
702 that are perfectly valid, so we'd waste too much effort for
703 little gain doing the checks here. Focus on catching invalid
704 transformations involving integer constants. */
707 {
708 /* Sanity check that we're replacing oldval with a CONST_INT
709 that is a valid sign-extension for the original mode. */
713 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
714 CONST_INT is not valid, because after the replacement, the
715 original mode would be gone. Unfortunately, we can't tell
716 when do_SUBST is called to replace the operand thereof, so we
717 perform this test on oldval instead, checking whether an
718 invalid replacement took place before we got here. */
723 }
727 else
736 }
738 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
740 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
741 for the value of a HOST_WIDE_INT value (including CONST_INT) is
742 not safe. */
744 static void
746 {
755 else
764 }
766 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
768 /* Similar to SUBST, but just substitute the mode. This is used when
769 changing the mode of a pseudo-register, so that any other
770 references to the entry in the regno_reg_rtx array will change as
771 well. */
773 static void
775 {
784 else
793 }
795 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
797 #ifndef HAVE_cc0
798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
800 static void
802 {
811 else
820 }
822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
823 #endif
824 \f
825 /* Subroutine of try_combine. Determine whether the replacement patterns
826 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
827 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
828 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
829 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
830 of all the instructions can be estimated and the replacements are more
831 expensive than the original sequence. */
833 static bool
836 {
841 /* Lookup the original insn_rtx_costs. */
846 {
849 {
853 }
854 else
855 {
859 }
860 }
861 else
862 {
865 }
867 /* Calculate the replacement insn_rtx_costs. */
870 {
874 }
875 else
876 {
879 }
882 {
888 {
891 }
892 else
894 }
896 /* Disallow this combination if both new_cost and old_cost are greater than
897 zero, and new_cost is greater than old cost. */
899 {
901 {
903 {
910 }
912 {
918 }
919 else
920 {
926 }
929 {
932 }
933 else
935 }
938 }
940 /* Update the uid_insn_cost array with the replacement costs. */
944 {
948 }
951 }
954 /* Delete any insns that copy a register to itself. */
956 static void
958 {
960 basic_block bb;
963 {
965 {
968 {
973 }
974 }
975 }
976 }
978 \f
979 /* Fill in log links field for all insns. */
981 static void
983 {
984 basic_block bb;
990 /* Pass through each block from the end, recording the uses of each
991 register and establishing log links when def is encountered.
992 Note that we do not clear next_use array in order to save time,
993 so we have to test whether the use is in the same basic block as def.
995 There are a few cases below when we do not consider the definition or
996 usage -- these are taken from original flow.c did. Don't ask me why it is
997 done this way; I don't know and if it works, I don't want to know. */
1000 {
1002 {
1006 /* Log links are created only once. */
1010 {
1013 rtx use_insn;
1018 /* Do not consider if it is pre/post modification in MEM. */
1022 /* Do not make the log link for frame pointer. */
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1028 #endif
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1031 #endif
1032 )
1037 {
1038 /* flow.c claimed:
1040 We don't build a LOG_LINK for hard registers contained
1041 in ASM_OPERANDs. If these registers get replaced,
1042 we might wind up changing the semantics of the insn,
1043 even if reload can make what appear to be valid
1044 assignments later. */
1047 {
1048 /* Don't add duplicate links between instructions. */
1057 }
1058 }
1060 }
1063 {
1067 /* Do not consider the usage of the stack pointer
1068 by function call. */
1073 }
1074 }
1075 }
1078 }
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1081 true if we found a LOG_LINK that proves that A feeds B. This only works
1082 if there are no instructions between A and B which could have a link
1083 depending on A, since in that case we would not record a link for B.
1084 We also check the implicit dependency created by a cc0 setter/user
1085 pair. */
1087 static bool
1089 {
1094 #ifdef HAVE_cc0
1097 #endif
1099 }
1100 \f
1101 /* Main entry point for combiner. F is the first insn of the function.
1102 NREGS is the first unused pseudo-reg number.
1104 Return nonzero if the combiner has turned an indirect jump
1105 instruction into a direct jump. */
1106 static int
1108 {
1110 #ifdef HAVE_cc0
1111 rtx prev;
1112 #endif
1114 rtx first;
1115 basic_block last_bb;
1135 /* Allocate array for insn info. */
1143 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1144 problems when, for example, we have j <<= 1 in a loop. */
1149 /* Scan all SETs and see if we can deduce anything about what
1150 bits are known to be zero for some registers and how many copies
1151 of the sign bit are known to exist for those registers.
1153 Also set any known values so that we can use it while searching
1154 for what bits are known to be set. */
1157 /* Allow the entry block and the first block to fall into the same EBB.
1158 Conceptually the incoming promotions are assigned to the entry block. */
1163 {
1168 label_tick++;
1176 {
1177 #ifdef AUTO_INC_DEC
1178 rtx links;
1179 #endif
1185 insn);
1188 #ifdef AUTO_INC_DEC
1192 insn);
1193 #endif
1195 /* Record the current insn_rtx_cost of this instruction. */
1198 optimize_this_for_speed_p);
1202 }
1203 }
1207 /* Now scan all the insns in forward order. */
1214 {
1220 label_tick++;
1230 {
1233 {
1243 /* See if we know about function return values before this
1244 insn based upon SUBREG flags. */
1247 /* See if we can find hardregs and subreg of pseudos in
1248 narrower modes. This could help turning TRUNCATEs
1249 into SUBREGs. */
1252 /* Try this insn with each insn it links back to. */
1260 /* Try each sequence of three linked insns ending with this one. */
1263 {
1266 /* If the linked insn has been replaced by a note, then there
1267 is no point in pursuing this chain any further. */
1276 }
1278 #ifdef HAVE_cc0
1279 /* Try to combine a jump insn that uses CC0
1280 with a preceding insn that sets CC0, and maybe with its
1281 logical predecessor as well.
1282 This is how we make decrement-and-branch insns.
1283 We need this special code because data flow connections
1284 via CC0 do not get entered in LOG_LINKS. */
1290 {
1301 }
1303 /* Do the same for an insn that explicitly references CC0. */
1310 {
1321 }
1323 /* Finally, see if any of the insns that this insn links to
1324 explicitly references CC0. If so, try this insn, that insn,
1325 and its predecessor if it sets CC0. */
1337 #endif
1339 /* Try combining an insn with two different insns whose results it
1340 uses. */
1350 /* Try four-instruction combinations. */
1352 {
1356 /* If the linked insn has been replaced by a note, then there
1357 is no point in pursuing this chain any further. */
1362 {
1366 /* I0 -> I1 -> I2 -> I3. */
1373 /* I0, I1 -> I2, I2 -> I3. */
1381 }
1384 {
1388 /* I0 -> I2; I1, I2 -> I3. */
1395 /* I0 -> I1; I1, I2 -> I3. */
1402 }
1403 }
1405 /* Try this insn with each REG_EQUAL note it links back to. */
1407 {
1413 /* Avoid using a register that may already been marked
1414 dead by an earlier instruction. */
1419 {
1420 /* Temporarily replace the set's source with the
1421 contents of the REG_EQUAL note. The insn will
1422 be deleted or recognized by try_combine. */
1430 last_combined_insn);
1435 }
1436 }
1441 retry:
1442 ;
1443 }
1444 }
1445 }
1452 /* Clean up. */
1458 {
1461 {
1464 }
1466 }
1476 /* Make recognizer allow volatile MEMs again. */
1480 }
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1484 static void
1486 {
1492 }
1493 \f
1494 /* Set up any promoted values for incoming argument registers. */
1496 static void
1498 {
1499 tree arg;
1504 {
1509 /* Only continue if the incoming argument is in a register. */
1513 /* Determine, if possible, whether all call sites of the current
1514 function lie within the current compilation unit. (This does
1515 take into account the exporting of a function via taking its
1516 address, and so forth.) */
1519 /* The mode and signedness of the argument before any promotions happen
1520 (equal to the mode of the pseudo holding it at that stage). */
1524 /* The mode and signedness of the argument after any source language and
1525 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1529 /* The mode and signedness of the argument as it is actually passed,
1530 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1534 /* The mode of the register in which the argument is being passed. */
1537 /* Eliminate sign extensions in the callee when:
1538 (a) A mode promotion has occurred; */
1541 /* (b) The mode of the register is the same as the mode of
1542 the argument as it is passed; */
1545 /* (c) There's no language level extension; */
1547 ;
1548 /* (c.1) All callers are from the current compilation unit. If that's
1549 the case we don't have to rely on an ABI, we only have to know
1550 what we're generating right now, and we know that we will do the
1551 mode1 to mode2 promotion with the given sign. */
1554 /* (c.2) The combination of the two promotions is useful. This is
1555 true when the signs match, or if the first promotion is unsigned.
1556 In the later case, (sign_extend (zero_extend x)) is the same as
1557 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1563 /* Record that the value was promoted from mode1 to mode3,
1564 so that any sign extension at the head of the current
1565 function may be eliminated. */
1569 }
1570 }
1572 /* Called via note_stores. If X is a pseudo that is narrower than
1573 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1575 If we are setting only a portion of X and we can't figure out what
1576 portion, assume all bits will be used since we don't know what will
1577 be happening.
1579 Similarly, set how many bits of X are known to be copies of the sign bit
1580 at all locations in the function. This is the smallest number implied
1581 by any set of X. */
1583 static void
1585 {
1591 /* If this register is undefined at the start of the file, we can't
1592 say what its contents were. */
1593 && ! REGNO_REG_SET_P
1596 {
1600 {
1604 }
1606 /* If this register is being initialized using itself, and the
1607 register is uninitialized in this basic block, and there are
1608 no LOG_LINKS which set the register, then part of the
1609 register is uninitialized. In that case we can't assume
1610 anything about the number of nonzero bits.
1612 ??? We could do better if we checked this in
1613 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1614 could avoid making assumptions about the insn which initially
1615 sets the register, while still using the information in other
1616 insns. We would have to be careful to check every insn
1617 involved in the combination. */
1623 {
1630 {
1634 }
1635 }
1637 /* If this is a complex assignment, see if we can convert it into a
1638 simple assignment. */
1641 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642 set what we know about X. */
1647 {
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651 /* If X is narrower than a word and SRC is a non-negative
1652 constant that would appear negative in the mode of X,
1653 sign-extend it for use in reg_stat[].nonzero_bits because some
1654 machines (maybe most) will actually do the sign-extension
1655 and this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard
1658 instead of this kludge. */
1665 #endif
1667 /* Don't call nonzero_bits if it cannot change anything. */
1674 }
1675 else
1676 {
1679 }
1680 }
1681 }
1682 \f
1683 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1684 optionally insns that were previously combined into I3 or that will be
1685 combined into the merger of INSN and I3. The order is PRED, PRED2,
1686 INSN, SUCC, SUCC2, I3.
1688 Return 0 if the combination is not allowed for any reason.
1690 If the combination is allowed, *PDEST will be set to the single
1691 destination of INSN and *PSRC to the single source, and this function
1692 will return 1. */
1694 static int
1698 {
1702 rtx p;
1703 #ifdef AUTO_INC_DEC
1704 rtx link;
1705 #endif
1710 {
1712 {
1717 }
1722 }
1726 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727 or a PARALLEL consisting of such a SET and CLOBBERs.
1729 If INSN has CLOBBER parallel parts, ignore them for our processing.
1730 By definition, these happen during the execution of the insn. When it
1731 is merged with another insn, all bets are off. If they are, in fact,
1732 needed and aren't also supplied in I3, they may be added by
1733 recog_for_combine. Otherwise, it won't match.
1735 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1736 note.
1738 Get the source and destination of INSN. If more than one, can't
1739 combine. */
1745 {
1747 {
1751 {
1752 /* This is important to combine floating point insns
1753 for the SH4 port. */
1755 /* Combining an isolated USE doesn't make sense.
1756 We depend here on combinable_i3pat to reject them. */
1757 /* The code below this loop only verifies that the inputs of
1758 the SET in INSN do not change. We call reg_set_between_p
1759 to verify that the REG in the USE does not change between
1760 I3 and INSN.
1761 If the USE in INSN was for a pseudo register, the matching
1762 insn pattern will likely match any register; combining this
1763 with any other USE would only be safe if we knew that the
1764 used registers have identical values, or if there was
1765 something to tell them apart, e.g. different modes. For
1766 now, we forgo such complicated tests and simply disallow
1767 combining of USES of pseudo registers with any other USE. */
1770 {
1775 do
1776 {
1786 }
1788 }
1791 /* We can ignore CLOBBERs. */
1796 /* Ignore SETs whose result isn't used but not those that
1797 have side-effects. */
1803 /* If we have already found a SET, this is a second one and
1804 so we cannot combine with this insn. */
1812 /* Anything else means we can't combine. */
1814 }
1815 }
1818 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819 so don't do anything with it. */
1822 }
1823 else
1829 /* The simplification in expand_field_assignment may call back to
1830 get_last_value, so set safe guard here. */
1836 /* Don't eliminate a store in the stack pointer. */
1838 /* Don't combine with an insn that sets a register to itself if it has
1839 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1841 /* Can't merge an ASM_OPERANDS. */
1843 /* Can't merge a function call. */
1845 /* Don't eliminate a function call argument. */
1851 /* Don't substitute into an incremented register. */
1855 /* Don't substitute into a non-local goto, this confuses CFG. */
1857 /* Make sure that DEST is not used after SUCC but before I3. */
1858 || (!all_adjacent
1859 && ((succ2
1863 /* Make sure that the value that is to be substituted for the register
1864 does not use any registers whose values alter in between. However,
1865 If the insns are adjacent, a use can't cross a set even though we
1866 think it might (this can happen for a sequence of insns each setting
1867 the same destination; last_set of that register might point to
1868 a NOTE). If INSN has a REG_EQUIV note, the register is always
1869 equivalent to the memory so the substitution is valid even if there
1870 are intervening stores. Also, don't move a volatile asm or
1871 UNSPEC_VOLATILE across any other insns. */
1872 || (! all_adjacent
1878 /* Don't combine across a CALL_INSN, because that would possibly
1879 change whether the life span of some REGs crosses calls or not,
1880 and it is a pain to update that information.
1881 Exception: if source is a constant, moving it later can't hurt.
1882 Accept that as a special case. */
1886 /* DEST must either be a REG or CC0. */
1888 {
1889 /* If register alignment is being enforced for multi-word items in all
1890 cases except for parameters, it is possible to have a register copy
1891 insn referencing a hard register that is not allowed to contain the
1892 mode being copied and which would not be valid as an operand of most
1893 insns. Eliminate this problem by not combining with such an insn.
1895 Also, on some machines we don't want to extend the life of a hard
1896 register. */
1901 /* Don't extend the life of a hard register unless it is
1902 user variable (if we have few registers) or it can't
1903 fit into the desired register (meaning something special
1904 is going on).
1905 Also avoid substituting a return register into I3, because
1906 reload can't handle a conflict with constraints of other
1907 inputs. */
1911 }
1919 {
1920 /* Don't substitute for a register intended as a clobberable
1921 operand. */
1926 /* If the clobber represents an earlyclobber operand, we must not
1927 substitute an expression containing the clobbered register.
1928 As we do not analyze the constraint strings here, we have to
1929 make the conservative assumption. However, if the register is
1930 a fixed hard reg, the clobber cannot represent any operand;
1931 we leave it up to the machine description to either accept or
1932 reject use-and-clobber patterns. */
1938 }
1940 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941 or not), reject, unless nothing volatile comes between it and I3 */
1944 {
1945 /* Make sure neither succ nor succ2 contains a volatile reference. */
1950 /* We'll check insns between INSN and I3 below. */
1951 }
1953 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954 to be an explicit register variable, and was chosen for a reason. */
1960 /* If INSN contains volatile references (specifically volatile MEMs),
1961 we cannot combine across any other volatile references.
1962 Even if INSN doesn't contain volatile references, any intervening
1963 volatile insn might affect machine state. */
1966 ? volatile_refs_p
1973 /* If INSN contains an autoincrement or autodecrement, make sure that
1974 register is not used between there and I3, and not already used in
1975 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1976 Also insist that I3 not be a jump; if it were one
1977 and the incremented register were spilled, we would lose. */
1979 #ifdef AUTO_INC_DEC
1994 #endif
1996 #ifdef HAVE_cc0
1997 /* Don't combine an insn that follows a CC0-setting insn.
1998 An insn that uses CC0 must not be separated from the one that sets it.
1999 We do, however, allow I2 to follow a CC0-setting insn if that insn
2000 is passed as I1; in that case it will be deleted also.
2001 We also allow combining in this case if all the insns are adjacent
2002 because that would leave the two CC0 insns adjacent as well.
2003 It would be more logical to test whether CC0 occurs inside I1 or I2,
2004 but that would be much slower, and this ought to be equivalent. */
2010 #endif
2012 /* If we get here, we have passed all the tests and the combination is
2013 to be allowed. */
2019 }
2020 \f
2021 /* LOC is the location within I3 that contains its pattern or the component
2022 of a PARALLEL of the pattern. We validate that it is valid for combining.
2024 One problem is if I3 modifies its output, as opposed to replacing it
2025 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026 doing so would produce an insn that is not equivalent to the original insns.
2028 Consider:
2030 (set (reg:DI 101) (reg:DI 100))
2031 (set (subreg:SI (reg:DI 101) 0) <foo>)
2033 This is NOT equivalent to:
2035 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036 (set (reg:DI 101) (reg:DI 100))])
2038 Not only does this modify 100 (in which case it might still be valid
2039 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2041 We can also run into a problem if I2 sets a register that I1
2042 uses and I1 gets directly substituted into I3 (not via I2). In that
2043 case, we would be getting the wrong value of I2DEST into I3, so we
2044 must reject the combination. This case occurs when I2 and I1 both
2045 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047 of a SET must prevent combination from occurring. The same situation
2048 can occur for I0, in which case I0_NOT_IN_SRC is set.
2050 Before doing the above check, we first try to expand a field assignment
2051 into a set of logical operations.
2053 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054 we place a register that is both set and used within I3. If more than one
2055 such register is detected, we fail.
2057 Return 1 if the combination is valid, zero otherwise. */
2059 static int
2062 {
2066 {
2071 rtx subdest;
2078 /* Check for the case where I3 modifies its output, as discussed
2079 above. We don't want to prevent pseudos from being combined
2080 into the address of a MEM, so only prevent the combination if
2081 i1 or i2 set the same MEM. */
2091 /* This is the same test done in can_combine_p except we can't test
2092 all_adjacent; we don't have to, since this instruction will stay
2093 in place, thus we are not considering increasing the lifetime of
2094 INNER_DEST.
2096 Also, if this insn sets a function argument, combining it with
2097 something that might need a spill could clobber a previous
2098 function argument; the all_adjacent test in can_combine_p also
2099 checks this; here, we do a more specific test for this case. */
2109 /* If DEST is used in I3, it is being killed in this insn, so
2110 record that for later. We have to consider paradoxical
2111 subregs here, since they kill the whole register, but we
2112 ignore partial subregs, STRICT_LOW_PART, etc.
2113 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114 STACK_POINTER_REGNUM, since these are always considered to be
2115 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2127 #endif
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2131 #endif
2133 {
2138 }
2139 }
2142 {
2149 }
2152 }
2153 \f
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155 and division. We don't count multiplications by powers of two here. */
2157 static int
2159 {
2161 {
2177 }
2178 }
2179 \f
2180 /* Determine whether INSN can be used in a combination. Return nonzero if
2181 not. This is used in try_combine to detect early some cases where we
2182 can't perform combinations. */
2184 static int
2186 {
2187 rtx set;
2190 /* If this isn't really an insn, we can't do anything.
2191 This can occur when flow deletes an insn that it has merged into an
2192 auto-increment address. */
2196 /* Never combine loads and stores involving hard regs that are likely
2197 to be spilled. The register allocator can usually handle such
2198 reg-reg moves by tying. If we allow the combiner to make
2199 substitutions of likely-spilled regs, reload might die.
2200 As an exception, we allow combinations involving fixed regs; these are
2201 not available to the register allocator so there's no risk involved. */
2222 }
2224 struct likely_spilled_retval_info
2225 {
2228 };
2230 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2231 hard registers that are known to be written to / clobbered in full. */
2232 static void
2234 {
2251 else
2254 }
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257 it is likely spilled. This can happen when more than one insn is needed
2258 to copy the return value, e.g. when we consider to combine into the
2259 second copy insn for a complex value. */
2261 static int
2263 {
2267 /* We assume here that no machine mode needs more than
2268 32 hard registers when the value overlaps with a register
2269 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2284 /* Disregard parts of the return value that are set later. */
2293 /* Check if any of the (probably) live return value registers is
2294 likely spilled. */
2295 nregs --;
2296 do
2297 {
2303 }
2305 /* Adjust INSN after we made a change to its destination.
2307 Changing the destination can invalidate notes that say something about
2308 the results of the insn and a LOG_LINK pointing to the insn. */
2310 static void
2312 {
2313 /* For notes, be conservative and simply remove them. */
2316 /* The new insn will have a destination that was previously the destination
2317 of an insn just above it. Call distribute_links to make a LOG_LINK from
2318 the next use of that destination. */
2322 }
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325 ADDED_SETS is nonzero if the original set is still required. */
2326 static bool
2328 {
2335 /* Allow hard registers if the new mode is legal, and occupies no more
2336 registers than the old mode. */
2342 /* Or a pseudo that is only used once. */
2345 }
2348 /* Check whether X, the destination of a set, refers to part of
2349 the register specified by REG. */
2351 static bool
2353 {
2354 /* Check that reg is an integer mode register. */
2365 }
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368 Note that the INSN should be deleted *after* removing dead edges, so
2369 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370 but not for a (set (pc) (label_ref FOO)). */
2372 static void
2374 {
2382 {
2383 rtx insn;
2387 /* Remove barriers from the footer if there are any. */
2390 {
2393 else
2397 }
2400 }
2401 }
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404 Here I0, I1 and I2 appear earlier than I3.
2405 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2406 I3.
2408 If we are combining more than two insns and the resulting insn is not
2409 recognized, try splitting it into two insns. If that happens, I2 and I3
2410 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411 Otherwise, I0, I1 and I2 are pseudo-deleted.
2413 Return 0 if the combination does not work. Then nothing is changed.
2414 If we did the combination, return the insn at which combine should
2415 resume scanning.
2417 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418 new direct jump instruction.
2420 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421 been I3 passed to an earlier try_combine within the same basic
2422 block. */
2424 static rtx
2426 rtx last_combined_insn)
2427 {
2428 /* New patterns for I3 and I2, respectively. */
2432 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2433 dead. */
2435 /* Total number of SETs to put into I3. */
2437 /* Nonzero if I2's or I1's body now appears in I3. */
2439 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2441 /* Contains I3 if the destination of I3 is used in its source, which means
2442 that the old life of I3 is being killed. If that usage is placed into
2443 I2 and not in I3, a REG_DEAD note must be made. */
2445 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2447 /* Copy of SET_SRC of I1 and I0, if needed. */
2449 /* Set if I2DEST was reused as a scratch register. */
2451 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2453 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2458 /* Notes that must be added to REG_NOTES in I3 and I2. */
2460 /* Notes that we substituted I3 into I2 instead of the normal case. */
2462 /* Notes that I1, I2 or I3 is a MULT operation. */
2468 rtx temp;
2471 rtx new_other_notes;
2474 /* Only try four-insn combinations when there's high likelihood of
2475 success. Look for simple insns, such as loads of constants or
2476 binary operations involving a constant. */
2478 {
2487 {
2490 rtx src;
2495 {
2498 }
2500 ngood++;
2503 nshift++;
2504 }
2507 }
2509 /* Exit early if one of the insns involved can't be used for
2510 combinations. */
2518 combine_attempts++;
2521 /* Reset the hard register usage information. */
2525 {
2532 else
2535 }
2537 /* If multiple insns feed into one of I2 or I3, they can be in any
2538 order. To simplify the code below, reorder them in sequence. */
2548 /* First check for one important special case that the code below will
2549 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2550 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2551 we may be able to replace that destination with the destination of I3.
2552 This occurs in the common code where we compute both a quotient and
2553 remainder into a structure, in which case we want to do the computation
2554 directly into the structure to avoid register-register copies.
2556 Note that this case handles both multiple sets in I2 and also cases
2557 where I2 has a number of CLOBBERs inside the PARALLEL.
2559 We make very conservative checks below and only try to handle the
2560 most common cases of this. For example, we only handle the case
2561 where I2 and I3 are adjacent to avoid making difficult register
2562 usage tests. */
2570 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571 below would need to check what is inside (and reg_overlap_mentioned_p
2572 doesn't support those codes anyway). Don't allow those destinations;
2573 the resulting insn isn't likely to be recognized anyway. */
2579 {
2582 /* Make sure that the destination of I3,
2583 which we are going to substitute into one output of I2,
2584 is not used within another output of I2. We must avoid making this:
2585 (parallel [(set (mem (reg 69)) ...)
2586 (set (reg 69) ...)])
2587 which is not well-defined as to order of actions.
2588 (Besides, reload can't handle output reloads for this.)
2590 The problem can also happen if the dest of I3 is a memory ref,
2591 if another dest in I2 is an indirect memory ref. */
2603 {
2604 combine_merges++;
2614 /* Replace the dest in I2 with our dest and make the resulting
2615 insn the new pattern for I3. Then skip to where we validate
2616 the pattern. Everything was set up above. */
2621 }
2622 }
2624 /* If I2 is setting a pseudo to a constant and I3 is setting some
2625 sub-part of it to another constant, merge them by making a new
2626 constant. */
2633 {
2639 {
2642 {
2648 }
2649 }
2650 else
2651 {
2656 }
2659 {
2660 /* If this is the low part, we're done. */
2662 ;
2663 /* Handle the case where inner is twice the size of outer. */
2667 /* Otherwise give up for now. */
2668 else
2670 }
2675 {
2689 combine_merges++;
2696 /* Replace the source in I2 with the new constant and make the
2697 resulting insn the new pattern for I3. Then skip to where we
2698 validate the pattern. Everything was set up above. */
2704 /* The dest of I3 has been replaced with the dest of I2. */
2707 }
2708 }
2710 #ifndef HAVE_cc0
2711 /* If we have no I1 and I2 looks like:
2712 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2713 (set Y OP)])
2714 make up a dummy I1 that is
2715 (set Y OP)
2716 and change I2 to be
2717 (set (reg:CC X) (compare:CC Y (const_int 0)))
2719 (We can ignore any trailing CLOBBERs.)
2721 This undoes a previous combination and allows us to match a branch-and-
2722 decrement insn. */
2735 {
2741 {
2742 /* We make I1 with the same INSN_UID as I2. This gives it
2743 the same DF_INSN_LUID for value tracking. Our fake I1 will
2744 never appear in the insn stream so giving it the same INSN_UID
2745 as I2 will not cause a problem. */
2755 }
2756 }
2757 #endif
2759 /* Verify that I2 and I1 are valid for combining. */
2765 {
2768 }
2770 /* Record whether I2DEST is used in I2SRC and similarly for the other
2771 cases. Knowing this will help in register status updating below. */
2782 /* For the earlier insns, determine which of the subsequent ones they
2783 feed. */
2790 /* Ensure that I3's pattern can be the destination of combines. */
2796 {
2799 }
2801 /* See if any of the insns is a MULT operation. Unless one is, we will
2802 reject a combination that is, since it must be slower. Be conservative
2803 here. */
2811 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2812 We used to do this EXCEPT in one case: I3 has a post-inc in an
2813 output operand. However, that exception can give rise to insns like
2814 mov r3,(r3)+
2815 which is a famous insn on the PDP-11 where the value of r3 used as the
2816 source was model-dependent. Avoid this sort of thing. */
2818 #if 0
2824 /* It's not the exception. */
2825 #endif
2826 #ifdef AUTO_INC_DEC
2827 {
2828 rtx link;
2834 {
2837 }
2838 }
2839 #endif
2841 /* See if the SETs in I1 or I2 need to be kept around in the merged
2842 instruction: whenever the value set there is still needed past I3.
2843 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2845 For the SET in I1, we have two cases: if I1 and I2 independently feed
2846 into I3, the set in I1 needs to be kept around unless I1DEST dies
2847 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2848 in I1 needs to be kept around unless I1DEST dies or is set in either
2849 I2 or I3. The same considerations apply to I0. */
2856 else
2864 else
2867 /* We are about to copy insns for the case where they need to be kept
2868 around. Check that they can be copied in the merged instruction. */
2874 {
2877 }
2879 /* If the set in I2 needs to be kept around, we must make a copy of
2880 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2881 PATTERN (I2), we are only substituting for the original I1DEST, not into
2882 an already-substituted copy. This also prevents making self-referential
2883 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2884 I2DEST. */
2887 {
2890 else
2892 }
2895 {
2898 else
2900 }
2903 {
2906 else
2908 }
2910 combine_merges++;
2912 /* Substitute in the latest insn for the regs set by the earlier ones. */
2918 #ifndef HAVE_cc0
2919 /* Many machines that don't use CC0 have insns that can both perform an
2920 arithmetic operation and set the condition code. These operations will
2921 be represented as a PARALLEL with the first element of the vector
2922 being a COMPARE of an arithmetic operation with the constant zero.
2923 The second element of the vector will set some pseudo to the result
2924 of the same arithmetic operation. If we simplify the COMPARE, we won't
2925 match such a pattern and so will generate an extra insn. Here we test
2926 for this case, where both the comparison and the operation result are
2927 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2928 I2SRC. Later we will make the PARALLEL that contains I2. */
2934 {
2935 rtx newpat_dest;
2948 {
2953 }
2955 /* Do the rest only if op1 is const0_rtx, which may be the
2956 result of simplification. */
2958 {
2959 /* If a single use of the CC is found, prepare to modify it
2960 when SELECT_CC_MODE returns a new CC-class mode, or when
2961 the above simplify_compare_const() returned a new comparison
2962 operator. undobuf.other_insn is assigned the CC use insn
2963 when modifying it. */
2965 {
2966 #ifdef SELECT_CC_MODE
2967 enum machine_mode new_mode
2972 {
2977 else
2978 {
2981 }
2982 }
2983 #endif
2984 /* Cases for modifying the CC-using comparison. */
2986 /* ??? Do we need to verify the zero rtx? */
2988 {
2989 /* Replace cc_use_loc with entire new RTX. */
2994 }
2996 {
2997 /* Just replace the CC reg with a new mode. */
3000 }
3001 }
3003 /* Now we modify the current newpat:
3004 First, SET_DEST(newpat) is updated if the CC mode has been
3005 altered. For targets without SELECT_CC_MODE, this should be
3006 optimized away. */
3009 /* This is always done to propagate i2src into newpat. */
3012 /* Create new version of i2pat if needed; the below PARALLEL
3013 creation needs this to work correctly. */
3017 }
3018 }
3019 #endif
3022 {
3023 /* It is possible that the source of I2 or I1 may be performing
3024 an unneeded operation, such as a ZERO_EXTEND of something
3025 that is known to have the high part zero. Handle that case
3026 by letting subst look at the inner insns.
3028 Another way to do this would be to have a function that tries
3029 to simplify a single insn instead of merging two or more
3030 insns. We don't do this because of the potential of infinite
3031 loops and because of the potential extra memory required.
3032 However, doing it the way we are is a bit of a kludge and
3033 doesn't catch all cases.
3035 But only do this if -fexpensive-optimizations since it slows
3036 things down and doesn't usually win.
3038 This is not done in the COMPARE case above because the
3039 unmodified I2PAT is used in the PARALLEL and so a pattern
3040 with a modified I2SRC would not match. */
3043 {
3044 /* Pass pc_rtx so no substitutions are done, just
3045 simplifications. */
3047 {
3050 }
3054 }
3059 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3060 copy of I2SRC each time we substitute it, in order to avoid creating
3061 self-referential RTL when we will be substituting I1SRC for I1DEST
3062 later. Likewise if I0 feeds into I2, either directly or indirectly
3063 through I1, and I0DEST is in I0SRC. */
3070 /* Record whether I2's body now appears within I3's body. */
3072 }
3074 /* If we already got a failure, don't try to do more. Otherwise, try to
3075 substitute I1 if we have it. */
3078 {
3079 /* Check that an autoincrement side-effect on I1 has not been lost.
3080 This happens if I1DEST is mentioned in I2 and dies there, and
3081 has disappeared from the new pattern. */
3083 && i1_feeds_i2_n
3086 /* Before we can do this substitution, we must redo the test done
3087 above (see detailed comments there) that ensures I1DEST isn't
3088 mentioned in any SETs in NEWPAT that are field assignments. */
3091 {
3094 }
3099 /* If the following substitution will modify I1SRC, make a copy of it
3100 for the case where it is substituted for I1DEST in I2PAT later. */
3104 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3105 copy of I1SRC each time we substitute it, in order to avoid creating
3106 self-referential RTL when we will be substituting I0SRC for I0DEST
3107 later. */
3112 /* Record whether I1's body now appears within I3's body. */
3114 }
3116 /* Likewise for I0 if we have it. */
3119 {
3126 {
3129 }
3131 /* If the following substitution will modify I0SRC, make a copy of it
3132 for the case where it is substituted for I0DEST in I1PAT later. */
3135 /* And a copy for I0DEST in I2PAT substitution. */
3144 }
3146 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3147 to count all the ways that I2SRC and I1SRC can be used. */
3158 /* Fail if we tried to make a new register. */
3160 /* Fail if we couldn't do something and have a CLOBBER. */
3162 /* Fail if this new pattern is a MULT and we didn't have one before
3163 at the outer level. */
3166 {
3169 }
3171 /* If the actions of the earlier insns must be kept
3172 in addition to substituting them into the latest one,
3173 we must make a new PARALLEL for the latest insn
3174 to hold additional the SETs. */
3177 {
3179 combine_extras++;
3182 {
3188 }
3189 else
3190 {
3195 }
3201 {
3207 }
3209 {
3218 }
3219 }
3221 validate_replacement:
3223 /* Note which hard regs this insn has as inputs. */
3226 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3227 consider splitting this pattern, we might need these clobbers. */
3230 {
3236 }
3238 /* Is the result of combination a valid instruction? */
3241 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242 the second SET's destination is a register that is unused and isn't
3243 marked as an instruction that might trap in an EH region. In that case,
3244 we just need the first SET. This can occur when simplifying a divmod
3245 insn. We *must* test for this case here because the code below that
3246 splits two independent SETs doesn't handle this case correctly when it
3247 updates the register status.
3249 It's pointless doing this if we originally had two sets, one from
3250 i3, and one from i2. Combining then splitting the parallel results
3251 in the original i2 again plus an invalid insn (which we delete).
3252 The net effect is only to move instructions around, which makes
3253 debug info less accurate.
3255 Also check the case where the first SET's destination is unused.
3256 That would not cause incorrect code, but does cause an unneeded
3257 insn to remain. */
3266 {
3276 {
3279 }
3288 {
3294 }
3295 }
3297 /* If we were combining three insns and the result is a simple SET
3298 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299 insns. There are two ways to do this. It can be split using a
3300 machine-specific method (like when you have an addition of a large
3301 constant) or by combine in the function find_split_point. */
3305 {
3308 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3309 use I2DEST as a scratch register will help. In the latter case,
3310 convert I2DEST to the mode of the source of NEWPAT if we can. */
3314 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315 inputs of NEWPAT. */
3317 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318 possible to try that as a scratch reg. This would require adding
3319 more code to make it work though. */
3322 {
3325 /* First try to split using the original register as a
3326 scratch register. */
3330 i2dest)));
3333 /* If that didn't work, try changing the mode of I2DEST if
3334 we can. */
3339 {
3341 rtx ni2dest;
3345 else
3346 {
3349 }
3351 parallel = (gen_rtx_PARALLEL
3355 ni2dest))));
3360 {
3368 }
3369 }
3372 }
3374 /* If recog_for_combine has discarded clobbers, try to use them
3375 again for the split. */
3377 {
3380 }
3383 {
3388 }
3392 {
3402 /* If I2 or I3 has multiple SETs, we won't know how to track
3403 register status, so don't use these insns. If I2's destination
3404 is used between I2 and I3, we also can't use these insns. */
3414 /* It is possible that both insns now set the destination of I3.
3415 If so, we must show an extra use of it. */
3418 {
3436 }
3437 }
3439 /* If we can split it and use I2DEST, go ahead and see if that
3440 helps things be recognized. Verify that none of the registers
3441 are set between I2 and I3. */
3444 #ifdef HAVE_cc0
3446 #endif
3447 /* We need I2DEST in the proper mode. If it is a hard register
3448 or the only use of a pseudo, we can change its mode.
3449 Make sure we don't change a hard register to have a mode that
3450 isn't valid for it, or change the number of registers. */
3457 /* We can't overwrite I2DEST if its value is still used by
3458 NEWPAT. */
3460 {
3469 /* *SPLIT may be part of I2SRC, so make sure we have the
3470 original expression around for later debug processing.
3471 We should not need I2SRC any more in other cases. */
3474 else
3477 /* Get NEWDEST as a register in the proper mode. We have already
3478 validated that we can do this. */
3480 {
3483 else
3484 {
3487 }
3488 }
3490 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491 an ASHIFT. This can occur if it was inside a PLUS and hence
3492 appeared to be a memory address. This is a kludge. */
3497 {
3500 /* Update split_code because we may not have a multiply
3501 anymore. */
3503 }
3505 #ifdef INSN_SCHEDULING
3506 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507 be written as a ZERO_EXTEND. */
3509 {
3510 #ifdef LOAD_EXTEND_OP
3511 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512 what it really is. */
3517 else
3518 #endif
3521 }
3522 #endif
3524 /* Attempt to split binary operators using arithmetic identities. */
3528 {
3535 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3537 {
3542 }
3543 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3550 {
3556 /* Split both "((X op Y) op X) op Y" and
3557 "((X op Y) op Y) op X" as "T op T" where T is
3558 "X op Y". */
3561 {
3567 }
3568 /* Split "((X op X) op Y) op Y)" as "T op T" where
3569 T is "X op Y". */
3571 {
3577 }
3578 }
3579 }
3582 {
3585 }
3589 /* recog_for_combine might have added CLOBBERs to newi2pat.
3590 Make sure NEWPAT does not depend on the clobbered regs. */
3594 {
3597 {
3600 }
3601 }
3603 /* If the split point was a MULT and we didn't have one before,
3604 don't use one now. */
3607 }
3608 }
3610 /* Check for a case where we loaded from memory in a narrow mode and
3611 then sign extended it, but we need both registers. In that case,
3612 we have a PARALLEL with both loads from the same memory location.
3613 We can split this into a load from memory followed by a register-register
3614 copy. This saves at least one insn, more if register allocation can
3615 eliminate the copy.
3617 We cannot do this if the destination of the first assignment is a
3618 condition code register or cc0. We eliminate this case by making sure
3619 the SET_DEST and SET_SRC have the same mode.
3621 We cannot do this if the destination of the second assignment is
3622 a register that we have already assumed is zero-extended. Similarly
3623 for a SUBREG of such a register. */
3658 {
3659 rtx ni2dest;
3673 }
3675 /* Similarly, check for a case where we have a PARALLEL of two independent
3676 SETs but we started with three insns. In this case, we can do the sets
3677 as two separate insns. This case occurs when some SET allows two
3678 other insns to combine, but the destination of that SET is still live. */
3695 {
3696 /* Normally, it doesn't matter which of the two is done first,
3697 but the one that references cc0 can't be the second, and
3698 one which uses any regs/memory set in between i2 and i3 can't
3699 be first. */
3702 #ifdef HAVE_cc0
3704 #endif
3705 )
3706 {
3709 }
3712 #ifdef HAVE_cc0
3714 #endif
3715 )
3716 {
3719 }
3720 else
3721 {
3724 }
3729 {
3730 /* recog_for_combine might have added CLOBBERs to newi2pat.
3731 Make sure NEWPAT does not depend on the clobbered regs. */
3733 {
3736 {
3739 {
3742 }
3743 }
3744 }
3747 }
3748 }
3750 /* If it still isn't recognized, fail and change things back the way they
3751 were. */
3753 /* Is the result a reasonable ASM_OPERANDS? */
3755 {
3758 }
3760 /* If we had to change another insn, make sure it is valid also. */
3762 {
3770 {
3773 }
3774 }
3776 #ifdef HAVE_cc0
3777 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3778 they are adjacent to each other or not. */
3779 {
3783 {
3786 }
3787 }
3788 #endif
3790 /* Only allow this combination if insn_rtx_costs reports that the
3791 replacement instructions are cheaper than the originals. */
3793 {
3796 }
3799 {
3804 {
3809 /* Temporarily revert mode back. */
3813 {
3814 /* If we used i2dest as a scratch register with a
3815 different mode, substitute it for the original
3816 i2src while its original mode is temporarily
3817 restored, and then clear i2scratch so that we don't
3818 do it again later. */
3820 this_basic_block);
3822 /* Put back the new mode. */
3824 }
3825 else
3826 {
3831 {
3834 }
3835 else
3836 {
3843 }
3845 /* We're dealing with a reg that changed mode but not
3846 meaning, so we want to turn it into a subreg for
3847 the new mode. However, because of REG sharing and
3848 because its mode had already changed, we have to do
3849 it in two steps. First, replace any debug uses of
3850 reg, with its original mode temporarily restored,
3851 with this copy we have created; then, replace the
3852 copy with the SUBREG of the original shared reg,
3853 once again changed to the new mode. */
3855 this_basic_block);
3859 this_basic_block);
3860 }
3861 }
3862 }
3864 /* If we will be able to accept this, we have made a
3865 change to the destination of I3. This requires us to
3866 do a few adjustments. */
3869 {
3872 }
3874 /* We now know that we can do this combination. Merge the insns and
3875 update the status of registers and LOG_LINKS. */
3878 {
3883 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3884 are still valid. Then add any non-duplicate notes added by
3885 recog_for_combine. */
3887 {
3893 }
3897 NULL_RTX);
3898 }
3901 {
3902 rtx insn;
3904 rtx ni2dest;
3906 /* I3 now uses what used to be its destination and which is now
3907 I2's destination. This requires us to do a few adjustments. */
3911 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3912 so we still will.
3914 However, some later insn might be using I2's dest and have
3915 a LOG_LINK pointing at I3. We must remove this link.
3916 The simplest way to remove the link is to point it at I1,
3917 which we know will be a NOTE. */
3919 /* newi2pat is usually a SET here; however, recog_for_combine might
3920 have added some clobbers. */
3923 else
3930 {
3932 {
3938 }
3939 }
3940 }
3942 {
3947 /* Compute which registers we expect to eliminate. newi2pat may be setting
3948 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3949 same as i3dest, in which case newi2pat may be setting i1dest. */
3952 || !i2dest_killed
3956 || !i1dest_killed
3960 || !i0dest_killed
3963 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3964 clear them. */
3972 /* Ensure that we do not have something that should not be shared but
3973 occurs multiple times in the new insns. Check this by first
3974 resetting all the `used' flags and then copying anything is shared. */
3998 {
4005 {
4006 /* I2SRC must still be meaningful at this point. Some splitting
4007 operations can invalidate I2SRC, but those operations do not
4008 apply to calls. */
4011 }
4019 }
4024 /* We had one special case above where I2 had more than one set and
4025 we replaced a destination of one of those sets with the destination
4026 of I3. In that case, we have to update LOG_LINKS of insns later
4027 in this basic block. Note that this (expensive) case is rare.
4029 Also, in this case, we must pretend that all REG_NOTEs for I2
4030 actually came from I3, so that REG_UNUSED notes from I2 will be
4031 properly handled. */
4034 {
4052 {
4057 }
4058 else
4061 }
4069 {
4072 this_basic_block);
4075 }
4076 else
4077 {
4080 this_basic_block);
4082 }
4085 {
4090 this_basic_block);
4092 }
4095 {
4100 this_basic_block);
4102 }
4104 /* Get death notes for everything that is now used in either I3 or
4105 I2 and used to die in a previous insn. If we built two new
4106 patterns, move from I1 to I2 then I2 to I3 so that we get the
4107 proper movement on registers that I2 modifies. */
4113 else
4119 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4136 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4137 know these are REG_UNUSED and want them to go to the desired insn,
4138 so we always pass it as i3. */
4142 NULL_RTX);
4146 NULL_RTX);
4148 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4149 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4150 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4151 in that case, it might delete I2. Similarly for I2 and I1.
4152 Show an additional death due to the REG_DEAD note we make here. If
4153 we discard it in distribute_notes, we will decrement it again. */
4156 {
4161 else
4164 }
4167 {
4172 else
4175 }
4178 {
4183 else
4186 }
4189 {
4194 else
4197 }
4205 {
4209 /* The insn that used to set this register doesn't exist, and
4210 this life of the register may not exist either. See if one of
4211 I3's links points to an insn that sets I2DEST. If it does,
4212 that is now the last known value for I2DEST. If we don't update
4213 this and I2 set the register to a value that depended on its old
4214 contents, we will get confused. If this insn is used, thing
4215 will be set correctly in combine_instructions. */
4223 /* If the reg formerly set in I2 died only once and that was in I3,
4224 zero its use count so it won't make `reload' do any work. */
4229 }
4232 {
4245 }
4248 {
4261 }
4263 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4264 been made to this insn. The order of
4265 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4266 can affect nonzero_bits of newpat */
4270 }
4273 {
4275 {
4278 }
4280 }
4283 {
4285 {
4288 }
4290 }
4293 {
4295 {
4298 }
4300 }
4303 {
4305 {
4308 }
4310 }
4313 {
4315 {
4318 }
4320 }
4322 /* Set new_direct_jump_p if a new return or simple jump instruction
4323 has been created. Adjust the CFG accordingly. */
4326 {
4330 }
4335 {
4338 }
4340 /* A noop might also need cleaning up of CFG, if it comes from the
4341 simplification of a jump. */
4346 {
4349 }
4356 {
4359 }
4361 combine_successes++;
4368 else
4370 }
4371 \f
4372 /* Undo all the modifications recorded in undobuf. */
4374 static void
4376 {
4380 {
4383 {
4398 }
4402 }
4405 }
4407 /* We've committed to accepting the changes we made. Move all
4408 of the undos to the free list. */
4410 static void
4412 {
4416 {
4420 }
4422 }
4423 \f
4424 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4425 where we have an arithmetic expression and return that point. LOC will
4426 be inside INSN.
4428 try_combine will call this function to see if an insn can be split into
4429 two insns. */
4433 {
4442 /* First special-case some codes. */
4444 {
4446 #ifdef INSN_SCHEDULING
4447 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4448 point. */
4451 #endif
4455 #ifdef HAVE_lo_sum
4456 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4457 using LO_SUM and HIGH. */
4460 {
4468 }
4469 #endif
4471 /* If we have a PLUS whose second operand is a constant and the
4472 address is not valid, perhaps will can split it up using
4473 the machine-specific way to split large constants. We use
4474 the first pseudo-reg (one of the virtual regs) as a placeholder;
4475 it will not remain in the result. */
4480 {
4484 subst_insn);
4486 /* This should have produced two insns, each of which sets our
4487 placeholder. If the source of the second is a valid address,
4488 we can make put both sources together and make a split point
4489 in the middle. */
4502 && memory_address_addr_space_p
4505 {
4509 /* Replace the placeholder in SRC2 with SRC1. If we can
4510 find where in SRC2 it was placed, that can become our
4511 split point and we can replace this address with SRC2.
4512 Just try two obvious places. */
4523 {
4526 }
4527 }
4529 /* If that didn't work, perhaps the first operand is complex and
4530 needs to be computed separately, so make a split point there.
4531 This will occur on machines that just support REG + CONST
4532 and have a constant moved through some previous computation. */
4538 }
4540 /* If we have a PLUS whose first operand is complex, try computing it
4541 separately by making a split there. */
4552 #ifdef HAVE_cc0
4553 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4554 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4555 we need to put the operand into a register. So split at that
4556 point. */
4565 #endif
4567 /* See if we can split SET_SRC as it stands. */
4572 /* See if we can split SET_DEST as it stands. */
4577 /* See if this is a bitfield assignment with everything constant. If
4578 so, this is an IOR of an AND, so split it into that. */
4588 {
4594 unsigned HOST_WIDE_INT mask
4596 rtx or_mask;
4605 else
4606 {
4612 or_mask));
4613 }
4620 }
4622 /* Otherwise, see if this is an operation that we can split into two.
4623 If so, try to split that. */
4627 {
4629 /* If we are AND'ing with a large constant that is only a single
4630 bit and the result is only being used in a context where we
4631 need to know if it is zero or nonzero, replace it with a bit
4632 extraction. This will avoid the large constant, which might
4633 have taken more than one insn to make. If the constant were
4634 not a valid argument to the AND but took only one insn to make,
4635 this is no worse, but if it took more than one insn, it will
4636 be better. */
4646 {
4651 {
4654 }
4655 }
4659 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4660 is known to be on, this can be converted into a NEG of a shift. */
4666 {
4678 }
4684 /* We can't optimize if either mode is a partial integer
4685 mode as we don't know how many bits are significant
4686 in those modes. */
4700 {
4708 }
4713 }
4717 {
4720 /* For unsigned, we have a choice of a shift followed by an
4721 AND or two shifts. Use two shifts for field sizes where the
4722 constant might be too large. We assume here that we can
4723 always at least get 8-bit constants in an AND insn, which is
4724 true for every current RISC. */
4727 {
4728 unsigned HOST_WIDE_INT mask
4732 gen_rtx_LSHIFTRT
4740 }
4741 else
4742 {
4744 gen_rtx_fmt_ee
4755 }
4756 }
4758 /* See if this is a simple operation with a constant as the second
4759 operand. It might be that this constant is out of range and hence
4760 could be used as a split point. */
4768 /* Finally, see if this is a simple operation with its first operand
4769 not in a register. The operation might require this operand in a
4770 register, so return it as a split point. We can always do this
4771 because if the first operand were another operation, we would have
4772 already found it as a split point. */
4781 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4782 it is better to write this as (not (ior A B)) so we can split it.
4783 Similarly for IOR. */
4785 {
4793 }
4795 /* Many RISC machines have a large set of logical insns. If the
4796 second operand is a NOT, put it first so we will try to split the
4797 other operand first. */
4799 {
4803 }
4808 /* Canonicalization can produce (minus A (mult B C)), where C is a
4809 constant. It may be better to try splitting (plus (mult B -C) A)
4810 instead if this isn't a multiply by a power of two. */
4814 {
4822 mode)),
4825 }
4827 /* Split at a multiply-accumulate instruction. However if this is
4828 the SET_SRC, we likely do not have such an instruction and it's
4829 worthless to try this split. */
4835 }
4837 /* Otherwise, select our actions depending on our rtx class. */
4839 {
4845 /* ... fall through ... */
4853 /* ... fall through ... */
4855 /* Some machines have (and (shift ...) ...) insns. If X is not
4856 an AND, but XEXP (X, 0) is, use it as our split point. */
4866 /* Otherwise, we don't have a split point. */
4868 }
4869 }
4870 \f
4871 /* Throughout X, replace FROM with TO, and return the result.
4872 The result is TO if X is FROM;
4873 otherwise the result is X, but its contents may have been modified.
4874 If they were modified, a record was made in undobuf so that
4875 undo_all will (among other things) return X to its original state.
4877 If the number of changes necessary is too much to record to undo,
4878 the excess changes are not made, so the result is invalid.
4879 The changes already made can still be undone.
4880 undobuf.num_undo is incremented for such changes, so by testing that
4881 the caller can tell whether the result is valid.
4883 `n_occurrences' is incremented each time FROM is replaced.
4885 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4887 IN_COND is nonzero if we are at the top level of a condition.
4889 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4890 by copying if `n_occurrences' is nonzero. */
4892 static rtx
4894 {
4899 rtx new_rtx;
4901 /* Two expressions are equal if they are identical copies of a shared
4902 RTX or if they are both registers with the same register number
4903 and mode. */
4905 #define COMBINE_RTX_EQUAL_P(X,Y) \
4906 ((X) == (Y) \
4907 || (REG_P (X) && REG_P (Y) \
4908 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4911 {
4912 n_occurrences++;
4914 }
4916 /* If X and FROM are the same register but different modes, they
4917 will not have been seen as equal above. However, the log links code
4918 will make a LOG_LINKS entry for that case. If we do nothing, we
4919 will try to rerecognize our original insn and, when it succeeds,
4920 we will delete the feeding insn, which is incorrect.
4922 So force this insn not to match in this (rare) case. */
4927 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4928 of which may contain things that can be combined. */
4932 /* It is possible to have a subexpression appear twice in the insn.
4933 Suppose that FROM is a register that appears within TO.
4934 Then, after that subexpression has been scanned once by `subst',
4935 the second time it is scanned, TO may be found. If we were
4936 to scan TO here, we would find FROM within it and create a
4937 self-referent rtl structure which is completely wrong. */
4941 /* Parallel asm_operands need special attention because all of the
4942 inputs are shared across the arms. Furthermore, unsharing the
4943 rtl results in recognition failures. Failure to handle this case
4944 specially can result in circular rtl.
4946 Solve this by doing a normal pass across the first entry of the
4947 parallel, and only processing the SET_DESTs of the subsequent
4948 entries. Ug. */
4953 {
4956 /* If this substitution failed, this whole thing fails. */
4964 {
4970 {
4973 /* If this substitution failed, this whole thing fails. */
4979 }
4980 }
4981 }
4982 else
4983 {
4987 /* We don't need to process a SET_DEST that is a register, CC0,
4988 or PC, so set up to skip this common case. All other cases
4989 where we want to suppress replacing something inside a
4990 SET_SRC are handled via the IN_DEST operand. */
4997 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4998 constant. */
5003 {
5005 {
5008 {
5010 {
5013 n_occurrences++;
5014 }
5015 else
5016 {
5018 unique_copy);
5020 /* If this substitution failed, this whole thing
5021 fails. */
5025 }
5028 }
5029 }
5031 {
5032 /* If this is a register being set, ignore it. */
5039 ;
5042 {
5043 /* In general, don't install a subreg involving two
5044 modes not tieable. It can worsen register
5045 allocation, and can even make invalid reload
5046 insns, since the reg inside may need to be copied
5047 from in the outside mode, and that may be invalid
5048 if it is an fp reg copied in integer mode.
5050 We allow two exceptions to this: It is valid if
5051 it is inside another SUBREG and the mode of that
5052 SUBREG and the mode of the inside of TO is
5053 tieable and it is valid if X is a SET that copies
5054 FROM to CC0. */
5062 #ifdef HAVE_cc0
5064 #endif
5065 )
5068 #ifdef CANNOT_CHANGE_MODE_CLASS
5076 #endif
5079 n_occurrences++;
5080 }
5081 else
5082 /* If we are in a SET_DEST, suppress most cases unless we
5083 have gone inside a MEM, in which case we want to
5084 simplify the address. We assume here that things that
5085 are actually part of the destination have their inner
5086 parts in the first expression. This is true for SUBREG,
5087 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5088 things aside from REG and MEM that should appear in a
5089 SET_DEST. */
5091 (((in_dest
5097 unique_copy);
5099 /* If we found that we will have to reject this combination,
5100 indicate that by returning the CLOBBER ourselves, rather than
5101 an expression containing it. This will speed things up as
5102 well as prevent accidents where two CLOBBERs are considered
5103 to be equal, thus producing an incorrect simplification. */
5109 {
5117 }
5120 {
5124 }
5125 else
5127 }
5128 }
5129 }
5131 /* Check if we are loading something from the constant pool via float
5132 extension; in this case we would undo compress_float_constant
5133 optimization and degenerate constant load to an immediate value. */
5137 {
5141 }
5143 /* Try to simplify X. If the simplification changed the code, it is likely
5144 that further simplification will help, so loop, but limit the number
5145 of repetitions that will be performed. */
5148 {
5149 /* If X is sufficiently simple, don't bother trying to do anything
5150 with it. */
5159 /* We no longer know the original mode of operand 0 since we
5160 have changed the form of X) */
5162 }
5165 }
5166 \f
5167 /* Simplify X, a piece of RTL. We just operate on the expression at the
5168 outer level; call `subst' to simplify recursively. Return the new
5169 expression.
5171 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5172 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5173 of a condition. */
5175 static rtx
5178 {
5181 rtx temp;
5184 /* If this is a commutative operation, put a constant last and a complex
5185 expression first. We don't need to do this for comparisons here. */
5188 {
5192 }
5194 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5195 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5196 things. Check for cases where both arms are testing the same
5197 condition.
5199 Don't do anything if all operands are very simple. */
5212 {
5217 /* If everything is a comparison, what we have is highly unlikely
5218 to be simpler, so don't use it. */
5221 {
5228 /* Simplify the alternative arms; this may collapse the true and
5229 false arms to store-flag values. Be careful to use copy_rtx
5230 here since true_rtx or false_rtx might share RTL with x as a
5231 result of the if_then_else_cond call above. */
5235 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5236 is unlikely to be simpler. */
5239 {
5242 /* Restarting if we generate a store-flag expression will cause
5243 us to loop. Just drop through in this case. */
5245 /* If the result values are STORE_FLAG_VALUE and zero, we can
5246 just make the comparison operation. */
5257 /* Likewise, we can make the negate of a comparison operation
5258 if the result values are - STORE_FLAG_VALUE and zero. */
5266 mode);
5277 mode);
5278 else
5281 mode,
5282 VOIDmode,
5283 cond,
5284 cop1),
5289 }
5290 }
5291 }
5293 /* Try to fold this expression in case we have constants that weren't
5294 present before. */
5297 {
5305 {
5308 {
5312 }
5315 }
5328 }
5331 {
5336 }
5338 /* First see if we can apply the inverse distributive law. */
5341 {
5345 }
5347 /* If CODE is an associative operation not otherwise handled, see if we
5348 can associate some operands. This can win if they are constants or
5349 if they are logically related (i.e. (a & b) & a). */
5355 {
5357 {
5361 rtx inner;
5363 /* Make sure we pass the constant operand if any as the second
5364 one if this is a commutative operation. */
5366 {
5370 }
5376 /* For commutative operations, try the other pair if that one
5377 didn't simplify. */
5379 {
5384 }
5388 }
5389 }
5391 /* A little bit of algebraic simplification here. */
5393 {
5395 /* Ensure that our address has any ASHIFTs converted to MULT in case
5396 address-recognizing predicates are called later. */
5405 /* See if this can be moved to simplify_subreg. */
5408 /* Don't call gen_lowpart if the inner mode
5409 is VOIDmode and we cannot simplify it, as SUBREG without
5410 inner mode is invalid. */
5417 {
5418 rtx temp;
5424 /* If op is known to have all lower bits zero, the result is zero. */
5434 }
5436 /* Don't change the mode of the MEM if that would change the meaning
5437 of the address. */
5444 /* Note that we cannot do any narrowing for non-constants since
5445 we might have been counting on using the fact that some bits were
5446 zero. We now do this in the SET. */
5453 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5454 replaced by (lshiftrt X C). This will convert
5455 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5463 /* If X has only a single bit that might be nonzero, say, bit I, convert
5464 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5465 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5466 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5467 or a SUBREG of one since we'd be making the expression more
5468 complex if it was just a register. */
5474 {
5475 rtx temp1 = simplify_shift_const
5481 /* If all we did was surround TEMP with the two shifts, we
5482 haven't improved anything, so don't use it. Otherwise,
5483 we are better off with TEMP1. */
5488 }
5492 /* We can't handle truncation to a partial integer mode here
5493 because we don't know the real bitsize of the partial
5494 integer mode. */
5503 /* We can truncate a constant value and return it. */
5507 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5508 whose value is a comparison can be replaced with a subreg if
5509 STORE_FLAG_VALUE permits. */
5518 /* (const (const X)) can become (const X). Do it this way rather than
5519 returning the inner CONST since CONST can be shared with a
5520 REG_EQUAL note. */
5525 #ifdef HAVE_lo_sum
5527 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5528 can add in an offset. find_split_point will split this address up
5529 again if it doesn't match. */
5534 #endif
5537 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5538 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5539 bit-field and can be replaced by either a sign_extend or a
5540 sign_extract. The `and' may be a zero_extend and the two
5541 <c>, -<c> constants may be reversed. */
5556 return simplify_shift_const
5563 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5564 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5565 the bitsize of the mode - 1. This allows simplification of
5566 "a = (b & 8) == 0;" */
5578 /* If we are adding two things that have no bits in common, convert
5579 the addition into an IOR. This will often be further simplified,
5580 for example in cases like ((a & 1) + (a & 2)), which can
5581 become a & 3. */
5586 {
5587 /* Try to simplify the expression further. */
5591 /* If we could, great. If not, do not go ahead with the IOR
5592 replacement, since PLUS appears in many special purpose
5593 address arithmetic instructions. */
5601 }
5605 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5606 (and <foo> (const_int pow2-1)) */
5616 /* If we have (mult (plus A B) C), apply the distributive law and then
5617 the inverse distributive law to see if things simplify. This
5618 occurs mostly in addresses, often when unrolling loops. */
5621 {
5625 }
5627 /* Try simplify a*(b/c) as (a*b)/c. */
5630 {
5636 }
5640 /* If this is a divide by a power of two, treat it as a shift if
5641 its first operand is a shift. */
5659 /* If the first operand is a condition code, we can't do anything
5660 with it. */
5664 {
5672 /* Simplify our comparison, if possible. */
5675 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5676 if only the low-order bit is possibly nonzero in X (such as when
5677 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5678 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5679 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5680 (plus X 1).
5682 Remove any ZERO_EXTRACT we made when thinking this was a
5683 comparison. It may now be simpler to use, e.g., an AND. If a
5684 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5685 the call to make_compound_operation in the SET case.
5687 Don't apply these optimizations if the caller would
5688 prefer a comparison rather than a value.
5689 E.g., for the condition in an IF_THEN_ELSE most targets need
5690 an explicit comparison. */
5693 ;
5709 {
5713 mode);
5714 }
5721 {
5725 const1_rtx);
5726 }
5734 {
5737 }
5739 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5740 those above. */
5742 ;
5757 {
5761 mode);
5762 }
5770 {
5774 mode);
5775 }
5777 /* If X is 0/1, (eq X 0) is X-1. */
5783 {
5786 }
5788 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5789 one bit that might be nonzero, we can convert (ne x 0) to
5790 (ashift x c) where C puts the bit in the sign bit. Remove any
5791 AND with STORE_FLAG_VALUE when we are done, since we are only
5792 going to test the sign bit. */
5799 {
5805 else
5807 }
5809 /* If the code changed, return a whole new comparison.
5810 We also need to avoid using SUBST in cases where
5811 simplify_comparison has widened a comparison with a CONST_INT,
5812 since in that case the wider CONST_INT may fail the sanity
5813 checks in do_SUBST. */
5820 /* Otherwise, keep this operation, but maybe change its operands.
5821 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5824 }
5834 /* If we are processing SET_DEST, we are done. */
5852 /* If this is a shift by a constant amount, simplify it. */
5868 }
5871 }
5872 \f
5873 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5875 static rtx
5877 {
5884 rtx temp;
5887 rtx reversed;
5889 /* Simplify storing of the truth value. */
5894 /* Also when the truth value has to be reversed. */
5900 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5901 in it is being compared against certain values. Get the true and false
5902 comparisons and see if that says anything about the value of each arm. */
5908 {
5909 HOST_WIDE_INT nzb;
5915 /* If FALSE_CODE is EQ, swap the codes and arms. */
5918 {
5921 }
5923 /* If we are comparing against zero and the expression being tested has
5924 only a single bit that might be nonzero, that is its value when it is
5925 not equal to zero. Similarly if it is known to be -1 or 0. */
5929 {
5932 }
5936 {
5939 }
5941 /* Now simplify an arm if we know the value of the register in the
5942 branch and it is used in the arm. Be careful due to the potential
5943 of locally-shared RTL. */
5960 }
5962 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5963 reversed, do so to avoid needing two sets of patterns for
5964 subtract-and-branch insns. Similarly if we have a constant in the true
5965 arm, the false arm is the same as the first operand of the comparison, or
5966 the false arm is more complicated than the true arm. */
5979 {
5988 /* It is possible that the conditional has been simplified out. */
5991 }
5993 /* If the two arms are identical, we don't need the comparison. */
5998 /* Convert a == b ? b : a to "a". */
6010 /* Look for cases where we have (abs x) or (neg (abs X)). */
6013 && comparison_p
6020 {
6026 return
6029 mode);
6032 }
6034 /* Look for MIN or MAX. */
6037 && comparison_p
6042 {
6057 }
6059 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6060 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6061 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6062 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6063 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6064 neither 1 or -1, but it isn't worth checking for. */
6067 && comparison_p
6070 {
6086 /* If an identity-zero op is commutative, check whether there
6087 would be a match if we swapped the operands. */
6107 {
6111 }
6123 {
6127 }
6143 {
6147 }
6159 {
6163 }
6166 {
6172 const_true_rtx));
6180 }
6181 }
6183 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6184 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6185 negation of a single bit, we can convert this operation to a shift. We
6186 can actually do this more generally, but it doesn't seem worth it. */
6195 return
6199 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6209 }
6210 \f
6211 /* Simplify X, a SET expression. Return the new expression. */
6213 static rtx
6215 {
6218 enum machine_mode mode
6220 rtx other_insn;
6223 /* (set (pc) (return)) gets written as (return). */
6227 /* Now that we know for sure which bits of SRC we are using, see if we can
6228 simplify the expression for the object knowing that we only need the
6229 low-order bits. */
6232 {
6235 }
6237 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6238 the comparison result and try to simplify it unless we already have used
6239 undobuf.other_insn. */
6247 {
6256 {
6259 {
6262 }
6263 }
6264 else
6272 {
6276 }
6277 else
6278 {
6283 /* Attempt to simplify CC user. */
6285 {
6289 }
6291 /* Convert X into a no-op move. */
6295 }
6297 /* Simplify our comparison, if possible. */
6300 #ifdef SELECT_CC_MODE
6301 /* If this machine has CC modes other than CCmode, check to see if we
6302 need to use a different CC mode here. */
6311 else
6314 #ifndef HAVE_cc0
6315 /* If the mode changed, we have to change SET_DEST, the mode in the
6316 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6317 a hard register, just build new versions with the proper mode. If it
6318 is a pseudo, we lose unless it is only time we set the pseudo, in
6319 which case we can safely change its mode. */
6321 {
6323 {
6325 rtx new_dest;
6329 else
6330 {
6333 }
6340 }
6341 }
6345 /* If the code changed, we have to build a new comparison in
6346 undobuf.other_insn. */
6348 {
6357 /* If the only change we made was to change an EQ into an NE or
6358 vice versa, OP0 has only one bit that might be nonzero, and OP1
6359 is zero, check if changing the user of the condition code will
6360 produce a valid insn. If it won't, we can keep the original code
6361 in that insn by surrounding our operation with an XOR. */
6368 {
6373 {
6380 }
6381 }
6382 }
6387 /* Otherwise, if we didn't previously have a COMPARE in the
6388 correct mode, we need one. */
6390 {
6393 }
6395 {
6398 }
6399 /* Otherwise, update the COMPARE if needed. */
6401 {
6404 }
6405 }
6406 else
6407 {
6408 /* Get SET_SRC in a form where we have placed back any
6409 compound expressions. Then do the checks below. */
6412 }
6414 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6415 and X being a REG or (subreg (reg)), we may be able to convert this to
6416 (set (subreg:m2 x) (op)).
6418 We can always do this if M1 is narrower than M2 because that means that
6419 we only care about the low bits of the result.
6421 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6422 perform a narrower operation than requested since the high-order bits will
6423 be undefined. On machine where it is defined, this transformation is safe
6424 as long as M1 and M2 have the same number of words. */
6432 #ifndef WORD_REGISTER_OPERATIONS
6435 #endif
6436 #ifdef CANNOT_CHANGE_MODE_CLASS
6441 #endif
6445 {
6448 dest));
6452 }
6454 #ifdef HAVE_cc0
6455 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6456 in SRC. */
6462 {
6466 /* Here we make sure that we don't have a sign bit on. */
6469 {
6472 }
6473 }
6474 #endif
6476 #ifdef LOAD_EXTEND_OP
6477 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6478 would require a paradoxical subreg. Replace the subreg with a
6479 zero_extend to avoid the reload that would otherwise be required. */
6487 {
6493 }
6494 #endif
6496 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6497 are comparing an item known to be 0 or -1 against 0, use a logical
6498 operation instead. Check for one of the arms being an IOR of the other
6499 arm with some value. We compute three terms to be IOR'ed together. In
6500 practice, at most two will be nonzero. Then we do the IOR's. */
6508 #ifdef HAVE_conditional_move
6510 #endif
6515 {
6541 false_rtx);
6547 term3));
6550 }
6552 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6553 whole thing fail. */
6558 else
6559 /* Convert this into a field assignment operation, if possible. */
6561 }
6562 \f
6563 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6564 result. */
6566 static rtx
6568 {
6574 {
6576 /* We can call simplify_and_const_int only if we don't lose
6577 any (sign) bits when converting INTVAL (op1) to
6578 "unsigned HOST_WIDE_INT". */
6582 {
6589 }
6591 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6592 apply the distributive law and then the inverse distributive
6593 law to see if things simplify. */
6595 {
6599 }
6601 {
6605 }
6609 /* If we have (ior (and A B) C), apply the distributive law and then
6610 the inverse distributive law to see if things simplify. */
6613 {
6617 }
6620 {
6624 }
6629 }
6632 }
6633 \f
6634 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6635 operations" because they can be replaced with two more basic operations.
6636 ZERO_EXTEND is also considered "compound" because it can be replaced with
6637 an AND operation, which is simpler, though only one operation.
6639 The function expand_compound_operation is called with an rtx expression
6640 and will convert it to the appropriate shifts and AND operations,
6641 simplifying at each stage.
6643 The function make_compound_operation is called to convert an expression
6644 consisting of shifts and ANDs into the equivalent compound expression.
6645 It is the inverse of this function, loosely speaking. */
6647 static rtx
6649 {
6653 rtx tem;
6656 {
6660 /* We can't necessarily use a const_int for a multiword mode;
6661 it depends on implicitly extending the value.
6662 Since we don't know the right way to extend it,
6663 we can't tell whether the implicit way is right.
6665 Even for a mode that is no wider than a const_int,
6666 we can't win, because we need to sign extend one of its bits through
6667 the rest of it, and we don't know which bit. */
6671 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6672 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6673 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6674 reloaded. If not for that, MEM's would very rarely be safe.
6676 Reject MODEs bigger than a word, because we might not be able
6677 to reference a two-register group starting with an arbitrary register
6678 (and currently gen_lowpart might crash for a SUBREG). */
6683 /* Reject MODEs that aren't scalar integers because turning vector
6684 or complex modes into shifts causes problems. */
6690 /* If the inner object has VOIDmode (the only way this can happen
6691 is if it is an ASM_OPERANDS), we can't do anything since we don't
6692 know how much masking to do. */
6701 /* ... fall through ... */
6704 /* If the operand is a CLOBBER, just return it. */
6713 /* Reject MODEs that aren't scalar integers because turning vector
6714 or complex modes into shifts causes problems. */
6722 /* This should stay within the object being extracted, fail otherwise. */
6733 }
6734 /* Convert sign extension to zero extension, if we know that the high
6735 bit is not set, as this is easier to optimize. It will be converted
6736 back to cheaper alternative in make_extraction. */
6744 {
6748 /* Make sure this is a profitable operation. */
6755 else
6757 }
6759 /* We can optimize some special cases of ZERO_EXTEND. */
6761 {
6762 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6763 know that the last value didn't have any inappropriate bits
6764 set. */
6772 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6781 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6782 is a comparison and STORE_FLAG_VALUE permits. This is like
6783 the first case, but it works even when GET_MODE (x) is larger
6784 than HOST_WIDE_INT. */
6793 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6803 }
6805 /* If we reach here, we want to return a pair of shifts. The inner
6806 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6807 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6808 logical depending on the value of UNSIGNEDP.
6810 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6811 converted into an AND of a shift.
6813 We must check for the case where the left shift would have a negative
6814 count. This can happen in a case like (x >> 31) & 255 on machines
6815 that can't shift by a constant. On those machines, we would first
6816 combine the shift with the AND to produce a variable-position
6817 extraction. Then the constant of 31 would be substituted in
6818 to produce such a position. */
6822 {
6831 }
6838 else
6839 /* Any other cases we can't handle. */
6842 /* If we couldn't do this for some reason, return the original
6843 expression. */
6848 }
6849 \f
6850 /* X is a SET which contains an assignment of one object into
6851 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6852 or certain SUBREGS). If possible, convert it into a series of
6853 logical operations.
6855 We half-heartedly support variable positions, but do not at all
6856 support variable lengths. */
6858 static const_rtx
6860 {
6861 rtx inner;
6867 /* Loop until we find something we can't simplify. */
6869 {
6872 {
6876 }
6879 {
6884 /* A constant position should stay within the width of INNER. */
6890 {
6898 /* If position is ADJUST - X, new position is X. */
6900 else
6901 {
6906 pos);
6907 }
6908 }
6909 }
6911 /* A SUBREG between two modes that occupy the same numbers of words
6912 can be done by moving the SUBREG to the source. */
6914 /* We need SUBREGs to compute nonzero_bits properly. */
6915 && nonzero_sign_valid
6920 {
6922 gen_lowpart
6926 }
6927 else
6935 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6937 {
6940 /* Don't do anything for vector or complex integral types. */
6944 /* Try to find an integral mode to pun with. */
6951 }
6953 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6957 /* Now compute the equivalent expression. Make a copy of INNER
6958 for the SET_DEST in case it is a MEM into which we will substitute;
6959 we don't want shared RTL in that case. */
6961 compute_mode);
6965 compute_mode,
6967 compute_mode),
6968 inner);
6973 mask),
6974 pos);
6979 }
6982 }
6983 \f
6984 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6985 it is an RTX that represents the (variable) starting position; otherwise,
6986 POS is the (constant) starting bit position. Both are counted from the LSB.
6988 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6990 IN_DEST is nonzero if this is a reference in the destination of a SET.
6991 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6992 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6993 be used.
6995 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6996 ZERO_EXTRACT should be built even for bits starting at bit 0.
6998 MODE is the desired mode of the result (if IN_DEST == 0).
7000 The result is an RTX for the extraction or NULL_RTX if the target
7001 can't handle it. */
7003 static rtx
7007 {
7008 /* This mode describes the size of the storage area
7009 to fetch the overall value from. Within that, we
7010 ignore the POS lowest bits, etc. */
7020 HOST_WIDE_INT orig_pos;
7026 {
7027 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7028 consider just the QI as the memory to extract from.
7029 The subreg adds or removes high bits; its mode is
7030 irrelevant to the meaning of this extraction,
7031 since POS and LEN count from the lsb. */
7035 }
7040 {
7041 /* We're extracting the least significant bits of an rtx
7042 (ashift X (const_int C)), where LEN > C. Extract the
7043 least significant (LEN - C) bits of X, giving an rtx
7044 whose mode is MODE, then shift it left C times. */
7050 }
7056 /* See if this can be done without an extraction. We never can if the
7057 width of the field is not the same as that of some integer mode. For
7058 registers, we can only avoid the extraction if the position is at the
7059 low-order bit and this is either not in the destination or we have the
7060 appropriate STRICT_LOW_PART operation available.
7062 For MEM, we can avoid an extract if the field starts on an appropriate
7063 boundary and we can change the mode of the memory reference. */
7072 && (! in_dest
7076 && (pos
7079 /* We can't do this if we are widening INNER_MODE (it
7080 may not be aligned, for one thing). */
7086 {
7087 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7088 field. If the original and current mode are the same, we need not
7089 adjust the offset. Otherwise, we do if bytes big endian.
7091 If INNER is not a MEM, get a piece consisting of just the field
7092 of interest (in this case POS % BITS_PER_WORD must be 0). */
7095 {
7096 HOST_WIDE_INT offset;
7098 /* POS counts from lsb, but make OFFSET count in memory order. */
7101 else
7105 }
7107 {
7109 {
7110 /* We can't call gen_lowpart in a DEST since we
7111 always want a SUBREG (see below) and it would sometimes
7112 return a new hard register. */
7114 {
7129 /* Avoid creating invalid subregs, for example when
7130 simplifying (x>>32)&255. */
7135 }
7136 else
7138 }
7139 else
7141 }
7142 else
7144 len >= HOST_BITS_PER_WIDE_INT
7149 /* If this extraction is going into the destination of a SET,
7150 make a STRICT_LOW_PART unless we made a MEM. */
7165 /* If we know that no extraneous bits are set, and that the high
7166 bit is not set, convert the extraction to the cheaper of
7167 sign and zero extension, that are equivalent in these cases. */
7173 {
7177 /* Prefer ZERO_EXTENSION, since it gives more information to
7178 backends. */
7183 }
7185 /* Otherwise, sign- or zero-extend unless we already are in the
7186 proper mode. */
7190 }
7192 /* Unless this is a COMPARE or we have a funny memory reference,
7193 don't do anything with zero-extending field extracts starting at
7194 the low-order bit since they are simple AND operations. */
7199 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7200 if the position is not a constant and the length is not 1. In all
7201 other cases, we would only be going outside our object in cases when
7202 an original shift would have been undefined. */
7211 /* If INNER is not from memory, we want it to have the mode of a register
7212 extraction pattern's structure operand, or word_mode if there is no
7213 such pattern. The same applies to extraction_mode and pos_mode
7214 and their respective operands.
7216 For memory, assume that the desired extraction_mode and pos_mode
7217 are the same as for a register operation, since at present we don't
7218 have named patterns for aligned memory structures. */
7222 {
7226 }
7228 /* Never narrow an object, since that might not be safe. */
7236 else
7237 {
7238 /* Be careful not to go beyond the extracted object and maintain the
7239 natural alignment of the memory. */
7243 {
7246 }
7247 }
7252 {
7253 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7254 BITS_BIG_ENDIAN style. If position is constant, compute new
7255 position. Otherwise, build subtraction.
7256 Note that POS is relative to the mode of the original argument.
7257 If it's a MEM we need to recompute POS relative to that.
7258 However, if we're extracting from (or inserting into) a register,
7259 we want to recompute POS relative to wanted_inner_mode. */
7266 else
7267 pos_rtx
7270 pos_rtx);
7271 /* POS may be less than 0 now, but we check for that below.
7272 Note that it can only be less than 0 if !MEM_P (inner). */
7273 }
7275 /* If INNER has a wider mode, and this is a constant extraction, try to
7276 make it smaller and adjust the byte to point to the byte containing
7277 the value. */
7280 && ! pos_rtx
7285 {
7288 /* The computations below will be correct if the machine is big
7289 endian in both bits and bytes or little endian in bits and bytes.
7290 If it is mixed, we must adjust. */
7292 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7293 adjust OFFSET to compensate. */
7298 /* We can now move to the desired byte. */
7309 }
7311 /* If INNER is not memory, get it into the proper mode. If we are changing
7312 its mode, POS must be a constant and smaller than the size of the new
7313 mode. */
7315 {
7316 /* On the LHS, don't create paradoxical subregs implicitely truncating
7317 the register unless TRULY_NOOP_TRUNCATION. */
7320 wanted_inner_mode))
7332 pos_rtx
7338 }
7340 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7341 have to zero extend. Otherwise, we can just use a SUBREG. */
7344 {
7348 /* If we know that no extraneous bits are set, and that the high
7349 bit is not set, convert extraction to cheaper one - either
7350 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7351 cases. */
7359 {
7363 /* Prefer ZERO_EXTENSION, since it gives more information to
7364 backends. */
7368 }
7370 }
7372 /* Make POS_RTX unless we already have it and it is correct. If we don't
7373 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7374 be a CONST_INT. */
7381 /* Make the required operation. See if we can use existing rtx. */
7388 }
7389 \f
7390 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7391 with any other operations in X. Return X without that shift if so. */
7393 static rtx
7395 {
7398 rtx tem;
7401 {
7403 /* This is the shift itself. If it is wide enough, we will return
7404 either the value being shifted if the shift count is equal to
7405 COUNT or a shift for the difference. */
7419 /* If we can safely shift this constant and we find the inner shift,
7420 make a new operation. */
7425 {
7429 }
7434 }
7437 }
7438 \f
7439 /* Look at the expression rooted at X. Look for expressions
7440 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7441 Form these expressions.
7443 Return the new rtx, usually just X.
7445 Also, for machines like the VAX that don't have logical shift insns,
7446 try to convert logical to arithmetic shift operations in cases where
7447 they are equivalent. This undoes the canonicalizations to logical
7448 shifts done elsewhere.
7450 We try, as much as possible, to re-use rtl expressions to save memory.
7452 IN_CODE says what kind of expression we are processing. Normally, it is
7453 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7454 being kludges), it is MEM. When processing the arguments of a comparison
7455 or a COMPARE against zero, it is COMPARE. */
7457 rtx
7459 {
7467 rtx tem;
7470 /* Select the code to be used in recursive calls. Once we are inside an
7471 address, we stay there. If we have a comparison, set to COMPARE,
7472 but once inside, go back to our default of SET. */
7481 /* Process depending on the code of this operation. If NEW is set
7482 nonzero, it will be returned. */
7485 {
7487 /* Convert shifts by constants into multiplications if inside
7488 an address. */
7493 {
7499 {
7502 }
7505 }
7515 {
7519 }
7522 {
7526 mode));
7528 }
7529 else
7530 {
7534 }
7545 {
7549 }
7552 {
7556 mode));
7558 }
7559 else
7560 {
7564 }
7568 /* If the second operand is not a constant, we can't do anything
7569 with it. */
7573 /* If the constant is a power of two minus one and the first operand
7574 is a logical right shift, make an extraction. */
7577 {
7581 }
7583 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7588 {
7590 next_code);
7594 }
7595 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7601 {
7602 /* Apply the distributive law, and then try to make extractions. */
7609 }
7611 /* If we are have (and (rotate X C) M) and C is larger than the number
7612 of bits in M, this is an extraction. */
7618 {
7624 }
7626 /* On machines without logical shifts, if the operand of the AND is
7627 a logical shift and our mask turns off all the propagated sign
7628 bits, we can replace the logical shift with an arithmetic shift. */
7636 {
7643 make_compound_operation
7646 }
7648 /* If the constant is one less than a power of two, this might be
7649 representable by an extraction even if no shift is present.
7650 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7651 we are in a COMPARE. */
7655 next_code),
7658 /* If we are in a comparison and this is an AND with a power of two,
7659 convert this into the appropriate bit extract. */
7664 next_code),
7670 /* If the sign bit is known to be zero, replace this with an
7671 arithmetic shift. */
7676 {
7679 next_code),
7682 }
7684 /* ... fall through ... */
7690 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7691 this is a SIGN_EXTRACT. */
7698 {
7705 }
7707 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7708 If so, try to merge the shifts into a SIGN_EXTEND. We could
7709 also do this for some cases of SIGN_EXTRACT, but it doesn't
7710 seem worth the effort; the case checked for occurs on Alpha. */
7726 /* Call ourselves recursively on the inner expression. If we are
7727 narrowing the object and it has a different RTL code from
7728 what it originally did, do this SUBREG as a force_to_mode. */
7729 {
7733 /* If in_code is COMPARE, it isn't always safe to pass it through
7734 to the recursive make_compound_operation call. */
7738 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7739 is (const_int 0), rather than
7740 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7750 simplified
7758 {
7759 rtx newer
7762 /* If we have something other than a SUBREG, we might have
7763 done an expansion, so rerun ourselves. */
7767 /* force_to_mode can expand compounds. If it just re-expanded the
7768 compound, use gen_lowpart to convert to the desired mode. */
7770 /* Likewise if it re-expanded the compound only partially.
7771 This happens for SUBREG of ZERO_EXTRACT if they extract
7772 the same number of bits. */
7781 }
7785 }
7790 }
7793 {
7796 }
7798 /* Now recursively process each operand of this operation. We need to
7799 handle ZERO_EXTEND specially so that we don't lose track of the
7800 inner mode. */
7802 {
7810 }
7815 {
7818 }
7821 {
7824 }
7826 maybe_swap:
7827 /* If this is a commutative operation, the changes to the operands
7828 may have made it noncanonical. */
7831 {
7835 }
7838 }
7839 \f
7840 /* Given M see if it is a value that would select a field of bits
7841 within an item, but not the entire word. Return -1 if not.
7842 Otherwise, return the starting position of the field, where 0 is the
7843 low-order bit.
7845 *PLEN is set to the length of the field. */
7847 static int
7849 {
7850 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7855 /* Now shift off the low-order zero bits and see if we have a
7856 power of two minus 1. */
7864 }
7865 \f
7866 /* If X refers to a register that equals REG in value, replace these
7867 references with REG. */
7868 static rtx
7870 {
7878 {
7914 {
7918 else
7920 }
7922 /* fall through */
7929 {
7932 {
7934 {
7937 }
7939 }
7940 }
7942 {
7945 {
7948 {
7950 {
7953 }
7955 }
7956 }
7957 }
7960 }
7963 }
7965 /* Return X converted to MODE. If the value is already truncated to
7966 MODE we can just return a subreg even though in the general case we
7967 would need an explicit truncation. */
7969 static rtx
7971 {
7976 {
7977 /* Bit-cast X into an integer mode. */
7982 }
7985 }
7987 /* See if X can be simplified knowing that we will only refer to it in
7988 MODE and will only refer to those bits that are nonzero in MASK.
7989 If other bits are being computed or if masking operations are done
7990 that select a superset of the bits in MASK, they can sometimes be
7991 ignored.
7993 Return a possibly simplified expression, but always convert X to
7994 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7996 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7997 are all off in X. This is used when X will be complemented, by either
7998 NOT, NEG, or XOR. */
8000 static rtx
8003 {
8010 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8011 code below will do the wrong thing since the mode of such an
8012 expression is VOIDmode.
8014 Also do nothing if X is a CLOBBER; this can happen if X was
8015 the return value from a call to gen_lowpart. */
8019 /* We want to perform the operation is its present mode unless we know
8020 that the operation is valid in MODE, in which case we do the operation
8021 in MODE. */
8026 /* It is not valid to do a right-shift in a narrower mode
8027 than the one it came in with. */
8032 /* Truncate MASK to fit OP_MODE. */
8036 /* When we have an arithmetic operation, or a shift whose count we
8037 do not know, we need to assume that all bits up to the highest-order
8038 bit in MASK will be needed. This is how we form such a mask. */
8041 else
8045 /* Determine what bits of X are guaranteed to be (non)zero. */
8048 /* If none of the bits in X are needed, return a zero. */
8052 /* If X is a CONST_INT, return a new one. Do this here since the
8053 test below will fail. */
8055 {
8058 else
8059 {
8062 }
8063 }
8065 /* If X is narrower than MODE and we want all the bits in X's mode, just
8066 get X in the proper mode. */
8071 /* We can ignore the effect of a SUBREG if it narrows the mode or
8072 if the constant masks to zero all the bits the mode doesn't have. */
8082 /* The arithmetic simplifications here only work for scalar integer modes. */
8087 {
8089 /* If X is a (clobber (const_int)), return it since we know we are
8090 generating something that won't match. */
8103 /* Similarly for a truncate. */
8107 /* If this is an AND with a constant, convert it into an AND
8108 whose constant is the AND of that constant with MASK. If it
8109 remains an AND of MASK, delete it since it is redundant. */
8112 {
8116 /* If X is still an AND, see if it is an AND with a mask that
8117 is just some low-order bits. If so, and it is MASK, we don't
8118 need it. */
8125 /* If it remains an AND, try making another AND with the bits
8126 in the mode mask that aren't in MASK turned on. If the
8127 constant in the AND is wide enough, this might make a
8128 cheaper constant. */
8133 {
8134 unsigned HOST_WIDE_INT cval
8137 rtx y;
8144 }
8147 }
8152 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8153 low-order bits (as in an alignment operation) and FOO is already
8154 aligned to that boundary, mask C1 to that boundary as well.
8155 This may eliminate that PLUS and, later, the AND. */
8157 {
8161 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8162 number, sign extend it. */
8175 }
8177 /* ... fall through ... */
8180 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8181 most significant bit in MASK since carries from those bits will
8182 affect the bits we are interested in. */
8187 /* If X is (minus C Y) where C's least set bit is larger than any bit
8188 in the mask, then we may replace with (neg Y). */
8193 {
8197 }
8199 /* Similarly, if C contains every bit in the fuller_mask, then we may
8200 replace with (not Y). */
8203 {
8207 }
8214 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8215 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8216 operation which may be a bitfield extraction. Ensure that the
8217 constant we form is not wider than the mode of X. */
8229 {
8238 }
8240 binop:
8241 /* For most binary operations, just propagate into the operation and
8242 change the mode if we have an operation of that mode. */
8247 /* If we ended up truncating both operands, truncate the result of the
8248 operation instead. */
8251 {
8254 }
8264 /* For left shifts, do the same, but just for the first operand.
8265 However, we cannot do anything with shifts where we cannot
8266 guarantee that the counts are smaller than the size of the mode
8267 because such a count will have a different meaning in a
8268 wider mode. */
8278 /* If the shift count is a constant and we can do arithmetic in
8279 the mode of the shift, refine which bits we need. Otherwise, use the
8280 conservative form of the mask. */
8286 else
8298 /* Here we can only do something if the shift count is a constant,
8299 this shift constant is valid for the host, and we can do arithmetic
8300 in OP_MODE. */
8306 {
8310 /* Select the mask of the bits we need for the shift operand. */
8313 /* We can only change the mode of the shift if we can do arithmetic
8314 in the mode of the shift and INNER_MASK is no wider than the
8315 width of X's mode. */
8323 }
8325 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8326 shift and AND produces only copies of the sign bit (C2 is one less
8327 than a power of two), we can do this with just a shift. */
8331 /* The shift puts one of the sign bit copies in the least significant
8332 bit. */
8337 /* Number of bits left after the shift must be more than the mask
8338 needs. */
8341 /* Must be more sign bit copies than the mask needs. */
8351 /* If we are just looking for the sign bit, we don't need this shift at
8352 all, even if it has a variable count. */
8356 /* If this is a shift by a constant, get a mask that contains those bits
8357 that are not copies of the sign bit. We then have two cases: If
8358 MASK only includes those bits, this can be a logical shift, which may
8359 allow simplifications. If MASK is a single-bit field not within
8360 those bits, we are requesting a copy of the sign bit and hence can
8361 shift the sign bit to the appropriate location. */
8365 {
8368 /* If the considered data is wider than HOST_WIDE_INT, we can't
8369 represent a mask for all its bits in a single scalar.
8370 But we only care about the lower bits, so calculate these. */
8373 {
8376 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8377 is the number of bits a full-width mask would have set.
8378 We need only shift if these are fewer than nonzero can
8379 hold. If not, we must keep all bits set in nonzero. */
8384 + HOST_BITS_PER_WIDE_INT
8386 }
8387 else
8388 {
8391 }
8394 {
8399 }
8402 {
8403 x = simplify_shift_const
8409 }
8410 }
8412 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8413 even if the shift count isn't a constant. */
8418 shiftrt:
8420 /* If this is a zero- or sign-extension operation that just affects bits
8421 we don't care about, remove it. Be sure the call above returned
8422 something that is still a shift. */
8432 next_select);
8438 /* If the shift count is constant and we can do computations
8439 in the mode of X, compute where the bits we care about are.
8440 Otherwise, we can't do anything. Don't change the mode of
8441 the shift or propagate MODE into the shift, though. */
8444 {
8453 }
8457 /* If we just want the low-order bit, the NEG isn't needed since it
8458 won't change the low-order bit. */
8462 /* We need any bits less significant than the most significant bit in
8463 MASK since carries from those bits will affect the bits we are
8464 interested in. */
8469 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8470 same as the XOR case above. Ensure that the constant we form is not
8471 wider than the mode of X. */
8479 {
8488 }
8490 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8491 use the full mask inside the NOT. */
8494 unop:
8497 next_select));
8503 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8504 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8505 which is equal to STORE_FLAG_VALUE. */
8517 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8518 written in a narrower mode. We play it safe and do not do so. */
8532 }
8534 /* Ensure we return a value of the proper mode. */
8536 }
8537 \f
8538 /* Return nonzero if X is an expression that has one of two values depending on
8539 whether some other value is zero or nonzero. In that case, we return the
8540 value that is being tested, *PTRUE is set to the value if the rtx being
8541 returned has a nonzero value, and *PFALSE is set to the other alternative.
8543 If we return zero, we set *PTRUE and *PFALSE to X. */
8545 static rtx
8547 {
8553 /* If we are comparing a value against zero, we are done. */
8556 {
8560 }
8562 /* If this is a unary operation whose operand has one of two values, apply
8563 our opcode to compute those values. */
8566 {
8571 }
8573 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8574 make can't possibly match and would suppress other optimizations. */
8576 ;
8578 /* If this is a binary operation, see if either side has only one of two
8579 values. If either one does or if both do and they are conditional on
8580 the same value, compute the new true and false values. */
8582 {
8588 {
8589 /* If if_then_else_cond returned zero, then true/false are the
8590 same rtl. We must copy one of them to prevent invalid rtl
8591 sharing. */
8598 {
8603 }
8604 else
8605 {
8608 }
8611 }
8613 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8614 operands is zero when the other is nonzero, and vice-versa,
8615 and STORE_FLAG_VALUE is 1 or -1. */
8621 {
8638 {
8645 const_true_rtx);
8647 }
8648 }
8650 /* Similarly for MULT, AND and UMIN, except that for these the result
8651 is always zero. */
8655 {
8669 {
8672 }
8673 }
8674 }
8677 {
8678 /* If we have IF_THEN_ELSE already, extract the condition and
8679 canonicalize it if it is NE or EQ. */
8685 {
8688 }
8689 else
8691 }
8693 /* If X is a SUBREG, we can narrow both the true and false values
8694 if the inner expression, if there is a condition. */
8698 {
8704 {
8708 }
8709 }
8711 /* If X is a constant, this isn't special and will cause confusions
8712 if we treat it as such. Likewise if it is equivalent to a constant. */
8715 ;
8717 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8718 will be least confusing to the rest of the compiler. */
8720 {
8723 }
8725 /* If X is known to be either 0 or -1, those are the true and
8726 false values when testing X. */
8730 {
8733 }
8735 /* Likewise for 0 or a single bit. */
8738 {
8741 }
8743 /* Otherwise fail; show no condition with true and false values the same. */
8746 }
8747 \f
8748 /* Return the value of expression X given the fact that condition COND
8749 is known to be true when applied to REG as its first operand and VAL
8750 as its second. X is known to not be shared and so can be modified in
8751 place.
8753 We only handle the simplest cases, and specifically those cases that
8754 arise with IF_THEN_ELSE expressions. */
8756 static rtx
8758 {
8760 rtx temp;
8767 /* If either operand of the condition is a floating point value,
8768 then we have to avoid collapsing an EQ comparison. */
8778 /* If X is (abs REG) and we know something about REG's relationship
8779 with zero, we may be able to simplify this. */
8783 {
8792 }
8794 /* The only other cases we handle are MIN, MAX, and comparisons if the
8795 operands are the same as REG and VAL. */
8798 {
8803 {
8805 {
8813 else
8815 }
8818 {
8821 /* Do not reverse the condition when it is NE or EQ.
8822 This is because we cannot conclude anything about
8823 the value of 'SMAX (x, y)' when x is not equal to y,
8824 but we can when x equals y. */
8830 {
8841 }
8842 }
8843 }
8844 }
8846 {
8851 {
8852 /* We must simplify subreg here, before we lose track of the
8853 original inner_mode. */
8858 else
8860 }
8863 }
8864 /* We don't have to handle SIGN_EXTEND here, because even in the
8865 case of replacing something with a modeless CONST_INT, a
8866 CONST_INT is already (supposed to be) a valid sign extension for
8867 its narrower mode, which implies it's already properly
8868 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8869 story is different. */
8871 {
8876 {
8877 /* We must simplify the zero_extend here, before we lose
8878 track of the original inner_mode. */
8883 else
8885 }
8888 }
8892 {
8899 }
8902 }
8903 \f
8904 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8905 assignment as a field assignment. */
8907 static int
8909 {
8916 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8917 Note that all SUBREGs of MEM are paradoxical; otherwise they
8918 would have been rewritten. */
8931 /* We used to see if get_last_value of X and Y were the same but that's
8932 not correct. In one direction, we'll cause the assignment to have
8933 the wrong destination and in the case, we'll import a register into this
8934 insn that might have already have been dead. So fail if none of the
8935 above cases are true. */
8937 }
8938 \f
8939 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8940 Return that assignment if so.
8942 We only handle the most common cases. */
8944 static rtx
8946 {
8949 rtx assign;
8951 HOST_WIDE_INT c1;
8952 HOST_WIDE_INT pos;
8954 rtx other;
8957 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8958 a clear of a one-bit field. We will have changed it to
8959 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8960 for a SUBREG. */
8966 {
8972 }
8982 {
8989 }
8991 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8992 one-bit field. */
8996 {
9002 }
9004 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9005 SRC is an AND with all bits of that field set, then we can discard
9006 the AND. */
9011 {
9018 else
9021 /* Complete overlap. We can remove the source AND. */
9025 /* Partial overlap. We can reduce the source AND. */
9027 {
9032 }
9033 }
9035 /* The other case we handle is assignments into a constant-position
9036 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9037 a mask that has all one bits except for a group of zero bits and
9038 OTHER is known to have zeros where C1 has ones, this is such an
9039 assignment. Compute the position and length from C1. Shift OTHER
9040 to the appropriate position, force it to the required mode, and
9041 make the extraction. Check for the AND in both operands. */
9057 else
9070 /* The mode to use for the source is the mode of the assignment, or of
9071 what is inside a possible STRICT_LOW_PART. */
9075 /* Shift OTHER right POS places and make it the source, restricting it
9076 to the proper length and mode. */
9081 dest);
9088 /* If SRC is masked by an AND that does not make a difference in
9089 the value being stored, strip it. */
9100 }
9101 \f
9102 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9103 if so. */
9105 static rtx
9107 {
9111 rtx tem;
9113 /* Distributivity is not true for floating point as it can change the
9114 value. So we don't do it unless -funsafe-math-optimizations. */
9119 /* The outer operation can only be one of the following: */
9127 /* If either operand is a primitive we can't do anything, so get out
9128 fast. */
9138 /* See if the inner and outer operations distribute. */
9140 {
9145 /* These all distribute except over PLUS. */
9156 /* This is also a multiply, so it distributes over everything. */
9159 /* This used to handle SUBREG, but this turned out to be counter-
9160 productive, since (subreg (op ...)) usually is not handled by
9161 insn patterns, and this "optimization" therefore transformed
9162 recognizable patterns into unrecognizable ones. Therefore the
9163 SUBREG case was removed from here.
9165 It is possible that distributing SUBREG over arithmetic operations
9166 leads to an intermediate result than can then be optimized further,
9167 e.g. by moving the outer SUBREG to the other side of a SET as done
9168 in simplify_set. This seems to have been the original intent of
9169 handling SUBREGs here.
9171 However, with current GCC this does not appear to actually happen,
9172 at least on major platforms. If some case is found where removing
9173 the SUBREG case here prevents follow-on optimizations, distributing
9174 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9178 }
9180 /* Set LHS and RHS to the inner operands (A and B in the example
9181 above) and set OTHER to the common operand (C in the example).
9182 There is only one way to do this unless the inner operation is
9183 commutative. */
9195 else
9198 /* Form the new inner operation, seeing if it simplifies first. */
9201 /* There is one exception to the general way of distributing:
9202 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9204 {
9207 }
9209 /* We may be able to continuing distributing the result, so call
9210 ourselves recursively on the inner operation before forming the
9211 outer operation, which we return. */
9214 }
9216 /* See if X is of the form (* (+ A B) C), and if so convert to
9217 (+ (* A C) (* B C)) and try to simplify.
9219 Most of the time, this results in no change. However, if some of
9220 the operands are the same or inverses of each other, simplifications
9221 will result.
9223 For example, (and (ior A B) (not B)) can occur as the result of
9224 expanding a bit field assignment. When we apply the distributive
9225 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9226 which then simplifies to (and (A (not B))).
9228 Note that no checks happen on the validity of applying the inverse
9229 distributive law. This is pointless since we can do it in the
9230 few places where this routine is called.
9232 N is the index of the term that is decomposed (the arithmetic operation,
9233 i.e. (+ A B) in the first example above). !N is the index of the term that
9234 is distributed, i.e. of C in the first example above. */
9235 static rtx
9237 {
9242 /* Distributivity is not true for floating point as it can change the
9243 value. So we don't do it unless -funsafe-math-optimizations. */
9260 /* Special case (and (xor B C) (not A)), which is equivalent to
9261 (xor (ior A B) (ior A C)) */
9263 {
9266 }
9269 {
9270 /* Distribute the second term. */
9273 }
9274 else
9275 {
9276 /* Distribute the first term. */
9279 }
9289 }
9290 \f
9291 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9292 in MODE. Return an equivalent form, if different from (and VAROP
9293 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9295 static rtx
9298 {
9301 rtx orig_varop;
9309 /* Simplify VAROP knowing that we will be only looking at some of the
9310 bits in it.
9312 Note by passing in CONSTOP, we guarantee that the bits not set in
9313 CONSTOP are not significant and will never be examined. We must
9314 ensure that is the case by explicitly masking out those bits
9315 before returning. */
9318 /* If VAROP is a CLOBBER, we will fail so return it. */
9322 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9323 to VAROP and return the new constant. */
9327 /* See what bits may be nonzero in VAROP. Unlike the general case of
9328 a call to nonzero_bits, here we don't care about bits outside
9329 MODE. */
9333 /* Turn off all bits in the constant that are known to already be zero.
9334 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9335 which is tested below. */
9339 /* If we don't have any bits left, return zero. */
9343 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9344 a power of two, we can replace this with an ASHIFT. */
9349 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9350 or XOR, then try to apply the distributive law. This may eliminate
9351 operations if either branch can be simplified because of the AND.
9352 It may also make some cases more complex, but those cases probably
9353 won't match a pattern either with or without this. */
9356 return
9357 gen_lowpart
9359 apply_distributive_law
9364 constop),
9368 constop))));
9370 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9371 the AND and see if one of the operands simplifies to zero. If so, we
9372 may eliminate it. */
9376 {
9385 }
9387 /* Make a SUBREG if necessary. If we can't make it, fail. */
9392 /* If we are only masking insignificant bits, return VAROP. */
9399 /* Otherwise, return an AND. */
9401 }
9404 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9405 in MODE.
9407 Return an equivalent form, if different from X. Otherwise, return X. If
9408 X is zero, we are to always construct the equivalent form. */
9410 static rtx
9413 {
9424 }
9425 \f
9426 /* Given a REG, X, compute which bits in X can be nonzero.
9427 We don't care about bits outside of those defined in MODE.
9429 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9430 a shift, AND, or zero_extract, we can do better. */
9432 static rtx
9434 const_rtx known_x ATTRIBUTE_UNUSED,
9438 {
9439 rtx tem;
9442 /* If X is a register whose nonzero bits value is current, use it.
9443 Otherwise, if X is a register whose value we can find, use that
9444 value. Otherwise, use the previously-computed global nonzero bits
9445 for this register. */
9458 && !REGNO_REG_SET_P
9460 {
9463 }
9468 {
9469 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9470 /* If X is narrower than MODE and TEM is a non-negative
9471 constant that would appear negative in the mode of X,
9472 sign-extend it for use in reg_nonzero_bits because some
9473 machines (maybe most) will actually do the sign-extension
9474 and this is the conservative approach.
9476 ??? For 2.5, try to tighten up the MD files in this regard
9477 instead of this kludge. */
9484 #endif
9486 }
9488 {
9492 /* We don't know anything about the upper bits. */
9495 }
9498 }
9500 /* Return the number of bits at the high-order end of X that are known to
9501 be equal to the sign bit. X will be used in mode MODE; if MODE is
9502 VOIDmode, X will be used in its own mode. The returned value will always
9503 be between 1 and the number of bits in MODE. */
9505 static rtx
9507 const_rtx known_x ATTRIBUTE_UNUSED,
9508 enum machine_mode known_mode
9509 ATTRIBUTE_UNUSED,
9512 {
9513 rtx tem;
9525 && !REGNO_REG_SET_P
9527 {
9530 }
9541 }
9542 \f
9543 /* Return the number of "extended" bits there are in X, when interpreted
9544 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9545 unsigned quantities, this is the number of high-order zero bits.
9546 For signed quantities, this is the number of copies of the sign bit
9547 minus 1. In both case, this function returns the number of "spare"
9548 bits. For example, if two quantities for which this function returns
9549 at least 1 are added, the addition is known not to overflow.
9551 This function will always return 0 unless called during combine, which
9552 implies that it must be called from a define_split. */
9554 unsigned int
9556 {
9566 }
9568 /* This function is called from `simplify_shift_const' to merge two
9569 outer operations. Specifically, we have already found that we need
9570 to perform operation *POP0 with constant *PCONST0 at the outermost
9571 position. We would now like to also perform OP1 with constant CONST1
9572 (with *POP0 being done last).
9574 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9575 the resulting operation. *PCOMP_P is set to 1 if we would need to
9576 complement the innermost operand, otherwise it is unchanged.
9578 MODE is the mode in which the operation will be done. No bits outside
9579 the width of this mode matter. It is assumed that the width of this mode
9580 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9582 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9583 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9584 result is simply *PCONST0.
9586 If the resulting operation cannot be expressed as one operation, we
9587 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9589 static int
9590 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9591 {
9598 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9602 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9603 if OP0 is SET. */
9612 {
9614 {
9632 }
9633 }
9635 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9639 /* If the two constants aren't the same, we can't do anything. The
9640 remaining six cases can all be done. */
9644 else
9646 {
9649 /* (a & b) | b == b */
9652 /* (a ^ b) | b == a | b */
9653 {;}
9658 /* (a & b) ^ b == (~a) & b */
9661 /* (a | b) ^ b == a & ~b */
9667 /* (a | b) & b == b */
9670 /* (a ^ b) & b) == (~a) & b */
9675 }
9677 /* Check for NO-OP cases. */
9690 /* ??? Slightly redundant with the above mask, but not entirely.
9691 Moving this above means we'd have to sign-extend the mode mask
9692 for the final test. */
9697 }
9698 \f
9699 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9700 the shift in. The original shift operation CODE is performed on OP in
9701 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9702 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9703 result of the shift is subject to operation OUTER_CODE with operand
9704 OUTER_CONST. */
9706 static enum machine_mode
9710 {
9715 /* In general we can't perform in wider mode for right shift and rotate. */
9717 {
9719 /* We can still widen if the bits brought in from the left are identical
9720 to the sign bit of ORIG_MODE. */
9728 /* Similarly here but with zero bits. */
9733 /* We can also widen if the bits brought in will be masked off. This
9734 operation is performed in ORIG_MODE. */
9736 {
9742 }
9743 /* fall through */
9753 }
9754 }
9756 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9757 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9758 if we cannot simplify it. Otherwise, return a simplified value.
9760 The shift is normally computed in the widest mode we find in VAROP, as
9761 long as it isn't a different number of words than RESULT_MODE. Exceptions
9762 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9764 static rtx
9767 {
9773 unsigned int mode_words
9775 /* We form (outer_op (code varop count) (outer_const)). */
9781 /* Make sure and truncate the "natural" shift on the way in. We don't
9782 want to do this inside the loop as it makes it more difficult to
9783 combine shifts. */
9787 /* If we were given an invalid count, don't do anything except exactly
9788 what was requested. */
9795 /* Unless one of the branches of the `if' in this loop does a `continue',
9796 we will `break' the loop after the `if'. */
9799 {
9800 /* If we have an operand of (clobber (const_int 0)), fail. */
9804 /* Convert ROTATERT to ROTATE. */
9806 {
9811 else
9813 }
9818 /* Handle cases where the count is greater than the size of the mode
9819 minus 1. For ASHIFT, use the size minus one as the count (this can
9820 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9821 take the count modulo the size. For other shifts, the result is
9822 zero.
9824 Since these shifts are being produced by the compiler by combining
9825 multiple operations, each of which are defined, we know what the
9826 result is supposed to be. */
9829 {
9834 else
9835 {
9836 /* We can't simply return zero because there may be an
9837 outer op. */
9841 }
9842 }
9844 /* If we discovered we had to complement VAROP, leave. Making a NOT
9845 here would cause an infinite loop. */
9849 /* An arithmetic right shift of a quantity known to be -1 or 0
9850 is a no-op. */
9854 {
9857 }
9859 /* If we are doing an arithmetic right shift and discarding all but
9860 the sign bit copies, this is equivalent to doing a shift by the
9861 bitsize minus one. Convert it into that shift because it will often
9862 allow other simplifications. */
9869 /* We simplify the tests below and elsewhere by converting
9870 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9871 `make_compound_operation' will convert it to an ASHIFTRT for
9872 those machines (such as VAX) that don't have an LSHIFTRT. */
9889 {
9896 {
9899 }
9903 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9904 minus the width of a smaller mode, we can do this with a
9905 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9912 {
9921 }
9925 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9926 the same number of words as what we've seen so far. Then store
9927 the widest mode in MODE. */
9933 == mode_words
9936 {
9941 }
9945 /* Some machines use MULT instead of ASHIFT because MULT
9946 is cheaper. But it is still better on those machines to
9947 merge two shifts into one. */
9950 {
9951 varop
9957 }
9961 /* Similar, for when divides are cheaper. */
9964 {
9965 varop
9971 }
9975 /* If we are extracting just the sign bit of an arithmetic
9976 right shift, that shift is not needed. However, the sign
9977 bit of a wider mode may be different from what would be
9978 interpreted as the sign bit in a narrower mode, so, if
9979 the result is narrower, don't discard the shift. */
9984 {
9987 }
9989 /* ... fall through ... */
9994 /* Here we have two nested shifts. The result is usually the
9995 AND of a new shift with a mask. We compute the result below. */
10002 {
10006 rtx mask_rtx;
10008 /* We have one common special case. We can't do any merging if
10009 the inner code is an ASHIFTRT of a smaller mode. However, if
10010 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10011 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10012 we can convert it to
10013 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10014 This simplifies certain SIGN_EXTEND operations. */
10018 {
10019 /* C3 has the low-order C1 bits zero. */
10031 }
10033 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10034 than C1 high-order bits equal to the sign bit, we can convert
10035 this to either an ASHIFT or an ASHIFTRT depending on the
10036 two counts.
10038 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10044 {
10048 {
10051 }
10054 }
10056 /* There are some cases we can't do. If CODE is ASHIFTRT,
10057 we can only do this if FIRST_CODE is also ASHIFTRT.
10059 We can't do the case when CODE is ROTATE and FIRST_CODE is
10060 ASHIFTRT.
10062 If the mode of this shift is not the mode of the outer shift,
10063 we can't do this if either shift is a right shift or ROTATE.
10065 Finally, we can't do any of these if the mode is too wide
10066 unless the codes are the same.
10068 Handle the case where the shift codes are the same
10069 first. */
10072 {
10081 }
10092 /* To compute the mask to apply after the shift, shift the
10093 nonzero bits of the inner shift the same way the
10094 outer shift will. */
10097 result_mode);
10099 mask_rtx
10103 /* Give up if we can't compute an outer operation to use. */
10111 /* If the shifts are in the same direction, we add the
10112 counts. Otherwise, we subtract them. */
10116 else
10119 /* If COUNT is positive, the new shift is usually CODE,
10120 except for the two exceptions below, in which case it is
10121 FIRST_CODE. If the count is negative, FIRST_CODE should
10122 always be used */
10132 }
10134 /* If we have (A << B << C) for any shift, we can convert this to
10135 (A << C << B). This wins if A is a constant. Only try this if
10136 B is not a constant. */
10141 {
10148 }
10155 /* Make this fit the case below. */
10162 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10163 with C the size of VAROP - 1 and the shift is logical if
10164 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10165 we have an (le X 0) operation. If we have an arithmetic shift
10166 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10167 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10175 {
10178 const0_rtx);
10184 }
10186 /* If we have (shift (logical)), move the logical to the outside
10187 to allow it to possibly combine with another logical and the
10188 shift to combine with another shift. This also canonicalizes to
10189 what a ZERO_EXTRACT looks like. Also, some machines have
10190 (and (shift)) insns. */
10193 /* We can't do this if we have (ashiftrt (xor)) and the
10194 constant has its sign bit set in shift_mode. */
10197 shift_mode))
10205 {
10208 }
10210 /* If we can't do that, try to simplify the shift in each arm of the
10211 logical expression, make a new logical expression, and apply
10212 the inverse distributive law. This also can't be done
10213 for some (ashiftrt (xor)). */
10217 shift_mode)))
10218 {
10230 }
10234 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10235 says that the sign bit can be tested, FOO has mode MODE, C is
10236 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10237 that may be nonzero. */
10247 {
10251 }
10255 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10256 than the number of bits in the mode is equivalent to A. */
10260 {
10264 }
10266 /* NEG commutes with ASHIFT since it is multiplication. Move the
10267 NEG outside to allow shifts to combine. */
10271 {
10274 }
10278 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10279 is one less than the number of bits in the mode is
10280 equivalent to (xor A 1). */
10287 {
10291 }
10293 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10294 that might be nonzero in BAR are those being shifted out and those
10295 bits are known zero in FOO, we can replace the PLUS with FOO.
10296 Similarly in the other operand order. This code occurs when
10297 we are computing the size of a variable-size array. */
10304 {
10307 }
10315 result_mode)))
10316 {
10319 }
10321 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10330 {
10333 }
10335 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10336 signbit', and attempt to change the PLUS to an XOR and move it to
10337 the outer operation as is done above in the AND/IOR/XOR case
10338 leg for shift(logical). See details in logical handling above
10339 for reasoning in doing so. */
10349 {
10352 }
10357 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10358 with C the size of VAROP - 1 and the shift is logical if
10359 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10360 we have a (gt X 0) operation. If the shift is arithmetic with
10361 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10362 we have a (neg (gt X 0)) operation. */
10371 {
10374 const0_rtx);
10380 }
10384 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10385 if the truncate does not affect the value. */
10392 {
10395 varop_inner
10398 GEN_INT
10403 }
10408 }
10411 }
10416 /* We have now finished analyzing the shift. The result should be
10417 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10418 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10419 to the result of the shift. OUTER_CONST is the relevant constant,
10420 but we must turn off all bits turned off in the shift. */
10428 /* Make a SUBREG if necessary. If we can't make it, fail. */
10433 /* If we have an outer operation and we just made a shift, it is
10434 possible that we could have simplified the shift were it not
10435 for the outer operation. So try to do the simplification
10436 recursively. */
10440 else
10446 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10447 turn off all the bits that the shift would have turned off. */
10452 /* Do the remainder of the processing in RESULT_MODE. */
10455 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10456 operation. */
10461 {
10469 {
10470 /* This means that we have determined that the result is
10471 equivalent to a constant. This should be rare. */
10474 }
10477 else
10480 }
10483 }
10485 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10486 The result of the shift is RESULT_MODE. If we cannot simplify it,
10487 return X or, if it is NULL, synthesize the expression with
10488 simplify_gen_binary. Otherwise, return a simplified value.
10490 The shift is normally computed in the widest mode we find in VAROP, as
10491 long as it isn't a different number of words than RESULT_MODE. Exceptions
10492 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10494 static rtx
10497 {
10507 }
10509 \f
10510 /* Like recog, but we receive the address of a pointer to a new pattern.
10511 We try to match the rtx that the pointer points to.
10512 If that fails, we may try to modify or replace the pattern,
10513 storing the replacement into the same pointer object.
10515 Modifications include deletion or addition of CLOBBERs.
10517 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10518 the CLOBBERs are placed.
10520 The value is the final insn code from the pattern ultimately matched,
10521 or -1. */
10523 static int
10525 {
10527 rtx pat_without_clobbers;
10535 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10536 we use to indicate that something didn't match. If we find such a
10537 thing, force rejection. */
10551 {
10554 else
10557 }
10559 /* If it isn't, there is the possibility that we previously had an insn
10560 that clobbered some register as a side effect, but the combined
10561 insn doesn't need to do that. So try once more without the clobbers
10562 unless this represents an ASM insn. */
10566 {
10571 {
10574 pos++;
10575 }
10585 {
10588 else
10591 }
10592 }
10599 /* Recognize all noop sets, these will be killed by followup pass. */
10603 /* If we had any clobbers to add, make a new pattern than contains
10604 them. Then check to make sure that all of them are dead. */
10606 {
10616 else
10623 {
10628 {
10632 }
10633 }
10635 }
10639 {
10646 /* Allow targets to reject combined insn. */
10648 {
10651 dump_file);
10653 /* Callers expect recog_for_combine to strip
10654 clobbers from the pattern on failure. */
10659 }
10664 }
10670 }
10671 \f
10672 /* Like gen_lowpart_general but for use by combine. In combine it
10673 is not possible to create any new pseudoregs. However, it is
10674 safe to create invalid memory addresses, because combine will
10675 try to recognize them and all they will do is make the combine
10676 attempt fail.
10678 If for some reason this cannot do its job, an rtx
10679 (clobber (const_int 0)) is returned.
10680 An insn containing that will not be recognized. */
10682 static rtx
10684 {
10688 rtx result;
10693 /* We can only support MODE being wider than a word if X is a
10694 constant integer or has a mode the same size. */
10699 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10700 won't know what to do. So we will strip off the SUBREG here and
10701 process normally. */
10703 {
10706 /* For use in case we fall down into the address adjustments
10707 further below, we need to adjust the known mode and size of
10708 x; imode and isize, since we just adjusted x. */
10715 }
10723 {
10726 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10727 address. */
10732 /* If we want to refer to something bigger than the original memref,
10733 generate a paradoxical subreg instead. That will force a reload
10734 of the original memref X. */
10741 /* Adjust the address so that the address-after-the-data is
10742 unchanged. */
10747 }
10749 /* If X is a comparison operator, rewrite it in a new mode. This
10750 probably won't match, but may allow further simplifications. */
10754 /* If we couldn't simplify X any other way, just enclose it in a
10755 SUBREG. Normally, this SUBREG won't match, but some patterns may
10756 include an explicit SUBREG or we may simplify it further in combine. */
10757 else
10758 {
10760 rtx res;
10764 {
10769 }
10773 }
10775 fail:
10777 }
10778 \f
10779 /* Try to simplify a comparison between OP0 and a constant OP1,
10780 where CODE is the comparison code that will be tested, into a
10781 (CODE OP0 const0_rtx) form.
10783 The result is a possibly different comparison code to use.
10784 *POP1 may be updated. */
10786 static enum rtx_code
10788 {
10793 /* Get the constant we are comparing against and turn off all bits
10794 not on in our mode. */
10798 /* If we are comparing against a constant power of two and the value
10799 being compared can only have that single bit nonzero (e.g., it was
10800 `and'ed with that bit), we can replace this with a comparison
10801 with zero. */
10809 {
10812 }
10814 /* Similarly, if we are comparing a value known to be either -1 or
10815 0 with -1, change it to the opposite comparison against zero. */
10820 {
10823 }
10825 /* Do some canonicalizations based on the comparison code. We prefer
10826 comparisons against zero and then prefer equality comparisons.
10827 If we can reduce the size of a constant, we will do that too. */
10829 {
10831 /* < C is equivalent to <= (C - 1) */
10833 {
10836 /* ... fall through to LE case below. */
10837 }
10838 else
10842 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10844 {
10847 }
10849 /* If we are doing a <= 0 comparison on a value known to have
10850 a zero sign bit, we can replace this with == 0. */
10860 /* >= C is equivalent to > (C - 1). */
10862 {
10865 /* ... fall through to GT below. */
10866 }
10867 else
10871 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10873 {
10876 }
10878 /* If we are doing a > 0 comparison on a value known to have
10879 a zero sign bit, we can replace this with != 0. */
10889 /* < C is equivalent to <= (C - 1). */
10891 {
10894 /* ... fall through ... */
10895 }
10896 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10900 {
10904 }
10905 else
10909 /* unsigned <= 0 is equivalent to == 0 */
10912 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10916 {
10919 }
10923 /* >= C is equivalent to > (C - 1). */
10925 {
10928 /* ... fall through ... */
10929 }
10931 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10935 {
10939 }
10940 else
10944 /* unsigned > 0 is equivalent to != 0 */
10947 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10951 {
10954 }
10959 }
10963 }
10964 \f
10965 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10966 comparison code that will be tested.
10968 The result is a possibly different comparison code to use. *POP0 and
10969 *POP1 may be updated.
10971 It is possible that we might detect that a comparison is either always
10972 true or always false. However, we do not perform general constant
10973 folding in combine, so this knowledge isn't useful. Such tautologies
10974 should have been detected earlier. Hence we ignore all such cases. */
10976 static enum rtx_code
10978 {
10985 /* Try a few ways of applying the same transformation to both operands. */
10987 {
10988 #ifndef WORD_REGISTER_OPERATIONS
10989 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10990 so check specially. */
11005 - (GET_MODE_PRECISION
11007 {
11010 }
11011 #endif
11013 /* If both operands are the same constant shift, see if we can ignore the
11014 shift. We can if the shift is a rotate or if the bits shifted out of
11015 this shift are known to be zero for both inputs and if the type of
11016 comparison is compatible with the shift. */
11029 {
11042 else
11044 }
11046 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11047 SUBREGs are of the same mode, and, in both cases, the AND would
11048 be redundant if the comparison was done in the narrower mode,
11049 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11050 and the operand's possibly nonzero bits are 0xffffff01; in that case
11051 if we only care about QImode, we don't need the AND). This case
11052 occurs if the output mode of an scc insn is not SImode and
11053 STORE_FLAG_VALUE == 1 (e.g., the 386).
11055 Similarly, check for a case where the AND's are ZERO_EXTEND
11056 operations from some narrower mode even though a SUBREG is not
11057 present. */
11062 {
11079 {
11083 /* The resulting comparison is always unsigned since we masked
11084 off the original sign bit. */
11088 }
11095 {
11101 }
11105 }
11107 /* If both operands are NOT, we can strip off the outer operation
11108 and adjust the comparison code for swapped operands; similarly for
11109 NEG, except that this must be an equality comparison. */
11115 else
11117 }
11119 /* If the first operand is a constant, swap the operands and adjust the
11120 comparison code appropriately, but don't do this if the second operand
11121 is already a constant integer. */
11123 {
11126 }
11128 /* We now enter a loop during which we will try to simplify the comparison.
11129 For the most part, we only are concerned with comparisons with zero,
11130 but some things may really be comparisons with zero but not start
11131 out looking that way. */
11134 {
11141 HOST_WIDE_INT const_op;
11143 /* We only want to handle integral modes. This catches VOIDmode,
11144 CCmode, and the floating-point modes. An exception is that we
11145 can handle VOIDmode if OP0 is a COMPARE or a comparison
11146 operation. */
11153 /* Try to simplify the compare to constant, possibly changing the
11154 comparison op, and/or changing op1 to zero. */
11158 /* Compute some predicates to simplify code below. */
11165 /* If this is a sign bit comparison and we can do arithmetic in
11166 MODE, say that we will only be needing the sign bit of OP0. */
11173 /* Now try cases based on the opcode of OP0. If none of the cases
11174 does a "continue", we exit this loop immediately after the
11175 switch. */
11178 {
11180 /* If we are extracting a single bit from a variable position in
11181 a constant that has only a single bit set and are comparing it
11182 with zero, we can convert this into an equality comparison
11183 between the position and the location of the single bit. */
11184 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11185 have already reduced the shift count modulo the word size. */
11191 {
11199 /* Result is nonzero iff shift count is equal to I. */
11202 }
11204 /* ... fall through ... */
11209 {
11212 }
11216 /* If testing for equality, we can take the NOT of the constant. */
11219 {
11223 }
11225 /* If just looking at the sign bit, reverse the sense of the
11226 comparison. */
11228 {
11232 }
11236 /* If testing for equality, we can take the NEG of the constant. */
11239 {
11243 }
11245 /* The remaining cases only apply to comparisons with zero. */
11249 /* When X is ABS or is known positive,
11250 (neg X) is < 0 if and only if X != 0. */
11258 {
11262 }
11264 /* If we have NEG of something whose two high-order bits are the
11265 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11267 {
11271 }
11275 /* If we are testing equality and our count is a constant, we
11276 can perform the inverse operation on our RHS. */
11280 {
11284 }
11286 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11287 a particular bit. Convert it to an AND of a constant of that
11288 bit. This will be converted into a ZERO_EXTRACT. */
11292 {
11299 }
11301 /* Fall through. */
11304 /* ABS is ignorable inside an equality comparison with zero. */
11306 {
11309 }
11313 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11314 (compare FOO CONST) if CONST fits in FOO's mode and we
11315 are either testing inequality or have an unsigned
11316 comparison with ZERO_EXTEND or a signed comparison with
11317 SIGN_EXTEND. But don't do it if we don't have a compare
11318 insn of the given mode, since we'd have to revert it
11319 later on, and then we wouldn't know whether to sign- or
11320 zero-extend. */
11323 && ! unsigned_comparison_p
11327 {
11330 }
11334 /* Check for the case where we are comparing A - C1 with C2, that is
11336 (subreg:MODE (plus (A) (-C1))) op (C2)
11338 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11339 comparison in the wider mode. One of the following two conditions
11340 must be true in order for this to be valid:
11342 1. The mode extension results in the same bit pattern being added
11343 on both sides and the comparison is equality or unsigned. As
11344 C2 has been truncated to fit in MODE, the pattern can only be
11345 all 0s or all 1s.
11347 2. The mode extension results in the sign bit being copied on
11348 each side.
11350 The difficulty here is that we have predicates for A but not for
11351 (A - C1) so we need to check that C1 is within proper bounds so
11352 as to perturbate A as little as possible. */
11359 {
11368 /* (A - C1) zero-extends if it is positive and sign-extends
11369 if it is negative, C2 both zero- and sign-extends. */
11373 /* (A - C1) sign-extends if it is positive and 1-extends
11374 if it is negative, C2 both sign- and 1-extends. */
11381 /* (A - C1) always sign-extends, like C2. */
11385 {
11388 }
11389 }
11391 /* If the inner mode is narrower and we are extracting the low part,
11392 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11396 else
11399 /* ... fall through ... */
11409 {
11412 }
11416 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11417 this for equality comparisons due to pathological cases involving
11418 overflows. */
11422 {
11426 }
11428 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11431 {
11435 }
11439 /* We used to optimize signed comparisons against zero, but that
11440 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11441 arrive here as equality comparisons, or (GEU, LTU) are
11442 optimized away. No need to special-case them. */
11444 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11445 (eq B (minus A C)), whichever simplifies. We can only do
11446 this for equality comparisons due to pathological cases involving
11447 overflows. */
11451 {
11455 }
11460 {
11464 }
11466 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11467 of bits in X minus 1, is one iff X > 0. */
11472 {
11476 }
11480 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11481 if C is zero or B is a constant. */
11485 {
11489 }
11497 /* We can't do anything if OP0 is a condition code value, rather
11498 than an actual data value. */
11504 /* Get the two operands being compared. */
11507 else
11510 /* Check for the cases where we simply want the result of the
11511 earlier test or the opposite of that result. */
11515 {
11519 else
11523 {
11528 }
11529 }
11533 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11534 iff X <= 0. */
11538 {
11542 }
11546 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11547 will be converted to a ZERO_EXTRACT later. */
11551 {
11556 }
11558 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11559 zero and X is a comparison and C1 and C2 describe only bits set
11560 in STORE_FLAG_VALUE, we can compare with X. */
11568 {
11575 {
11578 }
11579 }
11581 /* If we are doing an equality comparison of an AND of a bit equal
11582 to the sign bit, replace this with a LT or GE comparison of
11583 the underlying value. */
11590 {
11594 }
11596 /* If this AND operation is really a ZERO_EXTEND from a narrower
11597 mode, the constant fits within that mode, and this is either an
11598 equality or unsigned comparison, try to do this comparison in
11599 the narrower mode.
11601 Note that in:
11603 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11604 -> (ne:DI (reg:SI 4) (const_int 0))
11606 unless TRULY_NOOP_TRUNCATION allows it or the register is
11607 known to hold a value of the required mode the
11608 transformation is invalid. */
11619 {
11622 }
11624 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11625 fits in both M1 and M2 and the SUBREG is either paradoxical
11626 or represents the low part, permute the SUBREG and the AND
11627 and try again. */
11629 {
11632 /* Require an integral mode, to avoid creating something like
11633 (AND:SF ...). */
11635 /* It is unsafe to commute the AND into the SUBREG if the
11636 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11637 not defined. As originally written the upper bits
11638 have a defined value due to the AND operation.
11639 However, if we commute the AND inside the SUBREG then
11640 they no longer have defined values and the meaning of
11641 the code has been changed. */
11643 #ifdef WORD_REGISTER_OPERATIONS
11646 #endif
11656 {
11662 }
11663 }
11665 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11669 {
11674 }
11676 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11677 (eq (and (lshiftrt X) 1) 0).
11678 Also handle the case where (not X) is expressed using xor. */
11682 {
11694 {
11695 op0
11700 }
11701 }
11705 /* If we have (compare (ashift FOO N) (const_int C)) and
11706 the high order N bits of FOO (N+1 if an inequality comparison)
11707 are known to be zero, we can do this by comparing FOO with C
11708 shifted right N bits so long as the low-order N bits of C are
11709 zero. */
11721 {
11722 /* We must perform a logical shift, not an arithmetic one,
11723 as we want the top N bits of C to be zero. */
11730 }
11732 /* If we are doing a sign bit comparison, it means we are testing
11733 a particular bit. Convert it to the appropriate AND. */
11736 {
11743 }
11745 /* If this an equality comparison with zero and we are shifting
11746 the low bit to the sign bit, we can convert this to an AND of the
11747 low-order bit. */
11751 {
11754 }
11758 /* If this is an equality comparison with zero, we can do this
11759 as a logical shift, which might be much simpler. */
11762 {
11767 }
11769 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11770 do the comparison in a narrower mode. */
11780 {
11783 }
11785 /* Likewise if OP0 is a PLUS of a sign extension with a
11786 constant, which is usually represented with the PLUS
11787 between the shifts. */
11799 {
11807 new_const);
11809 }
11811 /* ... fall through ... */
11813 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11814 the low order N bits of FOO are known to be zero, we can do this
11815 by comparing FOO with C shifted left N bits so long as no
11816 overflow occurs. Even if the low order N bits of FOO aren't known
11817 to be zero, if the comparison is >= or < we can use the same
11818 optimization and for > or <= by setting all the low
11819 order N bits in the comparison constant. */
11830 {
11831 unsigned HOST_WIDE_INT low_bits
11836 {
11837 /* If the shift was logical, then we must make the condition
11838 unsigned. */
11846 const_op
11851 }
11852 }
11854 /* If we are using this shift to extract just the sign bit, we
11855 can replace this with an LT or GE comparison. */
11860 {
11864 }
11869 }
11872 }
11874 /* Now make any compound operations involved in this comparison. Then,
11875 check for an outmost SUBREG on OP0 that is not doing anything or is
11876 paradoxical. The latter transformation must only be performed when
11877 it is known that the "extra" bits will be the same in op0 and op1 or
11878 that they don't matter. There are three cases to consider:
11880 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11881 care bits and we can assume they have any convenient value. So
11882 making the transformation is safe.
11884 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11885 In this case the upper bits of op0 are undefined. We should not make
11886 the simplification in that case as we do not know the contents of
11887 those bits.
11889 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11890 UNKNOWN. In that case we know those bits are zeros or ones. We must
11891 also be sure that they are the same as the upper bits of op1.
11893 We can never remove a SUBREG for a non-equality comparison because
11894 the sign bit is in a different place in the underlying object. */
11903 {
11905 {
11906 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11907 implemented. */
11909 {
11912 }
11913 }
11919 {
11925 }
11926 }
11928 /* We now do the opposite procedure: Some machines don't have compare
11929 insns in all modes. If OP0's mode is an integer mode smaller than a
11930 word and we can't do a compare in that mode, see if there is a larger
11931 mode for which we can do the compare. There are a number of cases in
11932 which we can use the wider mode. */
11942 {
11945 /* If this is a test for negative, we can make an explicit
11946 test of the sign bit. Test this first so we can use
11947 a paradoxical subreg to extend OP0. */
11951 {
11952 unsigned HOST_WIDE_INT sign
11959 }
11961 /* If the only nonzero bits in OP0 and OP1 are those in the
11962 narrower mode and this is an equality or unsigned comparison,
11963 we can use the wider mode. Similarly for sign-extended
11964 values, in which case it is true for all comparisons. */
11981 {
11982 /* If OP0 is an AND and we don't have an AND in MODE either,
11983 make a new AND in the proper mode. */
11991 else
11992 {
11994 {
11997 }
11998 else
11999 {
12002 }
12004 }
12005 }
12006 }
12008 /* We may have changed the comparison operands. Re-canonicalize. */
12010 {
12013 }
12015 /* If this machine only supports a subset of valid comparisons, see if we
12016 can convert an unsupported one into a supported one. */
12023 }
12024 \f
12025 /* Utility function for record_value_for_reg. Count number of
12026 rtxs in X. */
12027 static int
12029 {
12036 {
12056 }
12067 }
12068 \f
12069 /* Utility function for following routine. Called when X is part of a value
12070 being stored into last_set_value. Sets last_set_table_tick
12071 for each register mentioned. Similar to mention_regs in cse.c */
12073 static void
12075 {
12081 {
12087 {
12090 }
12093 }
12097 {
12098 /* Check for identical subexpressions. If x contains
12099 identical subexpression we only have to traverse one of
12100 them. */
12102 {
12103 /* Note that at this point x1 has already been
12104 processed. */
12108 /* If x0 and x1 are identical then there is no need to
12109 process x0. */
12113 /* If x0 is identical to a subexpression of x1 then while
12114 processing x1, x0 has already been processed. Thus we
12115 are done with x. */
12120 /* If x1 is identical to a subexpression of x0 then we
12121 still have to process the rest of x0. */
12124 {
12127 }
12128 }
12131 }
12135 }
12137 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12138 are saying that the register is clobbered and we no longer know its
12139 value. If INSN is zero, don't update reg_stat[].last_set; this is
12140 only permitted with VALUE also zero and is used to invalidate the
12141 register. */
12143 static void
12145 {
12151 /* If VALUE contains REG and we have a previous value for REG, substitute
12152 the previous value. */
12154 {
12155 rtx tem;
12157 /* Set things up so get_last_value is allowed to see anything set up to
12158 our insn. */
12162 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12163 it isn't going to be useful and will take a lot of time to process,
12164 so just use the CLOBBER. */
12167 {
12173 {
12174 /* If there are two or more occurrences of REG in VALUE,
12175 prevent the value from growing too much. */
12178 }
12181 }
12182 }
12184 /* For each register modified, show we don't know its value, that
12185 we don't know about its bitwise content, that its value has been
12186 updated, and that we don't know the location of the death of the
12187 register. */
12189 {
12201 }
12203 /* Mark registers that are being referenced in this value. */
12207 /* Now update the status of each register being set.
12208 If someone is using this register in this block, set this register
12209 to invalid since we will get confused between the two lives in this
12210 basic block. This makes using this register always invalid. In cse, we
12211 scan the table to invalidate all entries using this register, but this
12212 is too much work for us. */
12215 {
12221 else
12223 }
12225 /* The value being assigned might refer to X (like in "x++;"). In that
12226 case, we must replace it with (clobber (const_int 0)) to prevent
12227 infinite loops. */
12230 {
12234 }
12236 /* For the main register being modified, update the value, the mode, the
12237 nonzero bits, and the number of sign bit copies. */
12242 {
12250 rsp->last_set_sign_bit_copies
12252 }
12253 }
12255 /* Called via note_stores from record_dead_and_set_regs to handle one
12256 SET or CLOBBER in an insn. DATA is the instruction in which the
12257 set is occurring. */
12259 static void
12261 {
12268 {
12272 }
12275 {
12276 /* If we are setting the whole register, we know its value. Otherwise
12277 show that we don't know the value. We can handle SUBREG in
12278 some cases. */
12289 else
12291 }
12293 /* Ignore pushes, they clobber nothing. */
12296 }
12298 /* Update the records of when each REG was most recently set or killed
12299 for the things done by INSN. This is the last thing done in processing
12300 INSN in the combiner loop.
12302 We update reg_stat[], in particular fields last_set, last_set_value,
12303 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12304 last_death, and also the similar information mem_last_set (which insn
12305 most recently modified memory) and last_call_luid (which insn was the
12306 most recent subroutine call). */
12308 static void
12310 {
12311 rtx link;
12315 {
12318 {
12323 {
12328 }
12329 }
12332 }
12335 {
12336 hard_reg_set_iterator hrsi;
12338 {
12350 }
12354 /* We can't combine into a call pattern. Remember, though, that
12355 the return value register is set at this LUID. We could
12356 still replace a register with the return value from the
12357 wrong subroutine call! */
12359 }
12360 else
12362 }
12364 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12365 register present in the SUBREG, so for each such SUBREG go back and
12366 adjust nonzero and sign bit information of the registers that are
12367 known to have some zero/sign bits set.
12369 This is needed because when combine blows the SUBREGs away, the
12370 information on zero/sign bits is lost and further combines can be
12371 missed because of that. */
12373 static void
12375 {
12377 rtx set;
12385 {
12394 {
12397 }
12401 {
12404 }
12407 {
12410 }
12411 else
12413 }
12414 }
12416 /* Check if X, a register, is known to contain a value already
12417 truncated to MODE. In this case we can use a subreg to refer to
12418 the truncated value even though in the generic case we would need
12419 an explicit truncation. */
12421 static bool
12423 {
12435 }
12437 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12438 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12439 might be able to turn a truncate into a subreg using this information.
12440 Return -1 if traversing *P is complete or 0 otherwise. */
12442 static int
12444 {
12450 {
12461 }
12462 /* ??? For hard-regs we now record everything. We might be able to
12463 optimize this using last_set_mode. */
12466 else
12474 {
12477 }
12480 }
12482 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12483 the modes they are used in. This can help truning TRUNCATEs into
12484 SUBREGs. */
12486 static void
12488 {
12490 }
12492 /* Scan X for promoted SUBREGs. For each one found,
12493 note what it implies to the registers used in it. */
12495 static void
12497 {
12502 else
12503 {
12509 {
12519 }
12520 }
12521 }
12522 \f
12523 /* Verify that all the registers and memory references mentioned in *LOC are
12524 still valid. *LOC was part of a value set in INSN when label_tick was
12525 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12526 the invalid references with (clobber (const_int 0)) and return 1. This
12527 replacement is useful because we often can get useful information about
12528 the form of a value (e.g., if it was produced by a shift that always
12529 produces -1 or 0) even though we don't know exactly what registers it
12530 was produced from. */
12532 static int
12534 {
12541 {
12547 {
12550 /* If this is a pseudo-register that was only set once and not
12551 live at the beginning of the function, it is always valid. */
12554 && (!REGNO_REG_SET_P
12557 {
12561 }
12562 }
12565 }
12566 /* If this is a memory reference, make sure that there were no stores after
12567 it that might have clobbered the value. We don't have alias info, so we
12568 assume any store invalidates it. Moreover, we only have local UIDs, so
12569 we also assume that there were stores in the intervening basic blocks. */
12572 {
12576 }
12579 {
12581 {
12582 /* Check for identical subexpressions. If x contains
12583 identical subexpression we only have to traverse one of
12584 them. */
12586 {
12587 /* Note that at this point x0 has already been checked
12588 and found valid. */
12592 /* If x0 and x1 are identical then x is also valid. */
12596 /* If x1 is identical to a subexpression of x0 then
12597 while checking x0, x1 has already been checked. Thus
12598 it is valid and so as x. */
12603 /* If x0 is identical to a subexpression of x1 then x is
12604 valid iff the rest of x1 is valid. */
12607 return
12611 }
12616 }
12622 }
12624 /* If we haven't found a reason for it to be invalid, it is valid. */
12626 }
12628 /* Get the last value assigned to X, if known. Some registers
12629 in the value may be replaced with (clobber (const_int 0)) if their value
12630 is known longer known reliably. */
12632 static rtx
12634 {
12636 rtx value;
12639 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12640 then convert it to the desired mode. If this is a paradoxical SUBREG,
12641 we cannot predict what values the "extra" bits might have. */
12655 /* If we don't have a value, or if it isn't for this basic block and
12656 it's either a hard register, set more than once, or it's a live
12657 at the beginning of the function, return 0.
12659 Because if it's not live at the beginning of the function then the reg
12660 is always set before being used (is never used without being set).
12661 And, if it's set only once, and it's always set before use, then all
12662 uses must have the same last value, even if it's not from this basic
12663 block. */
12669 || REGNO_REG_SET_P
12673 /* If the value was set in a later insn than the ones we are processing,
12674 we can't use it even if the register was only set once. */
12679 /* If the value has all its registers valid, return it. */
12683 /* Otherwise, make a copy and replace any invalid register with
12684 (clobber (const_int 0)). If that fails for some reason, return 0. */
12691 }
12692 \f
12693 /* Return nonzero if expression X refers to a REG or to memory
12694 that is set in an instruction more recent than FROM_LUID. */
12696 static int
12698 {
12704 {
12708 #ifdef PUSH_ROUNDING
12709 /* Don't allow uses of the stack pointer to be moved,
12710 because we don't know whether the move crosses a push insn. */
12713 #endif
12715 {
12721 }
12723 }
12731 {
12733 {
12738 }
12742 }
12744 }
12745 \f
12746 /* Define three variables used for communication between the following
12747 routines. */
12752 /* Function called via note_stores from reg_dead_at_p.
12754 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12755 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12757 static void
12759 {
12769 }
12771 /* Return nonzero if REG is known to be dead at INSN.
12773 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12774 referencing REG, it is dead. If we hit a SET referencing REG, it is
12775 live. Otherwise, see if it is live or dead at the start of the basic
12776 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12777 must be assumed to be always live. */
12779 static int
12781 {
12782 basic_block block;
12785 /* Set variables for reg_dead_at_p_1. */
12791 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12792 we allow the machine description to decide whether use-and-clobber
12793 patterns are OK. */
12795 {
12799 }
12801 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12802 beginning of basic block. */
12805 {
12807 {
12814 }
12820 }
12822 /* Look at live-in sets for the basic block that we were in. */
12828 }
12829 \f
12830 /* Note hard registers in X that are used. */
12832 static void
12834 {
12840 {
12844 CASE_CONST_ANY:
12849 #ifdef HAVE_cc0
12850 /* CC0 must die in the insn after it is set, so we don't need to take
12851 special note of it here. */
12853 #endif
12857 /* If we are clobbering a MEM, mark any hard registers inside the
12858 address as used. */
12865 /* A hard reg in a wide mode may really be multiple registers.
12866 If so, mark all of them just like the first. */
12868 {
12869 /* None of this applies to the stack, frame or arg pointers. */
12871 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12873 #endif
12874 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12876 #endif
12881 }
12885 {
12886 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12887 the address. */
12899 }
12904 }
12906 /* Recursively scan the operands of this expression. */
12908 {
12912 {
12916 {
12921 }
12922 }
12923 }
12924 }
12925 \f
12926 /* Remove register number REGNO from the dead registers list of INSN.
12928 Return the note used to record the death, if there was one. */
12930 rtx
12932 {
12939 }
12941 /* For each register (hardware or pseudo) used within expression X, if its
12942 death is in an instruction with luid between FROM_LUID (inclusive) and
12943 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12944 list headed by PNOTES.
12946 That said, don't move registers killed by maybe_kill_insn.
12948 This is done when X is being merged by combination into TO_INSN. These
12949 notes will then be distributed as needed. */
12951 static void
12954 {
12960 {
12964 /* Don't move the register if it gets killed in between from and to. */
12973 {
12976 /* It is possible for the call above to return 0. This can occur
12977 when last_death points to I2 or I1 that we combined with.
12978 In that case make a new note.
12980 We must also check for the case where X is a hard register
12981 and NOTE is a death note for a range of hard registers
12982 including X. In that case, we must put REG_DEAD notes for
12983 the remaining registers in place of NOTE. */
12988 {
12997 }
12999 /* If we didn't find any note, or if we found a REG_DEAD note that
13000 covers only part of the given reg, and we have a multi-reg hard
13001 register, then to be safe we must check for REG_DEAD notes
13002 for each register other than the first. They could have
13003 their own REG_DEAD notes lying around. */
13010 {
13017 else
13023 }
13026 {
13029 }
13030 else
13032 }
13035 }
13038 {
13043 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13044 that accesses one word of a multi-word item, some
13045 piece of everything register in the expression is used by
13046 this insn, so remove any old death. */
13047 /* ??? So why do we test for equality of the sizes? */
13056 {
13059 }
13061 /* If this is some other SUBREG, we know it replaces the entire
13062 value, so use that as the destination. */
13066 /* If this is a MEM, adjust deaths of anything used in the address.
13067 For a REG (the only other possibility), the entire value is
13068 being replaced so the old value is not used in this insn. */
13074 }
13083 {
13085 {
13090 }
13093 }
13094 }
13095 \f
13096 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13097 pattern of an insn. X must be a REG. */
13099 static int
13101 {
13105 {
13107 rtx target;
13114 else
13131 }
13139 }
13140 \f
13141 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13142 as appropriate. I3 and I2 are the insns resulting from the combination
13143 insns including FROM (I2 may be zero).
13145 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13146 not need REG_DEAD notes because they are being substituted for. This
13147 saves searching in the most common cases.
13149 Each note in the list is either ignored or placed on some insns, depending
13150 on the type of note. */
13152 static void
13155 {
13157 rtx tem;
13160 {
13165 {
13168 /* Doesn't matter much where we put this, as long as it's somewhere.
13169 It is preferable to keep these notes on branches, which is most
13170 likely to be i3. */
13177 else
13178 {
13181 }
13185 /* These notes must remain with the call or trapping instruction. */
13190 else
13191 {
13197 /* ??? Otherwise assume we've combined things such that we
13198 can now prove that the instructions can't trap. Drop the
13199 note in this case. */
13200 }
13204 /* ??? How to distribute between i3-i1. Assume i3 contains the
13205 entire adjustment. Assert i3 contains at least some adjust. */
13207 {
13209 /* fixup_args_size_notes looks at REG_NORETURN note,
13210 so ensure the note is placed there first. */
13212 {
13216 {
13222 }
13223 }
13225 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13226 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13229 && !ACCUMULATE_OUTGOING_ARGS
13231 }
13237 /* These notes must remain with the call. It should not be
13238 possible for both I2 and I3 to be a call. */
13241 else
13242 {
13245 }
13249 /* Any clobbers for i3 may still exist, and so we must process
13250 REG_UNUSED notes from that insn.
13252 Any clobbers from i2 or i1 can only exist if they were added by
13253 recog_for_combine. In that case, recog_for_combine created the
13254 necessary REG_UNUSED notes. Trying to keep any original
13255 REG_UNUSED notes from these insns can cause incorrect output
13256 if it is for the same register as the original i3 dest.
13257 In that case, we will notice that the register is set in i3,
13258 and then add a REG_UNUSED note for the destination of i3, which
13259 is wrong. However, it is possible to have REG_UNUSED notes from
13260 i2 or i1 for register which were both used and clobbered, so
13261 we keep notes from i2 or i1 if they will turn into REG_DEAD
13262 notes. */
13264 /* If this register is set or clobbered in I3, put the note there
13265 unless there is one already. */
13267 {
13275 }
13276 /* Otherwise, if this register is used by I3, then this register
13277 now dies here, so we must put a REG_DEAD note here unless there
13278 is one already. */
13284 {
13287 }
13293 /* These notes say something about results of an insn. We can
13294 only support them if they used to be on I3 in which case they
13295 remain on I3. Otherwise they are ignored.
13297 If the note refers to an expression that is not a constant, we
13298 must also ignore the note since we cannot tell whether the
13299 equivalence is still true. It might be possible to do
13300 slightly better than this (we only have a problem if I2DEST
13301 or I1DEST is present in the expression), but it doesn't
13302 seem worth the trouble. */
13310 /* These notes say something about how a register is used. They must
13311 be present on any use of the register in I2 or I3. */
13316 {
13319 else
13321 }
13326 /* This can show up in several ways -- either directly in the
13327 pattern, or hidden off in the constant pool with (or without?)
13328 a REG_EQUAL note. */
13329 /* ??? Ignore the without-reg_equal-note problem for now. */
13341 {
13344 else
13346 }
13348 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13349 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13350 there. */
13355 {
13362 }
13368 {
13376 }
13380 /* This note says something about the value of a register prior
13381 to the execution of an insn. It is too much trouble to see
13382 if the note is still correct in all situations. It is better
13383 to simply delete it. */
13387 /* If we replaced the right hand side of FROM_INSN with a
13388 REG_EQUAL note, the original use of the dying register
13389 will not have been combined into I3 and I2. In such cases,
13390 FROM_INSN is guaranteed to be the first of the combined
13391 instructions, so we simply need to search back before
13392 FROM_INSN for the previous use or set of this register,
13393 then alter the notes there appropriately.
13395 If the register is used as an input in I3, it dies there.
13396 Similarly for I2, if it is nonzero and adjacent to I3.
13398 If the register is not used as an input in either I3 or I2
13399 and it is not one of the registers we were supposed to eliminate,
13400 there are two possibilities. We might have a non-adjacent I2
13401 or we might have somehow eliminated an additional register
13402 from a computation. For example, we might have had A & B where
13403 we discover that B will always be zero. In this case we will
13404 eliminate the reference to A.
13406 In both cases, we must search to see if we can find a previous
13407 use of A and put the death note there. */
13413 else
13414 {
13425 && !(i2mod
13427 i2mod_old_rhs)))
13432 }
13435 {
13439 {
13441 {
13445 }
13447 /* If the register is being set at TEM, see if that is all
13448 TEM is doing. If so, delete TEM. Otherwise, make this
13449 into a REG_UNUSED note instead. Don't delete sets to
13450 global register vars. */
13454 {
13457 #ifdef HAVE_cc0
13459 #endif
13467 ;
13469 /* Verify that it was the set, and not a clobber that
13470 modified the register.
13472 CC0 targets must be careful to maintain setter/user
13473 pairs. If we cannot delete the setter due to side
13474 effects, mark the user with an UNUSED note instead
13475 of deleting it. */
13479 #ifdef HAVE_cc0
13483 #endif
13484 )
13485 {
13486 /* Move the notes and links of TEM elsewhere.
13487 This might delete other dead insns recursively.
13488 First set the pattern to something that won't use
13489 any register. */
13503 #ifdef HAVE_cc0
13504 /* Delete the setter too. */
13506 {
13519 }
13520 #endif
13521 }
13522 else
13523 {
13526 /* If there isn't already a REG_UNUSED note, put one
13527 here. Do not place a REG_DEAD note, even if
13528 the register is also used here; that would not
13529 match the algorithm used in lifetime analysis
13530 and can cause the consistency check in the
13531 scheduler to fail. */
13536 }
13537 }
13541 {
13544 /* If we are doing a 3->2 combination, and we have a
13545 register which formerly died in i3 and was not used
13546 by i2, which now no longer dies in i3 and is used in
13547 i2 but does not die in i2, and place is between i2
13548 and i3, then we may need to move a link from place to
13549 i2. */
13551 && from_insn
13554 {
13558 }
13560 }
13564 }
13566 }
13568 /* If the register is set or already dead at PLACE, we needn't do
13569 anything with this note if it is still a REG_DEAD note.
13570 We check here if it is set at all, not if is it totally replaced,
13571 which is what `dead_or_set_p' checks, so also check for it being
13572 set partially. */
13575 {
13581 {
13582 /* Unless the register previously died in PLACE, clear
13583 last_death. [I no longer understand why this is
13584 being done.] */
13588 }
13589 else
13592 /* If this is a death note for a hard reg that is occupying
13593 multiple registers, ensure that we are still using all
13594 parts of the object. If we find a piece of the object
13595 that is unused, we must arrange for an appropriate REG_DEAD
13596 note to be added for it. However, we can't just emit a USE
13597 and tag the note to it, since the register might actually
13598 be dead; so we recourse, and the recursive call then finds
13599 the previous insn that used this register. */
13603 {
13612 {
13615 }
13618 {
13619 /* Put only REG_DEAD notes for pieces that are
13620 not already dead or set. */
13624 {
13631 {
13633 NULL_RTX);
13637 NULL_RTX);
13638 }
13644 {
13646 {
13650 }
13654 {
13657 }
13658 }
13659 }
13662 }
13663 }
13664 }
13668 /* Any other notes should not be present at this point in the
13669 compilation. */
13671 }
13674 {
13677 }
13681 }
13682 }
13683 \f
13684 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13685 I3, I2, and I1 to new locations. This is also called to add a link
13686 pointing at I3 when I3's destination is changed. */
13688 static void
13690 {
13694 {
13696 rtx insn;
13701 /* If the insn that this link points to is a NOTE or isn't a single
13702 set, ignore it. In the latter case, it isn't clear what we
13703 can do other than ignore the link, since we can't tell which
13704 register it was for. Such links wouldn't be used by combine
13705 anyway.
13707 It is not possible for the destination of the target of the link to
13708 have been changed by combine. The only potential of this is if we
13709 replace I3, I2, and I1 by I3 and I2. But in that case the
13710 destination of I2 also remains unchanged. */
13721 /* A LOG_LINK is defined as being placed on the first insn that uses
13722 a register and points to the insn that sets the register. Start
13723 searching at the next insn after the target of the link and stop
13724 when we reach a set of the register or the end of the basic block.
13726 Note that this correctly handles the link that used to point from
13727 I3 to I2. Also note that not much searching is typically done here
13728 since most links don't point very far away. */
13737 {
13741 }
13744 {
13747 }
13751 /* If we found a place to put the link, place it there unless there
13752 is already a link to the same insn as LINK at that point. */
13755 {
13763 {
13767 /* Set added_links_insn to the earliest insn we added a
13768 link to. */
13772 }
13773 }
13774 }
13775 }
13776 \f
13777 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13778 Check whether the expression pointer to by LOC is a register or
13779 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13780 Otherwise return zero. */
13782 static int
13784 {
13792 }
13794 /* Check for any register or memory mentioned in EQUIV that is not
13795 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13796 of EXPR where some registers may have been replaced by constants. */
13798 static bool
13800 {
13802 }
13803 \f
13804 DEBUG_FUNCTION void
13806 {
13807 fprintf
13809 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13811 }
13813 void
13815 {
13816 fprintf
13818 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13820 }
13821 \f
13822 static bool
13824 {
13826 }
13828 /* Try combining insns through substitution. */
13829 static unsigned int
13831 {
13840 rebuild_jump_labels_after_combine
13843 /* Combining insns may have turned an indirect jump into a
13844 direct jump. Rebuild the JUMP_LABEL fields of jumping
13845 instructions. */
13847 {
13852 }
13856 }
13861 {
13873 };
13876 {
13880 {}
13882 /* opt_pass methods: */
13890 rtl_opt_pass *
13892 {
13894 }