1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
40 #include "diagnostic-core.h"
44 #include "tree-pass.h"
48 static int reload_cse_noop_set_p (rtx
);
49 static bool reload_cse_simplify (rtx
, rtx
);
50 static void reload_cse_regs_1 (void);
51 static int reload_cse_simplify_set (rtx
, rtx
);
52 static int reload_cse_simplify_operands (rtx
, rtx
);
54 static void reload_combine (void);
55 static void reload_combine_note_use (rtx
*, rtx
, int, rtx
);
56 static void reload_combine_note_store (rtx
, const_rtx
, void *);
58 static bool reload_cse_move2add (rtx
);
59 static void move2add_note_store (rtx
, const_rtx
, void *);
61 /* Call cse / combine like post-reload optimization phases.
62 FIRST is the first instruction. */
65 reload_cse_regs (rtx first ATTRIBUTE_UNUSED
)
70 moves_converted
= reload_cse_move2add (first
);
71 if (flag_expensive_optimizations
)
79 /* See whether a single set SET is a noop. */
81 reload_cse_noop_set_p (rtx set
)
83 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
86 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
89 /* Try to simplify INSN. Return true if the CFG may have changed. */
91 reload_cse_simplify (rtx insn
, rtx testreg
)
93 rtx body
= PATTERN (insn
);
94 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
95 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
97 if (GET_CODE (body
) == SET
)
101 /* Simplify even if we may think it is a no-op.
102 We may think a memory load of a value smaller than WORD_SIZE
103 is redundant because we haven't taken into account possible
104 implicit extension. reload_cse_simplify_set() will bring
105 this out, so it's safer to simplify before we delete. */
106 count
+= reload_cse_simplify_set (body
, insn
);
108 if (!count
&& reload_cse_noop_set_p (body
))
110 rtx value
= SET_DEST (body
);
112 && ! REG_FUNCTION_VALUE_P (value
))
114 if (check_for_inc_dec (insn
))
115 delete_insn_and_edges (insn
);
116 /* We're done with this insn. */
121 apply_change_group ();
123 reload_cse_simplify_operands (insn
, testreg
);
125 else if (GET_CODE (body
) == PARALLEL
)
129 rtx value
= NULL_RTX
;
131 /* Registers mentioned in the clobber list for an asm cannot be reused
132 within the body of the asm. Invalidate those registers now so that
133 we don't try to substitute values for them. */
134 if (asm_noperands (body
) >= 0)
136 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
138 rtx part
= XVECEXP (body
, 0, i
);
139 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
140 cselib_invalidate_rtx (XEXP (part
, 0));
144 /* If every action in a PARALLEL is a noop, we can delete
145 the entire PARALLEL. */
146 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
148 rtx part
= XVECEXP (body
, 0, i
);
149 if (GET_CODE (part
) == SET
)
151 if (! reload_cse_noop_set_p (part
))
153 if (REG_P (SET_DEST (part
))
154 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
158 value
= SET_DEST (part
);
161 else if (GET_CODE (part
) != CLOBBER
)
167 if (check_for_inc_dec (insn
))
168 delete_insn_and_edges (insn
);
169 /* We're done with this insn. */
173 /* It's not a no-op, but we can try to simplify it. */
174 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
175 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
176 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
179 apply_change_group ();
181 reload_cse_simplify_operands (insn
, testreg
);
185 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
188 /* Do a very simple CSE pass over the hard registers.
190 This function detects no-op moves where we happened to assign two
191 different pseudo-registers to the same hard register, and then
192 copied one to the other. Reload will generate a useless
193 instruction copying a register to itself.
195 This function also detects cases where we load a value from memory
196 into two different registers, and (if memory is more expensive than
197 registers) changes it to simply copy the first register into the
200 Another optimization is performed that scans the operands of each
201 instruction to see whether the value is already available in a
202 hard register. It then replaces the operand with the hard register
203 if possible, much like an optional reload would. */
206 reload_cse_regs_1 (void)
208 bool cfg_changed
= false;
211 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
213 cselib_init (CSELIB_RECORD_MEMORY
);
214 init_alias_analysis ();
216 FOR_EACH_BB_FN (bb
, cfun
)
217 FOR_BB_INSNS (bb
, insn
)
220 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
222 cselib_process_insn (insn
);
226 end_alias_analysis ();
232 /* Try to simplify a single SET instruction. SET is the set pattern.
233 INSN is the instruction it came from.
234 This function only handles one case: if we set a register to a value
235 which is not a register, we try to find that value in some other register
236 and change the set into a register copy. */
239 reload_cse_simplify_set (rtx set
, rtx insn
)
247 struct elt_loc_list
*l
;
248 #ifdef LOAD_EXTEND_OP
249 enum rtx_code extend_op
= UNKNOWN
;
251 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
253 dreg
= true_regnum (SET_DEST (set
));
258 if (side_effects_p (src
) || true_regnum (src
) >= 0)
261 dclass
= REGNO_REG_CLASS (dreg
);
263 #ifdef LOAD_EXTEND_OP
264 /* When replacing a memory with a register, we need to honor assumptions
265 that combine made wrt the contents of sign bits. We'll do this by
266 generating an extend instruction instead of a reg->reg copy. Thus
267 the destination must be a register that we can widen. */
269 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
270 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
271 && !REG_P (SET_DEST (set
)))
275 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
279 /* If memory loads are cheaper than register copies, don't change them. */
281 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
282 else if (REG_P (src
))
283 old_cost
= register_move_cost (GET_MODE (src
),
284 REGNO_REG_CLASS (REGNO (src
)), dclass
);
286 old_cost
= set_src_cost (src
, speed
);
288 for (l
= val
->locs
; l
; l
= l
->next
)
290 rtx this_rtx
= l
->loc
;
293 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
295 #ifdef LOAD_EXTEND_OP
296 if (extend_op
!= UNKNOWN
)
298 HOST_WIDE_INT this_val
;
300 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
301 constants, such as SYMBOL_REF, cannot be extended. */
302 if (!CONST_INT_P (this_rtx
))
305 this_val
= INTVAL (this_rtx
);
309 this_val
&= GET_MODE_MASK (GET_MODE (src
));
312 /* ??? In theory we're already extended. */
313 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
318 this_rtx
= GEN_INT (this_val
);
321 this_cost
= set_src_cost (this_rtx
, speed
);
323 else if (REG_P (this_rtx
))
325 #ifdef LOAD_EXTEND_OP
326 if (extend_op
!= UNKNOWN
)
328 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
329 this_cost
= set_src_cost (this_rtx
, speed
);
333 this_cost
= register_move_cost (GET_MODE (this_rtx
),
334 REGNO_REG_CLASS (REGNO (this_rtx
)),
340 /* If equal costs, prefer registers over anything else. That
341 tends to lead to smaller instructions on some machines. */
342 if (this_cost
< old_cost
343 || (this_cost
== old_cost
345 && !REG_P (SET_SRC (set
))))
347 #ifdef LOAD_EXTEND_OP
348 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
349 && extend_op
!= UNKNOWN
350 #ifdef CANNOT_CHANGE_MODE_CLASS
351 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
353 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
357 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
358 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
359 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
363 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
364 old_cost
= this_cost
, did_change
= 1;
371 /* Try to replace operands in INSN with equivalent values that are already
372 in registers. This can be viewed as optional reloading.
374 For each non-register operand in the insn, see if any hard regs are
375 known to be equivalent to that operand. Record the alternatives which
376 can accept these hard registers. Among all alternatives, select the
377 ones which are better or equal to the one currently matching, where
378 "better" is in terms of '?' and '!' constraints. Among the remaining
379 alternatives, select the one which replaces most operands with
383 reload_cse_simplify_operands (rtx insn
, rtx testreg
)
387 /* For each operand, all registers that are equivalent to it. */
388 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
390 const char *constraints
[MAX_RECOG_OPERANDS
];
392 /* Vector recording how bad an alternative is. */
393 int *alternative_reject
;
394 /* Vector recording how many registers can be introduced by choosing
396 int *alternative_nregs
;
397 /* Array of vectors recording, for each operand and each alternative,
398 which hard register to substitute, or -1 if the operand should be
400 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
401 /* Array of alternatives, sorted in order of decreasing desirability. */
402 int *alternative_order
;
406 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
409 /* Figure out which alternative currently matches. */
410 if (! constrain_operands (1))
411 fatal_insn_not_found (insn
);
413 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
414 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
415 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
416 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
417 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
419 /* For each operand, find out which regs are equivalent. */
420 for (i
= 0; i
< recog_data
.n_operands
; i
++)
423 struct elt_loc_list
*l
;
426 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
428 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
429 right, so avoid the problem here. Likewise if we have a constant
430 and the insn pattern doesn't tell us the mode we need. */
431 if (LABEL_P (recog_data
.operand
[i
])
432 || (CONSTANT_P (recog_data
.operand
[i
])
433 && recog_data
.operand_mode
[i
] == VOIDmode
))
436 op
= recog_data
.operand
[i
];
437 #ifdef LOAD_EXTEND_OP
439 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
440 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
442 rtx set
= single_set (insn
);
444 /* We might have multiple sets, some of which do implicit
445 extension. Punt on this for now. */
448 /* If the destination is also a MEM or a STRICT_LOW_PART, no
450 Also, if there is an explicit extension, we don't have to
451 worry about an implicit one. */
452 else if (MEM_P (SET_DEST (set
))
453 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
454 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
455 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
456 ; /* Continue ordinary processing. */
457 #ifdef CANNOT_CHANGE_MODE_CLASS
458 /* If the register cannot change mode to word_mode, it follows that
459 it cannot have been used in word_mode. */
460 else if (REG_P (SET_DEST (set
))
461 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
463 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
464 ; /* Continue ordinary processing. */
466 /* If this is a straight load, make the extension explicit. */
467 else if (REG_P (SET_DEST (set
))
468 && recog_data
.n_operands
== 2
469 && SET_SRC (set
) == op
470 && SET_DEST (set
) == recog_data
.operand
[1-i
])
472 validate_change (insn
, recog_data
.operand_loc
[i
],
473 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
476 validate_change (insn
, recog_data
.operand_loc
[1-i
],
477 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
479 if (! apply_change_group ())
481 return reload_cse_simplify_operands (insn
, testreg
);
484 /* ??? There might be arithmetic operations with memory that are
485 safe to optimize, but is it worth the trouble? */
488 #endif /* LOAD_EXTEND_OP */
489 if (side_effects_p (op
))
491 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
495 for (l
= v
->locs
; l
; l
= l
->next
)
497 /* If postreload cse replace an expr in call insn with
498 frame pointer reg, we will end up getting call (...bp...),
499 this is wrong for frame pointer shrinkwrapping. */
500 && !(frame_pointer_partially_needed
502 && REGNO (l
->loc
) == HARD_FRAME_POINTER_REGNUM
))
503 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
506 for (i
= 0; i
< recog_data
.n_operands
; i
++)
508 enum machine_mode mode
;
512 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
513 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
514 op_alt_regno
[i
][j
] = -1;
516 p
= constraints
[i
] = recog_data
.constraints
[i
];
517 mode
= recog_data
.operand_mode
[i
];
519 /* Add the reject values for each alternative given by the constraints
528 alternative_reject
[j
] += 3;
530 alternative_reject
[j
] += 300;
533 /* We won't change operands which are already registers. We
534 also don't want to modify output operands. */
535 regno
= true_regnum (recog_data
.operand
[i
]);
537 || constraints
[i
][0] == '='
538 || constraints
[i
][0] == '+')
541 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
543 enum reg_class rclass
= NO_REGS
;
545 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
548 SET_REGNO_RAW (testreg
, regno
);
549 PUT_MODE (testreg
, mode
);
551 /* We found a register equal to this operand. Now look for all
552 alternatives that can accept this register and have not been
553 assigned a register they can use yet. */
562 case '=': case '+': case '?':
563 case '#': case '&': case '!':
565 case '0': case '1': case '2': case '3': case '4':
566 case '5': case '6': case '7': case '8': case '9':
567 case '<': case '>': case 'V': case 'o':
568 case 'E': case 'F': case 'G': case 'H':
569 case 's': case 'i': case 'n':
570 case 'I': case 'J': case 'K': case 'L':
571 case 'M': case 'N': case 'O': case 'P':
572 case 'p': case 'X': case TARGET_MEM_CONSTRAINT
:
573 /* These don't say anything we care about. */
577 rclass
= reg_class_subunion
[(int) rclass
][(int) GENERAL_REGS
];
582 = (reg_class_subunion
584 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
588 /* See if REGNO fits this alternative, and set it up as the
589 replacement register if we don't have one for this
590 alternative yet and the operand being replaced is not
591 a cheap CONST_INT. */
592 if (op_alt_regno
[i
][j
] == -1
593 && recog_data
.alternative_enabled_p
[j
]
594 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
595 && (!CONST_INT_P (recog_data
.operand
[i
])
596 || (set_src_cost (recog_data
.operand
[i
],
597 optimize_bb_for_speed_p
598 (BLOCK_FOR_INSN (insn
)))
599 > set_src_cost (testreg
,
600 optimize_bb_for_speed_p
601 (BLOCK_FOR_INSN (insn
))))))
603 alternative_nregs
[j
]++;
604 op_alt_regno
[i
][j
] = regno
;
610 p
+= CONSTRAINT_LEN (c
, p
);
618 /* Record all alternatives which are better or equal to the currently
619 matching one in the alternative_order array. */
620 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
621 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
622 alternative_order
[j
++] = i
;
623 recog_data
.n_alternatives
= j
;
625 /* Sort it. Given a small number of alternatives, a dumb algorithm
626 won't hurt too much. */
627 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
630 int best_reject
= alternative_reject
[alternative_order
[i
]];
631 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
634 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
636 int this_reject
= alternative_reject
[alternative_order
[j
]];
637 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
639 if (this_reject
< best_reject
640 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
643 best_reject
= this_reject
;
644 best_nregs
= this_nregs
;
648 tmp
= alternative_order
[best
];
649 alternative_order
[best
] = alternative_order
[i
];
650 alternative_order
[i
] = tmp
;
653 /* Substitute the operands as determined by op_alt_regno for the best
655 j
= alternative_order
[0];
657 for (i
= 0; i
< recog_data
.n_operands
; i
++)
659 enum machine_mode mode
= recog_data
.operand_mode
[i
];
660 if (op_alt_regno
[i
][j
] == -1)
663 validate_change (insn
, recog_data
.operand_loc
[i
],
664 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
667 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
669 int op
= recog_data
.dup_num
[i
];
670 enum machine_mode mode
= recog_data
.operand_mode
[op
];
672 if (op_alt_regno
[op
][j
] == -1)
675 validate_change (insn
, recog_data
.dup_loc
[i
],
676 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
679 return apply_change_group ();
682 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
684 This code might also be useful when reload gave up on reg+reg addressing
685 because of clashes between the return register and INDEX_REG_CLASS. */
687 /* The maximum number of uses of a register we can keep track of to
688 replace them with reg+reg addressing. */
689 #define RELOAD_COMBINE_MAX_USES 16
691 /* Describes a recorded use of a register. */
694 /* The insn where a register has been used. */
696 /* Points to the memory reference enclosing the use, if any, NULL_RTX
699 /* Location of the register within INSN. */
701 /* The reverse uid of the insn. */
705 /* If the register is used in some unknown fashion, USE_INDEX is negative.
706 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
707 indicates where it is first set or clobbered.
708 Otherwise, USE_INDEX is the index of the last encountered use of the
709 register (which is first among these we have seen since we scan backwards).
710 USE_RUID indicates the first encountered, i.e. last, of these uses.
711 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
712 with a constant offset; OFFSET contains this constant in that case.
713 STORE_RUID is always meaningful if we only want to use a value in a
714 register in a different place: it denotes the next insn in the insn
715 stream (i.e. the last encountered) that sets or clobbers the register.
716 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
719 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
725 bool all_offsets_match
;
726 } reg_state
[FIRST_PSEUDO_REGISTER
];
728 /* Reverse linear uid. This is increased in reload_combine while scanning
729 the instructions from last to first. It is used to set last_label_ruid
730 and the store_ruid / use_ruid fields in reg_state. */
731 static int reload_combine_ruid
;
733 /* The RUID of the last label we encountered in reload_combine. */
734 static int last_label_ruid
;
736 /* The RUID of the last jump we encountered in reload_combine. */
737 static int last_jump_ruid
;
739 /* The register numbers of the first and last index register. A value of
740 -1 in LAST_INDEX_REG indicates that we've previously computed these
741 values and found no suitable index registers. */
742 static int first_index_reg
= -1;
743 static int last_index_reg
;
745 #define LABEL_LIVE(LABEL) \
746 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
748 /* Subroutine of reload_combine_split_ruids, called to fix up a single
749 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
752 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
754 if (*pruid
> split_ruid
)
758 /* Called when we insert a new insn in a position we've already passed in
759 the scan. Examine all our state, increasing all ruids that are higher
760 than SPLIT_RUID by one in order to make room for a new insn. */
763 reload_combine_split_ruids (int split_ruid
)
767 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
768 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
769 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
771 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
773 int j
, idx
= reg_state
[i
].use_index
;
774 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
775 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
776 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
780 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
782 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
788 /* Called when we are about to rescan a previously encountered insn with
789 reload_combine_note_use after modifying some part of it. This clears all
790 information about uses in that particular insn. */
793 reload_combine_purge_insn_uses (rtx insn
)
797 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
799 int j
, k
, idx
= reg_state
[i
].use_index
;
802 j
= k
= RELOAD_COMBINE_MAX_USES
;
805 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
809 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
812 reg_state
[i
].use_index
= k
;
816 /* Called when we need to forget about all uses of REGNO after an insn
817 which is identified by RUID. */
820 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
822 int j
, k
, idx
= reg_state
[regno
].use_index
;
825 j
= k
= RELOAD_COMBINE_MAX_USES
;
828 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
832 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
835 reg_state
[regno
].use_index
= k
;
838 /* Find the use of REGNO with the ruid that is highest among those
839 lower than RUID_LIMIT, and return it if it is the only use of this
840 reg in the insn. Return NULL otherwise. */
842 static struct reg_use
*
843 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
845 int i
, best_ruid
= 0;
846 int use_idx
= reg_state
[regno
].use_index
;
847 struct reg_use
*retval
;
852 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
854 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
855 int this_ruid
= use
->ruid
;
856 if (this_ruid
>= ruid_limit
)
858 if (this_ruid
> best_ruid
)
860 best_ruid
= this_ruid
;
863 else if (this_ruid
== best_ruid
)
866 if (last_label_ruid
>= best_ruid
)
871 /* After we've moved an add insn, fix up any debug insns that occur
872 between the old location of the add and the new location. REG is
873 the destination register of the add insn; REPLACEMENT is the
874 SET_SRC of the add. FROM and TO specify the range in which we
875 should make this change on debug insns. */
878 fixup_debug_insns (rtx reg
, rtx replacement
, rtx from
, rtx to
)
881 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
885 if (!DEBUG_INSN_P (insn
))
888 t
= INSN_VAR_LOCATION_LOC (insn
);
889 t
= simplify_replace_rtx (t
, reg
, replacement
);
890 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
894 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
895 with SRC in the insn described by USE, taking costs into account. Return
896 true if we made the replacement. */
899 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
901 rtx use_insn
= use
->insn
;
902 rtx mem
= use
->containing_mem
;
903 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
907 addr_space_t as
= MEM_ADDR_SPACE (mem
);
908 rtx oldaddr
= XEXP (mem
, 0);
909 rtx newaddr
= NULL_RTX
;
910 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
913 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
914 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
916 XEXP (mem
, 0) = newaddr
;
917 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
918 XEXP (mem
, 0) = oldaddr
;
919 if (new_cost
<= old_cost
920 && validate_change (use_insn
,
921 &XEXP (mem
, 0), newaddr
, 0))
927 rtx new_set
= single_set (use_insn
);
929 && REG_P (SET_DEST (new_set
))
930 && GET_CODE (SET_SRC (new_set
)) == PLUS
931 && REG_P (XEXP (SET_SRC (new_set
), 0))
932 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
935 int old_cost
= set_src_cost (SET_SRC (new_set
), speed
);
937 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
938 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
940 if (set_src_cost (new_src
, speed
) <= old_cost
941 && validate_change (use_insn
, &SET_SRC (new_set
),
949 /* Called by reload_combine when scanning INSN. This function tries to detect
950 patterns where a constant is added to a register, and the result is used
952 Return true if no further processing is needed on INSN; false if it wasn't
953 recognized and should be handled normally. */
956 reload_combine_recognize_const_pattern (rtx insn
)
958 int from_ruid
= reload_combine_ruid
;
959 rtx set
, pat
, reg
, src
, addreg
;
963 rtx add_moved_after_insn
= NULL_RTX
;
964 int add_moved_after_ruid
= 0;
965 int clobbered_regno
= -1;
967 set
= single_set (insn
);
971 reg
= SET_DEST (set
);
974 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1
975 || GET_MODE (reg
) != Pmode
976 || reg
== stack_pointer_rtx
)
981 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
982 uses of REG1 inside an address, or inside another add insn. If
983 possible and profitable, merge the addition into subsequent
985 if (GET_CODE (src
) != PLUS
986 || !REG_P (XEXP (src
, 0))
987 || !CONSTANT_P (XEXP (src
, 1)))
990 addreg
= XEXP (src
, 0);
991 must_move_add
= rtx_equal_p (reg
, addreg
);
993 pat
= PATTERN (insn
);
994 if (must_move_add
&& set
!= pat
)
996 /* We have to be careful when moving the add; apart from the
997 single_set there may also be clobbers. Recognize one special
998 case, that of one clobber alongside the set (likely a clobber
999 of the CC register). */
1000 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
1001 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
1002 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
1003 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
1005 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
1010 use
= reload_combine_closest_single_use (regno
, from_ruid
);
1013 /* Start the search for the next use from here. */
1014 from_ruid
= use
->ruid
;
1016 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
1018 bool delete_add
= false;
1019 rtx use_insn
= use
->insn
;
1020 int use_ruid
= use
->ruid
;
1022 /* Avoid moving the add insn past a jump. */
1023 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
1026 /* If the add clobbers another hard reg in parallel, don't move
1027 it past a real set of this hard reg. */
1028 if (must_move_add
&& clobbered_regno
>= 0
1029 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
1033 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1034 if (must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
1038 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
1039 /* Avoid moving a use of ADDREG past a point where it is stored. */
1040 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1043 /* We also must not move the addition past an insn that sets
1044 the same register, unless we can combine two add insns. */
1045 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1047 if (use
->containing_mem
== NULL_RTX
)
1053 if (try_replace_in_use (use
, reg
, src
))
1055 reload_combine_purge_insn_uses (use_insn
);
1056 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1057 use_ruid
, NULL_RTX
);
1061 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1067 add_moved_after_insn
= use_insn
;
1068 add_moved_after_ruid
= use_ruid
;
1073 /* If we get here, we couldn't handle this use. */
1079 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1080 /* Process the add normally. */
1083 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1085 reorder_insns (insn
, insn
, add_moved_after_insn
);
1086 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1087 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1088 reload_combine_note_use (&PATTERN (insn
), insn
,
1089 add_moved_after_ruid
, NULL_RTX
);
1090 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1095 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1096 can handle and improve. Return true if no further processing is needed on
1097 INSN; false if it wasn't recognized and should be handled normally. */
1100 reload_combine_recognize_pattern (rtx insn
)
1105 set
= single_set (insn
);
1106 if (set
== NULL_RTX
)
1109 reg
= SET_DEST (set
);
1110 src
= SET_SRC (set
);
1112 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1)
1115 regno
= REGNO (reg
);
1117 /* Look for (set (REGX) (CONST_INT))
1118 (set (REGX) (PLUS (REGX) (REGY)))
1120 ... (MEM (REGX)) ...
1122 (set (REGZ) (CONST_INT))
1124 ... (MEM (PLUS (REGZ) (REGY)))... .
1126 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1127 and that we know all uses of REGX before it dies.
1128 Also, explicitly check that REGX != REGY; our life information
1129 does not yet show whether REGY changes in this insn. */
1131 if (GET_CODE (src
) == PLUS
1132 && reg_state
[regno
].all_offsets_match
1133 && last_index_reg
!= -1
1134 && REG_P (XEXP (src
, 1))
1135 && rtx_equal_p (XEXP (src
, 0), reg
)
1136 && !rtx_equal_p (XEXP (src
, 1), reg
)
1137 && reg_state
[regno
].use_index
>= 0
1138 && reg_state
[regno
].use_index
< RELOAD_COMBINE_MAX_USES
1139 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1141 rtx base
= XEXP (src
, 1);
1142 rtx prev
= prev_nonnote_nondebug_insn (insn
);
1143 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1144 rtx index_reg
= NULL_RTX
;
1145 rtx reg_sum
= NULL_RTX
;
1148 /* Now we need to set INDEX_REG to an index register (denoted as
1149 REGZ in the illustration above) and REG_SUM to the expression
1150 register+register that we want to use to substitute uses of REG
1151 (typically in MEMs) with. First check REG and BASE for being
1152 index registers; we can use them even if they are not dead. */
1153 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1154 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1162 /* Otherwise, look for a free index register. Since we have
1163 checked above that neither REG nor BASE are index registers,
1164 if we find anything at all, it will be different from these
1166 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1168 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1169 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1170 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1171 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1172 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1173 && !fixed_regs
[i
] && !global_regs
[i
]
1174 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1175 && targetm
.hard_regno_scratch_ok (i
))
1177 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1178 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1184 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1185 (REGY), i.e. BASE, is not clobbered before the last use we'll
1189 && CONST_INT_P (SET_SRC (prev_set
))
1190 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1191 && (reg_state
[REGNO (base
)].store_ruid
1192 <= reg_state
[regno
].use_ruid
))
1194 /* Change destination register and, if necessary, the constant
1195 value in PREV, the constant loading instruction. */
1196 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1197 if (reg_state
[regno
].offset
!= const0_rtx
)
1198 validate_change (prev
,
1199 &SET_SRC (prev_set
),
1200 GEN_INT (INTVAL (SET_SRC (prev_set
))
1201 + INTVAL (reg_state
[regno
].offset
)),
1204 /* Now for every use of REG that we have recorded, replace REG
1206 for (i
= reg_state
[regno
].use_index
;
1207 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1208 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1209 reg_state
[regno
].reg_use
[i
].usep
,
1210 /* Each change must have its own
1214 if (apply_change_group ())
1216 struct reg_use
*lowest_ruid
= NULL
;
1218 /* For every new use of REG_SUM, we have to record the use
1219 of BASE therein, i.e. operand 1. */
1220 for (i
= reg_state
[regno
].use_index
;
1221 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1223 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1224 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1225 use
->ruid
, use
->containing_mem
);
1226 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1230 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1232 /* Delete the reg-reg addition. */
1235 if (reg_state
[regno
].offset
!= const0_rtx
)
1236 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1238 remove_reg_equal_equiv_notes (prev
);
1240 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1249 reload_combine (void)
1254 int min_labelno
, n_labels
;
1255 HARD_REG_SET ever_live_at_start
, *label_live
;
1257 /* To avoid wasting too much time later searching for an index register,
1258 determine the minimum and maximum index register numbers. */
1259 if (INDEX_REG_CLASS
== NO_REGS
)
1260 last_index_reg
= -1;
1261 else if (first_index_reg
== -1 && last_index_reg
== 0)
1263 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1264 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1266 if (first_index_reg
== -1)
1267 first_index_reg
= r
;
1272 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1273 to -1 so we'll know to quit early the next time we get here. */
1274 if (first_index_reg
== -1)
1276 last_index_reg
= -1;
1281 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1282 information is a bit fuzzy immediately after reload, but it's
1283 still good enough to determine which registers are live at a jump
1285 min_labelno
= get_first_label_num ();
1286 n_labels
= max_label_num () - min_labelno
;
1287 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1288 CLEAR_HARD_REG_SET (ever_live_at_start
);
1290 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1292 insn
= BB_HEAD (bb
);
1296 bitmap live_in
= df_get_live_in (bb
);
1298 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1299 compute_use_by_pseudos (&live
, live_in
);
1300 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1301 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1305 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1306 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1307 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1309 reg_state
[r
].store_ruid
= 0;
1310 reg_state
[r
].real_store_ruid
= 0;
1312 reg_state
[r
].use_index
= -1;
1314 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1317 for (insn
= get_last_insn (); insn
; insn
= prev
)
1319 bool control_flow_insn
;
1322 prev
= PREV_INSN (insn
);
1324 /* We cannot do our optimization across labels. Invalidating all the use
1325 information we have would be costly, so we just note where the label
1326 is and then later disable any optimization that would cross it. */
1328 last_label_ruid
= reload_combine_ruid
;
1329 else if (BARRIER_P (insn
))
1331 /* Crossing a barrier resets all the use information. */
1332 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1333 if (! fixed_regs
[r
])
1334 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1336 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1337 /* Optimizations across insns being marked as volatile must be
1338 prevented. All the usage information is invalidated
1340 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1342 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1343 reg_state
[r
].use_index
= -1;
1345 if (! NONDEBUG_INSN_P (insn
))
1348 reload_combine_ruid
++;
1350 control_flow_insn
= control_flow_insn_p (insn
);
1351 if (control_flow_insn
)
1352 last_jump_ruid
= reload_combine_ruid
;
1354 if (reload_combine_recognize_const_pattern (insn
)
1355 || reload_combine_recognize_pattern (insn
))
1358 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1364 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1365 if (call_used_regs
[r
])
1367 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1368 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1371 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1372 link
= XEXP (link
, 1))
1374 rtx setuse
= XEXP (link
, 0);
1375 rtx usage_rtx
= XEXP (setuse
, 0);
1376 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1377 && REG_P (usage_rtx
))
1380 unsigned int start_reg
= REGNO (usage_rtx
);
1381 unsigned int num_regs
1382 = hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
1383 unsigned int end_reg
= start_reg
+ num_regs
- 1;
1384 for (i
= start_reg
; i
<= end_reg
; i
++)
1385 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1387 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1388 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1391 reg_state
[i
].use_index
= -1;
1396 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1398 /* Non-spill registers might be used at the call destination in
1399 some unknown fashion, so we have to mark the unknown use. */
1402 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1403 && JUMP_LABEL (insn
))
1405 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1408 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1411 live
= &ever_live_at_start
;
1414 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1415 if (TEST_HARD_REG_BIT (*live
, r
))
1416 reg_state
[r
].use_index
= -1;
1419 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1422 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1424 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1426 int regno
= REGNO (XEXP (note
, 0));
1427 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1428 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1429 reg_state
[regno
].use_index
= -1;
1437 /* Check if DST is a register or a subreg of a register; if it is,
1438 update store_ruid, real_store_ruid and use_index in the reg_state
1439 structure accordingly. Called via note_stores from reload_combine. */
1442 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1446 enum machine_mode mode
= GET_MODE (dst
);
1448 if (GET_CODE (dst
) == SUBREG
)
1450 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1451 GET_MODE (SUBREG_REG (dst
)),
1454 dst
= SUBREG_REG (dst
);
1457 /* Some targets do argument pushes without adding REG_INC notes. */
1461 dst
= XEXP (dst
, 0);
1462 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1463 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1464 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1466 regno
= REGNO (XEXP (dst
, 0));
1467 mode
= GET_MODE (XEXP (dst
, 0));
1468 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1470 /* We could probably do better, but for now mark the register
1471 as used in an unknown fashion and set/clobbered at this
1473 reg_state
[i
].use_index
= -1;
1474 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1475 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1484 regno
+= REGNO (dst
);
1486 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1487 careful with registers / register parts that are not full words.
1488 Similarly for ZERO_EXTRACT. */
1489 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1490 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1492 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1494 reg_state
[i
].use_index
= -1;
1495 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1496 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1501 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1503 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1504 if (GET_CODE (set
) == SET
)
1505 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1506 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1511 /* XP points to a piece of rtl that has to be checked for any uses of
1513 *XP is the pattern of INSN, or a part of it.
1514 Called from reload_combine, and recursively by itself. */
1516 reload_combine_note_use (rtx
*xp
, rtx insn
, int ruid
, rtx containing_mem
)
1519 enum rtx_code code
= x
->code
;
1522 rtx offset
= const0_rtx
; /* For the REG case below. */
1527 if (REG_P (SET_DEST (x
)))
1529 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1535 /* If this is the USE of a return value, we can't change it. */
1536 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1538 /* Mark the return register as used in an unknown fashion. */
1539 rtx reg
= XEXP (x
, 0);
1540 int regno
= REGNO (reg
);
1541 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1543 while (--nregs
>= 0)
1544 reg_state
[regno
+ nregs
].use_index
= -1;
1550 if (REG_P (SET_DEST (x
)))
1552 /* No spurious CLOBBERs of pseudo registers may remain. */
1553 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1559 /* We are interested in (plus (reg) (const_int)) . */
1560 if (!REG_P (XEXP (x
, 0))
1561 || !CONST_INT_P (XEXP (x
, 1)))
1563 offset
= XEXP (x
, 1);
1568 int regno
= REGNO (x
);
1572 /* No spurious USEs of pseudo registers may remain. */
1573 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1575 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1577 /* We can't substitute into multi-hard-reg uses. */
1580 while (--nregs
>= 0)
1581 reg_state
[regno
+ nregs
].use_index
= -1;
1585 /* We may be called to update uses in previously seen insns.
1586 Don't add uses beyond the last store we saw. */
1587 if (ruid
< reg_state
[regno
].store_ruid
)
1590 /* If this register is already used in some unknown fashion, we
1592 If we decrement the index from zero to -1, we can't store more
1593 uses, so this register becomes used in an unknown fashion. */
1594 use_index
= --reg_state
[regno
].use_index
;
1598 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1600 /* This is the first use of this register we have seen since we
1601 marked it as dead. */
1602 reg_state
[regno
].offset
= offset
;
1603 reg_state
[regno
].all_offsets_match
= true;
1604 reg_state
[regno
].use_ruid
= ruid
;
1608 if (reg_state
[regno
].use_ruid
> ruid
)
1609 reg_state
[regno
].use_ruid
= ruid
;
1611 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1612 reg_state
[regno
].all_offsets_match
= false;
1615 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1616 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1617 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1618 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1630 /* Recursively process the components of X. */
1631 fmt
= GET_RTX_FORMAT (code
);
1632 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1635 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1636 else if (fmt
[i
] == 'E')
1638 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1639 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1645 /* See if we can reduce the cost of a constant by replacing a move
1646 with an add. We track situations in which a register is set to a
1647 constant or to a register plus a constant. */
1648 /* We cannot do our optimization across labels. Invalidating all the
1649 information about register contents we have would be costly, so we
1650 use move2add_last_label_luid to note where the label is and then
1651 later disable any optimization that would cross it.
1652 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1653 are only valid if reg_set_luid[n] is greater than
1654 move2add_last_label_luid.
1655 For a set that established a new (potential) base register with
1656 non-constant value, we use move2add_luid from the place where the
1657 setting insn is encountered; registers based off that base then
1658 get the same reg_set_luid. Constants all get
1659 move2add_last_label_luid + 1 as their reg_set_luid. */
1660 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1662 /* If reg_base_reg[n] is negative, register n has been set to
1663 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1664 If reg_base_reg[n] is non-negative, register n has been set to the
1665 sum of reg_offset[n] and the value of register reg_base_reg[n]
1666 before reg_set_luid[n], calculated in mode reg_mode[n] .
1667 For multi-hard-register registers, all but the first one are
1668 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1669 marks it as invalid. */
1670 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1671 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1672 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1673 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1675 /* move2add_luid is linearly increased while scanning the instructions
1676 from first to last. It is used to set reg_set_luid in
1677 reload_cse_move2add and move2add_note_store. */
1678 static int move2add_luid
;
1680 /* move2add_last_label_luid is set whenever a label is found. Labels
1681 invalidate all previously collected reg_offset data. */
1682 static int move2add_last_label_luid
;
1684 /* ??? We don't know how zero / sign extension is handled, hence we
1685 can't go from a narrower to a wider mode. */
1686 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1687 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1688 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1689 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1691 /* Record that REG is being set to a value with the mode of REG. */
1694 move2add_record_mode (rtx reg
)
1697 enum machine_mode mode
= GET_MODE (reg
);
1699 if (GET_CODE (reg
) == SUBREG
)
1701 regno
= subreg_regno (reg
);
1702 nregs
= subreg_nregs (reg
);
1704 else if (REG_P (reg
))
1706 regno
= REGNO (reg
);
1707 nregs
= hard_regno_nregs
[regno
][mode
];
1711 for (int i
= nregs
- 1; i
> 0; i
--)
1712 reg_mode
[regno
+ i
] = BLKmode
;
1713 reg_mode
[regno
] = mode
;
1716 /* Record that REG is being set to the sum of SYM and OFF. */
1719 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1721 int regno
= REGNO (reg
);
1723 move2add_record_mode (reg
);
1724 reg_set_luid
[regno
] = move2add_luid
;
1725 reg_base_reg
[regno
] = -1;
1726 reg_symbol_ref
[regno
] = sym
;
1727 reg_offset
[regno
] = INTVAL (off
);
1730 /* Check if REGNO contains a valid value in MODE. */
1733 move2add_valid_value_p (int regno
, enum machine_mode mode
)
1735 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1738 if (mode
!= reg_mode
[regno
])
1740 if (!MODES_OK_FOR_MOVE2ADD (mode
, reg_mode
[regno
]))
1742 /* The value loaded into regno in reg_mode[regno] is also valid in
1743 mode after truncation only if (REG:mode regno) is the lowpart of
1744 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1745 regno of the lowpart might be different. */
1746 int s_off
= subreg_lowpart_offset (mode
, reg_mode
[regno
]);
1747 s_off
= subreg_regno_offset (regno
, reg_mode
[regno
], s_off
, mode
);
1749 /* We could in principle adjust regno, check reg_mode[regno] to be
1750 BLKmode, and return s_off to the caller (vs. -1 for failure),
1751 but we currently have no callers that could make use of this
1756 for (int i
= hard_regno_nregs
[regno
][mode
] - 1; i
> 0; i
--)
1757 if (reg_mode
[regno
+ i
] != BLKmode
)
1762 /* This function is called with INSN that sets REG to (SYM + OFF),
1763 while REG is known to already have value (SYM + offset).
1764 This function tries to change INSN into an add instruction
1765 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1766 It also updates the information about REG's known value.
1767 Return true if we made a change. */
1770 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx insn
)
1772 rtx pat
= PATTERN (insn
);
1773 rtx src
= SET_SRC (pat
);
1774 int regno
= REGNO (reg
);
1775 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
],
1777 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1778 bool changed
= false;
1780 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1781 use (set (reg) (reg)) instead.
1782 We don't delete this insn, nor do we convert it into a
1783 note, to avoid losing register notes or the return
1784 value flag. jump2 already knows how to get rid of
1786 if (new_src
== const0_rtx
)
1788 /* If the constants are different, this is a
1789 truncation, that, if turned into (set (reg)
1790 (reg)), would be discarded. Maybe we should
1791 try a truncMN pattern? */
1792 if (INTVAL (off
) == reg_offset
[regno
])
1793 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1797 struct full_rtx_costs oldcst
, newcst
;
1798 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1800 get_full_set_rtx_cost (pat
, &oldcst
);
1801 SET_SRC (pat
) = tem
;
1802 get_full_set_rtx_cost (pat
, &newcst
);
1803 SET_SRC (pat
) = src
;
1805 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1806 && have_add2_insn (reg
, new_src
))
1807 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1808 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1810 enum machine_mode narrow_mode
;
1811 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1812 narrow_mode
!= VOIDmode
1813 && narrow_mode
!= GET_MODE (reg
);
1814 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1816 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1817 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1818 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1820 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1821 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1824 = gen_rtx_SET (VOIDmode
,
1825 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1828 changed
= validate_change (insn
, &PATTERN (insn
),
1836 move2add_record_sym_value (reg
, sym
, off
);
1841 /* This function is called with INSN that sets REG to (SYM + OFF),
1842 but REG doesn't have known value (SYM + offset). This function
1843 tries to find another register which is known to already have
1844 value (SYM + offset) and change INSN into an add instruction
1845 (set (REG) (plus (the found register) (OFF - offset))) if such
1846 a register is found. It also updates the information about
1848 Return true iff we made a change. */
1851 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx insn
)
1853 rtx pat
= PATTERN (insn
);
1854 rtx src
= SET_SRC (pat
);
1855 int regno
= REGNO (reg
);
1857 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1859 bool changed
= false;
1860 struct full_rtx_costs oldcst
, newcst
, mincst
;
1863 init_costs_to_max (&mincst
);
1864 get_full_set_rtx_cost (pat
, &oldcst
);
1866 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1867 SET_SRC (pat
) = plus_expr
;
1869 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1870 if (move2add_valid_value_p (i
, GET_MODE (reg
))
1871 && reg_base_reg
[i
] < 0
1872 && reg_symbol_ref
[i
] != NULL_RTX
1873 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1875 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1877 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1878 use (set (reg) (reg)) instead.
1879 We don't delete this insn, nor do we convert it into a
1880 note, to avoid losing register notes or the return
1881 value flag. jump2 already knows how to get rid of
1883 if (new_src
== const0_rtx
)
1885 init_costs_to_zero (&mincst
);
1891 XEXP (plus_expr
, 1) = new_src
;
1892 get_full_set_rtx_cost (pat
, &newcst
);
1894 if (costs_lt_p (&newcst
, &mincst
, speed
))
1901 SET_SRC (pat
) = src
;
1903 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1907 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1910 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1912 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1914 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1917 reg_set_luid
[regno
] = move2add_luid
;
1918 move2add_record_sym_value (reg
, sym
, off
);
1922 /* Convert move insns with constant inputs to additions if they are cheaper.
1923 Return true if any changes were made. */
1925 reload_cse_move2add (rtx first
)
1929 bool changed
= false;
1931 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1933 reg_set_luid
[i
] = 0;
1935 reg_base_reg
[i
] = 0;
1936 reg_symbol_ref
[i
] = NULL_RTX
;
1937 reg_mode
[i
] = VOIDmode
;
1940 move2add_last_label_luid
= 0;
1942 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1948 move2add_last_label_luid
= move2add_luid
;
1949 /* We're going to increment move2add_luid twice after a
1950 label, so that we can use move2add_last_label_luid + 1 as
1951 the luid for constants. */
1955 if (! INSN_P (insn
))
1957 pat
= PATTERN (insn
);
1958 /* For simplicity, we only perform this optimization on
1959 straightforward SETs. */
1960 if (GET_CODE (pat
) == SET
1961 && REG_P (SET_DEST (pat
)))
1963 rtx reg
= SET_DEST (pat
);
1964 int regno
= REGNO (reg
);
1965 rtx src
= SET_SRC (pat
);
1967 /* Check if we have valid information on the contents of this
1968 register in the mode of REG. */
1969 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
1970 && dbg_cnt (cse2_move2add
))
1972 /* Try to transform (set (REGX) (CONST_INT A))
1974 (set (REGX) (CONST_INT B))
1976 (set (REGX) (CONST_INT A))
1978 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1980 (set (REGX) (CONST_INT A))
1982 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1985 if (CONST_INT_P (src
)
1986 && reg_base_reg
[regno
] < 0
1987 && reg_symbol_ref
[regno
] == NULL_RTX
)
1989 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1993 /* Try to transform (set (REGX) (REGY))
1994 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1997 (set (REGX) (PLUS (REGX) (CONST_INT B)))
2000 (set (REGX) (PLUS (REGX) (CONST_INT A)))
2002 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
2003 else if (REG_P (src
)
2004 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
2005 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
2006 && move2add_valid_value_p (REGNO (src
), GET_MODE (reg
)))
2008 rtx next
= next_nonnote_nondebug_insn (insn
);
2011 set
= single_set (next
);
2013 && SET_DEST (set
) == reg
2014 && GET_CODE (SET_SRC (set
)) == PLUS
2015 && XEXP (SET_SRC (set
), 0) == reg
2016 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
2018 rtx src3
= XEXP (SET_SRC (set
), 1);
2019 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
2020 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
2021 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
2023 gen_int_mode (added_offset
2027 bool success
= false;
2028 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
2030 if (new_src
== const0_rtx
)
2031 /* See above why we create (set (reg) (reg)) here. */
2033 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2036 rtx old_src
= SET_SRC (set
);
2037 struct full_rtx_costs oldcst
, newcst
;
2038 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
2040 get_full_set_rtx_cost (set
, &oldcst
);
2041 SET_SRC (set
) = tem
;
2042 get_full_set_src_cost (tem
, &newcst
);
2043 SET_SRC (set
) = old_src
;
2044 costs_add_n_insns (&oldcst
, 1);
2046 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2047 && have_add2_insn (reg
, new_src
))
2049 rtx newpat
= gen_rtx_SET (VOIDmode
, reg
, tem
);
2051 = validate_change (next
, &PATTERN (next
),
2059 move2add_record_mode (reg
);
2061 = trunc_int_for_mode (added_offset
+ base_offset
,
2069 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2071 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2073 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2075 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2076 if ((GET_CODE (src
) == SYMBOL_REF
2077 || (GET_CODE (src
) == CONST
2078 && GET_CODE (XEXP (src
, 0)) == PLUS
2079 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2080 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2081 && dbg_cnt (cse2_move2add
))
2085 if (GET_CODE (src
) == SYMBOL_REF
)
2092 sym
= XEXP (XEXP (src
, 0), 0);
2093 off
= XEXP (XEXP (src
, 0), 1);
2096 /* If the reg already contains the value which is sum of
2097 sym and some constant value, we can use an add2 insn. */
2098 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
2099 && reg_base_reg
[regno
] < 0
2100 && reg_symbol_ref
[regno
] != NULL_RTX
2101 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2102 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
2104 /* Otherwise, we have to find a register whose value is sum
2105 of sym and some constant value. */
2107 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
2113 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2115 if (REG_NOTE_KIND (note
) == REG_INC
2116 && REG_P (XEXP (note
, 0)))
2118 /* Reset the information about this register. */
2119 int regno
= REGNO (XEXP (note
, 0));
2120 if (regno
< FIRST_PSEUDO_REGISTER
)
2122 move2add_record_mode (XEXP (note
, 0));
2123 reg_mode
[regno
] = VOIDmode
;
2127 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2129 /* If INSN is a conditional branch, we try to extract an
2130 implicit set out of it. */
2131 if (any_condjump_p (insn
))
2133 rtx cnd
= fis_get_condition (insn
);
2136 && GET_CODE (cnd
) == NE
2137 && REG_P (XEXP (cnd
, 0))
2138 && !reg_set_p (XEXP (cnd
, 0), insn
)
2139 /* The following two checks, which are also in
2140 move2add_note_store, are intended to reduce the
2141 number of calls to gen_rtx_SET to avoid memory
2142 allocation if possible. */
2143 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2144 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
2145 && CONST_INT_P (XEXP (cnd
, 1)))
2148 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
2149 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2153 /* If this is a CALL_INSN, all call used registers are stored with
2157 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2159 if (call_used_regs
[i
])
2160 /* Reset the information about this register. */
2161 reg_mode
[i
] = VOIDmode
;
2168 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2170 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2171 Called from reload_cse_move2add via note_stores. */
2174 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2176 rtx insn
= (rtx
) data
;
2177 unsigned int regno
= 0;
2178 enum machine_mode mode
= GET_MODE (dst
);
2180 /* Some targets do argument pushes without adding REG_INC notes. */
2184 dst
= XEXP (dst
, 0);
2185 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2186 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2187 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2191 if (GET_CODE (dst
) == SUBREG
)
2192 regno
= subreg_regno (dst
);
2193 else if (REG_P (dst
))
2194 regno
= REGNO (dst
);
2198 if (SCALAR_INT_MODE_P (mode
)
2199 && GET_CODE (set
) == SET
)
2201 rtx note
, sym
= NULL_RTX
;
2204 note
= find_reg_equal_equiv_note (insn
);
2205 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2207 sym
= XEXP (note
, 0);
2210 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2211 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2212 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2213 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2215 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2216 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2219 if (sym
!= NULL_RTX
)
2221 move2add_record_sym_value (dst
, sym
, off
);
2226 if (SCALAR_INT_MODE_P (mode
)
2227 && GET_CODE (set
) == SET
2228 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2229 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2231 rtx src
= SET_SRC (set
);
2233 unsigned HOST_WIDE_INT offset
;
2236 switch (GET_CODE (src
))
2239 if (REG_P (XEXP (src
, 0)))
2241 base_reg
= XEXP (src
, 0);
2243 if (CONST_INT_P (XEXP (src
, 1)))
2244 offset
= UINTVAL (XEXP (src
, 1));
2245 else if (REG_P (XEXP (src
, 1))
2246 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2248 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2249 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2250 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2251 /* Maybe the first register is known to be a
2253 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2254 && reg_base_reg
[REGNO (base_reg
)] < 0
2255 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2257 offset
= reg_offset
[REGNO (base_reg
)];
2258 base_reg
= XEXP (src
, 1);
2277 /* Start tracking the register as a constant. */
2278 reg_base_reg
[regno
] = -1;
2279 reg_symbol_ref
[regno
] = NULL_RTX
;
2280 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2281 /* We assign the same luid to all registers set to constants. */
2282 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2283 move2add_record_mode (dst
);
2290 base_regno
= REGNO (base_reg
);
2291 /* If information about the base register is not valid, set it
2292 up as a new base register, pretending its value is known
2293 starting from the current insn. */
2294 if (!move2add_valid_value_p (base_regno
, mode
))
2296 reg_base_reg
[base_regno
] = base_regno
;
2297 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2298 reg_offset
[base_regno
] = 0;
2299 reg_set_luid
[base_regno
] = move2add_luid
;
2300 gcc_assert (GET_MODE (base_reg
) == mode
);
2301 move2add_record_mode (base_reg
);
2304 /* Copy base information from our base register. */
2305 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2306 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2307 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2309 /* Compute the sum of the offsets or constants. */
2311 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2313 move2add_record_mode (dst
);
2318 /* Invalidate the contents of the register. */
2319 move2add_record_mode (dst
);
2320 reg_mode
[regno
] = VOIDmode
;
2325 gate_handle_postreload (void)
2327 return (optimize
> 0 && reload_completed
);
2332 rest_of_handle_postreload (void)
2334 if (!dbg_cnt (postreload_cse
))
2337 /* Do a very simple CSE pass over just the hard registers. */
2338 reload_cse_regs (get_insns ());
2339 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2340 Remove any EH edges associated with them. */
2341 if (cfun
->can_throw_non_call_exceptions
2342 && purge_all_dead_edges ())
2350 const pass_data pass_data_postreload_cse
=
2352 RTL_PASS
, /* type */
2353 "postreload", /* name */
2354 OPTGROUP_NONE
, /* optinfo_flags */
2355 true, /* has_gate */
2356 true, /* has_execute */
2357 TV_RELOAD_CSE_REGS
, /* tv_id */
2358 0, /* properties_required */
2359 0, /* properties_provided */
2360 0, /* properties_destroyed */
2361 0, /* todo_flags_start */
2362 ( TODO_df_finish
| TODO_verify_rtl_sharing
| 0 ), /* todo_flags_finish */
2365 class pass_postreload_cse
: public rtl_opt_pass
2368 pass_postreload_cse (gcc::context
*ctxt
)
2369 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2372 /* opt_pass methods: */
2373 bool gate () { return gate_handle_postreload (); }
2374 unsigned int execute () { return rest_of_handle_postreload (); }
2376 }; // class pass_postreload_cse
2381 make_pass_postreload_cse (gcc::context
*ctxt
)
2383 return new pass_postreload_cse (ctxt
);