1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Changing spilled pseudos to stack memory or their equivalences;
41 o Allocation stack memory changes the address displacement and
42 new iteration is needed.
44 Here is block diagram of LRA passes:
46 ------------------------
47 --------------- | Undo inheritance for | ---------------
48 | Memory-memory | | spilled pseudos, | | New (and old) |
49 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
50 --------------- | the same hard regs, | | assignment |
51 Start | | and optional reloads | ---------------
52 | | ------------------------ ^
53 V | ---------------- |
54 ----------- V | Update virtual | |
55 | Remove |----> ------------>| register | |
56 | scratches | ^ | displacements | |
57 ----------- | ---------------- |
60 ---------------- No ------------ pseudos -------------------
61 | Spilled pseudo | change |Constraints:| or insns | Inheritance/split |
62 | to memory |<-------| RTL |--------->| transformations |
63 | substitution | | transfor- | | in EBB scope |
64 ---------------- | mations | -------------------
67 -------------------------
68 | Hard regs substitution, |
69 | devirtalization, and |------> Finish
70 | restoring scratches got |
72 -------------------------
74 To speed up the process:
75 o We process only insns affected by changes on previous
77 o We don't use DFA-infrastructure because it results in much slower
78 compiler speed than a special IR described below does;
79 o We use a special insn representation for quick access to insn
80 info which is always *synchronized* with the current RTL;
81 o Insn IR is minimized by memory. It is divided on three parts:
82 o one specific for each insn in RTL (only operand locations);
83 o one common for all insns in RTL with the same insn code
84 (different operand attributes from machine descriptions);
85 o one oriented for maintenance of live info (list of pseudos).
87 o all insns where the pseudo is referenced;
88 o live info (conflicting hard regs, live ranges, # of
90 o data used for assigning (preferred hard regs, costs etc).
92 This file contains LRA driver, LRA utility functions and data, and
93 code for dealing with scratches. */
97 #include "coretypes.h"
99 #include "hard-reg-set.h"
103 #include "insn-config.h"
104 #include "insn-codes.h"
107 #include "addresses.h"
110 #include "hash-set.h"
112 #include "machmode.h"
114 #include "function.h"
117 #include "dominance.h"
120 #include "cfgbuild.h"
121 #include "basic-block.h"
123 #include "tree-pass.h"
130 /* Hard registers currently not available for allocation. It can
131 changed after some hard registers become not eliminable. */
132 HARD_REG_SET lra_no_alloc_regs
;
134 static int get_new_reg_value (void);
135 static void expand_reg_info (void);
136 static void invalidate_insn_recog_data (int);
137 static int get_insn_freq (rtx_insn
*);
138 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
,
141 /* Expand all regno related info needed for LRA. */
143 expand_reg_data (int old
)
147 ira_expand_reg_equiv ();
148 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
149 lra_change_class (i
, ALL_REGS
, " Set", true);
152 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
153 or of VOIDmode, use MD_MODE for the new reg. Initialize its
154 register class to RCLASS. Print message about assigning class
155 RCLASS containing new register name TITLE unless it is NULL. Use
156 attributes of ORIGINAL if it is a register. The created register
157 will have unique held value. */
159 lra_create_new_reg_with_unique_value (machine_mode md_mode
, rtx original
,
160 enum reg_class rclass
, const char *title
)
165 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
167 lra_assert (mode
!= VOIDmode
);
168 new_reg
= gen_reg_rtx (mode
);
169 if (original
== NULL_RTX
|| ! REG_P (original
))
171 if (lra_dump_file
!= NULL
)
172 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
176 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
177 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
178 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
179 REG_POINTER (new_reg
) = REG_POINTER (original
);
180 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
181 if (lra_dump_file
!= NULL
)
182 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
183 REGNO (new_reg
), REGNO (original
));
185 if (lra_dump_file
!= NULL
)
188 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
189 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
190 title
, REGNO (new_reg
));
191 fprintf (lra_dump_file
, "\n");
193 expand_reg_data (max_reg_num ());
194 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
198 /* Analogous to the previous function but also inherits value of
201 lra_create_new_reg (machine_mode md_mode
, rtx original
,
202 enum reg_class rclass
, const char *title
)
207 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
208 if (original
!= NULL_RTX
&& REG_P (original
))
209 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
213 /* Set up for REGNO unique hold value. */
215 lra_set_regno_unique_value (int regno
)
217 lra_reg_info
[regno
].val
= get_new_reg_value ();
220 /* Invalidate INSN related info used by LRA. The info should never be
223 lra_invalidate_insn_data (rtx_insn
*insn
)
225 lra_invalidate_insn_regno_info (insn
);
226 invalidate_insn_recog_data (INSN_UID (insn
));
229 /* Mark INSN deleted and invalidate the insn related info used by
232 lra_set_insn_deleted (rtx_insn
*insn
)
234 lra_invalidate_insn_data (insn
);
235 SET_INSN_DELETED (insn
);
238 /* Delete an unneeded INSN and any previous insns who sole purpose is
239 loading data that is dead in INSN. */
241 lra_delete_dead_insn (rtx_insn
*insn
)
243 rtx_insn
*prev
= prev_real_insn (insn
);
246 /* If the previous insn sets a register that dies in our insn,
248 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
249 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
250 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
251 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
252 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
253 lra_delete_dead_insn (prev
);
255 lra_set_insn_deleted (insn
);
258 /* Emit insn x = y + z. Return NULL if we failed to do it.
259 Otherwise, return the insn. We don't use gen_add3_insn as it might
262 emit_add3_insn (rtx x
, rtx y
, rtx z
)
266 last
= get_last_insn ();
268 if (have_addptr3_insn (x
, y
, z
))
270 rtx insn
= gen_addptr3_insn (x
, y
, z
);
272 /* If the target provides an "addptr" pattern it hopefully does
273 for a reason. So falling back to the normal add would be
275 lra_assert (insn
!= NULL_RTX
);
280 rtx_insn
*insn
= emit_insn (gen_rtx_SET (VOIDmode
, x
,
281 gen_rtx_PLUS (GET_MODE (y
), y
, z
)));
282 if (recog_memoized (insn
) < 0)
284 delete_insns_since (last
);
290 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
293 emit_add2_insn (rtx x
, rtx y
)
297 insn
= emit_add3_insn (x
, x
, y
);
298 if (insn
== NULL_RTX
)
300 insn
= gen_add2_insn (x
, y
);
301 if (insn
!= NULL_RTX
)
307 /* Target checks operands through operand predicates to recognize an
308 insn. We should have a special precaution to generate add insns
309 which are frequent results of elimination.
311 Emit insns for x = y + z. X can be used to store intermediate
312 values and should be not in Y and Z when we use X to store an
313 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
314 + disp] where base and index are registers, disp and scale are
315 constants. Y should contain base if it is present, Z should
316 contain disp if any. index[*scale] can be part of Y or Z. */
318 lra_emit_add (rtx x
, rtx y
, rtx z
)
322 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
325 rtx add3_insn
= emit_add3_insn (x
, y
, z
);
326 old
= max_reg_num ();
327 if (add3_insn
!= NULL
)
331 disp
= a2
= NULL_RTX
;
332 if (GET_CODE (y
) == PLUS
)
346 index_scale
= scale
= NULL_RTX
;
347 if (GET_CODE (a1
) == MULT
)
350 index
= XEXP (a1
, 0);
351 scale
= XEXP (a1
, 1);
354 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
357 index
= XEXP (a2
, 0);
358 scale
= XEXP (a2
, 1);
366 if (! (REG_P (base
) || GET_CODE (base
) == SUBREG
)
367 || (index
!= NULL_RTX
368 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
369 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
370 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
372 /* Probably we have no 3 op add. Last chance is to use 2-op
373 add insn. To succeed, don't move Z to X as an address
374 segment always comes in Y. Otherwise, we might fail when
375 adding the address segment to register. */
376 lra_assert (x
!= y
&& x
!= z
);
377 emit_move_insn (x
, y
);
378 rtx insn
= emit_add2_insn (x
, z
);
379 lra_assert (insn
!= NULL_RTX
);
383 if (index_scale
== NULL_RTX
)
385 if (disp
== NULL_RTX
)
387 /* Generate x = index_scale; x = x + base. */
388 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
389 emit_move_insn (x
, index_scale
);
390 rtx insn
= emit_add2_insn (x
, base
);
391 lra_assert (insn
!= NULL_RTX
);
393 else if (scale
== NULL_RTX
)
395 /* Try x = base + disp. */
396 lra_assert (base
!= NULL_RTX
);
397 last
= get_last_insn ();
398 rtx_insn
*move_insn
=
399 emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
), base
, disp
));
400 if (recog_memoized (move_insn
) < 0)
402 delete_insns_since (last
);
403 /* Generate x = disp; x = x + base. */
404 emit_move_insn (x
, disp
);
405 rtx add2_insn
= emit_add2_insn (x
, base
);
406 lra_assert (add2_insn
!= NULL_RTX
);
408 /* Generate x = x + index. */
409 if (index
!= NULL_RTX
)
411 rtx insn
= emit_add2_insn (x
, index
);
412 lra_assert (insn
!= NULL_RTX
);
417 /* Try x = index_scale; x = x + disp; x = x + base. */
418 last
= get_last_insn ();
419 rtx_insn
*move_insn
= emit_move_insn (x
, index_scale
);
421 if (recog_memoized (move_insn
) >= 0)
423 rtx insn
= emit_add2_insn (x
, disp
);
424 if (insn
!= NULL_RTX
)
426 insn
= emit_add2_insn (x
, disp
);
427 if (insn
!= NULL_RTX
)
433 delete_insns_since (last
);
434 /* Generate x = disp; x = x + base; x = x + index_scale. */
435 emit_move_insn (x
, disp
);
436 rtx insn
= emit_add2_insn (x
, base
);
437 lra_assert (insn
!= NULL_RTX
);
438 insn
= emit_add2_insn (x
, index_scale
);
439 lra_assert (insn
!= NULL_RTX
);
444 /* Functions emit_... can create pseudos -- so expand the pseudo
446 if (old
!= max_reg_num ())
447 expand_reg_data (old
);
450 /* The number of emitted reload insns so far. */
451 int lra_curr_reload_num
;
453 /* Emit x := y, processing special case when y = u + v or y = u + v *
454 scale + w through emit_add (Y can be an address which is base +
455 index reg * scale + displacement in general case). X may be used
456 as intermediate result therefore it should be not in Y. */
458 lra_emit_move (rtx x
, rtx y
)
462 if (GET_CODE (y
) != PLUS
)
464 if (rtx_equal_p (x
, y
))
466 old
= max_reg_num ();
467 emit_move_insn (x
, y
);
469 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
470 /* Function emit_move can create pseudos -- so expand the pseudo
472 if (old
!= max_reg_num ())
473 expand_reg_data (old
);
476 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
479 /* Update insn operands which are duplication of operands whose
480 numbers are in array of NOPS (with end marker -1). The insn is
481 represented by its LRA internal representation ID. */
483 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
486 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
488 for (i
= 0; i
< static_id
->n_dups
; i
++)
489 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
490 if (static_id
->dup_num
[i
] == nop
)
491 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
496 /* This page contains code dealing with info about registers in the
499 /* Pools for insn reg info. */
500 static alloc_pool insn_reg_pool
;
502 /* Initiate pool for insn reg info. */
504 init_insn_regs (void)
507 = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg
), 100);
510 /* Create LRA insn related info about a reference to REGNO in INSN with
511 TYPE (in/out/inout), biggest reference mode MODE, flag that it is
512 reference through subreg (SUBREG_P), flag that is early clobbered
513 in the insn (EARLY_CLOBBER), and reference to the next insn reg
515 static struct lra_insn_reg
*
516 new_insn_reg (rtx_insn
*insn
, int regno
, enum op_type type
,
518 bool subreg_p
, bool early_clobber
, struct lra_insn_reg
*next
)
520 struct lra_insn_reg
*ir
;
522 ir
= (struct lra_insn_reg
*) pool_alloc (insn_reg_pool
);
524 ir
->biggest_mode
= mode
;
525 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (lra_reg_info
[regno
].biggest_mode
)
526 && NONDEBUG_INSN_P (insn
))
527 lra_reg_info
[regno
].biggest_mode
= mode
;
528 ir
->subreg_p
= subreg_p
;
529 ir
->early_clobber
= early_clobber
;
535 /* Free insn reg info IR. */
537 free_insn_reg (struct lra_insn_reg
*ir
)
539 pool_free (insn_reg_pool
, ir
);
542 /* Free insn reg info list IR. */
544 free_insn_regs (struct lra_insn_reg
*ir
)
546 struct lra_insn_reg
*next_ir
;
548 for (; ir
!= NULL
; ir
= next_ir
)
555 /* Finish pool for insn reg info. */
557 finish_insn_regs (void)
559 free_alloc_pool (insn_reg_pool
);
564 /* This page contains code dealing LRA insn info (or in other words
565 LRA internal insn representation). */
567 /* Map INSN_CODE -> the static insn data. This info is valid during
568 all translation unit. */
569 struct lra_static_insn_data
*insn_code_data
[LAST_INSN_CODE
];
571 /* Debug insns are represented as a special insn with one input
572 operand which is RTL expression in var_location. */
574 /* The following data are used as static insn operand data for all
575 debug insns. If structure lra_operand_data is changed, the
576 initializer should be changed too. */
577 static struct lra_operand_data debug_operand_data
=
579 NULL
, /* alternative */
580 VOIDmode
, /* We are not interesting in the operand mode. */
585 /* The following data are used as static insn data for all debug
586 insns. If structure lra_static_insn_data is changed, the
587 initializer should be changed too. */
588 static struct lra_static_insn_data debug_insn_static_data
=
591 0, /* Duplication operands #. */
592 -1, /* Commutative operand #. */
593 1, /* Operands #. There is only one operand which is debug RTL
595 0, /* Duplications #. */
596 0, /* Alternatives #. We are not interesting in alternatives
597 because we does not proceed debug_insns for reloads. */
598 NULL
, /* Hard registers referenced in machine description. */
599 NULL
/* Descriptions of operands in alternatives. */
602 /* Called once per compiler work to initialize some LRA data related
605 init_insn_code_data_once (void)
607 memset (insn_code_data
, 0, sizeof (insn_code_data
));
610 /* Called once per compiler work to finalize some LRA data related to
613 finish_insn_code_data_once (void)
617 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
619 if (insn_code_data
[i
] != NULL
)
620 free (insn_code_data
[i
]);
624 /* Return static insn data, allocate and setup if necessary. Although
625 dup_num is static data (it depends only on icode), to set it up we
626 need to extract insn first. So recog_data should be valid for
627 normal insn (ICODE >= 0) before the call. */
628 static struct lra_static_insn_data
*
629 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
631 struct lra_static_insn_data
*data
;
634 lra_assert (icode
< LAST_INSN_CODE
);
635 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
637 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
638 n_bytes
= sizeof (struct lra_static_insn_data
)
639 + sizeof (struct lra_operand_data
) * nop
640 + sizeof (int) * ndup
;
641 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
642 data
->operand_alternative
= NULL
;
643 data
->n_operands
= nop
;
645 data
->n_alternatives
= nalt
;
646 data
->operand
= ((struct lra_operand_data
*)
647 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
648 data
->dup_num
= ((int *) ((char *) data
->operand
649 + sizeof (struct lra_operand_data
) * nop
));
654 insn_code_data
[icode
] = data
;
655 for (i
= 0; i
< nop
; i
++)
657 data
->operand
[i
].constraint
658 = insn_data
[icode
].operand
[i
].constraint
;
659 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
660 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
661 data
->operand
[i
].is_operator
662 = insn_data
[icode
].operand
[i
].is_operator
;
663 data
->operand
[i
].type
664 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
665 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
667 data
->operand
[i
].is_address
= false;
669 for (i
= 0; i
< ndup
; i
++)
670 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
675 /* The current length of the following array. */
676 int lra_insn_recog_data_len
;
678 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
679 lra_insn_recog_data_t
*lra_insn_recog_data
;
681 /* Initialize LRA data about insns. */
683 init_insn_recog_data (void)
685 lra_insn_recog_data_len
= 0;
686 lra_insn_recog_data
= NULL
;
690 /* Expand, if necessary, LRA data about insns. */
692 check_and_expand_insn_recog_data (int index
)
696 if (lra_insn_recog_data_len
> index
)
698 old
= lra_insn_recog_data_len
;
699 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
700 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
702 lra_insn_recog_data_len
);
703 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
704 lra_insn_recog_data
[i
] = NULL
;
707 /* Finish LRA DATA about insn. */
709 free_insn_recog_data (lra_insn_recog_data_t data
)
711 if (data
->operand_loc
!= NULL
)
712 free (data
->operand_loc
);
713 if (data
->dup_loc
!= NULL
)
714 free (data
->dup_loc
);
715 if (data
->arg_hard_regs
!= NULL
)
716 free (data
->arg_hard_regs
);
717 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
719 if (data
->insn_static_data
->operand_alternative
!= NULL
)
720 free (const_cast <operand_alternative
*>
721 (data
->insn_static_data
->operand_alternative
));
722 free_insn_regs (data
->insn_static_data
->hard_regs
);
723 free (data
->insn_static_data
);
725 free_insn_regs (data
->regs
);
730 /* Finish LRA data about all insns. */
732 finish_insn_recog_data (void)
735 lra_insn_recog_data_t data
;
737 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
738 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
739 free_insn_recog_data (data
);
741 free (lra_insn_recog_data
);
744 /* Setup info about operands in alternatives of LRA DATA of insn. */
746 setup_operand_alternative (lra_insn_recog_data_t data
,
747 const operand_alternative
*op_alt
)
750 int icode
= data
->icode
;
751 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
753 static_data
->commutative
= -1;
754 nop
= static_data
->n_operands
;
755 nalt
= static_data
->n_alternatives
;
756 static_data
->operand_alternative
= op_alt
;
757 for (i
= 0; i
< nop
; i
++)
759 static_data
->operand
[i
].early_clobber
= false;
760 static_data
->operand
[i
].is_address
= false;
761 if (static_data
->operand
[i
].constraint
[0] == '%')
763 /* We currently only support one commutative pair of operands. */
764 if (static_data
->commutative
< 0)
765 static_data
->commutative
= i
;
767 lra_assert (icode
< 0); /* Asm */
768 /* The last operand should not be marked commutative. */
769 lra_assert (i
!= nop
- 1);
772 for (j
= 0; j
< nalt
; j
++)
773 for (i
= 0; i
< nop
; i
++, op_alt
++)
775 static_data
->operand
[i
].early_clobber
|= op_alt
->earlyclobber
;
776 static_data
->operand
[i
].is_address
|= op_alt
->is_address
;
780 /* Recursively process X and collect info about registers, which are
781 not the insn operands, in X with TYPE (in/out/inout) and flag that
782 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
783 to LIST. X is a part of insn given by DATA. Return the result
785 static struct lra_insn_reg
*
786 collect_non_operand_hard_regs (rtx
*x
, lra_insn_recog_data_t data
,
787 struct lra_insn_reg
*list
,
788 enum op_type type
, bool early_clobber
)
790 int i
, j
, regno
, last
;
793 struct lra_insn_reg
*curr
;
795 enum rtx_code code
= GET_CODE (op
);
796 const char *fmt
= GET_RTX_FORMAT (code
);
798 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
799 if (x
== data
->operand_loc
[i
])
800 /* It is an operand loc. Stop here. */
802 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
803 if (x
== data
->dup_loc
[i
])
804 /* It is a dup loc. Stop here. */
806 mode
= GET_MODE (op
);
810 op
= SUBREG_REG (op
);
811 code
= GET_CODE (op
);
812 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (op
)))
814 mode
= GET_MODE (op
);
815 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
821 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
823 for (last
= regno
+ hard_regno_nregs
[regno
][mode
];
826 if (! TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
827 || TEST_HARD_REG_BIT (eliminable_regset
, regno
))
829 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
830 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
831 && curr
->biggest_mode
== mode
)
833 if (curr
->type
!= type
)
834 curr
->type
= OP_INOUT
;
835 if (curr
->early_clobber
!= early_clobber
)
836 curr
->early_clobber
= true;
841 /* This is a new hard regno or the info can not be
842 integrated into the found structure. */
846 /* This clobber is to inform popping floating
848 && ! (FIRST_STACK_REG
<= regno
849 && regno
<= LAST_STACK_REG
));
851 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
852 early_clobber
, list
);
860 list
= collect_non_operand_hard_regs (&SET_DEST (op
), data
,
861 list
, OP_OUT
, false);
862 list
= collect_non_operand_hard_regs (&SET_SRC (op
), data
,
866 /* We treat clobber of non-operand hard registers as early
867 clobber (the behavior is expected from asm). */
868 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
871 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
872 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
873 list
, OP_INOUT
, false);
875 case PRE_MODIFY
: case POST_MODIFY
:
876 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
877 list
, OP_INOUT
, false);
878 list
= collect_non_operand_hard_regs (&XEXP (op
, 1), data
,
882 fmt
= GET_RTX_FORMAT (code
);
883 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
886 list
= collect_non_operand_hard_regs (&XEXP (op
, i
), data
,
888 else if (fmt
[i
] == 'E')
889 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
890 list
= collect_non_operand_hard_regs (&XVECEXP (op
, i
, j
), data
,
897 /* Set up and return info about INSN. Set up the info if it is not set up
899 lra_insn_recog_data_t
900 lra_set_insn_recog_data (rtx_insn
*insn
)
902 lra_insn_recog_data_t data
;
905 unsigned int uid
= INSN_UID (insn
);
906 struct lra_static_insn_data
*insn_static_data
;
908 check_and_expand_insn_recog_data (uid
);
909 if (DEBUG_INSN_P (insn
))
913 icode
= INSN_CODE (insn
);
915 /* It might be a new simple insn which is not recognized yet. */
916 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
918 data
= XNEW (struct lra_insn_recog_data
);
919 lra_insn_recog_data
[uid
] = data
;
921 data
->used_insn_alternative
= -1;
924 if (DEBUG_INSN_P (insn
))
926 data
->insn_static_data
= &debug_insn_static_data
;
927 data
->dup_loc
= NULL
;
928 data
->arg_hard_regs
= NULL
;
929 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
930 data
->operand_loc
= XNEWVEC (rtx
*, 1);
931 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
937 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
938 const char *constraints
[MAX_RECOG_OPERANDS
];
940 nop
= asm_noperands (PATTERN (insn
));
941 data
->operand_loc
= data
->dup_loc
= NULL
;
945 /* It is a special insn like USE or CLOBBER. We should
946 recognize any regular insn otherwise LRA can do nothing
948 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
949 || GET_CODE (PATTERN (insn
)) == CLOBBER
950 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
951 data
->insn_static_data
= insn_static_data
952 = get_static_insn_data (-1, 0, 0, nalt
);
956 /* expand_asm_operands makes sure there aren't too many
958 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
960 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
961 /* Now get the operand values and constraints out of the
963 decode_asm_operands (PATTERN (insn
), NULL
,
965 constraints
, operand_mode
, NULL
);
968 const char *p
= recog_data
.constraints
[0];
970 for (p
= constraints
[0]; *p
; p
++)
973 data
->insn_static_data
= insn_static_data
974 = get_static_insn_data (-1, nop
, 0, nalt
);
975 for (i
= 0; i
< nop
; i
++)
977 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
978 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
979 insn_static_data
->operand
[i
].strict_low
= false;
980 insn_static_data
->operand
[i
].is_operator
= false;
981 insn_static_data
->operand
[i
].is_address
= false;
984 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
985 insn_static_data
->operand
[i
].type
986 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
987 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
989 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
992 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
,
994 preprocess_constraints (nop
, nalt
, constraints
, op_alt
);
995 setup_operand_alternative (data
, op_alt
);
1000 insn_extract (insn
);
1001 data
->insn_static_data
= insn_static_data
1002 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1003 insn_data
[icode
].n_dups
,
1004 insn_data
[icode
].n_alternatives
);
1005 n
= insn_static_data
->n_operands
;
1010 locs
= XNEWVEC (rtx
*, n
);
1011 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1013 data
->operand_loc
= locs
;
1014 n
= insn_static_data
->n_dups
;
1019 locs
= XNEWVEC (rtx
*, n
);
1020 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1022 data
->dup_loc
= locs
;
1023 data
->preferred_alternatives
= get_preferred_alternatives (insn
);
1024 const operand_alternative
*op_alt
= preprocess_insn_constraints (icode
);
1025 if (!insn_static_data
->operand_alternative
)
1026 setup_operand_alternative (data
, op_alt
);
1027 else if (op_alt
!= insn_static_data
->operand_alternative
)
1028 insn_static_data
->operand_alternative
= op_alt
;
1030 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1031 insn_static_data
->hard_regs
= NULL
;
1033 insn_static_data
->hard_regs
1034 = collect_non_operand_hard_regs (&PATTERN (insn
), data
,
1035 NULL
, OP_IN
, false);
1036 data
->arg_hard_regs
= NULL
;
1040 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1043 /* Finding implicit hard register usage. We believe it will be
1044 not changed whatever transformations are used. Call insns
1045 are such example. */
1046 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1048 link
= XEXP (link
, 1))
1049 if (GET_CODE (XEXP (link
, 0)) == USE
1050 && REG_P (XEXP (XEXP (link
, 0), 0)))
1052 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1053 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1054 /* It is an argument register. */
1055 for (i
= (hard_regno_nregs
1056 [regno
][GET_MODE (XEXP (XEXP (link
, 0), 0))]) - 1;
1059 arg_hard_regs
[n_hard_regs
++] = regno
+ i
;
1061 if (n_hard_regs
!= 0)
1063 arg_hard_regs
[n_hard_regs
++] = -1;
1064 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1065 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1066 sizeof (int) * n_hard_regs
);
1069 /* Some output operand can be recognized only from the context not
1070 from the constraints which are empty in this case. Call insn may
1071 contain a hard register in set destination with empty constraint
1072 and extract_insn treats them as an input. */
1073 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1077 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1079 /* ??? Should we treat 'X' the same way. It looks to me that
1080 'X' means anything and empty constraint means we do not
1082 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1083 || operand
->is_operator
)
1085 pat
= PATTERN (insn
);
1086 if (GET_CODE (pat
) == SET
)
1088 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1091 else if (GET_CODE (pat
) == PARALLEL
)
1093 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1095 set
= XVECEXP (PATTERN (insn
), 0, j
);
1096 if (GET_CODE (set
) == SET
1097 && &SET_DEST (set
) == data
->operand_loc
[i
])
1105 operand
->type
= OP_OUT
;
1110 /* Return info about insn give by UID. The info should be already set
1112 static lra_insn_recog_data_t
1113 get_insn_recog_data_by_uid (int uid
)
1115 lra_insn_recog_data_t data
;
1117 data
= lra_insn_recog_data
[uid
];
1118 lra_assert (data
!= NULL
);
1122 /* Invalidate all info about insn given by its UID. */
1124 invalidate_insn_recog_data (int uid
)
1126 lra_insn_recog_data_t data
;
1128 data
= lra_insn_recog_data
[uid
];
1129 lra_assert (data
!= NULL
);
1130 free_insn_recog_data (data
);
1131 lra_insn_recog_data
[uid
] = NULL
;
1134 /* Update all the insn info about INSN. It is usually called when
1135 something in the insn was changed. Return the updated info. */
1136 lra_insn_recog_data_t
1137 lra_update_insn_recog_data (rtx_insn
*insn
)
1139 lra_insn_recog_data_t data
;
1141 unsigned int uid
= INSN_UID (insn
);
1142 struct lra_static_insn_data
*insn_static_data
;
1143 HOST_WIDE_INT sp_offset
= 0;
1145 check_and_expand_insn_recog_data (uid
);
1146 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1147 && data
->icode
!= INSN_CODE (insn
))
1149 sp_offset
= data
->sp_offset
;
1150 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1151 invalidate_insn_recog_data (uid
);
1156 data
= lra_get_insn_recog_data (insn
);
1157 /* Initiate or restore SP offset. */
1158 data
->sp_offset
= sp_offset
;
1161 insn_static_data
= data
->insn_static_data
;
1162 data
->used_insn_alternative
= -1;
1163 if (DEBUG_INSN_P (insn
))
1165 if (data
->icode
< 0)
1168 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1169 const char *constraints
[MAX_RECOG_OPERANDS
];
1171 nop
= asm_noperands (PATTERN (insn
));
1174 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1175 /* Now get the operand values and constraints out of the
1177 decode_asm_operands (PATTERN (insn
), NULL
,
1179 constraints
, operand_mode
, NULL
);
1180 #ifdef ENABLE_CHECKING
1184 for (i
= 0; i
< nop
; i
++)
1186 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1187 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1188 && ! insn_static_data
->operand
[i
].is_operator
);
1192 #ifdef ENABLE_CHECKING
1196 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1198 (insn_static_data
->operand
[i
].type
1199 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1200 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1207 insn_extract (insn
);
1208 n
= insn_static_data
->n_operands
;
1210 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1211 n
= insn_static_data
->n_dups
;
1213 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1214 lra_assert (check_bool_attrs (insn
));
1219 /* Set up that INSN is using alternative ALT now. */
1221 lra_set_used_insn_alternative (rtx_insn
*insn
, int alt
)
1223 lra_insn_recog_data_t data
;
1225 data
= lra_get_insn_recog_data (insn
);
1226 data
->used_insn_alternative
= alt
;
1229 /* Set up that insn with UID is using alternative ALT now. The insn
1230 info should be already set up. */
1232 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1234 lra_insn_recog_data_t data
;
1236 check_and_expand_insn_recog_data (uid
);
1237 data
= lra_insn_recog_data
[uid
];
1238 lra_assert (data
!= NULL
);
1239 data
->used_insn_alternative
= alt
;
1244 /* This page contains code dealing with common register info and
1247 /* The size of the following array. */
1248 static int reg_info_size
;
1249 /* Common info about each register. */
1250 struct lra_reg
*lra_reg_info
;
1252 /* Last register value. */
1253 static int last_reg_value
;
1255 /* Return new register value. */
1257 get_new_reg_value (void)
1259 return ++last_reg_value
;
1262 /* Pools for copies. */
1263 static alloc_pool copy_pool
;
1265 /* Vec referring to pseudo copies. */
1266 static vec
<lra_copy_t
> copy_vec
;
1268 /* Initialize I-th element of lra_reg_info. */
1270 initialize_lra_reg_info_element (int i
)
1272 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1274 lra_reg_info
[i
].no_stack_p
= false;
1276 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1277 CLEAR_HARD_REG_SET (lra_reg_info
[i
].actual_call_used_reg_set
);
1278 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1279 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1280 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1281 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1282 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1283 lra_reg_info
[i
].live_ranges
= NULL
;
1284 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1285 lra_reg_info
[i
].last_reload
= 0;
1286 lra_reg_info
[i
].restore_regno
= -1;
1287 lra_reg_info
[i
].val
= get_new_reg_value ();
1288 lra_reg_info
[i
].offset
= 0;
1289 lra_reg_info
[i
].copies
= NULL
;
1292 /* Initialize common reg info and copies. */
1294 init_reg_info (void)
1299 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1300 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1301 for (i
= 0; i
< reg_info_size
; i
++)
1302 initialize_lra_reg_info_element (i
);
1304 = create_alloc_pool ("lra copies", sizeof (struct lra_copy
), 100);
1305 copy_vec
.create (100);
1309 /* Finish common reg info and copies. */
1311 finish_reg_info (void)
1315 for (i
= 0; i
< reg_info_size
; i
++)
1316 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1317 free (lra_reg_info
);
1319 free_alloc_pool (copy_pool
);
1320 copy_vec
.release ();
1323 /* Expand common reg info if it is necessary. */
1325 expand_reg_info (void)
1327 int i
, old
= reg_info_size
;
1329 if (reg_info_size
> max_reg_num ())
1331 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1332 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1333 for (i
= old
; i
< reg_info_size
; i
++)
1334 initialize_lra_reg_info_element (i
);
1337 /* Free all copies. */
1339 lra_free_copies (void)
1343 while (copy_vec
.length () != 0)
1345 cp
= copy_vec
.pop ();
1346 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1347 pool_free (copy_pool
, cp
);
1351 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1352 frequency is FREQ. */
1354 lra_create_copy (int regno1
, int regno2
, int freq
)
1359 lra_assert (regno1
!= regno2
);
1360 regno1_dest_p
= true;
1361 if (regno1
> regno2
)
1365 regno1_dest_p
= false;
1369 cp
= (lra_copy_t
) pool_alloc (copy_pool
);
1370 copy_vec
.safe_push (cp
);
1371 cp
->regno1_dest_p
= regno1_dest_p
;
1373 cp
->regno1
= regno1
;
1374 cp
->regno2
= regno2
;
1375 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1376 lra_reg_info
[regno1
].copies
= cp
;
1377 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1378 lra_reg_info
[regno2
].copies
= cp
;
1379 if (lra_dump_file
!= NULL
)
1380 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1381 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1384 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1387 lra_get_copy (int n
)
1389 if (n
>= (int) copy_vec
.length ())
1396 /* This page contains code dealing with info about registers in
1399 /* Process X of insn UID recursively and add info (operand type is
1400 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1401 about registers in X to the insn DATA. */
1403 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
, int uid
,
1404 enum op_type type
, bool early_clobber
)
1411 struct lra_insn_reg
*curr
;
1413 code
= GET_CODE (x
);
1414 mode
= GET_MODE (x
);
1416 if (GET_CODE (x
) == SUBREG
)
1419 code
= GET_CODE (x
);
1420 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
)))
1422 mode
= GET_MODE (x
);
1423 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
1430 if (regno
< FIRST_PSEUDO_REGISTER
1431 && TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
1432 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
1435 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, uid
))
1437 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1438 early_clobber
, data
->regs
);
1443 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1444 if (curr
->regno
== regno
)
1446 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1447 /* The info can not be integrated into the found
1449 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1450 subreg_p
, early_clobber
,
1454 if (curr
->type
!= type
)
1455 curr
->type
= OP_INOUT
;
1456 if (curr
->early_clobber
!= early_clobber
)
1457 curr
->early_clobber
= true;
1468 add_regs_to_insn_regno_info (data
, SET_DEST (x
), uid
, OP_OUT
, false);
1469 add_regs_to_insn_regno_info (data
, SET_SRC (x
), uid
, OP_IN
, false);
1472 /* We treat clobber of non-operand hard registers as early
1473 clobber (the behavior is expected from asm). */
1474 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_OUT
, true);
1476 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1477 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1479 case PRE_MODIFY
: case POST_MODIFY
:
1480 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1481 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), uid
, OP_IN
, false);
1484 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1485 /* Some targets place small structures in registers for return
1486 values of functions, and those registers are wrapped in
1487 PARALLEL that we may see as the destination of a SET. Here
1490 (call_insn 13 12 14 2 (set (parallel:BLK [
1491 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1493 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1494 (const_int 8 [0x8]))
1496 (call (mem:QI (symbol_ref:DI (... */
1498 fmt
= GET_RTX_FORMAT (code
);
1499 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1502 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), uid
, type
, false);
1503 else if (fmt
[i
] == 'E')
1505 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1506 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), uid
,
1513 /* Return execution frequency of INSN. */
1515 get_insn_freq (rtx_insn
*insn
)
1517 basic_block bb
= BLOCK_FOR_INSN (insn
);
1519 gcc_checking_assert (bb
!= NULL
);
1520 return REG_FREQ_FROM_BB (bb
);
1523 /* Invalidate all reg info of INSN with DATA and execution frequency
1524 FREQ. Update common info about the invalidated registers. */
1526 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx_insn
*insn
,
1532 struct lra_insn_reg
*ir
, *next_ir
;
1534 uid
= INSN_UID (insn
);
1535 debug_p
= DEBUG_INSN_P (insn
);
1536 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1541 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1542 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1544 lra_reg_info
[i
].nrefs
--;
1545 lra_reg_info
[i
].freq
-= freq
;
1546 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1552 /* Invalidate all reg info of INSN. Update common info about the
1553 invalidated registers. */
1555 lra_invalidate_insn_regno_info (rtx_insn
*insn
)
1557 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1558 get_insn_freq (insn
));
1561 /* Update common reg info from reg info of insn given by its DATA and
1562 execution frequency FREQ. */
1564 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1567 struct lra_insn_reg
*ir
;
1569 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1570 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1572 lra_reg_info
[i
].nrefs
++;
1573 lra_reg_info
[i
].freq
+= freq
;
1577 /* Set up insn reg info of INSN. Update common reg info from reg info
1580 lra_update_insn_regno_info (rtx_insn
*insn
)
1583 lra_insn_recog_data_t data
;
1584 struct lra_static_insn_data
*static_data
;
1587 if (! INSN_P (insn
))
1589 data
= lra_get_insn_recog_data (insn
);
1590 static_data
= data
->insn_static_data
;
1591 freq
= get_insn_freq (insn
);
1592 invalidate_insn_data_regno_info (data
, insn
, freq
);
1593 uid
= INSN_UID (insn
);
1594 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1595 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], uid
,
1596 static_data
->operand
[i
].type
,
1597 static_data
->operand
[i
].early_clobber
);
1598 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1599 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), uid
,
1600 code
== USE
? OP_IN
: OP_OUT
, false);
1601 if (NONDEBUG_INSN_P (insn
))
1602 setup_insn_reg_info (data
, freq
);
1605 /* Return reg info of insn given by it UID. */
1606 struct lra_insn_reg
*
1607 lra_get_insn_regs (int uid
)
1609 lra_insn_recog_data_t data
;
1611 data
= get_insn_recog_data_by_uid (uid
);
1617 /* This page contains code dealing with stack of the insns which
1618 should be processed by the next constraint pass. */
1620 /* Bitmap used to put an insn on the stack only in one exemplar. */
1621 static sbitmap lra_constraint_insn_stack_bitmap
;
1623 /* The stack itself. */
1624 vec
<rtx_insn
*> lra_constraint_insn_stack
;
1626 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1627 info for INSN, otherwise only update it if INSN is not already on the
1630 lra_push_insn_1 (rtx_insn
*insn
, bool always_update
)
1632 unsigned int uid
= INSN_UID (insn
);
1634 lra_update_insn_regno_info (insn
);
1635 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1636 lra_constraint_insn_stack_bitmap
=
1637 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1638 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1640 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1641 if (! always_update
)
1642 lra_update_insn_regno_info (insn
);
1643 lra_constraint_insn_stack
.safe_push (insn
);
1646 /* Put INSN on the stack. */
1648 lra_push_insn (rtx_insn
*insn
)
1650 lra_push_insn_1 (insn
, false);
1653 /* Put INSN on the stack and update its reg info. */
1655 lra_push_insn_and_update_insn_regno_info (rtx_insn
*insn
)
1657 lra_push_insn_1 (insn
, true);
1660 /* Put insn with UID on the stack. */
1662 lra_push_insn_by_uid (unsigned int uid
)
1664 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1667 /* Take the last-inserted insns off the stack and return it. */
1671 rtx_insn
*insn
= lra_constraint_insn_stack
.pop ();
1672 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1676 /* Return the current size of the insn stack. */
1678 lra_insn_stack_length (void)
1680 return lra_constraint_insn_stack
.length ();
1683 /* Push insns FROM to TO (excluding it) going in reverse order. */
1685 push_insns (rtx_insn
*from
, rtx_insn
*to
)
1689 if (from
== NULL_RTX
)
1691 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1693 lra_push_insn (insn
);
1696 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1697 taken from the next BB insn after LAST or zero if there in such
1700 setup_sp_offset (rtx_insn
*from
, rtx_insn
*last
)
1702 rtx_insn
*before
= next_nonnote_insn_bb (last
);
1703 HOST_WIDE_INT offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1704 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1706 for (rtx_insn
*insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1707 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1710 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1711 insns onto the stack. Print about emitting the insns with
1714 lra_process_new_insns (rtx_insn
*insn
, rtx_insn
*before
, rtx_insn
*after
,
1719 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1721 if (lra_dump_file
!= NULL
)
1723 dump_insn_slim (lra_dump_file
, insn
);
1724 if (before
!= NULL_RTX
)
1726 fprintf (lra_dump_file
," %s before:\n", title
);
1727 dump_rtl_slim (lra_dump_file
, before
, NULL
, -1, 0);
1729 if (after
!= NULL_RTX
)
1731 fprintf (lra_dump_file
, " %s after:\n", title
);
1732 dump_rtl_slim (lra_dump_file
, after
, NULL
, -1, 0);
1734 fprintf (lra_dump_file
, "\n");
1736 if (before
!= NULL_RTX
)
1738 emit_insn_before (before
, insn
);
1739 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1740 setup_sp_offset (before
, PREV_INSN (insn
));
1742 if (after
!= NULL_RTX
)
1744 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1746 emit_insn_after (after
, insn
);
1747 push_insns (last
, insn
);
1748 setup_sp_offset (after
, last
);
1754 /* This page contains code dealing with scratches (changing them onto
1755 pseudos and restoring them from the pseudos).
1757 We change scratches into pseudos at the beginning of LRA to
1758 simplify dealing with them (conflicts, hard register assignments).
1760 If the pseudo denoting scratch was spilled it means that we do need
1761 a hard register for it. Such pseudos are transformed back to
1762 scratches at the end of LRA. */
1764 /* Description of location of a former scratch operand. */
1767 rtx_insn
*insn
; /* Insn where the scratch was. */
1768 int nop
; /* Number of the operand which was a scratch. */
1771 typedef struct sloc
*sloc_t
;
1773 /* Locations of the former scratches. */
1774 static vec
<sloc_t
> scratches
;
1776 /* Bitmap of scratch regnos. */
1777 static bitmap_head scratch_bitmap
;
1779 /* Bitmap of scratch operands. */
1780 static bitmap_head scratch_operand_bitmap
;
1782 /* Return true if pseudo REGNO is made of SCRATCH. */
1784 lra_former_scratch_p (int regno
)
1786 return bitmap_bit_p (&scratch_bitmap
, regno
);
1789 /* Return true if the operand NOP of INSN is a former scratch. */
1791 lra_former_scratch_operand_p (rtx_insn
*insn
, int nop
)
1793 return bitmap_bit_p (&scratch_operand_bitmap
,
1794 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
1797 /* Change scratches onto pseudos and save their location. */
1799 remove_scratches (void)
1802 bool insn_changed_p
;
1807 lra_insn_recog_data_t id
;
1808 struct lra_static_insn_data
*static_id
;
1810 scratches
.create (get_max_uid ());
1811 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
1812 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
1813 FOR_EACH_BB_FN (bb
, cfun
)
1814 FOR_BB_INSNS (bb
, insn
)
1817 id
= lra_get_insn_recog_data (insn
);
1818 static_id
= id
->insn_static_data
;
1819 insn_changed_p
= false;
1820 for (i
= 0; i
< static_id
->n_operands
; i
++)
1821 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
1822 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
1824 insn_changed_p
= true;
1825 *id
->operand_loc
[i
] = reg
1826 = lra_create_new_reg (static_id
->operand
[i
].mode
,
1827 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
1828 add_reg_note (insn
, REG_UNUSED
, reg
);
1829 lra_update_dup (id
, i
);
1830 loc
= XNEW (struct sloc
);
1833 scratches
.safe_push (loc
);
1834 bitmap_set_bit (&scratch_bitmap
, REGNO (*id
->operand_loc
[i
]));
1835 bitmap_set_bit (&scratch_operand_bitmap
,
1836 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ i
);
1837 if (lra_dump_file
!= NULL
)
1838 fprintf (lra_dump_file
,
1839 "Removing SCRATCH in insn #%u (nop %d)\n",
1840 INSN_UID (insn
), i
);
1843 /* Because we might use DF right after caller-saves sub-pass
1844 we need to keep DF info up to date. */
1845 df_insn_rescan (insn
);
1849 /* Changes pseudos created by function remove_scratches onto scratches. */
1851 restore_scratches (void)
1856 rtx_insn
*last
= NULL
;
1857 lra_insn_recog_data_t id
= NULL
;
1859 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1861 if (last
!= loc
->insn
)
1864 id
= lra_get_insn_recog_data (last
);
1866 if (REG_P (*id
->operand_loc
[loc
->nop
])
1867 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
1868 >= FIRST_PSEUDO_REGISTER
)
1869 && lra_get_regno_hard_regno (regno
) < 0)
1871 /* It should be only case when scratch register with chosen
1872 constraint 'X' did not get memory or hard register. */
1873 lra_assert (lra_former_scratch_p (regno
));
1874 *id
->operand_loc
[loc
->nop
]
1875 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
1876 lra_update_dup (id
, loc
->nop
);
1877 if (lra_dump_file
!= NULL
)
1878 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
1879 INSN_UID (loc
->insn
), loc
->nop
);
1882 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1884 scratches
.release ();
1885 bitmap_clear (&scratch_bitmap
);
1886 bitmap_clear (&scratch_operand_bitmap
);
1891 #ifdef ENABLE_CHECKING
1893 /* Function checks RTL for correctness. If FINAL_P is true, it is
1894 done at the end of LRA and the check is more rigorous. */
1896 check_rtl (bool final_p
)
1901 lra_assert (! final_p
|| reload_completed
);
1902 FOR_EACH_BB_FN (bb
, cfun
)
1903 FOR_BB_INSNS (bb
, insn
)
1904 if (NONDEBUG_INSN_P (insn
)
1905 && GET_CODE (PATTERN (insn
)) != USE
1906 && GET_CODE (PATTERN (insn
)) != CLOBBER
1907 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
1911 #ifdef ENABLED_CHECKING
1912 extract_constrain_insn (insn
);
1916 /* LRA code is based on assumption that all addresses can be
1917 correctly decomposed. LRA can generate reloads for
1918 decomposable addresses. The decomposition code checks the
1919 correctness of the addresses. So we don't need to check
1920 the addresses here. Don't call insn_invalid_p here, it can
1921 change the code at this stage. */
1922 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
1923 fatal_insn_not_found (insn
);
1926 #endif /* #ifdef ENABLE_CHECKING */
1928 /* Determine if the current function has an exception receiver block
1929 that reaches the exit block via non-exceptional edges */
1931 has_nonexceptional_receiver (void)
1935 basic_block
*tos
, *worklist
, bb
;
1937 /* If we're not optimizing, then just err on the safe side. */
1941 /* First determine which blocks can reach exit via normal paths. */
1942 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
1944 FOR_EACH_BB_FN (bb
, cfun
)
1945 bb
->flags
&= ~BB_REACHABLE
;
1947 /* Place the exit block on our worklist. */
1948 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
1949 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
1951 /* Iterate: find everything reachable from what we've already seen. */
1952 while (tos
!= worklist
)
1956 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
1957 if (e
->flags
& EDGE_ABNORMAL
)
1964 basic_block src
= e
->src
;
1966 if (!(src
->flags
& BB_REACHABLE
))
1968 src
->flags
|= BB_REACHABLE
;
1974 /* No exceptional block reached exit unexceptionally. */
1980 /* Process recursively X of INSN and add REG_INC notes if necessary. */
1982 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
1984 enum rtx_code code
= GET_CODE (x
);
1988 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
1990 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
1994 /* Scan all X sub-expressions. */
1995 fmt
= GET_RTX_FORMAT (code
);
1996 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1999 add_auto_inc_notes (insn
, XEXP (x
, i
));
2000 else if (fmt
[i
] == 'E')
2001 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2002 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2008 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2009 We change pseudos by hard registers without notification of DF and
2010 that can make the notes obsolete. DF-infrastructure does not deal
2011 with REG_INC notes -- so we should regenerate them here. */
2013 update_inc_notes (void)
2019 FOR_EACH_BB_FN (bb
, cfun
)
2020 FOR_BB_INSNS (bb
, insn
)
2021 if (NONDEBUG_INSN_P (insn
))
2023 pnote
= ®_NOTES (insn
);
2026 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2027 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2028 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2029 *pnote
= XEXP (*pnote
, 1);
2031 pnote
= &XEXP (*pnote
, 1);
2034 add_auto_inc_notes (insn
, PATTERN (insn
));
2039 /* Set to 1 while in lra. */
2040 int lra_in_progress
;
2042 /* Start of pseudo regnos before the LRA. */
2043 int lra_new_regno_start
;
2045 /* Start of reload pseudo regnos before the new spill pass. */
2046 int lra_constraint_new_regno_start
;
2048 /* Inheritance pseudo regnos before the new spill pass. */
2049 bitmap_head lra_inheritance_pseudos
;
2051 /* Split regnos before the new spill pass. */
2052 bitmap_head lra_split_regs
;
2054 /* Reload pseudo regnos before the new assignmnet pass which still can
2055 be spilled after the assinment pass as memory is also accepted in
2056 insns for the reload pseudos. */
2057 bitmap_head lra_optional_reload_pseudos
;
2059 /* Pseudo regnos used for subreg reloads before the new assignment
2060 pass. Such pseudos still can be spilled after the assinment
2062 bitmap_head lra_subreg_reload_pseudos
;
2064 /* First UID of insns generated before a new spill pass. */
2065 int lra_constraint_new_insn_uid_start
;
2067 /* File used for output of LRA debug information. */
2068 FILE *lra_dump_file
;
2070 /* True if we should try spill into registers of different classes
2071 instead of memory. */
2072 bool lra_reg_spill_p
;
2074 /* Set up value LRA_REG_SPILL_P. */
2076 setup_reg_spill_flag (void)
2080 if (targetm
.spill_class
!= NULL
)
2081 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2082 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2083 if (targetm
.spill_class ((enum reg_class
) cl
,
2084 (machine_mode
) mode
) != NO_REGS
)
2086 lra_reg_spill_p
= true;
2089 lra_reg_spill_p
= false;
2092 /* True if the current function is too big to use regular algorithms
2093 in LRA. In other words, we should use simpler and faster algorithms
2094 in LRA. It also means we should not worry about generation code
2095 for caller saves. The value is set up in IRA. */
2098 /* Major LRA entry function. F is a file should be used to dump LRA
2104 bool live_p
, scratch_p
, inserted_p
;
2108 timevar_push (TV_LRA
);
2110 /* Make sure that the last insn is a note. Some subsequent passes
2112 emit_note (NOTE_INSN_DELETED
);
2114 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2119 init_insn_recog_data ();
2121 #ifdef ENABLE_CHECKING
2122 /* Some quick check on RTL generated by previous passes. */
2126 lra_in_progress
= 1;
2128 lra_live_range_iter
= lra_coalesce_iter
= lra_constraint_iter
= 0;
2129 lra_assignment_iter
= lra_assignment_iter_after_spill
= 0;
2130 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2132 setup_reg_spill_flag ();
2134 /* Function remove_scratches can creates new pseudos for clobbers --
2135 so set up lra_constraint_new_regno_start before its call to
2136 permit changing reg classes for pseudos created by this
2138 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2139 remove_scratches ();
2140 scratch_p
= lra_constraint_new_regno_start
!= max_reg_num ();
2142 /* A function that has a non-local label that can reach the exit
2143 block via non-exceptional paths must save all call-saved
2145 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2146 crtl
->saves_all_registers
= 1;
2148 if (crtl
->saves_all_registers
)
2149 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2150 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2151 df_set_regs_ever_live (i
, true);
2153 /* We don't DF from now and avoid its using because it is to
2154 expensive when a lot of RTL changes are made. */
2155 df_set_flags (DF_NO_INSN_RESCAN
);
2156 lra_constraint_insn_stack
.create (get_max_uid ());
2157 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2158 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2159 lra_live_ranges_init ();
2160 lra_constraints_init ();
2161 lra_curr_reload_num
= 0;
2162 push_insns (get_last_insn (), NULL
);
2163 /* It is needed for the 1st coalescing. */
2164 lra_constraint_new_insn_uid_start
= get_max_uid ();
2165 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2166 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2167 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2168 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2170 if (get_frame_size () != 0 && crtl
->stack_alignment_needed
)
2171 /* If we have a stack frame, we must align it now. The stack size
2172 may be a part of the offset computation for register
2174 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2180 /* We should try to assign hard registers to scratches even
2181 if there were no RTL transformations in
2183 if (! lra_constraints (lra_constraint_iter
== 0)
2184 && (lra_constraint_iter
> 1
2185 || (! scratch_p
&& ! caller_save_needed
)))
2187 /* Constraint transformations may result in that eliminable
2188 hard regs become uneliminable and pseudos which use them
2189 should be spilled. It is better to do it before pseudo
2192 For example, rs6000 can make
2193 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2194 to use a constant pool. */
2195 lra_eliminate (false, false);
2196 /* Do inheritance only for regular algorithms. */
2199 if (flag_use_caller_save
)
2202 lra_clear_live_ranges ();
2203 /* As a side-effect of lra_create_live_ranges, we calculate
2204 actual_call_used_reg_set, which is needed during
2206 lra_create_live_ranges (true);
2211 lra_clear_live_ranges ();
2212 /* We need live ranges for lra_assign -- so build them. */
2213 lra_create_live_ranges (true);
2215 /* If we don't spill non-reload and non-inheritance pseudos,
2216 there is no sense to run memory-memory move coalescing.
2217 If inheritance pseudos were spilled, the memory-memory
2218 moves involving them will be removed by pass undoing
2224 bool spill_p
= !lra_assign ();
2226 if (lra_undo_inheritance ())
2232 lra_create_live_ranges (true);
2235 if (lra_coalesce ())
2239 lra_clear_live_ranges ();
2242 /* Don't clear optional reloads bitmap until all constraints are
2243 satisfied as we need to differ them from regular reloads. */
2244 bitmap_clear (&lra_optional_reload_pseudos
);
2245 bitmap_clear (&lra_subreg_reload_pseudos
);
2246 bitmap_clear (&lra_inheritance_pseudos
);
2247 bitmap_clear (&lra_split_regs
);
2248 if (! lra_need_for_spills_p ())
2252 /* We need full live info for spilling pseudos into
2253 registers instead of memory. */
2254 lra_create_live_ranges (lra_reg_spill_p
);
2258 /* Assignment of stack slots changes elimination offsets for
2259 some eliminations. So update the offsets here. */
2260 lra_eliminate (false, false);
2261 lra_constraint_new_regno_start
= max_reg_num ();
2262 lra_constraint_new_insn_uid_start
= get_max_uid ();
2263 lra_assignment_iter_after_spill
= 0;
2265 restore_scratches ();
2266 lra_eliminate (true, false);
2267 lra_final_code_change ();
2268 lra_in_progress
= 0;
2270 lra_clear_live_ranges ();
2271 lra_live_ranges_finish ();
2272 lra_constraints_finish ();
2274 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2275 lra_constraint_insn_stack
.release ();
2276 finish_insn_recog_data ();
2277 regstat_free_n_sets_and_refs ();
2279 reload_completed
= 1;
2280 update_inc_notes ();
2282 inserted_p
= fixup_abnormal_edges ();
2284 /* We've possibly turned single trapping insn into multiple ones. */
2285 if (cfun
->can_throw_non_call_exceptions
)
2288 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2289 bitmap_ones (blocks
);
2290 find_many_sub_basic_blocks (blocks
);
2291 sbitmap_free (blocks
);
2295 commit_edge_insertions ();
2297 /* Replacing pseudos with their memory equivalents might have
2298 created shared rtx. Subsequent passes would get confused
2299 by this, so unshare everything here. */
2300 unshare_all_rtl_again (get_insns ());
2302 #ifdef ENABLE_CHECKING
2306 timevar_pop (TV_LRA
);
2309 /* Called once per compiler to initialize LRA data once. */
2311 lra_init_once (void)
2313 init_insn_code_data_once ();
2316 /* Called once per compiler to finish LRA data which are initialize
2319 lra_finish_once (void)
2321 finish_insn_code_data_once ();